From ffcf53ef00389aca1b2420ee40fb80b809570046 Mon Sep 17 00:00:00 2001 From: Thomas Otto Date: Sun, 2 May 2010 20:28:51 +0200 Subject: Make examples/other make use of new clock setup. --- examples/other/timer_interrupt/timer.c | 44 +--------------------------------- 1 file changed, 1 insertion(+), 43 deletions(-) (limited to 'examples/other/timer_interrupt') diff --git a/examples/other/timer_interrupt/timer.c b/examples/other/timer_interrupt/timer.c index f88de86..5c9791c 100644 --- a/examples/other/timer_interrupt/timer.c +++ b/examples/other/timer_interrupt/timer.c @@ -20,51 +20,9 @@ #include #include #include -#include #include #include -/* Set STM32 to 72 MHz. HSE 16MHz */ -void clock_setup(void) -{ - /* enable Internal High Speed Oscillator */ - rcc_osc_on(HSI); - rcc_wait_for_osc_ready(HSI); - - /* Select HSI as SYSCLK source. */ - rcc_set_sysclk_source(SW_SYSCLKSEL_HSICLK); - - /* enable External High Speed Oscillator 16MHz */ - rcc_osc_on(HSE); - rcc_wait_for_osc_ready(HSE); - rcc_set_sysclk_source(SW_SYSCLKSEL_HSECLK); - - /* set prescalers for ADC, ABP1, ABP2... make this before touching the PLL */ - rcc_set_hpre(HPRE_SYSCLK_NODIV); //prescales the AHB clock from the SYSCLK - rcc_set_adcpre(ADCPRE_PLCK2_DIV6); //prescales the ADC from the APB2 clock; max 14MHz - rcc_set_ppre1(PPRE1_HCLK_DIV2); //prescales the APB1 from the AHB clock; max 36MHz - rcc_set_ppre2(PPRE2_HCLK_NODIV); //prescales the APB2 from the AHB clock; max 72MHz - - /* sysclk should run with 72MHz -> 2 Waitstates ; choose 0WS from 0-24MHz, 1WS from 24-48MHz, 2WS from 48-72MHz */ - flash_set_ws(FLASH_LATENCY_2WS); - - /* Set the PLL multiplication factor to 9. -> 16MHz (external) * 9 (multiplier) / 2 (PLLXTPRE_HSE_CLK_DIV2) = 72MHz */ - rcc_set_pll_multiplication_factor(PLLMUL_PLL_CLK_MUL9); - - /* Select HSI as PLL source. */ - rcc_set_pll_source(PLLSRC_HSE_CLK); - - /* divide external frequency by 2 before entering pll (only valid/needed for HSE) */ - rcc_set_pllxtpre(PLLXTPRE_HSE_CLK_DIV2); - - /* Enable PLL oscillator and wait for it to stabilize. */ - rcc_osc_on(PLL); - rcc_wait_for_osc_ready(PLL); - - /* Select PLL as SYSCLK source. */ - rcc_set_sysclk_source(SW_SYSCLKSEL_PLLCLK); -} - void gpio_setup(void) { /* Enable GPIOB clock. */ @@ -95,7 +53,7 @@ void tim2_isr() int main(void) { - clock_setup(); + rcc_clock_setup_in_hse_16mhz_out_72mhz(); gpio_setup(); nvic_setup(); -- cgit v1.2.3