From 9645172453488a0d490dd0a930a2b2e122e7ea82 Mon Sep 17 00:00:00 2001 From: Michael Ossmann Date: Tue, 22 May 2012 14:47:27 -0600 Subject: lpc43xx example, copied from lpc17xx and modified --- examples/lpc43xx/Makefile.include | 125 +++++++++++++++++++++ examples/lpc43xx/hackrf-jellybean/README | 4 + .../lpc43xx/hackrf-jellybean/jellybean-lpc4330.ld | 32 ++++++ .../lpc43xx/hackrf-jellybean/miniblink/Makefile | 24 ++++ examples/lpc43xx/hackrf-jellybean/miniblink/README | 11 ++ .../lpc43xx/hackrf-jellybean/miniblink/miniblink.c | 46 ++++++++ 6 files changed, 242 insertions(+) create mode 100644 examples/lpc43xx/Makefile.include create mode 100644 examples/lpc43xx/hackrf-jellybean/README create mode 100644 examples/lpc43xx/hackrf-jellybean/jellybean-lpc4330.ld create mode 100644 examples/lpc43xx/hackrf-jellybean/miniblink/Makefile create mode 100644 examples/lpc43xx/hackrf-jellybean/miniblink/README create mode 100644 examples/lpc43xx/hackrf-jellybean/miniblink/miniblink.c (limited to 'examples/lpc43xx') diff --git a/examples/lpc43xx/Makefile.include b/examples/lpc43xx/Makefile.include new file mode 100644 index 0000000..6b0b8b9 --- /dev/null +++ b/examples/lpc43xx/Makefile.include @@ -0,0 +1,125 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## Copyright (C) 2010 Piotr Esden-Tempski +## Copyright (C) 2012 Michael Ossmann +## +## This library is free software: you can redistribute it and/or modify +## it under the terms of the GNU Lesser General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This library is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU Lesser General Public License for more details. +## +## You should have received a copy of the GNU Lesser General Public License +## along with this library. If not, see . +## + +PREFIX ?= arm-none-eabi +#PREFIX ?= arm-elf +CC = $(PREFIX)-gcc +LD = $(PREFIX)-gcc +OBJCOPY = $(PREFIX)-objcopy +OBJDUMP = $(PREFIX)-objdump +GDB = $(PREFIX)-gdb +# Uncomment this line if you want to use the installed (not local) library. +# TOOLCHAIN_DIR := $(shell dirname `which $(CC)`)/../$(PREFIX) +TOOLCHAIN_DIR = ../../../.. +CFLAGS += -O0 -g -Wall -Wextra -I$(TOOLCHAIN_DIR)/include -fno-common \ + -mcpu=cortex-m4 -mthumb -MD \ + -mfloat-abi=hard -mfpu=fpv4-sp-d16 +LDSCRIPT ?= $(BINARY).ld +LDFLAGS += -L$(TOOLCHAIN_DIR)/lib -L$(TOOLCHAIN_DIR)/lib/lpc43xx \ + -T$(LDSCRIPT) -nostartfiles -Wl,--gc-sections +OBJS += $(BINARY).o + +OOCD ?= openocd +OOCD_INTERFACE ?= flossjtag +OOCD_BOARD ?= olimex_stm32_h103 + +# Be silent per default, but 'make V=1' will show all compiler calls. +ifneq ($(V),1) +Q := @ +NULL := 2>/dev/null +else +LDFLAGS += -Wl,--print-gc-sections +endif + +.SUFFIXES: .elf .bin .hex .srec .list .images +.SECONDEXPANSION: +.SECONDARY: + +all: images + +images: $(BINARY).images +flash: $(BINARY).flash + +%.images: %.bin %.hex %.srec %.list + @#echo "*** $* images generated ***" + +%.bin: %.elf + @#printf " OBJCOPY $(*).bin\n" + $(Q)$(OBJCOPY) -Obinary $(*).elf $(*).bin + +%.hex: %.elf + @#printf " OBJCOPY $(*).hex\n" + $(Q)$(OBJCOPY) -Oihex $(*).elf $(*).hex + +%.srec: %.elf + @#printf " OBJCOPY $(*).srec\n" + $(Q)$(OBJCOPY) -Osrec $(*).elf $(*).srec + +%.list: %.elf + @#printf " OBJDUMP $(*).list\n" + $(Q)$(OBJDUMP) -S $(*).elf > $(*).list + +%.elf: $(OBJS) $(LDSCRIPT) $(TOOLCHAIN_DIR)/lib/lpc43xx/libopencm3_lpc43xx.a + @#printf " LD $(subst $(shell pwd)/,,$(@))\n" + $(Q)$(LD) $(LDFLAGS) -o $(*).elf $(OBJS) -lopencm3_lpc43xx + +%.o: %.c Makefile + @#printf " CC $(subst $(shell pwd)/,,$(@))\n" + $(Q)$(CC) $(CFLAGS) -o $@ -c $< + +clean: + $(Q)rm -f *.o + $(Q)rm -f *.d + $(Q)rm -f *.elf + $(Q)rm -f *.bin + $(Q)rm -f *.hex + $(Q)rm -f *.srec + $(Q)rm -f *.list + +# FIXME: Replace STM32 stuff with proper LPC43XX OpenOCD support later. +ifeq ($(OOCD_SERIAL),) +%.flash: %.hex + @printf " FLASH $<\n" + @# IMPORTANT: Don't use "resume", only "reset" will work correctly! + $(Q)$(OOCD) -f interface/$(OOCD_INTERFACE).cfg \ + -f board/$(OOCD_BOARD).cfg \ + -c "init" -c "reset init" \ + -c "stm32x mass_erase 0" \ + -c "flash write_image $(*).hex" \ + -c "reset" \ + -c "shutdown" $(NULL) +else +%.flash: %.hex + @printf " FLASH $<\n" + @# IMPORTANT: Don't use "resume", only "reset" will work correctly! + $(Q)$(OOCD) -f interface/$(OOCD_INTERFACE).cfg \ + -f board/$(OOCD_BOARD).cfg \ + -c "ft2232_serial $(OOCD_SERIAL)" \ + -c "init" -c "reset init" \ + -c "stm32x mass_erase 0" \ + -c "flash write_image $(*).hex" \ + -c "reset" \ + -c "shutdown" $(NULL) +endif + +.PHONY: images clean + +-include $(OBJS:.o=.d) diff --git a/examples/lpc43xx/hackrf-jellybean/README b/examples/lpc43xx/hackrf-jellybean/README new file mode 100644 index 0000000..07aaeee --- /dev/null +++ b/examples/lpc43xx/hackrf-jellybean/README @@ -0,0 +1,4 @@ +These example programs are written for the Jellybean development board from the +HackRF project: + +https://github.com/mossmann/hackrf diff --git a/examples/lpc43xx/hackrf-jellybean/jellybean-lpc4330.ld b/examples/lpc43xx/hackrf-jellybean/jellybean-lpc4330.ld new file mode 100644 index 0000000..92c25af --- /dev/null +++ b/examples/lpc43xx/hackrf-jellybean/jellybean-lpc4330.ld @@ -0,0 +1,32 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Uwe Hermann + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* Linker script for HackRF Jellybean (LPC4330, 1M SPI flash, 64K SRAM). */ + +/* Define memory regions. */ +MEMORY +{ + /* rom is really the shadow region that points to SPI flash or elsewhere */ + rom (rx) : ORIGIN = 0x00000000, LENGTH = 1M + ram (rwx) : ORIGIN = 0x10000000, LENGTH = 128K + /* there are some additional RAM regions */ +} + +/* Include the common ld script. */ +INCLUDE libopencm3_lpc43xx.ld diff --git a/examples/lpc43xx/hackrf-jellybean/miniblink/Makefile b/examples/lpc43xx/hackrf-jellybean/miniblink/Makefile new file mode 100644 index 0000000..32da7ff --- /dev/null +++ b/examples/lpc43xx/hackrf-jellybean/miniblink/Makefile @@ -0,0 +1,24 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2010 Uwe Hermann +## +## This library is free software: you can redistribute it and/or modify +## it under the terms of the GNU Lesser General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This library is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU Lesser General Public License for more details. +## +## You should have received a copy of the GNU Lesser General Public License +## along with this library. If not, see . +## + +BINARY = miniblink + +LDSCRIPT = ../jellybean-lpc4330.ld + +include ../../Makefile.include diff --git a/examples/lpc43xx/hackrf-jellybean/miniblink/README b/examples/lpc43xx/hackrf-jellybean/miniblink/README new file mode 100644 index 0000000..556ed92 --- /dev/null +++ b/examples/lpc43xx/hackrf-jellybean/miniblink/README @@ -0,0 +1,11 @@ +------------------------------------------------------------------------------ +README +------------------------------------------------------------------------------ + +This is the smallest-possible example program using libopencm3. + +It's intended for the Jellybean development board from the HackRF project: + +https://github.com/mossmann/hackrf + +It should blink LED1 on the board. diff --git a/examples/lpc43xx/hackrf-jellybean/miniblink/miniblink.c b/examples/lpc43xx/hackrf-jellybean/miniblink/miniblink.c new file mode 100644 index 0000000..6d8a9bc --- /dev/null +++ b/examples/lpc43xx/hackrf-jellybean/miniblink/miniblink.c @@ -0,0 +1,46 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Uwe Hermann + * Copyright (C) 2012 Michael Ossmann + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include + +void gpio_setup(void) +{ + GPIO2_DIR |= (1 << 1); /* Configure GPIO2[1] (P4_1) as output. */ +} + +int main(void) +{ + int i; + + gpio_setup(); + + /* Blink LED1 on the board. */ + while (1) { + + gpio_set(GPIO2, GPIOPIN1); /* LED on */ + for (i = 0; i < 800000; i++) /* Wait a bit. */ + __asm__("nop"); + gpio_clear(GPIO2, GPIOPIN1); /* LED off */ + for (i = 0; i < 800000; i++) /* Wait a bit. */ + __asm__("nop"); + } + + return 0; +} -- cgit v1.2.3 From 3e036a107ffabe1a4092468f50c60c404b47c42e Mon Sep 17 00:00:00 2001 From: Michael Ossmann Date: Sun, 27 May 2012 23:02:56 -0600 Subject: added diolan-lpc-4350-db1 examples --- examples/lpc43xx/diolan-lpc-4350-db1/README | 3 ++ .../diolan-lpc-4350-db1/diolan-lpc-4350-db1.ld | 32 +++++++++++++++ .../lpc43xx/diolan-lpc-4350-db1/miniblink/Makefile | 24 +++++++++++ .../lpc43xx/diolan-lpc-4350-db1/miniblink/README | 11 ++++++ .../diolan-lpc-4350-db1/miniblink/miniblink.c | 46 ++++++++++++++++++++++ 5 files changed, 116 insertions(+) create mode 100644 examples/lpc43xx/diolan-lpc-4350-db1/README create mode 100644 examples/lpc43xx/diolan-lpc-4350-db1/diolan-lpc-4350-db1.ld create mode 100644 examples/lpc43xx/diolan-lpc-4350-db1/miniblink/Makefile create mode 100644 examples/lpc43xx/diolan-lpc-4350-db1/miniblink/README create mode 100644 examples/lpc43xx/diolan-lpc-4350-db1/miniblink/miniblink.c (limited to 'examples/lpc43xx') diff --git a/examples/lpc43xx/diolan-lpc-4350-db1/README b/examples/lpc43xx/diolan-lpc-4350-db1/README new file mode 100644 index 0000000..bff2388 --- /dev/null +++ b/examples/lpc43xx/diolan-lpc-4350-db1/README @@ -0,0 +1,3 @@ +These example programs are written for the Diolan LPC-4350-DB1: + +http://www.diolan.com/lpc4350-features.html diff --git a/examples/lpc43xx/diolan-lpc-4350-db1/diolan-lpc-4350-db1.ld b/examples/lpc43xx/diolan-lpc-4350-db1/diolan-lpc-4350-db1.ld new file mode 100644 index 0000000..92c25af --- /dev/null +++ b/examples/lpc43xx/diolan-lpc-4350-db1/diolan-lpc-4350-db1.ld @@ -0,0 +1,32 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Uwe Hermann + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* Linker script for HackRF Jellybean (LPC4330, 1M SPI flash, 64K SRAM). */ + +/* Define memory regions. */ +MEMORY +{ + /* rom is really the shadow region that points to SPI flash or elsewhere */ + rom (rx) : ORIGIN = 0x00000000, LENGTH = 1M + ram (rwx) : ORIGIN = 0x10000000, LENGTH = 128K + /* there are some additional RAM regions */ +} + +/* Include the common ld script. */ +INCLUDE libopencm3_lpc43xx.ld diff --git a/examples/lpc43xx/diolan-lpc-4350-db1/miniblink/Makefile b/examples/lpc43xx/diolan-lpc-4350-db1/miniblink/Makefile new file mode 100644 index 0000000..bf0ca91 --- /dev/null +++ b/examples/lpc43xx/diolan-lpc-4350-db1/miniblink/Makefile @@ -0,0 +1,24 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2010 Uwe Hermann +## +## This library is free software: you can redistribute it and/or modify +## it under the terms of the GNU Lesser General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This library is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU Lesser General Public License for more details. +## +## You should have received a copy of the GNU Lesser General Public License +## along with this library. If not, see . +## + +BINARY = miniblink + +LDSCRIPT = ../diolan-lpc-4350-db1.ld + +include ../../Makefile.include diff --git a/examples/lpc43xx/diolan-lpc-4350-db1/miniblink/README b/examples/lpc43xx/diolan-lpc-4350-db1/miniblink/README new file mode 100644 index 0000000..009b9a9 --- /dev/null +++ b/examples/lpc43xx/diolan-lpc-4350-db1/miniblink/README @@ -0,0 +1,11 @@ +------------------------------------------------------------------------------ +README +------------------------------------------------------------------------------ + +This is the smallest-possible example program using libopencm3. + +It's intended for the Diolan LPC-4350-DB1: + +http://www.diolan.com/lpc4350-features.html + +It should blink D2 on the board. diff --git a/examples/lpc43xx/diolan-lpc-4350-db1/miniblink/miniblink.c b/examples/lpc43xx/diolan-lpc-4350-db1/miniblink/miniblink.c new file mode 100644 index 0000000..ce73289 --- /dev/null +++ b/examples/lpc43xx/diolan-lpc-4350-db1/miniblink/miniblink.c @@ -0,0 +1,46 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Uwe Hermann + * Copyright (C) 2012 Michael Ossmann + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include + +void gpio_setup(void) +{ + GPIO0_DIR |= (1 << 5); /* Configure GPIO0[5] (P6_6) as output. */ +} + +int main(void) +{ + int i; + + gpio_setup(); + + /* Blink D2 on the board. */ + while (1) { + + gpio_set(GPIO0, GPIOPIN5); /* LED on */ + for (i = 0; i < 800000; i++) /* Wait a bit. */ + __asm__("nop"); + gpio_clear(GPIO0, GPIOPIN5); /* LED off */ + for (i = 0; i < 800000; i++) /* Wait a bit. */ + __asm__("nop"); + } + + return 0; +} -- cgit v1.2.3 From 10e71edb82943da81b22473df069c4b0df9c9027 Mon Sep 17 00:00:00 2001 From: Michael Ossmann Date: Wed, 30 May 2012 10:08:04 -0600 Subject: started i2c example, still incomplete and much will be moved to drivers/headers elsewhere --- examples/lpc43xx/hackrf-jellybean/i2c/Makefile | 24 ++++++ examples/lpc43xx/hackrf-jellybean/i2c/README | 5 ++ examples/lpc43xx/hackrf-jellybean/i2c/i2cdemo.c | 102 ++++++++++++++++++++++++ 3 files changed, 131 insertions(+) create mode 100644 examples/lpc43xx/hackrf-jellybean/i2c/Makefile create mode 100644 examples/lpc43xx/hackrf-jellybean/i2c/README create mode 100644 examples/lpc43xx/hackrf-jellybean/i2c/i2cdemo.c (limited to 'examples/lpc43xx') diff --git a/examples/lpc43xx/hackrf-jellybean/i2c/Makefile b/examples/lpc43xx/hackrf-jellybean/i2c/Makefile new file mode 100644 index 0000000..b18f122 --- /dev/null +++ b/examples/lpc43xx/hackrf-jellybean/i2c/Makefile @@ -0,0 +1,24 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2010 Uwe Hermann +## +## This library is free software: you can redistribute it and/or modify +## it under the terms of the GNU Lesser General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This library is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU Lesser General Public License for more details. +## +## You should have received a copy of the GNU Lesser General Public License +## along with this library. If not, see . +## + +BINARY = i2cdemo + +LDSCRIPT = ../jellybean-lpc4330.ld + +include ../../Makefile.include diff --git a/examples/lpc43xx/hackrf-jellybean/i2c/README b/examples/lpc43xx/hackrf-jellybean/i2c/README new file mode 100644 index 0000000..0785a11 --- /dev/null +++ b/examples/lpc43xx/hackrf-jellybean/i2c/README @@ -0,0 +1,5 @@ +------------------------------------------------------------------------------ +README +------------------------------------------------------------------------------ + +This program exercises the I2C peripheral on Jellybean's LPC43xx. diff --git a/examples/lpc43xx/hackrf-jellybean/i2c/i2cdemo.c b/examples/lpc43xx/hackrf-jellybean/i2c/i2cdemo.c new file mode 100644 index 0000000..d6441ab --- /dev/null +++ b/examples/lpc43xx/hackrf-jellybean/i2c/i2cdemo.c @@ -0,0 +1,102 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Uwe Hermann + * Copyright (C) 2012 Michael Ossmann + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include +#include +#include + +//FIXME generalize and move to drivers + +#define SCU_SFSI2C0_SCL_EFP (1 << 1) /* 3 ns glitch filter */ +#define SCU_SFSI2C0_SCL_EHD (1 << 2) /* Fast-mode Plus transmit */ +#define SCU_SFSI2C0_SCL_EZI (1 << 3) /* Enable the input receiver */ +#define SCU_SFSI2C0_SCL_ZIF (1 << 7) /* Disable input glitch filter */ +#define SCU_SFSI2C0_SDA_EFP (1 << 8) /* 3 ns glitch filter */ +#define SCU_SFSI2C0_SDA_EHD (1 << 10) /* Fast-mode Plus transmit */ +#define SCU_SFSI2C0_SDA_EZI (1 << 11) /* Enable the input receiver */ +#define SCU_SFSI2C0_SDA_ZIF (1 << 15) /* Disable input glitch filter */ + +#define I2C_CONCLR_AAC (1 << 2) /* Assert acknowledge Clear */ +#define I2C_CONCLR_SIC (1 << 3) /* I2C interrupt Clear */ +#define I2C_CONCLR_STAC (1 << 5) /* START flag Clear */ +#define I2C_CONCLR_I2ENC (1 << 6) /* I2C interface Disable bit */ + +#define I2C_CONSET_AA (1 << 2) /* Assert acknowledge flag */ +#define I2C_CONSET_SI (1 << 3) /* I2C interrupt flag */ +#define I2C_CONSET_STO (1 << 4) /* STOP flag */ +#define I2C_CONSET_STA (1 << 5) /* START flag */ +#define I2C_CONSET_I2EN (1 << 6) /* I2C interface enable */ + +#define CGU_SRC_32K 0x00 +#define CGU_SRC_IRC 0x01 +#define CGU_SRC_ENET_RX 0x02 +#define CGU_SRC_ENET_TX 0x03 +#define CGU_SRC_GP_CLKIN 0x04 +#define CGU_SRC_XTAL 0x06 +#define CGU_SRC_PLL0USB 0x07 +#define CGU_SRC_PLL0AUDIO 0x08 +#define CGU_SRC_PLL1 0x09 +#define CGU_SRC_IDIVA 0x0C +#define CGU_SRC_IDIVB 0x0D +#define CGU_SRC_IDIVC 0x0E +#define CGU_SRC_IDIVD 0x0F +#define CGU_SRC_IDIVE 0x10 + +#define CGU_BASE_CLK_PD (1 << 0) /* output stage power-down */ +#define CGU_BASE_CLK_AUTOBLOCK (1 << 11) /* block clock automatically */ +#define CGU_BASE_CLK_SEL_SHIFT 24 /* clock source selection (5 bits) */ + +void i2c0_init() +{ + /* enable input on SCL and SDA pins */ + SCU_SFSI2C0 = (SCU_SFSI2C0_SCL_EZI | SCU_SFSI2C0_SDA_EZI); + + /* use PLL1 as clock source for APB1 (including I2C0) */ + CGU_BASE_APB1_CLK = (CGU_SRC_PLL1 << CGU_BASE_CLK_SEL_SHIFT); + + //FIXME assuming we're on IRC at 96 MHz + + /* 400 kHz I2C */ + I2C0_SCLH = 120; + I2C0_SCLL = 120; + + /* 100 kHz I2C */ + //I2C0_SCLH = 480; + //I2C0_SCLL = 480; + + /* clear the control bits */ + I2C0_CONCLR = (I2C_CONCLR_AAC | I2C_CONCLR_SIC + | I2C_CONCLR_STAC | I2C_CONCLR_I2ENC); + + /* enable I2C0 */ + I2C0_CONSET = I2C_CONSET_I2EN; +} + +int main(void) +{ + int i; + + i2c0_init(); + + //TODO I2C tx/rx + + return 0; +} -- cgit v1.2.3 From e7fbc2220b23b1d50fc0285c260a8787694328fe Mon Sep 17 00:00:00 2001 From: TitanMKD Date: Sat, 2 Jun 2012 09:45:03 +0200 Subject: Added JellyBean Configuration for PinMux, GPIO In/Out (work in progress). Added scu driver file scu.c. Modified Makefile/Makefile.include to generate .map file and use -O2 as optimization. Modified hackrf-jellybean miniblink.c to enable 1V8 and blink LED1,2&3 with configuration of PinMux and GPIO. --- examples/lpc43xx/Makefile.include | 5 +- examples/lpc43xx/hackrf-jellybean/jellybean_conf.h | 80 +++++ .../lpc43xx/hackrf-jellybean/miniblink/miniblink.c | 54 +++- include/libopencm3/cm3/common.h | 34 +++ include/libopencm3/lpc43xx/scu.h | 323 ++++++++++++++++++++- lib/lpc43xx/Makefile | 5 +- lib/lpc43xx/scu.c | 30 ++ 7 files changed, 516 insertions(+), 15 deletions(-) create mode 100644 examples/lpc43xx/hackrf-jellybean/jellybean_conf.h create mode 100644 lib/lpc43xx/scu.c (limited to 'examples/lpc43xx') diff --git a/examples/lpc43xx/Makefile.include b/examples/lpc43xx/Makefile.include index 6b0b8b9..89e356d 100644 --- a/examples/lpc43xx/Makefile.include +++ b/examples/lpc43xx/Makefile.include @@ -4,6 +4,7 @@ ## Copyright (C) 2009 Uwe Hermann ## Copyright (C) 2010 Piotr Esden-Tempski ## Copyright (C) 2012 Michael Ossmann +## Copyright (C) 2012 Benjamin Vernoux ## ## This library is free software: you can redistribute it and/or modify ## it under the terms of the GNU Lesser General Public License as published by @@ -29,12 +30,12 @@ GDB = $(PREFIX)-gdb # Uncomment this line if you want to use the installed (not local) library. # TOOLCHAIN_DIR := $(shell dirname `which $(CC)`)/../$(PREFIX) TOOLCHAIN_DIR = ../../../.. -CFLAGS += -O0 -g -Wall -Wextra -I$(TOOLCHAIN_DIR)/include -fno-common \ +CFLAGS += -O2 -g -Wall -Wextra -I$(TOOLCHAIN_DIR)/include -fno-common \ -mcpu=cortex-m4 -mthumb -MD \ -mfloat-abi=hard -mfpu=fpv4-sp-d16 LDSCRIPT ?= $(BINARY).ld LDFLAGS += -L$(TOOLCHAIN_DIR)/lib -L$(TOOLCHAIN_DIR)/lib/lpc43xx \ - -T$(LDSCRIPT) -nostartfiles -Wl,--gc-sections + -T$(LDSCRIPT) -nostartfiles -Wl,--gc-sections -Xlinker -Map=$(BINARY).map OBJS += $(BINARY).o OOCD ?= openocd diff --git a/examples/lpc43xx/hackrf-jellybean/jellybean_conf.h b/examples/lpc43xx/hackrf-jellybean/jellybean_conf.h new file mode 100644 index 0000000..a5ad8d0 --- /dev/null +++ b/examples/lpc43xx/hackrf-jellybean/jellybean_conf.h @@ -0,0 +1,80 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Benjamin Vernoux + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef __JELLYBEAN_CONF_H +#define __JELLYBEAN_CONF_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include + +/************************/ +/* JellyBean SCU PinMux */ +/************************/ + +/* GPIO Output PinMux */ +#define SCU_PINMUX_LED1 (P4_1) /* GPIO2[1] on P4_1 */ +#define SCU_PINMUX_LED2 (P4_2) /* GPIO2[2] on P4_2 */ +#define SCU_PINMUX_LED3 (P6_12) /* GPIO2[8] on P6_12 */ + +#define SCU_PINMUX_EN1V8 (P6_10) /* GPIO3[6] on P6_10 */ + +/* GPIO Input PinMux */ +#define SCU_PINMUX_BOOT0 (P1_1) /* GPIO0[8] on P1_1 */ +#define SCU_PINMUX_BOOT1 (P1_2) /* GPIO0[9] on P1_2 */ +#define SCU_PINMUX_BOOT2 (P2_8) /* GPIO5[7] on P2_8 */ +#define SCU_PINMUX_BOOT3 (P2_9) /* GPIO1[10] on P2_9 */ + +/* TODO add other Pins */ + +/**********************/ +/* JellyBean GPIO Pin */ +/**********************/ + +/* GPIO Output */ +#define PIN_LED1 (BIT1) /* GPIO2[1] on P4_1 */ +#define PIN_LED2 (BIT2) /* GPIO2[2] on P4_2 */ +#define PIN_LED3 (BIT8) /* GPIO2[8] on P6_12 */ +#define PORT_LED1_3 (GPIO2) /* PORT for LED1, 2 & 3 */ + +#define PIN_EN1V8 (BIT6) /* GPIO3[6] on P6_10 */ +#define PORT_EN1V8 (GPIO3) + +/* GPIO Input */ +#define PIN_BOOT0 (BIT8) /* GPIO0[8] on P1_1 */ +#define PIN_BOOT1 (BIT9) /* GPIO0[9] on P1_2 */ +#define PIN_BOOT2 (BIT7) /* GPIO5[7] on P2_8 */ +#define PIN_BOOT3 (BIT10) /* GPIO1[10] on P2_9 */ + +/* Read GPIO Pin */ +#define BOOT0_STATE ( (GPIO0_PIN & PIN_BOOT0)==PIN_BOOT0 ) +#define BOOT1_STATE ( (GPIO0_PIN & PIN_BOOT1)==PIN_BOOT1 ) +#define BOOT2_STATE ( (GPIO5_PIN & PIN_BOOT2)==PIN_BOOT2 ) +#define BOOT3_STATE ( (GPIO1_PIN & PIN_BOOT3)==PIN_BOOT3 ) + +/* TODO add other Pins */ + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/examples/lpc43xx/hackrf-jellybean/miniblink/miniblink.c b/examples/lpc43xx/hackrf-jellybean/miniblink/miniblink.c index 6d8a9bc..567d9dc 100644 --- a/examples/lpc43xx/hackrf-jellybean/miniblink/miniblink.c +++ b/examples/lpc43xx/hackrf-jellybean/miniblink/miniblink.c @@ -19,26 +19,62 @@ */ #include +#include + +#include "../jellybean_conf.h" void gpio_setup(void) { - GPIO2_DIR |= (1 << 1); /* Configure GPIO2[1] (P4_1) as output. */ + /* Configure SCU Pin Mux as GPIO */ + scu_pinmux(SCU_PINMUX_LED1, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_LED2, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_LED3, SCU_GPIO_FAST); + + scu_pinmux(SCU_PINMUX_EN1V8, SCU_GPIO_FAST); + + scu_pinmux(SCU_PINMUX_BOOT0, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_BOOT1, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_BOOT2, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_BOOT3, SCU_GPIO_FAST); + + /* Configure all GPIO as Input (safe state) */ + GPIO0_DIR = 0; + GPIO1_DIR = 0; + GPIO2_DIR = 0; + GPIO3_DIR = 0; + GPIO4_DIR = 0; + GPIO5_DIR = 0; + GPIO6_DIR = 0; + GPIO7_DIR = 0; + + /* Configure GPIO as Output */ + GPIO2_DIR |= (PIN_LED1|PIN_LED2|PIN_LED3); /* Configure GPIO2[1/2/8] (P4_1/2 P6_12) as output. */ + GPIO3_DIR |= PIN_EN1V8; /* GPIO3[6] on P6_10 as output. */ } +u32 boot0, boot1, boot2, boot3; + int main(void) { int i; - gpio_setup(); - /* Blink LED1 on the board. */ - while (1) { - - gpio_set(GPIO2, GPIOPIN1); /* LED on */ - for (i = 0; i < 800000; i++) /* Wait a bit. */ + /* Set 1V8 */ + gpio_set(PORT_EN1V8, PIN_EN1V8); + + /* Blink LED1/2/3 on the board and Read BOOT0/1/2/3 pins. */ + while (1) + { + boot0 = BOOT0_STATE; + boot1 = BOOT1_STATE; + boot2 = BOOT2_STATE; + boot3 = BOOT3_STATE; + + gpio_set(PORT_LED1_3, (PIN_LED1|PIN_LED2|PIN_LED3)); /* LEDs on */ + for (i = 0; i < 2000000; i++) /* Wait a bit. */ __asm__("nop"); - gpio_clear(GPIO2, GPIOPIN1); /* LED off */ - for (i = 0; i < 800000; i++) /* Wait a bit. */ + gpio_clear(PORT_LED1_3, (PIN_LED1|PIN_LED2|PIN_LED3)); /* LED off */ + for (i = 0; i < 2000000; i++) /* Wait a bit. */ __asm__("nop"); } diff --git a/include/libopencm3/cm3/common.h b/include/libopencm3/cm3/common.h index dc3e433..7947017 100644 --- a/include/libopencm3/cm3/common.h +++ b/include/libopencm3/cm3/common.h @@ -38,6 +38,40 @@ typedef uint64_t u64; #define MMIO32(addr) (*(volatile u32 *)(addr)) #define MMIO64(addr) (*(volatile u64 *)(addr)) +/* Generic bit definition */ +#define BIT0 (1<<0) +#define BIT1 (1<<1) +#define BIT2 (1<<2) +#define BIT3 (1<<3) +#define BIT4 (1<<4) +#define BIT5 (1<<5) +#define BIT6 (1<<6) +#define BIT7 (1<<7) +#define BIT8 (1<<8) +#define BIT9 (1<<9) +#define BIT10 (1<<10) +#define BIT11 (1<<11) +#define BIT12 (1<<12) +#define BIT13 (1<<13) +#define BIT14 (1<<14) +#define BIT15 (1<<15) +#define BIT16 (1<<16) +#define BIT17 (1<<17) +#define BIT18 (1<<18) +#define BIT19 (1<<19) +#define BIT20 (1<<20) +#define BIT21 (1<<21) +#define BIT22 (1<<22) +#define BIT23 (1<<23) +#define BIT24 (1<<24) +#define BIT25 (1<<25) +#define BIT26 (1<<26) +#define BIT27 (1<<27) +#define BIT28 (1<<28) +#define BIT29 (1<<29) +#define BIT30 (1<<30) +#define BIT31 (1<<31) + /* Main page for the doxygen-generated documentation: */ /** diff --git a/include/libopencm3/lpc43xx/scu.h b/include/libopencm3/lpc43xx/scu.h index 83688e2..146aafc 100644 --- a/include/libopencm3/lpc43xx/scu.h +++ b/include/libopencm3/lpc43xx/scu.h @@ -288,7 +288,6 @@ #define SCU_SFSUSB MMIO32(SCU_BASE + 0xC80) #define SCU_SFSI2C0 MMIO32(SCU_BASE + 0xC84) - /* ADC pin select registers */ /* ADC0 function select register */ @@ -311,6 +310,326 @@ #define SCU_PINTSEL0 MMIO32(SCU_BASE + 0xE00) /* Pin interrupt select register for pin interrupts 4 to 7 */ -#define SCU_PINTSEL1 MMIO32(SCU_BASE + 0xE00) +#define SCU_PINTSEL1 MMIO32(SCU_BASE + 0xE04) + +/* +SCU PIN Normal Drive: +The pin configuration registers for normal-drive pins control the following pins: +- P0_0 and P0_1 +- P1_0 to P1_16 and P1_18 to P1_20 +- P2_0 to P2_2 and P2_6 to P2_13 +- P3_0 to P3_2 and P3_4 to P3_8 +- P4_0 to P4_10 +- P5_0 to P5_7 +- P6_0 to P6_12 +- P7_0 to P7_7 +- P8_3 to P8_8 +- P9_0 to P9_6 +- PA_0 and PA_4 +- PB_0 to PB_6 +- PC_0 to PC_14 +- PE_0 to PE_15 +- PF_0 to PF_11 + +Pin configuration registers for High-Drive pins. +The pin configuration registers for high-drive pins control the following pins: +• P1_17 +• P2_3 to P2_5 +• P8_0 to P8_2 +• PA_1 to PA_3 + +Pin configuration registers for High-Speed pins. +This register controls the following pins: +P3_3 and pins CLK0 to CLK3. +*/ +typedef enum { + /* Group Port 0 */ + P0_0 = (PIN_GROUP0+PIN0), + P0_1 = (PIN_GROUP0+PIN1), + + /* Group Port 1 */ + P1_0 = (PIN_GROUP1+PIN0), + P1_1 = (PIN_GROUP1+PIN1), + P1_2 = (PIN_GROUP1+PIN2), + P1_3 = (PIN_GROUP1+PIN3), + P1_4 = (PIN_GROUP1+PIN4), + P1_5 = (PIN_GROUP1+PIN5), + P1_6 = (PIN_GROUP1+PIN6), + P1_7 = (PIN_GROUP1+PIN7), + P1_8 = (PIN_GROUP1+PIN8), + P1_9 = (PIN_GROUP1+PIN9), + P1_10 = (PIN_GROUP1+PIN10), + P1_11 = (PIN_GROUP1+PIN11), + P1_12 = (PIN_GROUP1+PIN12), + P1_13 = (PIN_GROUP1+PIN13), + P1_14 = (PIN_GROUP1+PIN14), + P1_15 = (PIN_GROUP1+PIN15), + P1_16 = (PIN_GROUP1+PIN16), + + /* P1_17 is High-Drive pin */ + P1_17 = (PIN_GROUP1+PIN17), + + P1_18 = (PIN_GROUP1+PIN18), + P1_19 = (PIN_GROUP1+PIN19), + P1_20 = (PIN_GROUP1+PIN20), + + /* Group Port 2 */ + P2_0 = (PIN_GROUP2+PIN0), + P2_1 = (PIN_GROUP2+PIN1), + P2_2 = (PIN_GROUP2+PIN2), + + /* P2_3 to P2_5 are High-Drive pins */ + P2_3 = (PIN_GROUP2+PIN3), + P2_4 = (PIN_GROUP2+PIN4), + P2_5 = (PIN_GROUP2+PIN5), + + P2_6 = (PIN_GROUP2+PIN6), + P2_7 = (PIN_GROUP2+PIN7), + P2_8 = (PIN_GROUP2+PIN8), + P2_9 = (PIN_GROUP2+PIN9), + P2_10 = (PIN_GROUP2+PIN10), + P2_11 = (PIN_GROUP2+PIN11), + P2_12 = (PIN_GROUP2+PIN12), + P2_13 = (PIN_GROUP2+PIN13), + + /* Group Port 3 */ + P3_0 = (PIN_GROUP3+PIN0), + P3_1 = (PIN_GROUP3+PIN1), + P3_2 = (PIN_GROUP3+PIN2), + + /* P3_3 is High-Speed pin */ + P3_3 = (PIN_GROUP3+PIN3), + + P3_4 = (PIN_GROUP3+PIN4), + P3_5 = (PIN_GROUP3+PIN5), + P3_6 = (PIN_GROUP3+PIN6), + P3_7 = (PIN_GROUP3+PIN7), + P3_8 = (PIN_GROUP3+PIN8), + + /* Group Port 4 */ + P4_0 = (PIN_GROUP4+PIN0), + P4_1 = (PIN_GROUP4+PIN1), + P4_2 = (PIN_GROUP4+PIN2), + P4_3 = (PIN_GROUP4+PIN3), + P4_4 = (PIN_GROUP4+PIN4), + P4_5 = (PIN_GROUP4+PIN5), + P4_6 = (PIN_GROUP4+PIN6), + P4_7 = (PIN_GROUP4+PIN7), + P4_8 = (PIN_GROUP4+PIN8), + P4_9 = (PIN_GROUP4+PIN9), + P4_10 = (PIN_GROUP4+PIN10), + + /* Group Port 5 */ + P5_0 = (PIN_GROUP5+PIN0), + P5_1 = (PIN_GROUP5+PIN1), + P5_2 = (PIN_GROUP5+PIN2), + P5_3 = (PIN_GROUP5+PIN3), + P5_4 = (PIN_GROUP5+PIN4), + P5_5 = (PIN_GROUP5+PIN5), + P5_6 = (PIN_GROUP5+PIN6), + P5_7 = (PIN_GROUP5+PIN7), + + /* Group Port 6 */ + P6_0 = (PIN_GROUP6+PIN0), + P6_1 = (PIN_GROUP6+PIN1), + P6_2 = (PIN_GROUP6+PIN2), + P6_3 = (PIN_GROUP6+PIN3), + P6_4 = (PIN_GROUP6+PIN4), + P6_5 = (PIN_GROUP6+PIN5), + P6_6 = (PIN_GROUP6+PIN6), + P6_7 = (PIN_GROUP6+PIN7), + P6_8 = (PIN_GROUP6+PIN8), + P6_9 = (PIN_GROUP6+PIN9), + P6_10 = (PIN_GROUP6+PIN10), + P6_11 = (PIN_GROUP6+PIN11), + P6_12 = (PIN_GROUP6+PIN12), + + /* Group Port 7 */ + P7_0 = (PIN_GROUP7+PIN0), + P7_1 = (PIN_GROUP7+PIN1), + P7_2 = (PIN_GROUP7+PIN2), + P7_3 = (PIN_GROUP7+PIN3), + P7_4 = (PIN_GROUP7+PIN4), + P7_5 = (PIN_GROUP7+PIN5), + P7_6 = (PIN_GROUP7+PIN6), + P7_7 = (PIN_GROUP7+PIN7), + + /* Group Port 8 */ + /* P8_0 to P8_2 are High-Drive pins */ + P8_0 = (PIN_GROUP8+PIN0), + P8_1 = (PIN_GROUP8+PIN1), + P8_2 = (PIN_GROUP8+PIN2), + + P8_3 = (PIN_GROUP8+PIN3), + P8_4 = (PIN_GROUP8+PIN4), + P8_5 = (PIN_GROUP8+PIN5), + P8_6 = (PIN_GROUP8+PIN6), + P8_7 = (PIN_GROUP8+PIN7), + P8_8 = (PIN_GROUP8+PIN8), + + /* Group Port 9 */ + P9_0 = (PIN_GROUP9+PIN0), + P9_1 = (PIN_GROUP9+PIN1), + P9_2 = (PIN_GROUP9+PIN2), + P9_3 = (PIN_GROUP9+PIN3), + P9_4 = (PIN_GROUP9+PIN4), + P9_5 = (PIN_GROUP9+PIN5), + P9_6 = (PIN_GROUP9+PIN6), + + /* Group Port A */ + PA_0 = (PIN_GROUPA+PIN0), + /* PA_1 to PA_3 are Normal & High-Drive Pins */ + PA_1 = (PIN_GROUPA+PIN1), + PA_2 = (PIN_GROUPA+PIN2), + PA_3 = (PIN_GROUPA+PIN3), + PA_4 = (PIN_GROUPA+PIN4), + + /* Group Port B */ + PB_0 = (PIN_GROUPB+PIN0), + PB_1 = (PIN_GROUPB+PIN1), + PB_2 = (PIN_GROUPB+PIN2), + PB_3 = (PIN_GROUPB+PIN3), + PB_4 = (PIN_GROUPB+PIN4), + PB_5 = (PIN_GROUPB+PIN5), + PB_6 = (PIN_GROUPB+PIN6), + + /* Group Port C */ + PC_0 = (PIN_GROUPC+PIN0), + PC_1 = (PIN_GROUPC+PIN1), + PC_2 = (PIN_GROUPC+PIN2), + PC_3 = (PIN_GROUPC+PIN3), + PC_4 = (PIN_GROUPC+PIN4), + PC_5 = (PIN_GROUPC+PIN5), + PC_6 = (PIN_GROUPC+PIN6), + PC_7 = (PIN_GROUPC+PIN7), + PC_8 = (PIN_GROUPC+PIN8), + PC_9 = (PIN_GROUPC+PIN9), + PC_10 = (PIN_GROUPC+PIN10), + PC_11 = (PIN_GROUPC+PIN11), + PC_12 = (PIN_GROUPC+PIN12), + PC_13 = (PIN_GROUPC+PIN13), + PC_14 = (PIN_GROUPC+PIN14), + + /* Group Port D (seems not configurable through SCU, not defined in UM10503.pdf Rev.1, keep it here) */ + PD_0 = (PIN_GROUPD+PIN0), + PD_1 = (PIN_GROUPD+PIN1), + PD_2 = (PIN_GROUPD+PIN2), + PD_3 = (PIN_GROUPD+PIN3), + PD_4 = (PIN_GROUPD+PIN4), + PD_5 = (PIN_GROUPD+PIN5), + PD_6 = (PIN_GROUPD+PIN6), + PD_7 = (PIN_GROUPD+PIN7), + PD_8 = (PIN_GROUPD+PIN8), + PD_9 = (PIN_GROUPD+PIN9), + PD_10 = (PIN_GROUPD+PIN10), + PD_11 = (PIN_GROUPD+PIN11), + PD_12 = (PIN_GROUPD+PIN12), + PD_13 = (PIN_GROUPD+PIN13), + PD_14 = (PIN_GROUPD+PIN14), + PD_15 = (PIN_GROUPD+PIN15), + PD_16 = (PIN_GROUPD+PIN16), + + /* Group Port E */ + PE_0 = (PIN_GROUPE+PIN0), + PE_1 = (PIN_GROUPE+PIN1), + PE_2 = (PIN_GROUPE+PIN2), + PE_3 = (PIN_GROUPE+PIN3), + PE_4 = (PIN_GROUPE+PIN4), + PE_5 = (PIN_GROUPE+PIN5), + PE_6 = (PIN_GROUPE+PIN6), + PE_7 = (PIN_GROUPE+PIN7), + PE_8 = (PIN_GROUPE+PIN8), + PE_9 = (PIN_GROUPE+PIN9), + PE_10 = (PIN_GROUPE+PIN10), + PE_11 = (PIN_GROUPE+PIN11), + PE_12 = (PIN_GROUPE+PIN12), + PE_13 = (PIN_GROUPE+PIN13), + PE_14 = (PIN_GROUPE+PIN14), + PE_15 = (PIN_GROUPE+PIN15), + + /* Group Port F */ + PF_0 = (PIN_GROUPF+PIN0), + PF_1 = (PIN_GROUPF+PIN1), + PF_2 = (PIN_GROUPF+PIN2), + PF_3 = (PIN_GROUPF+PIN3), + PF_4 = (PIN_GROUPF+PIN4), + PF_5 = (PIN_GROUPF+PIN5), + PF_6 = (PIN_GROUPF+PIN6), + PF_7 = (PIN_GROUPF+PIN7), + PF_8 = (PIN_GROUPF+PIN8), + PF_9 = (PIN_GROUPF+PIN9), + PF_10 = (PIN_GROUPF+PIN10), + PF_11 = (PIN_GROUPF+PIN11), + + /* Group Clock 0 to 3 High-Speed pins */ + CLK0 = (SCU_BASE + 0xC00), + CLK1 = (SCU_BASE + 0xC04), + CLK2 = (SCU_BASE + 0xC08), + CLK3 = (SCU_BASE + 0xC0C) + +} scu_grp_pin_t; + +/******************************************************************/ +/* Pin Configuration to be used for scu_pinmux() parameter scu_conf + For normal-drive pins, high-drive pins, high-speed pins */ +/******************************************************************/ +/* Function BIT0 to 2. +Common to normal-drive pins, high-drive pins, high-speed pins. */ +#define SCU_CONF_FUNCTION0 (0x0) +#define SCU_CONF_FUNCTION1 (0x1) +#define SCU_CONF_FUNCTION2 (0x2) +#define SCU_CONF_FUNCTION3 (0x3) +#define SCU_CONF_FUNCTION4 (0x4) +#define SCU_CONF_FUNCTION5 (0x5) +#define SCU_CONF_FUNCTION6 (0x6) +#define SCU_CONF_FUNCTION7 (0x7) + +/* Enable pull-down resistor at pad +By default=0 Disable pull-down. +Available to normal-drive pins, high-drive pins, high-speed pins */ +#define SCU_CONF_EPD_EN_PULLDOWN (BIT3) + +/* Disable pull-up resistor at pad. +By default=0 the pull-up resistor is enabled at reset. +Available to normal-drive pins, high-drive pins, high-speed pins */ +#define SCU_CONF_EPUN_DIS_PULLUP (BIT4) + +/* Select Slew Rate. +By Default=0 Slow. +Available to normal-drive pins and high-speed pins, reserved for high-drive pins. */ +#define SCU_CONF_EHS_FAST (BIT5) + +/* Input buffer enable. +By Default=0 Disable Input Buffer. +The input buffer is disabled by default at reset and must be enabled +for receiving(in normal/highspeed-drive) or to transfer data from the I/O buffer to the pad(in high-drive pins). +Available to normal-drive pins, high-drive pins, high-speed pins */ +#define SCU_CONF_EZI_EN_IN_BUFFER (BIT6) + +/* Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz. +Available to normal-drive pins, high-drive pins, high-speed pins */ +#define SCU_CONF_ZIF_DIS_IN_GLITCH_FILT (BIT7) + +/* Select drive strength. (default=0 Normal-drive: 4 mA drive strength) (BIT8/9) +Available to high-drive pins, reserved for others. */ +#define SCU_CONF_EHD_NORMAL_DRIVE_8MILLIA (0x100) +#define SCU_CONF_EHD_NORMAL_DRIVE_14MILLIA (0x200) +#define SCU_CONF_EHD_NORMAL_DRIVE_20MILLIA (0x300) + +/* BIT10 to 31 are Reserved */ + +/* Configuration for different I/O pins types */ +#define SCU_EMC_IO (SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) +#define SCU_LCD (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) +#define SCU_CLK_IN (SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) +#define SCU_CLK_OUT (SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) +#define SCU_GPIO_PUP (SCU_CONF_EZI_EN_IN_BUFFER) +#define SCU_GPIO_PDN (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EZI_EN_IN_BUFFER) +#define SCU_GPIO_NOPULL (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EZI_EN_IN_BUFFER) +#define SCU_GPIO_FAST (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) +#define SCU_UART_RX_TX (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EZI_EN_IN_BUFFER) +#define SCU_SSP_IO (SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) + +void scu_pinmux(scu_grp_pin_t group_pin, u32 scu_conf); #endif diff --git a/lib/lpc43xx/Makefile b/lib/lpc43xx/Makefile index 4b8eae4..dd6f1cd 100644 --- a/lib/lpc43xx/Makefile +++ b/lib/lpc43xx/Makefile @@ -3,6 +3,7 @@ ## ## Copyright (C) 2009 Uwe Hermann ## Copyright (C) 2012 Michael Ossmann +## Copyright (C) 2012 Benjamin Vernoux ## ## This library is free software: you can redistribute it and/or modify ## it under the terms of the GNU Lesser General Public License as published by @@ -24,13 +25,13 @@ PREFIX ?= arm-none-eabi #PREFIX ?= arm-elf CC = $(PREFIX)-gcc AR = $(PREFIX)-ar -CFLAGS = -O0 -g -Wall -Wextra -I../../include -fno-common \ +CFLAGS = -O2 -g -Wall -Wextra -I../../include -fno-common \ -mcpu=cortex-m4 -mthumb -Wstrict-prototypes \ -ffunction-sections -fdata-sections -MD \ -mfloat-abi=hard -mfpu=fpv4-sp-d16 # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = gpio.o vector.o +OBJS = gpio.o vector.o scu.o # VPATH += ../usb diff --git a/lib/lpc43xx/scu.c b/lib/lpc43xx/scu.c new file mode 100644 index 0000000..bc495cd --- /dev/null +++ b/lib/lpc43xx/scu.c @@ -0,0 +1,30 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Benjamin Vernoux + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include + +/* For pin_conf_normal value see scu.h define SCU_CONF_XXX or Configuration for different I/O pins types */ +void scu_pinmux(scu_grp_pin_t group_pin, u32 scu_conf) +{ + MMIO32(group_pin) = scu_conf; +} + +/* For other special SCU register USB1, I2C0, ADC0/1, DAC, EMC clock delay See scu.h */ + +/* For Pin interrupt select register see scu.h SCU_PINTSEL0 & SCU_PINTSEL1 */ -- cgit v1.2.3 From 67a048b5b054f9470d45f7285a622f4dc90aff78 Mon Sep 17 00:00:00 2001 From: TitanMKD Date: Sun, 3 Jun 2012 18:57:33 +0200 Subject: Added SCU I2C0 specific configuration. --- .../lpc43xx/hackrf-jellybean/miniblink/miniblink.c | 3 + include/libopencm3/lpc43xx/scu.h | 74 ++++++++++++++++++++++ 2 files changed, 77 insertions(+) (limited to 'examples/lpc43xx') diff --git a/examples/lpc43xx/hackrf-jellybean/miniblink/miniblink.c b/examples/lpc43xx/hackrf-jellybean/miniblink/miniblink.c index 567d9dc..2826126 100644 --- a/examples/lpc43xx/hackrf-jellybean/miniblink/miniblink.c +++ b/examples/lpc43xx/hackrf-jellybean/miniblink/miniblink.c @@ -37,6 +37,9 @@ void gpio_setup(void) scu_pinmux(SCU_PINMUX_BOOT2, SCU_GPIO_FAST); scu_pinmux(SCU_PINMUX_BOOT3, SCU_GPIO_FAST); + /* Configure SCU I2C0 Peripheral (to be moved later in I2C driver) */ + SCU_SFSI2C0 = SCU_I2C0_NOMINAL; + /* Configure all GPIO as Input (safe state) */ GPIO0_DIR = 0; GPIO1_DIR = 0; diff --git a/include/libopencm3/lpc43xx/scu.h b/include/libopencm3/lpc43xx/scu.h index 146aafc..324ee57 100644 --- a/include/libopencm3/lpc43xx/scu.h +++ b/include/libopencm3/lpc43xx/scu.h @@ -312,6 +312,80 @@ /* Pin interrupt select register for pin interrupts 4 to 7 */ #define SCU_PINTSEL1 MMIO32(SCU_BASE + 0xE04) +/**************************/ +/* SCU I2C0 Configuration */ +/**************************/ +/* Select input glitch filter time constant for the SCL pin. + 0 = 50 ns glitch filter. + 1 = 3ns glitch filter. + */ +#define SCU_SCL_EFP (BIT0) + +/* BIT1 Reserved. Always write a 0 to this bit. */ + +/* Select I2C mode for the SCL pin. + 0 = Standard/Fast mode transmit. + 1 = Fast-mode Plus transmit. +*/ +#define SCU_SCL_EHD (BIT2) + +/* Enable the input receiver for the SCL pin. +Always write a 1 to this bit when using the +I2C0. + 0 = Disabled. + 1 = Enabled. +*/ +#define SCU_SCL_EZI_EN (BIT3) + +/* BIT4-6 Reserved. */ + +/* Enable or disable input glitch filter for the +SCL pin. The filter time constant is +determined by bit EFP. + 0 = Enable input filter. + 1 = Disable input filter. +*/ +#define SCU_SCL_ZIF_DIS (BIT7) + +/* Select input glitch filter time constant for the SDA pin. + 0 = 50 ns glitch filter. + 1 = 3ns glitch filter. + */ +#define SCU_SDA_EFP (BIT8) + +/* BIT9 Reserved. Always write a 0 to this bit. */ + +/* Select I2C mode for the SDA pin. + 0 = Standard/Fast mode transmit. + 1 = Fast-mode Plus transmit. +*/ +#define SCU_SDA_EHD (BIT10) + +/* Enable the input receiver for the SDA pin. +Always write a 1 to this bit when using the +I2C0. + 0 = Disabled. + 1 = Enabled. +*/ +#define SCU_SDA_EZI_EN (BIT11) + +/* BIT 12-14 - Reserved */ + +/* Enable or disable input glitch filter for the +SDA pin. The filter time constant is +determined by bit SDA_EFP. + 0 = Enable input filter. + 1 = Disable input filter. +*/ +#define SCU_SDA_ZIF_DIS (BIT15) + +/* Standard mode for I2C SCL/SDA Standard/Fast mode */ +#define SCU_I2C0_NOMINAL (SCU_SCL_EZI_EN | SCU_SDA_EZI_EN) + +/* Standard mode for I2C SCL/SDA Fast-mode Plus transmit */ +#define SCU_I2C0_FAST (SCU_SCL_EFP | SCU_SCL_EHD | SCU_SCL_EZI_EN | SCU_SCL_ZIF_DIS \ + SCU_SDA_EFP | SCU_SDA_EHD | SCU_SDA_EZI_EN) + /* SCU PIN Normal Drive: The pin configuration registers for normal-drive pins control the following pins: -- cgit v1.2.3 From b55d006d024fa100b3bba38685e97e292325c780 Mon Sep 17 00:00:00 2001 From: Michael Ossmann Date: Sun, 3 Jun 2012 14:55:51 -0600 Subject: got I2C demo working but stuff still needs to be moved out of here and into drivers --- examples/lpc43xx/hackrf-jellybean/i2c/README | 11 ++- examples/lpc43xx/hackrf-jellybean/i2c/i2cdemo.c | 96 +++++++++++++++++++++++-- 2 files changed, 101 insertions(+), 6 deletions(-) (limited to 'examples/lpc43xx') diff --git a/examples/lpc43xx/hackrf-jellybean/i2c/README b/examples/lpc43xx/hackrf-jellybean/i2c/README index 0785a11..14745f6 100644 --- a/examples/lpc43xx/hackrf-jellybean/i2c/README +++ b/examples/lpc43xx/hackrf-jellybean/i2c/README @@ -2,4 +2,13 @@ README ------------------------------------------------------------------------------ -This program exercises the I2C peripheral on Jellybean's LPC43xx. +This program exercises the I2C peripheral on Jellybean's LPC43xx. You can +scope SCL on P6 pin 3 and SDA on P6 pin 5. If Lemondrop is connected, LED1 +will illuminate if I2C communication to the Si5351C on Lemondrop is successful. + +Required Lemondrop -> Jellybean connections: + +SCL: Lemondrop P7 pin 3 -> Jellybean P6 pin 3 +SDA: Lemondrop P7 pin 5 -> Jellybean P6 pin 5 +VCC: Lemondrop P4 pin 2, 4, or 6 -> Jellybean P17 pin 2, 4, or 6 +GND: Lemondrop P5 -> Jellybean P13 diff --git a/examples/lpc43xx/hackrf-jellybean/i2c/i2cdemo.c b/examples/lpc43xx/hackrf-jellybean/i2c/i2cdemo.c index d6441ab..88bbec4 100644 --- a/examples/lpc43xx/hackrf-jellybean/i2c/i2cdemo.c +++ b/examples/lpc43xx/hackrf-jellybean/i2c/i2cdemo.c @@ -23,6 +23,11 @@ #include #include +void gpio_setup(void) +{ + GPIO2_DIR |= (1 << 1); /* Configure GPIO2[1] (P4_1) as output. */ +} + //FIXME generalize and move to drivers #define SCU_SFSI2C0_SCL_EFP (1 << 1) /* 3 ns glitch filter */ @@ -75,12 +80,13 @@ void i2c0_init() //FIXME assuming we're on IRC at 96 MHz /* 400 kHz I2C */ - I2C0_SCLH = 120; - I2C0_SCLL = 120; + //I2C0_SCLH = 120; + //I2C0_SCLL = 120; /* 100 kHz I2C */ - //I2C0_SCLH = 480; - //I2C0_SCLL = 480; + I2C0_SCLH = 480; + I2C0_SCLL = 480; + //FIXME not sure why this appears to run at about 290 kHz /* clear the control bits */ I2C0_CONCLR = (I2C_CONCLR_AAC | I2C_CONCLR_SIC @@ -90,13 +96,93 @@ void i2c0_init() I2C0_CONSET = I2C_CONSET_I2EN; } +/* transmit start bit */ +void i2c0_tx_start() +{ + I2C0_CONCLR = I2C_CONCLR_SIC; + I2C0_CONSET = I2C_CONSET_STA; + while (!(I2C0_CONSET & I2C_CONSET_SI)); + I2C0_CONCLR = I2C_CONCLR_STAC; +} + +/* transmit data byte */ +void i2c0_tx_byte(u8 byte) +{ + if (I2C0_CONSET & I2C_CONSET_STA) + I2C0_CONCLR = I2C_CONCLR_STAC; + I2C0_DAT = byte; + I2C0_CONCLR = I2C_CONCLR_SIC; + while (!(I2C0_CONSET & I2C_CONSET_SI)); +} + +/* receive data byte */ +u8 i2c0_rx_byte() +{ + if (I2C0_CONSET & I2C_CONSET_STA) + I2C0_CONCLR = I2C_CONCLR_STAC; + I2C0_CONCLR = I2C_CONCLR_SIC; + while (!(I2C0_CONSET & I2C_CONSET_SI)); + return I2C0_DAT; +} + +/* transmit stop bit */ +void i2c0_stop() +{ + if (I2C0_CONSET & I2C_CONSET_STA) + I2C0_CONCLR = I2C_CONCLR_STAC; + I2C0_CONSET = I2C_CONSET_STO; + I2C0_CONCLR = I2C_CONCLR_SIC; +} + +#define SI5351C_I2C_ADDR (0x60 << 1) +#define I2C_WRITE 0 +#define I2C_READ 1 + +/* write to single register */ +void si5351c_write_reg(uint8_t reg, uint8_t val) +{ + i2c0_tx_start(); + i2c0_tx_byte(SI5351C_I2C_ADDR | I2C_WRITE); + i2c0_tx_byte(reg); + i2c0_tx_byte(val); + i2c0_stop(); +} + +/* read single register */ +uint8_t si5351c_read_reg(uint8_t reg) +{ + uint8_t val; + + /* set register address with write */ + i2c0_tx_start(); + i2c0_tx_byte(SI5351C_I2C_ADDR | I2C_WRITE); + i2c0_tx_byte(reg); + + /* read the value */ + i2c0_tx_start(); + i2c0_tx_byte(SI5351C_I2C_ADDR | I2C_READ); + val = i2c0_rx_byte(); + i2c0_stop(); + + return val; +} + int main(void) { int i; + gpio_setup(); i2c0_init(); - //TODO I2C tx/rx + while (1) { + if (si5351c_read_reg(0) == 0x10) + gpio_set(GPIO2, GPIOPIN1); /* LED on */ + else + gpio_clear(GPIO2, GPIOPIN1); /* LED off */ + + for (i = 0; i < 1000; i++) /* Wait a bit. */ + __asm__("nop"); + } return 0; } -- cgit v1.2.3 From 44db38301c2a6f7eefa8b7acc68eb0a5e46ec4d5 Mon Sep 17 00:00:00 2001 From: Michael Ossmann Date: Mon, 4 Jun 2012 16:41:12 -0600 Subject: fixed i2cdemo to supply 1V8 for Si5351C output supply --- examples/lpc43xx/hackrf-jellybean/i2c/README | 1 + examples/lpc43xx/hackrf-jellybean/i2c/i2cdemo.c | 33 ++++++++++++++++++++++++- 2 files changed, 33 insertions(+), 1 deletion(-) (limited to 'examples/lpc43xx') diff --git a/examples/lpc43xx/hackrf-jellybean/i2c/README b/examples/lpc43xx/hackrf-jellybean/i2c/README index 14745f6..86763fe 100644 --- a/examples/lpc43xx/hackrf-jellybean/i2c/README +++ b/examples/lpc43xx/hackrf-jellybean/i2c/README @@ -11,4 +11,5 @@ Required Lemondrop -> Jellybean connections: SCL: Lemondrop P7 pin 3 -> Jellybean P6 pin 3 SDA: Lemondrop P7 pin 5 -> Jellybean P6 pin 5 VCC: Lemondrop P4 pin 2, 4, or 6 -> Jellybean P17 pin 2, 4, or 6 +1V8: Lemondrop P11 pin 2, 4, or 6 -> Jellybean P16 pin 2, 4, or 6 GND: Lemondrop P5 -> Jellybean P13 diff --git a/examples/lpc43xx/hackrf-jellybean/i2c/i2cdemo.c b/examples/lpc43xx/hackrf-jellybean/i2c/i2cdemo.c index 88bbec4..7198bb3 100644 --- a/examples/lpc43xx/hackrf-jellybean/i2c/i2cdemo.c +++ b/examples/lpc43xx/hackrf-jellybean/i2c/i2cdemo.c @@ -23,9 +23,38 @@ #include #include +#include "../jellybean_conf.h" + void gpio_setup(void) { - GPIO2_DIR |= (1 << 1); /* Configure GPIO2[1] (P4_1) as output. */ + /* Configure SCU Pin Mux as GPIO */ + scu_pinmux(SCU_PINMUX_LED1, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_LED2, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_LED3, SCU_GPIO_FAST); + + scu_pinmux(SCU_PINMUX_EN1V8, SCU_GPIO_FAST); + + scu_pinmux(SCU_PINMUX_BOOT0, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_BOOT1, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_BOOT2, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_BOOT3, SCU_GPIO_FAST); + + /* Configure SCU I2C0 Peripheral */ + SCU_SFSI2C0 = SCU_I2C0_NOMINAL; + + /* Configure all GPIO as Input (safe state) */ + GPIO0_DIR = 0; + GPIO1_DIR = 0; + GPIO2_DIR = 0; + GPIO3_DIR = 0; + GPIO4_DIR = 0; + GPIO5_DIR = 0; + GPIO6_DIR = 0; + GPIO7_DIR = 0; + + /* Configure GPIO as Output */ + GPIO2_DIR |= (PIN_LED1|PIN_LED2|PIN_LED3); /* Configure GPIO2[1/2/8] (P4_1/2 P6_12) as output. */ + GPIO3_DIR |= PIN_EN1V8; /* GPIO3[6] on P6_10 as output. */ } //FIXME generalize and move to drivers @@ -174,6 +203,8 @@ int main(void) gpio_setup(); i2c0_init(); + gpio_set(PORT_EN1V8, PIN_EN1V8); /* 1V8 on */ + while (1) { if (si5351c_read_reg(0) == 0x10) gpio_set(GPIO2, GPIOPIN1); /* LED on */ -- cgit v1.2.3 From 569801687744d5f4f4157ea186a8a6c1d159d285 Mon Sep 17 00:00:00 2001 From: Michael Ossmann Date: Mon, 4 Jun 2012 17:30:08 -0600 Subject: moved stuff out of i2cdemo.c and into drivers/headers --- examples/lpc43xx/hackrf-jellybean/i2c/i2cdemo.c | 113 ------------------------ include/libopencm3/lpc43xx/cgu.h | 23 +++++ include/libopencm3/lpc43xx/i2c.h | 29 +++++- lib/lpc43xx/Makefile | 2 +- 4 files changed, 52 insertions(+), 115 deletions(-) (limited to 'examples/lpc43xx') diff --git a/examples/lpc43xx/hackrf-jellybean/i2c/i2cdemo.c b/examples/lpc43xx/hackrf-jellybean/i2c/i2cdemo.c index 7198bb3..102365b 100644 --- a/examples/lpc43xx/hackrf-jellybean/i2c/i2cdemo.c +++ b/examples/lpc43xx/hackrf-jellybean/i2c/i2cdemo.c @@ -19,8 +19,6 @@ */ #include -#include -#include #include #include "../jellybean_conf.h" @@ -39,9 +37,6 @@ void gpio_setup(void) scu_pinmux(SCU_PINMUX_BOOT2, SCU_GPIO_FAST); scu_pinmux(SCU_PINMUX_BOOT3, SCU_GPIO_FAST); - /* Configure SCU I2C0 Peripheral */ - SCU_SFSI2C0 = SCU_I2C0_NOMINAL; - /* Configure all GPIO as Input (safe state) */ GPIO0_DIR = 0; GPIO1_DIR = 0; @@ -57,115 +52,7 @@ void gpio_setup(void) GPIO3_DIR |= PIN_EN1V8; /* GPIO3[6] on P6_10 as output. */ } -//FIXME generalize and move to drivers - -#define SCU_SFSI2C0_SCL_EFP (1 << 1) /* 3 ns glitch filter */ -#define SCU_SFSI2C0_SCL_EHD (1 << 2) /* Fast-mode Plus transmit */ -#define SCU_SFSI2C0_SCL_EZI (1 << 3) /* Enable the input receiver */ -#define SCU_SFSI2C0_SCL_ZIF (1 << 7) /* Disable input glitch filter */ -#define SCU_SFSI2C0_SDA_EFP (1 << 8) /* 3 ns glitch filter */ -#define SCU_SFSI2C0_SDA_EHD (1 << 10) /* Fast-mode Plus transmit */ -#define SCU_SFSI2C0_SDA_EZI (1 << 11) /* Enable the input receiver */ -#define SCU_SFSI2C0_SDA_ZIF (1 << 15) /* Disable input glitch filter */ - -#define I2C_CONCLR_AAC (1 << 2) /* Assert acknowledge Clear */ -#define I2C_CONCLR_SIC (1 << 3) /* I2C interrupt Clear */ -#define I2C_CONCLR_STAC (1 << 5) /* START flag Clear */ -#define I2C_CONCLR_I2ENC (1 << 6) /* I2C interface Disable bit */ - -#define I2C_CONSET_AA (1 << 2) /* Assert acknowledge flag */ -#define I2C_CONSET_SI (1 << 3) /* I2C interrupt flag */ -#define I2C_CONSET_STO (1 << 4) /* STOP flag */ -#define I2C_CONSET_STA (1 << 5) /* START flag */ -#define I2C_CONSET_I2EN (1 << 6) /* I2C interface enable */ - -#define CGU_SRC_32K 0x00 -#define CGU_SRC_IRC 0x01 -#define CGU_SRC_ENET_RX 0x02 -#define CGU_SRC_ENET_TX 0x03 -#define CGU_SRC_GP_CLKIN 0x04 -#define CGU_SRC_XTAL 0x06 -#define CGU_SRC_PLL0USB 0x07 -#define CGU_SRC_PLL0AUDIO 0x08 -#define CGU_SRC_PLL1 0x09 -#define CGU_SRC_IDIVA 0x0C -#define CGU_SRC_IDIVB 0x0D -#define CGU_SRC_IDIVC 0x0E -#define CGU_SRC_IDIVD 0x0F -#define CGU_SRC_IDIVE 0x10 - -#define CGU_BASE_CLK_PD (1 << 0) /* output stage power-down */ -#define CGU_BASE_CLK_AUTOBLOCK (1 << 11) /* block clock automatically */ -#define CGU_BASE_CLK_SEL_SHIFT 24 /* clock source selection (5 bits) */ - -void i2c0_init() -{ - /* enable input on SCL and SDA pins */ - SCU_SFSI2C0 = (SCU_SFSI2C0_SCL_EZI | SCU_SFSI2C0_SDA_EZI); - - /* use PLL1 as clock source for APB1 (including I2C0) */ - CGU_BASE_APB1_CLK = (CGU_SRC_PLL1 << CGU_BASE_CLK_SEL_SHIFT); - - //FIXME assuming we're on IRC at 96 MHz - - /* 400 kHz I2C */ - //I2C0_SCLH = 120; - //I2C0_SCLL = 120; - - /* 100 kHz I2C */ - I2C0_SCLH = 480; - I2C0_SCLL = 480; - //FIXME not sure why this appears to run at about 290 kHz - - /* clear the control bits */ - I2C0_CONCLR = (I2C_CONCLR_AAC | I2C_CONCLR_SIC - | I2C_CONCLR_STAC | I2C_CONCLR_I2ENC); - - /* enable I2C0 */ - I2C0_CONSET = I2C_CONSET_I2EN; -} - -/* transmit start bit */ -void i2c0_tx_start() -{ - I2C0_CONCLR = I2C_CONCLR_SIC; - I2C0_CONSET = I2C_CONSET_STA; - while (!(I2C0_CONSET & I2C_CONSET_SI)); - I2C0_CONCLR = I2C_CONCLR_STAC; -} - -/* transmit data byte */ -void i2c0_tx_byte(u8 byte) -{ - if (I2C0_CONSET & I2C_CONSET_STA) - I2C0_CONCLR = I2C_CONCLR_STAC; - I2C0_DAT = byte; - I2C0_CONCLR = I2C_CONCLR_SIC; - while (!(I2C0_CONSET & I2C_CONSET_SI)); -} - -/* receive data byte */ -u8 i2c0_rx_byte() -{ - if (I2C0_CONSET & I2C_CONSET_STA) - I2C0_CONCLR = I2C_CONCLR_STAC; - I2C0_CONCLR = I2C_CONCLR_SIC; - while (!(I2C0_CONSET & I2C_CONSET_SI)); - return I2C0_DAT; -} - -/* transmit stop bit */ -void i2c0_stop() -{ - if (I2C0_CONSET & I2C_CONSET_STA) - I2C0_CONCLR = I2C_CONCLR_STAC; - I2C0_CONSET = I2C_CONSET_STO; - I2C0_CONCLR = I2C_CONCLR_SIC; -} - #define SI5351C_I2C_ADDR (0x60 << 1) -#define I2C_WRITE 0 -#define I2C_READ 1 /* write to single register */ void si5351c_write_reg(uint8_t reg, uint8_t val) diff --git a/include/libopencm3/lpc43xx/cgu.h b/include/libopencm3/lpc43xx/cgu.h index 1234834..48eb9cb 100644 --- a/include/libopencm3/lpc43xx/cgu.h +++ b/include/libopencm3/lpc43xx/cgu.h @@ -163,4 +163,27 @@ /* Output stage 27 control CLK register for base clock */ #define CGU_BASE_CGU_OUT1_CLK MMIO32(CGU_BASE + 0x0C8) +/* --- CGU_BASE_x_CLK values ----------------------------------------------- */ + +#define CGU_BASE_CLK_PD (1 << 0) /* output stage power-down */ +#define CGU_BASE_CLK_AUTOBLOCK (1 << 11) /* block clock automatically */ +#define CGU_BASE_CLK_SEL_SHIFT 24 /* clock source selection (5 bits) */ + +/* --- CGU_BASE_x_CLK clock sources --------------------------------------- */ + +#define CGU_SRC_32K 0x00 +#define CGU_SRC_IRC 0x01 +#define CGU_SRC_ENET_RX 0x02 +#define CGU_SRC_ENET_TX 0x03 +#define CGU_SRC_GP_CLKIN 0x04 +#define CGU_SRC_XTAL 0x06 +#define CGU_SRC_PLL0USB 0x07 +#define CGU_SRC_PLL0AUDIO 0x08 +#define CGU_SRC_PLL1 0x09 +#define CGU_SRC_IDIVA 0x0C +#define CGU_SRC_IDIVB 0x0D +#define CGU_SRC_IDIVC 0x0E +#define CGU_SRC_IDIVD 0x0F +#define CGU_SRC_IDIVE 0x10 + #endif diff --git a/include/libopencm3/lpc43xx/i2c.h b/include/libopencm3/lpc43xx/i2c.h index 1fe7655..249962c 100644 --- a/include/libopencm3/lpc43xx/i2c.h +++ b/include/libopencm3/lpc43xx/i2c.h @@ -29,7 +29,6 @@ #define I2C0 I2C0_BASE #define I2C1 I2C1_BASE - /* --- I2C registers ------------------------------------------------------- */ /* I2C Control Set Register */ @@ -112,4 +111,32 @@ #define I2C0_MASK3 I2C_MASK3(I2C0) #define I2C1_MASK3 I2C_MASK3(I2C1) +/* --- I2Cx_CONCLR values -------------------------------------------------- */ + +#define I2C_CONCLR_AAC (1 << 2) /* Assert acknowledge Clear */ +#define I2C_CONCLR_SIC (1 << 3) /* I2C interrupt Clear */ +#define I2C_CONCLR_STAC (1 << 5) /* START flag Clear */ +#define I2C_CONCLR_I2ENC (1 << 6) /* I2C interface Disable bit */ + +/* --- I2Cx_CONSET values -------------------------------------------------- */ + +#define I2C_CONSET_AA (1 << 2) /* Assert acknowledge flag */ +#define I2C_CONSET_SI (1 << 3) /* I2C interrupt flag */ +#define I2C_CONSET_STO (1 << 4) /* STOP flag */ +#define I2C_CONSET_STA (1 << 5) /* START flag */ +#define I2C_CONSET_I2EN (1 << 6) /* I2C interface enable */ + +/* --- I2C const definitions ----------------------------------------------- */ + +#define I2C_WRITE 0 +#define I2C_READ 1 + +/* --- I2C funtion prototypes----------------------------------------------- */ + +void i2c0_init(void); +void i2c0_tx_start(void); +void i2c0_tx_byte(u8 byte); +u8 i2c0_rx_byte(void); +void i2c0_stop(void); + #endif diff --git a/lib/lpc43xx/Makefile b/lib/lpc43xx/Makefile index 041e3bc..6df4b29 100644 --- a/lib/lpc43xx/Makefile +++ b/lib/lpc43xx/Makefile @@ -31,7 +31,7 @@ CFLAGS = -O2 -g -Wall -Wextra -I../../include -fno-common \ -mfloat-abi=hard -mfpu=fpv4-sp-d16 # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = gpio.o vector.o scu.o +OBJS = gpio.o vector.o scu.o i2c.o # VPATH += ../usb -- cgit v1.2.3 From d7a7fd9d3037a5e490be3e73027a11f779d7d35c Mon Sep 17 00:00:00 2001 From: TitanMKD Date: Tue, 5 Jun 2012 01:41:54 +0200 Subject: * Added SSP Driver (Not Tested). * Replaced leading space by tabulations. --- examples/lpc43xx/Makefile.include | 1 + examples/lpc43xx/hackrf-jellybean/jellybean_conf.h | 19 +- .../lpc43xx/hackrf-jellybean/miniblink/miniblink.c | 98 +- examples/lpc43xx/hackrf-jellybean/ssp/Makefile | 24 + examples/lpc43xx/hackrf-jellybean/ssp/README | 20 + examples/lpc43xx/hackrf-jellybean/ssp/sspdemo.c | 99 ++ include/libopencm3/lpc43xx/scu.h | 1228 ++++++++++---------- include/libopencm3/lpc43xx/ssp.h | 188 ++- lib/lpc43xx/Makefile | 2 +- lib/lpc43xx/scu.c | 36 +- lib/lpc43xx/ssp.c | 132 +++ 11 files changed, 1112 insertions(+), 735 deletions(-) create mode 100644 examples/lpc43xx/hackrf-jellybean/ssp/Makefile create mode 100644 examples/lpc43xx/hackrf-jellybean/ssp/README create mode 100644 examples/lpc43xx/hackrf-jellybean/ssp/sspdemo.c create mode 100644 lib/lpc43xx/ssp.c (limited to 'examples/lpc43xx') diff --git a/examples/lpc43xx/Makefile.include b/examples/lpc43xx/Makefile.include index 89e356d..588ddee 100644 --- a/examples/lpc43xx/Makefile.include +++ b/examples/lpc43xx/Makefile.include @@ -94,6 +94,7 @@ clean: $(Q)rm -f *.hex $(Q)rm -f *.srec $(Q)rm -f *.list + $(Q)rm -f *.map # FIXME: Replace STM32 stuff with proper LPC43XX OpenOCD support later. ifeq ($(OOCD_SERIAL),) diff --git a/examples/lpc43xx/hackrf-jellybean/jellybean_conf.h b/examples/lpc43xx/hackrf-jellybean/jellybean_conf.h index a5ad8d0..dc791b3 100644 --- a/examples/lpc43xx/hackrf-jellybean/jellybean_conf.h +++ b/examples/lpc43xx/hackrf-jellybean/jellybean_conf.h @@ -27,9 +27,9 @@ extern "C" #include -/************************/ -/* JellyBean SCU PinMux */ -/************************/ +/* + * JellyBean SCU PinMux + */ /* GPIO Output PinMux */ #define SCU_PINMUX_LED1 (P4_1) /* GPIO2[1] on P4_1 */ @@ -44,12 +44,17 @@ extern "C" #define SCU_PINMUX_BOOT2 (P2_8) /* GPIO5[7] on P2_8 */ #define SCU_PINMUX_BOOT3 (P2_9) /* GPIO1[10] on P2_9 */ -/* TODO add other Pins */ +/* SSP1 Peripheral PinMux */ +#define SCU_SSP1_MISO (P1_3) /* P1_3 */ +#define SCU_SSP1_MOSI (P1_4) /* P1_4 */ +#define SCU_SSP1_SCK (P1_19) /* P1_19 */ +#define SCU_SSP1_SSEL (P1_20) /* P1_20 */ -/**********************/ -/* JellyBean GPIO Pin */ -/**********************/ +/* TODO add other Pins */ +/* + * JellyBean GPIO Pin + */ /* GPIO Output */ #define PIN_LED1 (BIT1) /* GPIO2[1] on P4_1 */ #define PIN_LED2 (BIT2) /* GPIO2[2] on P4_2 */ diff --git a/examples/lpc43xx/hackrf-jellybean/miniblink/miniblink.c b/examples/lpc43xx/hackrf-jellybean/miniblink/miniblink.c index 2826126..b1a22fa 100644 --- a/examples/lpc43xx/hackrf-jellybean/miniblink/miniblink.c +++ b/examples/lpc43xx/hackrf-jellybean/miniblink/miniblink.c @@ -1,22 +1,22 @@ /* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Uwe Hermann - * Copyright (C) 2012 Michael Ossmann - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ +* This file is part of the libopencm3 project. +* +* Copyright (C) 2010 Uwe Hermann +* Copyright (C) 2012 Michael Ossmann +* +* This library is free software: you can redistribute it and/or modify +* it under the terms of the GNU Lesser General Public License as published by +* the Free Software Foundation, either version 3 of the License, or +* (at your option) any later version. +* +* This library is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU Lesser General Public License for more details. +* +* You should have received a copy of the GNU Lesser General Public License +* along with this library. If not, see . +*/ #include #include @@ -25,32 +25,38 @@ void gpio_setup(void) { - /* Configure SCU Pin Mux as GPIO */ - scu_pinmux(SCU_PINMUX_LED1, SCU_GPIO_FAST); - scu_pinmux(SCU_PINMUX_LED2, SCU_GPIO_FAST); - scu_pinmux(SCU_PINMUX_LED3, SCU_GPIO_FAST); + /* Configure SCU Pin Mux as GPIO */ + scu_pinmux(SCU_PINMUX_LED1, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_LED2, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_LED3, SCU_GPIO_FAST); - scu_pinmux(SCU_PINMUX_EN1V8, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_EN1V8, SCU_GPIO_FAST); - scu_pinmux(SCU_PINMUX_BOOT0, SCU_GPIO_FAST); - scu_pinmux(SCU_PINMUX_BOOT1, SCU_GPIO_FAST); - scu_pinmux(SCU_PINMUX_BOOT2, SCU_GPIO_FAST); - scu_pinmux(SCU_PINMUX_BOOT3, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_BOOT0, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_BOOT1, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_BOOT2, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_BOOT3, SCU_GPIO_FAST); - /* Configure SCU I2C0 Peripheral (to be moved later in I2C driver) */ - SCU_SFSI2C0 = SCU_I2C0_NOMINAL; + /* Configure SCU I2C0 Peripheral (to be moved later in I2C driver) */ + SCU_SFSI2C0 = SCU_I2C0_NOMINAL; - /* Configure all GPIO as Input (safe state) */ - GPIO0_DIR = 0; - GPIO1_DIR = 0; - GPIO2_DIR = 0; - GPIO3_DIR = 0; - GPIO4_DIR = 0; - GPIO5_DIR = 0; - GPIO6_DIR = 0; - GPIO7_DIR = 0; + /* Configure SSP1 Peripheral (to be moved later in SSP driver) */ + scu_pinmux(SCU_SSP1_MISO, (SCU_SSP_IO | SCU_CONF_FUNCTION5)); + scu_pinmux(SCU_SSP1_MOSI, (SCU_SSP_IO | SCU_CONF_FUNCTION5)); + scu_pinmux(SCU_SSP1_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION1)); + scu_pinmux(SCU_SSP1_SSEL, (SCU_SSP_IO | SCU_CONF_FUNCTION1)); - /* Configure GPIO as Output */ + /* Configure all GPIO as Input (safe state) */ + GPIO0_DIR = 0; + GPIO1_DIR = 0; + GPIO2_DIR = 0; + GPIO3_DIR = 0; + GPIO4_DIR = 0; + GPIO5_DIR = 0; + GPIO6_DIR = 0; + GPIO7_DIR = 0; + + /* Configure GPIO as Output */ GPIO2_DIR |= (PIN_LED1|PIN_LED2|PIN_LED3); /* Configure GPIO2[1/2/8] (P4_1/2 P6_12) as output. */ GPIO3_DIR |= PIN_EN1V8; /* GPIO3[6] on P6_10 as output. */ } @@ -62,16 +68,16 @@ int main(void) int i; gpio_setup(); - /* Set 1V8 */ - gpio_set(PORT_EN1V8, PIN_EN1V8); + /* Set 1V8 */ + gpio_set(PORT_EN1V8, PIN_EN1V8); /* Blink LED1/2/3 on the board and Read BOOT0/1/2/3 pins. */ while (1) - { - boot0 = BOOT0_STATE; - boot1 = BOOT1_STATE; - boot2 = BOOT2_STATE; - boot3 = BOOT3_STATE; + { + boot0 = BOOT0_STATE; + boot1 = BOOT1_STATE; + boot2 = BOOT2_STATE; + boot3 = BOOT3_STATE; gpio_set(PORT_LED1_3, (PIN_LED1|PIN_LED2|PIN_LED3)); /* LEDs on */ for (i = 0; i < 2000000; i++) /* Wait a bit. */ diff --git a/examples/lpc43xx/hackrf-jellybean/ssp/Makefile b/examples/lpc43xx/hackrf-jellybean/ssp/Makefile new file mode 100644 index 0000000..8a3b1cc --- /dev/null +++ b/examples/lpc43xx/hackrf-jellybean/ssp/Makefile @@ -0,0 +1,24 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2010 Uwe Hermann +## +## This library is free software: you can redistribute it and/or modify +## it under the terms of the GNU Lesser General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This library is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU Lesser General Public License for more details. +## +## You should have received a copy of the GNU Lesser General Public License +## along with this library. If not, see . +## + +BINARY = sspdemo + +LDSCRIPT = ../jellybean-lpc4330.ld + +include ../../Makefile.include diff --git a/examples/lpc43xx/hackrf-jellybean/ssp/README b/examples/lpc43xx/hackrf-jellybean/ssp/README new file mode 100644 index 0000000..9b43214 --- /dev/null +++ b/examples/lpc43xx/hackrf-jellybean/ssp/README @@ -0,0 +1,20 @@ +------------------------------------------------------------------------------ +README +------------------------------------------------------------------------------ + +This program exercises the SSP1 peripheral on Jellybean's LPC43xx. + + Jellybean (connector) + P9 SPI + |-----------------| + | Pin2 Pin4 Pin6 | +||------| | +|| Pin1 |Pin3 Pin5 | +||------|----------| +|-------| + +SSP1_MISO: Jellybean P9 SPI Pin6 +SSP1_MOSI: Jellybean P9 SPI Pin4 +SSP1_SCK: Jellybean P9 SPI Pin2 +SSP1_SSEL: Jellybean P9 SPI Pin3 +GND: Can be connected to P12 SD Pin1 diff --git a/examples/lpc43xx/hackrf-jellybean/ssp/sspdemo.c b/examples/lpc43xx/hackrf-jellybean/ssp/sspdemo.c new file mode 100644 index 0000000..388afc8 --- /dev/null +++ b/examples/lpc43xx/hackrf-jellybean/ssp/sspdemo.c @@ -0,0 +1,99 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Benjamin Vernoux + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include +#include +#include + +#include "../jellybean_conf.h" + +void gpio_setup(void) +{ + /* Configure SCU Pin Mux as GPIO */ + scu_pinmux(SCU_PINMUX_LED1, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_LED2, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_LED3, SCU_GPIO_FAST); + + scu_pinmux(SCU_PINMUX_EN1V8, SCU_GPIO_FAST); + + scu_pinmux(SCU_PINMUX_BOOT0, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_BOOT1, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_BOOT2, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_BOOT3, SCU_GPIO_FAST); + + /* Configure SSP1 Peripheral (to be moved later in SSP driver) */ + scu_pinmux(SCU_SSP1_MISO, (SCU_SSP_IO | SCU_CONF_FUNCTION5)); + scu_pinmux(SCU_SSP1_MOSI, (SCU_SSP_IO | SCU_CONF_FUNCTION5)); + scu_pinmux(SCU_SSP1_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION1)); + scu_pinmux(SCU_SSP1_SSEL, (SCU_SSP_IO | SCU_CONF_FUNCTION1)); + + /* Configure all GPIO as Input (safe state) */ + GPIO0_DIR = 0; + GPIO1_DIR = 0; + GPIO2_DIR = 0; + GPIO3_DIR = 0; + GPIO4_DIR = 0; + GPIO5_DIR = 0; + GPIO6_DIR = 0; + GPIO7_DIR = 0; + + /* Configure GPIO as Output */ + GPIO2_DIR |= (PIN_LED1|PIN_LED2|PIN_LED3); /* Configure GPIO2[1/2/8] (P4_1/2 P6_12) as output. */ + GPIO3_DIR |= PIN_EN1V8; /* GPIO3[6] on P6_10 as output. */ +} + +int main(void) +{ + int i; + u8 ssp_val; + u8 serial_clock_rate; + + gpio_setup(); + + /* FIX Me freq */ + serial_clock_rate = 128; + + ssp_init(SSP1_NUM, + SSP_DATA_8BITS, + SSP_FRAME_SPI, + SSP_CPOL_0_CPHA_0, + serial_clock_rate, + SSP_MODE_NORMAL, + SSP_MASTER, + SSP_SLAVE_OUT_ENABLE); + + ssp_val = 0x0; + + while (1) { + + ssp_write(SSP1_NUM, (u16)ssp_val); + + gpio_set(GPIO2, GPIOPIN1); /* LED on */ + + for (i = 0; i < 1000; i++) /* Wait a bit. */ + __asm__("nop"); + + gpio_clear(GPIO2, GPIOPIN1); /* LED off */ + + ssp_val++; + } + + return 0; +} diff --git a/include/libopencm3/lpc43xx/scu.h b/include/libopencm3/lpc43xx/scu.h index c61918a..b9be79f 100644 --- a/include/libopencm3/lpc43xx/scu.h +++ b/include/libopencm3/lpc43xx/scu.h @@ -1,22 +1,22 @@ /* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 Michael Ossmann - * Copyright (C) 2012 Benjamin Vernoux - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ +* This file is part of the libopencm3 project. +* +* Copyright (C) 2012 Michael Ossmann +* Copyright (C) 2012 Benjamin Vernoux +* +* This library is free software: you can redistribute it and/or modify +* it under the terms of the GNU Lesser General Public License as published by +* the Free Software Foundation, either version 3 of the License, or +* (at your option) any later version. +* +* This library is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU Lesser General Public License for more details. +* +* You should have received a copy of the GNU Lesser General Public License +* along with this library. If not, see . +*/ #ifndef LPC43XX_SCU_H #define LPC43XX_SCU_H @@ -27,703 +27,703 @@ /* --- Convenience macros -------------------------------------------------- */ /* Pin group base addresses */ -#define PIN_GROUP0 (SCU_BASE + 0x000) -#define PIN_GROUP1 (SCU_BASE + 0x080) -#define PIN_GROUP2 (SCU_BASE + 0x100) -#define PIN_GROUP3 (SCU_BASE + 0x180) -#define PIN_GROUP4 (SCU_BASE + 0x200) -#define PIN_GROUP5 (SCU_BASE + 0x280) -#define PIN_GROUP6 (SCU_BASE + 0x300) -#define PIN_GROUP7 (SCU_BASE + 0x380) -#define PIN_GROUP8 (SCU_BASE + 0x400) -#define PIN_GROUP9 (SCU_BASE + 0x480) -#define PIN_GROUPA (SCU_BASE + 0x500) -#define PIN_GROUPB (SCU_BASE + 0x580) -#define PIN_GROUPC (SCU_BASE + 0x600) -#define PIN_GROUPD (SCU_BASE + 0x680) -#define PIN_GROUPE (SCU_BASE + 0x700) -#define PIN_GROUPF (SCU_BASE + 0x780) - -#define PIN0 0x000 -#define PIN1 0x004 -#define PIN2 0x008 -#define PIN3 0x00C -#define PIN4 0x010 -#define PIN5 0x014 -#define PIN6 0x018 -#define PIN7 0x01C -#define PIN8 0x020 -#define PIN9 0x024 -#define PIN10 0x028 -#define PIN11 0x02C -#define PIN12 0x030 -#define PIN13 0x034 -#define PIN14 0x038 -#define PIN15 0x03C -#define PIN16 0x040 -#define PIN17 0x044 -#define PIN18 0x048 -#define PIN19 0x04C -#define PIN20 0x050 +#define PIN_GROUP0 (SCU_BASE + 0x000) +#define PIN_GROUP1 (SCU_BASE + 0x080) +#define PIN_GROUP2 (SCU_BASE + 0x100) +#define PIN_GROUP3 (SCU_BASE + 0x180) +#define PIN_GROUP4 (SCU_BASE + 0x200) +#define PIN_GROUP5 (SCU_BASE + 0x280) +#define PIN_GROUP6 (SCU_BASE + 0x300) +#define PIN_GROUP7 (SCU_BASE + 0x380) +#define PIN_GROUP8 (SCU_BASE + 0x400) +#define PIN_GROUP9 (SCU_BASE + 0x480) +#define PIN_GROUPA (SCU_BASE + 0x500) +#define PIN_GROUPB (SCU_BASE + 0x580) +#define PIN_GROUPC (SCU_BASE + 0x600) +#define PIN_GROUPD (SCU_BASE + 0x680) +#define PIN_GROUPE (SCU_BASE + 0x700) +#define PIN_GROUPF (SCU_BASE + 0x780) + +#define PIN0 0x000 +#define PIN1 0x004 +#define PIN2 0x008 +#define PIN3 0x00C +#define PIN4 0x010 +#define PIN5 0x014 +#define PIN6 0x018 +#define PIN7 0x01C +#define PIN8 0x020 +#define PIN9 0x024 +#define PIN10 0x028 +#define PIN11 0x02C +#define PIN12 0x030 +#define PIN13 0x034 +#define PIN14 0x038 +#define PIN15 0x03C +#define PIN16 0x040 +#define PIN17 0x044 +#define PIN18 0x048 +#define PIN19 0x04C +#define PIN20 0x050 /* --- SCU registers ------------------------------------------------------- */ /* Pin configuration registers */ -#define SCU_SFS(group, pin) MMIO32(group + pin) +#define SCU_SFS(group, pin) MMIO32(group + pin) /* Pins P0_n */ -#define SCU_SFSP0_0 SCU_SFS(PIN_GROUP0, PIN0) -#define SCU_SFSP0_1 SCU_SFS(PIN_GROUP0, PIN1) +#define SCU_SFSP0_0 SCU_SFS(PIN_GROUP0, PIN0) +#define SCU_SFSP0_1 SCU_SFS(PIN_GROUP0, PIN1) /* Pins P1_n */ -#define SCU_SFSP1_0 SCU_SFS(PIN_GROUP1, PIN0) -#define SCU_SFSP1_1 SCU_SFS(PIN_GROUP1, PIN1) -#define SCU_SFSP1_2 SCU_SFS(PIN_GROUP1, PIN2) -#define SCU_SFSP1_3 SCU_SFS(PIN_GROUP1, PIN3) -#define SCU_SFSP1_4 SCU_SFS(PIN_GROUP1, PIN4) -#define SCU_SFSP1_5 SCU_SFS(PIN_GROUP1, PIN5) -#define SCU_SFSP1_6 SCU_SFS(PIN_GROUP1, PIN6) -#define SCU_SFSP1_7 SCU_SFS(PIN_GROUP1, PIN7) -#define SCU_SFSP1_8 SCU_SFS(PIN_GROUP1, PIN8) -#define SCU_SFSP1_9 SCU_SFS(PIN_GROUP1, PIN9) -#define SCU_SFSP1_10 SCU_SFS(PIN_GROUP1, PIN10) -#define SCU_SFSP1_11 SCU_SFS(PIN_GROUP1, PIN11) -#define SCU_SFSP1_12 SCU_SFS(PIN_GROUP1, PIN12) -#define SCU_SFSP1_13 SCU_SFS(PIN_GROUP1, PIN13) -#define SCU_SFSP1_14 SCU_SFS(PIN_GROUP1, PIN14) -#define SCU_SFSP1_15 SCU_SFS(PIN_GROUP1, PIN15) -#define SCU_SFSP1_16 SCU_SFS(PIN_GROUP1, PIN16) -#define SCU_SFSP1_17 SCU_SFS(PIN_GROUP1, PIN17) -#define SCU_SFSP1_18 SCU_SFS(PIN_GROUP1, PIN18) -#define SCU_SFSP1_19 SCU_SFS(PIN_GROUP1, PIN19) -#define SCU_SFSP1_20 SCU_SFS(PIN_GROUP1, PIN20) +#define SCU_SFSP1_0 SCU_SFS(PIN_GROUP1, PIN0) +#define SCU_SFSP1_1 SCU_SFS(PIN_GROUP1, PIN1) +#define SCU_SFSP1_2 SCU_SFS(PIN_GROUP1, PIN2) +#define SCU_SFSP1_3 SCU_SFS(PIN_GROUP1, PIN3) +#define SCU_SFSP1_4 SCU_SFS(PIN_GROUP1, PIN4) +#define SCU_SFSP1_5 SCU_SFS(PIN_GROUP1, PIN5) +#define SCU_SFSP1_6 SCU_SFS(PIN_GROUP1, PIN6) +#define SCU_SFSP1_7 SCU_SFS(PIN_GROUP1, PIN7) +#define SCU_SFSP1_8 SCU_SFS(PIN_GROUP1, PIN8) +#define SCU_SFSP1_9 SCU_SFS(PIN_GROUP1, PIN9) +#define SCU_SFSP1_10 SCU_SFS(PIN_GROUP1, PIN10) +#define SCU_SFSP1_11 SCU_SFS(PIN_GROUP1, PIN11) +#define SCU_SFSP1_12 SCU_SFS(PIN_GROUP1, PIN12) +#define SCU_SFSP1_13 SCU_SFS(PIN_GROUP1, PIN13) +#define SCU_SFSP1_14 SCU_SFS(PIN_GROUP1, PIN14) +#define SCU_SFSP1_15 SCU_SFS(PIN_GROUP1, PIN15) +#define SCU_SFSP1_16 SCU_SFS(PIN_GROUP1, PIN16) +#define SCU_SFSP1_17 SCU_SFS(PIN_GROUP1, PIN17) +#define SCU_SFSP1_18 SCU_SFS(PIN_GROUP1, PIN18) +#define SCU_SFSP1_19 SCU_SFS(PIN_GROUP1, PIN19) +#define SCU_SFSP1_20 SCU_SFS(PIN_GROUP1, PIN20) /* Pins P2_n */ -#define SCU_SFSP2_0 SCU_SFS(PIN_GROUP2, PIN0) -#define SCU_SFSP2_1 SCU_SFS(PIN_GROUP2, PIN1) -#define SCU_SFSP2_2 SCU_SFS(PIN_GROUP2, PIN2) -#define SCU_SFSP2_3 SCU_SFS(PIN_GROUP2, PIN3) -#define SCU_SFSP2_4 SCU_SFS(PIN_GROUP2, PIN4) -#define SCU_SFSP2_5 SCU_SFS(PIN_GROUP2, PIN5) -#define SCU_SFSP2_6 SCU_SFS(PIN_GROUP2, PIN6) -#define SCU_SFSP2_7 SCU_SFS(PIN_GROUP2, PIN7) -#define SCU_SFSP2_8 SCU_SFS(PIN_GROUP2, PIN8) -#define SCU_SFSP2_9 SCU_SFS(PIN_GROUP2, PIN9) -#define SCU_SFSP2_10 SCU_SFS(PIN_GROUP2, PIN10) -#define SCU_SFSP2_11 SCU_SFS(PIN_GROUP2, PIN11) -#define SCU_SFSP2_12 SCU_SFS(PIN_GROUP2, PIN12) -#define SCU_SFSP2_13 SCU_SFS(PIN_GROUP2, PIN13) +#define SCU_SFSP2_0 SCU_SFS(PIN_GROUP2, PIN0) +#define SCU_SFSP2_1 SCU_SFS(PIN_GROUP2, PIN1) +#define SCU_SFSP2_2 SCU_SFS(PIN_GROUP2, PIN2) +#define SCU_SFSP2_3 SCU_SFS(PIN_GROUP2, PIN3) +#define SCU_SFSP2_4 SCU_SFS(PIN_GROUP2, PIN4) +#define SCU_SFSP2_5 SCU_SFS(PIN_GROUP2, PIN5) +#define SCU_SFSP2_6 SCU_SFS(PIN_GROUP2, PIN6) +#define SCU_SFSP2_7 SCU_SFS(PIN_GROUP2, PIN7) +#define SCU_SFSP2_8 SCU_SFS(PIN_GROUP2, PIN8) +#define SCU_SFSP2_9 SCU_SFS(PIN_GROUP2, PIN9) +#define SCU_SFSP2_10 SCU_SFS(PIN_GROUP2, PIN10) +#define SCU_SFSP2_11 SCU_SFS(PIN_GROUP2, PIN11) +#define SCU_SFSP2_12 SCU_SFS(PIN_GROUP2, PIN12) +#define SCU_SFSP2_13 SCU_SFS(PIN_GROUP2, PIN13) /* Pins P3_n */ -#define SCU_SFSP3_0 SCU_SFS(PIN_GROUP3, PIN0) -#define SCU_SFSP3_1 SCU_SFS(PIN_GROUP3, PIN1) -#define SCU_SFSP3_2 SCU_SFS(PIN_GROUP3, PIN2) -#define SCU_SFSP3_3 SCU_SFS(PIN_GROUP3, PIN3) -#define SCU_SFSP3_4 SCU_SFS(PIN_GROUP3, PIN4) -#define SCU_SFSP3_5 SCU_SFS(PIN_GROUP3, PIN5) -#define SCU_SFSP3_6 SCU_SFS(PIN_GROUP3, PIN6) -#define SCU_SFSP3_7 SCU_SFS(PIN_GROUP3, PIN7) -#define SCU_SFSP3_8 SCU_SFS(PIN_GROUP3, PIN8) +#define SCU_SFSP3_0 SCU_SFS(PIN_GROUP3, PIN0) +#define SCU_SFSP3_1 SCU_SFS(PIN_GROUP3, PIN1) +#define SCU_SFSP3_2 SCU_SFS(PIN_GROUP3, PIN2) +#define SCU_SFSP3_3 SCU_SFS(PIN_GROUP3, PIN3) +#define SCU_SFSP3_4 SCU_SFS(PIN_GROUP3, PIN4) +#define SCU_SFSP3_5 SCU_SFS(PIN_GROUP3, PIN5) +#define SCU_SFSP3_6 SCU_SFS(PIN_GROUP3, PIN6) +#define SCU_SFSP3_7 SCU_SFS(PIN_GROUP3, PIN7) +#define SCU_SFSP3_8 SCU_SFS(PIN_GROUP3, PIN8) /* Pins P4_n */ -#define SCU_SFSP4_0 SCU_SFS(PIN_GROUP4, PIN0) -#define SCU_SFSP4_1 SCU_SFS(PIN_GROUP4, PIN1) -#define SCU_SFSP4_2 SCU_SFS(PIN_GROUP4, PIN2) -#define SCU_SFSP4_3 SCU_SFS(PIN_GROUP4, PIN3) -#define SCU_SFSP4_4 SCU_SFS(PIN_GROUP4, PIN4) -#define SCU_SFSP4_5 SCU_SFS(PIN_GROUP4, PIN5) -#define SCU_SFSP4_6 SCU_SFS(PIN_GROUP4, PIN6) -#define SCU_SFSP4_7 SCU_SFS(PIN_GROUP4, PIN7) -#define SCU_SFSP4_8 SCU_SFS(PIN_GROUP4, PIN8) -#define SCU_SFSP4_9 SCU_SFS(PIN_GROUP4, PIN9) -#define SCU_SFSP4_10 SCU_SFS(PIN_GROUP4, PIN10) +#define SCU_SFSP4_0 SCU_SFS(PIN_GROUP4, PIN0) +#define SCU_SFSP4_1 SCU_SFS(PIN_GROUP4, PIN1) +#define SCU_SFSP4_2 SCU_SFS(PIN_GROUP4, PIN2) +#define SCU_SFSP4_3 SCU_SFS(PIN_GROUP4, PIN3) +#define SCU_SFSP4_4 SCU_SFS(PIN_GROUP4, PIN4) +#define SCU_SFSP4_5 SCU_SFS(PIN_GROUP4, PIN5) +#define SCU_SFSP4_6 SCU_SFS(PIN_GROUP4, PIN6) +#define SCU_SFSP4_7 SCU_SFS(PIN_GROUP4, PIN7) +#define SCU_SFSP4_8 SCU_SFS(PIN_GROUP4, PIN8) +#define SCU_SFSP4_9 SCU_SFS(PIN_GROUP4, PIN9) +#define SCU_SFSP4_10 SCU_SFS(PIN_GROUP4, PIN10) /* Pins P5_n */ -#define SCU_SFSP5_0 SCU_SFS(PIN_GROUP5, PIN0) -#define SCU_SFSP5_1 SCU_SFS(PIN_GROUP5, PIN1) -#define SCU_SFSP5_2 SCU_SFS(PIN_GROUP5, PIN2) -#define SCU_SFSP5_3 SCU_SFS(PIN_GROUP5, PIN3) -#define SCU_SFSP5_4 SCU_SFS(PIN_GROUP5, PIN4) -#define SCU_SFSP5_5 SCU_SFS(PIN_GROUP5, PIN5) -#define SCU_SFSP5_6 SCU_SFS(PIN_GROUP5, PIN6) -#define SCU_SFSP5_7 SCU_SFS(PIN_GROUP5, PIN7) +#define SCU_SFSP5_0 SCU_SFS(PIN_GROUP5, PIN0) +#define SCU_SFSP5_1 SCU_SFS(PIN_GROUP5, PIN1) +#define SCU_SFSP5_2 SCU_SFS(PIN_GROUP5, PIN2) +#define SCU_SFSP5_3 SCU_SFS(PIN_GROUP5, PIN3) +#define SCU_SFSP5_4 SCU_SFS(PIN_GROUP5, PIN4) +#define SCU_SFSP5_5 SCU_SFS(PIN_GROUP5, PIN5) +#define SCU_SFSP5_6 SCU_SFS(PIN_GROUP5, PIN6) +#define SCU_SFSP5_7 SCU_SFS(PIN_GROUP5, PIN7) /* Pins P6_n */ -#define SCU_SFSP6_0 SCU_SFS(PIN_GROUP6, PIN0) -#define SCU_SFSP6_1 SCU_SFS(PIN_GROUP6, PIN1) -#define SCU_SFSP6_2 SCU_SFS(PIN_GROUP6, PIN2) -#define SCU_SFSP6_3 SCU_SFS(PIN_GROUP6, PIN3) -#define SCU_SFSP6_4 SCU_SFS(PIN_GROUP6, PIN4) -#define SCU_SFSP6_5 SCU_SFS(PIN_GROUP6, PIN5) -#define SCU_SFSP6_6 SCU_SFS(PIN_GROUP6, PIN6) -#define SCU_SFSP6_7 SCU_SFS(PIN_GROUP6, PIN7) -#define SCU_SFSP6_8 SCU_SFS(PIN_GROUP6, PIN8) -#define SCU_SFSP6_9 SCU_SFS(PIN_GROUP6, PIN9) -#define SCU_SFSP6_10 SCU_SFS(PIN_GROUP6, PIN10) -#define SCU_SFSP6_11 SCU_SFS(PIN_GROUP6, PIN11) -#define SCU_SFSP6_12 SCU_SFS(PIN_GROUP6, PIN12) +#define SCU_SFSP6_0 SCU_SFS(PIN_GROUP6, PIN0) +#define SCU_SFSP6_1 SCU_SFS(PIN_GROUP6, PIN1) +#define SCU_SFSP6_2 SCU_SFS(PIN_GROUP6, PIN2) +#define SCU_SFSP6_3 SCU_SFS(PIN_GROUP6, PIN3) +#define SCU_SFSP6_4 SCU_SFS(PIN_GROUP6, PIN4) +#define SCU_SFSP6_5 SCU_SFS(PIN_GROUP6, PIN5) +#define SCU_SFSP6_6 SCU_SFS(PIN_GROUP6, PIN6) +#define SCU_SFSP6_7 SCU_SFS(PIN_GROUP6, PIN7) +#define SCU_SFSP6_8 SCU_SFS(PIN_GROUP6, PIN8) +#define SCU_SFSP6_9 SCU_SFS(PIN_GROUP6, PIN9) +#define SCU_SFSP6_10 SCU_SFS(PIN_GROUP6, PIN10) +#define SCU_SFSP6_11 SCU_SFS(PIN_GROUP6, PIN11) +#define SCU_SFSP6_12 SCU_SFS(PIN_GROUP6, PIN12) /* Pins P7_n */ -#define SCU_SFSP7_0 SCU_SFS(PIN_GROUP7, PIN0) -#define SCU_SFSP7_1 SCU_SFS(PIN_GROUP7, PIN1) -#define SCU_SFSP7_2 SCU_SFS(PIN_GROUP7, PIN2) -#define SCU_SFSP7_3 SCU_SFS(PIN_GROUP7, PIN3) -#define SCU_SFSP7_4 SCU_SFS(PIN_GROUP7, PIN4) -#define SCU_SFSP7_5 SCU_SFS(PIN_GROUP7, PIN5) -#define SCU_SFSP7_6 SCU_SFS(PIN_GROUP7, PIN6) -#define SCU_SFSP7_7 SCU_SFS(PIN_GROUP7, PIN7) +#define SCU_SFSP7_0 SCU_SFS(PIN_GROUP7, PIN0) +#define SCU_SFSP7_1 SCU_SFS(PIN_GROUP7, PIN1) +#define SCU_SFSP7_2 SCU_SFS(PIN_GROUP7, PIN2) +#define SCU_SFSP7_3 SCU_SFS(PIN_GROUP7, PIN3) +#define SCU_SFSP7_4 SCU_SFS(PIN_GROUP7, PIN4) +#define SCU_SFSP7_5 SCU_SFS(PIN_GROUP7, PIN5) +#define SCU_SFSP7_6 SCU_SFS(PIN_GROUP7, PIN6) +#define SCU_SFSP7_7 SCU_SFS(PIN_GROUP7, PIN7) /* Pins P8_n */ -#define SCU_SFSP8_0 SCU_SFS(PIN_GROUP8, PIN0) -#define SCU_SFSP8_1 SCU_SFS(PIN_GROUP8, PIN1) -#define SCU_SFSP8_2 SCU_SFS(PIN_GROUP8, PIN2) -#define SCU_SFSP8_3 SCU_SFS(PIN_GROUP8, PIN3) -#define SCU_SFSP8_4 SCU_SFS(PIN_GROUP8, PIN4) -#define SCU_SFSP8_5 SCU_SFS(PIN_GROUP8, PIN5) -#define SCU_SFSP8_6 SCU_SFS(PIN_GROUP8, PIN6) -#define SCU_SFSP8_7 SCU_SFS(PIN_GROUP8, PIN7) -#define SCU_SFSP8_8 SCU_SFS(PIN_GROUP8, PIN8) +#define SCU_SFSP8_0 SCU_SFS(PIN_GROUP8, PIN0) +#define SCU_SFSP8_1 SCU_SFS(PIN_GROUP8, PIN1) +#define SCU_SFSP8_2 SCU_SFS(PIN_GROUP8, PIN2) +#define SCU_SFSP8_3 SCU_SFS(PIN_GROUP8, PIN3) +#define SCU_SFSP8_4 SCU_SFS(PIN_GROUP8, PIN4) +#define SCU_SFSP8_5 SCU_SFS(PIN_GROUP8, PIN5) +#define SCU_SFSP8_6 SCU_SFS(PIN_GROUP8, PIN6) +#define SCU_SFSP8_7 SCU_SFS(PIN_GROUP8, PIN7) +#define SCU_SFSP8_8 SCU_SFS(PIN_GROUP8, PIN8) /* Pins P9_n */ -#define SCU_SFSP9_0 SCU_SFS(PIN_GROUP9, PIN0) -#define SCU_SFSP9_1 SCU_SFS(PIN_GROUP9, PIN1) -#define SCU_SFSP9_2 SCU_SFS(PIN_GROUP9, PIN2) -#define SCU_SFSP9_3 SCU_SFS(PIN_GROUP9, PIN3) -#define SCU_SFSP9_4 SCU_SFS(PIN_GROUP9, PIN4) -#define SCU_SFSP9_5 SCU_SFS(PIN_GROUP9, PIN5) -#define SCU_SFSP9_6 SCU_SFS(PIN_GROUP9, PIN6) +#define SCU_SFSP9_0 SCU_SFS(PIN_GROUP9, PIN0) +#define SCU_SFSP9_1 SCU_SFS(PIN_GROUP9, PIN1) +#define SCU_SFSP9_2 SCU_SFS(PIN_GROUP9, PIN2) +#define SCU_SFSP9_3 SCU_SFS(PIN_GROUP9, PIN3) +#define SCU_SFSP9_4 SCU_SFS(PIN_GROUP9, PIN4) +#define SCU_SFSP9_5 SCU_SFS(PIN_GROUP9, PIN5) +#define SCU_SFSP9_6 SCU_SFS(PIN_GROUP9, PIN6) /* Pins PA_n */ -#define SCU_SFSPA_0 SCU_SFS(PIN_GROUPA, PIN0) -#define SCU_SFSPA_1 SCU_SFS(PIN_GROUPA, PIN1) -#define SCU_SFSPA_2 SCU_SFS(PIN_GROUPA, PIN2) -#define SCU_SFSPA_3 SCU_SFS(PIN_GROUPA, PIN3) -#define SCU_SFSPA_4 SCU_SFS(PIN_GROUPA, PIN4) +#define SCU_SFSPA_0 SCU_SFS(PIN_GROUPA, PIN0) +#define SCU_SFSPA_1 SCU_SFS(PIN_GROUPA, PIN1) +#define SCU_SFSPA_2 SCU_SFS(PIN_GROUPA, PIN2) +#define SCU_SFSPA_3 SCU_SFS(PIN_GROUPA, PIN3) +#define SCU_SFSPA_4 SCU_SFS(PIN_GROUPA, PIN4) /* Pins PB_n */ -#define SCU_SFSPB_0 SCU_SFS(PIN_GROUPB, PIN0) -#define SCU_SFSPB_1 SCU_SFS(PIN_GROUPB, PIN1) -#define SCU_SFSPB_2 SCU_SFS(PIN_GROUPB, PIN2) -#define SCU_SFSPB_3 SCU_SFS(PIN_GROUPB, PIN3) -#define SCU_SFSPB_4 SCU_SFS(PIN_GROUPB, PIN4) -#define SCU_SFSPB_5 SCU_SFS(PIN_GROUPB, PIN5) -#define SCU_SFSPB_6 SCU_SFS(PIN_GROUPB, PIN6) +#define SCU_SFSPB_0 SCU_SFS(PIN_GROUPB, PIN0) +#define SCU_SFSPB_1 SCU_SFS(PIN_GROUPB, PIN1) +#define SCU_SFSPB_2 SCU_SFS(PIN_GROUPB, PIN2) +#define SCU_SFSPB_3 SCU_SFS(PIN_GROUPB, PIN3) +#define SCU_SFSPB_4 SCU_SFS(PIN_GROUPB, PIN4) +#define SCU_SFSPB_5 SCU_SFS(PIN_GROUPB, PIN5) +#define SCU_SFSPB_6 SCU_SFS(PIN_GROUPB, PIN6) /* Pins PC_n */ -#define SCU_SFSPC_0 SCU_SFS(PIN_GROUPC, PIN0) -#define SCU_SFSPC_1 SCU_SFS(PIN_GROUPC, PIN1) -#define SCU_SFSPC_2 SCU_SFS(PIN_GROUPC, PIN2) -#define SCU_SFSPC_3 SCU_SFS(PIN_GROUPC, PIN3) -#define SCU_SFSPC_4 SCU_SFS(PIN_GROUPC, PIN4) -#define SCU_SFSPC_5 SCU_SFS(PIN_GROUPC, PIN5) -#define SCU_SFSPC_6 SCU_SFS(PIN_GROUPC, PIN6) -#define SCU_SFSPC_7 SCU_SFS(PIN_GROUPC, PIN7) -#define SCU_SFSPC_8 SCU_SFS(PIN_GROUPC, PIN8) -#define SCU_SFSPC_9 SCU_SFS(PIN_GROUPC, PIN9) -#define SCU_SFSPC_10 SCU_SFS(PIN_GROUPC, PIN10) -#define SCU_SFSPC_11 SCU_SFS(PIN_GROUPC, PIN11) -#define SCU_SFSPC_12 SCU_SFS(PIN_GROUPC, PIN12) -#define SCU_SFSPC_13 SCU_SFS(PIN_GROUPC, PIN13) -#define SCU_SFSPC_14 SCU_SFS(PIN_GROUPC, PIN14) +#define SCU_SFSPC_0 SCU_SFS(PIN_GROUPC, PIN0) +#define SCU_SFSPC_1 SCU_SFS(PIN_GROUPC, PIN1) +#define SCU_SFSPC_2 SCU_SFS(PIN_GROUPC, PIN2) +#define SCU_SFSPC_3 SCU_SFS(PIN_GROUPC, PIN3) +#define SCU_SFSPC_4 SCU_SFS(PIN_GROUPC, PIN4) +#define SCU_SFSPC_5 SCU_SFS(PIN_GROUPC, PIN5) +#define SCU_SFSPC_6 SCU_SFS(PIN_GROUPC, PIN6) +#define SCU_SFSPC_7 SCU_SFS(PIN_GROUPC, PIN7) +#define SCU_SFSPC_8 SCU_SFS(PIN_GROUPC, PIN8) +#define SCU_SFSPC_9 SCU_SFS(PIN_GROUPC, PIN9) +#define SCU_SFSPC_10 SCU_SFS(PIN_GROUPC, PIN10) +#define SCU_SFSPC_11 SCU_SFS(PIN_GROUPC, PIN11) +#define SCU_SFSPC_12 SCU_SFS(PIN_GROUPC, PIN12) +#define SCU_SFSPC_13 SCU_SFS(PIN_GROUPC, PIN13) +#define SCU_SFSPC_14 SCU_SFS(PIN_GROUPC, PIN14) /* Pins PD_n */ -#define SCU_SFSPD_0 SCU_SFS(PIN_GROUPD, PIN0) -#define SCU_SFSPD_1 SCU_SFS(PIN_GROUPD, PIN1) -#define SCU_SFSPD_2 SCU_SFS(PIN_GROUPD, PIN2) -#define SCU_SFSPD_3 SCU_SFS(PIN_GROUPD, PIN3) -#define SCU_SFSPD_4 SCU_SFS(PIN_GROUPD, PIN4) -#define SCU_SFSPD_5 SCU_SFS(PIN_GROUPD, PIN5) -#define SCU_SFSPD_6 SCU_SFS(PIN_GROUPD, PIN6) -#define SCU_SFSPD_7 SCU_SFS(PIN_GROUPD, PIN7) -#define SCU_SFSPD_8 SCU_SFS(PIN_GROUPD, PIN8) -#define SCU_SFSPD_9 SCU_SFS(PIN_GROUPD, PIN9) -#define SCU_SFSPD_10 SCU_SFS(PIN_GROUPD, PIN10) -#define SCU_SFSPD_11 SCU_SFS(PIN_GROUPD, PIN11) -#define SCU_SFSPD_12 SCU_SFS(PIN_GROUPD, PIN12) -#define SCU_SFSPD_13 SCU_SFS(PIN_GROUPD, PIN13) -#define SCU_SFSPD_14 SCU_SFS(PIN_GROUPD, PIN14) -#define SCU_SFSPD_15 SCU_SFS(PIN_GROUPD, PIN15) -#define SCU_SFSPD_16 SCU_SFS(PIN_GROUPD, PIN16) +#define SCU_SFSPD_0 SCU_SFS(PIN_GROUPD, PIN0) +#define SCU_SFSPD_1 SCU_SFS(PIN_GROUPD, PIN1) +#define SCU_SFSPD_2 SCU_SFS(PIN_GROUPD, PIN2) +#define SCU_SFSPD_3 SCU_SFS(PIN_GROUPD, PIN3) +#define SCU_SFSPD_4 SCU_SFS(PIN_GROUPD, PIN4) +#define SCU_SFSPD_5 SCU_SFS(PIN_GROUPD, PIN5) +#define SCU_SFSPD_6 SCU_SFS(PIN_GROUPD, PIN6) +#define SCU_SFSPD_7 SCU_SFS(PIN_GROUPD, PIN7) +#define SCU_SFSPD_8 SCU_SFS(PIN_GROUPD, PIN8) +#define SCU_SFSPD_9 SCU_SFS(PIN_GROUPD, PIN9) +#define SCU_SFSPD_10 SCU_SFS(PIN_GROUPD, PIN10) +#define SCU_SFSPD_11 SCU_SFS(PIN_GROUPD, PIN11) +#define SCU_SFSPD_12 SCU_SFS(PIN_GROUPD, PIN12) +#define SCU_SFSPD_13 SCU_SFS(PIN_GROUPD, PIN13) +#define SCU_SFSPD_14 SCU_SFS(PIN_GROUPD, PIN14) +#define SCU_SFSPD_15 SCU_SFS(PIN_GROUPD, PIN15) +#define SCU_SFSPD_16 SCU_SFS(PIN_GROUPD, PIN16) /* Pins PE_n */ -#define SCU_SFSPE_0 SCU_SFS(PIN_GROUPE, PIN0) -#define SCU_SFSPE_1 SCU_SFS(PIN_GROUPE, PIN1) -#define SCU_SFSPE_2 SCU_SFS(PIN_GROUPE, PIN2) -#define SCU_SFSPE_3 SCU_SFS(PIN_GROUPE, PIN3) -#define SCU_SFSPE_4 SCU_SFS(PIN_GROUPE, PIN4) -#define SCU_SFSPE_5 SCU_SFS(PIN_GROUPE, PIN5) -#define SCU_SFSPE_6 SCU_SFS(PIN_GROUPE, PIN6) -#define SCU_SFSPE_7 SCU_SFS(PIN_GROUPE, PIN7) -#define SCU_SFSPE_8 SCU_SFS(PIN_GROUPE, PIN8) -#define SCU_SFSPE_9 SCU_SFS(PIN_GROUPE, PIN9) -#define SCU_SFSPE_10 SCU_SFS(PIN_GROUPE, PIN10) -#define SCU_SFSPE_11 SCU_SFS(PIN_GROUPE, PIN11) -#define SCU_SFSPE_12 SCU_SFS(PIN_GROUPE, PIN12) -#define SCU_SFSPE_13 SCU_SFS(PIN_GROUPE, PIN13) -#define SCU_SFSPE_14 SCU_SFS(PIN_GROUPE, PIN14) -#define SCU_SFSPE_15 SCU_SFS(PIN_GROUPE, PIN15) +#define SCU_SFSPE_0 SCU_SFS(PIN_GROUPE, PIN0) +#define SCU_SFSPE_1 SCU_SFS(PIN_GROUPE, PIN1) +#define SCU_SFSPE_2 SCU_SFS(PIN_GROUPE, PIN2) +#define SCU_SFSPE_3 SCU_SFS(PIN_GROUPE, PIN3) +#define SCU_SFSPE_4 SCU_SFS(PIN_GROUPE, PIN4) +#define SCU_SFSPE_5 SCU_SFS(PIN_GROUPE, PIN5) +#define SCU_SFSPE_6 SCU_SFS(PIN_GROUPE, PIN6) +#define SCU_SFSPE_7 SCU_SFS(PIN_GROUPE, PIN7) +#define SCU_SFSPE_8 SCU_SFS(PIN_GROUPE, PIN8) +#define SCU_SFSPE_9 SCU_SFS(PIN_GROUPE, PIN9) +#define SCU_SFSPE_10 SCU_SFS(PIN_GROUPE, PIN10) +#define SCU_SFSPE_11 SCU_SFS(PIN_GROUPE, PIN11) +#define SCU_SFSPE_12 SCU_SFS(PIN_GROUPE, PIN12) +#define SCU_SFSPE_13 SCU_SFS(PIN_GROUPE, PIN13) +#define SCU_SFSPE_14 SCU_SFS(PIN_GROUPE, PIN14) +#define SCU_SFSPE_15 SCU_SFS(PIN_GROUPE, PIN15) /* Pins PF_n */ -#define SCU_SFSPF_0 SCU_SFS(PIN_GROUPF, PIN0) -#define SCU_SFSPF_1 SCU_SFS(PIN_GROUPF, PIN1) -#define SCU_SFSPF_2 SCU_SFS(PIN_GROUPF, PIN2) -#define SCU_SFSPF_3 SCU_SFS(PIN_GROUPF, PIN3) -#define SCU_SFSPF_4 SCU_SFS(PIN_GROUPF, PIN4) -#define SCU_SFSPF_5 SCU_SFS(PIN_GROUPF, PIN5) -#define SCU_SFSPF_6 SCU_SFS(PIN_GROUPF, PIN6) -#define SCU_SFSPF_7 SCU_SFS(PIN_GROUPF, PIN7) -#define SCU_SFSPF_8 SCU_SFS(PIN_GROUPF, PIN8) -#define SCU_SFSPF_9 SCU_SFS(PIN_GROUPF, PIN9) -#define SCU_SFSPF_10 SCU_SFS(PIN_GROUPF, PIN10) -#define SCU_SFSPF_11 SCU_SFS(PIN_GROUPF, PIN11) +#define SCU_SFSPF_0 SCU_SFS(PIN_GROUPF, PIN0) +#define SCU_SFSPF_1 SCU_SFS(PIN_GROUPF, PIN1) +#define SCU_SFSPF_2 SCU_SFS(PIN_GROUPF, PIN2) +#define SCU_SFSPF_3 SCU_SFS(PIN_GROUPF, PIN3) +#define SCU_SFSPF_4 SCU_SFS(PIN_GROUPF, PIN4) +#define SCU_SFSPF_5 SCU_SFS(PIN_GROUPF, PIN5) +#define SCU_SFSPF_6 SCU_SFS(PIN_GROUPF, PIN6) +#define SCU_SFSPF_7 SCU_SFS(PIN_GROUPF, PIN7) +#define SCU_SFSPF_8 SCU_SFS(PIN_GROUPF, PIN8) +#define SCU_SFSPF_9 SCU_SFS(PIN_GROUPF, PIN9) +#define SCU_SFSPF_10 SCU_SFS(PIN_GROUPF, PIN10) +#define SCU_SFSPF_11 SCU_SFS(PIN_GROUPF, PIN11) /* CLKn pins */ -#define SCU_SFSCLK0 MMIO32(SCU_BASE + 0xC00) -#define SCU_SFSCLK1 MMIO32(SCU_BASE + 0xC04) -#define SCU_SFSCLK2 MMIO32(SCU_BASE + 0xC08) -#define SCU_SFSCLK3 MMIO32(SCU_BASE + 0xC0C) +#define SCU_SFSCLK0 MMIO32(SCU_BASE + 0xC00) +#define SCU_SFSCLK1 MMIO32(SCU_BASE + 0xC04) +#define SCU_SFSCLK2 MMIO32(SCU_BASE + 0xC08) +#define SCU_SFSCLK3 MMIO32(SCU_BASE + 0xC0C) /* USB1 USB1_DP/USB1_DM pins and I2C-bus open-drain pins */ -#define SCU_SFSUSB MMIO32(SCU_BASE + 0xC80) -#define SCU_SFSI2C0 MMIO32(SCU_BASE + 0xC84) +#define SCU_SFSUSB MMIO32(SCU_BASE + 0xC80) +#define SCU_SFSI2C0 MMIO32(SCU_BASE + 0xC84) /* ADC pin select registers */ /* ADC0 function select register */ -#define SCU_ENAIO0 MMIO32(SCU_BASE + 0xC88) +#define SCU_ENAIO0 MMIO32(SCU_BASE + 0xC88) /* ADC1 function select register */ -#define SCU_ENAIO1 MMIO32(SCU_BASE + 0xC8C) +#define SCU_ENAIO1 MMIO32(SCU_BASE + 0xC8C) /* Analog function select register */ -#define SCU_ENAIO2 MMIO32(SCU_BASE + 0xC90) +#define SCU_ENAIO2 MMIO32(SCU_BASE + 0xC90) /* EMC clock delay register */ -#define SCU_EMCDELAYCLK MMIO32(SCU_BASE + 0xD00) +#define SCU_EMCDELAYCLK MMIO32(SCU_BASE + 0xD00) /* Pin interrupt select registers */ /* Pin interrupt select register for pin interrupts 0 to 3 */ -#define SCU_PINTSEL0 MMIO32(SCU_BASE + 0xE00) +#define SCU_PINTSEL0 MMIO32(SCU_BASE + 0xE00) /* Pin interrupt select register for pin interrupts 4 to 7 */ -#define SCU_PINTSEL1 MMIO32(SCU_BASE + 0xE04) +#define SCU_PINTSEL1 MMIO32(SCU_BASE + 0xE04) /**************************/ /* SCU I2C0 Configuration */ /**************************/ -/* - * Select input glitch filter time constant for the SCL pin. - * 0 = 50 ns glitch filter. - * 1 = 3ns glitch filter. - */ -#define SCU_SCL_EFP (BIT0) +/* +* Select input glitch filter time constant for the SCL pin. +* 0 = 50 ns glitch filter. +* 1 = 3ns glitch filter. +*/ +#define SCU_SCL_EFP (BIT0) /* BIT1 Reserved. Always write a 0 to this bit. */ /* - * Select I2C mode for the SCL pin. - * 0 = Standard/Fast mode transmit. - * 1 = Fast-mode Plus transmit. - */ -#define SCU_SCL_EHD (BIT2) +* Select I2C mode for the SCL pin. +* 0 = Standard/Fast mode transmit. +* 1 = Fast-mode Plus transmit. +*/ +#define SCU_SCL_EHD (BIT2) /* - * Enable the input receiver for the SCL pin. - * Always write a 1 to this bit when using the - * I2C0. - * 0 = Disabled. - * 1 = Enabled. - */ -#define SCU_SCL_EZI_EN (BIT3) +* Enable the input receiver for the SCL pin. +* Always write a 1 to this bit when using the +* I2C0. +* 0 = Disabled. +* 1 = Enabled. +*/ +#define SCU_SCL_EZI_EN (BIT3) /* BIT4-6 Reserved. */ -/* - * Enable or disable input glitch filter for the - * SCL pin. The filter time constant is - * determined by bit EFP. - * 0 = Enable input filter. - * 1 = Disable input filter. - */ -#define SCU_SCL_ZIF_DIS (BIT7) +/* +* Enable or disable input glitch filter for the +* SCL pin. The filter time constant is +* determined by bit EFP. +* 0 = Enable input filter. +* 1 = Disable input filter. +*/ +#define SCU_SCL_ZIF_DIS (BIT7) /* - * Select input glitch filter time constant for the SDA pin. - * 0 = 50 ns glitch filter. - * 1 = 3ns glitch filter. - */ -#define SCU_SDA_EFP (BIT8) +* Select input glitch filter time constant for the SDA pin. +* 0 = 50 ns glitch filter. +* 1 = 3ns glitch filter. +*/ +#define SCU_SDA_EFP (BIT8) /* BIT9 Reserved. Always write a 0 to this bit. */ -/* - * Select I2C mode for the SDA pin. - * 0 = Standard/Fast mode transmit. - * 1 = Fast-mode Plus transmit. - */ -#define SCU_SDA_EHD (BIT10) +/* +* Select I2C mode for the SDA pin. +* 0 = Standard/Fast mode transmit. +* 1 = Fast-mode Plus transmit. +*/ +#define SCU_SDA_EHD (BIT10) /* - * Enable the input receiver for the SDA pin. - * Always write a 1 to this bit when using the - * I2C0. - * 0 = Disabled. - * 1 = Enabled. - */ -#define SCU_SDA_EZI_EN (BIT11) +* Enable the input receiver for the SDA pin. +* Always write a 1 to this bit when using the +* I2C0. +* 0 = Disabled. +* 1 = Enabled. +*/ +#define SCU_SDA_EZI_EN (BIT11) /* BIT 12-14 - Reserved */ /* - * Enable or disable input glitch filter for the - * SDA pin. The filter time constant is - * determined by bit SDA_EFP. - * 0 = Enable input filter. - * 1 = Disable input filter. - */ -#define SCU_SDA_ZIF_DIS (BIT15) +* Enable or disable input glitch filter for the +* SDA pin. The filter time constant is +* determined by bit SDA_EFP. +* 0 = Enable input filter. +* 1 = Disable input filter. +*/ +#define SCU_SDA_ZIF_DIS (BIT15) /* Standard mode for I2C SCL/SDA Standard/Fast mode */ -#define SCU_I2C0_NOMINAL (SCU_SCL_EZI_EN | SCU_SDA_EZI_EN) +#define SCU_I2C0_NOMINAL (SCU_SCL_EZI_EN | SCU_SDA_EZI_EN) /* Standard mode for I2C SCL/SDA Fast-mode Plus transmit */ -#define SCU_I2C0_FAST (SCU_SCL_EFP | SCU_SCL_EHD | SCU_SCL_EZI_EN | SCU_SCL_ZIF_DIS \ - SCU_SDA_EFP | SCU_SDA_EHD | SCU_SDA_EZI_EN) - -/* - * SCU PIN Normal Drive: - * The pin configuration registers for normal-drive pins control the following pins: - * - P0_0 and P0_1 - * - P1_0 to P1_16 and P1_18 to P1_20 - * - P2_0 to P2_2 and P2_6 to P2_13 - * - P3_0 to P3_2 and P3_4 to P3_8 - * - P4_0 to P4_10 - * - P5_0 to P5_7 - * - P6_0 to P6_12 - * - P7_0 to P7_7 - * - P8_3 to P8_8 - * - P9_0 to P9_6 - * - PA_0 and PA_4 - * - PB_0 to PB_6 - * - PC_0 to PC_14 - * - PE_0 to PE_15 - * - PF_0 to PF_11 - * - * Pin configuration registers for High-Drive pins. - * The pin configuration registers for high-drive pins control the following pins: - * - P1_17 - * - P2_3 to P2_5 - * - P8_0 to P8_2 - * - PA_1 to PA_3 - * - * Pin configuration registers for High-Speed pins. - * This register controls the following pins: - * - P3_3 and pins CLK0 to CLK3. - */ +#define SCU_I2C0_FAST (SCU_SCL_EFP | SCU_SCL_EHD | SCU_SCL_EZI_EN | SCU_SCL_ZIF_DIS \ + SCU_SDA_EFP | SCU_SDA_EHD | SCU_SDA_EZI_EN) + +/* +* SCU PIN Normal Drive: +* The pin configuration registers for normal-drive pins control the following pins: +* - P0_0 and P0_1 +* - P1_0 to P1_16 and P1_18 to P1_20 +* - P2_0 to P2_2 and P2_6 to P2_13 +* - P3_0 to P3_2 and P3_4 to P3_8 +* - P4_0 to P4_10 +* - P5_0 to P5_7 +* - P6_0 to P6_12 +* - P7_0 to P7_7 +* - P8_3 to P8_8 +* - P9_0 to P9_6 +* - PA_0 and PA_4 +* - PB_0 to PB_6 +* - PC_0 to PC_14 +* - PE_0 to PE_15 +* - PF_0 to PF_11 +* +* Pin configuration registers for High-Drive pins. +* The pin configuration registers for high-drive pins control the following pins: +* - P1_17 +* - P2_3 to P2_5 +* - P8_0 to P8_2 +* - PA_1 to PA_3 +* +* Pin configuration registers for High-Speed pins. +* This register controls the following pins: +* - P3_3 and pins CLK0 to CLK3. +*/ typedef enum { - /* Group Port 0 */ + /* Group Port 0 */ P0_0 = (PIN_GROUP0+PIN0), - P0_1 = (PIN_GROUP0+PIN1), - - /* Group Port 1 */ - P1_0 = (PIN_GROUP1+PIN0), - P1_1 = (PIN_GROUP1+PIN1), - P1_2 = (PIN_GROUP1+PIN2), - P1_3 = (PIN_GROUP1+PIN3), - P1_4 = (PIN_GROUP1+PIN4), - P1_5 = (PIN_GROUP1+PIN5), - P1_6 = (PIN_GROUP1+PIN6), - P1_7 = (PIN_GROUP1+PIN7), - P1_8 = (PIN_GROUP1+PIN8), - P1_9 = (PIN_GROUP1+PIN9), - P1_10 = (PIN_GROUP1+PIN10), - P1_11 = (PIN_GROUP1+PIN11), - P1_12 = (PIN_GROUP1+PIN12), - P1_13 = (PIN_GROUP1+PIN13), - P1_14 = (PIN_GROUP1+PIN14), - P1_15 = (PIN_GROUP1+PIN15), - P1_16 = (PIN_GROUP1+PIN16), - - /* P1_17 is High-Drive pin */ - P1_17 = (PIN_GROUP1+PIN17), - - P1_18 = (PIN_GROUP1+PIN18), - P1_19 = (PIN_GROUP1+PIN19), - P1_20 = (PIN_GROUP1+PIN20), - - /* Group Port 2 */ - P2_0 = (PIN_GROUP2+PIN0), - P2_1 = (PIN_GROUP2+PIN1), - P2_2 = (PIN_GROUP2+PIN2), - - /* P2_3 to P2_5 are High-Drive pins */ - P2_3 = (PIN_GROUP2+PIN3), - P2_4 = (PIN_GROUP2+PIN4), - P2_5 = (PIN_GROUP2+PIN5), - - P2_6 = (PIN_GROUP2+PIN6), - P2_7 = (PIN_GROUP2+PIN7), - P2_8 = (PIN_GROUP2+PIN8), - P2_9 = (PIN_GROUP2+PIN9), - P2_10 = (PIN_GROUP2+PIN10), - P2_11 = (PIN_GROUP2+PIN11), - P2_12 = (PIN_GROUP2+PIN12), - P2_13 = (PIN_GROUP2+PIN13), - - /* Group Port 3 */ - P3_0 = (PIN_GROUP3+PIN0), - P3_1 = (PIN_GROUP3+PIN1), - P3_2 = (PIN_GROUP3+PIN2), - - /* P3_3 is High-Speed pin */ - P3_3 = (PIN_GROUP3+PIN3), - - P3_4 = (PIN_GROUP3+PIN4), - P3_5 = (PIN_GROUP3+PIN5), - P3_6 = (PIN_GROUP3+PIN6), - P3_7 = (PIN_GROUP3+PIN7), - P3_8 = (PIN_GROUP3+PIN8), - - /* Group Port 4 */ - P4_0 = (PIN_GROUP4+PIN0), - P4_1 = (PIN_GROUP4+PIN1), - P4_2 = (PIN_GROUP4+PIN2), - P4_3 = (PIN_GROUP4+PIN3), - P4_4 = (PIN_GROUP4+PIN4), - P4_5 = (PIN_GROUP4+PIN5), - P4_6 = (PIN_GROUP4+PIN6), - P4_7 = (PIN_GROUP4+PIN7), - P4_8 = (PIN_GROUP4+PIN8), - P4_9 = (PIN_GROUP4+PIN9), - P4_10 = (PIN_GROUP4+PIN10), - - /* Group Port 5 */ - P5_0 = (PIN_GROUP5+PIN0), - P5_1 = (PIN_GROUP5+PIN1), - P5_2 = (PIN_GROUP5+PIN2), - P5_3 = (PIN_GROUP5+PIN3), - P5_4 = (PIN_GROUP5+PIN4), - P5_5 = (PIN_GROUP5+PIN5), - P5_6 = (PIN_GROUP5+PIN6), - P5_7 = (PIN_GROUP5+PIN7), - - /* Group Port 6 */ - P6_0 = (PIN_GROUP6+PIN0), - P6_1 = (PIN_GROUP6+PIN1), - P6_2 = (PIN_GROUP6+PIN2), - P6_3 = (PIN_GROUP6+PIN3), - P6_4 = (PIN_GROUP6+PIN4), - P6_5 = (PIN_GROUP6+PIN5), - P6_6 = (PIN_GROUP6+PIN6), - P6_7 = (PIN_GROUP6+PIN7), - P6_8 = (PIN_GROUP6+PIN8), - P6_9 = (PIN_GROUP6+PIN9), - P6_10 = (PIN_GROUP6+PIN10), - P6_11 = (PIN_GROUP6+PIN11), - P6_12 = (PIN_GROUP6+PIN12), - - /* Group Port 7 */ - P7_0 = (PIN_GROUP7+PIN0), - P7_1 = (PIN_GROUP7+PIN1), - P7_2 = (PIN_GROUP7+PIN2), - P7_3 = (PIN_GROUP7+PIN3), - P7_4 = (PIN_GROUP7+PIN4), - P7_5 = (PIN_GROUP7+PIN5), - P7_6 = (PIN_GROUP7+PIN6), - P7_7 = (PIN_GROUP7+PIN7), - - /* Group Port 8 */ - /* P8_0 to P8_2 are High-Drive pins */ - P8_0 = (PIN_GROUP8+PIN0), - P8_1 = (PIN_GROUP8+PIN1), - P8_2 = (PIN_GROUP8+PIN2), - - P8_3 = (PIN_GROUP8+PIN3), - P8_4 = (PIN_GROUP8+PIN4), - P8_5 = (PIN_GROUP8+PIN5), - P8_6 = (PIN_GROUP8+PIN6), - P8_7 = (PIN_GROUP8+PIN7), - P8_8 = (PIN_GROUP8+PIN8), - - /* Group Port 9 */ - P9_0 = (PIN_GROUP9+PIN0), - P9_1 = (PIN_GROUP9+PIN1), - P9_2 = (PIN_GROUP9+PIN2), - P9_3 = (PIN_GROUP9+PIN3), - P9_4 = (PIN_GROUP9+PIN4), - P9_5 = (PIN_GROUP9+PIN5), - P9_6 = (PIN_GROUP9+PIN6), - - /* Group Port A */ - PA_0 = (PIN_GROUPA+PIN0), - /* PA_1 to PA_3 are Normal & High-Drive Pins */ - PA_1 = (PIN_GROUPA+PIN1), - PA_2 = (PIN_GROUPA+PIN2), - PA_3 = (PIN_GROUPA+PIN3), - PA_4 = (PIN_GROUPA+PIN4), - - /* Group Port B */ - PB_0 = (PIN_GROUPB+PIN0), - PB_1 = (PIN_GROUPB+PIN1), - PB_2 = (PIN_GROUPB+PIN2), - PB_3 = (PIN_GROUPB+PIN3), - PB_4 = (PIN_GROUPB+PIN4), - PB_5 = (PIN_GROUPB+PIN5), - PB_6 = (PIN_GROUPB+PIN6), - - /* Group Port C */ - PC_0 = (PIN_GROUPC+PIN0), - PC_1 = (PIN_GROUPC+PIN1), - PC_2 = (PIN_GROUPC+PIN2), - PC_3 = (PIN_GROUPC+PIN3), - PC_4 = (PIN_GROUPC+PIN4), - PC_5 = (PIN_GROUPC+PIN5), - PC_6 = (PIN_GROUPC+PIN6), - PC_7 = (PIN_GROUPC+PIN7), - PC_8 = (PIN_GROUPC+PIN8), - PC_9 = (PIN_GROUPC+PIN9), - PC_10 = (PIN_GROUPC+PIN10), - PC_11 = (PIN_GROUPC+PIN11), - PC_12 = (PIN_GROUPC+PIN12), - PC_13 = (PIN_GROUPC+PIN13), - PC_14 = (PIN_GROUPC+PIN14), - - /* Group Port D (seems not configurable through SCU, not defined in UM10503.pdf Rev.1, keep it here) */ - PD_0 = (PIN_GROUPD+PIN0), - PD_1 = (PIN_GROUPD+PIN1), - PD_2 = (PIN_GROUPD+PIN2), - PD_3 = (PIN_GROUPD+PIN3), - PD_4 = (PIN_GROUPD+PIN4), - PD_5 = (PIN_GROUPD+PIN5), - PD_6 = (PIN_GROUPD+PIN6), - PD_7 = (PIN_GROUPD+PIN7), - PD_8 = (PIN_GROUPD+PIN8), - PD_9 = (PIN_GROUPD+PIN9), - PD_10 = (PIN_GROUPD+PIN10), - PD_11 = (PIN_GROUPD+PIN11), - PD_12 = (PIN_GROUPD+PIN12), - PD_13 = (PIN_GROUPD+PIN13), - PD_14 = (PIN_GROUPD+PIN14), - PD_15 = (PIN_GROUPD+PIN15), - PD_16 = (PIN_GROUPD+PIN16), - - /* Group Port E */ - PE_0 = (PIN_GROUPE+PIN0), - PE_1 = (PIN_GROUPE+PIN1), - PE_2 = (PIN_GROUPE+PIN2), - PE_3 = (PIN_GROUPE+PIN3), - PE_4 = (PIN_GROUPE+PIN4), - PE_5 = (PIN_GROUPE+PIN5), - PE_6 = (PIN_GROUPE+PIN6), - PE_7 = (PIN_GROUPE+PIN7), - PE_8 = (PIN_GROUPE+PIN8), - PE_9 = (PIN_GROUPE+PIN9), - PE_10 = (PIN_GROUPE+PIN10), - PE_11 = (PIN_GROUPE+PIN11), - PE_12 = (PIN_GROUPE+PIN12), - PE_13 = (PIN_GROUPE+PIN13), - PE_14 = (PIN_GROUPE+PIN14), - PE_15 = (PIN_GROUPE+PIN15), - - /* Group Port F */ - PF_0 = (PIN_GROUPF+PIN0), - PF_1 = (PIN_GROUPF+PIN1), - PF_2 = (PIN_GROUPF+PIN2), - PF_3 = (PIN_GROUPF+PIN3), - PF_4 = (PIN_GROUPF+PIN4), - PF_5 = (PIN_GROUPF+PIN5), - PF_6 = (PIN_GROUPF+PIN6), - PF_7 = (PIN_GROUPF+PIN7), - PF_8 = (PIN_GROUPF+PIN8), - PF_9 = (PIN_GROUPF+PIN9), - PF_10 = (PIN_GROUPF+PIN10), - PF_11 = (PIN_GROUPF+PIN11), - - /* Group Clock 0 to 3 High-Speed pins */ - CLK0 = (SCU_BASE + 0xC00), - CLK1 = (SCU_BASE + 0xC04), - CLK2 = (SCU_BASE + 0xC08), - CLK3 = (SCU_BASE + 0xC0C) + P0_1 = (PIN_GROUP0+PIN1), + + /* Group Port 1 */ + P1_0 = (PIN_GROUP1+PIN0), + P1_1 = (PIN_GROUP1+PIN1), + P1_2 = (PIN_GROUP1+PIN2), + P1_3 = (PIN_GROUP1+PIN3), + P1_4 = (PIN_GROUP1+PIN4), + P1_5 = (PIN_GROUP1+PIN5), + P1_6 = (PIN_GROUP1+PIN6), + P1_7 = (PIN_GROUP1+PIN7), + P1_8 = (PIN_GROUP1+PIN8), + P1_9 = (PIN_GROUP1+PIN9), + P1_10 = (PIN_GROUP1+PIN10), + P1_11 = (PIN_GROUP1+PIN11), + P1_12 = (PIN_GROUP1+PIN12), + P1_13 = (PIN_GROUP1+PIN13), + P1_14 = (PIN_GROUP1+PIN14), + P1_15 = (PIN_GROUP1+PIN15), + P1_16 = (PIN_GROUP1+PIN16), + + /* P1_17 is High-Drive pin */ + P1_17 = (PIN_GROUP1+PIN17), + + P1_18 = (PIN_GROUP1+PIN18), + P1_19 = (PIN_GROUP1+PIN19), + P1_20 = (PIN_GROUP1+PIN20), + + /* Group Port 2 */ + P2_0 = (PIN_GROUP2+PIN0), + P2_1 = (PIN_GROUP2+PIN1), + P2_2 = (PIN_GROUP2+PIN2), + + /* P2_3 to P2_5 are High-Drive pins */ + P2_3 = (PIN_GROUP2+PIN3), + P2_4 = (PIN_GROUP2+PIN4), + P2_5 = (PIN_GROUP2+PIN5), + + P2_6 = (PIN_GROUP2+PIN6), + P2_7 = (PIN_GROUP2+PIN7), + P2_8 = (PIN_GROUP2+PIN8), + P2_9 = (PIN_GROUP2+PIN9), + P2_10 = (PIN_GROUP2+PIN10), + P2_11 = (PIN_GROUP2+PIN11), + P2_12 = (PIN_GROUP2+PIN12), + P2_13 = (PIN_GROUP2+PIN13), + + /* Group Port 3 */ + P3_0 = (PIN_GROUP3+PIN0), + P3_1 = (PIN_GROUP3+PIN1), + P3_2 = (PIN_GROUP3+PIN2), + + /* P3_3 is High-Speed pin */ + P3_3 = (PIN_GROUP3+PIN3), + + P3_4 = (PIN_GROUP3+PIN4), + P3_5 = (PIN_GROUP3+PIN5), + P3_6 = (PIN_GROUP3+PIN6), + P3_7 = (PIN_GROUP3+PIN7), + P3_8 = (PIN_GROUP3+PIN8), + + /* Group Port 4 */ + P4_0 = (PIN_GROUP4+PIN0), + P4_1 = (PIN_GROUP4+PIN1), + P4_2 = (PIN_GROUP4+PIN2), + P4_3 = (PIN_GROUP4+PIN3), + P4_4 = (PIN_GROUP4+PIN4), + P4_5 = (PIN_GROUP4+PIN5), + P4_6 = (PIN_GROUP4+PIN6), + P4_7 = (PIN_GROUP4+PIN7), + P4_8 = (PIN_GROUP4+PIN8), + P4_9 = (PIN_GROUP4+PIN9), + P4_10 = (PIN_GROUP4+PIN10), + + /* Group Port 5 */ + P5_0 = (PIN_GROUP5+PIN0), + P5_1 = (PIN_GROUP5+PIN1), + P5_2 = (PIN_GROUP5+PIN2), + P5_3 = (PIN_GROUP5+PIN3), + P5_4 = (PIN_GROUP5+PIN4), + P5_5 = (PIN_GROUP5+PIN5), + P5_6 = (PIN_GROUP5+PIN6), + P5_7 = (PIN_GROUP5+PIN7), + + /* Group Port 6 */ + P6_0 = (PIN_GROUP6+PIN0), + P6_1 = (PIN_GROUP6+PIN1), + P6_2 = (PIN_GROUP6+PIN2), + P6_3 = (PIN_GROUP6+PIN3), + P6_4 = (PIN_GROUP6+PIN4), + P6_5 = (PIN_GROUP6+PIN5), + P6_6 = (PIN_GROUP6+PIN6), + P6_7 = (PIN_GROUP6+PIN7), + P6_8 = (PIN_GROUP6+PIN8), + P6_9 = (PIN_GROUP6+PIN9), + P6_10 = (PIN_GROUP6+PIN10), + P6_11 = (PIN_GROUP6+PIN11), + P6_12 = (PIN_GROUP6+PIN12), + + /* Group Port 7 */ + P7_0 = (PIN_GROUP7+PIN0), + P7_1 = (PIN_GROUP7+PIN1), + P7_2 = (PIN_GROUP7+PIN2), + P7_3 = (PIN_GROUP7+PIN3), + P7_4 = (PIN_GROUP7+PIN4), + P7_5 = (PIN_GROUP7+PIN5), + P7_6 = (PIN_GROUP7+PIN6), + P7_7 = (PIN_GROUP7+PIN7), + + /* Group Port 8 */ + /* P8_0 to P8_2 are High-Drive pins */ + P8_0 = (PIN_GROUP8+PIN0), + P8_1 = (PIN_GROUP8+PIN1), + P8_2 = (PIN_GROUP8+PIN2), + + P8_3 = (PIN_GROUP8+PIN3), + P8_4 = (PIN_GROUP8+PIN4), + P8_5 = (PIN_GROUP8+PIN5), + P8_6 = (PIN_GROUP8+PIN6), + P8_7 = (PIN_GROUP8+PIN7), + P8_8 = (PIN_GROUP8+PIN8), + + /* Group Port 9 */ + P9_0 = (PIN_GROUP9+PIN0), + P9_1 = (PIN_GROUP9+PIN1), + P9_2 = (PIN_GROUP9+PIN2), + P9_3 = (PIN_GROUP9+PIN3), + P9_4 = (PIN_GROUP9+PIN4), + P9_5 = (PIN_GROUP9+PIN5), + P9_6 = (PIN_GROUP9+PIN6), + + /* Group Port A */ + PA_0 = (PIN_GROUPA+PIN0), + /* PA_1 to PA_3 are Normal & High-Drive Pins */ + PA_1 = (PIN_GROUPA+PIN1), + PA_2 = (PIN_GROUPA+PIN2), + PA_3 = (PIN_GROUPA+PIN3), + PA_4 = (PIN_GROUPA+PIN4), + + /* Group Port B */ + PB_0 = (PIN_GROUPB+PIN0), + PB_1 = (PIN_GROUPB+PIN1), + PB_2 = (PIN_GROUPB+PIN2), + PB_3 = (PIN_GROUPB+PIN3), + PB_4 = (PIN_GROUPB+PIN4), + PB_5 = (PIN_GROUPB+PIN5), + PB_6 = (PIN_GROUPB+PIN6), + + /* Group Port C */ + PC_0 = (PIN_GROUPC+PIN0), + PC_1 = (PIN_GROUPC+PIN1), + PC_2 = (PIN_GROUPC+PIN2), + PC_3 = (PIN_GROUPC+PIN3), + PC_4 = (PIN_GROUPC+PIN4), + PC_5 = (PIN_GROUPC+PIN5), + PC_6 = (PIN_GROUPC+PIN6), + PC_7 = (PIN_GROUPC+PIN7), + PC_8 = (PIN_GROUPC+PIN8), + PC_9 = (PIN_GROUPC+PIN9), + PC_10 = (PIN_GROUPC+PIN10), + PC_11 = (PIN_GROUPC+PIN11), + PC_12 = (PIN_GROUPC+PIN12), + PC_13 = (PIN_GROUPC+PIN13), + PC_14 = (PIN_GROUPC+PIN14), + + /* Group Port D (seems not configurable through SCU, not defined in UM10503.pdf Rev.1, keep it here) */ + PD_0 = (PIN_GROUPD+PIN0), + PD_1 = (PIN_GROUPD+PIN1), + PD_2 = (PIN_GROUPD+PIN2), + PD_3 = (PIN_GROUPD+PIN3), + PD_4 = (PIN_GROUPD+PIN4), + PD_5 = (PIN_GROUPD+PIN5), + PD_6 = (PIN_GROUPD+PIN6), + PD_7 = (PIN_GROUPD+PIN7), + PD_8 = (PIN_GROUPD+PIN8), + PD_9 = (PIN_GROUPD+PIN9), + PD_10 = (PIN_GROUPD+PIN10), + PD_11 = (PIN_GROUPD+PIN11), + PD_12 = (PIN_GROUPD+PIN12), + PD_13 = (PIN_GROUPD+PIN13), + PD_14 = (PIN_GROUPD+PIN14), + PD_15 = (PIN_GROUPD+PIN15), + PD_16 = (PIN_GROUPD+PIN16), + + /* Group Port E */ + PE_0 = (PIN_GROUPE+PIN0), + PE_1 = (PIN_GROUPE+PIN1), + PE_2 = (PIN_GROUPE+PIN2), + PE_3 = (PIN_GROUPE+PIN3), + PE_4 = (PIN_GROUPE+PIN4), + PE_5 = (PIN_GROUPE+PIN5), + PE_6 = (PIN_GROUPE+PIN6), + PE_7 = (PIN_GROUPE+PIN7), + PE_8 = (PIN_GROUPE+PIN8), + PE_9 = (PIN_GROUPE+PIN9), + PE_10 = (PIN_GROUPE+PIN10), + PE_11 = (PIN_GROUPE+PIN11), + PE_12 = (PIN_GROUPE+PIN12), + PE_13 = (PIN_GROUPE+PIN13), + PE_14 = (PIN_GROUPE+PIN14), + PE_15 = (PIN_GROUPE+PIN15), + + /* Group Port F */ + PF_0 = (PIN_GROUPF+PIN0), + PF_1 = (PIN_GROUPF+PIN1), + PF_2 = (PIN_GROUPF+PIN2), + PF_3 = (PIN_GROUPF+PIN3), + PF_4 = (PIN_GROUPF+PIN4), + PF_5 = (PIN_GROUPF+PIN5), + PF_6 = (PIN_GROUPF+PIN6), + PF_7 = (PIN_GROUPF+PIN7), + PF_8 = (PIN_GROUPF+PIN8), + PF_9 = (PIN_GROUPF+PIN9), + PF_10 = (PIN_GROUPF+PIN10), + PF_11 = (PIN_GROUPF+PIN11), + + /* Group Clock 0 to 3 High-Speed pins */ + CLK0 = (SCU_BASE + 0xC00), + CLK1 = (SCU_BASE + 0xC04), + CLK2 = (SCU_BASE + 0xC08), + CLK3 = (SCU_BASE + 0xC0C) } scu_grp_pin_t; -/* - * Pin Configuration to be used for scu_pinmux() parameter scu_conf - * For normal-drive pins, high-drive pins, high-speed pins - */ -/* - * Function BIT0 to 2. - * Common to normal-drive pins, high-drive pins, high-speed pins. - */ -#define SCU_CONF_FUNCTION0 (0x0) -#define SCU_CONF_FUNCTION1 (0x1) -#define SCU_CONF_FUNCTION2 (0x2) -#define SCU_CONF_FUNCTION3 (0x3) -#define SCU_CONF_FUNCTION4 (0x4) -#define SCU_CONF_FUNCTION5 (0x5) -#define SCU_CONF_FUNCTION6 (0x6) -#define SCU_CONF_FUNCTION7 (0x7) - -/* - * Enable pull-down resistor at pad - * By default=0 Disable pull-down. - * Available to normal-drive pins, high-drive pins, high-speed pins - */ -#define SCU_CONF_EPD_EN_PULLDOWN (BIT3) - -/* - * Disable pull-up resistor at pad. - * By default=0 the pull-up resistor is enabled at reset. - * Available to normal-drive pins, high-drive pins, high-speed pins - */ -#define SCU_CONF_EPUN_DIS_PULLUP (BIT4) - -/* - * Select Slew Rate. - * By Default=0 Slow. - * Available to normal-drive pins and high-speed pins, reserved for high-drive pins. - */ -#define SCU_CONF_EHS_FAST (BIT5) +/* +* Pin Configuration to be used for scu_pinmux() parameter scu_conf +* For normal-drive pins, high-drive pins, high-speed pins +*/ +/* +* Function BIT0 to 2. +* Common to normal-drive pins, high-drive pins, high-speed pins. +*/ +#define SCU_CONF_FUNCTION0 (0x0) +#define SCU_CONF_FUNCTION1 (0x1) +#define SCU_CONF_FUNCTION2 (0x2) +#define SCU_CONF_FUNCTION3 (0x3) +#define SCU_CONF_FUNCTION4 (0x4) +#define SCU_CONF_FUNCTION5 (0x5) +#define SCU_CONF_FUNCTION6 (0x6) +#define SCU_CONF_FUNCTION7 (0x7) + +/* +* Enable pull-down resistor at pad +* By default=0 Disable pull-down. +* Available to normal-drive pins, high-drive pins, high-speed pins +*/ +#define SCU_CONF_EPD_EN_PULLDOWN (BIT3) + +/* +* Disable pull-up resistor at pad. +* By default=0 the pull-up resistor is enabled at reset. +* Available to normal-drive pins, high-drive pins, high-speed pins +*/ +#define SCU_CONF_EPUN_DIS_PULLUP (BIT4) + +/* +* Select Slew Rate. +* By Default=0 Slow. +* Available to normal-drive pins and high-speed pins, reserved for high-drive pins. +*/ +#define SCU_CONF_EHS_FAST (BIT5) /* - * Input buffer enable. - * By Default=0 Disable Input Buffer. - * The input buffer is disabled by default at reset and must be enabled. - * for receiving(in normal/highspeed-drive) or to transfer data from the I/O buffer to the pad(in high-drive pins). - * Available to normal-drive pins, high-drive pins, high-speed pins. - */ -#define SCU_CONF_EZI_EN_IN_BUFFER (BIT6) +* Input buffer enable. +* By Default=0 Disable Input Buffer. +* The input buffer is disabled by default at reset and must be enabled. +* for receiving(in normal/highspeed-drive) or to transfer data from the I/O buffer to the pad(in high-drive pins). +* Available to normal-drive pins, high-drive pins, high-speed pins. +*/ +#define SCU_CONF_EZI_EN_IN_BUFFER (BIT6) /* - * Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz. - * Available to normal-drive pins, high-drive pins, high-speed pins. - */ -#define SCU_CONF_ZIF_DIS_IN_GLITCH_FILT (BIT7) +* Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz. +* Available to normal-drive pins, high-drive pins, high-speed pins. +*/ +#define SCU_CONF_ZIF_DIS_IN_GLITCH_FILT (BIT7) /* - * Select drive strength. (default=0 Normal-drive: 4 mA drive strength) (BIT8/9). - * Available to high-drive pins, reserved for others. - */ -#define SCU_CONF_EHD_NORMAL_DRIVE_8MILLIA (0x100) -#define SCU_CONF_EHD_NORMAL_DRIVE_14MILLIA (0x200) -#define SCU_CONF_EHD_NORMAL_DRIVE_20MILLIA (0x300) +* Select drive strength. (default=0 Normal-drive: 4 mA drive strength) (BIT8/9). +* Available to high-drive pins, reserved for others. +*/ +#define SCU_CONF_EHD_NORMAL_DRIVE_8MILLIA (0x100) +#define SCU_CONF_EHD_NORMAL_DRIVE_14MILLIA (0x200) +#define SCU_CONF_EHD_NORMAL_DRIVE_20MILLIA (0x300) /* BIT10 to 31 are Reserved */ /* Configuration for different I/O pins types */ -#define SCU_EMC_IO (SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) -#define SCU_LCD (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) -#define SCU_CLK_IN (SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) -#define SCU_CLK_OUT (SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) -#define SCU_GPIO_PUP (SCU_CONF_EZI_EN_IN_BUFFER) -#define SCU_GPIO_PDN (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EZI_EN_IN_BUFFER) -#define SCU_GPIO_NOPULL (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EZI_EN_IN_BUFFER) -#define SCU_GPIO_FAST (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) -#define SCU_UART_RX_TX (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EZI_EN_IN_BUFFER) -#define SCU_SSP_IO (SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) +#define SCU_EMC_IO (SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) +#define SCU_LCD (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) +#define SCU_CLK_IN (SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) +#define SCU_CLK_OUT (SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) +#define SCU_GPIO_PUP (SCU_CONF_EZI_EN_IN_BUFFER) +#define SCU_GPIO_PDN (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EZI_EN_IN_BUFFER) +#define SCU_GPIO_NOPULL (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EZI_EN_IN_BUFFER) +#define SCU_GPIO_FAST (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) +#define SCU_UART_RX_TX (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EZI_EN_IN_BUFFER) +#define SCU_SSP_IO (SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) void scu_pinmux(scu_grp_pin_t group_pin, u32 scu_conf); diff --git a/include/libopencm3/lpc43xx/ssp.h b/include/libopencm3/lpc43xx/ssp.h index f645e4c..6a1510c 100644 --- a/include/libopencm3/lpc43xx/ssp.h +++ b/include/libopencm3/lpc43xx/ssp.h @@ -1,21 +1,21 @@ /* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 Michael Ossmann - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ +* This file is part of the libopencm3 project. +* +* Copyright (C) 2012 Michael Ossmann +* +* This library is free software: you can redistribute it and/or modify +* it under the terms of the GNU Lesser General Public License as published by +* the Free Software Foundation, either version 3 of the License, or +* (at your option) any later version. +* +* This library is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU Lesser General Public License for more details. +* +* You should have received a copy of the GNU Lesser General Public License +* along with this library. If not, see . +*/ #ifndef LPC43XX_SSP_H #define LPC43XX_SSP_H @@ -26,60 +26,150 @@ /* --- Convenience macros -------------------------------------------------- */ /* SSP port base addresses (for convenience) */ -#define SSP0 SSP0_BASE -#define SSP1 SSP1_BASE +#define SSP0 SSP0_BASE +#define SSP1 SSP1_BASE /* --- SSP registers ------------------------------------------------------- */ /* Control Register 0 */ -#define SSP_CR0(port) MMIO32(port + 0x000) -#define SSP0_CR0 SSP_CR0(SSP0) -#define SSP1_CR0 SSP_CR0(SSP1) +#define SSP_CR0(port) MMIO32(port + 0x000) +#define SSP0_CR0 SSP_CR0(SSP0) +#define SSP1_CR0 SSP_CR0(SSP1) /* Control Register 1 */ -#define SSP_CR1(port) MMIO32(port + 0x004) -#define SSP0_CR1 SSP_CR1(SSP0) -#define SSP1_CR1 SSP_CR1(SSP1) +#define SSP_CR1(port) MMIO32(port + 0x004) +#define SSP0_CR1 SSP_CR1(SSP0) +#define SSP1_CR1 SSP_CR1(SSP1) /* Data Register */ -#define SSP_DR(port) MMIO32(port + 0x008) -#define SSP0_DR SSP_DR(SSP0) -#define SSP1_DR SSP_DR(SSP1) +#define SSP_DR(port) MMIO32(port + 0x008) +#define SSP0_DR SSP_DR(SSP0) +#define SSP1_DR SSP_DR(SSP1) /* Status Register */ -#define SSP_SR(port) MMIO32(port + 0x00C) -#define SSP0_SR SSP_SR(SSP0) -#define SSP1_SR SSP_SR(SSP1) +#define SSP_SR(port) MMIO32(port + 0x00C) +#define SSP0_SR SSP_SR(SSP0) +#define SSP1_SR SSP_SR(SSP1) + +#define SSP_SR_TFE BIT0 +#define SSP_SR_TNF BIT1 +#define SSP_SR_RNE BIT2 +#define SSP_SR_RFF BIT3 +#define SSP_SR_BSY BIT4 /* Clock Prescale Register */ -#define SSP_CPSR(port) MMIO32(port + 0x010) -#define SSP0_CPSR SSP_CPSR(SSP0) -#define SSP1_CPSR SSP_CPSR(SSP1) +#define SSP_CPSR(port) MMIO32(port + 0x010) +#define SSP0_CPSR SSP_CPSR(SSP0) +#define SSP1_CPSR SSP_CPSR(SSP1) /* Interrupt Mask Set and Clear Register */ -#define SSP_IMSC(port) MMIO32(port + 0x014) -#define SSP0_IMSC SSP_IMSC(SSP0) -#define SSP1_IMSC SSP_IMSC(SSP1) +#define SSP_IMSC(port) MMIO32(port + 0x014) +#define SSP0_IMSC SSP_IMSC(SSP0) +#define SSP1_IMSC SSP_IMSC(SSP1) /* Raw Interrupt Status Register */ -#define SSP_RIS(port) MMIO32(port + 0x018) -#define SSP0_RIS SSP_RIS(SSP0) -#define SSP1_RIS SSP_RIS(SSP1) +#define SSP_RIS(port) MMIO32(port + 0x018) +#define SSP0_RIS SSP_RIS(SSP0) +#define SSP1_RIS SSP_RIS(SSP1) /* Masked Interrupt Status Register */ -#define SSP_MIS(port) MMIO32(port + 0x01C) -#define SSP0_MIS SSP_MIS(SSP0) -#define SSP1_MIS SSP_MIS(SSP1) +#define SSP_MIS(port) MMIO32(port + 0x01C) +#define SSP0_MIS SSP_MIS(SSP0) +#define SSP1_MIS SSP_MIS(SSP1) /* SSPICR Interrupt Clear Register */ -#define SSP_ICR(port) MMIO32(port + 0x020) -#define SSP0_ICR SSP_ICR(SSP0) -#define SSP1_ICR SSP_ICR(SSP1) +#define SSP_ICR(port) MMIO32(port + 0x020) +#define SSP0_ICR SSP_ICR(SSP0) +#define SSP1_ICR SSP_ICR(SSP1) /* SSP1 DMA control register */ -#define SSP_DMACR(port) MMIO32(port + 0x024) -#define SSP0_DMACR SSP_DMACR(SSP0) -#define SSP1_DMACR SSP_DMACR(SSP1) +#define SSP_DMACR(port) MMIO32(port + 0x024) +#define SSP0_DMACR SSP_DMACR(SSP0) +#define SSP1_DMACR SSP_DMACR(SSP1) + +typedef enum { + SSP0_NUM = 0x0, + SSP1_NUM = 0x1 +} ssp_num_t; + +/* +* SSP Control Register 0 +*/ +/* SSP Data Size Bits 0 to 3 */ +typedef enum { + SSP_DATA_4BITS = 0x3, + SSP_DATA_5BITS = 0x4, + SSP_DATA_6BITS = 0x5, + SSP_DATA_7BITS = 0x6, + SSP_DATA_8BITS = 0x7, + SSP_DATA_9BITS = 0x8, + SSP_DATA_10BITS = 0x9, + SSP_DATA_11BITS = 0xA, + SSP_DATA_12BITS = 0xB, + SSP_DATA_13BITS = 0xC, + SSP_DATA_14BITS = 0xD, + SSP_DATA_15BITS = 0xE, + SSP_DATA_16BITS = 0xF +} ssp_datasize_t; + +/* SSP Frame Format/Type Bits 4 & 5 */ +typedef enum { + SSP_FRAME_SPI = 0x00, + SSP_FRAME_TI = BIT4, + SSP_FRAM_MICROWIRE = BIT5 +} ssp_frame_format_t; + +/* Clock Out Polarity / Clock Out Phase Bits Bits 6 & 7 */ +typedef enum { + SSP_CPOL_0_CPHA_0 = 0x0, + SSP_CPOL_1_CPHA_0 = BIT6, + SSP_CPOL_0_CPHA_1 = BIT7, + SSP_CPOL_1_CPHA_1 = (BIT6|BIT7) +} ssp_cpol_cpha_t; + +/* +* SSP Control Register 1 +*/ +/* SSP Mode Bit0 */ +typedef enum { + SSP_MODE_NORMAL = 0x0, + SSP_MODE_LOOPBACK = BIT0 +} ssp_mode_t; + +/* SSP Enable Bit1 */ +#define SSP_ENABLE BIT1 + +/* SSP Master/Slave Mode Bit2 */ +typedef enum { + SSP_MASTER = 0x0, + SSP_SLAVE = BIT2 +} ssp_master_slave_t; + +/* +* SSP Slave Output Disable Bit3 +* Slave Output Disable. This bit is relevant only in slave mode +* (MS = 1). If it is 1, this blocks this SSP controller from driving the +* transmit data line (MISO). +*/ +typedef enum { + SSP_SLAVE_OUT_ENABLE = 0x0, + SSP_SLAVE_OUT_DISABLE = BIT3 +} ssp_slave_option_t; /* This option is relevant only in slave mode */ + +void ssp_disable(ssp_num_t ssp_num); + +void ssp_init( ssp_num_t ssp_num, + ssp_datasize_t data_size, + ssp_frame_format_t frame_format, + ssp_cpol_cpha_t cpol_cpha_format, + u8 serial_clock_rate, + ssp_mode_t mode, + ssp_master_slave_t master_slave, + ssp_slave_option_t slave_option); + +u16 ssp_read(ssp_num_t ssp_num); + +void ssp_write(ssp_num_t ssp_num, u16 data); #endif diff --git a/lib/lpc43xx/Makefile b/lib/lpc43xx/Makefile index 041e3bc..54c788b 100644 --- a/lib/lpc43xx/Makefile +++ b/lib/lpc43xx/Makefile @@ -31,7 +31,7 @@ CFLAGS = -O2 -g -Wall -Wextra -I../../include -fno-common \ -mfloat-abi=hard -mfpu=fpv4-sp-d16 # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = gpio.o vector.o scu.o +OBJS = gpio.o vector.o scu.o ssp.o # VPATH += ../usb diff --git a/lib/lpc43xx/scu.c b/lib/lpc43xx/scu.c index bc495cd..addf5e2 100644 --- a/lib/lpc43xx/scu.c +++ b/lib/lpc43xx/scu.c @@ -1,28 +1,28 @@ /* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 Benjamin Vernoux - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ +* This file is part of the libopencm3 project. +* +* Copyright (C) 2012 Benjamin Vernoux +* +* This library is free software: you can redistribute it and/or modify +* it under the terms of the GNU Lesser General Public License as published by +* the Free Software Foundation, either version 3 of the License, or +* (at your option) any later version. +* +* This library is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU Lesser General Public License for more details. +* +* You should have received a copy of the GNU Lesser General Public License +* along with this library. If not, see . +*/ #include /* For pin_conf_normal value see scu.h define SCU_CONF_XXX or Configuration for different I/O pins types */ void scu_pinmux(scu_grp_pin_t group_pin, u32 scu_conf) { - MMIO32(group_pin) = scu_conf; + MMIO32(group_pin) = scu_conf; } /* For other special SCU register USB1, I2C0, ADC0/1, DAC, EMC clock delay See scu.h */ diff --git a/lib/lpc43xx/ssp.c b/lib/lpc43xx/ssp.c new file mode 100644 index 0000000..ba7026e --- /dev/null +++ b/lib/lpc43xx/ssp.c @@ -0,0 +1,132 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Benjamin Vernoux + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + +#define CGU_SRC_32K 0x00 +#define CGU_SRC_IRC 0x01 +#define CGU_SRC_ENET_RX 0x02 +#define CGU_SRC_ENET_TX 0x03 +#define CGU_SRC_GP_CLKIN 0x04 +#define CGU_SRC_XTAL 0x06 +#define CGU_SRC_PLL0USB 0x07 +#define CGU_SRC_PLL0AUDIO 0x08 +#define CGU_SRC_PLL1 0x09 +#define CGU_SRC_IDIVA 0x0C +#define CGU_SRC_IDIVB 0x0D +#define CGU_SRC_IDIVC 0x0E +#define CGU_SRC_IDIVD 0x0F +#define CGU_SRC_IDIVE 0x10 + +#define CGU_AUTOBLOCK_CLOCK_BIT 11 +#define CGU_BASE_CLK_SEL_SHIFT 24 /* clock source selection (5 bits) */ + +/* Disable SSP */ +void ssp_disable(ssp_num_t ssp_num) +{ + u32 ssp_port; + + if(ssp_num == SSP0_NUM) + { + ssp_port = SSP0; + }else + { + ssp_port = SSP1; + } + /* Disable SSP */ + SSP_CR1(ssp_port) = 0x0; +} + +/* +* SSP Init function +*/ +void ssp_init(ssp_num_t ssp_num, + ssp_datasize_t data_size, + ssp_frame_format_t frame_format, + ssp_cpol_cpha_t cpol_cpha_format, + u8 serial_clock_rate, + ssp_mode_t mode, + ssp_master_slave_t master_slave, + ssp_slave_option_t slave_option) +{ + u32 ssp_port; + u32 clock; + + if(ssp_num == SSP0_NUM) + { + ssp_port = SSP0; + }else + { + ssp_port = SSP1; + } + + /* use PLL1 as clock source for SSP1 */ + CGU_BASE_SSP1_CLK = (CGU_SRC_PLL1< Means MAX Divisor) +SSP1->CR0->SCR = 0x00 => CLK Freq 1.126MHz +SSP1->CR0->SCR = 0x01 => MOSI Freq 566.9KHz +... + +Test Oscilloscpe: +SCR=0, CPSDVSR=32 => CLK 9.025MHz +SCR=1, CPSDVSR=2 => CLK 73MHz +SCR=2, CPSDVSR=2 => CLK 49MHz +SCR=4, CPSDVSR=2 => CLK 29MHz +SCR=8, CPSDVSR=2 => CLK 16MHz +SCR=16, CPSDVSR=2 => CLK 8.5MHz +SCR=32, CPSDVSR=2 => CLK 4.386MHz +SCR=64, CPSDVSR=2 => CLK 2.227MHz +SCR=1, CPSDVSR=64 => CLK 2.262MHz + +Theory: +SCR=0, CPSDVSR=32 => 288MHz / (32*(0+1) = 9MHz +SCR=1, CPSDVSR=2 => 288MHz / (2*(1+1) = 72MHz +SCR=4, CPSDVSR=2 => 288MHz / (2*(4+1) = 28.8MHz +SCR=32, CPSDVSR=2 => 288MHz / (2*(32+1) = 4.364MHz +SCR=64, CPSDVSR=2 => 288MHz / (2*(64+1)) = 2.2154MHz +SCR=128, CPSDVSR=2 => 288MHz / (2*(128+1)) = 1.116MHz +SCR=1, CPSDVSR=64 => 288MHz / (64*(1+1)) = 2.25MHz diff --git a/examples/lpc43xx/hackrf-jellybean/ssp/sspdemo.c b/examples/lpc43xx/hackrf-jellybean/ssp/sspdemo.c index 388afc8..cdb3702 100644 --- a/examples/lpc43xx/hackrf-jellybean/ssp/sspdemo.c +++ b/examples/lpc43xx/hackrf-jellybean/ssp/sspdemo.c @@ -26,6 +26,16 @@ void gpio_setup(void) { + /* Configure all GPIO as Input (safe state) */ + GPIO0_DIR = 0; + GPIO1_DIR = 0; + GPIO2_DIR = 0; + GPIO3_DIR = 0; + GPIO4_DIR = 0; + GPIO5_DIR = 0; + GPIO6_DIR = 0; + GPIO7_DIR = 0; + /* Configure SCU Pin Mux as GPIO */ scu_pinmux(SCU_PINMUX_LED1, SCU_GPIO_FAST); scu_pinmux(SCU_PINMUX_LED2, SCU_GPIO_FAST); @@ -44,16 +54,6 @@ void gpio_setup(void) scu_pinmux(SCU_SSP1_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION1)); scu_pinmux(SCU_SSP1_SSEL, (SCU_SSP_IO | SCU_CONF_FUNCTION1)); - /* Configure all GPIO as Input (safe state) */ - GPIO0_DIR = 0; - GPIO1_DIR = 0; - GPIO2_DIR = 0; - GPIO3_DIR = 0; - GPIO4_DIR = 0; - GPIO5_DIR = 0; - GPIO6_DIR = 0; - GPIO7_DIR = 0; - /* Configure GPIO as Output */ GPIO2_DIR |= (PIN_LED1|PIN_LED2|PIN_LED3); /* Configure GPIO2[1/2/8] (P4_1/2 P6_12) as output. */ GPIO3_DIR |= PIN_EN1V8; /* GPIO3[6] on P6_10 as output. */ @@ -64,10 +64,12 @@ int main(void) int i; u8 ssp_val; u8 serial_clock_rate; + u8 clock_prescale_rate; gpio_setup(); - /* FIX Me freq */ + /* Freq About 1.12MHz => Freq = PCLK / (CPSDVSR * [SCR+1]) with PCLK=PLL1=288MHz */ + clock_prescale_rate = 2; serial_clock_rate = 128; ssp_init(SSP1_NUM, @@ -75,6 +77,7 @@ int main(void) SSP_FRAME_SPI, SSP_CPOL_0_CPHA_0, serial_clock_rate, + clock_prescale_rate, SSP_MODE_NORMAL, SSP_MASTER, SSP_SLAVE_OUT_ENABLE); diff --git a/include/libopencm3/lpc43xx/scu.h b/include/libopencm3/lpc43xx/scu.h index 641331a..6e1be7f 100644 --- a/include/libopencm3/lpc43xx/scu.h +++ b/include/libopencm3/lpc43xx/scu.h @@ -723,7 +723,7 @@ typedef enum { #define SCU_GPIO_NOPULL (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EZI_EN_IN_BUFFER) #define SCU_GPIO_FAST (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) #define SCU_UART_RX_TX (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EZI_EN_IN_BUFFER) -#define SCU_SSP_IO (SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) +#define SCU_SSP_IO (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) void scu_pinmux(scu_grp_pin_t group_pin, u32 scu_conf); diff --git a/include/libopencm3/lpc43xx/ssp.h b/include/libopencm3/lpc43xx/ssp.h index 338fd88..ed69668 100644 --- a/include/libopencm3/lpc43xx/ssp.h +++ b/include/libopencm3/lpc43xx/ssp.h @@ -159,11 +159,17 @@ typedef enum { void ssp_disable(ssp_num_t ssp_num); +/* + * SSP Init + * clk_prescale shall be in range 2 to 254 (even number only). + * Clock computation: PCLK / (CPSDVSR * [SCR+1]) => CPSDVSR=clk_prescale, SCR=serial_clock_rate + */ void ssp_init(ssp_num_t ssp_num, ssp_datasize_t data_size, ssp_frame_format_t frame_format, ssp_cpol_cpha_t cpol_cpha_format, u8 serial_clock_rate, + u8 clk_prescale, ssp_mode_t mode, ssp_master_slave_t master_slave, ssp_slave_option_t slave_option); diff --git a/lib/lpc43xx/ssp.c b/lib/lpc43xx/ssp.c index ba7026e..592b5d8 100644 --- a/lib/lpc43xx/ssp.c +++ b/lib/lpc43xx/ssp.c @@ -62,6 +62,7 @@ void ssp_init(ssp_num_t ssp_num, ssp_frame_format_t frame_format, ssp_cpol_cpha_t cpol_cpha_format, u8 serial_clock_rate, + u8 clk_prescale, ssp_mode_t mode, ssp_master_slave_t master_slave, ssp_slave_option_t slave_option) @@ -85,6 +86,7 @@ void ssp_init(ssp_num_t ssp_num, /* Configure SSP */ clock = serial_clock_rate; + SSP_CPSR(ssp_port) = clk_prescale; SSP_CR0(ssp_port) = (data_size | frame_format | cpol_cpha_format | (clock<<8) ); /* Enable SSP */ -- cgit v1.2.3 From 161aad0139deff9e65832a6bb7c87bccd80612f0 Mon Sep 17 00:00:00 2001 From: Michael Ossmann Date: Thu, 7 Jun 2012 07:14:17 -0600 Subject: quick comment fix --- examples/lpc43xx/hackrf-jellybean/jellybean-lpc4330.ld | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'examples/lpc43xx') diff --git a/examples/lpc43xx/hackrf-jellybean/jellybean-lpc4330.ld b/examples/lpc43xx/hackrf-jellybean/jellybean-lpc4330.ld index 92c25af..29e5700 100644 --- a/examples/lpc43xx/hackrf-jellybean/jellybean-lpc4330.ld +++ b/examples/lpc43xx/hackrf-jellybean/jellybean-lpc4330.ld @@ -17,7 +17,7 @@ * along with this library. If not, see . */ -/* Linker script for HackRF Jellybean (LPC4330, 1M SPI flash, 64K SRAM). */ +/* Linker script for HackRF Jellybean (LPC4330, 1M SPI flash, 264K SRAM). */ /* Define memory regions. */ MEMORY -- cgit v1.2.3 From 8d97dbc7c31d814e521ad9792fcf1914543288bf Mon Sep 17 00:00:00 2001 From: TitanMKD Date: Sat, 9 Jun 2012 18:27:42 +0200 Subject: Work on scs.h register and also nvic.h. ARM Interrupt API (see nvic.h). ARM SysTick API (see systick.h). Example using both Interrupt and SysTick and blink LED1/2/3 see systickdemo.c. --- examples/lpc43xx/hackrf-jellybean/systick/Makefile | 24 ++ examples/lpc43xx/hackrf-jellybean/systick/README | 8 + .../lpc43xx/hackrf-jellybean/systick/systickdemo.c | 184 ++++++++++++++++ include/libopencm3/cm3/scs.h | 242 +++++++++++++++++++++ include/libopencm3/lpc43xx/nvic.h | 53 +++++ include/libopencm3/lpc43xx/systick.h | 84 +++++++ lib/lpc43xx/Makefile | 2 +- lib/lpc43xx/nvic.c | 76 +++++++ lib/lpc43xx/systick.c | 69 ++++++ 9 files changed, 741 insertions(+), 1 deletion(-) create mode 100644 examples/lpc43xx/hackrf-jellybean/systick/Makefile create mode 100644 examples/lpc43xx/hackrf-jellybean/systick/README create mode 100644 examples/lpc43xx/hackrf-jellybean/systick/systickdemo.c create mode 100644 include/libopencm3/lpc43xx/systick.h create mode 100644 lib/lpc43xx/nvic.c create mode 100644 lib/lpc43xx/systick.c (limited to 'examples/lpc43xx') diff --git a/examples/lpc43xx/hackrf-jellybean/systick/Makefile b/examples/lpc43xx/hackrf-jellybean/systick/Makefile new file mode 100644 index 0000000..93b471e --- /dev/null +++ b/examples/lpc43xx/hackrf-jellybean/systick/Makefile @@ -0,0 +1,24 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2012 Benjamin Vernoux +## +## This library is free software: you can redistribute it and/or modify +## it under the terms of the GNU Lesser General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This library is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU Lesser General Public License for more details. +## +## You should have received a copy of the GNU Lesser General Public License +## along with this library. If not, see . +## + +BINARY = systickdemo + +LDSCRIPT = ../jellybean-lpc4330.ld + +include ../../Makefile.include diff --git a/examples/lpc43xx/hackrf-jellybean/systick/README b/examples/lpc43xx/hackrf-jellybean/systick/README new file mode 100644 index 0000000..8c32cdc --- /dev/null +++ b/examples/lpc43xx/hackrf-jellybean/systick/README @@ -0,0 +1,8 @@ +------------------------------------------------------------------------------ +README +------------------------------------------------------------------------------ + +This program exercises the SysTick Interrupt of ARM CortexM4 on Jellybean's LPC43xx. +It also enable Cycle Counter to be used for accurate delay independant from Clock Frequency. +The Demo Use Cycle Counter and SysTick Interrupt to compute number of cycles executed per second. +The result is LED1/2 & 3 Blink with an accurate 1s Period (using SysTick) (Checked visualy and with Oscilloscope). diff --git a/examples/lpc43xx/hackrf-jellybean/systick/systickdemo.c b/examples/lpc43xx/hackrf-jellybean/systick/systickdemo.c new file mode 100644 index 0000000..66c8e06 --- /dev/null +++ b/examples/lpc43xx/hackrf-jellybean/systick/systickdemo.c @@ -0,0 +1,184 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Benjamin Vernoux + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include +#include +#include +#include +#include + +#include "../jellybean_conf.h" + +/* Global counter incremented by SysTick Interrupt each millisecond */ +volatile u32 g_ulSysTickCount; +u32 g_NbCyclePerSecond; + +void gpio_setup(void) +{ + /* Configure all GPIO as Input (safe state) */ + GPIO0_DIR = 0; + GPIO1_DIR = 0; + GPIO2_DIR = 0; + GPIO3_DIR = 0; + GPIO4_DIR = 0; + GPIO5_DIR = 0; + GPIO6_DIR = 0; + GPIO7_DIR = 0; + + /* Configure SCU Pin Mux as GPIO */ + scu_pinmux(SCU_PINMUX_LED1, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_LED2, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_LED3, SCU_GPIO_FAST); + + scu_pinmux(SCU_PINMUX_EN1V8, SCU_GPIO_FAST); + + scu_pinmux(SCU_PINMUX_BOOT0, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_BOOT1, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_BOOT2, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_BOOT3, SCU_GPIO_FAST); + + /* Configure SSP1 Peripheral (to be moved later in SSP driver) */ + scu_pinmux(SCU_SSP1_MISO, (SCU_SSP_IO | SCU_CONF_FUNCTION5)); + scu_pinmux(SCU_SSP1_MOSI, (SCU_SSP_IO | SCU_CONF_FUNCTION5)); + scu_pinmux(SCU_SSP1_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION1)); + scu_pinmux(SCU_SSP1_SSEL, (SCU_SSP_IO | SCU_CONF_FUNCTION1)); + + /* Configure GPIO as Output */ + GPIO2_DIR |= (PIN_LED1|PIN_LED2|PIN_LED3); /* Configure GPIO2[1/2/8] (P4_1/2 P6_12) as output. */ + GPIO3_DIR |= PIN_EN1V8; /* GPIO3[6] on P6_10 as output. */ +} + +void systick_setup(void) +{ + u32 systick_reload_val; + g_ulSysTickCount = 0; + + /* Disable IRQ globally */ + asm volatile ("cpsid i"); + + /* Set processor Clock as Source Clock */ + systick_set_clocksource(STK_CTRL_CLKSOURCE); + + /* Get SysTick calibration value to obtain by default 1 tick = 10ms */ + systick_reload_val = systick_get_calib(); + /* + * Calibration seems wrong on LPC43xx(TBC) for default Freq it assume System Clock is 12MHz but it is 12*8=96MHz + * Fix the Calibration value bu multiplication by 8 + */ + systick_reload_val = (systick_reload_val*8); + + /* To obtain 1ms per tick just divide by 10 the 10ms base tick and set the reload */ + systick_reload_val = systick_reload_val/10; + systick_set_reload(systick_reload_val); + + systick_interrupt_enable(); + + /* Start counting. */ + systick_counter_enable(); + + /* Set SysTick Priority to maximum */ + nvic_set_priority(NVIC_SYSTICK_IRQ, 0xFF); + + /* Enable IRQ globally */ + asm volatile ("cpsie i"); +} + +void scs_dwt_cycle_counter_enabled(void) +{ + SCS_DEMCR |= SCS_DEMCR_TRCENA; + SCS_DWT_CTRL |= SCS_DWT_CTRL_CYCCNTENA; +} + +u32 sys_tick_get_time_ms(void) +{ + return g_ulSysTickCount; +} + +u32 sys_tick_delta_time_ms(u32 start, u32 end) +{ + #define MAX_T_U32 ((2^32)-1) + u32 diff; + + if(end > start) + { + diff=end-start; + }else + { + diff=MAX_T_U32-(start-end)+1; + } + + return diff; +} + +void sys_tick_wait_time_ms(u32 wait_ms) +{ + u32 start, end; + u32 tickms; + + start = sys_tick_get_time_ms(); + + do + { + end = sys_tick_get_time_ms(); + tickms = sys_tick_delta_time_ms(start, end); + }while(tickms < wait_ms); +} + +/* Called each 1ms/1000Hz by interrupt + 1) Count the number of cycle per second. + 2) Increment g_ulSysTickCount counter. +*/ +void sys_tick_handler(void) +{ + if(g_ulSysTickCount==0) + { + /* Clear Cycle Counter*/ + SCS_DWT_CYCCNT = 0; + }else if(g_ulSysTickCount==1000) + { + /* Capture number of cycle elapsed during 1 second */ + g_NbCyclePerSecond = SCS_DWT_CYCCNT; + } + + g_ulSysTickCount++; +} + +int main(void) +{ + systick_setup(); + + gpio_setup(); + + /* SCS & Cycle Counter enabled (used to count number of cycles executed per second see g_NbCyclePerSecond */ + scs_dwt_cycle_counter_enabled(); + + while (1) + { + gpio_set(PORT_LED1_3, (PIN_LED1|PIN_LED2|PIN_LED3)); /* LEDs on */ + + sys_tick_wait_time_ms(500); + + gpio_clear(PORT_LED1_3, (PIN_LED1|PIN_LED2|PIN_LED3)); /* LED off */ + + sys_tick_wait_time_ms(500); + } + + return 0; +} diff --git a/include/libopencm3/cm3/scs.h b/include/libopencm3/cm3/scs.h index 033ec73..fff4a1b 100644 --- a/include/libopencm3/cm3/scs.h +++ b/include/libopencm3/cm3/scs.h @@ -2,6 +2,7 @@ * This file is part of the libopencm3 project. * * Copyright (C) 2011 Gareth McMullin + * Copyright (C) 2012 Benjamin Vernoux * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by @@ -20,9 +21,85 @@ #ifndef LIBOPENCM3_CM3_SCS_H #define LIBOPENCM3_CM3_SCS_H +/* + * All the definition hereafter are generic for CortexMx ARMv7-M + * See ARM document "ARMv7-M Architecture Reference Manual" for more details. + * See also ARM document "ARM Compiler toolchain Developing Software for ARM Processors" for details on System Timer/SysTick. + */ + +/* + * The System Control Space (SCS) is a memory-mapped 4KB address space that provides 32-bit registers for + * configuration, status reporting and control. The SCS registers divide into the following groups: + * - system control and identification + * - the CPUID processor identification space + * - system configuration and status + * - fault reporting + * - a system timer, SysTick + * - a Nested Vectored Interrupt Controller (NVIC) + * - a Protected Memory System Architecture (PMSA) + * - system debug. + */ + +/* System Handler Priority 8 bits Registers, SHPR1/2/3 */ +/* Note: 12 8bit Registers */ +#define SCS_SHPR(ipr_id) MMIO8(SCS_BASE + 0xD18 + ipr_id) + +/* + * Debug Halting Control and Status Register (DHCSR). + * + * Purpose Controls halting debug. + * Usage constraints: The effect of modifying the C_STEP or C_MASKINTS bit when the system + * is running with halting debug enabled is UNPREDICTABLE. + * Halting debug is enabled when C_DEBUGEN is set to 1. The system is running when S_HALT is set to 0. + * - When C_DEBUGEN is set to 0, the processor ignores the values of all other bits in this register. + * - For more information about the use of DHCSR see Debug stepping on + * page C1-824. + * Configurations Always implemented. + */ +/* SCS_DHCSR register */ #define SCS_DHCSR MMIO32(SCS_BASE + 0xDF0) +/* + * Debug Core Register Selector Register (DCRSR). + * + * Purpose With the DCRDR, the DCRSR provides debug access to the ARM core registers, + * special-purpose registers, and Floating-point extension registers. A write to DCRSR + * specifies the register to transfer, whether the transfer is a read or a write, and starts + * the transfer. + * Usage constraints: Only accessible in Debug state. + * Configurations Always implemented. + * + */ +/* SCS_DCRS register */ #define SCS_DCRSR MMIO32(SCS_BASE + 0xDF4) +/* + * Debug Core Register Data Register (DCRDR) + * + * Purpose With the DCRSR, see Debug Core Register Selector Register, + * the DCRDR provides debug access to the ARM core registers, + * special-purpose registers, and Floating-point extension registers. The + * DCRDR is the data register for these accesses. + * - Used on its own, the DCRDR provides a message passing resource between + * an external debugger and a debug agent running on the processor. + * Note: + * The architecture does not define any handshaking mechanism for this use of DCRDR. + * Usage constraints: See Use of DCRSR and DCRDR for constraints that apply to + * particular transfers using the DCRSR and DCRDR. + * Configurations Always implemented. + * + */ +/* SCS_DCRDR register */ #define SCS_DCRDR MMIO32(SCS_BASE + 0xDF8) +/* + * Debug Exception and Monitor Control Register (DEMCR). + * + * Purpose Manages vector catch behavior and DebugMonitor handling when debugging. + * Usage constraints: + * - Bits [23:16] provide DebugMonitor exception control. + * - Bits [15:0] provide Debug state, halting debug, control. + * Configurations Always implemented. + * + */ +/* SCS_DEMCR register */ #define SCS_DEMCR MMIO32(SCS_BASE + 0xDFC) /* Debug Halting Control and Status Register (DHCSR) */ @@ -64,4 +141,169 @@ /* Bits 3:1 - Reserved */ #define SCS_DEMCR_VC_CORERESET (1 << 0) +/* + * System Control Space (SCS) => System timer register support in the SCS. + * To configure SysTick, load the interval required between SysTick events to the SysTick Reload + * Value register. The timer interrupt, or COUNTFLAG bit in the SysTick Control and Status + * register, is activated on the transition from 1 to 0, therefore it activates every n+1 clock ticks. + * If you require a period of 100, write 99 to the SysTick Reload Value register. The SysTick Reload + * Value register supports values between 0x1 and 0x00FFFFFF. + * + * If you want to use SysTick to generate an event at a timed interval, for example 1ms, you can + * use the SysTick Calibration Value Register to scale your value for the Reload register. The + * SysTick Calibration Value Register is a read-only register that contains the number of pulses for + * a period of 10ms, in the TENMS field, bits[23:0]. + * + * This register also has a SKEW bit. Bit[30] == 1 indicates that the calibration for 10ms in the + * TENMS section is not exactly 10ms due to clock frequency. Bit[31] == 1 indicates that the + * reference clock is not provided. + */ +/* + * SysTick Control and Status Register (CSR). + * Purpose Controls the system timer and provides status data. + * Usage constraints: There are no usage constraints. + * Configurations Always implemented. +*/ +#define SCS_SYST_CSR MMIO32(SCS_BASE + 0x10) + +/* SysTick Reload Value Register (CVR). + * Purpose Reads or clears the current counter value. + * Usage constraints: + * - Any write to the register clears the register to zero. + * - The counter does not provide read-modify-write protection. + * - Unsupported bits are read as zero + * Configurations Always implemented. + */ +#define CM_SCS_SYST_RVR MMIO32(SCS_BASE + 0x14) + +/* SysTick Current Value Register (RVR). + * Purpose Holds the reload value of the SYST_CVR. + * Usage constraints There are no usage constraints. + * Configurations Always implemented. + */ +#define CM_SCS_SYST_CVR MMIO32(SCS_BASE + 0x18) + +/* + * SysTick Calibration value Register(Read Only) (CALIB) + * Purpose Reads the calibration value and parameters for SysTick. + * Usage constraints: There are no usage constraints. + * Configurations Always implemented. + */ +#define CM_SCS_SYST_CALIB MMIO32(SCS_BASE + 0x1C) + +/* --- SCS_SYST_CSR values ----------------------------------------------- */ +/* Counter is operating. */ +#define SCS_SYST_CSR_ENABLE (BIT0) +/* Count to 0 changes the SysTick exception status to pending. */ +#define SCS_SYST_CSR_TICKINT (BIT1) +/* SysTick uses the processor clock. */ +#define SCS_SYST_CSR_CLKSOURCE (BIT2) +/* + * Indicates whether the counter has counted to 0 since the last read of this register: + * 0 = Timer has not counted to 0 + * 1 = Timer has counted to 0. + */ +#define SCS_SYST_CSR_COUNTFLAG (BIT16) + +/* --- CM_SCS_SYST_RVR values ----------------------------------------------- */ +/* Bit 0 to 23 => RELOAD The value to load into the SYST_CVR when the counter reaches 0. */ +/* Bit 24 to 31 are Reserved */ + +/* --- CM_SCS_SYST_CVR values ----------------------------------------------- */ +/* Bit0 to 31 => Reads or clears the current counter value. */ + +/* --- CM_SCS_SYST_CALIB values ----------------------------------------------- */ +/* + * Bit0 to 23 => TENMS Optionally, holds a reload value to be used for 10ms (100Hz) timing, subject to system clock + * skew errors. If this field is zero, the calibration value is not known. + */ +#define SCS_SYST_SYST_CALIB_TENMS_MASK (BIT24-1) + +/* + * Bit30 => SKEW Indicates whether the 10ms calibration value is exact: + * 0 = 10ms calibration value is exact. + * 1 = 10ms calibration value is inexact, because of the clock frequency + */ +#define SCS_SYST_SYST_CALIB_VALUE_INEXACT (BIT30) +/* + * Bit31 => NOREF Indicates whether the IMPLEMENTATION DEFINED reference clock is implemented: + * 0 = The reference clock is implemented. + * 1 = The reference clock is not implemented. + * When this bit is 1, the CLKSOURCE bit of the SYST_CSR register is forced to 1 and cannot + * be cleared to 0. + */ +#define SCS_SYST_SYST_CALIB_REF_NOT_IMPLEMENTED (BIT31) + +/* + * System Control Space (SCS) => Data Watchpoint and Trace (DWT). + * See http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0403c/index.html (ARMv7-M Architecture Reference Manual) + * The DWT is an optional debug unit that provides watchpoints, data tracing, and system profiling + * for the processor. + */ +/* + * DWT Control register + * Purpose Provides configuration and status information for the DWT block, and used to control features of the block + * Usage constraints: There are no usage constraints. + * Configurations Always implemented. + */ +#define SCS_DWT_CTRL MMIO32(DWT_BASE + 0x00) +/* + * DWT_CYCCNT register + * Cycle Count Register (Shows or sets the value of the processor cycle counter, CYCCNT) + * When enabled, CYCCNT increments on each processor clock cycle. On overflow, CYCCNT wraps to zero. + * + * Purpose Shows or sets the value of the processor cycle counter, CYCCNT. + * Usage constraints: The DWT unit suspends CYCCNT counting when the processor is in Debug state. + * Configurations Implemented: only when DWT_CTRL.NOCYCCNT is RAZ, see Control register, DWT_CTRL. + * When DWT_CTRL.NOCYCCNT is RAO no cycle counter is implemented and this register is UNK/SBZP. +*/ +#define SCS_DWT_CYCCNT MMIO32(DWT_BASE + 0x04) + +/* DWT_CPICNT register + * Purpose Counts additional cycles required to execute multi-cycle instructions and instruction fetch stalls. + * Usage constraints: The counter initializes to 0 when software enables its counter overflow event by + * setting the DWT_CTRL.CPIEVTENA bit to 1. + * Configurations Implemented: only when DWT_CTRL.NOPRFCNT is RAZ, see Control register, DWT_CTRL. + * If DWT_CTRL.NOPRFCNT is RAO, indicating that the implementation does not + * include the profiling counters, this register is UNK/SBZP. + */ +#define SCS_DWT_CPICNT MMIO32(DWT_BASE + 0x08) + +/* DWT_EXCCNT register */ +#define SCS_DWT_EXCCNT MMIO32(DWT_BASE + 0x0C) + +/* DWT_EXCCNT register */ +#define SCS_DWT_SLEEPCNT MMIO32(DWT_BASE + 0x10) + +/* DWT_EXCCNT register */ +#define SCS_DWT_LSUCNT MMIO32(DWT_BASE + 0x14) + +/* DWT_EXCCNT register */ +#define SCS_DWT_FOLDCNT MMIO32(DWT_BASE + 0x18) + +/* DWT_PCSR register */ +#define SCS_DWT_PCSR MMIO32(DWT_BASE + 0x18) + +/* --- SCS_DWT_CTRL values ----------------------------------------------- */ +/* + * Enables CYCCNT: + * 0 = Disabled, 1 = Enabled + * This bit is UNK/SBZP if the NOCYCCNT bit is RAO. + */ +#define SCS_DWT_CTRL_CYCCNTENA (BIT0) + +/* TODO bit definition values for other DWT_XXX register */ + +/* Macro to be called at startup to enable SCS & Cycle Counter */ +#define SCS_DWT_CYCLE_COUNTER_ENABLED() ( (SCS_DEMCR |= SCS_DEMCR_TRCENA)\ + (SCS_DWT_CTRL |= SCS_DWT_CTRL_CYCCNTENA) ) + +#define SCS_SYSTICK_DISABLED() (SCS_SYST_CSR=0) + +/* Macro to be called at startup to Enable CortexMx SysTick (but IRQ not enabled) */ +#define SCS_SYSTICK_ENABLED() (SCS_SYST_CSR=(SCS_SYST_CSR_ENABLE | SCS_SYST_CSR_CLKSOURCE)) + +/* Macro to be called at startup to Enable CortexMx SysTick and IRQ */ +#define SCS_SYSTICK_AND_IRQ_ENABLED() (SCS_SYST_CSR=(SCS_SYST_CSR_ENABLE | SCS_SYST_CSR_CLKSOURCE | SCS_SYST_CSR_TICKINT)) + #endif diff --git a/include/libopencm3/lpc43xx/nvic.h b/include/libopencm3/lpc43xx/nvic.h index 336eab8..b996ab8 100644 --- a/include/libopencm3/lpc43xx/nvic.h +++ b/include/libopencm3/lpc43xx/nvic.h @@ -3,6 +3,7 @@ * * Copyright (C) 2010 Piotr Esden-Tempski * Copyright (C) 2012 Michael Ossmann + * Copyright (C) 2012 Benjamin Vernoux * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by @@ -22,8 +23,48 @@ #define LPC43XX_NVIC_H #include +#include #include +/* --- NVIC Registers ------------------------------------------------------ */ + +/* ISER: Interrupt Set Enable Registers */ +/* Note: 8 32bit Registers */ +#define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + (iser_id * 4)) + +/* NVIC_BASE + 0x020 (0xE000 E120 - 0xE000 E17F): Reserved */ + +/* ICER: Interrupt Clear Enable Registers */ +/* Note: 8 32bit Registers */ +#define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + (icer_id * 4)) + +/* NVIC_BASE + 0x0A0 (0xE000 E1A0 - 0xE000 E1FF): Reserved */ + +/* ISPR: Interrupt Set Pending Registers */ +/* Note: 8 32bit Registers */ +#define NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + (ispr_id * 4)) + +/* NVIC_BASE + 0x120 (0xE000 E220 - 0xE000 E27F): Reserved */ + +/* ICPR: Interrupt Clear Pending Registers */ +/* Note: 8 32bit Registers */ +#define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + (icpr_id * 4)) + +/* NVIC_BASE + 0x1A0 (0xE000 E2A0 - 0xE00 E2FF): Reserved */ + +/* IABR: Interrupt Active Bit Register */ +/* Note: 8 32bit Registers */ +#define NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + (iabr_id * 4)) + +/* NVIC_BASE + 0x220 (0xE000 E320 - 0xE000 E3FF): Reserved */ + +/* IPR: Interrupt Priority Registers */ +/* Note: 240 8bit Registers */ +#define NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + ipr_id) + +/* STIR: Software Trigger Interrupt Register */ +#define NVIC_STIR MMIO32(STIR_BASE) + /* --- IRQ channel numbers-------------------------------------------------- */ /* Cortex M4 System Interrupts */ @@ -91,4 +132,16 @@ /* LPC43xx M0 specific user interrupts */ //TODO +/* --- NVIC functions ------------------------------------------------------ */ + +void nvic_enable_irq(u8 irqn); +void nvic_disable_irq(u8 irqn); +u8 nvic_get_pending_irq(u8 irqn); +void nvic_set_pending_irq(u8 irqn); +void nvic_clear_pending_irq(u8 irqn); +u8 nvic_get_active_irq(u8 irqn); +u8 nvic_get_irq_enabled(u8 irqn); +void nvic_set_priority(u8 irqn, u8 priority); +void nvic_generate_software_interrupt(u8 irqn); + #endif diff --git a/include/libopencm3/lpc43xx/systick.h b/include/libopencm3/lpc43xx/systick.h new file mode 100644 index 0000000..9f8b38d --- /dev/null +++ b/include/libopencm3/lpc43xx/systick.h @@ -0,0 +1,84 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * Copyright (C) 2012 Benjamin Vernoux + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_SYSTICK_H +#define LIBOPENCM3_SYSTICK_H + +#include +#include +#include + +/* --- SYSTICK registers --------------------------------------------------- */ +/* See also libopencm3\cm3\scs.h for details on SysTicks registers */ + +/* Control and status register (STK_CTRL) */ +#define STK_CTRL MMIO32(SYS_TICK_BASE + 0x00) + +/* reload value register (STK_LOAD) */ +#define STK_LOAD MMIO32(SYS_TICK_BASE + 0x04) + +/* current value register (STK_VAL) */ +#define STK_VAL MMIO32(SYS_TICK_BASE + 0x08) + +/* calibration value register (STK_CALIB) */ +#define STK_CALIB MMIO32(SYS_TICK_BASE + 0x0C) + +/* --- STK_CTRL values ----------------------------------------------------- */ +/* Bits [31:17] Reserved, must be kept cleared. */ +/* COUNTFLAG: */ +#define STK_CTRL_COUNTFLAG (1 << 16) +/* Bits [15:3] Reserved, must be kept cleared. */ +/* CLKSOURCE: Clock source selection */ +#define STK_CTRL_CLKSOURCE (1 << 2) +/* TICKINT: SysTick exception request enable */ +#define STK_CTRL_TICKINT (1 << 1) +/* ENABLE: Counter enable */ +#define STK_CTRL_ENABLE (1 << 0) + +/* --- STK_LOAD values ----------------------------------------------------- */ +/* Bits [31:24] Reserved, must be kept cleared. */ +/* RELOAD[23:0]: RELOAD value */ + +/* --- STK_VAL values ------------------------------------------------------ */ +/* Bits [31:24] Reserved, must be kept cleared. */ +/* CURRENT[23:0]: Current counter value */ + +/* --- STK_CALIB values ---------------------------------------------------- */ +/* NOREF: NOREF flag */ +#define STK_CALIB_NOREF (1 << 31) +/* SKEW: SKEW flag */ +#define STK_CALIB_SKEW (1 << 30) +/* Bits [29:24] Reserved, must be kept cleared. */ +/* TENMS[23:0]: Calibration value */ + +/* --- Function Prototypes ------------------------------------------------- */ + +void systick_set_reload(u32 value); +u32 systick_get_value(void); +void systick_set_clocksource(u8 clocksource); +void systick_interrupt_enable(void); +void systick_interrupt_disable(void); +void systick_counter_enable(void); +void systick_counter_disable(void); +u8 systick_get_countflag(void); + +u32 systick_get_calib(void); + +#endif diff --git a/lib/lpc43xx/Makefile b/lib/lpc43xx/Makefile index 38d5bf7..e8bd8fc 100644 --- a/lib/lpc43xx/Makefile +++ b/lib/lpc43xx/Makefile @@ -31,7 +31,7 @@ CFLAGS = -O2 -g -Wall -Wextra -I../../include -fno-common \ -mfloat-abi=hard -mfpu=fpv4-sp-d16 # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = gpio.o vector.o scu.o i2c.o ssp.o +OBJS = gpio.o vector.o scu.o i2c.o ssp.o nvic.o systick.o # VPATH += ../usb diff --git a/lib/lpc43xx/nvic.c b/lib/lpc43xx/nvic.c new file mode 100644 index 0000000..4793312 --- /dev/null +++ b/lib/lpc43xx/nvic.c @@ -0,0 +1,76 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * Copyright (C) 2012 Fergus Noble + * Copyright (C) 2012 Benjamin Vernoux + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ +#include +#include + +void nvic_enable_irq(u8 irqn) +{ + NVIC_ISER(irqn / 32) = (1 << (irqn % 32)); +} + +void nvic_disable_irq(u8 irqn) +{ + NVIC_ICER(irqn / 32) = (1 << (irqn % 32)); +} + +u8 nvic_get_pending_irq(u8 irqn) +{ + return NVIC_ISPR(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0; +} + +void nvic_set_pending_irq(u8 irqn) +{ + NVIC_ISPR(irqn / 32) = (1 << (irqn % 32)); +} + +void nvic_clear_pending_irq(u8 irqn) +{ + NVIC_ICPR(irqn / 32) = (1 << (irqn % 32)); +} + +u8 nvic_get_active_irq(u8 irqn) +{ + return NVIC_IABR(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0; +} + +u8 nvic_get_irq_enabled(u8 irqn) +{ + return NVIC_ISER(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0; +} + +void nvic_set_priority(u8 irqn, u8 priority) +{ + if(irqn>NVIC_M4_QEI_IRQ) + { + /* Cortex-M system interrupts */ + SCS_SHPR( (irqn&0xF)-4 ) = priority; + }else + { + /* Device specific interrupts */ + NVIC_IPR(irqn) = priority; + } +} + +void nvic_generate_software_interrupt(u8 irqn) +{ + if (irqn <= 239) + NVIC_STIR |= irqn; +} diff --git a/lib/lpc43xx/systick.c b/lib/lpc43xx/systick.c new file mode 100644 index 0000000..82345a9 --- /dev/null +++ b/lib/lpc43xx/systick.c @@ -0,0 +1,69 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * Copyright (C) 2012 Benjamin Vernoux + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include + +void systick_set_reload(u32 value) +{ + STK_LOAD = (value & 0x00FFFFFF); +} + +u32 systick_get_value(void) +{ + return STK_VAL; +} + +void systick_set_clocksource(u8 clocksource) +{ + STK_CTRL |= clocksource; +} + +void systick_interrupt_enable(void) +{ + STK_CTRL |= STK_CTRL_TICKINT; +} + +void systick_interrupt_disable(void) +{ + STK_CTRL &= ~STK_CTRL_TICKINT; +} + +void systick_counter_enable(void) +{ + STK_CTRL |= STK_CTRL_ENABLE; +} + +void systick_counter_disable(void) +{ + STK_CTRL &= ~STK_CTRL_ENABLE; +} + +u8 systick_get_countflag(void) +{ + if (STK_CTRL & STK_CTRL_COUNTFLAG) + return 1; + else + return 0; +} + +u32 systick_get_calib(void) +{ + return (STK_CALIB&0x00FFFFFF); +} -- cgit v1.2.3 From 3c8e76f679158d2a5cb1a16a7da1c4f48066ddfc Mon Sep 17 00:00:00 2001 From: TitanMKD Date: Sun, 10 Jun 2012 11:44:36 +0200 Subject: Added ROM to RAM code copy & exec with example of how to use it (miniblink_rom_to_ram). --- .../jellybean-lpc4330_rom_to_ram.ld | 35 ++++++++ .../hackrf-jellybean/miniblink_rom_to_ram/Makefile | 24 ++++++ .../hackrf-jellybean/miniblink_rom_to_ram/README | 12 +++ .../miniblink_rom_to_ram/miniblink.c | 82 ++++++++++++++++++ lib/lpc43xx/libopencm3_lpc43xx.ld | 4 + lib/lpc43xx/libopencm3_lpc43xx_rom_to_ram.ld | 97 ++++++++++++++++++++++ lib/lpc43xx/vector.c | 19 +++++ 7 files changed, 273 insertions(+) create mode 100644 examples/lpc43xx/hackrf-jellybean/jellybean-lpc4330_rom_to_ram.ld create mode 100644 examples/lpc43xx/hackrf-jellybean/miniblink_rom_to_ram/Makefile create mode 100644 examples/lpc43xx/hackrf-jellybean/miniblink_rom_to_ram/README create mode 100644 examples/lpc43xx/hackrf-jellybean/miniblink_rom_to_ram/miniblink.c create mode 100644 lib/lpc43xx/libopencm3_lpc43xx_rom_to_ram.ld (limited to 'examples/lpc43xx') diff --git a/examples/lpc43xx/hackrf-jellybean/jellybean-lpc4330_rom_to_ram.ld b/examples/lpc43xx/hackrf-jellybean/jellybean-lpc4330_rom_to_ram.ld new file mode 100644 index 0000000..385b081 --- /dev/null +++ b/examples/lpc43xx/hackrf-jellybean/jellybean-lpc4330_rom_to_ram.ld @@ -0,0 +1,35 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Uwe Hermann + * Copyright (C) 2012 Benjamin Vernoux + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* Linker script for HackRF Jellybean (LPC4330, 1M SPI flash, 264K SRAM). */ + +/* Define memory regions. */ +MEMORY +{ + /* Physical address in Flash used to copy Code from Flash to RAM */ + rom_flash (rx) : ORIGIN = 0x80000000, LENGTH = 1M + /* rom is really the shadow region that points to SPI flash or elsewhere */ + rom (rx) : ORIGIN = 0x00000000, LENGTH = 1M + ram (rwx) : ORIGIN = 0x10000000, LENGTH = 128K + /* there are some additional RAM regions */ +} + +/* Include the common ld script. */ +INCLUDE libopencm3_lpc43xx_rom_to_ram.ld diff --git a/examples/lpc43xx/hackrf-jellybean/miniblink_rom_to_ram/Makefile b/examples/lpc43xx/hackrf-jellybean/miniblink_rom_to_ram/Makefile new file mode 100644 index 0000000..56cb540 --- /dev/null +++ b/examples/lpc43xx/hackrf-jellybean/miniblink_rom_to_ram/Makefile @@ -0,0 +1,24 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2010 Uwe Hermann +## +## This library is free software: you can redistribute it and/or modify +## it under the terms of the GNU Lesser General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This library is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU Lesser General Public License for more details. +## +## You should have received a copy of the GNU Lesser General Public License +## along with this library. If not, see . +## + +BINARY = miniblink + +LDSCRIPT = ../jellybean-lpc4330_rom_to_ram.ld + +include ../../Makefile.include diff --git a/examples/lpc43xx/hackrf-jellybean/miniblink_rom_to_ram/README b/examples/lpc43xx/hackrf-jellybean/miniblink_rom_to_ram/README new file mode 100644 index 0000000..02960fa --- /dev/null +++ b/examples/lpc43xx/hackrf-jellybean/miniblink_rom_to_ram/README @@ -0,0 +1,12 @@ +------------------------------------------------------------------------------ +README +------------------------------------------------------------------------------ + +This is the smallest-possible example program using libopencm3. + +It's intended for the Jellybean development board from the HackRF project: + +https://github.com/mossmann/hackrf + +It should blink LED1 on the board. +This example copy the Code from ROM to RAM and execute code from RAM. diff --git a/examples/lpc43xx/hackrf-jellybean/miniblink_rom_to_ram/miniblink.c b/examples/lpc43xx/hackrf-jellybean/miniblink_rom_to_ram/miniblink.c new file mode 100644 index 0000000..3b3919b --- /dev/null +++ b/examples/lpc43xx/hackrf-jellybean/miniblink_rom_to_ram/miniblink.c @@ -0,0 +1,82 @@ +/* +* This file is part of the libopencm3 project. +* +* Copyright (C) 2010 Uwe Hermann +* Copyright (C) 2012 Michael Ossmann +* +* This library is free software: you can redistribute it and/or modify +* it under the terms of the GNU Lesser General Public License as published by +* the Free Software Foundation, either version 3 of the License, or +* (at your option) any later version. +* +* This library is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU Lesser General Public License for more details. +* +* You should have received a copy of the GNU Lesser General Public License +* along with this library. If not, see . +*/ + +#include +#include + +#include "../jellybean_conf.h" + +void gpio_setup(void) +{ + /* Configure SCU Pin Mux as GPIO */ + scu_pinmux(SCU_PINMUX_LED1, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_LED2, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_LED3, SCU_GPIO_FAST); + + scu_pinmux(SCU_PINMUX_EN1V8, SCU_GPIO_FAST); + + scu_pinmux(SCU_PINMUX_BOOT0, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_BOOT1, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_BOOT2, SCU_GPIO_FAST); + scu_pinmux(SCU_PINMUX_BOOT3, SCU_GPIO_FAST); + + /* Configure all GPIO as Input (safe state) */ + GPIO0_DIR = 0; + GPIO1_DIR = 0; + GPIO2_DIR = 0; + GPIO3_DIR = 0; + GPIO4_DIR = 0; + GPIO5_DIR = 0; + GPIO6_DIR = 0; + GPIO7_DIR = 0; + + /* Configure GPIO as Output */ + GPIO2_DIR |= (PIN_LED1|PIN_LED2|PIN_LED3); /* Configure GPIO2[1/2/8] (P4_1/2 P6_12) as output. */ + GPIO3_DIR |= PIN_EN1V8; /* GPIO3[6] on P6_10 as output. */ +} + +u32 boot0, boot1, boot2, boot3; + +int main(void) +{ + int i; + gpio_setup(); + + /* Set 1V8 */ + gpio_set(PORT_EN1V8, PIN_EN1V8); + + /* Blink LED1/2/3 on the board and Read BOOT0/1/2/3 pins. */ + while (1) + { + boot0 = BOOT0_STATE; + boot1 = BOOT1_STATE; + boot2 = BOOT2_STATE; + boot3 = BOOT3_STATE; + + gpio_set(PORT_LED1_3, (PIN_LED1|PIN_LED2|PIN_LED3)); /* LEDs on */ + for (i = 0; i < 2000000; i++) /* Wait a bit. */ + __asm__("nop"); + gpio_clear(PORT_LED1_3, (PIN_LED1|PIN_LED2|PIN_LED3)); /* LED off */ + for (i = 0; i < 2000000; i++) /* Wait a bit. */ + __asm__("nop"); + } + + return 0; +} diff --git a/lib/lpc43xx/libopencm3_lpc43xx.ld b/lib/lpc43xx/libopencm3_lpc43xx.ld index 5c3221b..47b403b 100644 --- a/lib/lpc43xx/libopencm3_lpc43xx.ld +++ b/lib/lpc43xx/libopencm3_lpc43xx.ld @@ -3,6 +3,7 @@ * * Copyright (C) 2009 Uwe Hermann * Copyright (C) 2012 Michael Ossmann + * Copyright (C) 2012 Benjamin Vernoux * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by @@ -35,6 +36,7 @@ SECTIONS .text : { . = ALIGN(0x400); + _text_ram = 0; /* Start of Code in RAM NULL because Copy of Code from ROM to RAM disabled */ *(.vectors) /* Vector table */ *(.text*) /* Program code */ . = ALIGN(4); @@ -50,6 +52,8 @@ SECTIONS __exidx_end = .; _etext = .; + _etext_ram = 0; /* Start of Code in RAM NULL because Copy of Code from ROM to RAM disabled */ + _etext_rom = 0; /* Start of Code in RAM NULL because Copy of Code from ROM to RAM disabled */ . = ORIGIN(ram); diff --git a/lib/lpc43xx/libopencm3_lpc43xx_rom_to_ram.ld b/lib/lpc43xx/libopencm3_lpc43xx_rom_to_ram.ld new file mode 100644 index 0000000..f833aaf --- /dev/null +++ b/lib/lpc43xx/libopencm3_lpc43xx_rom_to_ram.ld @@ -0,0 +1,97 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * Copyright (C) 2012 Michael Ossmann + * Copyright (C) 2012 Benjamin Vernoux + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* Generic linker script for LPC43XX targets using libopencm3. */ + +/* Memory regions must be defined in the ld script which includes this one. */ + +/* Enforce emmition of the vector table. */ +EXTERN (vector_table) + +/* Define the entry point of the output file. */ +ENTRY(reset_handler) + +/* Define sections. */ +SECTIONS +{ + . = ORIGIN(rom); + + .text : { + . = ALIGN(0x400); + _text_ram = . + ORIGIN(ram); /* Start of Code in RAM */ + + *(.vectors) /* Vector table */ + *(.text*) /* Program code */ + . = ALIGN(4); + *(.rodata*) /* Read-only data */ + . = ALIGN(4); + } >rom + + /* exception index - required due to libgcc.a issuing /0 exceptions */ + __exidx_start = .; + .ARM.exidx : { + *(.ARM.exidx*) + } > rom + __exidx_end = .; + + _etext = .; + _etext_ram = . + ORIGIN(ram); + _etext_rom = . + ORIGIN(rom_flash); + + . = ORIGIN(ram); + + .data : { + _data = .; + *(.data*) /* Read-write initialized data */ + . = ALIGN(4); + _edata = .; + } >ram AT >rom + + .bss : { + *(.bss*) /* Read-write zero initialized data */ + *(COMMON) + . = ALIGN(4); + _ebss = .; + } >ram + + /* exception unwind data - required due to libgcc.a issuing /0 exceptions */ + .ARM.extab : { + *(.ARM.extab*) + } >ram + + /* + * The .eh_frame section appears to be used for C++ exception handling. + * You may need to fix this if you're using C++. + */ + /DISCARD/ : { *(.eh_frame) } + + /* + * Another section used by C++ stuff, appears when using newlib with + * 64bit (long long) printf support - discard it for now. + */ + /DISCARD/ : { *(.ARM.exidx) } + + end = .; + + /* Leave room above stack for IAP to run. */ + __StackTop = ORIGIN(ram) + LENGTH(ram) - 32; + PROVIDE(_stack = __StackTop); +} diff --git a/lib/lpc43xx/vector.c b/lib/lpc43xx/vector.c index 33eee4a..631e54e 100644 --- a/lib/lpc43xx/vector.c +++ b/lib/lpc43xx/vector.c @@ -22,6 +22,7 @@ /* Symbols exported by the linker script(s). */ extern unsigned _etext, _data, _edata, _ebss, _stack; +extern unsigned _etext_ram, _text_ram, _etext_rom; void main(void); void reset_handler(void); @@ -158,11 +159,29 @@ void (*const vector_table[]) (void) = { qei_irqhandler, }; +#define MMIO32(addr) (*(volatile unsigned long*)(addr)) +#define CREG_M4MEMMAP MMIO32( (0x40043000 + 0x100) ) + void reset_handler(void) { volatile unsigned *src, *dest; __asm__("MSR msp, %0" : : "r"(&_stack)); + /* Copy the code from ROM to Real RAM (if enabled) */ + if( (&_etext_ram-&_text_ram) > 0 ) + { + src = &_etext_rom-(&_etext_ram-&_text_ram); + for(dest = &_text_ram; dest < &_etext_ram; ) + { + *dest++ = *src++; + } + + /* Change Shadow memory to Real RAM */ + CREG_M4MEMMAP = (unsigned long)&_text_ram; + + /* Continue Execution in RAM */ + } + for (src = &_etext, dest = &_data; dest < &_edata; src++, dest++) *dest = *src; -- cgit v1.2.3 From c65ca01044495774ad51c26c16ea97cf60798ecb Mon Sep 17 00:00:00 2001 From: TitanMKD Date: Wed, 13 Jun 2012 01:05:49 +0200 Subject: Fix Linker bug copy ROM to RAM & exec from RAM (need more test). --- .../lpc43xx/hackrf-jellybean/jellybean-lpc4330_rom_to_ram.ld | 3 ++- lib/lpc43xx/Makefile | 2 +- lib/lpc43xx/libopencm3_lpc43xx_rom_to_ram.ld | 10 +++++----- lib/lpc43xx/vector.c | 3 +++ 4 files changed, 11 insertions(+), 7 deletions(-) (limited to 'examples/lpc43xx') diff --git a/examples/lpc43xx/hackrf-jellybean/jellybean-lpc4330_rom_to_ram.ld b/examples/lpc43xx/hackrf-jellybean/jellybean-lpc4330_rom_to_ram.ld index 385b081..fb3d8f6 100644 --- a/examples/lpc43xx/hackrf-jellybean/jellybean-lpc4330_rom_to_ram.ld +++ b/examples/lpc43xx/hackrf-jellybean/jellybean-lpc4330_rom_to_ram.ld @@ -28,7 +28,8 @@ MEMORY /* rom is really the shadow region that points to SPI flash or elsewhere */ rom (rx) : ORIGIN = 0x00000000, LENGTH = 1M ram (rwx) : ORIGIN = 0x10000000, LENGTH = 128K - /* there are some additional RAM regions */ + /* there are some additional RAM regions for data */ + ram_data (rw) : ORIGIN = 0x10080000, LENGTH = 72K } /* Include the common ld script. */ diff --git a/lib/lpc43xx/Makefile b/lib/lpc43xx/Makefile index e8bd8fc..91169d4 100644 --- a/lib/lpc43xx/Makefile +++ b/lib/lpc43xx/Makefile @@ -25,7 +25,7 @@ PREFIX ?= arm-none-eabi #PREFIX ?= arm-elf CC = $(PREFIX)-gcc AR = $(PREFIX)-ar -CFLAGS = -O2 -g -Wall -Wextra -I../../include -fno-common \ +CFLAGS = -O2 -g3 -Wall -Wextra -I../../include -fno-common \ -mcpu=cortex-m4 -mthumb -Wstrict-prototypes \ -ffunction-sections -fdata-sections -MD \ -mfloat-abi=hard -mfpu=fpv4-sp-d16 diff --git a/lib/lpc43xx/libopencm3_lpc43xx_rom_to_ram.ld b/lib/lpc43xx/libopencm3_lpc43xx_rom_to_ram.ld index f833aaf..850218b 100644 --- a/lib/lpc43xx/libopencm3_lpc43xx_rom_to_ram.ld +++ b/lib/lpc43xx/libopencm3_lpc43xx_rom_to_ram.ld @@ -56,26 +56,26 @@ SECTIONS _etext_ram = . + ORIGIN(ram); _etext_rom = . + ORIGIN(rom_flash); - . = ORIGIN(ram); - .data : { _data = .; *(.data*) /* Read-write initialized data */ . = ALIGN(4); _edata = .; - } >ram AT >rom + } >ram_data AT >rom .bss : { + . = _edata; *(.bss*) /* Read-write zero initialized data */ *(COMMON) . = ALIGN(4); _ebss = .; - } >ram + } >ram_data /* exception unwind data - required due to libgcc.a issuing /0 exceptions */ .ARM.extab : { + . = _ebss; *(.ARM.extab*) - } >ram + } >ram_data /* * The .eh_frame section appears to be used for C++ exception handling. diff --git a/lib/lpc43xx/vector.c b/lib/lpc43xx/vector.c index 631e54e..daef5a9 100644 --- a/lib/lpc43xx/vector.c +++ b/lib/lpc43xx/vector.c @@ -171,6 +171,9 @@ void reset_handler(void) if( (&_etext_ram-&_text_ram) > 0 ) { src = &_etext_rom-(&_etext_ram-&_text_ram); + /* Change Shadow memory to ROM (for Debug Purpose in case Boot has not set correctly the M4MEMMAP because of debug) */ + CREG_M4MEMMAP = (unsigned long)src; + for(dest = &_text_ram; dest < &_etext_ram; ) { *dest++ = *src++; -- cgit v1.2.3