From 0a66d52ec836b361521652a09c3ebf7cd91fcd0f Mon Sep 17 00:00:00 2001 From: Piotr Esden-Tempski Date: Sun, 2 Oct 2011 01:13:14 -0700 Subject: Switched the makefile default from arm-elf to arm-none-eabi. --- examples/stm32/Makefile.include | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/examples/stm32/Makefile.include b/examples/stm32/Makefile.include index acb78e8..f370f45 100644 --- a/examples/stm32/Makefile.include +++ b/examples/stm32/Makefile.include @@ -18,8 +18,8 @@ ## along with this program. If not, see . ## -# PREFIX ?= arm-none-eabi -PREFIX ?= arm-elf +PREFIX ?= arm-none-eabi +#PREFIX ?= arm-elf CC = $(PREFIX)-gcc LD = $(PREFIX)-gcc OBJCOPY = $(PREFIX)-objcopy -- cgit v1.2.3 From 5d97653163c3ea5148655a875c30cfef4ecbb60d Mon Sep 17 00:00:00 2001 From: Piotr Esden-Tempski Date: Sun, 2 Oct 2011 01:20:44 -0700 Subject: Added black magic probe flashing support to the example code makefile. --- Makefile | 4 ++++ examples/stm32/Makefile.include | 13 +++++++++++++ scripts/black_magic_probe_debug.scr | 4 ++++ scripts/black_magic_probe_flash.scr | 4 ++++ 4 files changed, 25 insertions(+) create mode 100644 scripts/black_magic_probe_debug.scr create mode 100644 scripts/black_magic_probe_flash.scr diff --git a/Makefile b/Makefile index fe8db6a..766073d 100644 --- a/Makefile +++ b/Makefile @@ -22,6 +22,7 @@ PREFIX ?= arm-elf DESTDIR ?= /usr/local INCDIR = $(DESTDIR)/$(PREFIX)/include LIBDIR = $(DESTDIR)/$(PREFIX)/lib +SHAREDIR = $(DESTDIR)/$(PREFIX)/share/libopencm3/scripts INSTALL = install TARGETS = stm32 lpc13xx lm3s @@ -57,11 +58,14 @@ install: lib @printf " INSTALL headers\n" $(Q)$(INSTALL) -d $(INCDIR)/libopencm3 $(Q)$(INSTALL) -d $(LIBDIR) + $(Q)$(INSTALL) -d $(SHAREDIR) $(Q)cp -r include/libopencm3/* $(INCDIR)/libopencm3 @printf " INSTALL libs\n" $(Q)$(INSTALL) -m 0644 lib/*/*.a $(LIBDIR) @printf " INSTALL ldscripts\n" $(Q)$(INSTALL) -m 0644 lib/*/*.ld $(LIBDIR) + @printf " INSTALL scripts\n" + $(Q)$(INSTALL) -m 0644 scripts/* $(SHAREDIR) clean: $(Q)for i in $(addprefix lib/,$(TARGETS)) \ diff --git a/examples/stm32/Makefile.include b/examples/stm32/Makefile.include index f370f45..a4512e9 100644 --- a/examples/stm32/Makefile.include +++ b/examples/stm32/Makefile.include @@ -24,6 +24,7 @@ CC = $(PREFIX)-gcc LD = $(PREFIX)-gcc OBJCOPY = $(PREFIX)-objcopy OBJDUMP = $(PREFIX)-objdump +GDB = $(PREFIX)-gdb # Uncomment this line if you want to use the installed (not local) library. # TOOLCHAIN_DIR = `dirname \`which $(CC)\``/../$(PREFIX) TOOLCHAIN_DIR = ../../../.. @@ -38,6 +39,9 @@ OBJS += $(BINARY).o OOCD ?= openocd OOCD_INTERFACE ?= flossjtag OOCD_BOARD ?= olimex_stm32_h103 +# Black magic probe specific variables +# Set the BMP_PORT to a serial port and then BMP is used for flashing +BMP_PORT ?= # Be silent per default, but 'make V=1' will show all compiler calls. ifneq ($(V),1) @@ -92,6 +96,7 @@ clean: $(Q)rm -f *.srec $(Q)rm -f *.list +ifeq ($(BMP_PORT),) ifeq ($(OOCD_SERIAL),) %.flash: %.hex @printf " FLASH $<\n" @@ -116,6 +121,14 @@ else -c "reset" \ -c "shutdown" $(NULL) endif +else +%.flash: %.elf + @echo " GDB $(*).elf (flash)" + $(Q)$(GDB) --batch \ + -ex 'target extended-remote $(BMP_PORT)' \ + -x $(TOOLCHAIN_DIR)/scripts/black_magic_probe_flash.scr \ + $(*).elf +endif .PHONY: images clean diff --git a/scripts/black_magic_probe_debug.scr b/scripts/black_magic_probe_debug.scr new file mode 100644 index 0000000..0bf774c --- /dev/null +++ b/scripts/black_magic_probe_debug.scr @@ -0,0 +1,4 @@ +monitor version +monitor swdp_scan +attach 1 +run diff --git a/scripts/black_magic_probe_flash.scr b/scripts/black_magic_probe_flash.scr new file mode 100644 index 0000000..27663c8 --- /dev/null +++ b/scripts/black_magic_probe_flash.scr @@ -0,0 +1,4 @@ +monitor version +monitor swdp_scan +attach 1 +load -- cgit v1.2.3 From 03a4a18ed646413125217208e8eed48e1a33f58c Mon Sep 17 00:00:00 2001 From: Piotr Esden-Tempski Date: Tue, 4 Oct 2011 13:06:56 -0700 Subject: Switched all makefiles to arm-none-eabi default. --- Makefile | 4 ++-- examples/lm3s/Makefile.include | 4 ++-- examples/lpc13xx/Makefile.include | 4 ++-- lib/lm3s/Makefile | 4 ++-- lib/lpc13xx/Makefile | 4 ++-- lib/stm32/Makefile | 4 ++-- 6 files changed, 12 insertions(+), 12 deletions(-) diff --git a/Makefile b/Makefile index 766073d..fe06961 100644 --- a/Makefile +++ b/Makefile @@ -17,8 +17,8 @@ ## along with this program. If not, see . ## -# PREFIX ?= arm-none-eabi -PREFIX ?= arm-elf +PREFIX ?= arm-none-eabi +#PREFIX ?= arm-elf DESTDIR ?= /usr/local INCDIR = $(DESTDIR)/$(PREFIX)/include LIBDIR = $(DESTDIR)/$(PREFIX)/lib diff --git a/examples/lm3s/Makefile.include b/examples/lm3s/Makefile.include index 764a145..2424832 100644 --- a/examples/lm3s/Makefile.include +++ b/examples/lm3s/Makefile.include @@ -18,8 +18,8 @@ ## along with this program. If not, see . ## -# PREFIX ?= arm-none-eabi -PREFIX ?= arm-elf +PREFIX ?= arm-none-eabi +#PREFIX ?= arm-elf CC = $(PREFIX)-gcc LD = $(PREFIX)-gcc OBJCOPY = $(PREFIX)-objcopy diff --git a/examples/lpc13xx/Makefile.include b/examples/lpc13xx/Makefile.include index c9ae180..fe2c3ba 100644 --- a/examples/lpc13xx/Makefile.include +++ b/examples/lpc13xx/Makefile.include @@ -18,8 +18,8 @@ ## along with this program. If not, see . ## -# PREFIX ?= arm-none-eabi -PREFIX ?= arm-elf +PREFIX ?= arm-none-eabi +#PREFIX ?= arm-elf CC = $(PREFIX)-gcc LD = $(PREFIX)-gcc OBJCOPY = $(PREFIX)-objcopy diff --git a/lib/lm3s/Makefile b/lib/lm3s/Makefile index 2bdbd72..93a67ad 100644 --- a/lib/lm3s/Makefile +++ b/lib/lm3s/Makefile @@ -19,8 +19,8 @@ LIBNAME = libopencm3_lm3s -# PREFIX ?= arm-none-eabi -PREFIX ?= arm-elf +PREFIX ?= arm-none-eabi +#PREFIX ?= arm-elf CC = $(PREFIX)-gcc AR = $(PREFIX)-ar CFLAGS = -Os -g -Wall -Wextra -I../../include -fno-common \ diff --git a/lib/lpc13xx/Makefile b/lib/lpc13xx/Makefile index 7181a08..04e33c8 100644 --- a/lib/lpc13xx/Makefile +++ b/lib/lpc13xx/Makefile @@ -19,8 +19,8 @@ LIBNAME = libopencm3_lpc13xx -# PREFIX ?= arm-none-eabi -PREFIX ?= arm-elf +PREFIX ?= arm-none-eabi +#PREFIX ?= arm-elf CC = $(PREFIX)-gcc AR = $(PREFIX)-ar CFLAGS = -Os -g -Wall -Wextra -I../../include -fno-common \ diff --git a/lib/stm32/Makefile b/lib/stm32/Makefile index 095f524..5f26c29 100644 --- a/lib/stm32/Makefile +++ b/lib/stm32/Makefile @@ -19,8 +19,8 @@ LIBNAME = libopencm3_stm32 -# PREFIX ?= arm-none-eabi -PREFIX ?= arm-elf +PREFIX ?= arm-none-eabi +#PREFIX ?= arm-elf CC = $(PREFIX)-gcc AR = $(PREFIX)-ar CFLAGS = -Os -g -Wall -Wextra -I../../include -fno-common \ -- cgit v1.2.3 From 9e4522ad21d9489b912e39e5ecac7143e997b8fd Mon Sep 17 00:00:00 2001 From: Piotr Esden-Tempski Date: Tue, 4 Oct 2011 23:53:16 -0700 Subject: Corrected led io for lisa/m v1.1 cleaned up some whitespace. Trying to get it to work... --- examples/stm32/lisa-m/usb_hid/usbhid.c | 70 ++++++++++++++++++---------------- 1 file changed, 37 insertions(+), 33 deletions(-) diff --git a/examples/stm32/lisa-m/usb_hid/usbhid.c b/examples/stm32/lisa-m/usb_hid/usbhid.c index 5314241..414f346 100644 --- a/examples/stm32/lisa-m/usb_hid/usbhid.c +++ b/examples/stm32/lisa-m/usb_hid/usbhid.c @@ -2,6 +2,7 @@ * This file is part of the libopencm3 project. * * Copyright (C) 2010 Gareth McMullin + * Copyright (C) 2011 Piotr Esden-Tempski * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -33,20 +34,20 @@ #endif const struct usb_device_descriptor dev = { - .bLength = USB_DT_DEVICE_SIZE, - .bDescriptorType = USB_DT_DEVICE, - .bcdUSB = 0x0200, - .bDeviceClass = 0, - .bDeviceSubClass = 0, - .bDeviceProtocol = 0, - .bMaxPacketSize0 = 64, - .idVendor = 0x0483, - .idProduct = 0x5710, - .bcdDevice = 0x0200, - .iManufacturer = 1, - .iProduct = 2, - .iSerialNumber = 3, - .bNumConfigurations = 1, + .bLength = USB_DT_DEVICE_SIZE, + .bDescriptorType = USB_DT_DEVICE, + .bcdUSB = 0x0200, + .bDeviceClass = 0, + .bDeviceSubClass = 0, + .bDeviceProtocol = 0, + .bMaxPacketSize0 = 64, + .idVendor = 0x0483, + .idProduct = 0x5710, + .bcdDevice = 0x0200, + .iManufacturer = 1, + .iProduct = 2, + .iSerialNumber = 3, + .bNumConfigurations = 1, }; /* I have no idea what this means. I haven't read the HID spec. */ @@ -174,10 +175,10 @@ static int hid_control_request(struct usb_setup_data *req, u8 **buf, u16 *len, { (void)complete; - if((req->bmRequestType != 0x81) || + if((req->bmRequestType != 0x81) || (req->bRequest != USB_REQ_GET_DESCRIPTOR) || - (req->wValue != 0x2200)) - return 0; + (req->wValue != 0x2200)) + return 0; /* Handle the HID report descriptor */ *buf = (u8*)hid_report_descriptor; @@ -192,7 +193,7 @@ static void dfu_detach_complete(struct usb_setup_data *req) (void)req; gpio_set_mode(GPIOA, GPIO_MODE_INPUT, 0, GPIO15); - gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_2_MHZ, + gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_2_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO10); gpio_set(GPIOA, GPIO10); scb_reset_core(); @@ -201,10 +202,10 @@ static void dfu_detach_complete(struct usb_setup_data *req) static int dfu_control_request(struct usb_setup_data *req, u8 **buf, u16 *len, void (**complete)(struct usb_setup_data *req)) { - (void)buf; + (void)buf; (void)len; - if((req->bmRequestType != 0x21) || (req->bRequest != DFU_DETACH)) + if((req->bmRequestType != 0x21) || (req->bRequest != DFU_DETACH)) return 0; /* Only accept class request */ *complete = dfu_detach_complete; @@ -230,7 +231,7 @@ static void hid_set_config(u16 wValue) dfu_control_request); #endif - systick_set_clocksource(STK_CTRL_CLKSOURCE_AHB_DIV8); + systick_set_clocksource(STK_CTRL_CLKSOURCE_AHB_DIV8); systick_set_reload(100000); systick_interrupt_enable(); systick_counter_enable(); @@ -238,41 +239,44 @@ static void hid_set_config(u16 wValue) int main(void) { - rcc_clock_setup_in_hsi_out_48mhz(); + int usb_connect_blink = 0; + rcc_clock_setup_in_hsi_out_48mhz(); rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); /* USB_DETECT as input */ - gpio_set_mode(GPIOA, GPIO_MODE_INPUT, + gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO8); /* disconnect USB_DISC, as output */ gpio_set(GPIOC, GPIO15); - gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_2_MHZ, + gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_2_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO15); /* green LED off, as output */ - gpio_clear(GPIOC, GPIO13); - gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_2_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO13); + gpio_set(GPIOC, GPIO2); + gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_2_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO2); - usbd_init(&stm32f103_usb_driver, &dev, &config, usb_strings); + usbd_init(&stm32f107_usb_driver, &dev, &config, usb_strings); usbd_register_set_config_callback(hid_set_config); /* delay some seconds to show that pull-up switch works */ - {int i; for (i=0;i<0x800000;i++);} + {int i; for (i=0;i<0x800000;i++) asm("nop");} /* wait for USB Vbus */ - while(gpio_get(GPIOA, GPIO8) == 0); + while(gpio_get(GPIOA, GPIO8) == 0) asm("nop"); /* green LED on, connect USB */ - gpio_set(GPIOC, GPIO13); - gpio_clear(GPIOC, GPIO15); + gpio_clear(GPIOC, GPIO2); + gpio_set_mode(GPIOC, GPIO_MODE_INPUT, + GPIO_CNF_INPUT_FLOAT, GPIO15); + //gpio_clear(GPIOC, GPIO15); - while (1) + while (1) usbd_poll(); } -- cgit v1.2.3 From f9a28a3d5e7438842f64c123ffff2488bdccff4d Mon Sep 17 00:00:00 2001 From: Piotr Esden-Tempski Date: Wed, 5 Oct 2011 13:55:17 -0700 Subject: Changed clock on lisa-m hid example to 72MHz and removed disconnect pin control as the stm32f105 has built in pullups. --- examples/stm32/lisa-m/usb_hid/usbhid.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/examples/stm32/lisa-m/usb_hid/usbhid.c b/examples/stm32/lisa-m/usb_hid/usbhid.c index 414f346..f42454b 100644 --- a/examples/stm32/lisa-m/usb_hid/usbhid.c +++ b/examples/stm32/lisa-m/usb_hid/usbhid.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include @@ -240,7 +241,7 @@ static void hid_set_config(u16 wValue) int main(void) { int usb_connect_blink = 0; - rcc_clock_setup_in_hsi_out_48mhz(); + rcc_clock_setup_in_hse_12mhz_out_72mhz(); rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); @@ -250,11 +251,6 @@ int main(void) gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO8); - /* disconnect USB_DISC, as output */ - gpio_set(GPIOC, GPIO15); - gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_2_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO15); - /* green LED off, as output */ gpio_set(GPIOC, GPIO2); gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_2_MHZ, @@ -272,9 +268,7 @@ int main(void) /* green LED on, connect USB */ gpio_clear(GPIOC, GPIO2); - gpio_set_mode(GPIOC, GPIO_MODE_INPUT, - GPIO_CNF_INPUT_FLOAT, GPIO15); - //gpio_clear(GPIOC, GPIO15); + //OTG_FS_GCCFG &= ~OTG_FS_GCCFG_VBUSBSEN; while (1) usbd_poll(); -- cgit v1.2.3 From cbf6b8e54b526ef9c104bd9e3d9ae2e6fe3829c8 Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Fri, 9 Sep 2011 10:20:23 -0700 Subject: Update examples Makefiles to use the make shell function rather than backticks for shell command expansion. Backticks are unreliable and don't work on all platforms. --- examples/lm3s/Makefile.include | 2 +- examples/lpc13xx/Makefile.include | 2 +- examples/stm32/Makefile.include | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/examples/lm3s/Makefile.include b/examples/lm3s/Makefile.include index 2424832..0eafe7d 100644 --- a/examples/lm3s/Makefile.include +++ b/examples/lm3s/Makefile.include @@ -25,7 +25,7 @@ LD = $(PREFIX)-gcc OBJCOPY = $(PREFIX)-objcopy OBJDUMP = $(PREFIX)-objdump # Uncomment this line if you want to use the installed (not local) library. -# TOOLCHAIN_DIR = `dirname \`which $(CC)\``/../$(PREFIX) +# TOOLCHAIN_DIR := $(shell dirname `which $(CC)`)/../$(PREFIX) TOOLCHAIN_DIR = ../../../.. CFLAGS += -O0 -g3 -Wall -Wextra -I$(TOOLCHAIN_DIR)/include -fno-common \ -mcpu=cortex-m3 -mthumb -MD diff --git a/examples/lpc13xx/Makefile.include b/examples/lpc13xx/Makefile.include index fe2c3ba..948d6c4 100644 --- a/examples/lpc13xx/Makefile.include +++ b/examples/lpc13xx/Makefile.include @@ -25,7 +25,7 @@ LD = $(PREFIX)-gcc OBJCOPY = $(PREFIX)-objcopy OBJDUMP = $(PREFIX)-objdump # Uncomment this line if you want to use the installed (not local) library. -# TOOLCHAIN_DIR = `dirname \`which $(CC)\``/../$(PREFIX) +# TOOLCHAIN_DIR := $(shell dirname `which $(CC)`)/../$(PREFIX) TOOLCHAIN_DIR = ../../../.. CFLAGS += -Os -g -Wall -Wextra -I$(TOOLCHAIN_DIR)/include -fno-common \ -mcpu=cortex-m3 -mthumb -MD diff --git a/examples/stm32/Makefile.include b/examples/stm32/Makefile.include index a4512e9..3e30638 100644 --- a/examples/stm32/Makefile.include +++ b/examples/stm32/Makefile.include @@ -26,7 +26,7 @@ OBJCOPY = $(PREFIX)-objcopy OBJDUMP = $(PREFIX)-objdump GDB = $(PREFIX)-gdb # Uncomment this line if you want to use the installed (not local) library. -# TOOLCHAIN_DIR = `dirname \`which $(CC)\``/../$(PREFIX) +# TOOLCHAIN_DIR := $(shell dirname `which $(CC)`)/../$(PREFIX) TOOLCHAIN_DIR = ../../../.. CFLAGS += -Os -g -Wall -Wextra -I$(TOOLCHAIN_DIR)/include \ -fno-common -mcpu=cortex-m3 -mthumb -msoft-float -MD -- cgit v1.2.3 From 5ba3e77246fece4883381b6db00974fd1a0c2c34 Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Mon, 12 Sep 2011 18:05:41 -0700 Subject: Adding memory map for the stm32f2 series. --- include/libopencm3/stm32f2/memorymap.h | 131 +++++++++++++++++++++++++++++++++ 1 file changed, 131 insertions(+) create mode 100644 include/libopencm3/stm32f2/memorymap.h diff --git a/include/libopencm3/stm32f2/memorymap.h b/include/libopencm3/stm32f2/memorymap.h new file mode 100644 index 0000000..9fe77fa --- /dev/null +++ b/include/libopencm3/stm32f2/memorymap.h @@ -0,0 +1,131 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Fergus Noble + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_MEMORYMAP_H +#define LIBOPENCM3_MEMORYMAP_H + +#include + +/* --- STM32F20x specific peripheral definitions ------------------------------- */ + +/* Memory map for all busses */ +#define PERIPH_BASE 0x40000000 +#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000) +#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000) +#define PERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000) +#define PERIPH_BASE_AHB2 0x50000000 +#define PERIPH_BASE_AHB3 0x60000000 + +/* Register boundary addresses */ + +/* APB1 */ +#define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000) +#define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400) +#define TIM4_BASE (PERIPH_BASE_APB1 + 0x0800) +#define TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00) +#define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000) +#define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400) +#define TIM12_BASE (PERIPH_BASE_APB1 + 0x1800) +#define TIM13_BASE (PERIPH_BASE_APB1 + 0x1c00) +#define TIM14_BASE (PERIPH_BASE_APB1 + 0x2000) +/* PERIPH_BASE_APB1 + 0x2400 (0x4000 2400 - 0x4000 27FF): Reserved */ +#define RTC_BASE (PERIPH_BASE_APB1 + 0x2800) +#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00) +#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000) +/* PERIPH_BASE_APB1 + 0x3400 (0x4000 3400 - 0x4000 37FF): Reserved */ +#define SPI2_I2S_BASE (PERIPH_BASE_APB1 + 0x3800) +#define SPI3_I2S_BASE (PERIPH_BASE_APB1 + 0x3c00) +/* PERIPH_BASE_APB1 + 0x4000 (0x4000 4000 - 0x4000 3FFF): Reserved */ +#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400) +#define USART3_BASE (PERIPH_BASE_APB1 + 0x4800) +#define UART4_BASE (PERIPH_BASE_APB1 + 0x4c00) +#define UART5_BASE (PERIPH_BASE_APB1 + 0x5000) +#define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400) +#define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800) +#define I2C3_BASE (PERIPH_BASE_APB1 + 0x5C00) +/* PERIPH_BASE_APB1 + 0x6000 (0x4000 6000 - 0x4000 63FF): Reserved */ +#define BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400) +#define BX_CAN2_BASE (PERIPH_BASE_APB1 + 0x6800) +/* PERIPH_BASE_APB1 + 0x6C00 (0x4000 6C00 - 0x4000 6FFF): Reserved */ +#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000) +#define DAC_BASE (PERIPH_BASE_APB1 + 0x7400) +/* PERIPH_BASE_APB1 + 0x7800 (0x4000 7800 - 0x4000 FFFF): Reserved */ + +/* APB2 */ +#define TIM1_BASE (PERIPH_BASE_APB2 + 0x0000) +#define TIM8_BASE (PERIPH_BASE_APB2 + 0x0400) +/* PERIPH_BASE_APB2 + 0x0800 (0x4001 0800 - 0x4001 0FFF): Reserved */ +#define USART1_BASE (PERIPH_BASE_APB2 + 0x1000) +#define USART6_BASE (PERIPH_BASE_APB2 + 0x1400) +/* PERIPH_BASE_APB2 + 0x1800 (0x4001 1800 - 0x4001 1FFF): Reserved */ +#define ADC1_BASE (PERIPH_BASE_APB2 + 0x2000) +#define ADC2_BASE (PERIPH_BASE_APB2 + 0x2000) +#define ADC3_BASE (PERIPH_BASE_APB2 + 0x2000) +/* PERIPH_BASE_APB2 + 0x2400 (0x4001 2400 - 0x4001 27FF): Reserved */ +#define SDIO_BASE (PERIPH_BASE_APB2 + 0x2800) +/* PERIPH_BASE_APB2 + 0x2C00 (0x4001 2C00 - 0x4001 2FFF): Reserved */ +#define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000) +/* PERIPH_BASE_APB2 + 0x3400 (0x4001 3400 - 0x4001 37FF): Reserved */ +#define SYSCFG_BASE (PERIPH_BASE_APB2 + 0x3800) +#define EXTI_BASE (PERIPH_BASE_APB2 + 0x3C00) +#define TIM9_BASE (PERIPH_BASE_APB2 + 0x4000) +#define TIM10_BASE (PERIPH_BASE_APB2 + 0x4400) +#define TIM11_BASE (PERIPH_BASE_APB2 + 0x4800) +/* PERIPH_BASE_APB2 + 0x4C00 (0x4001 4C00 - 0x4001 FFFF): Reserved */ + +/* AHB1 */ +#define GPIO_PORT_A_BASE (PERIPH_BASE_AHB1 + 0x0000) +#define GPIO_PORT_B_BASE (PERIPH_BASE_AHB1 + 0x0400) +#define GPIO_PORT_C_BASE (PERIPH_BASE_AHB1 + 0x0800) +#define GPIO_PORT_D_BASE (PERIPH_BASE_AHB1 + 0x0C00) +#define GPIO_PORT_E_BASE (PERIPH_BASE_AHB1 + 0x1000) +#define GPIO_PORT_F_BASE (PERIPH_BASE_AHB1 + 0x1400) +#define GPIO_PORT_G_BASE (PERIPH_BASE_AHB1 + 0x1800) +#define GPIO_PORT_H_BASE (PERIPH_BASE_AHB1 + 0x1C00) +#define GPIO_PORT_I_BASE (PERIPH_BASE_AHB1 + 0x2000) +/* PERIPH_BASE_AHB1 + 0x2400 (0x4002 2400 - 0x4002 2FFF): Reserved */ +#define CRC_BASE (PERIPH_BASE_AHB1 + 0x3000) +/* PERIPH_BASE_AHB1 + 0x3400 (0x4002 3400 - 0x4002 37FF): Reserved */ +#define RCC_BASE (PERIPH_BASE_AHB1 + 0x3800) +#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x3C00) +#define BKPSRAM_BASE (PERIPH_BASE_AHB1 + 0x4000) +/* PERIPH_BASE_AHB1 + 0x5000 (0x4002 5000 - 0x4002 5FFF): Reserved */ +#define DMA1_BASE (PERIPH_BASE_AHB1 + 0x6000) +#define DMA2_BASE (PERIPH_BASE_AHB1 + 0x6400) +/* PERIPH_BASE_AHB1 + 0x6800 (0x4002 6800 - 0x4002 7FFF): Reserved */ +#define ETHERNET_BASE (PERIPH_BASE_AHB1 + 0x8000) +/* PERIPH_BASE_AHB1 + 0x9400 (0x4002 9400 - 0x4003 FFFF): Reserved */ +#define USB_OTG_HS_BASE (PERIPH_BASE_AHB1 + 0x20000) +/* PERIPH_BASE_AHB1 + 0x60000 (0x4008 0000 - 0x4FFF FFFF): Reserved */ + +/* AHB2 */ +#define USB_OTG_FS_BASE (PERIPH_BASE_AHB2 + 0x0000) +/* PERIPH_BASE_AHB2 + 0x40000 (0x5004 0000 - 0x5004 FFFF): Reserved */ +#define DCMI_BASE (PERIPH_BASE_AHB2 + 0x50000) +/* PERIPH_BASE_AHB2 + 0x50400 (0x5005 0400 - 0x5006 07FF): Reserved */ +#define RNG_BASE (PERIPH_BASE_AHB2 + 0x60800) +/* PERIPH_BASE_AHB2 + 0x61000 (0x5006 1000 - 0x5FFF FFFF): Reserved */ + +/* AHB3 */ +#define FSMC_BASE (PERIPH_BASE_AHB3 + 0x40000000) + +/* PPIB */ +#define DBGMCU_BASE (PPBI_BASE + 0x00042000) + +#endif -- cgit v1.2.3 From 18648708c887e24a1e30a37b133aad15b284a21d Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Mon, 12 Sep 2011 18:09:10 -0700 Subject: Moving renaming stm32 header files for f1 series. --- include/libopencm3/stm32/adc.h | 418 --------------- include/libopencm3/stm32/bkp.h | 208 -------- include/libopencm3/stm32/can.h | 642 ----------------------- include/libopencm3/stm32/crc.h | 52 -- include/libopencm3/stm32/dbgmcu.h | 60 --- include/libopencm3/stm32/dma.h | 723 -------------------------- include/libopencm3/stm32/ethernet.h | 203 -------- include/libopencm3/stm32/exti.h | 70 --- include/libopencm3/stm32/flash.h | 113 ---- include/libopencm3/stm32/fsmc.h | 284 ---------- include/libopencm3/stm32/gpio.h | 555 -------------------- include/libopencm3/stm32/i2c.h | 333 ------------ include/libopencm3/stm32/iwdg.h | 75 --- include/libopencm3/stm32/memorymap.h | 113 ---- include/libopencm3/stm32/nvic.h | 162 ------ include/libopencm3/stm32/otg_fs.h | 324 ------------ include/libopencm3/stm32/pwr.h | 81 --- include/libopencm3/stm32/rcc.h | 417 --------------- include/libopencm3/stm32/rtc.h | 146 ------ include/libopencm3/stm32/scb.h | 300 ----------- include/libopencm3/stm32/spi.h | 331 ------------ include/libopencm3/stm32/systick.h | 82 --- include/libopencm3/stm32/timer.h | 921 --------------------------------- include/libopencm3/stm32/tools.h | 64 --- include/libopencm3/stm32/usart.h | 312 ----------- include/libopencm3/stm32/usb.h | 258 --------- include/libopencm3/stm32/usb_desc.h | 101 ---- include/libopencm3/stm32/wwdg.h | 74 --- include/libopencm3/stm32f1/adc.h | 418 +++++++++++++++ include/libopencm3/stm32f1/bkp.h | 208 ++++++++ include/libopencm3/stm32f1/can.h | 642 +++++++++++++++++++++++ include/libopencm3/stm32f1/crc.h | 52 ++ include/libopencm3/stm32f1/dbgmcu.h | 60 +++ include/libopencm3/stm32f1/dma.h | 723 ++++++++++++++++++++++++++ include/libopencm3/stm32f1/ethernet.h | 203 ++++++++ include/libopencm3/stm32f1/exti.h | 70 +++ include/libopencm3/stm32f1/flash.h | 113 ++++ include/libopencm3/stm32f1/fsmc.h | 284 ++++++++++ include/libopencm3/stm32f1/gpio.h | 555 ++++++++++++++++++++ include/libopencm3/stm32f1/i2c.h | 333 ++++++++++++ include/libopencm3/stm32f1/iwdg.h | 75 +++ include/libopencm3/stm32f1/memorymap.h | 113 ++++ include/libopencm3/stm32f1/nvic.h | 162 ++++++ include/libopencm3/stm32f1/otg_fs.h | 324 ++++++++++++ include/libopencm3/stm32f1/pwr.h | 81 +++ include/libopencm3/stm32f1/rcc.h | 417 +++++++++++++++ include/libopencm3/stm32f1/rtc.h | 146 ++++++ include/libopencm3/stm32f1/scb.h | 300 +++++++++++ include/libopencm3/stm32f1/spi.h | 331 ++++++++++++ include/libopencm3/stm32f1/systick.h | 82 +++ include/libopencm3/stm32f1/timer.h | 921 +++++++++++++++++++++++++++++++++ include/libopencm3/stm32f1/tools.h | 64 +++ include/libopencm3/stm32f1/usart.h | 312 +++++++++++ include/libopencm3/stm32f1/usb.h | 258 +++++++++ include/libopencm3/stm32f1/usb_desc.h | 101 ++++ include/libopencm3/stm32f1/wwdg.h | 74 +++ 56 files changed, 7422 insertions(+), 7422 deletions(-) delete mode 100644 include/libopencm3/stm32/adc.h delete mode 100644 include/libopencm3/stm32/bkp.h delete mode 100644 include/libopencm3/stm32/can.h delete mode 100644 include/libopencm3/stm32/crc.h delete mode 100644 include/libopencm3/stm32/dbgmcu.h delete mode 100644 include/libopencm3/stm32/dma.h delete mode 100644 include/libopencm3/stm32/ethernet.h delete mode 100644 include/libopencm3/stm32/exti.h delete mode 100644 include/libopencm3/stm32/flash.h delete mode 100644 include/libopencm3/stm32/fsmc.h delete mode 100644 include/libopencm3/stm32/gpio.h delete mode 100644 include/libopencm3/stm32/i2c.h delete mode 100644 include/libopencm3/stm32/iwdg.h delete mode 100644 include/libopencm3/stm32/memorymap.h delete mode 100644 include/libopencm3/stm32/nvic.h delete mode 100644 include/libopencm3/stm32/otg_fs.h delete mode 100644 include/libopencm3/stm32/pwr.h delete mode 100644 include/libopencm3/stm32/rcc.h delete mode 100644 include/libopencm3/stm32/rtc.h delete mode 100644 include/libopencm3/stm32/scb.h delete mode 100644 include/libopencm3/stm32/spi.h delete mode 100644 include/libopencm3/stm32/systick.h delete mode 100644 include/libopencm3/stm32/timer.h delete mode 100644 include/libopencm3/stm32/tools.h delete mode 100644 include/libopencm3/stm32/usart.h delete mode 100644 include/libopencm3/stm32/usb.h delete mode 100644 include/libopencm3/stm32/usb_desc.h delete mode 100644 include/libopencm3/stm32/wwdg.h create mode 100644 include/libopencm3/stm32f1/adc.h create mode 100644 include/libopencm3/stm32f1/bkp.h create mode 100644 include/libopencm3/stm32f1/can.h create mode 100644 include/libopencm3/stm32f1/crc.h create mode 100644 include/libopencm3/stm32f1/dbgmcu.h create mode 100644 include/libopencm3/stm32f1/dma.h create mode 100644 include/libopencm3/stm32f1/ethernet.h create mode 100644 include/libopencm3/stm32f1/exti.h create mode 100644 include/libopencm3/stm32f1/flash.h create mode 100644 include/libopencm3/stm32f1/fsmc.h create mode 100644 include/libopencm3/stm32f1/gpio.h create mode 100644 include/libopencm3/stm32f1/i2c.h create mode 100644 include/libopencm3/stm32f1/iwdg.h create mode 100644 include/libopencm3/stm32f1/memorymap.h create mode 100644 include/libopencm3/stm32f1/nvic.h create mode 100644 include/libopencm3/stm32f1/otg_fs.h create mode 100644 include/libopencm3/stm32f1/pwr.h create mode 100644 include/libopencm3/stm32f1/rcc.h create mode 100644 include/libopencm3/stm32f1/rtc.h create mode 100644 include/libopencm3/stm32f1/scb.h create mode 100644 include/libopencm3/stm32f1/spi.h create mode 100644 include/libopencm3/stm32f1/systick.h create mode 100644 include/libopencm3/stm32f1/timer.h create mode 100644 include/libopencm3/stm32f1/tools.h create mode 100644 include/libopencm3/stm32f1/usart.h create mode 100644 include/libopencm3/stm32f1/usb.h create mode 100644 include/libopencm3/stm32f1/usb_desc.h create mode 100644 include/libopencm3/stm32f1/wwdg.h diff --git a/include/libopencm3/stm32/adc.h b/include/libopencm3/stm32/adc.h deleted file mode 100644 index 6e35d59..0000000 --- a/include/libopencm3/stm32/adc.h +++ /dev/null @@ -1,418 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Edward Cheeseman - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_ADC_H -#define LIBOPENCM3_ADC_H - -#include -#include - -/* --- Convenience macros -------------------------------------------------- */ - -/* ADC port base addresses (for convenience) */ -#define ADC1 ADC1_BASE -#define ADC2 ADC2_BASE -#define ADC3 ADC3_BASE - -/* --- ADC registers ------------------------------------------------------- */ - -/* ADC status register (ADC_SR) */ -#define ADC_SR(block) MMIO32(block + 0x00) -#define ADC1_SR ADC_SR(ADC1) -#define ADC2_SR ADC_SR(ADC2) -#define ADC3_SR ADC_SR(ADC3) - -/* ADC control register 1 (ADC_CR1) */ -#define ADC_CR1(block) MMIO32(block + 0x04) -#define ADC1_CR1 ADC_CR1(ADC1) -#define ADC2_CR1 ADC_CR1(ADC2) -#define ADC3_CR1 ADC_CR1(ADC3) - -/* ADC control register 2 (ADC_CR2) */ -#define ADC_CR2(block) MMIO32(block + 0x08) -#define ADC1_CR2 ADC_CR2(ADC1) -#define ADC2_CR2 ADC_CR2(ADC2) -#define ADC3_CR2 ADC_CR2(ADC3) - -/* ADC sample time register 1 (ADC_SMPR1) */ -#define ADC_SMPR1(block) MMIO32(block + 0x0c) -#define ADC1_SMPR1 ADC_SMPR1(ADC1) -#define ADC2_SMPR1 ADC_SMPR1(ADC2) -#define ADC3_SMPR1 ADC_SMPR1(ADC3) - -/* ADC sample time register 2 (ADC_SMPR2) */ -#define ADC_SMPR2(block) MMIO32(block + 0x10) -#define ADC1_SMPR2 ADC_SMPR2(ADC1) -#define ADC2_SMPR2 ADC_SMPR2(ADC2) -#define ADC3_SMPR2 ADC_SMPR2(ADC3) - -/* ADC injected channel data offset register x (ADC_JOFRx) (x=1..4) */ -#define ADC_JOFR1(block) MMIO32(block + 0x14) -#define ADC_JOFR2(block) MMIO32(block + 0x18) -#define ADC_JOFR3(block) MMIO32(block + 0x1c) -#define ADC_JOFR4(block) MMIO32(block + 0x20) -#define ADC1_JOFR1 ADC_JOFR1(ADC1) -#define ADC2_JOFR1 ADC_JOFR1(ADC2) -#define ADC3_JOFR1 ADC_JOFR1(ADC3) -#define ADC1_JOFR2 ADC_JOFR2(ADC1) -#define ADC2_JOFR2 ADC_JOFR2(ADC2) -#define ADC3_JOFR2 ADC_JOFR2(ADC3) -#define ADC1_JOFR3 ADC_JOFR3(ADC1) -#define ADC2_JOFR3 ADC_JOFR3(ADC2) -#define ADC3_JOFR3 ADC_JOFR3(ADC3) -#define ADC1_JOFR4 ADC_JOFR4(ADC1) -#define ADC2_JOFR4 ADC_JOFR4(ADC2) -#define ADC3_JOFR4 ADC_JOFR4(ADC3) - -/* ADC watchdog high threshold register (ADC_HTR) */ -#define ADC_HTR(block) MMIO32(block + 0x24) -#define ADC1_HTR ADC_HTR(ADC1) -#define ADC2_HTR ADC_HTR(ADC2) -#define ADC3_HTR ADC_HTR(ADC3) - -/* ADC watchdog low threshold register (ADC_LTR) */ -#define ADC_LTR(block) MMIO32(block + 0x28) -#define ADC1_LTR ADC_LTR(ADC1_BASE) -#define ADC2_LTR ADC_LTR(ADC2_BASE) -#define ADC3_LTR ADC_LTR(ADC3_BASE) - -/* ADC regular sequence register 1 (ADC_SQR1) */ -#define ADC_SQR1(block) MMIO32(block + 0x2c) -#define ADC1_SQR1 ADC_SQR1(ADC1) -#define ADC2_SQR1 ADC_SQR1(ADC2) -#define ADC3_SQR1 ADC_SQR1(ADC3) - -/* ADC regular sequence register 2 (ADC_SQR2) */ -#define ADC_SQR2(block) MMIO32(block + 0x30) -#define ADC1_SQR2 ADC_SQR2(ADC1) -#define ADC2_SQR2 ADC_SQR2(ADC2) -#define ADC3_SQR2 ADC_SQR2(ADC3) - -/* ADC regular sequence register 3 (ADC_SQR3) */ -#define ADC_SQR3(block) MMIO32(block + 0x34) -#define ADC1_SQR3 ADC_SQR3(ADC1) -#define ADC2_SQR3 ADC_SQR3(ADC2) -#define ADC3_SQR3 ADC_SQR3(ADC3) - -/* ADC injected sequence register (ADC_JSQR) */ -#define ADC_JSQR(block) MMIO32(block + 0x38) -#define ADC1_JSQR ADC_JSQR(ADC1_BASE) -#define ADC2_JSQR ADC_JSQR(ADC2_BASE) -#define ADC3_JSQR ADC_JSQR(ADC3_BASE) - -/* ADC injected data register x (ADC_JDRx) (x=1..4) */ -#define ADC_JDR1(block) MMIO32(block + 0x3c) -#define ADC_JDR2(block) MMIO32(block + 0x40) -#define ADC_JDR3(block) MMIO32(block + 0x44) -#define ADC_JDR4(block) MMIO32(block + 0x48) -#define ADC1_JDR1 ADC_JDR1(ADC1) -#define ADC2_JDR1 ADC_JDR1(ADC2) -#define ADC3_JDR1 ADC_JDR1(ADC3) -#define ADC1_JDR2 ADC_JDR2(ADC1) -#define ADC2_JDR2 ADC_JDR2(ADC2) -#define ADC3_JDR2 ADC_JDR2(ADC3) -#define ADC1_JDR3 ADC_JDR3(ADC1) -#define ADC2_JDR3 ADC_JDR3(ADC2) -#define ADC3_JDR3 ADC_JDR3(ADC3) -#define ADC1_JDR4 ADC_JDR4(ADC1) -#define ADC2_JDR4 ADC_JDR4(ADC2) -#define ADC3_JDR4 ADC_JDR4(ADC3) - -/* ADC regular data register (ADC_DR) */ -#define ADC_DR(block) MMIO32(block + 0x4c) -#define ADC1_DR ADC_DR(ADC1) -#define ADC2_DR ADC_DR(ADC2) -#define ADC3_DR ADC_DR(ADC3) - -/* --- ADC_SR values ------------------------------------------------------- */ - -#define ADC_SR_STRT (1 << 4) -#define ADC_SR_JSTRT (1 << 3) -#define ADC_SR_JEOC (1 << 2) -#define ADC_SR_EOC (1 << 1) -#define ADC_SR_AWD (1 << 0) - -/* --- ADC_CR1 values ------------------------------------------------------ */ - -#define ADC_CR1_AWDEN (1 << 23) -#define ADC_CR1_JAWDEN (1 << 22) -#define ADC_CR1_DUALMOD_LSB 16 -#define ADC_CR1_DUALMOD_MSK (0xf << ADC_DUALMOD_LSB) /* ADC1 only */ -#define ADC_CR1_DISCNUM_LSB 13 -#define ADC_CR1_DISCNUM_MSK (0x7 << ADC_DISCNUM_LSB) -#define ADC_CR1_JDISCEN (1 << 12) -#define ADC_CR1_DISCEN (1 << 11) -#define ADC_CR1_JAUTO (1 << 10) -#define ADC_CR1_AWDSGL (1 << 9) -#define ADC_CR1_SCAN (1 << 8) -#define ADC_CR1_JEOCIE (1 << 7) -#define ADC_CR1_AWDIE (1 << 6) -#define ADC_CR1_EOCIE (1 << 5) -#define ADC_CR1_AWDCH_LSB 0 -#define ADC_CR1_AWDCH_MSK (0x1f << ADC_AWDCH_LSB) - -/* --- ADC_CR2 values ------------------------------------------------------ */ - -#define ADC_CR2_TSVREFE (1 << 23) /* ADC1 only! */ -#define ADC_CR2_SWSTART (1 << 22) -#define ADC_CR2_JSWSTART (1 << 21) -#define ADC_CR2_EXTTRIG (1 << 20) -#define ADC_CR2_EXTSEL_LSB 17 -#define ADC_CR2_EXTSEL_MSK (0x7 << ADC_EXTSEL_LSB) -/* The following are only valid for ADC1 and ADC2. */ -#define ADC_CR2_EXTSEL_TIM1_CC1 0x0 -#define ADC_CR2_EXTSEL_TIM1_CC2 0x1 -#define ADC_CR2_EXTSEL_TIM1_CC3 0x2 -#define ADC_CR2_EXTSEL_TIM2_CC2 0x3 -#define ADC_CR2_EXTSEL_TIM3_TRGO 0x4 -#define ADC_CR2_EXTSEL_TIM4_CC4 0x5 -#define ADC_CR2_EXTSEL_EXTI11 0x6 -#define ADC_CR2_EXTSEL_SWSTART 0x7 - -/* The following are only valid for ADC3 */ -#define ADC_CR2_EXTSEL_TIM3_CC1 0x0 -#define ADC_CR2_EXTSEL_TIM2_CC3 0x1 -#define ADC_CR2_EXTSEL_TIM8_CC1 0x3 -#define ADC_CR2_EXTSEL_TIM8_TRGO 0x4 -#define ADC_CR2_EXTSEL_TIM5_CC1 0x5 -#define ADC_CR2_EXTSEL_TIM5_CC3 0x6 - -/* Bit 16: reserved, must be kept cleared */ -#define ADC_CR2_JEXTTRIG (1 << 15) -#define ADC_CR2_JEXTSEL_LSB 12 -#define ADC_CR2_JEXTSEL_MSK (0x7 << ADC_JEXTSEL_LSB) -/* The following are only valid for ADC1 and ADC2. */ -#define ADC_CR2_JEXTSEL_TIM1_TRGO 0x0 -#define ADC_CR2_JEXTSEL_TIM1_CC4 0x1 -#define ADC_CR2_JEXTSEL_TIM2_TRGO 0x2 -#define ADC_CR2_JEXTSEL_TIM2_CC1 0x3 -#define ADC_CR2_JEXTSEL_TIM3_CC4 0x4 -#define ADC_CR2_JEXTSEL_TIM4_TRGO 0x5 -#define ADC_CR2_JEXTSEL_EXTI15 0x6 -#define ADC_CR2_JEXTSEL_JSWSTART 0x7 - -/* The following are the different meanings for ADC3 only. */ -#define ADC_CR2_JEXTSEL_TIM4_CC3 0x2 -#define ADC_CR2_JEXTSEL_TIM8_CC2 0x3 -#define ADC_CR2_JEXTSEL_TIM8_CC4 0x4 -#define ADC_CR2_JEXTSEL_TIM5_TRGO 0x5 -#define ADC_CR2_JEXTSEL_TIM5_CC4 0x6 - -#define ADC_CR2_ALIGN (1 << 11) -#define ADC_CR2_DMA (1 << 8) /* ADC 1 & 3 only! */ -/* Bits [7:4] have to be kept 0. */ -#define ADC_CR2_RSTCAL (1 << 3) -#define ADC_CR2_CAL (1 << 2) -#define ADC_CR2_CONT (1 << 1) -#define ADC_CR2_ADON (1 << 0) /* Must be separately written. */ - -/* --- ADC_SMPR1 values ---------------------------------------------------- */ - -#define ADC_SMPR1_SMP17_LSB 21 -#define ADC_SMPR1_SMP16_LSB 18 -#define ADC_SMPR1_SMP15_LSB 15 -#define ADC_SMPR1_SMP14_LSB 12 -#define ADC_SMPR1_SMP13_LSB 9 -#define ADC_SMPR1_SMP12_LSB 6 -#define ADC_SMPR1_SMP11_LSB 3 -#define ADC_SMPR1_SMP10_LSB 0 -#define ADC_SMPR1_SMP17_MSK (0x7 << ADC_SMP17_LSB) -#define ADC_SMPR1_SMP16_MSK (0x7 << ADC_SMP16_LSB) -#define ADC_SMPR1_SMP15_MSK (0x7 << ADC_SMP15_LSB) -#define ADC_SMPR1_SMP14_MSK (0x7 << ADC_SMP14_LSB) -#define ADC_SMPR1_SMP13_MSK (0x7 << ADC_SMP13_LSB) -#define ADC_SMPR1_SMP12_MSK (0x7 << ADC_SMP12_LSB) -#define ADC_SMPR1_SMP11_MSK (0x7 << ADC_SMP11_LSB) -#define ADC_SMPR1_SMP10_MSK (0x7 << ADC_SMP10_LSB) -#define ADC_SMPR1_SMP_1DOT5CYC 0x0 -#define ADC_SMPR1_SMP_7DOT5CYC 0x1 -#define ADC_SMPR1_SMP_13DOT5CYC 0x2 -#define ADC_SMPR1_SMP_28DOT5CYC 0x3 -#define ADC_SMPR1_SMP_41DOT5CYC 0x4 -#define ADC_SMPR1_SMP_55DOT5CYC 0x5 -#define ADC_SMPR1_SMP_71DOT5CYC 0x6 -#define ADC_SMPR1_SMP_239DOT5CYC 0x7 - -/* --- ADC_SMPR2 values ---------------------------------------------------- */ - -#define ADC_SMPR2_SMP9_LSB 27 -#define ADC_SMPR2_SMP8_LSB 24 -#define ADC_SMPR2_SMP7_LSB 21 -#define ADC_SMPR2_SMP6_LSB 18 -#define ADC_SMPR2_SMP5_LSB 15 -#define ADC_SMPR2_SMP4_LSB 12 -#define ADC_SMPR2_SMP3_LSB 9 -#define ADC_SMPR2_SMP2_LSB 6 -#define ADC_SMPR2_SMP1_LSB 3 -#define ADC_SMPR2_SMP0_LSB 0 -#define ADC_SMPR2_SMP9_MSK (0x7 << ADC_SMP9_LSB) -#define ADC_SMPR2_SMP8_MSK (0x7 << ADC_SMP8_LSB) -#define ADC_SMPR2_SMP7_MSK (0x7 << ADC_SMP7_LSB) -#define ADC_SMPR2_SMP6_MSK (0x7 << ADC_SMP6_LSB) -#define ADC_SMPR2_SMP5_MSK (0x7 << ADC_SMP5_LSB) -#define ADC_SMPR2_SMP4_MSK (0x7 << ADC_SMP4_LSB) -#define ADC_SMPR2_SMP3_MSK (0x7 << ADC_SMP3_LSB) -#define ADC_SMPR2_SMP2_MSK (0x7 << ADC_SMP2_LSB) -#define ADC_SMPR2_SMP1_MSK (0x7 << ADC_SMP1_LSB) -#define ADC_SMPR2_SMP0_MSK (0x7 << ADC_SMP0_LSB) -#define ADC_SMPR2_SMP_1DOT5CYC 0x0 -#define ADC_SMPR2_SMP_7DOT5CYC 0x1 -#define ADC_SMPR2_SMP_13DOT5CYC 0x2 -#define ADC_SMPR2_SMP_28DOT5CYC 0x3 -#define ADC_SMPR2_SMP_41DOT5CYC 0x4 -#define ADC_SMPR2_SMP_55DOT5CYC 0x5 -#define ADC_SMPR2_SMP_71DOT5CYC 0x6 -#define ADC_SMPR2_SMP_239DOT5CYC 0x7 - -/* --- ADC_SMPRx generic values -------------------------------------------- */ - -#define ADC_SMPR_SMP_1DOT5CYC 0x0 -#define ADC_SMPR_SMP_7DOT5CYC 0x1 -#define ADC_SMPR_SMP_13DOT5CYC 0x2 -#define ADC_SMPR_SMP_28DOT5CYC 0x3 -#define ADC_SMPR_SMP_41DOT5CYC 0x4 -#define ADC_SMPR_SMP_55DOT5CYC 0x5 -#define ADC_SMPR_SMP_71DOT5CYC 0x6 -#define ADC_SMPR_SMP_239DOT5CYC 0x7 - -/* --- ADC_JOFRx, ADC_HTR, ADC_LTR values ---------------------------------- */ - -#define ADC_JOFFSET_LSB 0 -#define ADC_JOFFSET_MSK (0x7ff << 0) -#define ADC_HT_LSB 0 -#define ADC_HT_MSK (0x7ff << 0) -#define ADC_LT_LSB 0 -#define ADC_LT_MSK (0x7ff << 0) - -/* --- ADC_SQR1 values ----------------------------------------------------- */ - -#define ADC_SQR1_L_LSB 20 -#define ADC_SQR1_SQ16_LSB 15 -#define ADC_SQR1_SQ15_LSB 10 -#define ADC_SQR1_SQ14_LSB 5 -#define ADC_SQR1_SQ13_LSB 0 -#define ADC_SQR1_L_MSK (0xf << ADC_L_LSB) -#define ADC_SQR1_SQ16_MSK (0x1f << ADC_SQ16_LSB) -#define ADC_SQR1_SQ15_MSK (0x1f << ADC_SQ15_LSB) -#define ADC_SQR1_SQ14_MSK (0x1f << ADC_SQ14_LSB) -#define ADC_SQR1_SQ13_MSK (0x1f << ADC_SQ13_LSB) - -/* --- ADC_SQR2 values ----------------------------------------------------- */ - -#define ADC_SQR2_SQ12_LSB 25 -#define ADC_SQR2_SQ11_LSB 20 -#define ADC_SQR2_SQ10_LSB 15 -#define ADC_SQR2_SQ9_LSB 10 -#define ADC_SQR2_SQ8_LSB 5 -#define ADC_SQR2_SQ7_LSB 0 -#define ADC_SQR2_SQ12_MSK (0x1f << ADC_SQ12_LSB) -#define ADC_SQR2_SQ11_MSK (0x1f << ADC_SQ11_LSB) -#define ADC_SQR2_SQ10_MSK (0x1f << ADC_SQ10_LSB) -#define ADC_SQR2_SQ9_MSK (0x1f << ADC_SQ9_LSB) -#define ADC_SQR2_SQ8_MSK (0x1f << ADC_SQ8_LSB) -#define ADC_SQR2_SQ7_MSK (0x1f << ADC_SQ7_LSB) - -/* --- ADC_SQR3 values ----------------------------------------------------- */ - -#define ADC_SQR3_SQ6_LSB 25 -#define ADC_SQR3_SQ5_LSB 20 -#define ADC_SQR3_SQ4_LSB 15 -#define ADC_SQR3_SQ3_LSB 10 -#define ADC_SQR3_SQ2_LSB 5 -#define ADC_SQR3_SQ1_LSB 0 -#define ADC_SQR3_SQ6_MSK (0x1f << ADC_SQ6_LSB) -#define ADC_SQR3_SQ5_MSK (0x1f << ADC_SQ5_LSB) -#define ADC_SQR3_SQ4_MSK (0x1f << ADC_SQ4_LSB) -#define ADC_SQR3_SQ3_MSK (0x1f << ADC_SQ3_LSB) -#define ADC_SQR3_SQ2_MSK (0x1f << ADC_SQ2_LSB) -#define ADC_SQR3_SQ1_MSK (0x1f << ADC_SQ1_LSB) - -/* --- ADC_JSQR values ----------------------------------------------------- */ - -#define ADC_JSQR_JL_LSB 20 -#define ADC_JSQR_JSQ4_LSB 15 -#define ADC_JSQR_JSQ3_LSB 10 -#define ADC_JSQR_JSQ2_LSB 5 -#define ADC_JSQR_JSQ1_LSB 0 -#define ADC_JSQR_JL_MSK (0x2 << ADC_JL_LSB) -#define ADC_JSQR_JSQ4_MSK (0x1f << ADC_JSQ4_LSB) -#define ADC_JSQR_JSQ3_MSK (0x1f << ADC_JSQ3_LSB) -#define ADC_JSQR_JSQ2_MSK (0x1f << ADC_JSQ2_LSB) -#define ADC_JSQR_JSQ1_MSK (0x1f << ADC_JSQ1_LSB) - -/* --- ADC_JDRx, ADC_DR values --------------------------------------------- */ - -#define ADC_JDATA_LSB 0 -#define ADC_DATA_LSB 0 -#define ADC_ADC2DATA_LSB 16 /* ADC1 only (dual mode) */ -#define ADC_JDATA_MSK (0xffff << ADC_JDATA_LSB) -#define ADC_DATA_MSK (0xffff << ADC_DA) -#define ADC_ADC2DATA_MSK (0xffff << ADC_ADC2DATA_LSB) - /* ADC1 only (dual mode) */ - -/* --- Function prototypes ------------------------------------------------- */ - - -/* TODO */ -void adc_enable_analog_watchdog_regular(u32 adc); -void adc_disable_analog_watchdog_regular(u32 adc); -void adc_enable_analog_watchdog_injected(u32 adc); -void adc_disable_analog_watchdog_injected(u32 adc); -void adc_enable_discontinous_mode_regular(u32 adc); -void adc_disable_discontinous_mode_regular(u32 adc); -void adc_enable_discontinous_mode_injected(u32 adc); -void adc_disable_discontinous_mode_injected(u32 adc); -void adc_enable_automatic_injected_group_conversion(u32 adc); -void adc_disable_automatic_injected_group_conversion(u32 adc); -void adc_enable_analog_watchdog_on_all_channels(u32 adc); -void adc_enable_analog_watchdog_on_selected_channel(u32 adc, u8 channel); -void adc_enable_scan_mode(u32 adc); -void adc_disable_scan_mode(u32 adc); -void adc_enable_jeoc_interrupt(u32 adc); -void adc_disable_jeoc_interrupt(u32 adc); -void adc_enable_awd_interrupt(u32 adc); -void adc_disable_awd_interrupt(u32 adc); -void adc_enable_eoc_interrupt(u32 adc); -void adc_disable_eoc_interrupt(u32 adc); -void adc_enable_temperature_sensor(u32 adc); -void adc_disable_temperature_sensor(u32 adc); -void adc_start_conversion_regular(u32 adc); -void adc_start_conversion_injected(u32 adc); -void adc_enable_external_trigger_regular(u32 adc, u8 trigger); -void adc_disable_external_trigger_regular(u32 adc); -void adc_enable_external_trigger_injected(u32 adc, u8 trigger); -void adc_disable_external_trigger_injected(u32 adc); -void adc_set_left_aligned(u32 adc); -void adc_set_right_aligned(u32 adc); -void adc_enable_dma(u32 adc); -void adc_disable_dma(u32 adc); -void adc_reset_calibration(u32 adc); -void adc_calibration(u32 adc); -void adc_set_continous_conversion_mode(u32 adc); -void adc_set_single_conversion_mode(u32 adc); -void adc_on(u32 adc); -void adc_off(u32 adc); -void adc_set_conversion_time(u32 adc, u8 channel, u8 time); -void adc_set_conversion_time_on_all_channels(u32 adc, u8 time); -void adc_set_watchdog_high_threshold(u32 adc, u16 threshold); -void adc_set_watchdog_low_threshold(u32 adc, u16 threshold); -void adc_set_regular_sequence(u32 adc, u8 length, u8 channel[]); -void adc_set_injected_sequence(u32 adc, u8 length, u8 channel[]); - -#endif diff --git a/include/libopencm3/stm32/bkp.h b/include/libopencm3/stm32/bkp.h deleted file mode 100644 index d700f9b..0000000 --- a/include/libopencm3/stm32/bkp.h +++ /dev/null @@ -1,208 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_BKP_H -#define LIBOPENCM3_BKP_H - -#include -#include - -/* --- BKP registers ------------------------------------------------------- */ - -/* Backup data register 1 (BKP_DR1) */ -#define BKP_DR1 MMIO32(BACKUP_REGS_BASE + 0x04) - -/* Backup data register 2 (BKP_DR2) */ -#define BKP_DR2 MMIO32(BACKUP_REGS_BASE + 0x08) - -/* Backup data register 3 (BKP_DR3) */ -#define BKP_DR3 MMIO32(BACKUP_REGS_BASE + 0x0C) - -/* Backup data register 4 (BKP_DR4) */ -#define BKP_DR4 MMIO32(BACKUP_REGS_BASE + 0x10) - -/* Backup data register 5 (BKP_DR5) */ -#define BKP_DR5 MMIO32(BACKUP_REGS_BASE + 0x14) - -/* Backup data register 6 (BKP_DR6) */ -#define BKP_DR6 MMIO32(BACKUP_REGS_BASE + 0x18) - -/* Backup data register 7 (BKP_DR7) */ -#define BKP_DR7 MMIO32(BACKUP_REGS_BASE + 0x1C) - -/* Backup data register 8 (BKP_DR8) */ -#define BKP_DR8 MMIO32(BACKUP_REGS_BASE + 0x20) - -/* Backup data register 9 (BKP_DR9) */ -#define BKP_DR9 MMIO32(BACKUP_REGS_BASE + 0x24) - -/* Backup data register 10 (BKP_DR10) */ -#define BKP_DR10 MMIO32(BACKUP_REGS_BASE + 0x28) - -/* RTC clock calibration register (BKP_RTCCR) */ -#define BKP_RTCCR MMIO32(BACKUP_REGS_BASE + 0x2C) - -/* Backup control register (BKP_CR) */ -#define BKP_CR MMIO32(BACKUP_REGS_BASE + 0x30) - -/* Backup control/status register (BKP_CSR) */ -#define BKP_CSR MMIO32(BACKUP_REGS_BASE + 0x34) - -/* Backup data register 11 (BKP_DR11) */ -#define BKP_DR11 MMIO32(BACKUP_REGS_BASE + 0x40) - -/* Backup data register 12 (BKP_DR12) */ -#define BKP_DR12 MMIO32(BACKUP_REGS_BASE + 0x44) - -/* Backup data register 13 (BKP_DR13) */ -#define BKP_DR13 MMIO32(BACKUP_REGS_BASE + 0x48) - -/* Backup data register 14 (BKP_DR14) */ -#define BKP_DR14 MMIO32(BACKUP_REGS_BASE + 0x4C) - -/* Backup data register 15 (BKP_DR15) */ -#define BKP_DR15 MMIO32(BACKUP_REGS_BASE + 0x50) - -/* Backup data register 16 (BKP_DR16) */ -#define BKP_DR16 MMIO32(BACKUP_REGS_BASE + 0x54) - -/* Backup data register 17 (BKP_DR17) */ -#define BKP_DR17 MMIO32(BACKUP_REGS_BASE + 0x58) - -/* Backup data register 18 (BKP_DR18) */ -#define BKP_DR18 MMIO32(BACKUP_REGS_BASE + 0x5C) - -/* Backup data register 19 (BKP_DR19) */ -#define BKP_DR19 MMIO32(BACKUP_REGS_BASE + 0x60) - -/* Backup data register 20 (BKP_DR20) */ -#define BKP_DR20 MMIO32(BACKUP_REGS_BASE + 0x64) - -/* Backup data register 21 (BKP_DR21) */ -#define BKP_DR21 MMIO32(BACKUP_REGS_BASE + 0x68) - -/* Backup data register 22 (BKP_DR22) */ -#define BKP_DR22 MMIO32(BACKUP_REGS_BASE + 0x6C) - -/* Backup data register 23 (BKP_DR23) */ -#define BKP_DR23 MMIO32(BACKUP_REGS_BASE + 0x70) - -/* Backup data register 24 (BKP_DR24) */ -#define BKP_DR24 MMIO32(BACKUP_REGS_BASE + 0x74) - -/* Backup data register 25 (BKP_DR25) */ -#define BKP_DR25 MMIO32(BACKUP_REGS_BASE + 0x78) - -/* Backup data register 26 (BKP_DR26) */ -#define BKP_DR26 MMIO32(BACKUP_REGS_BASE + 0x7C) - -/* Backup data register 27 (BKP_DR27) */ -#define BKP_DR27 MMIO32(BACKUP_REGS_BASE + 0x80) - -/* Backup data register 28 (BKP_DR28) */ -#define BKP_DR28 MMIO32(BACKUP_REGS_BASE + 0x84) - -/* Backup data register 29 (BKP_DR29) */ -#define BKP_DR29 MMIO32(BACKUP_REGS_BASE + 0x88) - -/* Backup data register 30 (BKP_DR30) */ -#define BKP_DR30 MMIO32(BACKUP_REGS_BASE + 0x8C) - -/* Backup data register 31 (BKP_DR31) */ -#define BKP_DR31 MMIO32(BACKUP_REGS_BASE + 0x90) - -/* Backup data register 32 (BKP_DR32) */ -#define BKP_DR32 MMIO32(BACKUP_REGS_BASE + 0x94) - -/* Backup data register 33 (BKP_DR33) */ -#define BKP_DR33 MMIO32(BACKUP_REGS_BASE + 0x98) - -/* Backup data register 34 (BKP_DR34) */ -#define BKP_DR34 MMIO32(BACKUP_REGS_BASE + 0x9C) - -/* Backup data register 35 (BKP_DR35) */ -#define BKP_DR35 MMIO32(BACKUP_REGS_BASE + 0xA0) - -/* Backup data register 36 (BKP_DR36) */ -#define BKP_DR36 MMIO32(BACKUP_REGS_BASE + 0xA4) - -/* Backup data register 37 (BKP_DR37) */ -#define BKP_DR37 MMIO32(BACKUP_REGS_BASE + 0xA8) - -/* Backup data register 38 (BKP_DR38) */ -#define BKP_DR38 MMIO32(BACKUP_REGS_BASE + 0xAC) - -/* Backup data register 39 (BKP_DR39) */ -#define BKP_DR39 MMIO32(BACKUP_REGS_BASE + 0xB0) - -/* Backup data register 40 (BKP_DR40) */ -#define BKP_DR40 MMIO32(BACKUP_REGS_BASE + 0xB4) - -/* Backup data register 41 (BKP_DR41) */ -#define BKP_DR41 MMIO32(BACKUP_REGS_BASE + 0xB8) - -/* Backup data register 42 (BKP_DR42) */ -#define BKP_DR42 MMIO32(BACKUP_REGS_BASE + 0xBC) - -/* --- BKP_RTCCR values ---------------------------------------------------- */ - -/* ASOS: Alarm or second output selection */ -#define BKP_RTCCR_ASOS (1 << 9) - -/* ASOE: Alarm or second output enable */ -#define BKP_RTCCR_ASOE (1 << 8) - -/* CCO: Calibration clock output */ -#define BKP_RTCCR_CCO (1 << 7) - -/* CAL[6:0]: Calibration value */ -#define BKP_RTCCR_CAL_LSB 0 - -/* --- BKP_CR values ------------------------------------------------------- */ - -/* TPAL: TAMPER pin active level */ -#define BKP_CR_TAL (1 << 1) - -/* TPE: TAMPER pin enable */ -#define BKP_CR_TPE (1 << 0) - -/* --- BKP_CSR values ------------------------------------------------------ */ - -/* TIF: Tamper interrupt flag */ -#define BKP_CSR_TIF (1 << 9) - -/* TEF: Tamper event flag */ -#define BKP_CSR_TEF (1 << 8) - -/* TPIE: TAMPER pin interrupt enable */ -#define BKP_CSR_TPIE (1 << 2) - -/* CTI: Clear tamper interrupt */ -#define BKP_CSR_CTI (1 << 1) - -/* CTE: Clear tamper event */ -#define BKP_CSR_CTE (1 << 0) - -/* --- BKP_DRx values ------------------------------------------------------ */ - -/* Bits[15:0]: Backup data */ - -/* --- BKP function prototypes --------------------------------------------- */ - -#endif diff --git a/include/libopencm3/stm32/can.h b/include/libopencm3/stm32/can.h deleted file mode 100644 index 1aa95a1..0000000 --- a/include/libopencm3/stm32/can.h +++ /dev/null @@ -1,642 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_CAN_H -#define LIBOPENCM3_CAN_H - -#include -#include - -/* --- Convenience macros -------------------------------------------------- */ - -/* CAN register base adresses (for convenience) */ -#define CAN1 BX_CAN1_BASE -#define CAN2 BX_CAN2_BASE - -/* --- CAN registers ------------------------------------------------------- */ - -/* CAN master control register (CAN_MCR) */ -#define CAN_MCR(can_base) MMIO32(can_base + 0x000) -/* CAN master status register (CAN_MSR) */ -#define CAN_MSR(can_base) MMIO32(can_base + 0x004) -/* CAN transmit status register (CAN_TSR) */ -#define CAN_TSR(can_base) MMIO32(can_base + 0x008) - -/* CAN receive FIFO 0 register (CAN_RF0R) */ -#define CAN_RF0R(can_base) MMIO32(can_base + 0x00C) -/* CAN receive FIFO 1 register (CAN_RF1R) */ -#define CAN_RF1R(can_base) MMIO32(can_base + 0x010) - -/* CAN interrupt enable register (CAN_IER) */ -#define CAN_IER(can_base) MMIO32(can_base + 0x014) -/* CAN error status register (CAN_ESR) */ -#define CAN_ESR(can_base) MMIO32(can_base + 0x018) -/* CAN bit timing register (CAN_BTR) */ -#define CAN_BTR(can_base) MMIO32(can_base + 0x01C) - -/* Registers in the offset range 0x020 to 0x17F are reserved. */ - -/* --- CAN mailbox registers ----------------------------------------------- */ - -/* CAN mailbox / FIFO register offsets */ -#define CAN_MBOX0 0x180 -#define CAN_MBOX1 0x190 -#define CAN_MBOX2 0x1A0 -#define CAN_FIFO0 0x1B0 -#define CAN_FIFO1 0x1C0 - -/* CAN TX mailbox identifier register (CAN_TIxR) */ -#define CAN_TIxR(can_base, mbox) MMIO32(can_base + mbox + 0x0) -#define CAN_TI0R(can_base) CAN_TIxR(can_base, CAN_MBOX0) -#define CAN_TI1R(can_base) CAN_TIxR(can_base, CAN_MBOX1) -#define CAN_TI2R(can_base) CAN_TIxR(can_base, CAN_MBOX2) - -/* CAN mailbox data length control and time stamp register (CAN_TDTxR) */ -#define CAN_TDTxR(can_base, mbox) MMIO32(can_base + mbox + 0x4) -#define CAN_TDT0R(can_base) CAN_TDTxR(can_base, CAN_MBOX0) -#define CAN_TDT1R(can_base) CAN_TDTxR(can_base, CAN_MBOX1) -#define CAN_TDT2R(can_base) CAN_TDTxR(can_base, CAN_MBOX2) - -/* CAN mailbox data low register (CAN_TDLxR) */ -#define CAN_TDLxR(can_base, mbox) MMIO32(can_base + mbox + 0x8) -#define CAN_TDL0R(can_base) CAN_TDLxR(can_base, CAN_MBOX0) -#define CAN_TDL1R(can_base) CAN_TDLxR(can_base, CAN_MBOX1) -#define CAN_TDL2R(can_base) CAN_TDLxR(can_base, CAN_MBOX2) - -/* CAN mailbox data high register (CAN_TDHxR) */ -#define CAN_TDHxR(can_base, mbox) MMIO32(can_base + mbox + 0xC) -#define CAN_TDH0R(can_base) CAN_TDHxR(can_base, CAN_MBOX0) -#define CAN_TDH1R(can_base) CAN_TDHxR(can_base, CAN_MBOX1) -#define CAN_TDH2R(can_base) CAN_TDHxR(can_base, CAN_MBOX2) - -/* CAN RX FIFO identifier register (CAN_RIxR) */ -#define CAN_RIxR(can_base, fifo) MMIO32(can_base + fifo + 0x0) -#define CAN_RI0R(can_base) CAN_RIxR(can_base, CAN_FIFO0) -#define CAN_RI1R(can_base) CAN_RIxR(can_base, CAN_FIFO1) - -/* CAN RX FIFO mailbox data length control & time stamp register (CAN_RDTxR) */ -#define CAN_RDTxR(can_base, fifo) MMIO32(can_base + fifo + 0x4) -#define CAN_RDT0R(can_base) CAN_RDTxR(can_base, CAN_FIFO0) -#define CAN_RDT1R(can_base) CAN_RDTxR(can_base, CAN_FIFO1) - -/* CAN RX FIFO mailbox data low register (CAN_RDLxR) */ -#define CAN_RDLxR(can_base, fifo) MMIO32(can_base + fifo + 0x8) -#define CAN_RDL0R(can_base) CAN_RDLxR(can_base, CAN_FIFO0) -#define CAN_RDL1R(can_base) CAN_RDLxR(can_base, CAN_FIFO1) - -/* CAN RX FIFO mailbox data high register (CAN_RDHxR) */ -#define CAN_RDHxR(can_base, fifo) MMIO32(can_base + fifo + 0xC) -#define CAN_RDH0R(can_base) CAN_RDHxR(can_base, CAN_FIFO0) -#define CAN_RDH1R(can_base) CAN_RDHxR(can_base, CAN_FIFO1) - -/* --- CAN filter registers ------------------------------------------------ */ - -/* CAN filter master register (CAN_FMR) */ -#define CAN_FMR(can_base) MMIO32(can_base + 0x200) - -/* CAN filter mode register (CAN_FM1R) */ -#define CAN_FM1R(can_base) MMIO32(can_base + 0x204) - -/* Register offset 0x208 is reserved. */ - -/* CAN filter scale register (CAN_FS1R) */ -#define CAN_FS1R(can_base) MMIO32(can_base + 0x20C) - -/* Register offset 0x210 is reserved. */ - -/* CAN filter FIFO assignement register (CAN_FFA1R) */ -#define CAN_FFA1R(can_base) MMIO32(can_base + 0x214) - -/* Register offset 0x218 is reserved. */ - -/* CAN filter activation register (CAN_FA1R) */ -#define CAN_FA1R(can_base) MMIO32(can_base + 0x21C) - -/* Register offset 0x220 is reserved. */ - -/* Registers with offset 0x224 to 0x23F are reserved. */ - -/* CAN filter bank registers (CAN_FiRx) */ -/* - * Connectivity line devices have 28 banks so the bank ID spans 0..27 - * all other devices have 14 banks so the bank ID spans 0..13. - */ -#define CAN_FiR1(can_base, bank) MMIO32(can_base + 0x240 + (bank * 0x8) + 0x0) -#define CAN_FiR2(can_base, bank) MMIO32(can_base + 0x240 + (bank * 0x8) + 0x4) - -/* --- CAN_MCR values ------------------------------------------------------ */ - -/* 31:17 Reserved, forced by hardware to 0 */ - -/* DBF: Debug freeze */ -#define CAN_MCR_DBF (1 << 16) - -/* RESET: bxCAN software master reset */ -#define CAN_MCR_RESET (1 << 15) - -/* 14:8 Reserved, forced by hardware to 0 */ - -/* TTCM: Time triggered communication mode */ -#define CAN_MCR_TTCM (1 << 7) - -/* ABOM: Automatic bus-off management */ -#define CAN_MCR_ABOM (1 << 6) - -/* AWUM: Automatic wakeup mode */ -#define CAN_MCR_AWUM (1 << 5) - -/* NART: No automatic retransmission */ -#define CAN_MCR_NART (1 << 4) - -/* RFLM: Receive FIFO locked mode */ -#define CAN_MCR_RFLM (1 << 3) - -/* TXFP: Transmit FIFO priority */ -#define CAN_MCR_TXFP (1 << 2) - -/* SLEEP: Sleep mode request */ -#define CAN_MCR_SLEEP (1 << 1) - -/* INRQ: Initialization request */ -#define CAN_MCR_INRQ (1 << 0) - -/* --- CAN_MSR values ------------------------------------------------------ */ - -/* 31:12 Reserved, forced by hardware to 0 */ - -/* RX: CAN Rx signal */ -#define CAN_MSR_RX (1 << 11) - -/* SAMP: Last sample point */ -#define CAN_MSR_SAMP (1 << 10) - -/* RXM: Receive mode */ -#define CAN_MSR_RXM (1 << 9) - -/* TXM: Transmit mode */ -#define CAN_MSR_TXM (1 << 8) - -/* 7:5 Reserved, forced by hardware to 0 */ - -/* SLAKI: Sleep acknowledge interrupt */ -#define CAN_MSR_SLAKI (1 << 4) - -/* WKUI: Wakeup interrupt */ -#define CAN_MSR_WKUI (1 << 3) - -/* ERRI: Error interrupt */ -#define CAN_MSR_ERRI (1 << 2) - -/* SLAK: Sleep acknowledge */ -#define CAN_MSR_SLAK (1 << 1) - -/* INAK: Initialization acknowledge */ -#define CAN_MSR_INAK (1 << 0) - -/* --- CAN_TSR values ------------------------------------------------------ */ - -/* LOW2: Lowest priority flag for mailbox 2 */ -#define CAN_TSR_LOW2 (1 << 31) - -/* LOW1: Lowest priority flag for mailbox 1 */ -#define CAN_TSR_LOW1 (1 << 30) - -/* LOW0: Lowest priority flag for mailbox 0 */ -#define CAN_TSR_LOW0 (1 << 29) - -/* TME2: Transmit mailbox 2 empty */ -#define CAN_TSR_TME2 (1 << 28) - -/* TME1: Transmit mailbox 1 empty */ -#define CAN_TSR_TME1 (1 << 27) - -/* TME0: Transmit mailbox 0 empty */ -#define CAN_TSR_TME0 (1 << 26) - -/* CODE[1:0]: Mailbox code */ -#define CAN_TSR_CODE_MASK (0x3 << 24) - -/* ABRQ2: Abort request for mailbox 2 */ -#define CAN_TSR_TABRQ2 (1 << 23) - -/* 22:20 Reserved, forced by hardware to 0 */ - -/* TERR2: Transmission error for mailbox 2 */ -#define CAN_TSR_TERR2 (1 << 19) - -/* ALST2: Arbitration lost for mailbox 2 */ -#define CAN_TSR_ALST2 (1 << 18) - -/* TXOK2: Transmission OK for mailbox 2 */ -#define CAN_TSR_TXOK2 (1 << 17) - -/* RQCP2: Request completed mailbox 2 */ -#define CAN_TSR_RQCP2 (1 << 16) - -/* ABRQ1: Abort request for mailbox 1 */ -#define CAN_TSR_ABRQ1 (1 << 15) - -/* 14:12 Reserved, forced by hardware to 0 */ - -/* TERR1: Transmission error for mailbox 1 */ -#define CAN_TSR_TERR1 (1 << 11) - -/* ALST1: Arbitration lost for mailbox 1 */ -#define CAN_TSR_ALST1 (1 << 10) - -/* TXOK1: Transmission OK for mailbox 1 */ -#define CAN_TSR_TXOK1 (1 << 9) - -/* RQCP1: Request completed mailbox 1 */ -#define CAN_TSR_RQCP1 (1 << 8) - -/* ABRQ0: Abort request for mailbox 0 */ -#define CAN_TSR_ABRQ0 (1 << 7) - -/* 6:4 Reserved, forced by hardware to 0 */ - -/* TERR0: Transmission error for mailbox 0 */ -#define CAN_TSR_TERR0 (1 << 3) - -/* ALST0: Arbitration lost for mailbox 0 */ -#define CAN_TSR_ALST0 (1 << 2) - -/* TXOK0: Transmission OK for mailbox 0 */ -#define CAN_TSR_TXOK0 (1 << 1) - -/* RQCP0: Request completed mailbox 0 */ -#define CAN_TSR_RQCP0 (1 << 0) - -/* --- CAN_RF0R values ----------------------------------------------------- */ - -/* 31:6 Reserved, forced by hardware to 0 */ - -/* RFOM0: Release FIFO 0 output mailbox */ -#define CAN_RF0R_RFOM0 (1 << 5) - -/* FOVR0: FIFO 0 overrun */ -#define CAN_RF0R_FAVR0 (1 << 4) - -/* FULL0: FIFO 0 full */ -#define CAN_RF0R_FULL0 (1 << 3) - -/* 2 Reserved, forced by hardware to 0 */ - -/* FMP0[1:0]: FIFO 0 message pending */ -#define CAN_RF0R_FMP0_MASK (0x3 << 0) - -/* --- CAN_RF1R values ----------------------------------------------------- */ - -/* 31:6 Reserved, forced by hardware to 0 */ - -/* RFOM1: Release FIFO 1 output mailbox */ -#define CAN_RF1R_RFOM1 (1 << 5) - -/* FOVR1: FIFO 1 overrun */ -#define CAN_RF1R_FAVR1 (1 << 4) - -/* FULL1: FIFO 1 full */ -#define CAN_RF1R_FULL1 (1 << 3) - -/* 2 Reserved, forced by hardware to 0 */ - -/* FMP1[1:0]: FIFO 1 message pending */ -#define CAN_RF1R_FMP1_MASK (0x3 << 0) - -/* --- CAN_IER values ------------------------------------------------------ */ - -/* 32:18 Reserved, forced by hardware to 0 */ - -/* SLKIE: Sleep interrupt enable */ -#define CAN_IER_SLKIE (1 << 17) - -/* WKUIE: Wakeup interrupt enable */ -#define CAN_IER_WKUIE (1 << 16) - -/* ERRIE: Error interrupt enable */ -#define CAN_IER_ERRIE (1 << 15) - -/* 14:12 Reserved, forced by hardware to 0 */ - -/* LECIE: Last error code interrupt enable */ -#define CAN_IER_LECIE (1 << 11) - -/* BOFIE: Bus-off interrupt enable */ -#define CAN_IER_BOFIE (1 << 10) - -/* EPVIE: Error passive interrupt enable */ -#define CAN_IER_EPVIE (1 << 9) - -/* EWGIE: Error warning interrupt enable */ -#define CAN_IER_EWGIE (1 << 8) - -/* 7 Reserved, forced by hardware to 0 */ - -/* FOVIE1: FIFO overrun interrupt enable */ -#define CAN_IER_FOVIE1 (1 << 6) - -/* FFIE1: FIFO full interrupt enable */ -#define CAN_IER_FFIE1 (1 << 5) - -/* FMPIE1: FIFO message pending interrupt enable */ -#define CAN_IER_FMPIE1 (1 << 4) - -/* FOVIE0: FIFO overrun interrupt enable */ -#define CAN_IER_FOVIE0 (1 << 3) - -/* FFIE0: FIFO full interrupt enable */ -#define CAN_IER_FFIE0 (1 << 2) - -/* FMPIE0: FIFO message pending interrupt enable */ -#define CAN_IER_FMPIE0 (1 << 1) - -/* TMEIE: Transmit mailbox empty interrupt enable */ -#define CAN_IER_TMEIE (1 << 0) - -/* --- CAN_ESR values ------------------------------------------------------ */ - -/* REC[7:0]: Receive error counter */ -#define CAN_ESR_REC_MASK (0xF << 24) - -/* TEC[7:0]: Least significant byte of the 9-bit transmit error counter */ -#define CAN_ESR_TEC_MASK (0xF << 16) - -/* 15:7 Reserved, forced by hardware to 0 */ - -/* LEC[2:0]: Last error code */ -#define CAN_ESR_LEC_NO_ERROR (0x0 << 4) -#define CAN_ESR_LEC_STUFF_ERROR (0x1 << 4) -#define CAN_ESR_LEC_FORM_ERROR (0x2 << 4) -#define CAN_ESR_LEC_ACK_ERROR (0x3 << 4) -#define CAN_ESR_LEC_REC_ERROR (0x4 << 4) -#define CAN_ESR_LEC_DOM_ERROR (0x5 << 4) -#define CAN_ESR_LEC_CRC_ERROR (0x6 << 4) -#define CAN_ESR_LEC_SOFT_ERROR (0x7 << 4) -#define CAN_ESR_LEC_MASK (0x7 << 4) - -/* 3 Reserved, forced by hardware to 0 */ - -/* BOFF: Bus-off flag */ -#define CAN_ESR_BOFF (1 << 2) - -/* EPVF: Error passive flag */ -#define CAN_ESR_EPVF (1 << 1) - -/* EWGF: Error warning flag */ -#define CAN_ESR_EWGF (1 << 0) - -/* --- CAN_BTR values ------------------------------------------------------ */ - -/* SILM: Silent mode (debug) */ -#define CAN_BTR_SILM (1 << 31) - -/* LBKM: Loop back mode (debug) */ -#define CAN_BTR_LBKM (1 << 30) - -/* 29:26 Reserved, forced by hardware to 0 */ - -/* SJW[1:0]: Resynchronization jump width */ -#define CAN_BTR_SJW_1TQ (0x0 << 24) -#define CAN_BTR_SJW_2TQ (0x1 << 24) -#define CAN_BTR_SJW_3TQ (0x2 << 24) -#define CAN_BTR_SJW_4TQ (0x3 << 24) -#define CAN_BTR_SJW_MASK (0x3 << 24) - -/* 23 Reserved, forced by hardware to 0 */ - -/* TS2[2:0]: Time segment 2 */ -#define CAN_BTR_TS2_1TQ (0x0 << 20) -#define CAN_BTR_TS2_2TQ (0x1 << 20) -#define CAN_BTR_TS2_3TQ (0x2 << 20) -#define CAN_BTR_TS2_4TQ (0x3 << 20) -#define CAN_BTR_TS2_5TQ (0x4 << 20) -#define CAN_BTR_TS2_6TQ (0x5 << 20) -#define CAN_BTR_TS2_7TQ (0x6 << 20) -#define CAN_BTR_TS2_8TQ (0x7 << 20) -#define CAN_BTR_TS2_MASK (0x7 << 20) - -/* TS1[3:0]: Time segment 1 */ -#define CAN_BTR_TS1_1TQ (0x0 << 16) -#define CAN_BTR_TS1_2TQ (0x1 << 16) -#define CAN_BTR_TS1_3TQ (0x2 << 16) -#define CAN_BTR_TS1_4TQ (0x3 << 16) -#define CAN_BTR_TS1_5TQ (0x4 << 16) -#define CAN_BTR_TS1_6TQ (0x5 << 16) -#define CAN_BTR_TS1_7TQ (0x6 << 16) -#define CAN_BTR_TS1_8TQ (0x7 << 16) -#define CAN_BTR_TS1_9TQ (0x8 << 16) -#define CAN_BTR_TS1_10TQ (0x9 << 16) -#define CAN_BTR_TS1_11TQ (0xA << 16) -#define CAN_BTR_TS1_12TQ (0xB << 16) -#define CAN_BTR_TS1_13TQ (0xC << 16) -#define CAN_BTR_TS1_14TQ (0xD << 16) -#define CAN_BTR_TS1_15TQ (0xE << 16) -#define CAN_BTR_TS1_16TQ (0xF << 16) -#define CAN_BTR_TS1_MASK (0xF << 16) - -/* 15:10 Reserved, forced by hardware to 0 */ - -/* BRP[9:0]: Baud rate prescaler */ -#define CAN_BTR_BRP_MASK (0x1FF << 0) - -/* --- CAN_TIxR values ------------------------------------------------------ */ - -/* STID[10:0]: Standard identifier */ -#define CAN_TIxR_STID_MASK (0x3FF << 21) -#define CAN_TIxR_STID_SHIFT 21 - -/* EXID[15:0]: Extended identifier */ -#define CAN_TIxR_EXID_MASK (0x1FFFFFF << 3) -#define CAN_TIxR_EXID_SHIFT 3 - -/* IDE: Identifier extension */ -#define CAN_TIxR_IDE (1 << 2) - -/* RTR: Remote transmission request */ -#define CAN_TIxR_RTR (1 << 1) - -/* TXRQ: Transmit mailbox request */ -#define CAN_TIxR_TXRQ (1 << 0) - -/* --- CAN_TDTxR values ----------------------------------------------------- */ - -/* TIME[15:0]: Message time stamp */ -#define CAN_TDTxR_TIME_MASK (0xFFFF << 15) -#define CAN_TDTxR_TIME_SHIFT 15 - -/* 15:6 Reserved, forced by hardware to 0 */ - -/* TGT: Transmit global time */ -#define CAN_TDTxR_TGT (1 << 5) - -/* 7:4 Reserved, forced by hardware to 0 */ - -/* DLC[3:0]: Data length code */ -#define CAN_TDTxR_DLC_MASK (0xF << 0) -#define CAN_TDTxR_DLC_SHIFT 0 - -/* --- CAN_TDLxR values ----------------------------------------------------- */ - -/* DATA3[7:0]: Data byte 3 */ -/* DATA2[7:0]: Data byte 2 */ -/* DATA1[7:0]: Data byte 1 */ -/* DATA0[7:0]: Data byte 0 */ - -/* --- CAN_TDHxR values ----------------------------------------------------- */ - -/* DATA7[7:0]: Data byte 7 */ -/* DATA6[7:0]: Data byte 6 */ -/* DATA5[7:0]: Data byte 5 */ -/* DATA4[7:0]: Data byte 4 */ - -/* --- CAN_RIxR values ------------------------------------------------------ */ - -/* STID[10:0]: Standard identifier */ -#define CAN_RIxR_STID_MASK (0x3FF << 21) -#define CAN_RIxR_STID_SHIFT 21 - -/* EXID[15:0]: Extended identifier */ -#define CAN_RIxR_EXID_MASK (0x1FFFFFF << 3) -#define CAN_RIxR_EXID_SHIFT 3 - -/* IDE: Identifier extension */ -#define CAN_RIxR_IDE (1 << 2) - -/* RTR: Remote transmission request */ -#define CAN_RIxR_RTR (1 << 1) - -/* 0 Reserved */ - -/* --- CAN_RDTxR values ----------------------------------------------------- */ - -/* TIME[15:0]: Message time stamp */ -#define CAN_RDTxR_TIME_MASK (0xFFFF << 15) -#define CAN_RDTxR_TIME_SHIFT 15 - -/* FMI[7:0]: Filter match index */ -#define CAN_RDTxR_FMI_MASK (0xFF << 8) -#define CAN_RDTxR_FMI_SHIFT 8 - -/* 7:4 Reserved, forced by hardware to 0 */ - -/* DLC[3:0]: Data length code */ -#define CAN_RDTxR_DLC_MASK (0xF << 0) -#define CAN_RDTxR_DLC_SHIFT 0 - -/* --- CAN_RDLxR values ----------------------------------------------------- */ - -/* DATA3[7:0]: Data byte 3 */ -/* DATA2[7:0]: Data byte 2 */ -/* DATA1[7:0]: Data byte 1 */ -/* DATA0[7:0]: Data byte 0 */ - -/* --- CAN_RDHxR values ----------------------------------------------------- */ - -/* DATA7[7:0]: Data byte 7 */ -/* DATA6[7:0]: Data byte 6 */ -/* DATA5[7:0]: Data byte 5 */ -/* DATA4[7:0]: Data byte 4 */ - -/* --- CAN_FMR values ------------------------------------------------------- */ - -/* 31:14 Reserved, forced to reset value */ - -/* - * CAN2SB[5:0]: CAN2 start bank - * (only on connectivity line devices otherwise reserved) - */ -#define CAN_FMR_CAN2SB_MASK (0x3F << 8) -#define CAN_FMR_CAN2SB_SHIFT 15 - -/* 7:1 Reserved, forced to reset value */ - -/* FINIT: Filter init mode */ -#define CAN_FMR_FINIT (1 << 0) - -/* --- CAN_FM1R values ------------------------------------------------------ */ - -/* 31:28 Reserved, forced by hardware to 0 */ - -/* - * FBMx: Filter mode - * x is 0..27 should be calculated by a helper function making so many macros - * seems like an overkill? - */ - -/* --- CAN_FS1R values ------------------------------------------------------ */ - -/* 31:28 Reserved, forced by hardware to 0 */ - -/* - * FSCx: Filter scale configuration - * x is 0..27 should be calculated by a helper function making so many macros - * seems like an overkill? - */ - -/* --- CAN_FFA1R values ----------------------------------------------------- */ - -/* 31:28 Reserved, forced by hardware to 0 */ - -/* - * FFAx: Filter scale configuration - * x is 0..27 should be calculated by a helper function making so many macros - * seems like an overkill? - */ - -/* --- CAN_FA1R values ------------------------------------------------------ */ - -/* 31:28 Reserved, forced by hardware to 0 */ - -/* - * FACTx: Filter active - * x is 0..27 should be calculated by a helper function making so many macros - * seems like an overkill? - */ - -/* --- CAN_FiRx values ------------------------------------------------------ */ - -/* FB[31:0]: Filter bits */ - -/* --- CAN functions -------------------------------------------------------- */ - -void can_reset(u32 canport); -int can_init(u32 canport, bool ttcm, bool abom, bool awum, bool nart, - bool rflm, bool txfp, u32 sjw, u32 ts1, u32 ts2, u32 brp); - -void can_filter_init(u32 canport, u32 nr, bool scale_32bit, bool id_list_mode, - u32 fr1, u32 fr2, u32 fifo, bool enable); -void can_filter_id_mask_16bit_init(u32 canport, u32 nr, u16 id1, u16 mask1, - u16 id2, u16 mask2, u32 fifo, bool enable); -void can_filter_id_mask_32bit_init(u32 canport, u32 nr, u32 id, u32 mask, - u32 fifo, bool enable); -void can_filter_id_list_16bit_init(u32 canport, u32 nr, u16 id1, u16 id2, - u16 id3, u16 id4, u32 fifo, bool enable); -void can_filter_id_list_32bit_init(u32 canport, u32 nr, u32 id1, u32 id2, - u32 fifo, bool enable); - -void can_enable_irq(u32 canport, u32 irq); -void can_disable_irq(u32 canport, u32 irq); - -int can_transmit(u32 canport, u32 id, bool ext, bool rtr, u8 length, u8 *data); -void can_receive(u32 canport, u8 fifo, bool release, u32 *id, bool *ext, - bool *rtr, u32 *fmi, u8 *length, u8 *data); - -void can_fifo_release(u32 canport, u8 fifo); - -#endif diff --git a/include/libopencm3/stm32/crc.h b/include/libopencm3/stm32/crc.h deleted file mode 100644 index 5ad866e..0000000 --- a/include/libopencm3/stm32/crc.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_CRC_H -#define LIBOPENCM3_CRC_H - -#include -#include - -/* --- CRC registers ------------------------------------------------------- */ - -/* Data register (CRC_DR) */ -#define CRC_DR MMIO32(CRC_BASE + 0x00) - -/* Independent data register (CRC_IDR) */ -#define CRC_IDR MMIO32(CRC_BASE + 0x04) - -/* Control register (CRC_CR) */ -#define CRC_CR MMIO32(CRC_BASE + 0x08) - -/* --- CRC_DR values ------------------------------------------------------- */ - -/* Bits[31:0] Data register */ - -/* --- CRC_IDR values ------------------------------------------------------ */ - -/* Bits[7:0] General-purpose 8-bit data register bits */ - -/* --- CRC_CR values ------------------------------------------------------- */ - -/* RESET bit */ -#define CRC_CR_RESET (1 << 0) - -/* --- CRC function prototypes --------------------------------------------- */ - -#endif diff --git a/include/libopencm3/stm32/dbgmcu.h b/include/libopencm3/stm32/dbgmcu.h deleted file mode 100644 index e753f5e..0000000 --- a/include/libopencm3/stm32/dbgmcu.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Gareth McMullin - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_STM32_DBGMCU_H -#define LIBOPENCM3_STM32_DBGMCU_H - -#include -#include - -/* --- DBGMCU registers ---------------------------------------------------- */ - -#define DBGMCU_IDCODE MMIO32(DBGMCU_BASE + 0x00) -#define DBGMCU_CR MMIO32(DBGMCU_BASE + 0x04) - -/* DBGMCU_CR bits */ -#define DBGMCU_CR_SLEEP 0x00000001 -#define DBGMCU_CR_STOP 0x00000002 -#define DBGMCU_CR_STANDBY 0x00000004 -#define DBGMCU_CR_TRACE_IOEN 0x00000020 -#define DBGMCU_CR_TRACE_MODE_MASK 0x000000C0 -#define DBGMCU_CR_TRACE_MODE_ASYNC 0x00000000 -#define DBGMCU_CR_TRACE_MODE_SYNC_1 0x00000040 -#define DBGMCU_CR_TRACE_MODE_SYNC_2 0x00000080 -#define DBGMCU_CR_TRACE_MODE_SYNC_4 0x000000C0 -#define DBGMCU_CR_IWDG_STOP 0x00000100 -#define DBGMCU_CR_WWDG_STOP 0x00000200 -#define DBGMCU_CR_TIM1_STOP 0x00000400 -#define DBGMCU_CR_TIM2_STOP 0x00000800 -#define DBGMCU_CR_TIM3_STOP 0x00001000 -#define DBGMCU_CR_TIM4_STOP 0x00002000 -#define DBGMCU_CR_CAN1_STOP 0x00004000 -#define DBGMCU_CR_I2C1_SMBUS_TIMEOUT 0x00008000 -#define DBGMCU_CR_I2C2_SMBUS_TIMEOUT 0x00010000 -#define DBGMCU_CR_TIM8_STOP 0x00020000 -#define DBGMCU_CR_TIM5_STOP 0x00040000 -#define DBGMCU_CR_TIM6_STOP 0x00080000 -#define DBGMCU_CR_TIM7_STOP 0x00100000 -#define DBGMCU_CR_CAN2_STOP 0x00200000 - -/* DBGMCU_IDCODE bits */ -#define DBGMCU_IDCODE_DEV_ID_MASK 0x00000fff -#define DBGMCU_IDCODE_REV_ID_MASK 0xffff0000 - -#endif diff --git a/include/libopencm3/stm32/dma.h b/include/libopencm3/stm32/dma.h deleted file mode 100644 index 7d0a856..0000000 --- a/include/libopencm3/stm32/dma.h +++ /dev/null @@ -1,723 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_DMA_H -#define LIBOPENCM3_DMA_H - -#include -#include - -/* --- Convenience macros -------------------------------------------------- */ - -/* DMA register base adresses (for convenience) */ -#define DMA1 DMA1_BASE -#define DMA2 DMA2_BASE - -/* --- DMA registers ------------------------------------------------------- */ - -/* DMA interrupt status register (DMAx_ISR) */ -#define DMA_ISR(dma_base) MMIO32(dma_base + 0x00) -#define DMA1_ISR DMA_ISR(DMA1) -#define DMA2_ISR DMA_ISR(DMA2) - -/* DMA interrupt flag clear register (DMAx_IFCR) */ -#define DMA_IFCR(dma_base) MMIO32(dma_base + 0x04) -#define DMA1_IFCR DMA_IFCR(DMA1) -#define DMA2_IFCR DMA_IFCR(DMA2) - -/* DMA channel 1 configuration register (DMAx_CCR1) */ -#define DMA_CCR1(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 0) -#define DMA1_CCR1 DMA_CCR1(DMA1) -#define DMA2_CCR1 DMA_CCR1(DMA2) - -/* DMA channel 2 configuration register (DMAx_CCR2) */ -#define DMA_CCR2(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 1) -#define DMA1_CCR2 DMA_CCR2(DMA1) -#define DMA2_CCR2 DMA_CCR2(DMA2) - -/* DMA channel 3 configuration register (DMAx_CCR3) */ -#define DMA_CCR3(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 2) -#define DMA1_CCR3 DMA_CCR3(DMA1) -#define DMA2_CCR3 DMA_CCR3(DMA2) - -/* DMA channel 4 configuration register (DMAx_CCR4) */ -#define DMA_CCR4(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 3) -#define DMA1_CCR4 DMA_CCR4(DMA1) -#define DMA2_CCR4 DMA_CCR4(DMA2) - -/* DMA channel 5 configuration register (DMAx_CCR5) */ -#define DMA_CCR5(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 4) -#define DMA1_CCR5 DMA_CCR5(DMA1) -#define DMA2_CCR5 DMA_CCR5(DMA2) - -/* DMA channel 6 configuration register (DMAx_CCR6) */ -#define DMA_CCR6(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 5) -#define DMA1_CCR6 DMA_CCR6(DMA1) - -/* DMA channel 7 configuration register (DMAx_CCR7) */ -#define DMA_CCR7(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 6) -#define DMA1_CCR7 DMA_CCR7(DMA1) - -/* DMA channel 1 number of data register (DMAx_CNDTR1) */ -#define DMA_CNDTR1(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 0) -#define DMA1_CNDTR1 DMA_CNDTR1(DMA1) -#define DMA2_CNDTR1 DMA_CNDTR1(DMA2) - -/* DMA channel 2 number of data register (DMAx_CNDTR2) */ -#define DMA_CNDTR2(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 1) -#define DMA1_CNDTR2 DMA_CNDTR2(DMA1) -#define DMA2_CNDTR2 DMA_CNDTR2(DMA2) - -/* DMA channel 3 number of data register (DMAx_CNDTR3) */ -#define DMA_CNDTR3(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 2) -#define DMA1_CNDTR3 DMA_CNDTR3(DMA1) -#define DMA2_CNDTR3 DMA_CNDTR3(DMA2) - -/* DMA channel 4 number of data register (DMAx_CNDTR4) */ -#define DMA_CNDTR4(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 3) -#define DMA1_CNDTR4 DMA_CNDTR4(DMA1) -#define DMA2_CNDTR4 DMA_CNDTR4(DMA2) - -/* DMA channel 5 number of data register (DMAx_CNDTR5) */ -#define DMA_CNDTR5(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 4) -#define DMA1_CNDTR5 DMA_CNDTR5(DMA1) -#define DMA2_CNDTR5 DMA_CNDTR5(DMA2) - -/* DMA channel 6 number of data register (DMAx_CNDTR6) */ -#define DMA_CNDTR6(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 5) -#define DMA1_CNDTR6 DMA_CNDTR6(DMA1) - -/* DMA channel 7 number of data register (DMAx_CNDTR7) */ -#define DMA_CNDTR7(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 6) -#define DMA1_CNDTR7 DMA_CNDTR7(DMA1) - -/* DMA channel 1 peripheral address register (DMAx_CPAR1) */ -#define DMA_CPAR1(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 0) -#define DMA1_CPAR1 DMA_CPAR1(DMA1) -#define DMA2_CPAR1 DMA_CPAR1(DMA2) - -/* DMA channel 2 peripheral address register (DMAx_CPAR2) */ -#define DMA_CPAR2(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 1) -#define DMA1_CPAR2 DMA_CPAR2(DMA1) -#define DMA2_CPAR2 DMA_CPAR2(DMA2) - -/* DMA channel 3 peripheral address register (DMAx_CPAR3) */ -#define DMA_CPAR3(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 2) -#define DMA1_CPAR3 DMA_CPAR3(DMA1) -#define DMA2_CPAR3 DMA_CPAR3(DMA2) - -/* DMA channel 4 peripheral address register (DMAx_CPAR4) */ -#define DMA_CPAR4(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 3) -#define DMA1_CPAR4 DMA_CPAR4(DMA1) -#define DMA2_CPAR4 DMA_CPAR4(DMA2) - -/* DMA channel 5 peripheral address register (DMAx_CPAR5) */ -#define DMA_CPAR5(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 4) -#define DMA1_CPAR5 DMA_CPAR5(DMA1) -#define DMA2_CPAR5 DMA_CPAR5(DMA2) - -/* DMA channel 6 peripheral address register (DMAx_CPAR6) */ -#define DMA_CPAR6(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 5) -#define DMA1_CPAR6 DMA_CPAR6(DMA1) - -/* DMA channel 7 peripheral address register (DMAx_CPAR7) */ -#define DMA_CPAR7(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 6) -#define DMA1_CPAR7 DMA_CPAR7(DMA1) - -/* DMA channel 1 memory address register (DMAx_CMAR1) */ -#define DMA_CMAR1(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 0) -#define DMA1_CMAR1 DMA_CMAR1(DMA1) -#define DMA2_CMAR1 DMA_CMAR1(DMA2) - -/* DMA channel 2 memory address register (DMAx_CMAR2) */ -#define DMA_CMAR2(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 1) -#define DMA1_CMAR2 DMA_CMAR2(DMA1) -#define DMA2_CMAR2 DMA_CMAR2(DMA2) - -/* DMA channel 3 memory address register (DMAx_CMAR3) */ -#define DMA_CMAR3(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 2) -#define DMA1_CMAR3 DMA_CMAR3(DMA1) -#define DMA2_CMAR3 DMA_CMAR3(DMA2) - -/* DMA channel 4 memory address register (DMAx_CMAR4) */ -#define DMA_CMAR4(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 3) -#define DMA1_CMAR4 DMA_CMAR4(DMA1) -#define DMA2_CMAR4 DMA_CMAR4(DMA2) - -/* DMA channel 5 memory address register (DMAx_CMAR5) */ -#define DMA_CMAR5(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 4) -#define DMA1_CMAR5 DMA_CMAR5(DMA1) -#define DMA2_CMAR5 DMA_CMAR5(DMA2) - -/* DMA channel 6 memory address register (DMAx_CMAR6) */ -#define DMA_CMAR6(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 5) -#define DMA1_CMAR6 DMA_CMAR6(DMA1) - -/* DMA channel 7 memory address register (DMAx_CMAR7) */ -#define DMA_CMAR7(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 6) -#define DMA1_CMAR7 DMA_CMAR7(DMA1) - -/* --- DMA_ISR values ------------------------------------------------------ */ - -/* TEIF7: Channel 7 transfer error flag */ -#define DMA_ISR_TEIF7 (1 << 27) -/* HTIF7: Channel 7 half transfer flag */ -#define DMA_ISR_HTIF7 (1 << 26) -/* TCIF7: Channel 7 transfer complete flag */ -#define DMA_ISR_TCIF7 (1 << 25) -/* GIF7: Channel 7 global interrupt flag */ -#define DMA_ISR_GIF7 (1 << 24) -/* TEIF6: Channel 6 transfer error flag */ -#define DMA_ISR_TEIF6 (1 << 23) -/* HTIF6: Channel 6 half transfer flag */ -#define DMA_ISR_HTIF6 (1 << 22) -/* TCIF6: Channel 6 transfer complete flag */ -#define DMA_ISR_TCIF6 (1 << 21) -/* GIF6: Channel 6 global interrupt flag */ -#define DMA_ISR_GIF6 (1 << 20) -/* TEIF5: Channel 5 transfer error flag */ -#define DMA_ISR_TEIF5 (1 << 19) -/* HTIF5: Channel 5 half transfer flag */ -#define DMA_ISR_HTIF5 (1 << 18) -/* TCIF5: Channel 5 transfer complete flag */ -#define DMA_ISR_TCIF5 (1 << 17) -/* GIF5: Channel 5 global interrupt flag */ -#define DMA_ISR_GIF5 (1 << 16) -/* TEIF4: Channel 4 transfer error flag */ -#define DMA_ISR_TEIF4 (1 << 15) -/* HTIF4: Channel 4 half transfer flag */ -#define DMA_ISR_HTIF4 (1 << 14) -/* TCIF4: Channel 4 transfer complete flag */ -#define DMA_ISR_TCIF4 (1 << 13) -/* GIF4: Channel 4 global interrupt flag */ -#define DMA_ISR_GIF4 (1 << 12) -/* TEIF3: Channel 3 transfer error flag */ -#define DMA_ISR_TEIF3 (1 << 11) -/* HTIF3: Channel 3 half transfer flag */ -#define DMA_ISR_HTIF3 (1 << 10) -/* TCIF3: Channel 3 transfer complete flag */ -#define DMA_ISR_TCIF3 (1 << 9) -/* GIF3: Channel 3 global interrupt flag */ -#define DMA_ISR_GIF3 (1 << 8) -/* TEIF2: Channel 2 transfer error flag */ -#define DMA_ISR_TEIF2 (1 << 7) -/* HTIF2: Channel 23 half transfer flag */ -#define DMA_ISR_HTIF2 (1 << 6) -/* TCIF2: Channel 2 transfer complete flag */ -#define DMA_ISR_TCIF2 (1 << 5) -/* GIF2: Channel 2 global interrupt flag */ -#define DMA_ISR_GIF2 (1 << 4) -/* TEIF1: Channel 1 transfer error flag */ -#define DMA_ISR_TEIF1 (1 << 3) -/* HTIF1: Channel 1 half transfer flag */ -#define DMA_ISR_HTIF1 (1 << 2) -/* TCIF1: Channel 1 transfer complete flag */ -#define DMA_ISR_TCIF1 (1 << 1) -/* GIF1: Channel 1 global interrupt flag */ -#define DMA_ISR_GIF1 (1 << 0) - -/* --- DMA_IFCR values ----------------------------------------------------- */ - -/* CTEIF7: Channel 7 transfer error clear */ -#define DMA_IFCR_CTEIF7 (1 << 27) -/* CHTIF7: Channel 7 half transfer clear */ -#define DMA_IFCR_CHTIF7 (1 << 26) -/* CTCIF7: Channel 7 transfer complete clear */ -#define DMA_IFCR_CTCIF7 (1 << 25) -/* CGIF7: Channel 7 global interrupt clear */ -#define DMA_IFCR_CGIF7 (1 << 24) -/* CTEIF6: Channel 6 transfer error clear */ -#define DMA_IFCR_CTEIF6 (1 << 23) -/* CHTIF6: Channel 6 half transfer clear */ -#define DMA_IFCR_CHTIF6 (1 << 22) -/* CTCIF6: Channel 6 transfer complete clear */ -#define DMA_IFCR_CTCIF6 (1 << 21) -/* CGIF6: Channel 6 global interrupt clear */ -#define DMA_IFCR_CGIF6 (1 << 20) -/* CTEIF5: Channel 5 transfer error clear */ -#define DMA_IFCR_CTEIF5 (1 << 19) -/* CHTIF5: Channel 5 half transfer clear */ -#define DMA_IFCR_CHTIF5 (1 << 18) -/* CTCIF5: Channel 5 transfer complete clear */ -#define DMA_IFCR_CTCIF5 (1 << 17) -/* CGIF5: Channel 5 global interrupt clear */ -#define DMA_IFCR_CGIF5 (1 << 16) -/* CTEIF4: Channel 4 transfer error clear */ -#define DMA_IFCR_CTEIF4 (1 << 15) -/* CHTIF4: Channel 4 half transfer clear */ -#define DMA_IFCR_CHTIF4 (1 << 14) -/* CTCIF4: Channel 4 transfer complete clear */ -#define DMA_IFCR_CTCIF4 (1 << 13) -/* CGIF4: Channel 4 global interrupt clear */ -#define DMA_IFCR_CGIF4 (1 << 12) -/* CTEIF3: Channel 3 transfer error clear */ -#define DMA_IFCR_CTEIF3 (1 << 11) -/* CHTIF3: Channel 3 half transfer clear */ -#define DMA_IFCR_CHTIF3 (1 << 10) -/* CTCIF3: Channel 3 transfer complete clear */ -#define DMA_IFCR_CTCIF3 (1 << 9) -/* CGIF3: Channel 3 global interrupt clear */ -#define DMA_IFCR_CGIF3 (1 << 8) -/* CTEIF2: Channel 2 transfer error clear */ -#define DMA_IFCR_CTEIF2 (1 << 7) -/* CHTIF2: Channel 2 half transfer clear */ -#define DMA_IFCR_CHTIF2 (1 << 6) -/* CTCIF2: Channel 2 transfer complete clear */ -#define DMA_IFCR_CTCIF2 (1 << 5) -/* CGIF2: Channel 2 global interrupt clear */ -#define DMA_IFCR_CGIF2 (1 << 4) -/* CTEIF1: Channel 1 transfer error clear */ -#define DMA_IFCR_CTEIF1 (1 << 3) -/* CHTIF1: Channel 1 half transfer clear */ -#define DMA_IFCR_CHTIF1 (1 << 2) -/* CTCIF1: Channel 1 transfer complete clear */ -#define DMA_IFCR_CTCIF1 (1 << 1) -/* CGIF1: Channel 1 global interrupt clear */ -#define DMA_IFCR_CGIF1 (1 << 0) - -/* --- DMA_CCR1 values ----------------------------------------------------- */ - -/* MEM2MEM: Memory to memory mode */ -#define DMA_CCR1_MEM2MEM (1 << 14) - -/* PL[13:12]: Channel priority level */ -#define DMA_CCR1_PL_LSB 12 -#define DMA_CCR1_PL_LOW 0x0 -#define DMA_CCR1_PL_MEDIUM 0x1 -#define DMA_CCR1_PL_HIGH 0x2 -#define DMA_CCR1_PL_VERY_HIGH 0x3 - -/* MSIZE[11:10]: Memory size */ -#define DMA_CCR1_MSIZE_LSB 10 -#define DMA_CCR1_MSIZE_8BIT 0x0 -#define DMA_CCR1_MSIZE_16BIT 0x1 -#define DMA_CCR1_MSIZE_32BIT 0x2 - -/* PSIZE[9:8]: Peripheral size */ -#define DMA_CCR1_PSIZE_LSB 8 -#define DMA_CCR1_PSIZE_8BIT 0x0 -#define DMA_CCR1_PSIZE_16BIT 0x1 -#define DMA_CCR1_PSIZE_32BIT 0x2 - -/* MINC: Memory increment mode */ -#define DMA_CCR1_MINC (1 << 7) - -/* PINC: Peripheral increment mode */ -#define DMA_CCR1_PINC (1 << 6) - -/* CIRC: Circular mode */ -#define DMA_CCR1_CIRC (1 << 5) - -/* DIR: Data transfer direction */ -#define DMA_CCR1_DIR (1 << 4) - -/* TEIE: Transfer error interrupt enable */ -#define DMA_CCR1_TEIE (1 << 3) - -/* HTIE: Half transfer interrupt enable */ -#define DMA_CCR1_HTIE (1 << 2) - -/* TCIE: Transfer complete interrupt enable */ -#define DMA_CCR1_TCIE (1 << 1) - -/* EN: Channel enable */ -#define DMA_CCR1_EN (1 << 0) - -/* --- DMA_CCR2 values ----------------------------------------------------- */ - -/* MEM2MEM: Memory to memory mode */ -#define DMA_CCR2_MEM2MEM (1 << 14) - -/* PL[13:12]: Channel priority level */ -#define DMA_CCR2_PL_LSB 12 -#define DMA_CCR2_PL_LOW 0x0 -#define DMA_CCR2_PL_MEDIUM 0x1 -#define DMA_CCR2_PL_HIGH 0x2 -#define DMA_CCR2_PL_VERY_HIGH 0x3 - -/* MSIZE[11:10]: Memory size */ -#define DMA_CCR2_MSIZE_LSB 10 -#define DMA_CCR2_MSIZE_8BIT 0x0 -#define DMA_CCR2_MSIZE_16BIT 0x1 -#define DMA_CCR2_MSIZE_32BIT 0x2 - -/* PSIZE[9:8]: Peripheral size */ -#define DMA_CCR2_PSIZE_LSB 8 -#define DMA_CCR2_PSIZE_8BIT 0x0 -#define DMA_CCR2_PSIZE_16BIT 0x1 -#define DMA_CCR2_PSIZE_32BIT 0x2 - -/* MINC: Memory increment mode */ -#define DMA_CCR2_MINC (1 << 7) - -/* PINC: Peripheral increment mode */ -#define DMA_CCR2_PINC (1 << 6) - -/* CIRC: Circular mode */ -#define DMA_CCR2_CIRC (1 << 5) - -/* DIR: Data transfer direction */ -#define DMA_CCR2_DIR (1 << 4) - -/* TEIE: Transfer error interrupt enable */ -#define DMA_CCR2_TEIE (1 << 3) - -/* HTIE: Half transfer interrupt enable */ -#define DMA_CCR2_HTIE (1 << 2) - -/* TCIE: Transfer complete interrupt enable */ -#define DMA_CCR2_TCIE (1 << 1) - -/* EN: Channel enable */ -#define DMA_CCR2_EN (1 << 0) - -/* --- DMA_CCR3 values ----------------------------------------------------- */ - -/* MEM2MEM: Memory to memory mode */ -#define DMA_CCR3_MEM2MEM (1 << 14) - -/* PL[13:12]: Channel priority level */ -#define DMA_CCR3_PL_LSB 12 -#define DMA_CCR3_PL_LOW 0x0 -#define DMA_CCR3_PL_MEDIUM 0x1 -#define DMA_CCR3_PL_HIGH 0x2 -#define DMA_CCR3_PL_VERY_HIGH 0x3 - -/* MSIZE[11:10]: Memory size */ -#define DMA_CCR3_MSIZE_LSB 10 -#define DMA_CCR3_MSIZE_8BIT 0x0 -#define DMA_CCR31_MSIZE_16BIT 0x1 -#define DMA_CCR3_MSIZE_32BIT 0x2 - -/* PSIZE[9:8]: Peripheral size */ -#define DMA_CCR3_PSIZE_LSB 8 -#define DMA_CCR3_PSIZE_8BIT 0x0 -#define DMA_CCR3_PSIZE_16BIT 0x1 -#define DMA_CCR3_PSIZE_32BIT 0x2 - -/* MINC: Memory increment mode */ -#define DMA_CCR3_MINC (1 << 7) - -/* PINC: Peripheral increment mode */ -#define DMA_CCR3_PINC (1 << 6) - -/* CIRC: Circular mode */ -#define DMA_CCR3_CIRC (1 << 5) - -/* DIR: Data transfer direction */ -#define DMA_CCR3_DIR (1 << 4) - -/* TEIE: Transfer error interrupt enable */ -#define DMA_CCR3_TEIE (1 << 3) - -/* HTIE: Half transfer interrupt enable */ -#define DMA_CCR3_HTIE (1 << 2) - -/* TCIE: Transfer complete interrupt enable */ -#define DMA_CCR3_TCIE (1 << 1) - -/* EN: Channel enable */ -#define DMA_CCR3_EN (1 << 0) - -/* --- DMA_CCR4 values ----------------------------------------------------- */ - -/* MEM2MEM: Memory to memory mode */ -#define DMA_CCR4_MEM2MEM (1 << 14) - -/* PL[13:12]: Channel priority level */ -#define DMA_CCR4_PL_LSB 12 -#define DMA_CCR4_PL_LOW 0x0 -#define DMA_CCR4_PL_MEDIUM 0x1 -#define DMA_CCR4_PL_HIGH 0x2 -#define DMA_CCR4_PL_VERY_HIGH 0x3 - -/* MSIZE[11:10]: Memory size */ -#define DMA_CCR4_MSIZE_LSB 10 -#define DMA_CCR4_MSIZE_8BIT 0x0 -#define DMA_CCR4_MSIZE_16BIT 0x1 -#define DMA_CCR4_MSIZE_32BIT 0x2 - -/* PSIZE[9:8]: Peripheral size */ -#define DMA_CCR4_PSIZE_LSB 8 -#define DMA_CCR4_PSIZE_8BIT 0x0 -#define DMA_CCR4_PSIZE_16BIT 0x1 -#define DMA_CCR4_PSIZE_32BIT 0x2 - -/* MINC: Memory increment mode */ -#define DMA_CCR4_MINC (1 << 7) - -/* PINC: Peripheral increment mode */ -#define DMA_CCR4_PINC (1 << 6) - -/* CIRC: Circular mode */ -#define DMA_CCR4_CIRC (1 << 5) - -/* DIR: Data transfer direction */ -#define DMA_CCR4_DIR (1 << 4) - -/* TEIE: Transfer error interrupt enable */ -#define DMA_CCR4_TEIE (1 << 3) - -/* HTIE: Half transfer interrupt enable */ -#define DMA_CCR4_HTIE (1 << 2) - -/* TCIE: Transfer complete interrupt enable */ -#define DMA_CCR4_TCIE (1 << 1) - -/* EN: Channel enable */ -#define DMA_CCR4_EN (1 << 0) - -/* --- DMA_CCR5 values ----------------------------------------------------- */ - -/* MEM2MEM: Memory to memory mode */ -#define DMA_CCR5_MEM2MEM (1 << 14) - -/* PL[13:12]: Channel priority level */ -#define DMA_CCR5_PL_LSB 12 -#define DMA_CCR5_PL_LOW 0x0 -#define DMA_CCR5_PL_MEDIUM 0x1 -#define DMA_CCR5_PL_HIGH 0x2 -#define DMA_CCR5_PL_VERY_HIGH 0x3 - -/* MSIZE[11:10]: Memory size */ -#define DMA_CCR5_MSIZE_LSB 10 -#define DMA_CCR5_MSIZE_8BIT 0x0 -#define DMA_CCR5_MSIZE_16BIT 0x1 -#define DMA_CCR5_MSIZE_32BIT 0x2 - -/* PSIZE[9:8]: Peripheral size */ -#define DMA_CCR5_PSIZE_LSB 8 -#define DMA_CCR5_PSIZE_8BIT 0x0 -#define DMA_CCR5_PSIZE_16BIT 0x1 -#define DMA_CCR5_PSIZE_32BIT 0x2 - -/* MINC: Memory increment mode */ -#define DMA_CCR5_MINC (1 << 7) - -/* PINC: Peripheral increment mode */ -#define DMA_CCR5_PINC (1 << 6) - -/* CIRC: Circular mode */ -#define DMA_CCR5_CIRC (1 << 5) - -/* DIR: Data transfer direction */ -#define DMA_CCR5_DIR (1 << 4) - -/* TEIE: Transfer error interrupt enable */ -#define DMA_CCR5_TEIE (1 << 3) - -/* HTIE: Half transfer interrupt enable */ -#define DMA_CCR5_HTIE (1 << 2) - -/* TCIE: Transfer complete interrupt enable */ -#define DMA_CCR5_TCIE (1 << 1) - -/* EN: Channel enable */ -#define DMA_CCR5_EN (1 << 0) - -/* --- DMA_CCR6 values ----------------------------------------------------- */ - -/* MEM2MEM: Memory to memory mode */ -#define DMA_CCR6_MEM2MEM (1 << 14) - -/* PL[13:12]: Channel priority level */ -#define DMA_CCR6_PL_LSB 12 -#define DMA_CCR6_PL_LOW 0x0 -#define DMA_CCR6_PL_MEDIUM 0x1 -#define DMA_CCR6_PL_HIGH 0x2 -#define DMA_CCR6_PL_VERY_HIGH 0x3 - -/* MSIZE[11:10]: Memory size */ -#define DMA_CCR6_MSIZE_LSB 10 -#define DMA_CCR6_MSIZE_8BIT 0x0 -#define DMA_CCR6_MSIZE_16BIT 0x1 -#define DMA_CCR6_MSIZE_32BIT 0x2 - -/* PSIZE[9:8]: Peripheral size */ -#define DMA_CCR6_PSIZE_LSB 8 -#define DMA_CCR6_PSIZE_8BIT 0x0 -#define DMA_CCR6_PSIZE_16BIT 0x1 -#define DMA_CCR6_PSIZE_32BIT 0x2 - -/* MINC: Memory increment mode */ -#define DMA_CCR6_MINC (1 << 7) - -/* PINC: Peripheral increment mode */ -#define DMA_CCR6_PINC (1 << 6) - -/* CIRC: Circular mode */ -#define DMA_CCR6_CIRC (1 << 5) - -/* DIR: Data transfer direction */ -#define DMA_CCR6_DIR (1 << 4) - -/* TEIE: Transfer error interrupt enable */ -#define DMA_CCR6_TEIE (1 << 3) - -/* HTIE: Half transfer interrupt enable */ -#define DMA_CCR6_HTIE (1 << 2) - -/* TCIE: Transfer complete interrupt enable */ -#define DMA_CCR6_TCIE (1 << 1) - -/* EN: Channel enable */ -#define DMA_CCR6_EN (1 << 0) - -/* --- DMA_CCR7 values ----------------------------------------------------- */ - -/* MEM2MEM: Memory to memory mode */ -#define DMA_CCR7_MEM2MEM (1 << 14) - -/* PL[13:12]: Channel priority level */ -#define DMA_CCR7_PL_LSB 12 -#define DMA_CCR7_PL_LOW 0x0 -#define DMA_CCR7_PL_MEDIUM 0x1 -#define DMA_CCR7_PL_HIGH 0x2 -#define DMA_CCR7_PL_VERY_HIGH 0x3 - -/* MSIZE[11:10]: Memory size */ -#define DMA_CCR7_MSIZE_LSB 10 -#define DMA_CCR7_MSIZE_8BIT 0x0 -#define DMA_CCR7_MSIZE_16BIT 0x1 -#define DMA_CCR7_MSIZE_32BIT 0x2 - -/* PSIZE[9:8]: Peripheral size */ -#define DMA_CCR7_PSIZE_LSB 8 -#define DMA_CCR7_PSIZE_8BIT 0x0 -#define DMA_CCR7_PSIZE_16BIT 0x1 -#define DMA_CCR7_PSIZE_32BIT 0x2 - -/* MINC: Memory increment mode */ -#define DMA_CCR7_MINC (1 << 7) - -/* PINC: Peripheral increment mode */ -#define DMA_CCR7_PINC (1 << 6) - -/* CIRC: Circular mode */ -#define DMA_CCR7_CIRC (1 << 5) - -/* DIR: Data transfer direction */ -#define DMA_CCR7_DIR (1 << 4) - -/* TEIE: Transfer error interrupt enable */ -#define DMA_CCR7_TEIE (1 << 3) - -/* HTIE: Half transfer interrupt enable */ -#define DMA_CCR7_HTIE (1 << 2) - -/* TCIE: Transfer complete interrupt enable */ -#define DMA_CCR7_TCIE (1 << 1) - -/* EN: Channel enable */ -#define DMA_CCR7_EN (1 << 0) - -/* --- DMA_CCRx generic values --------------------------------------------- */ - -/* MEM2MEM: Memory to memory mode */ -#define DMA_CCR_MEM2MEM (1 << 14) - -/* PL[13:12]: Channel priority level */ -#define DMA_CCR_PL_LSB 12 -#define DMA_CCR_PL_LOW 0x0 -#define DMA_CCR_PL_MEDIUM 0x1 -#define DMA_CCR_PL_HIGH 0x2 -#define DMA_CCR_PL_VERY_HIGH 0x3 - -/* MSIZE[11:10]: Memory size */ -#define DMA_CCR_MSIZE_LSB 10 -#define DMA_CCR_MSIZE_8BIT 0x0 -#define DMA_CCR_MSIZE_16BIT 0x1 -#define DMA_CCR_MSIZE_32BIT 0x2 - -/* PSIZE[9:8]: Peripheral size */ -#define DMA_CCR_PSIZE_LSB 8 -#define DMA_CCR_PSIZE_8BIT 0x0 -#define DMA_CCR_PSIZE_16BIT 0x1 -#define DMA_CCR_PSIZE_32BIT 0x2 - -/* MINC: Memory increment mode */ -#define DMA_CCR_MINC (1 << 7) - -/* PINC: Peripheral increment mode */ -#define DMA_CCR_PINC (1 << 6) - -/* CIRC: Circular mode */ -#define DMA_CCR_CIRC (1 << 5) - -/* DIR: Data transfer direction */ -#define DMA_CCR_DIR (1 << 4) - -/* TEIE: Transfer error interrupt enable */ -#define DMA_CCR_TEIE (1 << 3) - -/* HTIE: Half transfer interrupt enable */ -#define DMA_CCR_HTIE (1 << 2) - -/* TCIE: Transfer complete interrupt enable */ -#define DMA_CCR_TCIE (1 << 1) - -/* EN: Channel enable */ -#define DMA_CCR_EN (1 << 0) - -/* --- DMA_CNDTRx values --------------------------------------------------- */ - -/* NDT[15:0]: Number of data to transfer */ - -/* --- DMA_CPARx values ---------------------------------------------------- */ - -/* PA[31:0]: Peripheral address */ - -/* --- DMA_CMARx values ---------------------------------------------------- */ - -/* MA[31:0]: Memory address */ - -/* --- Generic values ------------------------------------------------------ */ - -#define DMA_CHANNEL1 1 -#define DMA_CHANNEL2 2 -#define DMA_CHANNEL3 3 -#define DMA_CHANNEL4 4 -#define DMA_CHANNEL5 5 -#define DMA_CHANNEL6 6 -#define DMA_CHANNEL7 7 - -/* --- function prototypes ------------------------------------------------- */ - -void dma_enable_mem2mem_mode(u32 dma, u8 channel); -void dma_set_priority(u32 dma, u8 channel, u8 prio); -void dma_set_memory_size(u32 dma, u8 channel, u8 mem_size); -void dma_set_peripheral_size(u32 dma, u8 channel, u8 peripheral_size); -void dma_enable_memory_increment_mode(u32 dma, u8 channel); -void dma_enable_peripheral_increment_mode(u32 dma, u8 channel); -void dma_enable_circular_mode(u32 dma, u8 channel); -void dma_set_read_from_peripheral(u32 dma, u8 channel); -void dma_set_read_from_memory(u32 dma, u8 channel); -void dma_enable_transfer_error_interrupt(u32 dma, u8 channel); -void dma_disable_transfer_error_interrupt(u32 dma, u8 channel); -void dma_enable_half_transfer_interrupt(u32 dma, u8 channel); -void dma_disable_half_transfer_interrupt(u32 dma, u8 channel); -void dma_enable_transfer_complete_interrupt(u32 dma, u8 channel); -void dma_disable_transfer_complete_interrupt(u32 dma, u8 channel); -void dma_enable_channel(u32 dma, u8 channel); -void dma_disable_channel(u32 dma, u8 channel); -void dma_set_peripheral_address(u32 dma, u8 channel, u32 address); -void dma_set_memory_address(u32 dma, u8 channel, u32 address); -void dma_set_number_of_data(u32 dma, u8 channel, u16 number); - -#endif diff --git a/include/libopencm3/stm32/ethernet.h b/include/libopencm3/stm32/ethernet.h deleted file mode 100644 index 3d7f1ee..0000000 --- a/include/libopencm3/stm32/ethernet.h +++ /dev/null @@ -1,203 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Gareth McMullin - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_ETHERNET_H -#define LIBOPENCM3_ETHERNET_H - -#include -#include - -/* Ethernet MAC registers */ -#define ETH_MACCR MMIO32(ETHERNET_BASE + 0x00) -#define ETH_MACFFR MMIO32(ETHERNET_BASE + 0x04) -#define ETH_MACHTHR MMIO32(ETHERNET_BASE + 0x08) -#define ETH_MACHTLR MMIO32(ETHERNET_BASE + 0x0C) -#define ETH_MACMIIAR MMIO32(ETHERNET_BASE + 0x10) -#define ETH_MACMIIDR MMIO32(ETHERNET_BASE + 0x14) -#define ETH_MACFCR MMIO32(ETHERNET_BASE + 0x18) -#define ETH_MACVLANTR MMIO32(ETHERNET_BASE + 0x1C) -#define ETH_MACRWUFFR MMIO32(ETHERNET_BASE + 0x28) -#define ETH_MACPMTCSR MMIO32(ETHERNET_BASE + 0x2C) -#define ETH_MACSR MMIO32(ETHERNET_BASE + 0x38) -#define ETH_MACIMR MMIO32(ETHERNET_BASE + 0x3C) -#define ETH_MACA0HR MMIO32(ETHERNET_BASE + 0x40) -#define ETH_MACA0LR MMIO32(ETHERNET_BASE + 0x44) -#define ETH_MACA1HR MMIO32(ETHERNET_BASE + 0x48) -#define ETH_MACA1LR MMIO32(ETHERNET_BASE + 0x4C) -#define ETH_MACA2HR MMIO32(ETHERNET_BASE + 0x50) -#define ETH_MACA2LR MMIO32(ETHERNET_BASE + 0x54) -#define ETH_MACA3HR MMIO32(ETHERNET_BASE + 0x58) -#define ETH_MACA3LR MMIO32(ETHERNET_BASE + 0x5C) - -/* Ethernet MMC registers */ -#define ETH_MMCCR MMIO32(ETHERNET_BASE + 0x100) -#define ETH_MMCRIR MMIO32(ETHERNET_BASE + 0x104) -#define ETH_MMCTIR MMIO32(ETHERNET_BASE + 0x108) -#define ETH_MMCRIMR MMIO32(ETHERNET_BASE + 0x10C) -#define ETH_MMCTIMR MMIO32(ETHERNET_BASE + 0x110) -#define ETH_MMCTGFSCCR MMIO32(ETHERNET_BASE + 0x14C) -#define ETH_MMCTGFMSCCR MMIO32(ETHERNET_BASE + 0x150) -#define ETH_MMCTGFCR MMIO32(ETHERNET_BASE + 0x168) -#define ETH_MMCRFCECR MMIO32(ETHERNET_BASE + 0x194) -#define ETH_MMCRFAECR MMIO32(ETHERNET_BASE + 0x198) -#define ETH_MMCRGUFCR MMIO32(ETHERNET_BASE + 0x1C4) - -/* Ethrenet IEEE 1588 time stamp registers */ -#define ETH_PTPTSCR MMIO32(ETHERNET_BASE + 0x700) -#define ETH_PTPSSIR MMIO32(ETHERNET_BASE + 0x704) -#define ETH_PTPTSHR MMIO32(ETHERNET_BASE + 0x708) -#define ETH_PTPTSLR MMIO32(ETHERNET_BASE + 0x70C) -#define ETH_PTPTSHUR MMIO32(ETHERNET_BASE + 0x710) -#define ETH_PTPTSLUR MMIO32(ETHERNET_BASE + 0x714) -#define ETH_PTPTSAR MMIO32(ETHERNET_BASE + 0x718) -#define ETH_PTPTTHR MMIO32(ETHERNET_BASE + 0x71C) -#define ETH_PTPTTLR MMIO32(ETHERNET_BASE + 0x720) - -/* Ethernet DMA registers */ -#define ETH_DMABMR MMIO32(ETHERNET_BASE + 0x1000) -#define ETH_DMATPDR MMIO32(ETHERNET_BASE + 0x1004) -#define ETH_DMARPDR MMIO32(ETHERNET_BASE + 0x1008) -#define ETH_DMARDLAR MMIO32(ETHERNET_BASE + 0x100C) -#define ETH_DMATDLAR MMIO32(ETHERNET_BASE + 0x1010) -#define ETH_DMATDLAR MMIO32(ETHERNET_BASE + 0x1010) -#define ETH_DMASR MMIO32(ETHERNET_BASE + 0x1014) -#define ETH_DMAOMR MMIO32(ETHERNET_BASE + 0x1018) -#define ETH_DMAIER MMIO32(ETHERNET_BASE + 0x101C) -#define ETH_DMAMFBOCR MMIO32(ETHERNET_BASE + 0x1020) -#define ETH_DMACHTDR MMIO32(ETHERNET_BASE + 0x1048) -#define ETH_DMACHRDR MMIO32(ETHERNET_BASE + 0x104C) -#define ETH_DMACHTBAR MMIO32(ETHERNET_BASE + 0x1050) -#define ETH_DMACHRBAR MMIO32(ETHERNET_BASE + 0x1054) - -/* Ethernet MAC Register bit definitions */ -/* Ethernet MAC configuration register ETH_MACCR bits */ -#define ETH_MACCR_RE 0x00000004 -#define ETH_MACCR_TE 0x00000008 -#define ETH_MACCR_DC 0x00000010 -#define ETH_MACCR_BL 0x00000060 -#define ETH_MACCR_APCS 0x00000080 -#define ETH_MACCR_RD 0x00000200 -#define ETH_MACCR_IPCO 0x00000400 -#define ETH_MACCR_DM 0x00000800 -#define ETH_MACCR_LM 0x00001000 -#define ETH_MACCR_ROD 0x00002000 -#define ETH_MACCR_FES 0x00004000 -#define ETH_MACCR_CSD 0x00010000 -#define ETH_MACCR_IFG 0x000E0000 -#define ETH_MACCR_JD 0x00400000 -#define ETH_MACCR_WD 0x00800000 - -/* Ethernet MAC frame filter register ETH_MACFFR bits */ -#define ETH_MACFFR_PM 0x00000001 -#define ETH_MACFFR_HU 0x00000002 -#define ETH_MACFFR_HM 0x00000004 -#define ETH_MACFFR_DAIF 0x00000008 -#define ETH_MACFFR_PAM 0x00000010 -#define ETH_MACFFR_BFD 0x00000020 -#define ETH_MACFFR_PCF 0x000000C0 -#define ETH_MACFFR_SAIF 0x00000100 -#define ETH_MACFFR_SAF 0x00000200 -#define ETH_MACFFR_HPF 0x00000400 -#define ETH_MACFFR_PA 0x80000000 - -/* Ethernet MAC MII address register ETH_MACMIIAR bits */ -#define ETH_MACMIIAR_MB 0x0001 -#define ETH_MACMIIAR_MW 0x0002 -/* Clock Range for MDC frequency */ -#define ETH_MACMIIAR_CR_MASK 0x001C -#define ETH_MACMIIAR_CR_HCLK_DIV_42 0x0000 /* For HCLK 60-72 MHz */ -#define ETH_MACMIIAR_CR_HCLK_DIV_16 0x0008 /* For HCLK 20-35 MHz */ -#define ETH_MACMIIAR_CR_HCLK_DIV_24 0x000C /* For HCLK 35-60 MHz */ -#define ETH_MACMIIAR_MR 0x07C0 -#define ETH_MACMIIAR_PA 0xF800 - -/* Ethernet MAC flow control register ETH_MACFCR bits */ -#define ETH_MACFCR_FCB 0x00000001 -#define ETH_MACFCR_BPA 0x00000001 -#define ETH_MACFCR_TFCE 0x00000002 -#define ETH_MACFCR_RFCE 0x00000004 -#define ETH_MACFCR_UPFD 0x00000008 -#define ETH_MACFCR_PLT 0x00000030 -#define ETH_MACFCR_ZQPD 0x00000080 -#define ETH_MACFCR_PT 0xFFFF0000 - -/* Ethernet MAC interrupt status regster ETH_MACSR bits */ -#define ETH_MACSR_PMTS 0x0008 -#define ETH_MACSR_MMCS 0x0010 -#define ETH_MACSR_MMCRS 0x0020 -#define ETH_MACSR_MMCTS 0x0040 -#define ETH_MACSR_TSTS 0x0200 - -/* Ethernet MAC interrupt mask regster ETH_MACIMR bits */ -#define ETH_MACIMR_PMTIM 0x0008 -#define ETH_MACIMR_TSTIM 0x0200 - -/* Ethernet DMA Register bit definitions */ -/* Ethernet DMA bus mode register ETH_DMABMR bits */ -#define ETH_DMABMR_SR 0x00000001 -#define ETH_DMABMR_DA 0x00000002 -#define ETH_DMABMR_DSL_MASK 0x0000007C -#define ETH_DMABMR_PBL_MASK 0x00003F00 -#define ETH_DMABMR_RTPR_MASK 0x0000C000 -#define ETH_DMABMR_RTPR_1TO1 0x00000000 -#define ETH_DMABMR_RTPR_2TO1 0x00004000 -#define ETH_DMABMR_RTPR_3TO1 0x00008000 -#define ETH_DMABMR_RTPR_4TO1 0x0000C000 -#define ETH_DMABMR_FB 0x00010000 -#define ETH_DMABMR_RDP_MASK 0x007E0000 -#define ETH_DMABMR_USP 0x00800000 -#define ETH_DMABMR_FPM 0x01000000 -#define ETH_DMABMR_AAB 0x02000000 - -/* Ethernet DMA operation mode register ETH_DMAOMR bits */ -#define ETH_DMAOMR_SR 0x00000002 -#define ETH_DMAOMR_OSF 0x00000004 -#define ETH_DMAOMR_RTC_MASK 0x00000018 -#define ETH_DMAOMR_RTC_64 0x00000000 -#define ETH_DMAOMR_RTC_32 0x00000008 -#define ETH_DMAOMR_RTC_96 0x00000010 -#define ETH_DMAOMR_RTC_128 0x00000018 -#define ETH_DMAOMR_FUGF 0x00000040 -#define ETH_DMAOMR_FEF 0x00000080 -#define ETH_DMAOMR_ST 0x00002000 -#define ETH_DMAOMR_TTC_MASK 0x0001C000 -#define ETH_DMAOMR_FTF 0x00100000 -#define ETH_DMAOMR_TSF 0x00200000 -#define ETH_DMAOMR_DFRF 0x01000000 -#define ETH_DMAOMR_RSF 0x02000000 -#define ETH_DMAOMR_DTCEFD 0x04000000 - -/* Ethernet DMA interrupt enable register ETH_DMAIER bits */ -#define ETH_DMAIER_TIE 0x00000001 -#define ETH_DMAIER_TPSIE 0x00000002 -#define ETH_DMAIER_TBUIE 0x00000004 -#define ETH_DMAIER_TJTIE 0x00000008 -#define ETH_DMAIER_ROIE 0x00000010 -#define ETH_DMAIER_TUIE 0x00000020 -#define ETH_DMAIER_RIE 0x00000040 -#define ETH_DMAIER_RBUIE 0x00000080 -#define ETH_DMAIER_RPSIE 0x00000100 -#define ETH_DMAIER_RWTIE 0x00000200 -#define ETH_DMAIER_ETIE 0x00000400 -#define ETH_DMAIER_FBEIE 0x00002000 -#define ETH_DMAIER_ERIE 0x00004000 -#define ETH_DMAIER_AISE 0x00008000 -#define ETH_DMAIER_NSIE 0x00010000 - -#endif diff --git a/include/libopencm3/stm32/exti.h b/include/libopencm3/stm32/exti.h deleted file mode 100644 index 19ab547..0000000 --- a/include/libopencm3/stm32/exti.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Mark Butler - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_EXTI_H -#define LIBOPENCM3_EXTI_H - -#include -#include - -/* --- EXTI registers ------------------------------------------------------ */ - -#define EXTI_IMR MMIO32(EXTI_BASE + 0x00) -#define EXTI_EMR MMIO32(EXTI_BASE + 0x04) -#define EXTI_RTSR MMIO32(EXTI_BASE + 0x08) -#define EXTI_FTSR MMIO32(EXTI_BASE + 0x0c) -#define EXTI_SWIER MMIO32(EXTI_BASE + 0x10) -#define EXTI_PR MMIO32(EXTI_BASE + 0x14) - -/* EXTI number definitions */ -#define EXTI0 (1 << 0) -#define EXTI1 (1 << 1) -#define EXTI2 (1 << 2) -#define EXTI3 (1 << 3) -#define EXTI4 (1 << 4) -#define EXTI5 (1 << 5) -#define EXTI6 (1 << 6) -#define EXTI7 (1 << 7) -#define EXTI8 (1 << 8) -#define EXTI9 (1 << 9) -#define EXTI10 (1 << 10) -#define EXTI11 (1 << 11) -#define EXTI12 (1 << 12) -#define EXTI13 (1 << 13) -#define EXTI14 (1 << 14) -#define EXTI15 (1 << 15) -#define EXTI16 (1 << 16) -#define EXTI17 (1 << 17) -#define EXTI18 (1 << 18) -#define EXTI19 (1 << 19) - -/* Trigger types */ -typedef enum trigger_e { - EXTI_TRIGGER_RISING, - EXTI_TRIGGER_FALLING, - EXTI_TRIGGER_BOTH, -} exti_trigger_type; - -void exti_set_trigger(u32 extis, exti_trigger_type trig); -void exti_enable_request(u32 extis); -void exti_disable_request(u32 extis); -void exti_reset_request(u32 extis); -void exti_select_source(u32 exti, u32 gpioport); - -#endif diff --git a/include/libopencm3/stm32/flash.h b/include/libopencm3/stm32/flash.h deleted file mode 100644 index f9b2aa9..0000000 --- a/include/libopencm3/stm32/flash.h +++ /dev/null @@ -1,113 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * Copyright (C) 2010 Mark Butler - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* - * For details see: - * PM0042 Programming manual: STM32F10xxx Flash programming - * October 2009, Doc ID 13259 Rev 7 - * http://www.st.com/stonline/products/literature/pm/13259.pdf - */ - -#ifndef LIBOPENCM3_FLASH_H -#define LIBOPENCM3_FLASH_H - -#include -#include - -/* --- FLASH registers ----------------------------------------------------- */ - -#define FLASH_ACR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x00) -#define FLASH_KEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x04) -#define FLASH_OPTKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x08) -#define FLASH_SR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x0C) -#define FLASH_CR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x10) -#define FLASH_AR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14) -#define FLASH_OBR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x1C) -#define FLASH_WRPR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x20) - -/* --- FLASH_ACR values ---------------------------------------------------- */ - -#define FLASH_PRFTBS (1 << 5) -#define FLASH_PRFTBE (1 << 4) -#define FLASH_HLFCYA (1 << 3) -#define FLASH_LATENCY_0WS 0x00 -#define FLASH_LATENCY_1WS 0x01 -#define FLASH_LATENCY_2WS 0x02 - -/* --- FLASH_SR values ----------------------------------------------------- */ - -#define FLASH_EOP (1 << 5) -#define FLASH_WRPRTERR (1 << 4) -#define FLASH_PGERR (1 << 2) -#define FLASH_BSY (1 << 0) - -/* --- FLASH_CR values ----------------------------------------------------- */ - -#define FLASH_EOPIE (1 << 12) -#define FLASH_ERRIE (1 << 10) -#define FLASH_OPTWRE (1 << 9) -#define FLASH_LOCK (1 << 7) -#define FLASH_STRT (1 << 6) -#define FLASH_OPTER (1 << 5) -#define FLASH_OPTPG (1 << 4) -#define FLASH_MER (1 << 2) -#define FLASH_PER (1 << 1) -#define FLASH_PG (1 << 0) - -/* --- FLASH_OBR values ---------------------------------------------------- */ - -/* FLASH_OBR[25:18]: Data1 */ -/* FLASH_OBR[17:10]: Data0 */ -#define FLASH_NRST_STDBY (1 << 4) -#define FLASH_NRST_STOP (1 << 3) -#define FLASH_WDG_SW (1 << 2) -#define FLASH_RDPRT (1 << 1) -#define FLASH_OPTERR (1 << 0) - -/* --- FLASH Keys -----------------------------------------------------------*/ - -#define RDP_KEY ((u16)0x00a5) -#define FLASH_KEY1 ((u32)0x45670123) -#define FLASH_KEY2 ((u32)0xcdef89ab) - -/* --- Function prototypes ------------------------------------------------- */ - -void flash_prefetch_buffer_enable(void); -void flash_prefetch_buffer_disable(void); -void flash_halfcycle_enable(void); -void flash_halfcycle_disable(void); -void flash_set_ws(u32 ws); -void flash_unlock(void); -void flash_lock(void); -void flash_clear_pgerr_flag(void); -void flash_clear_eop_flag(void); -void flash_clear_wrprterr_flag(void); -void flash_clear_bsy_flag(void); -void flash_clear_status_flags(void); -void flash_unlock_option_bytes(void); -void flash_erase_all_pages(void); -void flash_erase_page(u32 page_address); -void flash_program_word(u32 address, u32 data); -void flash_program_half_word(u32 address, u16 data); -void flash_wait_for_last_operation(void); -void flash_erase_option_bytes(void); -void flash_program_option_bytes(u32 address, u16 data); - -#endif diff --git a/include/libopencm3/stm32/fsmc.h b/include/libopencm3/stm32/fsmc.h deleted file mode 100644 index 1d318e3..0000000 --- a/include/libopencm3/stm32/fsmc.h +++ /dev/null @@ -1,284 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_FSMC_H -#define LIBOPENCM3_FSMC_H - -#include -#include - -/* --- Convenience macros -------------------------------------------------- */ - -/* TODO: Move to memorymap.h? */ -#define FSMC_BASE 0xa0000000 - -#define FSMC_BANK1_BASE 0x60000000 /* NOR / PSRAM */ -#define FSMC_BANK2_BASE 0x70000000 /* NAND flash */ -#define FSMC_BANK3_BASE 0x80000000 /* NAND flash */ -#define FSMC_BANK4_BASE 0x90000000 /* PC card */ - -/* --- FSMC registers ------------------------------------------------------ */ - -/* SRAM/NOR-Flash chip-select control registers 1..4 (FSMC_BCRx) */ -#define FSMC_BCR(x) MMIO32(FSMC_BASE + 0x00 + 8 * x) -#define FSMC_BCR1 FSMC_BCR(0) -#define FSMC_BCR2 FSMC_BCR(1) -#define FSMC_BCR3 FSMC_BCR(2) -#define FSMC_BCR4 FSMC_BCR(3) - -/* SRAM/NOR-Flash chip-select timing registers 1..4 (FSMC_BTRx) */ -#define FSMC_BTR(x) MMIO32(FSMC_BASE + 0x04 + 8 * x) -#define FSMC_BTR1 FSMC_BTR(0) -#define FSMC_BTR2 FSMC_BTR(1) -#define FSMC_BTR3 FSMC_BTR(2) -#define FSMC_BTR4 FSMC_BTR(3) - -/* SRAM/NOR-Flash write timing registers 1..4 (FSMC_BWTRx) */ -#define FSMC_BWTR(x) MMIO32(FSMC_BASE + 0x104 + 8 * x) -#define FSMC_BWTR1 FSMC_BWTR(0) -#define FSMC_BWTR2 FSMC_BWTR(1) -#define FSMC_BWTR3 FSMC_BWTR(2) -#define FSMC_BWTR4 FSMC_BWTR(3) - -/* PC Card/NAND Flash control registers 2..4 (FSMC_PCRx) */ -#define FSMC_PCR(x) MMIO32(FSMC_BASE + 0x40 + 0x20 * x) -#define FSMC_PCR2 FSMC_PCR(1) -#define FSMC_PCR3 FSMC_PCR(2) -#define FSMC_PCR4 FSMC_PCR(3) - -/* FIFO status and interrupt registers 2..4 (FSMC_SRx) */ -#define FSMC_SR(x) MMIO32(FSMC_BASE + 0x44 + 0x20 * x) -#define FSMC_SR2 FSMC_SR(1) -#define FSMC_SR3 FSMC_SR(2) -#define FSMC_SR4 FSMC_SR(3) - -/* Common memory space timing registers 2..4 (FSMC_PMEMx) */ -#define FSMC_PMEM(x) MMIO32(FSMC_BASE + 0x48 + 0x20 * x) -#define FSMC_PMEM2 FSMC_PMEM(1) -#define FSMC_PMEM3 FSMC_PMEM(2) -#define FSMC_PMEM4 FSMC_PMEM(3) - -/* Attribute memory space timing registers 2..4 (FSMC_PATTx) */ -#define FSMC_PATT(x) MMIO32(FSMC_BASE + 0x4c + 0x20 * x) -#define FSMC_PATT2 FSMC_PATT(1) -#define FSMC_PATT3 FSMC_PATT(2) -#define FSMC_PATT4 FSMC_PATT(3) - -/* I/O space timing register 4 (FSMC_PIO4) */ -#define FSMC_PIO4 MMIO32(FSMC_BASE + 0xb0) - -/* ECC result registers 2/3 (FSMC_ECCRx) */ -#define FSMC_ECCR(x) MMIO32(FSMC_BASE + 0x54 + 0x20 * x) -#define FSMC_ECCR2 FSMC_ECCR(1) -#define FSMC_ECCR3 FSMC_ECCR(2) - -/* --- FSMC_BCRx values ---------------------------------------------------- */ - -/* CBURSTRW: Write burst enable */ -#define FSMC_BCR_CBURSTRW (1 << 19) - -/* Bits 18..16: Reserved. */ - -/* ASYNCWAIT: Wait signal during asynchronous transfers */ -#define FSMC_BCR_ASYNCWAIT (1 << 15) - -/* EXTMOD: Extended mode enable */ -#define FSMC_BCR_EXTMOD (1 << 14) - -/* WAITEN: Wait enable bit */ -#define FSMC_BCR_WAITEN (1 << 13) - -/* WREN: Write enable bit */ -#define FSMC_BCR_WREN (1 << 12) - -/* WAITCFG: Wait timing configuration */ -#define FSMC_BCR_WAITCFG (1 << 11) - -/* WRAPMOD: Wrapped burst mode support */ -#define FSMC_BCR_WRAPMOD (1 << 10) - -/* WAITPOL: Wait signal polarity bit */ -#define FSMC_BCR_WAITPOL (1 << 9) - -/* BURSTEN: Burst enable bit */ -#define FSMC_BCR_BURSTEN (1 << 8) - -/* Bit 7: Reserved. */ - -/* FACCEN: Flash access enable */ -#define FSMC_BCR_FACCEN (1 << 6) - -/* MWID[5:4]: Memory databus width */ -#define FSMC_BCR_MWID (1 << 4) - -/* MTYP[3:2]: Memory type */ -#define FSMC_BCR_MTYP (1 << 2) - -/* MUXEN: Address/data multiplexing enable bit */ -#define FSMC_BCR_MUXEN (1 << 1) - -/* MBKEN: Memory bank enable bit */ -#define FSMC_BCR_MBKEN (1 << 0) - -/* --- FSMC_BTRx values ---------------------------------------------------- */ - -/* ACCMOD[29:28]: Access mode */ -#define FSMC_BTR_ACCMOD (1 << 28) - -/* DATLAT[27:24]: Data latency (for synchronous burst NOR flash) */ -#define FSMC_BTR_DATLAT (1 << 24) - -/* CLKDIV[23:20]: Clock divide ratio (for CLK signal) */ -#define FSMC_BTR_CLKDIV (1 << 20) - -/* BUSTURN[19:16]: Bus turnaround phase duration */ -#define FSMC_BTR_BUSTURN (1 << 16) - -/* DATAST[15:8]: Data-phase duration */ -#define FSMC_BTR_DATAST (1 << 8) - -/* ADDHLD[7:4]: Address-hold phase duration */ -#define FSMC_BTR_ADDHLD (1 << 4) - -/* ADDSET[3:0]: Address setup phase duration */ -#define FSMC_BTR_ADDSET (1 << 0) - -/* --- FSMC_BWTRx values --------------------------------------------------- */ - -/* ACCMOD[29:28]: Access mode */ -#define FSMC_BWTR_ACCMOD (1 << 28) - -/* DATLAT[27:24]: Data latency (for synchronous burst NOR Flash) */ -#define FSMC_BWTR_DATLAT (1 << 24) - -/* CLKDIV[23:20]: Clock divide ratio (for CLK signal) */ -#define FSMC_BWTR_CLKDIV (1 << 20) - -/* Bits 19..16: Reserved. */ - -/* DATAST[15:8]: Data-phase duration */ -#define FSMC_BWTR_DATAST (1 << 8) - -/* ADDHLD[7:4]: Address-hold phase duration */ -#define FSMC_BWTR_ADDHLD (1 << 4) - -/* ADDSET[3:0]: Address setup phase duration */ -#define FSMC_BWTR_ADDSET (1 << 0) - -/* --- FSMC_PCRx values ---------------------------------------------------- */ - -/* ECCPS[19:17]: ECC page size */ -#define FSMC_PCR_ECCPS (1 << 17) - -/* TAR[16:13]: ALE to RE delay */ -#define FSMC_PCR_TAR (1 << 13) - -/* TCLR[12:9]: CLE to RE delay */ -#define FSMC_PCR_TCLR (1 << 9) - -/* Bits 8..7: Reserved. */ - -/* ECCEN: ECC computation logic enable bit */ -#define FSMC_PCR_ECCEN (1 << 6) - -/* PWID[5:4]: Databus width */ -#define FSMC_PCR_PWID (1 << 4) - -/* PTYP: Memory type */ -#define FSMC_PCR_PTYP (1 << 3) - -/* PBKEN: PC Card/NAND Flash memory bank enable bit */ -#define FSMC_PCR_PBKEN (1 << 2) - -/* PWAITEN: Wait feature enable bit */ -#define FSMC_PCR_PWAITEN (1 << 1) - -/* Bit 0: Reserved. */ - -/* --- FSMC_SRx values ----------------------------------------------------- */ - -/* FEMPT: FIFO empty */ -#define FSMC_SR_FEMPT (1 << 6) - -/* IFEN: Interrupt falling edge detection enable bit */ -#define FSMC_SR_IFEN (1 << 5) - -/* ILEN: Interrupt high-level detection enable bit */ -#define FSMC_SR_ILEN (1 << 4) - -/* IREN: Interrupt rising edge detection enable bit */ -#define FSMC_SR_IREN (1 << 3) - -/* IFS: Interrupt falling edge status */ -#define FSMC_SR_IFS (1 << 2) - -/* ILS: Interrupt high-level status */ -#define FSMC_SR_ILS (1 << 1) - -/* IRS: Interrupt rising edge status */ -#define FSMC_SR_IRS (1 << 0) - -/* --- FSMC_PMEMx values --------------------------------------------------- */ - -/* MEMHIZx[31:24]: Common memory x databus HiZ time */ -#define FSMC_PMEM_MEMHIZX (1 << 24) - -/* MEMHOLDx[23:16]: Common memory x hold time */ -#define FSMC_PMEM_MEMHOLDX (1 << 16) - -/* MEMWAITx[15:8]: Common memory x wait time */ -#define FSMC_PMEM_MEMHOLDX (1 << 8) - -/* MEMSETx[7:0]: Common memory x setup time */ -#define FSMC_PMEM_MEMSETX (1 << 0) - -/* --- FSMC_PATTx values --------------------------------------------------- */ - -/* ATTHIZx[31:24]: Attribute memory x databus HiZ time */ -#define FSMC_PATT_ATTHIZX (1 << 24) - -/* ATTHOLDx[23:16]: Attribute memory x hold time */ -#define FSMC_PATT_ATTHOLDX (1 << 16) - -/* ATTWAITx[15:8]: Attribute memory x wait time */ -#define FSMC_PATT_ATTWAITX (1 << 8) - -/* ATTSETx[7:0]: Attribute memory x setup time */ -#define FSMC_PATT_ATTSETX (1 << 0) - -/* --- FSMC_PIO4 values ---------------------------------------------------- */ - -/* IOHIZx[31:24]: I/O x databus HiZ time */ -#define FSMC_PIO4_IOHIZX (1 << 24) - -/* IOHOLDx[23:16]: I/O x hold time */ -#define FSMC_PIO4_IOHOLDX (1 << 16) - -/* IOWAITx[15:8]: I/O x wait time */ -#define FSMC_PIO4_IOWAITX (1 << 8) - -/* IOSETx[7:0]: I/O x setup time */ -#define FSMC_PIO4_IOSETX (1 << 0) - -/* --- FSMC_ECCRx values --------------------------------------------------- */ - -/* ECCx[31:0]: ECC result */ -#define FSMC_ECCR_ECCX (1 << 0) - -#endif diff --git a/include/libopencm3/stm32/gpio.h b/include/libopencm3/stm32/gpio.h deleted file mode 100644 index f1463a3..0000000 --- a/include/libopencm3/stm32/gpio.h +++ /dev/null @@ -1,555 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_GPIO_H -#define LIBOPENCM3_GPIO_H - -#include -#include - -/* --- Convenience macros -------------------------------------------------- */ - -/* GPIO port base addresses (for convenience) */ -#define GPIOA GPIO_PORT_A_BASE -#define GPIOB GPIO_PORT_B_BASE -#define GPIOC GPIO_PORT_C_BASE -#define GPIOD GPIO_PORT_D_BASE -#define GPIOE GPIO_PORT_E_BASE -#define GPIOF GPIO_PORT_F_BASE -#define GPIOG GPIO_PORT_G_BASE - -/* GPIO number definitions (for convenience) */ -#define GPIO0 (1 << 0) -#define GPIO1 (1 << 1) -#define GPIO2 (1 << 2) -#define GPIO3 (1 << 3) -#define GPIO4 (1 << 4) -#define GPIO5 (1 << 5) -#define GPIO6 (1 << 6) -#define GPIO7 (1 << 7) -#define GPIO8 (1 << 8) -#define GPIO9 (1 << 9) -#define GPIO10 (1 << 10) -#define GPIO11 (1 << 11) -#define GPIO12 (1 << 12) -#define GPIO13 (1 << 13) -#define GPIO14 (1 << 14) -#define GPIO15 (1 << 15) -#define GPIO_ALL 0xffff - -/* --- Alternate function GPIOs -------------------------------------------- */ - -/* Default alternate functions of some pins (with and without remapping) */ - -/* CAN1 / CAN */ -#define GPIO_CAN1_RX GPIO11 /* PA11 */ -#define GPIO_CAN1_TX GPIO12 /* PA12 */ -#define GPIO_CAN_RX GPIO_CAN1_RX /* Alias */ -#define GPIO_CAN_TX GPIO_CAN1_TX /* Alias */ - -#define GPIO_CAN_PB_RX GPIO8 /* PB8 */ -#define GPIO_CAN_PB_TX GPIO9 /* PB9 */ -#define GPIO_CAN1_PB_RX GPIO_CAN_PB_RX /* Alias */ -#define GPIO_CAN1_PB_TX GPIO_CAN_PB_TX /* Alias */ - -#define GPIO_CAN_PD_RX GPIO0 /* PD0 */ -#define GPIO_CAN_PD_TX GPIO1 /* PD1 */ -#define GPIO_CAN1_PD_RX GPIO_CAN_PD_RX /* Alias */ -#define GPIO_CAN1_PD_TX GPIO_CAN_PD_TX /* Alias */ - -/* CAN2 */ -#define GPIO_CAN2_RX GPIO12 /* PB12 */ -#define GPIO_CAN2_TX GPIO13 /* PB13 */ - -#define GPIO_CAN2_RE_RX GPIO5 /* PB5 */ -#define GPIO_CAN2_RE_TX GPIO6 /* PB6 */ - -/* JTAG/SWD */ -#define GPIO_JTMS_SWDIO GPIO13 /* PA13 */ -#define GPIO_JTCK_SWCLK GPIO14 /* PA14 */ -#define GPIO_JTDI GPIO15 /* PA15 */ -#define GPIO_JTDO_TRACESWO GPIO3 /* PB3 */ -#define GPIO_JNTRST GPIO4 /* PB4 */ -#define GPIO_TRACECK GPIO2 /* PE2 */ -#define GPIO_TRACED0 GPIO3 /* PE3 */ -#define GPIO_TRACED1 GPIO4 /* PE4 */ -#define GPIO_TRACED2 GPIO5 /* PE5 */ -#define GPIO_TRACED3 GPIO6 /* PE6 */ - -/* Timer5 */ -#define GPIO_TIM5_CH4 GPIO3 /* PA3 */ - -/* Timer4 */ -#define GPIO_TIM4_CH1 GPIO6 /* PB6 */ -#define GPIO_TIM4_CH2 GPIO7 /* PB7 */ -#define GPIO_TIM4_CH3 GPIO8 /* PB8 */ -#define GPIO_TIM4_CH4 GPIO9 /* PB9 */ - -#define GPIO_TIM4_RE_CH1 GPIO12 /* PD12 */ -#define GPIO_TIM4_RE_CH2 GPIO13 /* PD13 */ -#define GPIO_TIM4_RE_CH3 GPIO14 /* PD14 */ -#define GPIO_TIM4_RE_CH4 GPIO15 /* PD15 */ - -/* Timer3 */ -#define GPIO_TIM3_CH1 GPIO6 /* PA6 */ -#define GPIO_TIM3_CH2 GPIO7 /* PA7 */ -#define GPIO_TIM3_CH3 GPIO0 /* PB0 */ -#define GPIO_TIM3_CH4 GPIO1 /* PB1 */ - -#define GPIO_TIM3_PR_CH1 GPIO4 /* PB4 */ -#define GPIO_TIM3_PR_CH2 GPIO5 /* PB5 */ -#define GPIO_TIM3_PR_CH3 GPIO0 /* PB0 */ -#define GPIO_TIM3_PR_CH4 GPIO1 /* PB1 */ - -#define GPIO_TIM3_FR_CH1 GPIO6 /* PC6 */ -#define GPIO_TIM3_FR_CH2 GPIO7 /* PC7 */ -#define GPIO_TIM3_FR_CH3 GPIO8 /* PC8 */ -#define GPIO_TIM3_FR_CH4 GPIO9 /* PC9 */ - -/* Timer2 */ -#define GPIO_TIM2_CH1_ETR GPIO0 /* PA0 */ -#define GPIO_TIM2_CH2 GPIO1 /* PA1 */ -#define GPIO_TIM2_CH3 GPIO2 /* PA2 */ -#define GPIO_TIM2_CH4 GPIO3 /* PA3 */ - -#define GPIO_TIM2_PR1_CH1_ETR GPIO15 /* PA15 */ -#define GPIO_TIM2_PR1_CH2 GPIO3 /* PB3 */ -#define GPIO_TIM2_PR1_CH3 GPIO2 /* PA2 */ -#define GPIO_TIM2_PR1_CH4 GPIO3 /* PA3 */ - -#define GPIO_TIM2_PR2_CH1_ETR GPIO0 /* PA0 */ -#define GPIO_TIM2_PR2_CH2 GPIO1 /* PA1 */ -#define GPIO_TIM2_PR2_CH3 GPIO10 /* PB10 */ -#define GPIO_TIM2_PR2_CH4 GPIO11 /* PB11 */ - -#define GPIO_TIM2_FR_CH1_ETR GPIO15 /* PA15 */ -#define GPIO_TIM2_FR_CH2 GPIO3 /* PB3 */ -#define GPIO_TIM2_FR_CH3 GPIO10 /* PB10 */ -#define GPIO_TIM2_FR_CH4 GPIO11 /* PB11 */ - -/* Timer1 */ -#define GPIO_TIM1_ETR GPIO12 /* PA12 */ -#define GPIO_TIM1_CH1 GPIO8 /* PA8 */ -#define GPIO_TIM1_CH2 GPIO9 /* PA9 */ -#define GPIO_TIM1_CH3 GPIO10 /* PA10 */ -#define GPIO_TIM1_CH4 GPIO11 /* PA11 */ -#define GPIO_TIM1_BKIN GPIO12 /* PB12 */ -#define GPIO_TIM1_CH1N GPIO13 /* PB13 */ -#define GPIO_TIM1_CH2N GPIO14 /* PB14 */ -#define GPIO_TIM1_CH3N GPIO15 /* PB15 */ - -#define GPIO_TIM1_PR_ETR GPIO12 /* PA12 */ -#define GPIO_TIM1_PR_CH1 GPIO8 /* PA8 */ -#define GPIO_TIM1_PR_CH2 GPIO9 /* PA9 */ -#define GPIO_TIM1_PR_CH3 GPIO10 /* PA10 */ -#define GPIO_TIM1_PR_CH4 GPIO11 /* PA11 */ -#define GPIO_TIM1_PR_BKIN GPIO6 /* PA6 */ -#define GPIO_TIM1_PR_CH1N GPIO7 /* PA7 */ -#define GPIO_TIM1_PR_CH2N GPIO0 /* PB0 */ -#define GPIO_TIM1_PR_CH3N GPIO1 /* PB1 */ - -#define GPIO_TIM1_FR_ETR GPIO7 /* PE7 */ -#define GPIO_TIM1_FR_CH1 GPIO9 /* PE9 */ -#define GPIO_TIM1_FR_CH2 GPIO11 /* PE11 */ -#define GPIO_TIM1_FR_CH3 GPIO13 /* PE13 */ -#define GPIO_TIM1_FR_CH4 GPIO14 /* PE14 */ -#define GPIO_TIM1_FR_BKIN GPIO15 /* PE15 */ -#define GPIO_TIM1_FR_CH1N GPIO8 /* PE8 */ -#define GPIO_TIM1_FR_CH2N GPIO10 /* PE10 */ -#define GPIO_TIM1_FR_CH3N GPIO12 /* PE12 */ - -/* USART3 */ -#define GPIO_USART3_TX GPIO10 /* PB10 */ -#define GPIO_USART3_RX GPIO11 /* PB11 */ -#define GPIO_USART3_CK GPIO12 /* PB12 */ -#define GPIO_USART3_CTS GPIO13 /* PB13 */ -#define GPIO_USART3_RTS GPIO14 /* PB14 */ - -#define GPIO_USART3_PR_TX GPIO10 /* PC10 */ -#define GPIO_USART3_PR_RX GPIO11 /* PC11 */ -#define GPIO_USART3_PR_CK GPIO12 /* PC12 */ -#define GPIO_USART3_PR_CTS GPIO13 /* PB13 */ -#define GPIO_USART3_PR_RTS GPIO14 /* PB14 */ - -#define GPIO_USART3_FR_TX GPIO8 /* PD8 */ -#define GPIO_USART3_FR_RX GPIO9 /* PD9 */ -#define GPIO_USART3_FR_CK GPIO10 /* PD10 */ -#define GPIO_USART3_FR_CTS GPIO11 /* PD11 */ -#define GPIO_USART3_FR_RTS GPIO12 /* PD12 */ - -/* USART2 */ -#define GPIO_USART2_CTS GPIO0 /* PA0 */ -#define GPIO_USART2_RTS GPIO1 /* PA1 */ -#define GPIO_USART2_TX GPIO2 /* PA2 */ -#define GPIO_USART2_RX GPIO3 /* PA3 */ -#define GPIO_USART2_CK GPIO4 /* PA4 */ - -#define GPIO_USART2_RE_CTS GPIO3 /* PD3 */ -#define GPIO_USART2_RE_RTS GPIO4 /* PD4 */ -#define GPIO_USART2_RE_TX GPIO5 /* PD5 */ -#define GPIO_USART2_RE_RX GPIO6 /* PD6 */ -#define GPIO_USART2_RE_CK GPIO7 /* PD7 */ - -/* USART1 */ -#define GPIO_USART1_TX GPIO9 /* PA9 */ -#define GPIO_USART1_RX GPIO10 /* PA10 */ - -#define GPIO_USART1_RE_TX GPIO6 /* PB6 */ -#define GPIO_USART1_RE_RX GPIO7 /* PB7 */ - -/* I2C1 */ -#define GPIO_I2C1_SMBAI GPIO5 /* PB5 */ -#define GPIO_I2C1_SCL GPIO6 /* PB6 */ -#define GPIO_I2C1_SDA GPIO7 /* PB7 */ - -#define GPIO_I2C1_RE_SMBAI GPIO5 /* PB5 */ -#define GPIO_I2C1_RE_SCL GPIO8 /* PB8 */ -#define GPIO_I2C1_RE_SDA GPIO9 /* PB9 */ - -/* I2C2 */ -#define GPIO_I2C2_SCL GPIO10 /* PB10 */ -#define GPIO_I2C2_SDA GPIO11 /* PB11 */ -#define GPIO_I2C2_SMBAI GPIO12 /* PB12 */ - -/* SPI1 */ -#define GPIO_SPI1_NSS GPIO4 /* PA4 */ -#define GPIO_SPI1_SCK GPIO5 /* PA5 */ -#define GPIO_SPI1_MISO GPIO6 /* PA6 */ -#define GPIO_SPI1_MOSI GPIO7 /* PA7 */ - -#define GPIO_SPI1_RE_NSS GPIO15 /* PA15 */ -#define GPIO_SPI1_RE_SCK GPIO3 /* PB3 */ -#define GPIO_SPI1_RE_MISO GPIO4 /* PB4 */ -#define GPIO_SPI1_RE_MOSI GPIO5 /* PB5 */ - -/* SPI2 */ -#define GPIO_SPI2_NSS GPIO12 /* PB12 */ -#define GPIO_SPI2_SCK GPIO13 /* PB13 */ -#define GPIO_SPI2_MISO GPIO14 /* PB14 */ -#define GPIO_SPI2_MOSI GPIO15 /* PB15 */ - -/* SPI3 */ -#define GPIO_SPI3_NSS GPIO15 /* PA15 */ -#define GPIO_SPI3_SCK GPIO3 /* PB3 */ -#define GPIO_SPI3_MISO GPIO4 /* PB4 */ -#define GPIO_SPI3_MOSI GPIO5 /* PB5 */ - -#define GPIO_SPI3_RE_NSS GPIO4 /* PA4 */ -#define GPIO_SPI3_RE_SCK GPIO10 /* PC10 */ -#define GPIO_SPI3_RE_MISO GPIO11 /* PC11 */ -#define GPIO_SPI3_RE_MOSI GPIO12 /* PC12 */ - -/* ETH */ -#define GPIO_ETH_RX_DV_CRS_DV GPIO7 /* PA7 */ -#define GPIO_ETH_RXD0 GPIO4 /* PC4 */ -#define GPIO_ETH_RXD1 GPIO5 /* PC5 */ -#define GPIO_ETH_RXD2 GPIO0 /* PB0 */ -#define GPIO_ETH_RXD3 GPIO1 /* PB1 */ - -#define GPIO_ETH_RE_RX_DV_CRS_DV GPIO8 /* PD8 */ -#define GPIO_ETH_RE_RXD0 GPIO9 /* PD9 */ -#define GPIO_ETH_RE_RXD1 GPIO10 /* PD10 */ -#define GPIO_ETH_RE_RXD2 GPIO11 /* PD11 */ -#define GPIO_ETH_RE_RXD3 GPIO12 /* PD12 */ - -/* --- GPIO registers ------------------------------------------------------ */ - -/* Port configuration register low (GPIOx_CRL) */ -#define GPIO_CRL(port) MMIO32(port + 0x00) -#define GPIOA_CRL GPIO_CRL(GPIOA) -#define GPIOB_CRL GPIO_CRL(GPIOB) -#define GPIOC_CRL GPIO_CRL(GPIOC) -#define GPIOD_CRL GPIO_CRL(GPIOD) -#define GPIOE_CRL GPIO_CRL(GPIOE) -#define GPIOF_CRL GPIO_CRL(GPIOF) -#define GPIOG_CRL GPIO_CRL(GPIOG) - -/* Port configuration register low (GPIOx_CRH) */ -#define GPIO_CRH(port) MMIO32(port + 0x04) -#define GPIOA_CRH GPIO_CRH(GPIOA) -#define GPIOB_CRH GPIO_CRH(GPIOB) -#define GPIOC_CRH GPIO_CRH(GPIOC) -#define GPIOD_CRH GPIO_CRH(GPIOD) -#define GPIOE_CRH GPIO_CRH(GPIOE) -#define GPIOF_CRH GPIO_CRH(GPIOF) -#define GPIOG_CRH GPIO_CRH(GPIOG) - -/* Port input data register (GPIOx_IDR) */ -#define GPIO_IDR(port) MMIO32(port + 0x08) -#define GPIOA_IDR GPIO_IDR(GPIOA) -#define GPIOB_IDR GPIO_IDR(GPIOB) -#define GPIOC_IDR GPIO_IDR(GPIOC) -#define GPIOD_IDR GPIO_IDR(GPIOD) -#define GPIOE_IDR GPIO_IDR(GPIOE) -#define GPIOF_IDR GPIO_IDR(GPIOF) -#define GPIOG_IDR GPIO_IDR(GPIOG) - -/* Port output data register (GPIOx_ODR) */ -#define GPIO_ODR(port) MMIO32(port + 0x0c) -#define GPIOA_ODR GPIO_ODR(GPIOA) -#define GPIOB_ODR GPIO_ODR(GPIOB) -#define GPIOC_ODR GPIO_ODR(GPIOC) -#define GPIOD_ODR GPIO_ODR(GPIOD) -#define GPIOE_ODR GPIO_ODR(GPIOE) -#define GPIOF_ODR GPIO_ODR(GPIOF) -#define GPIOG_ODR GPIO_ODR(GPIOG) - -/* Port bit set/reset register (GPIOx_BSRR) */ -#define GPIO_BSRR(port) MMIO32(port + 0x10) -#define GPIOA_BSRR GPIO_BSRR(GPIOA) -#define GPIOB_BSRR GPIO_BSRR(GPIOB) -#define GPIOC_BSRR GPIO_BSRR(GPIOC) -#define GPIOD_BSRR GPIO_BSRR(GPIOD) -#define GPIOE_BSRR GPIO_BSRR(GPIOE) -#define GPIOF_BSRR GPIO_BSRR(GPIOF) -#define GPIOG_BSRR GPIO_BSRR(GPIOG) - -/* Port bit reset register (GPIOx_BRR) */ -#define GPIO_BRR(port) MMIO16(port + 0x14) -#define GPIOA_BRR GPIO_BRR(GPIOA) -#define GPIOB_BRR GPIO_BRR(GPIOB) -#define GPIOC_BRR GPIO_BRR(GPIOC) -#define GPIOD_BRR GPIO_BRR(GPIOD) -#define GPIOE_BRR GPIO_BRR(GPIOE) -#define GPIOF_BRR GPIO_BRR(GPIOF) -#define GPIOG_BRR GPIO_BRR(GPIOG) - -/* Port configuration lock register (GPIOx_LCKR) */ -#define GPIO_LCKR(port) MMIO32(port + 0x18) -#define GPIOA_LCKR GPIO_LCKR(GPIOA) -#define GPIOB_LCKR GPIO_LCKR(GPIOB) -#define GPIOC_LCKR GPIO_LCKR(GPIOC) -#define GPIOD_LCKR GPIO_LCKR(GPIOD) -#define GPIOE_LCKR GPIO_LCKR(GPIOE) -#define GPIOF_LCKR GPIO_LCKR(GPIOF) -#define GPIOG_LCKR GPIO_LCKR(GPIOG) - -/* --- GPIO_CRL/GPIO_CRH values -------------------------------------------- */ - -/* CNF[1:0] values when MODE[1:0] is 00 (input mode) */ -#define GPIO_CNF_INPUT_ANALOG 0x00 -#define GPIO_CNF_INPUT_FLOAT 0x01 /* Default */ -#define GPIO_CNF_INPUT_PULL_UPDOWN 0x02 - -/* Output mode (MODE[1:0]) values */ -#define GPIO_MODE_INPUT 0x00 /* Default */ -#define GPIO_MODE_OUTPUT_10_MHZ 0x01 -#define GPIO_MODE_OUTPUT_2_MHZ 0x02 -#define GPIO_MODE_OUTPUT_50_MHZ 0x03 - -/* CNF[1:0] values when MODE[1:0] is != 00 (one of the output modes) */ -#define GPIO_CNF_OUTPUT_PUSHPULL 0x00 -#define GPIO_CNF_OUTPUT_OPENDRAIN 0x01 -#define GPIO_CNF_OUTPUT_ALTFN_PUSHPULL 0x02 -#define GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN 0x03 - -/* --- GPIO_IDR values ----------------------------------------------------- */ - -/* GPIO_IDR[15:0]: IDRy[15:0]: Port input data (y = 0..15) */ - -/* --- GPIO_ODR values ----------------------------------------------------- */ - -/* GPIO_ODR[15:0]: ODRy[15:0]: Port output data (y = 0..15) */ - -/* --- GPIO_BSRR values ---------------------------------------------------- */ - -/* GPIO_BSRR[31:16]: BRy: Port x reset bit y (y = 0..15) */ -/* GPIO_BSRR[15:0]: BSy: Port x set bit y (y = 0..15) */ - -/* --- GPIO_BRR values ----------------------------------------------------- */ - -/* GPIO_BRR[15:0]: BRy: Port x reset bit y (y = 0..15) */ - -/* --- GPIO_LCKR values ---------------------------------------------------- */ - -#define GPIO_LCKK (1 << 16) -/* GPIO_LCKR[15:0]: LCKy: Port x lock bit y (y = 0..15) */ - -/* --- AFIO registers ------------------------------------------------------ */ - -/* Event control register (AFIO_EVCR) */ -#define AFIO_EVCR MMIO32(AFIO_BASE + 0x00) - -/* AF remap and debug I/O configuration register (AFIO_MAPR) */ -#define AFIO_MAPR MMIO32(AFIO_BASE + 0x04) - -/* External interrupt configuration register 1 (AFIO_EXTICR1) */ -#define AFIO_EXTICR1 MMIO32(AFIO_BASE + 0x08) - -/* External interrupt configuration register 2 (AFIO_EXTICR2) */ -#define AFIO_EXTICR2 MMIO32(AFIO_BASE + 0x0c) - -/* External interrupt configuration register 3 (AFIO_EXTICR3) */ -#define AFIO_EXTICR3 MMIO32(AFIO_BASE + 0x10) - -/* External interrupt configuration register 4 (AFIO_EXTICR4) */ -#define AFIO_EXTICR4 MMIO32(AFIO_BASE + 0x14) - -/* --- AFIO_EVCR values ---------------------------------------------------- */ - -/* EVOE: Event output enable */ -#define AFIO_EVCR_EVOE (1 << 7) - -/* PORT[2:0]: Port selection */ -#define AFIO_EVCR_PORT_PA (0x0 << 4) -#define AFIO_EVCR_PORT_PB (0x1 << 4) -#define AFIO_EVCR_PORT_PC (0x2 << 4) -#define AFIO_EVCR_PORT_PD (0x3 << 4) -#define AFIO_EVCR_PORT_PE (0x4 << 4) - -/* PIN[3:0]: Pin selection */ -#define AFIO_EVCR_PIN_Px0 (0x0 << 0) -#define AFIO_EVCR_PIN_Px1 (0x1 << 0) -#define AFIO_EVCR_PIN_Px2 (0x2 << 0) -#define AFIO_EVCR_PIN_Px3 (0x3 << 0) -#define AFIO_EVCR_PIN_Px4 (0x4 << 0) -#define AFIO_EVCR_PIN_Px5 (0x5 << 0) -#define AFIO_EVCR_PIN_Px6 (0x6 << 0) -#define AFIO_EVCR_PIN_Px7 (0x7 << 0) -#define AFIO_EVCR_PIN_Px8 (0x8 << 0) -#define AFIO_EVCR_PIN_Px9 (0x9 << 0) -#define AFIO_EVCR_PIN_Px10 (0xA << 0) -#define AFIO_EVCR_PIN_Px11 (0xB << 0) -#define AFIO_EVCR_PIN_Px12 (0xC << 0) -#define AFIO_EVCR_PIN_Px13 (0xD << 0) -#define AFIO_EVCR_PIN_Px14 (0xE << 0) -#define AFIO_EVCR_PIN_Px15 (0xF << 0) - -/* --- AFIO_MAPR values ---------------------------------------------------- */ - -/* 31 reserved */ - -/* PTP_PPS_REMAP: Ethernet PTP PPS remapping - * (only connectivity line devices) */ -#define AFIO_MAPR_PTP_PPS_REMAP (1 << 30) - -/* TIM2ITR1_IREMAP: TIM2 internal trigger 1 remapping - * (only connectivity line devices) */ -#define AFIO_MAPR_TIM2ITR1_IREMAP (1 << 29) - -/* SPI3_REMAP: SPI3/I2S3 remapping - * (only connectivity line devices) */ -#define AFIO_MAPR_SPI3_REMAP (1 << 28) - -/* 27 reserved */ - -/* SWJ_CFG[2:0]: Serial wire JTAG configuration */ -#define AFIO_MAPR_SWJ_CFG_FULL_SWJ (0x0 << 24) -#define AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_JNTRST (0x1 << 24) -#define AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_ON (0x2 << 24) -#define AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_OFF (0x4 << 24) - -/* MII_REMAP: MII or RMII selection - * (only connectivity line devices) */ -#define AFIO_MAPR_MII_RMII_SEL (1 << 23) - -/* CAN2_REMAP: CAN2 I/O remapping - * (only connectivity line devices) */ -#define AFIO_MAPR_CAN2_REMAP (1 << 22) - -/* ETH_REMAP: Ethernet MAC I/O remapping - * (only connectivity line devices) */ -#define AFIO_MAPR_ETH_REMAP (1 << 21) - -/* ADC2_ETRGREG_REMAP: ADC2 external trigger regulator conversion remapping - * (only low-, medium-, high- and XL-densitiy devices) */ -#define AFIO_MAPR_ADC2_ETRGREG_REMAP (1 << 20) - -/* ADC2_ETRGINJ_REMAP: ADC2 external trigger injected conversion remapping - * (only low-, medium-, high- and XL-densitiy devices) */ -#define AFIO_MAPR_ADC2_ETRGINJ_REMAP (1 << 19) - -/* ADC1_ETRGREG_REMAP: ADC1 external trigger regulator conversion remapping - * (only low-, medium-, high- and XL-densitiy devices) */ -#define AFIO_MAPR_ADC1_ETRGREG_REMAP (1 << 18) - -/* ADC1_ETRGINJ_REMAP: ADC1 external trigger injected conversion remapping - * (only low-, medium-, high- and XL-densitiy devices) */ -#define AFIO_MAPR_ADC1_ETRGINJ_REMAP (1 << 17) - -/* TIM5CH4_IREMAP: TIM5 channel4 internal remap */ -#define AFIO_MAPR_TIM5CH4_IREMAP (1 << 16) - -/* PD01_REMAP: Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ -#define AFIO_MAPR_PD01_REMAP (1 << 15) - -/* CAN_REMAP[1:0]: CAN1 alternate function remapping */ -#define AFIO_MAPR_CAN1_REMAP_PORTA (0x0 << 13) -#define AFIO_MAPR_CAN1_REMAP_PORTB (0x2 << 13) /* Not on 36pin pkg */ -#define AFIO_MAPR_CAN1_REMAP_PORTD (0x3 << 13) - -/* TIM4_REMAP: TIM4 remapping */ -#define AFIO_MAPR_TIM4_REMAP (1 << 12) - -/* TIM3_REMAP[1:0]: TIM3 remapping */ -#define AFIO_MAPR_TIM3_REMAP_NO_REMAP (0x0 << 10) -#define AFIO_MAPR_TIM3_REMAP_PARTIAL_REMAP (0x2 << 10) -#define AFIO_MAPR_TIM3_REMAP_FULL_REMAP (0x3 << 10) - -/* TIM2_REMAP[1:0]: TIM2 remapping */ -#define AFIO_MAPR_TIM2_REMAP_NO_REMAP (0x0 << 8) -#define AFIO_MAPR_TIM2_REMAP_PARTIAL_REMAP1 (0x1 << 8) -#define AFIO_MAPR_TIM2_REMAP_PARTIAL_REMAP2 (0x2 << 8) -#define AFIO_MAPR_TIM2_REMAP_FULL_REMAP (0x3 << 8) - -/* TIM1_REMAP[1:0]: TIM1 remapping */ -#define AFIO_MAPR_TIM1_REMAP_NO_REMAP (0x0 << 6) -#define AFIO_MAPR_TIM1_REMAP_PARTIAL_REMAP (0x1 << 6) -#define AFIO_MAPR_TIM1_REMAP_FULL_REMAP (0x3 << 6) - -/* USART3_REMAP[1:0]: USART3 remapping */ -#define AFIO_MAPR_USART3_REMAP_NO_REMAP (0x0 << 4) -#define AFIO_MAPR_USART3_REMAP_PARTIAL_REMAP (0x1 << 4) -#define AFIO_MAPR_USART3_REMAP_FULL_REMAP (0x3 << 4) - -/* USART2_REMAP[1:0]: USART2 remapping */ -#define AFIO_MAPR_USART2_REMAP (1 << 3) - -/* USART1_REMAP[1:0]: USART1 remapping */ -#define AFIO_MAPR_USART1_REMAP (1 << 2) - -/* I2C1_REMAP[1:0]: I2C1 remapping */ -#define AFIO_MAPR_I2C1_REMAP (1 << 1) - -/* SPI1_REMAP[1:0]: SPI1 remapping */ -#define AFIO_MAPR_SPI1_REMAP (1 << 0) - -/* --- AFIO_EXTICR1 values ------------------------------------------------- */ -/* --- AFIO_EXTICR2 values ------------------------------------------------- */ -/* --- AFIO_EXTICR3 values ------------------------------------------------- */ -/* --- AFIO_EXTICR4 values ------------------------------------------------- */ - -/* EXTI0 - EXTI15 interrupt source selection registers */ - -/* Note: For using them we should define a function that calculates the right - * registers, using definitions is probably not a good idea. - */ - -/* --- Function prototypes ------------------------------------------------- */ - -void gpio_set_mode(u32 gpioport, u8 mode, u8 cnf, u16 gpios); -void gpio_set(u32 gpioport, u16 gpios); -void gpio_clear(u32 gpioport, u16 gpios); -u16 gpio_get(u32 gpioport, u16 gpios); -void gpio_toggle(u32 gpioport, u16 gpios); -u16 gpio_port_read(u32 gpioport); -void gpio_port_write(u32 gpioport, u16 data); -void gpio_port_config_lock(u32 gpioport, u16 gpios); - -#endif diff --git a/include/libopencm3/stm32/i2c.h b/include/libopencm3/stm32/i2c.h deleted file mode 100644 index 1b837b8..0000000 --- a/include/libopencm3/stm32/i2c.h +++ /dev/null @@ -1,333 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_I2C_H -#define LIBOPENCM3_I2C_H - -#include -#include - -/* --- Convenience macros -------------------------------------------------- */ - -/* I2C register base adresses (for convenience) */ -#define I2C1 I2C1_BASE -#define I2C2 I2C2_BASE - -/* --- I2C registers ------------------------------------------------------- */ - -/* Control register 1 (I2Cx_CR1) */ -#define I2C_CR1(i2c_base) MMIO32(i2c_base + 0x00) -#define I2C1_CR1 I2C_CR1(I2C1) -#define I2C2_CR1 I2C_CR1(I2C2) - -/* Control register 2 (I2Cx_CR2) */ -#define I2C_CR2(i2c_base) MMIO32(i2c_base + 0x04) -#define I2C1_CR2 I2C_CR2(I2C1) -#define I2C2_CR2 I2C_CR2(I2C2) - -/* Own address register 1 (I2Cx_OAR1) */ -#define I2C_OAR1(i2c_base) MMIO32(i2c_base + 0x08) -#define I2C1_OAR1 I2C_OAR1(I2C1) -#define I2C2_OAR1 I2C_OAR1(I2C2) - -/* Own address register 2 (I2Cx_OAR2) */ -#define I2C_OAR2(i2c_base) MMIO32(i2c_base + 0x0c) -#define I2C1_OAR2 I2C_OAR2(I2C1) -#define I2C2_OAR2 I2C_OAR2(I2C2) - -/* Data register (I2Cx_DR) */ -#define I2C_DR(i2c_base) MMIO32(i2c_base + 0x10) -#define I2C1_DR I2C_DR(I2C1) -#define I2C2_DR I2C_DR(I2C2) - -/* Status register 1 (I2Cx_SR1) */ -#define I2C_SR1(i2c_base) MMIO32(i2c_base + 0x14) -#define I2C1_SR1 I2C_SR1(I2C1) -#define I2C2_SR1 I2C_SR1(I2C2) - -/* Status register 2 (I2Cx_SR2) */ -#define I2C_SR2(i2c_base) MMIO32(i2c_base + 0x18) -#define I2C1_SR2 I2C_SR2(I2C1) -#define I2C2_SR2 I2C_SR2(I2C2) - -/* Clock control register (I2Cx_CCR) */ -#define I2C_CCR(i2c_base) MMIO32(i2c_base + 0x1c) -#define I2C1_CCR I2C_CCR(I2C1) -#define I2C2_CCR I2C_CCR(I2C2) - -/* TRISE register (I2Cx_CCR) */ -#define I2C_TRISE(i2c_base) MMIO32(i2c_base + 0x20) -#define I2C1_TRISE I2C_TRISE(I2C1) -#define I2C2_TRISE I2C_TRISE(I2C2) - -/* --- I2Cx_CR1 values ----------------------------------------------------- */ - -/* SWRST: Software reset */ -#define I2C_CR1_SWRST (1 << 15) - -/* Note: Bit 14 is reserved, and forced to 0 by hardware. */ - -/* ALERT: SMBus alert */ -#define I2C_CR1_ALERT (1 << 13) - -/* PEC: Packet error checking */ -#define I2C_CR1_PEC (1 << 12) - -/* POS: Acknowledge / PEC postition */ -#define I2C_CR1_POS (1 << 11) - -/* ACK: Acknowledge enable */ -#define I2C_CR1_ACK (1 << 10) - -/* STOP: STOP generation */ -#define I2C_CR1_STOP (1 << 9) - -/* START: START generation */ -#define I2C_CR1_START (1 << 8) - -/* NOSTRETCH: Clock stretching disable (slave mode) */ -#define I2C_CR1_NOSTRETCH (1 << 7) - -/* ENGC: General call enable */ -#define I2C_CR1_ENGC (1 << 6) - -/* ENPEC: Enable PEC */ -#define I2C_CR1_ENPEC (1 << 5) - -/* ENARP: ARP enable */ -#define I2C_CR1_ENARP (1 << 4) - -/* SMBTYPE: SMBus type */ -#define I2C_CR1_SMBTYPE (1 << 3) - -/* Note: Bit 2 is reserved, and forced to 0 by hardware. */ - -/* SMBUS: SMBus mode */ -#define I2C_CR1_SMBUS (1 << 1) - -/* PE: Peripheral enable */ -#define I2C_CR1_PE (1 << 0) - -/* --- I2Cx_CR2 values ----------------------------------------------------- */ - -/* Note: Bits [15:13] are reserved, and forced to 0 by hardware. */ - -/* LAST: DMA last transfer */ -#define I2C_CR2_LAST (1 << 12) - -/* DMAEN: DMA requests enable */ -#define I2C_CR2_DMAEN (1 << 11) - -/* ITBUFEN: Buffer interrupt enable */ -#define I2C_CR2_ITBUFEN (1 << 10) - -/* ITEVTEN: Event interrupt enable */ -#define I2C_CR2_ITEVTEN (1 << 9) - -/* ITERREN: Error interrupt enable */ -#define I2C_CR2_ITERREN (1 << 8) - -/* Note: Bits [7:6] are reserved, and forced to 0 by hardware. */ - -/* FREQ[5:0]: Peripheral clock frequency (valid values: 2-36 MHz) */ -#define I2C_CR2_FREQ_2MHZ 0x02 -#define I2C_CR2_FREQ_3MHZ 0x03 -#define I2C_CR2_FREQ_4MHZ 0x04 -#define I2C_CR2_FREQ_5MHZ 0x05 -#define I2C_CR2_FREQ_6MHZ 0x06 -#define I2C_CR2_FREQ_7MHZ 0x07 -#define I2C_CR2_FREQ_8MHZ 0x08 -#define I2C_CR2_FREQ_9MHZ 0x09 -#define I2C_CR2_FREQ_10MHZ 0x0a -#define I2C_CR2_FREQ_11MHZ 0x0b -#define I2C_CR2_FREQ_12MHZ 0x0c -#define I2C_CR2_FREQ_13MHZ 0x0d -#define I2C_CR2_FREQ_14MHZ 0x0e -#define I2C_CR2_FREQ_15MHZ 0x0f -#define I2C_CR2_FREQ_16MHZ 0x10 -#define I2C_CR2_FREQ_17MHZ 0x11 -#define I2C_CR2_FREQ_18MHZ 0x12 -#define I2C_CR2_FREQ_19MHZ 0x13 -#define I2C_CR2_FREQ_20MHZ 0x14 -#define I2C_CR2_FREQ_21MHZ 0x15 -#define I2C_CR2_FREQ_22MHZ 0x16 -#define I2C_CR2_FREQ_23MHZ 0x17 -#define I2C_CR2_FREQ_24MHZ 0x18 -#define I2C_CR2_FREQ_25MHZ 0x19 -#define I2C_CR2_FREQ_26MHZ 0x1a -#define I2C_CR2_FREQ_27MHZ 0x1b -#define I2C_CR2_FREQ_28MHZ 0x1c -#define I2C_CR2_FREQ_29MHZ 0x1d -#define I2C_CR2_FREQ_30MHZ 0x1e -#define I2C_CR2_FREQ_31MHZ 0x1f -#define I2C_CR2_FREQ_32MHZ 0x20 -#define I2C_CR2_FREQ_33MHZ 0x21 -#define I2C_CR2_FREQ_34MHZ 0x22 -#define I2C_CR2_FREQ_35MHZ 0x23 -#define I2C_CR2_FREQ_36MHZ 0x24 - -/* --- I2Cx_OAR1 values ---------------------------------------------------- */ - -/* ADDMODE: Addressing mode (slave mode) */ -#define I2C_OAR1_ADDMODE (1 << 15) -#define I2C_OAR1_ADDMODE_7BIT 0 -#define I2C_OAR1_ADDMODE_10BIT 1 - -/* Note: Bit 14 should always be kept at 1 by software! */ - -/* Note: Bits [13:10] are reserved, and forced to 0 by hardware. */ - -/* ADD: Address bits: [7:1] in 7-bit mode, bits [9:0] in 10-bit mode */ - -/* --- I2Cx_OAR1 values ---------------------------------------------------- */ - -/* Note: Bits [15:8] are reserved, and forced to 0 by hardware. */ - -/* ADD2[7:1]: Interface address (bits [7:1] in dual addressing mode) */ - -/* ENDUAL: Dual addressing mode enable */ -#define I2C_OAR2_ENDUAL (1 << 0) - -/* --- I2Cx_DR values ------------------------------------------------------ */ - -/* Note: Bits [15:8] are reserved, and forced to 0 by hardware. */ - -/* DR[7:0] 8-bit data register */ - -/* --- I2Cx_SR1 values ----------------------------------------------------- */ - -/* SMBALERT: SMBus alert */ -#define I2C_SR1_SMBALERT (1 << 15) - -/* TIMEOUT: Timeout or Tlow Error */ -#define I2C_SR1_TIMEOUT (1 << 14) - -/* Note: Bit 13 is reserved, and forced to 0 by hardware. */ - -/* PECERR: PEC Error in reception */ -#define I2C_SR1_PECERR (1 << 12) - -/* OVR: Overrun/Underrun */ -#define I2C_SR1_OVR (1 << 11) - -/* AF: Acknowledge failure */ -#define I2C_SR1_AF (1 << 10) - -/* ARLO: Arbitration lost (master mode) */ -#define I2C_SR1_ARLO (1 << 9) - -/* BERR: Bus error */ -#define I2C_SR1_BERR (1 << 8) - -/* TxE: Data register empty (transmitters) */ -#define I2C_SR1_TxE (1 << 7) - -/* RxNE: Data register not empty (receivers) */ -#define I2C_SR1_RxNE (1 << 6) - -/* Note: Bit 5 is reserved, and forced to 0 by hardware. */ - -/* STOPF: STOP detection (slave mode) */ -#define I2C_SR1_STOPF (1 << 4) - -/* ADD10: 10-bit header sent (master mode) */ -#define I2C_SR1_ADD10 (1 << 3) - -/* BTF: Byte transfer finished */ -#define I2C_SR1_BTF (1 << 2) - -/* ADDR: Address sent (master mode) / address matched (slave mode) */ -#define I2C_SR1_ADDR (1 << 1) - -/* SB: Start bit (master mode) */ -#define I2C_SR1_SB (1 << 0) - -/* --- I2Cx_SR2 values ----------------------------------------------------- */ - -/* Bits [15:8]: PEC[7:0]: Packet error checking register */ - -/* DUALF: Dual flag (slave mode) */ -#define I2C_SR2_DUALF (1 << 7) - -/* SMBHOST: SMBus host header (slave mode) */ -#define I2C_SR2_SMBHOST (1 << 6) - -/* SMBDEFAULT: SMBus device default address (slave mode) */ -#define I2C_SR2_SMBDEFAULT (1 << 5) - -/* GENCALL: General call address (slave mode) */ -#define I2C_SR2_GENCALL (1 << 4) - -/* Note: Bit 3 is reserved, and forced to 0 by hardware. */ - -/* TRA: Transmitter / receiver */ -#define I2C_SR2_TRA (1 << 2) - -/* BUSY: Bus busy */ -#define I2C_SR2_BUSY (1 << 1) - -/* MSL: Master / slave */ -#define I2C_SR2_MSL (1 << 0) - -/* --- I2Cx_CCR values ----------------------------------------------------- */ - -/* F/S: I2C Master mode selection (fast / standard) */ -#define I2C_CCR_FS (1 << 15) - -/* DUTY: Fast Mode Duty Cycle */ -#define I2C_CCR_DUTY (1 << 14) - -/* Note: Bits [13:12] are reserved, and forced to 0 by hardware. */ - -/* - * Bits [11:0]: - * CCR[11:0]: Clock control register in Fast/Standard mode (master mode) - */ - -/* --- I2Cx_TRISE values --------------------------------------------------- */ - -/* Note: Bits [15:6] are reserved, and forced to 0 by hardware. */ - -/* - * Bits [5:0]: - * TRISE[5:0]: Maximum rise time in Fast/Standard mode (master mode) - */ - -/* --- I2C const definitions ----------------------------------------------- */ - -#define I2C_WRITE 0 -#define I2C_READ 1 - -/* --- I2C funtion prototypes----------------------------------------------- */ - -void i2c_peripheral_enable(u32 i2c); -void i2c_peripheral_disable(u32 i2c); -void i2c_send_start(u32 i2c); -void i2c_send_stop(u32 i2c); -void i2c_set_own_7bit_slave_address(u32 i2c, u8 slave); -void i2c_set_own_10bit_slave_address(u32 i2c, u16 slave); -void i2c_set_fast_mode(u32 i2c); -void i2c_set_standard_mode(u32 i2c); -void i2c_set_clock_frequency(u32 i2c, u8 freq); -void i2c_set_ccr(u32 i2c, u16 freq); -void i2c_set_trise(u32 i2c, u16 trise); -void i2c_send_7bit_address(u32 i2c, u8 slave, u8 readwrite); -void i2c_send_data(u32 i2c, u8 data); - -#endif diff --git a/include/libopencm3/stm32/iwdg.h b/include/libopencm3/stm32/iwdg.h deleted file mode 100644 index bf2784a..0000000 --- a/include/libopencm3/stm32/iwdg.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_IWDG_H -#define LIBOPENCM3_IWDG_H - -#include -#include - -/* --- IWDG registers ------------------------------------------------------ */ - -/* Key Register (IWDG_KR) */ -#define IWDG_KR MMIO32(IWDG_BASE + 0x00) - -/* Prescaler register (IWDG_PR) */ -#define IWDG_PR MMIO32(IWDG_BASE + 0x04) - -/* Reload register (IWDG_RLR) */ -#define IWDG_RLR MMIO32(IWDG_BASE + 0x08) - -/* Status register (IWDG_SR) */ -#define IWDG_SR MMIO32(IWDG_BASE + 0x0C) - -/* --- IWDG_KR values ------------------------------------------------------ */ - -/* KEY[15:0]: Key value */ -#define IWDG_KR_RESET 0xAAAA -#define IWDG_KR_UNLOCK 0x5555 -#define IWDG_KR_START 0xCCCC - -/* --- IWDG_PR values ------------------------------------------------------ */ - -/* PR[2:0]: Prescaler divider */ -#define IWDG_PR_LSB 0 -#define IWDG_PR_DIV4 0x0 -#define IWDG_PR_DIV8 0x1 -#define IWDG_PR_DIV16 0x2 -#define IWDG_PR_DIV32 0x3 -#define IWDG_PR_DIV64 0x4 -#define IWDG_PR_DIV128 0x5 -#define IWDG_PR_DIV256 0x6 -/* Double definition: 0x06 and 0x07 both mean DIV256 as per datasheet. */ -/* #define IWDG_PR_DIV256 0x7 */ - -/* --- IWDG_RLR values ----------------------------------------------------- */ - -/* RL[11:0]: Watchdog counter reload value */ - -/* --- IWDG_SR values ------------------------------------------------------ */ - -/* RVU: Watchdog counter reload value update */ -#define IWDG_SR_RVU (1 << 1) - -/* PVU: Watchdog prescaler value update */ -#define IWDG_SR_PVU (1 << 0) - -/* --- IWDG funtion prototypes---------------------------------------------- */ - -#endif diff --git a/include/libopencm3/stm32/memorymap.h b/include/libopencm3/stm32/memorymap.h deleted file mode 100644 index e3c57c8..0000000 --- a/include/libopencm3/stm32/memorymap.h +++ /dev/null @@ -1,113 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_MEMORYMAP_H -#define LIBOPENCM3_MEMORYMAP_H - -#include - -/* --- STM32 specific peripheral definitions ------------------------------- */ - -/* Memory map for all busses */ -#define PERIPH_BASE 0x40000000 -#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000) -#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000) -#define PERIPH_BASE_AHB (PERIPH_BASE + 0x18000) - -/* Register boundary addresses */ - -/* APB1 */ -#define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000) -#define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400) -#define TIM4_BASE (PERIPH_BASE_APB1 + 0x0800) -#define TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00) -#define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000) -#define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400) -#define TIM12_BASE (PERIPH_BASE_APB1 + 0x1800) -#define TIM13_BASE (PERIPH_BASE_APB1 + 0x1c00) -#define TIM14_BASE (PERIPH_BASE_APB1 + 0x2000) -/* PERIPH_BASE_APB1 + 0x2400 (0x4000 2400 - 0x4000 27FF): Reserved */ -#define RTC_BASE (PERIPH_BASE_APB1 + 0x2800) -#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00) -#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000) -/* PERIPH_BASE_APB1 + 0x3400 (0x4000 3400 - 0x4000 37FF): Reserved */ -#define SPI2_I2S_BASE (PERIPH_BASE_APB1 + 0x3800) -#define SPI3_I2S_BASE (PERIPH_BASE_APB1 + 0x3c00) -/* PERIPH_BASE_APB1 + 0x4000 (0x4000 4000 - 0x4000 3FFF): Reserved */ -#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400) -#define USART3_BASE (PERIPH_BASE_APB1 + 0x4800) -#define UART4_BASE (PERIPH_BASE_APB1 + 0x4c00) -#define UART5_BASE (PERIPH_BASE_APB1 + 0x5000) -#define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400) -#define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800) -#define USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x5c00) -#define USB_CAN_SRAM_BASE (PERIPH_BASE_APB1 + 0x6000) -#define BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400) -#define BX_CAN2_BASE (PERIPH_BASE_APB1 + 0x6800) -/* PERIPH_BASE_APB1 + 0x6800 (0x4000 6800 - 0x4000 6BFF): Reserved? Typo? */ -#define BACKUP_REGS_BASE (PERIPH_BASE_APB1 + 0x6c00) -#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000) -#define DAC_BASE (PERIPH_BASE_APB1 + 0x7400) -/* PERIPH_BASE_APB1 + 0x7800 (0x4000 7800 - 0x4000 FFFF): Reserved */ - -/* APB2 */ -#define AFIO_BASE (PERIPH_BASE_APB2 + 0x0000) -#define EXTI_BASE (PERIPH_BASE_APB2 + 0x0400) -#define GPIO_PORT_A_BASE (PERIPH_BASE_APB2 + 0x0800) -#define GPIO_PORT_B_BASE (PERIPH_BASE_APB2 + 0x0c00) -#define GPIO_PORT_C_BASE (PERIPH_BASE_APB2 + 0x1000) -#define GPIO_PORT_D_BASE (PERIPH_BASE_APB2 + 0x1400) -#define GPIO_PORT_E_BASE (PERIPH_BASE_APB2 + 0x1800) -#define GPIO_PORT_F_BASE (PERIPH_BASE_APB2 + 0x1c00) -#define GPIO_PORT_G_BASE (PERIPH_BASE_APB2 + 0x2000) -#define ADC1_BASE (PERIPH_BASE_APB2 + 0x2400) -#define ADC2_BASE (PERIPH_BASE_APB2 + 0x2800) -#define TIM1_BASE (PERIPH_BASE_APB2 + 0x2c00) -#define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000) -#define TIM8_BASE (PERIPH_BASE_APB2 + 0x3400) -#define USART1_BASE (PERIPH_BASE_APB2 + 0x3800) -#define ADC3_BASE (PERIPH_BASE_APB2 + 0x3c00) -/* PERIPH_BASE_APB2 + 0x4000 (0x4001 4000 - 0x4001 4FFF): Reserved */ -#define TIM9_BASE (PERIPH_BASE_APB2 + 0x4c00) -#define TIM10_BASE (PERIPH_BASE_APB2 + 0x5000) -#define TIM11_BASE (PERIPH_BASE_APB2 + 0x5400) -/* PERIPH_BASE_APB2 + 0x5800 (0x4001 5800 - 0x4001 7FFF): Reserved */ - -/* AHB */ -#define SDIO_BASE (PERIPH_BASE_AHB + 0x00000) -/* PERIPH_BASE_AHB + 0x0400 (0x4001 8400 - 0x4001 7FFF): Reserved */ -#define DMA1_BASE (PERIPH_BASE_AHB + 0x08000) -#define DMA2_BASE (PERIPH_BASE_AHB + 0x08400) -/* PERIPH_BASE_AHB + 0x8800 (0x4002 0800 - 0x4002 0FFF): Reserved */ -#define RCC_BASE (PERIPH_BASE_AHB + 0x09000) -/* PERIPH_BASE_AHB + 0x9400 (0x4002 1400 - 0x4002 1FFF): Reserved */ -#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB + 0x0a000) -#define CRC_BASE (PERIPH_BASE_AHB + 0x0b000) -/* PERIPH_BASE_AHB + 0xb400 (0x4002 3400 - 0x4002 7FFF): Reserved */ -#define ETHERNET_BASE (PERIPH_BASE_AHB + 0x10000) -/* PERIPH_BASE_AHB + 0x18000 (0x4003 0000 - 0x4FFF FFFF): Reserved */ -#define USB_OTG_FS_BASE (PERIPH_BASE_AHB + 0xffe8000) - -/* PPIB */ -#define DBGMCU_BASE (PPBI_BASE + 0x00042000) - -/* FSMC */ -#define FSMC_BASE (PERIPH_BASE + 0x60000000) - -#endif diff --git a/include/libopencm3/stm32/nvic.h b/include/libopencm3/stm32/nvic.h deleted file mode 100644 index d29c425..0000000 --- a/include/libopencm3/stm32/nvic.h +++ /dev/null @@ -1,162 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_NVIC_H -#define LIBOPENCM3_NVIC_H - -#include -#include - -/* --- NVIC Registers ------------------------------------------------------ */ - -/* ISER: Interrupt Set Enable Registers */ -/* Note: 8 32bit Registers */ -#define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + (iser_id * 4)) - -/* NVIC_BASE + 0x020 (0xE000 E120 - 0xE000 E17F): Reserved */ - -/* ICER: Interrupt Clear Enable Registers */ -/* Note: 8 32bit Registers */ -#define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + (icer_id * 4)) - -/* NVIC_BASE + 0x0A0 (0xE000 E1A0 - 0xE000 E1FF): Reserved */ - -/* ISPR: Interrupt Set Pending Registers */ -/* Note: 8 32bit Registers */ -#define NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + (ispr_id * 4)) - -/* NVIC_BASE + 0x120 (0xE000 E220 - 0xE000 E27F): Reserved */ - -/* ICPR: Interrupt Clear Pending Registers */ -/* Note: 8 32bit Registers */ -#define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + (icpr_id * 4)) - -/* NVIC_BASE + 0x1A0 (0xE000 E2A0 - 0xE00 E2FF): Reserved */ - -/* IABR: Interrupt Active Bit Register */ -/* Note: 8 32bit Registers */ -#define NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + (iabr_id * 4)) - -/* NVIC_BASE + 0x220 (0xE000 E320 - 0xE000 E3FF): Reserved */ - -/* IPR: Interrupt Priority Registers */ -/* Note: 240 8bit Registers */ -#define NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + ipr_id) - -/* STIR: Software Trigger Interrupt Register */ -#define NVIC_STIR MMIO32(STIR_BASE) - -/* --- IRQ channel numbers-------------------------------------------------- */ - -/* Cortex M3 System Interrupts */ -#define NVIC_NMI_IRQ -14 -#define NVIC_HARD_FAULT_IRQ -13 -#define NVIC_MEM_MANAGE_IRQ -12 -#define NVIC_BUS_FAULT_IRQ -11 -#define NVIC_USAGE_FAULT_IRQ -10 -/* irq numbers -6 to -9 are reserved */ -#define NVIC_SV_CALL_IRQ -5 -#define DEBUG_MONITOR_IRQ -4 -/* irq number -3 reserved */ -#define NVIC_PENDSV_IRQ -2 -#define NVIC_SYSTICK_IRQ -1 - -/* User Interrupts */ -#define NVIC_WWDG_IRQ 0 -#define NVIC_PVD_IRQ 1 -#define NVIC_TAMPER_IRQ 2 -#define NVIC_RTC_IRQ 3 -#define NVIC_FLASH_IRQ 4 -#define NVIC_RCC_IRQ 5 -#define NVIC_EXTI0_IRQ 6 -#define NVIC_EXTI1_IRQ 7 -#define NVIC_EXTI2_IRQ 8 -#define NVIC_EXTI3_IRQ 9 -#define NVIC_EXTI4_IRQ 10 -#define NVIC_DMA1_CHANNEL1_IRQ 11 -#define NVIC_DMA1_CHANNEL2_IRQ 12 -#define NVIC_DMA1_CHANNEL3_IRQ 13 -#define NVIC_DMA1_CHANNEL4_IRQ 14 -#define NVIC_DMA1_CHANNEL5_IRQ 15 -#define NVIC_DMA1_CHANNEL6_IRQ 16 -#define NVIC_DMA1_CHANNEL7_IRQ 17 -#define NVIC_ADC1_2_IRQ 18 -#define NVIC_USB_HP_CAN_TX_IRQ 19 -#define NVIC_USB_LP_CAN_RX0_IRQ 20 -#define NVIC_CAN_RX1_IRQ 21 -#define NVIC_CAN_SCE_IRQ 22 -#define NVIC_EXTI9_5_IRQ 23 -#define NVIC_TIM1_BRK_IRQ 24 -#define NVIC_TIM1_UP_IRQ 25 -#define NVIC_TIM1_TRG_COM_IRQ 26 -#define NVIC_TIM1_CC_IRQ 27 -#define NVIC_TIM2_IRQ 28 -#define NVIC_TIM3_IRQ 29 -#define NVIC_TIM4_IRQ 30 -#define NVIC_I2C1_EV_IRQ 31 -#define NVIC_I2C1_ER_IRQ 32 -#define NVIC_I2C2_EV_IRQ 33 -#define NVIC_I2C2_ER_IRQ 34 -#define NVIC_SPI1_IRQ 35 -#define NVIC_SPI2_IRQ 36 -#define NVIC_USART1_IRQ 37 -#define NVIC_USART2_IRQ 38 -#define NVIC_USART3_IRQ 39 -#define NVIC_EXTI15_10_IRQ 40 -#define NVIC_RTC_ALARM_IRQ 41 -#define NVIC_USB_WAKEUP_IRQ 42 -#define NVIC_TIM8_BRK_IRQ 43 -#define NVIC_TIM8_UP_IRQ 44 -#define NVIC_TIM8_TRG_COM_IRQ 45 -#define NVIC_TIM8_CC_IRQ 46 -#define NVIC_ADC3_IRQ 47 -#define NVIC_FSMC_IRQ 48 -#define NVIC_SDIO_IRQ 49 -#define NVIC_TIM5_IRQ 50 -#define NVIC_SPI3_IRQ 51 -#define NVIC_USART4_IRQ 52 -#define NVIC_USART5_IRQ 53 -#define NVIC_TIM6_IRQ 54 -#define NVIC_TIM7_IRQ 55 -#define NVIC_DMA2_CHANNEL1_IRQ 56 -#define NVIC_DMA2_CHANNEL2_IRQ 57 -#define NVIC_DMA2_CHANNEL3_IRQ 58 -#define NVIC_DMA2_CHANNEL4_5_IRQ 59 -#define NVIC_DMA2_CHANNEL5_IRQ 60 -#define NVIC_ETH_IRQ 61 -#define NVIC_ETH_WKUP_IRQ 62 -#define NVIC_CAN2_TX_IRQ 63 -#define NVIC_CAN2_RX0_IRQ 64 -#define NVIC_CAN2_RX1_IRQ 65 -#define NVIC_CAN2_SCE_IRQ 66 -#define NVIC_OTG_FS_IRQ 67 - -/* --- NVIC functions ------------------------------------------------------ */ - -void nvic_enable_irq(u8 irqn); -void nvic_disable_irq(u8 irqn); -u8 nvic_get_pending_irq(u8 irqn); -void nvic_set_pending_irq(u8 irqn); -void nvic_clear_pending_irq(u8 irqn); -u8 nvic_get_active_irq(u8 irqn); -u8 nvic_get_irq_enabled(u8 irqn); -void nvic_set_priority(u8 irqn, u8 priority); -void nvic_generate_software_interrupt(u8 irqn); - -#endif diff --git a/include/libopencm3/stm32/otg_fs.h b/include/libopencm3/stm32/otg_fs.h deleted file mode 100644 index e1d7a6a..0000000 --- a/include/libopencm3/stm32/otg_fs.h +++ /dev/null @@ -1,324 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Gareth McMullin - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_OTG_FS_H -#define LIBOPENCM3_OTG_FS_H - -#include -#include - -/* Core Global Control and Status Registers */ -#define OTG_FS_OTGCTL MMIO32(USB_OTG_FS_BASE + 0x000) -#define OTG_FS_GOTGINT MMIO32(USB_OTG_FS_BASE + 0x004) -#define OTG_FS_GAHBCFG MMIO32(USB_OTG_FS_BASE + 0x008) -#define OTG_FS_GUSBCFG MMIO32(USB_OTG_FS_BASE + 0x00C) -#define OTG_FS_GRSTCTL MMIO32(USB_OTG_FS_BASE + 0x010) -#define OTG_FS_GINTSTS MMIO32(USB_OTG_FS_BASE + 0x014) -#define OTG_FS_GINTMSK MMIO32(USB_OTG_FS_BASE + 0x018) -#define OTG_FS_GRXSTSR MMIO32(USB_OTG_FS_BASE + 0x01C) -#define OTG_FS_GRXSTSP MMIO32(USB_OTG_FS_BASE + 0x020) -#define OTG_FS_GRXFSIZ MMIO32(USB_OTG_FS_BASE + 0x024) -#define OTG_FS_GNPTXFSIZ MMIO32(USB_OTG_FS_BASE + 0x028) -#define OTG_FS_GNPTXSTS MMIO32(USB_OTG_FS_BASE + 0x02C) -#define OTG_FS_GCCFG MMIO32(USB_OTG_FS_BASE + 0x038) -#define OTG_FS_CID MMIO32(USB_OTG_FS_BASE + 0x03C) -#define OTG_FS_HPTXFSIZ MMIO32(USB_OTG_FS_BASE + 0x100) -#define OTG_FS_DIEPTXF(x) MMIO32(USB_OTG_FS_BASE + 0x104 + 4*(x)) - -/* Host-mode Control and Status Registers */ -#define OTG_FS_HCFG MMIO32(USB_OTG_FS_BASE + 0x400) -#define OTG_FS_HFIR MMIO32(USB_OTG_FS_BASE + 0x404) -#define OTG_FS_HFNUM MMIO32(USB_OTG_FS_BASE + 0x408) -#define OTG_FS_HPTXSTS MMIO32(USB_OTG_FS_BASE + 0x410) -#define OTG_FS_HAINT MMIO32(USB_OTG_FS_BASE + 0x414) -#define OTG_FS_HAINTMSK MMIO32(USB_OTG_FS_BASE + 0x418) -#define OTG_FS_HPRT MMIO32(USB_OTG_FS_BASE + 0x440) -#define OTG_FS_HCCHARx MMIO32(USB_OTG_FS_BASE + 0x500) -#define OTG_FS_HCINTx MMIO32(USB_OTG_FS_BASE + 0x508) -#define OTG_FS_HCINTMSKx MMIO32(USB_OTG_FS_BASE + 0x50C) -#define OTG_FS_HCTSIZx MMIO32(USB_OTG_FS_BASE + 0x510) - -/* Device-mode Control and Status Registers */ -#define OTG_FS_DCFG MMIO32(USB_OTG_FS_BASE + 0x800) -#define OTG_FS_DCTL MMIO32(USB_OTG_FS_BASE + 0x804) -#define OTG_FS_DSTS MMIO32(USB_OTG_FS_BASE + 0x808) -#define OTG_FS_DIEPMSK MMIO32(USB_OTG_FS_BASE + 0x810) -#define OTG_FS_DOEPMSK MMIO32(USB_OTG_FS_BASE + 0x814) -#define OTG_FS_DAINT MMIO32(USB_OTG_FS_BASE + 0x818) -#define OTG_FS_DAINTMSK MMIO32(USB_OTG_FS_BASE + 0x81C) -#define OTG_FS_DVBUSDIS MMIO32(USB_OTG_FS_BASE + 0x828) -#define OTG_FS_DVBUSPULSE MMIO32(USB_OTG_FS_BASE + 0x82C) -#define OTG_FS_DIEPEMPMSK MMIO32(USB_OTG_FS_BASE + 0x834) -#define OTG_FS_DIEPCTL0 MMIO32(USB_OTG_FS_BASE + 0x900) -#define OTG_FS_DIEPCTL(x) MMIO32(USB_OTG_FS_BASE + 0x900 + 0x20*(x)) -#define OTG_FS_DOEPCTL0 MMIO32(USB_OTG_FS_BASE + 0xB00) -#define OTG_FS_DOEPCTL(x) MMIO32(USB_OTG_FS_BASE + 0xB00 + 0x20*(x)) -#define OTG_FS_DIEPINT(x) MMIO32(USB_OTG_FS_BASE + 0x908 + 0x20*(x)) -#define OTG_FS_DOEPINT(x) MMIO32(USB_OTG_FS_BASE + 0xB08 + 0x20*(x)) -#define OTG_FS_DIEPTSIZ0 MMIO32(USB_OTG_FS_BASE + 0x910) -#define OTG_FS_DOEPTSIZ0 MMIO32(USB_OTG_FS_BASE + 0xB10) -#define OTG_FS_DIEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + 0x910 + 0x20*(x)) -#define OTG_FS_DTXFSTS(x) MMIO32(USB_OTG_FS_BASE + 0x918 + 0x20*(x)) -#define OTG_FS_DOEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + 0xB10 + 0x20*(x)) - -/* Power and clock gating control and status register */ -#define OTG_FS_PCGCCTL MMIO32(USB_OTG_FS_BASE + 0xE00) - -/* Data FIFO */ -#define OTG_FS_FIFO(x) ((u32*)(USB_OTG_FS_BASE + (((x) + 1) << 12))) - -/* Global CSRs */ -/* OTG_FS AHB configuration register (OTG_FS_GAHBCFG) */ -#define OTG_FS_GAHBCFG_GINT 0x0001 -#define OTG_FS_GAHBCFG_TXFELVL 0x0080 -#define OTG_FS_GAHBCFG_PTXFELVL 0x0100 - -/* OTG_FS USB configuration register (OTG_FS_GUSBCFG) */ -#define OTG_FS_GUSBCFG_TOCAL 0x00000003 -#define OTG_FS_GUSBCFG_SRPCAP 0x00000100 -#define OTG_FS_GUSBCFG_HNPCAP 0x00000200 -#define OTG_FS_GUSBCFG_TRDT_MASK (0xf << 10) -#define OTG_FS_GUSBCFG_TRDT_16BIT (0x5 << 10) -#define OTG_FS_GUSBCFG_TRDT_8BIT (0x9 << 10) -#define OTG_FS_GUSBCFG_NPTXRWEN 0x00004000 -#define OTG_FS_GUSBCFG_FHMOD 0x20000000 -#define OTG_FS_GUSBCFG_FDMOD 0x40000000 -#define OTG_FS_GUSBCFG_CTXPKT 0x80000000 -/* WARNING: not in reference manual */ -#define OTG_FS_GUSBCFG_PHYSEL (1 << 6) - -/* OTG_FS reset register (OTG_FS_GRSTCTL) */ -#define OTG_FS_GRSTCTL_AHBIDL (1 << 31) -/* Bits 30:11 - Reserved */ -#define OTG_FS_GRSTCTL_TXFNUM_MASK (0x1f << 6) -#define OTG_FS_GRSTCTL_TXFFLSH (1 << 5) -#define OTG_FS_GRSTCTL_RXFFLSH (1 << 4) -/* Bit 3 - Reserved */ -#define OTG_FS_GRSTCTL_FCRST (1 << 2) -#define OTG_FS_GRSTCTL_HSRST (1 << 1) -#define OTG_FS_GRSTCTL_CSRST (1 << 0) - -/* OTG_FS interrupt status register (OTG_FS_GINTSTS) */ -#define OTG_FS_GINTSTS_WKUPINT (1 << 31) -#define OTG_FS_GINTSTS_SRQINT (1 << 30) -#define OTG_FS_GINTSTS_DISCINT (1 << 29) -#define OTG_FS_GINTSTS_CIDSCHG (1 << 28) -/* Bit 27 - Reserved */ -#define OTG_FS_GINTSTS_PTXFE (1 << 26) -#define OTG_FS_GINTSTS_HCINT (1 << 25) -#define OTG_FS_GINTSTS_HPRTINT (1 << 24) -/* Bits 23:22 - Reserved */ -#define OTG_FS_GINTSTS_IPXFR (1 << 21) -#define OTG_FS_GINTSTS_INCOMPISOOUT (1 << 21) -#define OTG_FS_GINTSTS_IISOIXFR (1 << 20) -#define OTG_FS_GINTSTS_OEPINT (1 << 19) -#define OTG_FS_GINTSTS_IEPINT (1 << 18) -/* Bits 17:16 - Reserved */ -#define OTG_FS_GINTSTS_EOPF (1 << 15) -#define OTG_FS_GINTSTS_ISOODRP (1 << 14) -#define OTG_FS_GINTSTS_ENUMDNE (1 << 13) -#define OTG_FS_GINTSTS_USBRST (1 << 12) -#define OTG_FS_GINTSTS_USBSUSP (1 << 11) -#define OTG_FS_GINTSTS_ESUSP (1 << 10) -/* Bits 9:8 - Reserved */ -#define OTG_FS_GINTSTS_GONAKEFF (1 << 7) -#define OTG_FS_GINTSTS_GINAKEFF (1 << 6) -#define OTG_FS_GINTSTS_NPTXFE (1 << 5) -#define OTG_FS_GINTSTS_RXFLVL (1 << 4) -#define OTG_FS_GINTSTS_SOF (1 << 3) -#define OTG_FS_GINTSTS_OTGINT (1 << 2) -#define OTG_FS_GINTSTS_MMIS (1 << 1) -#define OTG_FS_GINTSTS_CMOD (1 << 0) - -/* OTG_FS interrupt mask register (OTG_FS_GINTMSK) */ -#define OTG_FS_GINTMSK_MMISM 0x00000002 -#define OTG_FS_GINTMSK_OTGINT 0x00000004 -#define OTG_FS_GINTMSK_SOFM 0x00000008 -#define OTG_FS_GINTMSK_RXFLVLM 0x00000010 -#define OTG_FS_GINTMSK_NPTXFEM 0x00000020 -#define OTG_FS_GINTMSK_GINAKEFFM 0x00000040 -#define OTG_FS_GINTMSK_GONAKEFFM 0x00000080 -#define OTG_FS_GINTMSK_ESUSPM 0x00000400 -#define OTG_FS_GINTMSK_USBSUSPM 0x00000800 -#define OTG_FS_GINTMSK_USBRST 0x00001000 -#define OTG_FS_GINTMSK_ENUMDNEM 0x00002000 -#define OTG_FS_GINTMSK_ISOODRPM 0x00004000 -#define OTG_FS_GINTMSK_EOPFM 0x00008000 -#define OTG_FS_GINTMSK_EPMISM 0x00020000 -#define OTG_FS_GINTMSK_IEPINT 0x00040000 -#define OTG_FS_GINTMSK_OEPINT 0x00080000 -#define OTG_FS_GINTMSK_IISOIXFRM 0x00100000 -#define OTG_FS_GINTMSK_IISOOXFRM 0x00200000 -#define OTG_FS_GINTMSK_IPXFRM 0x00200000 -#define OTG_FS_GINTMSK_PRTIM 0x01000000 -#define OTG_FS_GINTMSK_HCIM 0x02000000 -#define OTG_FS_GINTMSK_PTXFEM 0x04000000 -#define OTG_FS_GINTMSK_CIDSCHGM 0x10000000 -#define OTG_FS_GINTMSK_DISCINT 0x20000000 -#define OTG_FS_GINTMSK_SRQIM 0x40000000 -#define OTG_FS_GINTMSK_WUIM 0x80000000 - -/* OTG_FS Receive Status Pop Register (OTG_FS_GRXSTSP) */ -/* Bits 31:25 - Reserved */ -#define OTG_FS_GRXSTSP_FRMNUM_MASK (0xf << 21) -#define OTG_FS_GRXSTSP_PKTSTS_MASK (0xf << 17) -#define OTG_FS_GRXSTSP_PKTSTS_GOUTNAK (0x1 << 17) -#define OTG_FS_GRXSTSP_PKTSTS_OUT (0x2 << 17) -#define OTG_FS_GRXSTSP_PKTSTS_OUT_COMP (0x3 << 17) -#define OTG_FS_GRXSTSP_PKTSTS_SETUP_COMP (0x4 << 17) -#define OTG_FS_GRXSTSP_PKTSTS_SETUP (0x6 << 17) -#define OTG_FS_GRXSTSP_DPID_MASK (0x3 << 15) -#define OTG_FS_GRXSTSP_DPID_DATA0 (0x0 << 15) -#define OTG_FS_GRXSTSP_DPID_DATA1 (0x2 << 15) -#define OTG_FS_GRXSTSP_DPID_DATA2 (0x1 << 15) -#define OTG_FS_GRXSTSP_DPID_MDATA (0x3 << 15) -#define OTG_FS_GRXSTSP_BCNT_MASK (0x7ff << 4) -#define OTG_FS_GRXSTSP_EPNUM_MASK (0xf << 0) - -/* OTG_FS general core configuration register (OTG_FS_GCCFG) */ -/* Bits 31:21 - Reserved */ -#define OTG_FS_GCCFG_SOFOUTEN (1 << 20) -#define OTG_FS_GCCFG_VBUSBSEN (1 << 19) -#define OTG_FS_GCCFG_VBUSASEN (1 << 18) -/* Bit 17 - Reserved */ -#define OTG_FS_GCCFG_PWRDWN (1 << 16) -/* Bits 15:0 - Reserved */ - - -/* Device-mode CSRs */ -/* OTG_FS device control register (OTG_FS_DCTL) */ -/* Bits 31:12 - Reserved */ -#define OTG_FS_DCTL_POPRGDNE (1 << 11) -#define OTG_FS_DCTL_CGONAK (1 << 10) -#define OTG_FS_DCTL_SGONAK (1 << 9) -#define OTG_FS_DCTL_SGINAK (1 << 8) -#define OTG_FS_DCTL_TCTL_MASK (7 << 4) -#define OTG_FS_DCTL_GONSTS (1 << 3) -#define OTG_FS_DCTL_GINSTS (1 << 2) -#define OTG_FS_DCTL_SDIS (1 << 1) -#define OTG_FS_DCTL_RWUSIG (1 << 0) - -/* OTG_FS device configuration register (OTG_FS_DCFG) */ -#define OTG_FS_DCFG_DSPD 0x0003 -#define OTG_FS_DCFG_NZLSOHSK 0x0004 -#define OTG_FS_DCFG_DAD 0x07F0 -#define OTG_FS_DCFG_PFIVL 0x1800 - -/* OTG_FS Device IN Endpoint Common Interrupt Mask Register (OTG_FS_DIEPMSK) */ -/* Bits 31:10 - Reserved */ -#define OTG_FS_DIEPMSK_BIM (1 << 9) -#define OTG_FS_DIEPMSK_TXFURM (1 << 8) -/* Bit 7 - Reserved */ -#define OTG_FS_DIEPMSK_INEPNEM (1 << 6) -#define OTG_FS_DIEPMSK_INEPNMM (1 << 5) -#define OTG_FS_DIEPMSK_ITTXFEMSK (1 << 4) -#define OTG_FS_DIEPMSK_TOM (1 << 3) -/* Bit 2 - Reserved */ -#define OTG_FS_DIEPMSK_EPDM (1 << 1) -#define OTG_FS_DIEPMSK_XFRCM (1 << 0) - -/* OTG_FS Device OUT Endpoint Common Interrupt Mask Register (OTG_FS_DOEPMSK) */ -/* Bits 31:10 - Reserved */ -#define OTG_FS_DOEPMSK_BOIM (1 << 9) -#define OTG_FS_DOEPMSK_OPEM (1 << 8) -/* Bit 7 - Reserved */ -#define OTG_FS_DOEPMSK_B2BSTUP (1 << 6) -/* Bit 5 - Reserved */ -#define OTG_FS_DOEPMSK_OTEPDM (1 << 4) -#define OTG_FS_DOEPMSK_STUPM (1 << 3) -/* Bit 2 - Reserved */ -#define OTG_FS_DOEPMSK_EPDM (1 << 1) -#define OTG_FS_DOEPMSK_XFRCM (1 << 0) - -/* OTG_FS Device Control IN Endpoint 0 Control Register (OTG_FS_DIEPCTL0) */ -#define OTG_FS_DIEPCTL0_EPENA (1 << 31) -#define OTG_FS_DIEPCTL0_EPDIS (1 << 30) -/* Bits 29:28 - Reserved */ -#define OTG_FS_DIEPCTLX_SD0PID (1 << 28) -#define OTG_FS_DIEPCTL0_SNAK (1 << 27) -#define OTG_FS_DIEPCTL0_CNAK (1 << 26) -#define OTG_FS_DIEPCTL0_TXFNUM_MASK (0xf << 22) -#define OTG_FS_DIEPCTL0_STALL (1 << 21) -/* Bit 20 - Reserved */ -#define OTG_FS_DIEPCTL0_EPTYP_MASK (0x3 << 18) -#define OTG_FS_DIEPCTL0_NAKSTS (1 << 17) -/* Bit 16 - Reserved */ -#define OTG_FS_DIEPCTL0_USBAEP (1 << 15) -/* Bits 14:2 - Reserved */ -#define OTG_FS_DIEPCTL0_MPSIZ_MASK (0x3 << 0) -#define OTG_FS_DIEPCTL0_MPSIZ_64 (0x0 << 0) -#define OTG_FS_DIEPCTL0_MPSIZ_32 (0x1 << 0) -#define OTG_FS_DIEPCTL0_MPSIZ_16 (0x2 << 0) -#define OTG_FS_DIEPCTL0_MPSIZ_8 (0x3 << 0) - -/* OTG_FS Device Control OUT Endpoint 0 Control Register (OTG_FS_DOEPCTL0) */ -#define OTG_FS_DOEPCTL0_EPENA (1 << 31) -#define OTG_FS_DOEPCTL0_EPDIS (1 << 30) -/* Bits 29:28 - Reserved */ -#define OTG_FS_DOEPCTLX_SD0PID (1 << 28) -#define OTG_FS_DOEPCTL0_SNAK (1 << 27) -#define OTG_FS_DOEPCTL0_CNAK (1 << 26) -/* Bits 25:22 - Reserved */ -#define OTG_FS_DOEPCTL0_STALL (1 << 21) -#define OTG_FS_DOEPCTL0_SNPM (1 << 20) -#define OTG_FS_DOEPCTL0_EPTYP_MASK (0x3 << 18) -#define OTG_FS_DOEPCTL0_NAKSTS (1 << 17) -/* Bit 16 - Reserved */ -#define OTG_FS_DOEPCTL0_USBAEP (1 << 15) -/* Bits 14:2 - Reserved */ -#define OTG_FS_DOEPCTL0_MPSIZ_MASK (0x3 << 0) -#define OTG_FS_DOEPCTL0_MPSIZ_64 (0x0 << 0) -#define OTG_FS_DOEPCTL0_MPSIZ_32 (0x1 << 0) -#define OTG_FS_DOEPCTL0_MPSIZ_16 (0x2 << 0) -#define OTG_FS_DOEPCTL0_MPSIZ_8 (0x3 << 0) - -/* OTG_FS Device IN Endpoint Interrupt Register (OTG_FS_DIEPINTx) */ -/* Bits 31:8 - Reserved */ -#define OTG_FS_DIEPINTX_TXFE (1 << 7) -#define OTG_FS_DIEPINTX_INEPNE (1 << 6) -/* Bit 5 - Reserved */ -#define OTG_FS_DIEPINTX_ITTXFE (1 << 4) -#define OTG_FS_DIEPINTX_TOC (1 << 3) -/* Bit 2 - Reserved */ -#define OTG_FS_DIEPINTX_EPDISD (1 << 1) -#define OTG_FS_DIEPINTX_XFRC (1 << 0) - -/* OTG_FS Device IN Endpoint Interrupt Register (OTG_FS_DOEPINTx) */ -/* Bits 31:7 - Reserved */ -#define OTG_FS_DOEPINTX_B2BSTUP (1 << 6) -/* Bit 5 - Reserved */ -#define OTG_FS_DOEPINTX_OTEPDIS (1 << 4) -#define OTG_FS_DOEPINTX_STUP (1 << 3) -/* Bit 2 - Reserved */ -#define OTG_FS_DOEPINTX_EPDISD (1 << 1) -#define OTG_FS_DOEPINTX_XFRC (1 << 0) - -/* OTG_FS Device OUT Endpoint 0 Transfer Size Regsiter (OTG_FS_DOEPTSIZ0) */ -/* Bit 31 - Reserved */ -#define OTG_FS_DIEPSIZ0_STUPCNT_1 (0x1 << 29) -#define OTG_FS_DIEPSIZ0_STUPCNT_2 (0x2 << 29) -#define OTG_FS_DIEPSIZ0_STUPCNT_3 (0x3 << 29) -#define OTG_FS_DIEPSIZ0_STUPCNT_MASK (0x3 << 29) -/* Bits 28:20 - Reserved */ -#define OTG_FS_DIEPSIZ0_PKTCNT (1 << 19) -/* Bits 18:7 - Reserved */ -#define OTG_FS_DIEPSIZ0_XFRSIZ_MASK (0x7f << 0) - -#endif - diff --git a/include/libopencm3/stm32/pwr.h b/include/libopencm3/stm32/pwr.h deleted file mode 100644 index e5b9804..0000000 --- a/include/libopencm3/stm32/pwr.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_PWR_H -#define LIBOPENCM3_PWR_H - -#include -#include - -/* --- PWR registers ------------------------------------------------------- */ - -/* Power control register (PWR_CR) */ -#define PWR_CR MMIO32(POWER_CONTROL_BASE + 0x00) - -/* Power control/status register (PWR_CSR) */ -#define PWR_CSR MMIO32(POWER_CONTROL_BASE + 0x04) - -/* --- PWR_CR values ------------------------------------------------------- */ - -/* DBP: Disable backup domain write protection */ -#define PWR_CR_DBP (1 << 8) - -/* PLS[7:5]: PVD level selection */ -#define PWR_CR_PLS_LSB 5 -#define PWR_CR_PLS_2V2 0x0 -#define PWR_CR_PLS_2V3 0x1 -#define PWR_CR_PLS_2V4 0x2 -#define PWR_CR_PLS_2V5 0x3 -#define PWR_CR_PLS_2V6 0x4 -#define PWR_CR_PLS_2V7 0x5 -#define PWR_CR_PLS_2V8 0x6 -#define PWR_CR_PLS_2V9 0x7 - -/* PVDE: Power voltage detector enable */ -#define PWR_CR_PVDE (1 << 4) - -/* CSBF: Clear standby flag */ -#define PWR_CR_CSBF (1 << 3) - -/* CWUF: Clear wakeup flag */ -#define PWR_CR_CWUF (1 << 2) - -/* PDDS: Power down deepsleep */ -#define PWR_CR_PDDS (1 << 1) - -/* LPDS: Low-power deepsleep */ -#define PWR_CR_LPDS (1 << 0) - -/* --- PWR_CSR values ------------------------------------------------------ */ - -/* EWUP: Enable WKUP pin */ -#define PWR_CSR_EWUP (1 << 8) - -/* PVDO: PVD output */ -#define PWR_CSR_PVDO (1 << 2) - -/* SBF: Standby flag */ -#define PWR_CSR_SBF (1 << 1) - -/* WUF: Wakeup flag */ -#define PWR_CSR_WUF (1 << 0) - -/* --- PWR function prototypes ------------------------------------------- */ - -#endif diff --git a/include/libopencm3/stm32/rcc.h b/include/libopencm3/stm32/rcc.h deleted file mode 100644 index 1072445..0000000 --- a/include/libopencm3/stm32/rcc.h +++ /dev/null @@ -1,417 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * Copyright (C) 2009 Federico Ruiz-Ugalde - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_RCC_H -#define LIBOPENCM3_RCC_H - -#include -#include - -/* Note: Regs/bits marked (**) only exist in "connectivity line" STM32s. */ -/* Note: Regs/bits marked (XX) do NOT exist in "connectivity line" STM32s. */ - -/* --- RCC registers ------------------------------------------------------- */ - -#define RCC_CR MMIO32(RCC_BASE + 0x00) -#define RCC_CFGR MMIO32(RCC_BASE + 0x04) -#define RCC_CIR MMIO32(RCC_BASE + 0x08) -#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x0c) -#define RCC_APB1RSTR MMIO32(RCC_BASE + 0x10) -#define RCC_AHBENR MMIO32(RCC_BASE + 0x14) -#define RCC_APB2ENR MMIO32(RCC_BASE + 0x18) -#define RCC_APB1ENR MMIO32(RCC_BASE + 0x1c) -#define RCC_BDCR MMIO32(RCC_BASE + 0x20) -#define RCC_CSR MMIO32(RCC_BASE + 0x24) -#define RCC_AHBRSTR MMIO32(RCC_BASE + 0x28) /* (**) */ -#define RCC_CFGR2 MMIO32(RCC_BASE + 0x2c) /* (**) */ - -/* --- RCC_CR values ------------------------------------------------------- */ - -#define RCC_CR_PLL3RDY (1 << 29) /* (**) */ -#define RCC_CR_PLL3ON (1 << 28) /* (**) */ -#define RCC_CR_PLL2RDY (1 << 27) /* (**) */ -#define RCC_CR_PLL2ON (1 << 26) /* (**) */ -#define RCC_CR_PLLRDY (1 << 25) -#define RCC_CR_PLLON (1 << 24) -#define RCC_CR_CSSON (1 << 19) -#define RCC_CR_HSEBYP (1 << 18) -#define RCC_CR_HSERDY (1 << 17) -#define RCC_CR_HSEON (1 << 16) -/* HSICAL: [15:8] */ -/* HSITRIM: [7:3] */ -#define RCC_CR_HSIRDY (1 << 1) -#define RCC_CR_HSION (1 << 0) - -/* --- RCC_CFGR values ----------------------------------------------------- */ - -/* MCO: Microcontroller clock output */ -#define RCC_CFGR_MCO_NOCLK 0x0 -#define RCC_CFGR_MCO_SYSCLK 0x4 -#define RCC_CFGR_MCO_HSICLK 0x5 -#define RCC_CFGR_MCO_HSECLK 0x6 -#define RCC_CFGR_RMCO_PLLCLK_DIV2 0x7 -#define RCC_CFGR_MCO_PLL2CLK 0x8 /* (**) */ -#define RCC_CFGR_MCO_PLL3CLK_DIV2 0x9 /* (**) */ -#define RCC_CFGR_MCO_XT1 0xa /* (**) */ -#define RCC_CFGR_MCO_PLL3 0xb /* (**) */ - -/* USBPRE: USB prescaler (RCC_CFGR[22]) */ -#define RCC_CFGR_USBPRE_PLL_CLK_DIV1_5 0x0 -#define RCC_CFGR_USBPRE_PLL_CLK_NODIV 0x1 - -/* OTGFSPRE: USB OTG FS prescaler (RCC_CFGR[22]; only in conn. line STM32s) */ -#define RCC_CFGR_USBPRE_PLL_VCO_CLK_DIV3 0x0 -#define RCC_CFGR_USBPRE_PLL_VCO_CLK_DIV2 0x1 - -/* PLLMUL: PLL multiplication factor */ -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL2 0x0 /* (XX) */ -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL3 0x1 /* (XX) */ -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL4 0x2 -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL5 0x3 -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL6 0x4 -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL7 0x5 -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL8 0x6 -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL9 0x7 -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL10 0x8 /* (XX) */ -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL11 0x9 /* (XX) */ -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL12 0xa /* (XX) */ -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL13 0xb /* (XX) */ -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL14 0xc /* (XX) */ -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL15 0xd /* 0xd: PLL x 15 */ -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL6_5 0xd /* 0xd: PLL x 6.5 for conn. line */ -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL16 0xe /* (XX) */ -// #define PLLMUL_PLL_CLK_MUL16 0xf /* (XX) */ /* Errata? 17? */ - -/* TODO: conn. line differs. */ -/* PLLXTPRE: HSE divider for PLL entry */ -#define RCC_CFGR_PLLXTPRE_HSE_CLK 0x0 -#define RCC_CFGR_PLLXTPRE_HSE_CLK_DIV2 0x1 - -/* PLLSRC: PLL entry clock source */ -#define RCC_CFGR_PLLSRC_HSI_CLK_DIV2 0x0 -#define RCC_CFGR_PLLSRC_HSE_CLK 0x1 -#define RCC_CFGR_PLLSRC_PREDIV1_CLK 0x1 /* On conn. line */ - -/* ADCPRE: ADC prescaler */ -#define RCC_CFGR_ADCPRE_PCLK2_DIV2 0x0 -#define RCC_CFGR_ADCPRE_PCLK2_DIV4 0x1 -#define RCC_CFGR_ADCPRE_PCLK2_DIV6 0x2 -#define RCC_CFGR_ADCPRE_PCLK2_DIV8 0x3 - -/* PPRE2: APB high-speed prescaler (APB2) */ -#define RCC_CFGR_PPRE2_HCLK_NODIV 0x0 -#define RCC_CFGR_PPRE2_HCLK_DIV2 0x4 -#define RCC_CFGR_PPRE2_HCLK_DIV4 0x5 -#define RCC_CFGR_PPRE2_HCLK_DIV8 0x6 -#define RCC_CFGR_PPRE2_HCLK_DIV16 0x7 - -/* PPRE1: APB low-speed prescaler (APB1) */ -#define RCC_CFGR_PPRE1_HCLK_NODIV 0x0 -#define RCC_CFGR_PPRE1_HCLK_DIV2 0x4 -#define RCC_CFGR_PPRE1_HCLK_DIV4 0x5 -#define RCC_CFGR_PPRE1_HCLK_DIV8 0x6 -#define RCC_CFGR_PPRE1_HCLK_DIV16 0x7 - -/* HPRE: AHB prescaler */ -#define RCC_CFGR_HPRE_SYSCLK_NODIV 0x0 -#define RCC_CFGR_HPRE_SYSCLK_DIV2 0x8 -#define RCC_CFGR_HPRE_SYSCLK_DIV4 0x9 -#define RCC_CFGR_HPRE_SYSCLK_DIV8 0xa -#define RCC_CFGR_HPRE_SYSCLK_DIV16 0xb -#define RCC_CFGR_HPRE_SYSCLK_DIV64 0xc -#define RCC_CFGR_HPRE_SYSCLK_DIV128 0xd -#define RCC_CFGR_HPRE_SYSCLK_DIV256 0xe -#define RCC_CFGR_HPRE_SYSCLK_DIV512 0xf - -/* SWS: System clock switch status */ -#define RCC_CFGR_SWS_SYSCLKSEL_HSICLK 0x0 -#define RCC_CFGR_SWS_SYSCLKSEL_HSECLK 0x1 -#define RCC_CFGR_SWS_SYSCLKSEL_PLLCLK 0x2 - -/* SW: System clock switch */ -#define RCC_CFGR_SW_SYSCLKSEL_HSICLK 0x0 -#define RCC_CFGR_SW_SYSCLKSEL_HSECLK 0x1 -#define RCC_CFGR_SW_SYSCLKSEL_PLLCLK 0x2 - -/* --- RCC_CIR values ------------------------------------------------------ */ - -/* Clock security system interrupt clear bit */ -#define RCC_CIR_CSSC (1 << 23) - -/* OSC ready interrupt clear bits */ -#define RCC_CIR_PLL3RDYC (1 << 22) /* (**) */ -#define RCC_CIR_PLL2RDYC (1 << 21) /* (**) */ -#define RCC_CIR_PLLRDYC (1 << 20) -#define RCC_CIR_HSERDYC (1 << 19) -#define RCC_CIR_HSIRDYC (1 << 18) -#define RCC_CIR_LSERDYC (1 << 17) -#define RCC_CIR_LSIRDYC (1 << 16) - -/* OSC ready interrupt enable bits */ -#define RCC_CIR_PLL3RDYIE (1 << 14) /* (**) */ -#define RCC_CIR_PLL2RDYIE (1 << 13) /* (**) */ -#define RCC_CIR_PLLRDYIE (1 << 12) -#define RCC_CIR_HSERDYIE (1 << 11) -#define RCC_CIR_HSIRDYIE (1 << 10) -#define RCC_CIR_LSERDYIE (1 << 9) -#define RCC_CIR_LSIRDYIE (1 << 8) - -/* Clock security system interrupt flag bit */ -#define RCC_CIR_CSSF (1 << 7) - -/* OSC ready interrupt flag bits */ -#define RCC_CIR_PLL3RDYF (1 << 6) /* (**) */ -#define RCC_CIR_PLL2RDYF (1 << 5) /* (**) */ -#define RCC_CIR_PLLRDYF (1 << 4) -#define RCC_CIR_HSERDYF (1 << 3) -#define RCC_CIR_HSIRDYF (1 << 2) -#define RCC_CIR_LSERDYF (1 << 1) -#define RCC_CIR_LSIRDYF (1 << 0) - -/* --- RCC_APB2RSTR values ------------------------------------------------- */ - -#define RCC_APB2RSTR_ADC3RST (1 << 15) /* (XX) */ -#define RCC_APB2RSTR_USART1RST (1 << 14) -#define RCC_APB2RSTR_TIM8RST (1 << 13) /* (XX) */ -#define RCC_APB2RSTR_SPI1RST (1 << 12) -#define RCC_APB2RSTR_TIM1RST (1 << 11) -#define RCC_APB2RSTR_ADC2RST (1 << 10) -#define RCC_APB2RSTR_ADC1RST (1 << 9) -#define RCC_APB2RSTR_IOPGRST (1 << 8) /* (XX) */ -#define RCC_APB2RSTR_IOPFRST (1 << 7) /* (XX) */ -#define RCC_APB2RSTR_IOPERST (1 << 6) -#define RCC_APB2RSTR_IOPDRST (1 << 5) -#define RCC_APB2RSTR_IOPCRST (1 << 4) -#define RCC_APB2RSTR_IOPBRST (1 << 3) -#define RCC_APB2RSTR_IOPARST (1 << 2) -#define RCC_APB2RSTR_AFIORST (1 << 0) - -/* --- RCC_APB1RSTR values ------------------------------------------------- */ - -#define RCC_APB1RSTR_DACRST (1 << 29) -#define RCC_APB1RSTR_PWRRST (1 << 28) -#define RCC_APB1RSTR_BKPRST (1 << 27) -#define RCC_APB1RSTR_CAN2RST (1 << 26) /* (**) */ -#define RCC_APB1RSTR_CAN1RST (1 << 25) /* (**) */ -#define RCC_APB1RSTR_CANRST (1 << 25) /* (XX) Alias for CAN1RST */ -#define RCC_APB1RSTR_USBRST (1 << 23) /* (XX) */ -#define RCC_APB1RSTR_I2C2RST (1 << 22) -#define RCC_APB1RSTR_I2C1RST (1 << 21) -#define RCC_APB1RSTR_USART5RST (1 << 20) -#define RCC_APB1RSTR_USART4RST (1 << 19) -#define RCC_APB1RSTR_USART3RST (1 << 18) -#define RCC_APB1RSTR_USART2RST (1 << 17) -#define RCC_APB1RSTR_SPI3RST (1 << 15) -#define RCC_APB1RSTR_SPI2RST (1 << 14) -#define RCC_APB1RSTR_WWDGRST (1 << 11) -#define RCC_APB1RSTR_TIM7RST (1 << 5) -#define RCC_APB1RSTR_TIM6RST (1 << 4) -#define RCC_APB1RSTR_TIM5RST (1 << 3) -#define RCC_APB1RSTR_TIM4RST (1 << 2) -#define RCC_APB1RSTR_TIM3RST (1 << 1) -#define RCC_APB1RSTR_TIM2RST (1 << 0) - -/* --- RCC_AHBENR values --------------------------------------------------- */ - -#define RCC_AHBENR_ETHMACENRX (1 << 16) -#define RCC_AHBENR_ETHMACENTX (1 << 15) -#define RCC_AHBENR_ETHMACEN (1 << 14) -#define RCC_AHBENR_OTGFSEN (1 << 12) -#define RCC_AHBENR_SDIOEN (1 << 10) -#define RCC_AHBENR_FSMCEN (1 << 8) -#define RCC_AHBENR_CRCEN (1 << 6) -#define RCC_AHBENR_FLITFEN (1 << 4) -#define RCC_AHBENR_SRAMEN (1 << 2) -#define RCC_AHBENR_DMA2EN (1 << 1) -#define RCC_AHBENR_DMA1EN (1 << 0) - -/* --- RCC_APB2ENR values -------------------------------------------------- */ - -#define RCC_APB2ENR_ADC3EN (1 << 15) /* (XX) */ -#define RCC_APB2ENR_USART1EN (1 << 14) -#define RCC_APB2ENR_TIM8EN (1 << 13) /* (XX) */ -#define RCC_APB2ENR_SPI1EN (1 << 12) -#define RCC_APB2ENR_TIM1EN (1 << 11) -#define RCC_APB2ENR_ADC2EN (1 << 10) -#define RCC_APB2ENR_ADC1EN (1 << 9) -#define RCC_APB2ENR_IOPGEN (1 << 8) /* (XX) */ -#define RCC_APB2ENR_IOPFEN (1 << 7) /* (XX) */ -#define RCC_APB2ENR_IOPEEN (1 << 6) -#define RCC_APB2ENR_IOPDEN (1 << 5) -#define RCC_APB2ENR_IOPCEN (1 << 4) -#define RCC_APB2ENR_IOPBEN (1 << 3) -#define RCC_APB2ENR_IOPAEN (1 << 2) -#define RCC_APB2ENR_AFIOEN (1 << 0) - -/* --- RCC_APB1ENR values -------------------------------------------------- */ - -#define RCC_APB1ENR_DACEN (1 << 29) -#define RCC_APB1ENR_PWREN (1 << 28) -#define RCC_APB1ENR_BKPEN (1 << 27) -#define RCC_APB1ENR_CAN2EN (1 << 26) /* (**) */ -#define RCC_APB1ENR_CAN1EN (1 << 25) /* (**) */ -#define RCC_APB1ENR_CANEN (1 << 25) /* (XX) Alias for CAN1EN */ -#define RCC_APB1ENR_USBEN (1 << 23) /* (XX) */ -#define RCC_APB1ENR_I2C2EN (1 << 22) -#define RCC_APB1ENR_I2C1EN (1 << 21) -#define RCC_APB1ENR_USART5EN (1 << 20) -#define RCC_APB1ENR_USART4EN (1 << 19) -#define RCC_APB1ENR_USART3EN (1 << 18) -#define RCC_APB1ENR_USART2EN (1 << 17) -#define RCC_APB1ENR_SPI3EN (1 << 15) -#define RCC_APB1ENR_SPI2EN (1 << 14) -#define RCC_APB1ENR_WWDGEN (1 << 11) -#define RCC_APB1ENR_TIM7EN (1 << 5) -#define RCC_APB1ENR_TIM6EN (1 << 4) -#define RCC_APB1ENR_TIM5EN (1 << 3) -#define RCC_APB1ENR_TIM4EN (1 << 2) -#define RCC_APB1ENR_TIM3EN (1 << 1) -#define RCC_APB1ENR_TIM2EN (1 << 0) - -/* --- RCC_BDCR values ----------------------------------------------------- */ - -#define RCC_BDCR_BDRST (1 << 16) -#define RCC_BDCR_RTCEN (1 << 15) -/* RCC_BDCR[9:8]: RTCSEL */ -#define RCC_BDCR_LSEBYP (1 << 2) -#define RCC_BDCR_LSERDY (1 << 1) -#define RCC_BDCR_LSEON (1 << 0) - -/* --- RCC_CSR values ------------------------------------------------------ */ - -#define RCC_CSR_LPWRRSTF (1 << 31) -#define RCC_CSR_WWDGRSTF (1 << 30) -#define RCC_CSR_IWDGRSTF (1 << 29) -#define RCC_CSR_SFTRSTF (1 << 28) -#define RCC_CSR_PORRSTF (1 << 27) -#define RCC_CSR_PINRSTF (1 << 26) -#define RCC_CSR_RMVF (1 << 24) -#define RCC_CSR_LSIRDY (1 << 1) -#define RCC_CSR_LSION (1 << 0) - -/* --- RCC_AHBRSTR values -------------------------------------------------- */ - -#define RCC_AHBRSTR_ETHMACRST (1 << 14) -#define RCC_AHBRSTR_OTGFSRST (1 << 12) - -/* --- RCC_CFGR2 values ---------------------------------------------------- */ - -/* I2S3SRC: I2S3 clock source */ -#define RCC_CFGR2_I2S3SRC_SYSCLK 0x0 -#define RCC_CFGR2_I2S3SRC_PLL3_VCO_CLK 0x1 - -/* I2S2SRC: I2S2 clock source */ -#define RCC_CFGR2_I2S2SRC_SYSCLK 0x0 -#define RCC_CFGR2_I2S2SRC_PLL3_VCO_CLK 0x1 - -/* PREDIV1SRC: PREDIV1 entry clock source */ -#define RCC_CFGR2_PREDIV1SRC_HSE_CLK 0x0 -#define RCC_CFGR2_PREDIV1SRC_PLL2_CLK 0x1 - -#define RCC_CFGR2_PLL2MUL (1 << 0) -#define RCC_CFGR2_PREDIV2 (1 << 0) -#define RCC_CFGR2_PREDIV1 (1 << 0) - -/* PLL3MUL: PLL3 multiplication factor */ -#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL8 0x6 -#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL9 0x7 -#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL10 0x8 -#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL11 0x9 -#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL12 0xa -#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL13 0xb -#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL14 0xc -#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL16 0xe -#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL20 0xf - -/* PLL2MUL: PLL2 multiplication factor */ -#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL8 0x6 -#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL9 0x7 -#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL10 0x8 -#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL11 0x9 -#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL12 0xa -#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL13 0xb -#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL14 0xc -#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL16 0xe -#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL20 0xf - -/* PREDIV2: PREDIV2 division factor */ -#define RCC_CFGR2_PREDIV2_NODIV 0x0 -#define RCC_CFGR2_PREDIV2_DIV2 0x1 -#define RCC_CFGR2_PREDIV2_DIV3 0x2 -#define RCC_CFGR2_PREDIV2_DIV4 0x3 -#define RCC_CFGR2_PREDIV2_DIV5 0x4 -#define RCC_CFGR2_PREDIV2_DIV6 0x5 -#define RCC_CFGR2_PREDIV2_DIV7 0x6 -#define RCC_CFGR2_PREDIV2_DIV8 0x7 -#define RCC_CFGR2_PREDIV2_DIV9 0x8 -#define RCC_CFGR2_PREDIV2_DIV10 0x9 -#define RCC_CFGR2_PREDIV2_DIV11 0xa -#define RCC_CFGR2_PREDIV2_DIV12 0xb -#define RCC_CFGR2_PREDIV2_DIV13 0xc -#define RCC_CFGR2_PREDIV2_DIV14 0xd -#define RCC_CFGR2_PREDIV2_DIV15 0xe -#define RCC_CFGR2_PREDIV2_DIV16 0xf - -/* --- Variable definitions ------------------------------------------------ */ -extern u32 rcc_ppre1_frequency; -extern u32 rcc_ppre2_frequency; - -/* --- Function prototypes ------------------------------------------------- */ - -typedef enum { - PLL, HSE, HSI, LSE, LSI -} osc_t; - -void rcc_osc_ready_int_clear(osc_t osc); -void rcc_osc_ready_int_enable(osc_t osc); -void rcc_osc_ready_int_disable(osc_t osc); -int rcc_osc_ready_int_flag(osc_t osc); -void rcc_css_int_clear(void); -int rcc_css_int_flag(void); -void rcc_wait_for_osc_ready(osc_t osc); -void rcc_osc_on(osc_t osc); -void rcc_osc_off(osc_t osc); -void rcc_css_enable(void); -void rcc_css_disable(void); -void rcc_osc_bypass_enable(osc_t osc); -void rcc_osc_bypass_disable(osc_t osc); -void rcc_peripheral_enable_clock(volatile u32 *reg, u32 en); -void rcc_peripheral_disable_clock(volatile u32 *reg, u32 en); -void rcc_peripheral_reset(volatile u32 *reg, u32 reset); -void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset); -void rcc_set_sysclk_source(u32 clk); -void rcc_set_pll_multiplication_factor(u32 mul); -void rcc_set_pll_source(u32 pllsrc); -void rcc_set_pllxtpre(u32 pllxtpre); -void rcc_set_adcpre(u32 adcpre); -void rcc_set_ppre2(u32 ppre2); -void rcc_set_ppre1(u32 ppre1); -void rcc_set_hpre(u32 hpre); -void rcc_set_usbpre(u32 usbpre); -u32 rcc_get_system_clock_source(int i); -void rcc_clock_setup_in_hsi_out_64mhz(void); -void rcc_clock_setup_in_hsi_out_48mhz(void); -void rcc_clock_setup_in_hse_8mhz_out_24mhz(void); -void rcc_clock_setup_in_hse_8mhz_out_72mhz(void); -void rcc_clock_setup_in_hse_12mhz_out_72mhz(void); -void rcc_clock_setup_in_hse_16mhz_out_72mhz(void); -void rcc_backupdomain_reset(void); - -#endif diff --git a/include/libopencm3/stm32/rtc.h b/include/libopencm3/stm32/rtc.h deleted file mode 100644 index b71525e..0000000 --- a/include/libopencm3/stm32/rtc.h +++ /dev/null @@ -1,146 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_RTC_H -#define LIBOPENCM3_RTC_H - -#include -#include -#include - -/* --- RTC registers ------------------------------------------------------- */ - -/* RTC control register high (RTC_CRH) */ -#define RTC_CRH MMIO32(RTC_BASE + 0x00) - -/* RTC control register low (RTC_CRL) */ -#define RTC_CRL MMIO32(RTC_BASE + 0x04) - -/* RTC prescaler load register (RTC_PRLH / RTC_PRLL) */ -#define RTC_PRLH MMIO32(RTC_BASE + 0x08) -#define RTC_PRLL MMIO32(RTC_BASE + 0x0c) - -/* RTC prescaler divider register (RTC_DIVH / RTC_DIVL) */ -#define RTC_DIVH MMIO32(RTC_BASE + 0x10) -#define RTC_DIVL MMIO32(RTC_BASE + 0x14) - -/* RTC counter register (RTC_CNTH / RTC_CNTL) */ -#define RTC_CNTH MMIO32(RTC_BASE + 0x18) -#define RTC_CNTL MMIO32(RTC_BASE + 0x1c) - -/* RTC alarm register high (RTC_ALRH / RTC_ALRL) */ -#define RTC_ALRH MMIO32(RTC_BASE + 0x20) -#define RTC_ALRL MMIO32(RTC_BASE + 0x24) - -/* --- RTC_CRH values -------------------------------------------------------*/ - -/* Note: Bits [15:3] are reserved, and forced to 0 by hardware. */ - -/* OWIE: Overflow interrupt enable */ -#define RTC_CRH_OWIE (1 << 2) - -/* ALRIE: Alarm interrupt enable */ -#define RTC_CRH_ALRIE (1 << 1) - -/* SECIE: Second interrupt enable */ -#define RTC_CRH_SECIE (1 << 0) - -/* --- RTC_CRL values -------------------------------------------------------*/ - -/* Note: Bits [15:6] are reserved, and forced to 0 by hardware. */ - -/* RTOFF: RTC operation OFF */ -#define RTC_CRL_RTOFF (1 << 5) - -/* CNF: Configuration flag */ -#define RTC_CRL_CNF (1 << 4) - -/* RSF: Registers synchronized flag */ -#define RTC_CRL_RSF (1 << 3) - -/* OWF: Overflow flag */ -#define RTC_CRL_OWF (1 << 2) - -/* ALRF: Alarm flag */ -#define RTC_CRL_ALRF (1 << 1) - -/* SECF: Second flag */ -#define RTC_CRL_SECF (1 << 0) - -/* --- RTC_PRLH values ------------------------------------------------------*/ - -/* Note: Bits [15:4] are reserved, and forced to 0 by hardware. */ - -/* TODO */ - -/* --- RTC_PRLL values ------------------------------------------------------*/ - -/* TODO */ - -/* --- RTC_DIVH values ------------------------------------------------------*/ - -/* Bits [15:4] are reserved. */ - -/* TODO */ - -/* --- RTC_DIVL values ------------------------------------------------------*/ - -/* TODO */ - -/* --- RTC_CNTH values ------------------------------------------------------*/ - -/* TODO */ - -/* --- RTC_CNTL values ------------------------------------------------------*/ - -/* TODO */ - -/* --- RTC_ALRH values ------------------------------------------------------*/ - -/* TODO */ - -/* --- RTC_ALRL values ------------------------------------------------------*/ - -/* TODO */ - -/* --- Function prototypes --------------------------------------------------*/ - -typedef enum { - RTC_SEC, RTC_ALR, RTC_OW, -} rtcflag_t; - -void rtc_awake_from_off(osc_t clock_source); -void rtc_enter_config_mode(void); -void rtc_exit_config_mode(void); -void rtc_set_alarm_time(u32 alarm_time); -void rtc_enable_alarm(void); -void rtc_disable_alarm(void); -void rtc_set_prescale_val(u32 prescale_val); -u32 rtc_get_counter_val(void); -u32 rtc_get_prescale_div_val(void); -u32 rtc_get_alarm_val(void); -void rtc_set_counter_val(u32 counter_val); -void rtc_interrupt_enable(rtcflag_t flag_val); -void rtc_interrupt_disable(rtcflag_t flag_val); -void rtc_clear_flag(rtcflag_t flag_val); -u32 rtc_check_flag(rtcflag_t flag_val); -void rtc_awake_from_standby(void); -void rtc_auto_awake(osc_t clock_source, u32 prescale_val); - -#endif diff --git a/include/libopencm3/stm32/scb.h b/include/libopencm3/stm32/scb.h deleted file mode 100644 index 9594cf1..0000000 --- a/include/libopencm3/stm32/scb.h +++ /dev/null @@ -1,300 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_SCB_H -#define LIBOPENCM3_SCB_H - -#include -#include - -/* --- SCB: Registers ------------------------------------------------------ */ - -/* CPUID: CPUID base register */ -#define SCB_CPUID MMIO32(SCB_BASE + 0x00) - -/* ICSR: Interrupt Control State Register */ -#define SCB_ICSR MMIO32(SCB_BASE + 0x04) - -/* VTOR: Vector Table Offset Register */ -#define SCB_VTOR MMIO32(SCB_BASE + 0x08) - -/* AIRCR: Application Interrupt and Reset Control Register */ -#define SCB_AIRCR MMIO32(SCB_BASE + 0x0C) - -/* SCR: System Control Register */ -#define SCB_SCR MMIO32(SCB_BASE + 0x10) - -/* CCR: Configuration Control Register */ -#define SCB_CCR MMIO32(SCB_BASE + 0x14) - -/* SHP: System Handler Priority Registers */ -/* Note: 12 8bit registers */ -#define SCB_SHPR(shpr_id) MMIO8(SCB_BASE + 0x18 + shpr_id) -#define SCB_SHPR1 MMIO8(SCB_BASE + 0x18 + 1) -#define SCB_SHPR2 MMIO8(SCB_BASE + 0x18 + 2) -#define SCB_SHPR3 MMIO8(SCB_BASE + 0x18 + 3) - -/* SHCSR: System Handler Control and State Register */ -#define SCB_SHCSR MMIO32(SCB_BASE + 0x24) - -/* CFSR: Configurable Fault Status Registers */ -#define SCB_CFSR MMIO32(SCB_BASE + 0x28) - -/* HFSR: Hard Fault Status Register */ -#define SCB_HFSR MMIO32(SCB_BASE + 0x2C) - -/* DFSR: Debug Fault Status Register */ -#define SCB_DFSR MMIO32(SCB_BASE + 0x30) - -/* MMFAR: Memory Manage Fault Address Register */ -#define SCB_MMFAR MMIO32(SCB_BASE + 0x34) - -/* BFAR: Bus Fault Address Register */ -#define SCB_BFAR MMIO32(SCB_BASE + 0x38) - -/* AFSR: Auxiliary Fault Status Register */ -#define SCB_AFSR MMIO32(SCB_BASE + 0x3C) - -/* --- SCB values ---------------------------------------------------------- */ - -/* --- SCB_CPUID values ---------------------------------------------------- */ - -/* Implementer[31:24]: Implementer code */ -#define SCP_CPUID_IMPLEMENTER_LSB 24 -/* Variant[23:20]: Variant number */ -#define SCP_CPUID_VARIANT_LSB 20 -/* Constant[19:16]: Reads as 0xF */ -#define SCP_CPUID_CONSTANT_LSB 16 -/* PartNo[15:4]: Part number of the processor */ -#define SCP_CPUID_PARTNO_LSB 4 -/* Revision[3:0]: Revision number */ -#define SCP_CPUID_REVISION_LSB 0 - -/* --- SCB_ICSR values ----------------------------------------------------- */ - -/* NMIPENDSET: NMI set-pending bit */ -#define SCB_ICSR_NMIPENDSET (1 << 31) -/* Bits [30:29]: reserved - must be kept cleared */ -/* PENDSVSET: PendSV set-pending bit */ -#define SCB_ICSR_PENDSVSET (1 << 28) -/* PENDSVCLR: PendSV clear-pending bit */ -#define SCB_ICSR_PENDSVCLR (1 << 27) -/* PENDSTSET: SysTick exception set-pending bit */ -#define SCB_ICSR_PENDSTSET (1 << 26) -/* PENDSTCLR: SysTick exception clear-pending bit */ -#define SCB_ICSR_PENDSTCLR (1 << 25) -/* Bit 24: reserved - must be kept cleared */ -/* Bit 23: reserved for debug - reads as 0 when not in debug mode */ -/* ISRPENDING: Interrupt pending flag, excluding NMI and Faults */ -#define SCB_ICSR_ISRPENDING (1 << 22) -/* VECTPENDING[21:12] Pending vector */ -#define SCB_ICSR_VECTPENDING_LSB 12 -/* RETOBASE: Return to base level */ -#define SCB_ICSR_RETOBASE (1 << 11) -/* Bits [10:9]: reserved - must be kept cleared */ -/* VECTACTIVE[8:0] Active vector */ -#define SCB_ICSR_VECTACTIVE_LSB 0 - -/* --- SCB_VTOR values ----------------------------------------------------- */ - -/* Bits [31:30]: reserved - must be kept cleared */ -/* TBLOFF[29:9]: Vector table base offset field */ -#define SCB_VTOR_TBLOFF_LSB 9 /* inconsistent datasheet - LSB could be 11 */ - -/* --- SCB_AIRCR values ---------------------------------------------------- */ - -/* VECTKEYSTAT[31:16]/ VECTKEY[31:16] Register key */ -#define SCB_AIRCR_VECTKEYSTAT_LSB 16 -#define SCB_AIRCR_VECTKEY 0x05FA0000 -/* ENDIANESS Data endianness bit */ -#define SCB_AIRCR_ENDIANESS (1 << 15) -/* Bits [14:11]: reserved - must be kept cleared */ -/* PRIGROUP[10:8]: Interrupt priority grouping field */ -#define SCB_AIRCR_PRIGROUP_LSB 8 -#define SCB_AIRCR_PRIGROUP_GROUP16_NOSUB 0x3 -#define SCB_AIRCR_PRIGROUP_GROUP8_SUB2 0x4 -#define SCB_AIRCR_PRIGROUP_GROUP4_SUB4 0x5 -#define SCB_AIRCR_PRIGROUP_GROUP2_SUB8 0x6 -#define SCB_AIRCR_PRIGROUP_NOGROUP_SUB16 0x7 -/* Bits [7:3]: reserved - must be kept cleared */ -/* SYSRESETREQ System reset request */ -#define SCB_AIRCR_SYSRESETREQ (1 << 2) -/* VECTCLRACTIVE */ -#define SCB_AIRCR_VECTCLRACTIVE (1 << 1) -/* VECTRESET */ -#define SCB_AIRCR_VECTRESET (1 << 0) - -/* --- SCB_SCR values ------------------------------------------------------ */ - -/* Bits [31:5]: reserved - must be kept cleared */ -/* SEVEONPEND Send Event on Pending bit */ -#define SCB_SCR_SEVEONPEND (1 << 4) -/* Bit 3: reserved - must be kept cleared */ -/* SLEEPDEEP */ -#define SCB_SCR_SLEEPDEEP (1 << 2) -/* SLEEPONEXIT */ -#define SCB_SCR_SLEEPONEXIT (1 << 1) -/* Bit 0: reserved - must be kept cleared */ - -/* --- SCB_CCR values ------------------------------------------------------ */ - -/* Bits [31:10]: reserved - must be kept cleared */ -/* STKALIGN */ -#define SCB_CCR_STKALIGN (1 << 9) -/* BFHFNMIGN */ -#define SCB_CCR_BFHFNMIGN (1 << 8) -/* Bits [7:5]: reserved - must be kept cleared */ -/* DIV_0_TRP */ -#define SCB_CCR_DIV_0_TRP (1 << 4) -/* UNALIGN_TRP */ -#define SCB_CCR_UNALIGN_TRP (1 << 3) -/* Bit 2: reserved - must be kept cleared */ -/* USERSETMPEND */ -#define SCB_CCR_USERSETMPEND (1 << 1) -/* NONBASETHRDENA */ -#define SCB_CCR_NONBASETHRDENA (1 << 0) - -/* --- SCB_SHPR1 values ---------------------------------------------------- */ - -/* Bits [31:24]: reserved - must be kept cleared */ -/* PRI_6[23:16]: Priority of system handler 6, usage fault */ -#define SCB_SHPR1_PRI_6_LSB 16 -/* PRI_5[15:8]: Priority of system handler 5, bus fault */ -#define SCB_SHPR1_PRI_5_LSB 8 -/* PRI_4[7:0]: Priority of system handler 4, memory management fault */ -#define SCB_SHPR1_PRI_4_LSB 0 - -/* --- SCB_SHPR2 values ---------------------------------------------------- */ - -/* PRI_11[31:24]: Priority of system handler 11, SVCall */ -#define SCB_SHPR2_PRI_11_LSB 24 -/* Bits [23:0]: reserved - must be kept cleared */ - -/* --- SCB_SHPR3 values ---------------------------------------------------- */ - -/* PRI_15[31:24]: Priority of system handler 15, SysTick exception */ -#define SCB_SHPR3_PRI_15_LSB 24 -/* PRI_14[23:16]: Priority of system handler 14, PendSV */ -#define SCB_SHPR3_PRI_14_LSB 16 -/* Bits [15:0]: reserved - must be kept cleared */ - -/* --- SCB_SHCSR values ---------------------------------------------------- */ - -/* Bits [31:19]: reserved - must be kept cleared */ -/* USGFAULTENA: Usage fault enable */ -#define SCB_SHCSR_USGFAULTENA (1 << 18) -/* BUSFAULTENA: Bus fault enable */ -#define SCB_SHCSR_BUSFAULTENA (1 << 17) -/* MEMFAULTENA: Memory management fault enable */ -#define SCB_SHCSR_MEMFAULTENA (1 << 16) -/* SVCALLPENDED: SVC call pending */ -#define SCB_SHCSR_SVCALLPENDED (1 << 15) -/* BUSFAULTPENDED: Bus fault exception pending */ -#define SCB_SHCSR_BUSFAULTPENDED (1 << 14) -/* MEMFAULTPENDED: Memory management fault exception pending */ -#define SCB_SHCSR_MEMFAULTPENDED (1 << 13) -/* USGFAULTPENDED: Usage fault exception pending */ -#define SCB_SHCSR_USGFAULTPENDED (1 << 12) -/* SYSTICKACT: SysTick exception active */ -#define SCB_SHCSR_SYSTICKACT (1 << 11) -/* PENDSVACT: PendSV exception active */ -#define SCB_SHCSR_PENDSVACT (1 << 10) -/* Bit 9: reserved - must be kept cleared */ -/* MONITORACT: Debug monitor active */ -#define SCB_SHCSR_MONITORACT (1 << 8) -/* SVCALLACT: SVC call active */ -#define SCB_SHCSR_SVCALLACT (1 << 7) -/* Bits [6:4]: reserved - must be kept cleared */ -/* USGFAULTACT: Usage fault exception active */ -#define SCB_SHCSR_USGFAULTACT (1 << 3) -/* Bit 2: reserved - must be kept cleared */ -/* BUSFAULTACT: Bus fault exception active */ -#define SCB_SHCSR_BUSFAULTACT (1 << 1) -/* MEMFAULTACT: Memory management fault exception active */ -#define SCB_SHCSR_MEMFAULTACT (1 << 0) - -/* --- SCB_CFSR values ----------------------------------------------------- */ - -/* Bits [31:26]: reserved - must be kept cleared */ -/* DIVBYZERO: Divide by zero usage fault */ -#define SCB_CFSR_DIVBYZERO (1 << 25) -/* UNALIGNED: Unaligned access usage fault */ -#define SCB_CFSR_UNALIGNED (1 << 24) -/* Bits [23:20]: reserved - must be kept cleared */ -/* NOCP: No coprocessor usage fault */ -#define SCB_CFSR_NOCP (1 << 19) -/* INVPC: Invalid PC load usage fault */ -#define SCB_CFSR_INVPC (1 << 18) -/* INVSTATE: Invalid state usage fault */ -#define SCB_CFSR_INVSTATE (1 << 17) -/* UNDEFINSTR: Undefined instruction usage fault */ -#define SCB_CFSR_UNDEFINSTR (1 << 16) -/* BFARVALID: Bus Fault Address Register (BFAR) valid flag */ -#define SCB_CFSR_BFARVALID (1 << 15) -/* Bits [14:13]: reserved - must be kept cleared */ -/* STKERR: Bus fault on stacking for exception entry */ -#define SCB_CFSR_STKERR (1 << 12) -/* UNSTKERR: Bus fault on unstacking for a return from exception */ -#define SCB_CFSR_UNSTKERR (1 << 11) -/* IMPRECISERR: Imprecise data bus error */ -#define SCB_CFSR_IMPRECISERR (1 << 10) -/* PRECISERR: Precise data bus error */ -#define SCB_CFSR_PRECISERR (1 << 9) -/* IBUSERR: Instruction bus error */ -#define SCB_CFSR_IBUSERR (1 << 8) -/* MMARVALID: Memory Management Fault Address Register (MMAR) valid flag */ -#define SCB_CFSR_MMARVALID (1 << 7) -/* Bits [6:5]: reserved - must be kept cleared */ -/* MSTKERR: Memory manager fault on stacking for exception entry */ -#define SCB_CFSR_MSTKERR (1 << 4) -/* MUNSTKERR: Memory manager fault on unstacking for a return from exception */ -#define SCB_CFSR_MUNSTKERR (1 << 3) -/* Bit 2: reserved - must be kept cleared */ -/* DACCVIOL: Data access violation flag */ -#define SCB_CFSR_DACCVIOL (1 << 1) -/* IACCVIOL: Instruction access violation flag */ -#define SCB_CFSR_IACCVIOL (1 << 0) - -/* --- SCB_HFSR values ----------------------------------------------------- */ - -/* DEBUG_VT: reserved for debug use */ -#define SCB_HFSR_DEBUG_VT (1 << 31) -/* FORCED: Forced hard fault */ -#define SCB_HFSR_FORCED (1 << 30) -/* Bits [29:2]: reserved - must be kept cleared */ -/* VECTTBL: Vector table hard fault */ -#define SCB_HFSR_VECTTBL (1 << 1) -/* Bit 0: reserved - must be kept cleared */ - -/* --- SCB_MMFAR values ---------------------------------------------------- */ - -/* MMFAR [31:0]: Memory management fault address */ - -/* --- SCB_BFAR values ----------------------------------------------------- */ - -/* BFAR [31:0]: Bus fault address */ - -/* --- SCB functions ------------------------------------------------------- */ -void scb_reset_core(void); -void scb_reset_system(void); - -/* TODO: */ - -#endif diff --git a/include/libopencm3/stm32/spi.h b/include/libopencm3/stm32/spi.h deleted file mode 100644 index 726310a..0000000 --- a/include/libopencm3/stm32/spi.h +++ /dev/null @@ -1,331 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_SPI_H -#define LIBOPENCM3_SPI_H - -#include -#include - -/* Registers can be accessed as 16bit or 32bit values. */ - -/* --- Convenience macros -------------------------------------------------- */ - -#define SPI1 SPI1_BASE -#define SPI2 SPI2_I2S_BASE -#define SPI3 SPI3_I2S_BASE - -/* --- SPI registers ------------------------------------------------------- */ - -/* Control register 1 (SPIx_CR1) */ -#define SPI_CR1(spi_base) MMIO32(spi_base + 0x00) -#define SPI1_CR1 SPI_CR1(SPI1_BASE) -#define SPI2_CR1 SPI_CR1(SPI2_I2S_BASE) -#define SPI3_CR1 SPI_CR1(SPI3_I2S_BASE) - -/* Control register 2 (SPIx_CR2) */ -#define SPI_CR2(spi_base) MMIO32(spi_base + 0x04) -#define SPI1_CR2 SPI_CR2(SPI1_BASE) -#define SPI2_CR2 SPI_CR2(SPI2_I2S_BASE) -#define SPI3_CR2 SPI_CR2(SPI3_I2S_BASE) - -/* Status register (SPIx_SR) */ -#define SPI_SR(spi_base) MMIO32(spi_base + 0x08) -#define SPI1_SR SPI_SR(SPI1_BASE) -#define SPI2_SR SPI_SR(SPI2_I2S_BASE) -#define SPI3_SR SPI_SR(SPI3_I2S_BASE) - -/* Data register (SPIx_DR) */ -#define SPI_DR(spi_base) MMIO32(spi_base + 0x0c) -#define SPI1_DR SPI_DR(SPI1_BASE) -#define SPI2_DR SPI_DR(SPI2_I2S_BASE) -#define SPI3_DR SPI_DR(SPI3_I2S_BASE) - -/* CRC polynomial register (SPIx_CRCPR) */ -/* Note: Not used in I2S mode. */ -#define SPI_CRCPR(spi_base) MMIO32(spi_base + 0x10) -#define SPI1_CRCPR SPI_CRCPR(SPI1_BASE) -#define SPI2_CRCPR SPI_CRCPR(SPI2_I2S_BASE) -#define SPI3_CRCPR SPI_CRCPR(SPI3_I2S_BASE) - -/* RX CRC register (SPIx_RXCRCR) */ -/* Note: Not used in I2S mode. */ -#define SPI_RXCRCR(spi_base) MMIO32(spi_base + 0x14) -#define SPI1_RXCRCR SPI_RXCRCR(SPI1_BASE) -#define SPI2_RXCRCR SPI_RXCRCR(SPI2_I2S_BASE) -#define SPI3_RXCRCR SPI_RXCRCR(SPI3_I2S_BASE) - -/* TX CRC register (SPIx_RXCRCR) */ -/* Note: Not used in I2S mode. */ -#define SPI_TXCRCR(spi_base) MMIO32(spi_base + 0x18) -#define SPI1_TXCRCR SPI_TXCRCR(SPI1_BASE) -#define SPI2_TXCRCR SPI_TXCRCR(SPI2_I2S_BASE) -#define SPI3_TXCRCR SPI_TXCRCR(SPI3_I2S_BASE) - -/* I2S configuration register (SPIx_I2SCFGR) */ -#define SPI_I2SCFGR(spi_base) MMIO32(spi_base + 0x1c) -#define SPI1_I2SCFGR SPI_I2SCFGR(SPI1_BASE) -#define SPI2_I2SCFGR SPI_I2SCFGR(SPI2_I2S_BASE) -#define SPI3_I2SCFGR SPI_I2SCFGR(SPI3_I2S_BASE) - -/* I2S prescaler register (SPIx_I2SPR) */ -#define SPI_I2SPR(spi_base) MMIO32(spi_base + 0x20) -#define SPI1_I2SPR SPI_I2SPR(SPI1_BASE) -#define SPI2_I2SPR SPI_I2SPR(SPI2_I2S_BASE) -#define SPI3_I2SPR SPI_I2SPR(SPI3_I2S_BASE) - -/* --- SPI_CR1 values ------------------------------------------------------ */ - -/* Note: None of the CR1 bits are used in I2S mode. */ - -/* BIDIMODE: Bidirectional data mode enable */ -#define SPI_CR1_BIDIMODE_2LINE_UNIDIR (0 << 15) -#define SPI_CR1_BIDIMODE_1LINE_BIDIR (1 << 15) -#define SPI_CR1_BIDIMODE (1 << 15) - -/* BIDIOE: Output enable in bidirectional mode */ -#define SPI_CR1_BIDIOE (1 << 14) - -/* CRCEN: Hardware CRC calculation enable */ -#define SPI_CR1_CRCEN (1 << 13) - -/* CRCNEXT: Transmit CRC next */ -#define SPI_CR1_CRCNEXT (1 << 12) - -/* DFF: Data frame format */ -#define SPI_CR1_DFF_8BIT (0 << 11) -#define SPI_CR1_DFF_16BIT (1 << 11) -#define SPI_CR1_DFF (1 << 11) - -/* RXONLY: Receive only */ -#define SPI_CR1_RXONLY (1 << 10) - -/* SSM: Software slave management */ -#define SPI_CR1_SSM (1 << 9) - -/* SSI: Internal slave select */ -#define SPI_CR1_SSI (1 << 8) - -/* LSBFIRST: Frame format */ -#define SPI_CR1_MSBFIRST (0 << 7) -#define SPI_CR1_LSBFIRST (1 << 7) - -/* SPE: SPI enable */ -#define SPI_CR1_SPE (1 << 6) - -/* BR[2:0]: Baud rate control */ -#define SPI_CR1_BAUDRATE_FPCLK_DIV_2 (0x00 << 3) -#define SPI_CR1_BAUDRATE_FPCLK_DIV_4 (0x01 << 3) -#define SPI_CR1_BAUDRATE_FPCLK_DIV_8 (0x02 << 3) -#define SPI_CR1_BAUDRATE_FPCLK_DIV_16 (0x03 << 3) -#define SPI_CR1_BAUDRATE_FPCLK_DIV_32 (0x04 << 3) -#define SPI_CR1_BAUDRATE_FPCLK_DIV_64 (0x05 << 3) -#define SPI_CR1_BAUDRATE_FPCLK_DIV_128 (0x06 << 3) -#define SPI_CR1_BAUDRATE_FPCLK_DIV_256 (0x07 << 3) -#define SPI_CR1_BR_FPCLK_DIV_2 0x0 -#define SPI_CR1_BR_FPCLK_DIV_4 0x1 -#define SPI_CR1_BR_FPCLK_DIV_8 0x2 -#define SPI_CR1_BR_FPCLK_DIV_16 0x3 -#define SPI_CR1_BR_FPCLK_DIV_32 0x4 -#define SPI_CR1_BR_FPCLK_DIV_64 0x5 -#define SPI_CR1_BR_FPCLK_DIV_128 0x6 -#define SPI_CR1_BR_FPCLK_DIV_256 0x7 - -/* MSTR: Master selection */ -#define SPI_CR1_MSTR (1 << 2) - -/* CPOL: Clock polarity */ -#define SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE (0 << 1) -#define SPI_CR1_CPOL_CLK_TO_1_WHEN_IDLE (1 << 1) -#define SPI_CR1_CPOL (1 << 1) - -/* CPHA: Clock phase */ -#define SPI_CR1_CPHA_CLK_TRANSITION_1 (0 << 0) -#define SPI_CR1_CPHA_CLK_TRANSITION_2 (1 << 0) -#define SPI_CR1_CPHA (1 << 0) - -/* --- SPI_CR1 values ------------------------------------------------------ */ - -/* Bits [15:8]: Reserved. Forced to 0 by hardware. */ - -/* TXEIE: Tx buffer empty interrupt enable */ -#define SPI_CR2_TXEIE (1 << 7) - -/* RXNEIE: RX buffer not empty interrupt enable */ -#define SPI_CR2_RXNEIE (1 << 6) - -/* ERRIE: Error interrupt enable */ -#define SPI_CR2_ERRIE (1 << 5) - -/* Bits [4:3]: Reserved. Forced to 0 by hardware. */ - -/* SSOE: SS output enable */ -#define SPI_CR2_SSOE (1 << 2) - -/* TXDMAEN: Tx buffer DMA enable */ -#define SPI_CR2_TXDMAEN (1 << 1) - -/* RXDMAEN: Rx buffer DMA enable */ -#define SPI_CR2_RXDMAEN (1 << 0) - -/* --- SPI_SR values ------------------------------------------------------- */ - -/* Bits [15:8]: Reserved. Forced to 0 by hardware. */ - -/* BSY: Busy flag */ -#define SPI_SR_BSY (1 << 7) - -/* OVR: Overrun flag */ -#define SPI_SR_OVR (1 << 6) - -/* MODF: Mode fault */ -#define SPI_SR_MODF (1 << 5) - -/* CRCERR: CRC error flag */ -#define SPI_SR_CRCERR (1 << 4) - -/* UDR: Underrun flag */ -#define SPI_SR_UDR (1 << 3) - -/* CHSIDE: Channel side */ -#define SPI_SR_CHSIDE (1 << 2) - -/* TXE: Transmit buffer empty */ -#define SPI_SR_TXE (1 << 1) - -/* RXNE: Receive buffer not empty */ -#define SPI_SR_RXNE (1 << 0) - -/* --- SPI_SR values ------------------------------------------------------- */ - -/* SPI_DR[15:0]: Data Register. */ - -/* --- SPI_CRCPR values ---------------------------------------------------- */ - -/* SPI_CRCPR [15:0]: CRC Polynomial Register. */ - -/* --- SPI_RXCRCR values --------------------------------------------------- */ - -/* SPI_RXCRCR [15:0]: RX CRC Register. */ - -/* --- SPI_TXCRCR values --------------------------------------------------- */ - -/* SPI_TXCRCR [15:0]: TX CRC Register. */ - -/* --- SPI_I2SCFGR values -------------------------------------------------- */ - -/* Bits [15:12]: Reserved. Forced to 0 by hardware. */ - -/* I2SMOD: I2S mode selection */ -#define SPI_I2SCFGR_I2SMOD (1 << 11) - -/* I2SE: I2S Enable */ -#define SPI_I2SCFGR_I2SE (1 << 10) - -/* I2SCFG[9:8]: I2S configuration mode */ -#define SPI_I2SCFGR_I2SCFG_LSB 8 -#define SPI_I2SCFGR_I2SCFG_SLAVE_TRANSMIT 0x0 -#define SPI_I2SCFGR_I2SCFG_SLAVE_RECEIVE 0x1 -#define SPI_I2SCFGR_I2SCFG_MASTER_TRANSMIT 0x2 -#define SPI_I2SCFGR_I2SCFG_MASTER_RECEIVE 0x3 - -/* PCMSYNC: PCM frame synchronization */ -#define SPI_I2SCFGR_PCMSYNC (1 << 7) - -/* Bit 6: Reserved. Forced to 0 by hardware. */ - -/* I2SSTD[5:4]: I2S standard selection */ -#define SPI_I2SCFGR_I2SSTD_LSB 4 -#define SPI_I2SCFGR_I2SSTD_I2S_PHILLIPS 0x0 -#define SPI_I2SCFGR_I2SSTD_MSB_JUSTIFIED 0x1 -#define SPI_I2SCFGR_I2SSTD_LSB_JUSTIFIED 0x2 -#define SPI_I2SCFGR_I2SSTD_PCM 0x3 - -/* CKPOL: Steady state clock polarity */ -#define SPI_I2SCFGR_CKPOL (1 << 3) - -/* DATLEN[2:1]: Data length to be transferred */ -#define SPI_I2SCFGR_DATLEN_LSB 1 -#define SPI_I2SCFGR_DATLEN_16BIT 0x0 -#define SPI_I2SCFGR_DATLEN_24BIT 0x1 -#define SPI_I2SCFGR_DATLEN_32BIT 0x2 - -/* CHLEN: Channel length */ -#define SPI_I2SCFGR_CHLEN (1 << 0) - -/* --- SPI_I2SPR values ---------------------------------------------------- */ - -/* Bits [15:10]: Reserved. Forced to 0 by hardware. */ - -/* MCKOE: Master clock output enable */ -#define SPI_I2SPR_MCKOE (1 << 9) - -/* ODD: Odd factor for the prescaler */ -#define SPI_I2SPR_ODD (1 << 8) - -/* I2SDIV[7:0]: I2S Linear prescaler */ -/* 0 and 1 are forbidden values */ - -/* --- Function prototypes ------------------------------------------------- */ - -int spi_init_master(u32 spi, u32 br, u32 cpol, u32 cpha, u32 dff, u32 lsbfirst); -void spi_enable(u32 spi); -void spi_disable(u32 spi); -void spi_write(u32 spi, u16 data); -void spi_send(u32 spi, u16 data); -u16 spi_read(u32 spi); -void spi_set_bidirectional_mode(u32 spi); -void spi_set_unidirectional_mode(u32 spi); -void spi_set_bidirectional_receive_only_mode(u32 spi); -void spi_set_bidirectional_transmit_only_mode(u32 spi); -void spi_enable_crc(u32 spi); -void spi_disable_crc(u32 spi); -void spi_set_next_tx_from_buffer(u32 spi); -void spi_set_next_tx_from_crc(u32 spi); -void spi_set_dff_8bit(u32 spi); -void spi_set_dff_16bit(u32 spi); -void spi_set_full_duplex_mode(u32 spi); -void spi_set_receive_only_mode(u32 spi); -void spi_disable_software_slave_management(u32 spi); -void spi_enable_software_slave_management(u32 spi); -void spi_set_nss_high(u32 spi); -void spi_set_nss_low(u32 spi); -void spi_send_lsb_first(u32 spi); -void spi_send_msb_first(u32 spi); -void spi_set_baudrate_prescaler(u32 spi, u8 baudrate); -void spi_set_master_mode(u32 spi); -void spi_set_slave_mode(u32 spi); -void spi_set_clock_polarity_1(u32 spi); -void spi_set_clock_polarity_0(u32 spi); -void spi_set_clock_phase_1(u32 spi); -void spi_set_clock_phase_0(u32 spi); -void spi_enable_tx_buffer_empty_interrupt(u32 spi); -void spi_disable_tx_buffer_empty_interrupt(u32 spi); -void spi_enable_rx_buffer_not_empty_interrupt(u32 spi); -void spi_disable_rx_buffer_not_empty_interrupt(u32 spi); -void spi_enable_error_interrupt(u32 spi); -void spi_disable_error_interrupt(u32 spi); -void spi_enable_ss_output(u32 spi); -void spi_disable_ss_output(u32 spi); -void spi_enable_tx_dma(u32 spi); -void spi_disable_tx_dma(u32 spi); -void spi_enable_rx_dma(u32 spi); -void spi_disable_rx_dma(u32 spi); - -#endif diff --git a/include/libopencm3/stm32/systick.h b/include/libopencm3/stm32/systick.h deleted file mode 100644 index 7c2c9a3..0000000 --- a/include/libopencm3/stm32/systick.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_SYSTICK_H -#define LIBOPENCM3_SYSTICK_H - -#include -#include - -/* --- SYSTICK registers --------------------------------------------------- */ - -/* Control and status register (STK_CTRL) */ -#define STK_CTRL MMIO32(SYS_TICK_BASE + 0x00) - -/* reload value register (STK_LOAD) */ -#define STK_LOAD MMIO32(SYS_TICK_BASE + 0x04) - -/* current value register (STK_VAL) */ -#define STK_VAL MMIO32(SYS_TICK_BASE + 0x08) - -/* calibration value register (STK_CALIB) */ -#define STK_CALIB MMIO32(SYS_TICK_BASE + 0x0C) - -/* --- STK_CTRL values ----------------------------------------------------- */ -/* Bits [31:17] Reserved, must be kept cleared. */ -/* COUNTFLAG: */ -#define STK_CTRL_COUNTFLAG (1 << 16) -/* Bits [15:3] Reserved, must be kept cleared. */ -/* CLKSOURCE: Clock source selection */ -#define STK_CTRL_CLKSOURCE (1 << 2) -#define STK_CTRL_CLKSOURCE_LSB 2 -#define STK_CTRL_CLKSOURCE_AHB_DIV8 0 -#define STK_CTRL_CLKSOURCE_AHB 1 -/* TICKINT: SysTick exception request enable */ -#define STK_CTRL_TICKINT (1 << 1) -/* ENABLE: Counter enable */ -#define STK_CTRL_ENABLE (1 << 0) - -/* --- STK_LOAD values ----------------------------------------------------- */ -/* Bits [31:24] Reserved, must be kept cleared. */ -/* RELOAD[23:0]: RELOAD value */ - -/* --- STK_VAL values ------------------------------------------------------ */ -/* Bits [31:24] Reserved, must be kept cleared. */ -/* CURRENT[23:0]: Current counter value */ - -/* --- STK_CALIB values ---------------------------------------------------- */ -/* NOREF: NOREF flag */ -#define STK_CALIB_NOREF (1 << 31) -/* SKEW: SKEW flag */ -#define STK_CALIB_SKEW (1 << 30) -/* Bits [29:24] Reserved, must be kept cleared. */ -/* TENMS[23:0]: Calibration value */ - -/* --- Function Prototypes ------------------------------------------------- */ - -void systick_set_reload(u32 value); -u32 systick_get_value(void); -void systick_set_clocksource(u8 clocksource); -void systick_interrupt_enable(void); -void systick_interrupt_disable(void); -void systick_counter_enable(void); -void systick_counter_disable(void); -u8 systick_get_countflag(void); - -#endif diff --git a/include/libopencm3/stm32/timer.h b/include/libopencm3/stm32/timer.h deleted file mode 100644 index 7b5df86..0000000 --- a/include/libopencm3/stm32/timer.h +++ /dev/null @@ -1,921 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Piotr Esden-Tempski - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_TIMER_H -#define LIBOPENCM3_TIMER_H - -#include -#include - -/* --- Convenience macros -------------------------------------------------- */ - -/* Timer register base adresses (for convenience) */ -#define TIM1 TIM1_BASE -#define TIM2 TIM2_BASE -#define TIM3 TIM3_BASE -#define TIM4 TIM4_BASE -#define TIM5 TIM5_BASE -#define TIM6 TIM6_BASE -#define TIM7 TIM7_BASE -#define TIM8 TIM8_BASE - -/* --- Timer registers ----------------------------------------------------- */ - -/* Control register 1 (TIMx_CR1) */ -#define TIM_CR1(tim_base) MMIO32(tim_base + 0x00) -#define TIM1_CR1 TIM_CR1(TIM1) -#define TIM2_CR1 TIM_CR1(TIM2) -#define TIM3_CR1 TIM_CR1(TIM3) -#define TIM4_CR1 TIM_CR1(TIM4) -#define TIM5_CR1 TIM_CR1(TIM5) -#define TIM6_CR1 TIM_CR1(TIM6) -#define TIM7_CR1 TIM_CR1(TIM7) -#define TIM8_CR1 TIM_CR1(TIM8) - -/* Control register 2 (TIMx_CR2) */ -#define TIM_CR2(tim_base) MMIO32(tim_base + 0x04) -#define TIM1_CR2 TIM_CR2(TIM1) -#define TIM2_CR2 TIM_CR2(TIM2) -#define TIM3_CR2 TIM_CR2(TIM3) -#define TIM4_CR2 TIM_CR2(TIM4) -#define TIM5_CR2 TIM_CR2(TIM5) -#define TIM6_CR2 TIM_CR2(TIM6) -#define TIM7_CR2 TIM_CR2(TIM7) -#define TIM8_CR2 TIM_CR2(TIM8) - -/* Slave mode control register (TIMx_SMCR) */ -#define TIM_SMCR(tim_base) MMIO32(tim_base + 0x08) -#define TIM1_SMCR TIM_SMCR(TIM1) -#define TIM2_SMCR TIM_SMCR(TIM2) -#define TIM3_SMCR TIM_SMCR(TIM3) -#define TIM4_SMCR TIM_SMCR(TIM4) -#define TIM5_SMCR TIM_SMCR(TIM5) -#define TIM8_SMCR TIM_SMCR(TIM8) - -/* DMA/Interrupt enable register (TIMx_DIER) */ -#define TIM_DIER(tim_base) MMIO32(tim_base + 0x0C) -#define TIM1_DIER TIM_DIER(TIM1) -#define TIM2_DIER TIM_DIER(TIM2) -#define TIM3_DIER TIM_DIER(TIM3) -#define TIM4_DIER TIM_DIER(TIM4) -#define TIM5_DIER TIM_DIER(TIM5) -#define TIM6_DIER TIM_DIER(TIM6) -#define TIM7_DIER TIM_DIER(TIM7) -#define TIM8_DIER TIM_DIER(TIM8) - -/* Status register (TIMx_SR) */ -#define TIM_SR(tim_base) MMIO32(tim_base + 0x10) -#define TIM1_SR TIM_SR(TIM1) -#define TIM2_SR TIM_SR(TIM2) -#define TIM3_SR TIM_SR(TIM3) -#define TIM4_SR TIM_SR(TIM4) -#define TIM5_SR TIM_SR(TIM5) -#define TIM6_SR TIM_SR(TIM6) -#define TIM7_SR TIM_SR(TIM7) -#define TIM8_SR TIM_SR(TIM8) - -/* Event generation register (TIMx_EGR) */ -#define TIM_EGR(tim_base) MMIO32(tim_base + 0x14) -#define TIM1_EGR TIM_EGR(TIM1) -#define TIM2_EGR TIM_EGR(TIM2) -#define TIM3_EGR TIM_EGR(TIM3) -#define TIM4_EGR TIM_EGR(TIM4) -#define TIM5_EGR TIM_EGR(TIM5) -#define TIM6_EGR TIM_EGR(TIM6) -#define TIM7_EGR TIM_EGR(TIM7) -#define TIM8_EGR TIM_EGR(TIM8) - -/* Capture/compare mode register 1 (TIMx_CCMR1) */ -#define TIM_CCMR1(tim_base) MMIO32(tim_base + 0x18) -#define TIM1_CCMR1 TIM_CCMR1(TIM1) -#define TIM2_CCMR1 TIM_CCMR1(TIM2) -#define TIM3_CCMR1 TIM_CCMR1(TIM3) -#define TIM4_CCMR1 TIM_CCMR1(TIM4) -#define TIM5_CCMR1 TIM_CCMR1(TIM5) -#define TIM8_CCMR1 TIM_CCMR1(TIM8) - -/* Capture/compare mode register 2 (TIMx_CCMR2) */ -#define TIM_CCMR2(tim_base) MMIO32(tim_base + 0x1C) -#define TIM1_CCMR2 TIM_CCMR2(TIM1) -#define TIM2_CCMR2 TIM_CCMR2(TIM2) -#define TIM3_CCMR2 TIM_CCMR2(TIM3) -#define TIM4_CCMR2 TIM_CCMR2(TIM4) -#define TIM5_CCMR2 TIM_CCMR2(TIM5) -#define TIM8_CCMR2 TIM_CCMR2(TIM8) - -/* Capture/compare enable register (TIMx_CCER) */ -#define TIM_CCER(tim_base) MMIO32(tim_base + 0x20) -#define TIM1_CCER TIM_CCER(TIM1) -#define TIM2_CCER TIM_CCER(TIM2) -#define TIM3_CCER TIM_CCER(TIM3) -#define TIM4_CCER TIM_CCER(TIM4) -#define TIM5_CCER TIM_CCER(TIM5) -#define TIM8_CCER TIM_CCER(TIM8) - -/* Counter (TIMx_CNT) */ -#define TIM_CNT(tim_base) MMIO32(tim_base + 0x24) -#define TIM1_CNT TIM_CNT(TIM1) -#define TIM2_CNT TIM_CNT(TIM2) -#define TIM3_CNT TIM_CNT(TIM3) -#define TIM4_CNT TIM_CNT(TIM4) -#define TIM5_CNT TIM_CNT(TIM5) -#define TIM6_CNT TIM_CNT(TIM6) -#define TIM7_CNT TIM_CNT(TIM7) -#define TIM8_CNT TIM_CNT(TIM8) - -/* Prescaler (TIMx_PSC) */ -#define TIM_PSC(tim_base) MMIO32(tim_base + 0x28) -#define TIM1_PSC TIM_PSC(TIM1) -#define TIM2_PSC TIM_PSC(TIM2) -#define TIM3_PSC TIM_PSC(TIM3) -#define TIM4_PSC TIM_PSC(TIM4) -#define TIM5_PSC TIM_PSC(TIM5) -#define TIM6_PSC TIM_PSC(TIM6) -#define TIM7_PSC TIM_PSC(TIM7) -#define TIM8_PSC TIM_PSC(TIM8) - -/* Auto-reload register (TIMx_ARR) */ -#define TIM_ARR(tim_base) MMIO32(tim_base + 0x2C) -#define TIM1_ARR TIM_ARR(TIM1) -#define TIM2_ARR TIM_ARR(TIM2) -#define TIM3_ARR TIM_ARR(TIM3) -#define TIM4_ARR TIM_ARR(TIM4) -#define TIM5_ARR TIM_ARR(TIM5) -#define TIM6_ARR TIM_ARR(TIM6) -#define TIM7_ARR TIM_ARR(TIM7) -#define TIM8_ARR TIM_ARR(TIM8) - -/* Repetition counter register (TIMx_RCR) */ -#define TIM_RCR(tim_base) MMIO32(tim_base + 0x30) -#define TIM1_RCR TIM_RCR(TIM1) -#define TIM8_RCR TIM_RCR(TIM8) - -/* Capture/compare register 1 (TIMx_CCR1) */ -#define TIM_CCR1(tim_base) MMIO32(tim_base + 0x34) -#define TIM1_CCR1 TIM_CCR1(TIM1) -#define TIM2_CCR1 TIM_CCR1(TIM2) -#define TIM3_CCR1 TIM_CCR1(TIM3) -#define TIM4_CCR1 TIM_CCR1(TIM4) -#define TIM5_CCR1 TIM_CCR1(TIM5) -#define TIM8_CCR1 TIM_CCR1(TIM8) - -/* Capture/compare register 2 (TIMx_CCR2) */ -#define TIM_CCR2(tim_base) MMIO32(tim_base + 0x38) -#define TIM1_CCR2 TIM_CCR2(TIM1) -#define TIM2_CCR2 TIM_CCR2(TIM2) -#define TIM3_CCR2 TIM_CCR2(TIM3) -#define TIM4_CCR2 TIM_CCR2(TIM4) -#define TIM5_CCR2 TIM_CCR2(TIM5) -#define TIM8_CCR2 TIM_CCR2(TIM8) - -/* Capture/compare register 3 (TIMx_CCR3) */ -#define TIM_CCR3(tim_base) MMIO32(tim_base + 0x3C) -#define TIM1_CCR3 TIM_CCR3(TIM1) -#define TIM2_CCR3 TIM_CCR3(TIM2) -#define TIM3_CCR3 TIM_CCR3(TIM3) -#define TIM4_CCR3 TIM_CCR3(TIM4) -#define TIM5_CCR3 TIM_CCR3(TIM5) -#define TIM8_CCR3 TIM_CCR3(TIM8) - -/* Capture/compare register 4 (TIMx_CCR4) */ -#define TIM_CCR4(tim_base) MMIO32(tim_base + 0x40) -#define TIM1_CCR4 TIM_CCR4(TIM1) -#define TIM2_CCR4 TIM_CCR4(TIM2) -#define TIM3_CCR4 TIM_CCR4(TIM3) -#define TIM4_CCR4 TIM_CCR4(TIM4) -#define TIM5_CCR4 TIM_CCR4(TIM5) -#define TIM8_CCR4 TIM_CCR4(TIM8) - -/* Break and dead-time register (TIMx_BDTR) */ -#define TIM_BDTR(tim_base) MMIO32(tim_base + 0x44) -#define TIM1_BDTR TIM_BDTR(TIM1) -#define TIM8_BDTR TIM_BDTR(TIM8) - -/* DMA control register (TIMx_DCR) */ -#define TIM_DCR(tim_base) MMIO32(tim_base + 0x48) -#define TIM1_DCR TIM_DCR(TIM1) -#define TIM2_DCR TIM_DCR(TIM2) -#define TIM3_DCR TIM_DCR(TIM3) -#define TIM4_DCR TIM_DCR(TIM4) -#define TIM5_DCR TIM_DCR(TIM5) -#define TIM8_DCR TIM_DCR(TIM8) - -/* DMA address for full transfer (TIMx_DMAR) */ -#define TIM_DMAR(tim_base) MMIO32(tim_base + 0x4C) -#define TIM1_DMAR TIM_DMAR(TIM1) -#define TIM2_DMAR TIM_DMAR(TIM2) -#define TIM3_DMAR TIM_DMAR(TIM3) -#define TIM4_DMAR TIM_DMAR(TIM4) -#define TIM5_DMAR TIM_DMAR(TIM5) -#define TIM8_DMAR TIM_DMAR(TIM8) - -/* --- TIMx_CR1 values ----------------------------------------------------- */ - -/* CKD[1:0]: Clock division */ -#define TIM_CR1_CKD_CK_INT (0x0 << 8) -#define TIM_CR1_CKD_CK_INT_MUL_2 (0x1 << 8) -#define TIM_CR1_CKD_CK_INT_MUL_4 (0x2 << 8) -#define TIM_CR1_CKD_CK_INT_MASK (0x3 << 8) - -/* ARPE: Auto-reload preload enable */ -#define TIM_CR1_ARPE (1 << 7) - -/* CMS[1:0]: Center-aligned mode selection */ -#define TIM_CR1_CMS_EDGE (0x0 << 5) -#define TIM_CR1_CMS_CENTER_1 (0x1 << 5) -#define TIM_CR1_CMS_CENTER_2 (0x2 << 5) -#define TIM_CR1_CMS_CENTER_3 (0x3 << 5) -#define TIM_CR1_CMS_MASK (0x3 << 5) - -/* DIR: Direction */ -#define TIM_CR1_DIR_UP (0 << 4) -#define TIM_CR1_DIR_DOWN (1 << 4) - -/* OPM: One pulse mode */ -#define TIM_CR1_OPM (1 << 3) - -/* URS: Update request source */ -#define TIM_CR1_URS (1 << 2) - -/* UDIS: Update disable */ -#define TIM_CR1_UDIS (1 << 1) - -/* CEN: Counter enable */ -#define TIM_CR1_CEN (1 << 0) - -/* --- TIMx_CR2 values ----------------------------------------------------- */ - -/* OIS4: Output idle state 4 (OC4 output) */ -#define TIM_CR2_OIS4 (1 << 14) - -/* OIS3N: Output idle state 3 (OC3N output) */ -#define TIM_CR2_OIS3N (1 << 13) - -/* OIS3: Output idle state 3 (OC3 output) */ -#define TIM_CR2_OIS3 (1 << 12) - -/* OIS2N: Output idle state 2 (OC2N output) */ -#define TIM_CR2_OIS2N (1 << 11) - -/* OIS2: Output idle state 2 (OC2 output) */ -#define TIM_CR2_OIS2 (1 << 10) - -/* OIS1N: Output idle state 1 (OC1N output) */ -#define TIM_CR2_OIS1N (1 << 9) - -/* OIS1: Output idle state 1 (OC1 output) */ -#define TIM_CR2_OIS1 (1 << 8) -#define TIM_CR2_OIS_MASK (0x7f << 8) - -/* TI1S: TI1 selection */ -#define TIM_CR2_TI1S (1 << 7) - -/* MMS[2:0]: Master mode selection */ -#define TIM_CR2_MMS_RESET (0x0 << 4) -#define TIM_CR2_MMS_ENABLE (0x1 << 4) -#define TIM_CR2_MMS_UPDATE (0x2 << 4) -#define TIM_CR2_MMS_COMPARE_PULSE (0x3 << 4) -#define TIM_CR2_MMS_COMPARE_OC1REF (0x4 << 4) -#define TIM_CR2_MMS_COMPARE_OC2REF (0x5 << 4) -#define TIM_CR2_MMS_COMPARE_OC3REF (0x6 << 4) -#define TIM_CR2_MMS_COMPARE_OC4REF (0x7 << 4) -#define TIM_CR2_MMS_MASK (0x7 << 4) - -/* CCDS: Capture/compare DMA selection */ -#define TIM_CR2_CCDS (1 << 3) - -/* CCUS: Capture/compare control update selection */ -#define TIM_CR2_CCUS (1 << 2) - -/* CCPC: Capture/compare preload control */ -#define TIM_CR2_CCPC (1 << 0) - -/* --- TIMx_SMCR values ---------------------------------------------------- */ - -/* ETP: External trigger polarity */ -#define TIM_SMCR_ETP (1 << 15) - -/* ECE: External clock enable */ -#define TIM_SMCR_ECE (1 << 14) - -/* ETPS[1:0]: External trigger prescaler */ -#define TIM_SMCR_ETPS_OFF (0x0 << 12) -#define TIM_SMCR_ETPS_ETRP_DIV_2 (0x1 << 12) -#define TIM_SMCR_ETPS_ETRP_DIV_4 (0x2 << 12) -#define TIM_SMCR_ETPS_ETRP_DIV_8 (0x3 << 12) -#define TIM_SMCR_ETPS_MASK (0X3 << 12) - -/* ETF[3:0]: External trigger filter */ -#define TIM_SMCR_ETF_OFF (0x0 << 8) -#define TIM_SMCR_ETF_CK_INT_N_2 (0x1 << 8) -#define TIM_SMCR_ETF_CK_INT_N_4 (0x2 << 8) -#define TIM_SMCR_ETF_CK_INT_N_8 (0x3 << 8) -#define TIM_SMCR_ETF_DTS_DIV_2_N_6 (0x4 << 8) -#define TIM_SMCR_ETF_DTS_DIV_2_N_8 (0x5 << 8) -#define TIM_SMCR_ETF_DTS_DIV_4_N_6 (0x6 << 8) -#define TIM_SMCR_ETF_DTS_DIV_4_N_8 (0x7 << 8) -#define TIM_SMCR_ETF_DTS_DIV_8_N_6 (0x8 << 8) -#define TIM_SMCR_ETF_DTS_DIV_8_N_8 (0x9 << 8) -#define TIM_SMCR_ETF_DTS_DIV_16_N_5 (0xA << 8) -#define TIM_SMCR_ETF_DTS_DIV_16_N_6 (0xB << 8) -#define TIM_SMCR_ETF_DTS_DIV_16_N_8 (0xC << 8) -#define TIM_SMCR_ETF_DTS_DIV_32_N_5 (0xD << 8) -#define TIM_SMCR_ETF_DTS_DIV_32_N_6 (0xE << 8) -#define TIM_SMCR_ETF_DTS_DIV_32_N_8 (0xF << 8) -#define TIM_SMCR_ETF_MASK (0xF << 8) - -/* MSM: Master/slave mode */ -#define TIM_SMCR_MSM (1 << 7) - -/* TS[2:0]: Trigger selection */ -#define TIM_SMCR_TS_ITR0 (0x0 << 4) -#define TIM_SMCR_TS_ITR1 (0x1 << 4) -#define TIM_SMCR_TS_ITR2 (0x2 << 4) -#define TIM_SMCR_TS_ITR3 (0x3 << 4) -#define TIM_SMCR_TS_IT1F_ED (0x4 << 4) -#define TIM_SMCR_TS_IT1FP1 (0x5 << 4) -#define TIM_SMCR_TS_IT1FP2 (0x6 << 4) -#define TIM_SMCR_TS_ETRF (0x7 << 4) -#define TIM_SMCR_TS_MASK (0x7 << 4) - -/* SMS[2:0]: Slave mode selection */ -#define TIM_SMCR_SMS_OFF (0x0 << 0) -#define TIM_SMCR_SMS_EM1 (0x1 << 0) -#define TIM_SMCR_SMS_EM2 (0x2 << 0) -#define TIM_SMCR_SMS_EM3 (0x3 << 0) -#define TIM_SMCR_SMS_RM (0x4 << 0) -#define TIM_SMCR_SMS_GM (0x5 << 0) -#define TIM_SMCR_SMS_TM (0x6 << 0) -#define TIM_SMCR_SMS_ECM1 (0x7 << 0) -#define TIM_SMCR_SMS_MASK (0x7 << 0) - -/* --- TIMx_DIER values ---------------------------------------------------- */ - -/* TDE: Trigger DMA request enable */ -#define TIM_DIER_TDE (1 << 14) - -/* COMDE: COM DMA request enable */ -#define TIM_DIER_COMDE (1 << 13) - -/* CC4DE: Capture/Compare 4 DMA request enable */ -#define TIM_DIER_CC4DE (1 << 12) - -/* CC3DE: Capture/Compare 3 DMA request enable */ -#define TIM_DIER_CC3DE (1 << 11) - -/* CC2DE: Capture/Compare 2 DMA request enable */ -#define TIM_DIER_CC2DE (1 << 10) - -/* CC1DE: Capture/Compare 1 DMA request enable */ -#define TIM_DIER_CC1DE (1 << 9) - -/* UDE: Update DMA request enable */ -#define TIM_DIER_UDE (1 << 8) - -/* BIE: Break interrupt enable */ -#define TIM_DIER_BIE (1 << 7) - -/* TIE: Trigger interrupt enable */ -#define TIM_DIER_TIE (1 << 6) - -/* COMIE: COM interrupt enable */ -#define TIM_DIER_COMIE (1 << 5) - -/* CC4IE: Capture/compare 4 interrupt enable */ -#define TIM_DIER_CC4IE (1 << 4) - -/* CC3IE: Capture/compare 3 interrupt enable */ -#define TIM_DIER_CC3IE (1 << 3) - -/* CC2IE: Capture/compare 2 interrupt enable */ -#define TIM_DIER_CC2IE (1 << 2) - -/* CC1IE: Capture/compare 1 interrupt enable */ -#define TIM_DIER_CC1IE (1 << 1) - -/* UIE: Update interrupt enable */ -#define TIM_DIER_UIE (1 << 0) - -/* --- TIMx_SR values ------------------------------------------------------ */ - -/* CC4OF: Capture/compare 4 overcapture flag */ -#define TIM_SR_CC4OF (1 << 12) - -/* CC3OF: Capture/compare 3 overcapture flag */ -#define TIM_SR_CC3OF (1 << 11) - -/* CC2OF: Capture/compare 2 overcapture flag */ -#define TIM_SR_CC2OF (1 << 10) - -/* CC1OF: Capture/compare 1 overcapture flag */ -#define TIM_SR_CC1OF (1 << 9) - -/* BIF: Break interrupt flag */ -#define TIM_SR_BIF (1 << 7) - -/* TIF: Trigger interrupt flag */ -#define TIM_SR_TIF (1 << 6) - -/* COMIF: COM interrupt flag */ -#define TIM_SR_COMIF (1 << 5) - -/* CC4IF: Capture/compare 4 interrupt flag */ -#define TIM_SR_CC4IF (1 << 4) - -/* CC3IF: Capture/compare 3 interrupt flag */ -#define TIM_SR_CC3IF (1 << 3) - -/* CC2IF: Capture/compare 2 interrupt flag */ -#define TIM_SR_CC2IF (1 << 2) - -/* CC1IF: Capture/compare 1 interrupt flag */ -#define TIM_SR_CC1IF (1 << 1) - -/* UIF: Update interrupt flag */ -#define TIM_SR_UIF (1 << 0) - -/* --- TIMx_EGR values ----------------------------------------------------- */ - -/* BG: Break generation */ -#define TIM_EGR_BG (1 << 7) - -/* TG: Trigger generation */ -#define TIM_EGR_TG (1 << 6) - -/* COMG: Capture/compare control update generation */ -#define TIM_EGR_COMG (1 << 5) - -/* CC4G: Capture/compare 4 generation */ -#define TIM_EGR_CC4G (1 << 4) - -/* CC3G: Capture/compare 3 generation */ -#define TIM_EGR_CC3G (1 << 3) - -/* CC2G: Capture/compare 2 generation */ -#define TIM_EGR_CC2G (1 << 2) - -/* CC1G: Capture/compare 1 generation */ -#define TIM_EGR_CC1G (1 << 1) - -/* UG: Update generation */ -#define TIM_EGR_UG (1 << 0) - -/* --- TIMx_CCMR1 values --------------------------------------------------- */ - -/* --- Output compare mode --- */ - -/* OC2CE: Output compare 2 clear enable */ -#define TIM_CCMR1_OC2CE (1 << 15) - -/* OC2M[2:0]: Output compare 2 mode */ -#define TIM_CCMR1_OC2M_FROZEN (0x0 << 12) -#define TIM_CCMR1_OC2M_ACTIVE (0x1 << 12) -#define TIM_CCMR1_OC2M_INACTIVE (0x2 << 12) -#define TIM_CCMR1_OC2M_TOGGLE (0x3 << 12) -#define TIM_CCMR1_OC2M_FORCE_LOW (0x4 << 12) -#define TIM_CCMR1_OC2M_FORCE_HIGH (0x5 << 12) -#define TIM_CCMR1_OC2M_PWM1 (0x6 << 12) -#define TIM_CCMR1_OC2M_PWM2 (0x7 << 12) -#define TIM_CCMR1_OC2M_MASK (0x7 << 12) - -/* OC2PE: Output compare 2 preload enable */ -#define TIM_CCMR1_OC2PE (1 << 11) - -/* OC2FE: Output compare 2 fast enable */ -#define TIM_CCMR1_OC2FE (1 << 10) - -/* CC2S[1:0]: Capture/compare 2 selection */ -/* Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in - * TIMx_CCER). */ -#define TIM_CCMR1_CC2S_OUT (0x0 << 8) -#define TIM_CCMR1_CC2S_IN_TI2 (0x1 << 8) -#define TIM_CCMR1_CC2S_IN_TI1 (0x2 << 8) -#define TIM_CCMR1_CC2S_IN_TRC (0x3 << 8) -#define TIM_CCMR1_CC2S_MASK (0x3 << 8) - -/* OC1CE: Output compare 1 clear enable */ -#define TIM_CCMR1_OC1CE (1 << 7) - -/* OC1M[2:0]: Output compare 1 mode */ -#define TIM_CCMR1_OC1M_FROZEN (0x0 << 4) -#define TIM_CCMR1_OC1M_ACTIVE (0x1 << 4) -#define TIM_CCMR1_OC1M_INACTIVE (0x2 << 4) -#define TIM_CCMR1_OC1M_TOGGLE (0x3 << 4) -#define TIM_CCMR1_OC1M_FORCE_LOW (0x4 << 4) -#define TIM_CCMR1_OC1M_FORCE_HIGH (0x5 << 4) -#define TIM_CCMR1_OC1M_PWM1 (0x6 << 4) -#define TIM_CCMR1_OC1M_PWM2 (0x7 << 4) -#define TIM_CCMR1_OC1M_MASK (0x7 << 4) - -/* OC1PE: Output compare 1 preload enable */ -#define TIM_CCMR1_OC1PE (1 << 3) - -/* OC1FE: Output compare 1 fast enable */ -#define TIM_CCMR1_OC1FE (1 << 2) - -/* CC1S[1:0]: Capture/compare 1 selection */ -/* Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in - * TIMx_CCER). */ -#define TIM_CCMR1_CC1S_OUT (0x0 << 0) -#define TIM_CCMR1_CC1S_IN_TI2 (0x1 << 0) -#define TIM_CCMR1_CC1S_IN_TI1 (0x2 << 0) -#define TIM_CCMR1_CC1S_IN_TRC (0x3 << 0) -#define TIM_CCMR1_CC1S_MASK (0x3 << 0) - -/* --- Input capture mode --- */ - -/* IC2F[3:0]: Input capture 2 filter */ -#define TIM_CCMR1_IC2F_OFF (0x0 << 12) -#define TIM_CCMR1_IC2F_CK_INT_N_2 (0x1 << 12) -#define TIM_CCMR1_IC2F_CK_INT_N_4 (0x2 << 12) -#define TIM_CCMR1_IC2F_CK_INT_N_8 (0x3 << 12) -#define TIM_CCMR1_IC2F_DTF_DIV_2_N_6 (0x4 << 12) -#define TIM_CCMR1_IC2F_DTF_DIV_2_N_8 (0x5 << 12) -#define TIM_CCMR1_IC2F_DTF_DIV_4_N_6 (0x6 << 12) -#define TIM_CCMR1_IC2F_DTF_DIV_4_N_8 (0x7 << 12) -#define TIM_CCMR1_IC2F_DTF_DIV_8_N_6 (0x8 << 12) -#define TIM_CCMR1_IC2F_DTF_DIV_8_N_8 (0x9 << 12) -#define TIM_CCMR1_IC2F_DTF_DIV_16_N_5 (0xA << 12) -#define TIM_CCMR1_IC2F_DTF_DIV_16_N_6 (0xB << 12) -#define TIM_CCMR1_IC2F_DTF_DIV_16_N_8 (0xC << 12) -#define TIM_CCMR1_IC2F_DTF_DIV_32_N_5 (0xD << 12) -#define TIM_CCMR1_IC2F_DTF_DIV_32_N_6 (0xE << 12) -#define TIM_CCMR1_IC2F_DTF_DIV_32_N_8 (0xF << 12) -#define TIM_CCMR1_IC2F_MASK (0xF << 12) - -/* IC2PSC[1:0]: Input capture 2 prescaler */ -#define TIM_CCMR1_IC2PSC_OFF (0x0 << 10) -#define TIM_CCMR1_IC2PSC_2 (0x1 << 10) -#define TIM_CCMR1_IC2PSC_4 (0x2 << 10) -#define TIM_CCMR1_IC2PSC_8 (0x3 << 10) -#define TIM_CCMR1_IC2PSC_MASK (0x3 << 10) - -/* IC1F[3:0]: Input capture 1 filter */ -#define TIM_CCMR1_IC1F_OFF (0x0 << 4) -#define TIM_CCMR1_IC1F_CK_INT_N_2 (0x1 << 4) -#define TIM_CCMR1_IC1F_CK_INT_N_4 (0x2 << 4) -#define TIM_CCMR1_IC1F_CK_INT_N_8 (0x3 << 4) -#define TIM_CCMR1_IC1F_DTF_DIV_2_N_6 (0x4 << 4) -#define TIM_CCMR1_IC1F_DTF_DIV_2_N_8 (0x5 << 4) -#define TIM_CCMR1_IC1F_DTF_DIV_4_N_6 (0x6 << 4) -#define TIM_CCMR1_IC1F_DTF_DIV_4_N_8 (0x7 << 4) -#define TIM_CCMR1_IC1F_DTF_DIV_8_N_6 (0x8 << 4) -#define TIM_CCMR1_IC1F_DTF_DIV_8_N_8 (0x9 << 4) -#define TIM_CCMR1_IC1F_DTF_DIV_16_N_5 (0xA << 4) -#define TIM_CCMR1_IC1F_DTF_DIV_16_N_6 (0xB << 4) -#define TIM_CCMR1_IC1F_DTF_DIV_16_N_8 (0xC << 4) -#define TIM_CCMR1_IC1F_DTF_DIV_32_N_5 (0xD << 4) -#define TIM_CCMR1_IC1F_DTF_DIV_32_N_6 (0xE << 4) -#define TIM_CCMR1_IC1F_DTF_DIV_32_N_8 (0xF << 4) -#define TIM_CCMR1_IC1F_MASK (0xF << 4) - -/* IC1PSC[1:0]: Input capture 1 prescaler */ -#define TIM_CCMR1_IC1PSC_OFF (0x0 << 2) -#define TIM_CCMR1_IC1PSC_2 (0x1 << 2) -#define TIM_CCMR1_IC1PSC_4 (0x2 << 2) -#define TIM_CCMR1_IC1PSC_8 (0x3 << 2) -#define TIM_CCMR1_IC1PSC_MASK (0x3 << 2) - -/* --- TIMx_CCMR2 values --------------------------------------------------- */ - -/* --- Output compare mode --- */ - -/* OC4CE: Output compare 4 clear enable */ -#define TIM_CCMR2_OC4CE (1 << 15) - -/* OC4M[2:0]: Output compare 4 mode */ -#define TIM_CCMR2_OC4M_FROZEN (0x0 << 12) -#define TIM_CCMR2_OC4M_ACTIVE (0x1 << 12) -#define TIM_CCMR2_OC4M_INACTIVE (0x2 << 12) -#define TIM_CCMR2_OC4M_TOGGLE (0x3 << 12) -#define TIM_CCMR2_OC4M_FORCE_LOW (0x4 << 12) -#define TIM_CCMR2_OC4M_FORCE_HIGH (0x5 << 12) -#define TIM_CCMR2_OC4M_PWM1 (0x6 << 12) -#define TIM_CCMR2_OC4M_PWM2 (0x7 << 12) -#define TIM_CCMR2_OC4M_MASK (0x7 << 12) - -/* OC4PE: Output compare 4 preload enable */ -#define TIM_CCMR2_OC4PE (1 << 11) - -/* OC4FE: Output compare 4 fast enable */ -#define TIM_CCMR2_OC4FE (1 << 10) - -/* CC4S[1:0]: Capture/compare 4 selection */ -/* Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in - * TIMx_CCER). */ -#define TIM_CCMR2_CC4S_OUT (0x0 << 8) -#define TIM_CCMR2_CC4S_IN_TI2 (0x1 << 8) -#define TIM_CCMR2_CC4S_IN_TI1 (0x2 << 8) -#define TIM_CCMR2_CC4S_IN_TRC (0x3 << 8) -#define TIM_CCMR2_CC4S_MASK (0x3 << 8) - -/* OC3CE: Output compare 3 clear enable */ -#define TIM_CCMR2_OC3CE (1 << 7) - -/* OC3M[2:0]: Output compare 3 mode */ -#define TIM_CCMR2_OC3M_FROZEN (0x0 << 4) -#define TIM_CCMR2_OC3M_ACTIVE (0x1 << 4) -#define TIM_CCMR2_OC3M_INACTIVE (0x2 << 4) -#define TIM_CCMR2_OC3M_TOGGLE (0x3 << 4) -#define TIM_CCMR2_OC3M_FORCE_LOW (0x4 << 4) -#define TIM_CCMR2_OC3M_FORCE_HIGH (0x5 << 4) -#define TIM_CCMR2_OC3M_PWM1 (0x6 << 4) -#define TIM_CCMR2_OC3M_PWM2 (0x7 << 4) -#define TIM_CCMR2_OC3M_MASK (0x7 << 4) - -/* OC3PE: Output compare 3 preload enable */ -#define TIM_CCMR2_OC3PE (1 << 3) - -/* OC3FE: Output compare 3 fast enable */ -#define TIM_CCMR2_OC3FE (1 << 2) - -/* CC3S[1:0]: Capture/compare 3 selection */ -/* Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in - * TIMx_CCER). */ -#define TIM_CCMR2_CC3S_OUT (0x0 << 0) -#define TIM_CCMR2_CC3S_IN_TI2 (0x1 << 0) -#define TIM_CCMR2_CC3S_IN_TI1 (0x2 << 0) -#define TIM_CCMR2_CC3S_IN_TRC (0x3 << 0) -#define TIM_CCMR2_CC3S_MASK (0x3 << 0) - -/* --- Input capture mode --- */ - -/* IC4F[3:0]: Input capture 4 filter */ -#define TIM_CCMR2_IC4F_OFF (0x0 << 12) -#define TIM_CCMR2_IC4F_CK_INT_N_2 (0x1 << 12) -#define TIM_CCMR2_IC4F_CK_INT_N_4 (0x2 << 12) -#define TIM_CCMR2_IC4F_CK_INT_N_8 (0x3 << 12) -#define TIM_CCMR2_IC4F_DTF_DIV_2_N_6 (0x4 << 12) -#define TIM_CCMR2_IC4F_DTF_DIV_2_N_8 (0x5 << 12) -#define TIM_CCMR2_IC4F_DTF_DIV_4_N_6 (0x6 << 12) -#define TIM_CCMR2_IC4F_DTF_DIV_4_N_8 (0x7 << 12) -#define TIM_CCMR2_IC4F_DTF_DIV_8_N_6 (0x8 << 12) -#define TIM_CCMR2_IC4F_DTF_DIV_8_N_8 (0x9 << 12) -#define TIM_CCMR2_IC4F_DTF_DIV_16_N_5 (0xA << 12) -#define TIM_CCMR2_IC4F_DTF_DIV_16_N_6 (0xB << 12) -#define TIM_CCMR2_IC4F_DTF_DIV_16_N_8 (0xC << 12) -#define TIM_CCMR2_IC4F_DTF_DIV_32_N_5 (0xD << 12) -#define TIM_CCMR2_IC4F_DTF_DIV_32_N_6 (0xE << 12) -#define TIM_CCMR2_IC4F_DTF_DIV_32_N_8 (0xF << 12) -#define TIM_CCMR2_IC4F_MASK (0xF << 12) - -/* IC4PSC[1:0]: Input capture 4 prescaler */ -#define TIM_CCMR2_IC4PSC_OFF (0x0 << 10) -#define TIM_CCMR2_IC4PSC_2 (0x1 << 10) -#define TIM_CCMR2_IC4PSC_4 (0x2 << 10) -#define TIM_CCMR2_IC4PSC_8 (0x3 << 10) -#define TIM_CCMR2_IC4PSC_MASK (0x3 << 10) - -/* IC3F[3:0]: Input capture 3 filter */ -#define TIM_CCMR2_IC3F_OFF (0x0 << 4) -#define TIM_CCMR2_IC3F_CK_INT_N_2 (0x1 << 4) -#define TIM_CCMR2_IC3F_CK_INT_N_4 (0x2 << 4) -#define TIM_CCMR2_IC3F_CK_INT_N_8 (0x3 << 4) -#define TIM_CCMR2_IC3F_DTF_DIV_2_N_6 (0x4 << 4) -#define TIM_CCMR2_IC3F_DTF_DIV_2_N_8 (0x5 << 4) -#define TIM_CCMR2_IC3F_DTF_DIV_4_N_6 (0x6 << 4) -#define TIM_CCMR2_IC3F_DTF_DIV_4_N_8 (0x7 << 4) -#define TIM_CCMR2_IC3F_DTF_DIV_8_N_6 (0x8 << 4) -#define TIM_CCMR2_IC3F_DTF_DIV_8_N_8 (0x9 << 4) -#define TIM_CCMR2_IC3F_DTF_DIV_16_N_5 (0xA << 4) -#define TIM_CCMR2_IC3F_DTF_DIV_16_N_6 (0xB << 4) -#define TIM_CCMR2_IC3F_DTF_DIV_16_N_8 (0xC << 4) -#define TIM_CCMR2_IC3F_DTF_DIV_32_N_5 (0xD << 4) -#define TIM_CCMR2_IC3F_DTF_DIV_32_N_6 (0xE << 4) -#define TIM_CCMR2_IC3F_DTF_DIV_32_N_8 (0xF << 4) -#define TIM_CCMR2_IC3F_MASK (0xF << 4) - -/* IC3PSC[1:0]: Input capture 3 prescaler */ -#define TIM_CCMR2_IC3PSC_OFF (0x0 << 2) -#define TIM_CCMR2_IC3PSC_2 (0x1 << 2) -#define TIM_CCMR2_IC3PSC_4 (0x2 << 2) -#define TIM_CCMR2_IC3PSC_8 (0x3 << 2) -#define TIM_CCMR2_IC3PSC_MASK (0x3 << 2) - -/* --- TIMx_CCER values ---------------------------------------------------- */ - -/* CC4P: Capture/compare 4 output polarity */ -#define TIM_CCER_CC4P (1 << 13) - -/* CC4E: Capture/compare 4 output enable */ -#define TIM_CCER_CC4E (1 << 12) - -/* CC3NP: Capture/compare 3 complementary output polarity */ -#define TIM_CCER_CC3NP (1 << 11) - -/* CC3NE: Capture/compare 3 complementary output enable */ -#define TIM_CCER_CC3NE (1 << 10) - -/* CC3P: Capture/compare 3 output polarity */ -#define TIM_CCER_CC3P (1 << 9) - -/* CC3E: Capture/compare 3 output enable */ -#define TIM_CCER_CC3E (1 << 8) - -/* CC2NP: Capture/compare 2 complementary output polarity */ -#define TIM_CCER_CC2NP (1 << 7) - -/* CC2NE: Capture/compare 2 complementary output enable */ -#define TIM_CCER_CC2NE (1 << 6) - -/* CC2P: Capture/compare 2 output polarity */ -#define TIM_CCER_CC2P (1 << 5) - -/* CC2E: Capture/compare 2 output enable */ -#define TIM_CCER_CC2E (1 << 4) - -/* CC1NP: Capture/compare 1 complementary output polarity */ -#define TIM_CCER_CC1NP (1 << 3) - -/* CC1NE: Capture/compare 1 complementary output enable */ -#define TIM_CCER_CC1NE (1 << 2) - -/* CC1P: Capture/compare 1 output polarity */ -#define TIM_CCER_CC1P (1 << 1) - -/* CC1E: Capture/compare 1 output enable */ -#define TIM_CCER_CC1E (1 << 0) - -/* --- TIMx_CNT values ----------------------------------------------------- */ - -/* CNT[15:0]: Counter value */ - -/* --- TIMx_PSC values ----------------------------------------------------- */ - -/* PSC[15:0]: Prescaler value */ - -/* --- TIMx_ARR values ----------------------------------------------------- */ - -/* ARR[15:0]: Prescaler value */ - -/* --- TIMx_RCR values ----------------------------------------------------- */ - -/* REP[15:0]: Repetition counter value */ - -/* --- TIMx_CCR1 values ---------------------------------------------------- */ - -/* CCR1[15:0]: Capture/compare 1 value */ - -/* --- TIMx_CCR2 values ---------------------------------------------------- */ - -/* CCR2[15:0]: Capture/compare 2 value */ - -/* --- TIMx_CCR3 values ---------------------------------------------------- */ - -/* CCR3[15:0]: Capture/compare 3 value */ - -/* --- TIMx_CCR4 values ---------------------------------------------------- */ - -/* CCR4[15:0]: Capture/compare 4 value */ - -/* --- TIMx_BDTR values ---------------------------------------------------- */ - -/* MOE: Main output enable */ -#define TIM_BDTR_MOE (1 << 15) - -/* AOE: Automatic output enable */ -#define TIM_BDTR_AOE (1 << 14) - -/* BKP: Break polarity */ -#define TIM_BDTR_BKP (1 << 13) - -/* BKE: Break enable */ -#define TIM_BDTR_BKE (1 << 12) - -/* OSSR: Off-state selection of run mode */ -#define TIM_BDTR_OSSR (1 << 11) - -/* OSSI: Off-state selection of idle mode */ -#define TIM_BDTR_OSSI (1 << 10) - -/* LOCK[1:0]: Lock configuration */ -#define TIM_BDTR_LOCK_OFF (0x0 << 8) -#define TIM_BDTR_LOCK_LEVEL_1 (0x1 << 8) -#define TIM_BDTR_LOCK_LEVEL_2 (0x2 << 8) -#define TIM_BDTR_LOCK_LEVEL_3 (0x3 << 8) -#define TIM_BDTR_LOCK_MASK (0x3 << 8) - -/* DTG[7:0]: Dead-time generator set-up */ -#define TIM_BDTR_DTG_MASK 0x00FF - -/* --- TIMx_DCR values ----------------------------------------------------- */ - -/* DBL[4:0]: DMA burst length */ -#define TIM_BDTR_DBL_MASK (0x1F << 8) - -/* DBA[4:0]: DMA base address */ -#define TIM_BDTR_DBA_MASK (0x1F << 0) - -/* --- TIMx_DMAR values ---------------------------------------------------- */ - -/* DMAB[15:0]: DMA register for burst accesses */ - -/* --- TIMx convenience defines -------------------------------------------- */ - -/* Output Compare channel designators */ -enum tim_oc_id { - TIM_OC1=0, - TIM_OC1N, - TIM_OC2, - TIM_OC2N, - TIM_OC3, - TIM_OC3N, - TIM_OC4, -}; - -/* Output Compare mode designators */ -enum tim_oc_mode { - TIM_OCM_FROZEN, - TIM_OCM_ACTIVE, - TIM_OCM_INACTIVE, - TIM_OCM_TOGGLE, - TIM_OCM_FORCE_LOW, - TIM_OCM_FORCE_HIGH, - TIM_OCM_PWM1, - TIM_OCM_PWM2, -}; - -/* --- TIM functions ------------------------------------------------------- */ -void timer_reset(u32 timer_peripheral); -void timer_enable_irq(u32 timer_peripheral, u32 irq); -void timer_disable_irq(u32 timer_peripheral, u32 irq); -bool timer_get_flag(u32 timer_peripheral, u32 flag); -void timer_clear_flag(u32 timer_peripheral, u32 flag); -void timer_set_mode(u32 timer_peripheral, u8 clock_div, - u8 alignment, u8 direction); -void timer_set_clock_division(u32 timer_peripheral, u32 clock_div); -void timer_enable_preload(u32 timer_peripheral); -void timer_disable_preload(u32 timer_peripheral); -void timer_set_alignment(u32 timer_peripheral, u32 alignment); -void timer_direction_up(u32 timer_peripheral); -void timer_direction_down(u32 timer_peripheral); -void timer_one_shot_mode(u32 timer_peripheral); -void timer_continuous_mode(u32 timer_peripheral); -void timer_update_on_any(u32 timer_peripheral); -void timer_update_on_overflow(u32 timer_peripheral); -void timer_enable_update_event(u32 timer_peripheral); -void timer_disable_update_event(u32 timer_peripheral); -void timer_enable_counter(u32 timer_peripheral); -void timer_disable_counter(u32 timer_peripheral); -void timer_set_output_idle_state(u32 timer_peripheral, u32 outputs); -void timer_reset_output_idle_state(u32 timer_peripheral, u32 outputs); -void timer_set_ti1_ch123_xor(u32 timer_peripheral); -void timer_set_ti1_ch1(u32 timer_peripheral); -void timer_set_master_mode(u32 timer_peripheral, u32 mode); -void timer_set_dma_on_compare_event(u32 timer_peripheral); -void timer_set_dma_on_update_event(u32 timer_peripheral); -void timer_enable_compare_control_update_on_trigger(u32 timer_peripheral); -void timer_disable_compare_control_update_on_trigger(u32 timer_peripheral); -void timer_enable_preload_complementry_enable_bits(u32 timer_peripheral); -void timer_disable_preload_complementry_enable_bits(u32 timer_peripheral); -void timer_set_prescaler(u32 timer_peripheral, u32 value); -void timer_set_repetition_counter(u32 timer_peripheral, u32 value); -void timer_set_period(u32 timer_peripheral, u32 period); -void timer_enable_oc_clear(u32 timer_peripheral, enum tim_oc_id oc_id); -void timer_disable_oc_clear(u32 timer_peripheral, enum tim_oc_id oc_id); -void timer_set_oc_fast_mode(u32 timer_peripheral, enum tim_oc_id oc_id); -void timer_set_oc_slow_mode(u32 timer_peripheral, enum tim_oc_id oc_id); -void timer_set_oc_mode(u32 timer_peripheral, enum tim_oc_id oc_id, enum tim_oc_mode oc_mode); -void timer_enable_oc_preload(u32 timer_peripheral, enum tim_oc_id oc_id); -void timer_disable_oc_preload(u32 timer_peripheral, enum tim_oc_id oc_id); -void timer_set_oc_polarity_high(u32 timer_peripheral, enum tim_oc_id oc_id); -void timer_set_oc_polarity_low(u32 timer_peripheral, enum tim_oc_id oc_id); -void timer_enable_oc_output(u32 timer_peripheral, enum tim_oc_id oc_id); -void timer_disable_oc_output(u32 timer_peripheral, enum tim_oc_id oc_id); -void timer_set_oc_idle_state_set(u32 timer_peripheral, enum tim_oc_id oc_id); -void timer_set_oc_idle_state_unset(u32 timer_peripheral, enum tim_oc_id oc_id); -void timer_set_oc_value(u32 timer_peripheral, enum tim_oc_id oc_id, u32 value); -void timer_enable_break_main_output(u32 timer_peripheral); -void timer_disable_break_main_output(u32 timer_peripheral); -void timer_enable_break_automatic_output(u32 timer_peripheral); -void timer_disable_break_automatic_output(u32 timer_peripheral); -void timer_set_break_polarity_high(u32 timer_peripheral); -void timer_set_break_polarity_low(u32 timer_peripheral); -void timer_enable_break(u32 timer_peripheral); -void timer_disable_break(u32 timer_peripheral); -void timer_set_enabled_off_state_in_run_mode(u32 timer_peripheral); -void timer_set_disabled_off_state_in_run_mode(u32 timer_peripheral); -void timer_set_enabled_off_state_in_idle_mode(u32 timer_peripheral); -void timer_set_disabled_off_state_in_idle_mode(u32 timer_peripheral); -void timer_set_break_lock(u32 timer_peripheral, u32 lock); -void timer_set_deadtime(u32 timer_peripheral, u32 deadtime); -void timer_generate_event(u32 timer_peripheral, u32 event); -u32 timer_get_counter(u32 timer_peripheral); - -#endif diff --git a/include/libopencm3/stm32/tools.h b/include/libopencm3/stm32/tools.h deleted file mode 100644 index ac7f0bf..0000000 --- a/include/libopencm3/stm32/tools.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Piotr Esden-Tempski - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_TOOLS_H -#define LIBOPENCM3_TOOLS_H - -/* - * Register accessors / manipulators - */ - -/* Get register content. */ -#define GET_REG(REG) ((u16) *REG) - -/* Set register content. */ -#define SET_REG(REG, VAL) (*REG = (u16)VAL) - -/* Clear register bit. */ -#define CLR_REG_BIT(REG, BIT) SET_REG(REG, (~BIT)) - -/* Clear register bit masking out some bits that must not be touched. */ -#define CLR_REG_BIT_MSK(REG, MSK, BIT) \ - SET_REG(REG, (GET_REG(REG) & MSK & (~BIT))) - -/* Get masked out bit value. */ -#define GET_REG_BIT(REG, BIT) (GET_REG(REG) & BIT) - -/* - * Set/reset a bit in a masked window by using toggle mechanism. - * - * This means that we look at the bits in the bit window designated by - * the mask. If the bit in the masked window is not matching the - * bitmask BIT then we write 1 and if the bit in the masked window is - * matching the bitmask BIT we write 0. - * - * TODO: We may need a faster implementation of that one? - */ -#define TOG_SET_REG_BIT_MSK(REG, MSK, BIT) \ -do { \ - register u16 toggle_mask = GET_REG(REG) & (MSK); \ - register u16 bit_selector; \ - for (bit_selector = 1; bit_selector; bit_selector <<= 1) { \ - if ((bit_selector & (BIT)) != 0) \ - toggle_mask ^= bit_selector; \ - } \ - SET_REG(REG, toggle_mask); \ -} while(0) - -#endif diff --git a/include/libopencm3/stm32/usart.h b/include/libopencm3/stm32/usart.h deleted file mode 100644 index df6bc08..0000000 --- a/include/libopencm3/stm32/usart.h +++ /dev/null @@ -1,312 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_USART_H -#define LIBOPENCM3_USART_H - -#include -#include - -/* --- Convenience macros -------------------------------------------------- */ - -#define USART1 USART1_BASE -#define USART2 USART2_BASE -#define USART3 USART3_BASE -#define UART4 UART4_BASE -#define UART5 UART5_BASE - -/* --- USART registers ----------------------------------------------------- */ - -/* Status register (USARTx_SR) */ -#define USART_SR(usart_base) MMIO32(usart_base + 0x00) -#define USART1_SR USART_SR(USART1_BASE) -#define USART2_SR USART_SR(USART2_BASE) -#define USART3_SR USART_SR(USART3_BASE) -#define UART4_SR USART_SR(UART4_BASE) -#define UART5_SR USART_SR(UART5_BASE) - -/* Data register (USARTx_DR) */ -#define USART_DR(usart_base) MMIO32(usart_base + 0x04) -#define USART1_DR USART_DR(USART1_BASE) -#define USART2_DR USART_DR(USART2_BASE) -#define USART3_DR USART_DR(USART3_BASE) -#define UART4_DR USART_DR(UART4_BASE) -#define UART5_DR USART_DR(UART5_BASE) - -/* Baud rate register (USARTx_BRR) */ -#define USART_BRR(usart_base) MMIO32(usart_base + 0x08) -#define USART1_BRR USART_BRR(USART1_BASE) -#define USART2_BRR USART_BRR(USART2_BASE) -#define USART3_BRR USART_BRR(USART3_BASE) -#define UART4_BRR USART_BRR(UART4_BASE) -#define UART5_BRR USART_BRR(UART5_BASE) - -/* Control register 1 (USARTx_CR1) */ -#define USART_CR1(usart_base) MMIO32(usart_base + 0x0c) -#define USART1_CR1 USART_CR1(USART1_BASE) -#define USART2_CR1 USART_CR1(USART2_BASE) -#define USART3_CR1 USART_CR1(USART3_BASE) -#define UART4_CR1 USART_CR1(UART4_BASE) -#define UART5_CR1 USART_CR1(UART5_BASE) - -/* Control register 2 (USARTx_CR2) */ -#define USART_CR2(usart_base) MMIO32(usart_base + 0x10) -#define USART1_CR2 USART_CR2(USART1_BASE) -#define USART2_CR2 USART_CR2(USART2_BASE) -#define USART3_CR2 USART_CR2(USART3_BASE) -#define UART4_CR2 USART_CR2(UART4_BASE) -#define UART5_CR2 USART_CR2(UART5_BASE) - -/* Control register 3 (USARTx_CR3) */ -#define USART_CR3(usart_base) MMIO32(usart_base + 0x14) -#define USART1_CR3 USART_CR3(USART1_BASE) -#define USART2_CR3 USART_CR3(USART2_BASE) -#define USART3_CR3 USART_CR3(USART3_BASE) -#define UART4_CR3 USART_CR3(UART4_BASE) -#define UART5_CR3 USART_CR3(UART5_BASE) - -/* Guard time and prescaler register (USARTx_GTPR) */ -#define USART_GTPR(usart_base) MMIO32(usart_base + 0x18) -#define USART1_GTPR USART_GTPR(USART1_BASE) -#define USART2_GTPR USART_GTPR(USART2_BASE) -#define USART3_GTPR USART_GTPR(USART3_BASE) -#define UART4_GTPR USART_GTPR(UART4_BASE) -#define UART5_GTPR USART_GTPR(UART5_BASE) - -/* --- USART_SR values ----------------------------------------------------- */ - -/* CTS: CTS flag */ -/* Note: N/A on UART4/5 */ -#define USART_SR_CTS (1 << 9) - -/* LBD: LIN break detection flag */ -#define USART_SR_LBD (1 << 8) - -/* TXE: Transmit data buffer empty */ -#define USART_SR_TXE (1 << 7) - -/* TC: Transmission complete */ -#define USART_SR_TC (1 << 6) - -/* RXNE: Read data register not empty */ -#define USART_SR_RXNE (1 << 5) - -/* IDLE: Idle line detected */ -#define USART_SR_IDLE (1 << 4) - -/* ORE: Overrun error */ -#define USART_SR_ORE (1 << 3) - -/* NE: Noise error flag */ -#define USART_SR_NE (1 << 2) - -/* FE: Framing error */ -#define USART_SR_FE (1 << 1) - -/* PE: Parity error */ -#define USART_SR_PE (1 << 0) - -/* --- USART_DR values ----------------------------------------------------- */ - -/* USART_DR[8:0]: DR[8:0]: Data value */ -#define USART_DR_MASK 0x1FF - -/* --- USART_BRR values ---------------------------------------------------- */ - -/* DIV_Mantissa[11:0]: mantissa of USARTDIV */ -#define USART_BRR_DIV_MANTISSA_MASK (0xFFF << 4) -/* DIV_Fraction[3:0]: fraction of USARTDIV */ -#define USART_BRR_DIV_FRACTION_MASK 0xF - -/* --- USART_CR1 values ---------------------------------------------------- */ - -/* UE: USART enable */ -#define USART_CR1_UE (1 << 13) - -/* M: Word length */ -#define USART_CR1_M (1 << 12) - -/* WAKE: Wakeup method */ -#define USART_CR1_WAKE (1 << 11) - -/* PCE: Parity control enable */ -#define USART_CR1_PCE (1 << 10) - -/* PS: Parity selection */ -#define USART_CR1_PS (1 << 9) - -/* PEIE: PE interrupt enable */ -#define USART_CR1_PEIE (1 << 8) - -/* TXEIE: TXE interrupt enable */ -#define USART_CR1_TXEIE (1 << 7) - -/* TCIE: Transmission complete interrupt enable */ -#define USART_CR1_TCIE (1 << 6) - -/* RXNEIE: RXNE interrupt enable */ -#define USART_CR1_RXNEIE (1 << 5) - -/* IDLEIE: IDLE interrupt enable */ -#define USART_CR1_IDLEIE (1 << 4) - -/* TE: Transmitter enable */ -#define USART_CR1_TE (1 << 3) - -/* RE: Receiver enable */ -#define USART_CR1_RE (1 << 2) - -/* RWU: Receiver wakeup */ -#define USART_CR1_RWU (1 << 1) - -/* SBK: Send break */ -#define USART_CR1_SBK (1 << 0) - -/* --- USART_CR2 values ---------------------------------------------------- */ - -/* LINEN: LIN mode enable */ -#define USART_CR2_LINEN (1 << 14) - -/* STOP[13:12]: STOP bits */ -#define USART_CR2_STOPBITS_1 (0x00 << 12) /* 1 stop bit */ -#define USART_CR2_STOPBITS_0_5 (0x01 << 12) /* 0.5 stop bits */ -#define USART_CR2_STOPBITS_2 (0x02 << 12) /* 2 stop bits */ -#define USART_CR2_STOPBITS_1_5 (0x03 << 12) /* 1.5 stop bits */ -#define USART_CR2_STOPBITS_MASK (0x03 << 12) -#define USART_CR2_STOPBITS_SHIFT 12 - -/* CLKEN: Clock enable */ -#define USART_CR2_CLKEN (1 << 11) - -/* CPOL: Clock polarity */ -#define USART_CR2_CPOL (1 << 10) - -/* CPHA: Clock phase */ -#define USART_CR2_CPHA (1 << 9) - -/* LBCL: Last bit clock pulse */ -#define USART_CR2_LBCL (1 << 8) - -/* LBDIE: LIN break detection interrupt enable */ -#define USART_CR2_LBDIE (1 << 6) - -/* LBDL: LIN break detection length */ -#define USART_CR2_LBDL (1 << 5) - -/* ADD[3:0]: Addres of the usart node */ -#define USART_CR2_ADD_MASK 0xF - -/* --- USART_CR3 values ---------------------------------------------------- */ - -/* CTSIE: CTS interrupt enable */ -/* Note: N/A on UART4 & UART5 */ -#define USART_CR3_CTSIE (1 << 10) - -/* CTSE: CTS enable */ -/* Note: N/A on UART4 & UART5 */ -#define USART_CR3_CTSE (1 << 9) - -/* RTSE: RTS enable */ -/* Note: N/A on UART4 & UART5 */ -#define USART_CR3_RTSE (1 << 8) - -/* DMAT: DMA enable transmitter */ -/* Note: N/A on UART5 */ -#define USART_CR3_DMAT (1 << 7) - -/* DMAR: DMA enable receiver */ -/* Note: N/A on UART5 */ -#define USART_CR3_DMAR (1 << 6) - -/* SCEN: Smartcard mode enable */ -/* Note: N/A on UART4 & UART5 */ -#define USART_CR3_SCEN (1 << 5) - -/* NACK: Smartcard NACK enable */ -/* Note: N/A on UART4 & UART5 */ -#define USART_CR3_NACK (1 << 4) - -/* HDSEL: Half-duplex selection */ -#define USART_CR3_HDSEL (1 << 3) - -/* IRLP: IrDA low-power */ -#define USART_CR3_IRLP (1 << 2) - -/* IREN: IrDA mode enable */ -#define USART_CR3_IREN (1 << 1) - -/* EIE: Error interrupt enable */ -#define USART_CR3_EIE (1 << 0) - -/* --- USART_GTPR values --------------------------------------------------- */ - -/* GT[7:0]: Guard time value */ -/* Note: N/A on UART4 & UART5 */ -#define USART_GTPR_GT_MASK (0xFF << 8) - -/* PSC[7:0]: Prescaler value */ -/* Note: N/A on UART4/5 */ -#define USART_GTPR_PSC_MASK 0xFF - -/* TODO */ /* Note to Uwe: what needs to be done here? */ - -/* --- Convenience defines ------------------------------------------------- */ - -/* CR1_PCE / CR1_PS combined values */ -#define USART_PARITY_NONE 0x00 -#define USART_PARITY_ODD USART_CR1_PS -#define USART_PARITY_EVEN (USART_CR1_PS | USART_CR1_PCE) -#define USART_PARITY_MASK (USART_CR1_PS | USART_CR1_PCE) - -/* CR1_TE/CR1_RE combined values */ -#define USART_MODE_RX USART_CR1_RE -#define USART_MODE_TX USART_CR1_TE -#define USART_MODE_TX_RX (USART_CR1_RE | USART_CR1_TE) -#define USART_MODE_MASK (USART_CR1_RE | USART_CR1_TE) - -#define USART_STOPBITS_1 USART_CR2_STOPBITS_1 /* 1 stop bit */ -#define USART_STOPBITS_0_5 USART_CR2_STOPBITS_0_5 /* 0.5 stop bits */ -#define USART_STOPBITS_2 USART_CR2_STOPBITS_2 /* 2 stop bits */ -#define USART_STOPBITS_1_5 USART_CR2_STOPBITS_1_5 /* 1.5 stop bits */ - -/* CR3_CTSE/CR3_RTSE combined values */ -#define USART_FLOWCONTROL_NONE 0x00 -#define USART_FLOWCONTROL_RTS USART_CR3_RTSE -#define USART_FLOWCONTROL_CTS USART_CR3_CTSE -#define USART_FLOWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) -#define USART_FLOWCONTROL_MASK (USART_CR3_RTSE | USART_CR3_CTSE) - -/* --- Function prototypes ------------------------------------------------- */ - -void usart_set_baudrate(u32 usart, u32 baud); -void usart_set_databits(u32 usart, u32 bits); -void usart_set_stopbits(u32 usart, u32 stopbits); -void usart_set_parity(u32 usart, u32 parity); -void usart_set_mode(u32 usart, u32 mode); -void usart_set_flow_control(u32 usart, u32 flowcontrol); -void usart_enable(u32 usart); -void usart_disable(u32 usart); -void usart_send(u32 usart, u16 data); -u16 usart_recv(u32 usart); -void usart_wait_send_ready(u32 usart); -void usart_wait_recv_ready(u32 usart); -void usart_send_blocking(u32 usart, u16 data); -u16 usart_recv_blocking(u32 usart); - -#endif diff --git a/include/libopencm3/stm32/usb.h b/include/libopencm3/stm32/usb.h deleted file mode 100644 index e35075d..0000000 --- a/include/libopencm3/stm32/usb.h +++ /dev/null @@ -1,258 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Piotr Esden-Tempski - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_USB_H -#define LIBOPENCM3_USB_H - -#include -#include -#include - -/* --- USB base addresses -------------------------------------------------- */ - -#define USB_PMA_BASE 0x40006000L /* USB packet buffer memory base addr. */ - -/* --- USB general registers ----------------------------------------------- */ - -/* USB Control register */ -#define USB_CNTR_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x40)) -/* USB Interrupt status register */ -#define USB_ISTR_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x44)) -/* USB Frame number register */ -#define USB_FNR_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x48)) -/* USB Device address register */ -#define USB_DADDR_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x4C)) -/* USB Buffer table address register */ -#define USB_BTABLE_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x50)) -/* USB EP register */ -#define USB_EP_REG(EP) ((volatile u32 *)(USB_DEV_FS_BASE) + (EP)) - -/* --- USB control register masks / bits ----------------------------------- */ - -/* Interrupt mask bits, set to 1 to enable interrupt generation */ -#define USB_CNTR_CTRM 0x8000 -#define USB_CNTR_PMAOVRM 0x4000 -#define USB_CNTR_ERRM 0x2000 -#define USB_CNTR_WKUPM 0x1000 -#define USB_CNTR_SUSPM 0x0800 -#define USB_CNTR_RESETM 0x0400 -#define USB_CNTR_SOFM 0x0200 -#define USB_CNTR_ESOFM 0x0100 - -/* Request/Force bits */ -#define USB_CNTR_RESUME 0x0010 /* Resume request */ -#define USB_CNTR_FSUSP 0x0008 /* Force suspend */ -#define USB_CNTR_LP_MODE 0x0004 /* Low-power mode */ -#define USB_CNTR_PWDN 0x0002 /* Power down */ -#define USB_CNTR_FRES 0x0001 /* Force reset */ - -/* --- USB interrupt status register masks / bits -------------------------- */ - -#define USB_ISTR_CTR 0x8000 /* Correct Transfer */ -#define USB_ISTR_PMAOVR 0x4000 /* Packet Memory Area Over / Underrun */ -#define USB_ISTR_ERR 0x2000 /* Error */ -#define USB_ISTR_WKUP 0x1000 /* Wake up */ -#define USB_ISTR_SUSP 0x0800 /* Suspend mode request */ -#define USB_ISTR_RESET 0x0400 /* USB RESET request */ -#define USB_ISTR_SOF 0x0200 /* Start Of Frame */ -#define USB_ISTR_ESOF 0x0100 /* Expected Start Of Frame */ -#define USB_ISTR_DIR 0x0010 /* Direction of transaction */ -#define USB_ISTR_EP_ID 0x000F /* Endpoint Identifier */ - -/* --- USB interrupt status register manipulators -------------------------- */ - -/* Note: CTR is read only! */ -#define USB_CLR_ISTR_PMAOVR() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_PMAOVR) -#define USB_CLR_ISTR_ERR() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_ERR) -#define USB_CLR_ISTR_WKUP() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_WKUP) -#define USB_CLR_ISTR_SUSP() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_SUSP) -#define USB_CLR_ISTR_RESET() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_RESET) -#define USB_CLR_ISTR_SOF() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_SOF) -#define USB_CLR_ISTR_ESOF() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_ESOF) - -/* --- USB device addres register masks / bits ----------------------------- */ - -#define USB_DADDR_ENABLE 0x0080 -#define USB_DADDR_ADDR 0x007F - -/* --- USB device addres register manipulators ----------------------------- */ - -/* --- USB endpoint register offsets --------------------------------------- */ - -#define USB_EP0 0 -#define USB_EP1 1 -#define USB_EP2 2 -#define USB_EP3 3 -#define USB_EP4 4 -#define USB_EP5 5 -#define USB_EP6 6 -#define USB_EP7 7 - -/* --- USB endpoint register masks / bits ---------------------------------- */ - -/* Masks and toggle bits */ -#define USB_EP_RX_CTR 0x8000 /* Correct transfer RX */ -#define USB_EP_RX_DTOG 0x4000 /* Data toggle RX */ -#define USB_EP_RX_STAT 0x3000 /* Endpoint status for RX */ - -#define USB_EP_SETUP 0x0800 /* Setup transaction completed */ -#define USB_EP_TYPE 0x0600 /* Endpoint type */ -#define USB_EP_KIND 0x0100 /* Endpoint kind. - * When set and type=bulk -> double buffer - * When set and type=control -> status out - */ - -#define USB_EP_TX_CTR 0x0080 /* Correct transfer TX */ -#define USB_EP_TX_DTOG 0x0040 /* Data toggle TX */ -#define USB_EP_TX_STAT 0x0030 /* Endpoint status for TX */ - -#define USB_EP_ADDR 0x000F /* Endpoint Address */ - -/* Masking all toggle bits */ -#define USB_EP_NTOGGLE_MSK (USB_EP_RX_CTR | \ - USB_EP_SETUP | \ - USB_EP_TYPE | \ - USB_EP_KIND | \ - USB_EP_TX_CTR | \ - USB_EP_ADDR) - -/* All non toggle bits plus EP_RX toggle bits */ -#define USB_EP_RX_STAT_TOG_MSK (USB_EP_RX_STAT | USB_EP_NTOGGLE_MSK) -/* All non toggle bits plus EP_TX toggle bits */ -#define USB_EP_TX_STAT_TOG_MSK (USB_EP_TX_STAT | USB_EP_NTOGGLE_MSK) - -/* Endpoint status bits for USB_EP_RX_STAT bit field */ -#define USB_EP_RX_STAT_DISABLED 0x0000 -#define USB_EP_RX_STAT_STALL 0x1000 -#define USB_EP_RX_STAT_NAK 0x2000 -#define USB_EP_RX_STAT_VALID 0x3000 - -/* Endpoint status bits for USB_EP_TX_STAT bit field */ -#define USB_EP_TX_STAT_DISABLED 0x0000 -#define USB_EP_TX_STAT_STALL 0x0010 -#define USB_EP_TX_STAT_NAK 0x0020 -#define USB_EP_TX_STAT_VALID 0x0030 - -/* Endpoint type bits for USB_EP_TYPE bit field */ -#define USB_EP_TYPE_BULK 0x0000 -#define USB_EP_TYPE_CONTROL 0x0200 -#define USB_EP_TYPE_ISO 0x0400 -#define USB_EP_TYPE_INTERRUPT 0x0600 - -/* --- USB endpoint register manipulators ---------------------------------- */ - -/* - * Set USB endpoint tx/rx status. - * - * USB status field is changed using an awkward toggle mechanism, that - * is why we use some helper macros for that. - */ -#define USB_SET_EP_RX_STAT(EP, STAT) \ - TOG_SET_REG_BIT_MSK(USB_EP_REG(EP), USB_EP_RX_STAT_TOG_MSK, STAT) - -#define USB_SET_EP_TX_STAT(EP, STAT) \ - TOG_SET_REG_BIT_MSK(USB_EP_REG(EP), USB_EP_TX_STAT_TOG_MSK, STAT) - -/* - * Macros for clearing and setting USB endpoint register bits that do - * not use the toggle mechanism. - * - * Because the register contains some bits that use the toggle - * mechanism we need a helper macro here. Otherwise the code gets really messy. - */ -#define USB_CLR_EP_NTOGGLE_BIT(EP, BIT) \ - CLR_REG_BIT_MSK(USB_EP_REG(EP), USB_EP_NTOGGLE_MSK, BIT) - -#define USB_CLR_EP_RX_CTR(EP) \ - USB_CLR_EP_NTOGGLE_BIT(EP, USB_EP_RX_CTR) - -#define USB_CLR_EP_TX_CTR(EP) \ - USB_CLR_EP_NTOGGLE_BIT(EP, USB_EP_TX_CTR) - -#define USB_SET_EP_TYPE(EP, TYPE) \ - SET_REG(USB_EP_REG(EP), \ - (GET_REG(USB_EP_REG(EP)) & \ - (USB_EP_NTOGGLE_MSK & \ - (~USB_EP_TYPE))) | TYPE) - -#define USB_SET_EP_KIND(EP) \ - SET_REG(USB_EP_REG(EP), \ - (GET_REG(USB_EP_REG(EP)) & \ - (USB_EP_NTOGGLE_MSK & \ - (~USB_EP_KIND))) | USB_EP_KIND) - -#define USB_CLR_EP_KIND(EP) \ - SET_REG(USB_EP_REG(EP), \ - (GET_REG(USB_EP_REG(EP)) & \ - (USB_EP_NTOGGLE_MSK & (~USB_EP_KIND)))) - -#define USB_SET_EP_STAT_OUT(EP) USB_SET_EP_KIND(EP) -#define USB_CLR_EP_STAT_OUT(EP) USB_CLR_EP_KIND(EP) - -#define USB_SET_EP_ADDR(EP, ADDR) \ - SET_REG(USB_EP_REG(EP), \ - ((GET_REG(USB_EP_REG(EP)) & \ - (USB_EP_NTOGGLE_MSK & \ - (~USB_EP_ADDR))) | ADDR)) - -/* Macros for clearing DTOG bits */ -#define USB_CLR_EP_TX_DTOG(EP) \ - SET_REG(USB_EP_REG(EP), \ - GET_REG(USB_EP_REG(EP)) & \ - (USB_EP_NTOGGLE_MSK | USB_EP_TX_DTOG)) - -#define USB_CLR_EP_RX_DTOG(EP) \ - SET_REG(USB_EP_REG(EP), \ - GET_REG(USB_EP_REG(EP)) & \ - (USB_EP_NTOGGLE_MSK | USB_EP_RX_DTOG)) - -/* --- USB BTABLE registers ------------------------------------------------ */ - -#define USB_GET_BTABLE GET_REG(USB_BTABLE_REG) - -#define USB_EP_TX_ADDR(EP) \ - ((u32 *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 0) * 2)) - -#define USB_EP_TX_COUNT(EP) \ - ((u32 *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 2) * 2)) - -#define USB_EP_RX_ADDR(EP) \ - ((u32 *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 4) * 2)) - -#define USB_EP_RX_COUNT(EP) \ - ((u32 *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 6) * 2)) - -/* --- USB BTABLE manipulators --------------------------------------------- */ - -#define USB_GET_EP_TX_ADDR(EP) GET_REG(USB_EP_TX_ADDR(EP)) -#define USB_GET_EP_TX_COUNT(EP) GET_REG(USB_EP_TX_COUNT(EP)) -#define USB_GET_EP_RX_ADDR(EP) GET_REG(USB_EP_RX_ADDR(EP)) -#define USB_GET_EP_RX_COUNT(EP) GET_REG(USB_EP_RX_COUNT(EP)) -#define USB_SET_EP_TX_ADDR(EP, ADDR) SET_REG(USB_EP_TX_ADDR(EP), ADDR) -#define USB_SET_EP_TX_COUNT(EP, COUNT) SET_REG(USB_EP_TX_COUNT(EP), COUNT) -#define USB_SET_EP_RX_ADDR(EP, ADDR) SET_REG(USB_EP_RX_ADDR(EP), ADDR) -#define USB_SET_EP_RX_COUNT(EP, COUNT) SET_REG(USB_EP_RX_COUNT(EP), COUNT) - -#define USB_GET_EP_TX_BUFF(EP) \ - (USB_PMA_BASE + (u8 *)(USB_GET_EP_TX_ADDR(EP) * 2)) - -#define USB_GET_EP_RX_BUFF(EP) \ - (USB_PMA_BASE + (u8 *)(USB_GET_EP_RX_ADDR(EP) * 2)) - -#endif diff --git a/include/libopencm3/stm32/usb_desc.h b/include/libopencm3/stm32/usb_desc.h deleted file mode 100644 index da99bb0..0000000 --- a/include/libopencm3/stm32/usb_desc.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Piotr Esden-Tempski - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_USB_DESC -#define LIBOPENCM3_USB_DESC - -/* Descriptor types */ -#define USB_DT_DEVICE 0x01 -#define USB_DT_CONF 0x02 -#define USB_DT_STRING 0x03 -#define USB_DT_INTERFACE 0x04 -#define USB_DT_ENDPOINT 0x05 - -struct usb_desc_head { - u8 length; /* Descriptor size 0x012 */ - u8 type; /* Descriptor type ID */ -}; - -struct usb_device_desc { - struct usb_desc_head h; /* Size 0x12, ID 0x01 */ - u16 bcd_usb; /* USB Version */ - u8 class; /* Device class */ - u8 sub_class; /* Subclass code */ - u8 protocol; /* Protocol code */ - u8 max_psize; /* Maximum packet size -> 64bytes */ - u16 vendor; /* Vendor number */ - u16 product; /* Device number */ - u16 bcd_dev; /* Device version */ - u8 man_desc; /* Index of manufacturer string desc */ - u8 prod_desc; /* Index of product string desc */ - u8 sn_desc; /* Index of serial number string desc */ - u8 num_conf; /* Number of possible configurations */ -}; - -struct usb_conf_desc_header { - struct usb_desc_head h; /* Size 0x09, Id 0x02 */ - u16 tot_leng; /* Total length of data */ - u8 num_int; /* Number of interfaces */ - u8 conf_val; /* Configuration selector */ - u8 conf_desc; /* Index of conf string desc */ - u8 attr; /* Attribute bitmap: - * 7 : Bus powered - * 6 : Self powered - * 5 : Remote wakeup - * 4..0 : Reserved -> 0000 - */ - u8 max_power; /* Maximum power consumption in 2mA steps */ -}; - -struct usb_int_desc_header { - struct usb_desc_head h; /* Size 0x09, Id 0x04 */ - u8 iface_num; /* Interface id number */ - u8 alt_setting; /* Alternative setting selector */ - u8 num_endp; /* Endpoints used */ - u8 class; /* Interface class */ - u8 sub_class; /* Subclass code */ - u8 protocol; /* Protocol code */ - u8 iface_desc; /* Index of interface string desc */ -}; - -struct usb_ep_desc { - struct usb_desc_head h; /* Size 0x07, Id 0x05 */ - u8 ep_addr; /* Endpoint address: - 0..3 : Endpoint Number - 4..6 : Reserved -> 0 - 7 : Direction 0=out 1=in */ - u8 ep_attr; /* Endpoint attributes */ - u16 max_psize; /* Maximum packet size -> 64bytes */ - u8 interval; /* Interval for polling endpoint - data. Ignored for bulk & control - endpoints. */ -}; - -struct usb_conf_desc { - struct usb_conf_desc_header cdh; - struct usb_int_desc_header idh; - struct usb_ep_desc ep[]; -}; - -struct usb_string_desc { - struct usb_desc_head h; /* Size > 0x02, Id 0x03 */ - u16 string[]; /* String UTF16 encoded */ -}; - -#endif diff --git a/include/libopencm3/stm32/wwdg.h b/include/libopencm3/stm32/wwdg.h deleted file mode 100644 index 552d02e..0000000 --- a/include/libopencm3/stm32/wwdg.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_WWDG_H -#define LIBOPENCM3_WWDG_H - -#include -#include - -/* --- WWDG registers ------------------------------------------------------ */ - -/* Control register (WWDG_CR) */ -#define WWDG_CR MMIO32(WWDG_BASE + 0x00) - -/* Configuration register (WWDG_CFR) */ -#define WWDG_CFR MMIO32(WWDG_BASE + 0x04) - -/* Status register (WWDG_SR) */ -#define WWDG_SR MMIO32(WWDG_BASE + 0x08) - -/* --- WWDG_CR values ------------------------------------------------------ */ - -/* WDGA: Activation bit */ -#define WWDG_CR_WDGA (1 << 7) - -/* T[6:0]: 7-bit counter (MSB to LSB) */ -#define WWDG_CR_T_LSB 0 -#define WWDG_CR_T0 (1 << 0) -#define WWDG_CR_T1 (1 << 1) -#define WWDG_CR_T2 (1 << 2) -#define WWDG_CR_T3 (1 << 3) -#define WWDG_CR_T4 (1 << 4) -#define WWDG_CR_T5 (1 << 5) -#define WWDG_CR_T6 (1 << 6) - -/* --- WWDG_CFR values ----------------------------------------------------- */ - -/* EWI: Early wakeup interrupt */ -#define WWDG_CFR_EWI (1 << 9) - -/* WDGTB[8:7]: Timer base */ -#define WWDG_CFR_WDGTB_LSB 7 -#define WWDG_CFR_WDGTB_CK_DIV1 0x0 -#define WWDG_CFR_WDGTB_CK_DIV2 0x1 -#define WWDG_CFR_WDGTB_CK_DIV4 0x2 -#define WWDG_CFR_WDGTB_CK_DIV8 0x3 - -/* W[6:0]: 7-bit window value */ -#define WWDG_CFG_W_LSB 0 - -/* --- WWDG_SR values ------------------------------------------------------ */ - -/* EWIF: Early wakeup interrupt flag */ -#define WWDG_SR_EWIF (1 << 0) - -/* --- WWDG funtion prototypes---------------------------------------------- */ - -#endif diff --git a/include/libopencm3/stm32f1/adc.h b/include/libopencm3/stm32f1/adc.h new file mode 100644 index 0000000..6e35d59 --- /dev/null +++ b/include/libopencm3/stm32f1/adc.h @@ -0,0 +1,418 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Edward Cheeseman + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_ADC_H +#define LIBOPENCM3_ADC_H + +#include +#include + +/* --- Convenience macros -------------------------------------------------- */ + +/* ADC port base addresses (for convenience) */ +#define ADC1 ADC1_BASE +#define ADC2 ADC2_BASE +#define ADC3 ADC3_BASE + +/* --- ADC registers ------------------------------------------------------- */ + +/* ADC status register (ADC_SR) */ +#define ADC_SR(block) MMIO32(block + 0x00) +#define ADC1_SR ADC_SR(ADC1) +#define ADC2_SR ADC_SR(ADC2) +#define ADC3_SR ADC_SR(ADC3) + +/* ADC control register 1 (ADC_CR1) */ +#define ADC_CR1(block) MMIO32(block + 0x04) +#define ADC1_CR1 ADC_CR1(ADC1) +#define ADC2_CR1 ADC_CR1(ADC2) +#define ADC3_CR1 ADC_CR1(ADC3) + +/* ADC control register 2 (ADC_CR2) */ +#define ADC_CR2(block) MMIO32(block + 0x08) +#define ADC1_CR2 ADC_CR2(ADC1) +#define ADC2_CR2 ADC_CR2(ADC2) +#define ADC3_CR2 ADC_CR2(ADC3) + +/* ADC sample time register 1 (ADC_SMPR1) */ +#define ADC_SMPR1(block) MMIO32(block + 0x0c) +#define ADC1_SMPR1 ADC_SMPR1(ADC1) +#define ADC2_SMPR1 ADC_SMPR1(ADC2) +#define ADC3_SMPR1 ADC_SMPR1(ADC3) + +/* ADC sample time register 2 (ADC_SMPR2) */ +#define ADC_SMPR2(block) MMIO32(block + 0x10) +#define ADC1_SMPR2 ADC_SMPR2(ADC1) +#define ADC2_SMPR2 ADC_SMPR2(ADC2) +#define ADC3_SMPR2 ADC_SMPR2(ADC3) + +/* ADC injected channel data offset register x (ADC_JOFRx) (x=1..4) */ +#define ADC_JOFR1(block) MMIO32(block + 0x14) +#define ADC_JOFR2(block) MMIO32(block + 0x18) +#define ADC_JOFR3(block) MMIO32(block + 0x1c) +#define ADC_JOFR4(block) MMIO32(block + 0x20) +#define ADC1_JOFR1 ADC_JOFR1(ADC1) +#define ADC2_JOFR1 ADC_JOFR1(ADC2) +#define ADC3_JOFR1 ADC_JOFR1(ADC3) +#define ADC1_JOFR2 ADC_JOFR2(ADC1) +#define ADC2_JOFR2 ADC_JOFR2(ADC2) +#define ADC3_JOFR2 ADC_JOFR2(ADC3) +#define ADC1_JOFR3 ADC_JOFR3(ADC1) +#define ADC2_JOFR3 ADC_JOFR3(ADC2) +#define ADC3_JOFR3 ADC_JOFR3(ADC3) +#define ADC1_JOFR4 ADC_JOFR4(ADC1) +#define ADC2_JOFR4 ADC_JOFR4(ADC2) +#define ADC3_JOFR4 ADC_JOFR4(ADC3) + +/* ADC watchdog high threshold register (ADC_HTR) */ +#define ADC_HTR(block) MMIO32(block + 0x24) +#define ADC1_HTR ADC_HTR(ADC1) +#define ADC2_HTR ADC_HTR(ADC2) +#define ADC3_HTR ADC_HTR(ADC3) + +/* ADC watchdog low threshold register (ADC_LTR) */ +#define ADC_LTR(block) MMIO32(block + 0x28) +#define ADC1_LTR ADC_LTR(ADC1_BASE) +#define ADC2_LTR ADC_LTR(ADC2_BASE) +#define ADC3_LTR ADC_LTR(ADC3_BASE) + +/* ADC regular sequence register 1 (ADC_SQR1) */ +#define ADC_SQR1(block) MMIO32(block + 0x2c) +#define ADC1_SQR1 ADC_SQR1(ADC1) +#define ADC2_SQR1 ADC_SQR1(ADC2) +#define ADC3_SQR1 ADC_SQR1(ADC3) + +/* ADC regular sequence register 2 (ADC_SQR2) */ +#define ADC_SQR2(block) MMIO32(block + 0x30) +#define ADC1_SQR2 ADC_SQR2(ADC1) +#define ADC2_SQR2 ADC_SQR2(ADC2) +#define ADC3_SQR2 ADC_SQR2(ADC3) + +/* ADC regular sequence register 3 (ADC_SQR3) */ +#define ADC_SQR3(block) MMIO32(block + 0x34) +#define ADC1_SQR3 ADC_SQR3(ADC1) +#define ADC2_SQR3 ADC_SQR3(ADC2) +#define ADC3_SQR3 ADC_SQR3(ADC3) + +/* ADC injected sequence register (ADC_JSQR) */ +#define ADC_JSQR(block) MMIO32(block + 0x38) +#define ADC1_JSQR ADC_JSQR(ADC1_BASE) +#define ADC2_JSQR ADC_JSQR(ADC2_BASE) +#define ADC3_JSQR ADC_JSQR(ADC3_BASE) + +/* ADC injected data register x (ADC_JDRx) (x=1..4) */ +#define ADC_JDR1(block) MMIO32(block + 0x3c) +#define ADC_JDR2(block) MMIO32(block + 0x40) +#define ADC_JDR3(block) MMIO32(block + 0x44) +#define ADC_JDR4(block) MMIO32(block + 0x48) +#define ADC1_JDR1 ADC_JDR1(ADC1) +#define ADC2_JDR1 ADC_JDR1(ADC2) +#define ADC3_JDR1 ADC_JDR1(ADC3) +#define ADC1_JDR2 ADC_JDR2(ADC1) +#define ADC2_JDR2 ADC_JDR2(ADC2) +#define ADC3_JDR2 ADC_JDR2(ADC3) +#define ADC1_JDR3 ADC_JDR3(ADC1) +#define ADC2_JDR3 ADC_JDR3(ADC2) +#define ADC3_JDR3 ADC_JDR3(ADC3) +#define ADC1_JDR4 ADC_JDR4(ADC1) +#define ADC2_JDR4 ADC_JDR4(ADC2) +#define ADC3_JDR4 ADC_JDR4(ADC3) + +/* ADC regular data register (ADC_DR) */ +#define ADC_DR(block) MMIO32(block + 0x4c) +#define ADC1_DR ADC_DR(ADC1) +#define ADC2_DR ADC_DR(ADC2) +#define ADC3_DR ADC_DR(ADC3) + +/* --- ADC_SR values ------------------------------------------------------- */ + +#define ADC_SR_STRT (1 << 4) +#define ADC_SR_JSTRT (1 << 3) +#define ADC_SR_JEOC (1 << 2) +#define ADC_SR_EOC (1 << 1) +#define ADC_SR_AWD (1 << 0) + +/* --- ADC_CR1 values ------------------------------------------------------ */ + +#define ADC_CR1_AWDEN (1 << 23) +#define ADC_CR1_JAWDEN (1 << 22) +#define ADC_CR1_DUALMOD_LSB 16 +#define ADC_CR1_DUALMOD_MSK (0xf << ADC_DUALMOD_LSB) /* ADC1 only */ +#define ADC_CR1_DISCNUM_LSB 13 +#define ADC_CR1_DISCNUM_MSK (0x7 << ADC_DISCNUM_LSB) +#define ADC_CR1_JDISCEN (1 << 12) +#define ADC_CR1_DISCEN (1 << 11) +#define ADC_CR1_JAUTO (1 << 10) +#define ADC_CR1_AWDSGL (1 << 9) +#define ADC_CR1_SCAN (1 << 8) +#define ADC_CR1_JEOCIE (1 << 7) +#define ADC_CR1_AWDIE (1 << 6) +#define ADC_CR1_EOCIE (1 << 5) +#define ADC_CR1_AWDCH_LSB 0 +#define ADC_CR1_AWDCH_MSK (0x1f << ADC_AWDCH_LSB) + +/* --- ADC_CR2 values ------------------------------------------------------ */ + +#define ADC_CR2_TSVREFE (1 << 23) /* ADC1 only! */ +#define ADC_CR2_SWSTART (1 << 22) +#define ADC_CR2_JSWSTART (1 << 21) +#define ADC_CR2_EXTTRIG (1 << 20) +#define ADC_CR2_EXTSEL_LSB 17 +#define ADC_CR2_EXTSEL_MSK (0x7 << ADC_EXTSEL_LSB) +/* The following are only valid for ADC1 and ADC2. */ +#define ADC_CR2_EXTSEL_TIM1_CC1 0x0 +#define ADC_CR2_EXTSEL_TIM1_CC2 0x1 +#define ADC_CR2_EXTSEL_TIM1_CC3 0x2 +#define ADC_CR2_EXTSEL_TIM2_CC2 0x3 +#define ADC_CR2_EXTSEL_TIM3_TRGO 0x4 +#define ADC_CR2_EXTSEL_TIM4_CC4 0x5 +#define ADC_CR2_EXTSEL_EXTI11 0x6 +#define ADC_CR2_EXTSEL_SWSTART 0x7 + +/* The following are only valid for ADC3 */ +#define ADC_CR2_EXTSEL_TIM3_CC1 0x0 +#define ADC_CR2_EXTSEL_TIM2_CC3 0x1 +#define ADC_CR2_EXTSEL_TIM8_CC1 0x3 +#define ADC_CR2_EXTSEL_TIM8_TRGO 0x4 +#define ADC_CR2_EXTSEL_TIM5_CC1 0x5 +#define ADC_CR2_EXTSEL_TIM5_CC3 0x6 + +/* Bit 16: reserved, must be kept cleared */ +#define ADC_CR2_JEXTTRIG (1 << 15) +#define ADC_CR2_JEXTSEL_LSB 12 +#define ADC_CR2_JEXTSEL_MSK (0x7 << ADC_JEXTSEL_LSB) +/* The following are only valid for ADC1 and ADC2. */ +#define ADC_CR2_JEXTSEL_TIM1_TRGO 0x0 +#define ADC_CR2_JEXTSEL_TIM1_CC4 0x1 +#define ADC_CR2_JEXTSEL_TIM2_TRGO 0x2 +#define ADC_CR2_JEXTSEL_TIM2_CC1 0x3 +#define ADC_CR2_JEXTSEL_TIM3_CC4 0x4 +#define ADC_CR2_JEXTSEL_TIM4_TRGO 0x5 +#define ADC_CR2_JEXTSEL_EXTI15 0x6 +#define ADC_CR2_JEXTSEL_JSWSTART 0x7 + +/* The following are the different meanings for ADC3 only. */ +#define ADC_CR2_JEXTSEL_TIM4_CC3 0x2 +#define ADC_CR2_JEXTSEL_TIM8_CC2 0x3 +#define ADC_CR2_JEXTSEL_TIM8_CC4 0x4 +#define ADC_CR2_JEXTSEL_TIM5_TRGO 0x5 +#define ADC_CR2_JEXTSEL_TIM5_CC4 0x6 + +#define ADC_CR2_ALIGN (1 << 11) +#define ADC_CR2_DMA (1 << 8) /* ADC 1 & 3 only! */ +/* Bits [7:4] have to be kept 0. */ +#define ADC_CR2_RSTCAL (1 << 3) +#define ADC_CR2_CAL (1 << 2) +#define ADC_CR2_CONT (1 << 1) +#define ADC_CR2_ADON (1 << 0) /* Must be separately written. */ + +/* --- ADC_SMPR1 values ---------------------------------------------------- */ + +#define ADC_SMPR1_SMP17_LSB 21 +#define ADC_SMPR1_SMP16_LSB 18 +#define ADC_SMPR1_SMP15_LSB 15 +#define ADC_SMPR1_SMP14_LSB 12 +#define ADC_SMPR1_SMP13_LSB 9 +#define ADC_SMPR1_SMP12_LSB 6 +#define ADC_SMPR1_SMP11_LSB 3 +#define ADC_SMPR1_SMP10_LSB 0 +#define ADC_SMPR1_SMP17_MSK (0x7 << ADC_SMP17_LSB) +#define ADC_SMPR1_SMP16_MSK (0x7 << ADC_SMP16_LSB) +#define ADC_SMPR1_SMP15_MSK (0x7 << ADC_SMP15_LSB) +#define ADC_SMPR1_SMP14_MSK (0x7 << ADC_SMP14_LSB) +#define ADC_SMPR1_SMP13_MSK (0x7 << ADC_SMP13_LSB) +#define ADC_SMPR1_SMP12_MSK (0x7 << ADC_SMP12_LSB) +#define ADC_SMPR1_SMP11_MSK (0x7 << ADC_SMP11_LSB) +#define ADC_SMPR1_SMP10_MSK (0x7 << ADC_SMP10_LSB) +#define ADC_SMPR1_SMP_1DOT5CYC 0x0 +#define ADC_SMPR1_SMP_7DOT5CYC 0x1 +#define ADC_SMPR1_SMP_13DOT5CYC 0x2 +#define ADC_SMPR1_SMP_28DOT5CYC 0x3 +#define ADC_SMPR1_SMP_41DOT5CYC 0x4 +#define ADC_SMPR1_SMP_55DOT5CYC 0x5 +#define ADC_SMPR1_SMP_71DOT5CYC 0x6 +#define ADC_SMPR1_SMP_239DOT5CYC 0x7 + +/* --- ADC_SMPR2 values ---------------------------------------------------- */ + +#define ADC_SMPR2_SMP9_LSB 27 +#define ADC_SMPR2_SMP8_LSB 24 +#define ADC_SMPR2_SMP7_LSB 21 +#define ADC_SMPR2_SMP6_LSB 18 +#define ADC_SMPR2_SMP5_LSB 15 +#define ADC_SMPR2_SMP4_LSB 12 +#define ADC_SMPR2_SMP3_LSB 9 +#define ADC_SMPR2_SMP2_LSB 6 +#define ADC_SMPR2_SMP1_LSB 3 +#define ADC_SMPR2_SMP0_LSB 0 +#define ADC_SMPR2_SMP9_MSK (0x7 << ADC_SMP9_LSB) +#define ADC_SMPR2_SMP8_MSK (0x7 << ADC_SMP8_LSB) +#define ADC_SMPR2_SMP7_MSK (0x7 << ADC_SMP7_LSB) +#define ADC_SMPR2_SMP6_MSK (0x7 << ADC_SMP6_LSB) +#define ADC_SMPR2_SMP5_MSK (0x7 << ADC_SMP5_LSB) +#define ADC_SMPR2_SMP4_MSK (0x7 << ADC_SMP4_LSB) +#define ADC_SMPR2_SMP3_MSK (0x7 << ADC_SMP3_LSB) +#define ADC_SMPR2_SMP2_MSK (0x7 << ADC_SMP2_LSB) +#define ADC_SMPR2_SMP1_MSK (0x7 << ADC_SMP1_LSB) +#define ADC_SMPR2_SMP0_MSK (0x7 << ADC_SMP0_LSB) +#define ADC_SMPR2_SMP_1DOT5CYC 0x0 +#define ADC_SMPR2_SMP_7DOT5CYC 0x1 +#define ADC_SMPR2_SMP_13DOT5CYC 0x2 +#define ADC_SMPR2_SMP_28DOT5CYC 0x3 +#define ADC_SMPR2_SMP_41DOT5CYC 0x4 +#define ADC_SMPR2_SMP_55DOT5CYC 0x5 +#define ADC_SMPR2_SMP_71DOT5CYC 0x6 +#define ADC_SMPR2_SMP_239DOT5CYC 0x7 + +/* --- ADC_SMPRx generic values -------------------------------------------- */ + +#define ADC_SMPR_SMP_1DOT5CYC 0x0 +#define ADC_SMPR_SMP_7DOT5CYC 0x1 +#define ADC_SMPR_SMP_13DOT5CYC 0x2 +#define ADC_SMPR_SMP_28DOT5CYC 0x3 +#define ADC_SMPR_SMP_41DOT5CYC 0x4 +#define ADC_SMPR_SMP_55DOT5CYC 0x5 +#define ADC_SMPR_SMP_71DOT5CYC 0x6 +#define ADC_SMPR_SMP_239DOT5CYC 0x7 + +/* --- ADC_JOFRx, ADC_HTR, ADC_LTR values ---------------------------------- */ + +#define ADC_JOFFSET_LSB 0 +#define ADC_JOFFSET_MSK (0x7ff << 0) +#define ADC_HT_LSB 0 +#define ADC_HT_MSK (0x7ff << 0) +#define ADC_LT_LSB 0 +#define ADC_LT_MSK (0x7ff << 0) + +/* --- ADC_SQR1 values ----------------------------------------------------- */ + +#define ADC_SQR1_L_LSB 20 +#define ADC_SQR1_SQ16_LSB 15 +#define ADC_SQR1_SQ15_LSB 10 +#define ADC_SQR1_SQ14_LSB 5 +#define ADC_SQR1_SQ13_LSB 0 +#define ADC_SQR1_L_MSK (0xf << ADC_L_LSB) +#define ADC_SQR1_SQ16_MSK (0x1f << ADC_SQ16_LSB) +#define ADC_SQR1_SQ15_MSK (0x1f << ADC_SQ15_LSB) +#define ADC_SQR1_SQ14_MSK (0x1f << ADC_SQ14_LSB) +#define ADC_SQR1_SQ13_MSK (0x1f << ADC_SQ13_LSB) + +/* --- ADC_SQR2 values ----------------------------------------------------- */ + +#define ADC_SQR2_SQ12_LSB 25 +#define ADC_SQR2_SQ11_LSB 20 +#define ADC_SQR2_SQ10_LSB 15 +#define ADC_SQR2_SQ9_LSB 10 +#define ADC_SQR2_SQ8_LSB 5 +#define ADC_SQR2_SQ7_LSB 0 +#define ADC_SQR2_SQ12_MSK (0x1f << ADC_SQ12_LSB) +#define ADC_SQR2_SQ11_MSK (0x1f << ADC_SQ11_LSB) +#define ADC_SQR2_SQ10_MSK (0x1f << ADC_SQ10_LSB) +#define ADC_SQR2_SQ9_MSK (0x1f << ADC_SQ9_LSB) +#define ADC_SQR2_SQ8_MSK (0x1f << ADC_SQ8_LSB) +#define ADC_SQR2_SQ7_MSK (0x1f << ADC_SQ7_LSB) + +/* --- ADC_SQR3 values ----------------------------------------------------- */ + +#define ADC_SQR3_SQ6_LSB 25 +#define ADC_SQR3_SQ5_LSB 20 +#define ADC_SQR3_SQ4_LSB 15 +#define ADC_SQR3_SQ3_LSB 10 +#define ADC_SQR3_SQ2_LSB 5 +#define ADC_SQR3_SQ1_LSB 0 +#define ADC_SQR3_SQ6_MSK (0x1f << ADC_SQ6_LSB) +#define ADC_SQR3_SQ5_MSK (0x1f << ADC_SQ5_LSB) +#define ADC_SQR3_SQ4_MSK (0x1f << ADC_SQ4_LSB) +#define ADC_SQR3_SQ3_MSK (0x1f << ADC_SQ3_LSB) +#define ADC_SQR3_SQ2_MSK (0x1f << ADC_SQ2_LSB) +#define ADC_SQR3_SQ1_MSK (0x1f << ADC_SQ1_LSB) + +/* --- ADC_JSQR values ----------------------------------------------------- */ + +#define ADC_JSQR_JL_LSB 20 +#define ADC_JSQR_JSQ4_LSB 15 +#define ADC_JSQR_JSQ3_LSB 10 +#define ADC_JSQR_JSQ2_LSB 5 +#define ADC_JSQR_JSQ1_LSB 0 +#define ADC_JSQR_JL_MSK (0x2 << ADC_JL_LSB) +#define ADC_JSQR_JSQ4_MSK (0x1f << ADC_JSQ4_LSB) +#define ADC_JSQR_JSQ3_MSK (0x1f << ADC_JSQ3_LSB) +#define ADC_JSQR_JSQ2_MSK (0x1f << ADC_JSQ2_LSB) +#define ADC_JSQR_JSQ1_MSK (0x1f << ADC_JSQ1_LSB) + +/* --- ADC_JDRx, ADC_DR values --------------------------------------------- */ + +#define ADC_JDATA_LSB 0 +#define ADC_DATA_LSB 0 +#define ADC_ADC2DATA_LSB 16 /* ADC1 only (dual mode) */ +#define ADC_JDATA_MSK (0xffff << ADC_JDATA_LSB) +#define ADC_DATA_MSK (0xffff << ADC_DA) +#define ADC_ADC2DATA_MSK (0xffff << ADC_ADC2DATA_LSB) + /* ADC1 only (dual mode) */ + +/* --- Function prototypes ------------------------------------------------- */ + + +/* TODO */ +void adc_enable_analog_watchdog_regular(u32 adc); +void adc_disable_analog_watchdog_regular(u32 adc); +void adc_enable_analog_watchdog_injected(u32 adc); +void adc_disable_analog_watchdog_injected(u32 adc); +void adc_enable_discontinous_mode_regular(u32 adc); +void adc_disable_discontinous_mode_regular(u32 adc); +void adc_enable_discontinous_mode_injected(u32 adc); +void adc_disable_discontinous_mode_injected(u32 adc); +void adc_enable_automatic_injected_group_conversion(u32 adc); +void adc_disable_automatic_injected_group_conversion(u32 adc); +void adc_enable_analog_watchdog_on_all_channels(u32 adc); +void adc_enable_analog_watchdog_on_selected_channel(u32 adc, u8 channel); +void adc_enable_scan_mode(u32 adc); +void adc_disable_scan_mode(u32 adc); +void adc_enable_jeoc_interrupt(u32 adc); +void adc_disable_jeoc_interrupt(u32 adc); +void adc_enable_awd_interrupt(u32 adc); +void adc_disable_awd_interrupt(u32 adc); +void adc_enable_eoc_interrupt(u32 adc); +void adc_disable_eoc_interrupt(u32 adc); +void adc_enable_temperature_sensor(u32 adc); +void adc_disable_temperature_sensor(u32 adc); +void adc_start_conversion_regular(u32 adc); +void adc_start_conversion_injected(u32 adc); +void adc_enable_external_trigger_regular(u32 adc, u8 trigger); +void adc_disable_external_trigger_regular(u32 adc); +void adc_enable_external_trigger_injected(u32 adc, u8 trigger); +void adc_disable_external_trigger_injected(u32 adc); +void adc_set_left_aligned(u32 adc); +void adc_set_right_aligned(u32 adc); +void adc_enable_dma(u32 adc); +void adc_disable_dma(u32 adc); +void adc_reset_calibration(u32 adc); +void adc_calibration(u32 adc); +void adc_set_continous_conversion_mode(u32 adc); +void adc_set_single_conversion_mode(u32 adc); +void adc_on(u32 adc); +void adc_off(u32 adc); +void adc_set_conversion_time(u32 adc, u8 channel, u8 time); +void adc_set_conversion_time_on_all_channels(u32 adc, u8 time); +void adc_set_watchdog_high_threshold(u32 adc, u16 threshold); +void adc_set_watchdog_low_threshold(u32 adc, u16 threshold); +void adc_set_regular_sequence(u32 adc, u8 length, u8 channel[]); +void adc_set_injected_sequence(u32 adc, u8 length, u8 channel[]); + +#endif diff --git a/include/libopencm3/stm32f1/bkp.h b/include/libopencm3/stm32f1/bkp.h new file mode 100644 index 0000000..d700f9b --- /dev/null +++ b/include/libopencm3/stm32f1/bkp.h @@ -0,0 +1,208 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_BKP_H +#define LIBOPENCM3_BKP_H + +#include +#include + +/* --- BKP registers ------------------------------------------------------- */ + +/* Backup data register 1 (BKP_DR1) */ +#define BKP_DR1 MMIO32(BACKUP_REGS_BASE + 0x04) + +/* Backup data register 2 (BKP_DR2) */ +#define BKP_DR2 MMIO32(BACKUP_REGS_BASE + 0x08) + +/* Backup data register 3 (BKP_DR3) */ +#define BKP_DR3 MMIO32(BACKUP_REGS_BASE + 0x0C) + +/* Backup data register 4 (BKP_DR4) */ +#define BKP_DR4 MMIO32(BACKUP_REGS_BASE + 0x10) + +/* Backup data register 5 (BKP_DR5) */ +#define BKP_DR5 MMIO32(BACKUP_REGS_BASE + 0x14) + +/* Backup data register 6 (BKP_DR6) */ +#define BKP_DR6 MMIO32(BACKUP_REGS_BASE + 0x18) + +/* Backup data register 7 (BKP_DR7) */ +#define BKP_DR7 MMIO32(BACKUP_REGS_BASE + 0x1C) + +/* Backup data register 8 (BKP_DR8) */ +#define BKP_DR8 MMIO32(BACKUP_REGS_BASE + 0x20) + +/* Backup data register 9 (BKP_DR9) */ +#define BKP_DR9 MMIO32(BACKUP_REGS_BASE + 0x24) + +/* Backup data register 10 (BKP_DR10) */ +#define BKP_DR10 MMIO32(BACKUP_REGS_BASE + 0x28) + +/* RTC clock calibration register (BKP_RTCCR) */ +#define BKP_RTCCR MMIO32(BACKUP_REGS_BASE + 0x2C) + +/* Backup control register (BKP_CR) */ +#define BKP_CR MMIO32(BACKUP_REGS_BASE + 0x30) + +/* Backup control/status register (BKP_CSR) */ +#define BKP_CSR MMIO32(BACKUP_REGS_BASE + 0x34) + +/* Backup data register 11 (BKP_DR11) */ +#define BKP_DR11 MMIO32(BACKUP_REGS_BASE + 0x40) + +/* Backup data register 12 (BKP_DR12) */ +#define BKP_DR12 MMIO32(BACKUP_REGS_BASE + 0x44) + +/* Backup data register 13 (BKP_DR13) */ +#define BKP_DR13 MMIO32(BACKUP_REGS_BASE + 0x48) + +/* Backup data register 14 (BKP_DR14) */ +#define BKP_DR14 MMIO32(BACKUP_REGS_BASE + 0x4C) + +/* Backup data register 15 (BKP_DR15) */ +#define BKP_DR15 MMIO32(BACKUP_REGS_BASE + 0x50) + +/* Backup data register 16 (BKP_DR16) */ +#define BKP_DR16 MMIO32(BACKUP_REGS_BASE + 0x54) + +/* Backup data register 17 (BKP_DR17) */ +#define BKP_DR17 MMIO32(BACKUP_REGS_BASE + 0x58) + +/* Backup data register 18 (BKP_DR18) */ +#define BKP_DR18 MMIO32(BACKUP_REGS_BASE + 0x5C) + +/* Backup data register 19 (BKP_DR19) */ +#define BKP_DR19 MMIO32(BACKUP_REGS_BASE + 0x60) + +/* Backup data register 20 (BKP_DR20) */ +#define BKP_DR20 MMIO32(BACKUP_REGS_BASE + 0x64) + +/* Backup data register 21 (BKP_DR21) */ +#define BKP_DR21 MMIO32(BACKUP_REGS_BASE + 0x68) + +/* Backup data register 22 (BKP_DR22) */ +#define BKP_DR22 MMIO32(BACKUP_REGS_BASE + 0x6C) + +/* Backup data register 23 (BKP_DR23) */ +#define BKP_DR23 MMIO32(BACKUP_REGS_BASE + 0x70) + +/* Backup data register 24 (BKP_DR24) */ +#define BKP_DR24 MMIO32(BACKUP_REGS_BASE + 0x74) + +/* Backup data register 25 (BKP_DR25) */ +#define BKP_DR25 MMIO32(BACKUP_REGS_BASE + 0x78) + +/* Backup data register 26 (BKP_DR26) */ +#define BKP_DR26 MMIO32(BACKUP_REGS_BASE + 0x7C) + +/* Backup data register 27 (BKP_DR27) */ +#define BKP_DR27 MMIO32(BACKUP_REGS_BASE + 0x80) + +/* Backup data register 28 (BKP_DR28) */ +#define BKP_DR28 MMIO32(BACKUP_REGS_BASE + 0x84) + +/* Backup data register 29 (BKP_DR29) */ +#define BKP_DR29 MMIO32(BACKUP_REGS_BASE + 0x88) + +/* Backup data register 30 (BKP_DR30) */ +#define BKP_DR30 MMIO32(BACKUP_REGS_BASE + 0x8C) + +/* Backup data register 31 (BKP_DR31) */ +#define BKP_DR31 MMIO32(BACKUP_REGS_BASE + 0x90) + +/* Backup data register 32 (BKP_DR32) */ +#define BKP_DR32 MMIO32(BACKUP_REGS_BASE + 0x94) + +/* Backup data register 33 (BKP_DR33) */ +#define BKP_DR33 MMIO32(BACKUP_REGS_BASE + 0x98) + +/* Backup data register 34 (BKP_DR34) */ +#define BKP_DR34 MMIO32(BACKUP_REGS_BASE + 0x9C) + +/* Backup data register 35 (BKP_DR35) */ +#define BKP_DR35 MMIO32(BACKUP_REGS_BASE + 0xA0) + +/* Backup data register 36 (BKP_DR36) */ +#define BKP_DR36 MMIO32(BACKUP_REGS_BASE + 0xA4) + +/* Backup data register 37 (BKP_DR37) */ +#define BKP_DR37 MMIO32(BACKUP_REGS_BASE + 0xA8) + +/* Backup data register 38 (BKP_DR38) */ +#define BKP_DR38 MMIO32(BACKUP_REGS_BASE + 0xAC) + +/* Backup data register 39 (BKP_DR39) */ +#define BKP_DR39 MMIO32(BACKUP_REGS_BASE + 0xB0) + +/* Backup data register 40 (BKP_DR40) */ +#define BKP_DR40 MMIO32(BACKUP_REGS_BASE + 0xB4) + +/* Backup data register 41 (BKP_DR41) */ +#define BKP_DR41 MMIO32(BACKUP_REGS_BASE + 0xB8) + +/* Backup data register 42 (BKP_DR42) */ +#define BKP_DR42 MMIO32(BACKUP_REGS_BASE + 0xBC) + +/* --- BKP_RTCCR values ---------------------------------------------------- */ + +/* ASOS: Alarm or second output selection */ +#define BKP_RTCCR_ASOS (1 << 9) + +/* ASOE: Alarm or second output enable */ +#define BKP_RTCCR_ASOE (1 << 8) + +/* CCO: Calibration clock output */ +#define BKP_RTCCR_CCO (1 << 7) + +/* CAL[6:0]: Calibration value */ +#define BKP_RTCCR_CAL_LSB 0 + +/* --- BKP_CR values ------------------------------------------------------- */ + +/* TPAL: TAMPER pin active level */ +#define BKP_CR_TAL (1 << 1) + +/* TPE: TAMPER pin enable */ +#define BKP_CR_TPE (1 << 0) + +/* --- BKP_CSR values ------------------------------------------------------ */ + +/* TIF: Tamper interrupt flag */ +#define BKP_CSR_TIF (1 << 9) + +/* TEF: Tamper event flag */ +#define BKP_CSR_TEF (1 << 8) + +/* TPIE: TAMPER pin interrupt enable */ +#define BKP_CSR_TPIE (1 << 2) + +/* CTI: Clear tamper interrupt */ +#define BKP_CSR_CTI (1 << 1) + +/* CTE: Clear tamper event */ +#define BKP_CSR_CTE (1 << 0) + +/* --- BKP_DRx values ------------------------------------------------------ */ + +/* Bits[15:0]: Backup data */ + +/* --- BKP function prototypes --------------------------------------------- */ + +#endif diff --git a/include/libopencm3/stm32f1/can.h b/include/libopencm3/stm32f1/can.h new file mode 100644 index 0000000..1aa95a1 --- /dev/null +++ b/include/libopencm3/stm32f1/can.h @@ -0,0 +1,642 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Piotr Esden-Tempski + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_CAN_H +#define LIBOPENCM3_CAN_H + +#include +#include + +/* --- Convenience macros -------------------------------------------------- */ + +/* CAN register base adresses (for convenience) */ +#define CAN1 BX_CAN1_BASE +#define CAN2 BX_CAN2_BASE + +/* --- CAN registers ------------------------------------------------------- */ + +/* CAN master control register (CAN_MCR) */ +#define CAN_MCR(can_base) MMIO32(can_base + 0x000) +/* CAN master status register (CAN_MSR) */ +#define CAN_MSR(can_base) MMIO32(can_base + 0x004) +/* CAN transmit status register (CAN_TSR) */ +#define CAN_TSR(can_base) MMIO32(can_base + 0x008) + +/* CAN receive FIFO 0 register (CAN_RF0R) */ +#define CAN_RF0R(can_base) MMIO32(can_base + 0x00C) +/* CAN receive FIFO 1 register (CAN_RF1R) */ +#define CAN_RF1R(can_base) MMIO32(can_base + 0x010) + +/* CAN interrupt enable register (CAN_IER) */ +#define CAN_IER(can_base) MMIO32(can_base + 0x014) +/* CAN error status register (CAN_ESR) */ +#define CAN_ESR(can_base) MMIO32(can_base + 0x018) +/* CAN bit timing register (CAN_BTR) */ +#define CAN_BTR(can_base) MMIO32(can_base + 0x01C) + +/* Registers in the offset range 0x020 to 0x17F are reserved. */ + +/* --- CAN mailbox registers ----------------------------------------------- */ + +/* CAN mailbox / FIFO register offsets */ +#define CAN_MBOX0 0x180 +#define CAN_MBOX1 0x190 +#define CAN_MBOX2 0x1A0 +#define CAN_FIFO0 0x1B0 +#define CAN_FIFO1 0x1C0 + +/* CAN TX mailbox identifier register (CAN_TIxR) */ +#define CAN_TIxR(can_base, mbox) MMIO32(can_base + mbox + 0x0) +#define CAN_TI0R(can_base) CAN_TIxR(can_base, CAN_MBOX0) +#define CAN_TI1R(can_base) CAN_TIxR(can_base, CAN_MBOX1) +#define CAN_TI2R(can_base) CAN_TIxR(can_base, CAN_MBOX2) + +/* CAN mailbox data length control and time stamp register (CAN_TDTxR) */ +#define CAN_TDTxR(can_base, mbox) MMIO32(can_base + mbox + 0x4) +#define CAN_TDT0R(can_base) CAN_TDTxR(can_base, CAN_MBOX0) +#define CAN_TDT1R(can_base) CAN_TDTxR(can_base, CAN_MBOX1) +#define CAN_TDT2R(can_base) CAN_TDTxR(can_base, CAN_MBOX2) + +/* CAN mailbox data low register (CAN_TDLxR) */ +#define CAN_TDLxR(can_base, mbox) MMIO32(can_base + mbox + 0x8) +#define CAN_TDL0R(can_base) CAN_TDLxR(can_base, CAN_MBOX0) +#define CAN_TDL1R(can_base) CAN_TDLxR(can_base, CAN_MBOX1) +#define CAN_TDL2R(can_base) CAN_TDLxR(can_base, CAN_MBOX2) + +/* CAN mailbox data high register (CAN_TDHxR) */ +#define CAN_TDHxR(can_base, mbox) MMIO32(can_base + mbox + 0xC) +#define CAN_TDH0R(can_base) CAN_TDHxR(can_base, CAN_MBOX0) +#define CAN_TDH1R(can_base) CAN_TDHxR(can_base, CAN_MBOX1) +#define CAN_TDH2R(can_base) CAN_TDHxR(can_base, CAN_MBOX2) + +/* CAN RX FIFO identifier register (CAN_RIxR) */ +#define CAN_RIxR(can_base, fifo) MMIO32(can_base + fifo + 0x0) +#define CAN_RI0R(can_base) CAN_RIxR(can_base, CAN_FIFO0) +#define CAN_RI1R(can_base) CAN_RIxR(can_base, CAN_FIFO1) + +/* CAN RX FIFO mailbox data length control & time stamp register (CAN_RDTxR) */ +#define CAN_RDTxR(can_base, fifo) MMIO32(can_base + fifo + 0x4) +#define CAN_RDT0R(can_base) CAN_RDTxR(can_base, CAN_FIFO0) +#define CAN_RDT1R(can_base) CAN_RDTxR(can_base, CAN_FIFO1) + +/* CAN RX FIFO mailbox data low register (CAN_RDLxR) */ +#define CAN_RDLxR(can_base, fifo) MMIO32(can_base + fifo + 0x8) +#define CAN_RDL0R(can_base) CAN_RDLxR(can_base, CAN_FIFO0) +#define CAN_RDL1R(can_base) CAN_RDLxR(can_base, CAN_FIFO1) + +/* CAN RX FIFO mailbox data high register (CAN_RDHxR) */ +#define CAN_RDHxR(can_base, fifo) MMIO32(can_base + fifo + 0xC) +#define CAN_RDH0R(can_base) CAN_RDHxR(can_base, CAN_FIFO0) +#define CAN_RDH1R(can_base) CAN_RDHxR(can_base, CAN_FIFO1) + +/* --- CAN filter registers ------------------------------------------------ */ + +/* CAN filter master register (CAN_FMR) */ +#define CAN_FMR(can_base) MMIO32(can_base + 0x200) + +/* CAN filter mode register (CAN_FM1R) */ +#define CAN_FM1R(can_base) MMIO32(can_base + 0x204) + +/* Register offset 0x208 is reserved. */ + +/* CAN filter scale register (CAN_FS1R) */ +#define CAN_FS1R(can_base) MMIO32(can_base + 0x20C) + +/* Register offset 0x210 is reserved. */ + +/* CAN filter FIFO assignement register (CAN_FFA1R) */ +#define CAN_FFA1R(can_base) MMIO32(can_base + 0x214) + +/* Register offset 0x218 is reserved. */ + +/* CAN filter activation register (CAN_FA1R) */ +#define CAN_FA1R(can_base) MMIO32(can_base + 0x21C) + +/* Register offset 0x220 is reserved. */ + +/* Registers with offset 0x224 to 0x23F are reserved. */ + +/* CAN filter bank registers (CAN_FiRx) */ +/* + * Connectivity line devices have 28 banks so the bank ID spans 0..27 + * all other devices have 14 banks so the bank ID spans 0..13. + */ +#define CAN_FiR1(can_base, bank) MMIO32(can_base + 0x240 + (bank * 0x8) + 0x0) +#define CAN_FiR2(can_base, bank) MMIO32(can_base + 0x240 + (bank * 0x8) + 0x4) + +/* --- CAN_MCR values ------------------------------------------------------ */ + +/* 31:17 Reserved, forced by hardware to 0 */ + +/* DBF: Debug freeze */ +#define CAN_MCR_DBF (1 << 16) + +/* RESET: bxCAN software master reset */ +#define CAN_MCR_RESET (1 << 15) + +/* 14:8 Reserved, forced by hardware to 0 */ + +/* TTCM: Time triggered communication mode */ +#define CAN_MCR_TTCM (1 << 7) + +/* ABOM: Automatic bus-off management */ +#define CAN_MCR_ABOM (1 << 6) + +/* AWUM: Automatic wakeup mode */ +#define CAN_MCR_AWUM (1 << 5) + +/* NART: No automatic retransmission */ +#define CAN_MCR_NART (1 << 4) + +/* RFLM: Receive FIFO locked mode */ +#define CAN_MCR_RFLM (1 << 3) + +/* TXFP: Transmit FIFO priority */ +#define CAN_MCR_TXFP (1 << 2) + +/* SLEEP: Sleep mode request */ +#define CAN_MCR_SLEEP (1 << 1) + +/* INRQ: Initialization request */ +#define CAN_MCR_INRQ (1 << 0) + +/* --- CAN_MSR values ------------------------------------------------------ */ + +/* 31:12 Reserved, forced by hardware to 0 */ + +/* RX: CAN Rx signal */ +#define CAN_MSR_RX (1 << 11) + +/* SAMP: Last sample point */ +#define CAN_MSR_SAMP (1 << 10) + +/* RXM: Receive mode */ +#define CAN_MSR_RXM (1 << 9) + +/* TXM: Transmit mode */ +#define CAN_MSR_TXM (1 << 8) + +/* 7:5 Reserved, forced by hardware to 0 */ + +/* SLAKI: Sleep acknowledge interrupt */ +#define CAN_MSR_SLAKI (1 << 4) + +/* WKUI: Wakeup interrupt */ +#define CAN_MSR_WKUI (1 << 3) + +/* ERRI: Error interrupt */ +#define CAN_MSR_ERRI (1 << 2) + +/* SLAK: Sleep acknowledge */ +#define CAN_MSR_SLAK (1 << 1) + +/* INAK: Initialization acknowledge */ +#define CAN_MSR_INAK (1 << 0) + +/* --- CAN_TSR values ------------------------------------------------------ */ + +/* LOW2: Lowest priority flag for mailbox 2 */ +#define CAN_TSR_LOW2 (1 << 31) + +/* LOW1: Lowest priority flag for mailbox 1 */ +#define CAN_TSR_LOW1 (1 << 30) + +/* LOW0: Lowest priority flag for mailbox 0 */ +#define CAN_TSR_LOW0 (1 << 29) + +/* TME2: Transmit mailbox 2 empty */ +#define CAN_TSR_TME2 (1 << 28) + +/* TME1: Transmit mailbox 1 empty */ +#define CAN_TSR_TME1 (1 << 27) + +/* TME0: Transmit mailbox 0 empty */ +#define CAN_TSR_TME0 (1 << 26) + +/* CODE[1:0]: Mailbox code */ +#define CAN_TSR_CODE_MASK (0x3 << 24) + +/* ABRQ2: Abort request for mailbox 2 */ +#define CAN_TSR_TABRQ2 (1 << 23) + +/* 22:20 Reserved, forced by hardware to 0 */ + +/* TERR2: Transmission error for mailbox 2 */ +#define CAN_TSR_TERR2 (1 << 19) + +/* ALST2: Arbitration lost for mailbox 2 */ +#define CAN_TSR_ALST2 (1 << 18) + +/* TXOK2: Transmission OK for mailbox 2 */ +#define CAN_TSR_TXOK2 (1 << 17) + +/* RQCP2: Request completed mailbox 2 */ +#define CAN_TSR_RQCP2 (1 << 16) + +/* ABRQ1: Abort request for mailbox 1 */ +#define CAN_TSR_ABRQ1 (1 << 15) + +/* 14:12 Reserved, forced by hardware to 0 */ + +/* TERR1: Transmission error for mailbox 1 */ +#define CAN_TSR_TERR1 (1 << 11) + +/* ALST1: Arbitration lost for mailbox 1 */ +#define CAN_TSR_ALST1 (1 << 10) + +/* TXOK1: Transmission OK for mailbox 1 */ +#define CAN_TSR_TXOK1 (1 << 9) + +/* RQCP1: Request completed mailbox 1 */ +#define CAN_TSR_RQCP1 (1 << 8) + +/* ABRQ0: Abort request for mailbox 0 */ +#define CAN_TSR_ABRQ0 (1 << 7) + +/* 6:4 Reserved, forced by hardware to 0 */ + +/* TERR0: Transmission error for mailbox 0 */ +#define CAN_TSR_TERR0 (1 << 3) + +/* ALST0: Arbitration lost for mailbox 0 */ +#define CAN_TSR_ALST0 (1 << 2) + +/* TXOK0: Transmission OK for mailbox 0 */ +#define CAN_TSR_TXOK0 (1 << 1) + +/* RQCP0: Request completed mailbox 0 */ +#define CAN_TSR_RQCP0 (1 << 0) + +/* --- CAN_RF0R values ----------------------------------------------------- */ + +/* 31:6 Reserved, forced by hardware to 0 */ + +/* RFOM0: Release FIFO 0 output mailbox */ +#define CAN_RF0R_RFOM0 (1 << 5) + +/* FOVR0: FIFO 0 overrun */ +#define CAN_RF0R_FAVR0 (1 << 4) + +/* FULL0: FIFO 0 full */ +#define CAN_RF0R_FULL0 (1 << 3) + +/* 2 Reserved, forced by hardware to 0 */ + +/* FMP0[1:0]: FIFO 0 message pending */ +#define CAN_RF0R_FMP0_MASK (0x3 << 0) + +/* --- CAN_RF1R values ----------------------------------------------------- */ + +/* 31:6 Reserved, forced by hardware to 0 */ + +/* RFOM1: Release FIFO 1 output mailbox */ +#define CAN_RF1R_RFOM1 (1 << 5) + +/* FOVR1: FIFO 1 overrun */ +#define CAN_RF1R_FAVR1 (1 << 4) + +/* FULL1: FIFO 1 full */ +#define CAN_RF1R_FULL1 (1 << 3) + +/* 2 Reserved, forced by hardware to 0 */ + +/* FMP1[1:0]: FIFO 1 message pending */ +#define CAN_RF1R_FMP1_MASK (0x3 << 0) + +/* --- CAN_IER values ------------------------------------------------------ */ + +/* 32:18 Reserved, forced by hardware to 0 */ + +/* SLKIE: Sleep interrupt enable */ +#define CAN_IER_SLKIE (1 << 17) + +/* WKUIE: Wakeup interrupt enable */ +#define CAN_IER_WKUIE (1 << 16) + +/* ERRIE: Error interrupt enable */ +#define CAN_IER_ERRIE (1 << 15) + +/* 14:12 Reserved, forced by hardware to 0 */ + +/* LECIE: Last error code interrupt enable */ +#define CAN_IER_LECIE (1 << 11) + +/* BOFIE: Bus-off interrupt enable */ +#define CAN_IER_BOFIE (1 << 10) + +/* EPVIE: Error passive interrupt enable */ +#define CAN_IER_EPVIE (1 << 9) + +/* EWGIE: Error warning interrupt enable */ +#define CAN_IER_EWGIE (1 << 8) + +/* 7 Reserved, forced by hardware to 0 */ + +/* FOVIE1: FIFO overrun interrupt enable */ +#define CAN_IER_FOVIE1 (1 << 6) + +/* FFIE1: FIFO full interrupt enable */ +#define CAN_IER_FFIE1 (1 << 5) + +/* FMPIE1: FIFO message pending interrupt enable */ +#define CAN_IER_FMPIE1 (1 << 4) + +/* FOVIE0: FIFO overrun interrupt enable */ +#define CAN_IER_FOVIE0 (1 << 3) + +/* FFIE0: FIFO full interrupt enable */ +#define CAN_IER_FFIE0 (1 << 2) + +/* FMPIE0: FIFO message pending interrupt enable */ +#define CAN_IER_FMPIE0 (1 << 1) + +/* TMEIE: Transmit mailbox empty interrupt enable */ +#define CAN_IER_TMEIE (1 << 0) + +/* --- CAN_ESR values ------------------------------------------------------ */ + +/* REC[7:0]: Receive error counter */ +#define CAN_ESR_REC_MASK (0xF << 24) + +/* TEC[7:0]: Least significant byte of the 9-bit transmit error counter */ +#define CAN_ESR_TEC_MASK (0xF << 16) + +/* 15:7 Reserved, forced by hardware to 0 */ + +/* LEC[2:0]: Last error code */ +#define CAN_ESR_LEC_NO_ERROR (0x0 << 4) +#define CAN_ESR_LEC_STUFF_ERROR (0x1 << 4) +#define CAN_ESR_LEC_FORM_ERROR (0x2 << 4) +#define CAN_ESR_LEC_ACK_ERROR (0x3 << 4) +#define CAN_ESR_LEC_REC_ERROR (0x4 << 4) +#define CAN_ESR_LEC_DOM_ERROR (0x5 << 4) +#define CAN_ESR_LEC_CRC_ERROR (0x6 << 4) +#define CAN_ESR_LEC_SOFT_ERROR (0x7 << 4) +#define CAN_ESR_LEC_MASK (0x7 << 4) + +/* 3 Reserved, forced by hardware to 0 */ + +/* BOFF: Bus-off flag */ +#define CAN_ESR_BOFF (1 << 2) + +/* EPVF: Error passive flag */ +#define CAN_ESR_EPVF (1 << 1) + +/* EWGF: Error warning flag */ +#define CAN_ESR_EWGF (1 << 0) + +/* --- CAN_BTR values ------------------------------------------------------ */ + +/* SILM: Silent mode (debug) */ +#define CAN_BTR_SILM (1 << 31) + +/* LBKM: Loop back mode (debug) */ +#define CAN_BTR_LBKM (1 << 30) + +/* 29:26 Reserved, forced by hardware to 0 */ + +/* SJW[1:0]: Resynchronization jump width */ +#define CAN_BTR_SJW_1TQ (0x0 << 24) +#define CAN_BTR_SJW_2TQ (0x1 << 24) +#define CAN_BTR_SJW_3TQ (0x2 << 24) +#define CAN_BTR_SJW_4TQ (0x3 << 24) +#define CAN_BTR_SJW_MASK (0x3 << 24) + +/* 23 Reserved, forced by hardware to 0 */ + +/* TS2[2:0]: Time segment 2 */ +#define CAN_BTR_TS2_1TQ (0x0 << 20) +#define CAN_BTR_TS2_2TQ (0x1 << 20) +#define CAN_BTR_TS2_3TQ (0x2 << 20) +#define CAN_BTR_TS2_4TQ (0x3 << 20) +#define CAN_BTR_TS2_5TQ (0x4 << 20) +#define CAN_BTR_TS2_6TQ (0x5 << 20) +#define CAN_BTR_TS2_7TQ (0x6 << 20) +#define CAN_BTR_TS2_8TQ (0x7 << 20) +#define CAN_BTR_TS2_MASK (0x7 << 20) + +/* TS1[3:0]: Time segment 1 */ +#define CAN_BTR_TS1_1TQ (0x0 << 16) +#define CAN_BTR_TS1_2TQ (0x1 << 16) +#define CAN_BTR_TS1_3TQ (0x2 << 16) +#define CAN_BTR_TS1_4TQ (0x3 << 16) +#define CAN_BTR_TS1_5TQ (0x4 << 16) +#define CAN_BTR_TS1_6TQ (0x5 << 16) +#define CAN_BTR_TS1_7TQ (0x6 << 16) +#define CAN_BTR_TS1_8TQ (0x7 << 16) +#define CAN_BTR_TS1_9TQ (0x8 << 16) +#define CAN_BTR_TS1_10TQ (0x9 << 16) +#define CAN_BTR_TS1_11TQ (0xA << 16) +#define CAN_BTR_TS1_12TQ (0xB << 16) +#define CAN_BTR_TS1_13TQ (0xC << 16) +#define CAN_BTR_TS1_14TQ (0xD << 16) +#define CAN_BTR_TS1_15TQ (0xE << 16) +#define CAN_BTR_TS1_16TQ (0xF << 16) +#define CAN_BTR_TS1_MASK (0xF << 16) + +/* 15:10 Reserved, forced by hardware to 0 */ + +/* BRP[9:0]: Baud rate prescaler */ +#define CAN_BTR_BRP_MASK (0x1FF << 0) + +/* --- CAN_TIxR values ------------------------------------------------------ */ + +/* STID[10:0]: Standard identifier */ +#define CAN_TIxR_STID_MASK (0x3FF << 21) +#define CAN_TIxR_STID_SHIFT 21 + +/* EXID[15:0]: Extended identifier */ +#define CAN_TIxR_EXID_MASK (0x1FFFFFF << 3) +#define CAN_TIxR_EXID_SHIFT 3 + +/* IDE: Identifier extension */ +#define CAN_TIxR_IDE (1 << 2) + +/* RTR: Remote transmission request */ +#define CAN_TIxR_RTR (1 << 1) + +/* TXRQ: Transmit mailbox request */ +#define CAN_TIxR_TXRQ (1 << 0) + +/* --- CAN_TDTxR values ----------------------------------------------------- */ + +/* TIME[15:0]: Message time stamp */ +#define CAN_TDTxR_TIME_MASK (0xFFFF << 15) +#define CAN_TDTxR_TIME_SHIFT 15 + +/* 15:6 Reserved, forced by hardware to 0 */ + +/* TGT: Transmit global time */ +#define CAN_TDTxR_TGT (1 << 5) + +/* 7:4 Reserved, forced by hardware to 0 */ + +/* DLC[3:0]: Data length code */ +#define CAN_TDTxR_DLC_MASK (0xF << 0) +#define CAN_TDTxR_DLC_SHIFT 0 + +/* --- CAN_TDLxR values ----------------------------------------------------- */ + +/* DATA3[7:0]: Data byte 3 */ +/* DATA2[7:0]: Data byte 2 */ +/* DATA1[7:0]: Data byte 1 */ +/* DATA0[7:0]: Data byte 0 */ + +/* --- CAN_TDHxR values ----------------------------------------------------- */ + +/* DATA7[7:0]: Data byte 7 */ +/* DATA6[7:0]: Data byte 6 */ +/* DATA5[7:0]: Data byte 5 */ +/* DATA4[7:0]: Data byte 4 */ + +/* --- CAN_RIxR values ------------------------------------------------------ */ + +/* STID[10:0]: Standard identifier */ +#define CAN_RIxR_STID_MASK (0x3FF << 21) +#define CAN_RIxR_STID_SHIFT 21 + +/* EXID[15:0]: Extended identifier */ +#define CAN_RIxR_EXID_MASK (0x1FFFFFF << 3) +#define CAN_RIxR_EXID_SHIFT 3 + +/* IDE: Identifier extension */ +#define CAN_RIxR_IDE (1 << 2) + +/* RTR: Remote transmission request */ +#define CAN_RIxR_RTR (1 << 1) + +/* 0 Reserved */ + +/* --- CAN_RDTxR values ----------------------------------------------------- */ + +/* TIME[15:0]: Message time stamp */ +#define CAN_RDTxR_TIME_MASK (0xFFFF << 15) +#define CAN_RDTxR_TIME_SHIFT 15 + +/* FMI[7:0]: Filter match index */ +#define CAN_RDTxR_FMI_MASK (0xFF << 8) +#define CAN_RDTxR_FMI_SHIFT 8 + +/* 7:4 Reserved, forced by hardware to 0 */ + +/* DLC[3:0]: Data length code */ +#define CAN_RDTxR_DLC_MASK (0xF << 0) +#define CAN_RDTxR_DLC_SHIFT 0 + +/* --- CAN_RDLxR values ----------------------------------------------------- */ + +/* DATA3[7:0]: Data byte 3 */ +/* DATA2[7:0]: Data byte 2 */ +/* DATA1[7:0]: Data byte 1 */ +/* DATA0[7:0]: Data byte 0 */ + +/* --- CAN_RDHxR values ----------------------------------------------------- */ + +/* DATA7[7:0]: Data byte 7 */ +/* DATA6[7:0]: Data byte 6 */ +/* DATA5[7:0]: Data byte 5 */ +/* DATA4[7:0]: Data byte 4 */ + +/* --- CAN_FMR values ------------------------------------------------------- */ + +/* 31:14 Reserved, forced to reset value */ + +/* + * CAN2SB[5:0]: CAN2 start bank + * (only on connectivity line devices otherwise reserved) + */ +#define CAN_FMR_CAN2SB_MASK (0x3F << 8) +#define CAN_FMR_CAN2SB_SHIFT 15 + +/* 7:1 Reserved, forced to reset value */ + +/* FINIT: Filter init mode */ +#define CAN_FMR_FINIT (1 << 0) + +/* --- CAN_FM1R values ------------------------------------------------------ */ + +/* 31:28 Reserved, forced by hardware to 0 */ + +/* + * FBMx: Filter mode + * x is 0..27 should be calculated by a helper function making so many macros + * seems like an overkill? + */ + +/* --- CAN_FS1R values ------------------------------------------------------ */ + +/* 31:28 Reserved, forced by hardware to 0 */ + +/* + * FSCx: Filter scale configuration + * x is 0..27 should be calculated by a helper function making so many macros + * seems like an overkill? + */ + +/* --- CAN_FFA1R values ----------------------------------------------------- */ + +/* 31:28 Reserved, forced by hardware to 0 */ + +/* + * FFAx: Filter scale configuration + * x is 0..27 should be calculated by a helper function making so many macros + * seems like an overkill? + */ + +/* --- CAN_FA1R values ------------------------------------------------------ */ + +/* 31:28 Reserved, forced by hardware to 0 */ + +/* + * FACTx: Filter active + * x is 0..27 should be calculated by a helper function making so many macros + * seems like an overkill? + */ + +/* --- CAN_FiRx values ------------------------------------------------------ */ + +/* FB[31:0]: Filter bits */ + +/* --- CAN functions -------------------------------------------------------- */ + +void can_reset(u32 canport); +int can_init(u32 canport, bool ttcm, bool abom, bool awum, bool nart, + bool rflm, bool txfp, u32 sjw, u32 ts1, u32 ts2, u32 brp); + +void can_filter_init(u32 canport, u32 nr, bool scale_32bit, bool id_list_mode, + u32 fr1, u32 fr2, u32 fifo, bool enable); +void can_filter_id_mask_16bit_init(u32 canport, u32 nr, u16 id1, u16 mask1, + u16 id2, u16 mask2, u32 fifo, bool enable); +void can_filter_id_mask_32bit_init(u32 canport, u32 nr, u32 id, u32 mask, + u32 fifo, bool enable); +void can_filter_id_list_16bit_init(u32 canport, u32 nr, u16 id1, u16 id2, + u16 id3, u16 id4, u32 fifo, bool enable); +void can_filter_id_list_32bit_init(u32 canport, u32 nr, u32 id1, u32 id2, + u32 fifo, bool enable); + +void can_enable_irq(u32 canport, u32 irq); +void can_disable_irq(u32 canport, u32 irq); + +int can_transmit(u32 canport, u32 id, bool ext, bool rtr, u8 length, u8 *data); +void can_receive(u32 canport, u8 fifo, bool release, u32 *id, bool *ext, + bool *rtr, u32 *fmi, u8 *length, u8 *data); + +void can_fifo_release(u32 canport, u8 fifo); + +#endif diff --git a/include/libopencm3/stm32f1/crc.h b/include/libopencm3/stm32f1/crc.h new file mode 100644 index 0000000..5ad866e --- /dev/null +++ b/include/libopencm3/stm32f1/crc.h @@ -0,0 +1,52 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_CRC_H +#define LIBOPENCM3_CRC_H + +#include +#include + +/* --- CRC registers ------------------------------------------------------- */ + +/* Data register (CRC_DR) */ +#define CRC_DR MMIO32(CRC_BASE + 0x00) + +/* Independent data register (CRC_IDR) */ +#define CRC_IDR MMIO32(CRC_BASE + 0x04) + +/* Control register (CRC_CR) */ +#define CRC_CR MMIO32(CRC_BASE + 0x08) + +/* --- CRC_DR values ------------------------------------------------------- */ + +/* Bits[31:0] Data register */ + +/* --- CRC_IDR values ------------------------------------------------------ */ + +/* Bits[7:0] General-purpose 8-bit data register bits */ + +/* --- CRC_CR values ------------------------------------------------------- */ + +/* RESET bit */ +#define CRC_CR_RESET (1 << 0) + +/* --- CRC function prototypes --------------------------------------------- */ + +#endif diff --git a/include/libopencm3/stm32f1/dbgmcu.h b/include/libopencm3/stm32f1/dbgmcu.h new file mode 100644 index 0000000..e753f5e --- /dev/null +++ b/include/libopencm3/stm32f1/dbgmcu.h @@ -0,0 +1,60 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Gareth McMullin + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_STM32_DBGMCU_H +#define LIBOPENCM3_STM32_DBGMCU_H + +#include +#include + +/* --- DBGMCU registers ---------------------------------------------------- */ + +#define DBGMCU_IDCODE MMIO32(DBGMCU_BASE + 0x00) +#define DBGMCU_CR MMIO32(DBGMCU_BASE + 0x04) + +/* DBGMCU_CR bits */ +#define DBGMCU_CR_SLEEP 0x00000001 +#define DBGMCU_CR_STOP 0x00000002 +#define DBGMCU_CR_STANDBY 0x00000004 +#define DBGMCU_CR_TRACE_IOEN 0x00000020 +#define DBGMCU_CR_TRACE_MODE_MASK 0x000000C0 +#define DBGMCU_CR_TRACE_MODE_ASYNC 0x00000000 +#define DBGMCU_CR_TRACE_MODE_SYNC_1 0x00000040 +#define DBGMCU_CR_TRACE_MODE_SYNC_2 0x00000080 +#define DBGMCU_CR_TRACE_MODE_SYNC_4 0x000000C0 +#define DBGMCU_CR_IWDG_STOP 0x00000100 +#define DBGMCU_CR_WWDG_STOP 0x00000200 +#define DBGMCU_CR_TIM1_STOP 0x00000400 +#define DBGMCU_CR_TIM2_STOP 0x00000800 +#define DBGMCU_CR_TIM3_STOP 0x00001000 +#define DBGMCU_CR_TIM4_STOP 0x00002000 +#define DBGMCU_CR_CAN1_STOP 0x00004000 +#define DBGMCU_CR_I2C1_SMBUS_TIMEOUT 0x00008000 +#define DBGMCU_CR_I2C2_SMBUS_TIMEOUT 0x00010000 +#define DBGMCU_CR_TIM8_STOP 0x00020000 +#define DBGMCU_CR_TIM5_STOP 0x00040000 +#define DBGMCU_CR_TIM6_STOP 0x00080000 +#define DBGMCU_CR_TIM7_STOP 0x00100000 +#define DBGMCU_CR_CAN2_STOP 0x00200000 + +/* DBGMCU_IDCODE bits */ +#define DBGMCU_IDCODE_DEV_ID_MASK 0x00000fff +#define DBGMCU_IDCODE_REV_ID_MASK 0xffff0000 + +#endif diff --git a/include/libopencm3/stm32f1/dma.h b/include/libopencm3/stm32f1/dma.h new file mode 100644 index 0000000..7d0a856 --- /dev/null +++ b/include/libopencm3/stm32f1/dma.h @@ -0,0 +1,723 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_DMA_H +#define LIBOPENCM3_DMA_H + +#include +#include + +/* --- Convenience macros -------------------------------------------------- */ + +/* DMA register base adresses (for convenience) */ +#define DMA1 DMA1_BASE +#define DMA2 DMA2_BASE + +/* --- DMA registers ------------------------------------------------------- */ + +/* DMA interrupt status register (DMAx_ISR) */ +#define DMA_ISR(dma_base) MMIO32(dma_base + 0x00) +#define DMA1_ISR DMA_ISR(DMA1) +#define DMA2_ISR DMA_ISR(DMA2) + +/* DMA interrupt flag clear register (DMAx_IFCR) */ +#define DMA_IFCR(dma_base) MMIO32(dma_base + 0x04) +#define DMA1_IFCR DMA_IFCR(DMA1) +#define DMA2_IFCR DMA_IFCR(DMA2) + +/* DMA channel 1 configuration register (DMAx_CCR1) */ +#define DMA_CCR1(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 0) +#define DMA1_CCR1 DMA_CCR1(DMA1) +#define DMA2_CCR1 DMA_CCR1(DMA2) + +/* DMA channel 2 configuration register (DMAx_CCR2) */ +#define DMA_CCR2(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 1) +#define DMA1_CCR2 DMA_CCR2(DMA1) +#define DMA2_CCR2 DMA_CCR2(DMA2) + +/* DMA channel 3 configuration register (DMAx_CCR3) */ +#define DMA_CCR3(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 2) +#define DMA1_CCR3 DMA_CCR3(DMA1) +#define DMA2_CCR3 DMA_CCR3(DMA2) + +/* DMA channel 4 configuration register (DMAx_CCR4) */ +#define DMA_CCR4(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 3) +#define DMA1_CCR4 DMA_CCR4(DMA1) +#define DMA2_CCR4 DMA_CCR4(DMA2) + +/* DMA channel 5 configuration register (DMAx_CCR5) */ +#define DMA_CCR5(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 4) +#define DMA1_CCR5 DMA_CCR5(DMA1) +#define DMA2_CCR5 DMA_CCR5(DMA2) + +/* DMA channel 6 configuration register (DMAx_CCR6) */ +#define DMA_CCR6(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 5) +#define DMA1_CCR6 DMA_CCR6(DMA1) + +/* DMA channel 7 configuration register (DMAx_CCR7) */ +#define DMA_CCR7(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 6) +#define DMA1_CCR7 DMA_CCR7(DMA1) + +/* DMA channel 1 number of data register (DMAx_CNDTR1) */ +#define DMA_CNDTR1(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 0) +#define DMA1_CNDTR1 DMA_CNDTR1(DMA1) +#define DMA2_CNDTR1 DMA_CNDTR1(DMA2) + +/* DMA channel 2 number of data register (DMAx_CNDTR2) */ +#define DMA_CNDTR2(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 1) +#define DMA1_CNDTR2 DMA_CNDTR2(DMA1) +#define DMA2_CNDTR2 DMA_CNDTR2(DMA2) + +/* DMA channel 3 number of data register (DMAx_CNDTR3) */ +#define DMA_CNDTR3(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 2) +#define DMA1_CNDTR3 DMA_CNDTR3(DMA1) +#define DMA2_CNDTR3 DMA_CNDTR3(DMA2) + +/* DMA channel 4 number of data register (DMAx_CNDTR4) */ +#define DMA_CNDTR4(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 3) +#define DMA1_CNDTR4 DMA_CNDTR4(DMA1) +#define DMA2_CNDTR4 DMA_CNDTR4(DMA2) + +/* DMA channel 5 number of data register (DMAx_CNDTR5) */ +#define DMA_CNDTR5(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 4) +#define DMA1_CNDTR5 DMA_CNDTR5(DMA1) +#define DMA2_CNDTR5 DMA_CNDTR5(DMA2) + +/* DMA channel 6 number of data register (DMAx_CNDTR6) */ +#define DMA_CNDTR6(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 5) +#define DMA1_CNDTR6 DMA_CNDTR6(DMA1) + +/* DMA channel 7 number of data register (DMAx_CNDTR7) */ +#define DMA_CNDTR7(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 6) +#define DMA1_CNDTR7 DMA_CNDTR7(DMA1) + +/* DMA channel 1 peripheral address register (DMAx_CPAR1) */ +#define DMA_CPAR1(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 0) +#define DMA1_CPAR1 DMA_CPAR1(DMA1) +#define DMA2_CPAR1 DMA_CPAR1(DMA2) + +/* DMA channel 2 peripheral address register (DMAx_CPAR2) */ +#define DMA_CPAR2(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 1) +#define DMA1_CPAR2 DMA_CPAR2(DMA1) +#define DMA2_CPAR2 DMA_CPAR2(DMA2) + +/* DMA channel 3 peripheral address register (DMAx_CPAR3) */ +#define DMA_CPAR3(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 2) +#define DMA1_CPAR3 DMA_CPAR3(DMA1) +#define DMA2_CPAR3 DMA_CPAR3(DMA2) + +/* DMA channel 4 peripheral address register (DMAx_CPAR4) */ +#define DMA_CPAR4(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 3) +#define DMA1_CPAR4 DMA_CPAR4(DMA1) +#define DMA2_CPAR4 DMA_CPAR4(DMA2) + +/* DMA channel 5 peripheral address register (DMAx_CPAR5) */ +#define DMA_CPAR5(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 4) +#define DMA1_CPAR5 DMA_CPAR5(DMA1) +#define DMA2_CPAR5 DMA_CPAR5(DMA2) + +/* DMA channel 6 peripheral address register (DMAx_CPAR6) */ +#define DMA_CPAR6(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 5) +#define DMA1_CPAR6 DMA_CPAR6(DMA1) + +/* DMA channel 7 peripheral address register (DMAx_CPAR7) */ +#define DMA_CPAR7(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 6) +#define DMA1_CPAR7 DMA_CPAR7(DMA1) + +/* DMA channel 1 memory address register (DMAx_CMAR1) */ +#define DMA_CMAR1(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 0) +#define DMA1_CMAR1 DMA_CMAR1(DMA1) +#define DMA2_CMAR1 DMA_CMAR1(DMA2) + +/* DMA channel 2 memory address register (DMAx_CMAR2) */ +#define DMA_CMAR2(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 1) +#define DMA1_CMAR2 DMA_CMAR2(DMA1) +#define DMA2_CMAR2 DMA_CMAR2(DMA2) + +/* DMA channel 3 memory address register (DMAx_CMAR3) */ +#define DMA_CMAR3(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 2) +#define DMA1_CMAR3 DMA_CMAR3(DMA1) +#define DMA2_CMAR3 DMA_CMAR3(DMA2) + +/* DMA channel 4 memory address register (DMAx_CMAR4) */ +#define DMA_CMAR4(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 3) +#define DMA1_CMAR4 DMA_CMAR4(DMA1) +#define DMA2_CMAR4 DMA_CMAR4(DMA2) + +/* DMA channel 5 memory address register (DMAx_CMAR5) */ +#define DMA_CMAR5(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 4) +#define DMA1_CMAR5 DMA_CMAR5(DMA1) +#define DMA2_CMAR5 DMA_CMAR5(DMA2) + +/* DMA channel 6 memory address register (DMAx_CMAR6) */ +#define DMA_CMAR6(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 5) +#define DMA1_CMAR6 DMA_CMAR6(DMA1) + +/* DMA channel 7 memory address register (DMAx_CMAR7) */ +#define DMA_CMAR7(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 6) +#define DMA1_CMAR7 DMA_CMAR7(DMA1) + +/* --- DMA_ISR values ------------------------------------------------------ */ + +/* TEIF7: Channel 7 transfer error flag */ +#define DMA_ISR_TEIF7 (1 << 27) +/* HTIF7: Channel 7 half transfer flag */ +#define DMA_ISR_HTIF7 (1 << 26) +/* TCIF7: Channel 7 transfer complete flag */ +#define DMA_ISR_TCIF7 (1 << 25) +/* GIF7: Channel 7 global interrupt flag */ +#define DMA_ISR_GIF7 (1 << 24) +/* TEIF6: Channel 6 transfer error flag */ +#define DMA_ISR_TEIF6 (1 << 23) +/* HTIF6: Channel 6 half transfer flag */ +#define DMA_ISR_HTIF6 (1 << 22) +/* TCIF6: Channel 6 transfer complete flag */ +#define DMA_ISR_TCIF6 (1 << 21) +/* GIF6: Channel 6 global interrupt flag */ +#define DMA_ISR_GIF6 (1 << 20) +/* TEIF5: Channel 5 transfer error flag */ +#define DMA_ISR_TEIF5 (1 << 19) +/* HTIF5: Channel 5 half transfer flag */ +#define DMA_ISR_HTIF5 (1 << 18) +/* TCIF5: Channel 5 transfer complete flag */ +#define DMA_ISR_TCIF5 (1 << 17) +/* GIF5: Channel 5 global interrupt flag */ +#define DMA_ISR_GIF5 (1 << 16) +/* TEIF4: Channel 4 transfer error flag */ +#define DMA_ISR_TEIF4 (1 << 15) +/* HTIF4: Channel 4 half transfer flag */ +#define DMA_ISR_HTIF4 (1 << 14) +/* TCIF4: Channel 4 transfer complete flag */ +#define DMA_ISR_TCIF4 (1 << 13) +/* GIF4: Channel 4 global interrupt flag */ +#define DMA_ISR_GIF4 (1 << 12) +/* TEIF3: Channel 3 transfer error flag */ +#define DMA_ISR_TEIF3 (1 << 11) +/* HTIF3: Channel 3 half transfer flag */ +#define DMA_ISR_HTIF3 (1 << 10) +/* TCIF3: Channel 3 transfer complete flag */ +#define DMA_ISR_TCIF3 (1 << 9) +/* GIF3: Channel 3 global interrupt flag */ +#define DMA_ISR_GIF3 (1 << 8) +/* TEIF2: Channel 2 transfer error flag */ +#define DMA_ISR_TEIF2 (1 << 7) +/* HTIF2: Channel 23 half transfer flag */ +#define DMA_ISR_HTIF2 (1 << 6) +/* TCIF2: Channel 2 transfer complete flag */ +#define DMA_ISR_TCIF2 (1 << 5) +/* GIF2: Channel 2 global interrupt flag */ +#define DMA_ISR_GIF2 (1 << 4) +/* TEIF1: Channel 1 transfer error flag */ +#define DMA_ISR_TEIF1 (1 << 3) +/* HTIF1: Channel 1 half transfer flag */ +#define DMA_ISR_HTIF1 (1 << 2) +/* TCIF1: Channel 1 transfer complete flag */ +#define DMA_ISR_TCIF1 (1 << 1) +/* GIF1: Channel 1 global interrupt flag */ +#define DMA_ISR_GIF1 (1 << 0) + +/* --- DMA_IFCR values ----------------------------------------------------- */ + +/* CTEIF7: Channel 7 transfer error clear */ +#define DMA_IFCR_CTEIF7 (1 << 27) +/* CHTIF7: Channel 7 half transfer clear */ +#define DMA_IFCR_CHTIF7 (1 << 26) +/* CTCIF7: Channel 7 transfer complete clear */ +#define DMA_IFCR_CTCIF7 (1 << 25) +/* CGIF7: Channel 7 global interrupt clear */ +#define DMA_IFCR_CGIF7 (1 << 24) +/* CTEIF6: Channel 6 transfer error clear */ +#define DMA_IFCR_CTEIF6 (1 << 23) +/* CHTIF6: Channel 6 half transfer clear */ +#define DMA_IFCR_CHTIF6 (1 << 22) +/* CTCIF6: Channel 6 transfer complete clear */ +#define DMA_IFCR_CTCIF6 (1 << 21) +/* CGIF6: Channel 6 global interrupt clear */ +#define DMA_IFCR_CGIF6 (1 << 20) +/* CTEIF5: Channel 5 transfer error clear */ +#define DMA_IFCR_CTEIF5 (1 << 19) +/* CHTIF5: Channel 5 half transfer clear */ +#define DMA_IFCR_CHTIF5 (1 << 18) +/* CTCIF5: Channel 5 transfer complete clear */ +#define DMA_IFCR_CTCIF5 (1 << 17) +/* CGIF5: Channel 5 global interrupt clear */ +#define DMA_IFCR_CGIF5 (1 << 16) +/* CTEIF4: Channel 4 transfer error clear */ +#define DMA_IFCR_CTEIF4 (1 << 15) +/* CHTIF4: Channel 4 half transfer clear */ +#define DMA_IFCR_CHTIF4 (1 << 14) +/* CTCIF4: Channel 4 transfer complete clear */ +#define DMA_IFCR_CTCIF4 (1 << 13) +/* CGIF4: Channel 4 global interrupt clear */ +#define DMA_IFCR_CGIF4 (1 << 12) +/* CTEIF3: Channel 3 transfer error clear */ +#define DMA_IFCR_CTEIF3 (1 << 11) +/* CHTIF3: Channel 3 half transfer clear */ +#define DMA_IFCR_CHTIF3 (1 << 10) +/* CTCIF3: Channel 3 transfer complete clear */ +#define DMA_IFCR_CTCIF3 (1 << 9) +/* CGIF3: Channel 3 global interrupt clear */ +#define DMA_IFCR_CGIF3 (1 << 8) +/* CTEIF2: Channel 2 transfer error clear */ +#define DMA_IFCR_CTEIF2 (1 << 7) +/* CHTIF2: Channel 2 half transfer clear */ +#define DMA_IFCR_CHTIF2 (1 << 6) +/* CTCIF2: Channel 2 transfer complete clear */ +#define DMA_IFCR_CTCIF2 (1 << 5) +/* CGIF2: Channel 2 global interrupt clear */ +#define DMA_IFCR_CGIF2 (1 << 4) +/* CTEIF1: Channel 1 transfer error clear */ +#define DMA_IFCR_CTEIF1 (1 << 3) +/* CHTIF1: Channel 1 half transfer clear */ +#define DMA_IFCR_CHTIF1 (1 << 2) +/* CTCIF1: Channel 1 transfer complete clear */ +#define DMA_IFCR_CTCIF1 (1 << 1) +/* CGIF1: Channel 1 global interrupt clear */ +#define DMA_IFCR_CGIF1 (1 << 0) + +/* --- DMA_CCR1 values ----------------------------------------------------- */ + +/* MEM2MEM: Memory to memory mode */ +#define DMA_CCR1_MEM2MEM (1 << 14) + +/* PL[13:12]: Channel priority level */ +#define DMA_CCR1_PL_LSB 12 +#define DMA_CCR1_PL_LOW 0x0 +#define DMA_CCR1_PL_MEDIUM 0x1 +#define DMA_CCR1_PL_HIGH 0x2 +#define DMA_CCR1_PL_VERY_HIGH 0x3 + +/* MSIZE[11:10]: Memory size */ +#define DMA_CCR1_MSIZE_LSB 10 +#define DMA_CCR1_MSIZE_8BIT 0x0 +#define DMA_CCR1_MSIZE_16BIT 0x1 +#define DMA_CCR1_MSIZE_32BIT 0x2 + +/* PSIZE[9:8]: Peripheral size */ +#define DMA_CCR1_PSIZE_LSB 8 +#define DMA_CCR1_PSIZE_8BIT 0x0 +#define DMA_CCR1_PSIZE_16BIT 0x1 +#define DMA_CCR1_PSIZE_32BIT 0x2 + +/* MINC: Memory increment mode */ +#define DMA_CCR1_MINC (1 << 7) + +/* PINC: Peripheral increment mode */ +#define DMA_CCR1_PINC (1 << 6) + +/* CIRC: Circular mode */ +#define DMA_CCR1_CIRC (1 << 5) + +/* DIR: Data transfer direction */ +#define DMA_CCR1_DIR (1 << 4) + +/* TEIE: Transfer error interrupt enable */ +#define DMA_CCR1_TEIE (1 << 3) + +/* HTIE: Half transfer interrupt enable */ +#define DMA_CCR1_HTIE (1 << 2) + +/* TCIE: Transfer complete interrupt enable */ +#define DMA_CCR1_TCIE (1 << 1) + +/* EN: Channel enable */ +#define DMA_CCR1_EN (1 << 0) + +/* --- DMA_CCR2 values ----------------------------------------------------- */ + +/* MEM2MEM: Memory to memory mode */ +#define DMA_CCR2_MEM2MEM (1 << 14) + +/* PL[13:12]: Channel priority level */ +#define DMA_CCR2_PL_LSB 12 +#define DMA_CCR2_PL_LOW 0x0 +#define DMA_CCR2_PL_MEDIUM 0x1 +#define DMA_CCR2_PL_HIGH 0x2 +#define DMA_CCR2_PL_VERY_HIGH 0x3 + +/* MSIZE[11:10]: Memory size */ +#define DMA_CCR2_MSIZE_LSB 10 +#define DMA_CCR2_MSIZE_8BIT 0x0 +#define DMA_CCR2_MSIZE_16BIT 0x1 +#define DMA_CCR2_MSIZE_32BIT 0x2 + +/* PSIZE[9:8]: Peripheral size */ +#define DMA_CCR2_PSIZE_LSB 8 +#define DMA_CCR2_PSIZE_8BIT 0x0 +#define DMA_CCR2_PSIZE_16BIT 0x1 +#define DMA_CCR2_PSIZE_32BIT 0x2 + +/* MINC: Memory increment mode */ +#define DMA_CCR2_MINC (1 << 7) + +/* PINC: Peripheral increment mode */ +#define DMA_CCR2_PINC (1 << 6) + +/* CIRC: Circular mode */ +#define DMA_CCR2_CIRC (1 << 5) + +/* DIR: Data transfer direction */ +#define DMA_CCR2_DIR (1 << 4) + +/* TEIE: Transfer error interrupt enable */ +#define DMA_CCR2_TEIE (1 << 3) + +/* HTIE: Half transfer interrupt enable */ +#define DMA_CCR2_HTIE (1 << 2) + +/* TCIE: Transfer complete interrupt enable */ +#define DMA_CCR2_TCIE (1 << 1) + +/* EN: Channel enable */ +#define DMA_CCR2_EN (1 << 0) + +/* --- DMA_CCR3 values ----------------------------------------------------- */ + +/* MEM2MEM: Memory to memory mode */ +#define DMA_CCR3_MEM2MEM (1 << 14) + +/* PL[13:12]: Channel priority level */ +#define DMA_CCR3_PL_LSB 12 +#define DMA_CCR3_PL_LOW 0x0 +#define DMA_CCR3_PL_MEDIUM 0x1 +#define DMA_CCR3_PL_HIGH 0x2 +#define DMA_CCR3_PL_VERY_HIGH 0x3 + +/* MSIZE[11:10]: Memory size */ +#define DMA_CCR3_MSIZE_LSB 10 +#define DMA_CCR3_MSIZE_8BIT 0x0 +#define DMA_CCR31_MSIZE_16BIT 0x1 +#define DMA_CCR3_MSIZE_32BIT 0x2 + +/* PSIZE[9:8]: Peripheral size */ +#define DMA_CCR3_PSIZE_LSB 8 +#define DMA_CCR3_PSIZE_8BIT 0x0 +#define DMA_CCR3_PSIZE_16BIT 0x1 +#define DMA_CCR3_PSIZE_32BIT 0x2 + +/* MINC: Memory increment mode */ +#define DMA_CCR3_MINC (1 << 7) + +/* PINC: Peripheral increment mode */ +#define DMA_CCR3_PINC (1 << 6) + +/* CIRC: Circular mode */ +#define DMA_CCR3_CIRC (1 << 5) + +/* DIR: Data transfer direction */ +#define DMA_CCR3_DIR (1 << 4) + +/* TEIE: Transfer error interrupt enable */ +#define DMA_CCR3_TEIE (1 << 3) + +/* HTIE: Half transfer interrupt enable */ +#define DMA_CCR3_HTIE (1 << 2) + +/* TCIE: Transfer complete interrupt enable */ +#define DMA_CCR3_TCIE (1 << 1) + +/* EN: Channel enable */ +#define DMA_CCR3_EN (1 << 0) + +/* --- DMA_CCR4 values ----------------------------------------------------- */ + +/* MEM2MEM: Memory to memory mode */ +#define DMA_CCR4_MEM2MEM (1 << 14) + +/* PL[13:12]: Channel priority level */ +#define DMA_CCR4_PL_LSB 12 +#define DMA_CCR4_PL_LOW 0x0 +#define DMA_CCR4_PL_MEDIUM 0x1 +#define DMA_CCR4_PL_HIGH 0x2 +#define DMA_CCR4_PL_VERY_HIGH 0x3 + +/* MSIZE[11:10]: Memory size */ +#define DMA_CCR4_MSIZE_LSB 10 +#define DMA_CCR4_MSIZE_8BIT 0x0 +#define DMA_CCR4_MSIZE_16BIT 0x1 +#define DMA_CCR4_MSIZE_32BIT 0x2 + +/* PSIZE[9:8]: Peripheral size */ +#define DMA_CCR4_PSIZE_LSB 8 +#define DMA_CCR4_PSIZE_8BIT 0x0 +#define DMA_CCR4_PSIZE_16BIT 0x1 +#define DMA_CCR4_PSIZE_32BIT 0x2 + +/* MINC: Memory increment mode */ +#define DMA_CCR4_MINC (1 << 7) + +/* PINC: Peripheral increment mode */ +#define DMA_CCR4_PINC (1 << 6) + +/* CIRC: Circular mode */ +#define DMA_CCR4_CIRC (1 << 5) + +/* DIR: Data transfer direction */ +#define DMA_CCR4_DIR (1 << 4) + +/* TEIE: Transfer error interrupt enable */ +#define DMA_CCR4_TEIE (1 << 3) + +/* HTIE: Half transfer interrupt enable */ +#define DMA_CCR4_HTIE (1 << 2) + +/* TCIE: Transfer complete interrupt enable */ +#define DMA_CCR4_TCIE (1 << 1) + +/* EN: Channel enable */ +#define DMA_CCR4_EN (1 << 0) + +/* --- DMA_CCR5 values ----------------------------------------------------- */ + +/* MEM2MEM: Memory to memory mode */ +#define DMA_CCR5_MEM2MEM (1 << 14) + +/* PL[13:12]: Channel priority level */ +#define DMA_CCR5_PL_LSB 12 +#define DMA_CCR5_PL_LOW 0x0 +#define DMA_CCR5_PL_MEDIUM 0x1 +#define DMA_CCR5_PL_HIGH 0x2 +#define DMA_CCR5_PL_VERY_HIGH 0x3 + +/* MSIZE[11:10]: Memory size */ +#define DMA_CCR5_MSIZE_LSB 10 +#define DMA_CCR5_MSIZE_8BIT 0x0 +#define DMA_CCR5_MSIZE_16BIT 0x1 +#define DMA_CCR5_MSIZE_32BIT 0x2 + +/* PSIZE[9:8]: Peripheral size */ +#define DMA_CCR5_PSIZE_LSB 8 +#define DMA_CCR5_PSIZE_8BIT 0x0 +#define DMA_CCR5_PSIZE_16BIT 0x1 +#define DMA_CCR5_PSIZE_32BIT 0x2 + +/* MINC: Memory increment mode */ +#define DMA_CCR5_MINC (1 << 7) + +/* PINC: Peripheral increment mode */ +#define DMA_CCR5_PINC (1 << 6) + +/* CIRC: Circular mode */ +#define DMA_CCR5_CIRC (1 << 5) + +/* DIR: Data transfer direction */ +#define DMA_CCR5_DIR (1 << 4) + +/* TEIE: Transfer error interrupt enable */ +#define DMA_CCR5_TEIE (1 << 3) + +/* HTIE: Half transfer interrupt enable */ +#define DMA_CCR5_HTIE (1 << 2) + +/* TCIE: Transfer complete interrupt enable */ +#define DMA_CCR5_TCIE (1 << 1) + +/* EN: Channel enable */ +#define DMA_CCR5_EN (1 << 0) + +/* --- DMA_CCR6 values ----------------------------------------------------- */ + +/* MEM2MEM: Memory to memory mode */ +#define DMA_CCR6_MEM2MEM (1 << 14) + +/* PL[13:12]: Channel priority level */ +#define DMA_CCR6_PL_LSB 12 +#define DMA_CCR6_PL_LOW 0x0 +#define DMA_CCR6_PL_MEDIUM 0x1 +#define DMA_CCR6_PL_HIGH 0x2 +#define DMA_CCR6_PL_VERY_HIGH 0x3 + +/* MSIZE[11:10]: Memory size */ +#define DMA_CCR6_MSIZE_LSB 10 +#define DMA_CCR6_MSIZE_8BIT 0x0 +#define DMA_CCR6_MSIZE_16BIT 0x1 +#define DMA_CCR6_MSIZE_32BIT 0x2 + +/* PSIZE[9:8]: Peripheral size */ +#define DMA_CCR6_PSIZE_LSB 8 +#define DMA_CCR6_PSIZE_8BIT 0x0 +#define DMA_CCR6_PSIZE_16BIT 0x1 +#define DMA_CCR6_PSIZE_32BIT 0x2 + +/* MINC: Memory increment mode */ +#define DMA_CCR6_MINC (1 << 7) + +/* PINC: Peripheral increment mode */ +#define DMA_CCR6_PINC (1 << 6) + +/* CIRC: Circular mode */ +#define DMA_CCR6_CIRC (1 << 5) + +/* DIR: Data transfer direction */ +#define DMA_CCR6_DIR (1 << 4) + +/* TEIE: Transfer error interrupt enable */ +#define DMA_CCR6_TEIE (1 << 3) + +/* HTIE: Half transfer interrupt enable */ +#define DMA_CCR6_HTIE (1 << 2) + +/* TCIE: Transfer complete interrupt enable */ +#define DMA_CCR6_TCIE (1 << 1) + +/* EN: Channel enable */ +#define DMA_CCR6_EN (1 << 0) + +/* --- DMA_CCR7 values ----------------------------------------------------- */ + +/* MEM2MEM: Memory to memory mode */ +#define DMA_CCR7_MEM2MEM (1 << 14) + +/* PL[13:12]: Channel priority level */ +#define DMA_CCR7_PL_LSB 12 +#define DMA_CCR7_PL_LOW 0x0 +#define DMA_CCR7_PL_MEDIUM 0x1 +#define DMA_CCR7_PL_HIGH 0x2 +#define DMA_CCR7_PL_VERY_HIGH 0x3 + +/* MSIZE[11:10]: Memory size */ +#define DMA_CCR7_MSIZE_LSB 10 +#define DMA_CCR7_MSIZE_8BIT 0x0 +#define DMA_CCR7_MSIZE_16BIT 0x1 +#define DMA_CCR7_MSIZE_32BIT 0x2 + +/* PSIZE[9:8]: Peripheral size */ +#define DMA_CCR7_PSIZE_LSB 8 +#define DMA_CCR7_PSIZE_8BIT 0x0 +#define DMA_CCR7_PSIZE_16BIT 0x1 +#define DMA_CCR7_PSIZE_32BIT 0x2 + +/* MINC: Memory increment mode */ +#define DMA_CCR7_MINC (1 << 7) + +/* PINC: Peripheral increment mode */ +#define DMA_CCR7_PINC (1 << 6) + +/* CIRC: Circular mode */ +#define DMA_CCR7_CIRC (1 << 5) + +/* DIR: Data transfer direction */ +#define DMA_CCR7_DIR (1 << 4) + +/* TEIE: Transfer error interrupt enable */ +#define DMA_CCR7_TEIE (1 << 3) + +/* HTIE: Half transfer interrupt enable */ +#define DMA_CCR7_HTIE (1 << 2) + +/* TCIE: Transfer complete interrupt enable */ +#define DMA_CCR7_TCIE (1 << 1) + +/* EN: Channel enable */ +#define DMA_CCR7_EN (1 << 0) + +/* --- DMA_CCRx generic values --------------------------------------------- */ + +/* MEM2MEM: Memory to memory mode */ +#define DMA_CCR_MEM2MEM (1 << 14) + +/* PL[13:12]: Channel priority level */ +#define DMA_CCR_PL_LSB 12 +#define DMA_CCR_PL_LOW 0x0 +#define DMA_CCR_PL_MEDIUM 0x1 +#define DMA_CCR_PL_HIGH 0x2 +#define DMA_CCR_PL_VERY_HIGH 0x3 + +/* MSIZE[11:10]: Memory size */ +#define DMA_CCR_MSIZE_LSB 10 +#define DMA_CCR_MSIZE_8BIT 0x0 +#define DMA_CCR_MSIZE_16BIT 0x1 +#define DMA_CCR_MSIZE_32BIT 0x2 + +/* PSIZE[9:8]: Peripheral size */ +#define DMA_CCR_PSIZE_LSB 8 +#define DMA_CCR_PSIZE_8BIT 0x0 +#define DMA_CCR_PSIZE_16BIT 0x1 +#define DMA_CCR_PSIZE_32BIT 0x2 + +/* MINC: Memory increment mode */ +#define DMA_CCR_MINC (1 << 7) + +/* PINC: Peripheral increment mode */ +#define DMA_CCR_PINC (1 << 6) + +/* CIRC: Circular mode */ +#define DMA_CCR_CIRC (1 << 5) + +/* DIR: Data transfer direction */ +#define DMA_CCR_DIR (1 << 4) + +/* TEIE: Transfer error interrupt enable */ +#define DMA_CCR_TEIE (1 << 3) + +/* HTIE: Half transfer interrupt enable */ +#define DMA_CCR_HTIE (1 << 2) + +/* TCIE: Transfer complete interrupt enable */ +#define DMA_CCR_TCIE (1 << 1) + +/* EN: Channel enable */ +#define DMA_CCR_EN (1 << 0) + +/* --- DMA_CNDTRx values --------------------------------------------------- */ + +/* NDT[15:0]: Number of data to transfer */ + +/* --- DMA_CPARx values ---------------------------------------------------- */ + +/* PA[31:0]: Peripheral address */ + +/* --- DMA_CMARx values ---------------------------------------------------- */ + +/* MA[31:0]: Memory address */ + +/* --- Generic values ------------------------------------------------------ */ + +#define DMA_CHANNEL1 1 +#define DMA_CHANNEL2 2 +#define DMA_CHANNEL3 3 +#define DMA_CHANNEL4 4 +#define DMA_CHANNEL5 5 +#define DMA_CHANNEL6 6 +#define DMA_CHANNEL7 7 + +/* --- function prototypes ------------------------------------------------- */ + +void dma_enable_mem2mem_mode(u32 dma, u8 channel); +void dma_set_priority(u32 dma, u8 channel, u8 prio); +void dma_set_memory_size(u32 dma, u8 channel, u8 mem_size); +void dma_set_peripheral_size(u32 dma, u8 channel, u8 peripheral_size); +void dma_enable_memory_increment_mode(u32 dma, u8 channel); +void dma_enable_peripheral_increment_mode(u32 dma, u8 channel); +void dma_enable_circular_mode(u32 dma, u8 channel); +void dma_set_read_from_peripheral(u32 dma, u8 channel); +void dma_set_read_from_memory(u32 dma, u8 channel); +void dma_enable_transfer_error_interrupt(u32 dma, u8 channel); +void dma_disable_transfer_error_interrupt(u32 dma, u8 channel); +void dma_enable_half_transfer_interrupt(u32 dma, u8 channel); +void dma_disable_half_transfer_interrupt(u32 dma, u8 channel); +void dma_enable_transfer_complete_interrupt(u32 dma, u8 channel); +void dma_disable_transfer_complete_interrupt(u32 dma, u8 channel); +void dma_enable_channel(u32 dma, u8 channel); +void dma_disable_channel(u32 dma, u8 channel); +void dma_set_peripheral_address(u32 dma, u8 channel, u32 address); +void dma_set_memory_address(u32 dma, u8 channel, u32 address); +void dma_set_number_of_data(u32 dma, u8 channel, u16 number); + +#endif diff --git a/include/libopencm3/stm32f1/ethernet.h b/include/libopencm3/stm32f1/ethernet.h new file mode 100644 index 0000000..3d7f1ee --- /dev/null +++ b/include/libopencm3/stm32f1/ethernet.h @@ -0,0 +1,203 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Gareth McMullin + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_ETHERNET_H +#define LIBOPENCM3_ETHERNET_H + +#include +#include + +/* Ethernet MAC registers */ +#define ETH_MACCR MMIO32(ETHERNET_BASE + 0x00) +#define ETH_MACFFR MMIO32(ETHERNET_BASE + 0x04) +#define ETH_MACHTHR MMIO32(ETHERNET_BASE + 0x08) +#define ETH_MACHTLR MMIO32(ETHERNET_BASE + 0x0C) +#define ETH_MACMIIAR MMIO32(ETHERNET_BASE + 0x10) +#define ETH_MACMIIDR MMIO32(ETHERNET_BASE + 0x14) +#define ETH_MACFCR MMIO32(ETHERNET_BASE + 0x18) +#define ETH_MACVLANTR MMIO32(ETHERNET_BASE + 0x1C) +#define ETH_MACRWUFFR MMIO32(ETHERNET_BASE + 0x28) +#define ETH_MACPMTCSR MMIO32(ETHERNET_BASE + 0x2C) +#define ETH_MACSR MMIO32(ETHERNET_BASE + 0x38) +#define ETH_MACIMR MMIO32(ETHERNET_BASE + 0x3C) +#define ETH_MACA0HR MMIO32(ETHERNET_BASE + 0x40) +#define ETH_MACA0LR MMIO32(ETHERNET_BASE + 0x44) +#define ETH_MACA1HR MMIO32(ETHERNET_BASE + 0x48) +#define ETH_MACA1LR MMIO32(ETHERNET_BASE + 0x4C) +#define ETH_MACA2HR MMIO32(ETHERNET_BASE + 0x50) +#define ETH_MACA2LR MMIO32(ETHERNET_BASE + 0x54) +#define ETH_MACA3HR MMIO32(ETHERNET_BASE + 0x58) +#define ETH_MACA3LR MMIO32(ETHERNET_BASE + 0x5C) + +/* Ethernet MMC registers */ +#define ETH_MMCCR MMIO32(ETHERNET_BASE + 0x100) +#define ETH_MMCRIR MMIO32(ETHERNET_BASE + 0x104) +#define ETH_MMCTIR MMIO32(ETHERNET_BASE + 0x108) +#define ETH_MMCRIMR MMIO32(ETHERNET_BASE + 0x10C) +#define ETH_MMCTIMR MMIO32(ETHERNET_BASE + 0x110) +#define ETH_MMCTGFSCCR MMIO32(ETHERNET_BASE + 0x14C) +#define ETH_MMCTGFMSCCR MMIO32(ETHERNET_BASE + 0x150) +#define ETH_MMCTGFCR MMIO32(ETHERNET_BASE + 0x168) +#define ETH_MMCRFCECR MMIO32(ETHERNET_BASE + 0x194) +#define ETH_MMCRFAECR MMIO32(ETHERNET_BASE + 0x198) +#define ETH_MMCRGUFCR MMIO32(ETHERNET_BASE + 0x1C4) + +/* Ethrenet IEEE 1588 time stamp registers */ +#define ETH_PTPTSCR MMIO32(ETHERNET_BASE + 0x700) +#define ETH_PTPSSIR MMIO32(ETHERNET_BASE + 0x704) +#define ETH_PTPTSHR MMIO32(ETHERNET_BASE + 0x708) +#define ETH_PTPTSLR MMIO32(ETHERNET_BASE + 0x70C) +#define ETH_PTPTSHUR MMIO32(ETHERNET_BASE + 0x710) +#define ETH_PTPTSLUR MMIO32(ETHERNET_BASE + 0x714) +#define ETH_PTPTSAR MMIO32(ETHERNET_BASE + 0x718) +#define ETH_PTPTTHR MMIO32(ETHERNET_BASE + 0x71C) +#define ETH_PTPTTLR MMIO32(ETHERNET_BASE + 0x720) + +/* Ethernet DMA registers */ +#define ETH_DMABMR MMIO32(ETHERNET_BASE + 0x1000) +#define ETH_DMATPDR MMIO32(ETHERNET_BASE + 0x1004) +#define ETH_DMARPDR MMIO32(ETHERNET_BASE + 0x1008) +#define ETH_DMARDLAR MMIO32(ETHERNET_BASE + 0x100C) +#define ETH_DMATDLAR MMIO32(ETHERNET_BASE + 0x1010) +#define ETH_DMATDLAR MMIO32(ETHERNET_BASE + 0x1010) +#define ETH_DMASR MMIO32(ETHERNET_BASE + 0x1014) +#define ETH_DMAOMR MMIO32(ETHERNET_BASE + 0x1018) +#define ETH_DMAIER MMIO32(ETHERNET_BASE + 0x101C) +#define ETH_DMAMFBOCR MMIO32(ETHERNET_BASE + 0x1020) +#define ETH_DMACHTDR MMIO32(ETHERNET_BASE + 0x1048) +#define ETH_DMACHRDR MMIO32(ETHERNET_BASE + 0x104C) +#define ETH_DMACHTBAR MMIO32(ETHERNET_BASE + 0x1050) +#define ETH_DMACHRBAR MMIO32(ETHERNET_BASE + 0x1054) + +/* Ethernet MAC Register bit definitions */ +/* Ethernet MAC configuration register ETH_MACCR bits */ +#define ETH_MACCR_RE 0x00000004 +#define ETH_MACCR_TE 0x00000008 +#define ETH_MACCR_DC 0x00000010 +#define ETH_MACCR_BL 0x00000060 +#define ETH_MACCR_APCS 0x00000080 +#define ETH_MACCR_RD 0x00000200 +#define ETH_MACCR_IPCO 0x00000400 +#define ETH_MACCR_DM 0x00000800 +#define ETH_MACCR_LM 0x00001000 +#define ETH_MACCR_ROD 0x00002000 +#define ETH_MACCR_FES 0x00004000 +#define ETH_MACCR_CSD 0x00010000 +#define ETH_MACCR_IFG 0x000E0000 +#define ETH_MACCR_JD 0x00400000 +#define ETH_MACCR_WD 0x00800000 + +/* Ethernet MAC frame filter register ETH_MACFFR bits */ +#define ETH_MACFFR_PM 0x00000001 +#define ETH_MACFFR_HU 0x00000002 +#define ETH_MACFFR_HM 0x00000004 +#define ETH_MACFFR_DAIF 0x00000008 +#define ETH_MACFFR_PAM 0x00000010 +#define ETH_MACFFR_BFD 0x00000020 +#define ETH_MACFFR_PCF 0x000000C0 +#define ETH_MACFFR_SAIF 0x00000100 +#define ETH_MACFFR_SAF 0x00000200 +#define ETH_MACFFR_HPF 0x00000400 +#define ETH_MACFFR_PA 0x80000000 + +/* Ethernet MAC MII address register ETH_MACMIIAR bits */ +#define ETH_MACMIIAR_MB 0x0001 +#define ETH_MACMIIAR_MW 0x0002 +/* Clock Range for MDC frequency */ +#define ETH_MACMIIAR_CR_MASK 0x001C +#define ETH_MACMIIAR_CR_HCLK_DIV_42 0x0000 /* For HCLK 60-72 MHz */ +#define ETH_MACMIIAR_CR_HCLK_DIV_16 0x0008 /* For HCLK 20-35 MHz */ +#define ETH_MACMIIAR_CR_HCLK_DIV_24 0x000C /* For HCLK 35-60 MHz */ +#define ETH_MACMIIAR_MR 0x07C0 +#define ETH_MACMIIAR_PA 0xF800 + +/* Ethernet MAC flow control register ETH_MACFCR bits */ +#define ETH_MACFCR_FCB 0x00000001 +#define ETH_MACFCR_BPA 0x00000001 +#define ETH_MACFCR_TFCE 0x00000002 +#define ETH_MACFCR_RFCE 0x00000004 +#define ETH_MACFCR_UPFD 0x00000008 +#define ETH_MACFCR_PLT 0x00000030 +#define ETH_MACFCR_ZQPD 0x00000080 +#define ETH_MACFCR_PT 0xFFFF0000 + +/* Ethernet MAC interrupt status regster ETH_MACSR bits */ +#define ETH_MACSR_PMTS 0x0008 +#define ETH_MACSR_MMCS 0x0010 +#define ETH_MACSR_MMCRS 0x0020 +#define ETH_MACSR_MMCTS 0x0040 +#define ETH_MACSR_TSTS 0x0200 + +/* Ethernet MAC interrupt mask regster ETH_MACIMR bits */ +#define ETH_MACIMR_PMTIM 0x0008 +#define ETH_MACIMR_TSTIM 0x0200 + +/* Ethernet DMA Register bit definitions */ +/* Ethernet DMA bus mode register ETH_DMABMR bits */ +#define ETH_DMABMR_SR 0x00000001 +#define ETH_DMABMR_DA 0x00000002 +#define ETH_DMABMR_DSL_MASK 0x0000007C +#define ETH_DMABMR_PBL_MASK 0x00003F00 +#define ETH_DMABMR_RTPR_MASK 0x0000C000 +#define ETH_DMABMR_RTPR_1TO1 0x00000000 +#define ETH_DMABMR_RTPR_2TO1 0x00004000 +#define ETH_DMABMR_RTPR_3TO1 0x00008000 +#define ETH_DMABMR_RTPR_4TO1 0x0000C000 +#define ETH_DMABMR_FB 0x00010000 +#define ETH_DMABMR_RDP_MASK 0x007E0000 +#define ETH_DMABMR_USP 0x00800000 +#define ETH_DMABMR_FPM 0x01000000 +#define ETH_DMABMR_AAB 0x02000000 + +/* Ethernet DMA operation mode register ETH_DMAOMR bits */ +#define ETH_DMAOMR_SR 0x00000002 +#define ETH_DMAOMR_OSF 0x00000004 +#define ETH_DMAOMR_RTC_MASK 0x00000018 +#define ETH_DMAOMR_RTC_64 0x00000000 +#define ETH_DMAOMR_RTC_32 0x00000008 +#define ETH_DMAOMR_RTC_96 0x00000010 +#define ETH_DMAOMR_RTC_128 0x00000018 +#define ETH_DMAOMR_FUGF 0x00000040 +#define ETH_DMAOMR_FEF 0x00000080 +#define ETH_DMAOMR_ST 0x00002000 +#define ETH_DMAOMR_TTC_MASK 0x0001C000 +#define ETH_DMAOMR_FTF 0x00100000 +#define ETH_DMAOMR_TSF 0x00200000 +#define ETH_DMAOMR_DFRF 0x01000000 +#define ETH_DMAOMR_RSF 0x02000000 +#define ETH_DMAOMR_DTCEFD 0x04000000 + +/* Ethernet DMA interrupt enable register ETH_DMAIER bits */ +#define ETH_DMAIER_TIE 0x00000001 +#define ETH_DMAIER_TPSIE 0x00000002 +#define ETH_DMAIER_TBUIE 0x00000004 +#define ETH_DMAIER_TJTIE 0x00000008 +#define ETH_DMAIER_ROIE 0x00000010 +#define ETH_DMAIER_TUIE 0x00000020 +#define ETH_DMAIER_RIE 0x00000040 +#define ETH_DMAIER_RBUIE 0x00000080 +#define ETH_DMAIER_RPSIE 0x00000100 +#define ETH_DMAIER_RWTIE 0x00000200 +#define ETH_DMAIER_ETIE 0x00000400 +#define ETH_DMAIER_FBEIE 0x00002000 +#define ETH_DMAIER_ERIE 0x00004000 +#define ETH_DMAIER_AISE 0x00008000 +#define ETH_DMAIER_NSIE 0x00010000 + +#endif diff --git a/include/libopencm3/stm32f1/exti.h b/include/libopencm3/stm32f1/exti.h new file mode 100644 index 0000000..19ab547 --- /dev/null +++ b/include/libopencm3/stm32f1/exti.h @@ -0,0 +1,70 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Mark Butler + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_EXTI_H +#define LIBOPENCM3_EXTI_H + +#include +#include + +/* --- EXTI registers ------------------------------------------------------ */ + +#define EXTI_IMR MMIO32(EXTI_BASE + 0x00) +#define EXTI_EMR MMIO32(EXTI_BASE + 0x04) +#define EXTI_RTSR MMIO32(EXTI_BASE + 0x08) +#define EXTI_FTSR MMIO32(EXTI_BASE + 0x0c) +#define EXTI_SWIER MMIO32(EXTI_BASE + 0x10) +#define EXTI_PR MMIO32(EXTI_BASE + 0x14) + +/* EXTI number definitions */ +#define EXTI0 (1 << 0) +#define EXTI1 (1 << 1) +#define EXTI2 (1 << 2) +#define EXTI3 (1 << 3) +#define EXTI4 (1 << 4) +#define EXTI5 (1 << 5) +#define EXTI6 (1 << 6) +#define EXTI7 (1 << 7) +#define EXTI8 (1 << 8) +#define EXTI9 (1 << 9) +#define EXTI10 (1 << 10) +#define EXTI11 (1 << 11) +#define EXTI12 (1 << 12) +#define EXTI13 (1 << 13) +#define EXTI14 (1 << 14) +#define EXTI15 (1 << 15) +#define EXTI16 (1 << 16) +#define EXTI17 (1 << 17) +#define EXTI18 (1 << 18) +#define EXTI19 (1 << 19) + +/* Trigger types */ +typedef enum trigger_e { + EXTI_TRIGGER_RISING, + EXTI_TRIGGER_FALLING, + EXTI_TRIGGER_BOTH, +} exti_trigger_type; + +void exti_set_trigger(u32 extis, exti_trigger_type trig); +void exti_enable_request(u32 extis); +void exti_disable_request(u32 extis); +void exti_reset_request(u32 extis); +void exti_select_source(u32 exti, u32 gpioport); + +#endif diff --git a/include/libopencm3/stm32f1/flash.h b/include/libopencm3/stm32f1/flash.h new file mode 100644 index 0000000..f9b2aa9 --- /dev/null +++ b/include/libopencm3/stm32f1/flash.h @@ -0,0 +1,113 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * Copyright (C) 2010 Mark Butler + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* + * For details see: + * PM0042 Programming manual: STM32F10xxx Flash programming + * October 2009, Doc ID 13259 Rev 7 + * http://www.st.com/stonline/products/literature/pm/13259.pdf + */ + +#ifndef LIBOPENCM3_FLASH_H +#define LIBOPENCM3_FLASH_H + +#include +#include + +/* --- FLASH registers ----------------------------------------------------- */ + +#define FLASH_ACR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x00) +#define FLASH_KEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x04) +#define FLASH_OPTKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x08) +#define FLASH_SR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x0C) +#define FLASH_CR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x10) +#define FLASH_AR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14) +#define FLASH_OBR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x1C) +#define FLASH_WRPR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x20) + +/* --- FLASH_ACR values ---------------------------------------------------- */ + +#define FLASH_PRFTBS (1 << 5) +#define FLASH_PRFTBE (1 << 4) +#define FLASH_HLFCYA (1 << 3) +#define FLASH_LATENCY_0WS 0x00 +#define FLASH_LATENCY_1WS 0x01 +#define FLASH_LATENCY_2WS 0x02 + +/* --- FLASH_SR values ----------------------------------------------------- */ + +#define FLASH_EOP (1 << 5) +#define FLASH_WRPRTERR (1 << 4) +#define FLASH_PGERR (1 << 2) +#define FLASH_BSY (1 << 0) + +/* --- FLASH_CR values ----------------------------------------------------- */ + +#define FLASH_EOPIE (1 << 12) +#define FLASH_ERRIE (1 << 10) +#define FLASH_OPTWRE (1 << 9) +#define FLASH_LOCK (1 << 7) +#define FLASH_STRT (1 << 6) +#define FLASH_OPTER (1 << 5) +#define FLASH_OPTPG (1 << 4) +#define FLASH_MER (1 << 2) +#define FLASH_PER (1 << 1) +#define FLASH_PG (1 << 0) + +/* --- FLASH_OBR values ---------------------------------------------------- */ + +/* FLASH_OBR[25:18]: Data1 */ +/* FLASH_OBR[17:10]: Data0 */ +#define FLASH_NRST_STDBY (1 << 4) +#define FLASH_NRST_STOP (1 << 3) +#define FLASH_WDG_SW (1 << 2) +#define FLASH_RDPRT (1 << 1) +#define FLASH_OPTERR (1 << 0) + +/* --- FLASH Keys -----------------------------------------------------------*/ + +#define RDP_KEY ((u16)0x00a5) +#define FLASH_KEY1 ((u32)0x45670123) +#define FLASH_KEY2 ((u32)0xcdef89ab) + +/* --- Function prototypes ------------------------------------------------- */ + +void flash_prefetch_buffer_enable(void); +void flash_prefetch_buffer_disable(void); +void flash_halfcycle_enable(void); +void flash_halfcycle_disable(void); +void flash_set_ws(u32 ws); +void flash_unlock(void); +void flash_lock(void); +void flash_clear_pgerr_flag(void); +void flash_clear_eop_flag(void); +void flash_clear_wrprterr_flag(void); +void flash_clear_bsy_flag(void); +void flash_clear_status_flags(void); +void flash_unlock_option_bytes(void); +void flash_erase_all_pages(void); +void flash_erase_page(u32 page_address); +void flash_program_word(u32 address, u32 data); +void flash_program_half_word(u32 address, u16 data); +void flash_wait_for_last_operation(void); +void flash_erase_option_bytes(void); +void flash_program_option_bytes(u32 address, u16 data); + +#endif diff --git a/include/libopencm3/stm32f1/fsmc.h b/include/libopencm3/stm32f1/fsmc.h new file mode 100644 index 0000000..1d318e3 --- /dev/null +++ b/include/libopencm3/stm32f1/fsmc.h @@ -0,0 +1,284 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_FSMC_H +#define LIBOPENCM3_FSMC_H + +#include +#include + +/* --- Convenience macros -------------------------------------------------- */ + +/* TODO: Move to memorymap.h? */ +#define FSMC_BASE 0xa0000000 + +#define FSMC_BANK1_BASE 0x60000000 /* NOR / PSRAM */ +#define FSMC_BANK2_BASE 0x70000000 /* NAND flash */ +#define FSMC_BANK3_BASE 0x80000000 /* NAND flash */ +#define FSMC_BANK4_BASE 0x90000000 /* PC card */ + +/* --- FSMC registers ------------------------------------------------------ */ + +/* SRAM/NOR-Flash chip-select control registers 1..4 (FSMC_BCRx) */ +#define FSMC_BCR(x) MMIO32(FSMC_BASE + 0x00 + 8 * x) +#define FSMC_BCR1 FSMC_BCR(0) +#define FSMC_BCR2 FSMC_BCR(1) +#define FSMC_BCR3 FSMC_BCR(2) +#define FSMC_BCR4 FSMC_BCR(3) + +/* SRAM/NOR-Flash chip-select timing registers 1..4 (FSMC_BTRx) */ +#define FSMC_BTR(x) MMIO32(FSMC_BASE + 0x04 + 8 * x) +#define FSMC_BTR1 FSMC_BTR(0) +#define FSMC_BTR2 FSMC_BTR(1) +#define FSMC_BTR3 FSMC_BTR(2) +#define FSMC_BTR4 FSMC_BTR(3) + +/* SRAM/NOR-Flash write timing registers 1..4 (FSMC_BWTRx) */ +#define FSMC_BWTR(x) MMIO32(FSMC_BASE + 0x104 + 8 * x) +#define FSMC_BWTR1 FSMC_BWTR(0) +#define FSMC_BWTR2 FSMC_BWTR(1) +#define FSMC_BWTR3 FSMC_BWTR(2) +#define FSMC_BWTR4 FSMC_BWTR(3) + +/* PC Card/NAND Flash control registers 2..4 (FSMC_PCRx) */ +#define FSMC_PCR(x) MMIO32(FSMC_BASE + 0x40 + 0x20 * x) +#define FSMC_PCR2 FSMC_PCR(1) +#define FSMC_PCR3 FSMC_PCR(2) +#define FSMC_PCR4 FSMC_PCR(3) + +/* FIFO status and interrupt registers 2..4 (FSMC_SRx) */ +#define FSMC_SR(x) MMIO32(FSMC_BASE + 0x44 + 0x20 * x) +#define FSMC_SR2 FSMC_SR(1) +#define FSMC_SR3 FSMC_SR(2) +#define FSMC_SR4 FSMC_SR(3) + +/* Common memory space timing registers 2..4 (FSMC_PMEMx) */ +#define FSMC_PMEM(x) MMIO32(FSMC_BASE + 0x48 + 0x20 * x) +#define FSMC_PMEM2 FSMC_PMEM(1) +#define FSMC_PMEM3 FSMC_PMEM(2) +#define FSMC_PMEM4 FSMC_PMEM(3) + +/* Attribute memory space timing registers 2..4 (FSMC_PATTx) */ +#define FSMC_PATT(x) MMIO32(FSMC_BASE + 0x4c + 0x20 * x) +#define FSMC_PATT2 FSMC_PATT(1) +#define FSMC_PATT3 FSMC_PATT(2) +#define FSMC_PATT4 FSMC_PATT(3) + +/* I/O space timing register 4 (FSMC_PIO4) */ +#define FSMC_PIO4 MMIO32(FSMC_BASE + 0xb0) + +/* ECC result registers 2/3 (FSMC_ECCRx) */ +#define FSMC_ECCR(x) MMIO32(FSMC_BASE + 0x54 + 0x20 * x) +#define FSMC_ECCR2 FSMC_ECCR(1) +#define FSMC_ECCR3 FSMC_ECCR(2) + +/* --- FSMC_BCRx values ---------------------------------------------------- */ + +/* CBURSTRW: Write burst enable */ +#define FSMC_BCR_CBURSTRW (1 << 19) + +/* Bits 18..16: Reserved. */ + +/* ASYNCWAIT: Wait signal during asynchronous transfers */ +#define FSMC_BCR_ASYNCWAIT (1 << 15) + +/* EXTMOD: Extended mode enable */ +#define FSMC_BCR_EXTMOD (1 << 14) + +/* WAITEN: Wait enable bit */ +#define FSMC_BCR_WAITEN (1 << 13) + +/* WREN: Write enable bit */ +#define FSMC_BCR_WREN (1 << 12) + +/* WAITCFG: Wait timing configuration */ +#define FSMC_BCR_WAITCFG (1 << 11) + +/* WRAPMOD: Wrapped burst mode support */ +#define FSMC_BCR_WRAPMOD (1 << 10) + +/* WAITPOL: Wait signal polarity bit */ +#define FSMC_BCR_WAITPOL (1 << 9) + +/* BURSTEN: Burst enable bit */ +#define FSMC_BCR_BURSTEN (1 << 8) + +/* Bit 7: Reserved. */ + +/* FACCEN: Flash access enable */ +#define FSMC_BCR_FACCEN (1 << 6) + +/* MWID[5:4]: Memory databus width */ +#define FSMC_BCR_MWID (1 << 4) + +/* MTYP[3:2]: Memory type */ +#define FSMC_BCR_MTYP (1 << 2) + +/* MUXEN: Address/data multiplexing enable bit */ +#define FSMC_BCR_MUXEN (1 << 1) + +/* MBKEN: Memory bank enable bit */ +#define FSMC_BCR_MBKEN (1 << 0) + +/* --- FSMC_BTRx values ---------------------------------------------------- */ + +/* ACCMOD[29:28]: Access mode */ +#define FSMC_BTR_ACCMOD (1 << 28) + +/* DATLAT[27:24]: Data latency (for synchronous burst NOR flash) */ +#define FSMC_BTR_DATLAT (1 << 24) + +/* CLKDIV[23:20]: Clock divide ratio (for CLK signal) */ +#define FSMC_BTR_CLKDIV (1 << 20) + +/* BUSTURN[19:16]: Bus turnaround phase duration */ +#define FSMC_BTR_BUSTURN (1 << 16) + +/* DATAST[15:8]: Data-phase duration */ +#define FSMC_BTR_DATAST (1 << 8) + +/* ADDHLD[7:4]: Address-hold phase duration */ +#define FSMC_BTR_ADDHLD (1 << 4) + +/* ADDSET[3:0]: Address setup phase duration */ +#define FSMC_BTR_ADDSET (1 << 0) + +/* --- FSMC_BWTRx values --------------------------------------------------- */ + +/* ACCMOD[29:28]: Access mode */ +#define FSMC_BWTR_ACCMOD (1 << 28) + +/* DATLAT[27:24]: Data latency (for synchronous burst NOR Flash) */ +#define FSMC_BWTR_DATLAT (1 << 24) + +/* CLKDIV[23:20]: Clock divide ratio (for CLK signal) */ +#define FSMC_BWTR_CLKDIV (1 << 20) + +/* Bits 19..16: Reserved. */ + +/* DATAST[15:8]: Data-phase duration */ +#define FSMC_BWTR_DATAST (1 << 8) + +/* ADDHLD[7:4]: Address-hold phase duration */ +#define FSMC_BWTR_ADDHLD (1 << 4) + +/* ADDSET[3:0]: Address setup phase duration */ +#define FSMC_BWTR_ADDSET (1 << 0) + +/* --- FSMC_PCRx values ---------------------------------------------------- */ + +/* ECCPS[19:17]: ECC page size */ +#define FSMC_PCR_ECCPS (1 << 17) + +/* TAR[16:13]: ALE to RE delay */ +#define FSMC_PCR_TAR (1 << 13) + +/* TCLR[12:9]: CLE to RE delay */ +#define FSMC_PCR_TCLR (1 << 9) + +/* Bits 8..7: Reserved. */ + +/* ECCEN: ECC computation logic enable bit */ +#define FSMC_PCR_ECCEN (1 << 6) + +/* PWID[5:4]: Databus width */ +#define FSMC_PCR_PWID (1 << 4) + +/* PTYP: Memory type */ +#define FSMC_PCR_PTYP (1 << 3) + +/* PBKEN: PC Card/NAND Flash memory bank enable bit */ +#define FSMC_PCR_PBKEN (1 << 2) + +/* PWAITEN: Wait feature enable bit */ +#define FSMC_PCR_PWAITEN (1 << 1) + +/* Bit 0: Reserved. */ + +/* --- FSMC_SRx values ----------------------------------------------------- */ + +/* FEMPT: FIFO empty */ +#define FSMC_SR_FEMPT (1 << 6) + +/* IFEN: Interrupt falling edge detection enable bit */ +#define FSMC_SR_IFEN (1 << 5) + +/* ILEN: Interrupt high-level detection enable bit */ +#define FSMC_SR_ILEN (1 << 4) + +/* IREN: Interrupt rising edge detection enable bit */ +#define FSMC_SR_IREN (1 << 3) + +/* IFS: Interrupt falling edge status */ +#define FSMC_SR_IFS (1 << 2) + +/* ILS: Interrupt high-level status */ +#define FSMC_SR_ILS (1 << 1) + +/* IRS: Interrupt rising edge status */ +#define FSMC_SR_IRS (1 << 0) + +/* --- FSMC_PMEMx values --------------------------------------------------- */ + +/* MEMHIZx[31:24]: Common memory x databus HiZ time */ +#define FSMC_PMEM_MEMHIZX (1 << 24) + +/* MEMHOLDx[23:16]: Common memory x hold time */ +#define FSMC_PMEM_MEMHOLDX (1 << 16) + +/* MEMWAITx[15:8]: Common memory x wait time */ +#define FSMC_PMEM_MEMHOLDX (1 << 8) + +/* MEMSETx[7:0]: Common memory x setup time */ +#define FSMC_PMEM_MEMSETX (1 << 0) + +/* --- FSMC_PATTx values --------------------------------------------------- */ + +/* ATTHIZx[31:24]: Attribute memory x databus HiZ time */ +#define FSMC_PATT_ATTHIZX (1 << 24) + +/* ATTHOLDx[23:16]: Attribute memory x hold time */ +#define FSMC_PATT_ATTHOLDX (1 << 16) + +/* ATTWAITx[15:8]: Attribute memory x wait time */ +#define FSMC_PATT_ATTWAITX (1 << 8) + +/* ATTSETx[7:0]: Attribute memory x setup time */ +#define FSMC_PATT_ATTSETX (1 << 0) + +/* --- FSMC_PIO4 values ---------------------------------------------------- */ + +/* IOHIZx[31:24]: I/O x databus HiZ time */ +#define FSMC_PIO4_IOHIZX (1 << 24) + +/* IOHOLDx[23:16]: I/O x hold time */ +#define FSMC_PIO4_IOHOLDX (1 << 16) + +/* IOWAITx[15:8]: I/O x wait time */ +#define FSMC_PIO4_IOWAITX (1 << 8) + +/* IOSETx[7:0]: I/O x setup time */ +#define FSMC_PIO4_IOSETX (1 << 0) + +/* --- FSMC_ECCRx values --------------------------------------------------- */ + +/* ECCx[31:0]: ECC result */ +#define FSMC_ECCR_ECCX (1 << 0) + +#endif diff --git a/include/libopencm3/stm32f1/gpio.h b/include/libopencm3/stm32f1/gpio.h new file mode 100644 index 0000000..f1463a3 --- /dev/null +++ b/include/libopencm3/stm32f1/gpio.h @@ -0,0 +1,555 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_GPIO_H +#define LIBOPENCM3_GPIO_H + +#include +#include + +/* --- Convenience macros -------------------------------------------------- */ + +/* GPIO port base addresses (for convenience) */ +#define GPIOA GPIO_PORT_A_BASE +#define GPIOB GPIO_PORT_B_BASE +#define GPIOC GPIO_PORT_C_BASE +#define GPIOD GPIO_PORT_D_BASE +#define GPIOE GPIO_PORT_E_BASE +#define GPIOF GPIO_PORT_F_BASE +#define GPIOG GPIO_PORT_G_BASE + +/* GPIO number definitions (for convenience) */ +#define GPIO0 (1 << 0) +#define GPIO1 (1 << 1) +#define GPIO2 (1 << 2) +#define GPIO3 (1 << 3) +#define GPIO4 (1 << 4) +#define GPIO5 (1 << 5) +#define GPIO6 (1 << 6) +#define GPIO7 (1 << 7) +#define GPIO8 (1 << 8) +#define GPIO9 (1 << 9) +#define GPIO10 (1 << 10) +#define GPIO11 (1 << 11) +#define GPIO12 (1 << 12) +#define GPIO13 (1 << 13) +#define GPIO14 (1 << 14) +#define GPIO15 (1 << 15) +#define GPIO_ALL 0xffff + +/* --- Alternate function GPIOs -------------------------------------------- */ + +/* Default alternate functions of some pins (with and without remapping) */ + +/* CAN1 / CAN */ +#define GPIO_CAN1_RX GPIO11 /* PA11 */ +#define GPIO_CAN1_TX GPIO12 /* PA12 */ +#define GPIO_CAN_RX GPIO_CAN1_RX /* Alias */ +#define GPIO_CAN_TX GPIO_CAN1_TX /* Alias */ + +#define GPIO_CAN_PB_RX GPIO8 /* PB8 */ +#define GPIO_CAN_PB_TX GPIO9 /* PB9 */ +#define GPIO_CAN1_PB_RX GPIO_CAN_PB_RX /* Alias */ +#define GPIO_CAN1_PB_TX GPIO_CAN_PB_TX /* Alias */ + +#define GPIO_CAN_PD_RX GPIO0 /* PD0 */ +#define GPIO_CAN_PD_TX GPIO1 /* PD1 */ +#define GPIO_CAN1_PD_RX GPIO_CAN_PD_RX /* Alias */ +#define GPIO_CAN1_PD_TX GPIO_CAN_PD_TX /* Alias */ + +/* CAN2 */ +#define GPIO_CAN2_RX GPIO12 /* PB12 */ +#define GPIO_CAN2_TX GPIO13 /* PB13 */ + +#define GPIO_CAN2_RE_RX GPIO5 /* PB5 */ +#define GPIO_CAN2_RE_TX GPIO6 /* PB6 */ + +/* JTAG/SWD */ +#define GPIO_JTMS_SWDIO GPIO13 /* PA13 */ +#define GPIO_JTCK_SWCLK GPIO14 /* PA14 */ +#define GPIO_JTDI GPIO15 /* PA15 */ +#define GPIO_JTDO_TRACESWO GPIO3 /* PB3 */ +#define GPIO_JNTRST GPIO4 /* PB4 */ +#define GPIO_TRACECK GPIO2 /* PE2 */ +#define GPIO_TRACED0 GPIO3 /* PE3 */ +#define GPIO_TRACED1 GPIO4 /* PE4 */ +#define GPIO_TRACED2 GPIO5 /* PE5 */ +#define GPIO_TRACED3 GPIO6 /* PE6 */ + +/* Timer5 */ +#define GPIO_TIM5_CH4 GPIO3 /* PA3 */ + +/* Timer4 */ +#define GPIO_TIM4_CH1 GPIO6 /* PB6 */ +#define GPIO_TIM4_CH2 GPIO7 /* PB7 */ +#define GPIO_TIM4_CH3 GPIO8 /* PB8 */ +#define GPIO_TIM4_CH4 GPIO9 /* PB9 */ + +#define GPIO_TIM4_RE_CH1 GPIO12 /* PD12 */ +#define GPIO_TIM4_RE_CH2 GPIO13 /* PD13 */ +#define GPIO_TIM4_RE_CH3 GPIO14 /* PD14 */ +#define GPIO_TIM4_RE_CH4 GPIO15 /* PD15 */ + +/* Timer3 */ +#define GPIO_TIM3_CH1 GPIO6 /* PA6 */ +#define GPIO_TIM3_CH2 GPIO7 /* PA7 */ +#define GPIO_TIM3_CH3 GPIO0 /* PB0 */ +#define GPIO_TIM3_CH4 GPIO1 /* PB1 */ + +#define GPIO_TIM3_PR_CH1 GPIO4 /* PB4 */ +#define GPIO_TIM3_PR_CH2 GPIO5 /* PB5 */ +#define GPIO_TIM3_PR_CH3 GPIO0 /* PB0 */ +#define GPIO_TIM3_PR_CH4 GPIO1 /* PB1 */ + +#define GPIO_TIM3_FR_CH1 GPIO6 /* PC6 */ +#define GPIO_TIM3_FR_CH2 GPIO7 /* PC7 */ +#define GPIO_TIM3_FR_CH3 GPIO8 /* PC8 */ +#define GPIO_TIM3_FR_CH4 GPIO9 /* PC9 */ + +/* Timer2 */ +#define GPIO_TIM2_CH1_ETR GPIO0 /* PA0 */ +#define GPIO_TIM2_CH2 GPIO1 /* PA1 */ +#define GPIO_TIM2_CH3 GPIO2 /* PA2 */ +#define GPIO_TIM2_CH4 GPIO3 /* PA3 */ + +#define GPIO_TIM2_PR1_CH1_ETR GPIO15 /* PA15 */ +#define GPIO_TIM2_PR1_CH2 GPIO3 /* PB3 */ +#define GPIO_TIM2_PR1_CH3 GPIO2 /* PA2 */ +#define GPIO_TIM2_PR1_CH4 GPIO3 /* PA3 */ + +#define GPIO_TIM2_PR2_CH1_ETR GPIO0 /* PA0 */ +#define GPIO_TIM2_PR2_CH2 GPIO1 /* PA1 */ +#define GPIO_TIM2_PR2_CH3 GPIO10 /* PB10 */ +#define GPIO_TIM2_PR2_CH4 GPIO11 /* PB11 */ + +#define GPIO_TIM2_FR_CH1_ETR GPIO15 /* PA15 */ +#define GPIO_TIM2_FR_CH2 GPIO3 /* PB3 */ +#define GPIO_TIM2_FR_CH3 GPIO10 /* PB10 */ +#define GPIO_TIM2_FR_CH4 GPIO11 /* PB11 */ + +/* Timer1 */ +#define GPIO_TIM1_ETR GPIO12 /* PA12 */ +#define GPIO_TIM1_CH1 GPIO8 /* PA8 */ +#define GPIO_TIM1_CH2 GPIO9 /* PA9 */ +#define GPIO_TIM1_CH3 GPIO10 /* PA10 */ +#define GPIO_TIM1_CH4 GPIO11 /* PA11 */ +#define GPIO_TIM1_BKIN GPIO12 /* PB12 */ +#define GPIO_TIM1_CH1N GPIO13 /* PB13 */ +#define GPIO_TIM1_CH2N GPIO14 /* PB14 */ +#define GPIO_TIM1_CH3N GPIO15 /* PB15 */ + +#define GPIO_TIM1_PR_ETR GPIO12 /* PA12 */ +#define GPIO_TIM1_PR_CH1 GPIO8 /* PA8 */ +#define GPIO_TIM1_PR_CH2 GPIO9 /* PA9 */ +#define GPIO_TIM1_PR_CH3 GPIO10 /* PA10 */ +#define GPIO_TIM1_PR_CH4 GPIO11 /* PA11 */ +#define GPIO_TIM1_PR_BKIN GPIO6 /* PA6 */ +#define GPIO_TIM1_PR_CH1N GPIO7 /* PA7 */ +#define GPIO_TIM1_PR_CH2N GPIO0 /* PB0 */ +#define GPIO_TIM1_PR_CH3N GPIO1 /* PB1 */ + +#define GPIO_TIM1_FR_ETR GPIO7 /* PE7 */ +#define GPIO_TIM1_FR_CH1 GPIO9 /* PE9 */ +#define GPIO_TIM1_FR_CH2 GPIO11 /* PE11 */ +#define GPIO_TIM1_FR_CH3 GPIO13 /* PE13 */ +#define GPIO_TIM1_FR_CH4 GPIO14 /* PE14 */ +#define GPIO_TIM1_FR_BKIN GPIO15 /* PE15 */ +#define GPIO_TIM1_FR_CH1N GPIO8 /* PE8 */ +#define GPIO_TIM1_FR_CH2N GPIO10 /* PE10 */ +#define GPIO_TIM1_FR_CH3N GPIO12 /* PE12 */ + +/* USART3 */ +#define GPIO_USART3_TX GPIO10 /* PB10 */ +#define GPIO_USART3_RX GPIO11 /* PB11 */ +#define GPIO_USART3_CK GPIO12 /* PB12 */ +#define GPIO_USART3_CTS GPIO13 /* PB13 */ +#define GPIO_USART3_RTS GPIO14 /* PB14 */ + +#define GPIO_USART3_PR_TX GPIO10 /* PC10 */ +#define GPIO_USART3_PR_RX GPIO11 /* PC11 */ +#define GPIO_USART3_PR_CK GPIO12 /* PC12 */ +#define GPIO_USART3_PR_CTS GPIO13 /* PB13 */ +#define GPIO_USART3_PR_RTS GPIO14 /* PB14 */ + +#define GPIO_USART3_FR_TX GPIO8 /* PD8 */ +#define GPIO_USART3_FR_RX GPIO9 /* PD9 */ +#define GPIO_USART3_FR_CK GPIO10 /* PD10 */ +#define GPIO_USART3_FR_CTS GPIO11 /* PD11 */ +#define GPIO_USART3_FR_RTS GPIO12 /* PD12 */ + +/* USART2 */ +#define GPIO_USART2_CTS GPIO0 /* PA0 */ +#define GPIO_USART2_RTS GPIO1 /* PA1 */ +#define GPIO_USART2_TX GPIO2 /* PA2 */ +#define GPIO_USART2_RX GPIO3 /* PA3 */ +#define GPIO_USART2_CK GPIO4 /* PA4 */ + +#define GPIO_USART2_RE_CTS GPIO3 /* PD3 */ +#define GPIO_USART2_RE_RTS GPIO4 /* PD4 */ +#define GPIO_USART2_RE_TX GPIO5 /* PD5 */ +#define GPIO_USART2_RE_RX GPIO6 /* PD6 */ +#define GPIO_USART2_RE_CK GPIO7 /* PD7 */ + +/* USART1 */ +#define GPIO_USART1_TX GPIO9 /* PA9 */ +#define GPIO_USART1_RX GPIO10 /* PA10 */ + +#define GPIO_USART1_RE_TX GPIO6 /* PB6 */ +#define GPIO_USART1_RE_RX GPIO7 /* PB7 */ + +/* I2C1 */ +#define GPIO_I2C1_SMBAI GPIO5 /* PB5 */ +#define GPIO_I2C1_SCL GPIO6 /* PB6 */ +#define GPIO_I2C1_SDA GPIO7 /* PB7 */ + +#define GPIO_I2C1_RE_SMBAI GPIO5 /* PB5 */ +#define GPIO_I2C1_RE_SCL GPIO8 /* PB8 */ +#define GPIO_I2C1_RE_SDA GPIO9 /* PB9 */ + +/* I2C2 */ +#define GPIO_I2C2_SCL GPIO10 /* PB10 */ +#define GPIO_I2C2_SDA GPIO11 /* PB11 */ +#define GPIO_I2C2_SMBAI GPIO12 /* PB12 */ + +/* SPI1 */ +#define GPIO_SPI1_NSS GPIO4 /* PA4 */ +#define GPIO_SPI1_SCK GPIO5 /* PA5 */ +#define GPIO_SPI1_MISO GPIO6 /* PA6 */ +#define GPIO_SPI1_MOSI GPIO7 /* PA7 */ + +#define GPIO_SPI1_RE_NSS GPIO15 /* PA15 */ +#define GPIO_SPI1_RE_SCK GPIO3 /* PB3 */ +#define GPIO_SPI1_RE_MISO GPIO4 /* PB4 */ +#define GPIO_SPI1_RE_MOSI GPIO5 /* PB5 */ + +/* SPI2 */ +#define GPIO_SPI2_NSS GPIO12 /* PB12 */ +#define GPIO_SPI2_SCK GPIO13 /* PB13 */ +#define GPIO_SPI2_MISO GPIO14 /* PB14 */ +#define GPIO_SPI2_MOSI GPIO15 /* PB15 */ + +/* SPI3 */ +#define GPIO_SPI3_NSS GPIO15 /* PA15 */ +#define GPIO_SPI3_SCK GPIO3 /* PB3 */ +#define GPIO_SPI3_MISO GPIO4 /* PB4 */ +#define GPIO_SPI3_MOSI GPIO5 /* PB5 */ + +#define GPIO_SPI3_RE_NSS GPIO4 /* PA4 */ +#define GPIO_SPI3_RE_SCK GPIO10 /* PC10 */ +#define GPIO_SPI3_RE_MISO GPIO11 /* PC11 */ +#define GPIO_SPI3_RE_MOSI GPIO12 /* PC12 */ + +/* ETH */ +#define GPIO_ETH_RX_DV_CRS_DV GPIO7 /* PA7 */ +#define GPIO_ETH_RXD0 GPIO4 /* PC4 */ +#define GPIO_ETH_RXD1 GPIO5 /* PC5 */ +#define GPIO_ETH_RXD2 GPIO0 /* PB0 */ +#define GPIO_ETH_RXD3 GPIO1 /* PB1 */ + +#define GPIO_ETH_RE_RX_DV_CRS_DV GPIO8 /* PD8 */ +#define GPIO_ETH_RE_RXD0 GPIO9 /* PD9 */ +#define GPIO_ETH_RE_RXD1 GPIO10 /* PD10 */ +#define GPIO_ETH_RE_RXD2 GPIO11 /* PD11 */ +#define GPIO_ETH_RE_RXD3 GPIO12 /* PD12 */ + +/* --- GPIO registers ------------------------------------------------------ */ + +/* Port configuration register low (GPIOx_CRL) */ +#define GPIO_CRL(port) MMIO32(port + 0x00) +#define GPIOA_CRL GPIO_CRL(GPIOA) +#define GPIOB_CRL GPIO_CRL(GPIOB) +#define GPIOC_CRL GPIO_CRL(GPIOC) +#define GPIOD_CRL GPIO_CRL(GPIOD) +#define GPIOE_CRL GPIO_CRL(GPIOE) +#define GPIOF_CRL GPIO_CRL(GPIOF) +#define GPIOG_CRL GPIO_CRL(GPIOG) + +/* Port configuration register low (GPIOx_CRH) */ +#define GPIO_CRH(port) MMIO32(port + 0x04) +#define GPIOA_CRH GPIO_CRH(GPIOA) +#define GPIOB_CRH GPIO_CRH(GPIOB) +#define GPIOC_CRH GPIO_CRH(GPIOC) +#define GPIOD_CRH GPIO_CRH(GPIOD) +#define GPIOE_CRH GPIO_CRH(GPIOE) +#define GPIOF_CRH GPIO_CRH(GPIOF) +#define GPIOG_CRH GPIO_CRH(GPIOG) + +/* Port input data register (GPIOx_IDR) */ +#define GPIO_IDR(port) MMIO32(port + 0x08) +#define GPIOA_IDR GPIO_IDR(GPIOA) +#define GPIOB_IDR GPIO_IDR(GPIOB) +#define GPIOC_IDR GPIO_IDR(GPIOC) +#define GPIOD_IDR GPIO_IDR(GPIOD) +#define GPIOE_IDR GPIO_IDR(GPIOE) +#define GPIOF_IDR GPIO_IDR(GPIOF) +#define GPIOG_IDR GPIO_IDR(GPIOG) + +/* Port output data register (GPIOx_ODR) */ +#define GPIO_ODR(port) MMIO32(port + 0x0c) +#define GPIOA_ODR GPIO_ODR(GPIOA) +#define GPIOB_ODR GPIO_ODR(GPIOB) +#define GPIOC_ODR GPIO_ODR(GPIOC) +#define GPIOD_ODR GPIO_ODR(GPIOD) +#define GPIOE_ODR GPIO_ODR(GPIOE) +#define GPIOF_ODR GPIO_ODR(GPIOF) +#define GPIOG_ODR GPIO_ODR(GPIOG) + +/* Port bit set/reset register (GPIOx_BSRR) */ +#define GPIO_BSRR(port) MMIO32(port + 0x10) +#define GPIOA_BSRR GPIO_BSRR(GPIOA) +#define GPIOB_BSRR GPIO_BSRR(GPIOB) +#define GPIOC_BSRR GPIO_BSRR(GPIOC) +#define GPIOD_BSRR GPIO_BSRR(GPIOD) +#define GPIOE_BSRR GPIO_BSRR(GPIOE) +#define GPIOF_BSRR GPIO_BSRR(GPIOF) +#define GPIOG_BSRR GPIO_BSRR(GPIOG) + +/* Port bit reset register (GPIOx_BRR) */ +#define GPIO_BRR(port) MMIO16(port + 0x14) +#define GPIOA_BRR GPIO_BRR(GPIOA) +#define GPIOB_BRR GPIO_BRR(GPIOB) +#define GPIOC_BRR GPIO_BRR(GPIOC) +#define GPIOD_BRR GPIO_BRR(GPIOD) +#define GPIOE_BRR GPIO_BRR(GPIOE) +#define GPIOF_BRR GPIO_BRR(GPIOF) +#define GPIOG_BRR GPIO_BRR(GPIOG) + +/* Port configuration lock register (GPIOx_LCKR) */ +#define GPIO_LCKR(port) MMIO32(port + 0x18) +#define GPIOA_LCKR GPIO_LCKR(GPIOA) +#define GPIOB_LCKR GPIO_LCKR(GPIOB) +#define GPIOC_LCKR GPIO_LCKR(GPIOC) +#define GPIOD_LCKR GPIO_LCKR(GPIOD) +#define GPIOE_LCKR GPIO_LCKR(GPIOE) +#define GPIOF_LCKR GPIO_LCKR(GPIOF) +#define GPIOG_LCKR GPIO_LCKR(GPIOG) + +/* --- GPIO_CRL/GPIO_CRH values -------------------------------------------- */ + +/* CNF[1:0] values when MODE[1:0] is 00 (input mode) */ +#define GPIO_CNF_INPUT_ANALOG 0x00 +#define GPIO_CNF_INPUT_FLOAT 0x01 /* Default */ +#define GPIO_CNF_INPUT_PULL_UPDOWN 0x02 + +/* Output mode (MODE[1:0]) values */ +#define GPIO_MODE_INPUT 0x00 /* Default */ +#define GPIO_MODE_OUTPUT_10_MHZ 0x01 +#define GPIO_MODE_OUTPUT_2_MHZ 0x02 +#define GPIO_MODE_OUTPUT_50_MHZ 0x03 + +/* CNF[1:0] values when MODE[1:0] is != 00 (one of the output modes) */ +#define GPIO_CNF_OUTPUT_PUSHPULL 0x00 +#define GPIO_CNF_OUTPUT_OPENDRAIN 0x01 +#define GPIO_CNF_OUTPUT_ALTFN_PUSHPULL 0x02 +#define GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN 0x03 + +/* --- GPIO_IDR values ----------------------------------------------------- */ + +/* GPIO_IDR[15:0]: IDRy[15:0]: Port input data (y = 0..15) */ + +/* --- GPIO_ODR values ----------------------------------------------------- */ + +/* GPIO_ODR[15:0]: ODRy[15:0]: Port output data (y = 0..15) */ + +/* --- GPIO_BSRR values ---------------------------------------------------- */ + +/* GPIO_BSRR[31:16]: BRy: Port x reset bit y (y = 0..15) */ +/* GPIO_BSRR[15:0]: BSy: Port x set bit y (y = 0..15) */ + +/* --- GPIO_BRR values ----------------------------------------------------- */ + +/* GPIO_BRR[15:0]: BRy: Port x reset bit y (y = 0..15) */ + +/* --- GPIO_LCKR values ---------------------------------------------------- */ + +#define GPIO_LCKK (1 << 16) +/* GPIO_LCKR[15:0]: LCKy: Port x lock bit y (y = 0..15) */ + +/* --- AFIO registers ------------------------------------------------------ */ + +/* Event control register (AFIO_EVCR) */ +#define AFIO_EVCR MMIO32(AFIO_BASE + 0x00) + +/* AF remap and debug I/O configuration register (AFIO_MAPR) */ +#define AFIO_MAPR MMIO32(AFIO_BASE + 0x04) + +/* External interrupt configuration register 1 (AFIO_EXTICR1) */ +#define AFIO_EXTICR1 MMIO32(AFIO_BASE + 0x08) + +/* External interrupt configuration register 2 (AFIO_EXTICR2) */ +#define AFIO_EXTICR2 MMIO32(AFIO_BASE + 0x0c) + +/* External interrupt configuration register 3 (AFIO_EXTICR3) */ +#define AFIO_EXTICR3 MMIO32(AFIO_BASE + 0x10) + +/* External interrupt configuration register 4 (AFIO_EXTICR4) */ +#define AFIO_EXTICR4 MMIO32(AFIO_BASE + 0x14) + +/* --- AFIO_EVCR values ---------------------------------------------------- */ + +/* EVOE: Event output enable */ +#define AFIO_EVCR_EVOE (1 << 7) + +/* PORT[2:0]: Port selection */ +#define AFIO_EVCR_PORT_PA (0x0 << 4) +#define AFIO_EVCR_PORT_PB (0x1 << 4) +#define AFIO_EVCR_PORT_PC (0x2 << 4) +#define AFIO_EVCR_PORT_PD (0x3 << 4) +#define AFIO_EVCR_PORT_PE (0x4 << 4) + +/* PIN[3:0]: Pin selection */ +#define AFIO_EVCR_PIN_Px0 (0x0 << 0) +#define AFIO_EVCR_PIN_Px1 (0x1 << 0) +#define AFIO_EVCR_PIN_Px2 (0x2 << 0) +#define AFIO_EVCR_PIN_Px3 (0x3 << 0) +#define AFIO_EVCR_PIN_Px4 (0x4 << 0) +#define AFIO_EVCR_PIN_Px5 (0x5 << 0) +#define AFIO_EVCR_PIN_Px6 (0x6 << 0) +#define AFIO_EVCR_PIN_Px7 (0x7 << 0) +#define AFIO_EVCR_PIN_Px8 (0x8 << 0) +#define AFIO_EVCR_PIN_Px9 (0x9 << 0) +#define AFIO_EVCR_PIN_Px10 (0xA << 0) +#define AFIO_EVCR_PIN_Px11 (0xB << 0) +#define AFIO_EVCR_PIN_Px12 (0xC << 0) +#define AFIO_EVCR_PIN_Px13 (0xD << 0) +#define AFIO_EVCR_PIN_Px14 (0xE << 0) +#define AFIO_EVCR_PIN_Px15 (0xF << 0) + +/* --- AFIO_MAPR values ---------------------------------------------------- */ + +/* 31 reserved */ + +/* PTP_PPS_REMAP: Ethernet PTP PPS remapping + * (only connectivity line devices) */ +#define AFIO_MAPR_PTP_PPS_REMAP (1 << 30) + +/* TIM2ITR1_IREMAP: TIM2 internal trigger 1 remapping + * (only connectivity line devices) */ +#define AFIO_MAPR_TIM2ITR1_IREMAP (1 << 29) + +/* SPI3_REMAP: SPI3/I2S3 remapping + * (only connectivity line devices) */ +#define AFIO_MAPR_SPI3_REMAP (1 << 28) + +/* 27 reserved */ + +/* SWJ_CFG[2:0]: Serial wire JTAG configuration */ +#define AFIO_MAPR_SWJ_CFG_FULL_SWJ (0x0 << 24) +#define AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_JNTRST (0x1 << 24) +#define AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_ON (0x2 << 24) +#define AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_OFF (0x4 << 24) + +/* MII_REMAP: MII or RMII selection + * (only connectivity line devices) */ +#define AFIO_MAPR_MII_RMII_SEL (1 << 23) + +/* CAN2_REMAP: CAN2 I/O remapping + * (only connectivity line devices) */ +#define AFIO_MAPR_CAN2_REMAP (1 << 22) + +/* ETH_REMAP: Ethernet MAC I/O remapping + * (only connectivity line devices) */ +#define AFIO_MAPR_ETH_REMAP (1 << 21) + +/* ADC2_ETRGREG_REMAP: ADC2 external trigger regulator conversion remapping + * (only low-, medium-, high- and XL-densitiy devices) */ +#define AFIO_MAPR_ADC2_ETRGREG_REMAP (1 << 20) + +/* ADC2_ETRGINJ_REMAP: ADC2 external trigger injected conversion remapping + * (only low-, medium-, high- and XL-densitiy devices) */ +#define AFIO_MAPR_ADC2_ETRGINJ_REMAP (1 << 19) + +/* ADC1_ETRGREG_REMAP: ADC1 external trigger regulator conversion remapping + * (only low-, medium-, high- and XL-densitiy devices) */ +#define AFIO_MAPR_ADC1_ETRGREG_REMAP (1 << 18) + +/* ADC1_ETRGINJ_REMAP: ADC1 external trigger injected conversion remapping + * (only low-, medium-, high- and XL-densitiy devices) */ +#define AFIO_MAPR_ADC1_ETRGINJ_REMAP (1 << 17) + +/* TIM5CH4_IREMAP: TIM5 channel4 internal remap */ +#define AFIO_MAPR_TIM5CH4_IREMAP (1 << 16) + +/* PD01_REMAP: Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ +#define AFIO_MAPR_PD01_REMAP (1 << 15) + +/* CAN_REMAP[1:0]: CAN1 alternate function remapping */ +#define AFIO_MAPR_CAN1_REMAP_PORTA (0x0 << 13) +#define AFIO_MAPR_CAN1_REMAP_PORTB (0x2 << 13) /* Not on 36pin pkg */ +#define AFIO_MAPR_CAN1_REMAP_PORTD (0x3 << 13) + +/* TIM4_REMAP: TIM4 remapping */ +#define AFIO_MAPR_TIM4_REMAP (1 << 12) + +/* TIM3_REMAP[1:0]: TIM3 remapping */ +#define AFIO_MAPR_TIM3_REMAP_NO_REMAP (0x0 << 10) +#define AFIO_MAPR_TIM3_REMAP_PARTIAL_REMAP (0x2 << 10) +#define AFIO_MAPR_TIM3_REMAP_FULL_REMAP (0x3 << 10) + +/* TIM2_REMAP[1:0]: TIM2 remapping */ +#define AFIO_MAPR_TIM2_REMAP_NO_REMAP (0x0 << 8) +#define AFIO_MAPR_TIM2_REMAP_PARTIAL_REMAP1 (0x1 << 8) +#define AFIO_MAPR_TIM2_REMAP_PARTIAL_REMAP2 (0x2 << 8) +#define AFIO_MAPR_TIM2_REMAP_FULL_REMAP (0x3 << 8) + +/* TIM1_REMAP[1:0]: TIM1 remapping */ +#define AFIO_MAPR_TIM1_REMAP_NO_REMAP (0x0 << 6) +#define AFIO_MAPR_TIM1_REMAP_PARTIAL_REMAP (0x1 << 6) +#define AFIO_MAPR_TIM1_REMAP_FULL_REMAP (0x3 << 6) + +/* USART3_REMAP[1:0]: USART3 remapping */ +#define AFIO_MAPR_USART3_REMAP_NO_REMAP (0x0 << 4) +#define AFIO_MAPR_USART3_REMAP_PARTIAL_REMAP (0x1 << 4) +#define AFIO_MAPR_USART3_REMAP_FULL_REMAP (0x3 << 4) + +/* USART2_REMAP[1:0]: USART2 remapping */ +#define AFIO_MAPR_USART2_REMAP (1 << 3) + +/* USART1_REMAP[1:0]: USART1 remapping */ +#define AFIO_MAPR_USART1_REMAP (1 << 2) + +/* I2C1_REMAP[1:0]: I2C1 remapping */ +#define AFIO_MAPR_I2C1_REMAP (1 << 1) + +/* SPI1_REMAP[1:0]: SPI1 remapping */ +#define AFIO_MAPR_SPI1_REMAP (1 << 0) + +/* --- AFIO_EXTICR1 values ------------------------------------------------- */ +/* --- AFIO_EXTICR2 values ------------------------------------------------- */ +/* --- AFIO_EXTICR3 values ------------------------------------------------- */ +/* --- AFIO_EXTICR4 values ------------------------------------------------- */ + +/* EXTI0 - EXTI15 interrupt source selection registers */ + +/* Note: For using them we should define a function that calculates the right + * registers, using definitions is probably not a good idea. + */ + +/* --- Function prototypes ------------------------------------------------- */ + +void gpio_set_mode(u32 gpioport, u8 mode, u8 cnf, u16 gpios); +void gpio_set(u32 gpioport, u16 gpios); +void gpio_clear(u32 gpioport, u16 gpios); +u16 gpio_get(u32 gpioport, u16 gpios); +void gpio_toggle(u32 gpioport, u16 gpios); +u16 gpio_port_read(u32 gpioport); +void gpio_port_write(u32 gpioport, u16 data); +void gpio_port_config_lock(u32 gpioport, u16 gpios); + +#endif diff --git a/include/libopencm3/stm32f1/i2c.h b/include/libopencm3/stm32f1/i2c.h new file mode 100644 index 0000000..1b837b8 --- /dev/null +++ b/include/libopencm3/stm32f1/i2c.h @@ -0,0 +1,333 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_I2C_H +#define LIBOPENCM3_I2C_H + +#include +#include + +/* --- Convenience macros -------------------------------------------------- */ + +/* I2C register base adresses (for convenience) */ +#define I2C1 I2C1_BASE +#define I2C2 I2C2_BASE + +/* --- I2C registers ------------------------------------------------------- */ + +/* Control register 1 (I2Cx_CR1) */ +#define I2C_CR1(i2c_base) MMIO32(i2c_base + 0x00) +#define I2C1_CR1 I2C_CR1(I2C1) +#define I2C2_CR1 I2C_CR1(I2C2) + +/* Control register 2 (I2Cx_CR2) */ +#define I2C_CR2(i2c_base) MMIO32(i2c_base + 0x04) +#define I2C1_CR2 I2C_CR2(I2C1) +#define I2C2_CR2 I2C_CR2(I2C2) + +/* Own address register 1 (I2Cx_OAR1) */ +#define I2C_OAR1(i2c_base) MMIO32(i2c_base + 0x08) +#define I2C1_OAR1 I2C_OAR1(I2C1) +#define I2C2_OAR1 I2C_OAR1(I2C2) + +/* Own address register 2 (I2Cx_OAR2) */ +#define I2C_OAR2(i2c_base) MMIO32(i2c_base + 0x0c) +#define I2C1_OAR2 I2C_OAR2(I2C1) +#define I2C2_OAR2 I2C_OAR2(I2C2) + +/* Data register (I2Cx_DR) */ +#define I2C_DR(i2c_base) MMIO32(i2c_base + 0x10) +#define I2C1_DR I2C_DR(I2C1) +#define I2C2_DR I2C_DR(I2C2) + +/* Status register 1 (I2Cx_SR1) */ +#define I2C_SR1(i2c_base) MMIO32(i2c_base + 0x14) +#define I2C1_SR1 I2C_SR1(I2C1) +#define I2C2_SR1 I2C_SR1(I2C2) + +/* Status register 2 (I2Cx_SR2) */ +#define I2C_SR2(i2c_base) MMIO32(i2c_base + 0x18) +#define I2C1_SR2 I2C_SR2(I2C1) +#define I2C2_SR2 I2C_SR2(I2C2) + +/* Clock control register (I2Cx_CCR) */ +#define I2C_CCR(i2c_base) MMIO32(i2c_base + 0x1c) +#define I2C1_CCR I2C_CCR(I2C1) +#define I2C2_CCR I2C_CCR(I2C2) + +/* TRISE register (I2Cx_CCR) */ +#define I2C_TRISE(i2c_base) MMIO32(i2c_base + 0x20) +#define I2C1_TRISE I2C_TRISE(I2C1) +#define I2C2_TRISE I2C_TRISE(I2C2) + +/* --- I2Cx_CR1 values ----------------------------------------------------- */ + +/* SWRST: Software reset */ +#define I2C_CR1_SWRST (1 << 15) + +/* Note: Bit 14 is reserved, and forced to 0 by hardware. */ + +/* ALERT: SMBus alert */ +#define I2C_CR1_ALERT (1 << 13) + +/* PEC: Packet error checking */ +#define I2C_CR1_PEC (1 << 12) + +/* POS: Acknowledge / PEC postition */ +#define I2C_CR1_POS (1 << 11) + +/* ACK: Acknowledge enable */ +#define I2C_CR1_ACK (1 << 10) + +/* STOP: STOP generation */ +#define I2C_CR1_STOP (1 << 9) + +/* START: START generation */ +#define I2C_CR1_START (1 << 8) + +/* NOSTRETCH: Clock stretching disable (slave mode) */ +#define I2C_CR1_NOSTRETCH (1 << 7) + +/* ENGC: General call enable */ +#define I2C_CR1_ENGC (1 << 6) + +/* ENPEC: Enable PEC */ +#define I2C_CR1_ENPEC (1 << 5) + +/* ENARP: ARP enable */ +#define I2C_CR1_ENARP (1 << 4) + +/* SMBTYPE: SMBus type */ +#define I2C_CR1_SMBTYPE (1 << 3) + +/* Note: Bit 2 is reserved, and forced to 0 by hardware. */ + +/* SMBUS: SMBus mode */ +#define I2C_CR1_SMBUS (1 << 1) + +/* PE: Peripheral enable */ +#define I2C_CR1_PE (1 << 0) + +/* --- I2Cx_CR2 values ----------------------------------------------------- */ + +/* Note: Bits [15:13] are reserved, and forced to 0 by hardware. */ + +/* LAST: DMA last transfer */ +#define I2C_CR2_LAST (1 << 12) + +/* DMAEN: DMA requests enable */ +#define I2C_CR2_DMAEN (1 << 11) + +/* ITBUFEN: Buffer interrupt enable */ +#define I2C_CR2_ITBUFEN (1 << 10) + +/* ITEVTEN: Event interrupt enable */ +#define I2C_CR2_ITEVTEN (1 << 9) + +/* ITERREN: Error interrupt enable */ +#define I2C_CR2_ITERREN (1 << 8) + +/* Note: Bits [7:6] are reserved, and forced to 0 by hardware. */ + +/* FREQ[5:0]: Peripheral clock frequency (valid values: 2-36 MHz) */ +#define I2C_CR2_FREQ_2MHZ 0x02 +#define I2C_CR2_FREQ_3MHZ 0x03 +#define I2C_CR2_FREQ_4MHZ 0x04 +#define I2C_CR2_FREQ_5MHZ 0x05 +#define I2C_CR2_FREQ_6MHZ 0x06 +#define I2C_CR2_FREQ_7MHZ 0x07 +#define I2C_CR2_FREQ_8MHZ 0x08 +#define I2C_CR2_FREQ_9MHZ 0x09 +#define I2C_CR2_FREQ_10MHZ 0x0a +#define I2C_CR2_FREQ_11MHZ 0x0b +#define I2C_CR2_FREQ_12MHZ 0x0c +#define I2C_CR2_FREQ_13MHZ 0x0d +#define I2C_CR2_FREQ_14MHZ 0x0e +#define I2C_CR2_FREQ_15MHZ 0x0f +#define I2C_CR2_FREQ_16MHZ 0x10 +#define I2C_CR2_FREQ_17MHZ 0x11 +#define I2C_CR2_FREQ_18MHZ 0x12 +#define I2C_CR2_FREQ_19MHZ 0x13 +#define I2C_CR2_FREQ_20MHZ 0x14 +#define I2C_CR2_FREQ_21MHZ 0x15 +#define I2C_CR2_FREQ_22MHZ 0x16 +#define I2C_CR2_FREQ_23MHZ 0x17 +#define I2C_CR2_FREQ_24MHZ 0x18 +#define I2C_CR2_FREQ_25MHZ 0x19 +#define I2C_CR2_FREQ_26MHZ 0x1a +#define I2C_CR2_FREQ_27MHZ 0x1b +#define I2C_CR2_FREQ_28MHZ 0x1c +#define I2C_CR2_FREQ_29MHZ 0x1d +#define I2C_CR2_FREQ_30MHZ 0x1e +#define I2C_CR2_FREQ_31MHZ 0x1f +#define I2C_CR2_FREQ_32MHZ 0x20 +#define I2C_CR2_FREQ_33MHZ 0x21 +#define I2C_CR2_FREQ_34MHZ 0x22 +#define I2C_CR2_FREQ_35MHZ 0x23 +#define I2C_CR2_FREQ_36MHZ 0x24 + +/* --- I2Cx_OAR1 values ---------------------------------------------------- */ + +/* ADDMODE: Addressing mode (slave mode) */ +#define I2C_OAR1_ADDMODE (1 << 15) +#define I2C_OAR1_ADDMODE_7BIT 0 +#define I2C_OAR1_ADDMODE_10BIT 1 + +/* Note: Bit 14 should always be kept at 1 by software! */ + +/* Note: Bits [13:10] are reserved, and forced to 0 by hardware. */ + +/* ADD: Address bits: [7:1] in 7-bit mode, bits [9:0] in 10-bit mode */ + +/* --- I2Cx_OAR1 values ---------------------------------------------------- */ + +/* Note: Bits [15:8] are reserved, and forced to 0 by hardware. */ + +/* ADD2[7:1]: Interface address (bits [7:1] in dual addressing mode) */ + +/* ENDUAL: Dual addressing mode enable */ +#define I2C_OAR2_ENDUAL (1 << 0) + +/* --- I2Cx_DR values ------------------------------------------------------ */ + +/* Note: Bits [15:8] are reserved, and forced to 0 by hardware. */ + +/* DR[7:0] 8-bit data register */ + +/* --- I2Cx_SR1 values ----------------------------------------------------- */ + +/* SMBALERT: SMBus alert */ +#define I2C_SR1_SMBALERT (1 << 15) + +/* TIMEOUT: Timeout or Tlow Error */ +#define I2C_SR1_TIMEOUT (1 << 14) + +/* Note: Bit 13 is reserved, and forced to 0 by hardware. */ + +/* PECERR: PEC Error in reception */ +#define I2C_SR1_PECERR (1 << 12) + +/* OVR: Overrun/Underrun */ +#define I2C_SR1_OVR (1 << 11) + +/* AF: Acknowledge failure */ +#define I2C_SR1_AF (1 << 10) + +/* ARLO: Arbitration lost (master mode) */ +#define I2C_SR1_ARLO (1 << 9) + +/* BERR: Bus error */ +#define I2C_SR1_BERR (1 << 8) + +/* TxE: Data register empty (transmitters) */ +#define I2C_SR1_TxE (1 << 7) + +/* RxNE: Data register not empty (receivers) */ +#define I2C_SR1_RxNE (1 << 6) + +/* Note: Bit 5 is reserved, and forced to 0 by hardware. */ + +/* STOPF: STOP detection (slave mode) */ +#define I2C_SR1_STOPF (1 << 4) + +/* ADD10: 10-bit header sent (master mode) */ +#define I2C_SR1_ADD10 (1 << 3) + +/* BTF: Byte transfer finished */ +#define I2C_SR1_BTF (1 << 2) + +/* ADDR: Address sent (master mode) / address matched (slave mode) */ +#define I2C_SR1_ADDR (1 << 1) + +/* SB: Start bit (master mode) */ +#define I2C_SR1_SB (1 << 0) + +/* --- I2Cx_SR2 values ----------------------------------------------------- */ + +/* Bits [15:8]: PEC[7:0]: Packet error checking register */ + +/* DUALF: Dual flag (slave mode) */ +#define I2C_SR2_DUALF (1 << 7) + +/* SMBHOST: SMBus host header (slave mode) */ +#define I2C_SR2_SMBHOST (1 << 6) + +/* SMBDEFAULT: SMBus device default address (slave mode) */ +#define I2C_SR2_SMBDEFAULT (1 << 5) + +/* GENCALL: General call address (slave mode) */ +#define I2C_SR2_GENCALL (1 << 4) + +/* Note: Bit 3 is reserved, and forced to 0 by hardware. */ + +/* TRA: Transmitter / receiver */ +#define I2C_SR2_TRA (1 << 2) + +/* BUSY: Bus busy */ +#define I2C_SR2_BUSY (1 << 1) + +/* MSL: Master / slave */ +#define I2C_SR2_MSL (1 << 0) + +/* --- I2Cx_CCR values ----------------------------------------------------- */ + +/* F/S: I2C Master mode selection (fast / standard) */ +#define I2C_CCR_FS (1 << 15) + +/* DUTY: Fast Mode Duty Cycle */ +#define I2C_CCR_DUTY (1 << 14) + +/* Note: Bits [13:12] are reserved, and forced to 0 by hardware. */ + +/* + * Bits [11:0]: + * CCR[11:0]: Clock control register in Fast/Standard mode (master mode) + */ + +/* --- I2Cx_TRISE values --------------------------------------------------- */ + +/* Note: Bits [15:6] are reserved, and forced to 0 by hardware. */ + +/* + * Bits [5:0]: + * TRISE[5:0]: Maximum rise time in Fast/Standard mode (master mode) + */ + +/* --- I2C const definitions ----------------------------------------------- */ + +#define I2C_WRITE 0 +#define I2C_READ 1 + +/* --- I2C funtion prototypes----------------------------------------------- */ + +void i2c_peripheral_enable(u32 i2c); +void i2c_peripheral_disable(u32 i2c); +void i2c_send_start(u32 i2c); +void i2c_send_stop(u32 i2c); +void i2c_set_own_7bit_slave_address(u32 i2c, u8 slave); +void i2c_set_own_10bit_slave_address(u32 i2c, u16 slave); +void i2c_set_fast_mode(u32 i2c); +void i2c_set_standard_mode(u32 i2c); +void i2c_set_clock_frequency(u32 i2c, u8 freq); +void i2c_set_ccr(u32 i2c, u16 freq); +void i2c_set_trise(u32 i2c, u16 trise); +void i2c_send_7bit_address(u32 i2c, u8 slave, u8 readwrite); +void i2c_send_data(u32 i2c, u8 data); + +#endif diff --git a/include/libopencm3/stm32f1/iwdg.h b/include/libopencm3/stm32f1/iwdg.h new file mode 100644 index 0000000..bf2784a --- /dev/null +++ b/include/libopencm3/stm32f1/iwdg.h @@ -0,0 +1,75 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_IWDG_H +#define LIBOPENCM3_IWDG_H + +#include +#include + +/* --- IWDG registers ------------------------------------------------------ */ + +/* Key Register (IWDG_KR) */ +#define IWDG_KR MMIO32(IWDG_BASE + 0x00) + +/* Prescaler register (IWDG_PR) */ +#define IWDG_PR MMIO32(IWDG_BASE + 0x04) + +/* Reload register (IWDG_RLR) */ +#define IWDG_RLR MMIO32(IWDG_BASE + 0x08) + +/* Status register (IWDG_SR) */ +#define IWDG_SR MMIO32(IWDG_BASE + 0x0C) + +/* --- IWDG_KR values ------------------------------------------------------ */ + +/* KEY[15:0]: Key value */ +#define IWDG_KR_RESET 0xAAAA +#define IWDG_KR_UNLOCK 0x5555 +#define IWDG_KR_START 0xCCCC + +/* --- IWDG_PR values ------------------------------------------------------ */ + +/* PR[2:0]: Prescaler divider */ +#define IWDG_PR_LSB 0 +#define IWDG_PR_DIV4 0x0 +#define IWDG_PR_DIV8 0x1 +#define IWDG_PR_DIV16 0x2 +#define IWDG_PR_DIV32 0x3 +#define IWDG_PR_DIV64 0x4 +#define IWDG_PR_DIV128 0x5 +#define IWDG_PR_DIV256 0x6 +/* Double definition: 0x06 and 0x07 both mean DIV256 as per datasheet. */ +/* #define IWDG_PR_DIV256 0x7 */ + +/* --- IWDG_RLR values ----------------------------------------------------- */ + +/* RL[11:0]: Watchdog counter reload value */ + +/* --- IWDG_SR values ------------------------------------------------------ */ + +/* RVU: Watchdog counter reload value update */ +#define IWDG_SR_RVU (1 << 1) + +/* PVU: Watchdog prescaler value update */ +#define IWDG_SR_PVU (1 << 0) + +/* --- IWDG funtion prototypes---------------------------------------------- */ + +#endif diff --git a/include/libopencm3/stm32f1/memorymap.h b/include/libopencm3/stm32f1/memorymap.h new file mode 100644 index 0000000..e3c57c8 --- /dev/null +++ b/include/libopencm3/stm32f1/memorymap.h @@ -0,0 +1,113 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_MEMORYMAP_H +#define LIBOPENCM3_MEMORYMAP_H + +#include + +/* --- STM32 specific peripheral definitions ------------------------------- */ + +/* Memory map for all busses */ +#define PERIPH_BASE 0x40000000 +#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000) +#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000) +#define PERIPH_BASE_AHB (PERIPH_BASE + 0x18000) + +/* Register boundary addresses */ + +/* APB1 */ +#define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000) +#define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400) +#define TIM4_BASE (PERIPH_BASE_APB1 + 0x0800) +#define TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00) +#define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000) +#define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400) +#define TIM12_BASE (PERIPH_BASE_APB1 + 0x1800) +#define TIM13_BASE (PERIPH_BASE_APB1 + 0x1c00) +#define TIM14_BASE (PERIPH_BASE_APB1 + 0x2000) +/* PERIPH_BASE_APB1 + 0x2400 (0x4000 2400 - 0x4000 27FF): Reserved */ +#define RTC_BASE (PERIPH_BASE_APB1 + 0x2800) +#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00) +#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000) +/* PERIPH_BASE_APB1 + 0x3400 (0x4000 3400 - 0x4000 37FF): Reserved */ +#define SPI2_I2S_BASE (PERIPH_BASE_APB1 + 0x3800) +#define SPI3_I2S_BASE (PERIPH_BASE_APB1 + 0x3c00) +/* PERIPH_BASE_APB1 + 0x4000 (0x4000 4000 - 0x4000 3FFF): Reserved */ +#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400) +#define USART3_BASE (PERIPH_BASE_APB1 + 0x4800) +#define UART4_BASE (PERIPH_BASE_APB1 + 0x4c00) +#define UART5_BASE (PERIPH_BASE_APB1 + 0x5000) +#define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400) +#define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800) +#define USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x5c00) +#define USB_CAN_SRAM_BASE (PERIPH_BASE_APB1 + 0x6000) +#define BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400) +#define BX_CAN2_BASE (PERIPH_BASE_APB1 + 0x6800) +/* PERIPH_BASE_APB1 + 0x6800 (0x4000 6800 - 0x4000 6BFF): Reserved? Typo? */ +#define BACKUP_REGS_BASE (PERIPH_BASE_APB1 + 0x6c00) +#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000) +#define DAC_BASE (PERIPH_BASE_APB1 + 0x7400) +/* PERIPH_BASE_APB1 + 0x7800 (0x4000 7800 - 0x4000 FFFF): Reserved */ + +/* APB2 */ +#define AFIO_BASE (PERIPH_BASE_APB2 + 0x0000) +#define EXTI_BASE (PERIPH_BASE_APB2 + 0x0400) +#define GPIO_PORT_A_BASE (PERIPH_BASE_APB2 + 0x0800) +#define GPIO_PORT_B_BASE (PERIPH_BASE_APB2 + 0x0c00) +#define GPIO_PORT_C_BASE (PERIPH_BASE_APB2 + 0x1000) +#define GPIO_PORT_D_BASE (PERIPH_BASE_APB2 + 0x1400) +#define GPIO_PORT_E_BASE (PERIPH_BASE_APB2 + 0x1800) +#define GPIO_PORT_F_BASE (PERIPH_BASE_APB2 + 0x1c00) +#define GPIO_PORT_G_BASE (PERIPH_BASE_APB2 + 0x2000) +#define ADC1_BASE (PERIPH_BASE_APB2 + 0x2400) +#define ADC2_BASE (PERIPH_BASE_APB2 + 0x2800) +#define TIM1_BASE (PERIPH_BASE_APB2 + 0x2c00) +#define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000) +#define TIM8_BASE (PERIPH_BASE_APB2 + 0x3400) +#define USART1_BASE (PERIPH_BASE_APB2 + 0x3800) +#define ADC3_BASE (PERIPH_BASE_APB2 + 0x3c00) +/* PERIPH_BASE_APB2 + 0x4000 (0x4001 4000 - 0x4001 4FFF): Reserved */ +#define TIM9_BASE (PERIPH_BASE_APB2 + 0x4c00) +#define TIM10_BASE (PERIPH_BASE_APB2 + 0x5000) +#define TIM11_BASE (PERIPH_BASE_APB2 + 0x5400) +/* PERIPH_BASE_APB2 + 0x5800 (0x4001 5800 - 0x4001 7FFF): Reserved */ + +/* AHB */ +#define SDIO_BASE (PERIPH_BASE_AHB + 0x00000) +/* PERIPH_BASE_AHB + 0x0400 (0x4001 8400 - 0x4001 7FFF): Reserved */ +#define DMA1_BASE (PERIPH_BASE_AHB + 0x08000) +#define DMA2_BASE (PERIPH_BASE_AHB + 0x08400) +/* PERIPH_BASE_AHB + 0x8800 (0x4002 0800 - 0x4002 0FFF): Reserved */ +#define RCC_BASE (PERIPH_BASE_AHB + 0x09000) +/* PERIPH_BASE_AHB + 0x9400 (0x4002 1400 - 0x4002 1FFF): Reserved */ +#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB + 0x0a000) +#define CRC_BASE (PERIPH_BASE_AHB + 0x0b000) +/* PERIPH_BASE_AHB + 0xb400 (0x4002 3400 - 0x4002 7FFF): Reserved */ +#define ETHERNET_BASE (PERIPH_BASE_AHB + 0x10000) +/* PERIPH_BASE_AHB + 0x18000 (0x4003 0000 - 0x4FFF FFFF): Reserved */ +#define USB_OTG_FS_BASE (PERIPH_BASE_AHB + 0xffe8000) + +/* PPIB */ +#define DBGMCU_BASE (PPBI_BASE + 0x00042000) + +/* FSMC */ +#define FSMC_BASE (PERIPH_BASE + 0x60000000) + +#endif diff --git a/include/libopencm3/stm32f1/nvic.h b/include/libopencm3/stm32f1/nvic.h new file mode 100644 index 0000000..d29c425 --- /dev/null +++ b/include/libopencm3/stm32f1/nvic.h @@ -0,0 +1,162 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Piotr Esden-Tempski + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_NVIC_H +#define LIBOPENCM3_NVIC_H + +#include +#include + +/* --- NVIC Registers ------------------------------------------------------ */ + +/* ISER: Interrupt Set Enable Registers */ +/* Note: 8 32bit Registers */ +#define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + (iser_id * 4)) + +/* NVIC_BASE + 0x020 (0xE000 E120 - 0xE000 E17F): Reserved */ + +/* ICER: Interrupt Clear Enable Registers */ +/* Note: 8 32bit Registers */ +#define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + (icer_id * 4)) + +/* NVIC_BASE + 0x0A0 (0xE000 E1A0 - 0xE000 E1FF): Reserved */ + +/* ISPR: Interrupt Set Pending Registers */ +/* Note: 8 32bit Registers */ +#define NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + (ispr_id * 4)) + +/* NVIC_BASE + 0x120 (0xE000 E220 - 0xE000 E27F): Reserved */ + +/* ICPR: Interrupt Clear Pending Registers */ +/* Note: 8 32bit Registers */ +#define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + (icpr_id * 4)) + +/* NVIC_BASE + 0x1A0 (0xE000 E2A0 - 0xE00 E2FF): Reserved */ + +/* IABR: Interrupt Active Bit Register */ +/* Note: 8 32bit Registers */ +#define NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + (iabr_id * 4)) + +/* NVIC_BASE + 0x220 (0xE000 E320 - 0xE000 E3FF): Reserved */ + +/* IPR: Interrupt Priority Registers */ +/* Note: 240 8bit Registers */ +#define NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + ipr_id) + +/* STIR: Software Trigger Interrupt Register */ +#define NVIC_STIR MMIO32(STIR_BASE) + +/* --- IRQ channel numbers-------------------------------------------------- */ + +/* Cortex M3 System Interrupts */ +#define NVIC_NMI_IRQ -14 +#define NVIC_HARD_FAULT_IRQ -13 +#define NVIC_MEM_MANAGE_IRQ -12 +#define NVIC_BUS_FAULT_IRQ -11 +#define NVIC_USAGE_FAULT_IRQ -10 +/* irq numbers -6 to -9 are reserved */ +#define NVIC_SV_CALL_IRQ -5 +#define DEBUG_MONITOR_IRQ -4 +/* irq number -3 reserved */ +#define NVIC_PENDSV_IRQ -2 +#define NVIC_SYSTICK_IRQ -1 + +/* User Interrupts */ +#define NVIC_WWDG_IRQ 0 +#define NVIC_PVD_IRQ 1 +#define NVIC_TAMPER_IRQ 2 +#define NVIC_RTC_IRQ 3 +#define NVIC_FLASH_IRQ 4 +#define NVIC_RCC_IRQ 5 +#define NVIC_EXTI0_IRQ 6 +#define NVIC_EXTI1_IRQ 7 +#define NVIC_EXTI2_IRQ 8 +#define NVIC_EXTI3_IRQ 9 +#define NVIC_EXTI4_IRQ 10 +#define NVIC_DMA1_CHANNEL1_IRQ 11 +#define NVIC_DMA1_CHANNEL2_IRQ 12 +#define NVIC_DMA1_CHANNEL3_IRQ 13 +#define NVIC_DMA1_CHANNEL4_IRQ 14 +#define NVIC_DMA1_CHANNEL5_IRQ 15 +#define NVIC_DMA1_CHANNEL6_IRQ 16 +#define NVIC_DMA1_CHANNEL7_IRQ 17 +#define NVIC_ADC1_2_IRQ 18 +#define NVIC_USB_HP_CAN_TX_IRQ 19 +#define NVIC_USB_LP_CAN_RX0_IRQ 20 +#define NVIC_CAN_RX1_IRQ 21 +#define NVIC_CAN_SCE_IRQ 22 +#define NVIC_EXTI9_5_IRQ 23 +#define NVIC_TIM1_BRK_IRQ 24 +#define NVIC_TIM1_UP_IRQ 25 +#define NVIC_TIM1_TRG_COM_IRQ 26 +#define NVIC_TIM1_CC_IRQ 27 +#define NVIC_TIM2_IRQ 28 +#define NVIC_TIM3_IRQ 29 +#define NVIC_TIM4_IRQ 30 +#define NVIC_I2C1_EV_IRQ 31 +#define NVIC_I2C1_ER_IRQ 32 +#define NVIC_I2C2_EV_IRQ 33 +#define NVIC_I2C2_ER_IRQ 34 +#define NVIC_SPI1_IRQ 35 +#define NVIC_SPI2_IRQ 36 +#define NVIC_USART1_IRQ 37 +#define NVIC_USART2_IRQ 38 +#define NVIC_USART3_IRQ 39 +#define NVIC_EXTI15_10_IRQ 40 +#define NVIC_RTC_ALARM_IRQ 41 +#define NVIC_USB_WAKEUP_IRQ 42 +#define NVIC_TIM8_BRK_IRQ 43 +#define NVIC_TIM8_UP_IRQ 44 +#define NVIC_TIM8_TRG_COM_IRQ 45 +#define NVIC_TIM8_CC_IRQ 46 +#define NVIC_ADC3_IRQ 47 +#define NVIC_FSMC_IRQ 48 +#define NVIC_SDIO_IRQ 49 +#define NVIC_TIM5_IRQ 50 +#define NVIC_SPI3_IRQ 51 +#define NVIC_USART4_IRQ 52 +#define NVIC_USART5_IRQ 53 +#define NVIC_TIM6_IRQ 54 +#define NVIC_TIM7_IRQ 55 +#define NVIC_DMA2_CHANNEL1_IRQ 56 +#define NVIC_DMA2_CHANNEL2_IRQ 57 +#define NVIC_DMA2_CHANNEL3_IRQ 58 +#define NVIC_DMA2_CHANNEL4_5_IRQ 59 +#define NVIC_DMA2_CHANNEL5_IRQ 60 +#define NVIC_ETH_IRQ 61 +#define NVIC_ETH_WKUP_IRQ 62 +#define NVIC_CAN2_TX_IRQ 63 +#define NVIC_CAN2_RX0_IRQ 64 +#define NVIC_CAN2_RX1_IRQ 65 +#define NVIC_CAN2_SCE_IRQ 66 +#define NVIC_OTG_FS_IRQ 67 + +/* --- NVIC functions ------------------------------------------------------ */ + +void nvic_enable_irq(u8 irqn); +void nvic_disable_irq(u8 irqn); +u8 nvic_get_pending_irq(u8 irqn); +void nvic_set_pending_irq(u8 irqn); +void nvic_clear_pending_irq(u8 irqn); +u8 nvic_get_active_irq(u8 irqn); +u8 nvic_get_irq_enabled(u8 irqn); +void nvic_set_priority(u8 irqn, u8 priority); +void nvic_generate_software_interrupt(u8 irqn); + +#endif diff --git a/include/libopencm3/stm32f1/otg_fs.h b/include/libopencm3/stm32f1/otg_fs.h new file mode 100644 index 0000000..e1d7a6a --- /dev/null +++ b/include/libopencm3/stm32f1/otg_fs.h @@ -0,0 +1,324 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Gareth McMullin + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_OTG_FS_H +#define LIBOPENCM3_OTG_FS_H + +#include +#include + +/* Core Global Control and Status Registers */ +#define OTG_FS_OTGCTL MMIO32(USB_OTG_FS_BASE + 0x000) +#define OTG_FS_GOTGINT MMIO32(USB_OTG_FS_BASE + 0x004) +#define OTG_FS_GAHBCFG MMIO32(USB_OTG_FS_BASE + 0x008) +#define OTG_FS_GUSBCFG MMIO32(USB_OTG_FS_BASE + 0x00C) +#define OTG_FS_GRSTCTL MMIO32(USB_OTG_FS_BASE + 0x010) +#define OTG_FS_GINTSTS MMIO32(USB_OTG_FS_BASE + 0x014) +#define OTG_FS_GINTMSK MMIO32(USB_OTG_FS_BASE + 0x018) +#define OTG_FS_GRXSTSR MMIO32(USB_OTG_FS_BASE + 0x01C) +#define OTG_FS_GRXSTSP MMIO32(USB_OTG_FS_BASE + 0x020) +#define OTG_FS_GRXFSIZ MMIO32(USB_OTG_FS_BASE + 0x024) +#define OTG_FS_GNPTXFSIZ MMIO32(USB_OTG_FS_BASE + 0x028) +#define OTG_FS_GNPTXSTS MMIO32(USB_OTG_FS_BASE + 0x02C) +#define OTG_FS_GCCFG MMIO32(USB_OTG_FS_BASE + 0x038) +#define OTG_FS_CID MMIO32(USB_OTG_FS_BASE + 0x03C) +#define OTG_FS_HPTXFSIZ MMIO32(USB_OTG_FS_BASE + 0x100) +#define OTG_FS_DIEPTXF(x) MMIO32(USB_OTG_FS_BASE + 0x104 + 4*(x)) + +/* Host-mode Control and Status Registers */ +#define OTG_FS_HCFG MMIO32(USB_OTG_FS_BASE + 0x400) +#define OTG_FS_HFIR MMIO32(USB_OTG_FS_BASE + 0x404) +#define OTG_FS_HFNUM MMIO32(USB_OTG_FS_BASE + 0x408) +#define OTG_FS_HPTXSTS MMIO32(USB_OTG_FS_BASE + 0x410) +#define OTG_FS_HAINT MMIO32(USB_OTG_FS_BASE + 0x414) +#define OTG_FS_HAINTMSK MMIO32(USB_OTG_FS_BASE + 0x418) +#define OTG_FS_HPRT MMIO32(USB_OTG_FS_BASE + 0x440) +#define OTG_FS_HCCHARx MMIO32(USB_OTG_FS_BASE + 0x500) +#define OTG_FS_HCINTx MMIO32(USB_OTG_FS_BASE + 0x508) +#define OTG_FS_HCINTMSKx MMIO32(USB_OTG_FS_BASE + 0x50C) +#define OTG_FS_HCTSIZx MMIO32(USB_OTG_FS_BASE + 0x510) + +/* Device-mode Control and Status Registers */ +#define OTG_FS_DCFG MMIO32(USB_OTG_FS_BASE + 0x800) +#define OTG_FS_DCTL MMIO32(USB_OTG_FS_BASE + 0x804) +#define OTG_FS_DSTS MMIO32(USB_OTG_FS_BASE + 0x808) +#define OTG_FS_DIEPMSK MMIO32(USB_OTG_FS_BASE + 0x810) +#define OTG_FS_DOEPMSK MMIO32(USB_OTG_FS_BASE + 0x814) +#define OTG_FS_DAINT MMIO32(USB_OTG_FS_BASE + 0x818) +#define OTG_FS_DAINTMSK MMIO32(USB_OTG_FS_BASE + 0x81C) +#define OTG_FS_DVBUSDIS MMIO32(USB_OTG_FS_BASE + 0x828) +#define OTG_FS_DVBUSPULSE MMIO32(USB_OTG_FS_BASE + 0x82C) +#define OTG_FS_DIEPEMPMSK MMIO32(USB_OTG_FS_BASE + 0x834) +#define OTG_FS_DIEPCTL0 MMIO32(USB_OTG_FS_BASE + 0x900) +#define OTG_FS_DIEPCTL(x) MMIO32(USB_OTG_FS_BASE + 0x900 + 0x20*(x)) +#define OTG_FS_DOEPCTL0 MMIO32(USB_OTG_FS_BASE + 0xB00) +#define OTG_FS_DOEPCTL(x) MMIO32(USB_OTG_FS_BASE + 0xB00 + 0x20*(x)) +#define OTG_FS_DIEPINT(x) MMIO32(USB_OTG_FS_BASE + 0x908 + 0x20*(x)) +#define OTG_FS_DOEPINT(x) MMIO32(USB_OTG_FS_BASE + 0xB08 + 0x20*(x)) +#define OTG_FS_DIEPTSIZ0 MMIO32(USB_OTG_FS_BASE + 0x910) +#define OTG_FS_DOEPTSIZ0 MMIO32(USB_OTG_FS_BASE + 0xB10) +#define OTG_FS_DIEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + 0x910 + 0x20*(x)) +#define OTG_FS_DTXFSTS(x) MMIO32(USB_OTG_FS_BASE + 0x918 + 0x20*(x)) +#define OTG_FS_DOEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + 0xB10 + 0x20*(x)) + +/* Power and clock gating control and status register */ +#define OTG_FS_PCGCCTL MMIO32(USB_OTG_FS_BASE + 0xE00) + +/* Data FIFO */ +#define OTG_FS_FIFO(x) ((u32*)(USB_OTG_FS_BASE + (((x) + 1) << 12))) + +/* Global CSRs */ +/* OTG_FS AHB configuration register (OTG_FS_GAHBCFG) */ +#define OTG_FS_GAHBCFG_GINT 0x0001 +#define OTG_FS_GAHBCFG_TXFELVL 0x0080 +#define OTG_FS_GAHBCFG_PTXFELVL 0x0100 + +/* OTG_FS USB configuration register (OTG_FS_GUSBCFG) */ +#define OTG_FS_GUSBCFG_TOCAL 0x00000003 +#define OTG_FS_GUSBCFG_SRPCAP 0x00000100 +#define OTG_FS_GUSBCFG_HNPCAP 0x00000200 +#define OTG_FS_GUSBCFG_TRDT_MASK (0xf << 10) +#define OTG_FS_GUSBCFG_TRDT_16BIT (0x5 << 10) +#define OTG_FS_GUSBCFG_TRDT_8BIT (0x9 << 10) +#define OTG_FS_GUSBCFG_NPTXRWEN 0x00004000 +#define OTG_FS_GUSBCFG_FHMOD 0x20000000 +#define OTG_FS_GUSBCFG_FDMOD 0x40000000 +#define OTG_FS_GUSBCFG_CTXPKT 0x80000000 +/* WARNING: not in reference manual */ +#define OTG_FS_GUSBCFG_PHYSEL (1 << 6) + +/* OTG_FS reset register (OTG_FS_GRSTCTL) */ +#define OTG_FS_GRSTCTL_AHBIDL (1 << 31) +/* Bits 30:11 - Reserved */ +#define OTG_FS_GRSTCTL_TXFNUM_MASK (0x1f << 6) +#define OTG_FS_GRSTCTL_TXFFLSH (1 << 5) +#define OTG_FS_GRSTCTL_RXFFLSH (1 << 4) +/* Bit 3 - Reserved */ +#define OTG_FS_GRSTCTL_FCRST (1 << 2) +#define OTG_FS_GRSTCTL_HSRST (1 << 1) +#define OTG_FS_GRSTCTL_CSRST (1 << 0) + +/* OTG_FS interrupt status register (OTG_FS_GINTSTS) */ +#define OTG_FS_GINTSTS_WKUPINT (1 << 31) +#define OTG_FS_GINTSTS_SRQINT (1 << 30) +#define OTG_FS_GINTSTS_DISCINT (1 << 29) +#define OTG_FS_GINTSTS_CIDSCHG (1 << 28) +/* Bit 27 - Reserved */ +#define OTG_FS_GINTSTS_PTXFE (1 << 26) +#define OTG_FS_GINTSTS_HCINT (1 << 25) +#define OTG_FS_GINTSTS_HPRTINT (1 << 24) +/* Bits 23:22 - Reserved */ +#define OTG_FS_GINTSTS_IPXFR (1 << 21) +#define OTG_FS_GINTSTS_INCOMPISOOUT (1 << 21) +#define OTG_FS_GINTSTS_IISOIXFR (1 << 20) +#define OTG_FS_GINTSTS_OEPINT (1 << 19) +#define OTG_FS_GINTSTS_IEPINT (1 << 18) +/* Bits 17:16 - Reserved */ +#define OTG_FS_GINTSTS_EOPF (1 << 15) +#define OTG_FS_GINTSTS_ISOODRP (1 << 14) +#define OTG_FS_GINTSTS_ENUMDNE (1 << 13) +#define OTG_FS_GINTSTS_USBRST (1 << 12) +#define OTG_FS_GINTSTS_USBSUSP (1 << 11) +#define OTG_FS_GINTSTS_ESUSP (1 << 10) +/* Bits 9:8 - Reserved */ +#define OTG_FS_GINTSTS_GONAKEFF (1 << 7) +#define OTG_FS_GINTSTS_GINAKEFF (1 << 6) +#define OTG_FS_GINTSTS_NPTXFE (1 << 5) +#define OTG_FS_GINTSTS_RXFLVL (1 << 4) +#define OTG_FS_GINTSTS_SOF (1 << 3) +#define OTG_FS_GINTSTS_OTGINT (1 << 2) +#define OTG_FS_GINTSTS_MMIS (1 << 1) +#define OTG_FS_GINTSTS_CMOD (1 << 0) + +/* OTG_FS interrupt mask register (OTG_FS_GINTMSK) */ +#define OTG_FS_GINTMSK_MMISM 0x00000002 +#define OTG_FS_GINTMSK_OTGINT 0x00000004 +#define OTG_FS_GINTMSK_SOFM 0x00000008 +#define OTG_FS_GINTMSK_RXFLVLM 0x00000010 +#define OTG_FS_GINTMSK_NPTXFEM 0x00000020 +#define OTG_FS_GINTMSK_GINAKEFFM 0x00000040 +#define OTG_FS_GINTMSK_GONAKEFFM 0x00000080 +#define OTG_FS_GINTMSK_ESUSPM 0x00000400 +#define OTG_FS_GINTMSK_USBSUSPM 0x00000800 +#define OTG_FS_GINTMSK_USBRST 0x00001000 +#define OTG_FS_GINTMSK_ENUMDNEM 0x00002000 +#define OTG_FS_GINTMSK_ISOODRPM 0x00004000 +#define OTG_FS_GINTMSK_EOPFM 0x00008000 +#define OTG_FS_GINTMSK_EPMISM 0x00020000 +#define OTG_FS_GINTMSK_IEPINT 0x00040000 +#define OTG_FS_GINTMSK_OEPINT 0x00080000 +#define OTG_FS_GINTMSK_IISOIXFRM 0x00100000 +#define OTG_FS_GINTMSK_IISOOXFRM 0x00200000 +#define OTG_FS_GINTMSK_IPXFRM 0x00200000 +#define OTG_FS_GINTMSK_PRTIM 0x01000000 +#define OTG_FS_GINTMSK_HCIM 0x02000000 +#define OTG_FS_GINTMSK_PTXFEM 0x04000000 +#define OTG_FS_GINTMSK_CIDSCHGM 0x10000000 +#define OTG_FS_GINTMSK_DISCINT 0x20000000 +#define OTG_FS_GINTMSK_SRQIM 0x40000000 +#define OTG_FS_GINTMSK_WUIM 0x80000000 + +/* OTG_FS Receive Status Pop Register (OTG_FS_GRXSTSP) */ +/* Bits 31:25 - Reserved */ +#define OTG_FS_GRXSTSP_FRMNUM_MASK (0xf << 21) +#define OTG_FS_GRXSTSP_PKTSTS_MASK (0xf << 17) +#define OTG_FS_GRXSTSP_PKTSTS_GOUTNAK (0x1 << 17) +#define OTG_FS_GRXSTSP_PKTSTS_OUT (0x2 << 17) +#define OTG_FS_GRXSTSP_PKTSTS_OUT_COMP (0x3 << 17) +#define OTG_FS_GRXSTSP_PKTSTS_SETUP_COMP (0x4 << 17) +#define OTG_FS_GRXSTSP_PKTSTS_SETUP (0x6 << 17) +#define OTG_FS_GRXSTSP_DPID_MASK (0x3 << 15) +#define OTG_FS_GRXSTSP_DPID_DATA0 (0x0 << 15) +#define OTG_FS_GRXSTSP_DPID_DATA1 (0x2 << 15) +#define OTG_FS_GRXSTSP_DPID_DATA2 (0x1 << 15) +#define OTG_FS_GRXSTSP_DPID_MDATA (0x3 << 15) +#define OTG_FS_GRXSTSP_BCNT_MASK (0x7ff << 4) +#define OTG_FS_GRXSTSP_EPNUM_MASK (0xf << 0) + +/* OTG_FS general core configuration register (OTG_FS_GCCFG) */ +/* Bits 31:21 - Reserved */ +#define OTG_FS_GCCFG_SOFOUTEN (1 << 20) +#define OTG_FS_GCCFG_VBUSBSEN (1 << 19) +#define OTG_FS_GCCFG_VBUSASEN (1 << 18) +/* Bit 17 - Reserved */ +#define OTG_FS_GCCFG_PWRDWN (1 << 16) +/* Bits 15:0 - Reserved */ + + +/* Device-mode CSRs */ +/* OTG_FS device control register (OTG_FS_DCTL) */ +/* Bits 31:12 - Reserved */ +#define OTG_FS_DCTL_POPRGDNE (1 << 11) +#define OTG_FS_DCTL_CGONAK (1 << 10) +#define OTG_FS_DCTL_SGONAK (1 << 9) +#define OTG_FS_DCTL_SGINAK (1 << 8) +#define OTG_FS_DCTL_TCTL_MASK (7 << 4) +#define OTG_FS_DCTL_GONSTS (1 << 3) +#define OTG_FS_DCTL_GINSTS (1 << 2) +#define OTG_FS_DCTL_SDIS (1 << 1) +#define OTG_FS_DCTL_RWUSIG (1 << 0) + +/* OTG_FS device configuration register (OTG_FS_DCFG) */ +#define OTG_FS_DCFG_DSPD 0x0003 +#define OTG_FS_DCFG_NZLSOHSK 0x0004 +#define OTG_FS_DCFG_DAD 0x07F0 +#define OTG_FS_DCFG_PFIVL 0x1800 + +/* OTG_FS Device IN Endpoint Common Interrupt Mask Register (OTG_FS_DIEPMSK) */ +/* Bits 31:10 - Reserved */ +#define OTG_FS_DIEPMSK_BIM (1 << 9) +#define OTG_FS_DIEPMSK_TXFURM (1 << 8) +/* Bit 7 - Reserved */ +#define OTG_FS_DIEPMSK_INEPNEM (1 << 6) +#define OTG_FS_DIEPMSK_INEPNMM (1 << 5) +#define OTG_FS_DIEPMSK_ITTXFEMSK (1 << 4) +#define OTG_FS_DIEPMSK_TOM (1 << 3) +/* Bit 2 - Reserved */ +#define OTG_FS_DIEPMSK_EPDM (1 << 1) +#define OTG_FS_DIEPMSK_XFRCM (1 << 0) + +/* OTG_FS Device OUT Endpoint Common Interrupt Mask Register (OTG_FS_DOEPMSK) */ +/* Bits 31:10 - Reserved */ +#define OTG_FS_DOEPMSK_BOIM (1 << 9) +#define OTG_FS_DOEPMSK_OPEM (1 << 8) +/* Bit 7 - Reserved */ +#define OTG_FS_DOEPMSK_B2BSTUP (1 << 6) +/* Bit 5 - Reserved */ +#define OTG_FS_DOEPMSK_OTEPDM (1 << 4) +#define OTG_FS_DOEPMSK_STUPM (1 << 3) +/* Bit 2 - Reserved */ +#define OTG_FS_DOEPMSK_EPDM (1 << 1) +#define OTG_FS_DOEPMSK_XFRCM (1 << 0) + +/* OTG_FS Device Control IN Endpoint 0 Control Register (OTG_FS_DIEPCTL0) */ +#define OTG_FS_DIEPCTL0_EPENA (1 << 31) +#define OTG_FS_DIEPCTL0_EPDIS (1 << 30) +/* Bits 29:28 - Reserved */ +#define OTG_FS_DIEPCTLX_SD0PID (1 << 28) +#define OTG_FS_DIEPCTL0_SNAK (1 << 27) +#define OTG_FS_DIEPCTL0_CNAK (1 << 26) +#define OTG_FS_DIEPCTL0_TXFNUM_MASK (0xf << 22) +#define OTG_FS_DIEPCTL0_STALL (1 << 21) +/* Bit 20 - Reserved */ +#define OTG_FS_DIEPCTL0_EPTYP_MASK (0x3 << 18) +#define OTG_FS_DIEPCTL0_NAKSTS (1 << 17) +/* Bit 16 - Reserved */ +#define OTG_FS_DIEPCTL0_USBAEP (1 << 15) +/* Bits 14:2 - Reserved */ +#define OTG_FS_DIEPCTL0_MPSIZ_MASK (0x3 << 0) +#define OTG_FS_DIEPCTL0_MPSIZ_64 (0x0 << 0) +#define OTG_FS_DIEPCTL0_MPSIZ_32 (0x1 << 0) +#define OTG_FS_DIEPCTL0_MPSIZ_16 (0x2 << 0) +#define OTG_FS_DIEPCTL0_MPSIZ_8 (0x3 << 0) + +/* OTG_FS Device Control OUT Endpoint 0 Control Register (OTG_FS_DOEPCTL0) */ +#define OTG_FS_DOEPCTL0_EPENA (1 << 31) +#define OTG_FS_DOEPCTL0_EPDIS (1 << 30) +/* Bits 29:28 - Reserved */ +#define OTG_FS_DOEPCTLX_SD0PID (1 << 28) +#define OTG_FS_DOEPCTL0_SNAK (1 << 27) +#define OTG_FS_DOEPCTL0_CNAK (1 << 26) +/* Bits 25:22 - Reserved */ +#define OTG_FS_DOEPCTL0_STALL (1 << 21) +#define OTG_FS_DOEPCTL0_SNPM (1 << 20) +#define OTG_FS_DOEPCTL0_EPTYP_MASK (0x3 << 18) +#define OTG_FS_DOEPCTL0_NAKSTS (1 << 17) +/* Bit 16 - Reserved */ +#define OTG_FS_DOEPCTL0_USBAEP (1 << 15) +/* Bits 14:2 - Reserved */ +#define OTG_FS_DOEPCTL0_MPSIZ_MASK (0x3 << 0) +#define OTG_FS_DOEPCTL0_MPSIZ_64 (0x0 << 0) +#define OTG_FS_DOEPCTL0_MPSIZ_32 (0x1 << 0) +#define OTG_FS_DOEPCTL0_MPSIZ_16 (0x2 << 0) +#define OTG_FS_DOEPCTL0_MPSIZ_8 (0x3 << 0) + +/* OTG_FS Device IN Endpoint Interrupt Register (OTG_FS_DIEPINTx) */ +/* Bits 31:8 - Reserved */ +#define OTG_FS_DIEPINTX_TXFE (1 << 7) +#define OTG_FS_DIEPINTX_INEPNE (1 << 6) +/* Bit 5 - Reserved */ +#define OTG_FS_DIEPINTX_ITTXFE (1 << 4) +#define OTG_FS_DIEPINTX_TOC (1 << 3) +/* Bit 2 - Reserved */ +#define OTG_FS_DIEPINTX_EPDISD (1 << 1) +#define OTG_FS_DIEPINTX_XFRC (1 << 0) + +/* OTG_FS Device IN Endpoint Interrupt Register (OTG_FS_DOEPINTx) */ +/* Bits 31:7 - Reserved */ +#define OTG_FS_DOEPINTX_B2BSTUP (1 << 6) +/* Bit 5 - Reserved */ +#define OTG_FS_DOEPINTX_OTEPDIS (1 << 4) +#define OTG_FS_DOEPINTX_STUP (1 << 3) +/* Bit 2 - Reserved */ +#define OTG_FS_DOEPINTX_EPDISD (1 << 1) +#define OTG_FS_DOEPINTX_XFRC (1 << 0) + +/* OTG_FS Device OUT Endpoint 0 Transfer Size Regsiter (OTG_FS_DOEPTSIZ0) */ +/* Bit 31 - Reserved */ +#define OTG_FS_DIEPSIZ0_STUPCNT_1 (0x1 << 29) +#define OTG_FS_DIEPSIZ0_STUPCNT_2 (0x2 << 29) +#define OTG_FS_DIEPSIZ0_STUPCNT_3 (0x3 << 29) +#define OTG_FS_DIEPSIZ0_STUPCNT_MASK (0x3 << 29) +/* Bits 28:20 - Reserved */ +#define OTG_FS_DIEPSIZ0_PKTCNT (1 << 19) +/* Bits 18:7 - Reserved */ +#define OTG_FS_DIEPSIZ0_XFRSIZ_MASK (0x7f << 0) + +#endif + diff --git a/include/libopencm3/stm32f1/pwr.h b/include/libopencm3/stm32f1/pwr.h new file mode 100644 index 0000000..e5b9804 --- /dev/null +++ b/include/libopencm3/stm32f1/pwr.h @@ -0,0 +1,81 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_PWR_H +#define LIBOPENCM3_PWR_H + +#include +#include + +/* --- PWR registers ------------------------------------------------------- */ + +/* Power control register (PWR_CR) */ +#define PWR_CR MMIO32(POWER_CONTROL_BASE + 0x00) + +/* Power control/status register (PWR_CSR) */ +#define PWR_CSR MMIO32(POWER_CONTROL_BASE + 0x04) + +/* --- PWR_CR values ------------------------------------------------------- */ + +/* DBP: Disable backup domain write protection */ +#define PWR_CR_DBP (1 << 8) + +/* PLS[7:5]: PVD level selection */ +#define PWR_CR_PLS_LSB 5 +#define PWR_CR_PLS_2V2 0x0 +#define PWR_CR_PLS_2V3 0x1 +#define PWR_CR_PLS_2V4 0x2 +#define PWR_CR_PLS_2V5 0x3 +#define PWR_CR_PLS_2V6 0x4 +#define PWR_CR_PLS_2V7 0x5 +#define PWR_CR_PLS_2V8 0x6 +#define PWR_CR_PLS_2V9 0x7 + +/* PVDE: Power voltage detector enable */ +#define PWR_CR_PVDE (1 << 4) + +/* CSBF: Clear standby flag */ +#define PWR_CR_CSBF (1 << 3) + +/* CWUF: Clear wakeup flag */ +#define PWR_CR_CWUF (1 << 2) + +/* PDDS: Power down deepsleep */ +#define PWR_CR_PDDS (1 << 1) + +/* LPDS: Low-power deepsleep */ +#define PWR_CR_LPDS (1 << 0) + +/* --- PWR_CSR values ------------------------------------------------------ */ + +/* EWUP: Enable WKUP pin */ +#define PWR_CSR_EWUP (1 << 8) + +/* PVDO: PVD output */ +#define PWR_CSR_PVDO (1 << 2) + +/* SBF: Standby flag */ +#define PWR_CSR_SBF (1 << 1) + +/* WUF: Wakeup flag */ +#define PWR_CSR_WUF (1 << 0) + +/* --- PWR function prototypes ------------------------------------------- */ + +#endif diff --git a/include/libopencm3/stm32f1/rcc.h b/include/libopencm3/stm32f1/rcc.h new file mode 100644 index 0000000..1072445 --- /dev/null +++ b/include/libopencm3/stm32f1/rcc.h @@ -0,0 +1,417 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * Copyright (C) 2009 Federico Ruiz-Ugalde + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_RCC_H +#define LIBOPENCM3_RCC_H + +#include +#include + +/* Note: Regs/bits marked (**) only exist in "connectivity line" STM32s. */ +/* Note: Regs/bits marked (XX) do NOT exist in "connectivity line" STM32s. */ + +/* --- RCC registers ------------------------------------------------------- */ + +#define RCC_CR MMIO32(RCC_BASE + 0x00) +#define RCC_CFGR MMIO32(RCC_BASE + 0x04) +#define RCC_CIR MMIO32(RCC_BASE + 0x08) +#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x0c) +#define RCC_APB1RSTR MMIO32(RCC_BASE + 0x10) +#define RCC_AHBENR MMIO32(RCC_BASE + 0x14) +#define RCC_APB2ENR MMIO32(RCC_BASE + 0x18) +#define RCC_APB1ENR MMIO32(RCC_BASE + 0x1c) +#define RCC_BDCR MMIO32(RCC_BASE + 0x20) +#define RCC_CSR MMIO32(RCC_BASE + 0x24) +#define RCC_AHBRSTR MMIO32(RCC_BASE + 0x28) /* (**) */ +#define RCC_CFGR2 MMIO32(RCC_BASE + 0x2c) /* (**) */ + +/* --- RCC_CR values ------------------------------------------------------- */ + +#define RCC_CR_PLL3RDY (1 << 29) /* (**) */ +#define RCC_CR_PLL3ON (1 << 28) /* (**) */ +#define RCC_CR_PLL2RDY (1 << 27) /* (**) */ +#define RCC_CR_PLL2ON (1 << 26) /* (**) */ +#define RCC_CR_PLLRDY (1 << 25) +#define RCC_CR_PLLON (1 << 24) +#define RCC_CR_CSSON (1 << 19) +#define RCC_CR_HSEBYP (1 << 18) +#define RCC_CR_HSERDY (1 << 17) +#define RCC_CR_HSEON (1 << 16) +/* HSICAL: [15:8] */ +/* HSITRIM: [7:3] */ +#define RCC_CR_HSIRDY (1 << 1) +#define RCC_CR_HSION (1 << 0) + +/* --- RCC_CFGR values ----------------------------------------------------- */ + +/* MCO: Microcontroller clock output */ +#define RCC_CFGR_MCO_NOCLK 0x0 +#define RCC_CFGR_MCO_SYSCLK 0x4 +#define RCC_CFGR_MCO_HSICLK 0x5 +#define RCC_CFGR_MCO_HSECLK 0x6 +#define RCC_CFGR_RMCO_PLLCLK_DIV2 0x7 +#define RCC_CFGR_MCO_PLL2CLK 0x8 /* (**) */ +#define RCC_CFGR_MCO_PLL3CLK_DIV2 0x9 /* (**) */ +#define RCC_CFGR_MCO_XT1 0xa /* (**) */ +#define RCC_CFGR_MCO_PLL3 0xb /* (**) */ + +/* USBPRE: USB prescaler (RCC_CFGR[22]) */ +#define RCC_CFGR_USBPRE_PLL_CLK_DIV1_5 0x0 +#define RCC_CFGR_USBPRE_PLL_CLK_NODIV 0x1 + +/* OTGFSPRE: USB OTG FS prescaler (RCC_CFGR[22]; only in conn. line STM32s) */ +#define RCC_CFGR_USBPRE_PLL_VCO_CLK_DIV3 0x0 +#define RCC_CFGR_USBPRE_PLL_VCO_CLK_DIV2 0x1 + +/* PLLMUL: PLL multiplication factor */ +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL2 0x0 /* (XX) */ +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL3 0x1 /* (XX) */ +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL4 0x2 +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL5 0x3 +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL6 0x4 +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL7 0x5 +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL8 0x6 +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL9 0x7 +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL10 0x8 /* (XX) */ +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL11 0x9 /* (XX) */ +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL12 0xa /* (XX) */ +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL13 0xb /* (XX) */ +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL14 0xc /* (XX) */ +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL15 0xd /* 0xd: PLL x 15 */ +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL6_5 0xd /* 0xd: PLL x 6.5 for conn. line */ +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL16 0xe /* (XX) */ +// #define PLLMUL_PLL_CLK_MUL16 0xf /* (XX) */ /* Errata? 17? */ + +/* TODO: conn. line differs. */ +/* PLLXTPRE: HSE divider for PLL entry */ +#define RCC_CFGR_PLLXTPRE_HSE_CLK 0x0 +#define RCC_CFGR_PLLXTPRE_HSE_CLK_DIV2 0x1 + +/* PLLSRC: PLL entry clock source */ +#define RCC_CFGR_PLLSRC_HSI_CLK_DIV2 0x0 +#define RCC_CFGR_PLLSRC_HSE_CLK 0x1 +#define RCC_CFGR_PLLSRC_PREDIV1_CLK 0x1 /* On conn. line */ + +/* ADCPRE: ADC prescaler */ +#define RCC_CFGR_ADCPRE_PCLK2_DIV2 0x0 +#define RCC_CFGR_ADCPRE_PCLK2_DIV4 0x1 +#define RCC_CFGR_ADCPRE_PCLK2_DIV6 0x2 +#define RCC_CFGR_ADCPRE_PCLK2_DIV8 0x3 + +/* PPRE2: APB high-speed prescaler (APB2) */ +#define RCC_CFGR_PPRE2_HCLK_NODIV 0x0 +#define RCC_CFGR_PPRE2_HCLK_DIV2 0x4 +#define RCC_CFGR_PPRE2_HCLK_DIV4 0x5 +#define RCC_CFGR_PPRE2_HCLK_DIV8 0x6 +#define RCC_CFGR_PPRE2_HCLK_DIV16 0x7 + +/* PPRE1: APB low-speed prescaler (APB1) */ +#define RCC_CFGR_PPRE1_HCLK_NODIV 0x0 +#define RCC_CFGR_PPRE1_HCLK_DIV2 0x4 +#define RCC_CFGR_PPRE1_HCLK_DIV4 0x5 +#define RCC_CFGR_PPRE1_HCLK_DIV8 0x6 +#define RCC_CFGR_PPRE1_HCLK_DIV16 0x7 + +/* HPRE: AHB prescaler */ +#define RCC_CFGR_HPRE_SYSCLK_NODIV 0x0 +#define RCC_CFGR_HPRE_SYSCLK_DIV2 0x8 +#define RCC_CFGR_HPRE_SYSCLK_DIV4 0x9 +#define RCC_CFGR_HPRE_SYSCLK_DIV8 0xa +#define RCC_CFGR_HPRE_SYSCLK_DIV16 0xb +#define RCC_CFGR_HPRE_SYSCLK_DIV64 0xc +#define RCC_CFGR_HPRE_SYSCLK_DIV128 0xd +#define RCC_CFGR_HPRE_SYSCLK_DIV256 0xe +#define RCC_CFGR_HPRE_SYSCLK_DIV512 0xf + +/* SWS: System clock switch status */ +#define RCC_CFGR_SWS_SYSCLKSEL_HSICLK 0x0 +#define RCC_CFGR_SWS_SYSCLKSEL_HSECLK 0x1 +#define RCC_CFGR_SWS_SYSCLKSEL_PLLCLK 0x2 + +/* SW: System clock switch */ +#define RCC_CFGR_SW_SYSCLKSEL_HSICLK 0x0 +#define RCC_CFGR_SW_SYSCLKSEL_HSECLK 0x1 +#define RCC_CFGR_SW_SYSCLKSEL_PLLCLK 0x2 + +/* --- RCC_CIR values ------------------------------------------------------ */ + +/* Clock security system interrupt clear bit */ +#define RCC_CIR_CSSC (1 << 23) + +/* OSC ready interrupt clear bits */ +#define RCC_CIR_PLL3RDYC (1 << 22) /* (**) */ +#define RCC_CIR_PLL2RDYC (1 << 21) /* (**) */ +#define RCC_CIR_PLLRDYC (1 << 20) +#define RCC_CIR_HSERDYC (1 << 19) +#define RCC_CIR_HSIRDYC (1 << 18) +#define RCC_CIR_LSERDYC (1 << 17) +#define RCC_CIR_LSIRDYC (1 << 16) + +/* OSC ready interrupt enable bits */ +#define RCC_CIR_PLL3RDYIE (1 << 14) /* (**) */ +#define RCC_CIR_PLL2RDYIE (1 << 13) /* (**) */ +#define RCC_CIR_PLLRDYIE (1 << 12) +#define RCC_CIR_HSERDYIE (1 << 11) +#define RCC_CIR_HSIRDYIE (1 << 10) +#define RCC_CIR_LSERDYIE (1 << 9) +#define RCC_CIR_LSIRDYIE (1 << 8) + +/* Clock security system interrupt flag bit */ +#define RCC_CIR_CSSF (1 << 7) + +/* OSC ready interrupt flag bits */ +#define RCC_CIR_PLL3RDYF (1 << 6) /* (**) */ +#define RCC_CIR_PLL2RDYF (1 << 5) /* (**) */ +#define RCC_CIR_PLLRDYF (1 << 4) +#define RCC_CIR_HSERDYF (1 << 3) +#define RCC_CIR_HSIRDYF (1 << 2) +#define RCC_CIR_LSERDYF (1 << 1) +#define RCC_CIR_LSIRDYF (1 << 0) + +/* --- RCC_APB2RSTR values ------------------------------------------------- */ + +#define RCC_APB2RSTR_ADC3RST (1 << 15) /* (XX) */ +#define RCC_APB2RSTR_USART1RST (1 << 14) +#define RCC_APB2RSTR_TIM8RST (1 << 13) /* (XX) */ +#define RCC_APB2RSTR_SPI1RST (1 << 12) +#define RCC_APB2RSTR_TIM1RST (1 << 11) +#define RCC_APB2RSTR_ADC2RST (1 << 10) +#define RCC_APB2RSTR_ADC1RST (1 << 9) +#define RCC_APB2RSTR_IOPGRST (1 << 8) /* (XX) */ +#define RCC_APB2RSTR_IOPFRST (1 << 7) /* (XX) */ +#define RCC_APB2RSTR_IOPERST (1 << 6) +#define RCC_APB2RSTR_IOPDRST (1 << 5) +#define RCC_APB2RSTR_IOPCRST (1 << 4) +#define RCC_APB2RSTR_IOPBRST (1 << 3) +#define RCC_APB2RSTR_IOPARST (1 << 2) +#define RCC_APB2RSTR_AFIORST (1 << 0) + +/* --- RCC_APB1RSTR values ------------------------------------------------- */ + +#define RCC_APB1RSTR_DACRST (1 << 29) +#define RCC_APB1RSTR_PWRRST (1 << 28) +#define RCC_APB1RSTR_BKPRST (1 << 27) +#define RCC_APB1RSTR_CAN2RST (1 << 26) /* (**) */ +#define RCC_APB1RSTR_CAN1RST (1 << 25) /* (**) */ +#define RCC_APB1RSTR_CANRST (1 << 25) /* (XX) Alias for CAN1RST */ +#define RCC_APB1RSTR_USBRST (1 << 23) /* (XX) */ +#define RCC_APB1RSTR_I2C2RST (1 << 22) +#define RCC_APB1RSTR_I2C1RST (1 << 21) +#define RCC_APB1RSTR_USART5RST (1 << 20) +#define RCC_APB1RSTR_USART4RST (1 << 19) +#define RCC_APB1RSTR_USART3RST (1 << 18) +#define RCC_APB1RSTR_USART2RST (1 << 17) +#define RCC_APB1RSTR_SPI3RST (1 << 15) +#define RCC_APB1RSTR_SPI2RST (1 << 14) +#define RCC_APB1RSTR_WWDGRST (1 << 11) +#define RCC_APB1RSTR_TIM7RST (1 << 5) +#define RCC_APB1RSTR_TIM6RST (1 << 4) +#define RCC_APB1RSTR_TIM5RST (1 << 3) +#define RCC_APB1RSTR_TIM4RST (1 << 2) +#define RCC_APB1RSTR_TIM3RST (1 << 1) +#define RCC_APB1RSTR_TIM2RST (1 << 0) + +/* --- RCC_AHBENR values --------------------------------------------------- */ + +#define RCC_AHBENR_ETHMACENRX (1 << 16) +#define RCC_AHBENR_ETHMACENTX (1 << 15) +#define RCC_AHBENR_ETHMACEN (1 << 14) +#define RCC_AHBENR_OTGFSEN (1 << 12) +#define RCC_AHBENR_SDIOEN (1 << 10) +#define RCC_AHBENR_FSMCEN (1 << 8) +#define RCC_AHBENR_CRCEN (1 << 6) +#define RCC_AHBENR_FLITFEN (1 << 4) +#define RCC_AHBENR_SRAMEN (1 << 2) +#define RCC_AHBENR_DMA2EN (1 << 1) +#define RCC_AHBENR_DMA1EN (1 << 0) + +/* --- RCC_APB2ENR values -------------------------------------------------- */ + +#define RCC_APB2ENR_ADC3EN (1 << 15) /* (XX) */ +#define RCC_APB2ENR_USART1EN (1 << 14) +#define RCC_APB2ENR_TIM8EN (1 << 13) /* (XX) */ +#define RCC_APB2ENR_SPI1EN (1 << 12) +#define RCC_APB2ENR_TIM1EN (1 << 11) +#define RCC_APB2ENR_ADC2EN (1 << 10) +#define RCC_APB2ENR_ADC1EN (1 << 9) +#define RCC_APB2ENR_IOPGEN (1 << 8) /* (XX) */ +#define RCC_APB2ENR_IOPFEN (1 << 7) /* (XX) */ +#define RCC_APB2ENR_IOPEEN (1 << 6) +#define RCC_APB2ENR_IOPDEN (1 << 5) +#define RCC_APB2ENR_IOPCEN (1 << 4) +#define RCC_APB2ENR_IOPBEN (1 << 3) +#define RCC_APB2ENR_IOPAEN (1 << 2) +#define RCC_APB2ENR_AFIOEN (1 << 0) + +/* --- RCC_APB1ENR values -------------------------------------------------- */ + +#define RCC_APB1ENR_DACEN (1 << 29) +#define RCC_APB1ENR_PWREN (1 << 28) +#define RCC_APB1ENR_BKPEN (1 << 27) +#define RCC_APB1ENR_CAN2EN (1 << 26) /* (**) */ +#define RCC_APB1ENR_CAN1EN (1 << 25) /* (**) */ +#define RCC_APB1ENR_CANEN (1 << 25) /* (XX) Alias for CAN1EN */ +#define RCC_APB1ENR_USBEN (1 << 23) /* (XX) */ +#define RCC_APB1ENR_I2C2EN (1 << 22) +#define RCC_APB1ENR_I2C1EN (1 << 21) +#define RCC_APB1ENR_USART5EN (1 << 20) +#define RCC_APB1ENR_USART4EN (1 << 19) +#define RCC_APB1ENR_USART3EN (1 << 18) +#define RCC_APB1ENR_USART2EN (1 << 17) +#define RCC_APB1ENR_SPI3EN (1 << 15) +#define RCC_APB1ENR_SPI2EN (1 << 14) +#define RCC_APB1ENR_WWDGEN (1 << 11) +#define RCC_APB1ENR_TIM7EN (1 << 5) +#define RCC_APB1ENR_TIM6EN (1 << 4) +#define RCC_APB1ENR_TIM5EN (1 << 3) +#define RCC_APB1ENR_TIM4EN (1 << 2) +#define RCC_APB1ENR_TIM3EN (1 << 1) +#define RCC_APB1ENR_TIM2EN (1 << 0) + +/* --- RCC_BDCR values ----------------------------------------------------- */ + +#define RCC_BDCR_BDRST (1 << 16) +#define RCC_BDCR_RTCEN (1 << 15) +/* RCC_BDCR[9:8]: RTCSEL */ +#define RCC_BDCR_LSEBYP (1 << 2) +#define RCC_BDCR_LSERDY (1 << 1) +#define RCC_BDCR_LSEON (1 << 0) + +/* --- RCC_CSR values ------------------------------------------------------ */ + +#define RCC_CSR_LPWRRSTF (1 << 31) +#define RCC_CSR_WWDGRSTF (1 << 30) +#define RCC_CSR_IWDGRSTF (1 << 29) +#define RCC_CSR_SFTRSTF (1 << 28) +#define RCC_CSR_PORRSTF (1 << 27) +#define RCC_CSR_PINRSTF (1 << 26) +#define RCC_CSR_RMVF (1 << 24) +#define RCC_CSR_LSIRDY (1 << 1) +#define RCC_CSR_LSION (1 << 0) + +/* --- RCC_AHBRSTR values -------------------------------------------------- */ + +#define RCC_AHBRSTR_ETHMACRST (1 << 14) +#define RCC_AHBRSTR_OTGFSRST (1 << 12) + +/* --- RCC_CFGR2 values ---------------------------------------------------- */ + +/* I2S3SRC: I2S3 clock source */ +#define RCC_CFGR2_I2S3SRC_SYSCLK 0x0 +#define RCC_CFGR2_I2S3SRC_PLL3_VCO_CLK 0x1 + +/* I2S2SRC: I2S2 clock source */ +#define RCC_CFGR2_I2S2SRC_SYSCLK 0x0 +#define RCC_CFGR2_I2S2SRC_PLL3_VCO_CLK 0x1 + +/* PREDIV1SRC: PREDIV1 entry clock source */ +#define RCC_CFGR2_PREDIV1SRC_HSE_CLK 0x0 +#define RCC_CFGR2_PREDIV1SRC_PLL2_CLK 0x1 + +#define RCC_CFGR2_PLL2MUL (1 << 0) +#define RCC_CFGR2_PREDIV2 (1 << 0) +#define RCC_CFGR2_PREDIV1 (1 << 0) + +/* PLL3MUL: PLL3 multiplication factor */ +#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL8 0x6 +#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL9 0x7 +#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL10 0x8 +#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL11 0x9 +#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL12 0xa +#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL13 0xb +#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL14 0xc +#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL16 0xe +#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL20 0xf + +/* PLL2MUL: PLL2 multiplication factor */ +#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL8 0x6 +#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL9 0x7 +#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL10 0x8 +#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL11 0x9 +#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL12 0xa +#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL13 0xb +#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL14 0xc +#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL16 0xe +#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL20 0xf + +/* PREDIV2: PREDIV2 division factor */ +#define RCC_CFGR2_PREDIV2_NODIV 0x0 +#define RCC_CFGR2_PREDIV2_DIV2 0x1 +#define RCC_CFGR2_PREDIV2_DIV3 0x2 +#define RCC_CFGR2_PREDIV2_DIV4 0x3 +#define RCC_CFGR2_PREDIV2_DIV5 0x4 +#define RCC_CFGR2_PREDIV2_DIV6 0x5 +#define RCC_CFGR2_PREDIV2_DIV7 0x6 +#define RCC_CFGR2_PREDIV2_DIV8 0x7 +#define RCC_CFGR2_PREDIV2_DIV9 0x8 +#define RCC_CFGR2_PREDIV2_DIV10 0x9 +#define RCC_CFGR2_PREDIV2_DIV11 0xa +#define RCC_CFGR2_PREDIV2_DIV12 0xb +#define RCC_CFGR2_PREDIV2_DIV13 0xc +#define RCC_CFGR2_PREDIV2_DIV14 0xd +#define RCC_CFGR2_PREDIV2_DIV15 0xe +#define RCC_CFGR2_PREDIV2_DIV16 0xf + +/* --- Variable definitions ------------------------------------------------ */ +extern u32 rcc_ppre1_frequency; +extern u32 rcc_ppre2_frequency; + +/* --- Function prototypes ------------------------------------------------- */ + +typedef enum { + PLL, HSE, HSI, LSE, LSI +} osc_t; + +void rcc_osc_ready_int_clear(osc_t osc); +void rcc_osc_ready_int_enable(osc_t osc); +void rcc_osc_ready_int_disable(osc_t osc); +int rcc_osc_ready_int_flag(osc_t osc); +void rcc_css_int_clear(void); +int rcc_css_int_flag(void); +void rcc_wait_for_osc_ready(osc_t osc); +void rcc_osc_on(osc_t osc); +void rcc_osc_off(osc_t osc); +void rcc_css_enable(void); +void rcc_css_disable(void); +void rcc_osc_bypass_enable(osc_t osc); +void rcc_osc_bypass_disable(osc_t osc); +void rcc_peripheral_enable_clock(volatile u32 *reg, u32 en); +void rcc_peripheral_disable_clock(volatile u32 *reg, u32 en); +void rcc_peripheral_reset(volatile u32 *reg, u32 reset); +void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset); +void rcc_set_sysclk_source(u32 clk); +void rcc_set_pll_multiplication_factor(u32 mul); +void rcc_set_pll_source(u32 pllsrc); +void rcc_set_pllxtpre(u32 pllxtpre); +void rcc_set_adcpre(u32 adcpre); +void rcc_set_ppre2(u32 ppre2); +void rcc_set_ppre1(u32 ppre1); +void rcc_set_hpre(u32 hpre); +void rcc_set_usbpre(u32 usbpre); +u32 rcc_get_system_clock_source(int i); +void rcc_clock_setup_in_hsi_out_64mhz(void); +void rcc_clock_setup_in_hsi_out_48mhz(void); +void rcc_clock_setup_in_hse_8mhz_out_24mhz(void); +void rcc_clock_setup_in_hse_8mhz_out_72mhz(void); +void rcc_clock_setup_in_hse_12mhz_out_72mhz(void); +void rcc_clock_setup_in_hse_16mhz_out_72mhz(void); +void rcc_backupdomain_reset(void); + +#endif diff --git a/include/libopencm3/stm32f1/rtc.h b/include/libopencm3/stm32f1/rtc.h new file mode 100644 index 0000000..b71525e --- /dev/null +++ b/include/libopencm3/stm32f1/rtc.h @@ -0,0 +1,146 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_RTC_H +#define LIBOPENCM3_RTC_H + +#include +#include +#include + +/* --- RTC registers ------------------------------------------------------- */ + +/* RTC control register high (RTC_CRH) */ +#define RTC_CRH MMIO32(RTC_BASE + 0x00) + +/* RTC control register low (RTC_CRL) */ +#define RTC_CRL MMIO32(RTC_BASE + 0x04) + +/* RTC prescaler load register (RTC_PRLH / RTC_PRLL) */ +#define RTC_PRLH MMIO32(RTC_BASE + 0x08) +#define RTC_PRLL MMIO32(RTC_BASE + 0x0c) + +/* RTC prescaler divider register (RTC_DIVH / RTC_DIVL) */ +#define RTC_DIVH MMIO32(RTC_BASE + 0x10) +#define RTC_DIVL MMIO32(RTC_BASE + 0x14) + +/* RTC counter register (RTC_CNTH / RTC_CNTL) */ +#define RTC_CNTH MMIO32(RTC_BASE + 0x18) +#define RTC_CNTL MMIO32(RTC_BASE + 0x1c) + +/* RTC alarm register high (RTC_ALRH / RTC_ALRL) */ +#define RTC_ALRH MMIO32(RTC_BASE + 0x20) +#define RTC_ALRL MMIO32(RTC_BASE + 0x24) + +/* --- RTC_CRH values -------------------------------------------------------*/ + +/* Note: Bits [15:3] are reserved, and forced to 0 by hardware. */ + +/* OWIE: Overflow interrupt enable */ +#define RTC_CRH_OWIE (1 << 2) + +/* ALRIE: Alarm interrupt enable */ +#define RTC_CRH_ALRIE (1 << 1) + +/* SECIE: Second interrupt enable */ +#define RTC_CRH_SECIE (1 << 0) + +/* --- RTC_CRL values -------------------------------------------------------*/ + +/* Note: Bits [15:6] are reserved, and forced to 0 by hardware. */ + +/* RTOFF: RTC operation OFF */ +#define RTC_CRL_RTOFF (1 << 5) + +/* CNF: Configuration flag */ +#define RTC_CRL_CNF (1 << 4) + +/* RSF: Registers synchronized flag */ +#define RTC_CRL_RSF (1 << 3) + +/* OWF: Overflow flag */ +#define RTC_CRL_OWF (1 << 2) + +/* ALRF: Alarm flag */ +#define RTC_CRL_ALRF (1 << 1) + +/* SECF: Second flag */ +#define RTC_CRL_SECF (1 << 0) + +/* --- RTC_PRLH values ------------------------------------------------------*/ + +/* Note: Bits [15:4] are reserved, and forced to 0 by hardware. */ + +/* TODO */ + +/* --- RTC_PRLL values ------------------------------------------------------*/ + +/* TODO */ + +/* --- RTC_DIVH values ------------------------------------------------------*/ + +/* Bits [15:4] are reserved. */ + +/* TODO */ + +/* --- RTC_DIVL values ------------------------------------------------------*/ + +/* TODO */ + +/* --- RTC_CNTH values ------------------------------------------------------*/ + +/* TODO */ + +/* --- RTC_CNTL values ------------------------------------------------------*/ + +/* TODO */ + +/* --- RTC_ALRH values ------------------------------------------------------*/ + +/* TODO */ + +/* --- RTC_ALRL values ------------------------------------------------------*/ + +/* TODO */ + +/* --- Function prototypes --------------------------------------------------*/ + +typedef enum { + RTC_SEC, RTC_ALR, RTC_OW, +} rtcflag_t; + +void rtc_awake_from_off(osc_t clock_source); +void rtc_enter_config_mode(void); +void rtc_exit_config_mode(void); +void rtc_set_alarm_time(u32 alarm_time); +void rtc_enable_alarm(void); +void rtc_disable_alarm(void); +void rtc_set_prescale_val(u32 prescale_val); +u32 rtc_get_counter_val(void); +u32 rtc_get_prescale_div_val(void); +u32 rtc_get_alarm_val(void); +void rtc_set_counter_val(u32 counter_val); +void rtc_interrupt_enable(rtcflag_t flag_val); +void rtc_interrupt_disable(rtcflag_t flag_val); +void rtc_clear_flag(rtcflag_t flag_val); +u32 rtc_check_flag(rtcflag_t flag_val); +void rtc_awake_from_standby(void); +void rtc_auto_awake(osc_t clock_source, u32 prescale_val); + +#endif diff --git a/include/libopencm3/stm32f1/scb.h b/include/libopencm3/stm32f1/scb.h new file mode 100644 index 0000000..9594cf1 --- /dev/null +++ b/include/libopencm3/stm32f1/scb.h @@ -0,0 +1,300 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Piotr Esden-Tempski + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_SCB_H +#define LIBOPENCM3_SCB_H + +#include +#include + +/* --- SCB: Registers ------------------------------------------------------ */ + +/* CPUID: CPUID base register */ +#define SCB_CPUID MMIO32(SCB_BASE + 0x00) + +/* ICSR: Interrupt Control State Register */ +#define SCB_ICSR MMIO32(SCB_BASE + 0x04) + +/* VTOR: Vector Table Offset Register */ +#define SCB_VTOR MMIO32(SCB_BASE + 0x08) + +/* AIRCR: Application Interrupt and Reset Control Register */ +#define SCB_AIRCR MMIO32(SCB_BASE + 0x0C) + +/* SCR: System Control Register */ +#define SCB_SCR MMIO32(SCB_BASE + 0x10) + +/* CCR: Configuration Control Register */ +#define SCB_CCR MMIO32(SCB_BASE + 0x14) + +/* SHP: System Handler Priority Registers */ +/* Note: 12 8bit registers */ +#define SCB_SHPR(shpr_id) MMIO8(SCB_BASE + 0x18 + shpr_id) +#define SCB_SHPR1 MMIO8(SCB_BASE + 0x18 + 1) +#define SCB_SHPR2 MMIO8(SCB_BASE + 0x18 + 2) +#define SCB_SHPR3 MMIO8(SCB_BASE + 0x18 + 3) + +/* SHCSR: System Handler Control and State Register */ +#define SCB_SHCSR MMIO32(SCB_BASE + 0x24) + +/* CFSR: Configurable Fault Status Registers */ +#define SCB_CFSR MMIO32(SCB_BASE + 0x28) + +/* HFSR: Hard Fault Status Register */ +#define SCB_HFSR MMIO32(SCB_BASE + 0x2C) + +/* DFSR: Debug Fault Status Register */ +#define SCB_DFSR MMIO32(SCB_BASE + 0x30) + +/* MMFAR: Memory Manage Fault Address Register */ +#define SCB_MMFAR MMIO32(SCB_BASE + 0x34) + +/* BFAR: Bus Fault Address Register */ +#define SCB_BFAR MMIO32(SCB_BASE + 0x38) + +/* AFSR: Auxiliary Fault Status Register */ +#define SCB_AFSR MMIO32(SCB_BASE + 0x3C) + +/* --- SCB values ---------------------------------------------------------- */ + +/* --- SCB_CPUID values ---------------------------------------------------- */ + +/* Implementer[31:24]: Implementer code */ +#define SCP_CPUID_IMPLEMENTER_LSB 24 +/* Variant[23:20]: Variant number */ +#define SCP_CPUID_VARIANT_LSB 20 +/* Constant[19:16]: Reads as 0xF */ +#define SCP_CPUID_CONSTANT_LSB 16 +/* PartNo[15:4]: Part number of the processor */ +#define SCP_CPUID_PARTNO_LSB 4 +/* Revision[3:0]: Revision number */ +#define SCP_CPUID_REVISION_LSB 0 + +/* --- SCB_ICSR values ----------------------------------------------------- */ + +/* NMIPENDSET: NMI set-pending bit */ +#define SCB_ICSR_NMIPENDSET (1 << 31) +/* Bits [30:29]: reserved - must be kept cleared */ +/* PENDSVSET: PendSV set-pending bit */ +#define SCB_ICSR_PENDSVSET (1 << 28) +/* PENDSVCLR: PendSV clear-pending bit */ +#define SCB_ICSR_PENDSVCLR (1 << 27) +/* PENDSTSET: SysTick exception set-pending bit */ +#define SCB_ICSR_PENDSTSET (1 << 26) +/* PENDSTCLR: SysTick exception clear-pending bit */ +#define SCB_ICSR_PENDSTCLR (1 << 25) +/* Bit 24: reserved - must be kept cleared */ +/* Bit 23: reserved for debug - reads as 0 when not in debug mode */ +/* ISRPENDING: Interrupt pending flag, excluding NMI and Faults */ +#define SCB_ICSR_ISRPENDING (1 << 22) +/* VECTPENDING[21:12] Pending vector */ +#define SCB_ICSR_VECTPENDING_LSB 12 +/* RETOBASE: Return to base level */ +#define SCB_ICSR_RETOBASE (1 << 11) +/* Bits [10:9]: reserved - must be kept cleared */ +/* VECTACTIVE[8:0] Active vector */ +#define SCB_ICSR_VECTACTIVE_LSB 0 + +/* --- SCB_VTOR values ----------------------------------------------------- */ + +/* Bits [31:30]: reserved - must be kept cleared */ +/* TBLOFF[29:9]: Vector table base offset field */ +#define SCB_VTOR_TBLOFF_LSB 9 /* inconsistent datasheet - LSB could be 11 */ + +/* --- SCB_AIRCR values ---------------------------------------------------- */ + +/* VECTKEYSTAT[31:16]/ VECTKEY[31:16] Register key */ +#define SCB_AIRCR_VECTKEYSTAT_LSB 16 +#define SCB_AIRCR_VECTKEY 0x05FA0000 +/* ENDIANESS Data endianness bit */ +#define SCB_AIRCR_ENDIANESS (1 << 15) +/* Bits [14:11]: reserved - must be kept cleared */ +/* PRIGROUP[10:8]: Interrupt priority grouping field */ +#define SCB_AIRCR_PRIGROUP_LSB 8 +#define SCB_AIRCR_PRIGROUP_GROUP16_NOSUB 0x3 +#define SCB_AIRCR_PRIGROUP_GROUP8_SUB2 0x4 +#define SCB_AIRCR_PRIGROUP_GROUP4_SUB4 0x5 +#define SCB_AIRCR_PRIGROUP_GROUP2_SUB8 0x6 +#define SCB_AIRCR_PRIGROUP_NOGROUP_SUB16 0x7 +/* Bits [7:3]: reserved - must be kept cleared */ +/* SYSRESETREQ System reset request */ +#define SCB_AIRCR_SYSRESETREQ (1 << 2) +/* VECTCLRACTIVE */ +#define SCB_AIRCR_VECTCLRACTIVE (1 << 1) +/* VECTRESET */ +#define SCB_AIRCR_VECTRESET (1 << 0) + +/* --- SCB_SCR values ------------------------------------------------------ */ + +/* Bits [31:5]: reserved - must be kept cleared */ +/* SEVEONPEND Send Event on Pending bit */ +#define SCB_SCR_SEVEONPEND (1 << 4) +/* Bit 3: reserved - must be kept cleared */ +/* SLEEPDEEP */ +#define SCB_SCR_SLEEPDEEP (1 << 2) +/* SLEEPONEXIT */ +#define SCB_SCR_SLEEPONEXIT (1 << 1) +/* Bit 0: reserved - must be kept cleared */ + +/* --- SCB_CCR values ------------------------------------------------------ */ + +/* Bits [31:10]: reserved - must be kept cleared */ +/* STKALIGN */ +#define SCB_CCR_STKALIGN (1 << 9) +/* BFHFNMIGN */ +#define SCB_CCR_BFHFNMIGN (1 << 8) +/* Bits [7:5]: reserved - must be kept cleared */ +/* DIV_0_TRP */ +#define SCB_CCR_DIV_0_TRP (1 << 4) +/* UNALIGN_TRP */ +#define SCB_CCR_UNALIGN_TRP (1 << 3) +/* Bit 2: reserved - must be kept cleared */ +/* USERSETMPEND */ +#define SCB_CCR_USERSETMPEND (1 << 1) +/* NONBASETHRDENA */ +#define SCB_CCR_NONBASETHRDENA (1 << 0) + +/* --- SCB_SHPR1 values ---------------------------------------------------- */ + +/* Bits [31:24]: reserved - must be kept cleared */ +/* PRI_6[23:16]: Priority of system handler 6, usage fault */ +#define SCB_SHPR1_PRI_6_LSB 16 +/* PRI_5[15:8]: Priority of system handler 5, bus fault */ +#define SCB_SHPR1_PRI_5_LSB 8 +/* PRI_4[7:0]: Priority of system handler 4, memory management fault */ +#define SCB_SHPR1_PRI_4_LSB 0 + +/* --- SCB_SHPR2 values ---------------------------------------------------- */ + +/* PRI_11[31:24]: Priority of system handler 11, SVCall */ +#define SCB_SHPR2_PRI_11_LSB 24 +/* Bits [23:0]: reserved - must be kept cleared */ + +/* --- SCB_SHPR3 values ---------------------------------------------------- */ + +/* PRI_15[31:24]: Priority of system handler 15, SysTick exception */ +#define SCB_SHPR3_PRI_15_LSB 24 +/* PRI_14[23:16]: Priority of system handler 14, PendSV */ +#define SCB_SHPR3_PRI_14_LSB 16 +/* Bits [15:0]: reserved - must be kept cleared */ + +/* --- SCB_SHCSR values ---------------------------------------------------- */ + +/* Bits [31:19]: reserved - must be kept cleared */ +/* USGFAULTENA: Usage fault enable */ +#define SCB_SHCSR_USGFAULTENA (1 << 18) +/* BUSFAULTENA: Bus fault enable */ +#define SCB_SHCSR_BUSFAULTENA (1 << 17) +/* MEMFAULTENA: Memory management fault enable */ +#define SCB_SHCSR_MEMFAULTENA (1 << 16) +/* SVCALLPENDED: SVC call pending */ +#define SCB_SHCSR_SVCALLPENDED (1 << 15) +/* BUSFAULTPENDED: Bus fault exception pending */ +#define SCB_SHCSR_BUSFAULTPENDED (1 << 14) +/* MEMFAULTPENDED: Memory management fault exception pending */ +#define SCB_SHCSR_MEMFAULTPENDED (1 << 13) +/* USGFAULTPENDED: Usage fault exception pending */ +#define SCB_SHCSR_USGFAULTPENDED (1 << 12) +/* SYSTICKACT: SysTick exception active */ +#define SCB_SHCSR_SYSTICKACT (1 << 11) +/* PENDSVACT: PendSV exception active */ +#define SCB_SHCSR_PENDSVACT (1 << 10) +/* Bit 9: reserved - must be kept cleared */ +/* MONITORACT: Debug monitor active */ +#define SCB_SHCSR_MONITORACT (1 << 8) +/* SVCALLACT: SVC call active */ +#define SCB_SHCSR_SVCALLACT (1 << 7) +/* Bits [6:4]: reserved - must be kept cleared */ +/* USGFAULTACT: Usage fault exception active */ +#define SCB_SHCSR_USGFAULTACT (1 << 3) +/* Bit 2: reserved - must be kept cleared */ +/* BUSFAULTACT: Bus fault exception active */ +#define SCB_SHCSR_BUSFAULTACT (1 << 1) +/* MEMFAULTACT: Memory management fault exception active */ +#define SCB_SHCSR_MEMFAULTACT (1 << 0) + +/* --- SCB_CFSR values ----------------------------------------------------- */ + +/* Bits [31:26]: reserved - must be kept cleared */ +/* DIVBYZERO: Divide by zero usage fault */ +#define SCB_CFSR_DIVBYZERO (1 << 25) +/* UNALIGNED: Unaligned access usage fault */ +#define SCB_CFSR_UNALIGNED (1 << 24) +/* Bits [23:20]: reserved - must be kept cleared */ +/* NOCP: No coprocessor usage fault */ +#define SCB_CFSR_NOCP (1 << 19) +/* INVPC: Invalid PC load usage fault */ +#define SCB_CFSR_INVPC (1 << 18) +/* INVSTATE: Invalid state usage fault */ +#define SCB_CFSR_INVSTATE (1 << 17) +/* UNDEFINSTR: Undefined instruction usage fault */ +#define SCB_CFSR_UNDEFINSTR (1 << 16) +/* BFARVALID: Bus Fault Address Register (BFAR) valid flag */ +#define SCB_CFSR_BFARVALID (1 << 15) +/* Bits [14:13]: reserved - must be kept cleared */ +/* STKERR: Bus fault on stacking for exception entry */ +#define SCB_CFSR_STKERR (1 << 12) +/* UNSTKERR: Bus fault on unstacking for a return from exception */ +#define SCB_CFSR_UNSTKERR (1 << 11) +/* IMPRECISERR: Imprecise data bus error */ +#define SCB_CFSR_IMPRECISERR (1 << 10) +/* PRECISERR: Precise data bus error */ +#define SCB_CFSR_PRECISERR (1 << 9) +/* IBUSERR: Instruction bus error */ +#define SCB_CFSR_IBUSERR (1 << 8) +/* MMARVALID: Memory Management Fault Address Register (MMAR) valid flag */ +#define SCB_CFSR_MMARVALID (1 << 7) +/* Bits [6:5]: reserved - must be kept cleared */ +/* MSTKERR: Memory manager fault on stacking for exception entry */ +#define SCB_CFSR_MSTKERR (1 << 4) +/* MUNSTKERR: Memory manager fault on unstacking for a return from exception */ +#define SCB_CFSR_MUNSTKERR (1 << 3) +/* Bit 2: reserved - must be kept cleared */ +/* DACCVIOL: Data access violation flag */ +#define SCB_CFSR_DACCVIOL (1 << 1) +/* IACCVIOL: Instruction access violation flag */ +#define SCB_CFSR_IACCVIOL (1 << 0) + +/* --- SCB_HFSR values ----------------------------------------------------- */ + +/* DEBUG_VT: reserved for debug use */ +#define SCB_HFSR_DEBUG_VT (1 << 31) +/* FORCED: Forced hard fault */ +#define SCB_HFSR_FORCED (1 << 30) +/* Bits [29:2]: reserved - must be kept cleared */ +/* VECTTBL: Vector table hard fault */ +#define SCB_HFSR_VECTTBL (1 << 1) +/* Bit 0: reserved - must be kept cleared */ + +/* --- SCB_MMFAR values ---------------------------------------------------- */ + +/* MMFAR [31:0]: Memory management fault address */ + +/* --- SCB_BFAR values ----------------------------------------------------- */ + +/* BFAR [31:0]: Bus fault address */ + +/* --- SCB functions ------------------------------------------------------- */ +void scb_reset_core(void); +void scb_reset_system(void); + +/* TODO: */ + +#endif diff --git a/include/libopencm3/stm32f1/spi.h b/include/libopencm3/stm32f1/spi.h new file mode 100644 index 0000000..726310a --- /dev/null +++ b/include/libopencm3/stm32f1/spi.h @@ -0,0 +1,331 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_SPI_H +#define LIBOPENCM3_SPI_H + +#include +#include + +/* Registers can be accessed as 16bit or 32bit values. */ + +/* --- Convenience macros -------------------------------------------------- */ + +#define SPI1 SPI1_BASE +#define SPI2 SPI2_I2S_BASE +#define SPI3 SPI3_I2S_BASE + +/* --- SPI registers ------------------------------------------------------- */ + +/* Control register 1 (SPIx_CR1) */ +#define SPI_CR1(spi_base) MMIO32(spi_base + 0x00) +#define SPI1_CR1 SPI_CR1(SPI1_BASE) +#define SPI2_CR1 SPI_CR1(SPI2_I2S_BASE) +#define SPI3_CR1 SPI_CR1(SPI3_I2S_BASE) + +/* Control register 2 (SPIx_CR2) */ +#define SPI_CR2(spi_base) MMIO32(spi_base + 0x04) +#define SPI1_CR2 SPI_CR2(SPI1_BASE) +#define SPI2_CR2 SPI_CR2(SPI2_I2S_BASE) +#define SPI3_CR2 SPI_CR2(SPI3_I2S_BASE) + +/* Status register (SPIx_SR) */ +#define SPI_SR(spi_base) MMIO32(spi_base + 0x08) +#define SPI1_SR SPI_SR(SPI1_BASE) +#define SPI2_SR SPI_SR(SPI2_I2S_BASE) +#define SPI3_SR SPI_SR(SPI3_I2S_BASE) + +/* Data register (SPIx_DR) */ +#define SPI_DR(spi_base) MMIO32(spi_base + 0x0c) +#define SPI1_DR SPI_DR(SPI1_BASE) +#define SPI2_DR SPI_DR(SPI2_I2S_BASE) +#define SPI3_DR SPI_DR(SPI3_I2S_BASE) + +/* CRC polynomial register (SPIx_CRCPR) */ +/* Note: Not used in I2S mode. */ +#define SPI_CRCPR(spi_base) MMIO32(spi_base + 0x10) +#define SPI1_CRCPR SPI_CRCPR(SPI1_BASE) +#define SPI2_CRCPR SPI_CRCPR(SPI2_I2S_BASE) +#define SPI3_CRCPR SPI_CRCPR(SPI3_I2S_BASE) + +/* RX CRC register (SPIx_RXCRCR) */ +/* Note: Not used in I2S mode. */ +#define SPI_RXCRCR(spi_base) MMIO32(spi_base + 0x14) +#define SPI1_RXCRCR SPI_RXCRCR(SPI1_BASE) +#define SPI2_RXCRCR SPI_RXCRCR(SPI2_I2S_BASE) +#define SPI3_RXCRCR SPI_RXCRCR(SPI3_I2S_BASE) + +/* TX CRC register (SPIx_RXCRCR) */ +/* Note: Not used in I2S mode. */ +#define SPI_TXCRCR(spi_base) MMIO32(spi_base + 0x18) +#define SPI1_TXCRCR SPI_TXCRCR(SPI1_BASE) +#define SPI2_TXCRCR SPI_TXCRCR(SPI2_I2S_BASE) +#define SPI3_TXCRCR SPI_TXCRCR(SPI3_I2S_BASE) + +/* I2S configuration register (SPIx_I2SCFGR) */ +#define SPI_I2SCFGR(spi_base) MMIO32(spi_base + 0x1c) +#define SPI1_I2SCFGR SPI_I2SCFGR(SPI1_BASE) +#define SPI2_I2SCFGR SPI_I2SCFGR(SPI2_I2S_BASE) +#define SPI3_I2SCFGR SPI_I2SCFGR(SPI3_I2S_BASE) + +/* I2S prescaler register (SPIx_I2SPR) */ +#define SPI_I2SPR(spi_base) MMIO32(spi_base + 0x20) +#define SPI1_I2SPR SPI_I2SPR(SPI1_BASE) +#define SPI2_I2SPR SPI_I2SPR(SPI2_I2S_BASE) +#define SPI3_I2SPR SPI_I2SPR(SPI3_I2S_BASE) + +/* --- SPI_CR1 values ------------------------------------------------------ */ + +/* Note: None of the CR1 bits are used in I2S mode. */ + +/* BIDIMODE: Bidirectional data mode enable */ +#define SPI_CR1_BIDIMODE_2LINE_UNIDIR (0 << 15) +#define SPI_CR1_BIDIMODE_1LINE_BIDIR (1 << 15) +#define SPI_CR1_BIDIMODE (1 << 15) + +/* BIDIOE: Output enable in bidirectional mode */ +#define SPI_CR1_BIDIOE (1 << 14) + +/* CRCEN: Hardware CRC calculation enable */ +#define SPI_CR1_CRCEN (1 << 13) + +/* CRCNEXT: Transmit CRC next */ +#define SPI_CR1_CRCNEXT (1 << 12) + +/* DFF: Data frame format */ +#define SPI_CR1_DFF_8BIT (0 << 11) +#define SPI_CR1_DFF_16BIT (1 << 11) +#define SPI_CR1_DFF (1 << 11) + +/* RXONLY: Receive only */ +#define SPI_CR1_RXONLY (1 << 10) + +/* SSM: Software slave management */ +#define SPI_CR1_SSM (1 << 9) + +/* SSI: Internal slave select */ +#define SPI_CR1_SSI (1 << 8) + +/* LSBFIRST: Frame format */ +#define SPI_CR1_MSBFIRST (0 << 7) +#define SPI_CR1_LSBFIRST (1 << 7) + +/* SPE: SPI enable */ +#define SPI_CR1_SPE (1 << 6) + +/* BR[2:0]: Baud rate control */ +#define SPI_CR1_BAUDRATE_FPCLK_DIV_2 (0x00 << 3) +#define SPI_CR1_BAUDRATE_FPCLK_DIV_4 (0x01 << 3) +#define SPI_CR1_BAUDRATE_FPCLK_DIV_8 (0x02 << 3) +#define SPI_CR1_BAUDRATE_FPCLK_DIV_16 (0x03 << 3) +#define SPI_CR1_BAUDRATE_FPCLK_DIV_32 (0x04 << 3) +#define SPI_CR1_BAUDRATE_FPCLK_DIV_64 (0x05 << 3) +#define SPI_CR1_BAUDRATE_FPCLK_DIV_128 (0x06 << 3) +#define SPI_CR1_BAUDRATE_FPCLK_DIV_256 (0x07 << 3) +#define SPI_CR1_BR_FPCLK_DIV_2 0x0 +#define SPI_CR1_BR_FPCLK_DIV_4 0x1 +#define SPI_CR1_BR_FPCLK_DIV_8 0x2 +#define SPI_CR1_BR_FPCLK_DIV_16 0x3 +#define SPI_CR1_BR_FPCLK_DIV_32 0x4 +#define SPI_CR1_BR_FPCLK_DIV_64 0x5 +#define SPI_CR1_BR_FPCLK_DIV_128 0x6 +#define SPI_CR1_BR_FPCLK_DIV_256 0x7 + +/* MSTR: Master selection */ +#define SPI_CR1_MSTR (1 << 2) + +/* CPOL: Clock polarity */ +#define SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE (0 << 1) +#define SPI_CR1_CPOL_CLK_TO_1_WHEN_IDLE (1 << 1) +#define SPI_CR1_CPOL (1 << 1) + +/* CPHA: Clock phase */ +#define SPI_CR1_CPHA_CLK_TRANSITION_1 (0 << 0) +#define SPI_CR1_CPHA_CLK_TRANSITION_2 (1 << 0) +#define SPI_CR1_CPHA (1 << 0) + +/* --- SPI_CR1 values ------------------------------------------------------ */ + +/* Bits [15:8]: Reserved. Forced to 0 by hardware. */ + +/* TXEIE: Tx buffer empty interrupt enable */ +#define SPI_CR2_TXEIE (1 << 7) + +/* RXNEIE: RX buffer not empty interrupt enable */ +#define SPI_CR2_RXNEIE (1 << 6) + +/* ERRIE: Error interrupt enable */ +#define SPI_CR2_ERRIE (1 << 5) + +/* Bits [4:3]: Reserved. Forced to 0 by hardware. */ + +/* SSOE: SS output enable */ +#define SPI_CR2_SSOE (1 << 2) + +/* TXDMAEN: Tx buffer DMA enable */ +#define SPI_CR2_TXDMAEN (1 << 1) + +/* RXDMAEN: Rx buffer DMA enable */ +#define SPI_CR2_RXDMAEN (1 << 0) + +/* --- SPI_SR values ------------------------------------------------------- */ + +/* Bits [15:8]: Reserved. Forced to 0 by hardware. */ + +/* BSY: Busy flag */ +#define SPI_SR_BSY (1 << 7) + +/* OVR: Overrun flag */ +#define SPI_SR_OVR (1 << 6) + +/* MODF: Mode fault */ +#define SPI_SR_MODF (1 << 5) + +/* CRCERR: CRC error flag */ +#define SPI_SR_CRCERR (1 << 4) + +/* UDR: Underrun flag */ +#define SPI_SR_UDR (1 << 3) + +/* CHSIDE: Channel side */ +#define SPI_SR_CHSIDE (1 << 2) + +/* TXE: Transmit buffer empty */ +#define SPI_SR_TXE (1 << 1) + +/* RXNE: Receive buffer not empty */ +#define SPI_SR_RXNE (1 << 0) + +/* --- SPI_SR values ------------------------------------------------------- */ + +/* SPI_DR[15:0]: Data Register. */ + +/* --- SPI_CRCPR values ---------------------------------------------------- */ + +/* SPI_CRCPR [15:0]: CRC Polynomial Register. */ + +/* --- SPI_RXCRCR values --------------------------------------------------- */ + +/* SPI_RXCRCR [15:0]: RX CRC Register. */ + +/* --- SPI_TXCRCR values --------------------------------------------------- */ + +/* SPI_TXCRCR [15:0]: TX CRC Register. */ + +/* --- SPI_I2SCFGR values -------------------------------------------------- */ + +/* Bits [15:12]: Reserved. Forced to 0 by hardware. */ + +/* I2SMOD: I2S mode selection */ +#define SPI_I2SCFGR_I2SMOD (1 << 11) + +/* I2SE: I2S Enable */ +#define SPI_I2SCFGR_I2SE (1 << 10) + +/* I2SCFG[9:8]: I2S configuration mode */ +#define SPI_I2SCFGR_I2SCFG_LSB 8 +#define SPI_I2SCFGR_I2SCFG_SLAVE_TRANSMIT 0x0 +#define SPI_I2SCFGR_I2SCFG_SLAVE_RECEIVE 0x1 +#define SPI_I2SCFGR_I2SCFG_MASTER_TRANSMIT 0x2 +#define SPI_I2SCFGR_I2SCFG_MASTER_RECEIVE 0x3 + +/* PCMSYNC: PCM frame synchronization */ +#define SPI_I2SCFGR_PCMSYNC (1 << 7) + +/* Bit 6: Reserved. Forced to 0 by hardware. */ + +/* I2SSTD[5:4]: I2S standard selection */ +#define SPI_I2SCFGR_I2SSTD_LSB 4 +#define SPI_I2SCFGR_I2SSTD_I2S_PHILLIPS 0x0 +#define SPI_I2SCFGR_I2SSTD_MSB_JUSTIFIED 0x1 +#define SPI_I2SCFGR_I2SSTD_LSB_JUSTIFIED 0x2 +#define SPI_I2SCFGR_I2SSTD_PCM 0x3 + +/* CKPOL: Steady state clock polarity */ +#define SPI_I2SCFGR_CKPOL (1 << 3) + +/* DATLEN[2:1]: Data length to be transferred */ +#define SPI_I2SCFGR_DATLEN_LSB 1 +#define SPI_I2SCFGR_DATLEN_16BIT 0x0 +#define SPI_I2SCFGR_DATLEN_24BIT 0x1 +#define SPI_I2SCFGR_DATLEN_32BIT 0x2 + +/* CHLEN: Channel length */ +#define SPI_I2SCFGR_CHLEN (1 << 0) + +/* --- SPI_I2SPR values ---------------------------------------------------- */ + +/* Bits [15:10]: Reserved. Forced to 0 by hardware. */ + +/* MCKOE: Master clock output enable */ +#define SPI_I2SPR_MCKOE (1 << 9) + +/* ODD: Odd factor for the prescaler */ +#define SPI_I2SPR_ODD (1 << 8) + +/* I2SDIV[7:0]: I2S Linear prescaler */ +/* 0 and 1 are forbidden values */ + +/* --- Function prototypes ------------------------------------------------- */ + +int spi_init_master(u32 spi, u32 br, u32 cpol, u32 cpha, u32 dff, u32 lsbfirst); +void spi_enable(u32 spi); +void spi_disable(u32 spi); +void spi_write(u32 spi, u16 data); +void spi_send(u32 spi, u16 data); +u16 spi_read(u32 spi); +void spi_set_bidirectional_mode(u32 spi); +void spi_set_unidirectional_mode(u32 spi); +void spi_set_bidirectional_receive_only_mode(u32 spi); +void spi_set_bidirectional_transmit_only_mode(u32 spi); +void spi_enable_crc(u32 spi); +void spi_disable_crc(u32 spi); +void spi_set_next_tx_from_buffer(u32 spi); +void spi_set_next_tx_from_crc(u32 spi); +void spi_set_dff_8bit(u32 spi); +void spi_set_dff_16bit(u32 spi); +void spi_set_full_duplex_mode(u32 spi); +void spi_set_receive_only_mode(u32 spi); +void spi_disable_software_slave_management(u32 spi); +void spi_enable_software_slave_management(u32 spi); +void spi_set_nss_high(u32 spi); +void spi_set_nss_low(u32 spi); +void spi_send_lsb_first(u32 spi); +void spi_send_msb_first(u32 spi); +void spi_set_baudrate_prescaler(u32 spi, u8 baudrate); +void spi_set_master_mode(u32 spi); +void spi_set_slave_mode(u32 spi); +void spi_set_clock_polarity_1(u32 spi); +void spi_set_clock_polarity_0(u32 spi); +void spi_set_clock_phase_1(u32 spi); +void spi_set_clock_phase_0(u32 spi); +void spi_enable_tx_buffer_empty_interrupt(u32 spi); +void spi_disable_tx_buffer_empty_interrupt(u32 spi); +void spi_enable_rx_buffer_not_empty_interrupt(u32 spi); +void spi_disable_rx_buffer_not_empty_interrupt(u32 spi); +void spi_enable_error_interrupt(u32 spi); +void spi_disable_error_interrupt(u32 spi); +void spi_enable_ss_output(u32 spi); +void spi_disable_ss_output(u32 spi); +void spi_enable_tx_dma(u32 spi); +void spi_disable_tx_dma(u32 spi); +void spi_enable_rx_dma(u32 spi); +void spi_disable_rx_dma(u32 spi); + +#endif diff --git a/include/libopencm3/stm32f1/systick.h b/include/libopencm3/stm32f1/systick.h new file mode 100644 index 0000000..7c2c9a3 --- /dev/null +++ b/include/libopencm3/stm32f1/systick.h @@ -0,0 +1,82 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_SYSTICK_H +#define LIBOPENCM3_SYSTICK_H + +#include +#include + +/* --- SYSTICK registers --------------------------------------------------- */ + +/* Control and status register (STK_CTRL) */ +#define STK_CTRL MMIO32(SYS_TICK_BASE + 0x00) + +/* reload value register (STK_LOAD) */ +#define STK_LOAD MMIO32(SYS_TICK_BASE + 0x04) + +/* current value register (STK_VAL) */ +#define STK_VAL MMIO32(SYS_TICK_BASE + 0x08) + +/* calibration value register (STK_CALIB) */ +#define STK_CALIB MMIO32(SYS_TICK_BASE + 0x0C) + +/* --- STK_CTRL values ----------------------------------------------------- */ +/* Bits [31:17] Reserved, must be kept cleared. */ +/* COUNTFLAG: */ +#define STK_CTRL_COUNTFLAG (1 << 16) +/* Bits [15:3] Reserved, must be kept cleared. */ +/* CLKSOURCE: Clock source selection */ +#define STK_CTRL_CLKSOURCE (1 << 2) +#define STK_CTRL_CLKSOURCE_LSB 2 +#define STK_CTRL_CLKSOURCE_AHB_DIV8 0 +#define STK_CTRL_CLKSOURCE_AHB 1 +/* TICKINT: SysTick exception request enable */ +#define STK_CTRL_TICKINT (1 << 1) +/* ENABLE: Counter enable */ +#define STK_CTRL_ENABLE (1 << 0) + +/* --- STK_LOAD values ----------------------------------------------------- */ +/* Bits [31:24] Reserved, must be kept cleared. */ +/* RELOAD[23:0]: RELOAD value */ + +/* --- STK_VAL values ------------------------------------------------------ */ +/* Bits [31:24] Reserved, must be kept cleared. */ +/* CURRENT[23:0]: Current counter value */ + +/* --- STK_CALIB values ---------------------------------------------------- */ +/* NOREF: NOREF flag */ +#define STK_CALIB_NOREF (1 << 31) +/* SKEW: SKEW flag */ +#define STK_CALIB_SKEW (1 << 30) +/* Bits [29:24] Reserved, must be kept cleared. */ +/* TENMS[23:0]: Calibration value */ + +/* --- Function Prototypes ------------------------------------------------- */ + +void systick_set_reload(u32 value); +u32 systick_get_value(void); +void systick_set_clocksource(u8 clocksource); +void systick_interrupt_enable(void); +void systick_interrupt_disable(void); +void systick_counter_enable(void); +void systick_counter_disable(void); +u8 systick_get_countflag(void); + +#endif diff --git a/include/libopencm3/stm32f1/timer.h b/include/libopencm3/stm32f1/timer.h new file mode 100644 index 0000000..7b5df86 --- /dev/null +++ b/include/libopencm3/stm32f1/timer.h @@ -0,0 +1,921 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Piotr Esden-Tempski + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_TIMER_H +#define LIBOPENCM3_TIMER_H + +#include +#include + +/* --- Convenience macros -------------------------------------------------- */ + +/* Timer register base adresses (for convenience) */ +#define TIM1 TIM1_BASE +#define TIM2 TIM2_BASE +#define TIM3 TIM3_BASE +#define TIM4 TIM4_BASE +#define TIM5 TIM5_BASE +#define TIM6 TIM6_BASE +#define TIM7 TIM7_BASE +#define TIM8 TIM8_BASE + +/* --- Timer registers ----------------------------------------------------- */ + +/* Control register 1 (TIMx_CR1) */ +#define TIM_CR1(tim_base) MMIO32(tim_base + 0x00) +#define TIM1_CR1 TIM_CR1(TIM1) +#define TIM2_CR1 TIM_CR1(TIM2) +#define TIM3_CR1 TIM_CR1(TIM3) +#define TIM4_CR1 TIM_CR1(TIM4) +#define TIM5_CR1 TIM_CR1(TIM5) +#define TIM6_CR1 TIM_CR1(TIM6) +#define TIM7_CR1 TIM_CR1(TIM7) +#define TIM8_CR1 TIM_CR1(TIM8) + +/* Control register 2 (TIMx_CR2) */ +#define TIM_CR2(tim_base) MMIO32(tim_base + 0x04) +#define TIM1_CR2 TIM_CR2(TIM1) +#define TIM2_CR2 TIM_CR2(TIM2) +#define TIM3_CR2 TIM_CR2(TIM3) +#define TIM4_CR2 TIM_CR2(TIM4) +#define TIM5_CR2 TIM_CR2(TIM5) +#define TIM6_CR2 TIM_CR2(TIM6) +#define TIM7_CR2 TIM_CR2(TIM7) +#define TIM8_CR2 TIM_CR2(TIM8) + +/* Slave mode control register (TIMx_SMCR) */ +#define TIM_SMCR(tim_base) MMIO32(tim_base + 0x08) +#define TIM1_SMCR TIM_SMCR(TIM1) +#define TIM2_SMCR TIM_SMCR(TIM2) +#define TIM3_SMCR TIM_SMCR(TIM3) +#define TIM4_SMCR TIM_SMCR(TIM4) +#define TIM5_SMCR TIM_SMCR(TIM5) +#define TIM8_SMCR TIM_SMCR(TIM8) + +/* DMA/Interrupt enable register (TIMx_DIER) */ +#define TIM_DIER(tim_base) MMIO32(tim_base + 0x0C) +#define TIM1_DIER TIM_DIER(TIM1) +#define TIM2_DIER TIM_DIER(TIM2) +#define TIM3_DIER TIM_DIER(TIM3) +#define TIM4_DIER TIM_DIER(TIM4) +#define TIM5_DIER TIM_DIER(TIM5) +#define TIM6_DIER TIM_DIER(TIM6) +#define TIM7_DIER TIM_DIER(TIM7) +#define TIM8_DIER TIM_DIER(TIM8) + +/* Status register (TIMx_SR) */ +#define TIM_SR(tim_base) MMIO32(tim_base + 0x10) +#define TIM1_SR TIM_SR(TIM1) +#define TIM2_SR TIM_SR(TIM2) +#define TIM3_SR TIM_SR(TIM3) +#define TIM4_SR TIM_SR(TIM4) +#define TIM5_SR TIM_SR(TIM5) +#define TIM6_SR TIM_SR(TIM6) +#define TIM7_SR TIM_SR(TIM7) +#define TIM8_SR TIM_SR(TIM8) + +/* Event generation register (TIMx_EGR) */ +#define TIM_EGR(tim_base) MMIO32(tim_base + 0x14) +#define TIM1_EGR TIM_EGR(TIM1) +#define TIM2_EGR TIM_EGR(TIM2) +#define TIM3_EGR TIM_EGR(TIM3) +#define TIM4_EGR TIM_EGR(TIM4) +#define TIM5_EGR TIM_EGR(TIM5) +#define TIM6_EGR TIM_EGR(TIM6) +#define TIM7_EGR TIM_EGR(TIM7) +#define TIM8_EGR TIM_EGR(TIM8) + +/* Capture/compare mode register 1 (TIMx_CCMR1) */ +#define TIM_CCMR1(tim_base) MMIO32(tim_base + 0x18) +#define TIM1_CCMR1 TIM_CCMR1(TIM1) +#define TIM2_CCMR1 TIM_CCMR1(TIM2) +#define TIM3_CCMR1 TIM_CCMR1(TIM3) +#define TIM4_CCMR1 TIM_CCMR1(TIM4) +#define TIM5_CCMR1 TIM_CCMR1(TIM5) +#define TIM8_CCMR1 TIM_CCMR1(TIM8) + +/* Capture/compare mode register 2 (TIMx_CCMR2) */ +#define TIM_CCMR2(tim_base) MMIO32(tim_base + 0x1C) +#define TIM1_CCMR2 TIM_CCMR2(TIM1) +#define TIM2_CCMR2 TIM_CCMR2(TIM2) +#define TIM3_CCMR2 TIM_CCMR2(TIM3) +#define TIM4_CCMR2 TIM_CCMR2(TIM4) +#define TIM5_CCMR2 TIM_CCMR2(TIM5) +#define TIM8_CCMR2 TIM_CCMR2(TIM8) + +/* Capture/compare enable register (TIMx_CCER) */ +#define TIM_CCER(tim_base) MMIO32(tim_base + 0x20) +#define TIM1_CCER TIM_CCER(TIM1) +#define TIM2_CCER TIM_CCER(TIM2) +#define TIM3_CCER TIM_CCER(TIM3) +#define TIM4_CCER TIM_CCER(TIM4) +#define TIM5_CCER TIM_CCER(TIM5) +#define TIM8_CCER TIM_CCER(TIM8) + +/* Counter (TIMx_CNT) */ +#define TIM_CNT(tim_base) MMIO32(tim_base + 0x24) +#define TIM1_CNT TIM_CNT(TIM1) +#define TIM2_CNT TIM_CNT(TIM2) +#define TIM3_CNT TIM_CNT(TIM3) +#define TIM4_CNT TIM_CNT(TIM4) +#define TIM5_CNT TIM_CNT(TIM5) +#define TIM6_CNT TIM_CNT(TIM6) +#define TIM7_CNT TIM_CNT(TIM7) +#define TIM8_CNT TIM_CNT(TIM8) + +/* Prescaler (TIMx_PSC) */ +#define TIM_PSC(tim_base) MMIO32(tim_base + 0x28) +#define TIM1_PSC TIM_PSC(TIM1) +#define TIM2_PSC TIM_PSC(TIM2) +#define TIM3_PSC TIM_PSC(TIM3) +#define TIM4_PSC TIM_PSC(TIM4) +#define TIM5_PSC TIM_PSC(TIM5) +#define TIM6_PSC TIM_PSC(TIM6) +#define TIM7_PSC TIM_PSC(TIM7) +#define TIM8_PSC TIM_PSC(TIM8) + +/* Auto-reload register (TIMx_ARR) */ +#define TIM_ARR(tim_base) MMIO32(tim_base + 0x2C) +#define TIM1_ARR TIM_ARR(TIM1) +#define TIM2_ARR TIM_ARR(TIM2) +#define TIM3_ARR TIM_ARR(TIM3) +#define TIM4_ARR TIM_ARR(TIM4) +#define TIM5_ARR TIM_ARR(TIM5) +#define TIM6_ARR TIM_ARR(TIM6) +#define TIM7_ARR TIM_ARR(TIM7) +#define TIM8_ARR TIM_ARR(TIM8) + +/* Repetition counter register (TIMx_RCR) */ +#define TIM_RCR(tim_base) MMIO32(tim_base + 0x30) +#define TIM1_RCR TIM_RCR(TIM1) +#define TIM8_RCR TIM_RCR(TIM8) + +/* Capture/compare register 1 (TIMx_CCR1) */ +#define TIM_CCR1(tim_base) MMIO32(tim_base + 0x34) +#define TIM1_CCR1 TIM_CCR1(TIM1) +#define TIM2_CCR1 TIM_CCR1(TIM2) +#define TIM3_CCR1 TIM_CCR1(TIM3) +#define TIM4_CCR1 TIM_CCR1(TIM4) +#define TIM5_CCR1 TIM_CCR1(TIM5) +#define TIM8_CCR1 TIM_CCR1(TIM8) + +/* Capture/compare register 2 (TIMx_CCR2) */ +#define TIM_CCR2(tim_base) MMIO32(tim_base + 0x38) +#define TIM1_CCR2 TIM_CCR2(TIM1) +#define TIM2_CCR2 TIM_CCR2(TIM2) +#define TIM3_CCR2 TIM_CCR2(TIM3) +#define TIM4_CCR2 TIM_CCR2(TIM4) +#define TIM5_CCR2 TIM_CCR2(TIM5) +#define TIM8_CCR2 TIM_CCR2(TIM8) + +/* Capture/compare register 3 (TIMx_CCR3) */ +#define TIM_CCR3(tim_base) MMIO32(tim_base + 0x3C) +#define TIM1_CCR3 TIM_CCR3(TIM1) +#define TIM2_CCR3 TIM_CCR3(TIM2) +#define TIM3_CCR3 TIM_CCR3(TIM3) +#define TIM4_CCR3 TIM_CCR3(TIM4) +#define TIM5_CCR3 TIM_CCR3(TIM5) +#define TIM8_CCR3 TIM_CCR3(TIM8) + +/* Capture/compare register 4 (TIMx_CCR4) */ +#define TIM_CCR4(tim_base) MMIO32(tim_base + 0x40) +#define TIM1_CCR4 TIM_CCR4(TIM1) +#define TIM2_CCR4 TIM_CCR4(TIM2) +#define TIM3_CCR4 TIM_CCR4(TIM3) +#define TIM4_CCR4 TIM_CCR4(TIM4) +#define TIM5_CCR4 TIM_CCR4(TIM5) +#define TIM8_CCR4 TIM_CCR4(TIM8) + +/* Break and dead-time register (TIMx_BDTR) */ +#define TIM_BDTR(tim_base) MMIO32(tim_base + 0x44) +#define TIM1_BDTR TIM_BDTR(TIM1) +#define TIM8_BDTR TIM_BDTR(TIM8) + +/* DMA control register (TIMx_DCR) */ +#define TIM_DCR(tim_base) MMIO32(tim_base + 0x48) +#define TIM1_DCR TIM_DCR(TIM1) +#define TIM2_DCR TIM_DCR(TIM2) +#define TIM3_DCR TIM_DCR(TIM3) +#define TIM4_DCR TIM_DCR(TIM4) +#define TIM5_DCR TIM_DCR(TIM5) +#define TIM8_DCR TIM_DCR(TIM8) + +/* DMA address for full transfer (TIMx_DMAR) */ +#define TIM_DMAR(tim_base) MMIO32(tim_base + 0x4C) +#define TIM1_DMAR TIM_DMAR(TIM1) +#define TIM2_DMAR TIM_DMAR(TIM2) +#define TIM3_DMAR TIM_DMAR(TIM3) +#define TIM4_DMAR TIM_DMAR(TIM4) +#define TIM5_DMAR TIM_DMAR(TIM5) +#define TIM8_DMAR TIM_DMAR(TIM8) + +/* --- TIMx_CR1 values ----------------------------------------------------- */ + +/* CKD[1:0]: Clock division */ +#define TIM_CR1_CKD_CK_INT (0x0 << 8) +#define TIM_CR1_CKD_CK_INT_MUL_2 (0x1 << 8) +#define TIM_CR1_CKD_CK_INT_MUL_4 (0x2 << 8) +#define TIM_CR1_CKD_CK_INT_MASK (0x3 << 8) + +/* ARPE: Auto-reload preload enable */ +#define TIM_CR1_ARPE (1 << 7) + +/* CMS[1:0]: Center-aligned mode selection */ +#define TIM_CR1_CMS_EDGE (0x0 << 5) +#define TIM_CR1_CMS_CENTER_1 (0x1 << 5) +#define TIM_CR1_CMS_CENTER_2 (0x2 << 5) +#define TIM_CR1_CMS_CENTER_3 (0x3 << 5) +#define TIM_CR1_CMS_MASK (0x3 << 5) + +/* DIR: Direction */ +#define TIM_CR1_DIR_UP (0 << 4) +#define TIM_CR1_DIR_DOWN (1 << 4) + +/* OPM: One pulse mode */ +#define TIM_CR1_OPM (1 << 3) + +/* URS: Update request source */ +#define TIM_CR1_URS (1 << 2) + +/* UDIS: Update disable */ +#define TIM_CR1_UDIS (1 << 1) + +/* CEN: Counter enable */ +#define TIM_CR1_CEN (1 << 0) + +/* --- TIMx_CR2 values ----------------------------------------------------- */ + +/* OIS4: Output idle state 4 (OC4 output) */ +#define TIM_CR2_OIS4 (1 << 14) + +/* OIS3N: Output idle state 3 (OC3N output) */ +#define TIM_CR2_OIS3N (1 << 13) + +/* OIS3: Output idle state 3 (OC3 output) */ +#define TIM_CR2_OIS3 (1 << 12) + +/* OIS2N: Output idle state 2 (OC2N output) */ +#define TIM_CR2_OIS2N (1 << 11) + +/* OIS2: Output idle state 2 (OC2 output) */ +#define TIM_CR2_OIS2 (1 << 10) + +/* OIS1N: Output idle state 1 (OC1N output) */ +#define TIM_CR2_OIS1N (1 << 9) + +/* OIS1: Output idle state 1 (OC1 output) */ +#define TIM_CR2_OIS1 (1 << 8) +#define TIM_CR2_OIS_MASK (0x7f << 8) + +/* TI1S: TI1 selection */ +#define TIM_CR2_TI1S (1 << 7) + +/* MMS[2:0]: Master mode selection */ +#define TIM_CR2_MMS_RESET (0x0 << 4) +#define TIM_CR2_MMS_ENABLE (0x1 << 4) +#define TIM_CR2_MMS_UPDATE (0x2 << 4) +#define TIM_CR2_MMS_COMPARE_PULSE (0x3 << 4) +#define TIM_CR2_MMS_COMPARE_OC1REF (0x4 << 4) +#define TIM_CR2_MMS_COMPARE_OC2REF (0x5 << 4) +#define TIM_CR2_MMS_COMPARE_OC3REF (0x6 << 4) +#define TIM_CR2_MMS_COMPARE_OC4REF (0x7 << 4) +#define TIM_CR2_MMS_MASK (0x7 << 4) + +/* CCDS: Capture/compare DMA selection */ +#define TIM_CR2_CCDS (1 << 3) + +/* CCUS: Capture/compare control update selection */ +#define TIM_CR2_CCUS (1 << 2) + +/* CCPC: Capture/compare preload control */ +#define TIM_CR2_CCPC (1 << 0) + +/* --- TIMx_SMCR values ---------------------------------------------------- */ + +/* ETP: External trigger polarity */ +#define TIM_SMCR_ETP (1 << 15) + +/* ECE: External clock enable */ +#define TIM_SMCR_ECE (1 << 14) + +/* ETPS[1:0]: External trigger prescaler */ +#define TIM_SMCR_ETPS_OFF (0x0 << 12) +#define TIM_SMCR_ETPS_ETRP_DIV_2 (0x1 << 12) +#define TIM_SMCR_ETPS_ETRP_DIV_4 (0x2 << 12) +#define TIM_SMCR_ETPS_ETRP_DIV_8 (0x3 << 12) +#define TIM_SMCR_ETPS_MASK (0X3 << 12) + +/* ETF[3:0]: External trigger filter */ +#define TIM_SMCR_ETF_OFF (0x0 << 8) +#define TIM_SMCR_ETF_CK_INT_N_2 (0x1 << 8) +#define TIM_SMCR_ETF_CK_INT_N_4 (0x2 << 8) +#define TIM_SMCR_ETF_CK_INT_N_8 (0x3 << 8) +#define TIM_SMCR_ETF_DTS_DIV_2_N_6 (0x4 << 8) +#define TIM_SMCR_ETF_DTS_DIV_2_N_8 (0x5 << 8) +#define TIM_SMCR_ETF_DTS_DIV_4_N_6 (0x6 << 8) +#define TIM_SMCR_ETF_DTS_DIV_4_N_8 (0x7 << 8) +#define TIM_SMCR_ETF_DTS_DIV_8_N_6 (0x8 << 8) +#define TIM_SMCR_ETF_DTS_DIV_8_N_8 (0x9 << 8) +#define TIM_SMCR_ETF_DTS_DIV_16_N_5 (0xA << 8) +#define TIM_SMCR_ETF_DTS_DIV_16_N_6 (0xB << 8) +#define TIM_SMCR_ETF_DTS_DIV_16_N_8 (0xC << 8) +#define TIM_SMCR_ETF_DTS_DIV_32_N_5 (0xD << 8) +#define TIM_SMCR_ETF_DTS_DIV_32_N_6 (0xE << 8) +#define TIM_SMCR_ETF_DTS_DIV_32_N_8 (0xF << 8) +#define TIM_SMCR_ETF_MASK (0xF << 8) + +/* MSM: Master/slave mode */ +#define TIM_SMCR_MSM (1 << 7) + +/* TS[2:0]: Trigger selection */ +#define TIM_SMCR_TS_ITR0 (0x0 << 4) +#define TIM_SMCR_TS_ITR1 (0x1 << 4) +#define TIM_SMCR_TS_ITR2 (0x2 << 4) +#define TIM_SMCR_TS_ITR3 (0x3 << 4) +#define TIM_SMCR_TS_IT1F_ED (0x4 << 4) +#define TIM_SMCR_TS_IT1FP1 (0x5 << 4) +#define TIM_SMCR_TS_IT1FP2 (0x6 << 4) +#define TIM_SMCR_TS_ETRF (0x7 << 4) +#define TIM_SMCR_TS_MASK (0x7 << 4) + +/* SMS[2:0]: Slave mode selection */ +#define TIM_SMCR_SMS_OFF (0x0 << 0) +#define TIM_SMCR_SMS_EM1 (0x1 << 0) +#define TIM_SMCR_SMS_EM2 (0x2 << 0) +#define TIM_SMCR_SMS_EM3 (0x3 << 0) +#define TIM_SMCR_SMS_RM (0x4 << 0) +#define TIM_SMCR_SMS_GM (0x5 << 0) +#define TIM_SMCR_SMS_TM (0x6 << 0) +#define TIM_SMCR_SMS_ECM1 (0x7 << 0) +#define TIM_SMCR_SMS_MASK (0x7 << 0) + +/* --- TIMx_DIER values ---------------------------------------------------- */ + +/* TDE: Trigger DMA request enable */ +#define TIM_DIER_TDE (1 << 14) + +/* COMDE: COM DMA request enable */ +#define TIM_DIER_COMDE (1 << 13) + +/* CC4DE: Capture/Compare 4 DMA request enable */ +#define TIM_DIER_CC4DE (1 << 12) + +/* CC3DE: Capture/Compare 3 DMA request enable */ +#define TIM_DIER_CC3DE (1 << 11) + +/* CC2DE: Capture/Compare 2 DMA request enable */ +#define TIM_DIER_CC2DE (1 << 10) + +/* CC1DE: Capture/Compare 1 DMA request enable */ +#define TIM_DIER_CC1DE (1 << 9) + +/* UDE: Update DMA request enable */ +#define TIM_DIER_UDE (1 << 8) + +/* BIE: Break interrupt enable */ +#define TIM_DIER_BIE (1 << 7) + +/* TIE: Trigger interrupt enable */ +#define TIM_DIER_TIE (1 << 6) + +/* COMIE: COM interrupt enable */ +#define TIM_DIER_COMIE (1 << 5) + +/* CC4IE: Capture/compare 4 interrupt enable */ +#define TIM_DIER_CC4IE (1 << 4) + +/* CC3IE: Capture/compare 3 interrupt enable */ +#define TIM_DIER_CC3IE (1 << 3) + +/* CC2IE: Capture/compare 2 interrupt enable */ +#define TIM_DIER_CC2IE (1 << 2) + +/* CC1IE: Capture/compare 1 interrupt enable */ +#define TIM_DIER_CC1IE (1 << 1) + +/* UIE: Update interrupt enable */ +#define TIM_DIER_UIE (1 << 0) + +/* --- TIMx_SR values ------------------------------------------------------ */ + +/* CC4OF: Capture/compare 4 overcapture flag */ +#define TIM_SR_CC4OF (1 << 12) + +/* CC3OF: Capture/compare 3 overcapture flag */ +#define TIM_SR_CC3OF (1 << 11) + +/* CC2OF: Capture/compare 2 overcapture flag */ +#define TIM_SR_CC2OF (1 << 10) + +/* CC1OF: Capture/compare 1 overcapture flag */ +#define TIM_SR_CC1OF (1 << 9) + +/* BIF: Break interrupt flag */ +#define TIM_SR_BIF (1 << 7) + +/* TIF: Trigger interrupt flag */ +#define TIM_SR_TIF (1 << 6) + +/* COMIF: COM interrupt flag */ +#define TIM_SR_COMIF (1 << 5) + +/* CC4IF: Capture/compare 4 interrupt flag */ +#define TIM_SR_CC4IF (1 << 4) + +/* CC3IF: Capture/compare 3 interrupt flag */ +#define TIM_SR_CC3IF (1 << 3) + +/* CC2IF: Capture/compare 2 interrupt flag */ +#define TIM_SR_CC2IF (1 << 2) + +/* CC1IF: Capture/compare 1 interrupt flag */ +#define TIM_SR_CC1IF (1 << 1) + +/* UIF: Update interrupt flag */ +#define TIM_SR_UIF (1 << 0) + +/* --- TIMx_EGR values ----------------------------------------------------- */ + +/* BG: Break generation */ +#define TIM_EGR_BG (1 << 7) + +/* TG: Trigger generation */ +#define TIM_EGR_TG (1 << 6) + +/* COMG: Capture/compare control update generation */ +#define TIM_EGR_COMG (1 << 5) + +/* CC4G: Capture/compare 4 generation */ +#define TIM_EGR_CC4G (1 << 4) + +/* CC3G: Capture/compare 3 generation */ +#define TIM_EGR_CC3G (1 << 3) + +/* CC2G: Capture/compare 2 generation */ +#define TIM_EGR_CC2G (1 << 2) + +/* CC1G: Capture/compare 1 generation */ +#define TIM_EGR_CC1G (1 << 1) + +/* UG: Update generation */ +#define TIM_EGR_UG (1 << 0) + +/* --- TIMx_CCMR1 values --------------------------------------------------- */ + +/* --- Output compare mode --- */ + +/* OC2CE: Output compare 2 clear enable */ +#define TIM_CCMR1_OC2CE (1 << 15) + +/* OC2M[2:0]: Output compare 2 mode */ +#define TIM_CCMR1_OC2M_FROZEN (0x0 << 12) +#define TIM_CCMR1_OC2M_ACTIVE (0x1 << 12) +#define TIM_CCMR1_OC2M_INACTIVE (0x2 << 12) +#define TIM_CCMR1_OC2M_TOGGLE (0x3 << 12) +#define TIM_CCMR1_OC2M_FORCE_LOW (0x4 << 12) +#define TIM_CCMR1_OC2M_FORCE_HIGH (0x5 << 12) +#define TIM_CCMR1_OC2M_PWM1 (0x6 << 12) +#define TIM_CCMR1_OC2M_PWM2 (0x7 << 12) +#define TIM_CCMR1_OC2M_MASK (0x7 << 12) + +/* OC2PE: Output compare 2 preload enable */ +#define TIM_CCMR1_OC2PE (1 << 11) + +/* OC2FE: Output compare 2 fast enable */ +#define TIM_CCMR1_OC2FE (1 << 10) + +/* CC2S[1:0]: Capture/compare 2 selection */ +/* Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in + * TIMx_CCER). */ +#define TIM_CCMR1_CC2S_OUT (0x0 << 8) +#define TIM_CCMR1_CC2S_IN_TI2 (0x1 << 8) +#define TIM_CCMR1_CC2S_IN_TI1 (0x2 << 8) +#define TIM_CCMR1_CC2S_IN_TRC (0x3 << 8) +#define TIM_CCMR1_CC2S_MASK (0x3 << 8) + +/* OC1CE: Output compare 1 clear enable */ +#define TIM_CCMR1_OC1CE (1 << 7) + +/* OC1M[2:0]: Output compare 1 mode */ +#define TIM_CCMR1_OC1M_FROZEN (0x0 << 4) +#define TIM_CCMR1_OC1M_ACTIVE (0x1 << 4) +#define TIM_CCMR1_OC1M_INACTIVE (0x2 << 4) +#define TIM_CCMR1_OC1M_TOGGLE (0x3 << 4) +#define TIM_CCMR1_OC1M_FORCE_LOW (0x4 << 4) +#define TIM_CCMR1_OC1M_FORCE_HIGH (0x5 << 4) +#define TIM_CCMR1_OC1M_PWM1 (0x6 << 4) +#define TIM_CCMR1_OC1M_PWM2 (0x7 << 4) +#define TIM_CCMR1_OC1M_MASK (0x7 << 4) + +/* OC1PE: Output compare 1 preload enable */ +#define TIM_CCMR1_OC1PE (1 << 3) + +/* OC1FE: Output compare 1 fast enable */ +#define TIM_CCMR1_OC1FE (1 << 2) + +/* CC1S[1:0]: Capture/compare 1 selection */ +/* Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in + * TIMx_CCER). */ +#define TIM_CCMR1_CC1S_OUT (0x0 << 0) +#define TIM_CCMR1_CC1S_IN_TI2 (0x1 << 0) +#define TIM_CCMR1_CC1S_IN_TI1 (0x2 << 0) +#define TIM_CCMR1_CC1S_IN_TRC (0x3 << 0) +#define TIM_CCMR1_CC1S_MASK (0x3 << 0) + +/* --- Input capture mode --- */ + +/* IC2F[3:0]: Input capture 2 filter */ +#define TIM_CCMR1_IC2F_OFF (0x0 << 12) +#define TIM_CCMR1_IC2F_CK_INT_N_2 (0x1 << 12) +#define TIM_CCMR1_IC2F_CK_INT_N_4 (0x2 << 12) +#define TIM_CCMR1_IC2F_CK_INT_N_8 (0x3 << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_2_N_6 (0x4 << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_2_N_8 (0x5 << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_4_N_6 (0x6 << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_4_N_8 (0x7 << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_8_N_6 (0x8 << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_8_N_8 (0x9 << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_16_N_5 (0xA << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_16_N_6 (0xB << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_16_N_8 (0xC << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_32_N_5 (0xD << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_32_N_6 (0xE << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_32_N_8 (0xF << 12) +#define TIM_CCMR1_IC2F_MASK (0xF << 12) + +/* IC2PSC[1:0]: Input capture 2 prescaler */ +#define TIM_CCMR1_IC2PSC_OFF (0x0 << 10) +#define TIM_CCMR1_IC2PSC_2 (0x1 << 10) +#define TIM_CCMR1_IC2PSC_4 (0x2 << 10) +#define TIM_CCMR1_IC2PSC_8 (0x3 << 10) +#define TIM_CCMR1_IC2PSC_MASK (0x3 << 10) + +/* IC1F[3:0]: Input capture 1 filter */ +#define TIM_CCMR1_IC1F_OFF (0x0 << 4) +#define TIM_CCMR1_IC1F_CK_INT_N_2 (0x1 << 4) +#define TIM_CCMR1_IC1F_CK_INT_N_4 (0x2 << 4) +#define TIM_CCMR1_IC1F_CK_INT_N_8 (0x3 << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_2_N_6 (0x4 << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_2_N_8 (0x5 << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_4_N_6 (0x6 << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_4_N_8 (0x7 << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_8_N_6 (0x8 << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_8_N_8 (0x9 << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_16_N_5 (0xA << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_16_N_6 (0xB << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_16_N_8 (0xC << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_32_N_5 (0xD << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_32_N_6 (0xE << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_32_N_8 (0xF << 4) +#define TIM_CCMR1_IC1F_MASK (0xF << 4) + +/* IC1PSC[1:0]: Input capture 1 prescaler */ +#define TIM_CCMR1_IC1PSC_OFF (0x0 << 2) +#define TIM_CCMR1_IC1PSC_2 (0x1 << 2) +#define TIM_CCMR1_IC1PSC_4 (0x2 << 2) +#define TIM_CCMR1_IC1PSC_8 (0x3 << 2) +#define TIM_CCMR1_IC1PSC_MASK (0x3 << 2) + +/* --- TIMx_CCMR2 values --------------------------------------------------- */ + +/* --- Output compare mode --- */ + +/* OC4CE: Output compare 4 clear enable */ +#define TIM_CCMR2_OC4CE (1 << 15) + +/* OC4M[2:0]: Output compare 4 mode */ +#define TIM_CCMR2_OC4M_FROZEN (0x0 << 12) +#define TIM_CCMR2_OC4M_ACTIVE (0x1 << 12) +#define TIM_CCMR2_OC4M_INACTIVE (0x2 << 12) +#define TIM_CCMR2_OC4M_TOGGLE (0x3 << 12) +#define TIM_CCMR2_OC4M_FORCE_LOW (0x4 << 12) +#define TIM_CCMR2_OC4M_FORCE_HIGH (0x5 << 12) +#define TIM_CCMR2_OC4M_PWM1 (0x6 << 12) +#define TIM_CCMR2_OC4M_PWM2 (0x7 << 12) +#define TIM_CCMR2_OC4M_MASK (0x7 << 12) + +/* OC4PE: Output compare 4 preload enable */ +#define TIM_CCMR2_OC4PE (1 << 11) + +/* OC4FE: Output compare 4 fast enable */ +#define TIM_CCMR2_OC4FE (1 << 10) + +/* CC4S[1:0]: Capture/compare 4 selection */ +/* Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in + * TIMx_CCER). */ +#define TIM_CCMR2_CC4S_OUT (0x0 << 8) +#define TIM_CCMR2_CC4S_IN_TI2 (0x1 << 8) +#define TIM_CCMR2_CC4S_IN_TI1 (0x2 << 8) +#define TIM_CCMR2_CC4S_IN_TRC (0x3 << 8) +#define TIM_CCMR2_CC4S_MASK (0x3 << 8) + +/* OC3CE: Output compare 3 clear enable */ +#define TIM_CCMR2_OC3CE (1 << 7) + +/* OC3M[2:0]: Output compare 3 mode */ +#define TIM_CCMR2_OC3M_FROZEN (0x0 << 4) +#define TIM_CCMR2_OC3M_ACTIVE (0x1 << 4) +#define TIM_CCMR2_OC3M_INACTIVE (0x2 << 4) +#define TIM_CCMR2_OC3M_TOGGLE (0x3 << 4) +#define TIM_CCMR2_OC3M_FORCE_LOW (0x4 << 4) +#define TIM_CCMR2_OC3M_FORCE_HIGH (0x5 << 4) +#define TIM_CCMR2_OC3M_PWM1 (0x6 << 4) +#define TIM_CCMR2_OC3M_PWM2 (0x7 << 4) +#define TIM_CCMR2_OC3M_MASK (0x7 << 4) + +/* OC3PE: Output compare 3 preload enable */ +#define TIM_CCMR2_OC3PE (1 << 3) + +/* OC3FE: Output compare 3 fast enable */ +#define TIM_CCMR2_OC3FE (1 << 2) + +/* CC3S[1:0]: Capture/compare 3 selection */ +/* Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in + * TIMx_CCER). */ +#define TIM_CCMR2_CC3S_OUT (0x0 << 0) +#define TIM_CCMR2_CC3S_IN_TI2 (0x1 << 0) +#define TIM_CCMR2_CC3S_IN_TI1 (0x2 << 0) +#define TIM_CCMR2_CC3S_IN_TRC (0x3 << 0) +#define TIM_CCMR2_CC3S_MASK (0x3 << 0) + +/* --- Input capture mode --- */ + +/* IC4F[3:0]: Input capture 4 filter */ +#define TIM_CCMR2_IC4F_OFF (0x0 << 12) +#define TIM_CCMR2_IC4F_CK_INT_N_2 (0x1 << 12) +#define TIM_CCMR2_IC4F_CK_INT_N_4 (0x2 << 12) +#define TIM_CCMR2_IC4F_CK_INT_N_8 (0x3 << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_2_N_6 (0x4 << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_2_N_8 (0x5 << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_4_N_6 (0x6 << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_4_N_8 (0x7 << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_8_N_6 (0x8 << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_8_N_8 (0x9 << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_16_N_5 (0xA << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_16_N_6 (0xB << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_16_N_8 (0xC << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_32_N_5 (0xD << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_32_N_6 (0xE << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_32_N_8 (0xF << 12) +#define TIM_CCMR2_IC4F_MASK (0xF << 12) + +/* IC4PSC[1:0]: Input capture 4 prescaler */ +#define TIM_CCMR2_IC4PSC_OFF (0x0 << 10) +#define TIM_CCMR2_IC4PSC_2 (0x1 << 10) +#define TIM_CCMR2_IC4PSC_4 (0x2 << 10) +#define TIM_CCMR2_IC4PSC_8 (0x3 << 10) +#define TIM_CCMR2_IC4PSC_MASK (0x3 << 10) + +/* IC3F[3:0]: Input capture 3 filter */ +#define TIM_CCMR2_IC3F_OFF (0x0 << 4) +#define TIM_CCMR2_IC3F_CK_INT_N_2 (0x1 << 4) +#define TIM_CCMR2_IC3F_CK_INT_N_4 (0x2 << 4) +#define TIM_CCMR2_IC3F_CK_INT_N_8 (0x3 << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_2_N_6 (0x4 << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_2_N_8 (0x5 << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_4_N_6 (0x6 << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_4_N_8 (0x7 << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_8_N_6 (0x8 << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_8_N_8 (0x9 << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_16_N_5 (0xA << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_16_N_6 (0xB << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_16_N_8 (0xC << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_32_N_5 (0xD << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_32_N_6 (0xE << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_32_N_8 (0xF << 4) +#define TIM_CCMR2_IC3F_MASK (0xF << 4) + +/* IC3PSC[1:0]: Input capture 3 prescaler */ +#define TIM_CCMR2_IC3PSC_OFF (0x0 << 2) +#define TIM_CCMR2_IC3PSC_2 (0x1 << 2) +#define TIM_CCMR2_IC3PSC_4 (0x2 << 2) +#define TIM_CCMR2_IC3PSC_8 (0x3 << 2) +#define TIM_CCMR2_IC3PSC_MASK (0x3 << 2) + +/* --- TIMx_CCER values ---------------------------------------------------- */ + +/* CC4P: Capture/compare 4 output polarity */ +#define TIM_CCER_CC4P (1 << 13) + +/* CC4E: Capture/compare 4 output enable */ +#define TIM_CCER_CC4E (1 << 12) + +/* CC3NP: Capture/compare 3 complementary output polarity */ +#define TIM_CCER_CC3NP (1 << 11) + +/* CC3NE: Capture/compare 3 complementary output enable */ +#define TIM_CCER_CC3NE (1 << 10) + +/* CC3P: Capture/compare 3 output polarity */ +#define TIM_CCER_CC3P (1 << 9) + +/* CC3E: Capture/compare 3 output enable */ +#define TIM_CCER_CC3E (1 << 8) + +/* CC2NP: Capture/compare 2 complementary output polarity */ +#define TIM_CCER_CC2NP (1 << 7) + +/* CC2NE: Capture/compare 2 complementary output enable */ +#define TIM_CCER_CC2NE (1 << 6) + +/* CC2P: Capture/compare 2 output polarity */ +#define TIM_CCER_CC2P (1 << 5) + +/* CC2E: Capture/compare 2 output enable */ +#define TIM_CCER_CC2E (1 << 4) + +/* CC1NP: Capture/compare 1 complementary output polarity */ +#define TIM_CCER_CC1NP (1 << 3) + +/* CC1NE: Capture/compare 1 complementary output enable */ +#define TIM_CCER_CC1NE (1 << 2) + +/* CC1P: Capture/compare 1 output polarity */ +#define TIM_CCER_CC1P (1 << 1) + +/* CC1E: Capture/compare 1 output enable */ +#define TIM_CCER_CC1E (1 << 0) + +/* --- TIMx_CNT values ----------------------------------------------------- */ + +/* CNT[15:0]: Counter value */ + +/* --- TIMx_PSC values ----------------------------------------------------- */ + +/* PSC[15:0]: Prescaler value */ + +/* --- TIMx_ARR values ----------------------------------------------------- */ + +/* ARR[15:0]: Prescaler value */ + +/* --- TIMx_RCR values ----------------------------------------------------- */ + +/* REP[15:0]: Repetition counter value */ + +/* --- TIMx_CCR1 values ---------------------------------------------------- */ + +/* CCR1[15:0]: Capture/compare 1 value */ + +/* --- TIMx_CCR2 values ---------------------------------------------------- */ + +/* CCR2[15:0]: Capture/compare 2 value */ + +/* --- TIMx_CCR3 values ---------------------------------------------------- */ + +/* CCR3[15:0]: Capture/compare 3 value */ + +/* --- TIMx_CCR4 values ---------------------------------------------------- */ + +/* CCR4[15:0]: Capture/compare 4 value */ + +/* --- TIMx_BDTR values ---------------------------------------------------- */ + +/* MOE: Main output enable */ +#define TIM_BDTR_MOE (1 << 15) + +/* AOE: Automatic output enable */ +#define TIM_BDTR_AOE (1 << 14) + +/* BKP: Break polarity */ +#define TIM_BDTR_BKP (1 << 13) + +/* BKE: Break enable */ +#define TIM_BDTR_BKE (1 << 12) + +/* OSSR: Off-state selection of run mode */ +#define TIM_BDTR_OSSR (1 << 11) + +/* OSSI: Off-state selection of idle mode */ +#define TIM_BDTR_OSSI (1 << 10) + +/* LOCK[1:0]: Lock configuration */ +#define TIM_BDTR_LOCK_OFF (0x0 << 8) +#define TIM_BDTR_LOCK_LEVEL_1 (0x1 << 8) +#define TIM_BDTR_LOCK_LEVEL_2 (0x2 << 8) +#define TIM_BDTR_LOCK_LEVEL_3 (0x3 << 8) +#define TIM_BDTR_LOCK_MASK (0x3 << 8) + +/* DTG[7:0]: Dead-time generator set-up */ +#define TIM_BDTR_DTG_MASK 0x00FF + +/* --- TIMx_DCR values ----------------------------------------------------- */ + +/* DBL[4:0]: DMA burst length */ +#define TIM_BDTR_DBL_MASK (0x1F << 8) + +/* DBA[4:0]: DMA base address */ +#define TIM_BDTR_DBA_MASK (0x1F << 0) + +/* --- TIMx_DMAR values ---------------------------------------------------- */ + +/* DMAB[15:0]: DMA register for burst accesses */ + +/* --- TIMx convenience defines -------------------------------------------- */ + +/* Output Compare channel designators */ +enum tim_oc_id { + TIM_OC1=0, + TIM_OC1N, + TIM_OC2, + TIM_OC2N, + TIM_OC3, + TIM_OC3N, + TIM_OC4, +}; + +/* Output Compare mode designators */ +enum tim_oc_mode { + TIM_OCM_FROZEN, + TIM_OCM_ACTIVE, + TIM_OCM_INACTIVE, + TIM_OCM_TOGGLE, + TIM_OCM_FORCE_LOW, + TIM_OCM_FORCE_HIGH, + TIM_OCM_PWM1, + TIM_OCM_PWM2, +}; + +/* --- TIM functions ------------------------------------------------------- */ +void timer_reset(u32 timer_peripheral); +void timer_enable_irq(u32 timer_peripheral, u32 irq); +void timer_disable_irq(u32 timer_peripheral, u32 irq); +bool timer_get_flag(u32 timer_peripheral, u32 flag); +void timer_clear_flag(u32 timer_peripheral, u32 flag); +void timer_set_mode(u32 timer_peripheral, u8 clock_div, + u8 alignment, u8 direction); +void timer_set_clock_division(u32 timer_peripheral, u32 clock_div); +void timer_enable_preload(u32 timer_peripheral); +void timer_disable_preload(u32 timer_peripheral); +void timer_set_alignment(u32 timer_peripheral, u32 alignment); +void timer_direction_up(u32 timer_peripheral); +void timer_direction_down(u32 timer_peripheral); +void timer_one_shot_mode(u32 timer_peripheral); +void timer_continuous_mode(u32 timer_peripheral); +void timer_update_on_any(u32 timer_peripheral); +void timer_update_on_overflow(u32 timer_peripheral); +void timer_enable_update_event(u32 timer_peripheral); +void timer_disable_update_event(u32 timer_peripheral); +void timer_enable_counter(u32 timer_peripheral); +void timer_disable_counter(u32 timer_peripheral); +void timer_set_output_idle_state(u32 timer_peripheral, u32 outputs); +void timer_reset_output_idle_state(u32 timer_peripheral, u32 outputs); +void timer_set_ti1_ch123_xor(u32 timer_peripheral); +void timer_set_ti1_ch1(u32 timer_peripheral); +void timer_set_master_mode(u32 timer_peripheral, u32 mode); +void timer_set_dma_on_compare_event(u32 timer_peripheral); +void timer_set_dma_on_update_event(u32 timer_peripheral); +void timer_enable_compare_control_update_on_trigger(u32 timer_peripheral); +void timer_disable_compare_control_update_on_trigger(u32 timer_peripheral); +void timer_enable_preload_complementry_enable_bits(u32 timer_peripheral); +void timer_disable_preload_complementry_enable_bits(u32 timer_peripheral); +void timer_set_prescaler(u32 timer_peripheral, u32 value); +void timer_set_repetition_counter(u32 timer_peripheral, u32 value); +void timer_set_period(u32 timer_peripheral, u32 period); +void timer_enable_oc_clear(u32 timer_peripheral, enum tim_oc_id oc_id); +void timer_disable_oc_clear(u32 timer_peripheral, enum tim_oc_id oc_id); +void timer_set_oc_fast_mode(u32 timer_peripheral, enum tim_oc_id oc_id); +void timer_set_oc_slow_mode(u32 timer_peripheral, enum tim_oc_id oc_id); +void timer_set_oc_mode(u32 timer_peripheral, enum tim_oc_id oc_id, enum tim_oc_mode oc_mode); +void timer_enable_oc_preload(u32 timer_peripheral, enum tim_oc_id oc_id); +void timer_disable_oc_preload(u32 timer_peripheral, enum tim_oc_id oc_id); +void timer_set_oc_polarity_high(u32 timer_peripheral, enum tim_oc_id oc_id); +void timer_set_oc_polarity_low(u32 timer_peripheral, enum tim_oc_id oc_id); +void timer_enable_oc_output(u32 timer_peripheral, enum tim_oc_id oc_id); +void timer_disable_oc_output(u32 timer_peripheral, enum tim_oc_id oc_id); +void timer_set_oc_idle_state_set(u32 timer_peripheral, enum tim_oc_id oc_id); +void timer_set_oc_idle_state_unset(u32 timer_peripheral, enum tim_oc_id oc_id); +void timer_set_oc_value(u32 timer_peripheral, enum tim_oc_id oc_id, u32 value); +void timer_enable_break_main_output(u32 timer_peripheral); +void timer_disable_break_main_output(u32 timer_peripheral); +void timer_enable_break_automatic_output(u32 timer_peripheral); +void timer_disable_break_automatic_output(u32 timer_peripheral); +void timer_set_break_polarity_high(u32 timer_peripheral); +void timer_set_break_polarity_low(u32 timer_peripheral); +void timer_enable_break(u32 timer_peripheral); +void timer_disable_break(u32 timer_peripheral); +void timer_set_enabled_off_state_in_run_mode(u32 timer_peripheral); +void timer_set_disabled_off_state_in_run_mode(u32 timer_peripheral); +void timer_set_enabled_off_state_in_idle_mode(u32 timer_peripheral); +void timer_set_disabled_off_state_in_idle_mode(u32 timer_peripheral); +void timer_set_break_lock(u32 timer_peripheral, u32 lock); +void timer_set_deadtime(u32 timer_peripheral, u32 deadtime); +void timer_generate_event(u32 timer_peripheral, u32 event); +u32 timer_get_counter(u32 timer_peripheral); + +#endif diff --git a/include/libopencm3/stm32f1/tools.h b/include/libopencm3/stm32f1/tools.h new file mode 100644 index 0000000..ac7f0bf --- /dev/null +++ b/include/libopencm3/stm32f1/tools.h @@ -0,0 +1,64 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Piotr Esden-Tempski + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_TOOLS_H +#define LIBOPENCM3_TOOLS_H + +/* + * Register accessors / manipulators + */ + +/* Get register content. */ +#define GET_REG(REG) ((u16) *REG) + +/* Set register content. */ +#define SET_REG(REG, VAL) (*REG = (u16)VAL) + +/* Clear register bit. */ +#define CLR_REG_BIT(REG, BIT) SET_REG(REG, (~BIT)) + +/* Clear register bit masking out some bits that must not be touched. */ +#define CLR_REG_BIT_MSK(REG, MSK, BIT) \ + SET_REG(REG, (GET_REG(REG) & MSK & (~BIT))) + +/* Get masked out bit value. */ +#define GET_REG_BIT(REG, BIT) (GET_REG(REG) & BIT) + +/* + * Set/reset a bit in a masked window by using toggle mechanism. + * + * This means that we look at the bits in the bit window designated by + * the mask. If the bit in the masked window is not matching the + * bitmask BIT then we write 1 and if the bit in the masked window is + * matching the bitmask BIT we write 0. + * + * TODO: We may need a faster implementation of that one? + */ +#define TOG_SET_REG_BIT_MSK(REG, MSK, BIT) \ +do { \ + register u16 toggle_mask = GET_REG(REG) & (MSK); \ + register u16 bit_selector; \ + for (bit_selector = 1; bit_selector; bit_selector <<= 1) { \ + if ((bit_selector & (BIT)) != 0) \ + toggle_mask ^= bit_selector; \ + } \ + SET_REG(REG, toggle_mask); \ +} while(0) + +#endif diff --git a/include/libopencm3/stm32f1/usart.h b/include/libopencm3/stm32f1/usart.h new file mode 100644 index 0000000..df6bc08 --- /dev/null +++ b/include/libopencm3/stm32f1/usart.h @@ -0,0 +1,312 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_USART_H +#define LIBOPENCM3_USART_H + +#include +#include + +/* --- Convenience macros -------------------------------------------------- */ + +#define USART1 USART1_BASE +#define USART2 USART2_BASE +#define USART3 USART3_BASE +#define UART4 UART4_BASE +#define UART5 UART5_BASE + +/* --- USART registers ----------------------------------------------------- */ + +/* Status register (USARTx_SR) */ +#define USART_SR(usart_base) MMIO32(usart_base + 0x00) +#define USART1_SR USART_SR(USART1_BASE) +#define USART2_SR USART_SR(USART2_BASE) +#define USART3_SR USART_SR(USART3_BASE) +#define UART4_SR USART_SR(UART4_BASE) +#define UART5_SR USART_SR(UART5_BASE) + +/* Data register (USARTx_DR) */ +#define USART_DR(usart_base) MMIO32(usart_base + 0x04) +#define USART1_DR USART_DR(USART1_BASE) +#define USART2_DR USART_DR(USART2_BASE) +#define USART3_DR USART_DR(USART3_BASE) +#define UART4_DR USART_DR(UART4_BASE) +#define UART5_DR USART_DR(UART5_BASE) + +/* Baud rate register (USARTx_BRR) */ +#define USART_BRR(usart_base) MMIO32(usart_base + 0x08) +#define USART1_BRR USART_BRR(USART1_BASE) +#define USART2_BRR USART_BRR(USART2_BASE) +#define USART3_BRR USART_BRR(USART3_BASE) +#define UART4_BRR USART_BRR(UART4_BASE) +#define UART5_BRR USART_BRR(UART5_BASE) + +/* Control register 1 (USARTx_CR1) */ +#define USART_CR1(usart_base) MMIO32(usart_base + 0x0c) +#define USART1_CR1 USART_CR1(USART1_BASE) +#define USART2_CR1 USART_CR1(USART2_BASE) +#define USART3_CR1 USART_CR1(USART3_BASE) +#define UART4_CR1 USART_CR1(UART4_BASE) +#define UART5_CR1 USART_CR1(UART5_BASE) + +/* Control register 2 (USARTx_CR2) */ +#define USART_CR2(usart_base) MMIO32(usart_base + 0x10) +#define USART1_CR2 USART_CR2(USART1_BASE) +#define USART2_CR2 USART_CR2(USART2_BASE) +#define USART3_CR2 USART_CR2(USART3_BASE) +#define UART4_CR2 USART_CR2(UART4_BASE) +#define UART5_CR2 USART_CR2(UART5_BASE) + +/* Control register 3 (USARTx_CR3) */ +#define USART_CR3(usart_base) MMIO32(usart_base + 0x14) +#define USART1_CR3 USART_CR3(USART1_BASE) +#define USART2_CR3 USART_CR3(USART2_BASE) +#define USART3_CR3 USART_CR3(USART3_BASE) +#define UART4_CR3 USART_CR3(UART4_BASE) +#define UART5_CR3 USART_CR3(UART5_BASE) + +/* Guard time and prescaler register (USARTx_GTPR) */ +#define USART_GTPR(usart_base) MMIO32(usart_base + 0x18) +#define USART1_GTPR USART_GTPR(USART1_BASE) +#define USART2_GTPR USART_GTPR(USART2_BASE) +#define USART3_GTPR USART_GTPR(USART3_BASE) +#define UART4_GTPR USART_GTPR(UART4_BASE) +#define UART5_GTPR USART_GTPR(UART5_BASE) + +/* --- USART_SR values ----------------------------------------------------- */ + +/* CTS: CTS flag */ +/* Note: N/A on UART4/5 */ +#define USART_SR_CTS (1 << 9) + +/* LBD: LIN break detection flag */ +#define USART_SR_LBD (1 << 8) + +/* TXE: Transmit data buffer empty */ +#define USART_SR_TXE (1 << 7) + +/* TC: Transmission complete */ +#define USART_SR_TC (1 << 6) + +/* RXNE: Read data register not empty */ +#define USART_SR_RXNE (1 << 5) + +/* IDLE: Idle line detected */ +#define USART_SR_IDLE (1 << 4) + +/* ORE: Overrun error */ +#define USART_SR_ORE (1 << 3) + +/* NE: Noise error flag */ +#define USART_SR_NE (1 << 2) + +/* FE: Framing error */ +#define USART_SR_FE (1 << 1) + +/* PE: Parity error */ +#define USART_SR_PE (1 << 0) + +/* --- USART_DR values ----------------------------------------------------- */ + +/* USART_DR[8:0]: DR[8:0]: Data value */ +#define USART_DR_MASK 0x1FF + +/* --- USART_BRR values ---------------------------------------------------- */ + +/* DIV_Mantissa[11:0]: mantissa of USARTDIV */ +#define USART_BRR_DIV_MANTISSA_MASK (0xFFF << 4) +/* DIV_Fraction[3:0]: fraction of USARTDIV */ +#define USART_BRR_DIV_FRACTION_MASK 0xF + +/* --- USART_CR1 values ---------------------------------------------------- */ + +/* UE: USART enable */ +#define USART_CR1_UE (1 << 13) + +/* M: Word length */ +#define USART_CR1_M (1 << 12) + +/* WAKE: Wakeup method */ +#define USART_CR1_WAKE (1 << 11) + +/* PCE: Parity control enable */ +#define USART_CR1_PCE (1 << 10) + +/* PS: Parity selection */ +#define USART_CR1_PS (1 << 9) + +/* PEIE: PE interrupt enable */ +#define USART_CR1_PEIE (1 << 8) + +/* TXEIE: TXE interrupt enable */ +#define USART_CR1_TXEIE (1 << 7) + +/* TCIE: Transmission complete interrupt enable */ +#define USART_CR1_TCIE (1 << 6) + +/* RXNEIE: RXNE interrupt enable */ +#define USART_CR1_RXNEIE (1 << 5) + +/* IDLEIE: IDLE interrupt enable */ +#define USART_CR1_IDLEIE (1 << 4) + +/* TE: Transmitter enable */ +#define USART_CR1_TE (1 << 3) + +/* RE: Receiver enable */ +#define USART_CR1_RE (1 << 2) + +/* RWU: Receiver wakeup */ +#define USART_CR1_RWU (1 << 1) + +/* SBK: Send break */ +#define USART_CR1_SBK (1 << 0) + +/* --- USART_CR2 values ---------------------------------------------------- */ + +/* LINEN: LIN mode enable */ +#define USART_CR2_LINEN (1 << 14) + +/* STOP[13:12]: STOP bits */ +#define USART_CR2_STOPBITS_1 (0x00 << 12) /* 1 stop bit */ +#define USART_CR2_STOPBITS_0_5 (0x01 << 12) /* 0.5 stop bits */ +#define USART_CR2_STOPBITS_2 (0x02 << 12) /* 2 stop bits */ +#define USART_CR2_STOPBITS_1_5 (0x03 << 12) /* 1.5 stop bits */ +#define USART_CR2_STOPBITS_MASK (0x03 << 12) +#define USART_CR2_STOPBITS_SHIFT 12 + +/* CLKEN: Clock enable */ +#define USART_CR2_CLKEN (1 << 11) + +/* CPOL: Clock polarity */ +#define USART_CR2_CPOL (1 << 10) + +/* CPHA: Clock phase */ +#define USART_CR2_CPHA (1 << 9) + +/* LBCL: Last bit clock pulse */ +#define USART_CR2_LBCL (1 << 8) + +/* LBDIE: LIN break detection interrupt enable */ +#define USART_CR2_LBDIE (1 << 6) + +/* LBDL: LIN break detection length */ +#define USART_CR2_LBDL (1 << 5) + +/* ADD[3:0]: Addres of the usart node */ +#define USART_CR2_ADD_MASK 0xF + +/* --- USART_CR3 values ---------------------------------------------------- */ + +/* CTSIE: CTS interrupt enable */ +/* Note: N/A on UART4 & UART5 */ +#define USART_CR3_CTSIE (1 << 10) + +/* CTSE: CTS enable */ +/* Note: N/A on UART4 & UART5 */ +#define USART_CR3_CTSE (1 << 9) + +/* RTSE: RTS enable */ +/* Note: N/A on UART4 & UART5 */ +#define USART_CR3_RTSE (1 << 8) + +/* DMAT: DMA enable transmitter */ +/* Note: N/A on UART5 */ +#define USART_CR3_DMAT (1 << 7) + +/* DMAR: DMA enable receiver */ +/* Note: N/A on UART5 */ +#define USART_CR3_DMAR (1 << 6) + +/* SCEN: Smartcard mode enable */ +/* Note: N/A on UART4 & UART5 */ +#define USART_CR3_SCEN (1 << 5) + +/* NACK: Smartcard NACK enable */ +/* Note: N/A on UART4 & UART5 */ +#define USART_CR3_NACK (1 << 4) + +/* HDSEL: Half-duplex selection */ +#define USART_CR3_HDSEL (1 << 3) + +/* IRLP: IrDA low-power */ +#define USART_CR3_IRLP (1 << 2) + +/* IREN: IrDA mode enable */ +#define USART_CR3_IREN (1 << 1) + +/* EIE: Error interrupt enable */ +#define USART_CR3_EIE (1 << 0) + +/* --- USART_GTPR values --------------------------------------------------- */ + +/* GT[7:0]: Guard time value */ +/* Note: N/A on UART4 & UART5 */ +#define USART_GTPR_GT_MASK (0xFF << 8) + +/* PSC[7:0]: Prescaler value */ +/* Note: N/A on UART4/5 */ +#define USART_GTPR_PSC_MASK 0xFF + +/* TODO */ /* Note to Uwe: what needs to be done here? */ + +/* --- Convenience defines ------------------------------------------------- */ + +/* CR1_PCE / CR1_PS combined values */ +#define USART_PARITY_NONE 0x00 +#define USART_PARITY_ODD USART_CR1_PS +#define USART_PARITY_EVEN (USART_CR1_PS | USART_CR1_PCE) +#define USART_PARITY_MASK (USART_CR1_PS | USART_CR1_PCE) + +/* CR1_TE/CR1_RE combined values */ +#define USART_MODE_RX USART_CR1_RE +#define USART_MODE_TX USART_CR1_TE +#define USART_MODE_TX_RX (USART_CR1_RE | USART_CR1_TE) +#define USART_MODE_MASK (USART_CR1_RE | USART_CR1_TE) + +#define USART_STOPBITS_1 USART_CR2_STOPBITS_1 /* 1 stop bit */ +#define USART_STOPBITS_0_5 USART_CR2_STOPBITS_0_5 /* 0.5 stop bits */ +#define USART_STOPBITS_2 USART_CR2_STOPBITS_2 /* 2 stop bits */ +#define USART_STOPBITS_1_5 USART_CR2_STOPBITS_1_5 /* 1.5 stop bits */ + +/* CR3_CTSE/CR3_RTSE combined values */ +#define USART_FLOWCONTROL_NONE 0x00 +#define USART_FLOWCONTROL_RTS USART_CR3_RTSE +#define USART_FLOWCONTROL_CTS USART_CR3_CTSE +#define USART_FLOWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) +#define USART_FLOWCONTROL_MASK (USART_CR3_RTSE | USART_CR3_CTSE) + +/* --- Function prototypes ------------------------------------------------- */ + +void usart_set_baudrate(u32 usart, u32 baud); +void usart_set_databits(u32 usart, u32 bits); +void usart_set_stopbits(u32 usart, u32 stopbits); +void usart_set_parity(u32 usart, u32 parity); +void usart_set_mode(u32 usart, u32 mode); +void usart_set_flow_control(u32 usart, u32 flowcontrol); +void usart_enable(u32 usart); +void usart_disable(u32 usart); +void usart_send(u32 usart, u16 data); +u16 usart_recv(u32 usart); +void usart_wait_send_ready(u32 usart); +void usart_wait_recv_ready(u32 usart); +void usart_send_blocking(u32 usart, u16 data); +u16 usart_recv_blocking(u32 usart); + +#endif diff --git a/include/libopencm3/stm32f1/usb.h b/include/libopencm3/stm32f1/usb.h new file mode 100644 index 0000000..e35075d --- /dev/null +++ b/include/libopencm3/stm32f1/usb.h @@ -0,0 +1,258 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Piotr Esden-Tempski + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_USB_H +#define LIBOPENCM3_USB_H + +#include +#include +#include + +/* --- USB base addresses -------------------------------------------------- */ + +#define USB_PMA_BASE 0x40006000L /* USB packet buffer memory base addr. */ + +/* --- USB general registers ----------------------------------------------- */ + +/* USB Control register */ +#define USB_CNTR_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x40)) +/* USB Interrupt status register */ +#define USB_ISTR_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x44)) +/* USB Frame number register */ +#define USB_FNR_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x48)) +/* USB Device address register */ +#define USB_DADDR_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x4C)) +/* USB Buffer table address register */ +#define USB_BTABLE_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x50)) +/* USB EP register */ +#define USB_EP_REG(EP) ((volatile u32 *)(USB_DEV_FS_BASE) + (EP)) + +/* --- USB control register masks / bits ----------------------------------- */ + +/* Interrupt mask bits, set to 1 to enable interrupt generation */ +#define USB_CNTR_CTRM 0x8000 +#define USB_CNTR_PMAOVRM 0x4000 +#define USB_CNTR_ERRM 0x2000 +#define USB_CNTR_WKUPM 0x1000 +#define USB_CNTR_SUSPM 0x0800 +#define USB_CNTR_RESETM 0x0400 +#define USB_CNTR_SOFM 0x0200 +#define USB_CNTR_ESOFM 0x0100 + +/* Request/Force bits */ +#define USB_CNTR_RESUME 0x0010 /* Resume request */ +#define USB_CNTR_FSUSP 0x0008 /* Force suspend */ +#define USB_CNTR_LP_MODE 0x0004 /* Low-power mode */ +#define USB_CNTR_PWDN 0x0002 /* Power down */ +#define USB_CNTR_FRES 0x0001 /* Force reset */ + +/* --- USB interrupt status register masks / bits -------------------------- */ + +#define USB_ISTR_CTR 0x8000 /* Correct Transfer */ +#define USB_ISTR_PMAOVR 0x4000 /* Packet Memory Area Over / Underrun */ +#define USB_ISTR_ERR 0x2000 /* Error */ +#define USB_ISTR_WKUP 0x1000 /* Wake up */ +#define USB_ISTR_SUSP 0x0800 /* Suspend mode request */ +#define USB_ISTR_RESET 0x0400 /* USB RESET request */ +#define USB_ISTR_SOF 0x0200 /* Start Of Frame */ +#define USB_ISTR_ESOF 0x0100 /* Expected Start Of Frame */ +#define USB_ISTR_DIR 0x0010 /* Direction of transaction */ +#define USB_ISTR_EP_ID 0x000F /* Endpoint Identifier */ + +/* --- USB interrupt status register manipulators -------------------------- */ + +/* Note: CTR is read only! */ +#define USB_CLR_ISTR_PMAOVR() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_PMAOVR) +#define USB_CLR_ISTR_ERR() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_ERR) +#define USB_CLR_ISTR_WKUP() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_WKUP) +#define USB_CLR_ISTR_SUSP() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_SUSP) +#define USB_CLR_ISTR_RESET() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_RESET) +#define USB_CLR_ISTR_SOF() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_SOF) +#define USB_CLR_ISTR_ESOF() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_ESOF) + +/* --- USB device addres register masks / bits ----------------------------- */ + +#define USB_DADDR_ENABLE 0x0080 +#define USB_DADDR_ADDR 0x007F + +/* --- USB device addres register manipulators ----------------------------- */ + +/* --- USB endpoint register offsets --------------------------------------- */ + +#define USB_EP0 0 +#define USB_EP1 1 +#define USB_EP2 2 +#define USB_EP3 3 +#define USB_EP4 4 +#define USB_EP5 5 +#define USB_EP6 6 +#define USB_EP7 7 + +/* --- USB endpoint register masks / bits ---------------------------------- */ + +/* Masks and toggle bits */ +#define USB_EP_RX_CTR 0x8000 /* Correct transfer RX */ +#define USB_EP_RX_DTOG 0x4000 /* Data toggle RX */ +#define USB_EP_RX_STAT 0x3000 /* Endpoint status for RX */ + +#define USB_EP_SETUP 0x0800 /* Setup transaction completed */ +#define USB_EP_TYPE 0x0600 /* Endpoint type */ +#define USB_EP_KIND 0x0100 /* Endpoint kind. + * When set and type=bulk -> double buffer + * When set and type=control -> status out + */ + +#define USB_EP_TX_CTR 0x0080 /* Correct transfer TX */ +#define USB_EP_TX_DTOG 0x0040 /* Data toggle TX */ +#define USB_EP_TX_STAT 0x0030 /* Endpoint status for TX */ + +#define USB_EP_ADDR 0x000F /* Endpoint Address */ + +/* Masking all toggle bits */ +#define USB_EP_NTOGGLE_MSK (USB_EP_RX_CTR | \ + USB_EP_SETUP | \ + USB_EP_TYPE | \ + USB_EP_KIND | \ + USB_EP_TX_CTR | \ + USB_EP_ADDR) + +/* All non toggle bits plus EP_RX toggle bits */ +#define USB_EP_RX_STAT_TOG_MSK (USB_EP_RX_STAT | USB_EP_NTOGGLE_MSK) +/* All non toggle bits plus EP_TX toggle bits */ +#define USB_EP_TX_STAT_TOG_MSK (USB_EP_TX_STAT | USB_EP_NTOGGLE_MSK) + +/* Endpoint status bits for USB_EP_RX_STAT bit field */ +#define USB_EP_RX_STAT_DISABLED 0x0000 +#define USB_EP_RX_STAT_STALL 0x1000 +#define USB_EP_RX_STAT_NAK 0x2000 +#define USB_EP_RX_STAT_VALID 0x3000 + +/* Endpoint status bits for USB_EP_TX_STAT bit field */ +#define USB_EP_TX_STAT_DISABLED 0x0000 +#define USB_EP_TX_STAT_STALL 0x0010 +#define USB_EP_TX_STAT_NAK 0x0020 +#define USB_EP_TX_STAT_VALID 0x0030 + +/* Endpoint type bits for USB_EP_TYPE bit field */ +#define USB_EP_TYPE_BULK 0x0000 +#define USB_EP_TYPE_CONTROL 0x0200 +#define USB_EP_TYPE_ISO 0x0400 +#define USB_EP_TYPE_INTERRUPT 0x0600 + +/* --- USB endpoint register manipulators ---------------------------------- */ + +/* + * Set USB endpoint tx/rx status. + * + * USB status field is changed using an awkward toggle mechanism, that + * is why we use some helper macros for that. + */ +#define USB_SET_EP_RX_STAT(EP, STAT) \ + TOG_SET_REG_BIT_MSK(USB_EP_REG(EP), USB_EP_RX_STAT_TOG_MSK, STAT) + +#define USB_SET_EP_TX_STAT(EP, STAT) \ + TOG_SET_REG_BIT_MSK(USB_EP_REG(EP), USB_EP_TX_STAT_TOG_MSK, STAT) + +/* + * Macros for clearing and setting USB endpoint register bits that do + * not use the toggle mechanism. + * + * Because the register contains some bits that use the toggle + * mechanism we need a helper macro here. Otherwise the code gets really messy. + */ +#define USB_CLR_EP_NTOGGLE_BIT(EP, BIT) \ + CLR_REG_BIT_MSK(USB_EP_REG(EP), USB_EP_NTOGGLE_MSK, BIT) + +#define USB_CLR_EP_RX_CTR(EP) \ + USB_CLR_EP_NTOGGLE_BIT(EP, USB_EP_RX_CTR) + +#define USB_CLR_EP_TX_CTR(EP) \ + USB_CLR_EP_NTOGGLE_BIT(EP, USB_EP_TX_CTR) + +#define USB_SET_EP_TYPE(EP, TYPE) \ + SET_REG(USB_EP_REG(EP), \ + (GET_REG(USB_EP_REG(EP)) & \ + (USB_EP_NTOGGLE_MSK & \ + (~USB_EP_TYPE))) | TYPE) + +#define USB_SET_EP_KIND(EP) \ + SET_REG(USB_EP_REG(EP), \ + (GET_REG(USB_EP_REG(EP)) & \ + (USB_EP_NTOGGLE_MSK & \ + (~USB_EP_KIND))) | USB_EP_KIND) + +#define USB_CLR_EP_KIND(EP) \ + SET_REG(USB_EP_REG(EP), \ + (GET_REG(USB_EP_REG(EP)) & \ + (USB_EP_NTOGGLE_MSK & (~USB_EP_KIND)))) + +#define USB_SET_EP_STAT_OUT(EP) USB_SET_EP_KIND(EP) +#define USB_CLR_EP_STAT_OUT(EP) USB_CLR_EP_KIND(EP) + +#define USB_SET_EP_ADDR(EP, ADDR) \ + SET_REG(USB_EP_REG(EP), \ + ((GET_REG(USB_EP_REG(EP)) & \ + (USB_EP_NTOGGLE_MSK & \ + (~USB_EP_ADDR))) | ADDR)) + +/* Macros for clearing DTOG bits */ +#define USB_CLR_EP_TX_DTOG(EP) \ + SET_REG(USB_EP_REG(EP), \ + GET_REG(USB_EP_REG(EP)) & \ + (USB_EP_NTOGGLE_MSK | USB_EP_TX_DTOG)) + +#define USB_CLR_EP_RX_DTOG(EP) \ + SET_REG(USB_EP_REG(EP), \ + GET_REG(USB_EP_REG(EP)) & \ + (USB_EP_NTOGGLE_MSK | USB_EP_RX_DTOG)) + +/* --- USB BTABLE registers ------------------------------------------------ */ + +#define USB_GET_BTABLE GET_REG(USB_BTABLE_REG) + +#define USB_EP_TX_ADDR(EP) \ + ((u32 *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 0) * 2)) + +#define USB_EP_TX_COUNT(EP) \ + ((u32 *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 2) * 2)) + +#define USB_EP_RX_ADDR(EP) \ + ((u32 *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 4) * 2)) + +#define USB_EP_RX_COUNT(EP) \ + ((u32 *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 6) * 2)) + +/* --- USB BTABLE manipulators --------------------------------------------- */ + +#define USB_GET_EP_TX_ADDR(EP) GET_REG(USB_EP_TX_ADDR(EP)) +#define USB_GET_EP_TX_COUNT(EP) GET_REG(USB_EP_TX_COUNT(EP)) +#define USB_GET_EP_RX_ADDR(EP) GET_REG(USB_EP_RX_ADDR(EP)) +#define USB_GET_EP_RX_COUNT(EP) GET_REG(USB_EP_RX_COUNT(EP)) +#define USB_SET_EP_TX_ADDR(EP, ADDR) SET_REG(USB_EP_TX_ADDR(EP), ADDR) +#define USB_SET_EP_TX_COUNT(EP, COUNT) SET_REG(USB_EP_TX_COUNT(EP), COUNT) +#define USB_SET_EP_RX_ADDR(EP, ADDR) SET_REG(USB_EP_RX_ADDR(EP), ADDR) +#define USB_SET_EP_RX_COUNT(EP, COUNT) SET_REG(USB_EP_RX_COUNT(EP), COUNT) + +#define USB_GET_EP_TX_BUFF(EP) \ + (USB_PMA_BASE + (u8 *)(USB_GET_EP_TX_ADDR(EP) * 2)) + +#define USB_GET_EP_RX_BUFF(EP) \ + (USB_PMA_BASE + (u8 *)(USB_GET_EP_RX_ADDR(EP) * 2)) + +#endif diff --git a/include/libopencm3/stm32f1/usb_desc.h b/include/libopencm3/stm32f1/usb_desc.h new file mode 100644 index 0000000..da99bb0 --- /dev/null +++ b/include/libopencm3/stm32f1/usb_desc.h @@ -0,0 +1,101 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Piotr Esden-Tempski + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_USB_DESC +#define LIBOPENCM3_USB_DESC + +/* Descriptor types */ +#define USB_DT_DEVICE 0x01 +#define USB_DT_CONF 0x02 +#define USB_DT_STRING 0x03 +#define USB_DT_INTERFACE 0x04 +#define USB_DT_ENDPOINT 0x05 + +struct usb_desc_head { + u8 length; /* Descriptor size 0x012 */ + u8 type; /* Descriptor type ID */ +}; + +struct usb_device_desc { + struct usb_desc_head h; /* Size 0x12, ID 0x01 */ + u16 bcd_usb; /* USB Version */ + u8 class; /* Device class */ + u8 sub_class; /* Subclass code */ + u8 protocol; /* Protocol code */ + u8 max_psize; /* Maximum packet size -> 64bytes */ + u16 vendor; /* Vendor number */ + u16 product; /* Device number */ + u16 bcd_dev; /* Device version */ + u8 man_desc; /* Index of manufacturer string desc */ + u8 prod_desc; /* Index of product string desc */ + u8 sn_desc; /* Index of serial number string desc */ + u8 num_conf; /* Number of possible configurations */ +}; + +struct usb_conf_desc_header { + struct usb_desc_head h; /* Size 0x09, Id 0x02 */ + u16 tot_leng; /* Total length of data */ + u8 num_int; /* Number of interfaces */ + u8 conf_val; /* Configuration selector */ + u8 conf_desc; /* Index of conf string desc */ + u8 attr; /* Attribute bitmap: + * 7 : Bus powered + * 6 : Self powered + * 5 : Remote wakeup + * 4..0 : Reserved -> 0000 + */ + u8 max_power; /* Maximum power consumption in 2mA steps */ +}; + +struct usb_int_desc_header { + struct usb_desc_head h; /* Size 0x09, Id 0x04 */ + u8 iface_num; /* Interface id number */ + u8 alt_setting; /* Alternative setting selector */ + u8 num_endp; /* Endpoints used */ + u8 class; /* Interface class */ + u8 sub_class; /* Subclass code */ + u8 protocol; /* Protocol code */ + u8 iface_desc; /* Index of interface string desc */ +}; + +struct usb_ep_desc { + struct usb_desc_head h; /* Size 0x07, Id 0x05 */ + u8 ep_addr; /* Endpoint address: + 0..3 : Endpoint Number + 4..6 : Reserved -> 0 + 7 : Direction 0=out 1=in */ + u8 ep_attr; /* Endpoint attributes */ + u16 max_psize; /* Maximum packet size -> 64bytes */ + u8 interval; /* Interval for polling endpoint + data. Ignored for bulk & control + endpoints. */ +}; + +struct usb_conf_desc { + struct usb_conf_desc_header cdh; + struct usb_int_desc_header idh; + struct usb_ep_desc ep[]; +}; + +struct usb_string_desc { + struct usb_desc_head h; /* Size > 0x02, Id 0x03 */ + u16 string[]; /* String UTF16 encoded */ +}; + +#endif diff --git a/include/libopencm3/stm32f1/wwdg.h b/include/libopencm3/stm32f1/wwdg.h new file mode 100644 index 0000000..552d02e --- /dev/null +++ b/include/libopencm3/stm32f1/wwdg.h @@ -0,0 +1,74 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_WWDG_H +#define LIBOPENCM3_WWDG_H + +#include +#include + +/* --- WWDG registers ------------------------------------------------------ */ + +/* Control register (WWDG_CR) */ +#define WWDG_CR MMIO32(WWDG_BASE + 0x00) + +/* Configuration register (WWDG_CFR) */ +#define WWDG_CFR MMIO32(WWDG_BASE + 0x04) + +/* Status register (WWDG_SR) */ +#define WWDG_SR MMIO32(WWDG_BASE + 0x08) + +/* --- WWDG_CR values ------------------------------------------------------ */ + +/* WDGA: Activation bit */ +#define WWDG_CR_WDGA (1 << 7) + +/* T[6:0]: 7-bit counter (MSB to LSB) */ +#define WWDG_CR_T_LSB 0 +#define WWDG_CR_T0 (1 << 0) +#define WWDG_CR_T1 (1 << 1) +#define WWDG_CR_T2 (1 << 2) +#define WWDG_CR_T3 (1 << 3) +#define WWDG_CR_T4 (1 << 4) +#define WWDG_CR_T5 (1 << 5) +#define WWDG_CR_T6 (1 << 6) + +/* --- WWDG_CFR values ----------------------------------------------------- */ + +/* EWI: Early wakeup interrupt */ +#define WWDG_CFR_EWI (1 << 9) + +/* WDGTB[8:7]: Timer base */ +#define WWDG_CFR_WDGTB_LSB 7 +#define WWDG_CFR_WDGTB_CK_DIV1 0x0 +#define WWDG_CFR_WDGTB_CK_DIV2 0x1 +#define WWDG_CFR_WDGTB_CK_DIV4 0x2 +#define WWDG_CFR_WDGTB_CK_DIV8 0x3 + +/* W[6:0]: 7-bit window value */ +#define WWDG_CFG_W_LSB 0 + +/* --- WWDG_SR values ------------------------------------------------------ */ + +/* EWIF: Early wakeup interrupt flag */ +#define WWDG_SR_EWIF (1 << 0) + +/* --- WWDG funtion prototypes---------------------------------------------- */ + +#endif -- cgit v1.2.3 From cf8171e469ff726701bfdc5d14a169c87d1e5b54 Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Mon, 12 Sep 2011 18:12:11 -0700 Subject: Moving stm header files that are common to f1 and f2 series into their own folder. --- include/libopencm3/stm32_common/can.h | 642 +++++++++++++++++++++++++++++++ include/libopencm3/stm32_common/crc.h | 52 +++ include/libopencm3/stm32_common/dbgmcu.h | 60 +++ include/libopencm3/stm32_common/exti.h | 70 ++++ include/libopencm3/stm32_common/fsmc.h | 284 ++++++++++++++ include/libopencm3/stm32_common/iwdg.h | 75 ++++ include/libopencm3/stm32_common/wwdg.h | 74 ++++ include/libopencm3/stm32f1/can.h | 642 ------------------------------- include/libopencm3/stm32f1/crc.h | 52 --- include/libopencm3/stm32f1/dbgmcu.h | 60 --- include/libopencm3/stm32f1/exti.h | 70 ---- include/libopencm3/stm32f1/fsmc.h | 284 -------------- include/libopencm3/stm32f1/iwdg.h | 75 ---- include/libopencm3/stm32f1/wwdg.h | 74 ---- 14 files changed, 1257 insertions(+), 1257 deletions(-) create mode 100644 include/libopencm3/stm32_common/can.h create mode 100644 include/libopencm3/stm32_common/crc.h create mode 100644 include/libopencm3/stm32_common/dbgmcu.h create mode 100644 include/libopencm3/stm32_common/exti.h create mode 100644 include/libopencm3/stm32_common/fsmc.h create mode 100644 include/libopencm3/stm32_common/iwdg.h create mode 100644 include/libopencm3/stm32_common/wwdg.h delete mode 100644 include/libopencm3/stm32f1/can.h delete mode 100644 include/libopencm3/stm32f1/crc.h delete mode 100644 include/libopencm3/stm32f1/dbgmcu.h delete mode 100644 include/libopencm3/stm32f1/exti.h delete mode 100644 include/libopencm3/stm32f1/fsmc.h delete mode 100644 include/libopencm3/stm32f1/iwdg.h delete mode 100644 include/libopencm3/stm32f1/wwdg.h diff --git a/include/libopencm3/stm32_common/can.h b/include/libopencm3/stm32_common/can.h new file mode 100644 index 0000000..1aa95a1 --- /dev/null +++ b/include/libopencm3/stm32_common/can.h @@ -0,0 +1,642 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Piotr Esden-Tempski + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_CAN_H +#define LIBOPENCM3_CAN_H + +#include +#include + +/* --- Convenience macros -------------------------------------------------- */ + +/* CAN register base adresses (for convenience) */ +#define CAN1 BX_CAN1_BASE +#define CAN2 BX_CAN2_BASE + +/* --- CAN registers ------------------------------------------------------- */ + +/* CAN master control register (CAN_MCR) */ +#define CAN_MCR(can_base) MMIO32(can_base + 0x000) +/* CAN master status register (CAN_MSR) */ +#define CAN_MSR(can_base) MMIO32(can_base + 0x004) +/* CAN transmit status register (CAN_TSR) */ +#define CAN_TSR(can_base) MMIO32(can_base + 0x008) + +/* CAN receive FIFO 0 register (CAN_RF0R) */ +#define CAN_RF0R(can_base) MMIO32(can_base + 0x00C) +/* CAN receive FIFO 1 register (CAN_RF1R) */ +#define CAN_RF1R(can_base) MMIO32(can_base + 0x010) + +/* CAN interrupt enable register (CAN_IER) */ +#define CAN_IER(can_base) MMIO32(can_base + 0x014) +/* CAN error status register (CAN_ESR) */ +#define CAN_ESR(can_base) MMIO32(can_base + 0x018) +/* CAN bit timing register (CAN_BTR) */ +#define CAN_BTR(can_base) MMIO32(can_base + 0x01C) + +/* Registers in the offset range 0x020 to 0x17F are reserved. */ + +/* --- CAN mailbox registers ----------------------------------------------- */ + +/* CAN mailbox / FIFO register offsets */ +#define CAN_MBOX0 0x180 +#define CAN_MBOX1 0x190 +#define CAN_MBOX2 0x1A0 +#define CAN_FIFO0 0x1B0 +#define CAN_FIFO1 0x1C0 + +/* CAN TX mailbox identifier register (CAN_TIxR) */ +#define CAN_TIxR(can_base, mbox) MMIO32(can_base + mbox + 0x0) +#define CAN_TI0R(can_base) CAN_TIxR(can_base, CAN_MBOX0) +#define CAN_TI1R(can_base) CAN_TIxR(can_base, CAN_MBOX1) +#define CAN_TI2R(can_base) CAN_TIxR(can_base, CAN_MBOX2) + +/* CAN mailbox data length control and time stamp register (CAN_TDTxR) */ +#define CAN_TDTxR(can_base, mbox) MMIO32(can_base + mbox + 0x4) +#define CAN_TDT0R(can_base) CAN_TDTxR(can_base, CAN_MBOX0) +#define CAN_TDT1R(can_base) CAN_TDTxR(can_base, CAN_MBOX1) +#define CAN_TDT2R(can_base) CAN_TDTxR(can_base, CAN_MBOX2) + +/* CAN mailbox data low register (CAN_TDLxR) */ +#define CAN_TDLxR(can_base, mbox) MMIO32(can_base + mbox + 0x8) +#define CAN_TDL0R(can_base) CAN_TDLxR(can_base, CAN_MBOX0) +#define CAN_TDL1R(can_base) CAN_TDLxR(can_base, CAN_MBOX1) +#define CAN_TDL2R(can_base) CAN_TDLxR(can_base, CAN_MBOX2) + +/* CAN mailbox data high register (CAN_TDHxR) */ +#define CAN_TDHxR(can_base, mbox) MMIO32(can_base + mbox + 0xC) +#define CAN_TDH0R(can_base) CAN_TDHxR(can_base, CAN_MBOX0) +#define CAN_TDH1R(can_base) CAN_TDHxR(can_base, CAN_MBOX1) +#define CAN_TDH2R(can_base) CAN_TDHxR(can_base, CAN_MBOX2) + +/* CAN RX FIFO identifier register (CAN_RIxR) */ +#define CAN_RIxR(can_base, fifo) MMIO32(can_base + fifo + 0x0) +#define CAN_RI0R(can_base) CAN_RIxR(can_base, CAN_FIFO0) +#define CAN_RI1R(can_base) CAN_RIxR(can_base, CAN_FIFO1) + +/* CAN RX FIFO mailbox data length control & time stamp register (CAN_RDTxR) */ +#define CAN_RDTxR(can_base, fifo) MMIO32(can_base + fifo + 0x4) +#define CAN_RDT0R(can_base) CAN_RDTxR(can_base, CAN_FIFO0) +#define CAN_RDT1R(can_base) CAN_RDTxR(can_base, CAN_FIFO1) + +/* CAN RX FIFO mailbox data low register (CAN_RDLxR) */ +#define CAN_RDLxR(can_base, fifo) MMIO32(can_base + fifo + 0x8) +#define CAN_RDL0R(can_base) CAN_RDLxR(can_base, CAN_FIFO0) +#define CAN_RDL1R(can_base) CAN_RDLxR(can_base, CAN_FIFO1) + +/* CAN RX FIFO mailbox data high register (CAN_RDHxR) */ +#define CAN_RDHxR(can_base, fifo) MMIO32(can_base + fifo + 0xC) +#define CAN_RDH0R(can_base) CAN_RDHxR(can_base, CAN_FIFO0) +#define CAN_RDH1R(can_base) CAN_RDHxR(can_base, CAN_FIFO1) + +/* --- CAN filter registers ------------------------------------------------ */ + +/* CAN filter master register (CAN_FMR) */ +#define CAN_FMR(can_base) MMIO32(can_base + 0x200) + +/* CAN filter mode register (CAN_FM1R) */ +#define CAN_FM1R(can_base) MMIO32(can_base + 0x204) + +/* Register offset 0x208 is reserved. */ + +/* CAN filter scale register (CAN_FS1R) */ +#define CAN_FS1R(can_base) MMIO32(can_base + 0x20C) + +/* Register offset 0x210 is reserved. */ + +/* CAN filter FIFO assignement register (CAN_FFA1R) */ +#define CAN_FFA1R(can_base) MMIO32(can_base + 0x214) + +/* Register offset 0x218 is reserved. */ + +/* CAN filter activation register (CAN_FA1R) */ +#define CAN_FA1R(can_base) MMIO32(can_base + 0x21C) + +/* Register offset 0x220 is reserved. */ + +/* Registers with offset 0x224 to 0x23F are reserved. */ + +/* CAN filter bank registers (CAN_FiRx) */ +/* + * Connectivity line devices have 28 banks so the bank ID spans 0..27 + * all other devices have 14 banks so the bank ID spans 0..13. + */ +#define CAN_FiR1(can_base, bank) MMIO32(can_base + 0x240 + (bank * 0x8) + 0x0) +#define CAN_FiR2(can_base, bank) MMIO32(can_base + 0x240 + (bank * 0x8) + 0x4) + +/* --- CAN_MCR values ------------------------------------------------------ */ + +/* 31:17 Reserved, forced by hardware to 0 */ + +/* DBF: Debug freeze */ +#define CAN_MCR_DBF (1 << 16) + +/* RESET: bxCAN software master reset */ +#define CAN_MCR_RESET (1 << 15) + +/* 14:8 Reserved, forced by hardware to 0 */ + +/* TTCM: Time triggered communication mode */ +#define CAN_MCR_TTCM (1 << 7) + +/* ABOM: Automatic bus-off management */ +#define CAN_MCR_ABOM (1 << 6) + +/* AWUM: Automatic wakeup mode */ +#define CAN_MCR_AWUM (1 << 5) + +/* NART: No automatic retransmission */ +#define CAN_MCR_NART (1 << 4) + +/* RFLM: Receive FIFO locked mode */ +#define CAN_MCR_RFLM (1 << 3) + +/* TXFP: Transmit FIFO priority */ +#define CAN_MCR_TXFP (1 << 2) + +/* SLEEP: Sleep mode request */ +#define CAN_MCR_SLEEP (1 << 1) + +/* INRQ: Initialization request */ +#define CAN_MCR_INRQ (1 << 0) + +/* --- CAN_MSR values ------------------------------------------------------ */ + +/* 31:12 Reserved, forced by hardware to 0 */ + +/* RX: CAN Rx signal */ +#define CAN_MSR_RX (1 << 11) + +/* SAMP: Last sample point */ +#define CAN_MSR_SAMP (1 << 10) + +/* RXM: Receive mode */ +#define CAN_MSR_RXM (1 << 9) + +/* TXM: Transmit mode */ +#define CAN_MSR_TXM (1 << 8) + +/* 7:5 Reserved, forced by hardware to 0 */ + +/* SLAKI: Sleep acknowledge interrupt */ +#define CAN_MSR_SLAKI (1 << 4) + +/* WKUI: Wakeup interrupt */ +#define CAN_MSR_WKUI (1 << 3) + +/* ERRI: Error interrupt */ +#define CAN_MSR_ERRI (1 << 2) + +/* SLAK: Sleep acknowledge */ +#define CAN_MSR_SLAK (1 << 1) + +/* INAK: Initialization acknowledge */ +#define CAN_MSR_INAK (1 << 0) + +/* --- CAN_TSR values ------------------------------------------------------ */ + +/* LOW2: Lowest priority flag for mailbox 2 */ +#define CAN_TSR_LOW2 (1 << 31) + +/* LOW1: Lowest priority flag for mailbox 1 */ +#define CAN_TSR_LOW1 (1 << 30) + +/* LOW0: Lowest priority flag for mailbox 0 */ +#define CAN_TSR_LOW0 (1 << 29) + +/* TME2: Transmit mailbox 2 empty */ +#define CAN_TSR_TME2 (1 << 28) + +/* TME1: Transmit mailbox 1 empty */ +#define CAN_TSR_TME1 (1 << 27) + +/* TME0: Transmit mailbox 0 empty */ +#define CAN_TSR_TME0 (1 << 26) + +/* CODE[1:0]: Mailbox code */ +#define CAN_TSR_CODE_MASK (0x3 << 24) + +/* ABRQ2: Abort request for mailbox 2 */ +#define CAN_TSR_TABRQ2 (1 << 23) + +/* 22:20 Reserved, forced by hardware to 0 */ + +/* TERR2: Transmission error for mailbox 2 */ +#define CAN_TSR_TERR2 (1 << 19) + +/* ALST2: Arbitration lost for mailbox 2 */ +#define CAN_TSR_ALST2 (1 << 18) + +/* TXOK2: Transmission OK for mailbox 2 */ +#define CAN_TSR_TXOK2 (1 << 17) + +/* RQCP2: Request completed mailbox 2 */ +#define CAN_TSR_RQCP2 (1 << 16) + +/* ABRQ1: Abort request for mailbox 1 */ +#define CAN_TSR_ABRQ1 (1 << 15) + +/* 14:12 Reserved, forced by hardware to 0 */ + +/* TERR1: Transmission error for mailbox 1 */ +#define CAN_TSR_TERR1 (1 << 11) + +/* ALST1: Arbitration lost for mailbox 1 */ +#define CAN_TSR_ALST1 (1 << 10) + +/* TXOK1: Transmission OK for mailbox 1 */ +#define CAN_TSR_TXOK1 (1 << 9) + +/* RQCP1: Request completed mailbox 1 */ +#define CAN_TSR_RQCP1 (1 << 8) + +/* ABRQ0: Abort request for mailbox 0 */ +#define CAN_TSR_ABRQ0 (1 << 7) + +/* 6:4 Reserved, forced by hardware to 0 */ + +/* TERR0: Transmission error for mailbox 0 */ +#define CAN_TSR_TERR0 (1 << 3) + +/* ALST0: Arbitration lost for mailbox 0 */ +#define CAN_TSR_ALST0 (1 << 2) + +/* TXOK0: Transmission OK for mailbox 0 */ +#define CAN_TSR_TXOK0 (1 << 1) + +/* RQCP0: Request completed mailbox 0 */ +#define CAN_TSR_RQCP0 (1 << 0) + +/* --- CAN_RF0R values ----------------------------------------------------- */ + +/* 31:6 Reserved, forced by hardware to 0 */ + +/* RFOM0: Release FIFO 0 output mailbox */ +#define CAN_RF0R_RFOM0 (1 << 5) + +/* FOVR0: FIFO 0 overrun */ +#define CAN_RF0R_FAVR0 (1 << 4) + +/* FULL0: FIFO 0 full */ +#define CAN_RF0R_FULL0 (1 << 3) + +/* 2 Reserved, forced by hardware to 0 */ + +/* FMP0[1:0]: FIFO 0 message pending */ +#define CAN_RF0R_FMP0_MASK (0x3 << 0) + +/* --- CAN_RF1R values ----------------------------------------------------- */ + +/* 31:6 Reserved, forced by hardware to 0 */ + +/* RFOM1: Release FIFO 1 output mailbox */ +#define CAN_RF1R_RFOM1 (1 << 5) + +/* FOVR1: FIFO 1 overrun */ +#define CAN_RF1R_FAVR1 (1 << 4) + +/* FULL1: FIFO 1 full */ +#define CAN_RF1R_FULL1 (1 << 3) + +/* 2 Reserved, forced by hardware to 0 */ + +/* FMP1[1:0]: FIFO 1 message pending */ +#define CAN_RF1R_FMP1_MASK (0x3 << 0) + +/* --- CAN_IER values ------------------------------------------------------ */ + +/* 32:18 Reserved, forced by hardware to 0 */ + +/* SLKIE: Sleep interrupt enable */ +#define CAN_IER_SLKIE (1 << 17) + +/* WKUIE: Wakeup interrupt enable */ +#define CAN_IER_WKUIE (1 << 16) + +/* ERRIE: Error interrupt enable */ +#define CAN_IER_ERRIE (1 << 15) + +/* 14:12 Reserved, forced by hardware to 0 */ + +/* LECIE: Last error code interrupt enable */ +#define CAN_IER_LECIE (1 << 11) + +/* BOFIE: Bus-off interrupt enable */ +#define CAN_IER_BOFIE (1 << 10) + +/* EPVIE: Error passive interrupt enable */ +#define CAN_IER_EPVIE (1 << 9) + +/* EWGIE: Error warning interrupt enable */ +#define CAN_IER_EWGIE (1 << 8) + +/* 7 Reserved, forced by hardware to 0 */ + +/* FOVIE1: FIFO overrun interrupt enable */ +#define CAN_IER_FOVIE1 (1 << 6) + +/* FFIE1: FIFO full interrupt enable */ +#define CAN_IER_FFIE1 (1 << 5) + +/* FMPIE1: FIFO message pending interrupt enable */ +#define CAN_IER_FMPIE1 (1 << 4) + +/* FOVIE0: FIFO overrun interrupt enable */ +#define CAN_IER_FOVIE0 (1 << 3) + +/* FFIE0: FIFO full interrupt enable */ +#define CAN_IER_FFIE0 (1 << 2) + +/* FMPIE0: FIFO message pending interrupt enable */ +#define CAN_IER_FMPIE0 (1 << 1) + +/* TMEIE: Transmit mailbox empty interrupt enable */ +#define CAN_IER_TMEIE (1 << 0) + +/* --- CAN_ESR values ------------------------------------------------------ */ + +/* REC[7:0]: Receive error counter */ +#define CAN_ESR_REC_MASK (0xF << 24) + +/* TEC[7:0]: Least significant byte of the 9-bit transmit error counter */ +#define CAN_ESR_TEC_MASK (0xF << 16) + +/* 15:7 Reserved, forced by hardware to 0 */ + +/* LEC[2:0]: Last error code */ +#define CAN_ESR_LEC_NO_ERROR (0x0 << 4) +#define CAN_ESR_LEC_STUFF_ERROR (0x1 << 4) +#define CAN_ESR_LEC_FORM_ERROR (0x2 << 4) +#define CAN_ESR_LEC_ACK_ERROR (0x3 << 4) +#define CAN_ESR_LEC_REC_ERROR (0x4 << 4) +#define CAN_ESR_LEC_DOM_ERROR (0x5 << 4) +#define CAN_ESR_LEC_CRC_ERROR (0x6 << 4) +#define CAN_ESR_LEC_SOFT_ERROR (0x7 << 4) +#define CAN_ESR_LEC_MASK (0x7 << 4) + +/* 3 Reserved, forced by hardware to 0 */ + +/* BOFF: Bus-off flag */ +#define CAN_ESR_BOFF (1 << 2) + +/* EPVF: Error passive flag */ +#define CAN_ESR_EPVF (1 << 1) + +/* EWGF: Error warning flag */ +#define CAN_ESR_EWGF (1 << 0) + +/* --- CAN_BTR values ------------------------------------------------------ */ + +/* SILM: Silent mode (debug) */ +#define CAN_BTR_SILM (1 << 31) + +/* LBKM: Loop back mode (debug) */ +#define CAN_BTR_LBKM (1 << 30) + +/* 29:26 Reserved, forced by hardware to 0 */ + +/* SJW[1:0]: Resynchronization jump width */ +#define CAN_BTR_SJW_1TQ (0x0 << 24) +#define CAN_BTR_SJW_2TQ (0x1 << 24) +#define CAN_BTR_SJW_3TQ (0x2 << 24) +#define CAN_BTR_SJW_4TQ (0x3 << 24) +#define CAN_BTR_SJW_MASK (0x3 << 24) + +/* 23 Reserved, forced by hardware to 0 */ + +/* TS2[2:0]: Time segment 2 */ +#define CAN_BTR_TS2_1TQ (0x0 << 20) +#define CAN_BTR_TS2_2TQ (0x1 << 20) +#define CAN_BTR_TS2_3TQ (0x2 << 20) +#define CAN_BTR_TS2_4TQ (0x3 << 20) +#define CAN_BTR_TS2_5TQ (0x4 << 20) +#define CAN_BTR_TS2_6TQ (0x5 << 20) +#define CAN_BTR_TS2_7TQ (0x6 << 20) +#define CAN_BTR_TS2_8TQ (0x7 << 20) +#define CAN_BTR_TS2_MASK (0x7 << 20) + +/* TS1[3:0]: Time segment 1 */ +#define CAN_BTR_TS1_1TQ (0x0 << 16) +#define CAN_BTR_TS1_2TQ (0x1 << 16) +#define CAN_BTR_TS1_3TQ (0x2 << 16) +#define CAN_BTR_TS1_4TQ (0x3 << 16) +#define CAN_BTR_TS1_5TQ (0x4 << 16) +#define CAN_BTR_TS1_6TQ (0x5 << 16) +#define CAN_BTR_TS1_7TQ (0x6 << 16) +#define CAN_BTR_TS1_8TQ (0x7 << 16) +#define CAN_BTR_TS1_9TQ (0x8 << 16) +#define CAN_BTR_TS1_10TQ (0x9 << 16) +#define CAN_BTR_TS1_11TQ (0xA << 16) +#define CAN_BTR_TS1_12TQ (0xB << 16) +#define CAN_BTR_TS1_13TQ (0xC << 16) +#define CAN_BTR_TS1_14TQ (0xD << 16) +#define CAN_BTR_TS1_15TQ (0xE << 16) +#define CAN_BTR_TS1_16TQ (0xF << 16) +#define CAN_BTR_TS1_MASK (0xF << 16) + +/* 15:10 Reserved, forced by hardware to 0 */ + +/* BRP[9:0]: Baud rate prescaler */ +#define CAN_BTR_BRP_MASK (0x1FF << 0) + +/* --- CAN_TIxR values ------------------------------------------------------ */ + +/* STID[10:0]: Standard identifier */ +#define CAN_TIxR_STID_MASK (0x3FF << 21) +#define CAN_TIxR_STID_SHIFT 21 + +/* EXID[15:0]: Extended identifier */ +#define CAN_TIxR_EXID_MASK (0x1FFFFFF << 3) +#define CAN_TIxR_EXID_SHIFT 3 + +/* IDE: Identifier extension */ +#define CAN_TIxR_IDE (1 << 2) + +/* RTR: Remote transmission request */ +#define CAN_TIxR_RTR (1 << 1) + +/* TXRQ: Transmit mailbox request */ +#define CAN_TIxR_TXRQ (1 << 0) + +/* --- CAN_TDTxR values ----------------------------------------------------- */ + +/* TIME[15:0]: Message time stamp */ +#define CAN_TDTxR_TIME_MASK (0xFFFF << 15) +#define CAN_TDTxR_TIME_SHIFT 15 + +/* 15:6 Reserved, forced by hardware to 0 */ + +/* TGT: Transmit global time */ +#define CAN_TDTxR_TGT (1 << 5) + +/* 7:4 Reserved, forced by hardware to 0 */ + +/* DLC[3:0]: Data length code */ +#define CAN_TDTxR_DLC_MASK (0xF << 0) +#define CAN_TDTxR_DLC_SHIFT 0 + +/* --- CAN_TDLxR values ----------------------------------------------------- */ + +/* DATA3[7:0]: Data byte 3 */ +/* DATA2[7:0]: Data byte 2 */ +/* DATA1[7:0]: Data byte 1 */ +/* DATA0[7:0]: Data byte 0 */ + +/* --- CAN_TDHxR values ----------------------------------------------------- */ + +/* DATA7[7:0]: Data byte 7 */ +/* DATA6[7:0]: Data byte 6 */ +/* DATA5[7:0]: Data byte 5 */ +/* DATA4[7:0]: Data byte 4 */ + +/* --- CAN_RIxR values ------------------------------------------------------ */ + +/* STID[10:0]: Standard identifier */ +#define CAN_RIxR_STID_MASK (0x3FF << 21) +#define CAN_RIxR_STID_SHIFT 21 + +/* EXID[15:0]: Extended identifier */ +#define CAN_RIxR_EXID_MASK (0x1FFFFFF << 3) +#define CAN_RIxR_EXID_SHIFT 3 + +/* IDE: Identifier extension */ +#define CAN_RIxR_IDE (1 << 2) + +/* RTR: Remote transmission request */ +#define CAN_RIxR_RTR (1 << 1) + +/* 0 Reserved */ + +/* --- CAN_RDTxR values ----------------------------------------------------- */ + +/* TIME[15:0]: Message time stamp */ +#define CAN_RDTxR_TIME_MASK (0xFFFF << 15) +#define CAN_RDTxR_TIME_SHIFT 15 + +/* FMI[7:0]: Filter match index */ +#define CAN_RDTxR_FMI_MASK (0xFF << 8) +#define CAN_RDTxR_FMI_SHIFT 8 + +/* 7:4 Reserved, forced by hardware to 0 */ + +/* DLC[3:0]: Data length code */ +#define CAN_RDTxR_DLC_MASK (0xF << 0) +#define CAN_RDTxR_DLC_SHIFT 0 + +/* --- CAN_RDLxR values ----------------------------------------------------- */ + +/* DATA3[7:0]: Data byte 3 */ +/* DATA2[7:0]: Data byte 2 */ +/* DATA1[7:0]: Data byte 1 */ +/* DATA0[7:0]: Data byte 0 */ + +/* --- CAN_RDHxR values ----------------------------------------------------- */ + +/* DATA7[7:0]: Data byte 7 */ +/* DATA6[7:0]: Data byte 6 */ +/* DATA5[7:0]: Data byte 5 */ +/* DATA4[7:0]: Data byte 4 */ + +/* --- CAN_FMR values ------------------------------------------------------- */ + +/* 31:14 Reserved, forced to reset value */ + +/* + * CAN2SB[5:0]: CAN2 start bank + * (only on connectivity line devices otherwise reserved) + */ +#define CAN_FMR_CAN2SB_MASK (0x3F << 8) +#define CAN_FMR_CAN2SB_SHIFT 15 + +/* 7:1 Reserved, forced to reset value */ + +/* FINIT: Filter init mode */ +#define CAN_FMR_FINIT (1 << 0) + +/* --- CAN_FM1R values ------------------------------------------------------ */ + +/* 31:28 Reserved, forced by hardware to 0 */ + +/* + * FBMx: Filter mode + * x is 0..27 should be calculated by a helper function making so many macros + * seems like an overkill? + */ + +/* --- CAN_FS1R values ------------------------------------------------------ */ + +/* 31:28 Reserved, forced by hardware to 0 */ + +/* + * FSCx: Filter scale configuration + * x is 0..27 should be calculated by a helper function making so many macros + * seems like an overkill? + */ + +/* --- CAN_FFA1R values ----------------------------------------------------- */ + +/* 31:28 Reserved, forced by hardware to 0 */ + +/* + * FFAx: Filter scale configuration + * x is 0..27 should be calculated by a helper function making so many macros + * seems like an overkill? + */ + +/* --- CAN_FA1R values ------------------------------------------------------ */ + +/* 31:28 Reserved, forced by hardware to 0 */ + +/* + * FACTx: Filter active + * x is 0..27 should be calculated by a helper function making so many macros + * seems like an overkill? + */ + +/* --- CAN_FiRx values ------------------------------------------------------ */ + +/* FB[31:0]: Filter bits */ + +/* --- CAN functions -------------------------------------------------------- */ + +void can_reset(u32 canport); +int can_init(u32 canport, bool ttcm, bool abom, bool awum, bool nart, + bool rflm, bool txfp, u32 sjw, u32 ts1, u32 ts2, u32 brp); + +void can_filter_init(u32 canport, u32 nr, bool scale_32bit, bool id_list_mode, + u32 fr1, u32 fr2, u32 fifo, bool enable); +void can_filter_id_mask_16bit_init(u32 canport, u32 nr, u16 id1, u16 mask1, + u16 id2, u16 mask2, u32 fifo, bool enable); +void can_filter_id_mask_32bit_init(u32 canport, u32 nr, u32 id, u32 mask, + u32 fifo, bool enable); +void can_filter_id_list_16bit_init(u32 canport, u32 nr, u16 id1, u16 id2, + u16 id3, u16 id4, u32 fifo, bool enable); +void can_filter_id_list_32bit_init(u32 canport, u32 nr, u32 id1, u32 id2, + u32 fifo, bool enable); + +void can_enable_irq(u32 canport, u32 irq); +void can_disable_irq(u32 canport, u32 irq); + +int can_transmit(u32 canport, u32 id, bool ext, bool rtr, u8 length, u8 *data); +void can_receive(u32 canport, u8 fifo, bool release, u32 *id, bool *ext, + bool *rtr, u32 *fmi, u8 *length, u8 *data); + +void can_fifo_release(u32 canport, u8 fifo); + +#endif diff --git a/include/libopencm3/stm32_common/crc.h b/include/libopencm3/stm32_common/crc.h new file mode 100644 index 0000000..5ad866e --- /dev/null +++ b/include/libopencm3/stm32_common/crc.h @@ -0,0 +1,52 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_CRC_H +#define LIBOPENCM3_CRC_H + +#include +#include + +/* --- CRC registers ------------------------------------------------------- */ + +/* Data register (CRC_DR) */ +#define CRC_DR MMIO32(CRC_BASE + 0x00) + +/* Independent data register (CRC_IDR) */ +#define CRC_IDR MMIO32(CRC_BASE + 0x04) + +/* Control register (CRC_CR) */ +#define CRC_CR MMIO32(CRC_BASE + 0x08) + +/* --- CRC_DR values ------------------------------------------------------- */ + +/* Bits[31:0] Data register */ + +/* --- CRC_IDR values ------------------------------------------------------ */ + +/* Bits[7:0] General-purpose 8-bit data register bits */ + +/* --- CRC_CR values ------------------------------------------------------- */ + +/* RESET bit */ +#define CRC_CR_RESET (1 << 0) + +/* --- CRC function prototypes --------------------------------------------- */ + +#endif diff --git a/include/libopencm3/stm32_common/dbgmcu.h b/include/libopencm3/stm32_common/dbgmcu.h new file mode 100644 index 0000000..e753f5e --- /dev/null +++ b/include/libopencm3/stm32_common/dbgmcu.h @@ -0,0 +1,60 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Gareth McMullin + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_STM32_DBGMCU_H +#define LIBOPENCM3_STM32_DBGMCU_H + +#include +#include + +/* --- DBGMCU registers ---------------------------------------------------- */ + +#define DBGMCU_IDCODE MMIO32(DBGMCU_BASE + 0x00) +#define DBGMCU_CR MMIO32(DBGMCU_BASE + 0x04) + +/* DBGMCU_CR bits */ +#define DBGMCU_CR_SLEEP 0x00000001 +#define DBGMCU_CR_STOP 0x00000002 +#define DBGMCU_CR_STANDBY 0x00000004 +#define DBGMCU_CR_TRACE_IOEN 0x00000020 +#define DBGMCU_CR_TRACE_MODE_MASK 0x000000C0 +#define DBGMCU_CR_TRACE_MODE_ASYNC 0x00000000 +#define DBGMCU_CR_TRACE_MODE_SYNC_1 0x00000040 +#define DBGMCU_CR_TRACE_MODE_SYNC_2 0x00000080 +#define DBGMCU_CR_TRACE_MODE_SYNC_4 0x000000C0 +#define DBGMCU_CR_IWDG_STOP 0x00000100 +#define DBGMCU_CR_WWDG_STOP 0x00000200 +#define DBGMCU_CR_TIM1_STOP 0x00000400 +#define DBGMCU_CR_TIM2_STOP 0x00000800 +#define DBGMCU_CR_TIM3_STOP 0x00001000 +#define DBGMCU_CR_TIM4_STOP 0x00002000 +#define DBGMCU_CR_CAN1_STOP 0x00004000 +#define DBGMCU_CR_I2C1_SMBUS_TIMEOUT 0x00008000 +#define DBGMCU_CR_I2C2_SMBUS_TIMEOUT 0x00010000 +#define DBGMCU_CR_TIM8_STOP 0x00020000 +#define DBGMCU_CR_TIM5_STOP 0x00040000 +#define DBGMCU_CR_TIM6_STOP 0x00080000 +#define DBGMCU_CR_TIM7_STOP 0x00100000 +#define DBGMCU_CR_CAN2_STOP 0x00200000 + +/* DBGMCU_IDCODE bits */ +#define DBGMCU_IDCODE_DEV_ID_MASK 0x00000fff +#define DBGMCU_IDCODE_REV_ID_MASK 0xffff0000 + +#endif diff --git a/include/libopencm3/stm32_common/exti.h b/include/libopencm3/stm32_common/exti.h new file mode 100644 index 0000000..19ab547 --- /dev/null +++ b/include/libopencm3/stm32_common/exti.h @@ -0,0 +1,70 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Mark Butler + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_EXTI_H +#define LIBOPENCM3_EXTI_H + +#include +#include + +/* --- EXTI registers ------------------------------------------------------ */ + +#define EXTI_IMR MMIO32(EXTI_BASE + 0x00) +#define EXTI_EMR MMIO32(EXTI_BASE + 0x04) +#define EXTI_RTSR MMIO32(EXTI_BASE + 0x08) +#define EXTI_FTSR MMIO32(EXTI_BASE + 0x0c) +#define EXTI_SWIER MMIO32(EXTI_BASE + 0x10) +#define EXTI_PR MMIO32(EXTI_BASE + 0x14) + +/* EXTI number definitions */ +#define EXTI0 (1 << 0) +#define EXTI1 (1 << 1) +#define EXTI2 (1 << 2) +#define EXTI3 (1 << 3) +#define EXTI4 (1 << 4) +#define EXTI5 (1 << 5) +#define EXTI6 (1 << 6) +#define EXTI7 (1 << 7) +#define EXTI8 (1 << 8) +#define EXTI9 (1 << 9) +#define EXTI10 (1 << 10) +#define EXTI11 (1 << 11) +#define EXTI12 (1 << 12) +#define EXTI13 (1 << 13) +#define EXTI14 (1 << 14) +#define EXTI15 (1 << 15) +#define EXTI16 (1 << 16) +#define EXTI17 (1 << 17) +#define EXTI18 (1 << 18) +#define EXTI19 (1 << 19) + +/* Trigger types */ +typedef enum trigger_e { + EXTI_TRIGGER_RISING, + EXTI_TRIGGER_FALLING, + EXTI_TRIGGER_BOTH, +} exti_trigger_type; + +void exti_set_trigger(u32 extis, exti_trigger_type trig); +void exti_enable_request(u32 extis); +void exti_disable_request(u32 extis); +void exti_reset_request(u32 extis); +void exti_select_source(u32 exti, u32 gpioport); + +#endif diff --git a/include/libopencm3/stm32_common/fsmc.h b/include/libopencm3/stm32_common/fsmc.h new file mode 100644 index 0000000..1d318e3 --- /dev/null +++ b/include/libopencm3/stm32_common/fsmc.h @@ -0,0 +1,284 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_FSMC_H +#define LIBOPENCM3_FSMC_H + +#include +#include + +/* --- Convenience macros -------------------------------------------------- */ + +/* TODO: Move to memorymap.h? */ +#define FSMC_BASE 0xa0000000 + +#define FSMC_BANK1_BASE 0x60000000 /* NOR / PSRAM */ +#define FSMC_BANK2_BASE 0x70000000 /* NAND flash */ +#define FSMC_BANK3_BASE 0x80000000 /* NAND flash */ +#define FSMC_BANK4_BASE 0x90000000 /* PC card */ + +/* --- FSMC registers ------------------------------------------------------ */ + +/* SRAM/NOR-Flash chip-select control registers 1..4 (FSMC_BCRx) */ +#define FSMC_BCR(x) MMIO32(FSMC_BASE + 0x00 + 8 * x) +#define FSMC_BCR1 FSMC_BCR(0) +#define FSMC_BCR2 FSMC_BCR(1) +#define FSMC_BCR3 FSMC_BCR(2) +#define FSMC_BCR4 FSMC_BCR(3) + +/* SRAM/NOR-Flash chip-select timing registers 1..4 (FSMC_BTRx) */ +#define FSMC_BTR(x) MMIO32(FSMC_BASE + 0x04 + 8 * x) +#define FSMC_BTR1 FSMC_BTR(0) +#define FSMC_BTR2 FSMC_BTR(1) +#define FSMC_BTR3 FSMC_BTR(2) +#define FSMC_BTR4 FSMC_BTR(3) + +/* SRAM/NOR-Flash write timing registers 1..4 (FSMC_BWTRx) */ +#define FSMC_BWTR(x) MMIO32(FSMC_BASE + 0x104 + 8 * x) +#define FSMC_BWTR1 FSMC_BWTR(0) +#define FSMC_BWTR2 FSMC_BWTR(1) +#define FSMC_BWTR3 FSMC_BWTR(2) +#define FSMC_BWTR4 FSMC_BWTR(3) + +/* PC Card/NAND Flash control registers 2..4 (FSMC_PCRx) */ +#define FSMC_PCR(x) MMIO32(FSMC_BASE + 0x40 + 0x20 * x) +#define FSMC_PCR2 FSMC_PCR(1) +#define FSMC_PCR3 FSMC_PCR(2) +#define FSMC_PCR4 FSMC_PCR(3) + +/* FIFO status and interrupt registers 2..4 (FSMC_SRx) */ +#define FSMC_SR(x) MMIO32(FSMC_BASE + 0x44 + 0x20 * x) +#define FSMC_SR2 FSMC_SR(1) +#define FSMC_SR3 FSMC_SR(2) +#define FSMC_SR4 FSMC_SR(3) + +/* Common memory space timing registers 2..4 (FSMC_PMEMx) */ +#define FSMC_PMEM(x) MMIO32(FSMC_BASE + 0x48 + 0x20 * x) +#define FSMC_PMEM2 FSMC_PMEM(1) +#define FSMC_PMEM3 FSMC_PMEM(2) +#define FSMC_PMEM4 FSMC_PMEM(3) + +/* Attribute memory space timing registers 2..4 (FSMC_PATTx) */ +#define FSMC_PATT(x) MMIO32(FSMC_BASE + 0x4c + 0x20 * x) +#define FSMC_PATT2 FSMC_PATT(1) +#define FSMC_PATT3 FSMC_PATT(2) +#define FSMC_PATT4 FSMC_PATT(3) + +/* I/O space timing register 4 (FSMC_PIO4) */ +#define FSMC_PIO4 MMIO32(FSMC_BASE + 0xb0) + +/* ECC result registers 2/3 (FSMC_ECCRx) */ +#define FSMC_ECCR(x) MMIO32(FSMC_BASE + 0x54 + 0x20 * x) +#define FSMC_ECCR2 FSMC_ECCR(1) +#define FSMC_ECCR3 FSMC_ECCR(2) + +/* --- FSMC_BCRx values ---------------------------------------------------- */ + +/* CBURSTRW: Write burst enable */ +#define FSMC_BCR_CBURSTRW (1 << 19) + +/* Bits 18..16: Reserved. */ + +/* ASYNCWAIT: Wait signal during asynchronous transfers */ +#define FSMC_BCR_ASYNCWAIT (1 << 15) + +/* EXTMOD: Extended mode enable */ +#define FSMC_BCR_EXTMOD (1 << 14) + +/* WAITEN: Wait enable bit */ +#define FSMC_BCR_WAITEN (1 << 13) + +/* WREN: Write enable bit */ +#define FSMC_BCR_WREN (1 << 12) + +/* WAITCFG: Wait timing configuration */ +#define FSMC_BCR_WAITCFG (1 << 11) + +/* WRAPMOD: Wrapped burst mode support */ +#define FSMC_BCR_WRAPMOD (1 << 10) + +/* WAITPOL: Wait signal polarity bit */ +#define FSMC_BCR_WAITPOL (1 << 9) + +/* BURSTEN: Burst enable bit */ +#define FSMC_BCR_BURSTEN (1 << 8) + +/* Bit 7: Reserved. */ + +/* FACCEN: Flash access enable */ +#define FSMC_BCR_FACCEN (1 << 6) + +/* MWID[5:4]: Memory databus width */ +#define FSMC_BCR_MWID (1 << 4) + +/* MTYP[3:2]: Memory type */ +#define FSMC_BCR_MTYP (1 << 2) + +/* MUXEN: Address/data multiplexing enable bit */ +#define FSMC_BCR_MUXEN (1 << 1) + +/* MBKEN: Memory bank enable bit */ +#define FSMC_BCR_MBKEN (1 << 0) + +/* --- FSMC_BTRx values ---------------------------------------------------- */ + +/* ACCMOD[29:28]: Access mode */ +#define FSMC_BTR_ACCMOD (1 << 28) + +/* DATLAT[27:24]: Data latency (for synchronous burst NOR flash) */ +#define FSMC_BTR_DATLAT (1 << 24) + +/* CLKDIV[23:20]: Clock divide ratio (for CLK signal) */ +#define FSMC_BTR_CLKDIV (1 << 20) + +/* BUSTURN[19:16]: Bus turnaround phase duration */ +#define FSMC_BTR_BUSTURN (1 << 16) + +/* DATAST[15:8]: Data-phase duration */ +#define FSMC_BTR_DATAST (1 << 8) + +/* ADDHLD[7:4]: Address-hold phase duration */ +#define FSMC_BTR_ADDHLD (1 << 4) + +/* ADDSET[3:0]: Address setup phase duration */ +#define FSMC_BTR_ADDSET (1 << 0) + +/* --- FSMC_BWTRx values --------------------------------------------------- */ + +/* ACCMOD[29:28]: Access mode */ +#define FSMC_BWTR_ACCMOD (1 << 28) + +/* DATLAT[27:24]: Data latency (for synchronous burst NOR Flash) */ +#define FSMC_BWTR_DATLAT (1 << 24) + +/* CLKDIV[23:20]: Clock divide ratio (for CLK signal) */ +#define FSMC_BWTR_CLKDIV (1 << 20) + +/* Bits 19..16: Reserved. */ + +/* DATAST[15:8]: Data-phase duration */ +#define FSMC_BWTR_DATAST (1 << 8) + +/* ADDHLD[7:4]: Address-hold phase duration */ +#define FSMC_BWTR_ADDHLD (1 << 4) + +/* ADDSET[3:0]: Address setup phase duration */ +#define FSMC_BWTR_ADDSET (1 << 0) + +/* --- FSMC_PCRx values ---------------------------------------------------- */ + +/* ECCPS[19:17]: ECC page size */ +#define FSMC_PCR_ECCPS (1 << 17) + +/* TAR[16:13]: ALE to RE delay */ +#define FSMC_PCR_TAR (1 << 13) + +/* TCLR[12:9]: CLE to RE delay */ +#define FSMC_PCR_TCLR (1 << 9) + +/* Bits 8..7: Reserved. */ + +/* ECCEN: ECC computation logic enable bit */ +#define FSMC_PCR_ECCEN (1 << 6) + +/* PWID[5:4]: Databus width */ +#define FSMC_PCR_PWID (1 << 4) + +/* PTYP: Memory type */ +#define FSMC_PCR_PTYP (1 << 3) + +/* PBKEN: PC Card/NAND Flash memory bank enable bit */ +#define FSMC_PCR_PBKEN (1 << 2) + +/* PWAITEN: Wait feature enable bit */ +#define FSMC_PCR_PWAITEN (1 << 1) + +/* Bit 0: Reserved. */ + +/* --- FSMC_SRx values ----------------------------------------------------- */ + +/* FEMPT: FIFO empty */ +#define FSMC_SR_FEMPT (1 << 6) + +/* IFEN: Interrupt falling edge detection enable bit */ +#define FSMC_SR_IFEN (1 << 5) + +/* ILEN: Interrupt high-level detection enable bit */ +#define FSMC_SR_ILEN (1 << 4) + +/* IREN: Interrupt rising edge detection enable bit */ +#define FSMC_SR_IREN (1 << 3) + +/* IFS: Interrupt falling edge status */ +#define FSMC_SR_IFS (1 << 2) + +/* ILS: Interrupt high-level status */ +#define FSMC_SR_ILS (1 << 1) + +/* IRS: Interrupt rising edge status */ +#define FSMC_SR_IRS (1 << 0) + +/* --- FSMC_PMEMx values --------------------------------------------------- */ + +/* MEMHIZx[31:24]: Common memory x databus HiZ time */ +#define FSMC_PMEM_MEMHIZX (1 << 24) + +/* MEMHOLDx[23:16]: Common memory x hold time */ +#define FSMC_PMEM_MEMHOLDX (1 << 16) + +/* MEMWAITx[15:8]: Common memory x wait time */ +#define FSMC_PMEM_MEMHOLDX (1 << 8) + +/* MEMSETx[7:0]: Common memory x setup time */ +#define FSMC_PMEM_MEMSETX (1 << 0) + +/* --- FSMC_PATTx values --------------------------------------------------- */ + +/* ATTHIZx[31:24]: Attribute memory x databus HiZ time */ +#define FSMC_PATT_ATTHIZX (1 << 24) + +/* ATTHOLDx[23:16]: Attribute memory x hold time */ +#define FSMC_PATT_ATTHOLDX (1 << 16) + +/* ATTWAITx[15:8]: Attribute memory x wait time */ +#define FSMC_PATT_ATTWAITX (1 << 8) + +/* ATTSETx[7:0]: Attribute memory x setup time */ +#define FSMC_PATT_ATTSETX (1 << 0) + +/* --- FSMC_PIO4 values ---------------------------------------------------- */ + +/* IOHIZx[31:24]: I/O x databus HiZ time */ +#define FSMC_PIO4_IOHIZX (1 << 24) + +/* IOHOLDx[23:16]: I/O x hold time */ +#define FSMC_PIO4_IOHOLDX (1 << 16) + +/* IOWAITx[15:8]: I/O x wait time */ +#define FSMC_PIO4_IOWAITX (1 << 8) + +/* IOSETx[7:0]: I/O x setup time */ +#define FSMC_PIO4_IOSETX (1 << 0) + +/* --- FSMC_ECCRx values --------------------------------------------------- */ + +/* ECCx[31:0]: ECC result */ +#define FSMC_ECCR_ECCX (1 << 0) + +#endif diff --git a/include/libopencm3/stm32_common/iwdg.h b/include/libopencm3/stm32_common/iwdg.h new file mode 100644 index 0000000..bf2784a --- /dev/null +++ b/include/libopencm3/stm32_common/iwdg.h @@ -0,0 +1,75 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_IWDG_H +#define LIBOPENCM3_IWDG_H + +#include +#include + +/* --- IWDG registers ------------------------------------------------------ */ + +/* Key Register (IWDG_KR) */ +#define IWDG_KR MMIO32(IWDG_BASE + 0x00) + +/* Prescaler register (IWDG_PR) */ +#define IWDG_PR MMIO32(IWDG_BASE + 0x04) + +/* Reload register (IWDG_RLR) */ +#define IWDG_RLR MMIO32(IWDG_BASE + 0x08) + +/* Status register (IWDG_SR) */ +#define IWDG_SR MMIO32(IWDG_BASE + 0x0C) + +/* --- IWDG_KR values ------------------------------------------------------ */ + +/* KEY[15:0]: Key value */ +#define IWDG_KR_RESET 0xAAAA +#define IWDG_KR_UNLOCK 0x5555 +#define IWDG_KR_START 0xCCCC + +/* --- IWDG_PR values ------------------------------------------------------ */ + +/* PR[2:0]: Prescaler divider */ +#define IWDG_PR_LSB 0 +#define IWDG_PR_DIV4 0x0 +#define IWDG_PR_DIV8 0x1 +#define IWDG_PR_DIV16 0x2 +#define IWDG_PR_DIV32 0x3 +#define IWDG_PR_DIV64 0x4 +#define IWDG_PR_DIV128 0x5 +#define IWDG_PR_DIV256 0x6 +/* Double definition: 0x06 and 0x07 both mean DIV256 as per datasheet. */ +/* #define IWDG_PR_DIV256 0x7 */ + +/* --- IWDG_RLR values ----------------------------------------------------- */ + +/* RL[11:0]: Watchdog counter reload value */ + +/* --- IWDG_SR values ------------------------------------------------------ */ + +/* RVU: Watchdog counter reload value update */ +#define IWDG_SR_RVU (1 << 1) + +/* PVU: Watchdog prescaler value update */ +#define IWDG_SR_PVU (1 << 0) + +/* --- IWDG funtion prototypes---------------------------------------------- */ + +#endif diff --git a/include/libopencm3/stm32_common/wwdg.h b/include/libopencm3/stm32_common/wwdg.h new file mode 100644 index 0000000..552d02e --- /dev/null +++ b/include/libopencm3/stm32_common/wwdg.h @@ -0,0 +1,74 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_WWDG_H +#define LIBOPENCM3_WWDG_H + +#include +#include + +/* --- WWDG registers ------------------------------------------------------ */ + +/* Control register (WWDG_CR) */ +#define WWDG_CR MMIO32(WWDG_BASE + 0x00) + +/* Configuration register (WWDG_CFR) */ +#define WWDG_CFR MMIO32(WWDG_BASE + 0x04) + +/* Status register (WWDG_SR) */ +#define WWDG_SR MMIO32(WWDG_BASE + 0x08) + +/* --- WWDG_CR values ------------------------------------------------------ */ + +/* WDGA: Activation bit */ +#define WWDG_CR_WDGA (1 << 7) + +/* T[6:0]: 7-bit counter (MSB to LSB) */ +#define WWDG_CR_T_LSB 0 +#define WWDG_CR_T0 (1 << 0) +#define WWDG_CR_T1 (1 << 1) +#define WWDG_CR_T2 (1 << 2) +#define WWDG_CR_T3 (1 << 3) +#define WWDG_CR_T4 (1 << 4) +#define WWDG_CR_T5 (1 << 5) +#define WWDG_CR_T6 (1 << 6) + +/* --- WWDG_CFR values ----------------------------------------------------- */ + +/* EWI: Early wakeup interrupt */ +#define WWDG_CFR_EWI (1 << 9) + +/* WDGTB[8:7]: Timer base */ +#define WWDG_CFR_WDGTB_LSB 7 +#define WWDG_CFR_WDGTB_CK_DIV1 0x0 +#define WWDG_CFR_WDGTB_CK_DIV2 0x1 +#define WWDG_CFR_WDGTB_CK_DIV4 0x2 +#define WWDG_CFR_WDGTB_CK_DIV8 0x3 + +/* W[6:0]: 7-bit window value */ +#define WWDG_CFG_W_LSB 0 + +/* --- WWDG_SR values ------------------------------------------------------ */ + +/* EWIF: Early wakeup interrupt flag */ +#define WWDG_SR_EWIF (1 << 0) + +/* --- WWDG funtion prototypes---------------------------------------------- */ + +#endif diff --git a/include/libopencm3/stm32f1/can.h b/include/libopencm3/stm32f1/can.h deleted file mode 100644 index 1aa95a1..0000000 --- a/include/libopencm3/stm32f1/can.h +++ /dev/null @@ -1,642 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_CAN_H -#define LIBOPENCM3_CAN_H - -#include -#include - -/* --- Convenience macros -------------------------------------------------- */ - -/* CAN register base adresses (for convenience) */ -#define CAN1 BX_CAN1_BASE -#define CAN2 BX_CAN2_BASE - -/* --- CAN registers ------------------------------------------------------- */ - -/* CAN master control register (CAN_MCR) */ -#define CAN_MCR(can_base) MMIO32(can_base + 0x000) -/* CAN master status register (CAN_MSR) */ -#define CAN_MSR(can_base) MMIO32(can_base + 0x004) -/* CAN transmit status register (CAN_TSR) */ -#define CAN_TSR(can_base) MMIO32(can_base + 0x008) - -/* CAN receive FIFO 0 register (CAN_RF0R) */ -#define CAN_RF0R(can_base) MMIO32(can_base + 0x00C) -/* CAN receive FIFO 1 register (CAN_RF1R) */ -#define CAN_RF1R(can_base) MMIO32(can_base + 0x010) - -/* CAN interrupt enable register (CAN_IER) */ -#define CAN_IER(can_base) MMIO32(can_base + 0x014) -/* CAN error status register (CAN_ESR) */ -#define CAN_ESR(can_base) MMIO32(can_base + 0x018) -/* CAN bit timing register (CAN_BTR) */ -#define CAN_BTR(can_base) MMIO32(can_base + 0x01C) - -/* Registers in the offset range 0x020 to 0x17F are reserved. */ - -/* --- CAN mailbox registers ----------------------------------------------- */ - -/* CAN mailbox / FIFO register offsets */ -#define CAN_MBOX0 0x180 -#define CAN_MBOX1 0x190 -#define CAN_MBOX2 0x1A0 -#define CAN_FIFO0 0x1B0 -#define CAN_FIFO1 0x1C0 - -/* CAN TX mailbox identifier register (CAN_TIxR) */ -#define CAN_TIxR(can_base, mbox) MMIO32(can_base + mbox + 0x0) -#define CAN_TI0R(can_base) CAN_TIxR(can_base, CAN_MBOX0) -#define CAN_TI1R(can_base) CAN_TIxR(can_base, CAN_MBOX1) -#define CAN_TI2R(can_base) CAN_TIxR(can_base, CAN_MBOX2) - -/* CAN mailbox data length control and time stamp register (CAN_TDTxR) */ -#define CAN_TDTxR(can_base, mbox) MMIO32(can_base + mbox + 0x4) -#define CAN_TDT0R(can_base) CAN_TDTxR(can_base, CAN_MBOX0) -#define CAN_TDT1R(can_base) CAN_TDTxR(can_base, CAN_MBOX1) -#define CAN_TDT2R(can_base) CAN_TDTxR(can_base, CAN_MBOX2) - -/* CAN mailbox data low register (CAN_TDLxR) */ -#define CAN_TDLxR(can_base, mbox) MMIO32(can_base + mbox + 0x8) -#define CAN_TDL0R(can_base) CAN_TDLxR(can_base, CAN_MBOX0) -#define CAN_TDL1R(can_base) CAN_TDLxR(can_base, CAN_MBOX1) -#define CAN_TDL2R(can_base) CAN_TDLxR(can_base, CAN_MBOX2) - -/* CAN mailbox data high register (CAN_TDHxR) */ -#define CAN_TDHxR(can_base, mbox) MMIO32(can_base + mbox + 0xC) -#define CAN_TDH0R(can_base) CAN_TDHxR(can_base, CAN_MBOX0) -#define CAN_TDH1R(can_base) CAN_TDHxR(can_base, CAN_MBOX1) -#define CAN_TDH2R(can_base) CAN_TDHxR(can_base, CAN_MBOX2) - -/* CAN RX FIFO identifier register (CAN_RIxR) */ -#define CAN_RIxR(can_base, fifo) MMIO32(can_base + fifo + 0x0) -#define CAN_RI0R(can_base) CAN_RIxR(can_base, CAN_FIFO0) -#define CAN_RI1R(can_base) CAN_RIxR(can_base, CAN_FIFO1) - -/* CAN RX FIFO mailbox data length control & time stamp register (CAN_RDTxR) */ -#define CAN_RDTxR(can_base, fifo) MMIO32(can_base + fifo + 0x4) -#define CAN_RDT0R(can_base) CAN_RDTxR(can_base, CAN_FIFO0) -#define CAN_RDT1R(can_base) CAN_RDTxR(can_base, CAN_FIFO1) - -/* CAN RX FIFO mailbox data low register (CAN_RDLxR) */ -#define CAN_RDLxR(can_base, fifo) MMIO32(can_base + fifo + 0x8) -#define CAN_RDL0R(can_base) CAN_RDLxR(can_base, CAN_FIFO0) -#define CAN_RDL1R(can_base) CAN_RDLxR(can_base, CAN_FIFO1) - -/* CAN RX FIFO mailbox data high register (CAN_RDHxR) */ -#define CAN_RDHxR(can_base, fifo) MMIO32(can_base + fifo + 0xC) -#define CAN_RDH0R(can_base) CAN_RDHxR(can_base, CAN_FIFO0) -#define CAN_RDH1R(can_base) CAN_RDHxR(can_base, CAN_FIFO1) - -/* --- CAN filter registers ------------------------------------------------ */ - -/* CAN filter master register (CAN_FMR) */ -#define CAN_FMR(can_base) MMIO32(can_base + 0x200) - -/* CAN filter mode register (CAN_FM1R) */ -#define CAN_FM1R(can_base) MMIO32(can_base + 0x204) - -/* Register offset 0x208 is reserved. */ - -/* CAN filter scale register (CAN_FS1R) */ -#define CAN_FS1R(can_base) MMIO32(can_base + 0x20C) - -/* Register offset 0x210 is reserved. */ - -/* CAN filter FIFO assignement register (CAN_FFA1R) */ -#define CAN_FFA1R(can_base) MMIO32(can_base + 0x214) - -/* Register offset 0x218 is reserved. */ - -/* CAN filter activation register (CAN_FA1R) */ -#define CAN_FA1R(can_base) MMIO32(can_base + 0x21C) - -/* Register offset 0x220 is reserved. */ - -/* Registers with offset 0x224 to 0x23F are reserved. */ - -/* CAN filter bank registers (CAN_FiRx) */ -/* - * Connectivity line devices have 28 banks so the bank ID spans 0..27 - * all other devices have 14 banks so the bank ID spans 0..13. - */ -#define CAN_FiR1(can_base, bank) MMIO32(can_base + 0x240 + (bank * 0x8) + 0x0) -#define CAN_FiR2(can_base, bank) MMIO32(can_base + 0x240 + (bank * 0x8) + 0x4) - -/* --- CAN_MCR values ------------------------------------------------------ */ - -/* 31:17 Reserved, forced by hardware to 0 */ - -/* DBF: Debug freeze */ -#define CAN_MCR_DBF (1 << 16) - -/* RESET: bxCAN software master reset */ -#define CAN_MCR_RESET (1 << 15) - -/* 14:8 Reserved, forced by hardware to 0 */ - -/* TTCM: Time triggered communication mode */ -#define CAN_MCR_TTCM (1 << 7) - -/* ABOM: Automatic bus-off management */ -#define CAN_MCR_ABOM (1 << 6) - -/* AWUM: Automatic wakeup mode */ -#define CAN_MCR_AWUM (1 << 5) - -/* NART: No automatic retransmission */ -#define CAN_MCR_NART (1 << 4) - -/* RFLM: Receive FIFO locked mode */ -#define CAN_MCR_RFLM (1 << 3) - -/* TXFP: Transmit FIFO priority */ -#define CAN_MCR_TXFP (1 << 2) - -/* SLEEP: Sleep mode request */ -#define CAN_MCR_SLEEP (1 << 1) - -/* INRQ: Initialization request */ -#define CAN_MCR_INRQ (1 << 0) - -/* --- CAN_MSR values ------------------------------------------------------ */ - -/* 31:12 Reserved, forced by hardware to 0 */ - -/* RX: CAN Rx signal */ -#define CAN_MSR_RX (1 << 11) - -/* SAMP: Last sample point */ -#define CAN_MSR_SAMP (1 << 10) - -/* RXM: Receive mode */ -#define CAN_MSR_RXM (1 << 9) - -/* TXM: Transmit mode */ -#define CAN_MSR_TXM (1 << 8) - -/* 7:5 Reserved, forced by hardware to 0 */ - -/* SLAKI: Sleep acknowledge interrupt */ -#define CAN_MSR_SLAKI (1 << 4) - -/* WKUI: Wakeup interrupt */ -#define CAN_MSR_WKUI (1 << 3) - -/* ERRI: Error interrupt */ -#define CAN_MSR_ERRI (1 << 2) - -/* SLAK: Sleep acknowledge */ -#define CAN_MSR_SLAK (1 << 1) - -/* INAK: Initialization acknowledge */ -#define CAN_MSR_INAK (1 << 0) - -/* --- CAN_TSR values ------------------------------------------------------ */ - -/* LOW2: Lowest priority flag for mailbox 2 */ -#define CAN_TSR_LOW2 (1 << 31) - -/* LOW1: Lowest priority flag for mailbox 1 */ -#define CAN_TSR_LOW1 (1 << 30) - -/* LOW0: Lowest priority flag for mailbox 0 */ -#define CAN_TSR_LOW0 (1 << 29) - -/* TME2: Transmit mailbox 2 empty */ -#define CAN_TSR_TME2 (1 << 28) - -/* TME1: Transmit mailbox 1 empty */ -#define CAN_TSR_TME1 (1 << 27) - -/* TME0: Transmit mailbox 0 empty */ -#define CAN_TSR_TME0 (1 << 26) - -/* CODE[1:0]: Mailbox code */ -#define CAN_TSR_CODE_MASK (0x3 << 24) - -/* ABRQ2: Abort request for mailbox 2 */ -#define CAN_TSR_TABRQ2 (1 << 23) - -/* 22:20 Reserved, forced by hardware to 0 */ - -/* TERR2: Transmission error for mailbox 2 */ -#define CAN_TSR_TERR2 (1 << 19) - -/* ALST2: Arbitration lost for mailbox 2 */ -#define CAN_TSR_ALST2 (1 << 18) - -/* TXOK2: Transmission OK for mailbox 2 */ -#define CAN_TSR_TXOK2 (1 << 17) - -/* RQCP2: Request completed mailbox 2 */ -#define CAN_TSR_RQCP2 (1 << 16) - -/* ABRQ1: Abort request for mailbox 1 */ -#define CAN_TSR_ABRQ1 (1 << 15) - -/* 14:12 Reserved, forced by hardware to 0 */ - -/* TERR1: Transmission error for mailbox 1 */ -#define CAN_TSR_TERR1 (1 << 11) - -/* ALST1: Arbitration lost for mailbox 1 */ -#define CAN_TSR_ALST1 (1 << 10) - -/* TXOK1: Transmission OK for mailbox 1 */ -#define CAN_TSR_TXOK1 (1 << 9) - -/* RQCP1: Request completed mailbox 1 */ -#define CAN_TSR_RQCP1 (1 << 8) - -/* ABRQ0: Abort request for mailbox 0 */ -#define CAN_TSR_ABRQ0 (1 << 7) - -/* 6:4 Reserved, forced by hardware to 0 */ - -/* TERR0: Transmission error for mailbox 0 */ -#define CAN_TSR_TERR0 (1 << 3) - -/* ALST0: Arbitration lost for mailbox 0 */ -#define CAN_TSR_ALST0 (1 << 2) - -/* TXOK0: Transmission OK for mailbox 0 */ -#define CAN_TSR_TXOK0 (1 << 1) - -/* RQCP0: Request completed mailbox 0 */ -#define CAN_TSR_RQCP0 (1 << 0) - -/* --- CAN_RF0R values ----------------------------------------------------- */ - -/* 31:6 Reserved, forced by hardware to 0 */ - -/* RFOM0: Release FIFO 0 output mailbox */ -#define CAN_RF0R_RFOM0 (1 << 5) - -/* FOVR0: FIFO 0 overrun */ -#define CAN_RF0R_FAVR0 (1 << 4) - -/* FULL0: FIFO 0 full */ -#define CAN_RF0R_FULL0 (1 << 3) - -/* 2 Reserved, forced by hardware to 0 */ - -/* FMP0[1:0]: FIFO 0 message pending */ -#define CAN_RF0R_FMP0_MASK (0x3 << 0) - -/* --- CAN_RF1R values ----------------------------------------------------- */ - -/* 31:6 Reserved, forced by hardware to 0 */ - -/* RFOM1: Release FIFO 1 output mailbox */ -#define CAN_RF1R_RFOM1 (1 << 5) - -/* FOVR1: FIFO 1 overrun */ -#define CAN_RF1R_FAVR1 (1 << 4) - -/* FULL1: FIFO 1 full */ -#define CAN_RF1R_FULL1 (1 << 3) - -/* 2 Reserved, forced by hardware to 0 */ - -/* FMP1[1:0]: FIFO 1 message pending */ -#define CAN_RF1R_FMP1_MASK (0x3 << 0) - -/* --- CAN_IER values ------------------------------------------------------ */ - -/* 32:18 Reserved, forced by hardware to 0 */ - -/* SLKIE: Sleep interrupt enable */ -#define CAN_IER_SLKIE (1 << 17) - -/* WKUIE: Wakeup interrupt enable */ -#define CAN_IER_WKUIE (1 << 16) - -/* ERRIE: Error interrupt enable */ -#define CAN_IER_ERRIE (1 << 15) - -/* 14:12 Reserved, forced by hardware to 0 */ - -/* LECIE: Last error code interrupt enable */ -#define CAN_IER_LECIE (1 << 11) - -/* BOFIE: Bus-off interrupt enable */ -#define CAN_IER_BOFIE (1 << 10) - -/* EPVIE: Error passive interrupt enable */ -#define CAN_IER_EPVIE (1 << 9) - -/* EWGIE: Error warning interrupt enable */ -#define CAN_IER_EWGIE (1 << 8) - -/* 7 Reserved, forced by hardware to 0 */ - -/* FOVIE1: FIFO overrun interrupt enable */ -#define CAN_IER_FOVIE1 (1 << 6) - -/* FFIE1: FIFO full interrupt enable */ -#define CAN_IER_FFIE1 (1 << 5) - -/* FMPIE1: FIFO message pending interrupt enable */ -#define CAN_IER_FMPIE1 (1 << 4) - -/* FOVIE0: FIFO overrun interrupt enable */ -#define CAN_IER_FOVIE0 (1 << 3) - -/* FFIE0: FIFO full interrupt enable */ -#define CAN_IER_FFIE0 (1 << 2) - -/* FMPIE0: FIFO message pending interrupt enable */ -#define CAN_IER_FMPIE0 (1 << 1) - -/* TMEIE: Transmit mailbox empty interrupt enable */ -#define CAN_IER_TMEIE (1 << 0) - -/* --- CAN_ESR values ------------------------------------------------------ */ - -/* REC[7:0]: Receive error counter */ -#define CAN_ESR_REC_MASK (0xF << 24) - -/* TEC[7:0]: Least significant byte of the 9-bit transmit error counter */ -#define CAN_ESR_TEC_MASK (0xF << 16) - -/* 15:7 Reserved, forced by hardware to 0 */ - -/* LEC[2:0]: Last error code */ -#define CAN_ESR_LEC_NO_ERROR (0x0 << 4) -#define CAN_ESR_LEC_STUFF_ERROR (0x1 << 4) -#define CAN_ESR_LEC_FORM_ERROR (0x2 << 4) -#define CAN_ESR_LEC_ACK_ERROR (0x3 << 4) -#define CAN_ESR_LEC_REC_ERROR (0x4 << 4) -#define CAN_ESR_LEC_DOM_ERROR (0x5 << 4) -#define CAN_ESR_LEC_CRC_ERROR (0x6 << 4) -#define CAN_ESR_LEC_SOFT_ERROR (0x7 << 4) -#define CAN_ESR_LEC_MASK (0x7 << 4) - -/* 3 Reserved, forced by hardware to 0 */ - -/* BOFF: Bus-off flag */ -#define CAN_ESR_BOFF (1 << 2) - -/* EPVF: Error passive flag */ -#define CAN_ESR_EPVF (1 << 1) - -/* EWGF: Error warning flag */ -#define CAN_ESR_EWGF (1 << 0) - -/* --- CAN_BTR values ------------------------------------------------------ */ - -/* SILM: Silent mode (debug) */ -#define CAN_BTR_SILM (1 << 31) - -/* LBKM: Loop back mode (debug) */ -#define CAN_BTR_LBKM (1 << 30) - -/* 29:26 Reserved, forced by hardware to 0 */ - -/* SJW[1:0]: Resynchronization jump width */ -#define CAN_BTR_SJW_1TQ (0x0 << 24) -#define CAN_BTR_SJW_2TQ (0x1 << 24) -#define CAN_BTR_SJW_3TQ (0x2 << 24) -#define CAN_BTR_SJW_4TQ (0x3 << 24) -#define CAN_BTR_SJW_MASK (0x3 << 24) - -/* 23 Reserved, forced by hardware to 0 */ - -/* TS2[2:0]: Time segment 2 */ -#define CAN_BTR_TS2_1TQ (0x0 << 20) -#define CAN_BTR_TS2_2TQ (0x1 << 20) -#define CAN_BTR_TS2_3TQ (0x2 << 20) -#define CAN_BTR_TS2_4TQ (0x3 << 20) -#define CAN_BTR_TS2_5TQ (0x4 << 20) -#define CAN_BTR_TS2_6TQ (0x5 << 20) -#define CAN_BTR_TS2_7TQ (0x6 << 20) -#define CAN_BTR_TS2_8TQ (0x7 << 20) -#define CAN_BTR_TS2_MASK (0x7 << 20) - -/* TS1[3:0]: Time segment 1 */ -#define CAN_BTR_TS1_1TQ (0x0 << 16) -#define CAN_BTR_TS1_2TQ (0x1 << 16) -#define CAN_BTR_TS1_3TQ (0x2 << 16) -#define CAN_BTR_TS1_4TQ (0x3 << 16) -#define CAN_BTR_TS1_5TQ (0x4 << 16) -#define CAN_BTR_TS1_6TQ (0x5 << 16) -#define CAN_BTR_TS1_7TQ (0x6 << 16) -#define CAN_BTR_TS1_8TQ (0x7 << 16) -#define CAN_BTR_TS1_9TQ (0x8 << 16) -#define CAN_BTR_TS1_10TQ (0x9 << 16) -#define CAN_BTR_TS1_11TQ (0xA << 16) -#define CAN_BTR_TS1_12TQ (0xB << 16) -#define CAN_BTR_TS1_13TQ (0xC << 16) -#define CAN_BTR_TS1_14TQ (0xD << 16) -#define CAN_BTR_TS1_15TQ (0xE << 16) -#define CAN_BTR_TS1_16TQ (0xF << 16) -#define CAN_BTR_TS1_MASK (0xF << 16) - -/* 15:10 Reserved, forced by hardware to 0 */ - -/* BRP[9:0]: Baud rate prescaler */ -#define CAN_BTR_BRP_MASK (0x1FF << 0) - -/* --- CAN_TIxR values ------------------------------------------------------ */ - -/* STID[10:0]: Standard identifier */ -#define CAN_TIxR_STID_MASK (0x3FF << 21) -#define CAN_TIxR_STID_SHIFT 21 - -/* EXID[15:0]: Extended identifier */ -#define CAN_TIxR_EXID_MASK (0x1FFFFFF << 3) -#define CAN_TIxR_EXID_SHIFT 3 - -/* IDE: Identifier extension */ -#define CAN_TIxR_IDE (1 << 2) - -/* RTR: Remote transmission request */ -#define CAN_TIxR_RTR (1 << 1) - -/* TXRQ: Transmit mailbox request */ -#define CAN_TIxR_TXRQ (1 << 0) - -/* --- CAN_TDTxR values ----------------------------------------------------- */ - -/* TIME[15:0]: Message time stamp */ -#define CAN_TDTxR_TIME_MASK (0xFFFF << 15) -#define CAN_TDTxR_TIME_SHIFT 15 - -/* 15:6 Reserved, forced by hardware to 0 */ - -/* TGT: Transmit global time */ -#define CAN_TDTxR_TGT (1 << 5) - -/* 7:4 Reserved, forced by hardware to 0 */ - -/* DLC[3:0]: Data length code */ -#define CAN_TDTxR_DLC_MASK (0xF << 0) -#define CAN_TDTxR_DLC_SHIFT 0 - -/* --- CAN_TDLxR values ----------------------------------------------------- */ - -/* DATA3[7:0]: Data byte 3 */ -/* DATA2[7:0]: Data byte 2 */ -/* DATA1[7:0]: Data byte 1 */ -/* DATA0[7:0]: Data byte 0 */ - -/* --- CAN_TDHxR values ----------------------------------------------------- */ - -/* DATA7[7:0]: Data byte 7 */ -/* DATA6[7:0]: Data byte 6 */ -/* DATA5[7:0]: Data byte 5 */ -/* DATA4[7:0]: Data byte 4 */ - -/* --- CAN_RIxR values ------------------------------------------------------ */ - -/* STID[10:0]: Standard identifier */ -#define CAN_RIxR_STID_MASK (0x3FF << 21) -#define CAN_RIxR_STID_SHIFT 21 - -/* EXID[15:0]: Extended identifier */ -#define CAN_RIxR_EXID_MASK (0x1FFFFFF << 3) -#define CAN_RIxR_EXID_SHIFT 3 - -/* IDE: Identifier extension */ -#define CAN_RIxR_IDE (1 << 2) - -/* RTR: Remote transmission request */ -#define CAN_RIxR_RTR (1 << 1) - -/* 0 Reserved */ - -/* --- CAN_RDTxR values ----------------------------------------------------- */ - -/* TIME[15:0]: Message time stamp */ -#define CAN_RDTxR_TIME_MASK (0xFFFF << 15) -#define CAN_RDTxR_TIME_SHIFT 15 - -/* FMI[7:0]: Filter match index */ -#define CAN_RDTxR_FMI_MASK (0xFF << 8) -#define CAN_RDTxR_FMI_SHIFT 8 - -/* 7:4 Reserved, forced by hardware to 0 */ - -/* DLC[3:0]: Data length code */ -#define CAN_RDTxR_DLC_MASK (0xF << 0) -#define CAN_RDTxR_DLC_SHIFT 0 - -/* --- CAN_RDLxR values ----------------------------------------------------- */ - -/* DATA3[7:0]: Data byte 3 */ -/* DATA2[7:0]: Data byte 2 */ -/* DATA1[7:0]: Data byte 1 */ -/* DATA0[7:0]: Data byte 0 */ - -/* --- CAN_RDHxR values ----------------------------------------------------- */ - -/* DATA7[7:0]: Data byte 7 */ -/* DATA6[7:0]: Data byte 6 */ -/* DATA5[7:0]: Data byte 5 */ -/* DATA4[7:0]: Data byte 4 */ - -/* --- CAN_FMR values ------------------------------------------------------- */ - -/* 31:14 Reserved, forced to reset value */ - -/* - * CAN2SB[5:0]: CAN2 start bank - * (only on connectivity line devices otherwise reserved) - */ -#define CAN_FMR_CAN2SB_MASK (0x3F << 8) -#define CAN_FMR_CAN2SB_SHIFT 15 - -/* 7:1 Reserved, forced to reset value */ - -/* FINIT: Filter init mode */ -#define CAN_FMR_FINIT (1 << 0) - -/* --- CAN_FM1R values ------------------------------------------------------ */ - -/* 31:28 Reserved, forced by hardware to 0 */ - -/* - * FBMx: Filter mode - * x is 0..27 should be calculated by a helper function making so many macros - * seems like an overkill? - */ - -/* --- CAN_FS1R values ------------------------------------------------------ */ - -/* 31:28 Reserved, forced by hardware to 0 */ - -/* - * FSCx: Filter scale configuration - * x is 0..27 should be calculated by a helper function making so many macros - * seems like an overkill? - */ - -/* --- CAN_FFA1R values ----------------------------------------------------- */ - -/* 31:28 Reserved, forced by hardware to 0 */ - -/* - * FFAx: Filter scale configuration - * x is 0..27 should be calculated by a helper function making so many macros - * seems like an overkill? - */ - -/* --- CAN_FA1R values ------------------------------------------------------ */ - -/* 31:28 Reserved, forced by hardware to 0 */ - -/* - * FACTx: Filter active - * x is 0..27 should be calculated by a helper function making so many macros - * seems like an overkill? - */ - -/* --- CAN_FiRx values ------------------------------------------------------ */ - -/* FB[31:0]: Filter bits */ - -/* --- CAN functions -------------------------------------------------------- */ - -void can_reset(u32 canport); -int can_init(u32 canport, bool ttcm, bool abom, bool awum, bool nart, - bool rflm, bool txfp, u32 sjw, u32 ts1, u32 ts2, u32 brp); - -void can_filter_init(u32 canport, u32 nr, bool scale_32bit, bool id_list_mode, - u32 fr1, u32 fr2, u32 fifo, bool enable); -void can_filter_id_mask_16bit_init(u32 canport, u32 nr, u16 id1, u16 mask1, - u16 id2, u16 mask2, u32 fifo, bool enable); -void can_filter_id_mask_32bit_init(u32 canport, u32 nr, u32 id, u32 mask, - u32 fifo, bool enable); -void can_filter_id_list_16bit_init(u32 canport, u32 nr, u16 id1, u16 id2, - u16 id3, u16 id4, u32 fifo, bool enable); -void can_filter_id_list_32bit_init(u32 canport, u32 nr, u32 id1, u32 id2, - u32 fifo, bool enable); - -void can_enable_irq(u32 canport, u32 irq); -void can_disable_irq(u32 canport, u32 irq); - -int can_transmit(u32 canport, u32 id, bool ext, bool rtr, u8 length, u8 *data); -void can_receive(u32 canport, u8 fifo, bool release, u32 *id, bool *ext, - bool *rtr, u32 *fmi, u8 *length, u8 *data); - -void can_fifo_release(u32 canport, u8 fifo); - -#endif diff --git a/include/libopencm3/stm32f1/crc.h b/include/libopencm3/stm32f1/crc.h deleted file mode 100644 index 5ad866e..0000000 --- a/include/libopencm3/stm32f1/crc.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_CRC_H -#define LIBOPENCM3_CRC_H - -#include -#include - -/* --- CRC registers ------------------------------------------------------- */ - -/* Data register (CRC_DR) */ -#define CRC_DR MMIO32(CRC_BASE + 0x00) - -/* Independent data register (CRC_IDR) */ -#define CRC_IDR MMIO32(CRC_BASE + 0x04) - -/* Control register (CRC_CR) */ -#define CRC_CR MMIO32(CRC_BASE + 0x08) - -/* --- CRC_DR values ------------------------------------------------------- */ - -/* Bits[31:0] Data register */ - -/* --- CRC_IDR values ------------------------------------------------------ */ - -/* Bits[7:0] General-purpose 8-bit data register bits */ - -/* --- CRC_CR values ------------------------------------------------------- */ - -/* RESET bit */ -#define CRC_CR_RESET (1 << 0) - -/* --- CRC function prototypes --------------------------------------------- */ - -#endif diff --git a/include/libopencm3/stm32f1/dbgmcu.h b/include/libopencm3/stm32f1/dbgmcu.h deleted file mode 100644 index e753f5e..0000000 --- a/include/libopencm3/stm32f1/dbgmcu.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Gareth McMullin - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_STM32_DBGMCU_H -#define LIBOPENCM3_STM32_DBGMCU_H - -#include -#include - -/* --- DBGMCU registers ---------------------------------------------------- */ - -#define DBGMCU_IDCODE MMIO32(DBGMCU_BASE + 0x00) -#define DBGMCU_CR MMIO32(DBGMCU_BASE + 0x04) - -/* DBGMCU_CR bits */ -#define DBGMCU_CR_SLEEP 0x00000001 -#define DBGMCU_CR_STOP 0x00000002 -#define DBGMCU_CR_STANDBY 0x00000004 -#define DBGMCU_CR_TRACE_IOEN 0x00000020 -#define DBGMCU_CR_TRACE_MODE_MASK 0x000000C0 -#define DBGMCU_CR_TRACE_MODE_ASYNC 0x00000000 -#define DBGMCU_CR_TRACE_MODE_SYNC_1 0x00000040 -#define DBGMCU_CR_TRACE_MODE_SYNC_2 0x00000080 -#define DBGMCU_CR_TRACE_MODE_SYNC_4 0x000000C0 -#define DBGMCU_CR_IWDG_STOP 0x00000100 -#define DBGMCU_CR_WWDG_STOP 0x00000200 -#define DBGMCU_CR_TIM1_STOP 0x00000400 -#define DBGMCU_CR_TIM2_STOP 0x00000800 -#define DBGMCU_CR_TIM3_STOP 0x00001000 -#define DBGMCU_CR_TIM4_STOP 0x00002000 -#define DBGMCU_CR_CAN1_STOP 0x00004000 -#define DBGMCU_CR_I2C1_SMBUS_TIMEOUT 0x00008000 -#define DBGMCU_CR_I2C2_SMBUS_TIMEOUT 0x00010000 -#define DBGMCU_CR_TIM8_STOP 0x00020000 -#define DBGMCU_CR_TIM5_STOP 0x00040000 -#define DBGMCU_CR_TIM6_STOP 0x00080000 -#define DBGMCU_CR_TIM7_STOP 0x00100000 -#define DBGMCU_CR_CAN2_STOP 0x00200000 - -/* DBGMCU_IDCODE bits */ -#define DBGMCU_IDCODE_DEV_ID_MASK 0x00000fff -#define DBGMCU_IDCODE_REV_ID_MASK 0xffff0000 - -#endif diff --git a/include/libopencm3/stm32f1/exti.h b/include/libopencm3/stm32f1/exti.h deleted file mode 100644 index 19ab547..0000000 --- a/include/libopencm3/stm32f1/exti.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Mark Butler - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_EXTI_H -#define LIBOPENCM3_EXTI_H - -#include -#include - -/* --- EXTI registers ------------------------------------------------------ */ - -#define EXTI_IMR MMIO32(EXTI_BASE + 0x00) -#define EXTI_EMR MMIO32(EXTI_BASE + 0x04) -#define EXTI_RTSR MMIO32(EXTI_BASE + 0x08) -#define EXTI_FTSR MMIO32(EXTI_BASE + 0x0c) -#define EXTI_SWIER MMIO32(EXTI_BASE + 0x10) -#define EXTI_PR MMIO32(EXTI_BASE + 0x14) - -/* EXTI number definitions */ -#define EXTI0 (1 << 0) -#define EXTI1 (1 << 1) -#define EXTI2 (1 << 2) -#define EXTI3 (1 << 3) -#define EXTI4 (1 << 4) -#define EXTI5 (1 << 5) -#define EXTI6 (1 << 6) -#define EXTI7 (1 << 7) -#define EXTI8 (1 << 8) -#define EXTI9 (1 << 9) -#define EXTI10 (1 << 10) -#define EXTI11 (1 << 11) -#define EXTI12 (1 << 12) -#define EXTI13 (1 << 13) -#define EXTI14 (1 << 14) -#define EXTI15 (1 << 15) -#define EXTI16 (1 << 16) -#define EXTI17 (1 << 17) -#define EXTI18 (1 << 18) -#define EXTI19 (1 << 19) - -/* Trigger types */ -typedef enum trigger_e { - EXTI_TRIGGER_RISING, - EXTI_TRIGGER_FALLING, - EXTI_TRIGGER_BOTH, -} exti_trigger_type; - -void exti_set_trigger(u32 extis, exti_trigger_type trig); -void exti_enable_request(u32 extis); -void exti_disable_request(u32 extis); -void exti_reset_request(u32 extis); -void exti_select_source(u32 exti, u32 gpioport); - -#endif diff --git a/include/libopencm3/stm32f1/fsmc.h b/include/libopencm3/stm32f1/fsmc.h deleted file mode 100644 index 1d318e3..0000000 --- a/include/libopencm3/stm32f1/fsmc.h +++ /dev/null @@ -1,284 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_FSMC_H -#define LIBOPENCM3_FSMC_H - -#include -#include - -/* --- Convenience macros -------------------------------------------------- */ - -/* TODO: Move to memorymap.h? */ -#define FSMC_BASE 0xa0000000 - -#define FSMC_BANK1_BASE 0x60000000 /* NOR / PSRAM */ -#define FSMC_BANK2_BASE 0x70000000 /* NAND flash */ -#define FSMC_BANK3_BASE 0x80000000 /* NAND flash */ -#define FSMC_BANK4_BASE 0x90000000 /* PC card */ - -/* --- FSMC registers ------------------------------------------------------ */ - -/* SRAM/NOR-Flash chip-select control registers 1..4 (FSMC_BCRx) */ -#define FSMC_BCR(x) MMIO32(FSMC_BASE + 0x00 + 8 * x) -#define FSMC_BCR1 FSMC_BCR(0) -#define FSMC_BCR2 FSMC_BCR(1) -#define FSMC_BCR3 FSMC_BCR(2) -#define FSMC_BCR4 FSMC_BCR(3) - -/* SRAM/NOR-Flash chip-select timing registers 1..4 (FSMC_BTRx) */ -#define FSMC_BTR(x) MMIO32(FSMC_BASE + 0x04 + 8 * x) -#define FSMC_BTR1 FSMC_BTR(0) -#define FSMC_BTR2 FSMC_BTR(1) -#define FSMC_BTR3 FSMC_BTR(2) -#define FSMC_BTR4 FSMC_BTR(3) - -/* SRAM/NOR-Flash write timing registers 1..4 (FSMC_BWTRx) */ -#define FSMC_BWTR(x) MMIO32(FSMC_BASE + 0x104 + 8 * x) -#define FSMC_BWTR1 FSMC_BWTR(0) -#define FSMC_BWTR2 FSMC_BWTR(1) -#define FSMC_BWTR3 FSMC_BWTR(2) -#define FSMC_BWTR4 FSMC_BWTR(3) - -/* PC Card/NAND Flash control registers 2..4 (FSMC_PCRx) */ -#define FSMC_PCR(x) MMIO32(FSMC_BASE + 0x40 + 0x20 * x) -#define FSMC_PCR2 FSMC_PCR(1) -#define FSMC_PCR3 FSMC_PCR(2) -#define FSMC_PCR4 FSMC_PCR(3) - -/* FIFO status and interrupt registers 2..4 (FSMC_SRx) */ -#define FSMC_SR(x) MMIO32(FSMC_BASE + 0x44 + 0x20 * x) -#define FSMC_SR2 FSMC_SR(1) -#define FSMC_SR3 FSMC_SR(2) -#define FSMC_SR4 FSMC_SR(3) - -/* Common memory space timing registers 2..4 (FSMC_PMEMx) */ -#define FSMC_PMEM(x) MMIO32(FSMC_BASE + 0x48 + 0x20 * x) -#define FSMC_PMEM2 FSMC_PMEM(1) -#define FSMC_PMEM3 FSMC_PMEM(2) -#define FSMC_PMEM4 FSMC_PMEM(3) - -/* Attribute memory space timing registers 2..4 (FSMC_PATTx) */ -#define FSMC_PATT(x) MMIO32(FSMC_BASE + 0x4c + 0x20 * x) -#define FSMC_PATT2 FSMC_PATT(1) -#define FSMC_PATT3 FSMC_PATT(2) -#define FSMC_PATT4 FSMC_PATT(3) - -/* I/O space timing register 4 (FSMC_PIO4) */ -#define FSMC_PIO4 MMIO32(FSMC_BASE + 0xb0) - -/* ECC result registers 2/3 (FSMC_ECCRx) */ -#define FSMC_ECCR(x) MMIO32(FSMC_BASE + 0x54 + 0x20 * x) -#define FSMC_ECCR2 FSMC_ECCR(1) -#define FSMC_ECCR3 FSMC_ECCR(2) - -/* --- FSMC_BCRx values ---------------------------------------------------- */ - -/* CBURSTRW: Write burst enable */ -#define FSMC_BCR_CBURSTRW (1 << 19) - -/* Bits 18..16: Reserved. */ - -/* ASYNCWAIT: Wait signal during asynchronous transfers */ -#define FSMC_BCR_ASYNCWAIT (1 << 15) - -/* EXTMOD: Extended mode enable */ -#define FSMC_BCR_EXTMOD (1 << 14) - -/* WAITEN: Wait enable bit */ -#define FSMC_BCR_WAITEN (1 << 13) - -/* WREN: Write enable bit */ -#define FSMC_BCR_WREN (1 << 12) - -/* WAITCFG: Wait timing configuration */ -#define FSMC_BCR_WAITCFG (1 << 11) - -/* WRAPMOD: Wrapped burst mode support */ -#define FSMC_BCR_WRAPMOD (1 << 10) - -/* WAITPOL: Wait signal polarity bit */ -#define FSMC_BCR_WAITPOL (1 << 9) - -/* BURSTEN: Burst enable bit */ -#define FSMC_BCR_BURSTEN (1 << 8) - -/* Bit 7: Reserved. */ - -/* FACCEN: Flash access enable */ -#define FSMC_BCR_FACCEN (1 << 6) - -/* MWID[5:4]: Memory databus width */ -#define FSMC_BCR_MWID (1 << 4) - -/* MTYP[3:2]: Memory type */ -#define FSMC_BCR_MTYP (1 << 2) - -/* MUXEN: Address/data multiplexing enable bit */ -#define FSMC_BCR_MUXEN (1 << 1) - -/* MBKEN: Memory bank enable bit */ -#define FSMC_BCR_MBKEN (1 << 0) - -/* --- FSMC_BTRx values ---------------------------------------------------- */ - -/* ACCMOD[29:28]: Access mode */ -#define FSMC_BTR_ACCMOD (1 << 28) - -/* DATLAT[27:24]: Data latency (for synchronous burst NOR flash) */ -#define FSMC_BTR_DATLAT (1 << 24) - -/* CLKDIV[23:20]: Clock divide ratio (for CLK signal) */ -#define FSMC_BTR_CLKDIV (1 << 20) - -/* BUSTURN[19:16]: Bus turnaround phase duration */ -#define FSMC_BTR_BUSTURN (1 << 16) - -/* DATAST[15:8]: Data-phase duration */ -#define FSMC_BTR_DATAST (1 << 8) - -/* ADDHLD[7:4]: Address-hold phase duration */ -#define FSMC_BTR_ADDHLD (1 << 4) - -/* ADDSET[3:0]: Address setup phase duration */ -#define FSMC_BTR_ADDSET (1 << 0) - -/* --- FSMC_BWTRx values --------------------------------------------------- */ - -/* ACCMOD[29:28]: Access mode */ -#define FSMC_BWTR_ACCMOD (1 << 28) - -/* DATLAT[27:24]: Data latency (for synchronous burst NOR Flash) */ -#define FSMC_BWTR_DATLAT (1 << 24) - -/* CLKDIV[23:20]: Clock divide ratio (for CLK signal) */ -#define FSMC_BWTR_CLKDIV (1 << 20) - -/* Bits 19..16: Reserved. */ - -/* DATAST[15:8]: Data-phase duration */ -#define FSMC_BWTR_DATAST (1 << 8) - -/* ADDHLD[7:4]: Address-hold phase duration */ -#define FSMC_BWTR_ADDHLD (1 << 4) - -/* ADDSET[3:0]: Address setup phase duration */ -#define FSMC_BWTR_ADDSET (1 << 0) - -/* --- FSMC_PCRx values ---------------------------------------------------- */ - -/* ECCPS[19:17]: ECC page size */ -#define FSMC_PCR_ECCPS (1 << 17) - -/* TAR[16:13]: ALE to RE delay */ -#define FSMC_PCR_TAR (1 << 13) - -/* TCLR[12:9]: CLE to RE delay */ -#define FSMC_PCR_TCLR (1 << 9) - -/* Bits 8..7: Reserved. */ - -/* ECCEN: ECC computation logic enable bit */ -#define FSMC_PCR_ECCEN (1 << 6) - -/* PWID[5:4]: Databus width */ -#define FSMC_PCR_PWID (1 << 4) - -/* PTYP: Memory type */ -#define FSMC_PCR_PTYP (1 << 3) - -/* PBKEN: PC Card/NAND Flash memory bank enable bit */ -#define FSMC_PCR_PBKEN (1 << 2) - -/* PWAITEN: Wait feature enable bit */ -#define FSMC_PCR_PWAITEN (1 << 1) - -/* Bit 0: Reserved. */ - -/* --- FSMC_SRx values ----------------------------------------------------- */ - -/* FEMPT: FIFO empty */ -#define FSMC_SR_FEMPT (1 << 6) - -/* IFEN: Interrupt falling edge detection enable bit */ -#define FSMC_SR_IFEN (1 << 5) - -/* ILEN: Interrupt high-level detection enable bit */ -#define FSMC_SR_ILEN (1 << 4) - -/* IREN: Interrupt rising edge detection enable bit */ -#define FSMC_SR_IREN (1 << 3) - -/* IFS: Interrupt falling edge status */ -#define FSMC_SR_IFS (1 << 2) - -/* ILS: Interrupt high-level status */ -#define FSMC_SR_ILS (1 << 1) - -/* IRS: Interrupt rising edge status */ -#define FSMC_SR_IRS (1 << 0) - -/* --- FSMC_PMEMx values --------------------------------------------------- */ - -/* MEMHIZx[31:24]: Common memory x databus HiZ time */ -#define FSMC_PMEM_MEMHIZX (1 << 24) - -/* MEMHOLDx[23:16]: Common memory x hold time */ -#define FSMC_PMEM_MEMHOLDX (1 << 16) - -/* MEMWAITx[15:8]: Common memory x wait time */ -#define FSMC_PMEM_MEMHOLDX (1 << 8) - -/* MEMSETx[7:0]: Common memory x setup time */ -#define FSMC_PMEM_MEMSETX (1 << 0) - -/* --- FSMC_PATTx values --------------------------------------------------- */ - -/* ATTHIZx[31:24]: Attribute memory x databus HiZ time */ -#define FSMC_PATT_ATTHIZX (1 << 24) - -/* ATTHOLDx[23:16]: Attribute memory x hold time */ -#define FSMC_PATT_ATTHOLDX (1 << 16) - -/* ATTWAITx[15:8]: Attribute memory x wait time */ -#define FSMC_PATT_ATTWAITX (1 << 8) - -/* ATTSETx[7:0]: Attribute memory x setup time */ -#define FSMC_PATT_ATTSETX (1 << 0) - -/* --- FSMC_PIO4 values ---------------------------------------------------- */ - -/* IOHIZx[31:24]: I/O x databus HiZ time */ -#define FSMC_PIO4_IOHIZX (1 << 24) - -/* IOHOLDx[23:16]: I/O x hold time */ -#define FSMC_PIO4_IOHOLDX (1 << 16) - -/* IOWAITx[15:8]: I/O x wait time */ -#define FSMC_PIO4_IOWAITX (1 << 8) - -/* IOSETx[7:0]: I/O x setup time */ -#define FSMC_PIO4_IOSETX (1 << 0) - -/* --- FSMC_ECCRx values --------------------------------------------------- */ - -/* ECCx[31:0]: ECC result */ -#define FSMC_ECCR_ECCX (1 << 0) - -#endif diff --git a/include/libopencm3/stm32f1/iwdg.h b/include/libopencm3/stm32f1/iwdg.h deleted file mode 100644 index bf2784a..0000000 --- a/include/libopencm3/stm32f1/iwdg.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_IWDG_H -#define LIBOPENCM3_IWDG_H - -#include -#include - -/* --- IWDG registers ------------------------------------------------------ */ - -/* Key Register (IWDG_KR) */ -#define IWDG_KR MMIO32(IWDG_BASE + 0x00) - -/* Prescaler register (IWDG_PR) */ -#define IWDG_PR MMIO32(IWDG_BASE + 0x04) - -/* Reload register (IWDG_RLR) */ -#define IWDG_RLR MMIO32(IWDG_BASE + 0x08) - -/* Status register (IWDG_SR) */ -#define IWDG_SR MMIO32(IWDG_BASE + 0x0C) - -/* --- IWDG_KR values ------------------------------------------------------ */ - -/* KEY[15:0]: Key value */ -#define IWDG_KR_RESET 0xAAAA -#define IWDG_KR_UNLOCK 0x5555 -#define IWDG_KR_START 0xCCCC - -/* --- IWDG_PR values ------------------------------------------------------ */ - -/* PR[2:0]: Prescaler divider */ -#define IWDG_PR_LSB 0 -#define IWDG_PR_DIV4 0x0 -#define IWDG_PR_DIV8 0x1 -#define IWDG_PR_DIV16 0x2 -#define IWDG_PR_DIV32 0x3 -#define IWDG_PR_DIV64 0x4 -#define IWDG_PR_DIV128 0x5 -#define IWDG_PR_DIV256 0x6 -/* Double definition: 0x06 and 0x07 both mean DIV256 as per datasheet. */ -/* #define IWDG_PR_DIV256 0x7 */ - -/* --- IWDG_RLR values ----------------------------------------------------- */ - -/* RL[11:0]: Watchdog counter reload value */ - -/* --- IWDG_SR values ------------------------------------------------------ */ - -/* RVU: Watchdog counter reload value update */ -#define IWDG_SR_RVU (1 << 1) - -/* PVU: Watchdog prescaler value update */ -#define IWDG_SR_PVU (1 << 0) - -/* --- IWDG funtion prototypes---------------------------------------------- */ - -#endif diff --git a/include/libopencm3/stm32f1/wwdg.h b/include/libopencm3/stm32f1/wwdg.h deleted file mode 100644 index 552d02e..0000000 --- a/include/libopencm3/stm32f1/wwdg.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_WWDG_H -#define LIBOPENCM3_WWDG_H - -#include -#include - -/* --- WWDG registers ------------------------------------------------------ */ - -/* Control register (WWDG_CR) */ -#define WWDG_CR MMIO32(WWDG_BASE + 0x00) - -/* Configuration register (WWDG_CFR) */ -#define WWDG_CFR MMIO32(WWDG_BASE + 0x04) - -/* Status register (WWDG_SR) */ -#define WWDG_SR MMIO32(WWDG_BASE + 0x08) - -/* --- WWDG_CR values ------------------------------------------------------ */ - -/* WDGA: Activation bit */ -#define WWDG_CR_WDGA (1 << 7) - -/* T[6:0]: 7-bit counter (MSB to LSB) */ -#define WWDG_CR_T_LSB 0 -#define WWDG_CR_T0 (1 << 0) -#define WWDG_CR_T1 (1 << 1) -#define WWDG_CR_T2 (1 << 2) -#define WWDG_CR_T3 (1 << 3) -#define WWDG_CR_T4 (1 << 4) -#define WWDG_CR_T5 (1 << 5) -#define WWDG_CR_T6 (1 << 6) - -/* --- WWDG_CFR values ----------------------------------------------------- */ - -/* EWI: Early wakeup interrupt */ -#define WWDG_CFR_EWI (1 << 9) - -/* WDGTB[8:7]: Timer base */ -#define WWDG_CFR_WDGTB_LSB 7 -#define WWDG_CFR_WDGTB_CK_DIV1 0x0 -#define WWDG_CFR_WDGTB_CK_DIV2 0x1 -#define WWDG_CFR_WDGTB_CK_DIV4 0x2 -#define WWDG_CFR_WDGTB_CK_DIV8 0x3 - -/* W[6:0]: 7-bit window value */ -#define WWDG_CFG_W_LSB 0 - -/* --- WWDG_SR values ------------------------------------------------------ */ - -/* EWIF: Early wakeup interrupt flag */ -#define WWDG_SR_EWIF (1 << 0) - -/* --- WWDG funtion prototypes---------------------------------------------- */ - -#endif -- cgit v1.2.3 From 424b094ce83e6c9ae577cef22e86054cc2d945a5 Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Mon, 12 Sep 2011 18:25:11 -0700 Subject: Renaming lib code for stm32 f1 series. --- lib/stm32/Makefile | 61 --- lib/stm32/adc.c | 375 ---------------- lib/stm32/can.c | 303 ------------- lib/stm32/dma.c | 543 ---------------------- lib/stm32/ethernet.c | 53 --- lib/stm32/exti.c | 145 ------ lib/stm32/flash.c | 189 -------- lib/stm32/gpio.c | 118 ----- lib/stm32/i2c.c | 93 ---- lib/stm32/libopencm3_stm32.ld | 63 --- lib/stm32/nvic.c | 106 ----- lib/stm32/rcc.c | 677 ---------------------------- lib/stm32/rtc.c | 282 ------------ lib/stm32/scb.c | 30 -- lib/stm32/spi.c | 290 ------------ lib/stm32/systick.c | 64 --- lib/stm32/timer.c | 914 -------------------------------------- lib/stm32/usart.c | 131 ------ lib/stm32/vector.c | 296 ------------ lib/stm32f1/Makefile | 61 +++ lib/stm32f1/adc.c | 375 ++++++++++++++++ lib/stm32f1/can.c | 303 +++++++++++++ lib/stm32f1/dma.c | 543 ++++++++++++++++++++++ lib/stm32f1/ethernet.c | 53 +++ lib/stm32f1/exti.c | 145 ++++++ lib/stm32f1/flash.c | 189 ++++++++ lib/stm32f1/gpio.c | 118 +++++ lib/stm32f1/i2c.c | 93 ++++ lib/stm32f1/libopencm3_stm32f1.ld | 63 +++ lib/stm32f1/nvic.c | 106 +++++ lib/stm32f1/rcc.c | 677 ++++++++++++++++++++++++++++ lib/stm32f1/rtc.c | 282 ++++++++++++ lib/stm32f1/scb.c | 30 ++ lib/stm32f1/spi.c | 290 ++++++++++++ lib/stm32f1/systick.c | 64 +++ lib/stm32f1/timer.c | 914 ++++++++++++++++++++++++++++++++++++++ lib/stm32f1/usart.c | 131 ++++++ lib/stm32f1/vector.c | 296 ++++++++++++ 38 files changed, 4733 insertions(+), 4733 deletions(-) delete mode 100644 lib/stm32/Makefile delete mode 100644 lib/stm32/adc.c delete mode 100644 lib/stm32/can.c delete mode 100644 lib/stm32/dma.c delete mode 100644 lib/stm32/ethernet.c delete mode 100644 lib/stm32/exti.c delete mode 100644 lib/stm32/flash.c delete mode 100644 lib/stm32/gpio.c delete mode 100644 lib/stm32/i2c.c delete mode 100644 lib/stm32/libopencm3_stm32.ld delete mode 100644 lib/stm32/nvic.c delete mode 100644 lib/stm32/rcc.c delete mode 100644 lib/stm32/rtc.c delete mode 100644 lib/stm32/scb.c delete mode 100644 lib/stm32/spi.c delete mode 100644 lib/stm32/systick.c delete mode 100644 lib/stm32/timer.c delete mode 100644 lib/stm32/usart.c delete mode 100644 lib/stm32/vector.c create mode 100644 lib/stm32f1/Makefile create mode 100644 lib/stm32f1/adc.c create mode 100644 lib/stm32f1/can.c create mode 100644 lib/stm32f1/dma.c create mode 100644 lib/stm32f1/ethernet.c create mode 100644 lib/stm32f1/exti.c create mode 100644 lib/stm32f1/flash.c create mode 100644 lib/stm32f1/gpio.c create mode 100644 lib/stm32f1/i2c.c create mode 100644 lib/stm32f1/libopencm3_stm32f1.ld create mode 100644 lib/stm32f1/nvic.c create mode 100644 lib/stm32f1/rcc.c create mode 100644 lib/stm32f1/rtc.c create mode 100644 lib/stm32f1/scb.c create mode 100644 lib/stm32f1/spi.c create mode 100644 lib/stm32f1/systick.c create mode 100644 lib/stm32f1/timer.c create mode 100644 lib/stm32f1/usart.c create mode 100644 lib/stm32f1/vector.c diff --git a/lib/stm32/Makefile b/lib/stm32/Makefile deleted file mode 100644 index 5f26c29..0000000 --- a/lib/stm32/Makefile +++ /dev/null @@ -1,61 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2009 Uwe Hermann -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program. If not, see . -## - -LIBNAME = libopencm3_stm32 - -PREFIX ?= arm-none-eabi -#PREFIX ?= arm-elf -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar -CFLAGS = -Os -g -Wall -Wextra -I../../include -fno-common \ - -mcpu=cortex-m3 -mthumb -Wstrict-prototypes \ - -ffunction-sections -fdata-sections -MD -# ARFLAGS = rcsv -ARFLAGS = rcs -OBJS = vector.o rcc.o gpio.o usart.o adc.o spi.o flash.o nvic.o \ - rtc.o i2c.o dma.o systick.o exti.o scb.o ethernet.o \ - usb_f103.o usb.o usb_control.o usb_standard.o can.o \ - timer.o usb_f107.o - -VPATH += ../usb - -# Be silent per default, but 'make V=1' will show all compiler calls. -ifneq ($(V),1) -Q := @ -endif - -all: $(LIBNAME).a - -$(LIBNAME).a: $(OBJS) - @printf " AR $(subst $(shell pwd)/,,$(@))\n" - $(Q)$(AR) $(ARFLAGS) $@ $^ - -%.o: %.c - @printf " CC $(subst $(shell pwd)/,,$(@))\n" - $(Q)$(CC) $(CFLAGS) -o $@ -c $< - -clean: - @printf " CLEAN lib/stm32\n" - $(Q)rm -f *.o *.d - $(Q)rm -f $(LIBNAME).a - -.PHONY: clean - --include $(OBJS:.o=.d) - diff --git a/lib/stm32/adc.c b/lib/stm32/adc.c deleted file mode 100644 index 058837c..0000000 --- a/lib/stm32/adc.c +++ /dev/null @@ -1,375 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Edward Cheeseman - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* - * Basic ADC handling API. - * - * Examples: - * rcc_peripheral_enable_clock(&RCC_APB2ENR, ADC1EN); - * rcc_peripheral_disable_clock(&RCC_APB2ENR, ADC1EN); - * rcc_peripheral_reset(&RCC_APB2RSTR, ADC1RST); - * rcc_peripheral_clear_reset(&RCC_APB2RSTR, ADC1RST); - * - * rcc_set_adc_clk(ADC_PRE_PLCK2_DIV2); - * adc_set_mode(ADC1, TODO); - * reg16 = adc_read(ADC1, ADC_CH_0); - */ - -#include - -void rcc_set_adc_clk(u32 prescaler) -{ - /* TODO */ - - /* FIXME: QUICK HACK to prevent compiler warnings. */ - prescaler = prescaler; -} - -void adc_set_mode(u32 block, /* TODO */ u8 mode) -{ - /* TODO */ - - /* FIXME: QUICK HACK to prevent compiler warnings. */ - block = block; - mode = mode; -} - -void adc_read(u32 block, u32 channel) -{ - /* TODO */ - - /* FIXME: QUICK HACK to prevent compiler warnings. */ - block = block; - channel = channel; -} - -void adc_enable_analog_watchdog_regular(u32 adc) -{ - ADC_CR1(adc) |= ADC_CR1_AWDEN; -} - -void adc_disable_analog_watchdog_regular(u32 adc) -{ - ADC_CR1(adc) &= ~ADC_CR1_AWDEN; -} - -void adc_enable_analog_watchdog_injected(u32 adc) -{ - ADC_CR1(adc) |= ADC_CR1_JAWDEN; -} - -void adc_disable_analog_watchdog_injected(u32 adc) -{ - ADC_CR1(adc) &= ~ADC_CR1_JAWDEN; -} - -void adc_enable_discontinous_mode_regular(u32 adc) -{ - ADC_CR1(adc) |= ADC_CR1_DISCEN; -} - -void adc_disable_discontinous_mode_regular(u32 adc) -{ - ADC_CR1(adc) &= ~ADC_CR1_DISCEN; -} - -void adc_enable_discontinous_mode_injected(u32 adc) -{ - ADC_CR1(adc) |= ADC_CR1_JDISCEN; -} - -void adc_disable_discontinous_mode_injected(u32 adc) -{ - ADC_CR1(adc) &= ~ADC_CR1_JDISCEN; -} - -void adc_enable_automatic_injected_group_conversion(u32 adc) -{ - ADC_CR1(adc) |= ADC_CR1_JAUTO; -} - -void adc_disable_automatic_injected_group_conversion(u32 adc) -{ - ADC_CR1(adc) &= ~ADC_CR1_JAUTO; -} - -void adc_enable_analog_watchdog_on_all_channels(u32 adc) -{ - ADC_CR1(adc) |= ADC_CR1_AWDSGL; -} - -void adc_enable_analog_watchdog_on_selected_channel(u32 adc, u8 channel) -{ - u32 reg32; - - reg32 = (ADC_CR1(adc) & 0xffffffe0); /* Clear bits [4:0]. */ - if (channel < 18) - reg32 |= channel; - ADC_CR1(adc) = reg32; - ADC_CR1(adc) &= ~ADC_CR1_AWDSGL; -} - -void adc_enable_scan_mode(u32 adc) -{ - ADC_CR1(adc) |= ADC_CR1_SCAN; -} - -void adc_disable_scan_mode(u32 adc) -{ - ADC_CR1(adc) &= ~ADC_CR1_SCAN; -} - -void adc_enable_jeoc_interrupt(u32 adc) -{ - ADC_CR1(adc) |= ADC_CR1_JEOCIE; -} - -void adc_disable_jeoc_interrupt(u32 adc) -{ - ADC_CR1(adc) &= ~ADC_CR1_JEOCIE; -} - -void adc_enable_awd_interrupt(u32 adc) -{ - ADC_CR1(adc) |= ADC_CR1_AWDIE; -} - -void adc_disable_awd_interrupt(u32 adc) -{ - ADC_CR1(adc) &= ~ADC_CR1_AWDIE; -} - -void adc_enable_eoc_interrupt(u32 adc) -{ - ADC_CR1(adc) |= ADC_CR1_EOCIE; -} - -void adc_disable_eoc_interrupt(u32 adc) -{ - ADC_CR1(adc) &= ~ADC_CR1_EOCIE; -} - -void adc_enable_temperature_sensor(u32 adc) -{ - ADC_CR2(adc) |= ADC_CR2_TSVREFE; -} - -void adc_disable_temperature_sensor(u32 adc) -{ - ADC_CR2(adc) &= ~ADC_CR2_TSVREFE; -} - -void adc_start_conversion_regular(u32 adc) -{ - /* start conversion on regular channels */ - ADC_CR2(adc) |= ADC_CR2_SWSTART; - - /* wait til the ADC starts the conversion */ - while (ADC_CR2(adc) & ADC_CR2_SWSTART); -} - -void adc_start_conversion_injected(u32 adc) -{ - /* start conversion on injected channels */ - ADC_CR2(adc) |= ADC_CR2_JSWSTART; - - /* wait til the ADC starts the conversion */ - while (ADC_CR2(adc) & ADC_CR2_JSWSTART); -} - -void adc_enable_external_trigger_regular(u32 adc, u8 trigger) -{ - u32 reg32; - - reg32 = (ADC_CR2(adc) & 0xfff1ffff); /* Clear bits [19:17]. */ - if (trigger < 8) - reg32 |= (trigger << ADC_CR2_EXTSEL_LSB); - ADC_CR2(adc) = reg32; - ADC_CR2(adc) |= ADC_CR2_EXTTRIG; -} - -void adc_disable_external_trigger_regular(u32 adc) -{ - ADC_CR2(adc) &= ~ADC_CR2_EXTTRIG; -} - -void adc_enable_external_trigger_injected(u32 adc, u8 trigger) -{ - u32 reg32; - - reg32 = (ADC_CR2(adc) & 0xffff8fff); /* Clear bits [12:14]. */ - if (trigger < 8) - reg32 |= (trigger << ADC_CR2_JEXTSEL_LSB); - ADC_CR2(adc) = reg32; - ADC_CR2(adc) |= ADC_CR2_JEXTTRIG; -} - -void adc_disable_external_trigger_injected(u32 adc) -{ - ADC_CR2(adc) &= ~ADC_CR2_JEXTTRIG; -} - -void adc_set_left_aligned(u32 adc) -{ - ADC_CR2(adc) |= ADC_CR2_ALIGN; -} - -void adc_set_right_aligned(u32 adc) -{ - ADC_CR2(adc) &= ~ADC_CR2_ALIGN; -} - -void adc_enable_dma(u32 adc) -{ - if ((adc == ADC1) | (adc==ADC3)) - ADC_CR2(adc) |= ADC_CR2_DMA; -} - -void adc_disable_dma(u32 adc) -{ - if ((adc == ADC1) | (adc==ADC3)) - ADC_CR2(adc) &= ~ADC_CR2_DMA; -} - -void adc_reset_calibration(u32 adc) -{ - ADC_CR2(adc) |= ADC_CR2_RSTCAL; - while (ADC_CR2(adc) & ADC_CR2_RSTCAL); -} - -void adc_calibration(u32 adc) -{ - ADC_CR2(adc) |= ADC_CR2_CAL; - while (ADC_CR2(adc) & ADC_CR2_CAL); -} - -void adc_set_continous_conversion_mode(u32 adc) -{ - ADC_CR2(adc) |= ADC_CR2_CONT; -} - -void adc_set_single_conversion_mode(u32 adc) -{ - ADC_CR2(adc) &= ~ADC_CR2_CONT; -} - -void adc_on(u32 adc) -{ - ADC_CR2(adc) |= ADC_CR2_ADON; -} - -void adc_off(u32 adc) -{ - ADC_CR2(adc) &= ~ADC_CR2_ADON; -} - -void adc_set_conversion_time(u32 adc, u8 channel, u8 time) -{ - u32 reg32; - - if (channel < 10) { - reg32 = ADC_SMPR2(adc); - reg32 &= ~(0b111 << (channel * 3)); - reg32 |= (time << (channel * 3)); - ADC_SMPR2(adc) = reg32; - } - else { - reg32 = ADC_SMPR1(adc); - reg32 &= ~(0b111 << ((channel-10) * 3)); - reg32 |= (time << ((channel-10) * 3)); - ADC_SMPR1(adc) = reg32; - } -} - -void adc_set_conversion_time_on_all_channels(u32 adc, u8 time) -{ - u32 reg32 = 0; - u8 i; - - for (i = 0; i <= 9; i++) { - reg32 |= (time << (i * 3)); - } - ADC_SMPR2(adc) = reg32; - - for (i = 10; i <= 17; i++) { - reg32 |= (time << ((i-10) * 3)); - } - ADC_SMPR1(adc) = reg32; -} - -void adc_set_watchdog_high_threshold(u32 adc, u16 threshold) -{ - u32 reg32 = 0; - - reg32 = (u32)threshold; - reg32 &= ~0xfffff000; /* clear all bits above 11 */ - ADC_HTR(adc) = reg32; -} - -void adc_set_watchdog_low_threshold(u32 adc, u16 threshold) -{ - u32 reg32 = 0; - - reg32 = (u32)threshold; - reg32 &= ~0xfffff000; /* clear all bits above 11 */ - ADC_LTR(adc) = reg32; -} - -void adc_set_regular_sequence(u32 adc, u8 length, u8 channel[]) -{ - u32 reg32_1 = 0; - u32 reg32_2 = 0; - u32 reg32_3 = 0; - u8 i = 0; - - /* maximum sequence length is 16 channels */ - if (length > 16) - return; - - for (i=1; i<=length; i++) { - if (i <= 6) - reg32_3 |= (channel[i-1] << ((i-1) * 5)); - if ((i > 6) & (i <= 12)) - reg32_2 |= (channel[i-1] << ((i-6-1) * 5)); - if ((i > 12) & (i <= 16)) - reg32_1 |= (channel[i-1] << ((i-12-1) * 5)); - } - reg32_1 |= ((length -1) << ADC_SQR1_L_LSB); - - ADC_SQR1(adc) = reg32_1; - ADC_SQR2(adc) = reg32_2; - ADC_SQR3(adc) = reg32_3; -} - -void adc_set_injected_sequence(u32 adc, u8 length, u8 channel[]) -{ - u32 reg32 = 0; - u8 i = 0; - - /* maximum sequence length is 4 channels */ - if (length > 4) - return; - - for (i = 1; i <= length; i++) { - reg32 |= (channel[i-1] << ((i-1) * 5)); - } - reg32 |= ((length-1) << ADC_JSQR_JL_LSB); - - ADC_JSQR(adc) = reg32; -} diff --git a/lib/stm32/can.c b/lib/stm32/can.c deleted file mode 100644 index e571f8a..0000000 --- a/lib/stm32/can.c +++ /dev/null @@ -1,303 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include - -void can_reset(u32 canport) -{ - if (canport == CAN1) { - rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_CAN1RST); - rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_CAN1RST); - } else { - rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_CAN2RST); - rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_CAN2RST); - } -} - -int can_init(u32 canport, bool ttcm, bool abom, bool awum, bool nart, - bool rflm, bool txfp, u32 sjw, u32 ts1, u32 ts2, u32 brp) -{ - u32 wait_ack = 0x00000000; - u32 can_msr_inak_timeout = 0x0000FFFF; - int ret = 0; - - /* Exit from sleep mode. */ - CAN_MCR(canport) &= ~CAN_MCR_SLEEP; - - /* Request initialization "enter". */ - CAN_MCR(canport) |= CAN_MCR_INRQ; - - /* Wait for acknowledge. */ - while ((wait_ack != can_msr_inak_timeout) && - ((CAN_MSR(canport) & CAN_MSR_INAK) != CAN_MSR_INAK)) { - wait_ack++; - } - - /* Check the acknowledge. */ - if ((CAN_MSR(canport) & CAN_MSR_INAK) != CAN_MSR_INAK) - return 1; - - /* Set the automatic bus-off management. */ - if (ttcm) - CAN_MCR(canport) |= CAN_MCR_TTCM; - else - CAN_MCR(canport) &= ~CAN_MCR_TTCM; - - if (abom) - CAN_MCR(canport) |= CAN_MCR_ABOM; - else - CAN_MCR(canport) &= ~CAN_MCR_ABOM; - - if (awum) - CAN_MCR(canport) |= CAN_MCR_AWUM; - else - CAN_MCR(canport) &= ~CAN_MCR_AWUM; - - if (nart) - CAN_MCR(canport) |= CAN_MCR_NART; - else - CAN_MCR(canport) &= ~CAN_MCR_NART; - - if (rflm) - CAN_MCR(canport) |= CAN_MCR_RFLM; - else - CAN_MCR(canport) &= ~CAN_MCR_RFLM; - - if (txfp) - CAN_MCR(canport) |= CAN_MCR_TXFP; - else - CAN_MCR(canport) &= ~CAN_MCR_TXFP; - - /* Set bit timings. */ - CAN_BTR(canport) = sjw | ts2 | ts1 | - (u32)(CAN_BTR_BRP_MASK & (brp - 1)); - - /* Request initialization "leave". */ - CAN_MCR(canport) &= ~CAN_MCR_INRQ; - - /* Wait for acknowledge. */ - wait_ack = 0x00000000; - while ((wait_ack != can_msr_inak_timeout) && - ((CAN_MSR(canport) & CAN_MSR_INAK) == CAN_MSR_INAK)) { - wait_ack++; - } - - if ((CAN_MSR(canport) & CAN_MSR_INAK) == CAN_MSR_INAK) - ret = 1; - - return ret; -} - -void can_filter_init(u32 canport, u32 nr, bool scale_32bit, bool id_list_mode, - u32 fr1, u32 fr2, u32 fifo, bool enable) -{ - u32 filter_select_bit = 0x00000001 << nr; - - /* Request initialization "enter". */ - CAN_FMR(canport) |= CAN_FMR_FINIT; - - /* Deactivate the filter. */ - CAN_FA1R(canport) &= ~filter_select_bit; - - if (scale_32bit) { - /* Set 32-bit scale for the filter. */ - CAN_FS1R(canport) |= filter_select_bit; - } else { - /* Set 16-bit scale for the filter. */ - CAN_FS1R(canport) &= ~filter_select_bit; - } - - if (id_list_mode) { - /* Set filter mode to ID list mode. */ - CAN_FM1R(canport) |= filter_select_bit; - } else { - /* Set filter mode to id/mask mode. */ - CAN_FM1R(canport) &= ~filter_select_bit; - } - - /* Set the first filter register. */ - CAN_FiR1(canport, nr) = fr1; - - /* Set the second filter register. */ - CAN_FiR2(canport, nr) = fr2; - - /* Select FIFO0 or FIFO1 as filter assignement. */ - if (fifo) - CAN_FFA1R(canport) |= filter_select_bit; /* FIFO1 */ - else - CAN_FFA1R(canport) &= ~filter_select_bit; /* FIFO0 */ - - if (enable) - CAN_FA1R(canport) |= filter_select_bit; /* Activate filter. */ - - /* Request initialization "leave". */ - CAN_FMR(canport) &= ~CAN_FMR_FINIT; -} - -void can_filter_id_mask_16bit_init(u32 canport, u32 nr, u16 id1, u16 mask1, - u16 id2, u16 mask2, u32 fifo, bool enable) -{ - can_filter_init(canport, nr, false, false, - ((u32)id1 << 16) | (u32)mask1, - ((u32)id2 << 16) | (u32)mask2, fifo, enable); -} - -void can_filter_id_mask_32bit_init(u32 canport, u32 nr, u32 id, u32 mask, - u32 fifo, bool enable) -{ - can_filter_init(canport, nr, true, false, id, mask, fifo, enable); -} - -void can_filter_id_list_16bit_init(u32 canport, u32 nr, u16 id1, u16 id2, - u16 id3, u16 id4, u32 fifo, bool enable) -{ - can_filter_init(canport, nr, false, true, - ((u32)id1 << 16) | (u32)id2, - ((u32)id3 << 16) | (u32)id4, fifo, enable); -} - -void can_filter_id_list_32bit_init(u32 canport, u32 nr, u32 id1, u32 id2, - u32 fifo, bool enable) -{ - can_filter_init(canport, nr, true, true, id1, id2, fifo, enable); -} - -void can_enable_irq(u32 canport, u32 irq) -{ - CAN_IER(canport) |= irq; -} - -void can_disable_irq(u32 canport, u32 irq) -{ - CAN_IER(canport) &= ~irq; -} - -int can_transmit(u32 canport, u32 id, bool ext, bool rtr, u8 length, u8 *data) -{ - int ret = 0, i; - u32 mailbox = 0; - - if ((CAN_TSR(canport) & CAN_TSR_TME0) == CAN_TSR_TME0) { - ret = 0; - mailbox = CAN_MBOX0; - } else if ((CAN_TSR(canport) & CAN_TSR_TME1) == CAN_TSR_TME1) { - ret = 1; - mailbox = CAN_MBOX1; - } else if ((CAN_TSR(canport) & CAN_TSR_TME2) == CAN_TSR_TME2) { - ret = 2; - mailbox = CAN_MBOX2; - } else { - ret = -1; - } - - /* Check if we have an empty mailbox. */ - if (ret == -1) - return ret; - - /* Clear stale register bits */ - CAN_TIxR(canport, mailbox) = 0; - if (ext) { - /* Set extended ID. */ - CAN_TIxR(canport, mailbox) |= id << CAN_TIxR_EXID_SHIFT; - /* Set extended ID indicator bit. */ - CAN_TIxR(canport, mailbox) |= CAN_TIxR_IDE; - } else { - /* Set standard ID. */ - CAN_TIxR(canport, mailbox) |= id << CAN_TIxR_STID_SHIFT; - } - - /* Set/clear remote transmission request bit. */ - if (rtr) - CAN_TIxR(canport, mailbox) |= CAN_TIxR_RTR; /* Set */ - - /* Set the DLC. */ - CAN_TDTxR(canport, mailbox) &= 0xFFFFFFFF0; - CAN_TDTxR(canport, mailbox) |= length & CAN_TDTxR_DLC_MASK; - - /* Set the data. */ - CAN_TDLxR(canport, mailbox) = 0; - CAN_TDHxR(canport, mailbox) = 0; - for (i = 0; (i < 4) && (i < length); i++) - CAN_TDLxR(canport, mailbox) |= (u32)data[i] << (8 * i); - for (i = 4; (i < 8) && (i < length); i++) - CAN_TDHxR(canport, mailbox) |= (u32)data[i] << (8 * (i - 4)); - - /* Request transmission. */ - CAN_TIxR(canport, mailbox) |= CAN_TIxR_TXRQ; - - return ret; -} - -void can_fifo_release(u32 canport, u8 fifo) -{ - if (fifo == 0) - CAN_RF0R(canport) |= CAN_RF1R_RFOM1; - else - CAN_RF1R(canport) |= CAN_RF1R_RFOM1; -} - -void can_receive(u32 canport, u8 fifo, bool release, u32 *id, bool *ext, - bool *rtr, u32 *fmi, u8 *length, u8 *data) -{ - u32 fifo_id = 0; - int i; - - if (fifo == 0) - fifo_id = CAN_FIFO0; - else - fifo_id = CAN_FIFO1; - - /* Get type of CAN ID and CAN ID. */ - if (CAN_RIxR(canport, fifo_id) & CAN_RIxR_IDE) { - *ext = true; - /* Get extended CAN ID. */ - *id = ((CAN_RIxR(canport, fifo_id) & CAN_RIxR_EXID_MASK) >> - CAN_RIxR_EXID_SHIFT); - } else { - *ext = false; - /* Get standard CAN ID. */ - *id = ((CAN_RIxR(canport, fifo_id) & CAN_RIxR_STID_MASK) >> - CAN_RIxR_STID_SHIFT); - } - - /* Get request transmit flag. */ - if (CAN_RIxR(canport, fifo_id) & CAN_RIxR_RTR) - *rtr = true; - else - *rtr = false; - - /* Get filter match ID. */ - *fmi = ((CAN_RDTxR(canport, fifo_id) & CAN_RDTxR_FMI_MASK) > - CAN_RDTxR_FMI_SHIFT); - - /* Get data length. */ - *length = CAN_RDTxR(canport, fifo_id) & CAN_RDTxR_DLC_MASK; - - /* Get data. */ - for (i = 0; (i < 4) && (i < *length); i++) - data[i] = (CAN_RDLxR(canport, fifo_id) >> (8 * i)) & 0xFF; - - for (i = 4; (i < 8) && (i < *length); i++) - data[i] = (CAN_RDHxR(canport, fifo_id) >> (8 * (i - 4))) & 0xFF; - - /* Release the FIFO. */ - if (release) - can_fifo_release(CAN1, 0); -} diff --git a/lib/stm32/dma.c b/lib/stm32/dma.c deleted file mode 100644 index 8feb2c9..0000000 --- a/lib/stm32/dma.c +++ /dev/null @@ -1,543 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include - -void dma_enable_mem2mem_mode(u32 dma, u8 channel) -{ - switch (channel) - { - case 1: - DMA_CCR1(dma) |= DMA_CCR1_MEM2MEM; - DMA_CCR1(dma) &= ~DMA_CCR1_CIRC; - case 2: - DMA_CCR2(dma) |= DMA_CCR2_MEM2MEM; - DMA_CCR2(dma) &= ~DMA_CCR2_CIRC; - case 3: - DMA_CCR3(dma) |= DMA_CCR3_MEM2MEM; - DMA_CCR3(dma) &= ~DMA_CCR3_CIRC; - case 4: - DMA_CCR4(dma) |= DMA_CCR4_MEM2MEM; - DMA_CCR4(dma) &= ~DMA_CCR4_CIRC; - case 5: - DMA_CCR5(dma) |= DMA_CCR5_MEM2MEM; - DMA_CCR5(dma) &= ~DMA_CCR5_CIRC; - case 6: - if (dma == DMA1) { - DMA_CCR6(dma) |= DMA_CCR6_MEM2MEM; - DMA_CCR6(dma) &= ~DMA_CCR6_CIRC; - } - case 7: - if (dma == DMA1) { - DMA_CCR7(dma) |= DMA_CCR7_MEM2MEM; - DMA_CCR7(dma) &= ~DMA_CCR7_CIRC; - } - } -} - - - - -void dma_set_priority(u32 dma, u8 channel, u8 prio) -{ - /* parameter check */ - if (prio > 3) - return; - - switch (channel) - { - case 1: - DMA_CCR1(dma) &= ~(0x3 << DMA_CCR1_PL_LSB); - DMA_CCR1(dma) |= (prio << DMA_CCR1_PL_LSB); - case 2: - DMA_CCR2(dma) &= ~(0x3 << DMA_CCR2_PL_LSB); - DMA_CCR2(dma) |= (prio << DMA_CCR2_PL_LSB); - case 3: - DMA_CCR3(dma) &= ~(0x3 << DMA_CCR3_PL_LSB); - DMA_CCR3(dma) |= (prio << DMA_CCR3_PL_LSB); - case 4: - DMA_CCR4(dma) &= ~(0x3 << DMA_CCR4_PL_LSB); - DMA_CCR4(dma) |= (prio << DMA_CCR4_PL_LSB); - case 5: - DMA_CCR5(dma) &= ~(0x3 << DMA_CCR5_PL_LSB); - DMA_CCR5(dma) |= (prio << DMA_CCR5_PL_LSB); - case 6: - if (dma == DMA1) { - DMA_CCR6(dma) &= ~(0x3 << DMA_CCR6_PL_LSB); - DMA_CCR6(dma) |= (prio << DMA_CCR6_PL_LSB); - } - case 7: - if (dma == DMA1) { - DMA_CCR7(dma) &= ~(0x3 << DMA_CCR7_PL_LSB); - DMA_CCR7(dma) |= (prio << DMA_CCR7_PL_LSB); - } - } -} - -void dma_set_memory_size(u32 dma, u8 channel, u8 mem_size) -{ - /* parameter check */ - if (mem_size > 2) - return; - - switch (channel) - { - case 1: - DMA_CCR1(dma) &= ~(0x3 << DMA_CCR1_MSIZE_LSB); - DMA_CCR1(dma) |= (mem_size << DMA_CCR1_MSIZE_LSB); - case 2: - DMA_CCR2(dma) &= ~(0x3 << DMA_CCR2_MSIZE_LSB); - DMA_CCR2(dma) |= (mem_size << DMA_CCR2_MSIZE_LSB); - case 3: - DMA_CCR3(dma) &= ~(0x3 << DMA_CCR3_MSIZE_LSB); - DMA_CCR3(dma) |= (mem_size << DMA_CCR3_MSIZE_LSB); - case 4: - DMA_CCR4(dma) &= ~(0x3 << DMA_CCR4_MSIZE_LSB); - DMA_CCR4(dma) |= (mem_size << DMA_CCR4_MSIZE_LSB); - case 5: - DMA_CCR5(dma) &= ~(0x3 << DMA_CCR5_MSIZE_LSB); - DMA_CCR5(dma) |= (mem_size << DMA_CCR5_MSIZE_LSB); - case 6: - if (dma == DMA1) { - DMA_CCR6(dma) &= ~(0x3 << DMA_CCR6_MSIZE_LSB); - DMA_CCR6(dma) |= (mem_size << DMA_CCR6_MSIZE_LSB); - } - case 7: - if (dma == DMA1) { - DMA_CCR7(dma) &= ~(0x3 << DMA_CCR7_MSIZE_LSB); - DMA_CCR7(dma) |= (mem_size << DMA_CCR7_MSIZE_LSB); - } - } -} - - - -void dma_set_peripheral_size(u32 dma, u8 channel, u8 peripheral_size) -{ - /* parameter check */ - if (peripheral_size > 2) - return; - - switch (channel) - { - case 1: - DMA_CCR1(dma) &= ~(0x3 << DMA_CCR1_PSIZE_LSB); - DMA_CCR1(dma) |= (peripheral_size << DMA_CCR1_PSIZE_LSB); - case 2: - DMA_CCR2(dma) &= ~(0x3 << DMA_CCR2_PSIZE_LSB); - DMA_CCR2(dma) |= (peripheral_size << DMA_CCR2_PSIZE_LSB); - case 3: - DMA_CCR3(dma) &= ~(0x3 << DMA_CCR3_PSIZE_LSB); - DMA_CCR3(dma) |= (peripheral_size << DMA_CCR3_PSIZE_LSB); - case 4: - DMA_CCR4(dma) &= ~(0x3 << DMA_CCR4_PSIZE_LSB); - DMA_CCR4(dma) |= (peripheral_size << DMA_CCR4_PSIZE_LSB); - case 5: - DMA_CCR5(dma) &= ~(0x3 << DMA_CCR5_PSIZE_LSB); - DMA_CCR5(dma) |= (peripheral_size << DMA_CCR5_PSIZE_LSB); - case 6: - if (dma == DMA1) { - DMA_CCR6(dma) &= ~(0x3 << DMA_CCR6_PSIZE_LSB); - DMA_CCR6(dma) |= (peripheral_size << DMA_CCR6_PSIZE_LSB); - } - case 7: - if (dma == DMA1) { - DMA_CCR7(dma) &= ~(0x3 << DMA_CCR7_PSIZE_LSB); - DMA_CCR7(dma) |= (peripheral_size << DMA_CCR7_PSIZE_LSB); - } - } -} - - -void dma_enable_memory_increment_mode(u32 dma, u8 channel) -{ - switch (channel) - { - case 1: - DMA_CCR1(dma) |= DMA_CCR1_MINC; - case 2: - DMA_CCR2(dma) |= DMA_CCR2_MINC; - case 3: - DMA_CCR3(dma) |= DMA_CCR3_MINC; - case 4: - DMA_CCR4(dma) |= DMA_CCR4_MINC; - case 5: - DMA_CCR5(dma) |= DMA_CCR5_MINC; - case 6: - if (dma == DMA1) - DMA_CCR6(dma) |= DMA_CCR6_MINC; - case 7: - if (dma == DMA1) - DMA_CCR7(dma) |= DMA_CCR7_MINC; - } -} - -void dma_enable_peripheral_increment_mode(u32 dma, u8 channel) -{ - switch (channel) - { - case 1: - DMA_CCR1(dma) |= DMA_CCR1_PINC; - case 2: - DMA_CCR2(dma) |= DMA_CCR2_PINC; - case 3: - DMA_CCR3(dma) |= DMA_CCR3_PINC; - case 4: - DMA_CCR4(dma) |= DMA_CCR4_PINC; - case 5: - DMA_CCR5(dma) |= DMA_CCR5_PINC; - case 6: - if (dma == DMA1) - DMA_CCR6(dma) |= DMA_CCR6_PINC; - case 7: - if (dma == DMA1) - DMA_CCR7(dma) |= DMA_CCR7_PINC; - } -} - -void dma_enable_circular_mode(u32 dma, u8 channel) -{ - switch (channel) - { - case 1: - DMA_CCR1(dma) |= DMA_CCR1_CIRC; - DMA_CCR1(dma) &= ~DMA_CCR1_MEM2MEM; - case 2: - DMA_CCR2(dma) |= DMA_CCR2_CIRC; - DMA_CCR2(dma) &= ~DMA_CCR2_MEM2MEM; - case 3: - DMA_CCR3(dma) |= DMA_CCR3_CIRC; - DMA_CCR3(dma) &= ~DMA_CCR3_MEM2MEM; - case 4: - DMA_CCR4(dma) |= DMA_CCR4_CIRC; - DMA_CCR4(dma) &= ~DMA_CCR4_MEM2MEM; - case 5: - DMA_CCR5(dma) |= DMA_CCR5_CIRC; - DMA_CCR5(dma) &= ~DMA_CCR5_MEM2MEM; - case 6: - if (dma == DMA1) { - DMA_CCR6(dma) |= DMA_CCR6_CIRC; - DMA_CCR6(dma) &= ~DMA_CCR6_MEM2MEM; - } - case 7: - if (dma == DMA1) { - DMA_CCR7(dma) |= DMA_CCR7_CIRC; - DMA_CCR7(dma) &= ~DMA_CCR7_MEM2MEM; - } - } -} - -void dma_set_read_from_peripheral(u32 dma, u8 channel) -{ - switch (channel) - { - case 1: - DMA_CCR1(dma) &= ~DMA_CCR1_DIR; - case 2: - DMA_CCR2(dma) &= ~DMA_CCR2_DIR; - case 3: - DMA_CCR3(dma) &= ~DMA_CCR3_DIR; - case 4: - DMA_CCR4(dma) &= ~DMA_CCR4_DIR; - case 5: - DMA_CCR5(dma) &= ~DMA_CCR5_DIR; - case 6: - if (dma == DMA1) - DMA_CCR6(dma) &= ~DMA_CCR6_DIR; - case 7: - if (dma == DMA1) - DMA_CCR7(dma) &= ~DMA_CCR7_DIR; - } -} - -void dma_set_read_from_memory(u32 dma, u8 channel) -{ - switch (channel) - { - case 1: - DMA_CCR1(dma) |= DMA_CCR1_DIR; - case 2: - DMA_CCR2(dma) |= DMA_CCR2_DIR; - case 3: - DMA_CCR3(dma) |= DMA_CCR3_DIR; - case 4: - DMA_CCR4(dma) |= DMA_CCR4_DIR; - case 5: - DMA_CCR5(dma) |= DMA_CCR5_DIR; - case 6: - if (dma == DMA1) - DMA_CCR6(dma) |= DMA_CCR6_DIR; - case 7: - if (dma == DMA1) - DMA_CCR7(dma) |= DMA_CCR7_DIR; - } -} - -void dma_enable_transfer_error_interrupt(u32 dma, u8 channel) -{ - switch (channel) - { - case 1: - DMA_CCR1(dma) |= DMA_CCR1_TEIE; - case 2: - DMA_CCR2(dma) |= DMA_CCR2_TEIE; - case 3: - DMA_CCR3(dma) |= DMA_CCR3_TEIE; - case 4: - DMA_CCR4(dma) |= DMA_CCR4_TEIE; - case 5: - DMA_CCR5(dma) |= DMA_CCR5_TEIE; - case 6: - if (dma == DMA1) - DMA_CCR6(dma) |= DMA_CCR6_TEIE; - case 7: - if (dma == DMA1) - DMA_CCR7(dma) |= DMA_CCR7_TEIE; - } -} - -void dma_disable_transfer_error_interrupt(u32 dma, u8 channel) -{ - switch (channel) - { - case 1: - DMA_CCR1(dma) &= ~DMA_CCR1_TEIE; - case 2: - DMA_CCR2(dma) &= ~DMA_CCR2_TEIE; - case 3: - DMA_CCR3(dma) &= ~DMA_CCR3_TEIE; - case 4: - DMA_CCR4(dma) &= ~DMA_CCR4_TEIE; - case 5: - DMA_CCR5(dma) &= ~DMA_CCR5_TEIE; - case 6: - if (dma == DMA1) - DMA_CCR6(dma) &= ~DMA_CCR6_TEIE; - case 7: - if (dma == DMA1) - DMA_CCR7(dma) &= ~DMA_CCR7_TEIE; - } -} - -void dma_enable_half_transfer_interrupt(u32 dma, u8 channel) -{ - switch (channel) - { - case 1: - DMA_CCR1(dma) |= DMA_CCR1_HTIE; - case 2: - DMA_CCR2(dma) |= DMA_CCR2_HTIE; - case 3: - DMA_CCR3(dma) |= DMA_CCR3_HTIE; - case 4: - DMA_CCR4(dma) |= DMA_CCR4_HTIE; - case 5: - DMA_CCR5(dma) |= DMA_CCR5_HTIE; - case 6: - if (dma == DMA1) - DMA_CCR6(dma) |= DMA_CCR6_HTIE; - case 7: - if (dma == DMA1) - DMA_CCR7(dma) |= DMA_CCR7_HTIE; - } -} - -void dma_disable_half_transfer_interrupt(u32 dma, u8 channel) -{ - switch (channel) - { - case 1: - DMA_CCR1(dma) &= ~DMA_CCR1_HTIE; - case 2: - DMA_CCR2(dma) &= ~DMA_CCR2_HTIE; - case 3: - DMA_CCR3(dma) &= ~DMA_CCR3_HTIE; - case 4: - DMA_CCR4(dma) &= ~DMA_CCR4_HTIE; - case 5: - DMA_CCR5(dma) &= ~DMA_CCR5_HTIE; - case 6: - if (dma == DMA1) - DMA_CCR6(dma) &= ~DMA_CCR6_HTIE; - case 7: - if (dma == DMA1) - DMA_CCR7(dma) &= ~DMA_CCR7_HTIE; - } -} - -void dma_enable_transfer_complete_interrupt(u32 dma, u8 channel) -{ - switch (channel) - { - case 1: - DMA_CCR1(dma) |= DMA_CCR1_TCIE; - case 2: - DMA_CCR2(dma) |= DMA_CCR2_TCIE; - case 3: - DMA_CCR3(dma) |= DMA_CCR3_TCIE; - case 4: - DMA_CCR4(dma) |= DMA_CCR4_TCIE; - case 5: - DMA_CCR5(dma) |= DMA_CCR5_TCIE; - case 6: - if (dma == DMA1) - DMA_CCR6(dma) |= DMA_CCR6_TCIE; - case 7: - if (dma == DMA1) - DMA_CCR7(dma) |= DMA_CCR7_TCIE; - } -} - -void dma_disable_transfer_complete_interrupt(u32 dma, u8 channel) -{ - switch (channel) - { - case 1: - DMA_CCR1(dma) &= ~DMA_CCR1_TCIE; - case 2: - DMA_CCR2(dma) &= ~DMA_CCR2_TCIE; - case 3: - DMA_CCR3(dma) &= ~DMA_CCR3_TCIE; - case 4: - DMA_CCR4(dma) &= ~DMA_CCR4_TCIE; - case 5: - DMA_CCR5(dma) &= ~DMA_CCR5_TCIE; - case 6: - if (dma == DMA1) - DMA_CCR6(dma) &= ~DMA_CCR6_TCIE; - case 7: - if (dma == DMA1) - DMA_CCR7(dma) &= ~DMA_CCR7_TCIE; - } -} - -void dma_enable_channel(u32 dma, u8 channel) -{ - switch (channel) - { - case 1: - DMA_CCR1(dma) |= DMA_CCR1_EN; - case 2: - DMA_CCR2(dma) |= DMA_CCR2_EN; - case 3: - DMA_CCR3(dma) |= DMA_CCR3_EN; - case 4: - DMA_CCR4(dma) |= DMA_CCR4_EN; - case 5: - DMA_CCR5(dma) |= DMA_CCR5_EN; - case 6: - if (dma == DMA1) - DMA_CCR6(dma) |= DMA_CCR6_EN; - case 7: - if (dma == DMA1) - DMA_CCR7(dma) |= DMA_CCR7_EN; - } -} - -void dma_disable_channel(u32 dma, u8 channel) -{ - switch (channel) - { - case 1: - DMA_CCR1(dma) &= ~DMA_CCR1_EN; - case 2: - DMA_CCR2(dma) &= ~DMA_CCR2_EN; - case 3: - DMA_CCR3(dma) &= ~DMA_CCR3_EN; - case 4: - DMA_CCR4(dma) &= ~DMA_CCR4_EN; - case 5: - DMA_CCR5(dma) &= ~DMA_CCR5_EN; - case 6: - if (dma == DMA1) - DMA_CCR6(dma) &= ~DMA_CCR6_EN; - case 7: - if (dma == DMA1) - DMA_CCR7(dma) &= ~DMA_CCR7_EN; - } -} - -void dma_set_peripheral_address(u32 dma, u8 channel, u32 address) -{ - switch (channel) - { - case 1: - DMA_CPAR1(dma) = (u32)address; - case 2: - DMA_CPAR2(dma) = (u32)address; - case 3: - DMA_CPAR3(dma) = (u32)address; - case 4: - DMA_CPAR4(dma) = (u32)address; - case 5: - DMA_CPAR5(dma) = (u32)address; - case 6: - if (dma == DMA1) - DMA_CPAR6(dma) = (u32)address; - case 7: - if (dma == DMA1) - DMA_CPAR7(dma) = (u32)address; - } -} - -void dma_set_memory_address(u32 dma, u8 channel, u32 address) -{ - switch (channel) - { - case 1: - DMA_CMAR1(dma) = (u32)address; - case 2: - DMA_CMAR2(dma) = (u32)address; - case 3: - DMA_CMAR3(dma) = (u32)address; - case 4: - DMA_CMAR4(dma) = (u32)address; - case 5: - DMA_CMAR5(dma) = (u32)address; - case 6: - if (dma == DMA1) - DMA_CMAR6(dma) = (u32)address; - case 7: - if (dma == DMA1) - DMA_CMAR7(dma) = (u32)address; - } -} - -void dma_set_number_of_data(u32 dma, u8 channel, u16 number) -{ - switch (channel) - { - case 1: - DMA_CNDTR1(dma) = number; - case 2: - DMA_CNDTR2(dma) = number; - case 3: - DMA_CNDTR3(dma) = number; - case 4: - DMA_CNDTR4(dma) = number; - case 5: - DMA_CNDTR5(dma) = number; - case 6: - if (dma == DMA1) - DMA_CNDTR6(dma) = number; - case 7: - if (dma == DMA1) - DMA_CNDTR7(dma) = number; - } -} diff --git a/lib/stm32/ethernet.c b/lib/stm32/ethernet.c deleted file mode 100644 index 4a4d080..0000000 --- a/lib/stm32/ethernet.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Gareth McMullin - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include - -void eth_smi_write(u8 phy, u8 reg, u16 data) -{ - /* Set PHY and register addresses for write access. */ - ETH_MACMIIAR &= ~(ETH_MACMIIAR_MR | ETH_MACMIIAR_PA); - ETH_MACMIIAR |= (phy << 11) | (reg << 6) | ETH_MACMIIAR_MW; - - /* Set register value. */ - ETH_MACMIIDR = data; - - /* Begin transaction. */ - ETH_MACMIIAR |= ETH_MACMIIAR_MB; - - /* Wait for not busy. */ - while (ETH_MACMIIAR & ETH_MACMIIAR_MB); -} - -u16 eth_smi_read(u8 phy, u8 reg) -{ - /* Set PHY and register addresses for write access. */ - ETH_MACMIIAR &= ~(ETH_MACMIIAR_MR | ETH_MACMIIAR_PA | - ETH_MACMIIAR_MW); - ETH_MACMIIAR |= (phy << 11) | (reg << 6); - - /* Begin transaction. */ - ETH_MACMIIAR |= ETH_MACMIIAR_MB; - - /* Wait for not busy. */ - while (ETH_MACMIIAR & ETH_MACMIIAR_MB); - - /* Set register value. */ - return (u16)(ETH_MACMIIDR); -} diff --git a/lib/stm32/exti.c b/lib/stm32/exti.c deleted file mode 100644 index de037e7..0000000 --- a/lib/stm32/exti.c +++ /dev/null @@ -1,145 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Mark Butler - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include - -void exti_set_trigger(u32 extis, exti_trigger_type trig) -{ - switch (trig) { - case EXTI_TRIGGER_RISING: - EXTI_RTSR |= extis; - EXTI_FTSR &= ~extis; - break; - case EXTI_TRIGGER_FALLING: - EXTI_RTSR &= ~extis; - EXTI_FTSR |= extis; - break; - case EXTI_TRIGGER_BOTH: - EXTI_RTSR |= extis; - EXTI_FTSR |= extis; - break; - } -} - -void exti_enable_request(u32 extis) -{ - /* Enable interrupts. */ - EXTI_IMR |= extis; - - /* Enable events. */ - EXTI_EMR |= extis; -} - -void exti_disable_request(u32 extis) -{ - /* Disable interrupts. */ - EXTI_IMR &= ~extis; - - /* Disable events. */ - EXTI_EMR &= ~extis; -} - -/* - * Reset the interrupt request by writing a 1 to the corresponding - * pending bit register. - */ -void exti_reset_request(u32 extis) -{ - EXTI_PR |= extis; -} - -/* - * Remap an external interrupt line to the corresponding pin on the - * specified GPIO port. - * - * TODO: This could be rewritten in less lines of code. - */ -void exti_select_source(u32 exti, u32 gpioport) -{ - u8 shift, bits; - - shift = bits = 0; - - switch (exti) { - case EXTI0: - case EXTI4: - case EXTI8: - case EXTI12: - shift = 0; - break; - case EXTI1: - case EXTI5: - case EXTI9: - case EXTI13: - shift = 4; - break; - case EXTI2: - case EXTI6: - case EXTI10: - case EXTI14: - shift = 8; - break; - case EXTI3: - case EXTI7: - case EXTI11: - case EXTI15: - shift = 12; - break; - } - - switch (gpioport) { - case GPIOA: - bits = 0xf; - break; - case GPIOB: - bits = 0xe; - break; - case GPIOC: - bits = 0xd; - break; - case GPIOD: - bits = 0xc; - break; - case GPIOE: - bits = 0xb; - break; - case GPIOF: - bits = 0xa; - break; - case GPIOG: - bits = 0x9; - break; - } - - /* Ensure that only valid EXTI lines are used. */ - if (exti < EXTI4) { - AFIO_EXTICR1 &= ~(0x000F << shift); - AFIO_EXTICR1 |= (~bits << shift); - } else if (exti < EXTI8) { - AFIO_EXTICR2 &= ~(0x000F << shift); - AFIO_EXTICR2 |= (~bits << shift); - } else if (exti < EXTI12) { - AFIO_EXTICR3 &= ~(0x000F << shift); - AFIO_EXTICR3 |= (~bits << shift); - } else if (exti < EXTI16) { - AFIO_EXTICR4 &= ~(0x000F << shift); - AFIO_EXTICR4 |= (~bits << shift); - } -} diff --git a/lib/stm32/flash.c b/lib/stm32/flash.c deleted file mode 100644 index 98f7777..0000000 --- a/lib/stm32/flash.c +++ /dev/null @@ -1,189 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * Copyright (C) 2010 Mark Butler - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include - -void flash_prefetch_buffer_enable(void) -{ - FLASH_ACR |= FLASH_PRFTBE; -} - -void flash_prefetch_buffer_disable(void) -{ - FLASH_ACR &= ~FLASH_PRFTBE; -} - -void flash_halfcycle_enable(void) -{ - FLASH_ACR |= FLASH_HLFCYA; -} - -void flash_halfcycle_disable(void) -{ - FLASH_ACR &= ~FLASH_HLFCYA; -} - -void flash_set_ws(u32 ws) -{ - u32 reg32; - - reg32 = FLASH_ACR; - reg32 &= ~((1 << 0) | (1 << 1) | (1 << 2)); - reg32 |= ws; - FLASH_ACR = reg32; -} - -void flash_unlock(void) -{ - /* Authorize the FPEC access. */ - FLASH_KEYR = FLASH_KEY1; - FLASH_KEYR = FLASH_KEY2; -} - -void flash_lock(void) -{ - FLASH_CR |= FLASH_LOCK; -} - -void flash_clear_pgerr_flag(void) -{ - FLASH_SR |= FLASH_PGERR; -} - -void flash_clear_eop_flag(void) -{ - FLASH_SR |= FLASH_EOP; -} - -void flash_clear_wrprterr_flag(void) -{ - FLASH_SR |= FLASH_WRPRTERR; -} - -void flash_clear_bsy_flag(void) -{ - FLASH_SR &= ~FLASH_BSY; -} - -void flash_clear_status_flags(void) -{ - flash_clear_pgerr_flag(); - flash_clear_eop_flag(); - flash_clear_wrprterr_flag(); - flash_clear_bsy_flag(); -} - -void flash_unlock_option_bytes(void) -{ - FLASH_OPTKEYR = FLASH_KEY1; - FLASH_OPTKEYR = FLASH_KEY2; -} - -void flash_wait_for_last_operation(void) -{ - while ((FLASH_SR & FLASH_BSY) == FLASH_BSY) - ; -} - -void flash_program_word(u32 address, u32 data) -{ - /* Ensure that all flash operations are complete. */ - flash_wait_for_last_operation(); - - /* Enable writes to flash. */ - FLASH_CR |= FLASH_PG; - - /* Program the first half of the word. */ - (*(volatile u16 *)address) = (u16)data; - - /* Wait for the write to complete. */ - flash_wait_for_last_operation(); - - /* Program the second half of the word. */ - (*(volatile u16 *)(address + 2)) = data >> 16; - - /* Wait for the write to complete. */ - flash_wait_for_last_operation(); - - /* Disable writes to flash. */ - FLASH_CR &= ~FLASH_PG; -} - -void flash_program_half_word(u32 address, u16 data) -{ - flash_wait_for_last_operation(); - - FLASH_CR |= FLASH_PG; - - (*(volatile u16 *)address) = data; - - flash_wait_for_last_operation(); - - FLASH_CR &= ~FLASH_PG; /* Disable the PG bit. */ -} - -void flash_erase_page(u32 page_address) -{ - flash_wait_for_last_operation(); - - FLASH_CR |= FLASH_PER; - FLASH_AR = page_address; - FLASH_CR |= FLASH_STRT; - - flash_wait_for_last_operation(); - FLASH_CR &= ~FLASH_PER; -} - -void flash_erase_all_pages(void) -{ - flash_wait_for_last_operation(); - - FLASH_CR |= FLASH_MER; /* Enable mass erase. */ - FLASH_CR |= FLASH_STRT; /* Trigger the erase. */ - - flash_wait_for_last_operation(); - FLASH_CR &= ~FLASH_MER; /* Disable mass erase. */ -} - -void flash_erase_option_bytes(void) -{ - flash_wait_for_last_operation(); - - if ((FLASH_CR & FLASH_OPTWRE) == 0) - flash_unlock_option_bytes(); - - FLASH_CR |= FLASH_OPTER; /* Enable option byte erase. */ - FLASH_CR |= FLASH_STRT; - flash_wait_for_last_operation(); - FLASH_CR &= ~FLASH_OPTER; /* Disable option byte erase. */ -} - -void flash_program_option_bytes(u32 address, u16 data) -{ - flash_wait_for_last_operation(); - - if ((FLASH_CR & FLASH_OPTWRE) == 0) - flash_unlock_option_bytes(); - - FLASH_CR |= FLASH_OPTPG; /* Enable option byte programming. */ - (*(volatile u16 *)address) = data; - flash_wait_for_last_operation(); - FLASH_CR &= ~FLASH_OPTPG; /* Disable option byte programming. */ -} diff --git a/lib/stm32/gpio.c b/lib/stm32/gpio.c deleted file mode 100644 index 52c0c66..0000000 --- a/lib/stm32/gpio.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* - * Basic GPIO handling API. - * - * Examples: - * gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_2_MHZ, - * GPIO_CNF_OUTPUT_PUSHPULL, GPIO12); - * gpio_set(GPIOB, GPIO4); - * gpio_clear(GPIOG, GPIO2 | GPIO9); - * gpio_get(GPIOC, GPIO1); - * gpio_toggle(GPIOA, GPIO7 | GPIO8); - * reg16 = gpio_port_read(GPIOD); - * gpio_port_write(GPIOF, 0xc8fe); - * - * TODO: - * - GPIO remapping support - */ - -#include - -void gpio_set_mode(u32 gpioport, u8 mode, u8 cnf, u16 gpios) -{ - u16 i, offset = 0; - u32 crl = 0, crh = 0, tmp32 = 0; - - /* - * We want to set the config only for the pins mentioned in gpios, - * but keeping the others, so read out the actual config first. - */ - crl = GPIO_CRL(gpioport); - crh = GPIO_CRH(gpioport); - - /* Iterate over all bits, use i as the bitnumber. */ - for (i = 0; i < 16; i++) { - /* Only set the config if the bit is set in gpios. */ - if (!((1 << i) & gpios)) - continue; - - /* Calculate bit offset. */ - offset = (i < 8) ? (i * 4) : ((i - 8) * 4); - - /* Use tmp32 to either modify crl or crh. */ - tmp32 = (i < 8) ? crl : crh; - - /* Modify bits are needed. */ - tmp32 &= ~(0b1111 << offset); /* Clear the bits first. */ - tmp32 |= (mode << offset) | (cnf << (offset + 2)); - - /* Write tmp32 into crl or crh, leave the other unchanged. */ - crl = (i < 8) ? tmp32 : crl; - crh = (i >= 8) ? tmp32 : crh; - } - - GPIO_CRL(gpioport) = crl; - GPIO_CRH(gpioport) = crh; -} - -void gpio_set(u32 gpioport, u16 gpios) -{ - GPIO_BSRR(gpioport) = gpios; -} - -void gpio_clear(u32 gpioport, u16 gpios) -{ - GPIO_BRR(gpioport) = gpios; -} - -u16 gpio_get(u32 gpioport, u16 gpios) -{ - return gpio_port_read(gpioport) & gpios; -} - -void gpio_toggle(u32 gpioport, u16 gpios) -{ - GPIO_ODR(gpioport) = GPIO_IDR(gpioport) ^ gpios; -} - -u16 gpio_port_read(u32 gpioport) -{ - return (u16)GPIO_IDR(gpioport); -} - -void gpio_port_write(u32 gpioport, u16 data) -{ - GPIO_ODR(gpioport) = data; -} - -void gpio_port_config_lock(u32 gpioport, u16 gpios) -{ - u32 reg32; - - /* Special "Lock Key Writing Sequence", see datasheet. */ - GPIO_LCKR(gpioport) = GPIO_LCKK | gpios; /* Set LCKK. */ - GPIO_LCKR(gpioport) = ~GPIO_LCKK & gpios; /* Clear LCKK. */ - GPIO_LCKR(gpioport) = GPIO_LCKK | gpios; /* Set LCKK. */ - reg32 = GPIO_LCKR(gpioport); /* Read LCKK. */ - reg32 = GPIO_LCKR(gpioport); /* Read LCKK again. */ - - /* If (reg32 & GPIO_LCKK) is true, the lock is now active. */ -} diff --git a/lib/stm32/i2c.c b/lib/stm32/i2c.c deleted file mode 100644 index e1a3b84..0000000 --- a/lib/stm32/i2c.c +++ /dev/null @@ -1,93 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include - -void i2c_peripheral_enable(u32 i2c) -{ - I2C_CR1(i2c) |= I2C_CR1_PE; -} - -void i2c_peripheral_disable(u32 i2c) -{ - I2C_CR1(i2c) &= ~I2C_CR1_PE; -} - -void i2c_send_start(u32 i2c) -{ - I2C_CR1(i2c) |= I2C_CR1_START; -} - -void i2c_send_stop(u32 i2c) -{ - I2C_CR1(i2c) |= I2C_CR1_STOP; -} - -void i2c_set_own_7bit_slave_address(u32 i2c, u8 slave) -{ - I2C_OAR1(i2c) = (u16)(slave << 1); - I2C_OAR1(i2c) &= ~I2C_OAR1_ADDMODE; - I2C_OAR1(i2c) |= (1 << 14); /* Datasheet: always keep 1 by software. */ -} - -void i2c_set_own_10bit_slave_address(u32 i2c, u16 slave) -{ - I2C_OAR1(i2c) = (u16)(I2C_OAR1_ADDMODE | slave); -} - -void i2c_set_fast_mode(u32 i2c) -{ - I2C_CCR(i2c) |= I2C_CCR_FS; -} - -void i2c_set_standard_mode(u32 i2c) -{ - I2C_CCR(i2c) &= ~I2C_CCR_FS; -} - -void i2c_set_clock_frequency(u32 i2c, u8 freq) -{ - u16 reg16; - reg16 = I2C_CR2(i2c) & 0xffc0; /* Clear bits [5:0]. */ - reg16 |= freq; - I2C_CR2(i2c) = reg16; -} - -void i2c_set_ccr(u32 i2c, u16 freq) -{ - u16 reg16; - reg16 = I2C_CCR(i2c) & 0xf000; /* Clear bits [11:0]. */ - reg16 |= freq; - I2C_CCR(i2c) = reg16; -} - -void i2c_set_trise(u32 i2c, u16 trise) -{ - I2C_TRISE(i2c) = trise; -} - -void i2c_send_7bit_address(u32 i2c, u8 slave, u8 readwrite) -{ - I2C_DR(i2c) = (u8)((slave << 1) | readwrite); -} - -void i2c_send_data(u32 i2c, u8 data) -{ - I2C_DR(i2c) = data; -} diff --git a/lib/stm32/libopencm3_stm32.ld b/lib/stm32/libopencm3_stm32.ld deleted file mode 100644 index fda7d02..0000000 --- a/lib/stm32/libopencm3_stm32.ld +++ /dev/null @@ -1,63 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* Generic linker script for STM32 targets using libopencm3. */ - -/* Memory regions must be defined in the ld script which includes this one. */ - -/* Enforce emmition of the vector table. */ -EXTERN (vector_table) - -/* Define sections. */ -SECTIONS -{ - . = ORIGIN(rom); - - .text : { - *(.vectors) /* Vector table */ - *(.text*) /* Program code */ - *(.rodata*) /* Read-only data */ - _etext = .; - } >rom - - . = ORIGIN(ram); - - .data : { - _data = .; - *(.data*) /* Read-write initialized data */ - _edata = .; - } >ram AT >rom - - .bss : { - *(.bss*) /* Read-write zero initialized data */ - *(COMMON) - _ebss = .; - } >ram AT >rom - - /* - * The .eh_frame section appears to be used for C++ exception handling. - * You may need to fix this if you're using C++. - */ - /DISCARD/ : { *(.eh_frame) } - - end = .; -} - -PROVIDE(_stack = 0x20000800); - diff --git a/lib/stm32/nvic.c b/lib/stm32/nvic.c deleted file mode 100644 index cf77cc3..0000000 --- a/lib/stm32/nvic.c +++ /dev/null @@ -1,106 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include - -void nvic_enable_irq(u8 irqn) -{ - if (irqn < 32) - NVIC_ISER(0) |= (1 << irqn); - if ((irqn >= 32) & (irqn < 64)) - NVIC_ISER(1) |= (1 << (irqn - 32)); - if ((irqn >= 64) & (irqn < 68)) - NVIC_ISER(2) |= (1 << (irqn - 64)); -} - -void nvic_disable_irq(u8 irqn) -{ - if (irqn < 32) - NVIC_ICER(0) |= (1 << irqn); - if ((irqn >= 32) & (irqn < 64)) - NVIC_ICER(1) |= (1 << (irqn - 32)); - if ((irqn >= 64) & (irqn < 68)) - NVIC_ICER(2) |= (1 << (irqn - 64)); -} - -u8 nvic_get_pending_irq(u8 irqn) -{ - if (irqn < 32) - return (NVIC_ISPR(0) & (1 << irqn)); - if ((irqn >= 32) & (irqn < 64)) - return (NVIC_ISPR(1) & (1 << (irqn - 32))); - if ((irqn >= 64) & (irqn < 68)) - return (NVIC_ISPR(2) & (1 << (irqn - 64))); - return 0; -} - -void nvic_set_pending_irq(u8 irqn) -{ - if (irqn < 32) - NVIC_ISPR(0) |= (1 << irqn); - if ((irqn >= 32) & (irqn < 64)) - NVIC_ISPR(1) |= (1 << (irqn - 32)); - if ((irqn >= 64) & (irqn < 68)) - NVIC_ISPR(2) |= (1 << (irqn - 64)); -} - -void nvic_clear_pending_irq(u8 irqn) -{ - if (irqn < 32) - NVIC_ICPR(0) |= (1 << irqn); - if ((irqn >= 32) & (irqn < 64)) - NVIC_ICPR(1) |= (1 << (irqn - 32)); - if ((irqn >= 64) & (irqn < 68)) - NVIC_ICPR(2) |= (1 << (irqn - 64)); -} - -u8 nvic_get_active_irq(u8 irqn) -{ - if (irqn < 32) - return (NVIC_IABR(0) & (1 << irqn)); - if ((irqn >= 32) & (irqn < 64)) - return (NVIC_IABR(1) & (1 << (irqn - 32))); - if ((irqn >= 64) & (irqn < 68)) - return (NVIC_IABR(2) & (1 << (irqn - 64))); - return 0; -} - -u8 nvic_get_irq_enabled(u8 irqn) -{ - if (irqn < 32) - return (NVIC_ISER(0) & (1 << irqn)); - if ((irqn >= 32) & (irqn < 64)) - return (NVIC_ISER(1) & (1 << (irqn - 32))); - if ((irqn >= 64) & (irqn < 68)) - return (NVIC_ISER(2) & (1 << (irqn - 64))); - return 0; -} - -void nvic_set_priority(u8 irqn, u8 priority) -{ - NVIC_IPR(irqn/4) |= (priority << ((irqn % 4) * 8)); -} - -void nvic_generate_software_interrupt(u8 irqn) -{ - if (irqn <= 239) - NVIC_STIR |= irqn; -} - - diff --git a/lib/stm32/rcc.c b/lib/stm32/rcc.c deleted file mode 100644 index f646168..0000000 --- a/lib/stm32/rcc.c +++ /dev/null @@ -1,677 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Federico Ruiz-Ugalde - * Copyright (C) 2009 Uwe Hermann - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include - -/* Set the default ppre1 and ppre2 peripheral clock frequencies after reset */ -u32 rcc_ppre1_frequency = 8000000; -u32 rcc_ppre2_frequency = 8000000; - -void rcc_osc_ready_int_clear(osc_t osc) -{ - switch (osc) { - case PLL: - RCC_CIR |= RCC_CIR_PLLRDYC; - break; - case HSE: - RCC_CIR |= RCC_CIR_HSERDYC; - break; - case HSI: - RCC_CIR |= RCC_CIR_HSIRDYC; - break; - case LSE: - RCC_CIR |= RCC_CIR_LSERDYC; - break; - case LSI: - RCC_CIR |= RCC_CIR_LSIRDYC; - break; - } -} - -void rcc_osc_ready_int_enable(osc_t osc) -{ - switch (osc) { - case PLL: - RCC_CIR |= RCC_CIR_PLLRDYIE; - break; - case HSE: - RCC_CIR |= RCC_CIR_HSERDYIE; - break; - case HSI: - RCC_CIR |= RCC_CIR_HSIRDYIE; - break; - case LSE: - RCC_CIR |= RCC_CIR_LSERDYIE; - break; - case LSI: - RCC_CIR |= RCC_CIR_LSIRDYIE; - break; - } -} - -void rcc_osc_ready_int_disable(osc_t osc) -{ - switch (osc) { - case PLL: - RCC_CIR &= ~RCC_CIR_PLLRDYIE; - break; - case HSE: - RCC_CIR &= ~RCC_CIR_HSERDYIE; - break; - case HSI: - RCC_CIR &= ~RCC_CIR_HSIRDYIE; - break; - case LSE: - RCC_CIR &= ~RCC_CIR_LSERDYIE; - break; - case LSI: - RCC_CIR &= ~RCC_CIR_LSIRDYIE; - break; - } -} - -int rcc_osc_ready_int_flag(osc_t osc) -{ - switch (osc) { - case PLL: - return ((RCC_CIR & RCC_CIR_PLLRDYF) != 0); - break; - case HSE: - return ((RCC_CIR & RCC_CIR_HSERDYF) != 0); - break; - case HSI: - return ((RCC_CIR & RCC_CIR_HSIRDYF) != 0); - break; - case LSE: - return ((RCC_CIR & RCC_CIR_LSERDYF) != 0); - break; - case LSI: - return ((RCC_CIR & RCC_CIR_LSIRDYF) != 0); - break; - } - - /* Shouldn't be reached. */ - return -1; -} - -void rcc_css_int_clear(void) -{ - RCC_CIR |= RCC_CIR_CSSC; -} - -int rcc_css_int_flag(void) -{ - return ((RCC_CIR & RCC_CIR_CSSF) != 0); -} - -void rcc_wait_for_osc_ready(osc_t osc) -{ - switch (osc) { - case PLL: - while ((RCC_CR & RCC_CR_PLLRDY) == 0); - break; - case HSE: - while ((RCC_CR & RCC_CR_HSERDY) == 0); - break; - case HSI: - while ((RCC_CR & RCC_CR_HSIRDY) == 0); - break; - case LSE: - while ((RCC_BDCR & RCC_BDCR_LSERDY) == 0); - break; - case LSI: - while ((RCC_CSR & RCC_CSR_LSIRDY) == 0); - break; - } -} - -void rcc_osc_on(osc_t osc) -{ - switch (osc) { - case PLL: - RCC_CR |= RCC_CR_PLLON; - break; - case HSE: - RCC_CR |= RCC_CR_HSEON; - break; - case HSI: - RCC_CR |= RCC_CR_HSION; - break; - case LSE: - RCC_BDCR |= RCC_BDCR_LSEON; - break; - case LSI: - RCC_CSR |= RCC_CSR_LSION; - break; - } -} - -void rcc_osc_off(osc_t osc) -{ - switch (osc) { - case PLL: - RCC_CR &= ~RCC_CR_PLLON; - break; - case HSE: - RCC_CR &= ~RCC_CR_HSEON; - break; - case HSI: - RCC_CR &= ~RCC_CR_HSION; - break; - case LSE: - RCC_BDCR &= ~RCC_BDCR_LSEON; - break; - case LSI: - RCC_CSR &= ~RCC_CSR_LSION; - break; - } -} - -void rcc_css_enable(void) -{ - RCC_CR |= RCC_CR_CSSON; -} - -void rcc_css_disable(void) -{ - RCC_CR &= ~RCC_CR_CSSON; -} - -void rcc_osc_bypass_enable(osc_t osc) -{ - switch (osc) { - case HSE: - RCC_CR |= RCC_CR_HSEBYP; - break; - case LSE: - RCC_BDCR |= RCC_BDCR_LSEBYP; - break; - case PLL: - case HSI: - case LSI: - /* Do nothing, only HSE/LSE allowed here. */ - break; - } -} - -void rcc_osc_bypass_disable(osc_t osc) -{ - switch (osc) { - case HSE: - RCC_CR &= ~RCC_CR_HSEBYP; - break; - case LSE: - RCC_BDCR &= ~RCC_BDCR_LSEBYP; - break; - case PLL: - case HSI: - case LSI: - /* Do nothing, only HSE/LSE allowed here. */ - break; - } -} - -void rcc_peripheral_enable_clock(volatile u32 *reg, u32 en) -{ - *reg |= en; -} - -void rcc_peripheral_disable_clock(volatile u32 *reg, u32 en) -{ - *reg &= ~en; -} - -void rcc_peripheral_reset(volatile u32 *reg, u32 reset) -{ - *reg |= reset; -} - -void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset) -{ - *reg &= ~clear_reset; -} - -void rcc_set_sysclk_source(u32 clk) -{ - u32 reg32; - - reg32 = RCC_CFGR; - reg32 &= ~((1 << 1) | (1 << 0)); - RCC_CFGR = (reg32 | clk); -} - -void rcc_set_pll_multiplication_factor(u32 mul) -{ - u32 reg32; - - reg32 = RCC_CFGR; - reg32 &= ~((1 << 21) | (1 << 20) | (1 << 19) | (1 << 18)); - RCC_CFGR = (reg32 | (mul << 18)); -} - -void rcc_set_pll_source(u32 pllsrc) -{ - u32 reg32; - - reg32 = RCC_CFGR; - reg32 &= ~(1 << 16); - RCC_CFGR = (reg32 | (pllsrc << 16)); -} - -void rcc_set_pllxtpre(u32 pllxtpre) -{ - u32 reg32; - - reg32 = RCC_CFGR; - reg32 &= ~(1 << 17); - RCC_CFGR = (reg32 | (pllxtpre << 17)); -} - -void rcc_set_adcpre(u32 adcpre) -{ - u32 reg32; - - reg32 = RCC_CFGR; - reg32 &= ~((1 << 14) | (1 << 15)); - RCC_CFGR = (reg32 | (adcpre << 14)); -} - -void rcc_set_ppre2(u32 ppre2) -{ - u32 reg32; - - reg32 = RCC_CFGR; - reg32 &= ~((1 << 11) | (1 << 12) | (1 << 13)); - RCC_CFGR = (reg32 | (ppre2 << 11)); -} - -void rcc_set_ppre1(u32 ppre1) -{ - u32 reg32; - - reg32 = RCC_CFGR; - reg32 &= ~((1 << 8) | (1 << 9) | (1 << 10)); - RCC_CFGR = (reg32 | (ppre1 << 8)); -} - -void rcc_set_hpre(u32 hpre) -{ - u32 reg32; - - reg32 = RCC_CFGR; - reg32 &= ~((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7)); - RCC_CFGR = (reg32 | (hpre << 4)); -} - -void rcc_set_usbpre(u32 usbpre) -{ - u32 reg32; - - reg32 = RCC_CFGR; - reg32 &= ~(1 << 22); - RCC_CFGR = (reg32 | (usbpre << 22)); -} - -u32 rcc_system_clock_source(void) -{ - /* Return the clock source which is used as system clock. */ - return ((RCC_CFGR & 0x000c) >> 2); -} - -/* - * These functions are setting up the whole clock system for the most common - * input clock and output clock configurations. - */ -void rcc_clock_setup_in_hsi_out_64mhz(void) -{ - /* Enable internal high-speed oscillator. */ - rcc_osc_on(HSI); - rcc_wait_for_osc_ready(HSI); - - /* Select HSI as SYSCLK source. */ - rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK); - - /* - * Set prescalers for AHB, ADC, ABP1, ABP2. - * Do this before touching the PLL (TODO: why?). - */ - rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 64MHz Max. 72MHz */ - rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV8); /* Set. 8MHz Max. 14MHz */ - rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 32MHz Max. 36MHz */ - rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 64MHz Max. 72MHz */ - - /* - * Sysclk is running with 64MHz -> 2 waitstates. - * 0WS from 0-24MHz - * 1WS from 24-48MHz - * 2WS from 48-72MHz - */ - flash_set_ws(FLASH_LATENCY_2WS); - - /* - * Set the PLL multiplication factor to 16. - * 8MHz (internal) * 16 (multiplier) / 2 (PLLSRC_HSI_CLK_DIV2) = 64MHz - */ - rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_PLL_CLK_MUL16); - - /* Select HSI/2 as PLL source. */ - rcc_set_pll_source(RCC_CFGR_PLLSRC_HSI_CLK_DIV2); - - /* Enable PLL oscillator and wait for it to stabilize. */ - rcc_osc_on(PLL); - rcc_wait_for_osc_ready(PLL); - - /* Select PLL as SYSCLK source. */ - rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK); - - /* Set the peripheral clock frequencies used */ - rcc_ppre1_frequency = 32000000; - rcc_ppre2_frequency = 64000000; -} - -void rcc_clock_setup_in_hsi_out_48mhz(void) -{ - /* Enable internal high-speed oscillator. */ - rcc_osc_on(HSI); - rcc_wait_for_osc_ready(HSI); - - /* Select HSI as SYSCLK source. */ - rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK); - - /* - * Set prescalers for AHB, ADC, ABP1, ABP2. - * Do this before touching the PLL (TODO: why?). - */ - rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 48MHz Max. 72MHz */ - rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV8); /* Set. 6MHz Max. 14MHz */ - rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 24MHz Max. 36MHz */ - rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 48MHz Max. 72MHz */ - rcc_set_usbpre(RCC_CFGR_USBPRE_PLL_CLK_NODIV); /* Set. 48MHz Max. 48MHz */ - - /* - * Sysclk runs with 48MHz -> 1 waitstates. - * 0WS from 0-24MHz - * 1WS from 24-48MHz - * 2WS from 48-72MHz - */ - flash_set_ws(FLASH_LATENCY_1WS); - - /* - * Set the PLL multiplication factor to 12. - * 8MHz (internal) * 12 (multiplier) / 2 (PLLSRC_HSI_CLK_DIV2) = 48MHz - */ - rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_PLL_CLK_MUL12); - - /* Select HSI/2 as PLL source. */ - rcc_set_pll_source(RCC_CFGR_PLLSRC_HSI_CLK_DIV2); - - /* Enable PLL oscillator and wait for it to stabilize. */ - rcc_osc_on(PLL); - rcc_wait_for_osc_ready(PLL); - - /* Select PLL as SYSCLK source. */ - rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK); - - /* Set the peripheral clock frequencies used */ - rcc_ppre1_frequency = 24000000; - rcc_ppre2_frequency = 48000000; -} - -void rcc_clock_setup_in_hse_8mhz_out_24mhz(void) -{ - /* Enable internal high-speed oscillator. */ - rcc_osc_on(HSI); - rcc_wait_for_osc_ready(HSI); - - /* Select HSI as SYSCLK source. */ - rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK); - - /* Enable external high-speed oscillator 8MHz. */ - rcc_osc_on(HSE); - rcc_wait_for_osc_ready(HSE); - rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSECLK); - - /* - * Set prescalers for AHB, ADC, ABP1, ABP2. - * Do this before touching the PLL (TODO: why?). - */ - rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 24MHz Max. 72MHz */ - rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV2); /* Set. 12MHz Max. 14MHz */ - rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_NODIV); /* Set. 24MHz Max. 36MHz */ - rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 24MHz Max. 72MHz */ - - /* - * Sysclk runs with 24MHz -> 0 waitstates. - * 0WS from 0-24MHz - * 1WS from 24-48MHz - * 2WS from 48-72MHz - */ - flash_set_ws(FLASH_LATENCY_0WS); - - /* - * Set the PLL multiplication factor to 3. - * 8MHz (external) * 3 (multiplier) = 24MHz - */ - rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_PLL_CLK_MUL3); - - /* Select HSE as PLL source. */ - rcc_set_pll_source(RCC_CFGR_PLLSRC_HSE_CLK); - - /* - * External frequency undivided before entering PLL - * (only valid/needed for HSE). - */ - rcc_set_pllxtpre(RCC_CFGR_PLLXTPRE_HSE_CLK); - - /* Enable PLL oscillator and wait for it to stabilize. */ - rcc_osc_on(PLL); - rcc_wait_for_osc_ready(PLL); - - /* Select PLL as SYSCLK source. */ - rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK); - - /* Set the peripheral clock frequencies used */ - rcc_ppre1_frequency = 24000000; - rcc_ppre2_frequency = 24000000; -} -void rcc_clock_setup_in_hse_8mhz_out_72mhz(void) -{ - /* Enable internal high-speed oscillator. */ - rcc_osc_on(HSI); - rcc_wait_for_osc_ready(HSI); - - /* Select HSI as SYSCLK source. */ - rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK); - - /* Enable external high-speed oscillator 8MHz. */ - rcc_osc_on(HSE); - rcc_wait_for_osc_ready(HSE); - rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSECLK); - - /* - * Set prescalers for AHB, ADC, ABP1, ABP2. - * Do this before touching the PLL (TODO: why?). - */ - rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 72MHz Max. 72MHz */ - rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV8); /* Set. 9MHz Max. 14MHz */ - rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 36MHz Max. 36MHz */ - rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 72MHz Max. 72MHz */ - - /* - * Sysclk runs with 72MHz -> 2 waitstates. - * 0WS from 0-24MHz - * 1WS from 24-48MHz - * 2WS from 48-72MHz - */ - flash_set_ws(FLASH_LATENCY_2WS); - - /* - * Set the PLL multiplication factor to 9. - * 8MHz (external) * 9 (multiplier) = 72MHz - */ - rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_PLL_CLK_MUL9); - - /* Select HSE as PLL source. */ - rcc_set_pll_source(RCC_CFGR_PLLSRC_HSE_CLK); - - /* - * External frequency undivided before entering PLL - * (only valid/needed for HSE). - */ - rcc_set_pllxtpre(RCC_CFGR_PLLXTPRE_HSE_CLK); - - /* Enable PLL oscillator and wait for it to stabilize. */ - rcc_osc_on(PLL); - rcc_wait_for_osc_ready(PLL); - - /* Select PLL as SYSCLK source. */ - rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK); - - /* Set the peripheral clock frequencies used */ - rcc_ppre1_frequency = 36000000; - rcc_ppre2_frequency = 72000000; -} - -void rcc_clock_setup_in_hse_12mhz_out_72mhz(void) -{ - /* Enable internal high-speed oscillator. */ - rcc_osc_on(HSI); - rcc_wait_for_osc_ready(HSI); - - /* Select HSI as SYSCLK source. */ - rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK); - - /* Enable external high-speed oscillator 16MHz. */ - rcc_osc_on(HSE); - rcc_wait_for_osc_ready(HSE); - rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSECLK); - - /* - * Set prescalers for AHB, ADC, ABP1, ABP2. - * Do this before touching the PLL (TODO: why?). - */ - rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 72MHz Max. 72MHz */ - rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV6); /* Set. 12MHz Max. 14MHz */ - rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 36MHz Max. 36MHz */ - rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 72MHz Max. 72MHz */ - - /* - * Sysclk runs with 72MHz -> 2 waitstates. - * 0WS from 0-24MHz - * 1WS from 24-48MHz - * 2WS from 48-72MHz - */ - flash_set_ws(FLASH_LATENCY_2WS); - - /* - * Set the PLL multiplication factor to 9. - * 12MHz (external) * 6 (multiplier) / 1 (PLLXTPRE_HSE_CLK) = 72MHz - */ - rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_PLL_CLK_MUL6); - - /* Select HSI as PLL source. */ - rcc_set_pll_source(RCC_CFGR_PLLSRC_HSE_CLK); - - /* - * Divide external frequency by 2 before entering PLL - * (only valid/needed for HSE). - */ - rcc_set_pllxtpre(RCC_CFGR_PLLXTPRE_HSE_CLK); - - /* Enable PLL oscillator and wait for it to stabilize. */ - rcc_osc_on(PLL); - rcc_wait_for_osc_ready(PLL); - - /* Select PLL as SYSCLK source. */ - rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK); - - /* Set the peripheral clock frequencies used */ - rcc_ppre1_frequency = 36000000; - rcc_ppre2_frequency = 72000000; -} - -void rcc_clock_setup_in_hse_16mhz_out_72mhz(void) -{ - /* Enable internal high-speed oscillator. */ - rcc_osc_on(HSI); - rcc_wait_for_osc_ready(HSI); - - /* Select HSI as SYSCLK source. */ - rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK); - - /* Enable external high-speed oscillator 16MHz. */ - rcc_osc_on(HSE); - rcc_wait_for_osc_ready(HSE); - rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSECLK); - - /* - * Set prescalers for AHB, ADC, ABP1, ABP2. - * Do this before touching the PLL (TODO: why?). - */ - rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 72MHz Max. 72MHz */ - rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV6); /* Set. 12MHz Max. 14MHz */ - rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 36MHz Max. 36MHz */ - rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 72MHz Max. 72MHz */ - - /* - * Sysclk runs with 72MHz -> 2 waitstates. - * 0WS from 0-24MHz - * 1WS from 24-48MHz - * 2WS from 48-72MHz - */ - flash_set_ws(FLASH_LATENCY_2WS); - - /* - * Set the PLL multiplication factor to 9. - * 16MHz (external) * 9 (multiplier) / 2 (PLLXTPRE_HSE_CLK_DIV2) = 72MHz - */ - rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_PLL_CLK_MUL9); - - /* Select HSI as PLL source. */ - rcc_set_pll_source(RCC_CFGR_PLLSRC_HSE_CLK); - - /* - * Divide external frequency by 2 before entering PLL - * (only valid/needed for HSE). - */ - rcc_set_pllxtpre(RCC_CFGR_PLLXTPRE_HSE_CLK_DIV2); - - /* Enable PLL oscillator and wait for it to stabilize. */ - rcc_osc_on(PLL); - rcc_wait_for_osc_ready(PLL); - - /* Select PLL as SYSCLK source. */ - rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK); - - /* Set the peripheral clock frequencies used */ - rcc_ppre1_frequency = 36000000; - rcc_ppre2_frequency = 72000000; -} - -void rcc_backupdomain_reset(void) -{ - /* Set the backup domain software reset. */ - RCC_BDCR |= RCC_BDCR_BDRST; - - /* Clear the backup domain software reset. */ - RCC_BDCR &= ~RCC_BDCR_BDRST; -} diff --git a/lib/stm32/rtc.c b/lib/stm32/rtc.c deleted file mode 100644 index 4495641..0000000 --- a/lib/stm32/rtc.c +++ /dev/null @@ -1,282 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Uwe Hermann - * Copyright (C) 2010 Lord James - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include - -void rtc_awake_from_off(osc_t clock_source) -{ - u32 reg32; - - /* Enable power and backup interface clocks. */ - RCC_APB1ENR |= (RCC_APB1ENR_PWREN | RCC_APB1ENR_BKPEN); - - /* Enable access to the backup registers and the RTC. */ - PWR_CR |= PWR_CR_DBP; - - /* - * Reset the backup domain, clears everything RTC related. - * If not wanted use the rtc_awake_from_standby() function. - */ - rcc_backupdomain_reset(); - - switch (clock_source) { - case LSE: - /* Turn the LSE on and wait while it stabilises. */ - RCC_BDCR |= RCC_BDCR_LSEON; - while ((reg32 = (RCC_BDCR & RCC_BDCR_LSERDY)) == 0); - - /* Choose LSE as the RTC clock source. */ - RCC_BDCR &= ~((1 << 8) | (1 << 9)); - RCC_BDCR |= (1 << 8); - break; - case LSI: - /* Turn the LSI on and wait while it stabilises. */ - RCC_CSR |= RCC_CSR_LSION; - while ((reg32 = (RCC_CSR & RCC_CSR_LSIRDY)) == 0); - - /* Choose LSI as the RTC clock source. */ - RCC_BDCR &= ~((1 << 8) | (1 << 9)); - RCC_BDCR |= (1 << 9); - break; - case HSE: - /* Turn the HSE on and wait while it stabilises. */ - RCC_CR |= RCC_CR_HSEON; - while ((reg32 = (RCC_CR & RCC_CR_HSERDY)) == 0); - - /* Choose HSE as the RTC clock source. */ - RCC_BDCR &= ~((1 << 8) | (1 << 9)); - RCC_BDCR |= (1 << 9) | (1 << 8); - break; - case PLL: - case HSI: - /* Unusable clock source, here to prevent warnings. */ - /* Turn off clock sources to RTC. */ - RCC_BDCR &= ~((1 << 8) | (1 << 9)); - break; - } - - /* Enable the RTC. */ - RCC_BDCR |= RCC_BDCR_RTCEN; - - /* Wait for the RSF bit in RTC_CRL to be set by hardware. */ - RTC_CRL &= ~RTC_CRL_RSF; - while ((reg32 = (RTC_CRL & RTC_CRL_RSF)) == 0); - - /* Wait for the last write operation to finish. */ - /* TODO: Necessary? */ - while ((reg32 = (RTC_CRL & RTC_CRL_RTOFF)) == 0); -} - -void rtc_enter_config_mode(void) -{ - u32 reg32; - - /* Wait until the RTOFF bit is 1 (no RTC register writes ongoing). */ - while ((reg32 = (RTC_CRL & RTC_CRL_RTOFF)) == 0); - - /* Enter configuration mode. */ - RTC_CRL |= RTC_CRL_CNF; -} - -void rtc_exit_config_mode(void) -{ - /* u32 reg32; */ - - /* Exit configuration mode. */ - RTC_CRL &= ~RTC_CRL_CNF; - - /* Wait until the RTOFF bit is 1 (our RTC register write finished). */ - /* while ((reg32 = (RTC_CRL & RTC_CRL_RTOFF)) == 0); */ - /* TODO: Unnecessary since we poll the bit on config entry(?) */ -} - -void rtc_set_alarm_time(u32 alarm_time) -{ - rtc_enter_config_mode(); - RTC_ALRL = (alarm_time & 0x0000ffff); - RTC_ALRH = (alarm_time & 0xffff0000) >> 16; - rtc_exit_config_mode(); -} - -void rtc_enable_alarm(void) -{ - rtc_enter_config_mode(); - RTC_CRH |= RTC_CRH_ALRIE; - rtc_exit_config_mode(); -} - -void rtc_disable_alarm(void) -{ - rtc_enter_config_mode(); - RTC_CRH &= ~RTC_CRH_ALRIE; - rtc_exit_config_mode(); -} - -void rtc_set_prescale_val(u32 prescale_val) -{ - rtc_enter_config_mode(); - RTC_PRLL = prescale_val & 0x0000ffff; /* PRL[15:0] */ - RTC_PRLH = (prescale_val & 0x000f0000) >> 16; /* PRL[19:16] */ - rtc_exit_config_mode(); -} - -u32 rtc_get_counter_val(void) -{ - return (RTC_CNTH << 16) | RTC_CNTL; -} - -u32 rtc_get_prescale_div_val(void) -{ - return (RTC_DIVH << 16) | RTC_DIVL; -} - -u32 rtc_get_alarm_val(void) -{ - return (RTC_ALRH << 16) | RTC_ALRL; -} - -void rtc_set_counter_val(u32 counter_val) -{ - rtc_enter_config_mode(); - RTC_CNTH = (counter_val & 0xffff0000) >> 16; /* CNT[31:16] */ - RTC_CNTL = counter_val & 0x0000ffff; /* CNT[15:0] */ - rtc_exit_config_mode(); -} - -void rtc_interrupt_enable(rtcflag_t flag_val) -{ - rtc_enter_config_mode(); - - /* Set the correct interrupt enable. */ - switch(flag_val) { - case RTC_SEC: - RTC_CRH |= RTC_CRH_SECIE; - break; - case RTC_ALR: - RTC_CRH |= RTC_CRH_ALRIE; - break; - case RTC_OW: - RTC_CRH |= RTC_CRH_OWIE; - break; - } - - rtc_exit_config_mode(); -} - -void rtc_interrupt_disable(rtcflag_t flag_val) -{ - rtc_enter_config_mode(); - - /* Disable the correct interrupt enable. */ - switch(flag_val) { - case RTC_SEC: - RTC_CRH &= ~RTC_CRH_SECIE; - break; - case RTC_ALR: - RTC_CRH &= ~RTC_CRH_ALRIE; - break; - case RTC_OW: - RTC_CRH &= ~RTC_CRH_OWIE; - break; - } - - rtc_exit_config_mode(); -} - -void rtc_clear_flag(rtcflag_t flag_val) -{ - /* Configuration mode not needed. */ - - /* Clear the correct flag. */ - switch(flag_val) { - case RTC_SEC: - RTC_CRL &= ~RTC_CRL_SECF; - break; - case RTC_ALR: - RTC_CRL &= ~RTC_CRL_ALRF; - break; - case RTC_OW: - RTC_CRL &= ~RTC_CRL_OWF; - break; - } -} - -u32 rtc_check_flag(rtcflag_t flag_val) -{ - u32 reg32; - - /* Read correct flag. */ - switch(flag_val) { - case RTC_SEC: - reg32 = RTC_CRL & RTC_CRL_SECF; - break; - case RTC_ALR: - reg32 = RTC_CRL & RTC_CRL_ALRF; - break; - case RTC_OW: - reg32 = RTC_CRL & RTC_CRL_OWF; - break; - default: - reg32 = 0; - break; - } - - return reg32; -} - -void rtc_awake_from_standby(void) -{ - u32 reg32; - - /* Enable power and backup interface clocks. */ - RCC_APB1ENR |= (RCC_APB1ENR_PWREN | RCC_APB1ENR_BKPEN); - - /* Enable access to the backup registers and the RTC. */ - PWR_CR |= PWR_CR_DBP; - - /* Wait for the RSF bit in RTC_CRL to be set by hardware. */ - RTC_CRL &= ~RTC_CRL_RSF; - while ((reg32 = (RTC_CRL & RTC_CRL_RSF)) == 0); - - /* Wait for the last write operation to finish. */ - /* TODO: Necessary? */ - while ((reg32 = (RTC_CRL & RTC_CRL_RTOFF)) == 0); -} - -void rtc_auto_awake(osc_t clock_source, u32 prescale_val) -{ - u32 reg32; - - /* Enable power and backup interface clocks. */ - RCC_APB1ENR |= (RCC_APB1ENR_PWREN | RCC_APB1ENR_BKPEN); - - /* Enable access to the backup registers and the RTC. */ - /* TODO: Not sure if this is necessary to just read the flag. */ - PWR_CR |= PWR_CR_DBP; - - if ((reg32 = RCC_BDCR & RCC_BDCR_RTCEN) != 0) { - rtc_awake_from_standby(); - } else { - rtc_awake_from_off(clock_source); - rtc_set_prescale_val(prescale_val); - } -} diff --git a/lib/stm32/scb.c b/lib/stm32/scb.c deleted file mode 100644 index dfee6c3..0000000 --- a/lib/stm32/scb.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Gareth McMullin - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include - -void scb_reset_core(void) -{ - SCB_AIRCR = SCB_AIRCR_VECTKEY | SCB_AIRCR_VECTRESET; -} - -void scb_reset_system(void) -{ - SCB_AIRCR = SCB_AIRCR_VECTKEY | SCB_AIRCR_SYSRESETREQ; -} diff --git a/lib/stm32/spi.c b/lib/stm32/spi.c deleted file mode 100644 index 733a1bc..0000000 --- a/lib/stm32/spi.c +++ /dev/null @@ -1,290 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include - -/* - * SPI and I2S code. - * - * Examples: - * spi_init_master(SPI1, 1000000, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE, - * SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT, - * SPI_CR1_LSBFIRST); - * spi_write(SPI1, 0x55); // 8-bit write - * spi_write(SPI1, 0xaa88); // 16-bit write - * reg8 = spi_read(SPI1); // 8-bit read - * reg16 = spi_read(SPI1); // 16-bit read - */ - -int spi_init_master(u32 spi, u32 br, u32 cpol, u32 cpha, u32 dff, u32 lsbfirst) -{ - u32 reg32 = 0; - - reg32 |= SPI_CR1_MSTR; /* Configure SPI as master. */ - - reg32 |= br; /* Set BAUD rate bits. */ - reg32 |= cpol; /* Set CPOL value. */ - reg32 |= cpha; /* Set CPHA value. */ - reg32 |= dff; /* Set data format (8 or 16 bits). */ - reg32 |= lsbfirst; /* Set frame format (LSB- or MSB-first). */ - - /* TODO: NSS pin handling. */ - - SPI_CR1(spi) = reg32; - - return 0; /* TODO */ -} - -/* TODO: Error handling? */ -void spi_enable(u32 spi) -{ - u32 reg32; - - reg32 = SPI_CR1(spi); - reg32 |= SPI_CR1_SPE; /* Enable SPI. */ - SPI_CR1(spi) = reg32; -} - -/* TODO: Error handling? */ -void spi_disable(u32 spi) -{ - u32 reg32; - - /* TODO: Follow procedure from section 23.3.8 in the techref manual. */ - reg32 = SPI_CR1(spi); - reg32 &= ~(SPI_CR1_SPE); /* Disable SPI. */ - SPI_CR1(spi) = reg32; -} - -void spi_write(u32 spi, u16 data) -{ - /* Write data (8 or 16 bits, depending on DFF) into DR. */ - SPI_DR(spi) = data; -} - -void spi_send(u32 spi, u16 data) -{ - /* Write data (8 or 16 bits, depending on DFF) into DR. */ - SPI_DR(spi) = data; - - /* wait for transfer finished */ - while (SPI_SR(spi) & SPI_SR_BSY ) - { - } -} - -u16 spi_read(u32 spi) -{ - /* Read the data (8 or 16 bits, depending on DFF bit) from DR. */ - return SPI_DR(spi); -} - -void spi_set_bidirectional_mode(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_BIDIMODE; -} - -void spi_set_unidirectional_mode(u32 spi) -{ - SPI_CR1(spi) &= ~SPI_CR1_BIDIMODE; -} - -void spi_set_bidirectional_receive_only_mode(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_BIDIMODE; - SPI_CR1(spi) &= ~SPI_CR1_BIDIOE; -} - -void spi_set_bidirectional_transmit_only_mode(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_BIDIMODE; - SPI_CR1(spi) |= SPI_CR1_BIDIOE; -} - -void spi_enable_crc(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_CRCEN; -} - -void spi_disable_crc(u32 spi) -{ - SPI_CR1(spi) &= ~SPI_CR1_CRCEN; -} - -void spi_set_next_tx_from_buffer(u32 spi) -{ - SPI_CR1(spi) &= ~SPI_CR1_CRCNEXT; -} - -void spi_set_next_tx_from_crc(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_CRCNEXT; -} - -void spi_set_dff_8bit(u32 spi) -{ - SPI_CR1(spi) &= ~SPI_CR1_DFF; -} - -void spi_set_dff_16bit(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_DFF; -} - -void spi_set_full_duplex_mode(u32 spi) -{ - SPI_CR1(spi) &= ~SPI_CR1_RXONLY; -} - -void spi_set_receive_only_mode(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_RXONLY; -} - -void spi_disable_software_slave_management(u32 spi) -{ - SPI_CR1(spi) &= ~SPI_CR1_SSM; -} - -void spi_enable_software_slave_management(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_SSM; -} - -void spi_set_nss_high(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_SSI; -} - -void spi_set_nss_low(u32 spi) -{ - SPI_CR1(spi) &= ~SPI_CR1_SSI; -} - -void spi_send_lsb_first(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_LSBFIRST; -} - -void spi_send_msb_first(u32 spi) -{ - SPI_CR1(spi) &= ~SPI_CR1_LSBFIRST; -} - -void spi_set_baudrate_prescaler(u32 spi, u8 baudrate) -{ - u32 reg32; - - if (baudrate > 7) - return; - - reg32 = ( SPI_CR1(spi) & 0xffc7 ); /* clear bits [5:3] */ - reg32 |= (baudrate << 3); - SPI_CR1(spi) = reg32; -} - -void spi_set_master_mode(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_MSTR; -} - -void spi_set_slave_mode(u32 spi) -{ - SPI_CR1(spi) &= ~SPI_CR1_MSTR; -} - -void spi_set_clock_polarity_1(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_CPOL; -} - -void spi_set_clock_polarity_0(u32 spi) -{ - SPI_CR1(spi) &= ~SPI_CR1_CPOL; -} - -void spi_set_clock_phase_1(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_CPHA; -} - -void spi_set_clock_phase_0(u32 spi) -{ - SPI_CR1(spi) &= ~SPI_CR1_CPHA; -} - -void spi_enable_tx_buffer_empty_interrupt(u32 spi) -{ - SPI_CR2(spi) |= SPI_CR2_TXEIE; -} - -void spi_disable_tx_buffer_empty_interrupt(u32 spi) -{ - SPI_CR2(spi) &= ~SPI_CR2_TXEIE; -} - -void spi_enable_rx_buffer_not_empty_interrupt(u32 spi) -{ - SPI_CR2(spi) |= SPI_CR2_RXNEIE; -} - -void spi_disable_rx_buffer_not_empty_interrupt(u32 spi) -{ - SPI_CR2(spi) &= ~SPI_CR2_RXNEIE; -} - -void spi_enable_error_interrupt(u32 spi) -{ - SPI_CR2(spi) |= SPI_CR2_ERRIE; -} - -void spi_disable_error_interrupt(u32 spi) -{ - SPI_CR2(spi) &= ~SPI_CR2_ERRIE; -} - -void spi_enable_ss_output(u32 spi) -{ - SPI_CR2(spi) |= SPI_CR2_SSOE; -} - -void spi_disable_ss_output(u32 spi) -{ - SPI_CR2(spi) &= ~SPI_CR2_SSOE; -} - -void spi_enable_tx_dma(u32 spi) -{ - SPI_CR2(spi) |= SPI_CR2_TXDMAEN; -} - -void spi_disable_tx_dma(u32 spi) -{ - SPI_CR2(spi) &= ~SPI_CR2_TXDMAEN; -} - -void spi_enable_rx_dma(u32 spi) -{ - SPI_CR2(spi) |= SPI_CR2_RXDMAEN; -} - -void spi_disable_rx_dma(u32 spi) -{ - SPI_CR2(spi) &= ~SPI_CR2_RXDMAEN; -} diff --git a/lib/stm32/systick.c b/lib/stm32/systick.c deleted file mode 100644 index 882601d..0000000 --- a/lib/stm32/systick.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include - -void systick_set_reload(u32 value) -{ - STK_LOAD = (value & 0x00FFFFFF); -} - -u32 systick_get_value(void) -{ - return STK_VAL; -} - -void systick_set_clocksource(u8 clocksource) -{ - if (clocksource < 2) - STK_CTRL |= (clocksource << STK_CTRL_CLKSOURCE_LSB); -} - -void systick_interrupt_enable(void) -{ - STK_CTRL |= STK_CTRL_TICKINT; -} - -void systick_interrupt_disable(void) -{ - STK_CTRL &= ~STK_CTRL_TICKINT; -} - -void systick_counter_enable(void) -{ - STK_CTRL |= STK_CTRL_ENABLE; -} - -void systick_counter_disable(void) -{ - STK_CTRL &= ~STK_CTRL_ENABLE; -} - -u8 systick_get_countflag(void) -{ - if (STK_CTRL & STK_CTRL_COUNTFLAG) - return 1; - else - return 0; -} diff --git a/lib/stm32/timer.c b/lib/stm32/timer.c deleted file mode 100644 index 32e240d..0000000 --- a/lib/stm32/timer.c +++ /dev/null @@ -1,914 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Edward Cheeseman - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* - * Basic TIMER handling API. - * - * Examples: - * timer_set_mode(TIM1, TIM_CR1_CKD_CK_INT_MUL_2, - * TIM_CR1_CMS_CENTRE_3, TIM_CR1_DIR_UP); - */ - -#include -#include - -void timer_reset(u32 timer_peripheral) -{ - switch (timer_peripheral) { - case TIM1: - rcc_peripheral_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM1RST); - rcc_peripheral_clear_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM1RST); - break; - case TIM2: - rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM2RST); - rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM2RST); - break; - case TIM3: - rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM3RST); - rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM3RST); - break; - case TIM4: - rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM4RST); - rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM4RST); - break; - case TIM5: - rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM5RST); - rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM5RST); - break; - case TIM6: - rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM6RST); - rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM6RST); - break; - case TIM7: - rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM7RST); - rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM7RST); - break; - case TIM8: - rcc_peripheral_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM8RST); - rcc_peripheral_clear_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM8RST); - break; -/* These timers are not supported in libopencm3 yet */ -/* - case TIM9: - rcc_peripheral_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM9RST); - rcc_peripheral_clear_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM9RST); - break; - case TIM10: - rcc_peripheral_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM10RST); - rcc_peripheral_clear_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM10RST); - break; - case TIM11: - rcc_peripheral_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM11RST); - rcc_peripheral_clear_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM11RST); - break; - case TIM12: - rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM12RST); - rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM12RST); - break; - case TIM13: - rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM13RST); - rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM13RST); - break; - case TIM14: - rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM14RST); - rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM14RST); - break; -*/ - } -} - -void timer_enable_irq(u32 timer_peripheral, u32 irq) -{ - TIM_DIER(timer_peripheral) |= irq; -} - -void timer_disable_irq(u32 timer_peripheral, u32 irq) -{ - TIM_DIER(timer_peripheral) &= ~irq; -} - -bool timer_get_flag(u32 timer_peripheral, u32 flag) -{ - if (((TIM_SR(timer_peripheral) & flag) != 0) && - ((TIM_DIER(timer_peripheral) & flag) != 0)) { - return true; - } - - return false; -} - -void timer_clear_flag(u32 timer_peripheral, u32 flag) -{ - TIM_SR(timer_peripheral) &= ~flag; -} - -void timer_set_mode(u32 timer_peripheral, u8 clock_div, - u8 alignment, u8 direction) -{ - u32 cr1; - - cr1 = TIM_CR1(timer_peripheral); - - cr1 &= ~(TIM_CR1_CKD_CK_INT_MASK | - TIM_CR1_CMS_MASK | - TIM_CR1_DIR_DOWN); - - cr1 |= clock_div | alignment | direction; - - TIM_CR1(timer_peripheral) = cr1; -} - -void timer_set_clock_division(u32 timer_peripheral, u32 clock_div) -{ - clock_div &= TIM_CR1_CKD_CK_INT_MASK; - TIM_CR1(timer_peripheral) &= ~TIM_CR1_CKD_CK_INT_MASK; - TIM_CR1(timer_peripheral) |= clock_div; -} - -void timer_enable_preload(u32 timer_peripheral) -{ - TIM_CR1(timer_peripheral) |= TIM_CR1_ARPE; -} - -void timer_disable_preload(u32 timer_peripheral) -{ - TIM_CR1(timer_peripheral) &= ~TIM_CR1_ARPE; -} - -void timer_set_alignment(u32 timer_peripheral, u32 alignment) -{ - alignment &= TIM_CR1_CMS_MASK; - TIM_CR1(timer_peripheral) &= ~TIM_CR1_CMS_MASK; - TIM_CR1(timer_peripheral) |= alignment; -} - -void timer_direction_up(u32 timer_peripheral) -{ - TIM_CR1(timer_peripheral) &= ~TIM_CR1_DIR_DOWN; -} - -void timer_direction_down(u32 timer_peripheral) -{ - TIM_CR1(timer_peripheral) |= TIM_CR1_DIR_DOWN; -} - -void timer_one_shot_mode(u32 timer_peripheral) -{ - TIM_CR1(timer_peripheral) |= TIM_CR1_OPM; -} - -void timer_continuous_mode(u32 timer_peripheral) -{ - TIM_CR1(timer_peripheral) &= ~TIM_CR1_OPM; -} - -void timer_update_on_any(u32 timer_peripheral) -{ - TIM_CR1(timer_peripheral) &= ~TIM_CR1_URS; -} - -void timer_update_on_overflow(u32 timer_peripheral) -{ - TIM_CR1(timer_peripheral) |= TIM_CR1_URS; -} - -void timer_enable_update_event(u32 timer_peripheral) -{ - TIM_CR1(timer_peripheral) &= ~TIM_CR1_UDIS; -} - -void timer_disable_update_event(u32 timer_peripheral) -{ - TIM_CR1(timer_peripheral) |= TIM_CR1_UDIS; -} - -void timer_enable_counter(u32 timer_peripheral) -{ - TIM_CR1(timer_peripheral) |= TIM_CR1_CEN; -} - -void timer_disable_counter(u32 timer_peripheral) -{ - TIM_CR1(timer_peripheral) &= ~TIM_CR1_CEN; -} - -void timer_set_output_idle_state(u32 timer_peripheral, u32 outputs) -{ - TIM_CR2(timer_peripheral) |= outputs & TIM_CR2_OIS_MASK; -} - -void timer_reset_output_idle_state(u32 timer_peripheral, u32 outputs) -{ - TIM_CR2(timer_peripheral) &= ~(outputs & TIM_CR2_OIS_MASK); -} - -void timer_set_ti1_ch123_xor(u32 timer_peripheral) -{ - TIM_CR2(timer_peripheral) |= TIM_CR2_TI1S; -} - -void timer_set_ti1_ch1(u32 timer_peripheral) -{ - TIM_CR2(timer_peripheral) &= ~TIM_CR2_TI1S; -} - -void timer_set_master_mode(u32 timer_peripheral, u32 mode) -{ - TIM_CR2(timer_peripheral) &= ~TIM_CR2_MMS_MASK; - TIM_CR2(timer_peripheral) |= mode; -} - -void timer_set_dma_on_compare_event(u32 timer_peripheral) -{ - TIM_CR2(timer_peripheral) &= ~TIM_CR2_CCDS; -} - -void timer_set_dma_on_update_event(u32 timer_peripheral) -{ - TIM_CR2(timer_peripheral) |= TIM_CR2_CCDS; -} - -void timer_enable_compare_control_update_on_trigger(u32 timer_peripheral) -{ - TIM_CR2(timer_peripheral) |= TIM_CR2_CCUS; -} - -void timer_disable_compare_control_update_on_trigger(u32 timer_peripheral) -{ - TIM_CR2(timer_peripheral) &= ~TIM_CR2_CCUS; -} - -void timer_enable_preload_complementry_enable_bits(u32 timer_peripheral) -{ - TIM_CR2(timer_peripheral) |= TIM_CR2_CCPC; -} - -void timer_disable_preload_complementry_enable_bits(u32 timer_peripheral) -{ - TIM_CR2(timer_peripheral) &= ~TIM_CR2_CCPC; -} - -void timer_set_prescaler(u32 timer_peripheral, u32 value) -{ - TIM_PSC(timer_peripheral) = value; -} - -void timer_set_repetition_counter(u32 timer_peripheral, u32 value) -{ - if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) - TIM_RCR(timer_peripheral) = value; -} - -void timer_set_period(u32 timer_peripheral, u32 period) -{ - TIM_ARR(timer_peripheral) = period; -} - -void timer_enable_oc_clear(u32 timer_peripheral, enum tim_oc_id oc_id) -{ - switch (oc_id) { - case TIM_OC1: - TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1CE; - break; - case TIM_OC2: - TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2CE; - break; - case TIM_OC3: - TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3CE; - break; - case TIM_OC4: - TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4CE; - break; - case TIM_OC1N: - case TIM_OC2N: - case TIM_OC3N: - /* Ignoring as fast enable only applies to the whole channel. */ - break; - } -} - -void timer_disable_oc_clear(u32 timer_peripheral, enum tim_oc_id oc_id) -{ - switch (oc_id) { - case TIM_OC1: - TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC1CE; - break; - case TIM_OC2: - TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC2CE; - break; - case TIM_OC3: - TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC3CE; - break; - case TIM_OC4: - TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC4CE; - break; - case TIM_OC1N: - case TIM_OC2N: - case TIM_OC3N: - /* Ignoring as fast enable only applies to the whole channel. */ - break; - } -} - -void timer_set_oc_fast_mode(u32 timer_peripheral, enum tim_oc_id oc_id) -{ - switch (oc_id) { - case TIM_OC1: - TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1FE; - break; - case TIM_OC2: - TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2FE; - break; - case TIM_OC3: - TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3FE; - break; - case TIM_OC4: - TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4FE; - break; - case TIM_OC1N: - case TIM_OC2N: - case TIM_OC3N: - /* Ignoring as fast enable only applies to the whole channel. */ - break; - } -} - -void timer_set_oc_slow_mode(u32 timer_peripheral, enum tim_oc_id oc_id) -{ - switch (oc_id) { - case TIM_OC1: - TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC1FE; - break; - case TIM_OC2: - TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC2FE; - break; - case TIM_OC3: - TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC3FE; - break; - case TIM_OC4: - TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC4FE; - break; - case TIM_OC1N: - case TIM_OC2N: - case TIM_OC3N: - /* Ignoring as this option applies to the whole channel. */ - break; - } -} - -void timer_set_oc_mode(u32 timer_peripheral, enum tim_oc_id oc_id, - enum tim_oc_mode oc_mode) -{ - switch (oc_id) { - case TIM_OC1: - TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_CC1S_MASK; - TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_CC1S_OUT; - TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC1M_MASK; - switch (oc_mode) { - case TIM_OCM_FROZEN: - TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_FROZEN; - break; - case TIM_OCM_ACTIVE: - TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_ACTIVE; - break; - case TIM_OCM_INACTIVE: - TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_INACTIVE; - break; - case TIM_OCM_TOGGLE: - TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_TOGGLE; - break; - case TIM_OCM_FORCE_LOW: - TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_FORCE_LOW; - break; - case TIM_OCM_FORCE_HIGH: - TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_FORCE_HIGH; - break; - case TIM_OCM_PWM1: - TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_PWM1; - break; - case TIM_OCM_PWM2: - TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_PWM2; - break; - } - break; - case TIM_OC2: - TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_CC2S_MASK; - TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_CC2S_OUT; - TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC2M_MASK; - switch (oc_mode) { - case TIM_OCM_FROZEN: - TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_FROZEN; - break; - case TIM_OCM_ACTIVE: - TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_ACTIVE; - break; - case TIM_OCM_INACTIVE: - TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_INACTIVE; - break; - case TIM_OCM_TOGGLE: - TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_TOGGLE; - break; - case TIM_OCM_FORCE_LOW: - TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_FORCE_LOW; - break; - case TIM_OCM_FORCE_HIGH: - TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_FORCE_HIGH; - break; - case TIM_OCM_PWM1: - TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_PWM1; - break; - case TIM_OCM_PWM2: - TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_PWM2; - break; - } - break; - case TIM_OC3: - TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR2_CC3S_MASK; - TIM_CCMR1(timer_peripheral) |= TIM_CCMR2_CC3S_OUT; - TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC3M_MASK; - switch (oc_mode) { - case TIM_OCM_FROZEN: - TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_FROZEN; - break; - case TIM_OCM_ACTIVE: - TIM_CCMR1(timer_peripheral) |= TIM_CCMR2_OC3M_ACTIVE; - break; - case TIM_OCM_INACTIVE: - TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_INACTIVE; - break; - case TIM_OCM_TOGGLE: - TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_TOGGLE; - break; - case TIM_OCM_FORCE_LOW: - TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_FORCE_LOW; - break; - case TIM_OCM_FORCE_HIGH: - TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_FORCE_HIGH; - break; - case TIM_OCM_PWM1: - TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_PWM1; - break; - case TIM_OCM_PWM2: - TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_PWM2; - break; - } - break; - case TIM_OC4: - TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR2_CC4S_MASK; - TIM_CCMR1(timer_peripheral) |= TIM_CCMR2_CC4S_OUT; - TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC4M_MASK; - switch (oc_mode) { - case TIM_OCM_FROZEN: - TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_FROZEN; - break; - case TIM_OCM_ACTIVE: - TIM_CCMR1(timer_peripheral) |= TIM_CCMR2_OC4M_ACTIVE; - break; - case TIM_OCM_INACTIVE: - TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_INACTIVE; - break; - case TIM_OCM_TOGGLE: - TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_TOGGLE; - break; - case TIM_OCM_FORCE_LOW: - TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_FORCE_LOW; - break; - case TIM_OCM_FORCE_HIGH: - TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_FORCE_HIGH; - break; - case TIM_OCM_PWM1: - TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_PWM1; - break; - case TIM_OCM_PWM2: - TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_PWM2; - break; - } - break; - case TIM_OC1N: - case TIM_OC2N: - case TIM_OC3N: - /* Ignoring as this option applies to the whole channel. */ - break; - } -} - -void timer_enable_oc_preload(u32 timer_peripheral, enum tim_oc_id oc_id) -{ - switch (oc_id) { - case TIM_OC1: - TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1PE; - break; - case TIM_OC2: - TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2PE; - break; - case TIM_OC3: - TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3PE; - break; - case TIM_OC4: - TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4PE; - break; - case TIM_OC1N: - case TIM_OC2N: - case TIM_OC3N: - /* Ignoring as this option applies to the whole channel. */ - break; - } -} - -void timer_disable_oc_preload(u32 timer_peripheral, enum tim_oc_id oc_id) -{ - switch (oc_id) { - case TIM_OC1: - TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC1PE; - break; - case TIM_OC2: - TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC2PE; - break; - case TIM_OC3: - TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC3PE; - break; - case TIM_OC4: - TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC4PE; - break; - case TIM_OC1N: - case TIM_OC2N: - case TIM_OC3N: - /* Ignoring as this option applies to the whole channel. */ - break; - } -} - -void timer_set_oc_polarity_high(u32 timer_peripheral, enum tim_oc_id oc_id) -{ - switch (oc_id) { - case TIM_OC1: - TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC1P; - break; - case TIM_OC2: - TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC2P; - break; - case TIM_OC3: - TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC3P; - break; - case TIM_OC4: - TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC4P; - break; - case TIM_OC1N: - case TIM_OC2N: - case TIM_OC3N: - /* Ignoring as this option applies to TIM1 and TIM8 only. */ - break; - } - - /* Acting for TIM1 and TIM8 only from here onwards. */ - if ((timer_peripheral != TIM1) && (timer_peripheral != TIM8)) - return; - - switch (oc_id) { - case TIM_OC1N: - TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC1NP; - break; - case TIM_OC2N: - TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC2NP; - break; - case TIM_OC3N: - TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC3NP; - break; - case TIM_OC1: - case TIM_OC2: - case TIM_OC3: - case TIM_OC4: - /* Ignoring as this option was already set above. */ - break; - } -} - -void timer_set_oc_polarity_low(u32 timer_peripheral, enum tim_oc_id oc_id) -{ - switch (oc_id) { - case TIM_OC1: - TIM_CCER(timer_peripheral) |= TIM_CCER_CC1P; - break; - case TIM_OC2: - TIM_CCER(timer_peripheral) |= TIM_CCER_CC2P; - break; - case TIM_OC3: - TIM_CCER(timer_peripheral) |= TIM_CCER_CC3P; - break; - case TIM_OC4: - TIM_CCER(timer_peripheral) |= TIM_CCER_CC4P; - break; - case TIM_OC1N: - case TIM_OC2N: - case TIM_OC3N: - /* Ignoring as this option applies to TIM1 and TIM8 only. */ - break; - } - - /* Acting for TIM1 and TIM8 only from here onwards. */ - if ((timer_peripheral != TIM1) && (timer_peripheral != TIM8)) - return; - - switch (oc_id) { - case TIM_OC1N: - TIM_CCER(timer_peripheral) |= TIM_CCER_CC1NP; - break; - case TIM_OC2N: - TIM_CCER(timer_peripheral) |= TIM_CCER_CC2NP; - break; - case TIM_OC3N: - TIM_CCER(timer_peripheral) |= TIM_CCER_CC3NP; - break; - case TIM_OC1: - case TIM_OC2: - case TIM_OC3: - case TIM_OC4: - /* Ignoring as this option was already set above. */ - break; - } -} - -void timer_enable_oc_output(u32 timer_peripheral, enum tim_oc_id oc_id) -{ - switch (oc_id) { - case TIM_OC1: - TIM_CCER(timer_peripheral) |= TIM_CCER_CC1E; - break; - case TIM_OC2: - TIM_CCER(timer_peripheral) |= TIM_CCER_CC2E; - break; - case TIM_OC3: - TIM_CCER(timer_peripheral) |= TIM_CCER_CC3E; - break; - case TIM_OC4: - TIM_CCER(timer_peripheral) |= TIM_CCER_CC4E; - break; - case TIM_OC1N: - case TIM_OC2N: - case TIM_OC3N: - /* Ignoring as this option applies to TIM1 and TIM8 only. */ - break; - } - - /* Acting for TIM1 and TIM8 only from here onwards. */ - if ((timer_peripheral != TIM1) && (timer_peripheral != TIM8)) - return; - - switch (oc_id) { - case TIM_OC1N: - TIM_CCER(timer_peripheral) |= TIM_CCER_CC1NE; - break; - case TIM_OC2N: - TIM_CCER(timer_peripheral) |= TIM_CCER_CC2NE; - break; - case TIM_OC3N: - TIM_CCER(timer_peripheral) |= TIM_CCER_CC3NE; - break; - case TIM_OC1: - case TIM_OC2: - case TIM_OC3: - case TIM_OC4: - /* Ignoring as this option was already set above. */ - break; - } -} - -void timer_disable_oc_output(u32 timer_peripheral, enum tim_oc_id oc_id) -{ - switch (oc_id) { - case TIM_OC1: - TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC1E; - break; - case TIM_OC2: - TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC2E; - break; - case TIM_OC3: - TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC3E; - break; - case TIM_OC4: - TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC4E; - break; - case TIM_OC1N: - case TIM_OC2N: - case TIM_OC3N: - /* Ignoring as this option applies to TIM1 and TIM8 only. */ - break; - } - - /* Acting for TIM1 and TIM8 only from here onwards. */ - if ((timer_peripheral != TIM1) && (timer_peripheral != TIM8)) - return; - - switch (oc_id) { - case TIM_OC1N: - TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC1NE; - break; - case TIM_OC2N: - TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC2NE; - break; - case TIM_OC3N: - TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC3NE; - break; - case TIM_OC1: - case TIM_OC2: - case TIM_OC3: - case TIM_OC4: - /* Ignoring as this option was already set above. */ - break; - } -} - -void timer_set_oc_idle_state_set(u32 timer_peripheral, enum tim_oc_id oc_id) -{ - /* Acting for TIM1 and TIM8 only. */ - if ((timer_peripheral != TIM1) && (timer_peripheral != TIM8)) - return; - - switch (oc_id) { - case TIM_OC1: - TIM_CR2(timer_peripheral) |= TIM_CR2_OIS1; - break; - case TIM_OC1N: - TIM_CR2(timer_peripheral) |= TIM_CR2_OIS1N; - break; - case TIM_OC2: - TIM_CR2(timer_peripheral) |= TIM_CR2_OIS2; - break; - case TIM_OC2N: - TIM_CR2(timer_peripheral) |= TIM_CR2_OIS2N; - break; - case TIM_OC3: - TIM_CR2(timer_peripheral) |= TIM_CR2_OIS3; - break; - case TIM_OC3N: - TIM_CR2(timer_peripheral) |= TIM_CR2_OIS3N; - break; - case TIM_OC4: - TIM_CR2(timer_peripheral) |= TIM_CR2_OIS4; - break; - } -} - -void timer_set_oc_idle_state_unset(u32 timer_peripheral, enum tim_oc_id oc_id) -{ - /* Acting for TIM1 and TIM8 only. */ - if ((timer_peripheral != TIM1) && (timer_peripheral != TIM8)) - return; - - switch (oc_id) { - case TIM_OC1: - TIM_CR2(timer_peripheral) &= ~TIM_CR2_OIS1; - break; - case TIM_OC1N: - TIM_CR2(timer_peripheral) &= ~TIM_CR2_OIS1N; - break; - case TIM_OC2: - TIM_CR2(timer_peripheral) &= ~TIM_CR2_OIS2; - break; - case TIM_OC2N: - TIM_CR2(timer_peripheral) &= ~TIM_CR2_OIS2N; - break; - case TIM_OC3: - TIM_CR2(timer_peripheral) &= ~TIM_CR2_OIS3; - break; - case TIM_OC3N: - TIM_CR2(timer_peripheral) &= ~TIM_CR2_OIS3N; - break; - case TIM_OC4: - TIM_CR2(timer_peripheral) &= ~TIM_CR2_OIS4; - break; - } -} - -void timer_set_oc_value(u32 timer_peripheral, enum tim_oc_id oc_id, u32 value) -{ - switch (oc_id) { - case TIM_OC1: - TIM_CCR1(timer_peripheral) = value; - break; - case TIM_OC2: - TIM_CCR2(timer_peripheral) = value; - break; - case TIM_OC3: - TIM_CCR3(timer_peripheral) = value; - break; - case TIM_OC4: - TIM_CCR4(timer_peripheral) = value; - break; - case TIM_OC1N: - case TIM_OC2N: - case TIM_OC3N: - /* Ignoring as this option applies to the whole channel. */ - break; - } -} - -void timer_enable_break_main_output(u32 timer_peripheral) -{ - if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) - TIM_BDTR(timer_peripheral) |= TIM_BDTR_MOE; -} - -void timer_disable_break_main_output(u32 timer_peripheral) -{ - if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) - TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_MOE; -} - -void timer_enable_break_automatic_output(u32 timer_peripheral) -{ - if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) - TIM_BDTR(timer_peripheral) |= TIM_BDTR_AOE; -} - -void timer_disable_break_automatic_output(u32 timer_peripheral) -{ - if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) - TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_AOE; -} - -void timer_set_break_polarity_high(u32 timer_peripheral) -{ - if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) - TIM_BDTR(timer_peripheral) |= TIM_BDTR_BKP; -} - -void timer_set_break_polarity_low(u32 timer_peripheral) -{ - if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) - TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_BKP; -} - -void timer_enable_break(u32 timer_peripheral) -{ - if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) - TIM_BDTR(timer_peripheral) |= TIM_BDTR_BKE; -} - -void timer_disable_break(u32 timer_peripheral) -{ - if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) - TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_BKE; -} - -void timer_set_enabled_off_state_in_run_mode(u32 timer_peripheral) -{ - if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) - TIM_BDTR(timer_peripheral) |= TIM_BDTR_OSSR; -} - -void timer_set_disabled_off_state_in_run_mode(u32 timer_peripheral) -{ - if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) - TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_OSSR; -} - -void timer_set_enabled_off_state_in_idle_mode(u32 timer_peripheral) -{ - if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) - TIM_BDTR(timer_peripheral) |= TIM_BDTR_OSSI; -} - -void timer_set_disabled_off_state_in_idle_mode(u32 timer_peripheral) -{ - if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) - TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_OSSI; -} - -void timer_set_break_lock(u32 timer_peripheral, u32 lock) -{ - if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) - TIM_BDTR(timer_peripheral) |= lock; -} - -void timer_set_deadtime(u32 timer_peripheral, u32 deadtime) -{ - if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) - TIM_BDTR(timer_peripheral) |= deadtime; -} - -void timer_generate_event(u32 timer_peripheral, u32 event) -{ - TIM_EGR(timer_peripheral) |= event; -} - -u32 timer_get_counter(u32 timer_peripheral) -{ - return TIM_CNT(timer_peripheral); -} diff --git a/lib/stm32/usart.c b/lib/stm32/usart.c deleted file mode 100644 index ead0ef7..0000000 --- a/lib/stm32/usart.c +++ /dev/null @@ -1,131 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include - -#include - -void usart_set_baudrate(u32 usart, u32 baud) -{ - u32 clock = rcc_ppre1_frequency; - - if (usart == USART1) { - clock = rcc_ppre2_frequency; - } - - /* yes it is as simple as that. The reference manual is - * talking about factional calculation but it seems to be only - * marketting bable to sound awesome. It is nothing else but a - * simple divider to generate the correct baudrate. >_< If I - * am wrong feel free to correct me on that. :) (esden) - */ - USART_BRR(usart) = clock/baud; -} - -void usart_set_databits(u32 usart, u32 bits) -{ - if (bits == 8) - USART_CR1(usart) &= ~USART_CR1_M; /* 8 data bits */ - else - USART_CR1(usart) |= USART_CR1_M; /* 9 data bits */ -} - -void usart_set_stopbits(u32 usart, u32 stopbits) -{ - u32 reg32; - - reg32 = USART_CR2(usart); - reg32 = (reg32 & ~USART_CR2_STOPBITS_MASK) | stopbits; - USART_CR2(usart) = reg32; -} - -void usart_set_parity(u32 usart, u32 parity) -{ - u32 reg32; - - reg32 = USART_CR1(usart); - reg32 = (reg32 & ~USART_PARITY_MASK) | parity; - USART_CR1(usart) = reg32; -} - -void usart_set_mode(u32 usart, u32 mode) -{ - u32 reg32; - - reg32 = USART_CR1(usart); - reg32 = (reg32 & ~USART_MODE_MASK) | mode; - USART_CR1(usart) = reg32; -} - -void usart_set_flow_control(u32 usart, u32 flowcontrol) -{ - u32 reg32; - - reg32 = USART_CR3(usart); - reg32 = (reg32 & ~USART_FLOWCONTROL_MASK) | flowcontrol; - USART_CR3(usart) = reg32; -} - -void usart_enable(u32 usart) -{ - USART_CR1(usart) |= USART_CR1_UE; -} - -void usart_disable(u32 usart) -{ - USART_CR1(usart) &= ~USART_CR1_UE; -} - -void usart_send(u32 usart, u16 data) -{ - /* Send data. */ - USART_DR(usart) = (data & USART_DR_MASK); -} - -u16 usart_recv(u32 usart) -{ - /* Receive data. */ - return USART_DR(usart) & USART_DR_MASK; -} - -void usart_wait_send_ready(u32 usart) -{ - /* Wait until the data has been transferred into the shift register. */ - while ((USART_SR(usart) & USART_SR_TXE) == 0); -} - -void usart_wait_recv_ready(u32 usart) -{ - /* Wait until the data is ready to be received. */ - while ((USART_SR(usart) & USART_SR_RXNE) == 0); -} - -void usart_send_blocking(u32 usart, u16 data) -{ - usart_send(usart, data); - - usart_wait_send_ready(usart); -} - -u16 usart_recv_blocking(u32 usart) -{ - usart_wait_recv_ready(usart); - - return usart_recv(usart); -} diff --git a/lib/stm32/vector.c b/lib/stm32/vector.c deleted file mode 100644 index 39bd9a1..0000000 --- a/lib/stm32/vector.c +++ /dev/null @@ -1,296 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#define WEAK __attribute__ ((weak)) - -/* Symbols exported by linker script */ -extern unsigned _etext, _data, _edata, _ebss, _stack; - -void main(void); -void reset_handler(void); -void blocking_handler(void); -void null_handler(void); - -void WEAK nmi_handler(void); -void WEAK hard_fault_handler(void); -void WEAK mem_manage_handler(void); -void WEAK bus_fault_handler(void); -void WEAK usage_fault_handler(void); -void WEAK sv_call_handler(void); -void WEAK debug_monitor_handler(void); -void WEAK pend_sv_handler(void); -void WEAK sys_tick_handler(void); -void WEAK wwdg_isr(void); -void WEAK pvd_isr(void); -void WEAK tamper_isr(void); -void WEAK rtc_isr(void); -void WEAK flash_isr(void); -void WEAK rcc_isr(void); -void WEAK exti0_isr(void); -void WEAK exti1_isr(void); -void WEAK exti2_isr(void); -void WEAK exti3_isr(void); -void WEAK exti4_isr(void); -void WEAK dma1_channel1_isr(void); -void WEAK dma1_channel2_isr(void); -void WEAK dma1_channel3_isr(void); -void WEAK dma1_channel4_isr(void); -void WEAK dma1_channel5_isr(void); -void WEAK dma1_channel6_isr(void); -void WEAK dma1_channel7_isr(void); -void WEAK adc1_2_isr(void); -void WEAK usb_hp_can_tx_isr(void); -void WEAK usb_lp_can_rx0_isr(void); -void WEAK can_rx1_isr(void); -void WEAK can_sce_isr(void); -void WEAK exti9_5_isr(void); -void WEAK tim1_brk_isr(void); -void WEAK tim1_up_isr(void); -void WEAK tim1_trg_com_isr(void); -void WEAK tim1_cc_isr(void); -void WEAK tim2_isr(void); -void WEAK tim3_isr(void); -void WEAK tim4_isr(void); -void WEAK i2c1_ev_isr(void); -void WEAK i2c1_er_isr(void); -void WEAK i2c2_ev_isr(void); -void WEAK i2c2_er_isr(void); -void WEAK spi1_isr(void); -void WEAK spi2_isr(void); -void WEAK usart1_isr(void); -void WEAK usart2_isr(void); -void WEAK usart3_isr(void); -void WEAK exti15_10_isr(void); -void WEAK rtc_alarm_isr(void); -void WEAK usb_wakeup_isr(void); -void WEAK tim8_brk_isr(void); -void WEAK tim8_up_isr(void); -void WEAK tim8_trg_com_isr(void); -void WEAK tim8_cc_isr(void); -void WEAK adc3_isr(void); -void WEAK fsmc_isr(void); -void WEAK sdio_isr(void); -void WEAK tim5_isr(void); -void WEAK spi3_isr(void); -void WEAK usart4_isr(void); -void WEAK usart5_isr(void); -void WEAK tim6_isr(void); -void WEAK tim7_isr(void); -void WEAK dma2_channel1_isr(void); -void WEAK dma2_channel2_isr(void); -void WEAK dma2_channel3_isr(void); -void WEAK dma2_channel4_5_isr(void); -void WEAK dma2_channel5_isr(void); -void WEAK eth_isr(void); -void WEAK eth_wkup_isr(void); -void WEAK can2_tx_isr(void); -void WEAK can2_rx0_isr(void); -void WEAK can2_rx1_isr(void); -void WEAK can2_sce_isr(void); -void WEAK otg_fs_isr(void); - - -__attribute__ ((section(".vectors"))) -void (*const vector_table[]) (void) = { - (void*)&_stack, - reset_handler, - nmi_handler, - hard_fault_handler, - mem_manage_handler, - bus_fault_handler, - usage_fault_handler, - 0, 0, 0, 0, /* Reserved */ - sv_call_handler, - debug_monitor_handler, - 0, /* Reserved */ - pend_sv_handler, - sys_tick_handler, - wwdg_isr, - pvd_isr, - tamper_isr, - rtc_isr, - flash_isr, - rcc_isr, - exti0_isr, - exti1_isr, - exti2_isr, - exti3_isr, - exti4_isr, - dma1_channel1_isr, - dma1_channel2_isr, - dma1_channel3_isr, - dma1_channel4_isr, - dma1_channel5_isr, - dma1_channel6_isr, - dma1_channel7_isr, - adc1_2_isr, - usb_hp_can_tx_isr, - usb_lp_can_rx0_isr, - can_rx1_isr, - can_sce_isr, - exti9_5_isr, - tim1_brk_isr, - tim1_up_isr, - tim1_trg_com_isr, - tim1_cc_isr, - tim2_isr, - tim3_isr, - tim4_isr, - i2c1_ev_isr, - i2c1_er_isr, - i2c2_ev_isr, - i2c2_er_isr, - spi1_isr, - spi2_isr, - usart1_isr, - usart2_isr, - usart3_isr, - exti15_10_isr, - rtc_alarm_isr, - usb_wakeup_isr, - tim8_brk_isr, - tim8_up_isr, - tim8_trg_com_isr, - tim8_cc_isr, - adc3_isr, - fsmc_isr, - sdio_isr, - tim5_isr, - spi3_isr, - usart4_isr, - usart5_isr, - tim6_isr, - tim7_isr, - dma2_channel1_isr, - dma2_channel2_isr, - dma2_channel3_isr, - dma2_channel4_5_isr, - dma2_channel5_isr, - eth_isr, - eth_wkup_isr, - can2_tx_isr, - can2_rx0_isr, - can2_rx1_isr, - can2_sce_isr, - otg_fs_isr, -}; - -void reset_handler(void) -{ - volatile unsigned *src, *dest; - asm("MSR msp, %0" : : "r"(&_stack)); - - for (src = &_etext, dest = &_data; dest < &_edata; src++, dest++) - *dest = *src; - - while (dest < &_ebss) - *dest++ = 0; - - /* Call the application's entry point. */ - main(); -} - -void blocking_handler(void) -{ - while (1) ; -} - -void null_handler(void) -{ - /* Do nothing. */ -} - -#pragma weak nmi_handler = null_handler -#pragma weak hard_fault_handler = blocking_handler -#pragma weak mem_manage_handler = blocking_handler -#pragma weak bus_fault_handler = blocking_handler -#pragma weak usage_fault_handler = blocking_handler -#pragma weak sv_call_handler = null_handler -#pragma weak debug_monitor_handler = null_handler -#pragma weak pend_sv_handler = null_handler -#pragma weak sys_tick_handler = null_handler -#pragma weak wwdg_isr = null_handler -#pragma weak pvd_isr = null_handler -#pragma weak tamper_isr = null_handler -#pragma weak rtc_isr = null_handler -#pragma weak flash_isr = null_handler -#pragma weak rcc_isr = null_handler -#pragma weak exti0_isr = null_handler -#pragma weak exti1_isr = null_handler -#pragma weak exti2_isr = null_handler -#pragma weak exti3_isr = null_handler -#pragma weak exti4_isr = null_handler -#pragma weak dma1_channel1_isr = null_handler -#pragma weak dma1_channel2_isr = null_handler -#pragma weak dma1_channel3_isr = null_handler -#pragma weak dma1_channel4_isr = null_handler -#pragma weak dma1_channel5_isr = null_handler -#pragma weak dma1_channel6_isr = null_handler -#pragma weak dma1_channel7_isr = null_handler -#pragma weak adc1_2_isr = null_handler -#pragma weak usb_hp_can_tx_isr = null_handler -#pragma weak usb_lp_can_rx0_isr = null_handler -#pragma weak can_rx1_isr = null_handler -#pragma weak can_sce_isr = null_handler -#pragma weak exti9_5_isr = null_handler -#pragma weak tim1_brk_isr = null_handler -#pragma weak tim1_up_isr = null_handler -#pragma weak tim1_trg_com_isr = null_handler -#pragma weak tim1_cc_isr = null_handler -#pragma weak tim2_isr = null_handler -#pragma weak tim3_isr = null_handler -#pragma weak tim4_isr = null_handler -#pragma weak i2c1_ev_isr = null_handler -#pragma weak i2c1_er_isr = null_handler -#pragma weak i2c2_ev_isr = null_handler -#pragma weak i2c2_er_isr = null_handler -#pragma weak spi1_isr = null_handler -#pragma weak spi2_isr = null_handler -#pragma weak usart1_isr = null_handler -#pragma weak usart2_isr = null_handler -#pragma weak usart3_isr = null_handler -#pragma weak exti15_10_isr = null_handler -#pragma weak rtc_alarm_isr = null_handler -#pragma weak usb_wakeup_isr = null_handler -#pragma weak tim8_brk_isr = null_handler -#pragma weak tim8_up_isr = null_handler -#pragma weak tim8_trg_com_isr = null_handler -#pragma weak tim8_cc_isr = null_handler -#pragma weak adc3_isr = null_handler -#pragma weak fsmc_isr = null_handler -#pragma weak sdio_isr = null_handler -#pragma weak tim5_isr = null_handler -#pragma weak spi3_isr = null_handler -#pragma weak usart4_isr = null_handler -#pragma weak usart5_isr = null_handler -#pragma weak tim6_isr = null_handler -#pragma weak tim7_isr = null_handler -#pragma weak dma2_channel1_isr = null_handler -#pragma weak dma2_channel2_isr = null_handler -#pragma weak dma2_channel3_isr = null_handler -#pragma weak dma2_channel4_5_isr = null_handler -#pragma weak dma2_channel5_isr -#pragma weak eth_isr = null_handler -#pragma weak eth_wkup_isr = null_handler -#pragma weak can2_tx_isr = null_handler -#pragma weak can2_rx0_isr = null_handler -#pragma weak can2_rx1_isr = null_handler -#pragma weak can2_sce_isr = null_handler -#pragma weak otg_fs_isr = null_handler - diff --git a/lib/stm32f1/Makefile b/lib/stm32f1/Makefile new file mode 100644 index 0000000..5f26c29 --- /dev/null +++ b/lib/stm32f1/Makefile @@ -0,0 +1,61 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +## + +LIBNAME = libopencm3_stm32 + +PREFIX ?= arm-none-eabi +#PREFIX ?= arm-elf +CC = $(PREFIX)-gcc +AR = $(PREFIX)-ar +CFLAGS = -Os -g -Wall -Wextra -I../../include -fno-common \ + -mcpu=cortex-m3 -mthumb -Wstrict-prototypes \ + -ffunction-sections -fdata-sections -MD +# ARFLAGS = rcsv +ARFLAGS = rcs +OBJS = vector.o rcc.o gpio.o usart.o adc.o spi.o flash.o nvic.o \ + rtc.o i2c.o dma.o systick.o exti.o scb.o ethernet.o \ + usb_f103.o usb.o usb_control.o usb_standard.o can.o \ + timer.o usb_f107.o + +VPATH += ../usb + +# Be silent per default, but 'make V=1' will show all compiler calls. +ifneq ($(V),1) +Q := @ +endif + +all: $(LIBNAME).a + +$(LIBNAME).a: $(OBJS) + @printf " AR $(subst $(shell pwd)/,,$(@))\n" + $(Q)$(AR) $(ARFLAGS) $@ $^ + +%.o: %.c + @printf " CC $(subst $(shell pwd)/,,$(@))\n" + $(Q)$(CC) $(CFLAGS) -o $@ -c $< + +clean: + @printf " CLEAN lib/stm32\n" + $(Q)rm -f *.o *.d + $(Q)rm -f $(LIBNAME).a + +.PHONY: clean + +-include $(OBJS:.o=.d) + diff --git a/lib/stm32f1/adc.c b/lib/stm32f1/adc.c new file mode 100644 index 0000000..058837c --- /dev/null +++ b/lib/stm32f1/adc.c @@ -0,0 +1,375 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Edward Cheeseman + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* + * Basic ADC handling API. + * + * Examples: + * rcc_peripheral_enable_clock(&RCC_APB2ENR, ADC1EN); + * rcc_peripheral_disable_clock(&RCC_APB2ENR, ADC1EN); + * rcc_peripheral_reset(&RCC_APB2RSTR, ADC1RST); + * rcc_peripheral_clear_reset(&RCC_APB2RSTR, ADC1RST); + * + * rcc_set_adc_clk(ADC_PRE_PLCK2_DIV2); + * adc_set_mode(ADC1, TODO); + * reg16 = adc_read(ADC1, ADC_CH_0); + */ + +#include + +void rcc_set_adc_clk(u32 prescaler) +{ + /* TODO */ + + /* FIXME: QUICK HACK to prevent compiler warnings. */ + prescaler = prescaler; +} + +void adc_set_mode(u32 block, /* TODO */ u8 mode) +{ + /* TODO */ + + /* FIXME: QUICK HACK to prevent compiler warnings. */ + block = block; + mode = mode; +} + +void adc_read(u32 block, u32 channel) +{ + /* TODO */ + + /* FIXME: QUICK HACK to prevent compiler warnings. */ + block = block; + channel = channel; +} + +void adc_enable_analog_watchdog_regular(u32 adc) +{ + ADC_CR1(adc) |= ADC_CR1_AWDEN; +} + +void adc_disable_analog_watchdog_regular(u32 adc) +{ + ADC_CR1(adc) &= ~ADC_CR1_AWDEN; +} + +void adc_enable_analog_watchdog_injected(u32 adc) +{ + ADC_CR1(adc) |= ADC_CR1_JAWDEN; +} + +void adc_disable_analog_watchdog_injected(u32 adc) +{ + ADC_CR1(adc) &= ~ADC_CR1_JAWDEN; +} + +void adc_enable_discontinous_mode_regular(u32 adc) +{ + ADC_CR1(adc) |= ADC_CR1_DISCEN; +} + +void adc_disable_discontinous_mode_regular(u32 adc) +{ + ADC_CR1(adc) &= ~ADC_CR1_DISCEN; +} + +void adc_enable_discontinous_mode_injected(u32 adc) +{ + ADC_CR1(adc) |= ADC_CR1_JDISCEN; +} + +void adc_disable_discontinous_mode_injected(u32 adc) +{ + ADC_CR1(adc) &= ~ADC_CR1_JDISCEN; +} + +void adc_enable_automatic_injected_group_conversion(u32 adc) +{ + ADC_CR1(adc) |= ADC_CR1_JAUTO; +} + +void adc_disable_automatic_injected_group_conversion(u32 adc) +{ + ADC_CR1(adc) &= ~ADC_CR1_JAUTO; +} + +void adc_enable_analog_watchdog_on_all_channels(u32 adc) +{ + ADC_CR1(adc) |= ADC_CR1_AWDSGL; +} + +void adc_enable_analog_watchdog_on_selected_channel(u32 adc, u8 channel) +{ + u32 reg32; + + reg32 = (ADC_CR1(adc) & 0xffffffe0); /* Clear bits [4:0]. */ + if (channel < 18) + reg32 |= channel; + ADC_CR1(adc) = reg32; + ADC_CR1(adc) &= ~ADC_CR1_AWDSGL; +} + +void adc_enable_scan_mode(u32 adc) +{ + ADC_CR1(adc) |= ADC_CR1_SCAN; +} + +void adc_disable_scan_mode(u32 adc) +{ + ADC_CR1(adc) &= ~ADC_CR1_SCAN; +} + +void adc_enable_jeoc_interrupt(u32 adc) +{ + ADC_CR1(adc) |= ADC_CR1_JEOCIE; +} + +void adc_disable_jeoc_interrupt(u32 adc) +{ + ADC_CR1(adc) &= ~ADC_CR1_JEOCIE; +} + +void adc_enable_awd_interrupt(u32 adc) +{ + ADC_CR1(adc) |= ADC_CR1_AWDIE; +} + +void adc_disable_awd_interrupt(u32 adc) +{ + ADC_CR1(adc) &= ~ADC_CR1_AWDIE; +} + +void adc_enable_eoc_interrupt(u32 adc) +{ + ADC_CR1(adc) |= ADC_CR1_EOCIE; +} + +void adc_disable_eoc_interrupt(u32 adc) +{ + ADC_CR1(adc) &= ~ADC_CR1_EOCIE; +} + +void adc_enable_temperature_sensor(u32 adc) +{ + ADC_CR2(adc) |= ADC_CR2_TSVREFE; +} + +void adc_disable_temperature_sensor(u32 adc) +{ + ADC_CR2(adc) &= ~ADC_CR2_TSVREFE; +} + +void adc_start_conversion_regular(u32 adc) +{ + /* start conversion on regular channels */ + ADC_CR2(adc) |= ADC_CR2_SWSTART; + + /* wait til the ADC starts the conversion */ + while (ADC_CR2(adc) & ADC_CR2_SWSTART); +} + +void adc_start_conversion_injected(u32 adc) +{ + /* start conversion on injected channels */ + ADC_CR2(adc) |= ADC_CR2_JSWSTART; + + /* wait til the ADC starts the conversion */ + while (ADC_CR2(adc) & ADC_CR2_JSWSTART); +} + +void adc_enable_external_trigger_regular(u32 adc, u8 trigger) +{ + u32 reg32; + + reg32 = (ADC_CR2(adc) & 0xfff1ffff); /* Clear bits [19:17]. */ + if (trigger < 8) + reg32 |= (trigger << ADC_CR2_EXTSEL_LSB); + ADC_CR2(adc) = reg32; + ADC_CR2(adc) |= ADC_CR2_EXTTRIG; +} + +void adc_disable_external_trigger_regular(u32 adc) +{ + ADC_CR2(adc) &= ~ADC_CR2_EXTTRIG; +} + +void adc_enable_external_trigger_injected(u32 adc, u8 trigger) +{ + u32 reg32; + + reg32 = (ADC_CR2(adc) & 0xffff8fff); /* Clear bits [12:14]. */ + if (trigger < 8) + reg32 |= (trigger << ADC_CR2_JEXTSEL_LSB); + ADC_CR2(adc) = reg32; + ADC_CR2(adc) |= ADC_CR2_JEXTTRIG; +} + +void adc_disable_external_trigger_injected(u32 adc) +{ + ADC_CR2(adc) &= ~ADC_CR2_JEXTTRIG; +} + +void adc_set_left_aligned(u32 adc) +{ + ADC_CR2(adc) |= ADC_CR2_ALIGN; +} + +void adc_set_right_aligned(u32 adc) +{ + ADC_CR2(adc) &= ~ADC_CR2_ALIGN; +} + +void adc_enable_dma(u32 adc) +{ + if ((adc == ADC1) | (adc==ADC3)) + ADC_CR2(adc) |= ADC_CR2_DMA; +} + +void adc_disable_dma(u32 adc) +{ + if ((adc == ADC1) | (adc==ADC3)) + ADC_CR2(adc) &= ~ADC_CR2_DMA; +} + +void adc_reset_calibration(u32 adc) +{ + ADC_CR2(adc) |= ADC_CR2_RSTCAL; + while (ADC_CR2(adc) & ADC_CR2_RSTCAL); +} + +void adc_calibration(u32 adc) +{ + ADC_CR2(adc) |= ADC_CR2_CAL; + while (ADC_CR2(adc) & ADC_CR2_CAL); +} + +void adc_set_continous_conversion_mode(u32 adc) +{ + ADC_CR2(adc) |= ADC_CR2_CONT; +} + +void adc_set_single_conversion_mode(u32 adc) +{ + ADC_CR2(adc) &= ~ADC_CR2_CONT; +} + +void adc_on(u32 adc) +{ + ADC_CR2(adc) |= ADC_CR2_ADON; +} + +void adc_off(u32 adc) +{ + ADC_CR2(adc) &= ~ADC_CR2_ADON; +} + +void adc_set_conversion_time(u32 adc, u8 channel, u8 time) +{ + u32 reg32; + + if (channel < 10) { + reg32 = ADC_SMPR2(adc); + reg32 &= ~(0b111 << (channel * 3)); + reg32 |= (time << (channel * 3)); + ADC_SMPR2(adc) = reg32; + } + else { + reg32 = ADC_SMPR1(adc); + reg32 &= ~(0b111 << ((channel-10) * 3)); + reg32 |= (time << ((channel-10) * 3)); + ADC_SMPR1(adc) = reg32; + } +} + +void adc_set_conversion_time_on_all_channels(u32 adc, u8 time) +{ + u32 reg32 = 0; + u8 i; + + for (i = 0; i <= 9; i++) { + reg32 |= (time << (i * 3)); + } + ADC_SMPR2(adc) = reg32; + + for (i = 10; i <= 17; i++) { + reg32 |= (time << ((i-10) * 3)); + } + ADC_SMPR1(adc) = reg32; +} + +void adc_set_watchdog_high_threshold(u32 adc, u16 threshold) +{ + u32 reg32 = 0; + + reg32 = (u32)threshold; + reg32 &= ~0xfffff000; /* clear all bits above 11 */ + ADC_HTR(adc) = reg32; +} + +void adc_set_watchdog_low_threshold(u32 adc, u16 threshold) +{ + u32 reg32 = 0; + + reg32 = (u32)threshold; + reg32 &= ~0xfffff000; /* clear all bits above 11 */ + ADC_LTR(adc) = reg32; +} + +void adc_set_regular_sequence(u32 adc, u8 length, u8 channel[]) +{ + u32 reg32_1 = 0; + u32 reg32_2 = 0; + u32 reg32_3 = 0; + u8 i = 0; + + /* maximum sequence length is 16 channels */ + if (length > 16) + return; + + for (i=1; i<=length; i++) { + if (i <= 6) + reg32_3 |= (channel[i-1] << ((i-1) * 5)); + if ((i > 6) & (i <= 12)) + reg32_2 |= (channel[i-1] << ((i-6-1) * 5)); + if ((i > 12) & (i <= 16)) + reg32_1 |= (channel[i-1] << ((i-12-1) * 5)); + } + reg32_1 |= ((length -1) << ADC_SQR1_L_LSB); + + ADC_SQR1(adc) = reg32_1; + ADC_SQR2(adc) = reg32_2; + ADC_SQR3(adc) = reg32_3; +} + +void adc_set_injected_sequence(u32 adc, u8 length, u8 channel[]) +{ + u32 reg32 = 0; + u8 i = 0; + + /* maximum sequence length is 4 channels */ + if (length > 4) + return; + + for (i = 1; i <= length; i++) { + reg32 |= (channel[i-1] << ((i-1) * 5)); + } + reg32 |= ((length-1) << ADC_JSQR_JL_LSB); + + ADC_JSQR(adc) = reg32; +} diff --git a/lib/stm32f1/can.c b/lib/stm32f1/can.c new file mode 100644 index 0000000..e571f8a --- /dev/null +++ b/lib/stm32f1/can.c @@ -0,0 +1,303 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Piotr Esden-Tempski + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include + +void can_reset(u32 canport) +{ + if (canport == CAN1) { + rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_CAN1RST); + rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_CAN1RST); + } else { + rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_CAN2RST); + rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_CAN2RST); + } +} + +int can_init(u32 canport, bool ttcm, bool abom, bool awum, bool nart, + bool rflm, bool txfp, u32 sjw, u32 ts1, u32 ts2, u32 brp) +{ + u32 wait_ack = 0x00000000; + u32 can_msr_inak_timeout = 0x0000FFFF; + int ret = 0; + + /* Exit from sleep mode. */ + CAN_MCR(canport) &= ~CAN_MCR_SLEEP; + + /* Request initialization "enter". */ + CAN_MCR(canport) |= CAN_MCR_INRQ; + + /* Wait for acknowledge. */ + while ((wait_ack != can_msr_inak_timeout) && + ((CAN_MSR(canport) & CAN_MSR_INAK) != CAN_MSR_INAK)) { + wait_ack++; + } + + /* Check the acknowledge. */ + if ((CAN_MSR(canport) & CAN_MSR_INAK) != CAN_MSR_INAK) + return 1; + + /* Set the automatic bus-off management. */ + if (ttcm) + CAN_MCR(canport) |= CAN_MCR_TTCM; + else + CAN_MCR(canport) &= ~CAN_MCR_TTCM; + + if (abom) + CAN_MCR(canport) |= CAN_MCR_ABOM; + else + CAN_MCR(canport) &= ~CAN_MCR_ABOM; + + if (awum) + CAN_MCR(canport) |= CAN_MCR_AWUM; + else + CAN_MCR(canport) &= ~CAN_MCR_AWUM; + + if (nart) + CAN_MCR(canport) |= CAN_MCR_NART; + else + CAN_MCR(canport) &= ~CAN_MCR_NART; + + if (rflm) + CAN_MCR(canport) |= CAN_MCR_RFLM; + else + CAN_MCR(canport) &= ~CAN_MCR_RFLM; + + if (txfp) + CAN_MCR(canport) |= CAN_MCR_TXFP; + else + CAN_MCR(canport) &= ~CAN_MCR_TXFP; + + /* Set bit timings. */ + CAN_BTR(canport) = sjw | ts2 | ts1 | + (u32)(CAN_BTR_BRP_MASK & (brp - 1)); + + /* Request initialization "leave". */ + CAN_MCR(canport) &= ~CAN_MCR_INRQ; + + /* Wait for acknowledge. */ + wait_ack = 0x00000000; + while ((wait_ack != can_msr_inak_timeout) && + ((CAN_MSR(canport) & CAN_MSR_INAK) == CAN_MSR_INAK)) { + wait_ack++; + } + + if ((CAN_MSR(canport) & CAN_MSR_INAK) == CAN_MSR_INAK) + ret = 1; + + return ret; +} + +void can_filter_init(u32 canport, u32 nr, bool scale_32bit, bool id_list_mode, + u32 fr1, u32 fr2, u32 fifo, bool enable) +{ + u32 filter_select_bit = 0x00000001 << nr; + + /* Request initialization "enter". */ + CAN_FMR(canport) |= CAN_FMR_FINIT; + + /* Deactivate the filter. */ + CAN_FA1R(canport) &= ~filter_select_bit; + + if (scale_32bit) { + /* Set 32-bit scale for the filter. */ + CAN_FS1R(canport) |= filter_select_bit; + } else { + /* Set 16-bit scale for the filter. */ + CAN_FS1R(canport) &= ~filter_select_bit; + } + + if (id_list_mode) { + /* Set filter mode to ID list mode. */ + CAN_FM1R(canport) |= filter_select_bit; + } else { + /* Set filter mode to id/mask mode. */ + CAN_FM1R(canport) &= ~filter_select_bit; + } + + /* Set the first filter register. */ + CAN_FiR1(canport, nr) = fr1; + + /* Set the second filter register. */ + CAN_FiR2(canport, nr) = fr2; + + /* Select FIFO0 or FIFO1 as filter assignement. */ + if (fifo) + CAN_FFA1R(canport) |= filter_select_bit; /* FIFO1 */ + else + CAN_FFA1R(canport) &= ~filter_select_bit; /* FIFO0 */ + + if (enable) + CAN_FA1R(canport) |= filter_select_bit; /* Activate filter. */ + + /* Request initialization "leave". */ + CAN_FMR(canport) &= ~CAN_FMR_FINIT; +} + +void can_filter_id_mask_16bit_init(u32 canport, u32 nr, u16 id1, u16 mask1, + u16 id2, u16 mask2, u32 fifo, bool enable) +{ + can_filter_init(canport, nr, false, false, + ((u32)id1 << 16) | (u32)mask1, + ((u32)id2 << 16) | (u32)mask2, fifo, enable); +} + +void can_filter_id_mask_32bit_init(u32 canport, u32 nr, u32 id, u32 mask, + u32 fifo, bool enable) +{ + can_filter_init(canport, nr, true, false, id, mask, fifo, enable); +} + +void can_filter_id_list_16bit_init(u32 canport, u32 nr, u16 id1, u16 id2, + u16 id3, u16 id4, u32 fifo, bool enable) +{ + can_filter_init(canport, nr, false, true, + ((u32)id1 << 16) | (u32)id2, + ((u32)id3 << 16) | (u32)id4, fifo, enable); +} + +void can_filter_id_list_32bit_init(u32 canport, u32 nr, u32 id1, u32 id2, + u32 fifo, bool enable) +{ + can_filter_init(canport, nr, true, true, id1, id2, fifo, enable); +} + +void can_enable_irq(u32 canport, u32 irq) +{ + CAN_IER(canport) |= irq; +} + +void can_disable_irq(u32 canport, u32 irq) +{ + CAN_IER(canport) &= ~irq; +} + +int can_transmit(u32 canport, u32 id, bool ext, bool rtr, u8 length, u8 *data) +{ + int ret = 0, i; + u32 mailbox = 0; + + if ((CAN_TSR(canport) & CAN_TSR_TME0) == CAN_TSR_TME0) { + ret = 0; + mailbox = CAN_MBOX0; + } else if ((CAN_TSR(canport) & CAN_TSR_TME1) == CAN_TSR_TME1) { + ret = 1; + mailbox = CAN_MBOX1; + } else if ((CAN_TSR(canport) & CAN_TSR_TME2) == CAN_TSR_TME2) { + ret = 2; + mailbox = CAN_MBOX2; + } else { + ret = -1; + } + + /* Check if we have an empty mailbox. */ + if (ret == -1) + return ret; + + /* Clear stale register bits */ + CAN_TIxR(canport, mailbox) = 0; + if (ext) { + /* Set extended ID. */ + CAN_TIxR(canport, mailbox) |= id << CAN_TIxR_EXID_SHIFT; + /* Set extended ID indicator bit. */ + CAN_TIxR(canport, mailbox) |= CAN_TIxR_IDE; + } else { + /* Set standard ID. */ + CAN_TIxR(canport, mailbox) |= id << CAN_TIxR_STID_SHIFT; + } + + /* Set/clear remote transmission request bit. */ + if (rtr) + CAN_TIxR(canport, mailbox) |= CAN_TIxR_RTR; /* Set */ + + /* Set the DLC. */ + CAN_TDTxR(canport, mailbox) &= 0xFFFFFFFF0; + CAN_TDTxR(canport, mailbox) |= length & CAN_TDTxR_DLC_MASK; + + /* Set the data. */ + CAN_TDLxR(canport, mailbox) = 0; + CAN_TDHxR(canport, mailbox) = 0; + for (i = 0; (i < 4) && (i < length); i++) + CAN_TDLxR(canport, mailbox) |= (u32)data[i] << (8 * i); + for (i = 4; (i < 8) && (i < length); i++) + CAN_TDHxR(canport, mailbox) |= (u32)data[i] << (8 * (i - 4)); + + /* Request transmission. */ + CAN_TIxR(canport, mailbox) |= CAN_TIxR_TXRQ; + + return ret; +} + +void can_fifo_release(u32 canport, u8 fifo) +{ + if (fifo == 0) + CAN_RF0R(canport) |= CAN_RF1R_RFOM1; + else + CAN_RF1R(canport) |= CAN_RF1R_RFOM1; +} + +void can_receive(u32 canport, u8 fifo, bool release, u32 *id, bool *ext, + bool *rtr, u32 *fmi, u8 *length, u8 *data) +{ + u32 fifo_id = 0; + int i; + + if (fifo == 0) + fifo_id = CAN_FIFO0; + else + fifo_id = CAN_FIFO1; + + /* Get type of CAN ID and CAN ID. */ + if (CAN_RIxR(canport, fifo_id) & CAN_RIxR_IDE) { + *ext = true; + /* Get extended CAN ID. */ + *id = ((CAN_RIxR(canport, fifo_id) & CAN_RIxR_EXID_MASK) >> + CAN_RIxR_EXID_SHIFT); + } else { + *ext = false; + /* Get standard CAN ID. */ + *id = ((CAN_RIxR(canport, fifo_id) & CAN_RIxR_STID_MASK) >> + CAN_RIxR_STID_SHIFT); + } + + /* Get request transmit flag. */ + if (CAN_RIxR(canport, fifo_id) & CAN_RIxR_RTR) + *rtr = true; + else + *rtr = false; + + /* Get filter match ID. */ + *fmi = ((CAN_RDTxR(canport, fifo_id) & CAN_RDTxR_FMI_MASK) > + CAN_RDTxR_FMI_SHIFT); + + /* Get data length. */ + *length = CAN_RDTxR(canport, fifo_id) & CAN_RDTxR_DLC_MASK; + + /* Get data. */ + for (i = 0; (i < 4) && (i < *length); i++) + data[i] = (CAN_RDLxR(canport, fifo_id) >> (8 * i)) & 0xFF; + + for (i = 4; (i < 8) && (i < *length); i++) + data[i] = (CAN_RDHxR(canport, fifo_id) >> (8 * (i - 4))) & 0xFF; + + /* Release the FIFO. */ + if (release) + can_fifo_release(CAN1, 0); +} diff --git a/lib/stm32f1/dma.c b/lib/stm32f1/dma.c new file mode 100644 index 0000000..8feb2c9 --- /dev/null +++ b/lib/stm32f1/dma.c @@ -0,0 +1,543 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include + +void dma_enable_mem2mem_mode(u32 dma, u8 channel) +{ + switch (channel) + { + case 1: + DMA_CCR1(dma) |= DMA_CCR1_MEM2MEM; + DMA_CCR1(dma) &= ~DMA_CCR1_CIRC; + case 2: + DMA_CCR2(dma) |= DMA_CCR2_MEM2MEM; + DMA_CCR2(dma) &= ~DMA_CCR2_CIRC; + case 3: + DMA_CCR3(dma) |= DMA_CCR3_MEM2MEM; + DMA_CCR3(dma) &= ~DMA_CCR3_CIRC; + case 4: + DMA_CCR4(dma) |= DMA_CCR4_MEM2MEM; + DMA_CCR4(dma) &= ~DMA_CCR4_CIRC; + case 5: + DMA_CCR5(dma) |= DMA_CCR5_MEM2MEM; + DMA_CCR5(dma) &= ~DMA_CCR5_CIRC; + case 6: + if (dma == DMA1) { + DMA_CCR6(dma) |= DMA_CCR6_MEM2MEM; + DMA_CCR6(dma) &= ~DMA_CCR6_CIRC; + } + case 7: + if (dma == DMA1) { + DMA_CCR7(dma) |= DMA_CCR7_MEM2MEM; + DMA_CCR7(dma) &= ~DMA_CCR7_CIRC; + } + } +} + + + + +void dma_set_priority(u32 dma, u8 channel, u8 prio) +{ + /* parameter check */ + if (prio > 3) + return; + + switch (channel) + { + case 1: + DMA_CCR1(dma) &= ~(0x3 << DMA_CCR1_PL_LSB); + DMA_CCR1(dma) |= (prio << DMA_CCR1_PL_LSB); + case 2: + DMA_CCR2(dma) &= ~(0x3 << DMA_CCR2_PL_LSB); + DMA_CCR2(dma) |= (prio << DMA_CCR2_PL_LSB); + case 3: + DMA_CCR3(dma) &= ~(0x3 << DMA_CCR3_PL_LSB); + DMA_CCR3(dma) |= (prio << DMA_CCR3_PL_LSB); + case 4: + DMA_CCR4(dma) &= ~(0x3 << DMA_CCR4_PL_LSB); + DMA_CCR4(dma) |= (prio << DMA_CCR4_PL_LSB); + case 5: + DMA_CCR5(dma) &= ~(0x3 << DMA_CCR5_PL_LSB); + DMA_CCR5(dma) |= (prio << DMA_CCR5_PL_LSB); + case 6: + if (dma == DMA1) { + DMA_CCR6(dma) &= ~(0x3 << DMA_CCR6_PL_LSB); + DMA_CCR6(dma) |= (prio << DMA_CCR6_PL_LSB); + } + case 7: + if (dma == DMA1) { + DMA_CCR7(dma) &= ~(0x3 << DMA_CCR7_PL_LSB); + DMA_CCR7(dma) |= (prio << DMA_CCR7_PL_LSB); + } + } +} + +void dma_set_memory_size(u32 dma, u8 channel, u8 mem_size) +{ + /* parameter check */ + if (mem_size > 2) + return; + + switch (channel) + { + case 1: + DMA_CCR1(dma) &= ~(0x3 << DMA_CCR1_MSIZE_LSB); + DMA_CCR1(dma) |= (mem_size << DMA_CCR1_MSIZE_LSB); + case 2: + DMA_CCR2(dma) &= ~(0x3 << DMA_CCR2_MSIZE_LSB); + DMA_CCR2(dma) |= (mem_size << DMA_CCR2_MSIZE_LSB); + case 3: + DMA_CCR3(dma) &= ~(0x3 << DMA_CCR3_MSIZE_LSB); + DMA_CCR3(dma) |= (mem_size << DMA_CCR3_MSIZE_LSB); + case 4: + DMA_CCR4(dma) &= ~(0x3 << DMA_CCR4_MSIZE_LSB); + DMA_CCR4(dma) |= (mem_size << DMA_CCR4_MSIZE_LSB); + case 5: + DMA_CCR5(dma) &= ~(0x3 << DMA_CCR5_MSIZE_LSB); + DMA_CCR5(dma) |= (mem_size << DMA_CCR5_MSIZE_LSB); + case 6: + if (dma == DMA1) { + DMA_CCR6(dma) &= ~(0x3 << DMA_CCR6_MSIZE_LSB); + DMA_CCR6(dma) |= (mem_size << DMA_CCR6_MSIZE_LSB); + } + case 7: + if (dma == DMA1) { + DMA_CCR7(dma) &= ~(0x3 << DMA_CCR7_MSIZE_LSB); + DMA_CCR7(dma) |= (mem_size << DMA_CCR7_MSIZE_LSB); + } + } +} + + + +void dma_set_peripheral_size(u32 dma, u8 channel, u8 peripheral_size) +{ + /* parameter check */ + if (peripheral_size > 2) + return; + + switch (channel) + { + case 1: + DMA_CCR1(dma) &= ~(0x3 << DMA_CCR1_PSIZE_LSB); + DMA_CCR1(dma) |= (peripheral_size << DMA_CCR1_PSIZE_LSB); + case 2: + DMA_CCR2(dma) &= ~(0x3 << DMA_CCR2_PSIZE_LSB); + DMA_CCR2(dma) |= (peripheral_size << DMA_CCR2_PSIZE_LSB); + case 3: + DMA_CCR3(dma) &= ~(0x3 << DMA_CCR3_PSIZE_LSB); + DMA_CCR3(dma) |= (peripheral_size << DMA_CCR3_PSIZE_LSB); + case 4: + DMA_CCR4(dma) &= ~(0x3 << DMA_CCR4_PSIZE_LSB); + DMA_CCR4(dma) |= (peripheral_size << DMA_CCR4_PSIZE_LSB); + case 5: + DMA_CCR5(dma) &= ~(0x3 << DMA_CCR5_PSIZE_LSB); + DMA_CCR5(dma) |= (peripheral_size << DMA_CCR5_PSIZE_LSB); + case 6: + if (dma == DMA1) { + DMA_CCR6(dma) &= ~(0x3 << DMA_CCR6_PSIZE_LSB); + DMA_CCR6(dma) |= (peripheral_size << DMA_CCR6_PSIZE_LSB); + } + case 7: + if (dma == DMA1) { + DMA_CCR7(dma) &= ~(0x3 << DMA_CCR7_PSIZE_LSB); + DMA_CCR7(dma) |= (peripheral_size << DMA_CCR7_PSIZE_LSB); + } + } +} + + +void dma_enable_memory_increment_mode(u32 dma, u8 channel) +{ + switch (channel) + { + case 1: + DMA_CCR1(dma) |= DMA_CCR1_MINC; + case 2: + DMA_CCR2(dma) |= DMA_CCR2_MINC; + case 3: + DMA_CCR3(dma) |= DMA_CCR3_MINC; + case 4: + DMA_CCR4(dma) |= DMA_CCR4_MINC; + case 5: + DMA_CCR5(dma) |= DMA_CCR5_MINC; + case 6: + if (dma == DMA1) + DMA_CCR6(dma) |= DMA_CCR6_MINC; + case 7: + if (dma == DMA1) + DMA_CCR7(dma) |= DMA_CCR7_MINC; + } +} + +void dma_enable_peripheral_increment_mode(u32 dma, u8 channel) +{ + switch (channel) + { + case 1: + DMA_CCR1(dma) |= DMA_CCR1_PINC; + case 2: + DMA_CCR2(dma) |= DMA_CCR2_PINC; + case 3: + DMA_CCR3(dma) |= DMA_CCR3_PINC; + case 4: + DMA_CCR4(dma) |= DMA_CCR4_PINC; + case 5: + DMA_CCR5(dma) |= DMA_CCR5_PINC; + case 6: + if (dma == DMA1) + DMA_CCR6(dma) |= DMA_CCR6_PINC; + case 7: + if (dma == DMA1) + DMA_CCR7(dma) |= DMA_CCR7_PINC; + } +} + +void dma_enable_circular_mode(u32 dma, u8 channel) +{ + switch (channel) + { + case 1: + DMA_CCR1(dma) |= DMA_CCR1_CIRC; + DMA_CCR1(dma) &= ~DMA_CCR1_MEM2MEM; + case 2: + DMA_CCR2(dma) |= DMA_CCR2_CIRC; + DMA_CCR2(dma) &= ~DMA_CCR2_MEM2MEM; + case 3: + DMA_CCR3(dma) |= DMA_CCR3_CIRC; + DMA_CCR3(dma) &= ~DMA_CCR3_MEM2MEM; + case 4: + DMA_CCR4(dma) |= DMA_CCR4_CIRC; + DMA_CCR4(dma) &= ~DMA_CCR4_MEM2MEM; + case 5: + DMA_CCR5(dma) |= DMA_CCR5_CIRC; + DMA_CCR5(dma) &= ~DMA_CCR5_MEM2MEM; + case 6: + if (dma == DMA1) { + DMA_CCR6(dma) |= DMA_CCR6_CIRC; + DMA_CCR6(dma) &= ~DMA_CCR6_MEM2MEM; + } + case 7: + if (dma == DMA1) { + DMA_CCR7(dma) |= DMA_CCR7_CIRC; + DMA_CCR7(dma) &= ~DMA_CCR7_MEM2MEM; + } + } +} + +void dma_set_read_from_peripheral(u32 dma, u8 channel) +{ + switch (channel) + { + case 1: + DMA_CCR1(dma) &= ~DMA_CCR1_DIR; + case 2: + DMA_CCR2(dma) &= ~DMA_CCR2_DIR; + case 3: + DMA_CCR3(dma) &= ~DMA_CCR3_DIR; + case 4: + DMA_CCR4(dma) &= ~DMA_CCR4_DIR; + case 5: + DMA_CCR5(dma) &= ~DMA_CCR5_DIR; + case 6: + if (dma == DMA1) + DMA_CCR6(dma) &= ~DMA_CCR6_DIR; + case 7: + if (dma == DMA1) + DMA_CCR7(dma) &= ~DMA_CCR7_DIR; + } +} + +void dma_set_read_from_memory(u32 dma, u8 channel) +{ + switch (channel) + { + case 1: + DMA_CCR1(dma) |= DMA_CCR1_DIR; + case 2: + DMA_CCR2(dma) |= DMA_CCR2_DIR; + case 3: + DMA_CCR3(dma) |= DMA_CCR3_DIR; + case 4: + DMA_CCR4(dma) |= DMA_CCR4_DIR; + case 5: + DMA_CCR5(dma) |= DMA_CCR5_DIR; + case 6: + if (dma == DMA1) + DMA_CCR6(dma) |= DMA_CCR6_DIR; + case 7: + if (dma == DMA1) + DMA_CCR7(dma) |= DMA_CCR7_DIR; + } +} + +void dma_enable_transfer_error_interrupt(u32 dma, u8 channel) +{ + switch (channel) + { + case 1: + DMA_CCR1(dma) |= DMA_CCR1_TEIE; + case 2: + DMA_CCR2(dma) |= DMA_CCR2_TEIE; + case 3: + DMA_CCR3(dma) |= DMA_CCR3_TEIE; + case 4: + DMA_CCR4(dma) |= DMA_CCR4_TEIE; + case 5: + DMA_CCR5(dma) |= DMA_CCR5_TEIE; + case 6: + if (dma == DMA1) + DMA_CCR6(dma) |= DMA_CCR6_TEIE; + case 7: + if (dma == DMA1) + DMA_CCR7(dma) |= DMA_CCR7_TEIE; + } +} + +void dma_disable_transfer_error_interrupt(u32 dma, u8 channel) +{ + switch (channel) + { + case 1: + DMA_CCR1(dma) &= ~DMA_CCR1_TEIE; + case 2: + DMA_CCR2(dma) &= ~DMA_CCR2_TEIE; + case 3: + DMA_CCR3(dma) &= ~DMA_CCR3_TEIE; + case 4: + DMA_CCR4(dma) &= ~DMA_CCR4_TEIE; + case 5: + DMA_CCR5(dma) &= ~DMA_CCR5_TEIE; + case 6: + if (dma == DMA1) + DMA_CCR6(dma) &= ~DMA_CCR6_TEIE; + case 7: + if (dma == DMA1) + DMA_CCR7(dma) &= ~DMA_CCR7_TEIE; + } +} + +void dma_enable_half_transfer_interrupt(u32 dma, u8 channel) +{ + switch (channel) + { + case 1: + DMA_CCR1(dma) |= DMA_CCR1_HTIE; + case 2: + DMA_CCR2(dma) |= DMA_CCR2_HTIE; + case 3: + DMA_CCR3(dma) |= DMA_CCR3_HTIE; + case 4: + DMA_CCR4(dma) |= DMA_CCR4_HTIE; + case 5: + DMA_CCR5(dma) |= DMA_CCR5_HTIE; + case 6: + if (dma == DMA1) + DMA_CCR6(dma) |= DMA_CCR6_HTIE; + case 7: + if (dma == DMA1) + DMA_CCR7(dma) |= DMA_CCR7_HTIE; + } +} + +void dma_disable_half_transfer_interrupt(u32 dma, u8 channel) +{ + switch (channel) + { + case 1: + DMA_CCR1(dma) &= ~DMA_CCR1_HTIE; + case 2: + DMA_CCR2(dma) &= ~DMA_CCR2_HTIE; + case 3: + DMA_CCR3(dma) &= ~DMA_CCR3_HTIE; + case 4: + DMA_CCR4(dma) &= ~DMA_CCR4_HTIE; + case 5: + DMA_CCR5(dma) &= ~DMA_CCR5_HTIE; + case 6: + if (dma == DMA1) + DMA_CCR6(dma) &= ~DMA_CCR6_HTIE; + case 7: + if (dma == DMA1) + DMA_CCR7(dma) &= ~DMA_CCR7_HTIE; + } +} + +void dma_enable_transfer_complete_interrupt(u32 dma, u8 channel) +{ + switch (channel) + { + case 1: + DMA_CCR1(dma) |= DMA_CCR1_TCIE; + case 2: + DMA_CCR2(dma) |= DMA_CCR2_TCIE; + case 3: + DMA_CCR3(dma) |= DMA_CCR3_TCIE; + case 4: + DMA_CCR4(dma) |= DMA_CCR4_TCIE; + case 5: + DMA_CCR5(dma) |= DMA_CCR5_TCIE; + case 6: + if (dma == DMA1) + DMA_CCR6(dma) |= DMA_CCR6_TCIE; + case 7: + if (dma == DMA1) + DMA_CCR7(dma) |= DMA_CCR7_TCIE; + } +} + +void dma_disable_transfer_complete_interrupt(u32 dma, u8 channel) +{ + switch (channel) + { + case 1: + DMA_CCR1(dma) &= ~DMA_CCR1_TCIE; + case 2: + DMA_CCR2(dma) &= ~DMA_CCR2_TCIE; + case 3: + DMA_CCR3(dma) &= ~DMA_CCR3_TCIE; + case 4: + DMA_CCR4(dma) &= ~DMA_CCR4_TCIE; + case 5: + DMA_CCR5(dma) &= ~DMA_CCR5_TCIE; + case 6: + if (dma == DMA1) + DMA_CCR6(dma) &= ~DMA_CCR6_TCIE; + case 7: + if (dma == DMA1) + DMA_CCR7(dma) &= ~DMA_CCR7_TCIE; + } +} + +void dma_enable_channel(u32 dma, u8 channel) +{ + switch (channel) + { + case 1: + DMA_CCR1(dma) |= DMA_CCR1_EN; + case 2: + DMA_CCR2(dma) |= DMA_CCR2_EN; + case 3: + DMA_CCR3(dma) |= DMA_CCR3_EN; + case 4: + DMA_CCR4(dma) |= DMA_CCR4_EN; + case 5: + DMA_CCR5(dma) |= DMA_CCR5_EN; + case 6: + if (dma == DMA1) + DMA_CCR6(dma) |= DMA_CCR6_EN; + case 7: + if (dma == DMA1) + DMA_CCR7(dma) |= DMA_CCR7_EN; + } +} + +void dma_disable_channel(u32 dma, u8 channel) +{ + switch (channel) + { + case 1: + DMA_CCR1(dma) &= ~DMA_CCR1_EN; + case 2: + DMA_CCR2(dma) &= ~DMA_CCR2_EN; + case 3: + DMA_CCR3(dma) &= ~DMA_CCR3_EN; + case 4: + DMA_CCR4(dma) &= ~DMA_CCR4_EN; + case 5: + DMA_CCR5(dma) &= ~DMA_CCR5_EN; + case 6: + if (dma == DMA1) + DMA_CCR6(dma) &= ~DMA_CCR6_EN; + case 7: + if (dma == DMA1) + DMA_CCR7(dma) &= ~DMA_CCR7_EN; + } +} + +void dma_set_peripheral_address(u32 dma, u8 channel, u32 address) +{ + switch (channel) + { + case 1: + DMA_CPAR1(dma) = (u32)address; + case 2: + DMA_CPAR2(dma) = (u32)address; + case 3: + DMA_CPAR3(dma) = (u32)address; + case 4: + DMA_CPAR4(dma) = (u32)address; + case 5: + DMA_CPAR5(dma) = (u32)address; + case 6: + if (dma == DMA1) + DMA_CPAR6(dma) = (u32)address; + case 7: + if (dma == DMA1) + DMA_CPAR7(dma) = (u32)address; + } +} + +void dma_set_memory_address(u32 dma, u8 channel, u32 address) +{ + switch (channel) + { + case 1: + DMA_CMAR1(dma) = (u32)address; + case 2: + DMA_CMAR2(dma) = (u32)address; + case 3: + DMA_CMAR3(dma) = (u32)address; + case 4: + DMA_CMAR4(dma) = (u32)address; + case 5: + DMA_CMAR5(dma) = (u32)address; + case 6: + if (dma == DMA1) + DMA_CMAR6(dma) = (u32)address; + case 7: + if (dma == DMA1) + DMA_CMAR7(dma) = (u32)address; + } +} + +void dma_set_number_of_data(u32 dma, u8 channel, u16 number) +{ + switch (channel) + { + case 1: + DMA_CNDTR1(dma) = number; + case 2: + DMA_CNDTR2(dma) = number; + case 3: + DMA_CNDTR3(dma) = number; + case 4: + DMA_CNDTR4(dma) = number; + case 5: + DMA_CNDTR5(dma) = number; + case 6: + if (dma == DMA1) + DMA_CNDTR6(dma) = number; + case 7: + if (dma == DMA1) + DMA_CNDTR7(dma) = number; + } +} diff --git a/lib/stm32f1/ethernet.c b/lib/stm32f1/ethernet.c new file mode 100644 index 0000000..4a4d080 --- /dev/null +++ b/lib/stm32f1/ethernet.c @@ -0,0 +1,53 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Gareth McMullin + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include + +void eth_smi_write(u8 phy, u8 reg, u16 data) +{ + /* Set PHY and register addresses for write access. */ + ETH_MACMIIAR &= ~(ETH_MACMIIAR_MR | ETH_MACMIIAR_PA); + ETH_MACMIIAR |= (phy << 11) | (reg << 6) | ETH_MACMIIAR_MW; + + /* Set register value. */ + ETH_MACMIIDR = data; + + /* Begin transaction. */ + ETH_MACMIIAR |= ETH_MACMIIAR_MB; + + /* Wait for not busy. */ + while (ETH_MACMIIAR & ETH_MACMIIAR_MB); +} + +u16 eth_smi_read(u8 phy, u8 reg) +{ + /* Set PHY and register addresses for write access. */ + ETH_MACMIIAR &= ~(ETH_MACMIIAR_MR | ETH_MACMIIAR_PA | + ETH_MACMIIAR_MW); + ETH_MACMIIAR |= (phy << 11) | (reg << 6); + + /* Begin transaction. */ + ETH_MACMIIAR |= ETH_MACMIIAR_MB; + + /* Wait for not busy. */ + while (ETH_MACMIIAR & ETH_MACMIIAR_MB); + + /* Set register value. */ + return (u16)(ETH_MACMIIDR); +} diff --git a/lib/stm32f1/exti.c b/lib/stm32f1/exti.c new file mode 100644 index 0000000..de037e7 --- /dev/null +++ b/lib/stm32f1/exti.c @@ -0,0 +1,145 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Mark Butler + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include + +void exti_set_trigger(u32 extis, exti_trigger_type trig) +{ + switch (trig) { + case EXTI_TRIGGER_RISING: + EXTI_RTSR |= extis; + EXTI_FTSR &= ~extis; + break; + case EXTI_TRIGGER_FALLING: + EXTI_RTSR &= ~extis; + EXTI_FTSR |= extis; + break; + case EXTI_TRIGGER_BOTH: + EXTI_RTSR |= extis; + EXTI_FTSR |= extis; + break; + } +} + +void exti_enable_request(u32 extis) +{ + /* Enable interrupts. */ + EXTI_IMR |= extis; + + /* Enable events. */ + EXTI_EMR |= extis; +} + +void exti_disable_request(u32 extis) +{ + /* Disable interrupts. */ + EXTI_IMR &= ~extis; + + /* Disable events. */ + EXTI_EMR &= ~extis; +} + +/* + * Reset the interrupt request by writing a 1 to the corresponding + * pending bit register. + */ +void exti_reset_request(u32 extis) +{ + EXTI_PR |= extis; +} + +/* + * Remap an external interrupt line to the corresponding pin on the + * specified GPIO port. + * + * TODO: This could be rewritten in less lines of code. + */ +void exti_select_source(u32 exti, u32 gpioport) +{ + u8 shift, bits; + + shift = bits = 0; + + switch (exti) { + case EXTI0: + case EXTI4: + case EXTI8: + case EXTI12: + shift = 0; + break; + case EXTI1: + case EXTI5: + case EXTI9: + case EXTI13: + shift = 4; + break; + case EXTI2: + case EXTI6: + case EXTI10: + case EXTI14: + shift = 8; + break; + case EXTI3: + case EXTI7: + case EXTI11: + case EXTI15: + shift = 12; + break; + } + + switch (gpioport) { + case GPIOA: + bits = 0xf; + break; + case GPIOB: + bits = 0xe; + break; + case GPIOC: + bits = 0xd; + break; + case GPIOD: + bits = 0xc; + break; + case GPIOE: + bits = 0xb; + break; + case GPIOF: + bits = 0xa; + break; + case GPIOG: + bits = 0x9; + break; + } + + /* Ensure that only valid EXTI lines are used. */ + if (exti < EXTI4) { + AFIO_EXTICR1 &= ~(0x000F << shift); + AFIO_EXTICR1 |= (~bits << shift); + } else if (exti < EXTI8) { + AFIO_EXTICR2 &= ~(0x000F << shift); + AFIO_EXTICR2 |= (~bits << shift); + } else if (exti < EXTI12) { + AFIO_EXTICR3 &= ~(0x000F << shift); + AFIO_EXTICR3 |= (~bits << shift); + } else if (exti < EXTI16) { + AFIO_EXTICR4 &= ~(0x000F << shift); + AFIO_EXTICR4 |= (~bits << shift); + } +} diff --git a/lib/stm32f1/flash.c b/lib/stm32f1/flash.c new file mode 100644 index 0000000..98f7777 --- /dev/null +++ b/lib/stm32f1/flash.c @@ -0,0 +1,189 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * Copyright (C) 2010 Mark Butler + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include + +void flash_prefetch_buffer_enable(void) +{ + FLASH_ACR |= FLASH_PRFTBE; +} + +void flash_prefetch_buffer_disable(void) +{ + FLASH_ACR &= ~FLASH_PRFTBE; +} + +void flash_halfcycle_enable(void) +{ + FLASH_ACR |= FLASH_HLFCYA; +} + +void flash_halfcycle_disable(void) +{ + FLASH_ACR &= ~FLASH_HLFCYA; +} + +void flash_set_ws(u32 ws) +{ + u32 reg32; + + reg32 = FLASH_ACR; + reg32 &= ~((1 << 0) | (1 << 1) | (1 << 2)); + reg32 |= ws; + FLASH_ACR = reg32; +} + +void flash_unlock(void) +{ + /* Authorize the FPEC access. */ + FLASH_KEYR = FLASH_KEY1; + FLASH_KEYR = FLASH_KEY2; +} + +void flash_lock(void) +{ + FLASH_CR |= FLASH_LOCK; +} + +void flash_clear_pgerr_flag(void) +{ + FLASH_SR |= FLASH_PGERR; +} + +void flash_clear_eop_flag(void) +{ + FLASH_SR |= FLASH_EOP; +} + +void flash_clear_wrprterr_flag(void) +{ + FLASH_SR |= FLASH_WRPRTERR; +} + +void flash_clear_bsy_flag(void) +{ + FLASH_SR &= ~FLASH_BSY; +} + +void flash_clear_status_flags(void) +{ + flash_clear_pgerr_flag(); + flash_clear_eop_flag(); + flash_clear_wrprterr_flag(); + flash_clear_bsy_flag(); +} + +void flash_unlock_option_bytes(void) +{ + FLASH_OPTKEYR = FLASH_KEY1; + FLASH_OPTKEYR = FLASH_KEY2; +} + +void flash_wait_for_last_operation(void) +{ + while ((FLASH_SR & FLASH_BSY) == FLASH_BSY) + ; +} + +void flash_program_word(u32 address, u32 data) +{ + /* Ensure that all flash operations are complete. */ + flash_wait_for_last_operation(); + + /* Enable writes to flash. */ + FLASH_CR |= FLASH_PG; + + /* Program the first half of the word. */ + (*(volatile u16 *)address) = (u16)data; + + /* Wait for the write to complete. */ + flash_wait_for_last_operation(); + + /* Program the second half of the word. */ + (*(volatile u16 *)(address + 2)) = data >> 16; + + /* Wait for the write to complete. */ + flash_wait_for_last_operation(); + + /* Disable writes to flash. */ + FLASH_CR &= ~FLASH_PG; +} + +void flash_program_half_word(u32 address, u16 data) +{ + flash_wait_for_last_operation(); + + FLASH_CR |= FLASH_PG; + + (*(volatile u16 *)address) = data; + + flash_wait_for_last_operation(); + + FLASH_CR &= ~FLASH_PG; /* Disable the PG bit. */ +} + +void flash_erase_page(u32 page_address) +{ + flash_wait_for_last_operation(); + + FLASH_CR |= FLASH_PER; + FLASH_AR = page_address; + FLASH_CR |= FLASH_STRT; + + flash_wait_for_last_operation(); + FLASH_CR &= ~FLASH_PER; +} + +void flash_erase_all_pages(void) +{ + flash_wait_for_last_operation(); + + FLASH_CR |= FLASH_MER; /* Enable mass erase. */ + FLASH_CR |= FLASH_STRT; /* Trigger the erase. */ + + flash_wait_for_last_operation(); + FLASH_CR &= ~FLASH_MER; /* Disable mass erase. */ +} + +void flash_erase_option_bytes(void) +{ + flash_wait_for_last_operation(); + + if ((FLASH_CR & FLASH_OPTWRE) == 0) + flash_unlock_option_bytes(); + + FLASH_CR |= FLASH_OPTER; /* Enable option byte erase. */ + FLASH_CR |= FLASH_STRT; + flash_wait_for_last_operation(); + FLASH_CR &= ~FLASH_OPTER; /* Disable option byte erase. */ +} + +void flash_program_option_bytes(u32 address, u16 data) +{ + flash_wait_for_last_operation(); + + if ((FLASH_CR & FLASH_OPTWRE) == 0) + flash_unlock_option_bytes(); + + FLASH_CR |= FLASH_OPTPG; /* Enable option byte programming. */ + (*(volatile u16 *)address) = data; + flash_wait_for_last_operation(); + FLASH_CR &= ~FLASH_OPTPG; /* Disable option byte programming. */ +} diff --git a/lib/stm32f1/gpio.c b/lib/stm32f1/gpio.c new file mode 100644 index 0000000..52c0c66 --- /dev/null +++ b/lib/stm32f1/gpio.c @@ -0,0 +1,118 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* + * Basic GPIO handling API. + * + * Examples: + * gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_2_MHZ, + * GPIO_CNF_OUTPUT_PUSHPULL, GPIO12); + * gpio_set(GPIOB, GPIO4); + * gpio_clear(GPIOG, GPIO2 | GPIO9); + * gpio_get(GPIOC, GPIO1); + * gpio_toggle(GPIOA, GPIO7 | GPIO8); + * reg16 = gpio_port_read(GPIOD); + * gpio_port_write(GPIOF, 0xc8fe); + * + * TODO: + * - GPIO remapping support + */ + +#include + +void gpio_set_mode(u32 gpioport, u8 mode, u8 cnf, u16 gpios) +{ + u16 i, offset = 0; + u32 crl = 0, crh = 0, tmp32 = 0; + + /* + * We want to set the config only for the pins mentioned in gpios, + * but keeping the others, so read out the actual config first. + */ + crl = GPIO_CRL(gpioport); + crh = GPIO_CRH(gpioport); + + /* Iterate over all bits, use i as the bitnumber. */ + for (i = 0; i < 16; i++) { + /* Only set the config if the bit is set in gpios. */ + if (!((1 << i) & gpios)) + continue; + + /* Calculate bit offset. */ + offset = (i < 8) ? (i * 4) : ((i - 8) * 4); + + /* Use tmp32 to either modify crl or crh. */ + tmp32 = (i < 8) ? crl : crh; + + /* Modify bits are needed. */ + tmp32 &= ~(0b1111 << offset); /* Clear the bits first. */ + tmp32 |= (mode << offset) | (cnf << (offset + 2)); + + /* Write tmp32 into crl or crh, leave the other unchanged. */ + crl = (i < 8) ? tmp32 : crl; + crh = (i >= 8) ? tmp32 : crh; + } + + GPIO_CRL(gpioport) = crl; + GPIO_CRH(gpioport) = crh; +} + +void gpio_set(u32 gpioport, u16 gpios) +{ + GPIO_BSRR(gpioport) = gpios; +} + +void gpio_clear(u32 gpioport, u16 gpios) +{ + GPIO_BRR(gpioport) = gpios; +} + +u16 gpio_get(u32 gpioport, u16 gpios) +{ + return gpio_port_read(gpioport) & gpios; +} + +void gpio_toggle(u32 gpioport, u16 gpios) +{ + GPIO_ODR(gpioport) = GPIO_IDR(gpioport) ^ gpios; +} + +u16 gpio_port_read(u32 gpioport) +{ + return (u16)GPIO_IDR(gpioport); +} + +void gpio_port_write(u32 gpioport, u16 data) +{ + GPIO_ODR(gpioport) = data; +} + +void gpio_port_config_lock(u32 gpioport, u16 gpios) +{ + u32 reg32; + + /* Special "Lock Key Writing Sequence", see datasheet. */ + GPIO_LCKR(gpioport) = GPIO_LCKK | gpios; /* Set LCKK. */ + GPIO_LCKR(gpioport) = ~GPIO_LCKK & gpios; /* Clear LCKK. */ + GPIO_LCKR(gpioport) = GPIO_LCKK | gpios; /* Set LCKK. */ + reg32 = GPIO_LCKR(gpioport); /* Read LCKK. */ + reg32 = GPIO_LCKR(gpioport); /* Read LCKK again. */ + + /* If (reg32 & GPIO_LCKK) is true, the lock is now active. */ +} diff --git a/lib/stm32f1/i2c.c b/lib/stm32f1/i2c.c new file mode 100644 index 0000000..e1a3b84 --- /dev/null +++ b/lib/stm32f1/i2c.c @@ -0,0 +1,93 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include + +void i2c_peripheral_enable(u32 i2c) +{ + I2C_CR1(i2c) |= I2C_CR1_PE; +} + +void i2c_peripheral_disable(u32 i2c) +{ + I2C_CR1(i2c) &= ~I2C_CR1_PE; +} + +void i2c_send_start(u32 i2c) +{ + I2C_CR1(i2c) |= I2C_CR1_START; +} + +void i2c_send_stop(u32 i2c) +{ + I2C_CR1(i2c) |= I2C_CR1_STOP; +} + +void i2c_set_own_7bit_slave_address(u32 i2c, u8 slave) +{ + I2C_OAR1(i2c) = (u16)(slave << 1); + I2C_OAR1(i2c) &= ~I2C_OAR1_ADDMODE; + I2C_OAR1(i2c) |= (1 << 14); /* Datasheet: always keep 1 by software. */ +} + +void i2c_set_own_10bit_slave_address(u32 i2c, u16 slave) +{ + I2C_OAR1(i2c) = (u16)(I2C_OAR1_ADDMODE | slave); +} + +void i2c_set_fast_mode(u32 i2c) +{ + I2C_CCR(i2c) |= I2C_CCR_FS; +} + +void i2c_set_standard_mode(u32 i2c) +{ + I2C_CCR(i2c) &= ~I2C_CCR_FS; +} + +void i2c_set_clock_frequency(u32 i2c, u8 freq) +{ + u16 reg16; + reg16 = I2C_CR2(i2c) & 0xffc0; /* Clear bits [5:0]. */ + reg16 |= freq; + I2C_CR2(i2c) = reg16; +} + +void i2c_set_ccr(u32 i2c, u16 freq) +{ + u16 reg16; + reg16 = I2C_CCR(i2c) & 0xf000; /* Clear bits [11:0]. */ + reg16 |= freq; + I2C_CCR(i2c) = reg16; +} + +void i2c_set_trise(u32 i2c, u16 trise) +{ + I2C_TRISE(i2c) = trise; +} + +void i2c_send_7bit_address(u32 i2c, u8 slave, u8 readwrite) +{ + I2C_DR(i2c) = (u8)((slave << 1) | readwrite); +} + +void i2c_send_data(u32 i2c, u8 data) +{ + I2C_DR(i2c) = data; +} diff --git a/lib/stm32f1/libopencm3_stm32f1.ld b/lib/stm32f1/libopencm3_stm32f1.ld new file mode 100644 index 0000000..fda7d02 --- /dev/null +++ b/lib/stm32f1/libopencm3_stm32f1.ld @@ -0,0 +1,63 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Generic linker script for STM32 targets using libopencm3. */ + +/* Memory regions must be defined in the ld script which includes this one. */ + +/* Enforce emmition of the vector table. */ +EXTERN (vector_table) + +/* Define sections. */ +SECTIONS +{ + . = ORIGIN(rom); + + .text : { + *(.vectors) /* Vector table */ + *(.text*) /* Program code */ + *(.rodata*) /* Read-only data */ + _etext = .; + } >rom + + . = ORIGIN(ram); + + .data : { + _data = .; + *(.data*) /* Read-write initialized data */ + _edata = .; + } >ram AT >rom + + .bss : { + *(.bss*) /* Read-write zero initialized data */ + *(COMMON) + _ebss = .; + } >ram AT >rom + + /* + * The .eh_frame section appears to be used for C++ exception handling. + * You may need to fix this if you're using C++. + */ + /DISCARD/ : { *(.eh_frame) } + + end = .; +} + +PROVIDE(_stack = 0x20000800); + diff --git a/lib/stm32f1/nvic.c b/lib/stm32f1/nvic.c new file mode 100644 index 0000000..cf77cc3 --- /dev/null +++ b/lib/stm32f1/nvic.c @@ -0,0 +1,106 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include + +void nvic_enable_irq(u8 irqn) +{ + if (irqn < 32) + NVIC_ISER(0) |= (1 << irqn); + if ((irqn >= 32) & (irqn < 64)) + NVIC_ISER(1) |= (1 << (irqn - 32)); + if ((irqn >= 64) & (irqn < 68)) + NVIC_ISER(2) |= (1 << (irqn - 64)); +} + +void nvic_disable_irq(u8 irqn) +{ + if (irqn < 32) + NVIC_ICER(0) |= (1 << irqn); + if ((irqn >= 32) & (irqn < 64)) + NVIC_ICER(1) |= (1 << (irqn - 32)); + if ((irqn >= 64) & (irqn < 68)) + NVIC_ICER(2) |= (1 << (irqn - 64)); +} + +u8 nvic_get_pending_irq(u8 irqn) +{ + if (irqn < 32) + return (NVIC_ISPR(0) & (1 << irqn)); + if ((irqn >= 32) & (irqn < 64)) + return (NVIC_ISPR(1) & (1 << (irqn - 32))); + if ((irqn >= 64) & (irqn < 68)) + return (NVIC_ISPR(2) & (1 << (irqn - 64))); + return 0; +} + +void nvic_set_pending_irq(u8 irqn) +{ + if (irqn < 32) + NVIC_ISPR(0) |= (1 << irqn); + if ((irqn >= 32) & (irqn < 64)) + NVIC_ISPR(1) |= (1 << (irqn - 32)); + if ((irqn >= 64) & (irqn < 68)) + NVIC_ISPR(2) |= (1 << (irqn - 64)); +} + +void nvic_clear_pending_irq(u8 irqn) +{ + if (irqn < 32) + NVIC_ICPR(0) |= (1 << irqn); + if ((irqn >= 32) & (irqn < 64)) + NVIC_ICPR(1) |= (1 << (irqn - 32)); + if ((irqn >= 64) & (irqn < 68)) + NVIC_ICPR(2) |= (1 << (irqn - 64)); +} + +u8 nvic_get_active_irq(u8 irqn) +{ + if (irqn < 32) + return (NVIC_IABR(0) & (1 << irqn)); + if ((irqn >= 32) & (irqn < 64)) + return (NVIC_IABR(1) & (1 << (irqn - 32))); + if ((irqn >= 64) & (irqn < 68)) + return (NVIC_IABR(2) & (1 << (irqn - 64))); + return 0; +} + +u8 nvic_get_irq_enabled(u8 irqn) +{ + if (irqn < 32) + return (NVIC_ISER(0) & (1 << irqn)); + if ((irqn >= 32) & (irqn < 64)) + return (NVIC_ISER(1) & (1 << (irqn - 32))); + if ((irqn >= 64) & (irqn < 68)) + return (NVIC_ISER(2) & (1 << (irqn - 64))); + return 0; +} + +void nvic_set_priority(u8 irqn, u8 priority) +{ + NVIC_IPR(irqn/4) |= (priority << ((irqn % 4) * 8)); +} + +void nvic_generate_software_interrupt(u8 irqn) +{ + if (irqn <= 239) + NVIC_STIR |= irqn; +} + + diff --git a/lib/stm32f1/rcc.c b/lib/stm32f1/rcc.c new file mode 100644 index 0000000..f646168 --- /dev/null +++ b/lib/stm32f1/rcc.c @@ -0,0 +1,677 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Federico Ruiz-Ugalde + * Copyright (C) 2009 Uwe Hermann + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include + +/* Set the default ppre1 and ppre2 peripheral clock frequencies after reset */ +u32 rcc_ppre1_frequency = 8000000; +u32 rcc_ppre2_frequency = 8000000; + +void rcc_osc_ready_int_clear(osc_t osc) +{ + switch (osc) { + case PLL: + RCC_CIR |= RCC_CIR_PLLRDYC; + break; + case HSE: + RCC_CIR |= RCC_CIR_HSERDYC; + break; + case HSI: + RCC_CIR |= RCC_CIR_HSIRDYC; + break; + case LSE: + RCC_CIR |= RCC_CIR_LSERDYC; + break; + case LSI: + RCC_CIR |= RCC_CIR_LSIRDYC; + break; + } +} + +void rcc_osc_ready_int_enable(osc_t osc) +{ + switch (osc) { + case PLL: + RCC_CIR |= RCC_CIR_PLLRDYIE; + break; + case HSE: + RCC_CIR |= RCC_CIR_HSERDYIE; + break; + case HSI: + RCC_CIR |= RCC_CIR_HSIRDYIE; + break; + case LSE: + RCC_CIR |= RCC_CIR_LSERDYIE; + break; + case LSI: + RCC_CIR |= RCC_CIR_LSIRDYIE; + break; + } +} + +void rcc_osc_ready_int_disable(osc_t osc) +{ + switch (osc) { + case PLL: + RCC_CIR &= ~RCC_CIR_PLLRDYIE; + break; + case HSE: + RCC_CIR &= ~RCC_CIR_HSERDYIE; + break; + case HSI: + RCC_CIR &= ~RCC_CIR_HSIRDYIE; + break; + case LSE: + RCC_CIR &= ~RCC_CIR_LSERDYIE; + break; + case LSI: + RCC_CIR &= ~RCC_CIR_LSIRDYIE; + break; + } +} + +int rcc_osc_ready_int_flag(osc_t osc) +{ + switch (osc) { + case PLL: + return ((RCC_CIR & RCC_CIR_PLLRDYF) != 0); + break; + case HSE: + return ((RCC_CIR & RCC_CIR_HSERDYF) != 0); + break; + case HSI: + return ((RCC_CIR & RCC_CIR_HSIRDYF) != 0); + break; + case LSE: + return ((RCC_CIR & RCC_CIR_LSERDYF) != 0); + break; + case LSI: + return ((RCC_CIR & RCC_CIR_LSIRDYF) != 0); + break; + } + + /* Shouldn't be reached. */ + return -1; +} + +void rcc_css_int_clear(void) +{ + RCC_CIR |= RCC_CIR_CSSC; +} + +int rcc_css_int_flag(void) +{ + return ((RCC_CIR & RCC_CIR_CSSF) != 0); +} + +void rcc_wait_for_osc_ready(osc_t osc) +{ + switch (osc) { + case PLL: + while ((RCC_CR & RCC_CR_PLLRDY) == 0); + break; + case HSE: + while ((RCC_CR & RCC_CR_HSERDY) == 0); + break; + case HSI: + while ((RCC_CR & RCC_CR_HSIRDY) == 0); + break; + case LSE: + while ((RCC_BDCR & RCC_BDCR_LSERDY) == 0); + break; + case LSI: + while ((RCC_CSR & RCC_CSR_LSIRDY) == 0); + break; + } +} + +void rcc_osc_on(osc_t osc) +{ + switch (osc) { + case PLL: + RCC_CR |= RCC_CR_PLLON; + break; + case HSE: + RCC_CR |= RCC_CR_HSEON; + break; + case HSI: + RCC_CR |= RCC_CR_HSION; + break; + case LSE: + RCC_BDCR |= RCC_BDCR_LSEON; + break; + case LSI: + RCC_CSR |= RCC_CSR_LSION; + break; + } +} + +void rcc_osc_off(osc_t osc) +{ + switch (osc) { + case PLL: + RCC_CR &= ~RCC_CR_PLLON; + break; + case HSE: + RCC_CR &= ~RCC_CR_HSEON; + break; + case HSI: + RCC_CR &= ~RCC_CR_HSION; + break; + case LSE: + RCC_BDCR &= ~RCC_BDCR_LSEON; + break; + case LSI: + RCC_CSR &= ~RCC_CSR_LSION; + break; + } +} + +void rcc_css_enable(void) +{ + RCC_CR |= RCC_CR_CSSON; +} + +void rcc_css_disable(void) +{ + RCC_CR &= ~RCC_CR_CSSON; +} + +void rcc_osc_bypass_enable(osc_t osc) +{ + switch (osc) { + case HSE: + RCC_CR |= RCC_CR_HSEBYP; + break; + case LSE: + RCC_BDCR |= RCC_BDCR_LSEBYP; + break; + case PLL: + case HSI: + case LSI: + /* Do nothing, only HSE/LSE allowed here. */ + break; + } +} + +void rcc_osc_bypass_disable(osc_t osc) +{ + switch (osc) { + case HSE: + RCC_CR &= ~RCC_CR_HSEBYP; + break; + case LSE: + RCC_BDCR &= ~RCC_BDCR_LSEBYP; + break; + case PLL: + case HSI: + case LSI: + /* Do nothing, only HSE/LSE allowed here. */ + break; + } +} + +void rcc_peripheral_enable_clock(volatile u32 *reg, u32 en) +{ + *reg |= en; +} + +void rcc_peripheral_disable_clock(volatile u32 *reg, u32 en) +{ + *reg &= ~en; +} + +void rcc_peripheral_reset(volatile u32 *reg, u32 reset) +{ + *reg |= reset; +} + +void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset) +{ + *reg &= ~clear_reset; +} + +void rcc_set_sysclk_source(u32 clk) +{ + u32 reg32; + + reg32 = RCC_CFGR; + reg32 &= ~((1 << 1) | (1 << 0)); + RCC_CFGR = (reg32 | clk); +} + +void rcc_set_pll_multiplication_factor(u32 mul) +{ + u32 reg32; + + reg32 = RCC_CFGR; + reg32 &= ~((1 << 21) | (1 << 20) | (1 << 19) | (1 << 18)); + RCC_CFGR = (reg32 | (mul << 18)); +} + +void rcc_set_pll_source(u32 pllsrc) +{ + u32 reg32; + + reg32 = RCC_CFGR; + reg32 &= ~(1 << 16); + RCC_CFGR = (reg32 | (pllsrc << 16)); +} + +void rcc_set_pllxtpre(u32 pllxtpre) +{ + u32 reg32; + + reg32 = RCC_CFGR; + reg32 &= ~(1 << 17); + RCC_CFGR = (reg32 | (pllxtpre << 17)); +} + +void rcc_set_adcpre(u32 adcpre) +{ + u32 reg32; + + reg32 = RCC_CFGR; + reg32 &= ~((1 << 14) | (1 << 15)); + RCC_CFGR = (reg32 | (adcpre << 14)); +} + +void rcc_set_ppre2(u32 ppre2) +{ + u32 reg32; + + reg32 = RCC_CFGR; + reg32 &= ~((1 << 11) | (1 << 12) | (1 << 13)); + RCC_CFGR = (reg32 | (ppre2 << 11)); +} + +void rcc_set_ppre1(u32 ppre1) +{ + u32 reg32; + + reg32 = RCC_CFGR; + reg32 &= ~((1 << 8) | (1 << 9) | (1 << 10)); + RCC_CFGR = (reg32 | (ppre1 << 8)); +} + +void rcc_set_hpre(u32 hpre) +{ + u32 reg32; + + reg32 = RCC_CFGR; + reg32 &= ~((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7)); + RCC_CFGR = (reg32 | (hpre << 4)); +} + +void rcc_set_usbpre(u32 usbpre) +{ + u32 reg32; + + reg32 = RCC_CFGR; + reg32 &= ~(1 << 22); + RCC_CFGR = (reg32 | (usbpre << 22)); +} + +u32 rcc_system_clock_source(void) +{ + /* Return the clock source which is used as system clock. */ + return ((RCC_CFGR & 0x000c) >> 2); +} + +/* + * These functions are setting up the whole clock system for the most common + * input clock and output clock configurations. + */ +void rcc_clock_setup_in_hsi_out_64mhz(void) +{ + /* Enable internal high-speed oscillator. */ + rcc_osc_on(HSI); + rcc_wait_for_osc_ready(HSI); + + /* Select HSI as SYSCLK source. */ + rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK); + + /* + * Set prescalers for AHB, ADC, ABP1, ABP2. + * Do this before touching the PLL (TODO: why?). + */ + rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 64MHz Max. 72MHz */ + rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV8); /* Set. 8MHz Max. 14MHz */ + rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 32MHz Max. 36MHz */ + rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 64MHz Max. 72MHz */ + + /* + * Sysclk is running with 64MHz -> 2 waitstates. + * 0WS from 0-24MHz + * 1WS from 24-48MHz + * 2WS from 48-72MHz + */ + flash_set_ws(FLASH_LATENCY_2WS); + + /* + * Set the PLL multiplication factor to 16. + * 8MHz (internal) * 16 (multiplier) / 2 (PLLSRC_HSI_CLK_DIV2) = 64MHz + */ + rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_PLL_CLK_MUL16); + + /* Select HSI/2 as PLL source. */ + rcc_set_pll_source(RCC_CFGR_PLLSRC_HSI_CLK_DIV2); + + /* Enable PLL oscillator and wait for it to stabilize. */ + rcc_osc_on(PLL); + rcc_wait_for_osc_ready(PLL); + + /* Select PLL as SYSCLK source. */ + rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK); + + /* Set the peripheral clock frequencies used */ + rcc_ppre1_frequency = 32000000; + rcc_ppre2_frequency = 64000000; +} + +void rcc_clock_setup_in_hsi_out_48mhz(void) +{ + /* Enable internal high-speed oscillator. */ + rcc_osc_on(HSI); + rcc_wait_for_osc_ready(HSI); + + /* Select HSI as SYSCLK source. */ + rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK); + + /* + * Set prescalers for AHB, ADC, ABP1, ABP2. + * Do this before touching the PLL (TODO: why?). + */ + rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 48MHz Max. 72MHz */ + rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV8); /* Set. 6MHz Max. 14MHz */ + rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 24MHz Max. 36MHz */ + rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 48MHz Max. 72MHz */ + rcc_set_usbpre(RCC_CFGR_USBPRE_PLL_CLK_NODIV); /* Set. 48MHz Max. 48MHz */ + + /* + * Sysclk runs with 48MHz -> 1 waitstates. + * 0WS from 0-24MHz + * 1WS from 24-48MHz + * 2WS from 48-72MHz + */ + flash_set_ws(FLASH_LATENCY_1WS); + + /* + * Set the PLL multiplication factor to 12. + * 8MHz (internal) * 12 (multiplier) / 2 (PLLSRC_HSI_CLK_DIV2) = 48MHz + */ + rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_PLL_CLK_MUL12); + + /* Select HSI/2 as PLL source. */ + rcc_set_pll_source(RCC_CFGR_PLLSRC_HSI_CLK_DIV2); + + /* Enable PLL oscillator and wait for it to stabilize. */ + rcc_osc_on(PLL); + rcc_wait_for_osc_ready(PLL); + + /* Select PLL as SYSCLK source. */ + rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK); + + /* Set the peripheral clock frequencies used */ + rcc_ppre1_frequency = 24000000; + rcc_ppre2_frequency = 48000000; +} + +void rcc_clock_setup_in_hse_8mhz_out_24mhz(void) +{ + /* Enable internal high-speed oscillator. */ + rcc_osc_on(HSI); + rcc_wait_for_osc_ready(HSI); + + /* Select HSI as SYSCLK source. */ + rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK); + + /* Enable external high-speed oscillator 8MHz. */ + rcc_osc_on(HSE); + rcc_wait_for_osc_ready(HSE); + rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSECLK); + + /* + * Set prescalers for AHB, ADC, ABP1, ABP2. + * Do this before touching the PLL (TODO: why?). + */ + rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 24MHz Max. 72MHz */ + rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV2); /* Set. 12MHz Max. 14MHz */ + rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_NODIV); /* Set. 24MHz Max. 36MHz */ + rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 24MHz Max. 72MHz */ + + /* + * Sysclk runs with 24MHz -> 0 waitstates. + * 0WS from 0-24MHz + * 1WS from 24-48MHz + * 2WS from 48-72MHz + */ + flash_set_ws(FLASH_LATENCY_0WS); + + /* + * Set the PLL multiplication factor to 3. + * 8MHz (external) * 3 (multiplier) = 24MHz + */ + rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_PLL_CLK_MUL3); + + /* Select HSE as PLL source. */ + rcc_set_pll_source(RCC_CFGR_PLLSRC_HSE_CLK); + + /* + * External frequency undivided before entering PLL + * (only valid/needed for HSE). + */ + rcc_set_pllxtpre(RCC_CFGR_PLLXTPRE_HSE_CLK); + + /* Enable PLL oscillator and wait for it to stabilize. */ + rcc_osc_on(PLL); + rcc_wait_for_osc_ready(PLL); + + /* Select PLL as SYSCLK source. */ + rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK); + + /* Set the peripheral clock frequencies used */ + rcc_ppre1_frequency = 24000000; + rcc_ppre2_frequency = 24000000; +} +void rcc_clock_setup_in_hse_8mhz_out_72mhz(void) +{ + /* Enable internal high-speed oscillator. */ + rcc_osc_on(HSI); + rcc_wait_for_osc_ready(HSI); + + /* Select HSI as SYSCLK source. */ + rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK); + + /* Enable external high-speed oscillator 8MHz. */ + rcc_osc_on(HSE); + rcc_wait_for_osc_ready(HSE); + rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSECLK); + + /* + * Set prescalers for AHB, ADC, ABP1, ABP2. + * Do this before touching the PLL (TODO: why?). + */ + rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 72MHz Max. 72MHz */ + rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV8); /* Set. 9MHz Max. 14MHz */ + rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 36MHz Max. 36MHz */ + rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 72MHz Max. 72MHz */ + + /* + * Sysclk runs with 72MHz -> 2 waitstates. + * 0WS from 0-24MHz + * 1WS from 24-48MHz + * 2WS from 48-72MHz + */ + flash_set_ws(FLASH_LATENCY_2WS); + + /* + * Set the PLL multiplication factor to 9. + * 8MHz (external) * 9 (multiplier) = 72MHz + */ + rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_PLL_CLK_MUL9); + + /* Select HSE as PLL source. */ + rcc_set_pll_source(RCC_CFGR_PLLSRC_HSE_CLK); + + /* + * External frequency undivided before entering PLL + * (only valid/needed for HSE). + */ + rcc_set_pllxtpre(RCC_CFGR_PLLXTPRE_HSE_CLK); + + /* Enable PLL oscillator and wait for it to stabilize. */ + rcc_osc_on(PLL); + rcc_wait_for_osc_ready(PLL); + + /* Select PLL as SYSCLK source. */ + rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK); + + /* Set the peripheral clock frequencies used */ + rcc_ppre1_frequency = 36000000; + rcc_ppre2_frequency = 72000000; +} + +void rcc_clock_setup_in_hse_12mhz_out_72mhz(void) +{ + /* Enable internal high-speed oscillator. */ + rcc_osc_on(HSI); + rcc_wait_for_osc_ready(HSI); + + /* Select HSI as SYSCLK source. */ + rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK); + + /* Enable external high-speed oscillator 16MHz. */ + rcc_osc_on(HSE); + rcc_wait_for_osc_ready(HSE); + rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSECLK); + + /* + * Set prescalers for AHB, ADC, ABP1, ABP2. + * Do this before touching the PLL (TODO: why?). + */ + rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 72MHz Max. 72MHz */ + rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV6); /* Set. 12MHz Max. 14MHz */ + rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 36MHz Max. 36MHz */ + rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 72MHz Max. 72MHz */ + + /* + * Sysclk runs with 72MHz -> 2 waitstates. + * 0WS from 0-24MHz + * 1WS from 24-48MHz + * 2WS from 48-72MHz + */ + flash_set_ws(FLASH_LATENCY_2WS); + + /* + * Set the PLL multiplication factor to 9. + * 12MHz (external) * 6 (multiplier) / 1 (PLLXTPRE_HSE_CLK) = 72MHz + */ + rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_PLL_CLK_MUL6); + + /* Select HSI as PLL source. */ + rcc_set_pll_source(RCC_CFGR_PLLSRC_HSE_CLK); + + /* + * Divide external frequency by 2 before entering PLL + * (only valid/needed for HSE). + */ + rcc_set_pllxtpre(RCC_CFGR_PLLXTPRE_HSE_CLK); + + /* Enable PLL oscillator and wait for it to stabilize. */ + rcc_osc_on(PLL); + rcc_wait_for_osc_ready(PLL); + + /* Select PLL as SYSCLK source. */ + rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK); + + /* Set the peripheral clock frequencies used */ + rcc_ppre1_frequency = 36000000; + rcc_ppre2_frequency = 72000000; +} + +void rcc_clock_setup_in_hse_16mhz_out_72mhz(void) +{ + /* Enable internal high-speed oscillator. */ + rcc_osc_on(HSI); + rcc_wait_for_osc_ready(HSI); + + /* Select HSI as SYSCLK source. */ + rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK); + + /* Enable external high-speed oscillator 16MHz. */ + rcc_osc_on(HSE); + rcc_wait_for_osc_ready(HSE); + rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSECLK); + + /* + * Set prescalers for AHB, ADC, ABP1, ABP2. + * Do this before touching the PLL (TODO: why?). + */ + rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 72MHz Max. 72MHz */ + rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV6); /* Set. 12MHz Max. 14MHz */ + rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 36MHz Max. 36MHz */ + rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 72MHz Max. 72MHz */ + + /* + * Sysclk runs with 72MHz -> 2 waitstates. + * 0WS from 0-24MHz + * 1WS from 24-48MHz + * 2WS from 48-72MHz + */ + flash_set_ws(FLASH_LATENCY_2WS); + + /* + * Set the PLL multiplication factor to 9. + * 16MHz (external) * 9 (multiplier) / 2 (PLLXTPRE_HSE_CLK_DIV2) = 72MHz + */ + rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_PLL_CLK_MUL9); + + /* Select HSI as PLL source. */ + rcc_set_pll_source(RCC_CFGR_PLLSRC_HSE_CLK); + + /* + * Divide external frequency by 2 before entering PLL + * (only valid/needed for HSE). + */ + rcc_set_pllxtpre(RCC_CFGR_PLLXTPRE_HSE_CLK_DIV2); + + /* Enable PLL oscillator and wait for it to stabilize. */ + rcc_osc_on(PLL); + rcc_wait_for_osc_ready(PLL); + + /* Select PLL as SYSCLK source. */ + rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK); + + /* Set the peripheral clock frequencies used */ + rcc_ppre1_frequency = 36000000; + rcc_ppre2_frequency = 72000000; +} + +void rcc_backupdomain_reset(void) +{ + /* Set the backup domain software reset. */ + RCC_BDCR |= RCC_BDCR_BDRST; + + /* Clear the backup domain software reset. */ + RCC_BDCR &= ~RCC_BDCR_BDRST; +} diff --git a/lib/stm32f1/rtc.c b/lib/stm32f1/rtc.c new file mode 100644 index 0000000..4495641 --- /dev/null +++ b/lib/stm32f1/rtc.c @@ -0,0 +1,282 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Uwe Hermann + * Copyright (C) 2010 Lord James + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include + +void rtc_awake_from_off(osc_t clock_source) +{ + u32 reg32; + + /* Enable power and backup interface clocks. */ + RCC_APB1ENR |= (RCC_APB1ENR_PWREN | RCC_APB1ENR_BKPEN); + + /* Enable access to the backup registers and the RTC. */ + PWR_CR |= PWR_CR_DBP; + + /* + * Reset the backup domain, clears everything RTC related. + * If not wanted use the rtc_awake_from_standby() function. + */ + rcc_backupdomain_reset(); + + switch (clock_source) { + case LSE: + /* Turn the LSE on and wait while it stabilises. */ + RCC_BDCR |= RCC_BDCR_LSEON; + while ((reg32 = (RCC_BDCR & RCC_BDCR_LSERDY)) == 0); + + /* Choose LSE as the RTC clock source. */ + RCC_BDCR &= ~((1 << 8) | (1 << 9)); + RCC_BDCR |= (1 << 8); + break; + case LSI: + /* Turn the LSI on and wait while it stabilises. */ + RCC_CSR |= RCC_CSR_LSION; + while ((reg32 = (RCC_CSR & RCC_CSR_LSIRDY)) == 0); + + /* Choose LSI as the RTC clock source. */ + RCC_BDCR &= ~((1 << 8) | (1 << 9)); + RCC_BDCR |= (1 << 9); + break; + case HSE: + /* Turn the HSE on and wait while it stabilises. */ + RCC_CR |= RCC_CR_HSEON; + while ((reg32 = (RCC_CR & RCC_CR_HSERDY)) == 0); + + /* Choose HSE as the RTC clock source. */ + RCC_BDCR &= ~((1 << 8) | (1 << 9)); + RCC_BDCR |= (1 << 9) | (1 << 8); + break; + case PLL: + case HSI: + /* Unusable clock source, here to prevent warnings. */ + /* Turn off clock sources to RTC. */ + RCC_BDCR &= ~((1 << 8) | (1 << 9)); + break; + } + + /* Enable the RTC. */ + RCC_BDCR |= RCC_BDCR_RTCEN; + + /* Wait for the RSF bit in RTC_CRL to be set by hardware. */ + RTC_CRL &= ~RTC_CRL_RSF; + while ((reg32 = (RTC_CRL & RTC_CRL_RSF)) == 0); + + /* Wait for the last write operation to finish. */ + /* TODO: Necessary? */ + while ((reg32 = (RTC_CRL & RTC_CRL_RTOFF)) == 0); +} + +void rtc_enter_config_mode(void) +{ + u32 reg32; + + /* Wait until the RTOFF bit is 1 (no RTC register writes ongoing). */ + while ((reg32 = (RTC_CRL & RTC_CRL_RTOFF)) == 0); + + /* Enter configuration mode. */ + RTC_CRL |= RTC_CRL_CNF; +} + +void rtc_exit_config_mode(void) +{ + /* u32 reg32; */ + + /* Exit configuration mode. */ + RTC_CRL &= ~RTC_CRL_CNF; + + /* Wait until the RTOFF bit is 1 (our RTC register write finished). */ + /* while ((reg32 = (RTC_CRL & RTC_CRL_RTOFF)) == 0); */ + /* TODO: Unnecessary since we poll the bit on config entry(?) */ +} + +void rtc_set_alarm_time(u32 alarm_time) +{ + rtc_enter_config_mode(); + RTC_ALRL = (alarm_time & 0x0000ffff); + RTC_ALRH = (alarm_time & 0xffff0000) >> 16; + rtc_exit_config_mode(); +} + +void rtc_enable_alarm(void) +{ + rtc_enter_config_mode(); + RTC_CRH |= RTC_CRH_ALRIE; + rtc_exit_config_mode(); +} + +void rtc_disable_alarm(void) +{ + rtc_enter_config_mode(); + RTC_CRH &= ~RTC_CRH_ALRIE; + rtc_exit_config_mode(); +} + +void rtc_set_prescale_val(u32 prescale_val) +{ + rtc_enter_config_mode(); + RTC_PRLL = prescale_val & 0x0000ffff; /* PRL[15:0] */ + RTC_PRLH = (prescale_val & 0x000f0000) >> 16; /* PRL[19:16] */ + rtc_exit_config_mode(); +} + +u32 rtc_get_counter_val(void) +{ + return (RTC_CNTH << 16) | RTC_CNTL; +} + +u32 rtc_get_prescale_div_val(void) +{ + return (RTC_DIVH << 16) | RTC_DIVL; +} + +u32 rtc_get_alarm_val(void) +{ + return (RTC_ALRH << 16) | RTC_ALRL; +} + +void rtc_set_counter_val(u32 counter_val) +{ + rtc_enter_config_mode(); + RTC_CNTH = (counter_val & 0xffff0000) >> 16; /* CNT[31:16] */ + RTC_CNTL = counter_val & 0x0000ffff; /* CNT[15:0] */ + rtc_exit_config_mode(); +} + +void rtc_interrupt_enable(rtcflag_t flag_val) +{ + rtc_enter_config_mode(); + + /* Set the correct interrupt enable. */ + switch(flag_val) { + case RTC_SEC: + RTC_CRH |= RTC_CRH_SECIE; + break; + case RTC_ALR: + RTC_CRH |= RTC_CRH_ALRIE; + break; + case RTC_OW: + RTC_CRH |= RTC_CRH_OWIE; + break; + } + + rtc_exit_config_mode(); +} + +void rtc_interrupt_disable(rtcflag_t flag_val) +{ + rtc_enter_config_mode(); + + /* Disable the correct interrupt enable. */ + switch(flag_val) { + case RTC_SEC: + RTC_CRH &= ~RTC_CRH_SECIE; + break; + case RTC_ALR: + RTC_CRH &= ~RTC_CRH_ALRIE; + break; + case RTC_OW: + RTC_CRH &= ~RTC_CRH_OWIE; + break; + } + + rtc_exit_config_mode(); +} + +void rtc_clear_flag(rtcflag_t flag_val) +{ + /* Configuration mode not needed. */ + + /* Clear the correct flag. */ + switch(flag_val) { + case RTC_SEC: + RTC_CRL &= ~RTC_CRL_SECF; + break; + case RTC_ALR: + RTC_CRL &= ~RTC_CRL_ALRF; + break; + case RTC_OW: + RTC_CRL &= ~RTC_CRL_OWF; + break; + } +} + +u32 rtc_check_flag(rtcflag_t flag_val) +{ + u32 reg32; + + /* Read correct flag. */ + switch(flag_val) { + case RTC_SEC: + reg32 = RTC_CRL & RTC_CRL_SECF; + break; + case RTC_ALR: + reg32 = RTC_CRL & RTC_CRL_ALRF; + break; + case RTC_OW: + reg32 = RTC_CRL & RTC_CRL_OWF; + break; + default: + reg32 = 0; + break; + } + + return reg32; +} + +void rtc_awake_from_standby(void) +{ + u32 reg32; + + /* Enable power and backup interface clocks. */ + RCC_APB1ENR |= (RCC_APB1ENR_PWREN | RCC_APB1ENR_BKPEN); + + /* Enable access to the backup registers and the RTC. */ + PWR_CR |= PWR_CR_DBP; + + /* Wait for the RSF bit in RTC_CRL to be set by hardware. */ + RTC_CRL &= ~RTC_CRL_RSF; + while ((reg32 = (RTC_CRL & RTC_CRL_RSF)) == 0); + + /* Wait for the last write operation to finish. */ + /* TODO: Necessary? */ + while ((reg32 = (RTC_CRL & RTC_CRL_RTOFF)) == 0); +} + +void rtc_auto_awake(osc_t clock_source, u32 prescale_val) +{ + u32 reg32; + + /* Enable power and backup interface clocks. */ + RCC_APB1ENR |= (RCC_APB1ENR_PWREN | RCC_APB1ENR_BKPEN); + + /* Enable access to the backup registers and the RTC. */ + /* TODO: Not sure if this is necessary to just read the flag. */ + PWR_CR |= PWR_CR_DBP; + + if ((reg32 = RCC_BDCR & RCC_BDCR_RTCEN) != 0) { + rtc_awake_from_standby(); + } else { + rtc_awake_from_off(clock_source); + rtc_set_prescale_val(prescale_val); + } +} diff --git a/lib/stm32f1/scb.c b/lib/stm32f1/scb.c new file mode 100644 index 0000000..dfee6c3 --- /dev/null +++ b/lib/stm32f1/scb.c @@ -0,0 +1,30 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Gareth McMullin + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include + +void scb_reset_core(void) +{ + SCB_AIRCR = SCB_AIRCR_VECTKEY | SCB_AIRCR_VECTRESET; +} + +void scb_reset_system(void) +{ + SCB_AIRCR = SCB_AIRCR_VECTKEY | SCB_AIRCR_SYSRESETREQ; +} diff --git a/lib/stm32f1/spi.c b/lib/stm32f1/spi.c new file mode 100644 index 0000000..733a1bc --- /dev/null +++ b/lib/stm32f1/spi.c @@ -0,0 +1,290 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include + +/* + * SPI and I2S code. + * + * Examples: + * spi_init_master(SPI1, 1000000, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE, + * SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT, + * SPI_CR1_LSBFIRST); + * spi_write(SPI1, 0x55); // 8-bit write + * spi_write(SPI1, 0xaa88); // 16-bit write + * reg8 = spi_read(SPI1); // 8-bit read + * reg16 = spi_read(SPI1); // 16-bit read + */ + +int spi_init_master(u32 spi, u32 br, u32 cpol, u32 cpha, u32 dff, u32 lsbfirst) +{ + u32 reg32 = 0; + + reg32 |= SPI_CR1_MSTR; /* Configure SPI as master. */ + + reg32 |= br; /* Set BAUD rate bits. */ + reg32 |= cpol; /* Set CPOL value. */ + reg32 |= cpha; /* Set CPHA value. */ + reg32 |= dff; /* Set data format (8 or 16 bits). */ + reg32 |= lsbfirst; /* Set frame format (LSB- or MSB-first). */ + + /* TODO: NSS pin handling. */ + + SPI_CR1(spi) = reg32; + + return 0; /* TODO */ +} + +/* TODO: Error handling? */ +void spi_enable(u32 spi) +{ + u32 reg32; + + reg32 = SPI_CR1(spi); + reg32 |= SPI_CR1_SPE; /* Enable SPI. */ + SPI_CR1(spi) = reg32; +} + +/* TODO: Error handling? */ +void spi_disable(u32 spi) +{ + u32 reg32; + + /* TODO: Follow procedure from section 23.3.8 in the techref manual. */ + reg32 = SPI_CR1(spi); + reg32 &= ~(SPI_CR1_SPE); /* Disable SPI. */ + SPI_CR1(spi) = reg32; +} + +void spi_write(u32 spi, u16 data) +{ + /* Write data (8 or 16 bits, depending on DFF) into DR. */ + SPI_DR(spi) = data; +} + +void spi_send(u32 spi, u16 data) +{ + /* Write data (8 or 16 bits, depending on DFF) into DR. */ + SPI_DR(spi) = data; + + /* wait for transfer finished */ + while (SPI_SR(spi) & SPI_SR_BSY ) + { + } +} + +u16 spi_read(u32 spi) +{ + /* Read the data (8 or 16 bits, depending on DFF bit) from DR. */ + return SPI_DR(spi); +} + +void spi_set_bidirectional_mode(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_BIDIMODE; +} + +void spi_set_unidirectional_mode(u32 spi) +{ + SPI_CR1(spi) &= ~SPI_CR1_BIDIMODE; +} + +void spi_set_bidirectional_receive_only_mode(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_BIDIMODE; + SPI_CR1(spi) &= ~SPI_CR1_BIDIOE; +} + +void spi_set_bidirectional_transmit_only_mode(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_BIDIMODE; + SPI_CR1(spi) |= SPI_CR1_BIDIOE; +} + +void spi_enable_crc(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_CRCEN; +} + +void spi_disable_crc(u32 spi) +{ + SPI_CR1(spi) &= ~SPI_CR1_CRCEN; +} + +void spi_set_next_tx_from_buffer(u32 spi) +{ + SPI_CR1(spi) &= ~SPI_CR1_CRCNEXT; +} + +void spi_set_next_tx_from_crc(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_CRCNEXT; +} + +void spi_set_dff_8bit(u32 spi) +{ + SPI_CR1(spi) &= ~SPI_CR1_DFF; +} + +void spi_set_dff_16bit(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_DFF; +} + +void spi_set_full_duplex_mode(u32 spi) +{ + SPI_CR1(spi) &= ~SPI_CR1_RXONLY; +} + +void spi_set_receive_only_mode(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_RXONLY; +} + +void spi_disable_software_slave_management(u32 spi) +{ + SPI_CR1(spi) &= ~SPI_CR1_SSM; +} + +void spi_enable_software_slave_management(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_SSM; +} + +void spi_set_nss_high(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_SSI; +} + +void spi_set_nss_low(u32 spi) +{ + SPI_CR1(spi) &= ~SPI_CR1_SSI; +} + +void spi_send_lsb_first(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_LSBFIRST; +} + +void spi_send_msb_first(u32 spi) +{ + SPI_CR1(spi) &= ~SPI_CR1_LSBFIRST; +} + +void spi_set_baudrate_prescaler(u32 spi, u8 baudrate) +{ + u32 reg32; + + if (baudrate > 7) + return; + + reg32 = ( SPI_CR1(spi) & 0xffc7 ); /* clear bits [5:3] */ + reg32 |= (baudrate << 3); + SPI_CR1(spi) = reg32; +} + +void spi_set_master_mode(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_MSTR; +} + +void spi_set_slave_mode(u32 spi) +{ + SPI_CR1(spi) &= ~SPI_CR1_MSTR; +} + +void spi_set_clock_polarity_1(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_CPOL; +} + +void spi_set_clock_polarity_0(u32 spi) +{ + SPI_CR1(spi) &= ~SPI_CR1_CPOL; +} + +void spi_set_clock_phase_1(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_CPHA; +} + +void spi_set_clock_phase_0(u32 spi) +{ + SPI_CR1(spi) &= ~SPI_CR1_CPHA; +} + +void spi_enable_tx_buffer_empty_interrupt(u32 spi) +{ + SPI_CR2(spi) |= SPI_CR2_TXEIE; +} + +void spi_disable_tx_buffer_empty_interrupt(u32 spi) +{ + SPI_CR2(spi) &= ~SPI_CR2_TXEIE; +} + +void spi_enable_rx_buffer_not_empty_interrupt(u32 spi) +{ + SPI_CR2(spi) |= SPI_CR2_RXNEIE; +} + +void spi_disable_rx_buffer_not_empty_interrupt(u32 spi) +{ + SPI_CR2(spi) &= ~SPI_CR2_RXNEIE; +} + +void spi_enable_error_interrupt(u32 spi) +{ + SPI_CR2(spi) |= SPI_CR2_ERRIE; +} + +void spi_disable_error_interrupt(u32 spi) +{ + SPI_CR2(spi) &= ~SPI_CR2_ERRIE; +} + +void spi_enable_ss_output(u32 spi) +{ + SPI_CR2(spi) |= SPI_CR2_SSOE; +} + +void spi_disable_ss_output(u32 spi) +{ + SPI_CR2(spi) &= ~SPI_CR2_SSOE; +} + +void spi_enable_tx_dma(u32 spi) +{ + SPI_CR2(spi) |= SPI_CR2_TXDMAEN; +} + +void spi_disable_tx_dma(u32 spi) +{ + SPI_CR2(spi) &= ~SPI_CR2_TXDMAEN; +} + +void spi_enable_rx_dma(u32 spi) +{ + SPI_CR2(spi) |= SPI_CR2_RXDMAEN; +} + +void spi_disable_rx_dma(u32 spi) +{ + SPI_CR2(spi) &= ~SPI_CR2_RXDMAEN; +} diff --git a/lib/stm32f1/systick.c b/lib/stm32f1/systick.c new file mode 100644 index 0000000..882601d --- /dev/null +++ b/lib/stm32f1/systick.c @@ -0,0 +1,64 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include + +void systick_set_reload(u32 value) +{ + STK_LOAD = (value & 0x00FFFFFF); +} + +u32 systick_get_value(void) +{ + return STK_VAL; +} + +void systick_set_clocksource(u8 clocksource) +{ + if (clocksource < 2) + STK_CTRL |= (clocksource << STK_CTRL_CLKSOURCE_LSB); +} + +void systick_interrupt_enable(void) +{ + STK_CTRL |= STK_CTRL_TICKINT; +} + +void systick_interrupt_disable(void) +{ + STK_CTRL &= ~STK_CTRL_TICKINT; +} + +void systick_counter_enable(void) +{ + STK_CTRL |= STK_CTRL_ENABLE; +} + +void systick_counter_disable(void) +{ + STK_CTRL &= ~STK_CTRL_ENABLE; +} + +u8 systick_get_countflag(void) +{ + if (STK_CTRL & STK_CTRL_COUNTFLAG) + return 1; + else + return 0; +} diff --git a/lib/stm32f1/timer.c b/lib/stm32f1/timer.c new file mode 100644 index 0000000..32e240d --- /dev/null +++ b/lib/stm32f1/timer.c @@ -0,0 +1,914 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Edward Cheeseman + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* + * Basic TIMER handling API. + * + * Examples: + * timer_set_mode(TIM1, TIM_CR1_CKD_CK_INT_MUL_2, + * TIM_CR1_CMS_CENTRE_3, TIM_CR1_DIR_UP); + */ + +#include +#include + +void timer_reset(u32 timer_peripheral) +{ + switch (timer_peripheral) { + case TIM1: + rcc_peripheral_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM1RST); + rcc_peripheral_clear_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM1RST); + break; + case TIM2: + rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM2RST); + rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM2RST); + break; + case TIM3: + rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM3RST); + rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM3RST); + break; + case TIM4: + rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM4RST); + rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM4RST); + break; + case TIM5: + rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM5RST); + rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM5RST); + break; + case TIM6: + rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM6RST); + rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM6RST); + break; + case TIM7: + rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM7RST); + rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM7RST); + break; + case TIM8: + rcc_peripheral_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM8RST); + rcc_peripheral_clear_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM8RST); + break; +/* These timers are not supported in libopencm3 yet */ +/* + case TIM9: + rcc_peripheral_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM9RST); + rcc_peripheral_clear_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM9RST); + break; + case TIM10: + rcc_peripheral_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM10RST); + rcc_peripheral_clear_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM10RST); + break; + case TIM11: + rcc_peripheral_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM11RST); + rcc_peripheral_clear_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM11RST); + break; + case TIM12: + rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM12RST); + rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM12RST); + break; + case TIM13: + rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM13RST); + rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM13RST); + break; + case TIM14: + rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM14RST); + rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM14RST); + break; +*/ + } +} + +void timer_enable_irq(u32 timer_peripheral, u32 irq) +{ + TIM_DIER(timer_peripheral) |= irq; +} + +void timer_disable_irq(u32 timer_peripheral, u32 irq) +{ + TIM_DIER(timer_peripheral) &= ~irq; +} + +bool timer_get_flag(u32 timer_peripheral, u32 flag) +{ + if (((TIM_SR(timer_peripheral) & flag) != 0) && + ((TIM_DIER(timer_peripheral) & flag) != 0)) { + return true; + } + + return false; +} + +void timer_clear_flag(u32 timer_peripheral, u32 flag) +{ + TIM_SR(timer_peripheral) &= ~flag; +} + +void timer_set_mode(u32 timer_peripheral, u8 clock_div, + u8 alignment, u8 direction) +{ + u32 cr1; + + cr1 = TIM_CR1(timer_peripheral); + + cr1 &= ~(TIM_CR1_CKD_CK_INT_MASK | + TIM_CR1_CMS_MASK | + TIM_CR1_DIR_DOWN); + + cr1 |= clock_div | alignment | direction; + + TIM_CR1(timer_peripheral) = cr1; +} + +void timer_set_clock_division(u32 timer_peripheral, u32 clock_div) +{ + clock_div &= TIM_CR1_CKD_CK_INT_MASK; + TIM_CR1(timer_peripheral) &= ~TIM_CR1_CKD_CK_INT_MASK; + TIM_CR1(timer_peripheral) |= clock_div; +} + +void timer_enable_preload(u32 timer_peripheral) +{ + TIM_CR1(timer_peripheral) |= TIM_CR1_ARPE; +} + +void timer_disable_preload(u32 timer_peripheral) +{ + TIM_CR1(timer_peripheral) &= ~TIM_CR1_ARPE; +} + +void timer_set_alignment(u32 timer_peripheral, u32 alignment) +{ + alignment &= TIM_CR1_CMS_MASK; + TIM_CR1(timer_peripheral) &= ~TIM_CR1_CMS_MASK; + TIM_CR1(timer_peripheral) |= alignment; +} + +void timer_direction_up(u32 timer_peripheral) +{ + TIM_CR1(timer_peripheral) &= ~TIM_CR1_DIR_DOWN; +} + +void timer_direction_down(u32 timer_peripheral) +{ + TIM_CR1(timer_peripheral) |= TIM_CR1_DIR_DOWN; +} + +void timer_one_shot_mode(u32 timer_peripheral) +{ + TIM_CR1(timer_peripheral) |= TIM_CR1_OPM; +} + +void timer_continuous_mode(u32 timer_peripheral) +{ + TIM_CR1(timer_peripheral) &= ~TIM_CR1_OPM; +} + +void timer_update_on_any(u32 timer_peripheral) +{ + TIM_CR1(timer_peripheral) &= ~TIM_CR1_URS; +} + +void timer_update_on_overflow(u32 timer_peripheral) +{ + TIM_CR1(timer_peripheral) |= TIM_CR1_URS; +} + +void timer_enable_update_event(u32 timer_peripheral) +{ + TIM_CR1(timer_peripheral) &= ~TIM_CR1_UDIS; +} + +void timer_disable_update_event(u32 timer_peripheral) +{ + TIM_CR1(timer_peripheral) |= TIM_CR1_UDIS; +} + +void timer_enable_counter(u32 timer_peripheral) +{ + TIM_CR1(timer_peripheral) |= TIM_CR1_CEN; +} + +void timer_disable_counter(u32 timer_peripheral) +{ + TIM_CR1(timer_peripheral) &= ~TIM_CR1_CEN; +} + +void timer_set_output_idle_state(u32 timer_peripheral, u32 outputs) +{ + TIM_CR2(timer_peripheral) |= outputs & TIM_CR2_OIS_MASK; +} + +void timer_reset_output_idle_state(u32 timer_peripheral, u32 outputs) +{ + TIM_CR2(timer_peripheral) &= ~(outputs & TIM_CR2_OIS_MASK); +} + +void timer_set_ti1_ch123_xor(u32 timer_peripheral) +{ + TIM_CR2(timer_peripheral) |= TIM_CR2_TI1S; +} + +void timer_set_ti1_ch1(u32 timer_peripheral) +{ + TIM_CR2(timer_peripheral) &= ~TIM_CR2_TI1S; +} + +void timer_set_master_mode(u32 timer_peripheral, u32 mode) +{ + TIM_CR2(timer_peripheral) &= ~TIM_CR2_MMS_MASK; + TIM_CR2(timer_peripheral) |= mode; +} + +void timer_set_dma_on_compare_event(u32 timer_peripheral) +{ + TIM_CR2(timer_peripheral) &= ~TIM_CR2_CCDS; +} + +void timer_set_dma_on_update_event(u32 timer_peripheral) +{ + TIM_CR2(timer_peripheral) |= TIM_CR2_CCDS; +} + +void timer_enable_compare_control_update_on_trigger(u32 timer_peripheral) +{ + TIM_CR2(timer_peripheral) |= TIM_CR2_CCUS; +} + +void timer_disable_compare_control_update_on_trigger(u32 timer_peripheral) +{ + TIM_CR2(timer_peripheral) &= ~TIM_CR2_CCUS; +} + +void timer_enable_preload_complementry_enable_bits(u32 timer_peripheral) +{ + TIM_CR2(timer_peripheral) |= TIM_CR2_CCPC; +} + +void timer_disable_preload_complementry_enable_bits(u32 timer_peripheral) +{ + TIM_CR2(timer_peripheral) &= ~TIM_CR2_CCPC; +} + +void timer_set_prescaler(u32 timer_peripheral, u32 value) +{ + TIM_PSC(timer_peripheral) = value; +} + +void timer_set_repetition_counter(u32 timer_peripheral, u32 value) +{ + if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) + TIM_RCR(timer_peripheral) = value; +} + +void timer_set_period(u32 timer_peripheral, u32 period) +{ + TIM_ARR(timer_peripheral) = period; +} + +void timer_enable_oc_clear(u32 timer_peripheral, enum tim_oc_id oc_id) +{ + switch (oc_id) { + case TIM_OC1: + TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1CE; + break; + case TIM_OC2: + TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2CE; + break; + case TIM_OC3: + TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3CE; + break; + case TIM_OC4: + TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4CE; + break; + case TIM_OC1N: + case TIM_OC2N: + case TIM_OC3N: + /* Ignoring as fast enable only applies to the whole channel. */ + break; + } +} + +void timer_disable_oc_clear(u32 timer_peripheral, enum tim_oc_id oc_id) +{ + switch (oc_id) { + case TIM_OC1: + TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC1CE; + break; + case TIM_OC2: + TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC2CE; + break; + case TIM_OC3: + TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC3CE; + break; + case TIM_OC4: + TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC4CE; + break; + case TIM_OC1N: + case TIM_OC2N: + case TIM_OC3N: + /* Ignoring as fast enable only applies to the whole channel. */ + break; + } +} + +void timer_set_oc_fast_mode(u32 timer_peripheral, enum tim_oc_id oc_id) +{ + switch (oc_id) { + case TIM_OC1: + TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1FE; + break; + case TIM_OC2: + TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2FE; + break; + case TIM_OC3: + TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3FE; + break; + case TIM_OC4: + TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4FE; + break; + case TIM_OC1N: + case TIM_OC2N: + case TIM_OC3N: + /* Ignoring as fast enable only applies to the whole channel. */ + break; + } +} + +void timer_set_oc_slow_mode(u32 timer_peripheral, enum tim_oc_id oc_id) +{ + switch (oc_id) { + case TIM_OC1: + TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC1FE; + break; + case TIM_OC2: + TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC2FE; + break; + case TIM_OC3: + TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC3FE; + break; + case TIM_OC4: + TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC4FE; + break; + case TIM_OC1N: + case TIM_OC2N: + case TIM_OC3N: + /* Ignoring as this option applies to the whole channel. */ + break; + } +} + +void timer_set_oc_mode(u32 timer_peripheral, enum tim_oc_id oc_id, + enum tim_oc_mode oc_mode) +{ + switch (oc_id) { + case TIM_OC1: + TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_CC1S_MASK; + TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_CC1S_OUT; + TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC1M_MASK; + switch (oc_mode) { + case TIM_OCM_FROZEN: + TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_FROZEN; + break; + case TIM_OCM_ACTIVE: + TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_ACTIVE; + break; + case TIM_OCM_INACTIVE: + TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_INACTIVE; + break; + case TIM_OCM_TOGGLE: + TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_TOGGLE; + break; + case TIM_OCM_FORCE_LOW: + TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_FORCE_LOW; + break; + case TIM_OCM_FORCE_HIGH: + TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_FORCE_HIGH; + break; + case TIM_OCM_PWM1: + TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_PWM1; + break; + case TIM_OCM_PWM2: + TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_PWM2; + break; + } + break; + case TIM_OC2: + TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_CC2S_MASK; + TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_CC2S_OUT; + TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC2M_MASK; + switch (oc_mode) { + case TIM_OCM_FROZEN: + TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_FROZEN; + break; + case TIM_OCM_ACTIVE: + TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_ACTIVE; + break; + case TIM_OCM_INACTIVE: + TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_INACTIVE; + break; + case TIM_OCM_TOGGLE: + TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_TOGGLE; + break; + case TIM_OCM_FORCE_LOW: + TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_FORCE_LOW; + break; + case TIM_OCM_FORCE_HIGH: + TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_FORCE_HIGH; + break; + case TIM_OCM_PWM1: + TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_PWM1; + break; + case TIM_OCM_PWM2: + TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_PWM2; + break; + } + break; + case TIM_OC3: + TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR2_CC3S_MASK; + TIM_CCMR1(timer_peripheral) |= TIM_CCMR2_CC3S_OUT; + TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC3M_MASK; + switch (oc_mode) { + case TIM_OCM_FROZEN: + TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_FROZEN; + break; + case TIM_OCM_ACTIVE: + TIM_CCMR1(timer_peripheral) |= TIM_CCMR2_OC3M_ACTIVE; + break; + case TIM_OCM_INACTIVE: + TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_INACTIVE; + break; + case TIM_OCM_TOGGLE: + TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_TOGGLE; + break; + case TIM_OCM_FORCE_LOW: + TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_FORCE_LOW; + break; + case TIM_OCM_FORCE_HIGH: + TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_FORCE_HIGH; + break; + case TIM_OCM_PWM1: + TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_PWM1; + break; + case TIM_OCM_PWM2: + TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_PWM2; + break; + } + break; + case TIM_OC4: + TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR2_CC4S_MASK; + TIM_CCMR1(timer_peripheral) |= TIM_CCMR2_CC4S_OUT; + TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC4M_MASK; + switch (oc_mode) { + case TIM_OCM_FROZEN: + TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_FROZEN; + break; + case TIM_OCM_ACTIVE: + TIM_CCMR1(timer_peripheral) |= TIM_CCMR2_OC4M_ACTIVE; + break; + case TIM_OCM_INACTIVE: + TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_INACTIVE; + break; + case TIM_OCM_TOGGLE: + TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_TOGGLE; + break; + case TIM_OCM_FORCE_LOW: + TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_FORCE_LOW; + break; + case TIM_OCM_FORCE_HIGH: + TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_FORCE_HIGH; + break; + case TIM_OCM_PWM1: + TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_PWM1; + break; + case TIM_OCM_PWM2: + TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_PWM2; + break; + } + break; + case TIM_OC1N: + case TIM_OC2N: + case TIM_OC3N: + /* Ignoring as this option applies to the whole channel. */ + break; + } +} + +void timer_enable_oc_preload(u32 timer_peripheral, enum tim_oc_id oc_id) +{ + switch (oc_id) { + case TIM_OC1: + TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1PE; + break; + case TIM_OC2: + TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2PE; + break; + case TIM_OC3: + TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3PE; + break; + case TIM_OC4: + TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4PE; + break; + case TIM_OC1N: + case TIM_OC2N: + case TIM_OC3N: + /* Ignoring as this option applies to the whole channel. */ + break; + } +} + +void timer_disable_oc_preload(u32 timer_peripheral, enum tim_oc_id oc_id) +{ + switch (oc_id) { + case TIM_OC1: + TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC1PE; + break; + case TIM_OC2: + TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC2PE; + break; + case TIM_OC3: + TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC3PE; + break; + case TIM_OC4: + TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC4PE; + break; + case TIM_OC1N: + case TIM_OC2N: + case TIM_OC3N: + /* Ignoring as this option applies to the whole channel. */ + break; + } +} + +void timer_set_oc_polarity_high(u32 timer_peripheral, enum tim_oc_id oc_id) +{ + switch (oc_id) { + case TIM_OC1: + TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC1P; + break; + case TIM_OC2: + TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC2P; + break; + case TIM_OC3: + TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC3P; + break; + case TIM_OC4: + TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC4P; + break; + case TIM_OC1N: + case TIM_OC2N: + case TIM_OC3N: + /* Ignoring as this option applies to TIM1 and TIM8 only. */ + break; + } + + /* Acting for TIM1 and TIM8 only from here onwards. */ + if ((timer_peripheral != TIM1) && (timer_peripheral != TIM8)) + return; + + switch (oc_id) { + case TIM_OC1N: + TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC1NP; + break; + case TIM_OC2N: + TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC2NP; + break; + case TIM_OC3N: + TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC3NP; + break; + case TIM_OC1: + case TIM_OC2: + case TIM_OC3: + case TIM_OC4: + /* Ignoring as this option was already set above. */ + break; + } +} + +void timer_set_oc_polarity_low(u32 timer_peripheral, enum tim_oc_id oc_id) +{ + switch (oc_id) { + case TIM_OC1: + TIM_CCER(timer_peripheral) |= TIM_CCER_CC1P; + break; + case TIM_OC2: + TIM_CCER(timer_peripheral) |= TIM_CCER_CC2P; + break; + case TIM_OC3: + TIM_CCER(timer_peripheral) |= TIM_CCER_CC3P; + break; + case TIM_OC4: + TIM_CCER(timer_peripheral) |= TIM_CCER_CC4P; + break; + case TIM_OC1N: + case TIM_OC2N: + case TIM_OC3N: + /* Ignoring as this option applies to TIM1 and TIM8 only. */ + break; + } + + /* Acting for TIM1 and TIM8 only from here onwards. */ + if ((timer_peripheral != TIM1) && (timer_peripheral != TIM8)) + return; + + switch (oc_id) { + case TIM_OC1N: + TIM_CCER(timer_peripheral) |= TIM_CCER_CC1NP; + break; + case TIM_OC2N: + TIM_CCER(timer_peripheral) |= TIM_CCER_CC2NP; + break; + case TIM_OC3N: + TIM_CCER(timer_peripheral) |= TIM_CCER_CC3NP; + break; + case TIM_OC1: + case TIM_OC2: + case TIM_OC3: + case TIM_OC4: + /* Ignoring as this option was already set above. */ + break; + } +} + +void timer_enable_oc_output(u32 timer_peripheral, enum tim_oc_id oc_id) +{ + switch (oc_id) { + case TIM_OC1: + TIM_CCER(timer_peripheral) |= TIM_CCER_CC1E; + break; + case TIM_OC2: + TIM_CCER(timer_peripheral) |= TIM_CCER_CC2E; + break; + case TIM_OC3: + TIM_CCER(timer_peripheral) |= TIM_CCER_CC3E; + break; + case TIM_OC4: + TIM_CCER(timer_peripheral) |= TIM_CCER_CC4E; + break; + case TIM_OC1N: + case TIM_OC2N: + case TIM_OC3N: + /* Ignoring as this option applies to TIM1 and TIM8 only. */ + break; + } + + /* Acting for TIM1 and TIM8 only from here onwards. */ + if ((timer_peripheral != TIM1) && (timer_peripheral != TIM8)) + return; + + switch (oc_id) { + case TIM_OC1N: + TIM_CCER(timer_peripheral) |= TIM_CCER_CC1NE; + break; + case TIM_OC2N: + TIM_CCER(timer_peripheral) |= TIM_CCER_CC2NE; + break; + case TIM_OC3N: + TIM_CCER(timer_peripheral) |= TIM_CCER_CC3NE; + break; + case TIM_OC1: + case TIM_OC2: + case TIM_OC3: + case TIM_OC4: + /* Ignoring as this option was already set above. */ + break; + } +} + +void timer_disable_oc_output(u32 timer_peripheral, enum tim_oc_id oc_id) +{ + switch (oc_id) { + case TIM_OC1: + TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC1E; + break; + case TIM_OC2: + TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC2E; + break; + case TIM_OC3: + TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC3E; + break; + case TIM_OC4: + TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC4E; + break; + case TIM_OC1N: + case TIM_OC2N: + case TIM_OC3N: + /* Ignoring as this option applies to TIM1 and TIM8 only. */ + break; + } + + /* Acting for TIM1 and TIM8 only from here onwards. */ + if ((timer_peripheral != TIM1) && (timer_peripheral != TIM8)) + return; + + switch (oc_id) { + case TIM_OC1N: + TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC1NE; + break; + case TIM_OC2N: + TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC2NE; + break; + case TIM_OC3N: + TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC3NE; + break; + case TIM_OC1: + case TIM_OC2: + case TIM_OC3: + case TIM_OC4: + /* Ignoring as this option was already set above. */ + break; + } +} + +void timer_set_oc_idle_state_set(u32 timer_peripheral, enum tim_oc_id oc_id) +{ + /* Acting for TIM1 and TIM8 only. */ + if ((timer_peripheral != TIM1) && (timer_peripheral != TIM8)) + return; + + switch (oc_id) { + case TIM_OC1: + TIM_CR2(timer_peripheral) |= TIM_CR2_OIS1; + break; + case TIM_OC1N: + TIM_CR2(timer_peripheral) |= TIM_CR2_OIS1N; + break; + case TIM_OC2: + TIM_CR2(timer_peripheral) |= TIM_CR2_OIS2; + break; + case TIM_OC2N: + TIM_CR2(timer_peripheral) |= TIM_CR2_OIS2N; + break; + case TIM_OC3: + TIM_CR2(timer_peripheral) |= TIM_CR2_OIS3; + break; + case TIM_OC3N: + TIM_CR2(timer_peripheral) |= TIM_CR2_OIS3N; + break; + case TIM_OC4: + TIM_CR2(timer_peripheral) |= TIM_CR2_OIS4; + break; + } +} + +void timer_set_oc_idle_state_unset(u32 timer_peripheral, enum tim_oc_id oc_id) +{ + /* Acting for TIM1 and TIM8 only. */ + if ((timer_peripheral != TIM1) && (timer_peripheral != TIM8)) + return; + + switch (oc_id) { + case TIM_OC1: + TIM_CR2(timer_peripheral) &= ~TIM_CR2_OIS1; + break; + case TIM_OC1N: + TIM_CR2(timer_peripheral) &= ~TIM_CR2_OIS1N; + break; + case TIM_OC2: + TIM_CR2(timer_peripheral) &= ~TIM_CR2_OIS2; + break; + case TIM_OC2N: + TIM_CR2(timer_peripheral) &= ~TIM_CR2_OIS2N; + break; + case TIM_OC3: + TIM_CR2(timer_peripheral) &= ~TIM_CR2_OIS3; + break; + case TIM_OC3N: + TIM_CR2(timer_peripheral) &= ~TIM_CR2_OIS3N; + break; + case TIM_OC4: + TIM_CR2(timer_peripheral) &= ~TIM_CR2_OIS4; + break; + } +} + +void timer_set_oc_value(u32 timer_peripheral, enum tim_oc_id oc_id, u32 value) +{ + switch (oc_id) { + case TIM_OC1: + TIM_CCR1(timer_peripheral) = value; + break; + case TIM_OC2: + TIM_CCR2(timer_peripheral) = value; + break; + case TIM_OC3: + TIM_CCR3(timer_peripheral) = value; + break; + case TIM_OC4: + TIM_CCR4(timer_peripheral) = value; + break; + case TIM_OC1N: + case TIM_OC2N: + case TIM_OC3N: + /* Ignoring as this option applies to the whole channel. */ + break; + } +} + +void timer_enable_break_main_output(u32 timer_peripheral) +{ + if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) + TIM_BDTR(timer_peripheral) |= TIM_BDTR_MOE; +} + +void timer_disable_break_main_output(u32 timer_peripheral) +{ + if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) + TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_MOE; +} + +void timer_enable_break_automatic_output(u32 timer_peripheral) +{ + if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) + TIM_BDTR(timer_peripheral) |= TIM_BDTR_AOE; +} + +void timer_disable_break_automatic_output(u32 timer_peripheral) +{ + if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) + TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_AOE; +} + +void timer_set_break_polarity_high(u32 timer_peripheral) +{ + if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) + TIM_BDTR(timer_peripheral) |= TIM_BDTR_BKP; +} + +void timer_set_break_polarity_low(u32 timer_peripheral) +{ + if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) + TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_BKP; +} + +void timer_enable_break(u32 timer_peripheral) +{ + if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) + TIM_BDTR(timer_peripheral) |= TIM_BDTR_BKE; +} + +void timer_disable_break(u32 timer_peripheral) +{ + if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) + TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_BKE; +} + +void timer_set_enabled_off_state_in_run_mode(u32 timer_peripheral) +{ + if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) + TIM_BDTR(timer_peripheral) |= TIM_BDTR_OSSR; +} + +void timer_set_disabled_off_state_in_run_mode(u32 timer_peripheral) +{ + if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) + TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_OSSR; +} + +void timer_set_enabled_off_state_in_idle_mode(u32 timer_peripheral) +{ + if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) + TIM_BDTR(timer_peripheral) |= TIM_BDTR_OSSI; +} + +void timer_set_disabled_off_state_in_idle_mode(u32 timer_peripheral) +{ + if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) + TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_OSSI; +} + +void timer_set_break_lock(u32 timer_peripheral, u32 lock) +{ + if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) + TIM_BDTR(timer_peripheral) |= lock; +} + +void timer_set_deadtime(u32 timer_peripheral, u32 deadtime) +{ + if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) + TIM_BDTR(timer_peripheral) |= deadtime; +} + +void timer_generate_event(u32 timer_peripheral, u32 event) +{ + TIM_EGR(timer_peripheral) |= event; +} + +u32 timer_get_counter(u32 timer_peripheral) +{ + return TIM_CNT(timer_peripheral); +} diff --git a/lib/stm32f1/usart.c b/lib/stm32f1/usart.c new file mode 100644 index 0000000..ead0ef7 --- /dev/null +++ b/lib/stm32f1/usart.c @@ -0,0 +1,131 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include + +#include + +void usart_set_baudrate(u32 usart, u32 baud) +{ + u32 clock = rcc_ppre1_frequency; + + if (usart == USART1) { + clock = rcc_ppre2_frequency; + } + + /* yes it is as simple as that. The reference manual is + * talking about factional calculation but it seems to be only + * marketting bable to sound awesome. It is nothing else but a + * simple divider to generate the correct baudrate. >_< If I + * am wrong feel free to correct me on that. :) (esden) + */ + USART_BRR(usart) = clock/baud; +} + +void usart_set_databits(u32 usart, u32 bits) +{ + if (bits == 8) + USART_CR1(usart) &= ~USART_CR1_M; /* 8 data bits */ + else + USART_CR1(usart) |= USART_CR1_M; /* 9 data bits */ +} + +void usart_set_stopbits(u32 usart, u32 stopbits) +{ + u32 reg32; + + reg32 = USART_CR2(usart); + reg32 = (reg32 & ~USART_CR2_STOPBITS_MASK) | stopbits; + USART_CR2(usart) = reg32; +} + +void usart_set_parity(u32 usart, u32 parity) +{ + u32 reg32; + + reg32 = USART_CR1(usart); + reg32 = (reg32 & ~USART_PARITY_MASK) | parity; + USART_CR1(usart) = reg32; +} + +void usart_set_mode(u32 usart, u32 mode) +{ + u32 reg32; + + reg32 = USART_CR1(usart); + reg32 = (reg32 & ~USART_MODE_MASK) | mode; + USART_CR1(usart) = reg32; +} + +void usart_set_flow_control(u32 usart, u32 flowcontrol) +{ + u32 reg32; + + reg32 = USART_CR3(usart); + reg32 = (reg32 & ~USART_FLOWCONTROL_MASK) | flowcontrol; + USART_CR3(usart) = reg32; +} + +void usart_enable(u32 usart) +{ + USART_CR1(usart) |= USART_CR1_UE; +} + +void usart_disable(u32 usart) +{ + USART_CR1(usart) &= ~USART_CR1_UE; +} + +void usart_send(u32 usart, u16 data) +{ + /* Send data. */ + USART_DR(usart) = (data & USART_DR_MASK); +} + +u16 usart_recv(u32 usart) +{ + /* Receive data. */ + return USART_DR(usart) & USART_DR_MASK; +} + +void usart_wait_send_ready(u32 usart) +{ + /* Wait until the data has been transferred into the shift register. */ + while ((USART_SR(usart) & USART_SR_TXE) == 0); +} + +void usart_wait_recv_ready(u32 usart) +{ + /* Wait until the data is ready to be received. */ + while ((USART_SR(usart) & USART_SR_RXNE) == 0); +} + +void usart_send_blocking(u32 usart, u16 data) +{ + usart_send(usart, data); + + usart_wait_send_ready(usart); +} + +u16 usart_recv_blocking(u32 usart) +{ + usart_wait_recv_ready(usart); + + return usart_recv(usart); +} diff --git a/lib/stm32f1/vector.c b/lib/stm32f1/vector.c new file mode 100644 index 0000000..39bd9a1 --- /dev/null +++ b/lib/stm32f1/vector.c @@ -0,0 +1,296 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Piotr Esden-Tempski + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#define WEAK __attribute__ ((weak)) + +/* Symbols exported by linker script */ +extern unsigned _etext, _data, _edata, _ebss, _stack; + +void main(void); +void reset_handler(void); +void blocking_handler(void); +void null_handler(void); + +void WEAK nmi_handler(void); +void WEAK hard_fault_handler(void); +void WEAK mem_manage_handler(void); +void WEAK bus_fault_handler(void); +void WEAK usage_fault_handler(void); +void WEAK sv_call_handler(void); +void WEAK debug_monitor_handler(void); +void WEAK pend_sv_handler(void); +void WEAK sys_tick_handler(void); +void WEAK wwdg_isr(void); +void WEAK pvd_isr(void); +void WEAK tamper_isr(void); +void WEAK rtc_isr(void); +void WEAK flash_isr(void); +void WEAK rcc_isr(void); +void WEAK exti0_isr(void); +void WEAK exti1_isr(void); +void WEAK exti2_isr(void); +void WEAK exti3_isr(void); +void WEAK exti4_isr(void); +void WEAK dma1_channel1_isr(void); +void WEAK dma1_channel2_isr(void); +void WEAK dma1_channel3_isr(void); +void WEAK dma1_channel4_isr(void); +void WEAK dma1_channel5_isr(void); +void WEAK dma1_channel6_isr(void); +void WEAK dma1_channel7_isr(void); +void WEAK adc1_2_isr(void); +void WEAK usb_hp_can_tx_isr(void); +void WEAK usb_lp_can_rx0_isr(void); +void WEAK can_rx1_isr(void); +void WEAK can_sce_isr(void); +void WEAK exti9_5_isr(void); +void WEAK tim1_brk_isr(void); +void WEAK tim1_up_isr(void); +void WEAK tim1_trg_com_isr(void); +void WEAK tim1_cc_isr(void); +void WEAK tim2_isr(void); +void WEAK tim3_isr(void); +void WEAK tim4_isr(void); +void WEAK i2c1_ev_isr(void); +void WEAK i2c1_er_isr(void); +void WEAK i2c2_ev_isr(void); +void WEAK i2c2_er_isr(void); +void WEAK spi1_isr(void); +void WEAK spi2_isr(void); +void WEAK usart1_isr(void); +void WEAK usart2_isr(void); +void WEAK usart3_isr(void); +void WEAK exti15_10_isr(void); +void WEAK rtc_alarm_isr(void); +void WEAK usb_wakeup_isr(void); +void WEAK tim8_brk_isr(void); +void WEAK tim8_up_isr(void); +void WEAK tim8_trg_com_isr(void); +void WEAK tim8_cc_isr(void); +void WEAK adc3_isr(void); +void WEAK fsmc_isr(void); +void WEAK sdio_isr(void); +void WEAK tim5_isr(void); +void WEAK spi3_isr(void); +void WEAK usart4_isr(void); +void WEAK usart5_isr(void); +void WEAK tim6_isr(void); +void WEAK tim7_isr(void); +void WEAK dma2_channel1_isr(void); +void WEAK dma2_channel2_isr(void); +void WEAK dma2_channel3_isr(void); +void WEAK dma2_channel4_5_isr(void); +void WEAK dma2_channel5_isr(void); +void WEAK eth_isr(void); +void WEAK eth_wkup_isr(void); +void WEAK can2_tx_isr(void); +void WEAK can2_rx0_isr(void); +void WEAK can2_rx1_isr(void); +void WEAK can2_sce_isr(void); +void WEAK otg_fs_isr(void); + + +__attribute__ ((section(".vectors"))) +void (*const vector_table[]) (void) = { + (void*)&_stack, + reset_handler, + nmi_handler, + hard_fault_handler, + mem_manage_handler, + bus_fault_handler, + usage_fault_handler, + 0, 0, 0, 0, /* Reserved */ + sv_call_handler, + debug_monitor_handler, + 0, /* Reserved */ + pend_sv_handler, + sys_tick_handler, + wwdg_isr, + pvd_isr, + tamper_isr, + rtc_isr, + flash_isr, + rcc_isr, + exti0_isr, + exti1_isr, + exti2_isr, + exti3_isr, + exti4_isr, + dma1_channel1_isr, + dma1_channel2_isr, + dma1_channel3_isr, + dma1_channel4_isr, + dma1_channel5_isr, + dma1_channel6_isr, + dma1_channel7_isr, + adc1_2_isr, + usb_hp_can_tx_isr, + usb_lp_can_rx0_isr, + can_rx1_isr, + can_sce_isr, + exti9_5_isr, + tim1_brk_isr, + tim1_up_isr, + tim1_trg_com_isr, + tim1_cc_isr, + tim2_isr, + tim3_isr, + tim4_isr, + i2c1_ev_isr, + i2c1_er_isr, + i2c2_ev_isr, + i2c2_er_isr, + spi1_isr, + spi2_isr, + usart1_isr, + usart2_isr, + usart3_isr, + exti15_10_isr, + rtc_alarm_isr, + usb_wakeup_isr, + tim8_brk_isr, + tim8_up_isr, + tim8_trg_com_isr, + tim8_cc_isr, + adc3_isr, + fsmc_isr, + sdio_isr, + tim5_isr, + spi3_isr, + usart4_isr, + usart5_isr, + tim6_isr, + tim7_isr, + dma2_channel1_isr, + dma2_channel2_isr, + dma2_channel3_isr, + dma2_channel4_5_isr, + dma2_channel5_isr, + eth_isr, + eth_wkup_isr, + can2_tx_isr, + can2_rx0_isr, + can2_rx1_isr, + can2_sce_isr, + otg_fs_isr, +}; + +void reset_handler(void) +{ + volatile unsigned *src, *dest; + asm("MSR msp, %0" : : "r"(&_stack)); + + for (src = &_etext, dest = &_data; dest < &_edata; src++, dest++) + *dest = *src; + + while (dest < &_ebss) + *dest++ = 0; + + /* Call the application's entry point. */ + main(); +} + +void blocking_handler(void) +{ + while (1) ; +} + +void null_handler(void) +{ + /* Do nothing. */ +} + +#pragma weak nmi_handler = null_handler +#pragma weak hard_fault_handler = blocking_handler +#pragma weak mem_manage_handler = blocking_handler +#pragma weak bus_fault_handler = blocking_handler +#pragma weak usage_fault_handler = blocking_handler +#pragma weak sv_call_handler = null_handler +#pragma weak debug_monitor_handler = null_handler +#pragma weak pend_sv_handler = null_handler +#pragma weak sys_tick_handler = null_handler +#pragma weak wwdg_isr = null_handler +#pragma weak pvd_isr = null_handler +#pragma weak tamper_isr = null_handler +#pragma weak rtc_isr = null_handler +#pragma weak flash_isr = null_handler +#pragma weak rcc_isr = null_handler +#pragma weak exti0_isr = null_handler +#pragma weak exti1_isr = null_handler +#pragma weak exti2_isr = null_handler +#pragma weak exti3_isr = null_handler +#pragma weak exti4_isr = null_handler +#pragma weak dma1_channel1_isr = null_handler +#pragma weak dma1_channel2_isr = null_handler +#pragma weak dma1_channel3_isr = null_handler +#pragma weak dma1_channel4_isr = null_handler +#pragma weak dma1_channel5_isr = null_handler +#pragma weak dma1_channel6_isr = null_handler +#pragma weak dma1_channel7_isr = null_handler +#pragma weak adc1_2_isr = null_handler +#pragma weak usb_hp_can_tx_isr = null_handler +#pragma weak usb_lp_can_rx0_isr = null_handler +#pragma weak can_rx1_isr = null_handler +#pragma weak can_sce_isr = null_handler +#pragma weak exti9_5_isr = null_handler +#pragma weak tim1_brk_isr = null_handler +#pragma weak tim1_up_isr = null_handler +#pragma weak tim1_trg_com_isr = null_handler +#pragma weak tim1_cc_isr = null_handler +#pragma weak tim2_isr = null_handler +#pragma weak tim3_isr = null_handler +#pragma weak tim4_isr = null_handler +#pragma weak i2c1_ev_isr = null_handler +#pragma weak i2c1_er_isr = null_handler +#pragma weak i2c2_ev_isr = null_handler +#pragma weak i2c2_er_isr = null_handler +#pragma weak spi1_isr = null_handler +#pragma weak spi2_isr = null_handler +#pragma weak usart1_isr = null_handler +#pragma weak usart2_isr = null_handler +#pragma weak usart3_isr = null_handler +#pragma weak exti15_10_isr = null_handler +#pragma weak rtc_alarm_isr = null_handler +#pragma weak usb_wakeup_isr = null_handler +#pragma weak tim8_brk_isr = null_handler +#pragma weak tim8_up_isr = null_handler +#pragma weak tim8_trg_com_isr = null_handler +#pragma weak tim8_cc_isr = null_handler +#pragma weak adc3_isr = null_handler +#pragma weak fsmc_isr = null_handler +#pragma weak sdio_isr = null_handler +#pragma weak tim5_isr = null_handler +#pragma weak spi3_isr = null_handler +#pragma weak usart4_isr = null_handler +#pragma weak usart5_isr = null_handler +#pragma weak tim6_isr = null_handler +#pragma weak tim7_isr = null_handler +#pragma weak dma2_channel1_isr = null_handler +#pragma weak dma2_channel2_isr = null_handler +#pragma weak dma2_channel3_isr = null_handler +#pragma weak dma2_channel4_5_isr = null_handler +#pragma weak dma2_channel5_isr +#pragma weak eth_isr = null_handler +#pragma weak eth_wkup_isr = null_handler +#pragma weak can2_tx_isr = null_handler +#pragma weak can2_rx0_isr = null_handler +#pragma weak can2_rx1_isr = null_handler +#pragma weak can2_sce_isr = null_handler +#pragma weak otg_fs_isr = null_handler + -- cgit v1.2.3 From 76700510e08007fcbb461c22e71649bfa2bf95de Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Mon, 12 Sep 2011 20:48:41 -0700 Subject: Ability to choose memorymap for stm_common headers with define. --- include/libopencm3/stm32_common/can.h | 2 +- include/libopencm3/stm32_common/crc.h | 2 +- include/libopencm3/stm32_common/dbgmcu.h | 2 +- include/libopencm3/stm32_common/exti.h | 2 +- include/libopencm3/stm32_common/fsmc.h | 2 +- include/libopencm3/stm32_common/iwdg.h | 2 +- include/libopencm3/stm32_common/memorymap.h | 35 +++++++++++++++++++++++++++++ include/libopencm3/stm32_common/wwdg.h | 2 +- 8 files changed, 42 insertions(+), 7 deletions(-) create mode 100644 include/libopencm3/stm32_common/memorymap.h diff --git a/include/libopencm3/stm32_common/can.h b/include/libopencm3/stm32_common/can.h index 1aa95a1..eeac5d8 100644 --- a/include/libopencm3/stm32_common/can.h +++ b/include/libopencm3/stm32_common/can.h @@ -20,7 +20,7 @@ #ifndef LIBOPENCM3_CAN_H #define LIBOPENCM3_CAN_H -#include +#include #include /* --- Convenience macros -------------------------------------------------- */ diff --git a/include/libopencm3/stm32_common/crc.h b/include/libopencm3/stm32_common/crc.h index 5ad866e..a5bc35a 100644 --- a/include/libopencm3/stm32_common/crc.h +++ b/include/libopencm3/stm32_common/crc.h @@ -20,7 +20,7 @@ #ifndef LIBOPENCM3_CRC_H #define LIBOPENCM3_CRC_H -#include +#include #include /* --- CRC registers ------------------------------------------------------- */ diff --git a/include/libopencm3/stm32_common/dbgmcu.h b/include/libopencm3/stm32_common/dbgmcu.h index e753f5e..e6771a2 100644 --- a/include/libopencm3/stm32_common/dbgmcu.h +++ b/include/libopencm3/stm32_common/dbgmcu.h @@ -20,7 +20,7 @@ #ifndef LIBOPENCM3_STM32_DBGMCU_H #define LIBOPENCM3_STM32_DBGMCU_H -#include +#include #include /* --- DBGMCU registers ---------------------------------------------------- */ diff --git a/include/libopencm3/stm32_common/exti.h b/include/libopencm3/stm32_common/exti.h index 19ab547..caecee5 100644 --- a/include/libopencm3/stm32_common/exti.h +++ b/include/libopencm3/stm32_common/exti.h @@ -20,7 +20,7 @@ #ifndef LIBOPENCM3_EXTI_H #define LIBOPENCM3_EXTI_H -#include +#include #include /* --- EXTI registers ------------------------------------------------------ */ diff --git a/include/libopencm3/stm32_common/fsmc.h b/include/libopencm3/stm32_common/fsmc.h index 1d318e3..5ccd1d1 100644 --- a/include/libopencm3/stm32_common/fsmc.h +++ b/include/libopencm3/stm32_common/fsmc.h @@ -20,7 +20,7 @@ #ifndef LIBOPENCM3_FSMC_H #define LIBOPENCM3_FSMC_H -#include +#include #include /* --- Convenience macros -------------------------------------------------- */ diff --git a/include/libopencm3/stm32_common/iwdg.h b/include/libopencm3/stm32_common/iwdg.h index bf2784a..67f2961 100644 --- a/include/libopencm3/stm32_common/iwdg.h +++ b/include/libopencm3/stm32_common/iwdg.h @@ -20,7 +20,7 @@ #ifndef LIBOPENCM3_IWDG_H #define LIBOPENCM3_IWDG_H -#include +#include #include /* --- IWDG registers ------------------------------------------------------ */ diff --git a/include/libopencm3/stm32_common/memorymap.h b/include/libopencm3/stm32_common/memorymap.h new file mode 100644 index 0000000..0d0c60f --- /dev/null +++ b/include/libopencm3/stm32_common/memorymap.h @@ -0,0 +1,35 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Fergus Noble + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_MEMORYMAP_COMMON_H +#define LIBOPENCM3_MEMORYMAP_COMMON_H + +#include + +#ifdef STM32F1 +#include +#else +#ifdef STM32F1 +#include +#else +#error "stm32 family not defined." +#endif +#endif + +#endif diff --git a/include/libopencm3/stm32_common/wwdg.h b/include/libopencm3/stm32_common/wwdg.h index 552d02e..e1787c8 100644 --- a/include/libopencm3/stm32_common/wwdg.h +++ b/include/libopencm3/stm32_common/wwdg.h @@ -20,7 +20,7 @@ #ifndef LIBOPENCM3_WWDG_H #define LIBOPENCM3_WWDG_H -#include +#include #include /* --- WWDG registers ------------------------------------------------------ */ -- cgit v1.2.3 From e77bbff125d603f31899f505242577cca9ca7b43 Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Mon, 12 Sep 2011 20:48:56 -0700 Subject: Fixing small typo. --- include/libopencm3/stm32f1/spi.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/libopencm3/stm32f1/spi.h b/include/libopencm3/stm32f1/spi.h index 726310a..d85c0dc 100644 --- a/include/libopencm3/stm32f1/spi.h +++ b/include/libopencm3/stm32f1/spi.h @@ -160,7 +160,7 @@ #define SPI_CR1_CPHA_CLK_TRANSITION_2 (1 << 0) #define SPI_CR1_CPHA (1 << 0) -/* --- SPI_CR1 values ------------------------------------------------------ */ +/* --- SPI_CR2 values ------------------------------------------------------ */ /* Bits [15:8]: Reserved. Forced to 0 by hardware. */ -- cgit v1.2.3 From 6bf33af01070a7559bd5a129f5a4cde7f7e6151a Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Mon, 12 Sep 2011 20:49:43 -0700 Subject: Moved pwr.h to stm_common and added F2 series specific extensions in its own header. --- include/libopencm3/stm32_common/pwr.h | 81 +++++++++++++++++++++++++++++++++++ include/libopencm3/stm32f1/pwr.h | 81 ----------------------------------- include/libopencm3/stm32f2/pwr.h | 42 ++++++++++++++++++ 3 files changed, 123 insertions(+), 81 deletions(-) create mode 100644 include/libopencm3/stm32_common/pwr.h delete mode 100644 include/libopencm3/stm32f1/pwr.h create mode 100644 include/libopencm3/stm32f2/pwr.h diff --git a/include/libopencm3/stm32_common/pwr.h b/include/libopencm3/stm32_common/pwr.h new file mode 100644 index 0000000..4af8480 --- /dev/null +++ b/include/libopencm3/stm32_common/pwr.h @@ -0,0 +1,81 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_PWR_H +#define LIBOPENCM3_PWR_H + +#include +#include + +/* --- PWR registers ------------------------------------------------------- */ + +/* Power control register (PWR_CR) */ +#define PWR_CR MMIO32(POWER_CONTROL_BASE + 0x00) + +/* Power control/status register (PWR_CSR) */ +#define PWR_CSR MMIO32(POWER_CONTROL_BASE + 0x04) + +/* --- PWR_CR values ------------------------------------------------------- */ + +/* DBP: Disable backup domain write protection */ +#define PWR_CR_DBP (1 << 8) + +/* PLS[7:5]: PVD level selection */ +#define PWR_CR_PLS_LSB 5 +#define PWR_CR_PLS_2V2 0x0 +#define PWR_CR_PLS_2V3 0x1 +#define PWR_CR_PLS_2V4 0x2 +#define PWR_CR_PLS_2V5 0x3 +#define PWR_CR_PLS_2V6 0x4 +#define PWR_CR_PLS_2V7 0x5 +#define PWR_CR_PLS_2V8 0x6 +#define PWR_CR_PLS_2V9 0x7 + +/* PVDE: Power voltage detector enable */ +#define PWR_CR_PVDE (1 << 4) + +/* CSBF: Clear standby flag */ +#define PWR_CR_CSBF (1 << 3) + +/* CWUF: Clear wakeup flag */ +#define PWR_CR_CWUF (1 << 2) + +/* PDDS: Power down deepsleep */ +#define PWR_CR_PDDS (1 << 1) + +/* LPDS: Low-power deepsleep */ +#define PWR_CR_LPDS (1 << 0) + +/* --- PWR_CSR values ------------------------------------------------------ */ + +/* EWUP: Enable WKUP pin */ +#define PWR_CSR_EWUP (1 << 8) + +/* PVDO: PVD output */ +#define PWR_CSR_PVDO (1 << 2) + +/* SBF: Standby flag */ +#define PWR_CSR_SBF (1 << 1) + +/* WUF: Wakeup flag */ +#define PWR_CSR_WUF (1 << 0) + +/* --- PWR function prototypes ------------------------------------------- */ + +#endif diff --git a/include/libopencm3/stm32f1/pwr.h b/include/libopencm3/stm32f1/pwr.h deleted file mode 100644 index e5b9804..0000000 --- a/include/libopencm3/stm32f1/pwr.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_PWR_H -#define LIBOPENCM3_PWR_H - -#include -#include - -/* --- PWR registers ------------------------------------------------------- */ - -/* Power control register (PWR_CR) */ -#define PWR_CR MMIO32(POWER_CONTROL_BASE + 0x00) - -/* Power control/status register (PWR_CSR) */ -#define PWR_CSR MMIO32(POWER_CONTROL_BASE + 0x04) - -/* --- PWR_CR values ------------------------------------------------------- */ - -/* DBP: Disable backup domain write protection */ -#define PWR_CR_DBP (1 << 8) - -/* PLS[7:5]: PVD level selection */ -#define PWR_CR_PLS_LSB 5 -#define PWR_CR_PLS_2V2 0x0 -#define PWR_CR_PLS_2V3 0x1 -#define PWR_CR_PLS_2V4 0x2 -#define PWR_CR_PLS_2V5 0x3 -#define PWR_CR_PLS_2V6 0x4 -#define PWR_CR_PLS_2V7 0x5 -#define PWR_CR_PLS_2V8 0x6 -#define PWR_CR_PLS_2V9 0x7 - -/* PVDE: Power voltage detector enable */ -#define PWR_CR_PVDE (1 << 4) - -/* CSBF: Clear standby flag */ -#define PWR_CR_CSBF (1 << 3) - -/* CWUF: Clear wakeup flag */ -#define PWR_CR_CWUF (1 << 2) - -/* PDDS: Power down deepsleep */ -#define PWR_CR_PDDS (1 << 1) - -/* LPDS: Low-power deepsleep */ -#define PWR_CR_LPDS (1 << 0) - -/* --- PWR_CSR values ------------------------------------------------------ */ - -/* EWUP: Enable WKUP pin */ -#define PWR_CSR_EWUP (1 << 8) - -/* PVDO: PVD output */ -#define PWR_CSR_PVDO (1 << 2) - -/* SBF: Standby flag */ -#define PWR_CSR_SBF (1 << 1) - -/* WUF: Wakeup flag */ -#define PWR_CSR_WUF (1 << 0) - -/* --- PWR function prototypes ------------------------------------------- */ - -#endif diff --git a/include/libopencm3/stm32f2/pwr.h b/include/libopencm3/stm32f2/pwr.h new file mode 100644 index 0000000..8e8517e --- /dev/null +++ b/include/libopencm3/stm32f2/pwr.h @@ -0,0 +1,42 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Fergus Noble + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_PWR_F2_H +#define LIBOPENCM3_PWR_F2_H + +#include +#include + + +/* + * This file extends the version in stm_common with definitions only + * applicable to the STM32F2 series of devices. + */ + +/* --- PWR_CR values ------------------------------------------------------- */ + +/* FPDS: Flash power down in stop mode, only available in F2 family devices. */ +#define PWR_CR_FPDS (1 << 9) + +/* --- PWR_CSR values ------------------------------------------------------ */ + +/* BRE: Backup regulator enable */ +#define PWR_CSR_BRE (1 << 9) + +#endif -- cgit v1.2.3 From ac18a048696a675cc05acec91a6686164e0df29f Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Mon, 12 Sep 2011 21:11:09 -0700 Subject: Moved spi header over to common and created F2 specific header. --- include/libopencm3/stm32_common/spi.h | 331 ++++++++++++++++++++++++++++++++++ include/libopencm3/stm32f1/spi.h | 331 ---------------------------------- include/libopencm3/stm32f2/spi.h | 42 +++++ 3 files changed, 373 insertions(+), 331 deletions(-) create mode 100644 include/libopencm3/stm32_common/spi.h delete mode 100644 include/libopencm3/stm32f1/spi.h create mode 100644 include/libopencm3/stm32f2/spi.h diff --git a/include/libopencm3/stm32_common/spi.h b/include/libopencm3/stm32_common/spi.h new file mode 100644 index 0000000..3249457 --- /dev/null +++ b/include/libopencm3/stm32_common/spi.h @@ -0,0 +1,331 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_SPI_H +#define LIBOPENCM3_SPI_H + +#include +#include + +/* Registers can be accessed as 16bit or 32bit values. */ + +/* --- Convenience macros -------------------------------------------------- */ + +#define SPI1 SPI1_BASE +#define SPI2 SPI2_I2S_BASE +#define SPI3 SPI3_I2S_BASE + +/* --- SPI registers ------------------------------------------------------- */ + +/* Control register 1 (SPIx_CR1) */ +#define SPI_CR1(spi_base) MMIO32(spi_base + 0x00) +#define SPI1_CR1 SPI_CR1(SPI1_BASE) +#define SPI2_CR1 SPI_CR1(SPI2_I2S_BASE) +#define SPI3_CR1 SPI_CR1(SPI3_I2S_BASE) + +/* Control register 2 (SPIx_CR2) */ +#define SPI_CR2(spi_base) MMIO32(spi_base + 0x04) +#define SPI1_CR2 SPI_CR2(SPI1_BASE) +#define SPI2_CR2 SPI_CR2(SPI2_I2S_BASE) +#define SPI3_CR2 SPI_CR2(SPI3_I2S_BASE) + +/* Status register (SPIx_SR) */ +#define SPI_SR(spi_base) MMIO32(spi_base + 0x08) +#define SPI1_SR SPI_SR(SPI1_BASE) +#define SPI2_SR SPI_SR(SPI2_I2S_BASE) +#define SPI3_SR SPI_SR(SPI3_I2S_BASE) + +/* Data register (SPIx_DR) */ +#define SPI_DR(spi_base) MMIO32(spi_base + 0x0c) +#define SPI1_DR SPI_DR(SPI1_BASE) +#define SPI2_DR SPI_DR(SPI2_I2S_BASE) +#define SPI3_DR SPI_DR(SPI3_I2S_BASE) + +/* CRC polynomial register (SPIx_CRCPR) */ +/* Note: Not used in I2S mode. */ +#define SPI_CRCPR(spi_base) MMIO32(spi_base + 0x10) +#define SPI1_CRCPR SPI_CRCPR(SPI1_BASE) +#define SPI2_CRCPR SPI_CRCPR(SPI2_I2S_BASE) +#define SPI3_CRCPR SPI_CRCPR(SPI3_I2S_BASE) + +/* RX CRC register (SPIx_RXCRCR) */ +/* Note: Not used in I2S mode. */ +#define SPI_RXCRCR(spi_base) MMIO32(spi_base + 0x14) +#define SPI1_RXCRCR SPI_RXCRCR(SPI1_BASE) +#define SPI2_RXCRCR SPI_RXCRCR(SPI2_I2S_BASE) +#define SPI3_RXCRCR SPI_RXCRCR(SPI3_I2S_BASE) + +/* TX CRC register (SPIx_RXCRCR) */ +/* Note: Not used in I2S mode. */ +#define SPI_TXCRCR(spi_base) MMIO32(spi_base + 0x18) +#define SPI1_TXCRCR SPI_TXCRCR(SPI1_BASE) +#define SPI2_TXCRCR SPI_TXCRCR(SPI2_I2S_BASE) +#define SPI3_TXCRCR SPI_TXCRCR(SPI3_I2S_BASE) + +/* I2S configuration register (SPIx_I2SCFGR) */ +#define SPI_I2SCFGR(spi_base) MMIO32(spi_base + 0x1c) +#define SPI1_I2SCFGR SPI_I2SCFGR(SPI1_BASE) +#define SPI2_I2SCFGR SPI_I2SCFGR(SPI2_I2S_BASE) +#define SPI3_I2SCFGR SPI_I2SCFGR(SPI3_I2S_BASE) + +/* I2S prescaler register (SPIx_I2SPR) */ +#define SPI_I2SPR(spi_base) MMIO32(spi_base + 0x20) +#define SPI1_I2SPR SPI_I2SPR(SPI1_BASE) +#define SPI2_I2SPR SPI_I2SPR(SPI2_I2S_BASE) +#define SPI3_I2SPR SPI_I2SPR(SPI3_I2S_BASE) + +/* --- SPI_CR1 values ------------------------------------------------------ */ + +/* Note: None of the CR1 bits are used in I2S mode. */ + +/* BIDIMODE: Bidirectional data mode enable */ +#define SPI_CR1_BIDIMODE_2LINE_UNIDIR (0 << 15) +#define SPI_CR1_BIDIMODE_1LINE_BIDIR (1 << 15) +#define SPI_CR1_BIDIMODE (1 << 15) + +/* BIDIOE: Output enable in bidirectional mode */ +#define SPI_CR1_BIDIOE (1 << 14) + +/* CRCEN: Hardware CRC calculation enable */ +#define SPI_CR1_CRCEN (1 << 13) + +/* CRCNEXT: Transmit CRC next */ +#define SPI_CR1_CRCNEXT (1 << 12) + +/* DFF: Data frame format */ +#define SPI_CR1_DFF_8BIT (0 << 11) +#define SPI_CR1_DFF_16BIT (1 << 11) +#define SPI_CR1_DFF (1 << 11) + +/* RXONLY: Receive only */ +#define SPI_CR1_RXONLY (1 << 10) + +/* SSM: Software slave management */ +#define SPI_CR1_SSM (1 << 9) + +/* SSI: Internal slave select */ +#define SPI_CR1_SSI (1 << 8) + +/* LSBFIRST: Frame format */ +#define SPI_CR1_MSBFIRST (0 << 7) +#define SPI_CR1_LSBFIRST (1 << 7) + +/* SPE: SPI enable */ +#define SPI_CR1_SPE (1 << 6) + +/* BR[2:0]: Baud rate control */ +#define SPI_CR1_BAUDRATE_FPCLK_DIV_2 (0x00 << 3) +#define SPI_CR1_BAUDRATE_FPCLK_DIV_4 (0x01 << 3) +#define SPI_CR1_BAUDRATE_FPCLK_DIV_8 (0x02 << 3) +#define SPI_CR1_BAUDRATE_FPCLK_DIV_16 (0x03 << 3) +#define SPI_CR1_BAUDRATE_FPCLK_DIV_32 (0x04 << 3) +#define SPI_CR1_BAUDRATE_FPCLK_DIV_64 (0x05 << 3) +#define SPI_CR1_BAUDRATE_FPCLK_DIV_128 (0x06 << 3) +#define SPI_CR1_BAUDRATE_FPCLK_DIV_256 (0x07 << 3) +#define SPI_CR1_BR_FPCLK_DIV_2 0x0 +#define SPI_CR1_BR_FPCLK_DIV_4 0x1 +#define SPI_CR1_BR_FPCLK_DIV_8 0x2 +#define SPI_CR1_BR_FPCLK_DIV_16 0x3 +#define SPI_CR1_BR_FPCLK_DIV_32 0x4 +#define SPI_CR1_BR_FPCLK_DIV_64 0x5 +#define SPI_CR1_BR_FPCLK_DIV_128 0x6 +#define SPI_CR1_BR_FPCLK_DIV_256 0x7 + +/* MSTR: Master selection */ +#define SPI_CR1_MSTR (1 << 2) + +/* CPOL: Clock polarity */ +#define SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE (0 << 1) +#define SPI_CR1_CPOL_CLK_TO_1_WHEN_IDLE (1 << 1) +#define SPI_CR1_CPOL (1 << 1) + +/* CPHA: Clock phase */ +#define SPI_CR1_CPHA_CLK_TRANSITION_1 (0 << 0) +#define SPI_CR1_CPHA_CLK_TRANSITION_2 (1 << 0) +#define SPI_CR1_CPHA (1 << 0) + +/* --- SPI_CR2 values ------------------------------------------------------ */ + +/* Bits [15:8]: Reserved. Forced to 0 by hardware. */ + +/* TXEIE: Tx buffer empty interrupt enable */ +#define SPI_CR2_TXEIE (1 << 7) + +/* RXNEIE: RX buffer not empty interrupt enable */ +#define SPI_CR2_RXNEIE (1 << 6) + +/* ERRIE: Error interrupt enable */ +#define SPI_CR2_ERRIE (1 << 5) + +/* Bits [4:3]: Reserved. Forced to 0 by hardware. */ + +/* SSOE: SS output enable */ +#define SPI_CR2_SSOE (1 << 2) + +/* TXDMAEN: Tx buffer DMA enable */ +#define SPI_CR2_TXDMAEN (1 << 1) + +/* RXDMAEN: Rx buffer DMA enable */ +#define SPI_CR2_RXDMAEN (1 << 0) + +/* --- SPI_SR values ------------------------------------------------------- */ + +/* Bits [15:8]: Reserved. Forced to 0 by hardware. */ + +/* BSY: Busy flag */ +#define SPI_SR_BSY (1 << 7) + +/* OVR: Overrun flag */ +#define SPI_SR_OVR (1 << 6) + +/* MODF: Mode fault */ +#define SPI_SR_MODF (1 << 5) + +/* CRCERR: CRC error flag */ +#define SPI_SR_CRCERR (1 << 4) + +/* UDR: Underrun flag */ +#define SPI_SR_UDR (1 << 3) + +/* CHSIDE: Channel side */ +#define SPI_SR_CHSIDE (1 << 2) + +/* TXE: Transmit buffer empty */ +#define SPI_SR_TXE (1 << 1) + +/* RXNE: Receive buffer not empty */ +#define SPI_SR_RXNE (1 << 0) + +/* --- SPI_DR values ------------------------------------------------------- */ + +/* SPI_DR[15:0]: Data Register. */ + +/* --- SPI_CRCPR values ---------------------------------------------------- */ + +/* SPI_CRCPR [15:0]: CRC Polynomial Register. */ + +/* --- SPI_RXCRCR values --------------------------------------------------- */ + +/* SPI_RXCRCR [15:0]: RX CRC Register. */ + +/* --- SPI_TXCRCR values --------------------------------------------------- */ + +/* SPI_TXCRCR [15:0]: TX CRC Register. */ + +/* --- SPI_I2SCFGR values -------------------------------------------------- */ + +/* Bits [15:12]: Reserved. Forced to 0 by hardware. */ + +/* I2SMOD: I2S mode selection */ +#define SPI_I2SCFGR_I2SMOD (1 << 11) + +/* I2SE: I2S Enable */ +#define SPI_I2SCFGR_I2SE (1 << 10) + +/* I2SCFG[9:8]: I2S configuration mode */ +#define SPI_I2SCFGR_I2SCFG_LSB 8 +#define SPI_I2SCFGR_I2SCFG_SLAVE_TRANSMIT 0x0 +#define SPI_I2SCFGR_I2SCFG_SLAVE_RECEIVE 0x1 +#define SPI_I2SCFGR_I2SCFG_MASTER_TRANSMIT 0x2 +#define SPI_I2SCFGR_I2SCFG_MASTER_RECEIVE 0x3 + +/* PCMSYNC: PCM frame synchronization */ +#define SPI_I2SCFGR_PCMSYNC (1 << 7) + +/* Bit 6: Reserved. Forced to 0 by hardware. */ + +/* I2SSTD[5:4]: I2S standard selection */ +#define SPI_I2SCFGR_I2SSTD_LSB 4 +#define SPI_I2SCFGR_I2SSTD_I2S_PHILLIPS 0x0 +#define SPI_I2SCFGR_I2SSTD_MSB_JUSTIFIED 0x1 +#define SPI_I2SCFGR_I2SSTD_LSB_JUSTIFIED 0x2 +#define SPI_I2SCFGR_I2SSTD_PCM 0x3 + +/* CKPOL: Steady state clock polarity */ +#define SPI_I2SCFGR_CKPOL (1 << 3) + +/* DATLEN[2:1]: Data length to be transferred */ +#define SPI_I2SCFGR_DATLEN_LSB 1 +#define SPI_I2SCFGR_DATLEN_16BIT 0x0 +#define SPI_I2SCFGR_DATLEN_24BIT 0x1 +#define SPI_I2SCFGR_DATLEN_32BIT 0x2 + +/* CHLEN: Channel length */ +#define SPI_I2SCFGR_CHLEN (1 << 0) + +/* --- SPI_I2SPR values ---------------------------------------------------- */ + +/* Bits [15:10]: Reserved. Forced to 0 by hardware. */ + +/* MCKOE: Master clock output enable */ +#define SPI_I2SPR_MCKOE (1 << 9) + +/* ODD: Odd factor for the prescaler */ +#define SPI_I2SPR_ODD (1 << 8) + +/* I2SDIV[7:0]: I2S Linear prescaler */ +/* 0 and 1 are forbidden values */ + +/* --- Function prototypes ------------------------------------------------- */ + +int spi_init_master(u32 spi, u32 br, u32 cpol, u32 cpha, u32 dff, u32 lsbfirst); +void spi_enable(u32 spi); +void spi_disable(u32 spi); +void spi_write(u32 spi, u16 data); +void spi_send(u32 spi, u16 data); +u16 spi_read(u32 spi); +void spi_set_bidirectional_mode(u32 spi); +void spi_set_unidirectional_mode(u32 spi); +void spi_set_bidirectional_receive_only_mode(u32 spi); +void spi_set_bidirectional_transmit_only_mode(u32 spi); +void spi_enable_crc(u32 spi); +void spi_disable_crc(u32 spi); +void spi_set_next_tx_from_buffer(u32 spi); +void spi_set_next_tx_from_crc(u32 spi); +void spi_set_dff_8bit(u32 spi); +void spi_set_dff_16bit(u32 spi); +void spi_set_full_duplex_mode(u32 spi); +void spi_set_receive_only_mode(u32 spi); +void spi_disable_software_slave_management(u32 spi); +void spi_enable_software_slave_management(u32 spi); +void spi_set_nss_high(u32 spi); +void spi_set_nss_low(u32 spi); +void spi_send_lsb_first(u32 spi); +void spi_send_msb_first(u32 spi); +void spi_set_baudrate_prescaler(u32 spi, u8 baudrate); +void spi_set_master_mode(u32 spi); +void spi_set_slave_mode(u32 spi); +void spi_set_clock_polarity_1(u32 spi); +void spi_set_clock_polarity_0(u32 spi); +void spi_set_clock_phase_1(u32 spi); +void spi_set_clock_phase_0(u32 spi); +void spi_enable_tx_buffer_empty_interrupt(u32 spi); +void spi_disable_tx_buffer_empty_interrupt(u32 spi); +void spi_enable_rx_buffer_not_empty_interrupt(u32 spi); +void spi_disable_rx_buffer_not_empty_interrupt(u32 spi); +void spi_enable_error_interrupt(u32 spi); +void spi_disable_error_interrupt(u32 spi); +void spi_enable_ss_output(u32 spi); +void spi_disable_ss_output(u32 spi); +void spi_enable_tx_dma(u32 spi); +void spi_disable_tx_dma(u32 spi); +void spi_enable_rx_dma(u32 spi); +void spi_disable_rx_dma(u32 spi); + +#endif diff --git a/include/libopencm3/stm32f1/spi.h b/include/libopencm3/stm32f1/spi.h deleted file mode 100644 index d85c0dc..0000000 --- a/include/libopencm3/stm32f1/spi.h +++ /dev/null @@ -1,331 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_SPI_H -#define LIBOPENCM3_SPI_H - -#include -#include - -/* Registers can be accessed as 16bit or 32bit values. */ - -/* --- Convenience macros -------------------------------------------------- */ - -#define SPI1 SPI1_BASE -#define SPI2 SPI2_I2S_BASE -#define SPI3 SPI3_I2S_BASE - -/* --- SPI registers ------------------------------------------------------- */ - -/* Control register 1 (SPIx_CR1) */ -#define SPI_CR1(spi_base) MMIO32(spi_base + 0x00) -#define SPI1_CR1 SPI_CR1(SPI1_BASE) -#define SPI2_CR1 SPI_CR1(SPI2_I2S_BASE) -#define SPI3_CR1 SPI_CR1(SPI3_I2S_BASE) - -/* Control register 2 (SPIx_CR2) */ -#define SPI_CR2(spi_base) MMIO32(spi_base + 0x04) -#define SPI1_CR2 SPI_CR2(SPI1_BASE) -#define SPI2_CR2 SPI_CR2(SPI2_I2S_BASE) -#define SPI3_CR2 SPI_CR2(SPI3_I2S_BASE) - -/* Status register (SPIx_SR) */ -#define SPI_SR(spi_base) MMIO32(spi_base + 0x08) -#define SPI1_SR SPI_SR(SPI1_BASE) -#define SPI2_SR SPI_SR(SPI2_I2S_BASE) -#define SPI3_SR SPI_SR(SPI3_I2S_BASE) - -/* Data register (SPIx_DR) */ -#define SPI_DR(spi_base) MMIO32(spi_base + 0x0c) -#define SPI1_DR SPI_DR(SPI1_BASE) -#define SPI2_DR SPI_DR(SPI2_I2S_BASE) -#define SPI3_DR SPI_DR(SPI3_I2S_BASE) - -/* CRC polynomial register (SPIx_CRCPR) */ -/* Note: Not used in I2S mode. */ -#define SPI_CRCPR(spi_base) MMIO32(spi_base + 0x10) -#define SPI1_CRCPR SPI_CRCPR(SPI1_BASE) -#define SPI2_CRCPR SPI_CRCPR(SPI2_I2S_BASE) -#define SPI3_CRCPR SPI_CRCPR(SPI3_I2S_BASE) - -/* RX CRC register (SPIx_RXCRCR) */ -/* Note: Not used in I2S mode. */ -#define SPI_RXCRCR(spi_base) MMIO32(spi_base + 0x14) -#define SPI1_RXCRCR SPI_RXCRCR(SPI1_BASE) -#define SPI2_RXCRCR SPI_RXCRCR(SPI2_I2S_BASE) -#define SPI3_RXCRCR SPI_RXCRCR(SPI3_I2S_BASE) - -/* TX CRC register (SPIx_RXCRCR) */ -/* Note: Not used in I2S mode. */ -#define SPI_TXCRCR(spi_base) MMIO32(spi_base + 0x18) -#define SPI1_TXCRCR SPI_TXCRCR(SPI1_BASE) -#define SPI2_TXCRCR SPI_TXCRCR(SPI2_I2S_BASE) -#define SPI3_TXCRCR SPI_TXCRCR(SPI3_I2S_BASE) - -/* I2S configuration register (SPIx_I2SCFGR) */ -#define SPI_I2SCFGR(spi_base) MMIO32(spi_base + 0x1c) -#define SPI1_I2SCFGR SPI_I2SCFGR(SPI1_BASE) -#define SPI2_I2SCFGR SPI_I2SCFGR(SPI2_I2S_BASE) -#define SPI3_I2SCFGR SPI_I2SCFGR(SPI3_I2S_BASE) - -/* I2S prescaler register (SPIx_I2SPR) */ -#define SPI_I2SPR(spi_base) MMIO32(spi_base + 0x20) -#define SPI1_I2SPR SPI_I2SPR(SPI1_BASE) -#define SPI2_I2SPR SPI_I2SPR(SPI2_I2S_BASE) -#define SPI3_I2SPR SPI_I2SPR(SPI3_I2S_BASE) - -/* --- SPI_CR1 values ------------------------------------------------------ */ - -/* Note: None of the CR1 bits are used in I2S mode. */ - -/* BIDIMODE: Bidirectional data mode enable */ -#define SPI_CR1_BIDIMODE_2LINE_UNIDIR (0 << 15) -#define SPI_CR1_BIDIMODE_1LINE_BIDIR (1 << 15) -#define SPI_CR1_BIDIMODE (1 << 15) - -/* BIDIOE: Output enable in bidirectional mode */ -#define SPI_CR1_BIDIOE (1 << 14) - -/* CRCEN: Hardware CRC calculation enable */ -#define SPI_CR1_CRCEN (1 << 13) - -/* CRCNEXT: Transmit CRC next */ -#define SPI_CR1_CRCNEXT (1 << 12) - -/* DFF: Data frame format */ -#define SPI_CR1_DFF_8BIT (0 << 11) -#define SPI_CR1_DFF_16BIT (1 << 11) -#define SPI_CR1_DFF (1 << 11) - -/* RXONLY: Receive only */ -#define SPI_CR1_RXONLY (1 << 10) - -/* SSM: Software slave management */ -#define SPI_CR1_SSM (1 << 9) - -/* SSI: Internal slave select */ -#define SPI_CR1_SSI (1 << 8) - -/* LSBFIRST: Frame format */ -#define SPI_CR1_MSBFIRST (0 << 7) -#define SPI_CR1_LSBFIRST (1 << 7) - -/* SPE: SPI enable */ -#define SPI_CR1_SPE (1 << 6) - -/* BR[2:0]: Baud rate control */ -#define SPI_CR1_BAUDRATE_FPCLK_DIV_2 (0x00 << 3) -#define SPI_CR1_BAUDRATE_FPCLK_DIV_4 (0x01 << 3) -#define SPI_CR1_BAUDRATE_FPCLK_DIV_8 (0x02 << 3) -#define SPI_CR1_BAUDRATE_FPCLK_DIV_16 (0x03 << 3) -#define SPI_CR1_BAUDRATE_FPCLK_DIV_32 (0x04 << 3) -#define SPI_CR1_BAUDRATE_FPCLK_DIV_64 (0x05 << 3) -#define SPI_CR1_BAUDRATE_FPCLK_DIV_128 (0x06 << 3) -#define SPI_CR1_BAUDRATE_FPCLK_DIV_256 (0x07 << 3) -#define SPI_CR1_BR_FPCLK_DIV_2 0x0 -#define SPI_CR1_BR_FPCLK_DIV_4 0x1 -#define SPI_CR1_BR_FPCLK_DIV_8 0x2 -#define SPI_CR1_BR_FPCLK_DIV_16 0x3 -#define SPI_CR1_BR_FPCLK_DIV_32 0x4 -#define SPI_CR1_BR_FPCLK_DIV_64 0x5 -#define SPI_CR1_BR_FPCLK_DIV_128 0x6 -#define SPI_CR1_BR_FPCLK_DIV_256 0x7 - -/* MSTR: Master selection */ -#define SPI_CR1_MSTR (1 << 2) - -/* CPOL: Clock polarity */ -#define SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE (0 << 1) -#define SPI_CR1_CPOL_CLK_TO_1_WHEN_IDLE (1 << 1) -#define SPI_CR1_CPOL (1 << 1) - -/* CPHA: Clock phase */ -#define SPI_CR1_CPHA_CLK_TRANSITION_1 (0 << 0) -#define SPI_CR1_CPHA_CLK_TRANSITION_2 (1 << 0) -#define SPI_CR1_CPHA (1 << 0) - -/* --- SPI_CR2 values ------------------------------------------------------ */ - -/* Bits [15:8]: Reserved. Forced to 0 by hardware. */ - -/* TXEIE: Tx buffer empty interrupt enable */ -#define SPI_CR2_TXEIE (1 << 7) - -/* RXNEIE: RX buffer not empty interrupt enable */ -#define SPI_CR2_RXNEIE (1 << 6) - -/* ERRIE: Error interrupt enable */ -#define SPI_CR2_ERRIE (1 << 5) - -/* Bits [4:3]: Reserved. Forced to 0 by hardware. */ - -/* SSOE: SS output enable */ -#define SPI_CR2_SSOE (1 << 2) - -/* TXDMAEN: Tx buffer DMA enable */ -#define SPI_CR2_TXDMAEN (1 << 1) - -/* RXDMAEN: Rx buffer DMA enable */ -#define SPI_CR2_RXDMAEN (1 << 0) - -/* --- SPI_SR values ------------------------------------------------------- */ - -/* Bits [15:8]: Reserved. Forced to 0 by hardware. */ - -/* BSY: Busy flag */ -#define SPI_SR_BSY (1 << 7) - -/* OVR: Overrun flag */ -#define SPI_SR_OVR (1 << 6) - -/* MODF: Mode fault */ -#define SPI_SR_MODF (1 << 5) - -/* CRCERR: CRC error flag */ -#define SPI_SR_CRCERR (1 << 4) - -/* UDR: Underrun flag */ -#define SPI_SR_UDR (1 << 3) - -/* CHSIDE: Channel side */ -#define SPI_SR_CHSIDE (1 << 2) - -/* TXE: Transmit buffer empty */ -#define SPI_SR_TXE (1 << 1) - -/* RXNE: Receive buffer not empty */ -#define SPI_SR_RXNE (1 << 0) - -/* --- SPI_SR values ------------------------------------------------------- */ - -/* SPI_DR[15:0]: Data Register. */ - -/* --- SPI_CRCPR values ---------------------------------------------------- */ - -/* SPI_CRCPR [15:0]: CRC Polynomial Register. */ - -/* --- SPI_RXCRCR values --------------------------------------------------- */ - -/* SPI_RXCRCR [15:0]: RX CRC Register. */ - -/* --- SPI_TXCRCR values --------------------------------------------------- */ - -/* SPI_TXCRCR [15:0]: TX CRC Register. */ - -/* --- SPI_I2SCFGR values -------------------------------------------------- */ - -/* Bits [15:12]: Reserved. Forced to 0 by hardware. */ - -/* I2SMOD: I2S mode selection */ -#define SPI_I2SCFGR_I2SMOD (1 << 11) - -/* I2SE: I2S Enable */ -#define SPI_I2SCFGR_I2SE (1 << 10) - -/* I2SCFG[9:8]: I2S configuration mode */ -#define SPI_I2SCFGR_I2SCFG_LSB 8 -#define SPI_I2SCFGR_I2SCFG_SLAVE_TRANSMIT 0x0 -#define SPI_I2SCFGR_I2SCFG_SLAVE_RECEIVE 0x1 -#define SPI_I2SCFGR_I2SCFG_MASTER_TRANSMIT 0x2 -#define SPI_I2SCFGR_I2SCFG_MASTER_RECEIVE 0x3 - -/* PCMSYNC: PCM frame synchronization */ -#define SPI_I2SCFGR_PCMSYNC (1 << 7) - -/* Bit 6: Reserved. Forced to 0 by hardware. */ - -/* I2SSTD[5:4]: I2S standard selection */ -#define SPI_I2SCFGR_I2SSTD_LSB 4 -#define SPI_I2SCFGR_I2SSTD_I2S_PHILLIPS 0x0 -#define SPI_I2SCFGR_I2SSTD_MSB_JUSTIFIED 0x1 -#define SPI_I2SCFGR_I2SSTD_LSB_JUSTIFIED 0x2 -#define SPI_I2SCFGR_I2SSTD_PCM 0x3 - -/* CKPOL: Steady state clock polarity */ -#define SPI_I2SCFGR_CKPOL (1 << 3) - -/* DATLEN[2:1]: Data length to be transferred */ -#define SPI_I2SCFGR_DATLEN_LSB 1 -#define SPI_I2SCFGR_DATLEN_16BIT 0x0 -#define SPI_I2SCFGR_DATLEN_24BIT 0x1 -#define SPI_I2SCFGR_DATLEN_32BIT 0x2 - -/* CHLEN: Channel length */ -#define SPI_I2SCFGR_CHLEN (1 << 0) - -/* --- SPI_I2SPR values ---------------------------------------------------- */ - -/* Bits [15:10]: Reserved. Forced to 0 by hardware. */ - -/* MCKOE: Master clock output enable */ -#define SPI_I2SPR_MCKOE (1 << 9) - -/* ODD: Odd factor for the prescaler */ -#define SPI_I2SPR_ODD (1 << 8) - -/* I2SDIV[7:0]: I2S Linear prescaler */ -/* 0 and 1 are forbidden values */ - -/* --- Function prototypes ------------------------------------------------- */ - -int spi_init_master(u32 spi, u32 br, u32 cpol, u32 cpha, u32 dff, u32 lsbfirst); -void spi_enable(u32 spi); -void spi_disable(u32 spi); -void spi_write(u32 spi, u16 data); -void spi_send(u32 spi, u16 data); -u16 spi_read(u32 spi); -void spi_set_bidirectional_mode(u32 spi); -void spi_set_unidirectional_mode(u32 spi); -void spi_set_bidirectional_receive_only_mode(u32 spi); -void spi_set_bidirectional_transmit_only_mode(u32 spi); -void spi_enable_crc(u32 spi); -void spi_disable_crc(u32 spi); -void spi_set_next_tx_from_buffer(u32 spi); -void spi_set_next_tx_from_crc(u32 spi); -void spi_set_dff_8bit(u32 spi); -void spi_set_dff_16bit(u32 spi); -void spi_set_full_duplex_mode(u32 spi); -void spi_set_receive_only_mode(u32 spi); -void spi_disable_software_slave_management(u32 spi); -void spi_enable_software_slave_management(u32 spi); -void spi_set_nss_high(u32 spi); -void spi_set_nss_low(u32 spi); -void spi_send_lsb_first(u32 spi); -void spi_send_msb_first(u32 spi); -void spi_set_baudrate_prescaler(u32 spi, u8 baudrate); -void spi_set_master_mode(u32 spi); -void spi_set_slave_mode(u32 spi); -void spi_set_clock_polarity_1(u32 spi); -void spi_set_clock_polarity_0(u32 spi); -void spi_set_clock_phase_1(u32 spi); -void spi_set_clock_phase_0(u32 spi); -void spi_enable_tx_buffer_empty_interrupt(u32 spi); -void spi_disable_tx_buffer_empty_interrupt(u32 spi); -void spi_enable_rx_buffer_not_empty_interrupt(u32 spi); -void spi_disable_rx_buffer_not_empty_interrupt(u32 spi); -void spi_enable_error_interrupt(u32 spi); -void spi_disable_error_interrupt(u32 spi); -void spi_enable_ss_output(u32 spi); -void spi_disable_ss_output(u32 spi); -void spi_enable_tx_dma(u32 spi); -void spi_disable_tx_dma(u32 spi); -void spi_enable_rx_dma(u32 spi); -void spi_disable_rx_dma(u32 spi); - -#endif diff --git a/include/libopencm3/stm32f2/spi.h b/include/libopencm3/stm32f2/spi.h new file mode 100644 index 0000000..d4aa02e --- /dev/null +++ b/include/libopencm3/stm32f2/spi.h @@ -0,0 +1,42 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Fergus Noble + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_SPI_F2_H +#define LIBOPENCM3_SPI_F2_H + +#include + +/* + * This file extends the version in stm_common with definitions only + * applicable to the STM32F2 series of devices. + */ + +/* --- SPI_CR2 values ------------------------------------------------------ */ + +/* FRF: Frame format. */ +#define SPI_CR2_FRF (1 << 4) +#define SPI_CR2_FRF_TI (1 << 4) +#define SPI_CR2_FRF_MOTOROLA (1 << 4) + +/* --- SPI_SR values ------------------------------------------------------- */ + +/* TIFRFE: TI frame format error. */ +#define SPI_SR_RXNE (1 << 0) + +#endif -- cgit v1.2.3 From ab871dde0b3d9fa6ada9dfe42a71e5ca94589a70 Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Mon, 12 Sep 2011 21:11:24 -0700 Subject: Unnecessary include removed. --- include/libopencm3/stm32f2/pwr.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/libopencm3/stm32f2/pwr.h b/include/libopencm3/stm32f2/pwr.h index 8e8517e..49b3383 100644 --- a/include/libopencm3/stm32f2/pwr.h +++ b/include/libopencm3/stm32f2/pwr.h @@ -21,8 +21,6 @@ #define LIBOPENCM3_PWR_F2_H #include -#include - /* * This file extends the version in stm_common with definitions only -- cgit v1.2.3 From 69fb967eed15dfde14442ecfa36e42f824b704c2 Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Mon, 12 Sep 2011 22:13:55 -0700 Subject: Moves usart over to common and added F2 specific header. --- include/libopencm3/stm32_common/usart.h | 312 ++++++++++++++++++++++++++++++++ include/libopencm3/stm32f1/usart.h | 312 -------------------------------- include/libopencm3/stm32f2/usart.h | 35 ++++ 3 files changed, 347 insertions(+), 312 deletions(-) create mode 100644 include/libopencm3/stm32_common/usart.h delete mode 100644 include/libopencm3/stm32f1/usart.h create mode 100644 include/libopencm3/stm32f2/usart.h diff --git a/include/libopencm3/stm32_common/usart.h b/include/libopencm3/stm32_common/usart.h new file mode 100644 index 0000000..0a1ed36 --- /dev/null +++ b/include/libopencm3/stm32_common/usart.h @@ -0,0 +1,312 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_USART_H +#define LIBOPENCM3_USART_H + +#include +#include + +/* --- Convenience macros -------------------------------------------------- */ + +#define USART1 USART1_BASE +#define USART2 USART2_BASE +#define USART3 USART3_BASE +#define UART4 UART4_BASE +#define UART5 UART5_BASE + +/* --- USART registers ----------------------------------------------------- */ + +/* Status register (USARTx_SR) */ +#define USART_SR(usart_base) MMIO32(usart_base + 0x00) +#define USART1_SR USART_SR(USART1_BASE) +#define USART2_SR USART_SR(USART2_BASE) +#define USART3_SR USART_SR(USART3_BASE) +#define UART4_SR USART_SR(UART4_BASE) +#define UART5_SR USART_SR(UART5_BASE) + +/* Data register (USARTx_DR) */ +#define USART_DR(usart_base) MMIO32(usart_base + 0x04) +#define USART1_DR USART_DR(USART1_BASE) +#define USART2_DR USART_DR(USART2_BASE) +#define USART3_DR USART_DR(USART3_BASE) +#define UART4_DR USART_DR(UART4_BASE) +#define UART5_DR USART_DR(UART5_BASE) + +/* Baud rate register (USARTx_BRR) */ +#define USART_BRR(usart_base) MMIO32(usart_base + 0x08) +#define USART1_BRR USART_BRR(USART1_BASE) +#define USART2_BRR USART_BRR(USART2_BASE) +#define USART3_BRR USART_BRR(USART3_BASE) +#define UART4_BRR USART_BRR(UART4_BASE) +#define UART5_BRR USART_BRR(UART5_BASE) + +/* Control register 1 (USARTx_CR1) */ +#define USART_CR1(usart_base) MMIO32(usart_base + 0x0c) +#define USART1_CR1 USART_CR1(USART1_BASE) +#define USART2_CR1 USART_CR1(USART2_BASE) +#define USART3_CR1 USART_CR1(USART3_BASE) +#define UART4_CR1 USART_CR1(UART4_BASE) +#define UART5_CR1 USART_CR1(UART5_BASE) + +/* Control register 2 (USARTx_CR2) */ +#define USART_CR2(usart_base) MMIO32(usart_base + 0x10) +#define USART1_CR2 USART_CR2(USART1_BASE) +#define USART2_CR2 USART_CR2(USART2_BASE) +#define USART3_CR2 USART_CR2(USART3_BASE) +#define UART4_CR2 USART_CR2(UART4_BASE) +#define UART5_CR2 USART_CR2(UART5_BASE) + +/* Control register 3 (USARTx_CR3) */ +#define USART_CR3(usart_base) MMIO32(usart_base + 0x14) +#define USART1_CR3 USART_CR3(USART1_BASE) +#define USART2_CR3 USART_CR3(USART2_BASE) +#define USART3_CR3 USART_CR3(USART3_BASE) +#define UART4_CR3 USART_CR3(UART4_BASE) +#define UART5_CR3 USART_CR3(UART5_BASE) + +/* Guard time and prescaler register (USARTx_GTPR) */ +#define USART_GTPR(usart_base) MMIO32(usart_base + 0x18) +#define USART1_GTPR USART_GTPR(USART1_BASE) +#define USART2_GTPR USART_GTPR(USART2_BASE) +#define USART3_GTPR USART_GTPR(USART3_BASE) +#define UART4_GTPR USART_GTPR(UART4_BASE) +#define UART5_GTPR USART_GTPR(UART5_BASE) + +/* --- USART_SR values ----------------------------------------------------- */ + +/* CTS: CTS flag */ +/* Note: N/A on UART4/5 */ +#define USART_SR_CTS (1 << 9) + +/* LBD: LIN break detection flag */ +#define USART_SR_LBD (1 << 8) + +/* TXE: Transmit data buffer empty */ +#define USART_SR_TXE (1 << 7) + +/* TC: Transmission complete */ +#define USART_SR_TC (1 << 6) + +/* RXNE: Read data register not empty */ +#define USART_SR_RXNE (1 << 5) + +/* IDLE: Idle line detected */ +#define USART_SR_IDLE (1 << 4) + +/* ORE: Overrun error */ +#define USART_SR_ORE (1 << 3) + +/* NE: Noise error flag */ +#define USART_SR_NE (1 << 2) + +/* FE: Framing error */ +#define USART_SR_FE (1 << 1) + +/* PE: Parity error */ +#define USART_SR_PE (1 << 0) + +/* --- USART_DR values ----------------------------------------------------- */ + +/* USART_DR[8:0]: DR[8:0]: Data value */ +#define USART_DR_MASK 0x1FF + +/* --- USART_BRR values ---------------------------------------------------- */ + +/* DIV_Mantissa[11:0]: mantissa of USARTDIV */ +#define USART_BRR_DIV_MANTISSA_MASK (0xFFF << 4) +/* DIV_Fraction[3:0]: fraction of USARTDIV */ +#define USART_BRR_DIV_FRACTION_MASK 0xF + +/* --- USART_CR1 values ---------------------------------------------------- */ + +/* UE: USART enable */ +#define USART_CR1_UE (1 << 13) + +/* M: Word length */ +#define USART_CR1_M (1 << 12) + +/* WAKE: Wakeup method */ +#define USART_CR1_WAKE (1 << 11) + +/* PCE: Parity control enable */ +#define USART_CR1_PCE (1 << 10) + +/* PS: Parity selection */ +#define USART_CR1_PS (1 << 9) + +/* PEIE: PE interrupt enable */ +#define USART_CR1_PEIE (1 << 8) + +/* TXEIE: TXE interrupt enable */ +#define USART_CR1_TXEIE (1 << 7) + +/* TCIE: Transmission complete interrupt enable */ +#define USART_CR1_TCIE (1 << 6) + +/* RXNEIE: RXNE interrupt enable */ +#define USART_CR1_RXNEIE (1 << 5) + +/* IDLEIE: IDLE interrupt enable */ +#define USART_CR1_IDLEIE (1 << 4) + +/* TE: Transmitter enable */ +#define USART_CR1_TE (1 << 3) + +/* RE: Receiver enable */ +#define USART_CR1_RE (1 << 2) + +/* RWU: Receiver wakeup */ +#define USART_CR1_RWU (1 << 1) + +/* SBK: Send break */ +#define USART_CR1_SBK (1 << 0) + +/* --- USART_CR2 values ---------------------------------------------------- */ + +/* LINEN: LIN mode enable */ +#define USART_CR2_LINEN (1 << 14) + +/* STOP[13:12]: STOP bits */ +#define USART_CR2_STOPBITS_1 (0x00 << 12) /* 1 stop bit */ +#define USART_CR2_STOPBITS_0_5 (0x01 << 12) /* 0.5 stop bits */ +#define USART_CR2_STOPBITS_2 (0x02 << 12) /* 2 stop bits */ +#define USART_CR2_STOPBITS_1_5 (0x03 << 12) /* 1.5 stop bits */ +#define USART_CR2_STOPBITS_MASK (0x03 << 12) +#define USART_CR2_STOPBITS_SHIFT 12 + +/* CLKEN: Clock enable */ +#define USART_CR2_CLKEN (1 << 11) + +/* CPOL: Clock polarity */ +#define USART_CR2_CPOL (1 << 10) + +/* CPHA: Clock phase */ +#define USART_CR2_CPHA (1 << 9) + +/* LBCL: Last bit clock pulse */ +#define USART_CR2_LBCL (1 << 8) + +/* LBDIE: LIN break detection interrupt enable */ +#define USART_CR2_LBDIE (1 << 6) + +/* LBDL: LIN break detection length */ +#define USART_CR2_LBDL (1 << 5) + +/* ADD[3:0]: Addres of the usart node */ +#define USART_CR2_ADD_MASK 0xF + +/* --- USART_CR3 values ---------------------------------------------------- */ + +/* CTSIE: CTS interrupt enable */ +/* Note: N/A on UART4 & UART5 */ +#define USART_CR3_CTSIE (1 << 10) + +/* CTSE: CTS enable */ +/* Note: N/A on UART4 & UART5 */ +#define USART_CR3_CTSE (1 << 9) + +/* RTSE: RTS enable */ +/* Note: N/A on UART4 & UART5 */ +#define USART_CR3_RTSE (1 << 8) + +/* DMAT: DMA enable transmitter */ +/* Note: N/A on UART5 */ +#define USART_CR3_DMAT (1 << 7) + +/* DMAR: DMA enable receiver */ +/* Note: N/A on UART5 */ +#define USART_CR3_DMAR (1 << 6) + +/* SCEN: Smartcard mode enable */ +/* Note: N/A on UART4 & UART5 */ +#define USART_CR3_SCEN (1 << 5) + +/* NACK: Smartcard NACK enable */ +/* Note: N/A on UART4 & UART5 */ +#define USART_CR3_NACK (1 << 4) + +/* HDSEL: Half-duplex selection */ +#define USART_CR3_HDSEL (1 << 3) + +/* IRLP: IrDA low-power */ +#define USART_CR3_IRLP (1 << 2) + +/* IREN: IrDA mode enable */ +#define USART_CR3_IREN (1 << 1) + +/* EIE: Error interrupt enable */ +#define USART_CR3_EIE (1 << 0) + +/* --- USART_GTPR values --------------------------------------------------- */ + +/* GT[7:0]: Guard time value */ +/* Note: N/A on UART4 & UART5 */ +#define USART_GTPR_GT_MASK (0xFF << 8) + +/* PSC[7:0]: Prescaler value */ +/* Note: N/A on UART4/5 */ +#define USART_GTPR_PSC_MASK 0xFF + +/* TODO */ /* Note to Uwe: what needs to be done here? */ + +/* --- Convenience defines ------------------------------------------------- */ + +/* CR1_PCE / CR1_PS combined values */ +#define USART_PARITY_NONE 0x00 +#define USART_PARITY_ODD USART_CR1_PS +#define USART_PARITY_EVEN (USART_CR1_PS | USART_CR1_PCE) +#define USART_PARITY_MASK (USART_CR1_PS | USART_CR1_PCE) + +/* CR1_TE/CR1_RE combined values */ +#define USART_MODE_RX USART_CR1_RE +#define USART_MODE_TX USART_CR1_TE +#define USART_MODE_TX_RX (USART_CR1_RE | USART_CR1_TE) +#define USART_MODE_MASK (USART_CR1_RE | USART_CR1_TE) + +#define USART_STOPBITS_1 USART_CR2_STOPBITS_1 /* 1 stop bit */ +#define USART_STOPBITS_0_5 USART_CR2_STOPBITS_0_5 /* 0.5 stop bits */ +#define USART_STOPBITS_2 USART_CR2_STOPBITS_2 /* 2 stop bits */ +#define USART_STOPBITS_1_5 USART_CR2_STOPBITS_1_5 /* 1.5 stop bits */ + +/* CR3_CTSE/CR3_RTSE combined values */ +#define USART_FLOWCONTROL_NONE 0x00 +#define USART_FLOWCONTROL_RTS USART_CR3_RTSE +#define USART_FLOWCONTROL_CTS USART_CR3_CTSE +#define USART_FLOWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) +#define USART_FLOWCONTROL_MASK (USART_CR3_RTSE | USART_CR3_CTSE) + +/* --- Function prototypes ------------------------------------------------- */ + +void usart_set_baudrate(u32 usart, u32 baud); +void usart_set_databits(u32 usart, u32 bits); +void usart_set_stopbits(u32 usart, u32 stopbits); +void usart_set_parity(u32 usart, u32 parity); +void usart_set_mode(u32 usart, u32 mode); +void usart_set_flow_control(u32 usart, u32 flowcontrol); +void usart_enable(u32 usart); +void usart_disable(u32 usart); +void usart_send(u32 usart, u16 data); +u16 usart_recv(u32 usart); +void usart_wait_send_ready(u32 usart); +void usart_wait_recv_ready(u32 usart); +void usart_send_blocking(u32 usart, u16 data); +u16 usart_recv_blocking(u32 usart); + +#endif diff --git a/include/libopencm3/stm32f1/usart.h b/include/libopencm3/stm32f1/usart.h deleted file mode 100644 index df6bc08..0000000 --- a/include/libopencm3/stm32f1/usart.h +++ /dev/null @@ -1,312 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_USART_H -#define LIBOPENCM3_USART_H - -#include -#include - -/* --- Convenience macros -------------------------------------------------- */ - -#define USART1 USART1_BASE -#define USART2 USART2_BASE -#define USART3 USART3_BASE -#define UART4 UART4_BASE -#define UART5 UART5_BASE - -/* --- USART registers ----------------------------------------------------- */ - -/* Status register (USARTx_SR) */ -#define USART_SR(usart_base) MMIO32(usart_base + 0x00) -#define USART1_SR USART_SR(USART1_BASE) -#define USART2_SR USART_SR(USART2_BASE) -#define USART3_SR USART_SR(USART3_BASE) -#define UART4_SR USART_SR(UART4_BASE) -#define UART5_SR USART_SR(UART5_BASE) - -/* Data register (USARTx_DR) */ -#define USART_DR(usart_base) MMIO32(usart_base + 0x04) -#define USART1_DR USART_DR(USART1_BASE) -#define USART2_DR USART_DR(USART2_BASE) -#define USART3_DR USART_DR(USART3_BASE) -#define UART4_DR USART_DR(UART4_BASE) -#define UART5_DR USART_DR(UART5_BASE) - -/* Baud rate register (USARTx_BRR) */ -#define USART_BRR(usart_base) MMIO32(usart_base + 0x08) -#define USART1_BRR USART_BRR(USART1_BASE) -#define USART2_BRR USART_BRR(USART2_BASE) -#define USART3_BRR USART_BRR(USART3_BASE) -#define UART4_BRR USART_BRR(UART4_BASE) -#define UART5_BRR USART_BRR(UART5_BASE) - -/* Control register 1 (USARTx_CR1) */ -#define USART_CR1(usart_base) MMIO32(usart_base + 0x0c) -#define USART1_CR1 USART_CR1(USART1_BASE) -#define USART2_CR1 USART_CR1(USART2_BASE) -#define USART3_CR1 USART_CR1(USART3_BASE) -#define UART4_CR1 USART_CR1(UART4_BASE) -#define UART5_CR1 USART_CR1(UART5_BASE) - -/* Control register 2 (USARTx_CR2) */ -#define USART_CR2(usart_base) MMIO32(usart_base + 0x10) -#define USART1_CR2 USART_CR2(USART1_BASE) -#define USART2_CR2 USART_CR2(USART2_BASE) -#define USART3_CR2 USART_CR2(USART3_BASE) -#define UART4_CR2 USART_CR2(UART4_BASE) -#define UART5_CR2 USART_CR2(UART5_BASE) - -/* Control register 3 (USARTx_CR3) */ -#define USART_CR3(usart_base) MMIO32(usart_base + 0x14) -#define USART1_CR3 USART_CR3(USART1_BASE) -#define USART2_CR3 USART_CR3(USART2_BASE) -#define USART3_CR3 USART_CR3(USART3_BASE) -#define UART4_CR3 USART_CR3(UART4_BASE) -#define UART5_CR3 USART_CR3(UART5_BASE) - -/* Guard time and prescaler register (USARTx_GTPR) */ -#define USART_GTPR(usart_base) MMIO32(usart_base + 0x18) -#define USART1_GTPR USART_GTPR(USART1_BASE) -#define USART2_GTPR USART_GTPR(USART2_BASE) -#define USART3_GTPR USART_GTPR(USART3_BASE) -#define UART4_GTPR USART_GTPR(UART4_BASE) -#define UART5_GTPR USART_GTPR(UART5_BASE) - -/* --- USART_SR values ----------------------------------------------------- */ - -/* CTS: CTS flag */ -/* Note: N/A on UART4/5 */ -#define USART_SR_CTS (1 << 9) - -/* LBD: LIN break detection flag */ -#define USART_SR_LBD (1 << 8) - -/* TXE: Transmit data buffer empty */ -#define USART_SR_TXE (1 << 7) - -/* TC: Transmission complete */ -#define USART_SR_TC (1 << 6) - -/* RXNE: Read data register not empty */ -#define USART_SR_RXNE (1 << 5) - -/* IDLE: Idle line detected */ -#define USART_SR_IDLE (1 << 4) - -/* ORE: Overrun error */ -#define USART_SR_ORE (1 << 3) - -/* NE: Noise error flag */ -#define USART_SR_NE (1 << 2) - -/* FE: Framing error */ -#define USART_SR_FE (1 << 1) - -/* PE: Parity error */ -#define USART_SR_PE (1 << 0) - -/* --- USART_DR values ----------------------------------------------------- */ - -/* USART_DR[8:0]: DR[8:0]: Data value */ -#define USART_DR_MASK 0x1FF - -/* --- USART_BRR values ---------------------------------------------------- */ - -/* DIV_Mantissa[11:0]: mantissa of USARTDIV */ -#define USART_BRR_DIV_MANTISSA_MASK (0xFFF << 4) -/* DIV_Fraction[3:0]: fraction of USARTDIV */ -#define USART_BRR_DIV_FRACTION_MASK 0xF - -/* --- USART_CR1 values ---------------------------------------------------- */ - -/* UE: USART enable */ -#define USART_CR1_UE (1 << 13) - -/* M: Word length */ -#define USART_CR1_M (1 << 12) - -/* WAKE: Wakeup method */ -#define USART_CR1_WAKE (1 << 11) - -/* PCE: Parity control enable */ -#define USART_CR1_PCE (1 << 10) - -/* PS: Parity selection */ -#define USART_CR1_PS (1 << 9) - -/* PEIE: PE interrupt enable */ -#define USART_CR1_PEIE (1 << 8) - -/* TXEIE: TXE interrupt enable */ -#define USART_CR1_TXEIE (1 << 7) - -/* TCIE: Transmission complete interrupt enable */ -#define USART_CR1_TCIE (1 << 6) - -/* RXNEIE: RXNE interrupt enable */ -#define USART_CR1_RXNEIE (1 << 5) - -/* IDLEIE: IDLE interrupt enable */ -#define USART_CR1_IDLEIE (1 << 4) - -/* TE: Transmitter enable */ -#define USART_CR1_TE (1 << 3) - -/* RE: Receiver enable */ -#define USART_CR1_RE (1 << 2) - -/* RWU: Receiver wakeup */ -#define USART_CR1_RWU (1 << 1) - -/* SBK: Send break */ -#define USART_CR1_SBK (1 << 0) - -/* --- USART_CR2 values ---------------------------------------------------- */ - -/* LINEN: LIN mode enable */ -#define USART_CR2_LINEN (1 << 14) - -/* STOP[13:12]: STOP bits */ -#define USART_CR2_STOPBITS_1 (0x00 << 12) /* 1 stop bit */ -#define USART_CR2_STOPBITS_0_5 (0x01 << 12) /* 0.5 stop bits */ -#define USART_CR2_STOPBITS_2 (0x02 << 12) /* 2 stop bits */ -#define USART_CR2_STOPBITS_1_5 (0x03 << 12) /* 1.5 stop bits */ -#define USART_CR2_STOPBITS_MASK (0x03 << 12) -#define USART_CR2_STOPBITS_SHIFT 12 - -/* CLKEN: Clock enable */ -#define USART_CR2_CLKEN (1 << 11) - -/* CPOL: Clock polarity */ -#define USART_CR2_CPOL (1 << 10) - -/* CPHA: Clock phase */ -#define USART_CR2_CPHA (1 << 9) - -/* LBCL: Last bit clock pulse */ -#define USART_CR2_LBCL (1 << 8) - -/* LBDIE: LIN break detection interrupt enable */ -#define USART_CR2_LBDIE (1 << 6) - -/* LBDL: LIN break detection length */ -#define USART_CR2_LBDL (1 << 5) - -/* ADD[3:0]: Addres of the usart node */ -#define USART_CR2_ADD_MASK 0xF - -/* --- USART_CR3 values ---------------------------------------------------- */ - -/* CTSIE: CTS interrupt enable */ -/* Note: N/A on UART4 & UART5 */ -#define USART_CR3_CTSIE (1 << 10) - -/* CTSE: CTS enable */ -/* Note: N/A on UART4 & UART5 */ -#define USART_CR3_CTSE (1 << 9) - -/* RTSE: RTS enable */ -/* Note: N/A on UART4 & UART5 */ -#define USART_CR3_RTSE (1 << 8) - -/* DMAT: DMA enable transmitter */ -/* Note: N/A on UART5 */ -#define USART_CR3_DMAT (1 << 7) - -/* DMAR: DMA enable receiver */ -/* Note: N/A on UART5 */ -#define USART_CR3_DMAR (1 << 6) - -/* SCEN: Smartcard mode enable */ -/* Note: N/A on UART4 & UART5 */ -#define USART_CR3_SCEN (1 << 5) - -/* NACK: Smartcard NACK enable */ -/* Note: N/A on UART4 & UART5 */ -#define USART_CR3_NACK (1 << 4) - -/* HDSEL: Half-duplex selection */ -#define USART_CR3_HDSEL (1 << 3) - -/* IRLP: IrDA low-power */ -#define USART_CR3_IRLP (1 << 2) - -/* IREN: IrDA mode enable */ -#define USART_CR3_IREN (1 << 1) - -/* EIE: Error interrupt enable */ -#define USART_CR3_EIE (1 << 0) - -/* --- USART_GTPR values --------------------------------------------------- */ - -/* GT[7:0]: Guard time value */ -/* Note: N/A on UART4 & UART5 */ -#define USART_GTPR_GT_MASK (0xFF << 8) - -/* PSC[7:0]: Prescaler value */ -/* Note: N/A on UART4/5 */ -#define USART_GTPR_PSC_MASK 0xFF - -/* TODO */ /* Note to Uwe: what needs to be done here? */ - -/* --- Convenience defines ------------------------------------------------- */ - -/* CR1_PCE / CR1_PS combined values */ -#define USART_PARITY_NONE 0x00 -#define USART_PARITY_ODD USART_CR1_PS -#define USART_PARITY_EVEN (USART_CR1_PS | USART_CR1_PCE) -#define USART_PARITY_MASK (USART_CR1_PS | USART_CR1_PCE) - -/* CR1_TE/CR1_RE combined values */ -#define USART_MODE_RX USART_CR1_RE -#define USART_MODE_TX USART_CR1_TE -#define USART_MODE_TX_RX (USART_CR1_RE | USART_CR1_TE) -#define USART_MODE_MASK (USART_CR1_RE | USART_CR1_TE) - -#define USART_STOPBITS_1 USART_CR2_STOPBITS_1 /* 1 stop bit */ -#define USART_STOPBITS_0_5 USART_CR2_STOPBITS_0_5 /* 0.5 stop bits */ -#define USART_STOPBITS_2 USART_CR2_STOPBITS_2 /* 2 stop bits */ -#define USART_STOPBITS_1_5 USART_CR2_STOPBITS_1_5 /* 1.5 stop bits */ - -/* CR3_CTSE/CR3_RTSE combined values */ -#define USART_FLOWCONTROL_NONE 0x00 -#define USART_FLOWCONTROL_RTS USART_CR3_RTSE -#define USART_FLOWCONTROL_CTS USART_CR3_CTSE -#define USART_FLOWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) -#define USART_FLOWCONTROL_MASK (USART_CR3_RTSE | USART_CR3_CTSE) - -/* --- Function prototypes ------------------------------------------------- */ - -void usart_set_baudrate(u32 usart, u32 baud); -void usart_set_databits(u32 usart, u32 bits); -void usart_set_stopbits(u32 usart, u32 stopbits); -void usart_set_parity(u32 usart, u32 parity); -void usart_set_mode(u32 usart, u32 mode); -void usart_set_flow_control(u32 usart, u32 flowcontrol); -void usart_enable(u32 usart); -void usart_disable(u32 usart); -void usart_send(u32 usart, u16 data); -u16 usart_recv(u32 usart); -void usart_wait_send_ready(u32 usart); -void usart_wait_recv_ready(u32 usart); -void usart_send_blocking(u32 usart, u16 data); -u16 usart_recv_blocking(u32 usart); - -#endif diff --git a/include/libopencm3/stm32f2/usart.h b/include/libopencm3/stm32f2/usart.h new file mode 100644 index 0000000..8d1caca --- /dev/null +++ b/include/libopencm3/stm32f2/usart.h @@ -0,0 +1,35 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Fergus Noble + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_USART_F2_H +#define LIBOPENCM3_USART_F2_H + +#include + +/* --- USART_CR1 values ---------------------------------------------------- */ + +/* OVER8: Oversampling mode */ +#define USART_CR1_OVER8 (1 << 15) + +/* --- USART_CR3 values ---------------------------------------------------- */ + +/* ONEBIT: One sample bit method enable */ +#define USART_CR3_ONEBIT (1 << 11) + +#endif -- cgit v1.2.3 From fd2eb7a1bd3b7cbe06dd91fad6782a85afff86ba Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Mon, 12 Sep 2011 23:28:52 -0700 Subject: Moved I2C to common, no changes needed. --- include/libopencm3/stm32_common/i2c.h | 333 ++++++++++++++++++++++++++++++++++ include/libopencm3/stm32f1/i2c.h | 333 ---------------------------------- 2 files changed, 333 insertions(+), 333 deletions(-) create mode 100644 include/libopencm3/stm32_common/i2c.h delete mode 100644 include/libopencm3/stm32f1/i2c.h diff --git a/include/libopencm3/stm32_common/i2c.h b/include/libopencm3/stm32_common/i2c.h new file mode 100644 index 0000000..1fa4f37 --- /dev/null +++ b/include/libopencm3/stm32_common/i2c.h @@ -0,0 +1,333 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_I2C_H +#define LIBOPENCM3_I2C_H + +#include +#include + +/* --- Convenience macros -------------------------------------------------- */ + +/* I2C register base adresses (for convenience) */ +#define I2C1 I2C1_BASE +#define I2C2 I2C2_BASE + +/* --- I2C registers ------------------------------------------------------- */ + +/* Control register 1 (I2Cx_CR1) */ +#define I2C_CR1(i2c_base) MMIO32(i2c_base + 0x00) +#define I2C1_CR1 I2C_CR1(I2C1) +#define I2C2_CR1 I2C_CR1(I2C2) + +/* Control register 2 (I2Cx_CR2) */ +#define I2C_CR2(i2c_base) MMIO32(i2c_base + 0x04) +#define I2C1_CR2 I2C_CR2(I2C1) +#define I2C2_CR2 I2C_CR2(I2C2) + +/* Own address register 1 (I2Cx_OAR1) */ +#define I2C_OAR1(i2c_base) MMIO32(i2c_base + 0x08) +#define I2C1_OAR1 I2C_OAR1(I2C1) +#define I2C2_OAR1 I2C_OAR1(I2C2) + +/* Own address register 2 (I2Cx_OAR2) */ +#define I2C_OAR2(i2c_base) MMIO32(i2c_base + 0x0c) +#define I2C1_OAR2 I2C_OAR2(I2C1) +#define I2C2_OAR2 I2C_OAR2(I2C2) + +/* Data register (I2Cx_DR) */ +#define I2C_DR(i2c_base) MMIO32(i2c_base + 0x10) +#define I2C1_DR I2C_DR(I2C1) +#define I2C2_DR I2C_DR(I2C2) + +/* Status register 1 (I2Cx_SR1) */ +#define I2C_SR1(i2c_base) MMIO32(i2c_base + 0x14) +#define I2C1_SR1 I2C_SR1(I2C1) +#define I2C2_SR1 I2C_SR1(I2C2) + +/* Status register 2 (I2Cx_SR2) */ +#define I2C_SR2(i2c_base) MMIO32(i2c_base + 0x18) +#define I2C1_SR2 I2C_SR2(I2C1) +#define I2C2_SR2 I2C_SR2(I2C2) + +/* Clock control register (I2Cx_CCR) */ +#define I2C_CCR(i2c_base) MMIO32(i2c_base + 0x1c) +#define I2C1_CCR I2C_CCR(I2C1) +#define I2C2_CCR I2C_CCR(I2C2) + +/* TRISE register (I2Cx_CCR) */ +#define I2C_TRISE(i2c_base) MMIO32(i2c_base + 0x20) +#define I2C1_TRISE I2C_TRISE(I2C1) +#define I2C2_TRISE I2C_TRISE(I2C2) + +/* --- I2Cx_CR1 values ----------------------------------------------------- */ + +/* SWRST: Software reset */ +#define I2C_CR1_SWRST (1 << 15) + +/* Note: Bit 14 is reserved, and forced to 0 by hardware. */ + +/* ALERT: SMBus alert */ +#define I2C_CR1_ALERT (1 << 13) + +/* PEC: Packet error checking */ +#define I2C_CR1_PEC (1 << 12) + +/* POS: Acknowledge / PEC postition */ +#define I2C_CR1_POS (1 << 11) + +/* ACK: Acknowledge enable */ +#define I2C_CR1_ACK (1 << 10) + +/* STOP: STOP generation */ +#define I2C_CR1_STOP (1 << 9) + +/* START: START generation */ +#define I2C_CR1_START (1 << 8) + +/* NOSTRETCH: Clock stretching disable (slave mode) */ +#define I2C_CR1_NOSTRETCH (1 << 7) + +/* ENGC: General call enable */ +#define I2C_CR1_ENGC (1 << 6) + +/* ENPEC: Enable PEC */ +#define I2C_CR1_ENPEC (1 << 5) + +/* ENARP: ARP enable */ +#define I2C_CR1_ENARP (1 << 4) + +/* SMBTYPE: SMBus type */ +#define I2C_CR1_SMBTYPE (1 << 3) + +/* Note: Bit 2 is reserved, and forced to 0 by hardware. */ + +/* SMBUS: SMBus mode */ +#define I2C_CR1_SMBUS (1 << 1) + +/* PE: Peripheral enable */ +#define I2C_CR1_PE (1 << 0) + +/* --- I2Cx_CR2 values ----------------------------------------------------- */ + +/* Note: Bits [15:13] are reserved, and forced to 0 by hardware. */ + +/* LAST: DMA last transfer */ +#define I2C_CR2_LAST (1 << 12) + +/* DMAEN: DMA requests enable */ +#define I2C_CR2_DMAEN (1 << 11) + +/* ITBUFEN: Buffer interrupt enable */ +#define I2C_CR2_ITBUFEN (1 << 10) + +/* ITEVTEN: Event interrupt enable */ +#define I2C_CR2_ITEVTEN (1 << 9) + +/* ITERREN: Error interrupt enable */ +#define I2C_CR2_ITERREN (1 << 8) + +/* Note: Bits [7:6] are reserved, and forced to 0 by hardware. */ + +/* FREQ[5:0]: Peripheral clock frequency (valid values: 2-36 MHz) */ +#define I2C_CR2_FREQ_2MHZ 0x02 +#define I2C_CR2_FREQ_3MHZ 0x03 +#define I2C_CR2_FREQ_4MHZ 0x04 +#define I2C_CR2_FREQ_5MHZ 0x05 +#define I2C_CR2_FREQ_6MHZ 0x06 +#define I2C_CR2_FREQ_7MHZ 0x07 +#define I2C_CR2_FREQ_8MHZ 0x08 +#define I2C_CR2_FREQ_9MHZ 0x09 +#define I2C_CR2_FREQ_10MHZ 0x0a +#define I2C_CR2_FREQ_11MHZ 0x0b +#define I2C_CR2_FREQ_12MHZ 0x0c +#define I2C_CR2_FREQ_13MHZ 0x0d +#define I2C_CR2_FREQ_14MHZ 0x0e +#define I2C_CR2_FREQ_15MHZ 0x0f +#define I2C_CR2_FREQ_16MHZ 0x10 +#define I2C_CR2_FREQ_17MHZ 0x11 +#define I2C_CR2_FREQ_18MHZ 0x12 +#define I2C_CR2_FREQ_19MHZ 0x13 +#define I2C_CR2_FREQ_20MHZ 0x14 +#define I2C_CR2_FREQ_21MHZ 0x15 +#define I2C_CR2_FREQ_22MHZ 0x16 +#define I2C_CR2_FREQ_23MHZ 0x17 +#define I2C_CR2_FREQ_24MHZ 0x18 +#define I2C_CR2_FREQ_25MHZ 0x19 +#define I2C_CR2_FREQ_26MHZ 0x1a +#define I2C_CR2_FREQ_27MHZ 0x1b +#define I2C_CR2_FREQ_28MHZ 0x1c +#define I2C_CR2_FREQ_29MHZ 0x1d +#define I2C_CR2_FREQ_30MHZ 0x1e +#define I2C_CR2_FREQ_31MHZ 0x1f +#define I2C_CR2_FREQ_32MHZ 0x20 +#define I2C_CR2_FREQ_33MHZ 0x21 +#define I2C_CR2_FREQ_34MHZ 0x22 +#define I2C_CR2_FREQ_35MHZ 0x23 +#define I2C_CR2_FREQ_36MHZ 0x24 + +/* --- I2Cx_OAR1 values ---------------------------------------------------- */ + +/* ADDMODE: Addressing mode (slave mode) */ +#define I2C_OAR1_ADDMODE (1 << 15) +#define I2C_OAR1_ADDMODE_7BIT 0 +#define I2C_OAR1_ADDMODE_10BIT 1 + +/* Note: Bit 14 should always be kept at 1 by software! */ + +/* Note: Bits [13:10] are reserved, and forced to 0 by hardware. */ + +/* ADD: Address bits: [7:1] in 7-bit mode, bits [9:0] in 10-bit mode */ + +/* --- I2Cx_OAR2 values ---------------------------------------------------- */ + +/* Note: Bits [15:8] are reserved, and forced to 0 by hardware. */ + +/* ADD2[7:1]: Interface address (bits [7:1] in dual addressing mode) */ + +/* ENDUAL: Dual addressing mode enable */ +#define I2C_OAR2_ENDUAL (1 << 0) + +/* --- I2Cx_DR values ------------------------------------------------------ */ + +/* Note: Bits [15:8] are reserved, and forced to 0 by hardware. */ + +/* DR[7:0] 8-bit data register */ + +/* --- I2Cx_SR1 values ----------------------------------------------------- */ + +/* SMBALERT: SMBus alert */ +#define I2C_SR1_SMBALERT (1 << 15) + +/* TIMEOUT: Timeout or Tlow Error */ +#define I2C_SR1_TIMEOUT (1 << 14) + +/* Note: Bit 13 is reserved, and forced to 0 by hardware. */ + +/* PECERR: PEC Error in reception */ +#define I2C_SR1_PECERR (1 << 12) + +/* OVR: Overrun/Underrun */ +#define I2C_SR1_OVR (1 << 11) + +/* AF: Acknowledge failure */ +#define I2C_SR1_AF (1 << 10) + +/* ARLO: Arbitration lost (master mode) */ +#define I2C_SR1_ARLO (1 << 9) + +/* BERR: Bus error */ +#define I2C_SR1_BERR (1 << 8) + +/* TxE: Data register empty (transmitters) */ +#define I2C_SR1_TxE (1 << 7) + +/* RxNE: Data register not empty (receivers) */ +#define I2C_SR1_RxNE (1 << 6) + +/* Note: Bit 5 is reserved, and forced to 0 by hardware. */ + +/* STOPF: STOP detection (slave mode) */ +#define I2C_SR1_STOPF (1 << 4) + +/* ADD10: 10-bit header sent (master mode) */ +#define I2C_SR1_ADD10 (1 << 3) + +/* BTF: Byte transfer finished */ +#define I2C_SR1_BTF (1 << 2) + +/* ADDR: Address sent (master mode) / address matched (slave mode) */ +#define I2C_SR1_ADDR (1 << 1) + +/* SB: Start bit (master mode) */ +#define I2C_SR1_SB (1 << 0) + +/* --- I2Cx_SR2 values ----------------------------------------------------- */ + +/* Bits [15:8]: PEC[7:0]: Packet error checking register */ + +/* DUALF: Dual flag (slave mode) */ +#define I2C_SR2_DUALF (1 << 7) + +/* SMBHOST: SMBus host header (slave mode) */ +#define I2C_SR2_SMBHOST (1 << 6) + +/* SMBDEFAULT: SMBus device default address (slave mode) */ +#define I2C_SR2_SMBDEFAULT (1 << 5) + +/* GENCALL: General call address (slave mode) */ +#define I2C_SR2_GENCALL (1 << 4) + +/* Note: Bit 3 is reserved, and forced to 0 by hardware. */ + +/* TRA: Transmitter / receiver */ +#define I2C_SR2_TRA (1 << 2) + +/* BUSY: Bus busy */ +#define I2C_SR2_BUSY (1 << 1) + +/* MSL: Master / slave */ +#define I2C_SR2_MSL (1 << 0) + +/* --- I2Cx_CCR values ----------------------------------------------------- */ + +/* F/S: I2C Master mode selection (fast / standard) */ +#define I2C_CCR_FS (1 << 15) + +/* DUTY: Fast Mode Duty Cycle */ +#define I2C_CCR_DUTY (1 << 14) + +/* Note: Bits [13:12] are reserved, and forced to 0 by hardware. */ + +/* + * Bits [11:0]: + * CCR[11:0]: Clock control register in Fast/Standard mode (master mode) + */ + +/* --- I2Cx_TRISE values --------------------------------------------------- */ + +/* Note: Bits [15:6] are reserved, and forced to 0 by hardware. */ + +/* + * Bits [5:0]: + * TRISE[5:0]: Maximum rise time in Fast/Standard mode (master mode) + */ + +/* --- I2C const definitions ----------------------------------------------- */ + +#define I2C_WRITE 0 +#define I2C_READ 1 + +/* --- I2C funtion prototypes----------------------------------------------- */ + +void i2c_peripheral_enable(u32 i2c); +void i2c_peripheral_disable(u32 i2c); +void i2c_send_start(u32 i2c); +void i2c_send_stop(u32 i2c); +void i2c_set_own_7bit_slave_address(u32 i2c, u8 slave); +void i2c_set_own_10bit_slave_address(u32 i2c, u16 slave); +void i2c_set_fast_mode(u32 i2c); +void i2c_set_standard_mode(u32 i2c); +void i2c_set_clock_frequency(u32 i2c, u8 freq); +void i2c_set_ccr(u32 i2c, u16 freq); +void i2c_set_trise(u32 i2c, u16 trise); +void i2c_send_7bit_address(u32 i2c, u8 slave, u8 readwrite); +void i2c_send_data(u32 i2c, u8 data); + +#endif diff --git a/include/libopencm3/stm32f1/i2c.h b/include/libopencm3/stm32f1/i2c.h deleted file mode 100644 index 1b837b8..0000000 --- a/include/libopencm3/stm32f1/i2c.h +++ /dev/null @@ -1,333 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_I2C_H -#define LIBOPENCM3_I2C_H - -#include -#include - -/* --- Convenience macros -------------------------------------------------- */ - -/* I2C register base adresses (for convenience) */ -#define I2C1 I2C1_BASE -#define I2C2 I2C2_BASE - -/* --- I2C registers ------------------------------------------------------- */ - -/* Control register 1 (I2Cx_CR1) */ -#define I2C_CR1(i2c_base) MMIO32(i2c_base + 0x00) -#define I2C1_CR1 I2C_CR1(I2C1) -#define I2C2_CR1 I2C_CR1(I2C2) - -/* Control register 2 (I2Cx_CR2) */ -#define I2C_CR2(i2c_base) MMIO32(i2c_base + 0x04) -#define I2C1_CR2 I2C_CR2(I2C1) -#define I2C2_CR2 I2C_CR2(I2C2) - -/* Own address register 1 (I2Cx_OAR1) */ -#define I2C_OAR1(i2c_base) MMIO32(i2c_base + 0x08) -#define I2C1_OAR1 I2C_OAR1(I2C1) -#define I2C2_OAR1 I2C_OAR1(I2C2) - -/* Own address register 2 (I2Cx_OAR2) */ -#define I2C_OAR2(i2c_base) MMIO32(i2c_base + 0x0c) -#define I2C1_OAR2 I2C_OAR2(I2C1) -#define I2C2_OAR2 I2C_OAR2(I2C2) - -/* Data register (I2Cx_DR) */ -#define I2C_DR(i2c_base) MMIO32(i2c_base + 0x10) -#define I2C1_DR I2C_DR(I2C1) -#define I2C2_DR I2C_DR(I2C2) - -/* Status register 1 (I2Cx_SR1) */ -#define I2C_SR1(i2c_base) MMIO32(i2c_base + 0x14) -#define I2C1_SR1 I2C_SR1(I2C1) -#define I2C2_SR1 I2C_SR1(I2C2) - -/* Status register 2 (I2Cx_SR2) */ -#define I2C_SR2(i2c_base) MMIO32(i2c_base + 0x18) -#define I2C1_SR2 I2C_SR2(I2C1) -#define I2C2_SR2 I2C_SR2(I2C2) - -/* Clock control register (I2Cx_CCR) */ -#define I2C_CCR(i2c_base) MMIO32(i2c_base + 0x1c) -#define I2C1_CCR I2C_CCR(I2C1) -#define I2C2_CCR I2C_CCR(I2C2) - -/* TRISE register (I2Cx_CCR) */ -#define I2C_TRISE(i2c_base) MMIO32(i2c_base + 0x20) -#define I2C1_TRISE I2C_TRISE(I2C1) -#define I2C2_TRISE I2C_TRISE(I2C2) - -/* --- I2Cx_CR1 values ----------------------------------------------------- */ - -/* SWRST: Software reset */ -#define I2C_CR1_SWRST (1 << 15) - -/* Note: Bit 14 is reserved, and forced to 0 by hardware. */ - -/* ALERT: SMBus alert */ -#define I2C_CR1_ALERT (1 << 13) - -/* PEC: Packet error checking */ -#define I2C_CR1_PEC (1 << 12) - -/* POS: Acknowledge / PEC postition */ -#define I2C_CR1_POS (1 << 11) - -/* ACK: Acknowledge enable */ -#define I2C_CR1_ACK (1 << 10) - -/* STOP: STOP generation */ -#define I2C_CR1_STOP (1 << 9) - -/* START: START generation */ -#define I2C_CR1_START (1 << 8) - -/* NOSTRETCH: Clock stretching disable (slave mode) */ -#define I2C_CR1_NOSTRETCH (1 << 7) - -/* ENGC: General call enable */ -#define I2C_CR1_ENGC (1 << 6) - -/* ENPEC: Enable PEC */ -#define I2C_CR1_ENPEC (1 << 5) - -/* ENARP: ARP enable */ -#define I2C_CR1_ENARP (1 << 4) - -/* SMBTYPE: SMBus type */ -#define I2C_CR1_SMBTYPE (1 << 3) - -/* Note: Bit 2 is reserved, and forced to 0 by hardware. */ - -/* SMBUS: SMBus mode */ -#define I2C_CR1_SMBUS (1 << 1) - -/* PE: Peripheral enable */ -#define I2C_CR1_PE (1 << 0) - -/* --- I2Cx_CR2 values ----------------------------------------------------- */ - -/* Note: Bits [15:13] are reserved, and forced to 0 by hardware. */ - -/* LAST: DMA last transfer */ -#define I2C_CR2_LAST (1 << 12) - -/* DMAEN: DMA requests enable */ -#define I2C_CR2_DMAEN (1 << 11) - -/* ITBUFEN: Buffer interrupt enable */ -#define I2C_CR2_ITBUFEN (1 << 10) - -/* ITEVTEN: Event interrupt enable */ -#define I2C_CR2_ITEVTEN (1 << 9) - -/* ITERREN: Error interrupt enable */ -#define I2C_CR2_ITERREN (1 << 8) - -/* Note: Bits [7:6] are reserved, and forced to 0 by hardware. */ - -/* FREQ[5:0]: Peripheral clock frequency (valid values: 2-36 MHz) */ -#define I2C_CR2_FREQ_2MHZ 0x02 -#define I2C_CR2_FREQ_3MHZ 0x03 -#define I2C_CR2_FREQ_4MHZ 0x04 -#define I2C_CR2_FREQ_5MHZ 0x05 -#define I2C_CR2_FREQ_6MHZ 0x06 -#define I2C_CR2_FREQ_7MHZ 0x07 -#define I2C_CR2_FREQ_8MHZ 0x08 -#define I2C_CR2_FREQ_9MHZ 0x09 -#define I2C_CR2_FREQ_10MHZ 0x0a -#define I2C_CR2_FREQ_11MHZ 0x0b -#define I2C_CR2_FREQ_12MHZ 0x0c -#define I2C_CR2_FREQ_13MHZ 0x0d -#define I2C_CR2_FREQ_14MHZ 0x0e -#define I2C_CR2_FREQ_15MHZ 0x0f -#define I2C_CR2_FREQ_16MHZ 0x10 -#define I2C_CR2_FREQ_17MHZ 0x11 -#define I2C_CR2_FREQ_18MHZ 0x12 -#define I2C_CR2_FREQ_19MHZ 0x13 -#define I2C_CR2_FREQ_20MHZ 0x14 -#define I2C_CR2_FREQ_21MHZ 0x15 -#define I2C_CR2_FREQ_22MHZ 0x16 -#define I2C_CR2_FREQ_23MHZ 0x17 -#define I2C_CR2_FREQ_24MHZ 0x18 -#define I2C_CR2_FREQ_25MHZ 0x19 -#define I2C_CR2_FREQ_26MHZ 0x1a -#define I2C_CR2_FREQ_27MHZ 0x1b -#define I2C_CR2_FREQ_28MHZ 0x1c -#define I2C_CR2_FREQ_29MHZ 0x1d -#define I2C_CR2_FREQ_30MHZ 0x1e -#define I2C_CR2_FREQ_31MHZ 0x1f -#define I2C_CR2_FREQ_32MHZ 0x20 -#define I2C_CR2_FREQ_33MHZ 0x21 -#define I2C_CR2_FREQ_34MHZ 0x22 -#define I2C_CR2_FREQ_35MHZ 0x23 -#define I2C_CR2_FREQ_36MHZ 0x24 - -/* --- I2Cx_OAR1 values ---------------------------------------------------- */ - -/* ADDMODE: Addressing mode (slave mode) */ -#define I2C_OAR1_ADDMODE (1 << 15) -#define I2C_OAR1_ADDMODE_7BIT 0 -#define I2C_OAR1_ADDMODE_10BIT 1 - -/* Note: Bit 14 should always be kept at 1 by software! */ - -/* Note: Bits [13:10] are reserved, and forced to 0 by hardware. */ - -/* ADD: Address bits: [7:1] in 7-bit mode, bits [9:0] in 10-bit mode */ - -/* --- I2Cx_OAR1 values ---------------------------------------------------- */ - -/* Note: Bits [15:8] are reserved, and forced to 0 by hardware. */ - -/* ADD2[7:1]: Interface address (bits [7:1] in dual addressing mode) */ - -/* ENDUAL: Dual addressing mode enable */ -#define I2C_OAR2_ENDUAL (1 << 0) - -/* --- I2Cx_DR values ------------------------------------------------------ */ - -/* Note: Bits [15:8] are reserved, and forced to 0 by hardware. */ - -/* DR[7:0] 8-bit data register */ - -/* --- I2Cx_SR1 values ----------------------------------------------------- */ - -/* SMBALERT: SMBus alert */ -#define I2C_SR1_SMBALERT (1 << 15) - -/* TIMEOUT: Timeout or Tlow Error */ -#define I2C_SR1_TIMEOUT (1 << 14) - -/* Note: Bit 13 is reserved, and forced to 0 by hardware. */ - -/* PECERR: PEC Error in reception */ -#define I2C_SR1_PECERR (1 << 12) - -/* OVR: Overrun/Underrun */ -#define I2C_SR1_OVR (1 << 11) - -/* AF: Acknowledge failure */ -#define I2C_SR1_AF (1 << 10) - -/* ARLO: Arbitration lost (master mode) */ -#define I2C_SR1_ARLO (1 << 9) - -/* BERR: Bus error */ -#define I2C_SR1_BERR (1 << 8) - -/* TxE: Data register empty (transmitters) */ -#define I2C_SR1_TxE (1 << 7) - -/* RxNE: Data register not empty (receivers) */ -#define I2C_SR1_RxNE (1 << 6) - -/* Note: Bit 5 is reserved, and forced to 0 by hardware. */ - -/* STOPF: STOP detection (slave mode) */ -#define I2C_SR1_STOPF (1 << 4) - -/* ADD10: 10-bit header sent (master mode) */ -#define I2C_SR1_ADD10 (1 << 3) - -/* BTF: Byte transfer finished */ -#define I2C_SR1_BTF (1 << 2) - -/* ADDR: Address sent (master mode) / address matched (slave mode) */ -#define I2C_SR1_ADDR (1 << 1) - -/* SB: Start bit (master mode) */ -#define I2C_SR1_SB (1 << 0) - -/* --- I2Cx_SR2 values ----------------------------------------------------- */ - -/* Bits [15:8]: PEC[7:0]: Packet error checking register */ - -/* DUALF: Dual flag (slave mode) */ -#define I2C_SR2_DUALF (1 << 7) - -/* SMBHOST: SMBus host header (slave mode) */ -#define I2C_SR2_SMBHOST (1 << 6) - -/* SMBDEFAULT: SMBus device default address (slave mode) */ -#define I2C_SR2_SMBDEFAULT (1 << 5) - -/* GENCALL: General call address (slave mode) */ -#define I2C_SR2_GENCALL (1 << 4) - -/* Note: Bit 3 is reserved, and forced to 0 by hardware. */ - -/* TRA: Transmitter / receiver */ -#define I2C_SR2_TRA (1 << 2) - -/* BUSY: Bus busy */ -#define I2C_SR2_BUSY (1 << 1) - -/* MSL: Master / slave */ -#define I2C_SR2_MSL (1 << 0) - -/* --- I2Cx_CCR values ----------------------------------------------------- */ - -/* F/S: I2C Master mode selection (fast / standard) */ -#define I2C_CCR_FS (1 << 15) - -/* DUTY: Fast Mode Duty Cycle */ -#define I2C_CCR_DUTY (1 << 14) - -/* Note: Bits [13:12] are reserved, and forced to 0 by hardware. */ - -/* - * Bits [11:0]: - * CCR[11:0]: Clock control register in Fast/Standard mode (master mode) - */ - -/* --- I2Cx_TRISE values --------------------------------------------------- */ - -/* Note: Bits [15:6] are reserved, and forced to 0 by hardware. */ - -/* - * Bits [5:0]: - * TRISE[5:0]: Maximum rise time in Fast/Standard mode (master mode) - */ - -/* --- I2C const definitions ----------------------------------------------- */ - -#define I2C_WRITE 0 -#define I2C_READ 1 - -/* --- I2C funtion prototypes----------------------------------------------- */ - -void i2c_peripheral_enable(u32 i2c); -void i2c_peripheral_disable(u32 i2c); -void i2c_send_start(u32 i2c); -void i2c_send_stop(u32 i2c); -void i2c_set_own_7bit_slave_address(u32 i2c, u8 slave); -void i2c_set_own_10bit_slave_address(u32 i2c, u16 slave); -void i2c_set_fast_mode(u32 i2c); -void i2c_set_standard_mode(u32 i2c); -void i2c_set_clock_frequency(u32 i2c, u8 freq); -void i2c_set_ccr(u32 i2c, u16 freq); -void i2c_set_trise(u32 i2c, u16 trise); -void i2c_send_7bit_address(u32 i2c, u8 slave, u8 readwrite); -void i2c_send_data(u32 i2c, u8 data); - -#endif -- cgit v1.2.3 From 0d4931f91feba0f2e99b58b6b18345696e390b7a Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Tue, 13 Sep 2011 18:39:44 -0700 Subject: Moved timer stuff to common and added F2 specific header. --- include/libopencm3/stm32_common/timer.h | 921 ++++++++++++++++++++++++++++++++ include/libopencm3/stm32f1/timer.h | 921 -------------------------------- include/libopencm3/stm32f2/timer.h | 54 ++ 3 files changed, 975 insertions(+), 921 deletions(-) create mode 100644 include/libopencm3/stm32_common/timer.h delete mode 100644 include/libopencm3/stm32f1/timer.h create mode 100644 include/libopencm3/stm32f2/timer.h diff --git a/include/libopencm3/stm32_common/timer.h b/include/libopencm3/stm32_common/timer.h new file mode 100644 index 0000000..c1eac99 --- /dev/null +++ b/include/libopencm3/stm32_common/timer.h @@ -0,0 +1,921 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Piotr Esden-Tempski + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_TIMER_H +#define LIBOPENCM3_TIMER_H + +#include +#include + +/* --- Convenience macros -------------------------------------------------- */ + +/* Timer register base adresses (for convenience) */ +#define TIM1 TIM1_BASE +#define TIM2 TIM2_BASE +#define TIM3 TIM3_BASE +#define TIM4 TIM4_BASE +#define TIM5 TIM5_BASE +#define TIM6 TIM6_BASE +#define TIM7 TIM7_BASE +#define TIM8 TIM8_BASE + +/* --- Timer registers ----------------------------------------------------- */ + +/* Control register 1 (TIMx_CR1) */ +#define TIM_CR1(tim_base) MMIO32(tim_base + 0x00) +#define TIM1_CR1 TIM_CR1(TIM1) +#define TIM2_CR1 TIM_CR1(TIM2) +#define TIM3_CR1 TIM_CR1(TIM3) +#define TIM4_CR1 TIM_CR1(TIM4) +#define TIM5_CR1 TIM_CR1(TIM5) +#define TIM6_CR1 TIM_CR1(TIM6) +#define TIM7_CR1 TIM_CR1(TIM7) +#define TIM8_CR1 TIM_CR1(TIM8) + +/* Control register 2 (TIMx_CR2) */ +#define TIM_CR2(tim_base) MMIO32(tim_base + 0x04) +#define TIM1_CR2 TIM_CR2(TIM1) +#define TIM2_CR2 TIM_CR2(TIM2) +#define TIM3_CR2 TIM_CR2(TIM3) +#define TIM4_CR2 TIM_CR2(TIM4) +#define TIM5_CR2 TIM_CR2(TIM5) +#define TIM6_CR2 TIM_CR2(TIM6) +#define TIM7_CR2 TIM_CR2(TIM7) +#define TIM8_CR2 TIM_CR2(TIM8) + +/* Slave mode control register (TIMx_SMCR) */ +#define TIM_SMCR(tim_base) MMIO32(tim_base + 0x08) +#define TIM1_SMCR TIM_SMCR(TIM1) +#define TIM2_SMCR TIM_SMCR(TIM2) +#define TIM3_SMCR TIM_SMCR(TIM3) +#define TIM4_SMCR TIM_SMCR(TIM4) +#define TIM5_SMCR TIM_SMCR(TIM5) +#define TIM8_SMCR TIM_SMCR(TIM8) + +/* DMA/Interrupt enable register (TIMx_DIER) */ +#define TIM_DIER(tim_base) MMIO32(tim_base + 0x0C) +#define TIM1_DIER TIM_DIER(TIM1) +#define TIM2_DIER TIM_DIER(TIM2) +#define TIM3_DIER TIM_DIER(TIM3) +#define TIM4_DIER TIM_DIER(TIM4) +#define TIM5_DIER TIM_DIER(TIM5) +#define TIM6_DIER TIM_DIER(TIM6) +#define TIM7_DIER TIM_DIER(TIM7) +#define TIM8_DIER TIM_DIER(TIM8) + +/* Status register (TIMx_SR) */ +#define TIM_SR(tim_base) MMIO32(tim_base + 0x10) +#define TIM1_SR TIM_SR(TIM1) +#define TIM2_SR TIM_SR(TIM2) +#define TIM3_SR TIM_SR(TIM3) +#define TIM4_SR TIM_SR(TIM4) +#define TIM5_SR TIM_SR(TIM5) +#define TIM6_SR TIM_SR(TIM6) +#define TIM7_SR TIM_SR(TIM7) +#define TIM8_SR TIM_SR(TIM8) + +/* Event generation register (TIMx_EGR) */ +#define TIM_EGR(tim_base) MMIO32(tim_base + 0x14) +#define TIM1_EGR TIM_EGR(TIM1) +#define TIM2_EGR TIM_EGR(TIM2) +#define TIM3_EGR TIM_EGR(TIM3) +#define TIM4_EGR TIM_EGR(TIM4) +#define TIM5_EGR TIM_EGR(TIM5) +#define TIM6_EGR TIM_EGR(TIM6) +#define TIM7_EGR TIM_EGR(TIM7) +#define TIM8_EGR TIM_EGR(TIM8) + +/* Capture/compare mode register 1 (TIMx_CCMR1) */ +#define TIM_CCMR1(tim_base) MMIO32(tim_base + 0x18) +#define TIM1_CCMR1 TIM_CCMR1(TIM1) +#define TIM2_CCMR1 TIM_CCMR1(TIM2) +#define TIM3_CCMR1 TIM_CCMR1(TIM3) +#define TIM4_CCMR1 TIM_CCMR1(TIM4) +#define TIM5_CCMR1 TIM_CCMR1(TIM5) +#define TIM8_CCMR1 TIM_CCMR1(TIM8) + +/* Capture/compare mode register 2 (TIMx_CCMR2) */ +#define TIM_CCMR2(tim_base) MMIO32(tim_base + 0x1C) +#define TIM1_CCMR2 TIM_CCMR2(TIM1) +#define TIM2_CCMR2 TIM_CCMR2(TIM2) +#define TIM3_CCMR2 TIM_CCMR2(TIM3) +#define TIM4_CCMR2 TIM_CCMR2(TIM4) +#define TIM5_CCMR2 TIM_CCMR2(TIM5) +#define TIM8_CCMR2 TIM_CCMR2(TIM8) + +/* Capture/compare enable register (TIMx_CCER) */ +#define TIM_CCER(tim_base) MMIO32(tim_base + 0x20) +#define TIM1_CCER TIM_CCER(TIM1) +#define TIM2_CCER TIM_CCER(TIM2) +#define TIM3_CCER TIM_CCER(TIM3) +#define TIM4_CCER TIM_CCER(TIM4) +#define TIM5_CCER TIM_CCER(TIM5) +#define TIM8_CCER TIM_CCER(TIM8) + +/* Counter (TIMx_CNT) */ +#define TIM_CNT(tim_base) MMIO32(tim_base + 0x24) +#define TIM1_CNT TIM_CNT(TIM1) +#define TIM2_CNT TIM_CNT(TIM2) +#define TIM3_CNT TIM_CNT(TIM3) +#define TIM4_CNT TIM_CNT(TIM4) +#define TIM5_CNT TIM_CNT(TIM5) +#define TIM6_CNT TIM_CNT(TIM6) +#define TIM7_CNT TIM_CNT(TIM7) +#define TIM8_CNT TIM_CNT(TIM8) + +/* Prescaler (TIMx_PSC) */ +#define TIM_PSC(tim_base) MMIO32(tim_base + 0x28) +#define TIM1_PSC TIM_PSC(TIM1) +#define TIM2_PSC TIM_PSC(TIM2) +#define TIM3_PSC TIM_PSC(TIM3) +#define TIM4_PSC TIM_PSC(TIM4) +#define TIM5_PSC TIM_PSC(TIM5) +#define TIM6_PSC TIM_PSC(TIM6) +#define TIM7_PSC TIM_PSC(TIM7) +#define TIM8_PSC TIM_PSC(TIM8) + +/* Auto-reload register (TIMx_ARR) */ +#define TIM_ARR(tim_base) MMIO32(tim_base + 0x2C) +#define TIM1_ARR TIM_ARR(TIM1) +#define TIM2_ARR TIM_ARR(TIM2) +#define TIM3_ARR TIM_ARR(TIM3) +#define TIM4_ARR TIM_ARR(TIM4) +#define TIM5_ARR TIM_ARR(TIM5) +#define TIM6_ARR TIM_ARR(TIM6) +#define TIM7_ARR TIM_ARR(TIM7) +#define TIM8_ARR TIM_ARR(TIM8) + +/* Repetition counter register (TIMx_RCR) */ +#define TIM_RCR(tim_base) MMIO32(tim_base + 0x30) +#define TIM1_RCR TIM_RCR(TIM1) +#define TIM8_RCR TIM_RCR(TIM8) + +/* Capture/compare register 1 (TIMx_CCR1) */ +#define TIM_CCR1(tim_base) MMIO32(tim_base + 0x34) +#define TIM1_CCR1 TIM_CCR1(TIM1) +#define TIM2_CCR1 TIM_CCR1(TIM2) +#define TIM3_CCR1 TIM_CCR1(TIM3) +#define TIM4_CCR1 TIM_CCR1(TIM4) +#define TIM5_CCR1 TIM_CCR1(TIM5) +#define TIM8_CCR1 TIM_CCR1(TIM8) + +/* Capture/compare register 2 (TIMx_CCR2) */ +#define TIM_CCR2(tim_base) MMIO32(tim_base + 0x38) +#define TIM1_CCR2 TIM_CCR2(TIM1) +#define TIM2_CCR2 TIM_CCR2(TIM2) +#define TIM3_CCR2 TIM_CCR2(TIM3) +#define TIM4_CCR2 TIM_CCR2(TIM4) +#define TIM5_CCR2 TIM_CCR2(TIM5) +#define TIM8_CCR2 TIM_CCR2(TIM8) + +/* Capture/compare register 3 (TIMx_CCR3) */ +#define TIM_CCR3(tim_base) MMIO32(tim_base + 0x3C) +#define TIM1_CCR3 TIM_CCR3(TIM1) +#define TIM2_CCR3 TIM_CCR3(TIM2) +#define TIM3_CCR3 TIM_CCR3(TIM3) +#define TIM4_CCR3 TIM_CCR3(TIM4) +#define TIM5_CCR3 TIM_CCR3(TIM5) +#define TIM8_CCR3 TIM_CCR3(TIM8) + +/* Capture/compare register 4 (TIMx_CCR4) */ +#define TIM_CCR4(tim_base) MMIO32(tim_base + 0x40) +#define TIM1_CCR4 TIM_CCR4(TIM1) +#define TIM2_CCR4 TIM_CCR4(TIM2) +#define TIM3_CCR4 TIM_CCR4(TIM3) +#define TIM4_CCR4 TIM_CCR4(TIM4) +#define TIM5_CCR4 TIM_CCR4(TIM5) +#define TIM8_CCR4 TIM_CCR4(TIM8) + +/* Break and dead-time register (TIMx_BDTR) */ +#define TIM_BDTR(tim_base) MMIO32(tim_base + 0x44) +#define TIM1_BDTR TIM_BDTR(TIM1) +#define TIM8_BDTR TIM_BDTR(TIM8) + +/* DMA control register (TIMx_DCR) */ +#define TIM_DCR(tim_base) MMIO32(tim_base + 0x48) +#define TIM1_DCR TIM_DCR(TIM1) +#define TIM2_DCR TIM_DCR(TIM2) +#define TIM3_DCR TIM_DCR(TIM3) +#define TIM4_DCR TIM_DCR(TIM4) +#define TIM5_DCR TIM_DCR(TIM5) +#define TIM8_DCR TIM_DCR(TIM8) + +/* DMA address for full transfer (TIMx_DMAR) */ +#define TIM_DMAR(tim_base) MMIO32(tim_base + 0x4C) +#define TIM1_DMAR TIM_DMAR(TIM1) +#define TIM2_DMAR TIM_DMAR(TIM2) +#define TIM3_DMAR TIM_DMAR(TIM3) +#define TIM4_DMAR TIM_DMAR(TIM4) +#define TIM5_DMAR TIM_DMAR(TIM5) +#define TIM8_DMAR TIM_DMAR(TIM8) + +/* --- TIMx_CR1 values ----------------------------------------------------- */ + +/* CKD[1:0]: Clock division */ +#define TIM_CR1_CKD_CK_INT (0x0 << 8) +#define TIM_CR1_CKD_CK_INT_MUL_2 (0x1 << 8) +#define TIM_CR1_CKD_CK_INT_MUL_4 (0x2 << 8) +#define TIM_CR1_CKD_CK_INT_MASK (0x3 << 8) + +/* ARPE: Auto-reload preload enable */ +#define TIM_CR1_ARPE (1 << 7) + +/* CMS[1:0]: Center-aligned mode selection */ +#define TIM_CR1_CMS_EDGE (0x0 << 5) +#define TIM_CR1_CMS_CENTER_1 (0x1 << 5) +#define TIM_CR1_CMS_CENTER_2 (0x2 << 5) +#define TIM_CR1_CMS_CENTER_3 (0x3 << 5) +#define TIM_CR1_CMS_MASK (0x3 << 5) + +/* DIR: Direction */ +#define TIM_CR1_DIR_UP (0 << 4) +#define TIM_CR1_DIR_DOWN (1 << 4) + +/* OPM: One pulse mode */ +#define TIM_CR1_OPM (1 << 3) + +/* URS: Update request source */ +#define TIM_CR1_URS (1 << 2) + +/* UDIS: Update disable */ +#define TIM_CR1_UDIS (1 << 1) + +/* CEN: Counter enable */ +#define TIM_CR1_CEN (1 << 0) + +/* --- TIMx_CR2 values ----------------------------------------------------- */ + +/* OIS4: Output idle state 4 (OC4 output) */ +#define TIM_CR2_OIS4 (1 << 14) + +/* OIS3N: Output idle state 3 (OC3N output) */ +#define TIM_CR2_OIS3N (1 << 13) + +/* OIS3: Output idle state 3 (OC3 output) */ +#define TIM_CR2_OIS3 (1 << 12) + +/* OIS2N: Output idle state 2 (OC2N output) */ +#define TIM_CR2_OIS2N (1 << 11) + +/* OIS2: Output idle state 2 (OC2 output) */ +#define TIM_CR2_OIS2 (1 << 10) + +/* OIS1N: Output idle state 1 (OC1N output) */ +#define TIM_CR2_OIS1N (1 << 9) + +/* OIS1: Output idle state 1 (OC1 output) */ +#define TIM_CR2_OIS1 (1 << 8) +#define TIM_CR2_OIS_MASK (0x7f << 8) + +/* TI1S: TI1 selection */ +#define TIM_CR2_TI1S (1 << 7) + +/* MMS[2:0]: Master mode selection */ +#define TIM_CR2_MMS_RESET (0x0 << 4) +#define TIM_CR2_MMS_ENABLE (0x1 << 4) +#define TIM_CR2_MMS_UPDATE (0x2 << 4) +#define TIM_CR2_MMS_COMPARE_PULSE (0x3 << 4) +#define TIM_CR2_MMS_COMPARE_OC1REF (0x4 << 4) +#define TIM_CR2_MMS_COMPARE_OC2REF (0x5 << 4) +#define TIM_CR2_MMS_COMPARE_OC3REF (0x6 << 4) +#define TIM_CR2_MMS_COMPARE_OC4REF (0x7 << 4) +#define TIM_CR2_MMS_MASK (0x7 << 4) + +/* CCDS: Capture/compare DMA selection */ +#define TIM_CR2_CCDS (1 << 3) + +/* CCUS: Capture/compare control update selection */ +#define TIM_CR2_CCUS (1 << 2) + +/* CCPC: Capture/compare preload control */ +#define TIM_CR2_CCPC (1 << 0) + +/* --- TIMx_SMCR values ---------------------------------------------------- */ + +/* ETP: External trigger polarity */ +#define TIM_SMCR_ETP (1 << 15) + +/* ECE: External clock enable */ +#define TIM_SMCR_ECE (1 << 14) + +/* ETPS[1:0]: External trigger prescaler */ +#define TIM_SMCR_ETPS_OFF (0x0 << 12) +#define TIM_SMCR_ETPS_ETRP_DIV_2 (0x1 << 12) +#define TIM_SMCR_ETPS_ETRP_DIV_4 (0x2 << 12) +#define TIM_SMCR_ETPS_ETRP_DIV_8 (0x3 << 12) +#define TIM_SMCR_ETPS_MASK (0X3 << 12) + +/* ETF[3:0]: External trigger filter */ +#define TIM_SMCR_ETF_OFF (0x0 << 8) +#define TIM_SMCR_ETF_CK_INT_N_2 (0x1 << 8) +#define TIM_SMCR_ETF_CK_INT_N_4 (0x2 << 8) +#define TIM_SMCR_ETF_CK_INT_N_8 (0x3 << 8) +#define TIM_SMCR_ETF_DTS_DIV_2_N_6 (0x4 << 8) +#define TIM_SMCR_ETF_DTS_DIV_2_N_8 (0x5 << 8) +#define TIM_SMCR_ETF_DTS_DIV_4_N_6 (0x6 << 8) +#define TIM_SMCR_ETF_DTS_DIV_4_N_8 (0x7 << 8) +#define TIM_SMCR_ETF_DTS_DIV_8_N_6 (0x8 << 8) +#define TIM_SMCR_ETF_DTS_DIV_8_N_8 (0x9 << 8) +#define TIM_SMCR_ETF_DTS_DIV_16_N_5 (0xA << 8) +#define TIM_SMCR_ETF_DTS_DIV_16_N_6 (0xB << 8) +#define TIM_SMCR_ETF_DTS_DIV_16_N_8 (0xC << 8) +#define TIM_SMCR_ETF_DTS_DIV_32_N_5 (0xD << 8) +#define TIM_SMCR_ETF_DTS_DIV_32_N_6 (0xE << 8) +#define TIM_SMCR_ETF_DTS_DIV_32_N_8 (0xF << 8) +#define TIM_SMCR_ETF_MASK (0xF << 8) + +/* MSM: Master/slave mode */ +#define TIM_SMCR_MSM (1 << 7) + +/* TS[2:0]: Trigger selection */ +#define TIM_SMCR_TS_ITR0 (0x0 << 4) +#define TIM_SMCR_TS_ITR1 (0x1 << 4) +#define TIM_SMCR_TS_ITR2 (0x2 << 4) +#define TIM_SMCR_TS_ITR3 (0x3 << 4) +#define TIM_SMCR_TS_IT1F_ED (0x4 << 4) +#define TIM_SMCR_TS_IT1FP1 (0x5 << 4) +#define TIM_SMCR_TS_IT1FP2 (0x6 << 4) +#define TIM_SMCR_TS_ETRF (0x7 << 4) +#define TIM_SMCR_TS_MASK (0x7 << 4) + +/* SMS[2:0]: Slave mode selection */ +#define TIM_SMCR_SMS_OFF (0x0 << 0) +#define TIM_SMCR_SMS_EM1 (0x1 << 0) +#define TIM_SMCR_SMS_EM2 (0x2 << 0) +#define TIM_SMCR_SMS_EM3 (0x3 << 0) +#define TIM_SMCR_SMS_RM (0x4 << 0) +#define TIM_SMCR_SMS_GM (0x5 << 0) +#define TIM_SMCR_SMS_TM (0x6 << 0) +#define TIM_SMCR_SMS_ECM1 (0x7 << 0) +#define TIM_SMCR_SMS_MASK (0x7 << 0) + +/* --- TIMx_DIER values ---------------------------------------------------- */ + +/* TDE: Trigger DMA request enable */ +#define TIM_DIER_TDE (1 << 14) + +/* COMDE: COM DMA request enable */ +#define TIM_DIER_COMDE (1 << 13) + +/* CC4DE: Capture/Compare 4 DMA request enable */ +#define TIM_DIER_CC4DE (1 << 12) + +/* CC3DE: Capture/Compare 3 DMA request enable */ +#define TIM_DIER_CC3DE (1 << 11) + +/* CC2DE: Capture/Compare 2 DMA request enable */ +#define TIM_DIER_CC2DE (1 << 10) + +/* CC1DE: Capture/Compare 1 DMA request enable */ +#define TIM_DIER_CC1DE (1 << 9) + +/* UDE: Update DMA request enable */ +#define TIM_DIER_UDE (1 << 8) + +/* BIE: Break interrupt enable */ +#define TIM_DIER_BIE (1 << 7) + +/* TIE: Trigger interrupt enable */ +#define TIM_DIER_TIE (1 << 6) + +/* COMIE: COM interrupt enable */ +#define TIM_DIER_COMIE (1 << 5) + +/* CC4IE: Capture/compare 4 interrupt enable */ +#define TIM_DIER_CC4IE (1 << 4) + +/* CC3IE: Capture/compare 3 interrupt enable */ +#define TIM_DIER_CC3IE (1 << 3) + +/* CC2IE: Capture/compare 2 interrupt enable */ +#define TIM_DIER_CC2IE (1 << 2) + +/* CC1IE: Capture/compare 1 interrupt enable */ +#define TIM_DIER_CC1IE (1 << 1) + +/* UIE: Update interrupt enable */ +#define TIM_DIER_UIE (1 << 0) + +/* --- TIMx_SR values ------------------------------------------------------ */ + +/* CC4OF: Capture/compare 4 overcapture flag */ +#define TIM_SR_CC4OF (1 << 12) + +/* CC3OF: Capture/compare 3 overcapture flag */ +#define TIM_SR_CC3OF (1 << 11) + +/* CC2OF: Capture/compare 2 overcapture flag */ +#define TIM_SR_CC2OF (1 << 10) + +/* CC1OF: Capture/compare 1 overcapture flag */ +#define TIM_SR_CC1OF (1 << 9) + +/* BIF: Break interrupt flag */ +#define TIM_SR_BIF (1 << 7) + +/* TIF: Trigger interrupt flag */ +#define TIM_SR_TIF (1 << 6) + +/* COMIF: COM interrupt flag */ +#define TIM_SR_COMIF (1 << 5) + +/* CC4IF: Capture/compare 4 interrupt flag */ +#define TIM_SR_CC4IF (1 << 4) + +/* CC3IF: Capture/compare 3 interrupt flag */ +#define TIM_SR_CC3IF (1 << 3) + +/* CC2IF: Capture/compare 2 interrupt flag */ +#define TIM_SR_CC2IF (1 << 2) + +/* CC1IF: Capture/compare 1 interrupt flag */ +#define TIM_SR_CC1IF (1 << 1) + +/* UIF: Update interrupt flag */ +#define TIM_SR_UIF (1 << 0) + +/* --- TIMx_EGR values ----------------------------------------------------- */ + +/* BG: Break generation */ +#define TIM_EGR_BG (1 << 7) + +/* TG: Trigger generation */ +#define TIM_EGR_TG (1 << 6) + +/* COMG: Capture/compare control update generation */ +#define TIM_EGR_COMG (1 << 5) + +/* CC4G: Capture/compare 4 generation */ +#define TIM_EGR_CC4G (1 << 4) + +/* CC3G: Capture/compare 3 generation */ +#define TIM_EGR_CC3G (1 << 3) + +/* CC2G: Capture/compare 2 generation */ +#define TIM_EGR_CC2G (1 << 2) + +/* CC1G: Capture/compare 1 generation */ +#define TIM_EGR_CC1G (1 << 1) + +/* UG: Update generation */ +#define TIM_EGR_UG (1 << 0) + +/* --- TIMx_CCMR1 values --------------------------------------------------- */ + +/* --- Output compare mode --- */ + +/* OC2CE: Output compare 2 clear enable */ +#define TIM_CCMR1_OC2CE (1 << 15) + +/* OC2M[2:0]: Output compare 2 mode */ +#define TIM_CCMR1_OC2M_FROZEN (0x0 << 12) +#define TIM_CCMR1_OC2M_ACTIVE (0x1 << 12) +#define TIM_CCMR1_OC2M_INACTIVE (0x2 << 12) +#define TIM_CCMR1_OC2M_TOGGLE (0x3 << 12) +#define TIM_CCMR1_OC2M_FORCE_LOW (0x4 << 12) +#define TIM_CCMR1_OC2M_FORCE_HIGH (0x5 << 12) +#define TIM_CCMR1_OC2M_PWM1 (0x6 << 12) +#define TIM_CCMR1_OC2M_PWM2 (0x7 << 12) +#define TIM_CCMR1_OC2M_MASK (0x7 << 12) + +/* OC2PE: Output compare 2 preload enable */ +#define TIM_CCMR1_OC2PE (1 << 11) + +/* OC2FE: Output compare 2 fast enable */ +#define TIM_CCMR1_OC2FE (1 << 10) + +/* CC2S[1:0]: Capture/compare 2 selection */ +/* Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in + * TIMx_CCER). */ +#define TIM_CCMR1_CC2S_OUT (0x0 << 8) +#define TIM_CCMR1_CC2S_IN_TI2 (0x1 << 8) +#define TIM_CCMR1_CC2S_IN_TI1 (0x2 << 8) +#define TIM_CCMR1_CC2S_IN_TRC (0x3 << 8) +#define TIM_CCMR1_CC2S_MASK (0x3 << 8) + +/* OC1CE: Output compare 1 clear enable */ +#define TIM_CCMR1_OC1CE (1 << 7) + +/* OC1M[2:0]: Output compare 1 mode */ +#define TIM_CCMR1_OC1M_FROZEN (0x0 << 4) +#define TIM_CCMR1_OC1M_ACTIVE (0x1 << 4) +#define TIM_CCMR1_OC1M_INACTIVE (0x2 << 4) +#define TIM_CCMR1_OC1M_TOGGLE (0x3 << 4) +#define TIM_CCMR1_OC1M_FORCE_LOW (0x4 << 4) +#define TIM_CCMR1_OC1M_FORCE_HIGH (0x5 << 4) +#define TIM_CCMR1_OC1M_PWM1 (0x6 << 4) +#define TIM_CCMR1_OC1M_PWM2 (0x7 << 4) +#define TIM_CCMR1_OC1M_MASK (0x7 << 4) + +/* OC1PE: Output compare 1 preload enable */ +#define TIM_CCMR1_OC1PE (1 << 3) + +/* OC1FE: Output compare 1 fast enable */ +#define TIM_CCMR1_OC1FE (1 << 2) + +/* CC1S[1:0]: Capture/compare 1 selection */ +/* Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in + * TIMx_CCER). */ +#define TIM_CCMR1_CC1S_OUT (0x0 << 0) +#define TIM_CCMR1_CC1S_IN_TI2 (0x1 << 0) +#define TIM_CCMR1_CC1S_IN_TI1 (0x2 << 0) +#define TIM_CCMR1_CC1S_IN_TRC (0x3 << 0) +#define TIM_CCMR1_CC1S_MASK (0x3 << 0) + +/* --- Input capture mode --- */ + +/* IC2F[3:0]: Input capture 2 filter */ +#define TIM_CCMR1_IC2F_OFF (0x0 << 12) +#define TIM_CCMR1_IC2F_CK_INT_N_2 (0x1 << 12) +#define TIM_CCMR1_IC2F_CK_INT_N_4 (0x2 << 12) +#define TIM_CCMR1_IC2F_CK_INT_N_8 (0x3 << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_2_N_6 (0x4 << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_2_N_8 (0x5 << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_4_N_6 (0x6 << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_4_N_8 (0x7 << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_8_N_6 (0x8 << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_8_N_8 (0x9 << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_16_N_5 (0xA << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_16_N_6 (0xB << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_16_N_8 (0xC << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_32_N_5 (0xD << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_32_N_6 (0xE << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_32_N_8 (0xF << 12) +#define TIM_CCMR1_IC2F_MASK (0xF << 12) + +/* IC2PSC[1:0]: Input capture 2 prescaler */ +#define TIM_CCMR1_IC2PSC_OFF (0x0 << 10) +#define TIM_CCMR1_IC2PSC_2 (0x1 << 10) +#define TIM_CCMR1_IC2PSC_4 (0x2 << 10) +#define TIM_CCMR1_IC2PSC_8 (0x3 << 10) +#define TIM_CCMR1_IC2PSC_MASK (0x3 << 10) + +/* IC1F[3:0]: Input capture 1 filter */ +#define TIM_CCMR1_IC1F_OFF (0x0 << 4) +#define TIM_CCMR1_IC1F_CK_INT_N_2 (0x1 << 4) +#define TIM_CCMR1_IC1F_CK_INT_N_4 (0x2 << 4) +#define TIM_CCMR1_IC1F_CK_INT_N_8 (0x3 << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_2_N_6 (0x4 << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_2_N_8 (0x5 << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_4_N_6 (0x6 << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_4_N_8 (0x7 << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_8_N_6 (0x8 << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_8_N_8 (0x9 << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_16_N_5 (0xA << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_16_N_6 (0xB << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_16_N_8 (0xC << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_32_N_5 (0xD << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_32_N_6 (0xE << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_32_N_8 (0xF << 4) +#define TIM_CCMR1_IC1F_MASK (0xF << 4) + +/* IC1PSC[1:0]: Input capture 1 prescaler */ +#define TIM_CCMR1_IC1PSC_OFF (0x0 << 2) +#define TIM_CCMR1_IC1PSC_2 (0x1 << 2) +#define TIM_CCMR1_IC1PSC_4 (0x2 << 2) +#define TIM_CCMR1_IC1PSC_8 (0x3 << 2) +#define TIM_CCMR1_IC1PSC_MASK (0x3 << 2) + +/* --- TIMx_CCMR2 values --------------------------------------------------- */ + +/* --- Output compare mode --- */ + +/* OC4CE: Output compare 4 clear enable */ +#define TIM_CCMR2_OC4CE (1 << 15) + +/* OC4M[2:0]: Output compare 4 mode */ +#define TIM_CCMR2_OC4M_FROZEN (0x0 << 12) +#define TIM_CCMR2_OC4M_ACTIVE (0x1 << 12) +#define TIM_CCMR2_OC4M_INACTIVE (0x2 << 12) +#define TIM_CCMR2_OC4M_TOGGLE (0x3 << 12) +#define TIM_CCMR2_OC4M_FORCE_LOW (0x4 << 12) +#define TIM_CCMR2_OC4M_FORCE_HIGH (0x5 << 12) +#define TIM_CCMR2_OC4M_PWM1 (0x6 << 12) +#define TIM_CCMR2_OC4M_PWM2 (0x7 << 12) +#define TIM_CCMR2_OC4M_MASK (0x7 << 12) + +/* OC4PE: Output compare 4 preload enable */ +#define TIM_CCMR2_OC4PE (1 << 11) + +/* OC4FE: Output compare 4 fast enable */ +#define TIM_CCMR2_OC4FE (1 << 10) + +/* CC4S[1:0]: Capture/compare 4 selection */ +/* Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in + * TIMx_CCER). */ +#define TIM_CCMR2_CC4S_OUT (0x0 << 8) +#define TIM_CCMR2_CC4S_IN_TI2 (0x1 << 8) +#define TIM_CCMR2_CC4S_IN_TI1 (0x2 << 8) +#define TIM_CCMR2_CC4S_IN_TRC (0x3 << 8) +#define TIM_CCMR2_CC4S_MASK (0x3 << 8) + +/* OC3CE: Output compare 3 clear enable */ +#define TIM_CCMR2_OC3CE (1 << 7) + +/* OC3M[2:0]: Output compare 3 mode */ +#define TIM_CCMR2_OC3M_FROZEN (0x0 << 4) +#define TIM_CCMR2_OC3M_ACTIVE (0x1 << 4) +#define TIM_CCMR2_OC3M_INACTIVE (0x2 << 4) +#define TIM_CCMR2_OC3M_TOGGLE (0x3 << 4) +#define TIM_CCMR2_OC3M_FORCE_LOW (0x4 << 4) +#define TIM_CCMR2_OC3M_FORCE_HIGH (0x5 << 4) +#define TIM_CCMR2_OC3M_PWM1 (0x6 << 4) +#define TIM_CCMR2_OC3M_PWM2 (0x7 << 4) +#define TIM_CCMR2_OC3M_MASK (0x7 << 4) + +/* OC3PE: Output compare 3 preload enable */ +#define TIM_CCMR2_OC3PE (1 << 3) + +/* OC3FE: Output compare 3 fast enable */ +#define TIM_CCMR2_OC3FE (1 << 2) + +/* CC3S[1:0]: Capture/compare 3 selection */ +/* Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in + * TIMx_CCER). */ +#define TIM_CCMR2_CC3S_OUT (0x0 << 0) +#define TIM_CCMR2_CC3S_IN_TI2 (0x1 << 0) +#define TIM_CCMR2_CC3S_IN_TI1 (0x2 << 0) +#define TIM_CCMR2_CC3S_IN_TRC (0x3 << 0) +#define TIM_CCMR2_CC3S_MASK (0x3 << 0) + +/* --- Input capture mode --- */ + +/* IC4F[3:0]: Input capture 4 filter */ +#define TIM_CCMR2_IC4F_OFF (0x0 << 12) +#define TIM_CCMR2_IC4F_CK_INT_N_2 (0x1 << 12) +#define TIM_CCMR2_IC4F_CK_INT_N_4 (0x2 << 12) +#define TIM_CCMR2_IC4F_CK_INT_N_8 (0x3 << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_2_N_6 (0x4 << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_2_N_8 (0x5 << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_4_N_6 (0x6 << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_4_N_8 (0x7 << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_8_N_6 (0x8 << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_8_N_8 (0x9 << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_16_N_5 (0xA << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_16_N_6 (0xB << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_16_N_8 (0xC << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_32_N_5 (0xD << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_32_N_6 (0xE << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_32_N_8 (0xF << 12) +#define TIM_CCMR2_IC4F_MASK (0xF << 12) + +/* IC4PSC[1:0]: Input capture 4 prescaler */ +#define TIM_CCMR2_IC4PSC_OFF (0x0 << 10) +#define TIM_CCMR2_IC4PSC_2 (0x1 << 10) +#define TIM_CCMR2_IC4PSC_4 (0x2 << 10) +#define TIM_CCMR2_IC4PSC_8 (0x3 << 10) +#define TIM_CCMR2_IC4PSC_MASK (0x3 << 10) + +/* IC3F[3:0]: Input capture 3 filter */ +#define TIM_CCMR2_IC3F_OFF (0x0 << 4) +#define TIM_CCMR2_IC3F_CK_INT_N_2 (0x1 << 4) +#define TIM_CCMR2_IC3F_CK_INT_N_4 (0x2 << 4) +#define TIM_CCMR2_IC3F_CK_INT_N_8 (0x3 << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_2_N_6 (0x4 << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_2_N_8 (0x5 << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_4_N_6 (0x6 << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_4_N_8 (0x7 << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_8_N_6 (0x8 << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_8_N_8 (0x9 << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_16_N_5 (0xA << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_16_N_6 (0xB << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_16_N_8 (0xC << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_32_N_5 (0xD << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_32_N_6 (0xE << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_32_N_8 (0xF << 4) +#define TIM_CCMR2_IC3F_MASK (0xF << 4) + +/* IC3PSC[1:0]: Input capture 3 prescaler */ +#define TIM_CCMR2_IC3PSC_OFF (0x0 << 2) +#define TIM_CCMR2_IC3PSC_2 (0x1 << 2) +#define TIM_CCMR2_IC3PSC_4 (0x2 << 2) +#define TIM_CCMR2_IC3PSC_8 (0x3 << 2) +#define TIM_CCMR2_IC3PSC_MASK (0x3 << 2) + +/* --- TIMx_CCER values ---------------------------------------------------- */ + +/* CC4P: Capture/compare 4 output polarity */ +#define TIM_CCER_CC4P (1 << 13) + +/* CC4E: Capture/compare 4 output enable */ +#define TIM_CCER_CC4E (1 << 12) + +/* CC3NP: Capture/compare 3 complementary output polarity */ +#define TIM_CCER_CC3NP (1 << 11) + +/* CC3NE: Capture/compare 3 complementary output enable */ +#define TIM_CCER_CC3NE (1 << 10) + +/* CC3P: Capture/compare 3 output polarity */ +#define TIM_CCER_CC3P (1 << 9) + +/* CC3E: Capture/compare 3 output enable */ +#define TIM_CCER_CC3E (1 << 8) + +/* CC2NP: Capture/compare 2 complementary output polarity */ +#define TIM_CCER_CC2NP (1 << 7) + +/* CC2NE: Capture/compare 2 complementary output enable */ +#define TIM_CCER_CC2NE (1 << 6) + +/* CC2P: Capture/compare 2 output polarity */ +#define TIM_CCER_CC2P (1 << 5) + +/* CC2E: Capture/compare 2 output enable */ +#define TIM_CCER_CC2E (1 << 4) + +/* CC1NP: Capture/compare 1 complementary output polarity */ +#define TIM_CCER_CC1NP (1 << 3) + +/* CC1NE: Capture/compare 1 complementary output enable */ +#define TIM_CCER_CC1NE (1 << 2) + +/* CC1P: Capture/compare 1 output polarity */ +#define TIM_CCER_CC1P (1 << 1) + +/* CC1E: Capture/compare 1 output enable */ +#define TIM_CCER_CC1E (1 << 0) + +/* --- TIMx_CNT values ----------------------------------------------------- */ + +/* CNT[15:0]: Counter value */ + +/* --- TIMx_PSC values ----------------------------------------------------- */ + +/* PSC[15:0]: Prescaler value */ + +/* --- TIMx_ARR values ----------------------------------------------------- */ + +/* ARR[15:0]: Prescaler value */ + +/* --- TIMx_RCR values ----------------------------------------------------- */ + +/* REP[15:0]: Repetition counter value */ + +/* --- TIMx_CCR1 values ---------------------------------------------------- */ + +/* CCR1[15:0]: Capture/compare 1 value */ + +/* --- TIMx_CCR2 values ---------------------------------------------------- */ + +/* CCR2[15:0]: Capture/compare 2 value */ + +/* --- TIMx_CCR3 values ---------------------------------------------------- */ + +/* CCR3[15:0]: Capture/compare 3 value */ + +/* --- TIMx_CCR4 values ---------------------------------------------------- */ + +/* CCR4[15:0]: Capture/compare 4 value */ + +/* --- TIMx_BDTR values ---------------------------------------------------- */ + +/* MOE: Main output enable */ +#define TIM_BDTR_MOE (1 << 15) + +/* AOE: Automatic output enable */ +#define TIM_BDTR_AOE (1 << 14) + +/* BKP: Break polarity */ +#define TIM_BDTR_BKP (1 << 13) + +/* BKE: Break enable */ +#define TIM_BDTR_BKE (1 << 12) + +/* OSSR: Off-state selection of run mode */ +#define TIM_BDTR_OSSR (1 << 11) + +/* OSSI: Off-state selection of idle mode */ +#define TIM_BDTR_OSSI (1 << 10) + +/* LOCK[1:0]: Lock configuration */ +#define TIM_BDTR_LOCK_OFF (0x0 << 8) +#define TIM_BDTR_LOCK_LEVEL_1 (0x1 << 8) +#define TIM_BDTR_LOCK_LEVEL_2 (0x2 << 8) +#define TIM_BDTR_LOCK_LEVEL_3 (0x3 << 8) +#define TIM_BDTR_LOCK_MASK (0x3 << 8) + +/* DTG[7:0]: Dead-time generator set-up */ +#define TIM_BDTR_DTG_MASK 0x00FF + +/* --- TIMx_DCR values ----------------------------------------------------- */ + +/* DBL[4:0]: DMA burst length */ +#define TIM_BDTR_DBL_MASK (0x1F << 8) + +/* DBA[4:0]: DMA base address */ +#define TIM_BDTR_DBA_MASK (0x1F << 0) + +/* --- TIMx_DMAR values ---------------------------------------------------- */ + +/* DMAB[15:0]: DMA register for burst accesses */ + +/* --- TIMx convenience defines -------------------------------------------- */ + +/* Output Compare channel designators */ +enum tim_oc_id { + TIM_OC1=0, + TIM_OC1N, + TIM_OC2, + TIM_OC2N, + TIM_OC3, + TIM_OC3N, + TIM_OC4, +}; + +/* Output Compare mode designators */ +enum tim_oc_mode { + TIM_OCM_FROZEN, + TIM_OCM_ACTIVE, + TIM_OCM_INACTIVE, + TIM_OCM_TOGGLE, + TIM_OCM_FORCE_LOW, + TIM_OCM_FORCE_HIGH, + TIM_OCM_PWM1, + TIM_OCM_PWM2, +}; + +/* --- TIM functions ------------------------------------------------------- */ +void timer_reset(u32 timer_peripheral); +void timer_enable_irq(u32 timer_peripheral, u32 irq); +void timer_disable_irq(u32 timer_peripheral, u32 irq); +bool timer_get_flag(u32 timer_peripheral, u32 flag); +void timer_clear_flag(u32 timer_peripheral, u32 flag); +void timer_set_mode(u32 timer_peripheral, u8 clock_div, + u8 alignment, u8 direction); +void timer_set_clock_division(u32 timer_peripheral, u32 clock_div); +void timer_enable_preload(u32 timer_peripheral); +void timer_disable_preload(u32 timer_peripheral); +void timer_set_alignment(u32 timer_peripheral, u32 alignment); +void timer_direction_up(u32 timer_peripheral); +void timer_direction_down(u32 timer_peripheral); +void timer_one_shot_mode(u32 timer_peripheral); +void timer_continuous_mode(u32 timer_peripheral); +void timer_update_on_any(u32 timer_peripheral); +void timer_update_on_overflow(u32 timer_peripheral); +void timer_enable_update_event(u32 timer_peripheral); +void timer_disable_update_event(u32 timer_peripheral); +void timer_enable_counter(u32 timer_peripheral); +void timer_disable_counter(u32 timer_peripheral); +void timer_set_output_idle_state(u32 timer_peripheral, u32 outputs); +void timer_reset_output_idle_state(u32 timer_peripheral, u32 outputs); +void timer_set_ti1_ch123_xor(u32 timer_peripheral); +void timer_set_ti1_ch1(u32 timer_peripheral); +void timer_set_master_mode(u32 timer_peripheral, u32 mode); +void timer_set_dma_on_compare_event(u32 timer_peripheral); +void timer_set_dma_on_update_event(u32 timer_peripheral); +void timer_enable_compare_control_update_on_trigger(u32 timer_peripheral); +void timer_disable_compare_control_update_on_trigger(u32 timer_peripheral); +void timer_enable_preload_complementry_enable_bits(u32 timer_peripheral); +void timer_disable_preload_complementry_enable_bits(u32 timer_peripheral); +void timer_set_prescaler(u32 timer_peripheral, u32 value); +void timer_set_repetition_counter(u32 timer_peripheral, u32 value); +void timer_set_period(u32 timer_peripheral, u32 period); +void timer_enable_oc_clear(u32 timer_peripheral, enum tim_oc_id oc_id); +void timer_disable_oc_clear(u32 timer_peripheral, enum tim_oc_id oc_id); +void timer_set_oc_fast_mode(u32 timer_peripheral, enum tim_oc_id oc_id); +void timer_set_oc_slow_mode(u32 timer_peripheral, enum tim_oc_id oc_id); +void timer_set_oc_mode(u32 timer_peripheral, enum tim_oc_id oc_id, enum tim_oc_mode oc_mode); +void timer_enable_oc_preload(u32 timer_peripheral, enum tim_oc_id oc_id); +void timer_disable_oc_preload(u32 timer_peripheral, enum tim_oc_id oc_id); +void timer_set_oc_polarity_high(u32 timer_peripheral, enum tim_oc_id oc_id); +void timer_set_oc_polarity_low(u32 timer_peripheral, enum tim_oc_id oc_id); +void timer_enable_oc_output(u32 timer_peripheral, enum tim_oc_id oc_id); +void timer_disable_oc_output(u32 timer_peripheral, enum tim_oc_id oc_id); +void timer_set_oc_idle_state_set(u32 timer_peripheral, enum tim_oc_id oc_id); +void timer_set_oc_idle_state_unset(u32 timer_peripheral, enum tim_oc_id oc_id); +void timer_set_oc_value(u32 timer_peripheral, enum tim_oc_id oc_id, u32 value); +void timer_enable_break_main_output(u32 timer_peripheral); +void timer_disable_break_main_output(u32 timer_peripheral); +void timer_enable_break_automatic_output(u32 timer_peripheral); +void timer_disable_break_automatic_output(u32 timer_peripheral); +void timer_set_break_polarity_high(u32 timer_peripheral); +void timer_set_break_polarity_low(u32 timer_peripheral); +void timer_enable_break(u32 timer_peripheral); +void timer_disable_break(u32 timer_peripheral); +void timer_set_enabled_off_state_in_run_mode(u32 timer_peripheral); +void timer_set_disabled_off_state_in_run_mode(u32 timer_peripheral); +void timer_set_enabled_off_state_in_idle_mode(u32 timer_peripheral); +void timer_set_disabled_off_state_in_idle_mode(u32 timer_peripheral); +void timer_set_break_lock(u32 timer_peripheral, u32 lock); +void timer_set_deadtime(u32 timer_peripheral, u32 deadtime); +void timer_generate_event(u32 timer_peripheral, u32 event); +u32 timer_get_counter(u32 timer_peripheral); + +#endif diff --git a/include/libopencm3/stm32f1/timer.h b/include/libopencm3/stm32f1/timer.h deleted file mode 100644 index 7b5df86..0000000 --- a/include/libopencm3/stm32f1/timer.h +++ /dev/null @@ -1,921 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Piotr Esden-Tempski - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_TIMER_H -#define LIBOPENCM3_TIMER_H - -#include -#include - -/* --- Convenience macros -------------------------------------------------- */ - -/* Timer register base adresses (for convenience) */ -#define TIM1 TIM1_BASE -#define TIM2 TIM2_BASE -#define TIM3 TIM3_BASE -#define TIM4 TIM4_BASE -#define TIM5 TIM5_BASE -#define TIM6 TIM6_BASE -#define TIM7 TIM7_BASE -#define TIM8 TIM8_BASE - -/* --- Timer registers ----------------------------------------------------- */ - -/* Control register 1 (TIMx_CR1) */ -#define TIM_CR1(tim_base) MMIO32(tim_base + 0x00) -#define TIM1_CR1 TIM_CR1(TIM1) -#define TIM2_CR1 TIM_CR1(TIM2) -#define TIM3_CR1 TIM_CR1(TIM3) -#define TIM4_CR1 TIM_CR1(TIM4) -#define TIM5_CR1 TIM_CR1(TIM5) -#define TIM6_CR1 TIM_CR1(TIM6) -#define TIM7_CR1 TIM_CR1(TIM7) -#define TIM8_CR1 TIM_CR1(TIM8) - -/* Control register 2 (TIMx_CR2) */ -#define TIM_CR2(tim_base) MMIO32(tim_base + 0x04) -#define TIM1_CR2 TIM_CR2(TIM1) -#define TIM2_CR2 TIM_CR2(TIM2) -#define TIM3_CR2 TIM_CR2(TIM3) -#define TIM4_CR2 TIM_CR2(TIM4) -#define TIM5_CR2 TIM_CR2(TIM5) -#define TIM6_CR2 TIM_CR2(TIM6) -#define TIM7_CR2 TIM_CR2(TIM7) -#define TIM8_CR2 TIM_CR2(TIM8) - -/* Slave mode control register (TIMx_SMCR) */ -#define TIM_SMCR(tim_base) MMIO32(tim_base + 0x08) -#define TIM1_SMCR TIM_SMCR(TIM1) -#define TIM2_SMCR TIM_SMCR(TIM2) -#define TIM3_SMCR TIM_SMCR(TIM3) -#define TIM4_SMCR TIM_SMCR(TIM4) -#define TIM5_SMCR TIM_SMCR(TIM5) -#define TIM8_SMCR TIM_SMCR(TIM8) - -/* DMA/Interrupt enable register (TIMx_DIER) */ -#define TIM_DIER(tim_base) MMIO32(tim_base + 0x0C) -#define TIM1_DIER TIM_DIER(TIM1) -#define TIM2_DIER TIM_DIER(TIM2) -#define TIM3_DIER TIM_DIER(TIM3) -#define TIM4_DIER TIM_DIER(TIM4) -#define TIM5_DIER TIM_DIER(TIM5) -#define TIM6_DIER TIM_DIER(TIM6) -#define TIM7_DIER TIM_DIER(TIM7) -#define TIM8_DIER TIM_DIER(TIM8) - -/* Status register (TIMx_SR) */ -#define TIM_SR(tim_base) MMIO32(tim_base + 0x10) -#define TIM1_SR TIM_SR(TIM1) -#define TIM2_SR TIM_SR(TIM2) -#define TIM3_SR TIM_SR(TIM3) -#define TIM4_SR TIM_SR(TIM4) -#define TIM5_SR TIM_SR(TIM5) -#define TIM6_SR TIM_SR(TIM6) -#define TIM7_SR TIM_SR(TIM7) -#define TIM8_SR TIM_SR(TIM8) - -/* Event generation register (TIMx_EGR) */ -#define TIM_EGR(tim_base) MMIO32(tim_base + 0x14) -#define TIM1_EGR TIM_EGR(TIM1) -#define TIM2_EGR TIM_EGR(TIM2) -#define TIM3_EGR TIM_EGR(TIM3) -#define TIM4_EGR TIM_EGR(TIM4) -#define TIM5_EGR TIM_EGR(TIM5) -#define TIM6_EGR TIM_EGR(TIM6) -#define TIM7_EGR TIM_EGR(TIM7) -#define TIM8_EGR TIM_EGR(TIM8) - -/* Capture/compare mode register 1 (TIMx_CCMR1) */ -#define TIM_CCMR1(tim_base) MMIO32(tim_base + 0x18) -#define TIM1_CCMR1 TIM_CCMR1(TIM1) -#define TIM2_CCMR1 TIM_CCMR1(TIM2) -#define TIM3_CCMR1 TIM_CCMR1(TIM3) -#define TIM4_CCMR1 TIM_CCMR1(TIM4) -#define TIM5_CCMR1 TIM_CCMR1(TIM5) -#define TIM8_CCMR1 TIM_CCMR1(TIM8) - -/* Capture/compare mode register 2 (TIMx_CCMR2) */ -#define TIM_CCMR2(tim_base) MMIO32(tim_base + 0x1C) -#define TIM1_CCMR2 TIM_CCMR2(TIM1) -#define TIM2_CCMR2 TIM_CCMR2(TIM2) -#define TIM3_CCMR2 TIM_CCMR2(TIM3) -#define TIM4_CCMR2 TIM_CCMR2(TIM4) -#define TIM5_CCMR2 TIM_CCMR2(TIM5) -#define TIM8_CCMR2 TIM_CCMR2(TIM8) - -/* Capture/compare enable register (TIMx_CCER) */ -#define TIM_CCER(tim_base) MMIO32(tim_base + 0x20) -#define TIM1_CCER TIM_CCER(TIM1) -#define TIM2_CCER TIM_CCER(TIM2) -#define TIM3_CCER TIM_CCER(TIM3) -#define TIM4_CCER TIM_CCER(TIM4) -#define TIM5_CCER TIM_CCER(TIM5) -#define TIM8_CCER TIM_CCER(TIM8) - -/* Counter (TIMx_CNT) */ -#define TIM_CNT(tim_base) MMIO32(tim_base + 0x24) -#define TIM1_CNT TIM_CNT(TIM1) -#define TIM2_CNT TIM_CNT(TIM2) -#define TIM3_CNT TIM_CNT(TIM3) -#define TIM4_CNT TIM_CNT(TIM4) -#define TIM5_CNT TIM_CNT(TIM5) -#define TIM6_CNT TIM_CNT(TIM6) -#define TIM7_CNT TIM_CNT(TIM7) -#define TIM8_CNT TIM_CNT(TIM8) - -/* Prescaler (TIMx_PSC) */ -#define TIM_PSC(tim_base) MMIO32(tim_base + 0x28) -#define TIM1_PSC TIM_PSC(TIM1) -#define TIM2_PSC TIM_PSC(TIM2) -#define TIM3_PSC TIM_PSC(TIM3) -#define TIM4_PSC TIM_PSC(TIM4) -#define TIM5_PSC TIM_PSC(TIM5) -#define TIM6_PSC TIM_PSC(TIM6) -#define TIM7_PSC TIM_PSC(TIM7) -#define TIM8_PSC TIM_PSC(TIM8) - -/* Auto-reload register (TIMx_ARR) */ -#define TIM_ARR(tim_base) MMIO32(tim_base + 0x2C) -#define TIM1_ARR TIM_ARR(TIM1) -#define TIM2_ARR TIM_ARR(TIM2) -#define TIM3_ARR TIM_ARR(TIM3) -#define TIM4_ARR TIM_ARR(TIM4) -#define TIM5_ARR TIM_ARR(TIM5) -#define TIM6_ARR TIM_ARR(TIM6) -#define TIM7_ARR TIM_ARR(TIM7) -#define TIM8_ARR TIM_ARR(TIM8) - -/* Repetition counter register (TIMx_RCR) */ -#define TIM_RCR(tim_base) MMIO32(tim_base + 0x30) -#define TIM1_RCR TIM_RCR(TIM1) -#define TIM8_RCR TIM_RCR(TIM8) - -/* Capture/compare register 1 (TIMx_CCR1) */ -#define TIM_CCR1(tim_base) MMIO32(tim_base + 0x34) -#define TIM1_CCR1 TIM_CCR1(TIM1) -#define TIM2_CCR1 TIM_CCR1(TIM2) -#define TIM3_CCR1 TIM_CCR1(TIM3) -#define TIM4_CCR1 TIM_CCR1(TIM4) -#define TIM5_CCR1 TIM_CCR1(TIM5) -#define TIM8_CCR1 TIM_CCR1(TIM8) - -/* Capture/compare register 2 (TIMx_CCR2) */ -#define TIM_CCR2(tim_base) MMIO32(tim_base + 0x38) -#define TIM1_CCR2 TIM_CCR2(TIM1) -#define TIM2_CCR2 TIM_CCR2(TIM2) -#define TIM3_CCR2 TIM_CCR2(TIM3) -#define TIM4_CCR2 TIM_CCR2(TIM4) -#define TIM5_CCR2 TIM_CCR2(TIM5) -#define TIM8_CCR2 TIM_CCR2(TIM8) - -/* Capture/compare register 3 (TIMx_CCR3) */ -#define TIM_CCR3(tim_base) MMIO32(tim_base + 0x3C) -#define TIM1_CCR3 TIM_CCR3(TIM1) -#define TIM2_CCR3 TIM_CCR3(TIM2) -#define TIM3_CCR3 TIM_CCR3(TIM3) -#define TIM4_CCR3 TIM_CCR3(TIM4) -#define TIM5_CCR3 TIM_CCR3(TIM5) -#define TIM8_CCR3 TIM_CCR3(TIM8) - -/* Capture/compare register 4 (TIMx_CCR4) */ -#define TIM_CCR4(tim_base) MMIO32(tim_base + 0x40) -#define TIM1_CCR4 TIM_CCR4(TIM1) -#define TIM2_CCR4 TIM_CCR4(TIM2) -#define TIM3_CCR4 TIM_CCR4(TIM3) -#define TIM4_CCR4 TIM_CCR4(TIM4) -#define TIM5_CCR4 TIM_CCR4(TIM5) -#define TIM8_CCR4 TIM_CCR4(TIM8) - -/* Break and dead-time register (TIMx_BDTR) */ -#define TIM_BDTR(tim_base) MMIO32(tim_base + 0x44) -#define TIM1_BDTR TIM_BDTR(TIM1) -#define TIM8_BDTR TIM_BDTR(TIM8) - -/* DMA control register (TIMx_DCR) */ -#define TIM_DCR(tim_base) MMIO32(tim_base + 0x48) -#define TIM1_DCR TIM_DCR(TIM1) -#define TIM2_DCR TIM_DCR(TIM2) -#define TIM3_DCR TIM_DCR(TIM3) -#define TIM4_DCR TIM_DCR(TIM4) -#define TIM5_DCR TIM_DCR(TIM5) -#define TIM8_DCR TIM_DCR(TIM8) - -/* DMA address for full transfer (TIMx_DMAR) */ -#define TIM_DMAR(tim_base) MMIO32(tim_base + 0x4C) -#define TIM1_DMAR TIM_DMAR(TIM1) -#define TIM2_DMAR TIM_DMAR(TIM2) -#define TIM3_DMAR TIM_DMAR(TIM3) -#define TIM4_DMAR TIM_DMAR(TIM4) -#define TIM5_DMAR TIM_DMAR(TIM5) -#define TIM8_DMAR TIM_DMAR(TIM8) - -/* --- TIMx_CR1 values ----------------------------------------------------- */ - -/* CKD[1:0]: Clock division */ -#define TIM_CR1_CKD_CK_INT (0x0 << 8) -#define TIM_CR1_CKD_CK_INT_MUL_2 (0x1 << 8) -#define TIM_CR1_CKD_CK_INT_MUL_4 (0x2 << 8) -#define TIM_CR1_CKD_CK_INT_MASK (0x3 << 8) - -/* ARPE: Auto-reload preload enable */ -#define TIM_CR1_ARPE (1 << 7) - -/* CMS[1:0]: Center-aligned mode selection */ -#define TIM_CR1_CMS_EDGE (0x0 << 5) -#define TIM_CR1_CMS_CENTER_1 (0x1 << 5) -#define TIM_CR1_CMS_CENTER_2 (0x2 << 5) -#define TIM_CR1_CMS_CENTER_3 (0x3 << 5) -#define TIM_CR1_CMS_MASK (0x3 << 5) - -/* DIR: Direction */ -#define TIM_CR1_DIR_UP (0 << 4) -#define TIM_CR1_DIR_DOWN (1 << 4) - -/* OPM: One pulse mode */ -#define TIM_CR1_OPM (1 << 3) - -/* URS: Update request source */ -#define TIM_CR1_URS (1 << 2) - -/* UDIS: Update disable */ -#define TIM_CR1_UDIS (1 << 1) - -/* CEN: Counter enable */ -#define TIM_CR1_CEN (1 << 0) - -/* --- TIMx_CR2 values ----------------------------------------------------- */ - -/* OIS4: Output idle state 4 (OC4 output) */ -#define TIM_CR2_OIS4 (1 << 14) - -/* OIS3N: Output idle state 3 (OC3N output) */ -#define TIM_CR2_OIS3N (1 << 13) - -/* OIS3: Output idle state 3 (OC3 output) */ -#define TIM_CR2_OIS3 (1 << 12) - -/* OIS2N: Output idle state 2 (OC2N output) */ -#define TIM_CR2_OIS2N (1 << 11) - -/* OIS2: Output idle state 2 (OC2 output) */ -#define TIM_CR2_OIS2 (1 << 10) - -/* OIS1N: Output idle state 1 (OC1N output) */ -#define TIM_CR2_OIS1N (1 << 9) - -/* OIS1: Output idle state 1 (OC1 output) */ -#define TIM_CR2_OIS1 (1 << 8) -#define TIM_CR2_OIS_MASK (0x7f << 8) - -/* TI1S: TI1 selection */ -#define TIM_CR2_TI1S (1 << 7) - -/* MMS[2:0]: Master mode selection */ -#define TIM_CR2_MMS_RESET (0x0 << 4) -#define TIM_CR2_MMS_ENABLE (0x1 << 4) -#define TIM_CR2_MMS_UPDATE (0x2 << 4) -#define TIM_CR2_MMS_COMPARE_PULSE (0x3 << 4) -#define TIM_CR2_MMS_COMPARE_OC1REF (0x4 << 4) -#define TIM_CR2_MMS_COMPARE_OC2REF (0x5 << 4) -#define TIM_CR2_MMS_COMPARE_OC3REF (0x6 << 4) -#define TIM_CR2_MMS_COMPARE_OC4REF (0x7 << 4) -#define TIM_CR2_MMS_MASK (0x7 << 4) - -/* CCDS: Capture/compare DMA selection */ -#define TIM_CR2_CCDS (1 << 3) - -/* CCUS: Capture/compare control update selection */ -#define TIM_CR2_CCUS (1 << 2) - -/* CCPC: Capture/compare preload control */ -#define TIM_CR2_CCPC (1 << 0) - -/* --- TIMx_SMCR values ---------------------------------------------------- */ - -/* ETP: External trigger polarity */ -#define TIM_SMCR_ETP (1 << 15) - -/* ECE: External clock enable */ -#define TIM_SMCR_ECE (1 << 14) - -/* ETPS[1:0]: External trigger prescaler */ -#define TIM_SMCR_ETPS_OFF (0x0 << 12) -#define TIM_SMCR_ETPS_ETRP_DIV_2 (0x1 << 12) -#define TIM_SMCR_ETPS_ETRP_DIV_4 (0x2 << 12) -#define TIM_SMCR_ETPS_ETRP_DIV_8 (0x3 << 12) -#define TIM_SMCR_ETPS_MASK (0X3 << 12) - -/* ETF[3:0]: External trigger filter */ -#define TIM_SMCR_ETF_OFF (0x0 << 8) -#define TIM_SMCR_ETF_CK_INT_N_2 (0x1 << 8) -#define TIM_SMCR_ETF_CK_INT_N_4 (0x2 << 8) -#define TIM_SMCR_ETF_CK_INT_N_8 (0x3 << 8) -#define TIM_SMCR_ETF_DTS_DIV_2_N_6 (0x4 << 8) -#define TIM_SMCR_ETF_DTS_DIV_2_N_8 (0x5 << 8) -#define TIM_SMCR_ETF_DTS_DIV_4_N_6 (0x6 << 8) -#define TIM_SMCR_ETF_DTS_DIV_4_N_8 (0x7 << 8) -#define TIM_SMCR_ETF_DTS_DIV_8_N_6 (0x8 << 8) -#define TIM_SMCR_ETF_DTS_DIV_8_N_8 (0x9 << 8) -#define TIM_SMCR_ETF_DTS_DIV_16_N_5 (0xA << 8) -#define TIM_SMCR_ETF_DTS_DIV_16_N_6 (0xB << 8) -#define TIM_SMCR_ETF_DTS_DIV_16_N_8 (0xC << 8) -#define TIM_SMCR_ETF_DTS_DIV_32_N_5 (0xD << 8) -#define TIM_SMCR_ETF_DTS_DIV_32_N_6 (0xE << 8) -#define TIM_SMCR_ETF_DTS_DIV_32_N_8 (0xF << 8) -#define TIM_SMCR_ETF_MASK (0xF << 8) - -/* MSM: Master/slave mode */ -#define TIM_SMCR_MSM (1 << 7) - -/* TS[2:0]: Trigger selection */ -#define TIM_SMCR_TS_ITR0 (0x0 << 4) -#define TIM_SMCR_TS_ITR1 (0x1 << 4) -#define TIM_SMCR_TS_ITR2 (0x2 << 4) -#define TIM_SMCR_TS_ITR3 (0x3 << 4) -#define TIM_SMCR_TS_IT1F_ED (0x4 << 4) -#define TIM_SMCR_TS_IT1FP1 (0x5 << 4) -#define TIM_SMCR_TS_IT1FP2 (0x6 << 4) -#define TIM_SMCR_TS_ETRF (0x7 << 4) -#define TIM_SMCR_TS_MASK (0x7 << 4) - -/* SMS[2:0]: Slave mode selection */ -#define TIM_SMCR_SMS_OFF (0x0 << 0) -#define TIM_SMCR_SMS_EM1 (0x1 << 0) -#define TIM_SMCR_SMS_EM2 (0x2 << 0) -#define TIM_SMCR_SMS_EM3 (0x3 << 0) -#define TIM_SMCR_SMS_RM (0x4 << 0) -#define TIM_SMCR_SMS_GM (0x5 << 0) -#define TIM_SMCR_SMS_TM (0x6 << 0) -#define TIM_SMCR_SMS_ECM1 (0x7 << 0) -#define TIM_SMCR_SMS_MASK (0x7 << 0) - -/* --- TIMx_DIER values ---------------------------------------------------- */ - -/* TDE: Trigger DMA request enable */ -#define TIM_DIER_TDE (1 << 14) - -/* COMDE: COM DMA request enable */ -#define TIM_DIER_COMDE (1 << 13) - -/* CC4DE: Capture/Compare 4 DMA request enable */ -#define TIM_DIER_CC4DE (1 << 12) - -/* CC3DE: Capture/Compare 3 DMA request enable */ -#define TIM_DIER_CC3DE (1 << 11) - -/* CC2DE: Capture/Compare 2 DMA request enable */ -#define TIM_DIER_CC2DE (1 << 10) - -/* CC1DE: Capture/Compare 1 DMA request enable */ -#define TIM_DIER_CC1DE (1 << 9) - -/* UDE: Update DMA request enable */ -#define TIM_DIER_UDE (1 << 8) - -/* BIE: Break interrupt enable */ -#define TIM_DIER_BIE (1 << 7) - -/* TIE: Trigger interrupt enable */ -#define TIM_DIER_TIE (1 << 6) - -/* COMIE: COM interrupt enable */ -#define TIM_DIER_COMIE (1 << 5) - -/* CC4IE: Capture/compare 4 interrupt enable */ -#define TIM_DIER_CC4IE (1 << 4) - -/* CC3IE: Capture/compare 3 interrupt enable */ -#define TIM_DIER_CC3IE (1 << 3) - -/* CC2IE: Capture/compare 2 interrupt enable */ -#define TIM_DIER_CC2IE (1 << 2) - -/* CC1IE: Capture/compare 1 interrupt enable */ -#define TIM_DIER_CC1IE (1 << 1) - -/* UIE: Update interrupt enable */ -#define TIM_DIER_UIE (1 << 0) - -/* --- TIMx_SR values ------------------------------------------------------ */ - -/* CC4OF: Capture/compare 4 overcapture flag */ -#define TIM_SR_CC4OF (1 << 12) - -/* CC3OF: Capture/compare 3 overcapture flag */ -#define TIM_SR_CC3OF (1 << 11) - -/* CC2OF: Capture/compare 2 overcapture flag */ -#define TIM_SR_CC2OF (1 << 10) - -/* CC1OF: Capture/compare 1 overcapture flag */ -#define TIM_SR_CC1OF (1 << 9) - -/* BIF: Break interrupt flag */ -#define TIM_SR_BIF (1 << 7) - -/* TIF: Trigger interrupt flag */ -#define TIM_SR_TIF (1 << 6) - -/* COMIF: COM interrupt flag */ -#define TIM_SR_COMIF (1 << 5) - -/* CC4IF: Capture/compare 4 interrupt flag */ -#define TIM_SR_CC4IF (1 << 4) - -/* CC3IF: Capture/compare 3 interrupt flag */ -#define TIM_SR_CC3IF (1 << 3) - -/* CC2IF: Capture/compare 2 interrupt flag */ -#define TIM_SR_CC2IF (1 << 2) - -/* CC1IF: Capture/compare 1 interrupt flag */ -#define TIM_SR_CC1IF (1 << 1) - -/* UIF: Update interrupt flag */ -#define TIM_SR_UIF (1 << 0) - -/* --- TIMx_EGR values ----------------------------------------------------- */ - -/* BG: Break generation */ -#define TIM_EGR_BG (1 << 7) - -/* TG: Trigger generation */ -#define TIM_EGR_TG (1 << 6) - -/* COMG: Capture/compare control update generation */ -#define TIM_EGR_COMG (1 << 5) - -/* CC4G: Capture/compare 4 generation */ -#define TIM_EGR_CC4G (1 << 4) - -/* CC3G: Capture/compare 3 generation */ -#define TIM_EGR_CC3G (1 << 3) - -/* CC2G: Capture/compare 2 generation */ -#define TIM_EGR_CC2G (1 << 2) - -/* CC1G: Capture/compare 1 generation */ -#define TIM_EGR_CC1G (1 << 1) - -/* UG: Update generation */ -#define TIM_EGR_UG (1 << 0) - -/* --- TIMx_CCMR1 values --------------------------------------------------- */ - -/* --- Output compare mode --- */ - -/* OC2CE: Output compare 2 clear enable */ -#define TIM_CCMR1_OC2CE (1 << 15) - -/* OC2M[2:0]: Output compare 2 mode */ -#define TIM_CCMR1_OC2M_FROZEN (0x0 << 12) -#define TIM_CCMR1_OC2M_ACTIVE (0x1 << 12) -#define TIM_CCMR1_OC2M_INACTIVE (0x2 << 12) -#define TIM_CCMR1_OC2M_TOGGLE (0x3 << 12) -#define TIM_CCMR1_OC2M_FORCE_LOW (0x4 << 12) -#define TIM_CCMR1_OC2M_FORCE_HIGH (0x5 << 12) -#define TIM_CCMR1_OC2M_PWM1 (0x6 << 12) -#define TIM_CCMR1_OC2M_PWM2 (0x7 << 12) -#define TIM_CCMR1_OC2M_MASK (0x7 << 12) - -/* OC2PE: Output compare 2 preload enable */ -#define TIM_CCMR1_OC2PE (1 << 11) - -/* OC2FE: Output compare 2 fast enable */ -#define TIM_CCMR1_OC2FE (1 << 10) - -/* CC2S[1:0]: Capture/compare 2 selection */ -/* Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in - * TIMx_CCER). */ -#define TIM_CCMR1_CC2S_OUT (0x0 << 8) -#define TIM_CCMR1_CC2S_IN_TI2 (0x1 << 8) -#define TIM_CCMR1_CC2S_IN_TI1 (0x2 << 8) -#define TIM_CCMR1_CC2S_IN_TRC (0x3 << 8) -#define TIM_CCMR1_CC2S_MASK (0x3 << 8) - -/* OC1CE: Output compare 1 clear enable */ -#define TIM_CCMR1_OC1CE (1 << 7) - -/* OC1M[2:0]: Output compare 1 mode */ -#define TIM_CCMR1_OC1M_FROZEN (0x0 << 4) -#define TIM_CCMR1_OC1M_ACTIVE (0x1 << 4) -#define TIM_CCMR1_OC1M_INACTIVE (0x2 << 4) -#define TIM_CCMR1_OC1M_TOGGLE (0x3 << 4) -#define TIM_CCMR1_OC1M_FORCE_LOW (0x4 << 4) -#define TIM_CCMR1_OC1M_FORCE_HIGH (0x5 << 4) -#define TIM_CCMR1_OC1M_PWM1 (0x6 << 4) -#define TIM_CCMR1_OC1M_PWM2 (0x7 << 4) -#define TIM_CCMR1_OC1M_MASK (0x7 << 4) - -/* OC1PE: Output compare 1 preload enable */ -#define TIM_CCMR1_OC1PE (1 << 3) - -/* OC1FE: Output compare 1 fast enable */ -#define TIM_CCMR1_OC1FE (1 << 2) - -/* CC1S[1:0]: Capture/compare 1 selection */ -/* Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in - * TIMx_CCER). */ -#define TIM_CCMR1_CC1S_OUT (0x0 << 0) -#define TIM_CCMR1_CC1S_IN_TI2 (0x1 << 0) -#define TIM_CCMR1_CC1S_IN_TI1 (0x2 << 0) -#define TIM_CCMR1_CC1S_IN_TRC (0x3 << 0) -#define TIM_CCMR1_CC1S_MASK (0x3 << 0) - -/* --- Input capture mode --- */ - -/* IC2F[3:0]: Input capture 2 filter */ -#define TIM_CCMR1_IC2F_OFF (0x0 << 12) -#define TIM_CCMR1_IC2F_CK_INT_N_2 (0x1 << 12) -#define TIM_CCMR1_IC2F_CK_INT_N_4 (0x2 << 12) -#define TIM_CCMR1_IC2F_CK_INT_N_8 (0x3 << 12) -#define TIM_CCMR1_IC2F_DTF_DIV_2_N_6 (0x4 << 12) -#define TIM_CCMR1_IC2F_DTF_DIV_2_N_8 (0x5 << 12) -#define TIM_CCMR1_IC2F_DTF_DIV_4_N_6 (0x6 << 12) -#define TIM_CCMR1_IC2F_DTF_DIV_4_N_8 (0x7 << 12) -#define TIM_CCMR1_IC2F_DTF_DIV_8_N_6 (0x8 << 12) -#define TIM_CCMR1_IC2F_DTF_DIV_8_N_8 (0x9 << 12) -#define TIM_CCMR1_IC2F_DTF_DIV_16_N_5 (0xA << 12) -#define TIM_CCMR1_IC2F_DTF_DIV_16_N_6 (0xB << 12) -#define TIM_CCMR1_IC2F_DTF_DIV_16_N_8 (0xC << 12) -#define TIM_CCMR1_IC2F_DTF_DIV_32_N_5 (0xD << 12) -#define TIM_CCMR1_IC2F_DTF_DIV_32_N_6 (0xE << 12) -#define TIM_CCMR1_IC2F_DTF_DIV_32_N_8 (0xF << 12) -#define TIM_CCMR1_IC2F_MASK (0xF << 12) - -/* IC2PSC[1:0]: Input capture 2 prescaler */ -#define TIM_CCMR1_IC2PSC_OFF (0x0 << 10) -#define TIM_CCMR1_IC2PSC_2 (0x1 << 10) -#define TIM_CCMR1_IC2PSC_4 (0x2 << 10) -#define TIM_CCMR1_IC2PSC_8 (0x3 << 10) -#define TIM_CCMR1_IC2PSC_MASK (0x3 << 10) - -/* IC1F[3:0]: Input capture 1 filter */ -#define TIM_CCMR1_IC1F_OFF (0x0 << 4) -#define TIM_CCMR1_IC1F_CK_INT_N_2 (0x1 << 4) -#define TIM_CCMR1_IC1F_CK_INT_N_4 (0x2 << 4) -#define TIM_CCMR1_IC1F_CK_INT_N_8 (0x3 << 4) -#define TIM_CCMR1_IC1F_DTF_DIV_2_N_6 (0x4 << 4) -#define TIM_CCMR1_IC1F_DTF_DIV_2_N_8 (0x5 << 4) -#define TIM_CCMR1_IC1F_DTF_DIV_4_N_6 (0x6 << 4) -#define TIM_CCMR1_IC1F_DTF_DIV_4_N_8 (0x7 << 4) -#define TIM_CCMR1_IC1F_DTF_DIV_8_N_6 (0x8 << 4) -#define TIM_CCMR1_IC1F_DTF_DIV_8_N_8 (0x9 << 4) -#define TIM_CCMR1_IC1F_DTF_DIV_16_N_5 (0xA << 4) -#define TIM_CCMR1_IC1F_DTF_DIV_16_N_6 (0xB << 4) -#define TIM_CCMR1_IC1F_DTF_DIV_16_N_8 (0xC << 4) -#define TIM_CCMR1_IC1F_DTF_DIV_32_N_5 (0xD << 4) -#define TIM_CCMR1_IC1F_DTF_DIV_32_N_6 (0xE << 4) -#define TIM_CCMR1_IC1F_DTF_DIV_32_N_8 (0xF << 4) -#define TIM_CCMR1_IC1F_MASK (0xF << 4) - -/* IC1PSC[1:0]: Input capture 1 prescaler */ -#define TIM_CCMR1_IC1PSC_OFF (0x0 << 2) -#define TIM_CCMR1_IC1PSC_2 (0x1 << 2) -#define TIM_CCMR1_IC1PSC_4 (0x2 << 2) -#define TIM_CCMR1_IC1PSC_8 (0x3 << 2) -#define TIM_CCMR1_IC1PSC_MASK (0x3 << 2) - -/* --- TIMx_CCMR2 values --------------------------------------------------- */ - -/* --- Output compare mode --- */ - -/* OC4CE: Output compare 4 clear enable */ -#define TIM_CCMR2_OC4CE (1 << 15) - -/* OC4M[2:0]: Output compare 4 mode */ -#define TIM_CCMR2_OC4M_FROZEN (0x0 << 12) -#define TIM_CCMR2_OC4M_ACTIVE (0x1 << 12) -#define TIM_CCMR2_OC4M_INACTIVE (0x2 << 12) -#define TIM_CCMR2_OC4M_TOGGLE (0x3 << 12) -#define TIM_CCMR2_OC4M_FORCE_LOW (0x4 << 12) -#define TIM_CCMR2_OC4M_FORCE_HIGH (0x5 << 12) -#define TIM_CCMR2_OC4M_PWM1 (0x6 << 12) -#define TIM_CCMR2_OC4M_PWM2 (0x7 << 12) -#define TIM_CCMR2_OC4M_MASK (0x7 << 12) - -/* OC4PE: Output compare 4 preload enable */ -#define TIM_CCMR2_OC4PE (1 << 11) - -/* OC4FE: Output compare 4 fast enable */ -#define TIM_CCMR2_OC4FE (1 << 10) - -/* CC4S[1:0]: Capture/compare 4 selection */ -/* Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in - * TIMx_CCER). */ -#define TIM_CCMR2_CC4S_OUT (0x0 << 8) -#define TIM_CCMR2_CC4S_IN_TI2 (0x1 << 8) -#define TIM_CCMR2_CC4S_IN_TI1 (0x2 << 8) -#define TIM_CCMR2_CC4S_IN_TRC (0x3 << 8) -#define TIM_CCMR2_CC4S_MASK (0x3 << 8) - -/* OC3CE: Output compare 3 clear enable */ -#define TIM_CCMR2_OC3CE (1 << 7) - -/* OC3M[2:0]: Output compare 3 mode */ -#define TIM_CCMR2_OC3M_FROZEN (0x0 << 4) -#define TIM_CCMR2_OC3M_ACTIVE (0x1 << 4) -#define TIM_CCMR2_OC3M_INACTIVE (0x2 << 4) -#define TIM_CCMR2_OC3M_TOGGLE (0x3 << 4) -#define TIM_CCMR2_OC3M_FORCE_LOW (0x4 << 4) -#define TIM_CCMR2_OC3M_FORCE_HIGH (0x5 << 4) -#define TIM_CCMR2_OC3M_PWM1 (0x6 << 4) -#define TIM_CCMR2_OC3M_PWM2 (0x7 << 4) -#define TIM_CCMR2_OC3M_MASK (0x7 << 4) - -/* OC3PE: Output compare 3 preload enable */ -#define TIM_CCMR2_OC3PE (1 << 3) - -/* OC3FE: Output compare 3 fast enable */ -#define TIM_CCMR2_OC3FE (1 << 2) - -/* CC3S[1:0]: Capture/compare 3 selection */ -/* Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in - * TIMx_CCER). */ -#define TIM_CCMR2_CC3S_OUT (0x0 << 0) -#define TIM_CCMR2_CC3S_IN_TI2 (0x1 << 0) -#define TIM_CCMR2_CC3S_IN_TI1 (0x2 << 0) -#define TIM_CCMR2_CC3S_IN_TRC (0x3 << 0) -#define TIM_CCMR2_CC3S_MASK (0x3 << 0) - -/* --- Input capture mode --- */ - -/* IC4F[3:0]: Input capture 4 filter */ -#define TIM_CCMR2_IC4F_OFF (0x0 << 12) -#define TIM_CCMR2_IC4F_CK_INT_N_2 (0x1 << 12) -#define TIM_CCMR2_IC4F_CK_INT_N_4 (0x2 << 12) -#define TIM_CCMR2_IC4F_CK_INT_N_8 (0x3 << 12) -#define TIM_CCMR2_IC4F_DTF_DIV_2_N_6 (0x4 << 12) -#define TIM_CCMR2_IC4F_DTF_DIV_2_N_8 (0x5 << 12) -#define TIM_CCMR2_IC4F_DTF_DIV_4_N_6 (0x6 << 12) -#define TIM_CCMR2_IC4F_DTF_DIV_4_N_8 (0x7 << 12) -#define TIM_CCMR2_IC4F_DTF_DIV_8_N_6 (0x8 << 12) -#define TIM_CCMR2_IC4F_DTF_DIV_8_N_8 (0x9 << 12) -#define TIM_CCMR2_IC4F_DTF_DIV_16_N_5 (0xA << 12) -#define TIM_CCMR2_IC4F_DTF_DIV_16_N_6 (0xB << 12) -#define TIM_CCMR2_IC4F_DTF_DIV_16_N_8 (0xC << 12) -#define TIM_CCMR2_IC4F_DTF_DIV_32_N_5 (0xD << 12) -#define TIM_CCMR2_IC4F_DTF_DIV_32_N_6 (0xE << 12) -#define TIM_CCMR2_IC4F_DTF_DIV_32_N_8 (0xF << 12) -#define TIM_CCMR2_IC4F_MASK (0xF << 12) - -/* IC4PSC[1:0]: Input capture 4 prescaler */ -#define TIM_CCMR2_IC4PSC_OFF (0x0 << 10) -#define TIM_CCMR2_IC4PSC_2 (0x1 << 10) -#define TIM_CCMR2_IC4PSC_4 (0x2 << 10) -#define TIM_CCMR2_IC4PSC_8 (0x3 << 10) -#define TIM_CCMR2_IC4PSC_MASK (0x3 << 10) - -/* IC3F[3:0]: Input capture 3 filter */ -#define TIM_CCMR2_IC3F_OFF (0x0 << 4) -#define TIM_CCMR2_IC3F_CK_INT_N_2 (0x1 << 4) -#define TIM_CCMR2_IC3F_CK_INT_N_4 (0x2 << 4) -#define TIM_CCMR2_IC3F_CK_INT_N_8 (0x3 << 4) -#define TIM_CCMR2_IC3F_DTF_DIV_2_N_6 (0x4 << 4) -#define TIM_CCMR2_IC3F_DTF_DIV_2_N_8 (0x5 << 4) -#define TIM_CCMR2_IC3F_DTF_DIV_4_N_6 (0x6 << 4) -#define TIM_CCMR2_IC3F_DTF_DIV_4_N_8 (0x7 << 4) -#define TIM_CCMR2_IC3F_DTF_DIV_8_N_6 (0x8 << 4) -#define TIM_CCMR2_IC3F_DTF_DIV_8_N_8 (0x9 << 4) -#define TIM_CCMR2_IC3F_DTF_DIV_16_N_5 (0xA << 4) -#define TIM_CCMR2_IC3F_DTF_DIV_16_N_6 (0xB << 4) -#define TIM_CCMR2_IC3F_DTF_DIV_16_N_8 (0xC << 4) -#define TIM_CCMR2_IC3F_DTF_DIV_32_N_5 (0xD << 4) -#define TIM_CCMR2_IC3F_DTF_DIV_32_N_6 (0xE << 4) -#define TIM_CCMR2_IC3F_DTF_DIV_32_N_8 (0xF << 4) -#define TIM_CCMR2_IC3F_MASK (0xF << 4) - -/* IC3PSC[1:0]: Input capture 3 prescaler */ -#define TIM_CCMR2_IC3PSC_OFF (0x0 << 2) -#define TIM_CCMR2_IC3PSC_2 (0x1 << 2) -#define TIM_CCMR2_IC3PSC_4 (0x2 << 2) -#define TIM_CCMR2_IC3PSC_8 (0x3 << 2) -#define TIM_CCMR2_IC3PSC_MASK (0x3 << 2) - -/* --- TIMx_CCER values ---------------------------------------------------- */ - -/* CC4P: Capture/compare 4 output polarity */ -#define TIM_CCER_CC4P (1 << 13) - -/* CC4E: Capture/compare 4 output enable */ -#define TIM_CCER_CC4E (1 << 12) - -/* CC3NP: Capture/compare 3 complementary output polarity */ -#define TIM_CCER_CC3NP (1 << 11) - -/* CC3NE: Capture/compare 3 complementary output enable */ -#define TIM_CCER_CC3NE (1 << 10) - -/* CC3P: Capture/compare 3 output polarity */ -#define TIM_CCER_CC3P (1 << 9) - -/* CC3E: Capture/compare 3 output enable */ -#define TIM_CCER_CC3E (1 << 8) - -/* CC2NP: Capture/compare 2 complementary output polarity */ -#define TIM_CCER_CC2NP (1 << 7) - -/* CC2NE: Capture/compare 2 complementary output enable */ -#define TIM_CCER_CC2NE (1 << 6) - -/* CC2P: Capture/compare 2 output polarity */ -#define TIM_CCER_CC2P (1 << 5) - -/* CC2E: Capture/compare 2 output enable */ -#define TIM_CCER_CC2E (1 << 4) - -/* CC1NP: Capture/compare 1 complementary output polarity */ -#define TIM_CCER_CC1NP (1 << 3) - -/* CC1NE: Capture/compare 1 complementary output enable */ -#define TIM_CCER_CC1NE (1 << 2) - -/* CC1P: Capture/compare 1 output polarity */ -#define TIM_CCER_CC1P (1 << 1) - -/* CC1E: Capture/compare 1 output enable */ -#define TIM_CCER_CC1E (1 << 0) - -/* --- TIMx_CNT values ----------------------------------------------------- */ - -/* CNT[15:0]: Counter value */ - -/* --- TIMx_PSC values ----------------------------------------------------- */ - -/* PSC[15:0]: Prescaler value */ - -/* --- TIMx_ARR values ----------------------------------------------------- */ - -/* ARR[15:0]: Prescaler value */ - -/* --- TIMx_RCR values ----------------------------------------------------- */ - -/* REP[15:0]: Repetition counter value */ - -/* --- TIMx_CCR1 values ---------------------------------------------------- */ - -/* CCR1[15:0]: Capture/compare 1 value */ - -/* --- TIMx_CCR2 values ---------------------------------------------------- */ - -/* CCR2[15:0]: Capture/compare 2 value */ - -/* --- TIMx_CCR3 values ---------------------------------------------------- */ - -/* CCR3[15:0]: Capture/compare 3 value */ - -/* --- TIMx_CCR4 values ---------------------------------------------------- */ - -/* CCR4[15:0]: Capture/compare 4 value */ - -/* --- TIMx_BDTR values ---------------------------------------------------- */ - -/* MOE: Main output enable */ -#define TIM_BDTR_MOE (1 << 15) - -/* AOE: Automatic output enable */ -#define TIM_BDTR_AOE (1 << 14) - -/* BKP: Break polarity */ -#define TIM_BDTR_BKP (1 << 13) - -/* BKE: Break enable */ -#define TIM_BDTR_BKE (1 << 12) - -/* OSSR: Off-state selection of run mode */ -#define TIM_BDTR_OSSR (1 << 11) - -/* OSSI: Off-state selection of idle mode */ -#define TIM_BDTR_OSSI (1 << 10) - -/* LOCK[1:0]: Lock configuration */ -#define TIM_BDTR_LOCK_OFF (0x0 << 8) -#define TIM_BDTR_LOCK_LEVEL_1 (0x1 << 8) -#define TIM_BDTR_LOCK_LEVEL_2 (0x2 << 8) -#define TIM_BDTR_LOCK_LEVEL_3 (0x3 << 8) -#define TIM_BDTR_LOCK_MASK (0x3 << 8) - -/* DTG[7:0]: Dead-time generator set-up */ -#define TIM_BDTR_DTG_MASK 0x00FF - -/* --- TIMx_DCR values ----------------------------------------------------- */ - -/* DBL[4:0]: DMA burst length */ -#define TIM_BDTR_DBL_MASK (0x1F << 8) - -/* DBA[4:0]: DMA base address */ -#define TIM_BDTR_DBA_MASK (0x1F << 0) - -/* --- TIMx_DMAR values ---------------------------------------------------- */ - -/* DMAB[15:0]: DMA register for burst accesses */ - -/* --- TIMx convenience defines -------------------------------------------- */ - -/* Output Compare channel designators */ -enum tim_oc_id { - TIM_OC1=0, - TIM_OC1N, - TIM_OC2, - TIM_OC2N, - TIM_OC3, - TIM_OC3N, - TIM_OC4, -}; - -/* Output Compare mode designators */ -enum tim_oc_mode { - TIM_OCM_FROZEN, - TIM_OCM_ACTIVE, - TIM_OCM_INACTIVE, - TIM_OCM_TOGGLE, - TIM_OCM_FORCE_LOW, - TIM_OCM_FORCE_HIGH, - TIM_OCM_PWM1, - TIM_OCM_PWM2, -}; - -/* --- TIM functions ------------------------------------------------------- */ -void timer_reset(u32 timer_peripheral); -void timer_enable_irq(u32 timer_peripheral, u32 irq); -void timer_disable_irq(u32 timer_peripheral, u32 irq); -bool timer_get_flag(u32 timer_peripheral, u32 flag); -void timer_clear_flag(u32 timer_peripheral, u32 flag); -void timer_set_mode(u32 timer_peripheral, u8 clock_div, - u8 alignment, u8 direction); -void timer_set_clock_division(u32 timer_peripheral, u32 clock_div); -void timer_enable_preload(u32 timer_peripheral); -void timer_disable_preload(u32 timer_peripheral); -void timer_set_alignment(u32 timer_peripheral, u32 alignment); -void timer_direction_up(u32 timer_peripheral); -void timer_direction_down(u32 timer_peripheral); -void timer_one_shot_mode(u32 timer_peripheral); -void timer_continuous_mode(u32 timer_peripheral); -void timer_update_on_any(u32 timer_peripheral); -void timer_update_on_overflow(u32 timer_peripheral); -void timer_enable_update_event(u32 timer_peripheral); -void timer_disable_update_event(u32 timer_peripheral); -void timer_enable_counter(u32 timer_peripheral); -void timer_disable_counter(u32 timer_peripheral); -void timer_set_output_idle_state(u32 timer_peripheral, u32 outputs); -void timer_reset_output_idle_state(u32 timer_peripheral, u32 outputs); -void timer_set_ti1_ch123_xor(u32 timer_peripheral); -void timer_set_ti1_ch1(u32 timer_peripheral); -void timer_set_master_mode(u32 timer_peripheral, u32 mode); -void timer_set_dma_on_compare_event(u32 timer_peripheral); -void timer_set_dma_on_update_event(u32 timer_peripheral); -void timer_enable_compare_control_update_on_trigger(u32 timer_peripheral); -void timer_disable_compare_control_update_on_trigger(u32 timer_peripheral); -void timer_enable_preload_complementry_enable_bits(u32 timer_peripheral); -void timer_disable_preload_complementry_enable_bits(u32 timer_peripheral); -void timer_set_prescaler(u32 timer_peripheral, u32 value); -void timer_set_repetition_counter(u32 timer_peripheral, u32 value); -void timer_set_period(u32 timer_peripheral, u32 period); -void timer_enable_oc_clear(u32 timer_peripheral, enum tim_oc_id oc_id); -void timer_disable_oc_clear(u32 timer_peripheral, enum tim_oc_id oc_id); -void timer_set_oc_fast_mode(u32 timer_peripheral, enum tim_oc_id oc_id); -void timer_set_oc_slow_mode(u32 timer_peripheral, enum tim_oc_id oc_id); -void timer_set_oc_mode(u32 timer_peripheral, enum tim_oc_id oc_id, enum tim_oc_mode oc_mode); -void timer_enable_oc_preload(u32 timer_peripheral, enum tim_oc_id oc_id); -void timer_disable_oc_preload(u32 timer_peripheral, enum tim_oc_id oc_id); -void timer_set_oc_polarity_high(u32 timer_peripheral, enum tim_oc_id oc_id); -void timer_set_oc_polarity_low(u32 timer_peripheral, enum tim_oc_id oc_id); -void timer_enable_oc_output(u32 timer_peripheral, enum tim_oc_id oc_id); -void timer_disable_oc_output(u32 timer_peripheral, enum tim_oc_id oc_id); -void timer_set_oc_idle_state_set(u32 timer_peripheral, enum tim_oc_id oc_id); -void timer_set_oc_idle_state_unset(u32 timer_peripheral, enum tim_oc_id oc_id); -void timer_set_oc_value(u32 timer_peripheral, enum tim_oc_id oc_id, u32 value); -void timer_enable_break_main_output(u32 timer_peripheral); -void timer_disable_break_main_output(u32 timer_peripheral); -void timer_enable_break_automatic_output(u32 timer_peripheral); -void timer_disable_break_automatic_output(u32 timer_peripheral); -void timer_set_break_polarity_high(u32 timer_peripheral); -void timer_set_break_polarity_low(u32 timer_peripheral); -void timer_enable_break(u32 timer_peripheral); -void timer_disable_break(u32 timer_peripheral); -void timer_set_enabled_off_state_in_run_mode(u32 timer_peripheral); -void timer_set_disabled_off_state_in_run_mode(u32 timer_peripheral); -void timer_set_enabled_off_state_in_idle_mode(u32 timer_peripheral); -void timer_set_disabled_off_state_in_idle_mode(u32 timer_peripheral); -void timer_set_break_lock(u32 timer_peripheral, u32 lock); -void timer_set_deadtime(u32 timer_peripheral, u32 deadtime); -void timer_generate_event(u32 timer_peripheral, u32 event); -u32 timer_get_counter(u32 timer_peripheral); - -#endif diff --git a/include/libopencm3/stm32f2/timer.h b/include/libopencm3/stm32f2/timer.h new file mode 100644 index 0000000..f7c82ae --- /dev/null +++ b/include/libopencm3/stm32f2/timer.h @@ -0,0 +1,54 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Fergus Noble + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_TIMER_F2_H +#define LIBOPENCM3_TIMER_F2_H + +#include + + +/* + * TIM2 and TIM5 are now 32bit and the following registers are now 32-bit wide: + * CNT, ARR, CCR1, CCR2, CCR3, CCR4 + */ + +/* Timer 2/5 option register (TIMx_OR) */ +#define TIM_OR(tim_base) MMIO32(tim_base + 0x50) +#define TIM2_OR TIM_OR(TIM2) +#define TIM5_OR TIM_OR(TIM5) + +/* --- TIM2_OR values ---------------------------------------------------- */ + +/* MOE: Main output enable */ +#define TIM2_OR_ITR1_RMP_TIM8_TRGOUT (0x0 << 10) +#define TIM2_OR_ITR1_RMP_PTP (0x1 << 10) +#define TIM2_OR_ITR1_RMP_OTG_FS_SOF (0x2 << 10) +#define TIM2_OR_ITR1_RMP_OTG_HS_SOF (0x3 << 10) +#define TIM2_OR_ITR1_RMP_MASK (0x3 << 10) + +/* --- TIM5_OR values ---------------------------------------------------- */ + +/* MOE: Main output enable */ +#define TIM5_OR_TI4_RMP_GPIO (0x0 << 6) +#define TIM5_OR_TI4_RMP_LSI (0x1 << 6) +#define TIM5_OR_TI4_RMP_LSE (0x2 << 6) +#define TIM5_OR_TI4_RMP_RTC (0x3 << 6) +#define TIM5_OR_TI4_RMP_MASK (0x3 << 6) + +#endif -- cgit v1.2.3 From 4eff339e8caae6a16b3650343de483201d4ca490 Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Wed, 14 Sep 2011 13:47:33 -0700 Subject: Restructuring stm32 include directories. --- include/libopencm3/stm32/can.h | 642 +++++++++++++++++++ include/libopencm3/stm32/crc.h | 52 ++ include/libopencm3/stm32/dbgmcu.h | 60 ++ include/libopencm3/stm32/exti.h | 70 +++ include/libopencm3/stm32/f1/adc.h | 418 +++++++++++++ include/libopencm3/stm32/f1/bkp.h | 208 +++++++ include/libopencm3/stm32/f1/dma.h | 723 ++++++++++++++++++++++ include/libopencm3/stm32/f1/ethernet.h | 203 ++++++ include/libopencm3/stm32/f1/flash.h | 113 ++++ include/libopencm3/stm32/f1/gpio.h | 555 +++++++++++++++++ include/libopencm3/stm32/f1/memorymap.h | 113 ++++ include/libopencm3/stm32/f1/nvic.h | 162 +++++ include/libopencm3/stm32/f1/otg_fs.h | 324 ++++++++++ include/libopencm3/stm32/f1/rcc.h | 417 +++++++++++++ include/libopencm3/stm32/f1/rtc.h | 146 +++++ include/libopencm3/stm32/f1/scb.h | 300 +++++++++ include/libopencm3/stm32/f1/systick.h | 82 +++ include/libopencm3/stm32/f1/tools.h | 64 ++ include/libopencm3/stm32/f1/usb.h | 258 ++++++++ include/libopencm3/stm32/f1/usb_desc.h | 101 +++ include/libopencm3/stm32/f2/memorymap.h | 131 ++++ include/libopencm3/stm32/f2/pwr.h | 40 ++ include/libopencm3/stm32/f2/spi.h | 42 ++ include/libopencm3/stm32/f2/timer.h | 54 ++ include/libopencm3/stm32/f2/usart.h | 35 ++ include/libopencm3/stm32/fsmc.h | 284 +++++++++ include/libopencm3/stm32/i2c.h | 333 ++++++++++ include/libopencm3/stm32/iwdg.h | 75 +++ include/libopencm3/stm32/memorymap.h | 33 + include/libopencm3/stm32/pwr.h | 81 +++ include/libopencm3/stm32/spi.h | 331 ++++++++++ include/libopencm3/stm32/timer.h | 921 ++++++++++++++++++++++++++++ include/libopencm3/stm32/usart.h | 312 ++++++++++ include/libopencm3/stm32/wwdg.h | 74 +++ include/libopencm3/stm32_common/can.h | 642 ------------------- include/libopencm3/stm32_common/crc.h | 52 -- include/libopencm3/stm32_common/dbgmcu.h | 60 -- include/libopencm3/stm32_common/exti.h | 70 --- include/libopencm3/stm32_common/fsmc.h | 284 --------- include/libopencm3/stm32_common/i2c.h | 333 ---------- include/libopencm3/stm32_common/iwdg.h | 75 --- include/libopencm3/stm32_common/memorymap.h | 35 -- include/libopencm3/stm32_common/pwr.h | 81 --- include/libopencm3/stm32_common/spi.h | 331 ---------- include/libopencm3/stm32_common/timer.h | 921 ---------------------------- include/libopencm3/stm32_common/usart.h | 312 ---------- include/libopencm3/stm32_common/wwdg.h | 74 --- include/libopencm3/stm32f1/adc.h | 418 ------------- include/libopencm3/stm32f1/bkp.h | 208 ------- include/libopencm3/stm32f1/dma.h | 723 ---------------------- include/libopencm3/stm32f1/ethernet.h | 203 ------ include/libopencm3/stm32f1/flash.h | 113 ---- include/libopencm3/stm32f1/gpio.h | 555 ----------------- include/libopencm3/stm32f1/memorymap.h | 113 ---- include/libopencm3/stm32f1/nvic.h | 162 ----- include/libopencm3/stm32f1/otg_fs.h | 324 ---------- include/libopencm3/stm32f1/rcc.h | 417 ------------- include/libopencm3/stm32f1/rtc.h | 146 ----- include/libopencm3/stm32f1/scb.h | 300 --------- include/libopencm3/stm32f1/systick.h | 82 --- include/libopencm3/stm32f1/tools.h | 64 -- include/libopencm3/stm32f1/usb.h | 258 -------- include/libopencm3/stm32f1/usb_desc.h | 101 --- include/libopencm3/stm32f2/memorymap.h | 131 ---- include/libopencm3/stm32f2/pwr.h | 40 -- include/libopencm3/stm32f2/spi.h | 42 -- include/libopencm3/stm32f2/timer.h | 54 -- include/libopencm3/stm32f2/usart.h | 35 -- 68 files changed, 7757 insertions(+), 7759 deletions(-) create mode 100644 include/libopencm3/stm32/can.h create mode 100644 include/libopencm3/stm32/crc.h create mode 100644 include/libopencm3/stm32/dbgmcu.h create mode 100644 include/libopencm3/stm32/exti.h create mode 100644 include/libopencm3/stm32/f1/adc.h create mode 100644 include/libopencm3/stm32/f1/bkp.h create mode 100644 include/libopencm3/stm32/f1/dma.h create mode 100644 include/libopencm3/stm32/f1/ethernet.h create mode 100644 include/libopencm3/stm32/f1/flash.h create mode 100644 include/libopencm3/stm32/f1/gpio.h create mode 100644 include/libopencm3/stm32/f1/memorymap.h create mode 100644 include/libopencm3/stm32/f1/nvic.h create mode 100644 include/libopencm3/stm32/f1/otg_fs.h create mode 100644 include/libopencm3/stm32/f1/rcc.h create mode 100644 include/libopencm3/stm32/f1/rtc.h create mode 100644 include/libopencm3/stm32/f1/scb.h create mode 100644 include/libopencm3/stm32/f1/systick.h create mode 100644 include/libopencm3/stm32/f1/tools.h create mode 100644 include/libopencm3/stm32/f1/usb.h create mode 100644 include/libopencm3/stm32/f1/usb_desc.h create mode 100644 include/libopencm3/stm32/f2/memorymap.h create mode 100644 include/libopencm3/stm32/f2/pwr.h create mode 100644 include/libopencm3/stm32/f2/spi.h create mode 100644 include/libopencm3/stm32/f2/timer.h create mode 100644 include/libopencm3/stm32/f2/usart.h create mode 100644 include/libopencm3/stm32/fsmc.h create mode 100644 include/libopencm3/stm32/i2c.h create mode 100644 include/libopencm3/stm32/iwdg.h create mode 100644 include/libopencm3/stm32/memorymap.h create mode 100644 include/libopencm3/stm32/pwr.h create mode 100644 include/libopencm3/stm32/spi.h create mode 100644 include/libopencm3/stm32/timer.h create mode 100644 include/libopencm3/stm32/usart.h create mode 100644 include/libopencm3/stm32/wwdg.h delete mode 100644 include/libopencm3/stm32_common/can.h delete mode 100644 include/libopencm3/stm32_common/crc.h delete mode 100644 include/libopencm3/stm32_common/dbgmcu.h delete mode 100644 include/libopencm3/stm32_common/exti.h delete mode 100644 include/libopencm3/stm32_common/fsmc.h delete mode 100644 include/libopencm3/stm32_common/i2c.h delete mode 100644 include/libopencm3/stm32_common/iwdg.h delete mode 100644 include/libopencm3/stm32_common/memorymap.h delete mode 100644 include/libopencm3/stm32_common/pwr.h delete mode 100644 include/libopencm3/stm32_common/spi.h delete mode 100644 include/libopencm3/stm32_common/timer.h delete mode 100644 include/libopencm3/stm32_common/usart.h delete mode 100644 include/libopencm3/stm32_common/wwdg.h delete mode 100644 include/libopencm3/stm32f1/adc.h delete mode 100644 include/libopencm3/stm32f1/bkp.h delete mode 100644 include/libopencm3/stm32f1/dma.h delete mode 100644 include/libopencm3/stm32f1/ethernet.h delete mode 100644 include/libopencm3/stm32f1/flash.h delete mode 100644 include/libopencm3/stm32f1/gpio.h delete mode 100644 include/libopencm3/stm32f1/memorymap.h delete mode 100644 include/libopencm3/stm32f1/nvic.h delete mode 100644 include/libopencm3/stm32f1/otg_fs.h delete mode 100644 include/libopencm3/stm32f1/rcc.h delete mode 100644 include/libopencm3/stm32f1/rtc.h delete mode 100644 include/libopencm3/stm32f1/scb.h delete mode 100644 include/libopencm3/stm32f1/systick.h delete mode 100644 include/libopencm3/stm32f1/tools.h delete mode 100644 include/libopencm3/stm32f1/usb.h delete mode 100644 include/libopencm3/stm32f1/usb_desc.h delete mode 100644 include/libopencm3/stm32f2/memorymap.h delete mode 100644 include/libopencm3/stm32f2/pwr.h delete mode 100644 include/libopencm3/stm32f2/spi.h delete mode 100644 include/libopencm3/stm32f2/timer.h delete mode 100644 include/libopencm3/stm32f2/usart.h diff --git a/include/libopencm3/stm32/can.h b/include/libopencm3/stm32/can.h new file mode 100644 index 0000000..1aa95a1 --- /dev/null +++ b/include/libopencm3/stm32/can.h @@ -0,0 +1,642 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Piotr Esden-Tempski + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_CAN_H +#define LIBOPENCM3_CAN_H + +#include +#include + +/* --- Convenience macros -------------------------------------------------- */ + +/* CAN register base adresses (for convenience) */ +#define CAN1 BX_CAN1_BASE +#define CAN2 BX_CAN2_BASE + +/* --- CAN registers ------------------------------------------------------- */ + +/* CAN master control register (CAN_MCR) */ +#define CAN_MCR(can_base) MMIO32(can_base + 0x000) +/* CAN master status register (CAN_MSR) */ +#define CAN_MSR(can_base) MMIO32(can_base + 0x004) +/* CAN transmit status register (CAN_TSR) */ +#define CAN_TSR(can_base) MMIO32(can_base + 0x008) + +/* CAN receive FIFO 0 register (CAN_RF0R) */ +#define CAN_RF0R(can_base) MMIO32(can_base + 0x00C) +/* CAN receive FIFO 1 register (CAN_RF1R) */ +#define CAN_RF1R(can_base) MMIO32(can_base + 0x010) + +/* CAN interrupt enable register (CAN_IER) */ +#define CAN_IER(can_base) MMIO32(can_base + 0x014) +/* CAN error status register (CAN_ESR) */ +#define CAN_ESR(can_base) MMIO32(can_base + 0x018) +/* CAN bit timing register (CAN_BTR) */ +#define CAN_BTR(can_base) MMIO32(can_base + 0x01C) + +/* Registers in the offset range 0x020 to 0x17F are reserved. */ + +/* --- CAN mailbox registers ----------------------------------------------- */ + +/* CAN mailbox / FIFO register offsets */ +#define CAN_MBOX0 0x180 +#define CAN_MBOX1 0x190 +#define CAN_MBOX2 0x1A0 +#define CAN_FIFO0 0x1B0 +#define CAN_FIFO1 0x1C0 + +/* CAN TX mailbox identifier register (CAN_TIxR) */ +#define CAN_TIxR(can_base, mbox) MMIO32(can_base + mbox + 0x0) +#define CAN_TI0R(can_base) CAN_TIxR(can_base, CAN_MBOX0) +#define CAN_TI1R(can_base) CAN_TIxR(can_base, CAN_MBOX1) +#define CAN_TI2R(can_base) CAN_TIxR(can_base, CAN_MBOX2) + +/* CAN mailbox data length control and time stamp register (CAN_TDTxR) */ +#define CAN_TDTxR(can_base, mbox) MMIO32(can_base + mbox + 0x4) +#define CAN_TDT0R(can_base) CAN_TDTxR(can_base, CAN_MBOX0) +#define CAN_TDT1R(can_base) CAN_TDTxR(can_base, CAN_MBOX1) +#define CAN_TDT2R(can_base) CAN_TDTxR(can_base, CAN_MBOX2) + +/* CAN mailbox data low register (CAN_TDLxR) */ +#define CAN_TDLxR(can_base, mbox) MMIO32(can_base + mbox + 0x8) +#define CAN_TDL0R(can_base) CAN_TDLxR(can_base, CAN_MBOX0) +#define CAN_TDL1R(can_base) CAN_TDLxR(can_base, CAN_MBOX1) +#define CAN_TDL2R(can_base) CAN_TDLxR(can_base, CAN_MBOX2) + +/* CAN mailbox data high register (CAN_TDHxR) */ +#define CAN_TDHxR(can_base, mbox) MMIO32(can_base + mbox + 0xC) +#define CAN_TDH0R(can_base) CAN_TDHxR(can_base, CAN_MBOX0) +#define CAN_TDH1R(can_base) CAN_TDHxR(can_base, CAN_MBOX1) +#define CAN_TDH2R(can_base) CAN_TDHxR(can_base, CAN_MBOX2) + +/* CAN RX FIFO identifier register (CAN_RIxR) */ +#define CAN_RIxR(can_base, fifo) MMIO32(can_base + fifo + 0x0) +#define CAN_RI0R(can_base) CAN_RIxR(can_base, CAN_FIFO0) +#define CAN_RI1R(can_base) CAN_RIxR(can_base, CAN_FIFO1) + +/* CAN RX FIFO mailbox data length control & time stamp register (CAN_RDTxR) */ +#define CAN_RDTxR(can_base, fifo) MMIO32(can_base + fifo + 0x4) +#define CAN_RDT0R(can_base) CAN_RDTxR(can_base, CAN_FIFO0) +#define CAN_RDT1R(can_base) CAN_RDTxR(can_base, CAN_FIFO1) + +/* CAN RX FIFO mailbox data low register (CAN_RDLxR) */ +#define CAN_RDLxR(can_base, fifo) MMIO32(can_base + fifo + 0x8) +#define CAN_RDL0R(can_base) CAN_RDLxR(can_base, CAN_FIFO0) +#define CAN_RDL1R(can_base) CAN_RDLxR(can_base, CAN_FIFO1) + +/* CAN RX FIFO mailbox data high register (CAN_RDHxR) */ +#define CAN_RDHxR(can_base, fifo) MMIO32(can_base + fifo + 0xC) +#define CAN_RDH0R(can_base) CAN_RDHxR(can_base, CAN_FIFO0) +#define CAN_RDH1R(can_base) CAN_RDHxR(can_base, CAN_FIFO1) + +/* --- CAN filter registers ------------------------------------------------ */ + +/* CAN filter master register (CAN_FMR) */ +#define CAN_FMR(can_base) MMIO32(can_base + 0x200) + +/* CAN filter mode register (CAN_FM1R) */ +#define CAN_FM1R(can_base) MMIO32(can_base + 0x204) + +/* Register offset 0x208 is reserved. */ + +/* CAN filter scale register (CAN_FS1R) */ +#define CAN_FS1R(can_base) MMIO32(can_base + 0x20C) + +/* Register offset 0x210 is reserved. */ + +/* CAN filter FIFO assignement register (CAN_FFA1R) */ +#define CAN_FFA1R(can_base) MMIO32(can_base + 0x214) + +/* Register offset 0x218 is reserved. */ + +/* CAN filter activation register (CAN_FA1R) */ +#define CAN_FA1R(can_base) MMIO32(can_base + 0x21C) + +/* Register offset 0x220 is reserved. */ + +/* Registers with offset 0x224 to 0x23F are reserved. */ + +/* CAN filter bank registers (CAN_FiRx) */ +/* + * Connectivity line devices have 28 banks so the bank ID spans 0..27 + * all other devices have 14 banks so the bank ID spans 0..13. + */ +#define CAN_FiR1(can_base, bank) MMIO32(can_base + 0x240 + (bank * 0x8) + 0x0) +#define CAN_FiR2(can_base, bank) MMIO32(can_base + 0x240 + (bank * 0x8) + 0x4) + +/* --- CAN_MCR values ------------------------------------------------------ */ + +/* 31:17 Reserved, forced by hardware to 0 */ + +/* DBF: Debug freeze */ +#define CAN_MCR_DBF (1 << 16) + +/* RESET: bxCAN software master reset */ +#define CAN_MCR_RESET (1 << 15) + +/* 14:8 Reserved, forced by hardware to 0 */ + +/* TTCM: Time triggered communication mode */ +#define CAN_MCR_TTCM (1 << 7) + +/* ABOM: Automatic bus-off management */ +#define CAN_MCR_ABOM (1 << 6) + +/* AWUM: Automatic wakeup mode */ +#define CAN_MCR_AWUM (1 << 5) + +/* NART: No automatic retransmission */ +#define CAN_MCR_NART (1 << 4) + +/* RFLM: Receive FIFO locked mode */ +#define CAN_MCR_RFLM (1 << 3) + +/* TXFP: Transmit FIFO priority */ +#define CAN_MCR_TXFP (1 << 2) + +/* SLEEP: Sleep mode request */ +#define CAN_MCR_SLEEP (1 << 1) + +/* INRQ: Initialization request */ +#define CAN_MCR_INRQ (1 << 0) + +/* --- CAN_MSR values ------------------------------------------------------ */ + +/* 31:12 Reserved, forced by hardware to 0 */ + +/* RX: CAN Rx signal */ +#define CAN_MSR_RX (1 << 11) + +/* SAMP: Last sample point */ +#define CAN_MSR_SAMP (1 << 10) + +/* RXM: Receive mode */ +#define CAN_MSR_RXM (1 << 9) + +/* TXM: Transmit mode */ +#define CAN_MSR_TXM (1 << 8) + +/* 7:5 Reserved, forced by hardware to 0 */ + +/* SLAKI: Sleep acknowledge interrupt */ +#define CAN_MSR_SLAKI (1 << 4) + +/* WKUI: Wakeup interrupt */ +#define CAN_MSR_WKUI (1 << 3) + +/* ERRI: Error interrupt */ +#define CAN_MSR_ERRI (1 << 2) + +/* SLAK: Sleep acknowledge */ +#define CAN_MSR_SLAK (1 << 1) + +/* INAK: Initialization acknowledge */ +#define CAN_MSR_INAK (1 << 0) + +/* --- CAN_TSR values ------------------------------------------------------ */ + +/* LOW2: Lowest priority flag for mailbox 2 */ +#define CAN_TSR_LOW2 (1 << 31) + +/* LOW1: Lowest priority flag for mailbox 1 */ +#define CAN_TSR_LOW1 (1 << 30) + +/* LOW0: Lowest priority flag for mailbox 0 */ +#define CAN_TSR_LOW0 (1 << 29) + +/* TME2: Transmit mailbox 2 empty */ +#define CAN_TSR_TME2 (1 << 28) + +/* TME1: Transmit mailbox 1 empty */ +#define CAN_TSR_TME1 (1 << 27) + +/* TME0: Transmit mailbox 0 empty */ +#define CAN_TSR_TME0 (1 << 26) + +/* CODE[1:0]: Mailbox code */ +#define CAN_TSR_CODE_MASK (0x3 << 24) + +/* ABRQ2: Abort request for mailbox 2 */ +#define CAN_TSR_TABRQ2 (1 << 23) + +/* 22:20 Reserved, forced by hardware to 0 */ + +/* TERR2: Transmission error for mailbox 2 */ +#define CAN_TSR_TERR2 (1 << 19) + +/* ALST2: Arbitration lost for mailbox 2 */ +#define CAN_TSR_ALST2 (1 << 18) + +/* TXOK2: Transmission OK for mailbox 2 */ +#define CAN_TSR_TXOK2 (1 << 17) + +/* RQCP2: Request completed mailbox 2 */ +#define CAN_TSR_RQCP2 (1 << 16) + +/* ABRQ1: Abort request for mailbox 1 */ +#define CAN_TSR_ABRQ1 (1 << 15) + +/* 14:12 Reserved, forced by hardware to 0 */ + +/* TERR1: Transmission error for mailbox 1 */ +#define CAN_TSR_TERR1 (1 << 11) + +/* ALST1: Arbitration lost for mailbox 1 */ +#define CAN_TSR_ALST1 (1 << 10) + +/* TXOK1: Transmission OK for mailbox 1 */ +#define CAN_TSR_TXOK1 (1 << 9) + +/* RQCP1: Request completed mailbox 1 */ +#define CAN_TSR_RQCP1 (1 << 8) + +/* ABRQ0: Abort request for mailbox 0 */ +#define CAN_TSR_ABRQ0 (1 << 7) + +/* 6:4 Reserved, forced by hardware to 0 */ + +/* TERR0: Transmission error for mailbox 0 */ +#define CAN_TSR_TERR0 (1 << 3) + +/* ALST0: Arbitration lost for mailbox 0 */ +#define CAN_TSR_ALST0 (1 << 2) + +/* TXOK0: Transmission OK for mailbox 0 */ +#define CAN_TSR_TXOK0 (1 << 1) + +/* RQCP0: Request completed mailbox 0 */ +#define CAN_TSR_RQCP0 (1 << 0) + +/* --- CAN_RF0R values ----------------------------------------------------- */ + +/* 31:6 Reserved, forced by hardware to 0 */ + +/* RFOM0: Release FIFO 0 output mailbox */ +#define CAN_RF0R_RFOM0 (1 << 5) + +/* FOVR0: FIFO 0 overrun */ +#define CAN_RF0R_FAVR0 (1 << 4) + +/* FULL0: FIFO 0 full */ +#define CAN_RF0R_FULL0 (1 << 3) + +/* 2 Reserved, forced by hardware to 0 */ + +/* FMP0[1:0]: FIFO 0 message pending */ +#define CAN_RF0R_FMP0_MASK (0x3 << 0) + +/* --- CAN_RF1R values ----------------------------------------------------- */ + +/* 31:6 Reserved, forced by hardware to 0 */ + +/* RFOM1: Release FIFO 1 output mailbox */ +#define CAN_RF1R_RFOM1 (1 << 5) + +/* FOVR1: FIFO 1 overrun */ +#define CAN_RF1R_FAVR1 (1 << 4) + +/* FULL1: FIFO 1 full */ +#define CAN_RF1R_FULL1 (1 << 3) + +/* 2 Reserved, forced by hardware to 0 */ + +/* FMP1[1:0]: FIFO 1 message pending */ +#define CAN_RF1R_FMP1_MASK (0x3 << 0) + +/* --- CAN_IER values ------------------------------------------------------ */ + +/* 32:18 Reserved, forced by hardware to 0 */ + +/* SLKIE: Sleep interrupt enable */ +#define CAN_IER_SLKIE (1 << 17) + +/* WKUIE: Wakeup interrupt enable */ +#define CAN_IER_WKUIE (1 << 16) + +/* ERRIE: Error interrupt enable */ +#define CAN_IER_ERRIE (1 << 15) + +/* 14:12 Reserved, forced by hardware to 0 */ + +/* LECIE: Last error code interrupt enable */ +#define CAN_IER_LECIE (1 << 11) + +/* BOFIE: Bus-off interrupt enable */ +#define CAN_IER_BOFIE (1 << 10) + +/* EPVIE: Error passive interrupt enable */ +#define CAN_IER_EPVIE (1 << 9) + +/* EWGIE: Error warning interrupt enable */ +#define CAN_IER_EWGIE (1 << 8) + +/* 7 Reserved, forced by hardware to 0 */ + +/* FOVIE1: FIFO overrun interrupt enable */ +#define CAN_IER_FOVIE1 (1 << 6) + +/* FFIE1: FIFO full interrupt enable */ +#define CAN_IER_FFIE1 (1 << 5) + +/* FMPIE1: FIFO message pending interrupt enable */ +#define CAN_IER_FMPIE1 (1 << 4) + +/* FOVIE0: FIFO overrun interrupt enable */ +#define CAN_IER_FOVIE0 (1 << 3) + +/* FFIE0: FIFO full interrupt enable */ +#define CAN_IER_FFIE0 (1 << 2) + +/* FMPIE0: FIFO message pending interrupt enable */ +#define CAN_IER_FMPIE0 (1 << 1) + +/* TMEIE: Transmit mailbox empty interrupt enable */ +#define CAN_IER_TMEIE (1 << 0) + +/* --- CAN_ESR values ------------------------------------------------------ */ + +/* REC[7:0]: Receive error counter */ +#define CAN_ESR_REC_MASK (0xF << 24) + +/* TEC[7:0]: Least significant byte of the 9-bit transmit error counter */ +#define CAN_ESR_TEC_MASK (0xF << 16) + +/* 15:7 Reserved, forced by hardware to 0 */ + +/* LEC[2:0]: Last error code */ +#define CAN_ESR_LEC_NO_ERROR (0x0 << 4) +#define CAN_ESR_LEC_STUFF_ERROR (0x1 << 4) +#define CAN_ESR_LEC_FORM_ERROR (0x2 << 4) +#define CAN_ESR_LEC_ACK_ERROR (0x3 << 4) +#define CAN_ESR_LEC_REC_ERROR (0x4 << 4) +#define CAN_ESR_LEC_DOM_ERROR (0x5 << 4) +#define CAN_ESR_LEC_CRC_ERROR (0x6 << 4) +#define CAN_ESR_LEC_SOFT_ERROR (0x7 << 4) +#define CAN_ESR_LEC_MASK (0x7 << 4) + +/* 3 Reserved, forced by hardware to 0 */ + +/* BOFF: Bus-off flag */ +#define CAN_ESR_BOFF (1 << 2) + +/* EPVF: Error passive flag */ +#define CAN_ESR_EPVF (1 << 1) + +/* EWGF: Error warning flag */ +#define CAN_ESR_EWGF (1 << 0) + +/* --- CAN_BTR values ------------------------------------------------------ */ + +/* SILM: Silent mode (debug) */ +#define CAN_BTR_SILM (1 << 31) + +/* LBKM: Loop back mode (debug) */ +#define CAN_BTR_LBKM (1 << 30) + +/* 29:26 Reserved, forced by hardware to 0 */ + +/* SJW[1:0]: Resynchronization jump width */ +#define CAN_BTR_SJW_1TQ (0x0 << 24) +#define CAN_BTR_SJW_2TQ (0x1 << 24) +#define CAN_BTR_SJW_3TQ (0x2 << 24) +#define CAN_BTR_SJW_4TQ (0x3 << 24) +#define CAN_BTR_SJW_MASK (0x3 << 24) + +/* 23 Reserved, forced by hardware to 0 */ + +/* TS2[2:0]: Time segment 2 */ +#define CAN_BTR_TS2_1TQ (0x0 << 20) +#define CAN_BTR_TS2_2TQ (0x1 << 20) +#define CAN_BTR_TS2_3TQ (0x2 << 20) +#define CAN_BTR_TS2_4TQ (0x3 << 20) +#define CAN_BTR_TS2_5TQ (0x4 << 20) +#define CAN_BTR_TS2_6TQ (0x5 << 20) +#define CAN_BTR_TS2_7TQ (0x6 << 20) +#define CAN_BTR_TS2_8TQ (0x7 << 20) +#define CAN_BTR_TS2_MASK (0x7 << 20) + +/* TS1[3:0]: Time segment 1 */ +#define CAN_BTR_TS1_1TQ (0x0 << 16) +#define CAN_BTR_TS1_2TQ (0x1 << 16) +#define CAN_BTR_TS1_3TQ (0x2 << 16) +#define CAN_BTR_TS1_4TQ (0x3 << 16) +#define CAN_BTR_TS1_5TQ (0x4 << 16) +#define CAN_BTR_TS1_6TQ (0x5 << 16) +#define CAN_BTR_TS1_7TQ (0x6 << 16) +#define CAN_BTR_TS1_8TQ (0x7 << 16) +#define CAN_BTR_TS1_9TQ (0x8 << 16) +#define CAN_BTR_TS1_10TQ (0x9 << 16) +#define CAN_BTR_TS1_11TQ (0xA << 16) +#define CAN_BTR_TS1_12TQ (0xB << 16) +#define CAN_BTR_TS1_13TQ (0xC << 16) +#define CAN_BTR_TS1_14TQ (0xD << 16) +#define CAN_BTR_TS1_15TQ (0xE << 16) +#define CAN_BTR_TS1_16TQ (0xF << 16) +#define CAN_BTR_TS1_MASK (0xF << 16) + +/* 15:10 Reserved, forced by hardware to 0 */ + +/* BRP[9:0]: Baud rate prescaler */ +#define CAN_BTR_BRP_MASK (0x1FF << 0) + +/* --- CAN_TIxR values ------------------------------------------------------ */ + +/* STID[10:0]: Standard identifier */ +#define CAN_TIxR_STID_MASK (0x3FF << 21) +#define CAN_TIxR_STID_SHIFT 21 + +/* EXID[15:0]: Extended identifier */ +#define CAN_TIxR_EXID_MASK (0x1FFFFFF << 3) +#define CAN_TIxR_EXID_SHIFT 3 + +/* IDE: Identifier extension */ +#define CAN_TIxR_IDE (1 << 2) + +/* RTR: Remote transmission request */ +#define CAN_TIxR_RTR (1 << 1) + +/* TXRQ: Transmit mailbox request */ +#define CAN_TIxR_TXRQ (1 << 0) + +/* --- CAN_TDTxR values ----------------------------------------------------- */ + +/* TIME[15:0]: Message time stamp */ +#define CAN_TDTxR_TIME_MASK (0xFFFF << 15) +#define CAN_TDTxR_TIME_SHIFT 15 + +/* 15:6 Reserved, forced by hardware to 0 */ + +/* TGT: Transmit global time */ +#define CAN_TDTxR_TGT (1 << 5) + +/* 7:4 Reserved, forced by hardware to 0 */ + +/* DLC[3:0]: Data length code */ +#define CAN_TDTxR_DLC_MASK (0xF << 0) +#define CAN_TDTxR_DLC_SHIFT 0 + +/* --- CAN_TDLxR values ----------------------------------------------------- */ + +/* DATA3[7:0]: Data byte 3 */ +/* DATA2[7:0]: Data byte 2 */ +/* DATA1[7:0]: Data byte 1 */ +/* DATA0[7:0]: Data byte 0 */ + +/* --- CAN_TDHxR values ----------------------------------------------------- */ + +/* DATA7[7:0]: Data byte 7 */ +/* DATA6[7:0]: Data byte 6 */ +/* DATA5[7:0]: Data byte 5 */ +/* DATA4[7:0]: Data byte 4 */ + +/* --- CAN_RIxR values ------------------------------------------------------ */ + +/* STID[10:0]: Standard identifier */ +#define CAN_RIxR_STID_MASK (0x3FF << 21) +#define CAN_RIxR_STID_SHIFT 21 + +/* EXID[15:0]: Extended identifier */ +#define CAN_RIxR_EXID_MASK (0x1FFFFFF << 3) +#define CAN_RIxR_EXID_SHIFT 3 + +/* IDE: Identifier extension */ +#define CAN_RIxR_IDE (1 << 2) + +/* RTR: Remote transmission request */ +#define CAN_RIxR_RTR (1 << 1) + +/* 0 Reserved */ + +/* --- CAN_RDTxR values ----------------------------------------------------- */ + +/* TIME[15:0]: Message time stamp */ +#define CAN_RDTxR_TIME_MASK (0xFFFF << 15) +#define CAN_RDTxR_TIME_SHIFT 15 + +/* FMI[7:0]: Filter match index */ +#define CAN_RDTxR_FMI_MASK (0xFF << 8) +#define CAN_RDTxR_FMI_SHIFT 8 + +/* 7:4 Reserved, forced by hardware to 0 */ + +/* DLC[3:0]: Data length code */ +#define CAN_RDTxR_DLC_MASK (0xF << 0) +#define CAN_RDTxR_DLC_SHIFT 0 + +/* --- CAN_RDLxR values ----------------------------------------------------- */ + +/* DATA3[7:0]: Data byte 3 */ +/* DATA2[7:0]: Data byte 2 */ +/* DATA1[7:0]: Data byte 1 */ +/* DATA0[7:0]: Data byte 0 */ + +/* --- CAN_RDHxR values ----------------------------------------------------- */ + +/* DATA7[7:0]: Data byte 7 */ +/* DATA6[7:0]: Data byte 6 */ +/* DATA5[7:0]: Data byte 5 */ +/* DATA4[7:0]: Data byte 4 */ + +/* --- CAN_FMR values ------------------------------------------------------- */ + +/* 31:14 Reserved, forced to reset value */ + +/* + * CAN2SB[5:0]: CAN2 start bank + * (only on connectivity line devices otherwise reserved) + */ +#define CAN_FMR_CAN2SB_MASK (0x3F << 8) +#define CAN_FMR_CAN2SB_SHIFT 15 + +/* 7:1 Reserved, forced to reset value */ + +/* FINIT: Filter init mode */ +#define CAN_FMR_FINIT (1 << 0) + +/* --- CAN_FM1R values ------------------------------------------------------ */ + +/* 31:28 Reserved, forced by hardware to 0 */ + +/* + * FBMx: Filter mode + * x is 0..27 should be calculated by a helper function making so many macros + * seems like an overkill? + */ + +/* --- CAN_FS1R values ------------------------------------------------------ */ + +/* 31:28 Reserved, forced by hardware to 0 */ + +/* + * FSCx: Filter scale configuration + * x is 0..27 should be calculated by a helper function making so many macros + * seems like an overkill? + */ + +/* --- CAN_FFA1R values ----------------------------------------------------- */ + +/* 31:28 Reserved, forced by hardware to 0 */ + +/* + * FFAx: Filter scale configuration + * x is 0..27 should be calculated by a helper function making so many macros + * seems like an overkill? + */ + +/* --- CAN_FA1R values ------------------------------------------------------ */ + +/* 31:28 Reserved, forced by hardware to 0 */ + +/* + * FACTx: Filter active + * x is 0..27 should be calculated by a helper function making so many macros + * seems like an overkill? + */ + +/* --- CAN_FiRx values ------------------------------------------------------ */ + +/* FB[31:0]: Filter bits */ + +/* --- CAN functions -------------------------------------------------------- */ + +void can_reset(u32 canport); +int can_init(u32 canport, bool ttcm, bool abom, bool awum, bool nart, + bool rflm, bool txfp, u32 sjw, u32 ts1, u32 ts2, u32 brp); + +void can_filter_init(u32 canport, u32 nr, bool scale_32bit, bool id_list_mode, + u32 fr1, u32 fr2, u32 fifo, bool enable); +void can_filter_id_mask_16bit_init(u32 canport, u32 nr, u16 id1, u16 mask1, + u16 id2, u16 mask2, u32 fifo, bool enable); +void can_filter_id_mask_32bit_init(u32 canport, u32 nr, u32 id, u32 mask, + u32 fifo, bool enable); +void can_filter_id_list_16bit_init(u32 canport, u32 nr, u16 id1, u16 id2, + u16 id3, u16 id4, u32 fifo, bool enable); +void can_filter_id_list_32bit_init(u32 canport, u32 nr, u32 id1, u32 id2, + u32 fifo, bool enable); + +void can_enable_irq(u32 canport, u32 irq); +void can_disable_irq(u32 canport, u32 irq); + +int can_transmit(u32 canport, u32 id, bool ext, bool rtr, u8 length, u8 *data); +void can_receive(u32 canport, u8 fifo, bool release, u32 *id, bool *ext, + bool *rtr, u32 *fmi, u8 *length, u8 *data); + +void can_fifo_release(u32 canport, u8 fifo); + +#endif diff --git a/include/libopencm3/stm32/crc.h b/include/libopencm3/stm32/crc.h new file mode 100644 index 0000000..5ad866e --- /dev/null +++ b/include/libopencm3/stm32/crc.h @@ -0,0 +1,52 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_CRC_H +#define LIBOPENCM3_CRC_H + +#include +#include + +/* --- CRC registers ------------------------------------------------------- */ + +/* Data register (CRC_DR) */ +#define CRC_DR MMIO32(CRC_BASE + 0x00) + +/* Independent data register (CRC_IDR) */ +#define CRC_IDR MMIO32(CRC_BASE + 0x04) + +/* Control register (CRC_CR) */ +#define CRC_CR MMIO32(CRC_BASE + 0x08) + +/* --- CRC_DR values ------------------------------------------------------- */ + +/* Bits[31:0] Data register */ + +/* --- CRC_IDR values ------------------------------------------------------ */ + +/* Bits[7:0] General-purpose 8-bit data register bits */ + +/* --- CRC_CR values ------------------------------------------------------- */ + +/* RESET bit */ +#define CRC_CR_RESET (1 << 0) + +/* --- CRC function prototypes --------------------------------------------- */ + +#endif diff --git a/include/libopencm3/stm32/dbgmcu.h b/include/libopencm3/stm32/dbgmcu.h new file mode 100644 index 0000000..e753f5e --- /dev/null +++ b/include/libopencm3/stm32/dbgmcu.h @@ -0,0 +1,60 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Gareth McMullin + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_STM32_DBGMCU_H +#define LIBOPENCM3_STM32_DBGMCU_H + +#include +#include + +/* --- DBGMCU registers ---------------------------------------------------- */ + +#define DBGMCU_IDCODE MMIO32(DBGMCU_BASE + 0x00) +#define DBGMCU_CR MMIO32(DBGMCU_BASE + 0x04) + +/* DBGMCU_CR bits */ +#define DBGMCU_CR_SLEEP 0x00000001 +#define DBGMCU_CR_STOP 0x00000002 +#define DBGMCU_CR_STANDBY 0x00000004 +#define DBGMCU_CR_TRACE_IOEN 0x00000020 +#define DBGMCU_CR_TRACE_MODE_MASK 0x000000C0 +#define DBGMCU_CR_TRACE_MODE_ASYNC 0x00000000 +#define DBGMCU_CR_TRACE_MODE_SYNC_1 0x00000040 +#define DBGMCU_CR_TRACE_MODE_SYNC_2 0x00000080 +#define DBGMCU_CR_TRACE_MODE_SYNC_4 0x000000C0 +#define DBGMCU_CR_IWDG_STOP 0x00000100 +#define DBGMCU_CR_WWDG_STOP 0x00000200 +#define DBGMCU_CR_TIM1_STOP 0x00000400 +#define DBGMCU_CR_TIM2_STOP 0x00000800 +#define DBGMCU_CR_TIM3_STOP 0x00001000 +#define DBGMCU_CR_TIM4_STOP 0x00002000 +#define DBGMCU_CR_CAN1_STOP 0x00004000 +#define DBGMCU_CR_I2C1_SMBUS_TIMEOUT 0x00008000 +#define DBGMCU_CR_I2C2_SMBUS_TIMEOUT 0x00010000 +#define DBGMCU_CR_TIM8_STOP 0x00020000 +#define DBGMCU_CR_TIM5_STOP 0x00040000 +#define DBGMCU_CR_TIM6_STOP 0x00080000 +#define DBGMCU_CR_TIM7_STOP 0x00100000 +#define DBGMCU_CR_CAN2_STOP 0x00200000 + +/* DBGMCU_IDCODE bits */ +#define DBGMCU_IDCODE_DEV_ID_MASK 0x00000fff +#define DBGMCU_IDCODE_REV_ID_MASK 0xffff0000 + +#endif diff --git a/include/libopencm3/stm32/exti.h b/include/libopencm3/stm32/exti.h new file mode 100644 index 0000000..19ab547 --- /dev/null +++ b/include/libopencm3/stm32/exti.h @@ -0,0 +1,70 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Mark Butler + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_EXTI_H +#define LIBOPENCM3_EXTI_H + +#include +#include + +/* --- EXTI registers ------------------------------------------------------ */ + +#define EXTI_IMR MMIO32(EXTI_BASE + 0x00) +#define EXTI_EMR MMIO32(EXTI_BASE + 0x04) +#define EXTI_RTSR MMIO32(EXTI_BASE + 0x08) +#define EXTI_FTSR MMIO32(EXTI_BASE + 0x0c) +#define EXTI_SWIER MMIO32(EXTI_BASE + 0x10) +#define EXTI_PR MMIO32(EXTI_BASE + 0x14) + +/* EXTI number definitions */ +#define EXTI0 (1 << 0) +#define EXTI1 (1 << 1) +#define EXTI2 (1 << 2) +#define EXTI3 (1 << 3) +#define EXTI4 (1 << 4) +#define EXTI5 (1 << 5) +#define EXTI6 (1 << 6) +#define EXTI7 (1 << 7) +#define EXTI8 (1 << 8) +#define EXTI9 (1 << 9) +#define EXTI10 (1 << 10) +#define EXTI11 (1 << 11) +#define EXTI12 (1 << 12) +#define EXTI13 (1 << 13) +#define EXTI14 (1 << 14) +#define EXTI15 (1 << 15) +#define EXTI16 (1 << 16) +#define EXTI17 (1 << 17) +#define EXTI18 (1 << 18) +#define EXTI19 (1 << 19) + +/* Trigger types */ +typedef enum trigger_e { + EXTI_TRIGGER_RISING, + EXTI_TRIGGER_FALLING, + EXTI_TRIGGER_BOTH, +} exti_trigger_type; + +void exti_set_trigger(u32 extis, exti_trigger_type trig); +void exti_enable_request(u32 extis); +void exti_disable_request(u32 extis); +void exti_reset_request(u32 extis); +void exti_select_source(u32 exti, u32 gpioport); + +#endif diff --git a/include/libopencm3/stm32/f1/adc.h b/include/libopencm3/stm32/f1/adc.h new file mode 100644 index 0000000..6e35d59 --- /dev/null +++ b/include/libopencm3/stm32/f1/adc.h @@ -0,0 +1,418 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Edward Cheeseman + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_ADC_H +#define LIBOPENCM3_ADC_H + +#include +#include + +/* --- Convenience macros -------------------------------------------------- */ + +/* ADC port base addresses (for convenience) */ +#define ADC1 ADC1_BASE +#define ADC2 ADC2_BASE +#define ADC3 ADC3_BASE + +/* --- ADC registers ------------------------------------------------------- */ + +/* ADC status register (ADC_SR) */ +#define ADC_SR(block) MMIO32(block + 0x00) +#define ADC1_SR ADC_SR(ADC1) +#define ADC2_SR ADC_SR(ADC2) +#define ADC3_SR ADC_SR(ADC3) + +/* ADC control register 1 (ADC_CR1) */ +#define ADC_CR1(block) MMIO32(block + 0x04) +#define ADC1_CR1 ADC_CR1(ADC1) +#define ADC2_CR1 ADC_CR1(ADC2) +#define ADC3_CR1 ADC_CR1(ADC3) + +/* ADC control register 2 (ADC_CR2) */ +#define ADC_CR2(block) MMIO32(block + 0x08) +#define ADC1_CR2 ADC_CR2(ADC1) +#define ADC2_CR2 ADC_CR2(ADC2) +#define ADC3_CR2 ADC_CR2(ADC3) + +/* ADC sample time register 1 (ADC_SMPR1) */ +#define ADC_SMPR1(block) MMIO32(block + 0x0c) +#define ADC1_SMPR1 ADC_SMPR1(ADC1) +#define ADC2_SMPR1 ADC_SMPR1(ADC2) +#define ADC3_SMPR1 ADC_SMPR1(ADC3) + +/* ADC sample time register 2 (ADC_SMPR2) */ +#define ADC_SMPR2(block) MMIO32(block + 0x10) +#define ADC1_SMPR2 ADC_SMPR2(ADC1) +#define ADC2_SMPR2 ADC_SMPR2(ADC2) +#define ADC3_SMPR2 ADC_SMPR2(ADC3) + +/* ADC injected channel data offset register x (ADC_JOFRx) (x=1..4) */ +#define ADC_JOFR1(block) MMIO32(block + 0x14) +#define ADC_JOFR2(block) MMIO32(block + 0x18) +#define ADC_JOFR3(block) MMIO32(block + 0x1c) +#define ADC_JOFR4(block) MMIO32(block + 0x20) +#define ADC1_JOFR1 ADC_JOFR1(ADC1) +#define ADC2_JOFR1 ADC_JOFR1(ADC2) +#define ADC3_JOFR1 ADC_JOFR1(ADC3) +#define ADC1_JOFR2 ADC_JOFR2(ADC1) +#define ADC2_JOFR2 ADC_JOFR2(ADC2) +#define ADC3_JOFR2 ADC_JOFR2(ADC3) +#define ADC1_JOFR3 ADC_JOFR3(ADC1) +#define ADC2_JOFR3 ADC_JOFR3(ADC2) +#define ADC3_JOFR3 ADC_JOFR3(ADC3) +#define ADC1_JOFR4 ADC_JOFR4(ADC1) +#define ADC2_JOFR4 ADC_JOFR4(ADC2) +#define ADC3_JOFR4 ADC_JOFR4(ADC3) + +/* ADC watchdog high threshold register (ADC_HTR) */ +#define ADC_HTR(block) MMIO32(block + 0x24) +#define ADC1_HTR ADC_HTR(ADC1) +#define ADC2_HTR ADC_HTR(ADC2) +#define ADC3_HTR ADC_HTR(ADC3) + +/* ADC watchdog low threshold register (ADC_LTR) */ +#define ADC_LTR(block) MMIO32(block + 0x28) +#define ADC1_LTR ADC_LTR(ADC1_BASE) +#define ADC2_LTR ADC_LTR(ADC2_BASE) +#define ADC3_LTR ADC_LTR(ADC3_BASE) + +/* ADC regular sequence register 1 (ADC_SQR1) */ +#define ADC_SQR1(block) MMIO32(block + 0x2c) +#define ADC1_SQR1 ADC_SQR1(ADC1) +#define ADC2_SQR1 ADC_SQR1(ADC2) +#define ADC3_SQR1 ADC_SQR1(ADC3) + +/* ADC regular sequence register 2 (ADC_SQR2) */ +#define ADC_SQR2(block) MMIO32(block + 0x30) +#define ADC1_SQR2 ADC_SQR2(ADC1) +#define ADC2_SQR2 ADC_SQR2(ADC2) +#define ADC3_SQR2 ADC_SQR2(ADC3) + +/* ADC regular sequence register 3 (ADC_SQR3) */ +#define ADC_SQR3(block) MMIO32(block + 0x34) +#define ADC1_SQR3 ADC_SQR3(ADC1) +#define ADC2_SQR3 ADC_SQR3(ADC2) +#define ADC3_SQR3 ADC_SQR3(ADC3) + +/* ADC injected sequence register (ADC_JSQR) */ +#define ADC_JSQR(block) MMIO32(block + 0x38) +#define ADC1_JSQR ADC_JSQR(ADC1_BASE) +#define ADC2_JSQR ADC_JSQR(ADC2_BASE) +#define ADC3_JSQR ADC_JSQR(ADC3_BASE) + +/* ADC injected data register x (ADC_JDRx) (x=1..4) */ +#define ADC_JDR1(block) MMIO32(block + 0x3c) +#define ADC_JDR2(block) MMIO32(block + 0x40) +#define ADC_JDR3(block) MMIO32(block + 0x44) +#define ADC_JDR4(block) MMIO32(block + 0x48) +#define ADC1_JDR1 ADC_JDR1(ADC1) +#define ADC2_JDR1 ADC_JDR1(ADC2) +#define ADC3_JDR1 ADC_JDR1(ADC3) +#define ADC1_JDR2 ADC_JDR2(ADC1) +#define ADC2_JDR2 ADC_JDR2(ADC2) +#define ADC3_JDR2 ADC_JDR2(ADC3) +#define ADC1_JDR3 ADC_JDR3(ADC1) +#define ADC2_JDR3 ADC_JDR3(ADC2) +#define ADC3_JDR3 ADC_JDR3(ADC3) +#define ADC1_JDR4 ADC_JDR4(ADC1) +#define ADC2_JDR4 ADC_JDR4(ADC2) +#define ADC3_JDR4 ADC_JDR4(ADC3) + +/* ADC regular data register (ADC_DR) */ +#define ADC_DR(block) MMIO32(block + 0x4c) +#define ADC1_DR ADC_DR(ADC1) +#define ADC2_DR ADC_DR(ADC2) +#define ADC3_DR ADC_DR(ADC3) + +/* --- ADC_SR values ------------------------------------------------------- */ + +#define ADC_SR_STRT (1 << 4) +#define ADC_SR_JSTRT (1 << 3) +#define ADC_SR_JEOC (1 << 2) +#define ADC_SR_EOC (1 << 1) +#define ADC_SR_AWD (1 << 0) + +/* --- ADC_CR1 values ------------------------------------------------------ */ + +#define ADC_CR1_AWDEN (1 << 23) +#define ADC_CR1_JAWDEN (1 << 22) +#define ADC_CR1_DUALMOD_LSB 16 +#define ADC_CR1_DUALMOD_MSK (0xf << ADC_DUALMOD_LSB) /* ADC1 only */ +#define ADC_CR1_DISCNUM_LSB 13 +#define ADC_CR1_DISCNUM_MSK (0x7 << ADC_DISCNUM_LSB) +#define ADC_CR1_JDISCEN (1 << 12) +#define ADC_CR1_DISCEN (1 << 11) +#define ADC_CR1_JAUTO (1 << 10) +#define ADC_CR1_AWDSGL (1 << 9) +#define ADC_CR1_SCAN (1 << 8) +#define ADC_CR1_JEOCIE (1 << 7) +#define ADC_CR1_AWDIE (1 << 6) +#define ADC_CR1_EOCIE (1 << 5) +#define ADC_CR1_AWDCH_LSB 0 +#define ADC_CR1_AWDCH_MSK (0x1f << ADC_AWDCH_LSB) + +/* --- ADC_CR2 values ------------------------------------------------------ */ + +#define ADC_CR2_TSVREFE (1 << 23) /* ADC1 only! */ +#define ADC_CR2_SWSTART (1 << 22) +#define ADC_CR2_JSWSTART (1 << 21) +#define ADC_CR2_EXTTRIG (1 << 20) +#define ADC_CR2_EXTSEL_LSB 17 +#define ADC_CR2_EXTSEL_MSK (0x7 << ADC_EXTSEL_LSB) +/* The following are only valid for ADC1 and ADC2. */ +#define ADC_CR2_EXTSEL_TIM1_CC1 0x0 +#define ADC_CR2_EXTSEL_TIM1_CC2 0x1 +#define ADC_CR2_EXTSEL_TIM1_CC3 0x2 +#define ADC_CR2_EXTSEL_TIM2_CC2 0x3 +#define ADC_CR2_EXTSEL_TIM3_TRGO 0x4 +#define ADC_CR2_EXTSEL_TIM4_CC4 0x5 +#define ADC_CR2_EXTSEL_EXTI11 0x6 +#define ADC_CR2_EXTSEL_SWSTART 0x7 + +/* The following are only valid for ADC3 */ +#define ADC_CR2_EXTSEL_TIM3_CC1 0x0 +#define ADC_CR2_EXTSEL_TIM2_CC3 0x1 +#define ADC_CR2_EXTSEL_TIM8_CC1 0x3 +#define ADC_CR2_EXTSEL_TIM8_TRGO 0x4 +#define ADC_CR2_EXTSEL_TIM5_CC1 0x5 +#define ADC_CR2_EXTSEL_TIM5_CC3 0x6 + +/* Bit 16: reserved, must be kept cleared */ +#define ADC_CR2_JEXTTRIG (1 << 15) +#define ADC_CR2_JEXTSEL_LSB 12 +#define ADC_CR2_JEXTSEL_MSK (0x7 << ADC_JEXTSEL_LSB) +/* The following are only valid for ADC1 and ADC2. */ +#define ADC_CR2_JEXTSEL_TIM1_TRGO 0x0 +#define ADC_CR2_JEXTSEL_TIM1_CC4 0x1 +#define ADC_CR2_JEXTSEL_TIM2_TRGO 0x2 +#define ADC_CR2_JEXTSEL_TIM2_CC1 0x3 +#define ADC_CR2_JEXTSEL_TIM3_CC4 0x4 +#define ADC_CR2_JEXTSEL_TIM4_TRGO 0x5 +#define ADC_CR2_JEXTSEL_EXTI15 0x6 +#define ADC_CR2_JEXTSEL_JSWSTART 0x7 + +/* The following are the different meanings for ADC3 only. */ +#define ADC_CR2_JEXTSEL_TIM4_CC3 0x2 +#define ADC_CR2_JEXTSEL_TIM8_CC2 0x3 +#define ADC_CR2_JEXTSEL_TIM8_CC4 0x4 +#define ADC_CR2_JEXTSEL_TIM5_TRGO 0x5 +#define ADC_CR2_JEXTSEL_TIM5_CC4 0x6 + +#define ADC_CR2_ALIGN (1 << 11) +#define ADC_CR2_DMA (1 << 8) /* ADC 1 & 3 only! */ +/* Bits [7:4] have to be kept 0. */ +#define ADC_CR2_RSTCAL (1 << 3) +#define ADC_CR2_CAL (1 << 2) +#define ADC_CR2_CONT (1 << 1) +#define ADC_CR2_ADON (1 << 0) /* Must be separately written. */ + +/* --- ADC_SMPR1 values ---------------------------------------------------- */ + +#define ADC_SMPR1_SMP17_LSB 21 +#define ADC_SMPR1_SMP16_LSB 18 +#define ADC_SMPR1_SMP15_LSB 15 +#define ADC_SMPR1_SMP14_LSB 12 +#define ADC_SMPR1_SMP13_LSB 9 +#define ADC_SMPR1_SMP12_LSB 6 +#define ADC_SMPR1_SMP11_LSB 3 +#define ADC_SMPR1_SMP10_LSB 0 +#define ADC_SMPR1_SMP17_MSK (0x7 << ADC_SMP17_LSB) +#define ADC_SMPR1_SMP16_MSK (0x7 << ADC_SMP16_LSB) +#define ADC_SMPR1_SMP15_MSK (0x7 << ADC_SMP15_LSB) +#define ADC_SMPR1_SMP14_MSK (0x7 << ADC_SMP14_LSB) +#define ADC_SMPR1_SMP13_MSK (0x7 << ADC_SMP13_LSB) +#define ADC_SMPR1_SMP12_MSK (0x7 << ADC_SMP12_LSB) +#define ADC_SMPR1_SMP11_MSK (0x7 << ADC_SMP11_LSB) +#define ADC_SMPR1_SMP10_MSK (0x7 << ADC_SMP10_LSB) +#define ADC_SMPR1_SMP_1DOT5CYC 0x0 +#define ADC_SMPR1_SMP_7DOT5CYC 0x1 +#define ADC_SMPR1_SMP_13DOT5CYC 0x2 +#define ADC_SMPR1_SMP_28DOT5CYC 0x3 +#define ADC_SMPR1_SMP_41DOT5CYC 0x4 +#define ADC_SMPR1_SMP_55DOT5CYC 0x5 +#define ADC_SMPR1_SMP_71DOT5CYC 0x6 +#define ADC_SMPR1_SMP_239DOT5CYC 0x7 + +/* --- ADC_SMPR2 values ---------------------------------------------------- */ + +#define ADC_SMPR2_SMP9_LSB 27 +#define ADC_SMPR2_SMP8_LSB 24 +#define ADC_SMPR2_SMP7_LSB 21 +#define ADC_SMPR2_SMP6_LSB 18 +#define ADC_SMPR2_SMP5_LSB 15 +#define ADC_SMPR2_SMP4_LSB 12 +#define ADC_SMPR2_SMP3_LSB 9 +#define ADC_SMPR2_SMP2_LSB 6 +#define ADC_SMPR2_SMP1_LSB 3 +#define ADC_SMPR2_SMP0_LSB 0 +#define ADC_SMPR2_SMP9_MSK (0x7 << ADC_SMP9_LSB) +#define ADC_SMPR2_SMP8_MSK (0x7 << ADC_SMP8_LSB) +#define ADC_SMPR2_SMP7_MSK (0x7 << ADC_SMP7_LSB) +#define ADC_SMPR2_SMP6_MSK (0x7 << ADC_SMP6_LSB) +#define ADC_SMPR2_SMP5_MSK (0x7 << ADC_SMP5_LSB) +#define ADC_SMPR2_SMP4_MSK (0x7 << ADC_SMP4_LSB) +#define ADC_SMPR2_SMP3_MSK (0x7 << ADC_SMP3_LSB) +#define ADC_SMPR2_SMP2_MSK (0x7 << ADC_SMP2_LSB) +#define ADC_SMPR2_SMP1_MSK (0x7 << ADC_SMP1_LSB) +#define ADC_SMPR2_SMP0_MSK (0x7 << ADC_SMP0_LSB) +#define ADC_SMPR2_SMP_1DOT5CYC 0x0 +#define ADC_SMPR2_SMP_7DOT5CYC 0x1 +#define ADC_SMPR2_SMP_13DOT5CYC 0x2 +#define ADC_SMPR2_SMP_28DOT5CYC 0x3 +#define ADC_SMPR2_SMP_41DOT5CYC 0x4 +#define ADC_SMPR2_SMP_55DOT5CYC 0x5 +#define ADC_SMPR2_SMP_71DOT5CYC 0x6 +#define ADC_SMPR2_SMP_239DOT5CYC 0x7 + +/* --- ADC_SMPRx generic values -------------------------------------------- */ + +#define ADC_SMPR_SMP_1DOT5CYC 0x0 +#define ADC_SMPR_SMP_7DOT5CYC 0x1 +#define ADC_SMPR_SMP_13DOT5CYC 0x2 +#define ADC_SMPR_SMP_28DOT5CYC 0x3 +#define ADC_SMPR_SMP_41DOT5CYC 0x4 +#define ADC_SMPR_SMP_55DOT5CYC 0x5 +#define ADC_SMPR_SMP_71DOT5CYC 0x6 +#define ADC_SMPR_SMP_239DOT5CYC 0x7 + +/* --- ADC_JOFRx, ADC_HTR, ADC_LTR values ---------------------------------- */ + +#define ADC_JOFFSET_LSB 0 +#define ADC_JOFFSET_MSK (0x7ff << 0) +#define ADC_HT_LSB 0 +#define ADC_HT_MSK (0x7ff << 0) +#define ADC_LT_LSB 0 +#define ADC_LT_MSK (0x7ff << 0) + +/* --- ADC_SQR1 values ----------------------------------------------------- */ + +#define ADC_SQR1_L_LSB 20 +#define ADC_SQR1_SQ16_LSB 15 +#define ADC_SQR1_SQ15_LSB 10 +#define ADC_SQR1_SQ14_LSB 5 +#define ADC_SQR1_SQ13_LSB 0 +#define ADC_SQR1_L_MSK (0xf << ADC_L_LSB) +#define ADC_SQR1_SQ16_MSK (0x1f << ADC_SQ16_LSB) +#define ADC_SQR1_SQ15_MSK (0x1f << ADC_SQ15_LSB) +#define ADC_SQR1_SQ14_MSK (0x1f << ADC_SQ14_LSB) +#define ADC_SQR1_SQ13_MSK (0x1f << ADC_SQ13_LSB) + +/* --- ADC_SQR2 values ----------------------------------------------------- */ + +#define ADC_SQR2_SQ12_LSB 25 +#define ADC_SQR2_SQ11_LSB 20 +#define ADC_SQR2_SQ10_LSB 15 +#define ADC_SQR2_SQ9_LSB 10 +#define ADC_SQR2_SQ8_LSB 5 +#define ADC_SQR2_SQ7_LSB 0 +#define ADC_SQR2_SQ12_MSK (0x1f << ADC_SQ12_LSB) +#define ADC_SQR2_SQ11_MSK (0x1f << ADC_SQ11_LSB) +#define ADC_SQR2_SQ10_MSK (0x1f << ADC_SQ10_LSB) +#define ADC_SQR2_SQ9_MSK (0x1f << ADC_SQ9_LSB) +#define ADC_SQR2_SQ8_MSK (0x1f << ADC_SQ8_LSB) +#define ADC_SQR2_SQ7_MSK (0x1f << ADC_SQ7_LSB) + +/* --- ADC_SQR3 values ----------------------------------------------------- */ + +#define ADC_SQR3_SQ6_LSB 25 +#define ADC_SQR3_SQ5_LSB 20 +#define ADC_SQR3_SQ4_LSB 15 +#define ADC_SQR3_SQ3_LSB 10 +#define ADC_SQR3_SQ2_LSB 5 +#define ADC_SQR3_SQ1_LSB 0 +#define ADC_SQR3_SQ6_MSK (0x1f << ADC_SQ6_LSB) +#define ADC_SQR3_SQ5_MSK (0x1f << ADC_SQ5_LSB) +#define ADC_SQR3_SQ4_MSK (0x1f << ADC_SQ4_LSB) +#define ADC_SQR3_SQ3_MSK (0x1f << ADC_SQ3_LSB) +#define ADC_SQR3_SQ2_MSK (0x1f << ADC_SQ2_LSB) +#define ADC_SQR3_SQ1_MSK (0x1f << ADC_SQ1_LSB) + +/* --- ADC_JSQR values ----------------------------------------------------- */ + +#define ADC_JSQR_JL_LSB 20 +#define ADC_JSQR_JSQ4_LSB 15 +#define ADC_JSQR_JSQ3_LSB 10 +#define ADC_JSQR_JSQ2_LSB 5 +#define ADC_JSQR_JSQ1_LSB 0 +#define ADC_JSQR_JL_MSK (0x2 << ADC_JL_LSB) +#define ADC_JSQR_JSQ4_MSK (0x1f << ADC_JSQ4_LSB) +#define ADC_JSQR_JSQ3_MSK (0x1f << ADC_JSQ3_LSB) +#define ADC_JSQR_JSQ2_MSK (0x1f << ADC_JSQ2_LSB) +#define ADC_JSQR_JSQ1_MSK (0x1f << ADC_JSQ1_LSB) + +/* --- ADC_JDRx, ADC_DR values --------------------------------------------- */ + +#define ADC_JDATA_LSB 0 +#define ADC_DATA_LSB 0 +#define ADC_ADC2DATA_LSB 16 /* ADC1 only (dual mode) */ +#define ADC_JDATA_MSK (0xffff << ADC_JDATA_LSB) +#define ADC_DATA_MSK (0xffff << ADC_DA) +#define ADC_ADC2DATA_MSK (0xffff << ADC_ADC2DATA_LSB) + /* ADC1 only (dual mode) */ + +/* --- Function prototypes ------------------------------------------------- */ + + +/* TODO */ +void adc_enable_analog_watchdog_regular(u32 adc); +void adc_disable_analog_watchdog_regular(u32 adc); +void adc_enable_analog_watchdog_injected(u32 adc); +void adc_disable_analog_watchdog_injected(u32 adc); +void adc_enable_discontinous_mode_regular(u32 adc); +void adc_disable_discontinous_mode_regular(u32 adc); +void adc_enable_discontinous_mode_injected(u32 adc); +void adc_disable_discontinous_mode_injected(u32 adc); +void adc_enable_automatic_injected_group_conversion(u32 adc); +void adc_disable_automatic_injected_group_conversion(u32 adc); +void adc_enable_analog_watchdog_on_all_channels(u32 adc); +void adc_enable_analog_watchdog_on_selected_channel(u32 adc, u8 channel); +void adc_enable_scan_mode(u32 adc); +void adc_disable_scan_mode(u32 adc); +void adc_enable_jeoc_interrupt(u32 adc); +void adc_disable_jeoc_interrupt(u32 adc); +void adc_enable_awd_interrupt(u32 adc); +void adc_disable_awd_interrupt(u32 adc); +void adc_enable_eoc_interrupt(u32 adc); +void adc_disable_eoc_interrupt(u32 adc); +void adc_enable_temperature_sensor(u32 adc); +void adc_disable_temperature_sensor(u32 adc); +void adc_start_conversion_regular(u32 adc); +void adc_start_conversion_injected(u32 adc); +void adc_enable_external_trigger_regular(u32 adc, u8 trigger); +void adc_disable_external_trigger_regular(u32 adc); +void adc_enable_external_trigger_injected(u32 adc, u8 trigger); +void adc_disable_external_trigger_injected(u32 adc); +void adc_set_left_aligned(u32 adc); +void adc_set_right_aligned(u32 adc); +void adc_enable_dma(u32 adc); +void adc_disable_dma(u32 adc); +void adc_reset_calibration(u32 adc); +void adc_calibration(u32 adc); +void adc_set_continous_conversion_mode(u32 adc); +void adc_set_single_conversion_mode(u32 adc); +void adc_on(u32 adc); +void adc_off(u32 adc); +void adc_set_conversion_time(u32 adc, u8 channel, u8 time); +void adc_set_conversion_time_on_all_channels(u32 adc, u8 time); +void adc_set_watchdog_high_threshold(u32 adc, u16 threshold); +void adc_set_watchdog_low_threshold(u32 adc, u16 threshold); +void adc_set_regular_sequence(u32 adc, u8 length, u8 channel[]); +void adc_set_injected_sequence(u32 adc, u8 length, u8 channel[]); + +#endif diff --git a/include/libopencm3/stm32/f1/bkp.h b/include/libopencm3/stm32/f1/bkp.h new file mode 100644 index 0000000..d700f9b --- /dev/null +++ b/include/libopencm3/stm32/f1/bkp.h @@ -0,0 +1,208 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_BKP_H +#define LIBOPENCM3_BKP_H + +#include +#include + +/* --- BKP registers ------------------------------------------------------- */ + +/* Backup data register 1 (BKP_DR1) */ +#define BKP_DR1 MMIO32(BACKUP_REGS_BASE + 0x04) + +/* Backup data register 2 (BKP_DR2) */ +#define BKP_DR2 MMIO32(BACKUP_REGS_BASE + 0x08) + +/* Backup data register 3 (BKP_DR3) */ +#define BKP_DR3 MMIO32(BACKUP_REGS_BASE + 0x0C) + +/* Backup data register 4 (BKP_DR4) */ +#define BKP_DR4 MMIO32(BACKUP_REGS_BASE + 0x10) + +/* Backup data register 5 (BKP_DR5) */ +#define BKP_DR5 MMIO32(BACKUP_REGS_BASE + 0x14) + +/* Backup data register 6 (BKP_DR6) */ +#define BKP_DR6 MMIO32(BACKUP_REGS_BASE + 0x18) + +/* Backup data register 7 (BKP_DR7) */ +#define BKP_DR7 MMIO32(BACKUP_REGS_BASE + 0x1C) + +/* Backup data register 8 (BKP_DR8) */ +#define BKP_DR8 MMIO32(BACKUP_REGS_BASE + 0x20) + +/* Backup data register 9 (BKP_DR9) */ +#define BKP_DR9 MMIO32(BACKUP_REGS_BASE + 0x24) + +/* Backup data register 10 (BKP_DR10) */ +#define BKP_DR10 MMIO32(BACKUP_REGS_BASE + 0x28) + +/* RTC clock calibration register (BKP_RTCCR) */ +#define BKP_RTCCR MMIO32(BACKUP_REGS_BASE + 0x2C) + +/* Backup control register (BKP_CR) */ +#define BKP_CR MMIO32(BACKUP_REGS_BASE + 0x30) + +/* Backup control/status register (BKP_CSR) */ +#define BKP_CSR MMIO32(BACKUP_REGS_BASE + 0x34) + +/* Backup data register 11 (BKP_DR11) */ +#define BKP_DR11 MMIO32(BACKUP_REGS_BASE + 0x40) + +/* Backup data register 12 (BKP_DR12) */ +#define BKP_DR12 MMIO32(BACKUP_REGS_BASE + 0x44) + +/* Backup data register 13 (BKP_DR13) */ +#define BKP_DR13 MMIO32(BACKUP_REGS_BASE + 0x48) + +/* Backup data register 14 (BKP_DR14) */ +#define BKP_DR14 MMIO32(BACKUP_REGS_BASE + 0x4C) + +/* Backup data register 15 (BKP_DR15) */ +#define BKP_DR15 MMIO32(BACKUP_REGS_BASE + 0x50) + +/* Backup data register 16 (BKP_DR16) */ +#define BKP_DR16 MMIO32(BACKUP_REGS_BASE + 0x54) + +/* Backup data register 17 (BKP_DR17) */ +#define BKP_DR17 MMIO32(BACKUP_REGS_BASE + 0x58) + +/* Backup data register 18 (BKP_DR18) */ +#define BKP_DR18 MMIO32(BACKUP_REGS_BASE + 0x5C) + +/* Backup data register 19 (BKP_DR19) */ +#define BKP_DR19 MMIO32(BACKUP_REGS_BASE + 0x60) + +/* Backup data register 20 (BKP_DR20) */ +#define BKP_DR20 MMIO32(BACKUP_REGS_BASE + 0x64) + +/* Backup data register 21 (BKP_DR21) */ +#define BKP_DR21 MMIO32(BACKUP_REGS_BASE + 0x68) + +/* Backup data register 22 (BKP_DR22) */ +#define BKP_DR22 MMIO32(BACKUP_REGS_BASE + 0x6C) + +/* Backup data register 23 (BKP_DR23) */ +#define BKP_DR23 MMIO32(BACKUP_REGS_BASE + 0x70) + +/* Backup data register 24 (BKP_DR24) */ +#define BKP_DR24 MMIO32(BACKUP_REGS_BASE + 0x74) + +/* Backup data register 25 (BKP_DR25) */ +#define BKP_DR25 MMIO32(BACKUP_REGS_BASE + 0x78) + +/* Backup data register 26 (BKP_DR26) */ +#define BKP_DR26 MMIO32(BACKUP_REGS_BASE + 0x7C) + +/* Backup data register 27 (BKP_DR27) */ +#define BKP_DR27 MMIO32(BACKUP_REGS_BASE + 0x80) + +/* Backup data register 28 (BKP_DR28) */ +#define BKP_DR28 MMIO32(BACKUP_REGS_BASE + 0x84) + +/* Backup data register 29 (BKP_DR29) */ +#define BKP_DR29 MMIO32(BACKUP_REGS_BASE + 0x88) + +/* Backup data register 30 (BKP_DR30) */ +#define BKP_DR30 MMIO32(BACKUP_REGS_BASE + 0x8C) + +/* Backup data register 31 (BKP_DR31) */ +#define BKP_DR31 MMIO32(BACKUP_REGS_BASE + 0x90) + +/* Backup data register 32 (BKP_DR32) */ +#define BKP_DR32 MMIO32(BACKUP_REGS_BASE + 0x94) + +/* Backup data register 33 (BKP_DR33) */ +#define BKP_DR33 MMIO32(BACKUP_REGS_BASE + 0x98) + +/* Backup data register 34 (BKP_DR34) */ +#define BKP_DR34 MMIO32(BACKUP_REGS_BASE + 0x9C) + +/* Backup data register 35 (BKP_DR35) */ +#define BKP_DR35 MMIO32(BACKUP_REGS_BASE + 0xA0) + +/* Backup data register 36 (BKP_DR36) */ +#define BKP_DR36 MMIO32(BACKUP_REGS_BASE + 0xA4) + +/* Backup data register 37 (BKP_DR37) */ +#define BKP_DR37 MMIO32(BACKUP_REGS_BASE + 0xA8) + +/* Backup data register 38 (BKP_DR38) */ +#define BKP_DR38 MMIO32(BACKUP_REGS_BASE + 0xAC) + +/* Backup data register 39 (BKP_DR39) */ +#define BKP_DR39 MMIO32(BACKUP_REGS_BASE + 0xB0) + +/* Backup data register 40 (BKP_DR40) */ +#define BKP_DR40 MMIO32(BACKUP_REGS_BASE + 0xB4) + +/* Backup data register 41 (BKP_DR41) */ +#define BKP_DR41 MMIO32(BACKUP_REGS_BASE + 0xB8) + +/* Backup data register 42 (BKP_DR42) */ +#define BKP_DR42 MMIO32(BACKUP_REGS_BASE + 0xBC) + +/* --- BKP_RTCCR values ---------------------------------------------------- */ + +/* ASOS: Alarm or second output selection */ +#define BKP_RTCCR_ASOS (1 << 9) + +/* ASOE: Alarm or second output enable */ +#define BKP_RTCCR_ASOE (1 << 8) + +/* CCO: Calibration clock output */ +#define BKP_RTCCR_CCO (1 << 7) + +/* CAL[6:0]: Calibration value */ +#define BKP_RTCCR_CAL_LSB 0 + +/* --- BKP_CR values ------------------------------------------------------- */ + +/* TPAL: TAMPER pin active level */ +#define BKP_CR_TAL (1 << 1) + +/* TPE: TAMPER pin enable */ +#define BKP_CR_TPE (1 << 0) + +/* --- BKP_CSR values ------------------------------------------------------ */ + +/* TIF: Tamper interrupt flag */ +#define BKP_CSR_TIF (1 << 9) + +/* TEF: Tamper event flag */ +#define BKP_CSR_TEF (1 << 8) + +/* TPIE: TAMPER pin interrupt enable */ +#define BKP_CSR_TPIE (1 << 2) + +/* CTI: Clear tamper interrupt */ +#define BKP_CSR_CTI (1 << 1) + +/* CTE: Clear tamper event */ +#define BKP_CSR_CTE (1 << 0) + +/* --- BKP_DRx values ------------------------------------------------------ */ + +/* Bits[15:0]: Backup data */ + +/* --- BKP function prototypes --------------------------------------------- */ + +#endif diff --git a/include/libopencm3/stm32/f1/dma.h b/include/libopencm3/stm32/f1/dma.h new file mode 100644 index 0000000..7d0a856 --- /dev/null +++ b/include/libopencm3/stm32/f1/dma.h @@ -0,0 +1,723 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_DMA_H +#define LIBOPENCM3_DMA_H + +#include +#include + +/* --- Convenience macros -------------------------------------------------- */ + +/* DMA register base adresses (for convenience) */ +#define DMA1 DMA1_BASE +#define DMA2 DMA2_BASE + +/* --- DMA registers ------------------------------------------------------- */ + +/* DMA interrupt status register (DMAx_ISR) */ +#define DMA_ISR(dma_base) MMIO32(dma_base + 0x00) +#define DMA1_ISR DMA_ISR(DMA1) +#define DMA2_ISR DMA_ISR(DMA2) + +/* DMA interrupt flag clear register (DMAx_IFCR) */ +#define DMA_IFCR(dma_base) MMIO32(dma_base + 0x04) +#define DMA1_IFCR DMA_IFCR(DMA1) +#define DMA2_IFCR DMA_IFCR(DMA2) + +/* DMA channel 1 configuration register (DMAx_CCR1) */ +#define DMA_CCR1(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 0) +#define DMA1_CCR1 DMA_CCR1(DMA1) +#define DMA2_CCR1 DMA_CCR1(DMA2) + +/* DMA channel 2 configuration register (DMAx_CCR2) */ +#define DMA_CCR2(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 1) +#define DMA1_CCR2 DMA_CCR2(DMA1) +#define DMA2_CCR2 DMA_CCR2(DMA2) + +/* DMA channel 3 configuration register (DMAx_CCR3) */ +#define DMA_CCR3(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 2) +#define DMA1_CCR3 DMA_CCR3(DMA1) +#define DMA2_CCR3 DMA_CCR3(DMA2) + +/* DMA channel 4 configuration register (DMAx_CCR4) */ +#define DMA_CCR4(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 3) +#define DMA1_CCR4 DMA_CCR4(DMA1) +#define DMA2_CCR4 DMA_CCR4(DMA2) + +/* DMA channel 5 configuration register (DMAx_CCR5) */ +#define DMA_CCR5(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 4) +#define DMA1_CCR5 DMA_CCR5(DMA1) +#define DMA2_CCR5 DMA_CCR5(DMA2) + +/* DMA channel 6 configuration register (DMAx_CCR6) */ +#define DMA_CCR6(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 5) +#define DMA1_CCR6 DMA_CCR6(DMA1) + +/* DMA channel 7 configuration register (DMAx_CCR7) */ +#define DMA_CCR7(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 6) +#define DMA1_CCR7 DMA_CCR7(DMA1) + +/* DMA channel 1 number of data register (DMAx_CNDTR1) */ +#define DMA_CNDTR1(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 0) +#define DMA1_CNDTR1 DMA_CNDTR1(DMA1) +#define DMA2_CNDTR1 DMA_CNDTR1(DMA2) + +/* DMA channel 2 number of data register (DMAx_CNDTR2) */ +#define DMA_CNDTR2(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 1) +#define DMA1_CNDTR2 DMA_CNDTR2(DMA1) +#define DMA2_CNDTR2 DMA_CNDTR2(DMA2) + +/* DMA channel 3 number of data register (DMAx_CNDTR3) */ +#define DMA_CNDTR3(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 2) +#define DMA1_CNDTR3 DMA_CNDTR3(DMA1) +#define DMA2_CNDTR3 DMA_CNDTR3(DMA2) + +/* DMA channel 4 number of data register (DMAx_CNDTR4) */ +#define DMA_CNDTR4(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 3) +#define DMA1_CNDTR4 DMA_CNDTR4(DMA1) +#define DMA2_CNDTR4 DMA_CNDTR4(DMA2) + +/* DMA channel 5 number of data register (DMAx_CNDTR5) */ +#define DMA_CNDTR5(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 4) +#define DMA1_CNDTR5 DMA_CNDTR5(DMA1) +#define DMA2_CNDTR5 DMA_CNDTR5(DMA2) + +/* DMA channel 6 number of data register (DMAx_CNDTR6) */ +#define DMA_CNDTR6(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 5) +#define DMA1_CNDTR6 DMA_CNDTR6(DMA1) + +/* DMA channel 7 number of data register (DMAx_CNDTR7) */ +#define DMA_CNDTR7(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 6) +#define DMA1_CNDTR7 DMA_CNDTR7(DMA1) + +/* DMA channel 1 peripheral address register (DMAx_CPAR1) */ +#define DMA_CPAR1(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 0) +#define DMA1_CPAR1 DMA_CPAR1(DMA1) +#define DMA2_CPAR1 DMA_CPAR1(DMA2) + +/* DMA channel 2 peripheral address register (DMAx_CPAR2) */ +#define DMA_CPAR2(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 1) +#define DMA1_CPAR2 DMA_CPAR2(DMA1) +#define DMA2_CPAR2 DMA_CPAR2(DMA2) + +/* DMA channel 3 peripheral address register (DMAx_CPAR3) */ +#define DMA_CPAR3(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 2) +#define DMA1_CPAR3 DMA_CPAR3(DMA1) +#define DMA2_CPAR3 DMA_CPAR3(DMA2) + +/* DMA channel 4 peripheral address register (DMAx_CPAR4) */ +#define DMA_CPAR4(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 3) +#define DMA1_CPAR4 DMA_CPAR4(DMA1) +#define DMA2_CPAR4 DMA_CPAR4(DMA2) + +/* DMA channel 5 peripheral address register (DMAx_CPAR5) */ +#define DMA_CPAR5(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 4) +#define DMA1_CPAR5 DMA_CPAR5(DMA1) +#define DMA2_CPAR5 DMA_CPAR5(DMA2) + +/* DMA channel 6 peripheral address register (DMAx_CPAR6) */ +#define DMA_CPAR6(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 5) +#define DMA1_CPAR6 DMA_CPAR6(DMA1) + +/* DMA channel 7 peripheral address register (DMAx_CPAR7) */ +#define DMA_CPAR7(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 6) +#define DMA1_CPAR7 DMA_CPAR7(DMA1) + +/* DMA channel 1 memory address register (DMAx_CMAR1) */ +#define DMA_CMAR1(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 0) +#define DMA1_CMAR1 DMA_CMAR1(DMA1) +#define DMA2_CMAR1 DMA_CMAR1(DMA2) + +/* DMA channel 2 memory address register (DMAx_CMAR2) */ +#define DMA_CMAR2(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 1) +#define DMA1_CMAR2 DMA_CMAR2(DMA1) +#define DMA2_CMAR2 DMA_CMAR2(DMA2) + +/* DMA channel 3 memory address register (DMAx_CMAR3) */ +#define DMA_CMAR3(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 2) +#define DMA1_CMAR3 DMA_CMAR3(DMA1) +#define DMA2_CMAR3 DMA_CMAR3(DMA2) + +/* DMA channel 4 memory address register (DMAx_CMAR4) */ +#define DMA_CMAR4(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 3) +#define DMA1_CMAR4 DMA_CMAR4(DMA1) +#define DMA2_CMAR4 DMA_CMAR4(DMA2) + +/* DMA channel 5 memory address register (DMAx_CMAR5) */ +#define DMA_CMAR5(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 4) +#define DMA1_CMAR5 DMA_CMAR5(DMA1) +#define DMA2_CMAR5 DMA_CMAR5(DMA2) + +/* DMA channel 6 memory address register (DMAx_CMAR6) */ +#define DMA_CMAR6(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 5) +#define DMA1_CMAR6 DMA_CMAR6(DMA1) + +/* DMA channel 7 memory address register (DMAx_CMAR7) */ +#define DMA_CMAR7(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 6) +#define DMA1_CMAR7 DMA_CMAR7(DMA1) + +/* --- DMA_ISR values ------------------------------------------------------ */ + +/* TEIF7: Channel 7 transfer error flag */ +#define DMA_ISR_TEIF7 (1 << 27) +/* HTIF7: Channel 7 half transfer flag */ +#define DMA_ISR_HTIF7 (1 << 26) +/* TCIF7: Channel 7 transfer complete flag */ +#define DMA_ISR_TCIF7 (1 << 25) +/* GIF7: Channel 7 global interrupt flag */ +#define DMA_ISR_GIF7 (1 << 24) +/* TEIF6: Channel 6 transfer error flag */ +#define DMA_ISR_TEIF6 (1 << 23) +/* HTIF6: Channel 6 half transfer flag */ +#define DMA_ISR_HTIF6 (1 << 22) +/* TCIF6: Channel 6 transfer complete flag */ +#define DMA_ISR_TCIF6 (1 << 21) +/* GIF6: Channel 6 global interrupt flag */ +#define DMA_ISR_GIF6 (1 << 20) +/* TEIF5: Channel 5 transfer error flag */ +#define DMA_ISR_TEIF5 (1 << 19) +/* HTIF5: Channel 5 half transfer flag */ +#define DMA_ISR_HTIF5 (1 << 18) +/* TCIF5: Channel 5 transfer complete flag */ +#define DMA_ISR_TCIF5 (1 << 17) +/* GIF5: Channel 5 global interrupt flag */ +#define DMA_ISR_GIF5 (1 << 16) +/* TEIF4: Channel 4 transfer error flag */ +#define DMA_ISR_TEIF4 (1 << 15) +/* HTIF4: Channel 4 half transfer flag */ +#define DMA_ISR_HTIF4 (1 << 14) +/* TCIF4: Channel 4 transfer complete flag */ +#define DMA_ISR_TCIF4 (1 << 13) +/* GIF4: Channel 4 global interrupt flag */ +#define DMA_ISR_GIF4 (1 << 12) +/* TEIF3: Channel 3 transfer error flag */ +#define DMA_ISR_TEIF3 (1 << 11) +/* HTIF3: Channel 3 half transfer flag */ +#define DMA_ISR_HTIF3 (1 << 10) +/* TCIF3: Channel 3 transfer complete flag */ +#define DMA_ISR_TCIF3 (1 << 9) +/* GIF3: Channel 3 global interrupt flag */ +#define DMA_ISR_GIF3 (1 << 8) +/* TEIF2: Channel 2 transfer error flag */ +#define DMA_ISR_TEIF2 (1 << 7) +/* HTIF2: Channel 23 half transfer flag */ +#define DMA_ISR_HTIF2 (1 << 6) +/* TCIF2: Channel 2 transfer complete flag */ +#define DMA_ISR_TCIF2 (1 << 5) +/* GIF2: Channel 2 global interrupt flag */ +#define DMA_ISR_GIF2 (1 << 4) +/* TEIF1: Channel 1 transfer error flag */ +#define DMA_ISR_TEIF1 (1 << 3) +/* HTIF1: Channel 1 half transfer flag */ +#define DMA_ISR_HTIF1 (1 << 2) +/* TCIF1: Channel 1 transfer complete flag */ +#define DMA_ISR_TCIF1 (1 << 1) +/* GIF1: Channel 1 global interrupt flag */ +#define DMA_ISR_GIF1 (1 << 0) + +/* --- DMA_IFCR values ----------------------------------------------------- */ + +/* CTEIF7: Channel 7 transfer error clear */ +#define DMA_IFCR_CTEIF7 (1 << 27) +/* CHTIF7: Channel 7 half transfer clear */ +#define DMA_IFCR_CHTIF7 (1 << 26) +/* CTCIF7: Channel 7 transfer complete clear */ +#define DMA_IFCR_CTCIF7 (1 << 25) +/* CGIF7: Channel 7 global interrupt clear */ +#define DMA_IFCR_CGIF7 (1 << 24) +/* CTEIF6: Channel 6 transfer error clear */ +#define DMA_IFCR_CTEIF6 (1 << 23) +/* CHTIF6: Channel 6 half transfer clear */ +#define DMA_IFCR_CHTIF6 (1 << 22) +/* CTCIF6: Channel 6 transfer complete clear */ +#define DMA_IFCR_CTCIF6 (1 << 21) +/* CGIF6: Channel 6 global interrupt clear */ +#define DMA_IFCR_CGIF6 (1 << 20) +/* CTEIF5: Channel 5 transfer error clear */ +#define DMA_IFCR_CTEIF5 (1 << 19) +/* CHTIF5: Channel 5 half transfer clear */ +#define DMA_IFCR_CHTIF5 (1 << 18) +/* CTCIF5: Channel 5 transfer complete clear */ +#define DMA_IFCR_CTCIF5 (1 << 17) +/* CGIF5: Channel 5 global interrupt clear */ +#define DMA_IFCR_CGIF5 (1 << 16) +/* CTEIF4: Channel 4 transfer error clear */ +#define DMA_IFCR_CTEIF4 (1 << 15) +/* CHTIF4: Channel 4 half transfer clear */ +#define DMA_IFCR_CHTIF4 (1 << 14) +/* CTCIF4: Channel 4 transfer complete clear */ +#define DMA_IFCR_CTCIF4 (1 << 13) +/* CGIF4: Channel 4 global interrupt clear */ +#define DMA_IFCR_CGIF4 (1 << 12) +/* CTEIF3: Channel 3 transfer error clear */ +#define DMA_IFCR_CTEIF3 (1 << 11) +/* CHTIF3: Channel 3 half transfer clear */ +#define DMA_IFCR_CHTIF3 (1 << 10) +/* CTCIF3: Channel 3 transfer complete clear */ +#define DMA_IFCR_CTCIF3 (1 << 9) +/* CGIF3: Channel 3 global interrupt clear */ +#define DMA_IFCR_CGIF3 (1 << 8) +/* CTEIF2: Channel 2 transfer error clear */ +#define DMA_IFCR_CTEIF2 (1 << 7) +/* CHTIF2: Channel 2 half transfer clear */ +#define DMA_IFCR_CHTIF2 (1 << 6) +/* CTCIF2: Channel 2 transfer complete clear */ +#define DMA_IFCR_CTCIF2 (1 << 5) +/* CGIF2: Channel 2 global interrupt clear */ +#define DMA_IFCR_CGIF2 (1 << 4) +/* CTEIF1: Channel 1 transfer error clear */ +#define DMA_IFCR_CTEIF1 (1 << 3) +/* CHTIF1: Channel 1 half transfer clear */ +#define DMA_IFCR_CHTIF1 (1 << 2) +/* CTCIF1: Channel 1 transfer complete clear */ +#define DMA_IFCR_CTCIF1 (1 << 1) +/* CGIF1: Channel 1 global interrupt clear */ +#define DMA_IFCR_CGIF1 (1 << 0) + +/* --- DMA_CCR1 values ----------------------------------------------------- */ + +/* MEM2MEM: Memory to memory mode */ +#define DMA_CCR1_MEM2MEM (1 << 14) + +/* PL[13:12]: Channel priority level */ +#define DMA_CCR1_PL_LSB 12 +#define DMA_CCR1_PL_LOW 0x0 +#define DMA_CCR1_PL_MEDIUM 0x1 +#define DMA_CCR1_PL_HIGH 0x2 +#define DMA_CCR1_PL_VERY_HIGH 0x3 + +/* MSIZE[11:10]: Memory size */ +#define DMA_CCR1_MSIZE_LSB 10 +#define DMA_CCR1_MSIZE_8BIT 0x0 +#define DMA_CCR1_MSIZE_16BIT 0x1 +#define DMA_CCR1_MSIZE_32BIT 0x2 + +/* PSIZE[9:8]: Peripheral size */ +#define DMA_CCR1_PSIZE_LSB 8 +#define DMA_CCR1_PSIZE_8BIT 0x0 +#define DMA_CCR1_PSIZE_16BIT 0x1 +#define DMA_CCR1_PSIZE_32BIT 0x2 + +/* MINC: Memory increment mode */ +#define DMA_CCR1_MINC (1 << 7) + +/* PINC: Peripheral increment mode */ +#define DMA_CCR1_PINC (1 << 6) + +/* CIRC: Circular mode */ +#define DMA_CCR1_CIRC (1 << 5) + +/* DIR: Data transfer direction */ +#define DMA_CCR1_DIR (1 << 4) + +/* TEIE: Transfer error interrupt enable */ +#define DMA_CCR1_TEIE (1 << 3) + +/* HTIE: Half transfer interrupt enable */ +#define DMA_CCR1_HTIE (1 << 2) + +/* TCIE: Transfer complete interrupt enable */ +#define DMA_CCR1_TCIE (1 << 1) + +/* EN: Channel enable */ +#define DMA_CCR1_EN (1 << 0) + +/* --- DMA_CCR2 values ----------------------------------------------------- */ + +/* MEM2MEM: Memory to memory mode */ +#define DMA_CCR2_MEM2MEM (1 << 14) + +/* PL[13:12]: Channel priority level */ +#define DMA_CCR2_PL_LSB 12 +#define DMA_CCR2_PL_LOW 0x0 +#define DMA_CCR2_PL_MEDIUM 0x1 +#define DMA_CCR2_PL_HIGH 0x2 +#define DMA_CCR2_PL_VERY_HIGH 0x3 + +/* MSIZE[11:10]: Memory size */ +#define DMA_CCR2_MSIZE_LSB 10 +#define DMA_CCR2_MSIZE_8BIT 0x0 +#define DMA_CCR2_MSIZE_16BIT 0x1 +#define DMA_CCR2_MSIZE_32BIT 0x2 + +/* PSIZE[9:8]: Peripheral size */ +#define DMA_CCR2_PSIZE_LSB 8 +#define DMA_CCR2_PSIZE_8BIT 0x0 +#define DMA_CCR2_PSIZE_16BIT 0x1 +#define DMA_CCR2_PSIZE_32BIT 0x2 + +/* MINC: Memory increment mode */ +#define DMA_CCR2_MINC (1 << 7) + +/* PINC: Peripheral increment mode */ +#define DMA_CCR2_PINC (1 << 6) + +/* CIRC: Circular mode */ +#define DMA_CCR2_CIRC (1 << 5) + +/* DIR: Data transfer direction */ +#define DMA_CCR2_DIR (1 << 4) + +/* TEIE: Transfer error interrupt enable */ +#define DMA_CCR2_TEIE (1 << 3) + +/* HTIE: Half transfer interrupt enable */ +#define DMA_CCR2_HTIE (1 << 2) + +/* TCIE: Transfer complete interrupt enable */ +#define DMA_CCR2_TCIE (1 << 1) + +/* EN: Channel enable */ +#define DMA_CCR2_EN (1 << 0) + +/* --- DMA_CCR3 values ----------------------------------------------------- */ + +/* MEM2MEM: Memory to memory mode */ +#define DMA_CCR3_MEM2MEM (1 << 14) + +/* PL[13:12]: Channel priority level */ +#define DMA_CCR3_PL_LSB 12 +#define DMA_CCR3_PL_LOW 0x0 +#define DMA_CCR3_PL_MEDIUM 0x1 +#define DMA_CCR3_PL_HIGH 0x2 +#define DMA_CCR3_PL_VERY_HIGH 0x3 + +/* MSIZE[11:10]: Memory size */ +#define DMA_CCR3_MSIZE_LSB 10 +#define DMA_CCR3_MSIZE_8BIT 0x0 +#define DMA_CCR31_MSIZE_16BIT 0x1 +#define DMA_CCR3_MSIZE_32BIT 0x2 + +/* PSIZE[9:8]: Peripheral size */ +#define DMA_CCR3_PSIZE_LSB 8 +#define DMA_CCR3_PSIZE_8BIT 0x0 +#define DMA_CCR3_PSIZE_16BIT 0x1 +#define DMA_CCR3_PSIZE_32BIT 0x2 + +/* MINC: Memory increment mode */ +#define DMA_CCR3_MINC (1 << 7) + +/* PINC: Peripheral increment mode */ +#define DMA_CCR3_PINC (1 << 6) + +/* CIRC: Circular mode */ +#define DMA_CCR3_CIRC (1 << 5) + +/* DIR: Data transfer direction */ +#define DMA_CCR3_DIR (1 << 4) + +/* TEIE: Transfer error interrupt enable */ +#define DMA_CCR3_TEIE (1 << 3) + +/* HTIE: Half transfer interrupt enable */ +#define DMA_CCR3_HTIE (1 << 2) + +/* TCIE: Transfer complete interrupt enable */ +#define DMA_CCR3_TCIE (1 << 1) + +/* EN: Channel enable */ +#define DMA_CCR3_EN (1 << 0) + +/* --- DMA_CCR4 values ----------------------------------------------------- */ + +/* MEM2MEM: Memory to memory mode */ +#define DMA_CCR4_MEM2MEM (1 << 14) + +/* PL[13:12]: Channel priority level */ +#define DMA_CCR4_PL_LSB 12 +#define DMA_CCR4_PL_LOW 0x0 +#define DMA_CCR4_PL_MEDIUM 0x1 +#define DMA_CCR4_PL_HIGH 0x2 +#define DMA_CCR4_PL_VERY_HIGH 0x3 + +/* MSIZE[11:10]: Memory size */ +#define DMA_CCR4_MSIZE_LSB 10 +#define DMA_CCR4_MSIZE_8BIT 0x0 +#define DMA_CCR4_MSIZE_16BIT 0x1 +#define DMA_CCR4_MSIZE_32BIT 0x2 + +/* PSIZE[9:8]: Peripheral size */ +#define DMA_CCR4_PSIZE_LSB 8 +#define DMA_CCR4_PSIZE_8BIT 0x0 +#define DMA_CCR4_PSIZE_16BIT 0x1 +#define DMA_CCR4_PSIZE_32BIT 0x2 + +/* MINC: Memory increment mode */ +#define DMA_CCR4_MINC (1 << 7) + +/* PINC: Peripheral increment mode */ +#define DMA_CCR4_PINC (1 << 6) + +/* CIRC: Circular mode */ +#define DMA_CCR4_CIRC (1 << 5) + +/* DIR: Data transfer direction */ +#define DMA_CCR4_DIR (1 << 4) + +/* TEIE: Transfer error interrupt enable */ +#define DMA_CCR4_TEIE (1 << 3) + +/* HTIE: Half transfer interrupt enable */ +#define DMA_CCR4_HTIE (1 << 2) + +/* TCIE: Transfer complete interrupt enable */ +#define DMA_CCR4_TCIE (1 << 1) + +/* EN: Channel enable */ +#define DMA_CCR4_EN (1 << 0) + +/* --- DMA_CCR5 values ----------------------------------------------------- */ + +/* MEM2MEM: Memory to memory mode */ +#define DMA_CCR5_MEM2MEM (1 << 14) + +/* PL[13:12]: Channel priority level */ +#define DMA_CCR5_PL_LSB 12 +#define DMA_CCR5_PL_LOW 0x0 +#define DMA_CCR5_PL_MEDIUM 0x1 +#define DMA_CCR5_PL_HIGH 0x2 +#define DMA_CCR5_PL_VERY_HIGH 0x3 + +/* MSIZE[11:10]: Memory size */ +#define DMA_CCR5_MSIZE_LSB 10 +#define DMA_CCR5_MSIZE_8BIT 0x0 +#define DMA_CCR5_MSIZE_16BIT 0x1 +#define DMA_CCR5_MSIZE_32BIT 0x2 + +/* PSIZE[9:8]: Peripheral size */ +#define DMA_CCR5_PSIZE_LSB 8 +#define DMA_CCR5_PSIZE_8BIT 0x0 +#define DMA_CCR5_PSIZE_16BIT 0x1 +#define DMA_CCR5_PSIZE_32BIT 0x2 + +/* MINC: Memory increment mode */ +#define DMA_CCR5_MINC (1 << 7) + +/* PINC: Peripheral increment mode */ +#define DMA_CCR5_PINC (1 << 6) + +/* CIRC: Circular mode */ +#define DMA_CCR5_CIRC (1 << 5) + +/* DIR: Data transfer direction */ +#define DMA_CCR5_DIR (1 << 4) + +/* TEIE: Transfer error interrupt enable */ +#define DMA_CCR5_TEIE (1 << 3) + +/* HTIE: Half transfer interrupt enable */ +#define DMA_CCR5_HTIE (1 << 2) + +/* TCIE: Transfer complete interrupt enable */ +#define DMA_CCR5_TCIE (1 << 1) + +/* EN: Channel enable */ +#define DMA_CCR5_EN (1 << 0) + +/* --- DMA_CCR6 values ----------------------------------------------------- */ + +/* MEM2MEM: Memory to memory mode */ +#define DMA_CCR6_MEM2MEM (1 << 14) + +/* PL[13:12]: Channel priority level */ +#define DMA_CCR6_PL_LSB 12 +#define DMA_CCR6_PL_LOW 0x0 +#define DMA_CCR6_PL_MEDIUM 0x1 +#define DMA_CCR6_PL_HIGH 0x2 +#define DMA_CCR6_PL_VERY_HIGH 0x3 + +/* MSIZE[11:10]: Memory size */ +#define DMA_CCR6_MSIZE_LSB 10 +#define DMA_CCR6_MSIZE_8BIT 0x0 +#define DMA_CCR6_MSIZE_16BIT 0x1 +#define DMA_CCR6_MSIZE_32BIT 0x2 + +/* PSIZE[9:8]: Peripheral size */ +#define DMA_CCR6_PSIZE_LSB 8 +#define DMA_CCR6_PSIZE_8BIT 0x0 +#define DMA_CCR6_PSIZE_16BIT 0x1 +#define DMA_CCR6_PSIZE_32BIT 0x2 + +/* MINC: Memory increment mode */ +#define DMA_CCR6_MINC (1 << 7) + +/* PINC: Peripheral increment mode */ +#define DMA_CCR6_PINC (1 << 6) + +/* CIRC: Circular mode */ +#define DMA_CCR6_CIRC (1 << 5) + +/* DIR: Data transfer direction */ +#define DMA_CCR6_DIR (1 << 4) + +/* TEIE: Transfer error interrupt enable */ +#define DMA_CCR6_TEIE (1 << 3) + +/* HTIE: Half transfer interrupt enable */ +#define DMA_CCR6_HTIE (1 << 2) + +/* TCIE: Transfer complete interrupt enable */ +#define DMA_CCR6_TCIE (1 << 1) + +/* EN: Channel enable */ +#define DMA_CCR6_EN (1 << 0) + +/* --- DMA_CCR7 values ----------------------------------------------------- */ + +/* MEM2MEM: Memory to memory mode */ +#define DMA_CCR7_MEM2MEM (1 << 14) + +/* PL[13:12]: Channel priority level */ +#define DMA_CCR7_PL_LSB 12 +#define DMA_CCR7_PL_LOW 0x0 +#define DMA_CCR7_PL_MEDIUM 0x1 +#define DMA_CCR7_PL_HIGH 0x2 +#define DMA_CCR7_PL_VERY_HIGH 0x3 + +/* MSIZE[11:10]: Memory size */ +#define DMA_CCR7_MSIZE_LSB 10 +#define DMA_CCR7_MSIZE_8BIT 0x0 +#define DMA_CCR7_MSIZE_16BIT 0x1 +#define DMA_CCR7_MSIZE_32BIT 0x2 + +/* PSIZE[9:8]: Peripheral size */ +#define DMA_CCR7_PSIZE_LSB 8 +#define DMA_CCR7_PSIZE_8BIT 0x0 +#define DMA_CCR7_PSIZE_16BIT 0x1 +#define DMA_CCR7_PSIZE_32BIT 0x2 + +/* MINC: Memory increment mode */ +#define DMA_CCR7_MINC (1 << 7) + +/* PINC: Peripheral increment mode */ +#define DMA_CCR7_PINC (1 << 6) + +/* CIRC: Circular mode */ +#define DMA_CCR7_CIRC (1 << 5) + +/* DIR: Data transfer direction */ +#define DMA_CCR7_DIR (1 << 4) + +/* TEIE: Transfer error interrupt enable */ +#define DMA_CCR7_TEIE (1 << 3) + +/* HTIE: Half transfer interrupt enable */ +#define DMA_CCR7_HTIE (1 << 2) + +/* TCIE: Transfer complete interrupt enable */ +#define DMA_CCR7_TCIE (1 << 1) + +/* EN: Channel enable */ +#define DMA_CCR7_EN (1 << 0) + +/* --- DMA_CCRx generic values --------------------------------------------- */ + +/* MEM2MEM: Memory to memory mode */ +#define DMA_CCR_MEM2MEM (1 << 14) + +/* PL[13:12]: Channel priority level */ +#define DMA_CCR_PL_LSB 12 +#define DMA_CCR_PL_LOW 0x0 +#define DMA_CCR_PL_MEDIUM 0x1 +#define DMA_CCR_PL_HIGH 0x2 +#define DMA_CCR_PL_VERY_HIGH 0x3 + +/* MSIZE[11:10]: Memory size */ +#define DMA_CCR_MSIZE_LSB 10 +#define DMA_CCR_MSIZE_8BIT 0x0 +#define DMA_CCR_MSIZE_16BIT 0x1 +#define DMA_CCR_MSIZE_32BIT 0x2 + +/* PSIZE[9:8]: Peripheral size */ +#define DMA_CCR_PSIZE_LSB 8 +#define DMA_CCR_PSIZE_8BIT 0x0 +#define DMA_CCR_PSIZE_16BIT 0x1 +#define DMA_CCR_PSIZE_32BIT 0x2 + +/* MINC: Memory increment mode */ +#define DMA_CCR_MINC (1 << 7) + +/* PINC: Peripheral increment mode */ +#define DMA_CCR_PINC (1 << 6) + +/* CIRC: Circular mode */ +#define DMA_CCR_CIRC (1 << 5) + +/* DIR: Data transfer direction */ +#define DMA_CCR_DIR (1 << 4) + +/* TEIE: Transfer error interrupt enable */ +#define DMA_CCR_TEIE (1 << 3) + +/* HTIE: Half transfer interrupt enable */ +#define DMA_CCR_HTIE (1 << 2) + +/* TCIE: Transfer complete interrupt enable */ +#define DMA_CCR_TCIE (1 << 1) + +/* EN: Channel enable */ +#define DMA_CCR_EN (1 << 0) + +/* --- DMA_CNDTRx values --------------------------------------------------- */ + +/* NDT[15:0]: Number of data to transfer */ + +/* --- DMA_CPARx values ---------------------------------------------------- */ + +/* PA[31:0]: Peripheral address */ + +/* --- DMA_CMARx values ---------------------------------------------------- */ + +/* MA[31:0]: Memory address */ + +/* --- Generic values ------------------------------------------------------ */ + +#define DMA_CHANNEL1 1 +#define DMA_CHANNEL2 2 +#define DMA_CHANNEL3 3 +#define DMA_CHANNEL4 4 +#define DMA_CHANNEL5 5 +#define DMA_CHANNEL6 6 +#define DMA_CHANNEL7 7 + +/* --- function prototypes ------------------------------------------------- */ + +void dma_enable_mem2mem_mode(u32 dma, u8 channel); +void dma_set_priority(u32 dma, u8 channel, u8 prio); +void dma_set_memory_size(u32 dma, u8 channel, u8 mem_size); +void dma_set_peripheral_size(u32 dma, u8 channel, u8 peripheral_size); +void dma_enable_memory_increment_mode(u32 dma, u8 channel); +void dma_enable_peripheral_increment_mode(u32 dma, u8 channel); +void dma_enable_circular_mode(u32 dma, u8 channel); +void dma_set_read_from_peripheral(u32 dma, u8 channel); +void dma_set_read_from_memory(u32 dma, u8 channel); +void dma_enable_transfer_error_interrupt(u32 dma, u8 channel); +void dma_disable_transfer_error_interrupt(u32 dma, u8 channel); +void dma_enable_half_transfer_interrupt(u32 dma, u8 channel); +void dma_disable_half_transfer_interrupt(u32 dma, u8 channel); +void dma_enable_transfer_complete_interrupt(u32 dma, u8 channel); +void dma_disable_transfer_complete_interrupt(u32 dma, u8 channel); +void dma_enable_channel(u32 dma, u8 channel); +void dma_disable_channel(u32 dma, u8 channel); +void dma_set_peripheral_address(u32 dma, u8 channel, u32 address); +void dma_set_memory_address(u32 dma, u8 channel, u32 address); +void dma_set_number_of_data(u32 dma, u8 channel, u16 number); + +#endif diff --git a/include/libopencm3/stm32/f1/ethernet.h b/include/libopencm3/stm32/f1/ethernet.h new file mode 100644 index 0000000..3d7f1ee --- /dev/null +++ b/include/libopencm3/stm32/f1/ethernet.h @@ -0,0 +1,203 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Gareth McMullin + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_ETHERNET_H +#define LIBOPENCM3_ETHERNET_H + +#include +#include + +/* Ethernet MAC registers */ +#define ETH_MACCR MMIO32(ETHERNET_BASE + 0x00) +#define ETH_MACFFR MMIO32(ETHERNET_BASE + 0x04) +#define ETH_MACHTHR MMIO32(ETHERNET_BASE + 0x08) +#define ETH_MACHTLR MMIO32(ETHERNET_BASE + 0x0C) +#define ETH_MACMIIAR MMIO32(ETHERNET_BASE + 0x10) +#define ETH_MACMIIDR MMIO32(ETHERNET_BASE + 0x14) +#define ETH_MACFCR MMIO32(ETHERNET_BASE + 0x18) +#define ETH_MACVLANTR MMIO32(ETHERNET_BASE + 0x1C) +#define ETH_MACRWUFFR MMIO32(ETHERNET_BASE + 0x28) +#define ETH_MACPMTCSR MMIO32(ETHERNET_BASE + 0x2C) +#define ETH_MACSR MMIO32(ETHERNET_BASE + 0x38) +#define ETH_MACIMR MMIO32(ETHERNET_BASE + 0x3C) +#define ETH_MACA0HR MMIO32(ETHERNET_BASE + 0x40) +#define ETH_MACA0LR MMIO32(ETHERNET_BASE + 0x44) +#define ETH_MACA1HR MMIO32(ETHERNET_BASE + 0x48) +#define ETH_MACA1LR MMIO32(ETHERNET_BASE + 0x4C) +#define ETH_MACA2HR MMIO32(ETHERNET_BASE + 0x50) +#define ETH_MACA2LR MMIO32(ETHERNET_BASE + 0x54) +#define ETH_MACA3HR MMIO32(ETHERNET_BASE + 0x58) +#define ETH_MACA3LR MMIO32(ETHERNET_BASE + 0x5C) + +/* Ethernet MMC registers */ +#define ETH_MMCCR MMIO32(ETHERNET_BASE + 0x100) +#define ETH_MMCRIR MMIO32(ETHERNET_BASE + 0x104) +#define ETH_MMCTIR MMIO32(ETHERNET_BASE + 0x108) +#define ETH_MMCRIMR MMIO32(ETHERNET_BASE + 0x10C) +#define ETH_MMCTIMR MMIO32(ETHERNET_BASE + 0x110) +#define ETH_MMCTGFSCCR MMIO32(ETHERNET_BASE + 0x14C) +#define ETH_MMCTGFMSCCR MMIO32(ETHERNET_BASE + 0x150) +#define ETH_MMCTGFCR MMIO32(ETHERNET_BASE + 0x168) +#define ETH_MMCRFCECR MMIO32(ETHERNET_BASE + 0x194) +#define ETH_MMCRFAECR MMIO32(ETHERNET_BASE + 0x198) +#define ETH_MMCRGUFCR MMIO32(ETHERNET_BASE + 0x1C4) + +/* Ethrenet IEEE 1588 time stamp registers */ +#define ETH_PTPTSCR MMIO32(ETHERNET_BASE + 0x700) +#define ETH_PTPSSIR MMIO32(ETHERNET_BASE + 0x704) +#define ETH_PTPTSHR MMIO32(ETHERNET_BASE + 0x708) +#define ETH_PTPTSLR MMIO32(ETHERNET_BASE + 0x70C) +#define ETH_PTPTSHUR MMIO32(ETHERNET_BASE + 0x710) +#define ETH_PTPTSLUR MMIO32(ETHERNET_BASE + 0x714) +#define ETH_PTPTSAR MMIO32(ETHERNET_BASE + 0x718) +#define ETH_PTPTTHR MMIO32(ETHERNET_BASE + 0x71C) +#define ETH_PTPTTLR MMIO32(ETHERNET_BASE + 0x720) + +/* Ethernet DMA registers */ +#define ETH_DMABMR MMIO32(ETHERNET_BASE + 0x1000) +#define ETH_DMATPDR MMIO32(ETHERNET_BASE + 0x1004) +#define ETH_DMARPDR MMIO32(ETHERNET_BASE + 0x1008) +#define ETH_DMARDLAR MMIO32(ETHERNET_BASE + 0x100C) +#define ETH_DMATDLAR MMIO32(ETHERNET_BASE + 0x1010) +#define ETH_DMATDLAR MMIO32(ETHERNET_BASE + 0x1010) +#define ETH_DMASR MMIO32(ETHERNET_BASE + 0x1014) +#define ETH_DMAOMR MMIO32(ETHERNET_BASE + 0x1018) +#define ETH_DMAIER MMIO32(ETHERNET_BASE + 0x101C) +#define ETH_DMAMFBOCR MMIO32(ETHERNET_BASE + 0x1020) +#define ETH_DMACHTDR MMIO32(ETHERNET_BASE + 0x1048) +#define ETH_DMACHRDR MMIO32(ETHERNET_BASE + 0x104C) +#define ETH_DMACHTBAR MMIO32(ETHERNET_BASE + 0x1050) +#define ETH_DMACHRBAR MMIO32(ETHERNET_BASE + 0x1054) + +/* Ethernet MAC Register bit definitions */ +/* Ethernet MAC configuration register ETH_MACCR bits */ +#define ETH_MACCR_RE 0x00000004 +#define ETH_MACCR_TE 0x00000008 +#define ETH_MACCR_DC 0x00000010 +#define ETH_MACCR_BL 0x00000060 +#define ETH_MACCR_APCS 0x00000080 +#define ETH_MACCR_RD 0x00000200 +#define ETH_MACCR_IPCO 0x00000400 +#define ETH_MACCR_DM 0x00000800 +#define ETH_MACCR_LM 0x00001000 +#define ETH_MACCR_ROD 0x00002000 +#define ETH_MACCR_FES 0x00004000 +#define ETH_MACCR_CSD 0x00010000 +#define ETH_MACCR_IFG 0x000E0000 +#define ETH_MACCR_JD 0x00400000 +#define ETH_MACCR_WD 0x00800000 + +/* Ethernet MAC frame filter register ETH_MACFFR bits */ +#define ETH_MACFFR_PM 0x00000001 +#define ETH_MACFFR_HU 0x00000002 +#define ETH_MACFFR_HM 0x00000004 +#define ETH_MACFFR_DAIF 0x00000008 +#define ETH_MACFFR_PAM 0x00000010 +#define ETH_MACFFR_BFD 0x00000020 +#define ETH_MACFFR_PCF 0x000000C0 +#define ETH_MACFFR_SAIF 0x00000100 +#define ETH_MACFFR_SAF 0x00000200 +#define ETH_MACFFR_HPF 0x00000400 +#define ETH_MACFFR_PA 0x80000000 + +/* Ethernet MAC MII address register ETH_MACMIIAR bits */ +#define ETH_MACMIIAR_MB 0x0001 +#define ETH_MACMIIAR_MW 0x0002 +/* Clock Range for MDC frequency */ +#define ETH_MACMIIAR_CR_MASK 0x001C +#define ETH_MACMIIAR_CR_HCLK_DIV_42 0x0000 /* For HCLK 60-72 MHz */ +#define ETH_MACMIIAR_CR_HCLK_DIV_16 0x0008 /* For HCLK 20-35 MHz */ +#define ETH_MACMIIAR_CR_HCLK_DIV_24 0x000C /* For HCLK 35-60 MHz */ +#define ETH_MACMIIAR_MR 0x07C0 +#define ETH_MACMIIAR_PA 0xF800 + +/* Ethernet MAC flow control register ETH_MACFCR bits */ +#define ETH_MACFCR_FCB 0x00000001 +#define ETH_MACFCR_BPA 0x00000001 +#define ETH_MACFCR_TFCE 0x00000002 +#define ETH_MACFCR_RFCE 0x00000004 +#define ETH_MACFCR_UPFD 0x00000008 +#define ETH_MACFCR_PLT 0x00000030 +#define ETH_MACFCR_ZQPD 0x00000080 +#define ETH_MACFCR_PT 0xFFFF0000 + +/* Ethernet MAC interrupt status regster ETH_MACSR bits */ +#define ETH_MACSR_PMTS 0x0008 +#define ETH_MACSR_MMCS 0x0010 +#define ETH_MACSR_MMCRS 0x0020 +#define ETH_MACSR_MMCTS 0x0040 +#define ETH_MACSR_TSTS 0x0200 + +/* Ethernet MAC interrupt mask regster ETH_MACIMR bits */ +#define ETH_MACIMR_PMTIM 0x0008 +#define ETH_MACIMR_TSTIM 0x0200 + +/* Ethernet DMA Register bit definitions */ +/* Ethernet DMA bus mode register ETH_DMABMR bits */ +#define ETH_DMABMR_SR 0x00000001 +#define ETH_DMABMR_DA 0x00000002 +#define ETH_DMABMR_DSL_MASK 0x0000007C +#define ETH_DMABMR_PBL_MASK 0x00003F00 +#define ETH_DMABMR_RTPR_MASK 0x0000C000 +#define ETH_DMABMR_RTPR_1TO1 0x00000000 +#define ETH_DMABMR_RTPR_2TO1 0x00004000 +#define ETH_DMABMR_RTPR_3TO1 0x00008000 +#define ETH_DMABMR_RTPR_4TO1 0x0000C000 +#define ETH_DMABMR_FB 0x00010000 +#define ETH_DMABMR_RDP_MASK 0x007E0000 +#define ETH_DMABMR_USP 0x00800000 +#define ETH_DMABMR_FPM 0x01000000 +#define ETH_DMABMR_AAB 0x02000000 + +/* Ethernet DMA operation mode register ETH_DMAOMR bits */ +#define ETH_DMAOMR_SR 0x00000002 +#define ETH_DMAOMR_OSF 0x00000004 +#define ETH_DMAOMR_RTC_MASK 0x00000018 +#define ETH_DMAOMR_RTC_64 0x00000000 +#define ETH_DMAOMR_RTC_32 0x00000008 +#define ETH_DMAOMR_RTC_96 0x00000010 +#define ETH_DMAOMR_RTC_128 0x00000018 +#define ETH_DMAOMR_FUGF 0x00000040 +#define ETH_DMAOMR_FEF 0x00000080 +#define ETH_DMAOMR_ST 0x00002000 +#define ETH_DMAOMR_TTC_MASK 0x0001C000 +#define ETH_DMAOMR_FTF 0x00100000 +#define ETH_DMAOMR_TSF 0x00200000 +#define ETH_DMAOMR_DFRF 0x01000000 +#define ETH_DMAOMR_RSF 0x02000000 +#define ETH_DMAOMR_DTCEFD 0x04000000 + +/* Ethernet DMA interrupt enable register ETH_DMAIER bits */ +#define ETH_DMAIER_TIE 0x00000001 +#define ETH_DMAIER_TPSIE 0x00000002 +#define ETH_DMAIER_TBUIE 0x00000004 +#define ETH_DMAIER_TJTIE 0x00000008 +#define ETH_DMAIER_ROIE 0x00000010 +#define ETH_DMAIER_TUIE 0x00000020 +#define ETH_DMAIER_RIE 0x00000040 +#define ETH_DMAIER_RBUIE 0x00000080 +#define ETH_DMAIER_RPSIE 0x00000100 +#define ETH_DMAIER_RWTIE 0x00000200 +#define ETH_DMAIER_ETIE 0x00000400 +#define ETH_DMAIER_FBEIE 0x00002000 +#define ETH_DMAIER_ERIE 0x00004000 +#define ETH_DMAIER_AISE 0x00008000 +#define ETH_DMAIER_NSIE 0x00010000 + +#endif diff --git a/include/libopencm3/stm32/f1/flash.h b/include/libopencm3/stm32/f1/flash.h new file mode 100644 index 0000000..f9b2aa9 --- /dev/null +++ b/include/libopencm3/stm32/f1/flash.h @@ -0,0 +1,113 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * Copyright (C) 2010 Mark Butler + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* + * For details see: + * PM0042 Programming manual: STM32F10xxx Flash programming + * October 2009, Doc ID 13259 Rev 7 + * http://www.st.com/stonline/products/literature/pm/13259.pdf + */ + +#ifndef LIBOPENCM3_FLASH_H +#define LIBOPENCM3_FLASH_H + +#include +#include + +/* --- FLASH registers ----------------------------------------------------- */ + +#define FLASH_ACR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x00) +#define FLASH_KEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x04) +#define FLASH_OPTKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x08) +#define FLASH_SR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x0C) +#define FLASH_CR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x10) +#define FLASH_AR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14) +#define FLASH_OBR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x1C) +#define FLASH_WRPR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x20) + +/* --- FLASH_ACR values ---------------------------------------------------- */ + +#define FLASH_PRFTBS (1 << 5) +#define FLASH_PRFTBE (1 << 4) +#define FLASH_HLFCYA (1 << 3) +#define FLASH_LATENCY_0WS 0x00 +#define FLASH_LATENCY_1WS 0x01 +#define FLASH_LATENCY_2WS 0x02 + +/* --- FLASH_SR values ----------------------------------------------------- */ + +#define FLASH_EOP (1 << 5) +#define FLASH_WRPRTERR (1 << 4) +#define FLASH_PGERR (1 << 2) +#define FLASH_BSY (1 << 0) + +/* --- FLASH_CR values ----------------------------------------------------- */ + +#define FLASH_EOPIE (1 << 12) +#define FLASH_ERRIE (1 << 10) +#define FLASH_OPTWRE (1 << 9) +#define FLASH_LOCK (1 << 7) +#define FLASH_STRT (1 << 6) +#define FLASH_OPTER (1 << 5) +#define FLASH_OPTPG (1 << 4) +#define FLASH_MER (1 << 2) +#define FLASH_PER (1 << 1) +#define FLASH_PG (1 << 0) + +/* --- FLASH_OBR values ---------------------------------------------------- */ + +/* FLASH_OBR[25:18]: Data1 */ +/* FLASH_OBR[17:10]: Data0 */ +#define FLASH_NRST_STDBY (1 << 4) +#define FLASH_NRST_STOP (1 << 3) +#define FLASH_WDG_SW (1 << 2) +#define FLASH_RDPRT (1 << 1) +#define FLASH_OPTERR (1 << 0) + +/* --- FLASH Keys -----------------------------------------------------------*/ + +#define RDP_KEY ((u16)0x00a5) +#define FLASH_KEY1 ((u32)0x45670123) +#define FLASH_KEY2 ((u32)0xcdef89ab) + +/* --- Function prototypes ------------------------------------------------- */ + +void flash_prefetch_buffer_enable(void); +void flash_prefetch_buffer_disable(void); +void flash_halfcycle_enable(void); +void flash_halfcycle_disable(void); +void flash_set_ws(u32 ws); +void flash_unlock(void); +void flash_lock(void); +void flash_clear_pgerr_flag(void); +void flash_clear_eop_flag(void); +void flash_clear_wrprterr_flag(void); +void flash_clear_bsy_flag(void); +void flash_clear_status_flags(void); +void flash_unlock_option_bytes(void); +void flash_erase_all_pages(void); +void flash_erase_page(u32 page_address); +void flash_program_word(u32 address, u32 data); +void flash_program_half_word(u32 address, u16 data); +void flash_wait_for_last_operation(void); +void flash_erase_option_bytes(void); +void flash_program_option_bytes(u32 address, u16 data); + +#endif diff --git a/include/libopencm3/stm32/f1/gpio.h b/include/libopencm3/stm32/f1/gpio.h new file mode 100644 index 0000000..f1463a3 --- /dev/null +++ b/include/libopencm3/stm32/f1/gpio.h @@ -0,0 +1,555 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_GPIO_H +#define LIBOPENCM3_GPIO_H + +#include +#include + +/* --- Convenience macros -------------------------------------------------- */ + +/* GPIO port base addresses (for convenience) */ +#define GPIOA GPIO_PORT_A_BASE +#define GPIOB GPIO_PORT_B_BASE +#define GPIOC GPIO_PORT_C_BASE +#define GPIOD GPIO_PORT_D_BASE +#define GPIOE GPIO_PORT_E_BASE +#define GPIOF GPIO_PORT_F_BASE +#define GPIOG GPIO_PORT_G_BASE + +/* GPIO number definitions (for convenience) */ +#define GPIO0 (1 << 0) +#define GPIO1 (1 << 1) +#define GPIO2 (1 << 2) +#define GPIO3 (1 << 3) +#define GPIO4 (1 << 4) +#define GPIO5 (1 << 5) +#define GPIO6 (1 << 6) +#define GPIO7 (1 << 7) +#define GPIO8 (1 << 8) +#define GPIO9 (1 << 9) +#define GPIO10 (1 << 10) +#define GPIO11 (1 << 11) +#define GPIO12 (1 << 12) +#define GPIO13 (1 << 13) +#define GPIO14 (1 << 14) +#define GPIO15 (1 << 15) +#define GPIO_ALL 0xffff + +/* --- Alternate function GPIOs -------------------------------------------- */ + +/* Default alternate functions of some pins (with and without remapping) */ + +/* CAN1 / CAN */ +#define GPIO_CAN1_RX GPIO11 /* PA11 */ +#define GPIO_CAN1_TX GPIO12 /* PA12 */ +#define GPIO_CAN_RX GPIO_CAN1_RX /* Alias */ +#define GPIO_CAN_TX GPIO_CAN1_TX /* Alias */ + +#define GPIO_CAN_PB_RX GPIO8 /* PB8 */ +#define GPIO_CAN_PB_TX GPIO9 /* PB9 */ +#define GPIO_CAN1_PB_RX GPIO_CAN_PB_RX /* Alias */ +#define GPIO_CAN1_PB_TX GPIO_CAN_PB_TX /* Alias */ + +#define GPIO_CAN_PD_RX GPIO0 /* PD0 */ +#define GPIO_CAN_PD_TX GPIO1 /* PD1 */ +#define GPIO_CAN1_PD_RX GPIO_CAN_PD_RX /* Alias */ +#define GPIO_CAN1_PD_TX GPIO_CAN_PD_TX /* Alias */ + +/* CAN2 */ +#define GPIO_CAN2_RX GPIO12 /* PB12 */ +#define GPIO_CAN2_TX GPIO13 /* PB13 */ + +#define GPIO_CAN2_RE_RX GPIO5 /* PB5 */ +#define GPIO_CAN2_RE_TX GPIO6 /* PB6 */ + +/* JTAG/SWD */ +#define GPIO_JTMS_SWDIO GPIO13 /* PA13 */ +#define GPIO_JTCK_SWCLK GPIO14 /* PA14 */ +#define GPIO_JTDI GPIO15 /* PA15 */ +#define GPIO_JTDO_TRACESWO GPIO3 /* PB3 */ +#define GPIO_JNTRST GPIO4 /* PB4 */ +#define GPIO_TRACECK GPIO2 /* PE2 */ +#define GPIO_TRACED0 GPIO3 /* PE3 */ +#define GPIO_TRACED1 GPIO4 /* PE4 */ +#define GPIO_TRACED2 GPIO5 /* PE5 */ +#define GPIO_TRACED3 GPIO6 /* PE6 */ + +/* Timer5 */ +#define GPIO_TIM5_CH4 GPIO3 /* PA3 */ + +/* Timer4 */ +#define GPIO_TIM4_CH1 GPIO6 /* PB6 */ +#define GPIO_TIM4_CH2 GPIO7 /* PB7 */ +#define GPIO_TIM4_CH3 GPIO8 /* PB8 */ +#define GPIO_TIM4_CH4 GPIO9 /* PB9 */ + +#define GPIO_TIM4_RE_CH1 GPIO12 /* PD12 */ +#define GPIO_TIM4_RE_CH2 GPIO13 /* PD13 */ +#define GPIO_TIM4_RE_CH3 GPIO14 /* PD14 */ +#define GPIO_TIM4_RE_CH4 GPIO15 /* PD15 */ + +/* Timer3 */ +#define GPIO_TIM3_CH1 GPIO6 /* PA6 */ +#define GPIO_TIM3_CH2 GPIO7 /* PA7 */ +#define GPIO_TIM3_CH3 GPIO0 /* PB0 */ +#define GPIO_TIM3_CH4 GPIO1 /* PB1 */ + +#define GPIO_TIM3_PR_CH1 GPIO4 /* PB4 */ +#define GPIO_TIM3_PR_CH2 GPIO5 /* PB5 */ +#define GPIO_TIM3_PR_CH3 GPIO0 /* PB0 */ +#define GPIO_TIM3_PR_CH4 GPIO1 /* PB1 */ + +#define GPIO_TIM3_FR_CH1 GPIO6 /* PC6 */ +#define GPIO_TIM3_FR_CH2 GPIO7 /* PC7 */ +#define GPIO_TIM3_FR_CH3 GPIO8 /* PC8 */ +#define GPIO_TIM3_FR_CH4 GPIO9 /* PC9 */ + +/* Timer2 */ +#define GPIO_TIM2_CH1_ETR GPIO0 /* PA0 */ +#define GPIO_TIM2_CH2 GPIO1 /* PA1 */ +#define GPIO_TIM2_CH3 GPIO2 /* PA2 */ +#define GPIO_TIM2_CH4 GPIO3 /* PA3 */ + +#define GPIO_TIM2_PR1_CH1_ETR GPIO15 /* PA15 */ +#define GPIO_TIM2_PR1_CH2 GPIO3 /* PB3 */ +#define GPIO_TIM2_PR1_CH3 GPIO2 /* PA2 */ +#define GPIO_TIM2_PR1_CH4 GPIO3 /* PA3 */ + +#define GPIO_TIM2_PR2_CH1_ETR GPIO0 /* PA0 */ +#define GPIO_TIM2_PR2_CH2 GPIO1 /* PA1 */ +#define GPIO_TIM2_PR2_CH3 GPIO10 /* PB10 */ +#define GPIO_TIM2_PR2_CH4 GPIO11 /* PB11 */ + +#define GPIO_TIM2_FR_CH1_ETR GPIO15 /* PA15 */ +#define GPIO_TIM2_FR_CH2 GPIO3 /* PB3 */ +#define GPIO_TIM2_FR_CH3 GPIO10 /* PB10 */ +#define GPIO_TIM2_FR_CH4 GPIO11 /* PB11 */ + +/* Timer1 */ +#define GPIO_TIM1_ETR GPIO12 /* PA12 */ +#define GPIO_TIM1_CH1 GPIO8 /* PA8 */ +#define GPIO_TIM1_CH2 GPIO9 /* PA9 */ +#define GPIO_TIM1_CH3 GPIO10 /* PA10 */ +#define GPIO_TIM1_CH4 GPIO11 /* PA11 */ +#define GPIO_TIM1_BKIN GPIO12 /* PB12 */ +#define GPIO_TIM1_CH1N GPIO13 /* PB13 */ +#define GPIO_TIM1_CH2N GPIO14 /* PB14 */ +#define GPIO_TIM1_CH3N GPIO15 /* PB15 */ + +#define GPIO_TIM1_PR_ETR GPIO12 /* PA12 */ +#define GPIO_TIM1_PR_CH1 GPIO8 /* PA8 */ +#define GPIO_TIM1_PR_CH2 GPIO9 /* PA9 */ +#define GPIO_TIM1_PR_CH3 GPIO10 /* PA10 */ +#define GPIO_TIM1_PR_CH4 GPIO11 /* PA11 */ +#define GPIO_TIM1_PR_BKIN GPIO6 /* PA6 */ +#define GPIO_TIM1_PR_CH1N GPIO7 /* PA7 */ +#define GPIO_TIM1_PR_CH2N GPIO0 /* PB0 */ +#define GPIO_TIM1_PR_CH3N GPIO1 /* PB1 */ + +#define GPIO_TIM1_FR_ETR GPIO7 /* PE7 */ +#define GPIO_TIM1_FR_CH1 GPIO9 /* PE9 */ +#define GPIO_TIM1_FR_CH2 GPIO11 /* PE11 */ +#define GPIO_TIM1_FR_CH3 GPIO13 /* PE13 */ +#define GPIO_TIM1_FR_CH4 GPIO14 /* PE14 */ +#define GPIO_TIM1_FR_BKIN GPIO15 /* PE15 */ +#define GPIO_TIM1_FR_CH1N GPIO8 /* PE8 */ +#define GPIO_TIM1_FR_CH2N GPIO10 /* PE10 */ +#define GPIO_TIM1_FR_CH3N GPIO12 /* PE12 */ + +/* USART3 */ +#define GPIO_USART3_TX GPIO10 /* PB10 */ +#define GPIO_USART3_RX GPIO11 /* PB11 */ +#define GPIO_USART3_CK GPIO12 /* PB12 */ +#define GPIO_USART3_CTS GPIO13 /* PB13 */ +#define GPIO_USART3_RTS GPIO14 /* PB14 */ + +#define GPIO_USART3_PR_TX GPIO10 /* PC10 */ +#define GPIO_USART3_PR_RX GPIO11 /* PC11 */ +#define GPIO_USART3_PR_CK GPIO12 /* PC12 */ +#define GPIO_USART3_PR_CTS GPIO13 /* PB13 */ +#define GPIO_USART3_PR_RTS GPIO14 /* PB14 */ + +#define GPIO_USART3_FR_TX GPIO8 /* PD8 */ +#define GPIO_USART3_FR_RX GPIO9 /* PD9 */ +#define GPIO_USART3_FR_CK GPIO10 /* PD10 */ +#define GPIO_USART3_FR_CTS GPIO11 /* PD11 */ +#define GPIO_USART3_FR_RTS GPIO12 /* PD12 */ + +/* USART2 */ +#define GPIO_USART2_CTS GPIO0 /* PA0 */ +#define GPIO_USART2_RTS GPIO1 /* PA1 */ +#define GPIO_USART2_TX GPIO2 /* PA2 */ +#define GPIO_USART2_RX GPIO3 /* PA3 */ +#define GPIO_USART2_CK GPIO4 /* PA4 */ + +#define GPIO_USART2_RE_CTS GPIO3 /* PD3 */ +#define GPIO_USART2_RE_RTS GPIO4 /* PD4 */ +#define GPIO_USART2_RE_TX GPIO5 /* PD5 */ +#define GPIO_USART2_RE_RX GPIO6 /* PD6 */ +#define GPIO_USART2_RE_CK GPIO7 /* PD7 */ + +/* USART1 */ +#define GPIO_USART1_TX GPIO9 /* PA9 */ +#define GPIO_USART1_RX GPIO10 /* PA10 */ + +#define GPIO_USART1_RE_TX GPIO6 /* PB6 */ +#define GPIO_USART1_RE_RX GPIO7 /* PB7 */ + +/* I2C1 */ +#define GPIO_I2C1_SMBAI GPIO5 /* PB5 */ +#define GPIO_I2C1_SCL GPIO6 /* PB6 */ +#define GPIO_I2C1_SDA GPIO7 /* PB7 */ + +#define GPIO_I2C1_RE_SMBAI GPIO5 /* PB5 */ +#define GPIO_I2C1_RE_SCL GPIO8 /* PB8 */ +#define GPIO_I2C1_RE_SDA GPIO9 /* PB9 */ + +/* I2C2 */ +#define GPIO_I2C2_SCL GPIO10 /* PB10 */ +#define GPIO_I2C2_SDA GPIO11 /* PB11 */ +#define GPIO_I2C2_SMBAI GPIO12 /* PB12 */ + +/* SPI1 */ +#define GPIO_SPI1_NSS GPIO4 /* PA4 */ +#define GPIO_SPI1_SCK GPIO5 /* PA5 */ +#define GPIO_SPI1_MISO GPIO6 /* PA6 */ +#define GPIO_SPI1_MOSI GPIO7 /* PA7 */ + +#define GPIO_SPI1_RE_NSS GPIO15 /* PA15 */ +#define GPIO_SPI1_RE_SCK GPIO3 /* PB3 */ +#define GPIO_SPI1_RE_MISO GPIO4 /* PB4 */ +#define GPIO_SPI1_RE_MOSI GPIO5 /* PB5 */ + +/* SPI2 */ +#define GPIO_SPI2_NSS GPIO12 /* PB12 */ +#define GPIO_SPI2_SCK GPIO13 /* PB13 */ +#define GPIO_SPI2_MISO GPIO14 /* PB14 */ +#define GPIO_SPI2_MOSI GPIO15 /* PB15 */ + +/* SPI3 */ +#define GPIO_SPI3_NSS GPIO15 /* PA15 */ +#define GPIO_SPI3_SCK GPIO3 /* PB3 */ +#define GPIO_SPI3_MISO GPIO4 /* PB4 */ +#define GPIO_SPI3_MOSI GPIO5 /* PB5 */ + +#define GPIO_SPI3_RE_NSS GPIO4 /* PA4 */ +#define GPIO_SPI3_RE_SCK GPIO10 /* PC10 */ +#define GPIO_SPI3_RE_MISO GPIO11 /* PC11 */ +#define GPIO_SPI3_RE_MOSI GPIO12 /* PC12 */ + +/* ETH */ +#define GPIO_ETH_RX_DV_CRS_DV GPIO7 /* PA7 */ +#define GPIO_ETH_RXD0 GPIO4 /* PC4 */ +#define GPIO_ETH_RXD1 GPIO5 /* PC5 */ +#define GPIO_ETH_RXD2 GPIO0 /* PB0 */ +#define GPIO_ETH_RXD3 GPIO1 /* PB1 */ + +#define GPIO_ETH_RE_RX_DV_CRS_DV GPIO8 /* PD8 */ +#define GPIO_ETH_RE_RXD0 GPIO9 /* PD9 */ +#define GPIO_ETH_RE_RXD1 GPIO10 /* PD10 */ +#define GPIO_ETH_RE_RXD2 GPIO11 /* PD11 */ +#define GPIO_ETH_RE_RXD3 GPIO12 /* PD12 */ + +/* --- GPIO registers ------------------------------------------------------ */ + +/* Port configuration register low (GPIOx_CRL) */ +#define GPIO_CRL(port) MMIO32(port + 0x00) +#define GPIOA_CRL GPIO_CRL(GPIOA) +#define GPIOB_CRL GPIO_CRL(GPIOB) +#define GPIOC_CRL GPIO_CRL(GPIOC) +#define GPIOD_CRL GPIO_CRL(GPIOD) +#define GPIOE_CRL GPIO_CRL(GPIOE) +#define GPIOF_CRL GPIO_CRL(GPIOF) +#define GPIOG_CRL GPIO_CRL(GPIOG) + +/* Port configuration register low (GPIOx_CRH) */ +#define GPIO_CRH(port) MMIO32(port + 0x04) +#define GPIOA_CRH GPIO_CRH(GPIOA) +#define GPIOB_CRH GPIO_CRH(GPIOB) +#define GPIOC_CRH GPIO_CRH(GPIOC) +#define GPIOD_CRH GPIO_CRH(GPIOD) +#define GPIOE_CRH GPIO_CRH(GPIOE) +#define GPIOF_CRH GPIO_CRH(GPIOF) +#define GPIOG_CRH GPIO_CRH(GPIOG) + +/* Port input data register (GPIOx_IDR) */ +#define GPIO_IDR(port) MMIO32(port + 0x08) +#define GPIOA_IDR GPIO_IDR(GPIOA) +#define GPIOB_IDR GPIO_IDR(GPIOB) +#define GPIOC_IDR GPIO_IDR(GPIOC) +#define GPIOD_IDR GPIO_IDR(GPIOD) +#define GPIOE_IDR GPIO_IDR(GPIOE) +#define GPIOF_IDR GPIO_IDR(GPIOF) +#define GPIOG_IDR GPIO_IDR(GPIOG) + +/* Port output data register (GPIOx_ODR) */ +#define GPIO_ODR(port) MMIO32(port + 0x0c) +#define GPIOA_ODR GPIO_ODR(GPIOA) +#define GPIOB_ODR GPIO_ODR(GPIOB) +#define GPIOC_ODR GPIO_ODR(GPIOC) +#define GPIOD_ODR GPIO_ODR(GPIOD) +#define GPIOE_ODR GPIO_ODR(GPIOE) +#define GPIOF_ODR GPIO_ODR(GPIOF) +#define GPIOG_ODR GPIO_ODR(GPIOG) + +/* Port bit set/reset register (GPIOx_BSRR) */ +#define GPIO_BSRR(port) MMIO32(port + 0x10) +#define GPIOA_BSRR GPIO_BSRR(GPIOA) +#define GPIOB_BSRR GPIO_BSRR(GPIOB) +#define GPIOC_BSRR GPIO_BSRR(GPIOC) +#define GPIOD_BSRR GPIO_BSRR(GPIOD) +#define GPIOE_BSRR GPIO_BSRR(GPIOE) +#define GPIOF_BSRR GPIO_BSRR(GPIOF) +#define GPIOG_BSRR GPIO_BSRR(GPIOG) + +/* Port bit reset register (GPIOx_BRR) */ +#define GPIO_BRR(port) MMIO16(port + 0x14) +#define GPIOA_BRR GPIO_BRR(GPIOA) +#define GPIOB_BRR GPIO_BRR(GPIOB) +#define GPIOC_BRR GPIO_BRR(GPIOC) +#define GPIOD_BRR GPIO_BRR(GPIOD) +#define GPIOE_BRR GPIO_BRR(GPIOE) +#define GPIOF_BRR GPIO_BRR(GPIOF) +#define GPIOG_BRR GPIO_BRR(GPIOG) + +/* Port configuration lock register (GPIOx_LCKR) */ +#define GPIO_LCKR(port) MMIO32(port + 0x18) +#define GPIOA_LCKR GPIO_LCKR(GPIOA) +#define GPIOB_LCKR GPIO_LCKR(GPIOB) +#define GPIOC_LCKR GPIO_LCKR(GPIOC) +#define GPIOD_LCKR GPIO_LCKR(GPIOD) +#define GPIOE_LCKR GPIO_LCKR(GPIOE) +#define GPIOF_LCKR GPIO_LCKR(GPIOF) +#define GPIOG_LCKR GPIO_LCKR(GPIOG) + +/* --- GPIO_CRL/GPIO_CRH values -------------------------------------------- */ + +/* CNF[1:0] values when MODE[1:0] is 00 (input mode) */ +#define GPIO_CNF_INPUT_ANALOG 0x00 +#define GPIO_CNF_INPUT_FLOAT 0x01 /* Default */ +#define GPIO_CNF_INPUT_PULL_UPDOWN 0x02 + +/* Output mode (MODE[1:0]) values */ +#define GPIO_MODE_INPUT 0x00 /* Default */ +#define GPIO_MODE_OUTPUT_10_MHZ 0x01 +#define GPIO_MODE_OUTPUT_2_MHZ 0x02 +#define GPIO_MODE_OUTPUT_50_MHZ 0x03 + +/* CNF[1:0] values when MODE[1:0] is != 00 (one of the output modes) */ +#define GPIO_CNF_OUTPUT_PUSHPULL 0x00 +#define GPIO_CNF_OUTPUT_OPENDRAIN 0x01 +#define GPIO_CNF_OUTPUT_ALTFN_PUSHPULL 0x02 +#define GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN 0x03 + +/* --- GPIO_IDR values ----------------------------------------------------- */ + +/* GPIO_IDR[15:0]: IDRy[15:0]: Port input data (y = 0..15) */ + +/* --- GPIO_ODR values ----------------------------------------------------- */ + +/* GPIO_ODR[15:0]: ODRy[15:0]: Port output data (y = 0..15) */ + +/* --- GPIO_BSRR values ---------------------------------------------------- */ + +/* GPIO_BSRR[31:16]: BRy: Port x reset bit y (y = 0..15) */ +/* GPIO_BSRR[15:0]: BSy: Port x set bit y (y = 0..15) */ + +/* --- GPIO_BRR values ----------------------------------------------------- */ + +/* GPIO_BRR[15:0]: BRy: Port x reset bit y (y = 0..15) */ + +/* --- GPIO_LCKR values ---------------------------------------------------- */ + +#define GPIO_LCKK (1 << 16) +/* GPIO_LCKR[15:0]: LCKy: Port x lock bit y (y = 0..15) */ + +/* --- AFIO registers ------------------------------------------------------ */ + +/* Event control register (AFIO_EVCR) */ +#define AFIO_EVCR MMIO32(AFIO_BASE + 0x00) + +/* AF remap and debug I/O configuration register (AFIO_MAPR) */ +#define AFIO_MAPR MMIO32(AFIO_BASE + 0x04) + +/* External interrupt configuration register 1 (AFIO_EXTICR1) */ +#define AFIO_EXTICR1 MMIO32(AFIO_BASE + 0x08) + +/* External interrupt configuration register 2 (AFIO_EXTICR2) */ +#define AFIO_EXTICR2 MMIO32(AFIO_BASE + 0x0c) + +/* External interrupt configuration register 3 (AFIO_EXTICR3) */ +#define AFIO_EXTICR3 MMIO32(AFIO_BASE + 0x10) + +/* External interrupt configuration register 4 (AFIO_EXTICR4) */ +#define AFIO_EXTICR4 MMIO32(AFIO_BASE + 0x14) + +/* --- AFIO_EVCR values ---------------------------------------------------- */ + +/* EVOE: Event output enable */ +#define AFIO_EVCR_EVOE (1 << 7) + +/* PORT[2:0]: Port selection */ +#define AFIO_EVCR_PORT_PA (0x0 << 4) +#define AFIO_EVCR_PORT_PB (0x1 << 4) +#define AFIO_EVCR_PORT_PC (0x2 << 4) +#define AFIO_EVCR_PORT_PD (0x3 << 4) +#define AFIO_EVCR_PORT_PE (0x4 << 4) + +/* PIN[3:0]: Pin selection */ +#define AFIO_EVCR_PIN_Px0 (0x0 << 0) +#define AFIO_EVCR_PIN_Px1 (0x1 << 0) +#define AFIO_EVCR_PIN_Px2 (0x2 << 0) +#define AFIO_EVCR_PIN_Px3 (0x3 << 0) +#define AFIO_EVCR_PIN_Px4 (0x4 << 0) +#define AFIO_EVCR_PIN_Px5 (0x5 << 0) +#define AFIO_EVCR_PIN_Px6 (0x6 << 0) +#define AFIO_EVCR_PIN_Px7 (0x7 << 0) +#define AFIO_EVCR_PIN_Px8 (0x8 << 0) +#define AFIO_EVCR_PIN_Px9 (0x9 << 0) +#define AFIO_EVCR_PIN_Px10 (0xA << 0) +#define AFIO_EVCR_PIN_Px11 (0xB << 0) +#define AFIO_EVCR_PIN_Px12 (0xC << 0) +#define AFIO_EVCR_PIN_Px13 (0xD << 0) +#define AFIO_EVCR_PIN_Px14 (0xE << 0) +#define AFIO_EVCR_PIN_Px15 (0xF << 0) + +/* --- AFIO_MAPR values ---------------------------------------------------- */ + +/* 31 reserved */ + +/* PTP_PPS_REMAP: Ethernet PTP PPS remapping + * (only connectivity line devices) */ +#define AFIO_MAPR_PTP_PPS_REMAP (1 << 30) + +/* TIM2ITR1_IREMAP: TIM2 internal trigger 1 remapping + * (only connectivity line devices) */ +#define AFIO_MAPR_TIM2ITR1_IREMAP (1 << 29) + +/* SPI3_REMAP: SPI3/I2S3 remapping + * (only connectivity line devices) */ +#define AFIO_MAPR_SPI3_REMAP (1 << 28) + +/* 27 reserved */ + +/* SWJ_CFG[2:0]: Serial wire JTAG configuration */ +#define AFIO_MAPR_SWJ_CFG_FULL_SWJ (0x0 << 24) +#define AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_JNTRST (0x1 << 24) +#define AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_ON (0x2 << 24) +#define AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_OFF (0x4 << 24) + +/* MII_REMAP: MII or RMII selection + * (only connectivity line devices) */ +#define AFIO_MAPR_MII_RMII_SEL (1 << 23) + +/* CAN2_REMAP: CAN2 I/O remapping + * (only connectivity line devices) */ +#define AFIO_MAPR_CAN2_REMAP (1 << 22) + +/* ETH_REMAP: Ethernet MAC I/O remapping + * (only connectivity line devices) */ +#define AFIO_MAPR_ETH_REMAP (1 << 21) + +/* ADC2_ETRGREG_REMAP: ADC2 external trigger regulator conversion remapping + * (only low-, medium-, high- and XL-densitiy devices) */ +#define AFIO_MAPR_ADC2_ETRGREG_REMAP (1 << 20) + +/* ADC2_ETRGINJ_REMAP: ADC2 external trigger injected conversion remapping + * (only low-, medium-, high- and XL-densitiy devices) */ +#define AFIO_MAPR_ADC2_ETRGINJ_REMAP (1 << 19) + +/* ADC1_ETRGREG_REMAP: ADC1 external trigger regulator conversion remapping + * (only low-, medium-, high- and XL-densitiy devices) */ +#define AFIO_MAPR_ADC1_ETRGREG_REMAP (1 << 18) + +/* ADC1_ETRGINJ_REMAP: ADC1 external trigger injected conversion remapping + * (only low-, medium-, high- and XL-densitiy devices) */ +#define AFIO_MAPR_ADC1_ETRGINJ_REMAP (1 << 17) + +/* TIM5CH4_IREMAP: TIM5 channel4 internal remap */ +#define AFIO_MAPR_TIM5CH4_IREMAP (1 << 16) + +/* PD01_REMAP: Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ +#define AFIO_MAPR_PD01_REMAP (1 << 15) + +/* CAN_REMAP[1:0]: CAN1 alternate function remapping */ +#define AFIO_MAPR_CAN1_REMAP_PORTA (0x0 << 13) +#define AFIO_MAPR_CAN1_REMAP_PORTB (0x2 << 13) /* Not on 36pin pkg */ +#define AFIO_MAPR_CAN1_REMAP_PORTD (0x3 << 13) + +/* TIM4_REMAP: TIM4 remapping */ +#define AFIO_MAPR_TIM4_REMAP (1 << 12) + +/* TIM3_REMAP[1:0]: TIM3 remapping */ +#define AFIO_MAPR_TIM3_REMAP_NO_REMAP (0x0 << 10) +#define AFIO_MAPR_TIM3_REMAP_PARTIAL_REMAP (0x2 << 10) +#define AFIO_MAPR_TIM3_REMAP_FULL_REMAP (0x3 << 10) + +/* TIM2_REMAP[1:0]: TIM2 remapping */ +#define AFIO_MAPR_TIM2_REMAP_NO_REMAP (0x0 << 8) +#define AFIO_MAPR_TIM2_REMAP_PARTIAL_REMAP1 (0x1 << 8) +#define AFIO_MAPR_TIM2_REMAP_PARTIAL_REMAP2 (0x2 << 8) +#define AFIO_MAPR_TIM2_REMAP_FULL_REMAP (0x3 << 8) + +/* TIM1_REMAP[1:0]: TIM1 remapping */ +#define AFIO_MAPR_TIM1_REMAP_NO_REMAP (0x0 << 6) +#define AFIO_MAPR_TIM1_REMAP_PARTIAL_REMAP (0x1 << 6) +#define AFIO_MAPR_TIM1_REMAP_FULL_REMAP (0x3 << 6) + +/* USART3_REMAP[1:0]: USART3 remapping */ +#define AFIO_MAPR_USART3_REMAP_NO_REMAP (0x0 << 4) +#define AFIO_MAPR_USART3_REMAP_PARTIAL_REMAP (0x1 << 4) +#define AFIO_MAPR_USART3_REMAP_FULL_REMAP (0x3 << 4) + +/* USART2_REMAP[1:0]: USART2 remapping */ +#define AFIO_MAPR_USART2_REMAP (1 << 3) + +/* USART1_REMAP[1:0]: USART1 remapping */ +#define AFIO_MAPR_USART1_REMAP (1 << 2) + +/* I2C1_REMAP[1:0]: I2C1 remapping */ +#define AFIO_MAPR_I2C1_REMAP (1 << 1) + +/* SPI1_REMAP[1:0]: SPI1 remapping */ +#define AFIO_MAPR_SPI1_REMAP (1 << 0) + +/* --- AFIO_EXTICR1 values ------------------------------------------------- */ +/* --- AFIO_EXTICR2 values ------------------------------------------------- */ +/* --- AFIO_EXTICR3 values ------------------------------------------------- */ +/* --- AFIO_EXTICR4 values ------------------------------------------------- */ + +/* EXTI0 - EXTI15 interrupt source selection registers */ + +/* Note: For using them we should define a function that calculates the right + * registers, using definitions is probably not a good idea. + */ + +/* --- Function prototypes ------------------------------------------------- */ + +void gpio_set_mode(u32 gpioport, u8 mode, u8 cnf, u16 gpios); +void gpio_set(u32 gpioport, u16 gpios); +void gpio_clear(u32 gpioport, u16 gpios); +u16 gpio_get(u32 gpioport, u16 gpios); +void gpio_toggle(u32 gpioport, u16 gpios); +u16 gpio_port_read(u32 gpioport); +void gpio_port_write(u32 gpioport, u16 data); +void gpio_port_config_lock(u32 gpioport, u16 gpios); + +#endif diff --git a/include/libopencm3/stm32/f1/memorymap.h b/include/libopencm3/stm32/f1/memorymap.h new file mode 100644 index 0000000..e3c57c8 --- /dev/null +++ b/include/libopencm3/stm32/f1/memorymap.h @@ -0,0 +1,113 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_MEMORYMAP_H +#define LIBOPENCM3_MEMORYMAP_H + +#include + +/* --- STM32 specific peripheral definitions ------------------------------- */ + +/* Memory map for all busses */ +#define PERIPH_BASE 0x40000000 +#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000) +#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000) +#define PERIPH_BASE_AHB (PERIPH_BASE + 0x18000) + +/* Register boundary addresses */ + +/* APB1 */ +#define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000) +#define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400) +#define TIM4_BASE (PERIPH_BASE_APB1 + 0x0800) +#define TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00) +#define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000) +#define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400) +#define TIM12_BASE (PERIPH_BASE_APB1 + 0x1800) +#define TIM13_BASE (PERIPH_BASE_APB1 + 0x1c00) +#define TIM14_BASE (PERIPH_BASE_APB1 + 0x2000) +/* PERIPH_BASE_APB1 + 0x2400 (0x4000 2400 - 0x4000 27FF): Reserved */ +#define RTC_BASE (PERIPH_BASE_APB1 + 0x2800) +#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00) +#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000) +/* PERIPH_BASE_APB1 + 0x3400 (0x4000 3400 - 0x4000 37FF): Reserved */ +#define SPI2_I2S_BASE (PERIPH_BASE_APB1 + 0x3800) +#define SPI3_I2S_BASE (PERIPH_BASE_APB1 + 0x3c00) +/* PERIPH_BASE_APB1 + 0x4000 (0x4000 4000 - 0x4000 3FFF): Reserved */ +#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400) +#define USART3_BASE (PERIPH_BASE_APB1 + 0x4800) +#define UART4_BASE (PERIPH_BASE_APB1 + 0x4c00) +#define UART5_BASE (PERIPH_BASE_APB1 + 0x5000) +#define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400) +#define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800) +#define USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x5c00) +#define USB_CAN_SRAM_BASE (PERIPH_BASE_APB1 + 0x6000) +#define BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400) +#define BX_CAN2_BASE (PERIPH_BASE_APB1 + 0x6800) +/* PERIPH_BASE_APB1 + 0x6800 (0x4000 6800 - 0x4000 6BFF): Reserved? Typo? */ +#define BACKUP_REGS_BASE (PERIPH_BASE_APB1 + 0x6c00) +#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000) +#define DAC_BASE (PERIPH_BASE_APB1 + 0x7400) +/* PERIPH_BASE_APB1 + 0x7800 (0x4000 7800 - 0x4000 FFFF): Reserved */ + +/* APB2 */ +#define AFIO_BASE (PERIPH_BASE_APB2 + 0x0000) +#define EXTI_BASE (PERIPH_BASE_APB2 + 0x0400) +#define GPIO_PORT_A_BASE (PERIPH_BASE_APB2 + 0x0800) +#define GPIO_PORT_B_BASE (PERIPH_BASE_APB2 + 0x0c00) +#define GPIO_PORT_C_BASE (PERIPH_BASE_APB2 + 0x1000) +#define GPIO_PORT_D_BASE (PERIPH_BASE_APB2 + 0x1400) +#define GPIO_PORT_E_BASE (PERIPH_BASE_APB2 + 0x1800) +#define GPIO_PORT_F_BASE (PERIPH_BASE_APB2 + 0x1c00) +#define GPIO_PORT_G_BASE (PERIPH_BASE_APB2 + 0x2000) +#define ADC1_BASE (PERIPH_BASE_APB2 + 0x2400) +#define ADC2_BASE (PERIPH_BASE_APB2 + 0x2800) +#define TIM1_BASE (PERIPH_BASE_APB2 + 0x2c00) +#define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000) +#define TIM8_BASE (PERIPH_BASE_APB2 + 0x3400) +#define USART1_BASE (PERIPH_BASE_APB2 + 0x3800) +#define ADC3_BASE (PERIPH_BASE_APB2 + 0x3c00) +/* PERIPH_BASE_APB2 + 0x4000 (0x4001 4000 - 0x4001 4FFF): Reserved */ +#define TIM9_BASE (PERIPH_BASE_APB2 + 0x4c00) +#define TIM10_BASE (PERIPH_BASE_APB2 + 0x5000) +#define TIM11_BASE (PERIPH_BASE_APB2 + 0x5400) +/* PERIPH_BASE_APB2 + 0x5800 (0x4001 5800 - 0x4001 7FFF): Reserved */ + +/* AHB */ +#define SDIO_BASE (PERIPH_BASE_AHB + 0x00000) +/* PERIPH_BASE_AHB + 0x0400 (0x4001 8400 - 0x4001 7FFF): Reserved */ +#define DMA1_BASE (PERIPH_BASE_AHB + 0x08000) +#define DMA2_BASE (PERIPH_BASE_AHB + 0x08400) +/* PERIPH_BASE_AHB + 0x8800 (0x4002 0800 - 0x4002 0FFF): Reserved */ +#define RCC_BASE (PERIPH_BASE_AHB + 0x09000) +/* PERIPH_BASE_AHB + 0x9400 (0x4002 1400 - 0x4002 1FFF): Reserved */ +#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB + 0x0a000) +#define CRC_BASE (PERIPH_BASE_AHB + 0x0b000) +/* PERIPH_BASE_AHB + 0xb400 (0x4002 3400 - 0x4002 7FFF): Reserved */ +#define ETHERNET_BASE (PERIPH_BASE_AHB + 0x10000) +/* PERIPH_BASE_AHB + 0x18000 (0x4003 0000 - 0x4FFF FFFF): Reserved */ +#define USB_OTG_FS_BASE (PERIPH_BASE_AHB + 0xffe8000) + +/* PPIB */ +#define DBGMCU_BASE (PPBI_BASE + 0x00042000) + +/* FSMC */ +#define FSMC_BASE (PERIPH_BASE + 0x60000000) + +#endif diff --git a/include/libopencm3/stm32/f1/nvic.h b/include/libopencm3/stm32/f1/nvic.h new file mode 100644 index 0000000..d29c425 --- /dev/null +++ b/include/libopencm3/stm32/f1/nvic.h @@ -0,0 +1,162 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Piotr Esden-Tempski + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_NVIC_H +#define LIBOPENCM3_NVIC_H + +#include +#include + +/* --- NVIC Registers ------------------------------------------------------ */ + +/* ISER: Interrupt Set Enable Registers */ +/* Note: 8 32bit Registers */ +#define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + (iser_id * 4)) + +/* NVIC_BASE + 0x020 (0xE000 E120 - 0xE000 E17F): Reserved */ + +/* ICER: Interrupt Clear Enable Registers */ +/* Note: 8 32bit Registers */ +#define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + (icer_id * 4)) + +/* NVIC_BASE + 0x0A0 (0xE000 E1A0 - 0xE000 E1FF): Reserved */ + +/* ISPR: Interrupt Set Pending Registers */ +/* Note: 8 32bit Registers */ +#define NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + (ispr_id * 4)) + +/* NVIC_BASE + 0x120 (0xE000 E220 - 0xE000 E27F): Reserved */ + +/* ICPR: Interrupt Clear Pending Registers */ +/* Note: 8 32bit Registers */ +#define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + (icpr_id * 4)) + +/* NVIC_BASE + 0x1A0 (0xE000 E2A0 - 0xE00 E2FF): Reserved */ + +/* IABR: Interrupt Active Bit Register */ +/* Note: 8 32bit Registers */ +#define NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + (iabr_id * 4)) + +/* NVIC_BASE + 0x220 (0xE000 E320 - 0xE000 E3FF): Reserved */ + +/* IPR: Interrupt Priority Registers */ +/* Note: 240 8bit Registers */ +#define NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + ipr_id) + +/* STIR: Software Trigger Interrupt Register */ +#define NVIC_STIR MMIO32(STIR_BASE) + +/* --- IRQ channel numbers-------------------------------------------------- */ + +/* Cortex M3 System Interrupts */ +#define NVIC_NMI_IRQ -14 +#define NVIC_HARD_FAULT_IRQ -13 +#define NVIC_MEM_MANAGE_IRQ -12 +#define NVIC_BUS_FAULT_IRQ -11 +#define NVIC_USAGE_FAULT_IRQ -10 +/* irq numbers -6 to -9 are reserved */ +#define NVIC_SV_CALL_IRQ -5 +#define DEBUG_MONITOR_IRQ -4 +/* irq number -3 reserved */ +#define NVIC_PENDSV_IRQ -2 +#define NVIC_SYSTICK_IRQ -1 + +/* User Interrupts */ +#define NVIC_WWDG_IRQ 0 +#define NVIC_PVD_IRQ 1 +#define NVIC_TAMPER_IRQ 2 +#define NVIC_RTC_IRQ 3 +#define NVIC_FLASH_IRQ 4 +#define NVIC_RCC_IRQ 5 +#define NVIC_EXTI0_IRQ 6 +#define NVIC_EXTI1_IRQ 7 +#define NVIC_EXTI2_IRQ 8 +#define NVIC_EXTI3_IRQ 9 +#define NVIC_EXTI4_IRQ 10 +#define NVIC_DMA1_CHANNEL1_IRQ 11 +#define NVIC_DMA1_CHANNEL2_IRQ 12 +#define NVIC_DMA1_CHANNEL3_IRQ 13 +#define NVIC_DMA1_CHANNEL4_IRQ 14 +#define NVIC_DMA1_CHANNEL5_IRQ 15 +#define NVIC_DMA1_CHANNEL6_IRQ 16 +#define NVIC_DMA1_CHANNEL7_IRQ 17 +#define NVIC_ADC1_2_IRQ 18 +#define NVIC_USB_HP_CAN_TX_IRQ 19 +#define NVIC_USB_LP_CAN_RX0_IRQ 20 +#define NVIC_CAN_RX1_IRQ 21 +#define NVIC_CAN_SCE_IRQ 22 +#define NVIC_EXTI9_5_IRQ 23 +#define NVIC_TIM1_BRK_IRQ 24 +#define NVIC_TIM1_UP_IRQ 25 +#define NVIC_TIM1_TRG_COM_IRQ 26 +#define NVIC_TIM1_CC_IRQ 27 +#define NVIC_TIM2_IRQ 28 +#define NVIC_TIM3_IRQ 29 +#define NVIC_TIM4_IRQ 30 +#define NVIC_I2C1_EV_IRQ 31 +#define NVIC_I2C1_ER_IRQ 32 +#define NVIC_I2C2_EV_IRQ 33 +#define NVIC_I2C2_ER_IRQ 34 +#define NVIC_SPI1_IRQ 35 +#define NVIC_SPI2_IRQ 36 +#define NVIC_USART1_IRQ 37 +#define NVIC_USART2_IRQ 38 +#define NVIC_USART3_IRQ 39 +#define NVIC_EXTI15_10_IRQ 40 +#define NVIC_RTC_ALARM_IRQ 41 +#define NVIC_USB_WAKEUP_IRQ 42 +#define NVIC_TIM8_BRK_IRQ 43 +#define NVIC_TIM8_UP_IRQ 44 +#define NVIC_TIM8_TRG_COM_IRQ 45 +#define NVIC_TIM8_CC_IRQ 46 +#define NVIC_ADC3_IRQ 47 +#define NVIC_FSMC_IRQ 48 +#define NVIC_SDIO_IRQ 49 +#define NVIC_TIM5_IRQ 50 +#define NVIC_SPI3_IRQ 51 +#define NVIC_USART4_IRQ 52 +#define NVIC_USART5_IRQ 53 +#define NVIC_TIM6_IRQ 54 +#define NVIC_TIM7_IRQ 55 +#define NVIC_DMA2_CHANNEL1_IRQ 56 +#define NVIC_DMA2_CHANNEL2_IRQ 57 +#define NVIC_DMA2_CHANNEL3_IRQ 58 +#define NVIC_DMA2_CHANNEL4_5_IRQ 59 +#define NVIC_DMA2_CHANNEL5_IRQ 60 +#define NVIC_ETH_IRQ 61 +#define NVIC_ETH_WKUP_IRQ 62 +#define NVIC_CAN2_TX_IRQ 63 +#define NVIC_CAN2_RX0_IRQ 64 +#define NVIC_CAN2_RX1_IRQ 65 +#define NVIC_CAN2_SCE_IRQ 66 +#define NVIC_OTG_FS_IRQ 67 + +/* --- NVIC functions ------------------------------------------------------ */ + +void nvic_enable_irq(u8 irqn); +void nvic_disable_irq(u8 irqn); +u8 nvic_get_pending_irq(u8 irqn); +void nvic_set_pending_irq(u8 irqn); +void nvic_clear_pending_irq(u8 irqn); +u8 nvic_get_active_irq(u8 irqn); +u8 nvic_get_irq_enabled(u8 irqn); +void nvic_set_priority(u8 irqn, u8 priority); +void nvic_generate_software_interrupt(u8 irqn); + +#endif diff --git a/include/libopencm3/stm32/f1/otg_fs.h b/include/libopencm3/stm32/f1/otg_fs.h new file mode 100644 index 0000000..e1d7a6a --- /dev/null +++ b/include/libopencm3/stm32/f1/otg_fs.h @@ -0,0 +1,324 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Gareth McMullin + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_OTG_FS_H +#define LIBOPENCM3_OTG_FS_H + +#include +#include + +/* Core Global Control and Status Registers */ +#define OTG_FS_OTGCTL MMIO32(USB_OTG_FS_BASE + 0x000) +#define OTG_FS_GOTGINT MMIO32(USB_OTG_FS_BASE + 0x004) +#define OTG_FS_GAHBCFG MMIO32(USB_OTG_FS_BASE + 0x008) +#define OTG_FS_GUSBCFG MMIO32(USB_OTG_FS_BASE + 0x00C) +#define OTG_FS_GRSTCTL MMIO32(USB_OTG_FS_BASE + 0x010) +#define OTG_FS_GINTSTS MMIO32(USB_OTG_FS_BASE + 0x014) +#define OTG_FS_GINTMSK MMIO32(USB_OTG_FS_BASE + 0x018) +#define OTG_FS_GRXSTSR MMIO32(USB_OTG_FS_BASE + 0x01C) +#define OTG_FS_GRXSTSP MMIO32(USB_OTG_FS_BASE + 0x020) +#define OTG_FS_GRXFSIZ MMIO32(USB_OTG_FS_BASE + 0x024) +#define OTG_FS_GNPTXFSIZ MMIO32(USB_OTG_FS_BASE + 0x028) +#define OTG_FS_GNPTXSTS MMIO32(USB_OTG_FS_BASE + 0x02C) +#define OTG_FS_GCCFG MMIO32(USB_OTG_FS_BASE + 0x038) +#define OTG_FS_CID MMIO32(USB_OTG_FS_BASE + 0x03C) +#define OTG_FS_HPTXFSIZ MMIO32(USB_OTG_FS_BASE + 0x100) +#define OTG_FS_DIEPTXF(x) MMIO32(USB_OTG_FS_BASE + 0x104 + 4*(x)) + +/* Host-mode Control and Status Registers */ +#define OTG_FS_HCFG MMIO32(USB_OTG_FS_BASE + 0x400) +#define OTG_FS_HFIR MMIO32(USB_OTG_FS_BASE + 0x404) +#define OTG_FS_HFNUM MMIO32(USB_OTG_FS_BASE + 0x408) +#define OTG_FS_HPTXSTS MMIO32(USB_OTG_FS_BASE + 0x410) +#define OTG_FS_HAINT MMIO32(USB_OTG_FS_BASE + 0x414) +#define OTG_FS_HAINTMSK MMIO32(USB_OTG_FS_BASE + 0x418) +#define OTG_FS_HPRT MMIO32(USB_OTG_FS_BASE + 0x440) +#define OTG_FS_HCCHARx MMIO32(USB_OTG_FS_BASE + 0x500) +#define OTG_FS_HCINTx MMIO32(USB_OTG_FS_BASE + 0x508) +#define OTG_FS_HCINTMSKx MMIO32(USB_OTG_FS_BASE + 0x50C) +#define OTG_FS_HCTSIZx MMIO32(USB_OTG_FS_BASE + 0x510) + +/* Device-mode Control and Status Registers */ +#define OTG_FS_DCFG MMIO32(USB_OTG_FS_BASE + 0x800) +#define OTG_FS_DCTL MMIO32(USB_OTG_FS_BASE + 0x804) +#define OTG_FS_DSTS MMIO32(USB_OTG_FS_BASE + 0x808) +#define OTG_FS_DIEPMSK MMIO32(USB_OTG_FS_BASE + 0x810) +#define OTG_FS_DOEPMSK MMIO32(USB_OTG_FS_BASE + 0x814) +#define OTG_FS_DAINT MMIO32(USB_OTG_FS_BASE + 0x818) +#define OTG_FS_DAINTMSK MMIO32(USB_OTG_FS_BASE + 0x81C) +#define OTG_FS_DVBUSDIS MMIO32(USB_OTG_FS_BASE + 0x828) +#define OTG_FS_DVBUSPULSE MMIO32(USB_OTG_FS_BASE + 0x82C) +#define OTG_FS_DIEPEMPMSK MMIO32(USB_OTG_FS_BASE + 0x834) +#define OTG_FS_DIEPCTL0 MMIO32(USB_OTG_FS_BASE + 0x900) +#define OTG_FS_DIEPCTL(x) MMIO32(USB_OTG_FS_BASE + 0x900 + 0x20*(x)) +#define OTG_FS_DOEPCTL0 MMIO32(USB_OTG_FS_BASE + 0xB00) +#define OTG_FS_DOEPCTL(x) MMIO32(USB_OTG_FS_BASE + 0xB00 + 0x20*(x)) +#define OTG_FS_DIEPINT(x) MMIO32(USB_OTG_FS_BASE + 0x908 + 0x20*(x)) +#define OTG_FS_DOEPINT(x) MMIO32(USB_OTG_FS_BASE + 0xB08 + 0x20*(x)) +#define OTG_FS_DIEPTSIZ0 MMIO32(USB_OTG_FS_BASE + 0x910) +#define OTG_FS_DOEPTSIZ0 MMIO32(USB_OTG_FS_BASE + 0xB10) +#define OTG_FS_DIEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + 0x910 + 0x20*(x)) +#define OTG_FS_DTXFSTS(x) MMIO32(USB_OTG_FS_BASE + 0x918 + 0x20*(x)) +#define OTG_FS_DOEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + 0xB10 + 0x20*(x)) + +/* Power and clock gating control and status register */ +#define OTG_FS_PCGCCTL MMIO32(USB_OTG_FS_BASE + 0xE00) + +/* Data FIFO */ +#define OTG_FS_FIFO(x) ((u32*)(USB_OTG_FS_BASE + (((x) + 1) << 12))) + +/* Global CSRs */ +/* OTG_FS AHB configuration register (OTG_FS_GAHBCFG) */ +#define OTG_FS_GAHBCFG_GINT 0x0001 +#define OTG_FS_GAHBCFG_TXFELVL 0x0080 +#define OTG_FS_GAHBCFG_PTXFELVL 0x0100 + +/* OTG_FS USB configuration register (OTG_FS_GUSBCFG) */ +#define OTG_FS_GUSBCFG_TOCAL 0x00000003 +#define OTG_FS_GUSBCFG_SRPCAP 0x00000100 +#define OTG_FS_GUSBCFG_HNPCAP 0x00000200 +#define OTG_FS_GUSBCFG_TRDT_MASK (0xf << 10) +#define OTG_FS_GUSBCFG_TRDT_16BIT (0x5 << 10) +#define OTG_FS_GUSBCFG_TRDT_8BIT (0x9 << 10) +#define OTG_FS_GUSBCFG_NPTXRWEN 0x00004000 +#define OTG_FS_GUSBCFG_FHMOD 0x20000000 +#define OTG_FS_GUSBCFG_FDMOD 0x40000000 +#define OTG_FS_GUSBCFG_CTXPKT 0x80000000 +/* WARNING: not in reference manual */ +#define OTG_FS_GUSBCFG_PHYSEL (1 << 6) + +/* OTG_FS reset register (OTG_FS_GRSTCTL) */ +#define OTG_FS_GRSTCTL_AHBIDL (1 << 31) +/* Bits 30:11 - Reserved */ +#define OTG_FS_GRSTCTL_TXFNUM_MASK (0x1f << 6) +#define OTG_FS_GRSTCTL_TXFFLSH (1 << 5) +#define OTG_FS_GRSTCTL_RXFFLSH (1 << 4) +/* Bit 3 - Reserved */ +#define OTG_FS_GRSTCTL_FCRST (1 << 2) +#define OTG_FS_GRSTCTL_HSRST (1 << 1) +#define OTG_FS_GRSTCTL_CSRST (1 << 0) + +/* OTG_FS interrupt status register (OTG_FS_GINTSTS) */ +#define OTG_FS_GINTSTS_WKUPINT (1 << 31) +#define OTG_FS_GINTSTS_SRQINT (1 << 30) +#define OTG_FS_GINTSTS_DISCINT (1 << 29) +#define OTG_FS_GINTSTS_CIDSCHG (1 << 28) +/* Bit 27 - Reserved */ +#define OTG_FS_GINTSTS_PTXFE (1 << 26) +#define OTG_FS_GINTSTS_HCINT (1 << 25) +#define OTG_FS_GINTSTS_HPRTINT (1 << 24) +/* Bits 23:22 - Reserved */ +#define OTG_FS_GINTSTS_IPXFR (1 << 21) +#define OTG_FS_GINTSTS_INCOMPISOOUT (1 << 21) +#define OTG_FS_GINTSTS_IISOIXFR (1 << 20) +#define OTG_FS_GINTSTS_OEPINT (1 << 19) +#define OTG_FS_GINTSTS_IEPINT (1 << 18) +/* Bits 17:16 - Reserved */ +#define OTG_FS_GINTSTS_EOPF (1 << 15) +#define OTG_FS_GINTSTS_ISOODRP (1 << 14) +#define OTG_FS_GINTSTS_ENUMDNE (1 << 13) +#define OTG_FS_GINTSTS_USBRST (1 << 12) +#define OTG_FS_GINTSTS_USBSUSP (1 << 11) +#define OTG_FS_GINTSTS_ESUSP (1 << 10) +/* Bits 9:8 - Reserved */ +#define OTG_FS_GINTSTS_GONAKEFF (1 << 7) +#define OTG_FS_GINTSTS_GINAKEFF (1 << 6) +#define OTG_FS_GINTSTS_NPTXFE (1 << 5) +#define OTG_FS_GINTSTS_RXFLVL (1 << 4) +#define OTG_FS_GINTSTS_SOF (1 << 3) +#define OTG_FS_GINTSTS_OTGINT (1 << 2) +#define OTG_FS_GINTSTS_MMIS (1 << 1) +#define OTG_FS_GINTSTS_CMOD (1 << 0) + +/* OTG_FS interrupt mask register (OTG_FS_GINTMSK) */ +#define OTG_FS_GINTMSK_MMISM 0x00000002 +#define OTG_FS_GINTMSK_OTGINT 0x00000004 +#define OTG_FS_GINTMSK_SOFM 0x00000008 +#define OTG_FS_GINTMSK_RXFLVLM 0x00000010 +#define OTG_FS_GINTMSK_NPTXFEM 0x00000020 +#define OTG_FS_GINTMSK_GINAKEFFM 0x00000040 +#define OTG_FS_GINTMSK_GONAKEFFM 0x00000080 +#define OTG_FS_GINTMSK_ESUSPM 0x00000400 +#define OTG_FS_GINTMSK_USBSUSPM 0x00000800 +#define OTG_FS_GINTMSK_USBRST 0x00001000 +#define OTG_FS_GINTMSK_ENUMDNEM 0x00002000 +#define OTG_FS_GINTMSK_ISOODRPM 0x00004000 +#define OTG_FS_GINTMSK_EOPFM 0x00008000 +#define OTG_FS_GINTMSK_EPMISM 0x00020000 +#define OTG_FS_GINTMSK_IEPINT 0x00040000 +#define OTG_FS_GINTMSK_OEPINT 0x00080000 +#define OTG_FS_GINTMSK_IISOIXFRM 0x00100000 +#define OTG_FS_GINTMSK_IISOOXFRM 0x00200000 +#define OTG_FS_GINTMSK_IPXFRM 0x00200000 +#define OTG_FS_GINTMSK_PRTIM 0x01000000 +#define OTG_FS_GINTMSK_HCIM 0x02000000 +#define OTG_FS_GINTMSK_PTXFEM 0x04000000 +#define OTG_FS_GINTMSK_CIDSCHGM 0x10000000 +#define OTG_FS_GINTMSK_DISCINT 0x20000000 +#define OTG_FS_GINTMSK_SRQIM 0x40000000 +#define OTG_FS_GINTMSK_WUIM 0x80000000 + +/* OTG_FS Receive Status Pop Register (OTG_FS_GRXSTSP) */ +/* Bits 31:25 - Reserved */ +#define OTG_FS_GRXSTSP_FRMNUM_MASK (0xf << 21) +#define OTG_FS_GRXSTSP_PKTSTS_MASK (0xf << 17) +#define OTG_FS_GRXSTSP_PKTSTS_GOUTNAK (0x1 << 17) +#define OTG_FS_GRXSTSP_PKTSTS_OUT (0x2 << 17) +#define OTG_FS_GRXSTSP_PKTSTS_OUT_COMP (0x3 << 17) +#define OTG_FS_GRXSTSP_PKTSTS_SETUP_COMP (0x4 << 17) +#define OTG_FS_GRXSTSP_PKTSTS_SETUP (0x6 << 17) +#define OTG_FS_GRXSTSP_DPID_MASK (0x3 << 15) +#define OTG_FS_GRXSTSP_DPID_DATA0 (0x0 << 15) +#define OTG_FS_GRXSTSP_DPID_DATA1 (0x2 << 15) +#define OTG_FS_GRXSTSP_DPID_DATA2 (0x1 << 15) +#define OTG_FS_GRXSTSP_DPID_MDATA (0x3 << 15) +#define OTG_FS_GRXSTSP_BCNT_MASK (0x7ff << 4) +#define OTG_FS_GRXSTSP_EPNUM_MASK (0xf << 0) + +/* OTG_FS general core configuration register (OTG_FS_GCCFG) */ +/* Bits 31:21 - Reserved */ +#define OTG_FS_GCCFG_SOFOUTEN (1 << 20) +#define OTG_FS_GCCFG_VBUSBSEN (1 << 19) +#define OTG_FS_GCCFG_VBUSASEN (1 << 18) +/* Bit 17 - Reserved */ +#define OTG_FS_GCCFG_PWRDWN (1 << 16) +/* Bits 15:0 - Reserved */ + + +/* Device-mode CSRs */ +/* OTG_FS device control register (OTG_FS_DCTL) */ +/* Bits 31:12 - Reserved */ +#define OTG_FS_DCTL_POPRGDNE (1 << 11) +#define OTG_FS_DCTL_CGONAK (1 << 10) +#define OTG_FS_DCTL_SGONAK (1 << 9) +#define OTG_FS_DCTL_SGINAK (1 << 8) +#define OTG_FS_DCTL_TCTL_MASK (7 << 4) +#define OTG_FS_DCTL_GONSTS (1 << 3) +#define OTG_FS_DCTL_GINSTS (1 << 2) +#define OTG_FS_DCTL_SDIS (1 << 1) +#define OTG_FS_DCTL_RWUSIG (1 << 0) + +/* OTG_FS device configuration register (OTG_FS_DCFG) */ +#define OTG_FS_DCFG_DSPD 0x0003 +#define OTG_FS_DCFG_NZLSOHSK 0x0004 +#define OTG_FS_DCFG_DAD 0x07F0 +#define OTG_FS_DCFG_PFIVL 0x1800 + +/* OTG_FS Device IN Endpoint Common Interrupt Mask Register (OTG_FS_DIEPMSK) */ +/* Bits 31:10 - Reserved */ +#define OTG_FS_DIEPMSK_BIM (1 << 9) +#define OTG_FS_DIEPMSK_TXFURM (1 << 8) +/* Bit 7 - Reserved */ +#define OTG_FS_DIEPMSK_INEPNEM (1 << 6) +#define OTG_FS_DIEPMSK_INEPNMM (1 << 5) +#define OTG_FS_DIEPMSK_ITTXFEMSK (1 << 4) +#define OTG_FS_DIEPMSK_TOM (1 << 3) +/* Bit 2 - Reserved */ +#define OTG_FS_DIEPMSK_EPDM (1 << 1) +#define OTG_FS_DIEPMSK_XFRCM (1 << 0) + +/* OTG_FS Device OUT Endpoint Common Interrupt Mask Register (OTG_FS_DOEPMSK) */ +/* Bits 31:10 - Reserved */ +#define OTG_FS_DOEPMSK_BOIM (1 << 9) +#define OTG_FS_DOEPMSK_OPEM (1 << 8) +/* Bit 7 - Reserved */ +#define OTG_FS_DOEPMSK_B2BSTUP (1 << 6) +/* Bit 5 - Reserved */ +#define OTG_FS_DOEPMSK_OTEPDM (1 << 4) +#define OTG_FS_DOEPMSK_STUPM (1 << 3) +/* Bit 2 - Reserved */ +#define OTG_FS_DOEPMSK_EPDM (1 << 1) +#define OTG_FS_DOEPMSK_XFRCM (1 << 0) + +/* OTG_FS Device Control IN Endpoint 0 Control Register (OTG_FS_DIEPCTL0) */ +#define OTG_FS_DIEPCTL0_EPENA (1 << 31) +#define OTG_FS_DIEPCTL0_EPDIS (1 << 30) +/* Bits 29:28 - Reserved */ +#define OTG_FS_DIEPCTLX_SD0PID (1 << 28) +#define OTG_FS_DIEPCTL0_SNAK (1 << 27) +#define OTG_FS_DIEPCTL0_CNAK (1 << 26) +#define OTG_FS_DIEPCTL0_TXFNUM_MASK (0xf << 22) +#define OTG_FS_DIEPCTL0_STALL (1 << 21) +/* Bit 20 - Reserved */ +#define OTG_FS_DIEPCTL0_EPTYP_MASK (0x3 << 18) +#define OTG_FS_DIEPCTL0_NAKSTS (1 << 17) +/* Bit 16 - Reserved */ +#define OTG_FS_DIEPCTL0_USBAEP (1 << 15) +/* Bits 14:2 - Reserved */ +#define OTG_FS_DIEPCTL0_MPSIZ_MASK (0x3 << 0) +#define OTG_FS_DIEPCTL0_MPSIZ_64 (0x0 << 0) +#define OTG_FS_DIEPCTL0_MPSIZ_32 (0x1 << 0) +#define OTG_FS_DIEPCTL0_MPSIZ_16 (0x2 << 0) +#define OTG_FS_DIEPCTL0_MPSIZ_8 (0x3 << 0) + +/* OTG_FS Device Control OUT Endpoint 0 Control Register (OTG_FS_DOEPCTL0) */ +#define OTG_FS_DOEPCTL0_EPENA (1 << 31) +#define OTG_FS_DOEPCTL0_EPDIS (1 << 30) +/* Bits 29:28 - Reserved */ +#define OTG_FS_DOEPCTLX_SD0PID (1 << 28) +#define OTG_FS_DOEPCTL0_SNAK (1 << 27) +#define OTG_FS_DOEPCTL0_CNAK (1 << 26) +/* Bits 25:22 - Reserved */ +#define OTG_FS_DOEPCTL0_STALL (1 << 21) +#define OTG_FS_DOEPCTL0_SNPM (1 << 20) +#define OTG_FS_DOEPCTL0_EPTYP_MASK (0x3 << 18) +#define OTG_FS_DOEPCTL0_NAKSTS (1 << 17) +/* Bit 16 - Reserved */ +#define OTG_FS_DOEPCTL0_USBAEP (1 << 15) +/* Bits 14:2 - Reserved */ +#define OTG_FS_DOEPCTL0_MPSIZ_MASK (0x3 << 0) +#define OTG_FS_DOEPCTL0_MPSIZ_64 (0x0 << 0) +#define OTG_FS_DOEPCTL0_MPSIZ_32 (0x1 << 0) +#define OTG_FS_DOEPCTL0_MPSIZ_16 (0x2 << 0) +#define OTG_FS_DOEPCTL0_MPSIZ_8 (0x3 << 0) + +/* OTG_FS Device IN Endpoint Interrupt Register (OTG_FS_DIEPINTx) */ +/* Bits 31:8 - Reserved */ +#define OTG_FS_DIEPINTX_TXFE (1 << 7) +#define OTG_FS_DIEPINTX_INEPNE (1 << 6) +/* Bit 5 - Reserved */ +#define OTG_FS_DIEPINTX_ITTXFE (1 << 4) +#define OTG_FS_DIEPINTX_TOC (1 << 3) +/* Bit 2 - Reserved */ +#define OTG_FS_DIEPINTX_EPDISD (1 << 1) +#define OTG_FS_DIEPINTX_XFRC (1 << 0) + +/* OTG_FS Device IN Endpoint Interrupt Register (OTG_FS_DOEPINTx) */ +/* Bits 31:7 - Reserved */ +#define OTG_FS_DOEPINTX_B2BSTUP (1 << 6) +/* Bit 5 - Reserved */ +#define OTG_FS_DOEPINTX_OTEPDIS (1 << 4) +#define OTG_FS_DOEPINTX_STUP (1 << 3) +/* Bit 2 - Reserved */ +#define OTG_FS_DOEPINTX_EPDISD (1 << 1) +#define OTG_FS_DOEPINTX_XFRC (1 << 0) + +/* OTG_FS Device OUT Endpoint 0 Transfer Size Regsiter (OTG_FS_DOEPTSIZ0) */ +/* Bit 31 - Reserved */ +#define OTG_FS_DIEPSIZ0_STUPCNT_1 (0x1 << 29) +#define OTG_FS_DIEPSIZ0_STUPCNT_2 (0x2 << 29) +#define OTG_FS_DIEPSIZ0_STUPCNT_3 (0x3 << 29) +#define OTG_FS_DIEPSIZ0_STUPCNT_MASK (0x3 << 29) +/* Bits 28:20 - Reserved */ +#define OTG_FS_DIEPSIZ0_PKTCNT (1 << 19) +/* Bits 18:7 - Reserved */ +#define OTG_FS_DIEPSIZ0_XFRSIZ_MASK (0x7f << 0) + +#endif + diff --git a/include/libopencm3/stm32/f1/rcc.h b/include/libopencm3/stm32/f1/rcc.h new file mode 100644 index 0000000..1072445 --- /dev/null +++ b/include/libopencm3/stm32/f1/rcc.h @@ -0,0 +1,417 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * Copyright (C) 2009 Federico Ruiz-Ugalde + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_RCC_H +#define LIBOPENCM3_RCC_H + +#include +#include + +/* Note: Regs/bits marked (**) only exist in "connectivity line" STM32s. */ +/* Note: Regs/bits marked (XX) do NOT exist in "connectivity line" STM32s. */ + +/* --- RCC registers ------------------------------------------------------- */ + +#define RCC_CR MMIO32(RCC_BASE + 0x00) +#define RCC_CFGR MMIO32(RCC_BASE + 0x04) +#define RCC_CIR MMIO32(RCC_BASE + 0x08) +#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x0c) +#define RCC_APB1RSTR MMIO32(RCC_BASE + 0x10) +#define RCC_AHBENR MMIO32(RCC_BASE + 0x14) +#define RCC_APB2ENR MMIO32(RCC_BASE + 0x18) +#define RCC_APB1ENR MMIO32(RCC_BASE + 0x1c) +#define RCC_BDCR MMIO32(RCC_BASE + 0x20) +#define RCC_CSR MMIO32(RCC_BASE + 0x24) +#define RCC_AHBRSTR MMIO32(RCC_BASE + 0x28) /* (**) */ +#define RCC_CFGR2 MMIO32(RCC_BASE + 0x2c) /* (**) */ + +/* --- RCC_CR values ------------------------------------------------------- */ + +#define RCC_CR_PLL3RDY (1 << 29) /* (**) */ +#define RCC_CR_PLL3ON (1 << 28) /* (**) */ +#define RCC_CR_PLL2RDY (1 << 27) /* (**) */ +#define RCC_CR_PLL2ON (1 << 26) /* (**) */ +#define RCC_CR_PLLRDY (1 << 25) +#define RCC_CR_PLLON (1 << 24) +#define RCC_CR_CSSON (1 << 19) +#define RCC_CR_HSEBYP (1 << 18) +#define RCC_CR_HSERDY (1 << 17) +#define RCC_CR_HSEON (1 << 16) +/* HSICAL: [15:8] */ +/* HSITRIM: [7:3] */ +#define RCC_CR_HSIRDY (1 << 1) +#define RCC_CR_HSION (1 << 0) + +/* --- RCC_CFGR values ----------------------------------------------------- */ + +/* MCO: Microcontroller clock output */ +#define RCC_CFGR_MCO_NOCLK 0x0 +#define RCC_CFGR_MCO_SYSCLK 0x4 +#define RCC_CFGR_MCO_HSICLK 0x5 +#define RCC_CFGR_MCO_HSECLK 0x6 +#define RCC_CFGR_RMCO_PLLCLK_DIV2 0x7 +#define RCC_CFGR_MCO_PLL2CLK 0x8 /* (**) */ +#define RCC_CFGR_MCO_PLL3CLK_DIV2 0x9 /* (**) */ +#define RCC_CFGR_MCO_XT1 0xa /* (**) */ +#define RCC_CFGR_MCO_PLL3 0xb /* (**) */ + +/* USBPRE: USB prescaler (RCC_CFGR[22]) */ +#define RCC_CFGR_USBPRE_PLL_CLK_DIV1_5 0x0 +#define RCC_CFGR_USBPRE_PLL_CLK_NODIV 0x1 + +/* OTGFSPRE: USB OTG FS prescaler (RCC_CFGR[22]; only in conn. line STM32s) */ +#define RCC_CFGR_USBPRE_PLL_VCO_CLK_DIV3 0x0 +#define RCC_CFGR_USBPRE_PLL_VCO_CLK_DIV2 0x1 + +/* PLLMUL: PLL multiplication factor */ +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL2 0x0 /* (XX) */ +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL3 0x1 /* (XX) */ +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL4 0x2 +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL5 0x3 +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL6 0x4 +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL7 0x5 +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL8 0x6 +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL9 0x7 +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL10 0x8 /* (XX) */ +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL11 0x9 /* (XX) */ +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL12 0xa /* (XX) */ +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL13 0xb /* (XX) */ +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL14 0xc /* (XX) */ +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL15 0xd /* 0xd: PLL x 15 */ +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL6_5 0xd /* 0xd: PLL x 6.5 for conn. line */ +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL16 0xe /* (XX) */ +// #define PLLMUL_PLL_CLK_MUL16 0xf /* (XX) */ /* Errata? 17? */ + +/* TODO: conn. line differs. */ +/* PLLXTPRE: HSE divider for PLL entry */ +#define RCC_CFGR_PLLXTPRE_HSE_CLK 0x0 +#define RCC_CFGR_PLLXTPRE_HSE_CLK_DIV2 0x1 + +/* PLLSRC: PLL entry clock source */ +#define RCC_CFGR_PLLSRC_HSI_CLK_DIV2 0x0 +#define RCC_CFGR_PLLSRC_HSE_CLK 0x1 +#define RCC_CFGR_PLLSRC_PREDIV1_CLK 0x1 /* On conn. line */ + +/* ADCPRE: ADC prescaler */ +#define RCC_CFGR_ADCPRE_PCLK2_DIV2 0x0 +#define RCC_CFGR_ADCPRE_PCLK2_DIV4 0x1 +#define RCC_CFGR_ADCPRE_PCLK2_DIV6 0x2 +#define RCC_CFGR_ADCPRE_PCLK2_DIV8 0x3 + +/* PPRE2: APB high-speed prescaler (APB2) */ +#define RCC_CFGR_PPRE2_HCLK_NODIV 0x0 +#define RCC_CFGR_PPRE2_HCLK_DIV2 0x4 +#define RCC_CFGR_PPRE2_HCLK_DIV4 0x5 +#define RCC_CFGR_PPRE2_HCLK_DIV8 0x6 +#define RCC_CFGR_PPRE2_HCLK_DIV16 0x7 + +/* PPRE1: APB low-speed prescaler (APB1) */ +#define RCC_CFGR_PPRE1_HCLK_NODIV 0x0 +#define RCC_CFGR_PPRE1_HCLK_DIV2 0x4 +#define RCC_CFGR_PPRE1_HCLK_DIV4 0x5 +#define RCC_CFGR_PPRE1_HCLK_DIV8 0x6 +#define RCC_CFGR_PPRE1_HCLK_DIV16 0x7 + +/* HPRE: AHB prescaler */ +#define RCC_CFGR_HPRE_SYSCLK_NODIV 0x0 +#define RCC_CFGR_HPRE_SYSCLK_DIV2 0x8 +#define RCC_CFGR_HPRE_SYSCLK_DIV4 0x9 +#define RCC_CFGR_HPRE_SYSCLK_DIV8 0xa +#define RCC_CFGR_HPRE_SYSCLK_DIV16 0xb +#define RCC_CFGR_HPRE_SYSCLK_DIV64 0xc +#define RCC_CFGR_HPRE_SYSCLK_DIV128 0xd +#define RCC_CFGR_HPRE_SYSCLK_DIV256 0xe +#define RCC_CFGR_HPRE_SYSCLK_DIV512 0xf + +/* SWS: System clock switch status */ +#define RCC_CFGR_SWS_SYSCLKSEL_HSICLK 0x0 +#define RCC_CFGR_SWS_SYSCLKSEL_HSECLK 0x1 +#define RCC_CFGR_SWS_SYSCLKSEL_PLLCLK 0x2 + +/* SW: System clock switch */ +#define RCC_CFGR_SW_SYSCLKSEL_HSICLK 0x0 +#define RCC_CFGR_SW_SYSCLKSEL_HSECLK 0x1 +#define RCC_CFGR_SW_SYSCLKSEL_PLLCLK 0x2 + +/* --- RCC_CIR values ------------------------------------------------------ */ + +/* Clock security system interrupt clear bit */ +#define RCC_CIR_CSSC (1 << 23) + +/* OSC ready interrupt clear bits */ +#define RCC_CIR_PLL3RDYC (1 << 22) /* (**) */ +#define RCC_CIR_PLL2RDYC (1 << 21) /* (**) */ +#define RCC_CIR_PLLRDYC (1 << 20) +#define RCC_CIR_HSERDYC (1 << 19) +#define RCC_CIR_HSIRDYC (1 << 18) +#define RCC_CIR_LSERDYC (1 << 17) +#define RCC_CIR_LSIRDYC (1 << 16) + +/* OSC ready interrupt enable bits */ +#define RCC_CIR_PLL3RDYIE (1 << 14) /* (**) */ +#define RCC_CIR_PLL2RDYIE (1 << 13) /* (**) */ +#define RCC_CIR_PLLRDYIE (1 << 12) +#define RCC_CIR_HSERDYIE (1 << 11) +#define RCC_CIR_HSIRDYIE (1 << 10) +#define RCC_CIR_LSERDYIE (1 << 9) +#define RCC_CIR_LSIRDYIE (1 << 8) + +/* Clock security system interrupt flag bit */ +#define RCC_CIR_CSSF (1 << 7) + +/* OSC ready interrupt flag bits */ +#define RCC_CIR_PLL3RDYF (1 << 6) /* (**) */ +#define RCC_CIR_PLL2RDYF (1 << 5) /* (**) */ +#define RCC_CIR_PLLRDYF (1 << 4) +#define RCC_CIR_HSERDYF (1 << 3) +#define RCC_CIR_HSIRDYF (1 << 2) +#define RCC_CIR_LSERDYF (1 << 1) +#define RCC_CIR_LSIRDYF (1 << 0) + +/* --- RCC_APB2RSTR values ------------------------------------------------- */ + +#define RCC_APB2RSTR_ADC3RST (1 << 15) /* (XX) */ +#define RCC_APB2RSTR_USART1RST (1 << 14) +#define RCC_APB2RSTR_TIM8RST (1 << 13) /* (XX) */ +#define RCC_APB2RSTR_SPI1RST (1 << 12) +#define RCC_APB2RSTR_TIM1RST (1 << 11) +#define RCC_APB2RSTR_ADC2RST (1 << 10) +#define RCC_APB2RSTR_ADC1RST (1 << 9) +#define RCC_APB2RSTR_IOPGRST (1 << 8) /* (XX) */ +#define RCC_APB2RSTR_IOPFRST (1 << 7) /* (XX) */ +#define RCC_APB2RSTR_IOPERST (1 << 6) +#define RCC_APB2RSTR_IOPDRST (1 << 5) +#define RCC_APB2RSTR_IOPCRST (1 << 4) +#define RCC_APB2RSTR_IOPBRST (1 << 3) +#define RCC_APB2RSTR_IOPARST (1 << 2) +#define RCC_APB2RSTR_AFIORST (1 << 0) + +/* --- RCC_APB1RSTR values ------------------------------------------------- */ + +#define RCC_APB1RSTR_DACRST (1 << 29) +#define RCC_APB1RSTR_PWRRST (1 << 28) +#define RCC_APB1RSTR_BKPRST (1 << 27) +#define RCC_APB1RSTR_CAN2RST (1 << 26) /* (**) */ +#define RCC_APB1RSTR_CAN1RST (1 << 25) /* (**) */ +#define RCC_APB1RSTR_CANRST (1 << 25) /* (XX) Alias for CAN1RST */ +#define RCC_APB1RSTR_USBRST (1 << 23) /* (XX) */ +#define RCC_APB1RSTR_I2C2RST (1 << 22) +#define RCC_APB1RSTR_I2C1RST (1 << 21) +#define RCC_APB1RSTR_USART5RST (1 << 20) +#define RCC_APB1RSTR_USART4RST (1 << 19) +#define RCC_APB1RSTR_USART3RST (1 << 18) +#define RCC_APB1RSTR_USART2RST (1 << 17) +#define RCC_APB1RSTR_SPI3RST (1 << 15) +#define RCC_APB1RSTR_SPI2RST (1 << 14) +#define RCC_APB1RSTR_WWDGRST (1 << 11) +#define RCC_APB1RSTR_TIM7RST (1 << 5) +#define RCC_APB1RSTR_TIM6RST (1 << 4) +#define RCC_APB1RSTR_TIM5RST (1 << 3) +#define RCC_APB1RSTR_TIM4RST (1 << 2) +#define RCC_APB1RSTR_TIM3RST (1 << 1) +#define RCC_APB1RSTR_TIM2RST (1 << 0) + +/* --- RCC_AHBENR values --------------------------------------------------- */ + +#define RCC_AHBENR_ETHMACENRX (1 << 16) +#define RCC_AHBENR_ETHMACENTX (1 << 15) +#define RCC_AHBENR_ETHMACEN (1 << 14) +#define RCC_AHBENR_OTGFSEN (1 << 12) +#define RCC_AHBENR_SDIOEN (1 << 10) +#define RCC_AHBENR_FSMCEN (1 << 8) +#define RCC_AHBENR_CRCEN (1 << 6) +#define RCC_AHBENR_FLITFEN (1 << 4) +#define RCC_AHBENR_SRAMEN (1 << 2) +#define RCC_AHBENR_DMA2EN (1 << 1) +#define RCC_AHBENR_DMA1EN (1 << 0) + +/* --- RCC_APB2ENR values -------------------------------------------------- */ + +#define RCC_APB2ENR_ADC3EN (1 << 15) /* (XX) */ +#define RCC_APB2ENR_USART1EN (1 << 14) +#define RCC_APB2ENR_TIM8EN (1 << 13) /* (XX) */ +#define RCC_APB2ENR_SPI1EN (1 << 12) +#define RCC_APB2ENR_TIM1EN (1 << 11) +#define RCC_APB2ENR_ADC2EN (1 << 10) +#define RCC_APB2ENR_ADC1EN (1 << 9) +#define RCC_APB2ENR_IOPGEN (1 << 8) /* (XX) */ +#define RCC_APB2ENR_IOPFEN (1 << 7) /* (XX) */ +#define RCC_APB2ENR_IOPEEN (1 << 6) +#define RCC_APB2ENR_IOPDEN (1 << 5) +#define RCC_APB2ENR_IOPCEN (1 << 4) +#define RCC_APB2ENR_IOPBEN (1 << 3) +#define RCC_APB2ENR_IOPAEN (1 << 2) +#define RCC_APB2ENR_AFIOEN (1 << 0) + +/* --- RCC_APB1ENR values -------------------------------------------------- */ + +#define RCC_APB1ENR_DACEN (1 << 29) +#define RCC_APB1ENR_PWREN (1 << 28) +#define RCC_APB1ENR_BKPEN (1 << 27) +#define RCC_APB1ENR_CAN2EN (1 << 26) /* (**) */ +#define RCC_APB1ENR_CAN1EN (1 << 25) /* (**) */ +#define RCC_APB1ENR_CANEN (1 << 25) /* (XX) Alias for CAN1EN */ +#define RCC_APB1ENR_USBEN (1 << 23) /* (XX) */ +#define RCC_APB1ENR_I2C2EN (1 << 22) +#define RCC_APB1ENR_I2C1EN (1 << 21) +#define RCC_APB1ENR_USART5EN (1 << 20) +#define RCC_APB1ENR_USART4EN (1 << 19) +#define RCC_APB1ENR_USART3EN (1 << 18) +#define RCC_APB1ENR_USART2EN (1 << 17) +#define RCC_APB1ENR_SPI3EN (1 << 15) +#define RCC_APB1ENR_SPI2EN (1 << 14) +#define RCC_APB1ENR_WWDGEN (1 << 11) +#define RCC_APB1ENR_TIM7EN (1 << 5) +#define RCC_APB1ENR_TIM6EN (1 << 4) +#define RCC_APB1ENR_TIM5EN (1 << 3) +#define RCC_APB1ENR_TIM4EN (1 << 2) +#define RCC_APB1ENR_TIM3EN (1 << 1) +#define RCC_APB1ENR_TIM2EN (1 << 0) + +/* --- RCC_BDCR values ----------------------------------------------------- */ + +#define RCC_BDCR_BDRST (1 << 16) +#define RCC_BDCR_RTCEN (1 << 15) +/* RCC_BDCR[9:8]: RTCSEL */ +#define RCC_BDCR_LSEBYP (1 << 2) +#define RCC_BDCR_LSERDY (1 << 1) +#define RCC_BDCR_LSEON (1 << 0) + +/* --- RCC_CSR values ------------------------------------------------------ */ + +#define RCC_CSR_LPWRRSTF (1 << 31) +#define RCC_CSR_WWDGRSTF (1 << 30) +#define RCC_CSR_IWDGRSTF (1 << 29) +#define RCC_CSR_SFTRSTF (1 << 28) +#define RCC_CSR_PORRSTF (1 << 27) +#define RCC_CSR_PINRSTF (1 << 26) +#define RCC_CSR_RMVF (1 << 24) +#define RCC_CSR_LSIRDY (1 << 1) +#define RCC_CSR_LSION (1 << 0) + +/* --- RCC_AHBRSTR values -------------------------------------------------- */ + +#define RCC_AHBRSTR_ETHMACRST (1 << 14) +#define RCC_AHBRSTR_OTGFSRST (1 << 12) + +/* --- RCC_CFGR2 values ---------------------------------------------------- */ + +/* I2S3SRC: I2S3 clock source */ +#define RCC_CFGR2_I2S3SRC_SYSCLK 0x0 +#define RCC_CFGR2_I2S3SRC_PLL3_VCO_CLK 0x1 + +/* I2S2SRC: I2S2 clock source */ +#define RCC_CFGR2_I2S2SRC_SYSCLK 0x0 +#define RCC_CFGR2_I2S2SRC_PLL3_VCO_CLK 0x1 + +/* PREDIV1SRC: PREDIV1 entry clock source */ +#define RCC_CFGR2_PREDIV1SRC_HSE_CLK 0x0 +#define RCC_CFGR2_PREDIV1SRC_PLL2_CLK 0x1 + +#define RCC_CFGR2_PLL2MUL (1 << 0) +#define RCC_CFGR2_PREDIV2 (1 << 0) +#define RCC_CFGR2_PREDIV1 (1 << 0) + +/* PLL3MUL: PLL3 multiplication factor */ +#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL8 0x6 +#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL9 0x7 +#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL10 0x8 +#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL11 0x9 +#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL12 0xa +#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL13 0xb +#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL14 0xc +#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL16 0xe +#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL20 0xf + +/* PLL2MUL: PLL2 multiplication factor */ +#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL8 0x6 +#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL9 0x7 +#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL10 0x8 +#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL11 0x9 +#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL12 0xa +#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL13 0xb +#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL14 0xc +#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL16 0xe +#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL20 0xf + +/* PREDIV2: PREDIV2 division factor */ +#define RCC_CFGR2_PREDIV2_NODIV 0x0 +#define RCC_CFGR2_PREDIV2_DIV2 0x1 +#define RCC_CFGR2_PREDIV2_DIV3 0x2 +#define RCC_CFGR2_PREDIV2_DIV4 0x3 +#define RCC_CFGR2_PREDIV2_DIV5 0x4 +#define RCC_CFGR2_PREDIV2_DIV6 0x5 +#define RCC_CFGR2_PREDIV2_DIV7 0x6 +#define RCC_CFGR2_PREDIV2_DIV8 0x7 +#define RCC_CFGR2_PREDIV2_DIV9 0x8 +#define RCC_CFGR2_PREDIV2_DIV10 0x9 +#define RCC_CFGR2_PREDIV2_DIV11 0xa +#define RCC_CFGR2_PREDIV2_DIV12 0xb +#define RCC_CFGR2_PREDIV2_DIV13 0xc +#define RCC_CFGR2_PREDIV2_DIV14 0xd +#define RCC_CFGR2_PREDIV2_DIV15 0xe +#define RCC_CFGR2_PREDIV2_DIV16 0xf + +/* --- Variable definitions ------------------------------------------------ */ +extern u32 rcc_ppre1_frequency; +extern u32 rcc_ppre2_frequency; + +/* --- Function prototypes ------------------------------------------------- */ + +typedef enum { + PLL, HSE, HSI, LSE, LSI +} osc_t; + +void rcc_osc_ready_int_clear(osc_t osc); +void rcc_osc_ready_int_enable(osc_t osc); +void rcc_osc_ready_int_disable(osc_t osc); +int rcc_osc_ready_int_flag(osc_t osc); +void rcc_css_int_clear(void); +int rcc_css_int_flag(void); +void rcc_wait_for_osc_ready(osc_t osc); +void rcc_osc_on(osc_t osc); +void rcc_osc_off(osc_t osc); +void rcc_css_enable(void); +void rcc_css_disable(void); +void rcc_osc_bypass_enable(osc_t osc); +void rcc_osc_bypass_disable(osc_t osc); +void rcc_peripheral_enable_clock(volatile u32 *reg, u32 en); +void rcc_peripheral_disable_clock(volatile u32 *reg, u32 en); +void rcc_peripheral_reset(volatile u32 *reg, u32 reset); +void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset); +void rcc_set_sysclk_source(u32 clk); +void rcc_set_pll_multiplication_factor(u32 mul); +void rcc_set_pll_source(u32 pllsrc); +void rcc_set_pllxtpre(u32 pllxtpre); +void rcc_set_adcpre(u32 adcpre); +void rcc_set_ppre2(u32 ppre2); +void rcc_set_ppre1(u32 ppre1); +void rcc_set_hpre(u32 hpre); +void rcc_set_usbpre(u32 usbpre); +u32 rcc_get_system_clock_source(int i); +void rcc_clock_setup_in_hsi_out_64mhz(void); +void rcc_clock_setup_in_hsi_out_48mhz(void); +void rcc_clock_setup_in_hse_8mhz_out_24mhz(void); +void rcc_clock_setup_in_hse_8mhz_out_72mhz(void); +void rcc_clock_setup_in_hse_12mhz_out_72mhz(void); +void rcc_clock_setup_in_hse_16mhz_out_72mhz(void); +void rcc_backupdomain_reset(void); + +#endif diff --git a/include/libopencm3/stm32/f1/rtc.h b/include/libopencm3/stm32/f1/rtc.h new file mode 100644 index 0000000..b71525e --- /dev/null +++ b/include/libopencm3/stm32/f1/rtc.h @@ -0,0 +1,146 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_RTC_H +#define LIBOPENCM3_RTC_H + +#include +#include +#include + +/* --- RTC registers ------------------------------------------------------- */ + +/* RTC control register high (RTC_CRH) */ +#define RTC_CRH MMIO32(RTC_BASE + 0x00) + +/* RTC control register low (RTC_CRL) */ +#define RTC_CRL MMIO32(RTC_BASE + 0x04) + +/* RTC prescaler load register (RTC_PRLH / RTC_PRLL) */ +#define RTC_PRLH MMIO32(RTC_BASE + 0x08) +#define RTC_PRLL MMIO32(RTC_BASE + 0x0c) + +/* RTC prescaler divider register (RTC_DIVH / RTC_DIVL) */ +#define RTC_DIVH MMIO32(RTC_BASE + 0x10) +#define RTC_DIVL MMIO32(RTC_BASE + 0x14) + +/* RTC counter register (RTC_CNTH / RTC_CNTL) */ +#define RTC_CNTH MMIO32(RTC_BASE + 0x18) +#define RTC_CNTL MMIO32(RTC_BASE + 0x1c) + +/* RTC alarm register high (RTC_ALRH / RTC_ALRL) */ +#define RTC_ALRH MMIO32(RTC_BASE + 0x20) +#define RTC_ALRL MMIO32(RTC_BASE + 0x24) + +/* --- RTC_CRH values -------------------------------------------------------*/ + +/* Note: Bits [15:3] are reserved, and forced to 0 by hardware. */ + +/* OWIE: Overflow interrupt enable */ +#define RTC_CRH_OWIE (1 << 2) + +/* ALRIE: Alarm interrupt enable */ +#define RTC_CRH_ALRIE (1 << 1) + +/* SECIE: Second interrupt enable */ +#define RTC_CRH_SECIE (1 << 0) + +/* --- RTC_CRL values -------------------------------------------------------*/ + +/* Note: Bits [15:6] are reserved, and forced to 0 by hardware. */ + +/* RTOFF: RTC operation OFF */ +#define RTC_CRL_RTOFF (1 << 5) + +/* CNF: Configuration flag */ +#define RTC_CRL_CNF (1 << 4) + +/* RSF: Registers synchronized flag */ +#define RTC_CRL_RSF (1 << 3) + +/* OWF: Overflow flag */ +#define RTC_CRL_OWF (1 << 2) + +/* ALRF: Alarm flag */ +#define RTC_CRL_ALRF (1 << 1) + +/* SECF: Second flag */ +#define RTC_CRL_SECF (1 << 0) + +/* --- RTC_PRLH values ------------------------------------------------------*/ + +/* Note: Bits [15:4] are reserved, and forced to 0 by hardware. */ + +/* TODO */ + +/* --- RTC_PRLL values ------------------------------------------------------*/ + +/* TODO */ + +/* --- RTC_DIVH values ------------------------------------------------------*/ + +/* Bits [15:4] are reserved. */ + +/* TODO */ + +/* --- RTC_DIVL values ------------------------------------------------------*/ + +/* TODO */ + +/* --- RTC_CNTH values ------------------------------------------------------*/ + +/* TODO */ + +/* --- RTC_CNTL values ------------------------------------------------------*/ + +/* TODO */ + +/* --- RTC_ALRH values ------------------------------------------------------*/ + +/* TODO */ + +/* --- RTC_ALRL values ------------------------------------------------------*/ + +/* TODO */ + +/* --- Function prototypes --------------------------------------------------*/ + +typedef enum { + RTC_SEC, RTC_ALR, RTC_OW, +} rtcflag_t; + +void rtc_awake_from_off(osc_t clock_source); +void rtc_enter_config_mode(void); +void rtc_exit_config_mode(void); +void rtc_set_alarm_time(u32 alarm_time); +void rtc_enable_alarm(void); +void rtc_disable_alarm(void); +void rtc_set_prescale_val(u32 prescale_val); +u32 rtc_get_counter_val(void); +u32 rtc_get_prescale_div_val(void); +u32 rtc_get_alarm_val(void); +void rtc_set_counter_val(u32 counter_val); +void rtc_interrupt_enable(rtcflag_t flag_val); +void rtc_interrupt_disable(rtcflag_t flag_val); +void rtc_clear_flag(rtcflag_t flag_val); +u32 rtc_check_flag(rtcflag_t flag_val); +void rtc_awake_from_standby(void); +void rtc_auto_awake(osc_t clock_source, u32 prescale_val); + +#endif diff --git a/include/libopencm3/stm32/f1/scb.h b/include/libopencm3/stm32/f1/scb.h new file mode 100644 index 0000000..9594cf1 --- /dev/null +++ b/include/libopencm3/stm32/f1/scb.h @@ -0,0 +1,300 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Piotr Esden-Tempski + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_SCB_H +#define LIBOPENCM3_SCB_H + +#include +#include + +/* --- SCB: Registers ------------------------------------------------------ */ + +/* CPUID: CPUID base register */ +#define SCB_CPUID MMIO32(SCB_BASE + 0x00) + +/* ICSR: Interrupt Control State Register */ +#define SCB_ICSR MMIO32(SCB_BASE + 0x04) + +/* VTOR: Vector Table Offset Register */ +#define SCB_VTOR MMIO32(SCB_BASE + 0x08) + +/* AIRCR: Application Interrupt and Reset Control Register */ +#define SCB_AIRCR MMIO32(SCB_BASE + 0x0C) + +/* SCR: System Control Register */ +#define SCB_SCR MMIO32(SCB_BASE + 0x10) + +/* CCR: Configuration Control Register */ +#define SCB_CCR MMIO32(SCB_BASE + 0x14) + +/* SHP: System Handler Priority Registers */ +/* Note: 12 8bit registers */ +#define SCB_SHPR(shpr_id) MMIO8(SCB_BASE + 0x18 + shpr_id) +#define SCB_SHPR1 MMIO8(SCB_BASE + 0x18 + 1) +#define SCB_SHPR2 MMIO8(SCB_BASE + 0x18 + 2) +#define SCB_SHPR3 MMIO8(SCB_BASE + 0x18 + 3) + +/* SHCSR: System Handler Control and State Register */ +#define SCB_SHCSR MMIO32(SCB_BASE + 0x24) + +/* CFSR: Configurable Fault Status Registers */ +#define SCB_CFSR MMIO32(SCB_BASE + 0x28) + +/* HFSR: Hard Fault Status Register */ +#define SCB_HFSR MMIO32(SCB_BASE + 0x2C) + +/* DFSR: Debug Fault Status Register */ +#define SCB_DFSR MMIO32(SCB_BASE + 0x30) + +/* MMFAR: Memory Manage Fault Address Register */ +#define SCB_MMFAR MMIO32(SCB_BASE + 0x34) + +/* BFAR: Bus Fault Address Register */ +#define SCB_BFAR MMIO32(SCB_BASE + 0x38) + +/* AFSR: Auxiliary Fault Status Register */ +#define SCB_AFSR MMIO32(SCB_BASE + 0x3C) + +/* --- SCB values ---------------------------------------------------------- */ + +/* --- SCB_CPUID values ---------------------------------------------------- */ + +/* Implementer[31:24]: Implementer code */ +#define SCP_CPUID_IMPLEMENTER_LSB 24 +/* Variant[23:20]: Variant number */ +#define SCP_CPUID_VARIANT_LSB 20 +/* Constant[19:16]: Reads as 0xF */ +#define SCP_CPUID_CONSTANT_LSB 16 +/* PartNo[15:4]: Part number of the processor */ +#define SCP_CPUID_PARTNO_LSB 4 +/* Revision[3:0]: Revision number */ +#define SCP_CPUID_REVISION_LSB 0 + +/* --- SCB_ICSR values ----------------------------------------------------- */ + +/* NMIPENDSET: NMI set-pending bit */ +#define SCB_ICSR_NMIPENDSET (1 << 31) +/* Bits [30:29]: reserved - must be kept cleared */ +/* PENDSVSET: PendSV set-pending bit */ +#define SCB_ICSR_PENDSVSET (1 << 28) +/* PENDSVCLR: PendSV clear-pending bit */ +#define SCB_ICSR_PENDSVCLR (1 << 27) +/* PENDSTSET: SysTick exception set-pending bit */ +#define SCB_ICSR_PENDSTSET (1 << 26) +/* PENDSTCLR: SysTick exception clear-pending bit */ +#define SCB_ICSR_PENDSTCLR (1 << 25) +/* Bit 24: reserved - must be kept cleared */ +/* Bit 23: reserved for debug - reads as 0 when not in debug mode */ +/* ISRPENDING: Interrupt pending flag, excluding NMI and Faults */ +#define SCB_ICSR_ISRPENDING (1 << 22) +/* VECTPENDING[21:12] Pending vector */ +#define SCB_ICSR_VECTPENDING_LSB 12 +/* RETOBASE: Return to base level */ +#define SCB_ICSR_RETOBASE (1 << 11) +/* Bits [10:9]: reserved - must be kept cleared */ +/* VECTACTIVE[8:0] Active vector */ +#define SCB_ICSR_VECTACTIVE_LSB 0 + +/* --- SCB_VTOR values ----------------------------------------------------- */ + +/* Bits [31:30]: reserved - must be kept cleared */ +/* TBLOFF[29:9]: Vector table base offset field */ +#define SCB_VTOR_TBLOFF_LSB 9 /* inconsistent datasheet - LSB could be 11 */ + +/* --- SCB_AIRCR values ---------------------------------------------------- */ + +/* VECTKEYSTAT[31:16]/ VECTKEY[31:16] Register key */ +#define SCB_AIRCR_VECTKEYSTAT_LSB 16 +#define SCB_AIRCR_VECTKEY 0x05FA0000 +/* ENDIANESS Data endianness bit */ +#define SCB_AIRCR_ENDIANESS (1 << 15) +/* Bits [14:11]: reserved - must be kept cleared */ +/* PRIGROUP[10:8]: Interrupt priority grouping field */ +#define SCB_AIRCR_PRIGROUP_LSB 8 +#define SCB_AIRCR_PRIGROUP_GROUP16_NOSUB 0x3 +#define SCB_AIRCR_PRIGROUP_GROUP8_SUB2 0x4 +#define SCB_AIRCR_PRIGROUP_GROUP4_SUB4 0x5 +#define SCB_AIRCR_PRIGROUP_GROUP2_SUB8 0x6 +#define SCB_AIRCR_PRIGROUP_NOGROUP_SUB16 0x7 +/* Bits [7:3]: reserved - must be kept cleared */ +/* SYSRESETREQ System reset request */ +#define SCB_AIRCR_SYSRESETREQ (1 << 2) +/* VECTCLRACTIVE */ +#define SCB_AIRCR_VECTCLRACTIVE (1 << 1) +/* VECTRESET */ +#define SCB_AIRCR_VECTRESET (1 << 0) + +/* --- SCB_SCR values ------------------------------------------------------ */ + +/* Bits [31:5]: reserved - must be kept cleared */ +/* SEVEONPEND Send Event on Pending bit */ +#define SCB_SCR_SEVEONPEND (1 << 4) +/* Bit 3: reserved - must be kept cleared */ +/* SLEEPDEEP */ +#define SCB_SCR_SLEEPDEEP (1 << 2) +/* SLEEPONEXIT */ +#define SCB_SCR_SLEEPONEXIT (1 << 1) +/* Bit 0: reserved - must be kept cleared */ + +/* --- SCB_CCR values ------------------------------------------------------ */ + +/* Bits [31:10]: reserved - must be kept cleared */ +/* STKALIGN */ +#define SCB_CCR_STKALIGN (1 << 9) +/* BFHFNMIGN */ +#define SCB_CCR_BFHFNMIGN (1 << 8) +/* Bits [7:5]: reserved - must be kept cleared */ +/* DIV_0_TRP */ +#define SCB_CCR_DIV_0_TRP (1 << 4) +/* UNALIGN_TRP */ +#define SCB_CCR_UNALIGN_TRP (1 << 3) +/* Bit 2: reserved - must be kept cleared */ +/* USERSETMPEND */ +#define SCB_CCR_USERSETMPEND (1 << 1) +/* NONBASETHRDENA */ +#define SCB_CCR_NONBASETHRDENA (1 << 0) + +/* --- SCB_SHPR1 values ---------------------------------------------------- */ + +/* Bits [31:24]: reserved - must be kept cleared */ +/* PRI_6[23:16]: Priority of system handler 6, usage fault */ +#define SCB_SHPR1_PRI_6_LSB 16 +/* PRI_5[15:8]: Priority of system handler 5, bus fault */ +#define SCB_SHPR1_PRI_5_LSB 8 +/* PRI_4[7:0]: Priority of system handler 4, memory management fault */ +#define SCB_SHPR1_PRI_4_LSB 0 + +/* --- SCB_SHPR2 values ---------------------------------------------------- */ + +/* PRI_11[31:24]: Priority of system handler 11, SVCall */ +#define SCB_SHPR2_PRI_11_LSB 24 +/* Bits [23:0]: reserved - must be kept cleared */ + +/* --- SCB_SHPR3 values ---------------------------------------------------- */ + +/* PRI_15[31:24]: Priority of system handler 15, SysTick exception */ +#define SCB_SHPR3_PRI_15_LSB 24 +/* PRI_14[23:16]: Priority of system handler 14, PendSV */ +#define SCB_SHPR3_PRI_14_LSB 16 +/* Bits [15:0]: reserved - must be kept cleared */ + +/* --- SCB_SHCSR values ---------------------------------------------------- */ + +/* Bits [31:19]: reserved - must be kept cleared */ +/* USGFAULTENA: Usage fault enable */ +#define SCB_SHCSR_USGFAULTENA (1 << 18) +/* BUSFAULTENA: Bus fault enable */ +#define SCB_SHCSR_BUSFAULTENA (1 << 17) +/* MEMFAULTENA: Memory management fault enable */ +#define SCB_SHCSR_MEMFAULTENA (1 << 16) +/* SVCALLPENDED: SVC call pending */ +#define SCB_SHCSR_SVCALLPENDED (1 << 15) +/* BUSFAULTPENDED: Bus fault exception pending */ +#define SCB_SHCSR_BUSFAULTPENDED (1 << 14) +/* MEMFAULTPENDED: Memory management fault exception pending */ +#define SCB_SHCSR_MEMFAULTPENDED (1 << 13) +/* USGFAULTPENDED: Usage fault exception pending */ +#define SCB_SHCSR_USGFAULTPENDED (1 << 12) +/* SYSTICKACT: SysTick exception active */ +#define SCB_SHCSR_SYSTICKACT (1 << 11) +/* PENDSVACT: PendSV exception active */ +#define SCB_SHCSR_PENDSVACT (1 << 10) +/* Bit 9: reserved - must be kept cleared */ +/* MONITORACT: Debug monitor active */ +#define SCB_SHCSR_MONITORACT (1 << 8) +/* SVCALLACT: SVC call active */ +#define SCB_SHCSR_SVCALLACT (1 << 7) +/* Bits [6:4]: reserved - must be kept cleared */ +/* USGFAULTACT: Usage fault exception active */ +#define SCB_SHCSR_USGFAULTACT (1 << 3) +/* Bit 2: reserved - must be kept cleared */ +/* BUSFAULTACT: Bus fault exception active */ +#define SCB_SHCSR_BUSFAULTACT (1 << 1) +/* MEMFAULTACT: Memory management fault exception active */ +#define SCB_SHCSR_MEMFAULTACT (1 << 0) + +/* --- SCB_CFSR values ----------------------------------------------------- */ + +/* Bits [31:26]: reserved - must be kept cleared */ +/* DIVBYZERO: Divide by zero usage fault */ +#define SCB_CFSR_DIVBYZERO (1 << 25) +/* UNALIGNED: Unaligned access usage fault */ +#define SCB_CFSR_UNALIGNED (1 << 24) +/* Bits [23:20]: reserved - must be kept cleared */ +/* NOCP: No coprocessor usage fault */ +#define SCB_CFSR_NOCP (1 << 19) +/* INVPC: Invalid PC load usage fault */ +#define SCB_CFSR_INVPC (1 << 18) +/* INVSTATE: Invalid state usage fault */ +#define SCB_CFSR_INVSTATE (1 << 17) +/* UNDEFINSTR: Undefined instruction usage fault */ +#define SCB_CFSR_UNDEFINSTR (1 << 16) +/* BFARVALID: Bus Fault Address Register (BFAR) valid flag */ +#define SCB_CFSR_BFARVALID (1 << 15) +/* Bits [14:13]: reserved - must be kept cleared */ +/* STKERR: Bus fault on stacking for exception entry */ +#define SCB_CFSR_STKERR (1 << 12) +/* UNSTKERR: Bus fault on unstacking for a return from exception */ +#define SCB_CFSR_UNSTKERR (1 << 11) +/* IMPRECISERR: Imprecise data bus error */ +#define SCB_CFSR_IMPRECISERR (1 << 10) +/* PRECISERR: Precise data bus error */ +#define SCB_CFSR_PRECISERR (1 << 9) +/* IBUSERR: Instruction bus error */ +#define SCB_CFSR_IBUSERR (1 << 8) +/* MMARVALID: Memory Management Fault Address Register (MMAR) valid flag */ +#define SCB_CFSR_MMARVALID (1 << 7) +/* Bits [6:5]: reserved - must be kept cleared */ +/* MSTKERR: Memory manager fault on stacking for exception entry */ +#define SCB_CFSR_MSTKERR (1 << 4) +/* MUNSTKERR: Memory manager fault on unstacking for a return from exception */ +#define SCB_CFSR_MUNSTKERR (1 << 3) +/* Bit 2: reserved - must be kept cleared */ +/* DACCVIOL: Data access violation flag */ +#define SCB_CFSR_DACCVIOL (1 << 1) +/* IACCVIOL: Instruction access violation flag */ +#define SCB_CFSR_IACCVIOL (1 << 0) + +/* --- SCB_HFSR values ----------------------------------------------------- */ + +/* DEBUG_VT: reserved for debug use */ +#define SCB_HFSR_DEBUG_VT (1 << 31) +/* FORCED: Forced hard fault */ +#define SCB_HFSR_FORCED (1 << 30) +/* Bits [29:2]: reserved - must be kept cleared */ +/* VECTTBL: Vector table hard fault */ +#define SCB_HFSR_VECTTBL (1 << 1) +/* Bit 0: reserved - must be kept cleared */ + +/* --- SCB_MMFAR values ---------------------------------------------------- */ + +/* MMFAR [31:0]: Memory management fault address */ + +/* --- SCB_BFAR values ----------------------------------------------------- */ + +/* BFAR [31:0]: Bus fault address */ + +/* --- SCB functions ------------------------------------------------------- */ +void scb_reset_core(void); +void scb_reset_system(void); + +/* TODO: */ + +#endif diff --git a/include/libopencm3/stm32/f1/systick.h b/include/libopencm3/stm32/f1/systick.h new file mode 100644 index 0000000..7c2c9a3 --- /dev/null +++ b/include/libopencm3/stm32/f1/systick.h @@ -0,0 +1,82 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_SYSTICK_H +#define LIBOPENCM3_SYSTICK_H + +#include +#include + +/* --- SYSTICK registers --------------------------------------------------- */ + +/* Control and status register (STK_CTRL) */ +#define STK_CTRL MMIO32(SYS_TICK_BASE + 0x00) + +/* reload value register (STK_LOAD) */ +#define STK_LOAD MMIO32(SYS_TICK_BASE + 0x04) + +/* current value register (STK_VAL) */ +#define STK_VAL MMIO32(SYS_TICK_BASE + 0x08) + +/* calibration value register (STK_CALIB) */ +#define STK_CALIB MMIO32(SYS_TICK_BASE + 0x0C) + +/* --- STK_CTRL values ----------------------------------------------------- */ +/* Bits [31:17] Reserved, must be kept cleared. */ +/* COUNTFLAG: */ +#define STK_CTRL_COUNTFLAG (1 << 16) +/* Bits [15:3] Reserved, must be kept cleared. */ +/* CLKSOURCE: Clock source selection */ +#define STK_CTRL_CLKSOURCE (1 << 2) +#define STK_CTRL_CLKSOURCE_LSB 2 +#define STK_CTRL_CLKSOURCE_AHB_DIV8 0 +#define STK_CTRL_CLKSOURCE_AHB 1 +/* TICKINT: SysTick exception request enable */ +#define STK_CTRL_TICKINT (1 << 1) +/* ENABLE: Counter enable */ +#define STK_CTRL_ENABLE (1 << 0) + +/* --- STK_LOAD values ----------------------------------------------------- */ +/* Bits [31:24] Reserved, must be kept cleared. */ +/* RELOAD[23:0]: RELOAD value */ + +/* --- STK_VAL values ------------------------------------------------------ */ +/* Bits [31:24] Reserved, must be kept cleared. */ +/* CURRENT[23:0]: Current counter value */ + +/* --- STK_CALIB values ---------------------------------------------------- */ +/* NOREF: NOREF flag */ +#define STK_CALIB_NOREF (1 << 31) +/* SKEW: SKEW flag */ +#define STK_CALIB_SKEW (1 << 30) +/* Bits [29:24] Reserved, must be kept cleared. */ +/* TENMS[23:0]: Calibration value */ + +/* --- Function Prototypes ------------------------------------------------- */ + +void systick_set_reload(u32 value); +u32 systick_get_value(void); +void systick_set_clocksource(u8 clocksource); +void systick_interrupt_enable(void); +void systick_interrupt_disable(void); +void systick_counter_enable(void); +void systick_counter_disable(void); +u8 systick_get_countflag(void); + +#endif diff --git a/include/libopencm3/stm32/f1/tools.h b/include/libopencm3/stm32/f1/tools.h new file mode 100644 index 0000000..ac7f0bf --- /dev/null +++ b/include/libopencm3/stm32/f1/tools.h @@ -0,0 +1,64 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Piotr Esden-Tempski + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_TOOLS_H +#define LIBOPENCM3_TOOLS_H + +/* + * Register accessors / manipulators + */ + +/* Get register content. */ +#define GET_REG(REG) ((u16) *REG) + +/* Set register content. */ +#define SET_REG(REG, VAL) (*REG = (u16)VAL) + +/* Clear register bit. */ +#define CLR_REG_BIT(REG, BIT) SET_REG(REG, (~BIT)) + +/* Clear register bit masking out some bits that must not be touched. */ +#define CLR_REG_BIT_MSK(REG, MSK, BIT) \ + SET_REG(REG, (GET_REG(REG) & MSK & (~BIT))) + +/* Get masked out bit value. */ +#define GET_REG_BIT(REG, BIT) (GET_REG(REG) & BIT) + +/* + * Set/reset a bit in a masked window by using toggle mechanism. + * + * This means that we look at the bits in the bit window designated by + * the mask. If the bit in the masked window is not matching the + * bitmask BIT then we write 1 and if the bit in the masked window is + * matching the bitmask BIT we write 0. + * + * TODO: We may need a faster implementation of that one? + */ +#define TOG_SET_REG_BIT_MSK(REG, MSK, BIT) \ +do { \ + register u16 toggle_mask = GET_REG(REG) & (MSK); \ + register u16 bit_selector; \ + for (bit_selector = 1; bit_selector; bit_selector <<= 1) { \ + if ((bit_selector & (BIT)) != 0) \ + toggle_mask ^= bit_selector; \ + } \ + SET_REG(REG, toggle_mask); \ +} while(0) + +#endif diff --git a/include/libopencm3/stm32/f1/usb.h b/include/libopencm3/stm32/f1/usb.h new file mode 100644 index 0000000..e35075d --- /dev/null +++ b/include/libopencm3/stm32/f1/usb.h @@ -0,0 +1,258 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Piotr Esden-Tempski + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_USB_H +#define LIBOPENCM3_USB_H + +#include +#include +#include + +/* --- USB base addresses -------------------------------------------------- */ + +#define USB_PMA_BASE 0x40006000L /* USB packet buffer memory base addr. */ + +/* --- USB general registers ----------------------------------------------- */ + +/* USB Control register */ +#define USB_CNTR_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x40)) +/* USB Interrupt status register */ +#define USB_ISTR_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x44)) +/* USB Frame number register */ +#define USB_FNR_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x48)) +/* USB Device address register */ +#define USB_DADDR_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x4C)) +/* USB Buffer table address register */ +#define USB_BTABLE_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x50)) +/* USB EP register */ +#define USB_EP_REG(EP) ((volatile u32 *)(USB_DEV_FS_BASE) + (EP)) + +/* --- USB control register masks / bits ----------------------------------- */ + +/* Interrupt mask bits, set to 1 to enable interrupt generation */ +#define USB_CNTR_CTRM 0x8000 +#define USB_CNTR_PMAOVRM 0x4000 +#define USB_CNTR_ERRM 0x2000 +#define USB_CNTR_WKUPM 0x1000 +#define USB_CNTR_SUSPM 0x0800 +#define USB_CNTR_RESETM 0x0400 +#define USB_CNTR_SOFM 0x0200 +#define USB_CNTR_ESOFM 0x0100 + +/* Request/Force bits */ +#define USB_CNTR_RESUME 0x0010 /* Resume request */ +#define USB_CNTR_FSUSP 0x0008 /* Force suspend */ +#define USB_CNTR_LP_MODE 0x0004 /* Low-power mode */ +#define USB_CNTR_PWDN 0x0002 /* Power down */ +#define USB_CNTR_FRES 0x0001 /* Force reset */ + +/* --- USB interrupt status register masks / bits -------------------------- */ + +#define USB_ISTR_CTR 0x8000 /* Correct Transfer */ +#define USB_ISTR_PMAOVR 0x4000 /* Packet Memory Area Over / Underrun */ +#define USB_ISTR_ERR 0x2000 /* Error */ +#define USB_ISTR_WKUP 0x1000 /* Wake up */ +#define USB_ISTR_SUSP 0x0800 /* Suspend mode request */ +#define USB_ISTR_RESET 0x0400 /* USB RESET request */ +#define USB_ISTR_SOF 0x0200 /* Start Of Frame */ +#define USB_ISTR_ESOF 0x0100 /* Expected Start Of Frame */ +#define USB_ISTR_DIR 0x0010 /* Direction of transaction */ +#define USB_ISTR_EP_ID 0x000F /* Endpoint Identifier */ + +/* --- USB interrupt status register manipulators -------------------------- */ + +/* Note: CTR is read only! */ +#define USB_CLR_ISTR_PMAOVR() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_PMAOVR) +#define USB_CLR_ISTR_ERR() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_ERR) +#define USB_CLR_ISTR_WKUP() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_WKUP) +#define USB_CLR_ISTR_SUSP() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_SUSP) +#define USB_CLR_ISTR_RESET() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_RESET) +#define USB_CLR_ISTR_SOF() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_SOF) +#define USB_CLR_ISTR_ESOF() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_ESOF) + +/* --- USB device addres register masks / bits ----------------------------- */ + +#define USB_DADDR_ENABLE 0x0080 +#define USB_DADDR_ADDR 0x007F + +/* --- USB device addres register manipulators ----------------------------- */ + +/* --- USB endpoint register offsets --------------------------------------- */ + +#define USB_EP0 0 +#define USB_EP1 1 +#define USB_EP2 2 +#define USB_EP3 3 +#define USB_EP4 4 +#define USB_EP5 5 +#define USB_EP6 6 +#define USB_EP7 7 + +/* --- USB endpoint register masks / bits ---------------------------------- */ + +/* Masks and toggle bits */ +#define USB_EP_RX_CTR 0x8000 /* Correct transfer RX */ +#define USB_EP_RX_DTOG 0x4000 /* Data toggle RX */ +#define USB_EP_RX_STAT 0x3000 /* Endpoint status for RX */ + +#define USB_EP_SETUP 0x0800 /* Setup transaction completed */ +#define USB_EP_TYPE 0x0600 /* Endpoint type */ +#define USB_EP_KIND 0x0100 /* Endpoint kind. + * When set and type=bulk -> double buffer + * When set and type=control -> status out + */ + +#define USB_EP_TX_CTR 0x0080 /* Correct transfer TX */ +#define USB_EP_TX_DTOG 0x0040 /* Data toggle TX */ +#define USB_EP_TX_STAT 0x0030 /* Endpoint status for TX */ + +#define USB_EP_ADDR 0x000F /* Endpoint Address */ + +/* Masking all toggle bits */ +#define USB_EP_NTOGGLE_MSK (USB_EP_RX_CTR | \ + USB_EP_SETUP | \ + USB_EP_TYPE | \ + USB_EP_KIND | \ + USB_EP_TX_CTR | \ + USB_EP_ADDR) + +/* All non toggle bits plus EP_RX toggle bits */ +#define USB_EP_RX_STAT_TOG_MSK (USB_EP_RX_STAT | USB_EP_NTOGGLE_MSK) +/* All non toggle bits plus EP_TX toggle bits */ +#define USB_EP_TX_STAT_TOG_MSK (USB_EP_TX_STAT | USB_EP_NTOGGLE_MSK) + +/* Endpoint status bits for USB_EP_RX_STAT bit field */ +#define USB_EP_RX_STAT_DISABLED 0x0000 +#define USB_EP_RX_STAT_STALL 0x1000 +#define USB_EP_RX_STAT_NAK 0x2000 +#define USB_EP_RX_STAT_VALID 0x3000 + +/* Endpoint status bits for USB_EP_TX_STAT bit field */ +#define USB_EP_TX_STAT_DISABLED 0x0000 +#define USB_EP_TX_STAT_STALL 0x0010 +#define USB_EP_TX_STAT_NAK 0x0020 +#define USB_EP_TX_STAT_VALID 0x0030 + +/* Endpoint type bits for USB_EP_TYPE bit field */ +#define USB_EP_TYPE_BULK 0x0000 +#define USB_EP_TYPE_CONTROL 0x0200 +#define USB_EP_TYPE_ISO 0x0400 +#define USB_EP_TYPE_INTERRUPT 0x0600 + +/* --- USB endpoint register manipulators ---------------------------------- */ + +/* + * Set USB endpoint tx/rx status. + * + * USB status field is changed using an awkward toggle mechanism, that + * is why we use some helper macros for that. + */ +#define USB_SET_EP_RX_STAT(EP, STAT) \ + TOG_SET_REG_BIT_MSK(USB_EP_REG(EP), USB_EP_RX_STAT_TOG_MSK, STAT) + +#define USB_SET_EP_TX_STAT(EP, STAT) \ + TOG_SET_REG_BIT_MSK(USB_EP_REG(EP), USB_EP_TX_STAT_TOG_MSK, STAT) + +/* + * Macros for clearing and setting USB endpoint register bits that do + * not use the toggle mechanism. + * + * Because the register contains some bits that use the toggle + * mechanism we need a helper macro here. Otherwise the code gets really messy. + */ +#define USB_CLR_EP_NTOGGLE_BIT(EP, BIT) \ + CLR_REG_BIT_MSK(USB_EP_REG(EP), USB_EP_NTOGGLE_MSK, BIT) + +#define USB_CLR_EP_RX_CTR(EP) \ + USB_CLR_EP_NTOGGLE_BIT(EP, USB_EP_RX_CTR) + +#define USB_CLR_EP_TX_CTR(EP) \ + USB_CLR_EP_NTOGGLE_BIT(EP, USB_EP_TX_CTR) + +#define USB_SET_EP_TYPE(EP, TYPE) \ + SET_REG(USB_EP_REG(EP), \ + (GET_REG(USB_EP_REG(EP)) & \ + (USB_EP_NTOGGLE_MSK & \ + (~USB_EP_TYPE))) | TYPE) + +#define USB_SET_EP_KIND(EP) \ + SET_REG(USB_EP_REG(EP), \ + (GET_REG(USB_EP_REG(EP)) & \ + (USB_EP_NTOGGLE_MSK & \ + (~USB_EP_KIND))) | USB_EP_KIND) + +#define USB_CLR_EP_KIND(EP) \ + SET_REG(USB_EP_REG(EP), \ + (GET_REG(USB_EP_REG(EP)) & \ + (USB_EP_NTOGGLE_MSK & (~USB_EP_KIND)))) + +#define USB_SET_EP_STAT_OUT(EP) USB_SET_EP_KIND(EP) +#define USB_CLR_EP_STAT_OUT(EP) USB_CLR_EP_KIND(EP) + +#define USB_SET_EP_ADDR(EP, ADDR) \ + SET_REG(USB_EP_REG(EP), \ + ((GET_REG(USB_EP_REG(EP)) & \ + (USB_EP_NTOGGLE_MSK & \ + (~USB_EP_ADDR))) | ADDR)) + +/* Macros for clearing DTOG bits */ +#define USB_CLR_EP_TX_DTOG(EP) \ + SET_REG(USB_EP_REG(EP), \ + GET_REG(USB_EP_REG(EP)) & \ + (USB_EP_NTOGGLE_MSK | USB_EP_TX_DTOG)) + +#define USB_CLR_EP_RX_DTOG(EP) \ + SET_REG(USB_EP_REG(EP), \ + GET_REG(USB_EP_REG(EP)) & \ + (USB_EP_NTOGGLE_MSK | USB_EP_RX_DTOG)) + +/* --- USB BTABLE registers ------------------------------------------------ */ + +#define USB_GET_BTABLE GET_REG(USB_BTABLE_REG) + +#define USB_EP_TX_ADDR(EP) \ + ((u32 *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 0) * 2)) + +#define USB_EP_TX_COUNT(EP) \ + ((u32 *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 2) * 2)) + +#define USB_EP_RX_ADDR(EP) \ + ((u32 *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 4) * 2)) + +#define USB_EP_RX_COUNT(EP) \ + ((u32 *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 6) * 2)) + +/* --- USB BTABLE manipulators --------------------------------------------- */ + +#define USB_GET_EP_TX_ADDR(EP) GET_REG(USB_EP_TX_ADDR(EP)) +#define USB_GET_EP_TX_COUNT(EP) GET_REG(USB_EP_TX_COUNT(EP)) +#define USB_GET_EP_RX_ADDR(EP) GET_REG(USB_EP_RX_ADDR(EP)) +#define USB_GET_EP_RX_COUNT(EP) GET_REG(USB_EP_RX_COUNT(EP)) +#define USB_SET_EP_TX_ADDR(EP, ADDR) SET_REG(USB_EP_TX_ADDR(EP), ADDR) +#define USB_SET_EP_TX_COUNT(EP, COUNT) SET_REG(USB_EP_TX_COUNT(EP), COUNT) +#define USB_SET_EP_RX_ADDR(EP, ADDR) SET_REG(USB_EP_RX_ADDR(EP), ADDR) +#define USB_SET_EP_RX_COUNT(EP, COUNT) SET_REG(USB_EP_RX_COUNT(EP), COUNT) + +#define USB_GET_EP_TX_BUFF(EP) \ + (USB_PMA_BASE + (u8 *)(USB_GET_EP_TX_ADDR(EP) * 2)) + +#define USB_GET_EP_RX_BUFF(EP) \ + (USB_PMA_BASE + (u8 *)(USB_GET_EP_RX_ADDR(EP) * 2)) + +#endif diff --git a/include/libopencm3/stm32/f1/usb_desc.h b/include/libopencm3/stm32/f1/usb_desc.h new file mode 100644 index 0000000..da99bb0 --- /dev/null +++ b/include/libopencm3/stm32/f1/usb_desc.h @@ -0,0 +1,101 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Piotr Esden-Tempski + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_USB_DESC +#define LIBOPENCM3_USB_DESC + +/* Descriptor types */ +#define USB_DT_DEVICE 0x01 +#define USB_DT_CONF 0x02 +#define USB_DT_STRING 0x03 +#define USB_DT_INTERFACE 0x04 +#define USB_DT_ENDPOINT 0x05 + +struct usb_desc_head { + u8 length; /* Descriptor size 0x012 */ + u8 type; /* Descriptor type ID */ +}; + +struct usb_device_desc { + struct usb_desc_head h; /* Size 0x12, ID 0x01 */ + u16 bcd_usb; /* USB Version */ + u8 class; /* Device class */ + u8 sub_class; /* Subclass code */ + u8 protocol; /* Protocol code */ + u8 max_psize; /* Maximum packet size -> 64bytes */ + u16 vendor; /* Vendor number */ + u16 product; /* Device number */ + u16 bcd_dev; /* Device version */ + u8 man_desc; /* Index of manufacturer string desc */ + u8 prod_desc; /* Index of product string desc */ + u8 sn_desc; /* Index of serial number string desc */ + u8 num_conf; /* Number of possible configurations */ +}; + +struct usb_conf_desc_header { + struct usb_desc_head h; /* Size 0x09, Id 0x02 */ + u16 tot_leng; /* Total length of data */ + u8 num_int; /* Number of interfaces */ + u8 conf_val; /* Configuration selector */ + u8 conf_desc; /* Index of conf string desc */ + u8 attr; /* Attribute bitmap: + * 7 : Bus powered + * 6 : Self powered + * 5 : Remote wakeup + * 4..0 : Reserved -> 0000 + */ + u8 max_power; /* Maximum power consumption in 2mA steps */ +}; + +struct usb_int_desc_header { + struct usb_desc_head h; /* Size 0x09, Id 0x04 */ + u8 iface_num; /* Interface id number */ + u8 alt_setting; /* Alternative setting selector */ + u8 num_endp; /* Endpoints used */ + u8 class; /* Interface class */ + u8 sub_class; /* Subclass code */ + u8 protocol; /* Protocol code */ + u8 iface_desc; /* Index of interface string desc */ +}; + +struct usb_ep_desc { + struct usb_desc_head h; /* Size 0x07, Id 0x05 */ + u8 ep_addr; /* Endpoint address: + 0..3 : Endpoint Number + 4..6 : Reserved -> 0 + 7 : Direction 0=out 1=in */ + u8 ep_attr; /* Endpoint attributes */ + u16 max_psize; /* Maximum packet size -> 64bytes */ + u8 interval; /* Interval for polling endpoint + data. Ignored for bulk & control + endpoints. */ +}; + +struct usb_conf_desc { + struct usb_conf_desc_header cdh; + struct usb_int_desc_header idh; + struct usb_ep_desc ep[]; +}; + +struct usb_string_desc { + struct usb_desc_head h; /* Size > 0x02, Id 0x03 */ + u16 string[]; /* String UTF16 encoded */ +}; + +#endif diff --git a/include/libopencm3/stm32/f2/memorymap.h b/include/libopencm3/stm32/f2/memorymap.h new file mode 100644 index 0000000..9fe77fa --- /dev/null +++ b/include/libopencm3/stm32/f2/memorymap.h @@ -0,0 +1,131 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Fergus Noble + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_MEMORYMAP_H +#define LIBOPENCM3_MEMORYMAP_H + +#include + +/* --- STM32F20x specific peripheral definitions ------------------------------- */ + +/* Memory map for all busses */ +#define PERIPH_BASE 0x40000000 +#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000) +#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000) +#define PERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000) +#define PERIPH_BASE_AHB2 0x50000000 +#define PERIPH_BASE_AHB3 0x60000000 + +/* Register boundary addresses */ + +/* APB1 */ +#define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000) +#define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400) +#define TIM4_BASE (PERIPH_BASE_APB1 + 0x0800) +#define TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00) +#define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000) +#define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400) +#define TIM12_BASE (PERIPH_BASE_APB1 + 0x1800) +#define TIM13_BASE (PERIPH_BASE_APB1 + 0x1c00) +#define TIM14_BASE (PERIPH_BASE_APB1 + 0x2000) +/* PERIPH_BASE_APB1 + 0x2400 (0x4000 2400 - 0x4000 27FF): Reserved */ +#define RTC_BASE (PERIPH_BASE_APB1 + 0x2800) +#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00) +#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000) +/* PERIPH_BASE_APB1 + 0x3400 (0x4000 3400 - 0x4000 37FF): Reserved */ +#define SPI2_I2S_BASE (PERIPH_BASE_APB1 + 0x3800) +#define SPI3_I2S_BASE (PERIPH_BASE_APB1 + 0x3c00) +/* PERIPH_BASE_APB1 + 0x4000 (0x4000 4000 - 0x4000 3FFF): Reserved */ +#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400) +#define USART3_BASE (PERIPH_BASE_APB1 + 0x4800) +#define UART4_BASE (PERIPH_BASE_APB1 + 0x4c00) +#define UART5_BASE (PERIPH_BASE_APB1 + 0x5000) +#define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400) +#define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800) +#define I2C3_BASE (PERIPH_BASE_APB1 + 0x5C00) +/* PERIPH_BASE_APB1 + 0x6000 (0x4000 6000 - 0x4000 63FF): Reserved */ +#define BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400) +#define BX_CAN2_BASE (PERIPH_BASE_APB1 + 0x6800) +/* PERIPH_BASE_APB1 + 0x6C00 (0x4000 6C00 - 0x4000 6FFF): Reserved */ +#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000) +#define DAC_BASE (PERIPH_BASE_APB1 + 0x7400) +/* PERIPH_BASE_APB1 + 0x7800 (0x4000 7800 - 0x4000 FFFF): Reserved */ + +/* APB2 */ +#define TIM1_BASE (PERIPH_BASE_APB2 + 0x0000) +#define TIM8_BASE (PERIPH_BASE_APB2 + 0x0400) +/* PERIPH_BASE_APB2 + 0x0800 (0x4001 0800 - 0x4001 0FFF): Reserved */ +#define USART1_BASE (PERIPH_BASE_APB2 + 0x1000) +#define USART6_BASE (PERIPH_BASE_APB2 + 0x1400) +/* PERIPH_BASE_APB2 + 0x1800 (0x4001 1800 - 0x4001 1FFF): Reserved */ +#define ADC1_BASE (PERIPH_BASE_APB2 + 0x2000) +#define ADC2_BASE (PERIPH_BASE_APB2 + 0x2000) +#define ADC3_BASE (PERIPH_BASE_APB2 + 0x2000) +/* PERIPH_BASE_APB2 + 0x2400 (0x4001 2400 - 0x4001 27FF): Reserved */ +#define SDIO_BASE (PERIPH_BASE_APB2 + 0x2800) +/* PERIPH_BASE_APB2 + 0x2C00 (0x4001 2C00 - 0x4001 2FFF): Reserved */ +#define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000) +/* PERIPH_BASE_APB2 + 0x3400 (0x4001 3400 - 0x4001 37FF): Reserved */ +#define SYSCFG_BASE (PERIPH_BASE_APB2 + 0x3800) +#define EXTI_BASE (PERIPH_BASE_APB2 + 0x3C00) +#define TIM9_BASE (PERIPH_BASE_APB2 + 0x4000) +#define TIM10_BASE (PERIPH_BASE_APB2 + 0x4400) +#define TIM11_BASE (PERIPH_BASE_APB2 + 0x4800) +/* PERIPH_BASE_APB2 + 0x4C00 (0x4001 4C00 - 0x4001 FFFF): Reserved */ + +/* AHB1 */ +#define GPIO_PORT_A_BASE (PERIPH_BASE_AHB1 + 0x0000) +#define GPIO_PORT_B_BASE (PERIPH_BASE_AHB1 + 0x0400) +#define GPIO_PORT_C_BASE (PERIPH_BASE_AHB1 + 0x0800) +#define GPIO_PORT_D_BASE (PERIPH_BASE_AHB1 + 0x0C00) +#define GPIO_PORT_E_BASE (PERIPH_BASE_AHB1 + 0x1000) +#define GPIO_PORT_F_BASE (PERIPH_BASE_AHB1 + 0x1400) +#define GPIO_PORT_G_BASE (PERIPH_BASE_AHB1 + 0x1800) +#define GPIO_PORT_H_BASE (PERIPH_BASE_AHB1 + 0x1C00) +#define GPIO_PORT_I_BASE (PERIPH_BASE_AHB1 + 0x2000) +/* PERIPH_BASE_AHB1 + 0x2400 (0x4002 2400 - 0x4002 2FFF): Reserved */ +#define CRC_BASE (PERIPH_BASE_AHB1 + 0x3000) +/* PERIPH_BASE_AHB1 + 0x3400 (0x4002 3400 - 0x4002 37FF): Reserved */ +#define RCC_BASE (PERIPH_BASE_AHB1 + 0x3800) +#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x3C00) +#define BKPSRAM_BASE (PERIPH_BASE_AHB1 + 0x4000) +/* PERIPH_BASE_AHB1 + 0x5000 (0x4002 5000 - 0x4002 5FFF): Reserved */ +#define DMA1_BASE (PERIPH_BASE_AHB1 + 0x6000) +#define DMA2_BASE (PERIPH_BASE_AHB1 + 0x6400) +/* PERIPH_BASE_AHB1 + 0x6800 (0x4002 6800 - 0x4002 7FFF): Reserved */ +#define ETHERNET_BASE (PERIPH_BASE_AHB1 + 0x8000) +/* PERIPH_BASE_AHB1 + 0x9400 (0x4002 9400 - 0x4003 FFFF): Reserved */ +#define USB_OTG_HS_BASE (PERIPH_BASE_AHB1 + 0x20000) +/* PERIPH_BASE_AHB1 + 0x60000 (0x4008 0000 - 0x4FFF FFFF): Reserved */ + +/* AHB2 */ +#define USB_OTG_FS_BASE (PERIPH_BASE_AHB2 + 0x0000) +/* PERIPH_BASE_AHB2 + 0x40000 (0x5004 0000 - 0x5004 FFFF): Reserved */ +#define DCMI_BASE (PERIPH_BASE_AHB2 + 0x50000) +/* PERIPH_BASE_AHB2 + 0x50400 (0x5005 0400 - 0x5006 07FF): Reserved */ +#define RNG_BASE (PERIPH_BASE_AHB2 + 0x60800) +/* PERIPH_BASE_AHB2 + 0x61000 (0x5006 1000 - 0x5FFF FFFF): Reserved */ + +/* AHB3 */ +#define FSMC_BASE (PERIPH_BASE_AHB3 + 0x40000000) + +/* PPIB */ +#define DBGMCU_BASE (PPBI_BASE + 0x00042000) + +#endif diff --git a/include/libopencm3/stm32/f2/pwr.h b/include/libopencm3/stm32/f2/pwr.h new file mode 100644 index 0000000..7cf8dab --- /dev/null +++ b/include/libopencm3/stm32/f2/pwr.h @@ -0,0 +1,40 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Fergus Noble + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_PWR_F2_H +#define LIBOPENCM3_PWR_F2_H + +#include + +/* + * This file extends the version in stm_common with definitions only + * applicable to the STM32F2 series of devices. + */ + +/* --- PWR_CR values ------------------------------------------------------- */ + +/* FPDS: Flash power down in stop mode, only available in F2 family devices. */ +#define PWR_CR_FPDS (1 << 9) + +/* --- PWR_CSR values ------------------------------------------------------ */ + +/* BRE: Backup regulator enable */ +#define PWR_CSR_BRE (1 << 9) + +#endif diff --git a/include/libopencm3/stm32/f2/spi.h b/include/libopencm3/stm32/f2/spi.h new file mode 100644 index 0000000..62550cf --- /dev/null +++ b/include/libopencm3/stm32/f2/spi.h @@ -0,0 +1,42 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Fergus Noble + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_SPI_F2_H +#define LIBOPENCM3_SPI_F2_H + +#include + +/* + * This file extends the version in stm_common with definitions only + * applicable to the STM32F2 series of devices. + */ + +/* --- SPI_CR2 values ------------------------------------------------------ */ + +/* FRF: Frame format. */ +#define SPI_CR2_FRF (1 << 4) +#define SPI_CR2_FRF_TI (1 << 4) +#define SPI_CR2_FRF_MOTOROLA (1 << 4) + +/* --- SPI_SR values ------------------------------------------------------- */ + +/* TIFRFE: TI frame format error. */ +#define SPI_SR_RXNE (1 << 0) + +#endif diff --git a/include/libopencm3/stm32/f2/timer.h b/include/libopencm3/stm32/f2/timer.h new file mode 100644 index 0000000..f7c82ae --- /dev/null +++ b/include/libopencm3/stm32/f2/timer.h @@ -0,0 +1,54 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Fergus Noble + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_TIMER_F2_H +#define LIBOPENCM3_TIMER_F2_H + +#include + + +/* + * TIM2 and TIM5 are now 32bit and the following registers are now 32-bit wide: + * CNT, ARR, CCR1, CCR2, CCR3, CCR4 + */ + +/* Timer 2/5 option register (TIMx_OR) */ +#define TIM_OR(tim_base) MMIO32(tim_base + 0x50) +#define TIM2_OR TIM_OR(TIM2) +#define TIM5_OR TIM_OR(TIM5) + +/* --- TIM2_OR values ---------------------------------------------------- */ + +/* MOE: Main output enable */ +#define TIM2_OR_ITR1_RMP_TIM8_TRGOUT (0x0 << 10) +#define TIM2_OR_ITR1_RMP_PTP (0x1 << 10) +#define TIM2_OR_ITR1_RMP_OTG_FS_SOF (0x2 << 10) +#define TIM2_OR_ITR1_RMP_OTG_HS_SOF (0x3 << 10) +#define TIM2_OR_ITR1_RMP_MASK (0x3 << 10) + +/* --- TIM5_OR values ---------------------------------------------------- */ + +/* MOE: Main output enable */ +#define TIM5_OR_TI4_RMP_GPIO (0x0 << 6) +#define TIM5_OR_TI4_RMP_LSI (0x1 << 6) +#define TIM5_OR_TI4_RMP_LSE (0x2 << 6) +#define TIM5_OR_TI4_RMP_RTC (0x3 << 6) +#define TIM5_OR_TI4_RMP_MASK (0x3 << 6) + +#endif diff --git a/include/libopencm3/stm32/f2/usart.h b/include/libopencm3/stm32/f2/usart.h new file mode 100644 index 0000000..1baf5a1 --- /dev/null +++ b/include/libopencm3/stm32/f2/usart.h @@ -0,0 +1,35 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Fergus Noble + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_USART_F2_H +#define LIBOPENCM3_USART_F2_H + +#include + +/* --- USART_CR1 values ---------------------------------------------------- */ + +/* OVER8: Oversampling mode */ +#define USART_CR1_OVER8 (1 << 15) + +/* --- USART_CR3 values ---------------------------------------------------- */ + +/* ONEBIT: One sample bit method enable */ +#define USART_CR3_ONEBIT (1 << 11) + +#endif diff --git a/include/libopencm3/stm32/fsmc.h b/include/libopencm3/stm32/fsmc.h new file mode 100644 index 0000000..1d318e3 --- /dev/null +++ b/include/libopencm3/stm32/fsmc.h @@ -0,0 +1,284 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_FSMC_H +#define LIBOPENCM3_FSMC_H + +#include +#include + +/* --- Convenience macros -------------------------------------------------- */ + +/* TODO: Move to memorymap.h? */ +#define FSMC_BASE 0xa0000000 + +#define FSMC_BANK1_BASE 0x60000000 /* NOR / PSRAM */ +#define FSMC_BANK2_BASE 0x70000000 /* NAND flash */ +#define FSMC_BANK3_BASE 0x80000000 /* NAND flash */ +#define FSMC_BANK4_BASE 0x90000000 /* PC card */ + +/* --- FSMC registers ------------------------------------------------------ */ + +/* SRAM/NOR-Flash chip-select control registers 1..4 (FSMC_BCRx) */ +#define FSMC_BCR(x) MMIO32(FSMC_BASE + 0x00 + 8 * x) +#define FSMC_BCR1 FSMC_BCR(0) +#define FSMC_BCR2 FSMC_BCR(1) +#define FSMC_BCR3 FSMC_BCR(2) +#define FSMC_BCR4 FSMC_BCR(3) + +/* SRAM/NOR-Flash chip-select timing registers 1..4 (FSMC_BTRx) */ +#define FSMC_BTR(x) MMIO32(FSMC_BASE + 0x04 + 8 * x) +#define FSMC_BTR1 FSMC_BTR(0) +#define FSMC_BTR2 FSMC_BTR(1) +#define FSMC_BTR3 FSMC_BTR(2) +#define FSMC_BTR4 FSMC_BTR(3) + +/* SRAM/NOR-Flash write timing registers 1..4 (FSMC_BWTRx) */ +#define FSMC_BWTR(x) MMIO32(FSMC_BASE + 0x104 + 8 * x) +#define FSMC_BWTR1 FSMC_BWTR(0) +#define FSMC_BWTR2 FSMC_BWTR(1) +#define FSMC_BWTR3 FSMC_BWTR(2) +#define FSMC_BWTR4 FSMC_BWTR(3) + +/* PC Card/NAND Flash control registers 2..4 (FSMC_PCRx) */ +#define FSMC_PCR(x) MMIO32(FSMC_BASE + 0x40 + 0x20 * x) +#define FSMC_PCR2 FSMC_PCR(1) +#define FSMC_PCR3 FSMC_PCR(2) +#define FSMC_PCR4 FSMC_PCR(3) + +/* FIFO status and interrupt registers 2..4 (FSMC_SRx) */ +#define FSMC_SR(x) MMIO32(FSMC_BASE + 0x44 + 0x20 * x) +#define FSMC_SR2 FSMC_SR(1) +#define FSMC_SR3 FSMC_SR(2) +#define FSMC_SR4 FSMC_SR(3) + +/* Common memory space timing registers 2..4 (FSMC_PMEMx) */ +#define FSMC_PMEM(x) MMIO32(FSMC_BASE + 0x48 + 0x20 * x) +#define FSMC_PMEM2 FSMC_PMEM(1) +#define FSMC_PMEM3 FSMC_PMEM(2) +#define FSMC_PMEM4 FSMC_PMEM(3) + +/* Attribute memory space timing registers 2..4 (FSMC_PATTx) */ +#define FSMC_PATT(x) MMIO32(FSMC_BASE + 0x4c + 0x20 * x) +#define FSMC_PATT2 FSMC_PATT(1) +#define FSMC_PATT3 FSMC_PATT(2) +#define FSMC_PATT4 FSMC_PATT(3) + +/* I/O space timing register 4 (FSMC_PIO4) */ +#define FSMC_PIO4 MMIO32(FSMC_BASE + 0xb0) + +/* ECC result registers 2/3 (FSMC_ECCRx) */ +#define FSMC_ECCR(x) MMIO32(FSMC_BASE + 0x54 + 0x20 * x) +#define FSMC_ECCR2 FSMC_ECCR(1) +#define FSMC_ECCR3 FSMC_ECCR(2) + +/* --- FSMC_BCRx values ---------------------------------------------------- */ + +/* CBURSTRW: Write burst enable */ +#define FSMC_BCR_CBURSTRW (1 << 19) + +/* Bits 18..16: Reserved. */ + +/* ASYNCWAIT: Wait signal during asynchronous transfers */ +#define FSMC_BCR_ASYNCWAIT (1 << 15) + +/* EXTMOD: Extended mode enable */ +#define FSMC_BCR_EXTMOD (1 << 14) + +/* WAITEN: Wait enable bit */ +#define FSMC_BCR_WAITEN (1 << 13) + +/* WREN: Write enable bit */ +#define FSMC_BCR_WREN (1 << 12) + +/* WAITCFG: Wait timing configuration */ +#define FSMC_BCR_WAITCFG (1 << 11) + +/* WRAPMOD: Wrapped burst mode support */ +#define FSMC_BCR_WRAPMOD (1 << 10) + +/* WAITPOL: Wait signal polarity bit */ +#define FSMC_BCR_WAITPOL (1 << 9) + +/* BURSTEN: Burst enable bit */ +#define FSMC_BCR_BURSTEN (1 << 8) + +/* Bit 7: Reserved. */ + +/* FACCEN: Flash access enable */ +#define FSMC_BCR_FACCEN (1 << 6) + +/* MWID[5:4]: Memory databus width */ +#define FSMC_BCR_MWID (1 << 4) + +/* MTYP[3:2]: Memory type */ +#define FSMC_BCR_MTYP (1 << 2) + +/* MUXEN: Address/data multiplexing enable bit */ +#define FSMC_BCR_MUXEN (1 << 1) + +/* MBKEN: Memory bank enable bit */ +#define FSMC_BCR_MBKEN (1 << 0) + +/* --- FSMC_BTRx values ---------------------------------------------------- */ + +/* ACCMOD[29:28]: Access mode */ +#define FSMC_BTR_ACCMOD (1 << 28) + +/* DATLAT[27:24]: Data latency (for synchronous burst NOR flash) */ +#define FSMC_BTR_DATLAT (1 << 24) + +/* CLKDIV[23:20]: Clock divide ratio (for CLK signal) */ +#define FSMC_BTR_CLKDIV (1 << 20) + +/* BUSTURN[19:16]: Bus turnaround phase duration */ +#define FSMC_BTR_BUSTURN (1 << 16) + +/* DATAST[15:8]: Data-phase duration */ +#define FSMC_BTR_DATAST (1 << 8) + +/* ADDHLD[7:4]: Address-hold phase duration */ +#define FSMC_BTR_ADDHLD (1 << 4) + +/* ADDSET[3:0]: Address setup phase duration */ +#define FSMC_BTR_ADDSET (1 << 0) + +/* --- FSMC_BWTRx values --------------------------------------------------- */ + +/* ACCMOD[29:28]: Access mode */ +#define FSMC_BWTR_ACCMOD (1 << 28) + +/* DATLAT[27:24]: Data latency (for synchronous burst NOR Flash) */ +#define FSMC_BWTR_DATLAT (1 << 24) + +/* CLKDIV[23:20]: Clock divide ratio (for CLK signal) */ +#define FSMC_BWTR_CLKDIV (1 << 20) + +/* Bits 19..16: Reserved. */ + +/* DATAST[15:8]: Data-phase duration */ +#define FSMC_BWTR_DATAST (1 << 8) + +/* ADDHLD[7:4]: Address-hold phase duration */ +#define FSMC_BWTR_ADDHLD (1 << 4) + +/* ADDSET[3:0]: Address setup phase duration */ +#define FSMC_BWTR_ADDSET (1 << 0) + +/* --- FSMC_PCRx values ---------------------------------------------------- */ + +/* ECCPS[19:17]: ECC page size */ +#define FSMC_PCR_ECCPS (1 << 17) + +/* TAR[16:13]: ALE to RE delay */ +#define FSMC_PCR_TAR (1 << 13) + +/* TCLR[12:9]: CLE to RE delay */ +#define FSMC_PCR_TCLR (1 << 9) + +/* Bits 8..7: Reserved. */ + +/* ECCEN: ECC computation logic enable bit */ +#define FSMC_PCR_ECCEN (1 << 6) + +/* PWID[5:4]: Databus width */ +#define FSMC_PCR_PWID (1 << 4) + +/* PTYP: Memory type */ +#define FSMC_PCR_PTYP (1 << 3) + +/* PBKEN: PC Card/NAND Flash memory bank enable bit */ +#define FSMC_PCR_PBKEN (1 << 2) + +/* PWAITEN: Wait feature enable bit */ +#define FSMC_PCR_PWAITEN (1 << 1) + +/* Bit 0: Reserved. */ + +/* --- FSMC_SRx values ----------------------------------------------------- */ + +/* FEMPT: FIFO empty */ +#define FSMC_SR_FEMPT (1 << 6) + +/* IFEN: Interrupt falling edge detection enable bit */ +#define FSMC_SR_IFEN (1 << 5) + +/* ILEN: Interrupt high-level detection enable bit */ +#define FSMC_SR_ILEN (1 << 4) + +/* IREN: Interrupt rising edge detection enable bit */ +#define FSMC_SR_IREN (1 << 3) + +/* IFS: Interrupt falling edge status */ +#define FSMC_SR_IFS (1 << 2) + +/* ILS: Interrupt high-level status */ +#define FSMC_SR_ILS (1 << 1) + +/* IRS: Interrupt rising edge status */ +#define FSMC_SR_IRS (1 << 0) + +/* --- FSMC_PMEMx values --------------------------------------------------- */ + +/* MEMHIZx[31:24]: Common memory x databus HiZ time */ +#define FSMC_PMEM_MEMHIZX (1 << 24) + +/* MEMHOLDx[23:16]: Common memory x hold time */ +#define FSMC_PMEM_MEMHOLDX (1 << 16) + +/* MEMWAITx[15:8]: Common memory x wait time */ +#define FSMC_PMEM_MEMHOLDX (1 << 8) + +/* MEMSETx[7:0]: Common memory x setup time */ +#define FSMC_PMEM_MEMSETX (1 << 0) + +/* --- FSMC_PATTx values --------------------------------------------------- */ + +/* ATTHIZx[31:24]: Attribute memory x databus HiZ time */ +#define FSMC_PATT_ATTHIZX (1 << 24) + +/* ATTHOLDx[23:16]: Attribute memory x hold time */ +#define FSMC_PATT_ATTHOLDX (1 << 16) + +/* ATTWAITx[15:8]: Attribute memory x wait time */ +#define FSMC_PATT_ATTWAITX (1 << 8) + +/* ATTSETx[7:0]: Attribute memory x setup time */ +#define FSMC_PATT_ATTSETX (1 << 0) + +/* --- FSMC_PIO4 values ---------------------------------------------------- */ + +/* IOHIZx[31:24]: I/O x databus HiZ time */ +#define FSMC_PIO4_IOHIZX (1 << 24) + +/* IOHOLDx[23:16]: I/O x hold time */ +#define FSMC_PIO4_IOHOLDX (1 << 16) + +/* IOWAITx[15:8]: I/O x wait time */ +#define FSMC_PIO4_IOWAITX (1 << 8) + +/* IOSETx[7:0]: I/O x setup time */ +#define FSMC_PIO4_IOSETX (1 << 0) + +/* --- FSMC_ECCRx values --------------------------------------------------- */ + +/* ECCx[31:0]: ECC result */ +#define FSMC_ECCR_ECCX (1 << 0) + +#endif diff --git a/include/libopencm3/stm32/i2c.h b/include/libopencm3/stm32/i2c.h new file mode 100644 index 0000000..d182f4e --- /dev/null +++ b/include/libopencm3/stm32/i2c.h @@ -0,0 +1,333 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_I2C_H +#define LIBOPENCM3_I2C_H + +#include +#include + +/* --- Convenience macros -------------------------------------------------- */ + +/* I2C register base adresses (for convenience) */ +#define I2C1 I2C1_BASE +#define I2C2 I2C2_BASE + +/* --- I2C registers ------------------------------------------------------- */ + +/* Control register 1 (I2Cx_CR1) */ +#define I2C_CR1(i2c_base) MMIO32(i2c_base + 0x00) +#define I2C1_CR1 I2C_CR1(I2C1) +#define I2C2_CR1 I2C_CR1(I2C2) + +/* Control register 2 (I2Cx_CR2) */ +#define I2C_CR2(i2c_base) MMIO32(i2c_base + 0x04) +#define I2C1_CR2 I2C_CR2(I2C1) +#define I2C2_CR2 I2C_CR2(I2C2) + +/* Own address register 1 (I2Cx_OAR1) */ +#define I2C_OAR1(i2c_base) MMIO32(i2c_base + 0x08) +#define I2C1_OAR1 I2C_OAR1(I2C1) +#define I2C2_OAR1 I2C_OAR1(I2C2) + +/* Own address register 2 (I2Cx_OAR2) */ +#define I2C_OAR2(i2c_base) MMIO32(i2c_base + 0x0c) +#define I2C1_OAR2 I2C_OAR2(I2C1) +#define I2C2_OAR2 I2C_OAR2(I2C2) + +/* Data register (I2Cx_DR) */ +#define I2C_DR(i2c_base) MMIO32(i2c_base + 0x10) +#define I2C1_DR I2C_DR(I2C1) +#define I2C2_DR I2C_DR(I2C2) + +/* Status register 1 (I2Cx_SR1) */ +#define I2C_SR1(i2c_base) MMIO32(i2c_base + 0x14) +#define I2C1_SR1 I2C_SR1(I2C1) +#define I2C2_SR1 I2C_SR1(I2C2) + +/* Status register 2 (I2Cx_SR2) */ +#define I2C_SR2(i2c_base) MMIO32(i2c_base + 0x18) +#define I2C1_SR2 I2C_SR2(I2C1) +#define I2C2_SR2 I2C_SR2(I2C2) + +/* Clock control register (I2Cx_CCR) */ +#define I2C_CCR(i2c_base) MMIO32(i2c_base + 0x1c) +#define I2C1_CCR I2C_CCR(I2C1) +#define I2C2_CCR I2C_CCR(I2C2) + +/* TRISE register (I2Cx_CCR) */ +#define I2C_TRISE(i2c_base) MMIO32(i2c_base + 0x20) +#define I2C1_TRISE I2C_TRISE(I2C1) +#define I2C2_TRISE I2C_TRISE(I2C2) + +/* --- I2Cx_CR1 values ----------------------------------------------------- */ + +/* SWRST: Software reset */ +#define I2C_CR1_SWRST (1 << 15) + +/* Note: Bit 14 is reserved, and forced to 0 by hardware. */ + +/* ALERT: SMBus alert */ +#define I2C_CR1_ALERT (1 << 13) + +/* PEC: Packet error checking */ +#define I2C_CR1_PEC (1 << 12) + +/* POS: Acknowledge / PEC postition */ +#define I2C_CR1_POS (1 << 11) + +/* ACK: Acknowledge enable */ +#define I2C_CR1_ACK (1 << 10) + +/* STOP: STOP generation */ +#define I2C_CR1_STOP (1 << 9) + +/* START: START generation */ +#define I2C_CR1_START (1 << 8) + +/* NOSTRETCH: Clock stretching disable (slave mode) */ +#define I2C_CR1_NOSTRETCH (1 << 7) + +/* ENGC: General call enable */ +#define I2C_CR1_ENGC (1 << 6) + +/* ENPEC: Enable PEC */ +#define I2C_CR1_ENPEC (1 << 5) + +/* ENARP: ARP enable */ +#define I2C_CR1_ENARP (1 << 4) + +/* SMBTYPE: SMBus type */ +#define I2C_CR1_SMBTYPE (1 << 3) + +/* Note: Bit 2 is reserved, and forced to 0 by hardware. */ + +/* SMBUS: SMBus mode */ +#define I2C_CR1_SMBUS (1 << 1) + +/* PE: Peripheral enable */ +#define I2C_CR1_PE (1 << 0) + +/* --- I2Cx_CR2 values ----------------------------------------------------- */ + +/* Note: Bits [15:13] are reserved, and forced to 0 by hardware. */ + +/* LAST: DMA last transfer */ +#define I2C_CR2_LAST (1 << 12) + +/* DMAEN: DMA requests enable */ +#define I2C_CR2_DMAEN (1 << 11) + +/* ITBUFEN: Buffer interrupt enable */ +#define I2C_CR2_ITBUFEN (1 << 10) + +/* ITEVTEN: Event interrupt enable */ +#define I2C_CR2_ITEVTEN (1 << 9) + +/* ITERREN: Error interrupt enable */ +#define I2C_CR2_ITERREN (1 << 8) + +/* Note: Bits [7:6] are reserved, and forced to 0 by hardware. */ + +/* FREQ[5:0]: Peripheral clock frequency (valid values: 2-36 MHz) */ +#define I2C_CR2_FREQ_2MHZ 0x02 +#define I2C_CR2_FREQ_3MHZ 0x03 +#define I2C_CR2_FREQ_4MHZ 0x04 +#define I2C_CR2_FREQ_5MHZ 0x05 +#define I2C_CR2_FREQ_6MHZ 0x06 +#define I2C_CR2_FREQ_7MHZ 0x07 +#define I2C_CR2_FREQ_8MHZ 0x08 +#define I2C_CR2_FREQ_9MHZ 0x09 +#define I2C_CR2_FREQ_10MHZ 0x0a +#define I2C_CR2_FREQ_11MHZ 0x0b +#define I2C_CR2_FREQ_12MHZ 0x0c +#define I2C_CR2_FREQ_13MHZ 0x0d +#define I2C_CR2_FREQ_14MHZ 0x0e +#define I2C_CR2_FREQ_15MHZ 0x0f +#define I2C_CR2_FREQ_16MHZ 0x10 +#define I2C_CR2_FREQ_17MHZ 0x11 +#define I2C_CR2_FREQ_18MHZ 0x12 +#define I2C_CR2_FREQ_19MHZ 0x13 +#define I2C_CR2_FREQ_20MHZ 0x14 +#define I2C_CR2_FREQ_21MHZ 0x15 +#define I2C_CR2_FREQ_22MHZ 0x16 +#define I2C_CR2_FREQ_23MHZ 0x17 +#define I2C_CR2_FREQ_24MHZ 0x18 +#define I2C_CR2_FREQ_25MHZ 0x19 +#define I2C_CR2_FREQ_26MHZ 0x1a +#define I2C_CR2_FREQ_27MHZ 0x1b +#define I2C_CR2_FREQ_28MHZ 0x1c +#define I2C_CR2_FREQ_29MHZ 0x1d +#define I2C_CR2_FREQ_30MHZ 0x1e +#define I2C_CR2_FREQ_31MHZ 0x1f +#define I2C_CR2_FREQ_32MHZ 0x20 +#define I2C_CR2_FREQ_33MHZ 0x21 +#define I2C_CR2_FREQ_34MHZ 0x22 +#define I2C_CR2_FREQ_35MHZ 0x23 +#define I2C_CR2_FREQ_36MHZ 0x24 + +/* --- I2Cx_OAR1 values ---------------------------------------------------- */ + +/* ADDMODE: Addressing mode (slave mode) */ +#define I2C_OAR1_ADDMODE (1 << 15) +#define I2C_OAR1_ADDMODE_7BIT 0 +#define I2C_OAR1_ADDMODE_10BIT 1 + +/* Note: Bit 14 should always be kept at 1 by software! */ + +/* Note: Bits [13:10] are reserved, and forced to 0 by hardware. */ + +/* ADD: Address bits: [7:1] in 7-bit mode, bits [9:0] in 10-bit mode */ + +/* --- I2Cx_OAR2 values ---------------------------------------------------- */ + +/* Note: Bits [15:8] are reserved, and forced to 0 by hardware. */ + +/* ADD2[7:1]: Interface address (bits [7:1] in dual addressing mode) */ + +/* ENDUAL: Dual addressing mode enable */ +#define I2C_OAR2_ENDUAL (1 << 0) + +/* --- I2Cx_DR values ------------------------------------------------------ */ + +/* Note: Bits [15:8] are reserved, and forced to 0 by hardware. */ + +/* DR[7:0] 8-bit data register */ + +/* --- I2Cx_SR1 values ----------------------------------------------------- */ + +/* SMBALERT: SMBus alert */ +#define I2C_SR1_SMBALERT (1 << 15) + +/* TIMEOUT: Timeout or Tlow Error */ +#define I2C_SR1_TIMEOUT (1 << 14) + +/* Note: Bit 13 is reserved, and forced to 0 by hardware. */ + +/* PECERR: PEC Error in reception */ +#define I2C_SR1_PECERR (1 << 12) + +/* OVR: Overrun/Underrun */ +#define I2C_SR1_OVR (1 << 11) + +/* AF: Acknowledge failure */ +#define I2C_SR1_AF (1 << 10) + +/* ARLO: Arbitration lost (master mode) */ +#define I2C_SR1_ARLO (1 << 9) + +/* BERR: Bus error */ +#define I2C_SR1_BERR (1 << 8) + +/* TxE: Data register empty (transmitters) */ +#define I2C_SR1_TxE (1 << 7) + +/* RxNE: Data register not empty (receivers) */ +#define I2C_SR1_RxNE (1 << 6) + +/* Note: Bit 5 is reserved, and forced to 0 by hardware. */ + +/* STOPF: STOP detection (slave mode) */ +#define I2C_SR1_STOPF (1 << 4) + +/* ADD10: 10-bit header sent (master mode) */ +#define I2C_SR1_ADD10 (1 << 3) + +/* BTF: Byte transfer finished */ +#define I2C_SR1_BTF (1 << 2) + +/* ADDR: Address sent (master mode) / address matched (slave mode) */ +#define I2C_SR1_ADDR (1 << 1) + +/* SB: Start bit (master mode) */ +#define I2C_SR1_SB (1 << 0) + +/* --- I2Cx_SR2 values ----------------------------------------------------- */ + +/* Bits [15:8]: PEC[7:0]: Packet error checking register */ + +/* DUALF: Dual flag (slave mode) */ +#define I2C_SR2_DUALF (1 << 7) + +/* SMBHOST: SMBus host header (slave mode) */ +#define I2C_SR2_SMBHOST (1 << 6) + +/* SMBDEFAULT: SMBus device default address (slave mode) */ +#define I2C_SR2_SMBDEFAULT (1 << 5) + +/* GENCALL: General call address (slave mode) */ +#define I2C_SR2_GENCALL (1 << 4) + +/* Note: Bit 3 is reserved, and forced to 0 by hardware. */ + +/* TRA: Transmitter / receiver */ +#define I2C_SR2_TRA (1 << 2) + +/* BUSY: Bus busy */ +#define I2C_SR2_BUSY (1 << 1) + +/* MSL: Master / slave */ +#define I2C_SR2_MSL (1 << 0) + +/* --- I2Cx_CCR values ----------------------------------------------------- */ + +/* F/S: I2C Master mode selection (fast / standard) */ +#define I2C_CCR_FS (1 << 15) + +/* DUTY: Fast Mode Duty Cycle */ +#define I2C_CCR_DUTY (1 << 14) + +/* Note: Bits [13:12] are reserved, and forced to 0 by hardware. */ + +/* + * Bits [11:0]: + * CCR[11:0]: Clock control register in Fast/Standard mode (master mode) + */ + +/* --- I2Cx_TRISE values --------------------------------------------------- */ + +/* Note: Bits [15:6] are reserved, and forced to 0 by hardware. */ + +/* + * Bits [5:0]: + * TRISE[5:0]: Maximum rise time in Fast/Standard mode (master mode) + */ + +/* --- I2C const definitions ----------------------------------------------- */ + +#define I2C_WRITE 0 +#define I2C_READ 1 + +/* --- I2C funtion prototypes----------------------------------------------- */ + +void i2c_peripheral_enable(u32 i2c); +void i2c_peripheral_disable(u32 i2c); +void i2c_send_start(u32 i2c); +void i2c_send_stop(u32 i2c); +void i2c_set_own_7bit_slave_address(u32 i2c, u8 slave); +void i2c_set_own_10bit_slave_address(u32 i2c, u16 slave); +void i2c_set_fast_mode(u32 i2c); +void i2c_set_standard_mode(u32 i2c); +void i2c_set_clock_frequency(u32 i2c, u8 freq); +void i2c_set_ccr(u32 i2c, u16 freq); +void i2c_set_trise(u32 i2c, u16 trise); +void i2c_send_7bit_address(u32 i2c, u8 slave, u8 readwrite); +void i2c_send_data(u32 i2c, u8 data); + +#endif diff --git a/include/libopencm3/stm32/iwdg.h b/include/libopencm3/stm32/iwdg.h new file mode 100644 index 0000000..bf2784a --- /dev/null +++ b/include/libopencm3/stm32/iwdg.h @@ -0,0 +1,75 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_IWDG_H +#define LIBOPENCM3_IWDG_H + +#include +#include + +/* --- IWDG registers ------------------------------------------------------ */ + +/* Key Register (IWDG_KR) */ +#define IWDG_KR MMIO32(IWDG_BASE + 0x00) + +/* Prescaler register (IWDG_PR) */ +#define IWDG_PR MMIO32(IWDG_BASE + 0x04) + +/* Reload register (IWDG_RLR) */ +#define IWDG_RLR MMIO32(IWDG_BASE + 0x08) + +/* Status register (IWDG_SR) */ +#define IWDG_SR MMIO32(IWDG_BASE + 0x0C) + +/* --- IWDG_KR values ------------------------------------------------------ */ + +/* KEY[15:0]: Key value */ +#define IWDG_KR_RESET 0xAAAA +#define IWDG_KR_UNLOCK 0x5555 +#define IWDG_KR_START 0xCCCC + +/* --- IWDG_PR values ------------------------------------------------------ */ + +/* PR[2:0]: Prescaler divider */ +#define IWDG_PR_LSB 0 +#define IWDG_PR_DIV4 0x0 +#define IWDG_PR_DIV8 0x1 +#define IWDG_PR_DIV16 0x2 +#define IWDG_PR_DIV32 0x3 +#define IWDG_PR_DIV64 0x4 +#define IWDG_PR_DIV128 0x5 +#define IWDG_PR_DIV256 0x6 +/* Double definition: 0x06 and 0x07 both mean DIV256 as per datasheet. */ +/* #define IWDG_PR_DIV256 0x7 */ + +/* --- IWDG_RLR values ----------------------------------------------------- */ + +/* RL[11:0]: Watchdog counter reload value */ + +/* --- IWDG_SR values ------------------------------------------------------ */ + +/* RVU: Watchdog counter reload value update */ +#define IWDG_SR_RVU (1 << 1) + +/* PVU: Watchdog prescaler value update */ +#define IWDG_SR_PVU (1 << 0) + +/* --- IWDG funtion prototypes---------------------------------------------- */ + +#endif diff --git a/include/libopencm3/stm32/memorymap.h b/include/libopencm3/stm32/memorymap.h new file mode 100644 index 0000000..17a919e --- /dev/null +++ b/include/libopencm3/stm32/memorymap.h @@ -0,0 +1,33 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Fergus Noble + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_MEMORYMAP_COMMON_H +#define LIBOPENCM3_MEMORYMAP_COMMON_H + +#ifdef STM32F1 +#include +#else +#ifdef STM32F1 +#include +#else +#error "stm32 family not defined." +#endif +#endif + +#endif diff --git a/include/libopencm3/stm32/pwr.h b/include/libopencm3/stm32/pwr.h new file mode 100644 index 0000000..e5b9804 --- /dev/null +++ b/include/libopencm3/stm32/pwr.h @@ -0,0 +1,81 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_PWR_H +#define LIBOPENCM3_PWR_H + +#include +#include + +/* --- PWR registers ------------------------------------------------------- */ + +/* Power control register (PWR_CR) */ +#define PWR_CR MMIO32(POWER_CONTROL_BASE + 0x00) + +/* Power control/status register (PWR_CSR) */ +#define PWR_CSR MMIO32(POWER_CONTROL_BASE + 0x04) + +/* --- PWR_CR values ------------------------------------------------------- */ + +/* DBP: Disable backup domain write protection */ +#define PWR_CR_DBP (1 << 8) + +/* PLS[7:5]: PVD level selection */ +#define PWR_CR_PLS_LSB 5 +#define PWR_CR_PLS_2V2 0x0 +#define PWR_CR_PLS_2V3 0x1 +#define PWR_CR_PLS_2V4 0x2 +#define PWR_CR_PLS_2V5 0x3 +#define PWR_CR_PLS_2V6 0x4 +#define PWR_CR_PLS_2V7 0x5 +#define PWR_CR_PLS_2V8 0x6 +#define PWR_CR_PLS_2V9 0x7 + +/* PVDE: Power voltage detector enable */ +#define PWR_CR_PVDE (1 << 4) + +/* CSBF: Clear standby flag */ +#define PWR_CR_CSBF (1 << 3) + +/* CWUF: Clear wakeup flag */ +#define PWR_CR_CWUF (1 << 2) + +/* PDDS: Power down deepsleep */ +#define PWR_CR_PDDS (1 << 1) + +/* LPDS: Low-power deepsleep */ +#define PWR_CR_LPDS (1 << 0) + +/* --- PWR_CSR values ------------------------------------------------------ */ + +/* EWUP: Enable WKUP pin */ +#define PWR_CSR_EWUP (1 << 8) + +/* PVDO: PVD output */ +#define PWR_CSR_PVDO (1 << 2) + +/* SBF: Standby flag */ +#define PWR_CSR_SBF (1 << 1) + +/* WUF: Wakeup flag */ +#define PWR_CSR_WUF (1 << 0) + +/* --- PWR function prototypes ------------------------------------------- */ + +#endif diff --git a/include/libopencm3/stm32/spi.h b/include/libopencm3/stm32/spi.h new file mode 100644 index 0000000..3cadaf8 --- /dev/null +++ b/include/libopencm3/stm32/spi.h @@ -0,0 +1,331 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_SPI_H +#define LIBOPENCM3_SPI_H + +#include +#include + +/* Registers can be accessed as 16bit or 32bit values. */ + +/* --- Convenience macros -------------------------------------------------- */ + +#define SPI1 SPI1_BASE +#define SPI2 SPI2_I2S_BASE +#define SPI3 SPI3_I2S_BASE + +/* --- SPI registers ------------------------------------------------------- */ + +/* Control register 1 (SPIx_CR1) */ +#define SPI_CR1(spi_base) MMIO32(spi_base + 0x00) +#define SPI1_CR1 SPI_CR1(SPI1_BASE) +#define SPI2_CR1 SPI_CR1(SPI2_I2S_BASE) +#define SPI3_CR1 SPI_CR1(SPI3_I2S_BASE) + +/* Control register 2 (SPIx_CR2) */ +#define SPI_CR2(spi_base) MMIO32(spi_base + 0x04) +#define SPI1_CR2 SPI_CR2(SPI1_BASE) +#define SPI2_CR2 SPI_CR2(SPI2_I2S_BASE) +#define SPI3_CR2 SPI_CR2(SPI3_I2S_BASE) + +/* Status register (SPIx_SR) */ +#define SPI_SR(spi_base) MMIO32(spi_base + 0x08) +#define SPI1_SR SPI_SR(SPI1_BASE) +#define SPI2_SR SPI_SR(SPI2_I2S_BASE) +#define SPI3_SR SPI_SR(SPI3_I2S_BASE) + +/* Data register (SPIx_DR) */ +#define SPI_DR(spi_base) MMIO32(spi_base + 0x0c) +#define SPI1_DR SPI_DR(SPI1_BASE) +#define SPI2_DR SPI_DR(SPI2_I2S_BASE) +#define SPI3_DR SPI_DR(SPI3_I2S_BASE) + +/* CRC polynomial register (SPIx_CRCPR) */ +/* Note: Not used in I2S mode. */ +#define SPI_CRCPR(spi_base) MMIO32(spi_base + 0x10) +#define SPI1_CRCPR SPI_CRCPR(SPI1_BASE) +#define SPI2_CRCPR SPI_CRCPR(SPI2_I2S_BASE) +#define SPI3_CRCPR SPI_CRCPR(SPI3_I2S_BASE) + +/* RX CRC register (SPIx_RXCRCR) */ +/* Note: Not used in I2S mode. */ +#define SPI_RXCRCR(spi_base) MMIO32(spi_base + 0x14) +#define SPI1_RXCRCR SPI_RXCRCR(SPI1_BASE) +#define SPI2_RXCRCR SPI_RXCRCR(SPI2_I2S_BASE) +#define SPI3_RXCRCR SPI_RXCRCR(SPI3_I2S_BASE) + +/* TX CRC register (SPIx_RXCRCR) */ +/* Note: Not used in I2S mode. */ +#define SPI_TXCRCR(spi_base) MMIO32(spi_base + 0x18) +#define SPI1_TXCRCR SPI_TXCRCR(SPI1_BASE) +#define SPI2_TXCRCR SPI_TXCRCR(SPI2_I2S_BASE) +#define SPI3_TXCRCR SPI_TXCRCR(SPI3_I2S_BASE) + +/* I2S configuration register (SPIx_I2SCFGR) */ +#define SPI_I2SCFGR(spi_base) MMIO32(spi_base + 0x1c) +#define SPI1_I2SCFGR SPI_I2SCFGR(SPI1_BASE) +#define SPI2_I2SCFGR SPI_I2SCFGR(SPI2_I2S_BASE) +#define SPI3_I2SCFGR SPI_I2SCFGR(SPI3_I2S_BASE) + +/* I2S prescaler register (SPIx_I2SPR) */ +#define SPI_I2SPR(spi_base) MMIO32(spi_base + 0x20) +#define SPI1_I2SPR SPI_I2SPR(SPI1_BASE) +#define SPI2_I2SPR SPI_I2SPR(SPI2_I2S_BASE) +#define SPI3_I2SPR SPI_I2SPR(SPI3_I2S_BASE) + +/* --- SPI_CR1 values ------------------------------------------------------ */ + +/* Note: None of the CR1 bits are used in I2S mode. */ + +/* BIDIMODE: Bidirectional data mode enable */ +#define SPI_CR1_BIDIMODE_2LINE_UNIDIR (0 << 15) +#define SPI_CR1_BIDIMODE_1LINE_BIDIR (1 << 15) +#define SPI_CR1_BIDIMODE (1 << 15) + +/* BIDIOE: Output enable in bidirectional mode */ +#define SPI_CR1_BIDIOE (1 << 14) + +/* CRCEN: Hardware CRC calculation enable */ +#define SPI_CR1_CRCEN (1 << 13) + +/* CRCNEXT: Transmit CRC next */ +#define SPI_CR1_CRCNEXT (1 << 12) + +/* DFF: Data frame format */ +#define SPI_CR1_DFF_8BIT (0 << 11) +#define SPI_CR1_DFF_16BIT (1 << 11) +#define SPI_CR1_DFF (1 << 11) + +/* RXONLY: Receive only */ +#define SPI_CR1_RXONLY (1 << 10) + +/* SSM: Software slave management */ +#define SPI_CR1_SSM (1 << 9) + +/* SSI: Internal slave select */ +#define SPI_CR1_SSI (1 << 8) + +/* LSBFIRST: Frame format */ +#define SPI_CR1_MSBFIRST (0 << 7) +#define SPI_CR1_LSBFIRST (1 << 7) + +/* SPE: SPI enable */ +#define SPI_CR1_SPE (1 << 6) + +/* BR[2:0]: Baud rate control */ +#define SPI_CR1_BAUDRATE_FPCLK_DIV_2 (0x00 << 3) +#define SPI_CR1_BAUDRATE_FPCLK_DIV_4 (0x01 << 3) +#define SPI_CR1_BAUDRATE_FPCLK_DIV_8 (0x02 << 3) +#define SPI_CR1_BAUDRATE_FPCLK_DIV_16 (0x03 << 3) +#define SPI_CR1_BAUDRATE_FPCLK_DIV_32 (0x04 << 3) +#define SPI_CR1_BAUDRATE_FPCLK_DIV_64 (0x05 << 3) +#define SPI_CR1_BAUDRATE_FPCLK_DIV_128 (0x06 << 3) +#define SPI_CR1_BAUDRATE_FPCLK_DIV_256 (0x07 << 3) +#define SPI_CR1_BR_FPCLK_DIV_2 0x0 +#define SPI_CR1_BR_FPCLK_DIV_4 0x1 +#define SPI_CR1_BR_FPCLK_DIV_8 0x2 +#define SPI_CR1_BR_FPCLK_DIV_16 0x3 +#define SPI_CR1_BR_FPCLK_DIV_32 0x4 +#define SPI_CR1_BR_FPCLK_DIV_64 0x5 +#define SPI_CR1_BR_FPCLK_DIV_128 0x6 +#define SPI_CR1_BR_FPCLK_DIV_256 0x7 + +/* MSTR: Master selection */ +#define SPI_CR1_MSTR (1 << 2) + +/* CPOL: Clock polarity */ +#define SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE (0 << 1) +#define SPI_CR1_CPOL_CLK_TO_1_WHEN_IDLE (1 << 1) +#define SPI_CR1_CPOL (1 << 1) + +/* CPHA: Clock phase */ +#define SPI_CR1_CPHA_CLK_TRANSITION_1 (0 << 0) +#define SPI_CR1_CPHA_CLK_TRANSITION_2 (1 << 0) +#define SPI_CR1_CPHA (1 << 0) + +/* --- SPI_CR2 values ------------------------------------------------------ */ + +/* Bits [15:8]: Reserved. Forced to 0 by hardware. */ + +/* TXEIE: Tx buffer empty interrupt enable */ +#define SPI_CR2_TXEIE (1 << 7) + +/* RXNEIE: RX buffer not empty interrupt enable */ +#define SPI_CR2_RXNEIE (1 << 6) + +/* ERRIE: Error interrupt enable */ +#define SPI_CR2_ERRIE (1 << 5) + +/* Bits [4:3]: Reserved. Forced to 0 by hardware. */ + +/* SSOE: SS output enable */ +#define SPI_CR2_SSOE (1 << 2) + +/* TXDMAEN: Tx buffer DMA enable */ +#define SPI_CR2_TXDMAEN (1 << 1) + +/* RXDMAEN: Rx buffer DMA enable */ +#define SPI_CR2_RXDMAEN (1 << 0) + +/* --- SPI_SR values ------------------------------------------------------- */ + +/* Bits [15:8]: Reserved. Forced to 0 by hardware. */ + +/* BSY: Busy flag */ +#define SPI_SR_BSY (1 << 7) + +/* OVR: Overrun flag */ +#define SPI_SR_OVR (1 << 6) + +/* MODF: Mode fault */ +#define SPI_SR_MODF (1 << 5) + +/* CRCERR: CRC error flag */ +#define SPI_SR_CRCERR (1 << 4) + +/* UDR: Underrun flag */ +#define SPI_SR_UDR (1 << 3) + +/* CHSIDE: Channel side */ +#define SPI_SR_CHSIDE (1 << 2) + +/* TXE: Transmit buffer empty */ +#define SPI_SR_TXE (1 << 1) + +/* RXNE: Receive buffer not empty */ +#define SPI_SR_RXNE (1 << 0) + +/* --- SPI_DR values ------------------------------------------------------- */ + +/* SPI_DR[15:0]: Data Register. */ + +/* --- SPI_CRCPR values ---------------------------------------------------- */ + +/* SPI_CRCPR [15:0]: CRC Polynomial Register. */ + +/* --- SPI_RXCRCR values --------------------------------------------------- */ + +/* SPI_RXCRCR [15:0]: RX CRC Register. */ + +/* --- SPI_TXCRCR values --------------------------------------------------- */ + +/* SPI_TXCRCR [15:0]: TX CRC Register. */ + +/* --- SPI_I2SCFGR values -------------------------------------------------- */ + +/* Bits [15:12]: Reserved. Forced to 0 by hardware. */ + +/* I2SMOD: I2S mode selection */ +#define SPI_I2SCFGR_I2SMOD (1 << 11) + +/* I2SE: I2S Enable */ +#define SPI_I2SCFGR_I2SE (1 << 10) + +/* I2SCFG[9:8]: I2S configuration mode */ +#define SPI_I2SCFGR_I2SCFG_LSB 8 +#define SPI_I2SCFGR_I2SCFG_SLAVE_TRANSMIT 0x0 +#define SPI_I2SCFGR_I2SCFG_SLAVE_RECEIVE 0x1 +#define SPI_I2SCFGR_I2SCFG_MASTER_TRANSMIT 0x2 +#define SPI_I2SCFGR_I2SCFG_MASTER_RECEIVE 0x3 + +/* PCMSYNC: PCM frame synchronization */ +#define SPI_I2SCFGR_PCMSYNC (1 << 7) + +/* Bit 6: Reserved. Forced to 0 by hardware. */ + +/* I2SSTD[5:4]: I2S standard selection */ +#define SPI_I2SCFGR_I2SSTD_LSB 4 +#define SPI_I2SCFGR_I2SSTD_I2S_PHILLIPS 0x0 +#define SPI_I2SCFGR_I2SSTD_MSB_JUSTIFIED 0x1 +#define SPI_I2SCFGR_I2SSTD_LSB_JUSTIFIED 0x2 +#define SPI_I2SCFGR_I2SSTD_PCM 0x3 + +/* CKPOL: Steady state clock polarity */ +#define SPI_I2SCFGR_CKPOL (1 << 3) + +/* DATLEN[2:1]: Data length to be transferred */ +#define SPI_I2SCFGR_DATLEN_LSB 1 +#define SPI_I2SCFGR_DATLEN_16BIT 0x0 +#define SPI_I2SCFGR_DATLEN_24BIT 0x1 +#define SPI_I2SCFGR_DATLEN_32BIT 0x2 + +/* CHLEN: Channel length */ +#define SPI_I2SCFGR_CHLEN (1 << 0) + +/* --- SPI_I2SPR values ---------------------------------------------------- */ + +/* Bits [15:10]: Reserved. Forced to 0 by hardware. */ + +/* MCKOE: Master clock output enable */ +#define SPI_I2SPR_MCKOE (1 << 9) + +/* ODD: Odd factor for the prescaler */ +#define SPI_I2SPR_ODD (1 << 8) + +/* I2SDIV[7:0]: I2S Linear prescaler */ +/* 0 and 1 are forbidden values */ + +/* --- Function prototypes ------------------------------------------------- */ + +int spi_init_master(u32 spi, u32 br, u32 cpol, u32 cpha, u32 dff, u32 lsbfirst); +void spi_enable(u32 spi); +void spi_disable(u32 spi); +void spi_write(u32 spi, u16 data); +void spi_send(u32 spi, u16 data); +u16 spi_read(u32 spi); +void spi_set_bidirectional_mode(u32 spi); +void spi_set_unidirectional_mode(u32 spi); +void spi_set_bidirectional_receive_only_mode(u32 spi); +void spi_set_bidirectional_transmit_only_mode(u32 spi); +void spi_enable_crc(u32 spi); +void spi_disable_crc(u32 spi); +void spi_set_next_tx_from_buffer(u32 spi); +void spi_set_next_tx_from_crc(u32 spi); +void spi_set_dff_8bit(u32 spi); +void spi_set_dff_16bit(u32 spi); +void spi_set_full_duplex_mode(u32 spi); +void spi_set_receive_only_mode(u32 spi); +void spi_disable_software_slave_management(u32 spi); +void spi_enable_software_slave_management(u32 spi); +void spi_set_nss_high(u32 spi); +void spi_set_nss_low(u32 spi); +void spi_send_lsb_first(u32 spi); +void spi_send_msb_first(u32 spi); +void spi_set_baudrate_prescaler(u32 spi, u8 baudrate); +void spi_set_master_mode(u32 spi); +void spi_set_slave_mode(u32 spi); +void spi_set_clock_polarity_1(u32 spi); +void spi_set_clock_polarity_0(u32 spi); +void spi_set_clock_phase_1(u32 spi); +void spi_set_clock_phase_0(u32 spi); +void spi_enable_tx_buffer_empty_interrupt(u32 spi); +void spi_disable_tx_buffer_empty_interrupt(u32 spi); +void spi_enable_rx_buffer_not_empty_interrupt(u32 spi); +void spi_disable_rx_buffer_not_empty_interrupt(u32 spi); +void spi_enable_error_interrupt(u32 spi); +void spi_disable_error_interrupt(u32 spi); +void spi_enable_ss_output(u32 spi); +void spi_disable_ss_output(u32 spi); +void spi_enable_tx_dma(u32 spi); +void spi_disable_tx_dma(u32 spi); +void spi_enable_rx_dma(u32 spi); +void spi_disable_rx_dma(u32 spi); + +#endif diff --git a/include/libopencm3/stm32/timer.h b/include/libopencm3/stm32/timer.h new file mode 100644 index 0000000..7b5df86 --- /dev/null +++ b/include/libopencm3/stm32/timer.h @@ -0,0 +1,921 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Piotr Esden-Tempski + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_TIMER_H +#define LIBOPENCM3_TIMER_H + +#include +#include + +/* --- Convenience macros -------------------------------------------------- */ + +/* Timer register base adresses (for convenience) */ +#define TIM1 TIM1_BASE +#define TIM2 TIM2_BASE +#define TIM3 TIM3_BASE +#define TIM4 TIM4_BASE +#define TIM5 TIM5_BASE +#define TIM6 TIM6_BASE +#define TIM7 TIM7_BASE +#define TIM8 TIM8_BASE + +/* --- Timer registers ----------------------------------------------------- */ + +/* Control register 1 (TIMx_CR1) */ +#define TIM_CR1(tim_base) MMIO32(tim_base + 0x00) +#define TIM1_CR1 TIM_CR1(TIM1) +#define TIM2_CR1 TIM_CR1(TIM2) +#define TIM3_CR1 TIM_CR1(TIM3) +#define TIM4_CR1 TIM_CR1(TIM4) +#define TIM5_CR1 TIM_CR1(TIM5) +#define TIM6_CR1 TIM_CR1(TIM6) +#define TIM7_CR1 TIM_CR1(TIM7) +#define TIM8_CR1 TIM_CR1(TIM8) + +/* Control register 2 (TIMx_CR2) */ +#define TIM_CR2(tim_base) MMIO32(tim_base + 0x04) +#define TIM1_CR2 TIM_CR2(TIM1) +#define TIM2_CR2 TIM_CR2(TIM2) +#define TIM3_CR2 TIM_CR2(TIM3) +#define TIM4_CR2 TIM_CR2(TIM4) +#define TIM5_CR2 TIM_CR2(TIM5) +#define TIM6_CR2 TIM_CR2(TIM6) +#define TIM7_CR2 TIM_CR2(TIM7) +#define TIM8_CR2 TIM_CR2(TIM8) + +/* Slave mode control register (TIMx_SMCR) */ +#define TIM_SMCR(tim_base) MMIO32(tim_base + 0x08) +#define TIM1_SMCR TIM_SMCR(TIM1) +#define TIM2_SMCR TIM_SMCR(TIM2) +#define TIM3_SMCR TIM_SMCR(TIM3) +#define TIM4_SMCR TIM_SMCR(TIM4) +#define TIM5_SMCR TIM_SMCR(TIM5) +#define TIM8_SMCR TIM_SMCR(TIM8) + +/* DMA/Interrupt enable register (TIMx_DIER) */ +#define TIM_DIER(tim_base) MMIO32(tim_base + 0x0C) +#define TIM1_DIER TIM_DIER(TIM1) +#define TIM2_DIER TIM_DIER(TIM2) +#define TIM3_DIER TIM_DIER(TIM3) +#define TIM4_DIER TIM_DIER(TIM4) +#define TIM5_DIER TIM_DIER(TIM5) +#define TIM6_DIER TIM_DIER(TIM6) +#define TIM7_DIER TIM_DIER(TIM7) +#define TIM8_DIER TIM_DIER(TIM8) + +/* Status register (TIMx_SR) */ +#define TIM_SR(tim_base) MMIO32(tim_base + 0x10) +#define TIM1_SR TIM_SR(TIM1) +#define TIM2_SR TIM_SR(TIM2) +#define TIM3_SR TIM_SR(TIM3) +#define TIM4_SR TIM_SR(TIM4) +#define TIM5_SR TIM_SR(TIM5) +#define TIM6_SR TIM_SR(TIM6) +#define TIM7_SR TIM_SR(TIM7) +#define TIM8_SR TIM_SR(TIM8) + +/* Event generation register (TIMx_EGR) */ +#define TIM_EGR(tim_base) MMIO32(tim_base + 0x14) +#define TIM1_EGR TIM_EGR(TIM1) +#define TIM2_EGR TIM_EGR(TIM2) +#define TIM3_EGR TIM_EGR(TIM3) +#define TIM4_EGR TIM_EGR(TIM4) +#define TIM5_EGR TIM_EGR(TIM5) +#define TIM6_EGR TIM_EGR(TIM6) +#define TIM7_EGR TIM_EGR(TIM7) +#define TIM8_EGR TIM_EGR(TIM8) + +/* Capture/compare mode register 1 (TIMx_CCMR1) */ +#define TIM_CCMR1(tim_base) MMIO32(tim_base + 0x18) +#define TIM1_CCMR1 TIM_CCMR1(TIM1) +#define TIM2_CCMR1 TIM_CCMR1(TIM2) +#define TIM3_CCMR1 TIM_CCMR1(TIM3) +#define TIM4_CCMR1 TIM_CCMR1(TIM4) +#define TIM5_CCMR1 TIM_CCMR1(TIM5) +#define TIM8_CCMR1 TIM_CCMR1(TIM8) + +/* Capture/compare mode register 2 (TIMx_CCMR2) */ +#define TIM_CCMR2(tim_base) MMIO32(tim_base + 0x1C) +#define TIM1_CCMR2 TIM_CCMR2(TIM1) +#define TIM2_CCMR2 TIM_CCMR2(TIM2) +#define TIM3_CCMR2 TIM_CCMR2(TIM3) +#define TIM4_CCMR2 TIM_CCMR2(TIM4) +#define TIM5_CCMR2 TIM_CCMR2(TIM5) +#define TIM8_CCMR2 TIM_CCMR2(TIM8) + +/* Capture/compare enable register (TIMx_CCER) */ +#define TIM_CCER(tim_base) MMIO32(tim_base + 0x20) +#define TIM1_CCER TIM_CCER(TIM1) +#define TIM2_CCER TIM_CCER(TIM2) +#define TIM3_CCER TIM_CCER(TIM3) +#define TIM4_CCER TIM_CCER(TIM4) +#define TIM5_CCER TIM_CCER(TIM5) +#define TIM8_CCER TIM_CCER(TIM8) + +/* Counter (TIMx_CNT) */ +#define TIM_CNT(tim_base) MMIO32(tim_base + 0x24) +#define TIM1_CNT TIM_CNT(TIM1) +#define TIM2_CNT TIM_CNT(TIM2) +#define TIM3_CNT TIM_CNT(TIM3) +#define TIM4_CNT TIM_CNT(TIM4) +#define TIM5_CNT TIM_CNT(TIM5) +#define TIM6_CNT TIM_CNT(TIM6) +#define TIM7_CNT TIM_CNT(TIM7) +#define TIM8_CNT TIM_CNT(TIM8) + +/* Prescaler (TIMx_PSC) */ +#define TIM_PSC(tim_base) MMIO32(tim_base + 0x28) +#define TIM1_PSC TIM_PSC(TIM1) +#define TIM2_PSC TIM_PSC(TIM2) +#define TIM3_PSC TIM_PSC(TIM3) +#define TIM4_PSC TIM_PSC(TIM4) +#define TIM5_PSC TIM_PSC(TIM5) +#define TIM6_PSC TIM_PSC(TIM6) +#define TIM7_PSC TIM_PSC(TIM7) +#define TIM8_PSC TIM_PSC(TIM8) + +/* Auto-reload register (TIMx_ARR) */ +#define TIM_ARR(tim_base) MMIO32(tim_base + 0x2C) +#define TIM1_ARR TIM_ARR(TIM1) +#define TIM2_ARR TIM_ARR(TIM2) +#define TIM3_ARR TIM_ARR(TIM3) +#define TIM4_ARR TIM_ARR(TIM4) +#define TIM5_ARR TIM_ARR(TIM5) +#define TIM6_ARR TIM_ARR(TIM6) +#define TIM7_ARR TIM_ARR(TIM7) +#define TIM8_ARR TIM_ARR(TIM8) + +/* Repetition counter register (TIMx_RCR) */ +#define TIM_RCR(tim_base) MMIO32(tim_base + 0x30) +#define TIM1_RCR TIM_RCR(TIM1) +#define TIM8_RCR TIM_RCR(TIM8) + +/* Capture/compare register 1 (TIMx_CCR1) */ +#define TIM_CCR1(tim_base) MMIO32(tim_base + 0x34) +#define TIM1_CCR1 TIM_CCR1(TIM1) +#define TIM2_CCR1 TIM_CCR1(TIM2) +#define TIM3_CCR1 TIM_CCR1(TIM3) +#define TIM4_CCR1 TIM_CCR1(TIM4) +#define TIM5_CCR1 TIM_CCR1(TIM5) +#define TIM8_CCR1 TIM_CCR1(TIM8) + +/* Capture/compare register 2 (TIMx_CCR2) */ +#define TIM_CCR2(tim_base) MMIO32(tim_base + 0x38) +#define TIM1_CCR2 TIM_CCR2(TIM1) +#define TIM2_CCR2 TIM_CCR2(TIM2) +#define TIM3_CCR2 TIM_CCR2(TIM3) +#define TIM4_CCR2 TIM_CCR2(TIM4) +#define TIM5_CCR2 TIM_CCR2(TIM5) +#define TIM8_CCR2 TIM_CCR2(TIM8) + +/* Capture/compare register 3 (TIMx_CCR3) */ +#define TIM_CCR3(tim_base) MMIO32(tim_base + 0x3C) +#define TIM1_CCR3 TIM_CCR3(TIM1) +#define TIM2_CCR3 TIM_CCR3(TIM2) +#define TIM3_CCR3 TIM_CCR3(TIM3) +#define TIM4_CCR3 TIM_CCR3(TIM4) +#define TIM5_CCR3 TIM_CCR3(TIM5) +#define TIM8_CCR3 TIM_CCR3(TIM8) + +/* Capture/compare register 4 (TIMx_CCR4) */ +#define TIM_CCR4(tim_base) MMIO32(tim_base + 0x40) +#define TIM1_CCR4 TIM_CCR4(TIM1) +#define TIM2_CCR4 TIM_CCR4(TIM2) +#define TIM3_CCR4 TIM_CCR4(TIM3) +#define TIM4_CCR4 TIM_CCR4(TIM4) +#define TIM5_CCR4 TIM_CCR4(TIM5) +#define TIM8_CCR4 TIM_CCR4(TIM8) + +/* Break and dead-time register (TIMx_BDTR) */ +#define TIM_BDTR(tim_base) MMIO32(tim_base + 0x44) +#define TIM1_BDTR TIM_BDTR(TIM1) +#define TIM8_BDTR TIM_BDTR(TIM8) + +/* DMA control register (TIMx_DCR) */ +#define TIM_DCR(tim_base) MMIO32(tim_base + 0x48) +#define TIM1_DCR TIM_DCR(TIM1) +#define TIM2_DCR TIM_DCR(TIM2) +#define TIM3_DCR TIM_DCR(TIM3) +#define TIM4_DCR TIM_DCR(TIM4) +#define TIM5_DCR TIM_DCR(TIM5) +#define TIM8_DCR TIM_DCR(TIM8) + +/* DMA address for full transfer (TIMx_DMAR) */ +#define TIM_DMAR(tim_base) MMIO32(tim_base + 0x4C) +#define TIM1_DMAR TIM_DMAR(TIM1) +#define TIM2_DMAR TIM_DMAR(TIM2) +#define TIM3_DMAR TIM_DMAR(TIM3) +#define TIM4_DMAR TIM_DMAR(TIM4) +#define TIM5_DMAR TIM_DMAR(TIM5) +#define TIM8_DMAR TIM_DMAR(TIM8) + +/* --- TIMx_CR1 values ----------------------------------------------------- */ + +/* CKD[1:0]: Clock division */ +#define TIM_CR1_CKD_CK_INT (0x0 << 8) +#define TIM_CR1_CKD_CK_INT_MUL_2 (0x1 << 8) +#define TIM_CR1_CKD_CK_INT_MUL_4 (0x2 << 8) +#define TIM_CR1_CKD_CK_INT_MASK (0x3 << 8) + +/* ARPE: Auto-reload preload enable */ +#define TIM_CR1_ARPE (1 << 7) + +/* CMS[1:0]: Center-aligned mode selection */ +#define TIM_CR1_CMS_EDGE (0x0 << 5) +#define TIM_CR1_CMS_CENTER_1 (0x1 << 5) +#define TIM_CR1_CMS_CENTER_2 (0x2 << 5) +#define TIM_CR1_CMS_CENTER_3 (0x3 << 5) +#define TIM_CR1_CMS_MASK (0x3 << 5) + +/* DIR: Direction */ +#define TIM_CR1_DIR_UP (0 << 4) +#define TIM_CR1_DIR_DOWN (1 << 4) + +/* OPM: One pulse mode */ +#define TIM_CR1_OPM (1 << 3) + +/* URS: Update request source */ +#define TIM_CR1_URS (1 << 2) + +/* UDIS: Update disable */ +#define TIM_CR1_UDIS (1 << 1) + +/* CEN: Counter enable */ +#define TIM_CR1_CEN (1 << 0) + +/* --- TIMx_CR2 values ----------------------------------------------------- */ + +/* OIS4: Output idle state 4 (OC4 output) */ +#define TIM_CR2_OIS4 (1 << 14) + +/* OIS3N: Output idle state 3 (OC3N output) */ +#define TIM_CR2_OIS3N (1 << 13) + +/* OIS3: Output idle state 3 (OC3 output) */ +#define TIM_CR2_OIS3 (1 << 12) + +/* OIS2N: Output idle state 2 (OC2N output) */ +#define TIM_CR2_OIS2N (1 << 11) + +/* OIS2: Output idle state 2 (OC2 output) */ +#define TIM_CR2_OIS2 (1 << 10) + +/* OIS1N: Output idle state 1 (OC1N output) */ +#define TIM_CR2_OIS1N (1 << 9) + +/* OIS1: Output idle state 1 (OC1 output) */ +#define TIM_CR2_OIS1 (1 << 8) +#define TIM_CR2_OIS_MASK (0x7f << 8) + +/* TI1S: TI1 selection */ +#define TIM_CR2_TI1S (1 << 7) + +/* MMS[2:0]: Master mode selection */ +#define TIM_CR2_MMS_RESET (0x0 << 4) +#define TIM_CR2_MMS_ENABLE (0x1 << 4) +#define TIM_CR2_MMS_UPDATE (0x2 << 4) +#define TIM_CR2_MMS_COMPARE_PULSE (0x3 << 4) +#define TIM_CR2_MMS_COMPARE_OC1REF (0x4 << 4) +#define TIM_CR2_MMS_COMPARE_OC2REF (0x5 << 4) +#define TIM_CR2_MMS_COMPARE_OC3REF (0x6 << 4) +#define TIM_CR2_MMS_COMPARE_OC4REF (0x7 << 4) +#define TIM_CR2_MMS_MASK (0x7 << 4) + +/* CCDS: Capture/compare DMA selection */ +#define TIM_CR2_CCDS (1 << 3) + +/* CCUS: Capture/compare control update selection */ +#define TIM_CR2_CCUS (1 << 2) + +/* CCPC: Capture/compare preload control */ +#define TIM_CR2_CCPC (1 << 0) + +/* --- TIMx_SMCR values ---------------------------------------------------- */ + +/* ETP: External trigger polarity */ +#define TIM_SMCR_ETP (1 << 15) + +/* ECE: External clock enable */ +#define TIM_SMCR_ECE (1 << 14) + +/* ETPS[1:0]: External trigger prescaler */ +#define TIM_SMCR_ETPS_OFF (0x0 << 12) +#define TIM_SMCR_ETPS_ETRP_DIV_2 (0x1 << 12) +#define TIM_SMCR_ETPS_ETRP_DIV_4 (0x2 << 12) +#define TIM_SMCR_ETPS_ETRP_DIV_8 (0x3 << 12) +#define TIM_SMCR_ETPS_MASK (0X3 << 12) + +/* ETF[3:0]: External trigger filter */ +#define TIM_SMCR_ETF_OFF (0x0 << 8) +#define TIM_SMCR_ETF_CK_INT_N_2 (0x1 << 8) +#define TIM_SMCR_ETF_CK_INT_N_4 (0x2 << 8) +#define TIM_SMCR_ETF_CK_INT_N_8 (0x3 << 8) +#define TIM_SMCR_ETF_DTS_DIV_2_N_6 (0x4 << 8) +#define TIM_SMCR_ETF_DTS_DIV_2_N_8 (0x5 << 8) +#define TIM_SMCR_ETF_DTS_DIV_4_N_6 (0x6 << 8) +#define TIM_SMCR_ETF_DTS_DIV_4_N_8 (0x7 << 8) +#define TIM_SMCR_ETF_DTS_DIV_8_N_6 (0x8 << 8) +#define TIM_SMCR_ETF_DTS_DIV_8_N_8 (0x9 << 8) +#define TIM_SMCR_ETF_DTS_DIV_16_N_5 (0xA << 8) +#define TIM_SMCR_ETF_DTS_DIV_16_N_6 (0xB << 8) +#define TIM_SMCR_ETF_DTS_DIV_16_N_8 (0xC << 8) +#define TIM_SMCR_ETF_DTS_DIV_32_N_5 (0xD << 8) +#define TIM_SMCR_ETF_DTS_DIV_32_N_6 (0xE << 8) +#define TIM_SMCR_ETF_DTS_DIV_32_N_8 (0xF << 8) +#define TIM_SMCR_ETF_MASK (0xF << 8) + +/* MSM: Master/slave mode */ +#define TIM_SMCR_MSM (1 << 7) + +/* TS[2:0]: Trigger selection */ +#define TIM_SMCR_TS_ITR0 (0x0 << 4) +#define TIM_SMCR_TS_ITR1 (0x1 << 4) +#define TIM_SMCR_TS_ITR2 (0x2 << 4) +#define TIM_SMCR_TS_ITR3 (0x3 << 4) +#define TIM_SMCR_TS_IT1F_ED (0x4 << 4) +#define TIM_SMCR_TS_IT1FP1 (0x5 << 4) +#define TIM_SMCR_TS_IT1FP2 (0x6 << 4) +#define TIM_SMCR_TS_ETRF (0x7 << 4) +#define TIM_SMCR_TS_MASK (0x7 << 4) + +/* SMS[2:0]: Slave mode selection */ +#define TIM_SMCR_SMS_OFF (0x0 << 0) +#define TIM_SMCR_SMS_EM1 (0x1 << 0) +#define TIM_SMCR_SMS_EM2 (0x2 << 0) +#define TIM_SMCR_SMS_EM3 (0x3 << 0) +#define TIM_SMCR_SMS_RM (0x4 << 0) +#define TIM_SMCR_SMS_GM (0x5 << 0) +#define TIM_SMCR_SMS_TM (0x6 << 0) +#define TIM_SMCR_SMS_ECM1 (0x7 << 0) +#define TIM_SMCR_SMS_MASK (0x7 << 0) + +/* --- TIMx_DIER values ---------------------------------------------------- */ + +/* TDE: Trigger DMA request enable */ +#define TIM_DIER_TDE (1 << 14) + +/* COMDE: COM DMA request enable */ +#define TIM_DIER_COMDE (1 << 13) + +/* CC4DE: Capture/Compare 4 DMA request enable */ +#define TIM_DIER_CC4DE (1 << 12) + +/* CC3DE: Capture/Compare 3 DMA request enable */ +#define TIM_DIER_CC3DE (1 << 11) + +/* CC2DE: Capture/Compare 2 DMA request enable */ +#define TIM_DIER_CC2DE (1 << 10) + +/* CC1DE: Capture/Compare 1 DMA request enable */ +#define TIM_DIER_CC1DE (1 << 9) + +/* UDE: Update DMA request enable */ +#define TIM_DIER_UDE (1 << 8) + +/* BIE: Break interrupt enable */ +#define TIM_DIER_BIE (1 << 7) + +/* TIE: Trigger interrupt enable */ +#define TIM_DIER_TIE (1 << 6) + +/* COMIE: COM interrupt enable */ +#define TIM_DIER_COMIE (1 << 5) + +/* CC4IE: Capture/compare 4 interrupt enable */ +#define TIM_DIER_CC4IE (1 << 4) + +/* CC3IE: Capture/compare 3 interrupt enable */ +#define TIM_DIER_CC3IE (1 << 3) + +/* CC2IE: Capture/compare 2 interrupt enable */ +#define TIM_DIER_CC2IE (1 << 2) + +/* CC1IE: Capture/compare 1 interrupt enable */ +#define TIM_DIER_CC1IE (1 << 1) + +/* UIE: Update interrupt enable */ +#define TIM_DIER_UIE (1 << 0) + +/* --- TIMx_SR values ------------------------------------------------------ */ + +/* CC4OF: Capture/compare 4 overcapture flag */ +#define TIM_SR_CC4OF (1 << 12) + +/* CC3OF: Capture/compare 3 overcapture flag */ +#define TIM_SR_CC3OF (1 << 11) + +/* CC2OF: Capture/compare 2 overcapture flag */ +#define TIM_SR_CC2OF (1 << 10) + +/* CC1OF: Capture/compare 1 overcapture flag */ +#define TIM_SR_CC1OF (1 << 9) + +/* BIF: Break interrupt flag */ +#define TIM_SR_BIF (1 << 7) + +/* TIF: Trigger interrupt flag */ +#define TIM_SR_TIF (1 << 6) + +/* COMIF: COM interrupt flag */ +#define TIM_SR_COMIF (1 << 5) + +/* CC4IF: Capture/compare 4 interrupt flag */ +#define TIM_SR_CC4IF (1 << 4) + +/* CC3IF: Capture/compare 3 interrupt flag */ +#define TIM_SR_CC3IF (1 << 3) + +/* CC2IF: Capture/compare 2 interrupt flag */ +#define TIM_SR_CC2IF (1 << 2) + +/* CC1IF: Capture/compare 1 interrupt flag */ +#define TIM_SR_CC1IF (1 << 1) + +/* UIF: Update interrupt flag */ +#define TIM_SR_UIF (1 << 0) + +/* --- TIMx_EGR values ----------------------------------------------------- */ + +/* BG: Break generation */ +#define TIM_EGR_BG (1 << 7) + +/* TG: Trigger generation */ +#define TIM_EGR_TG (1 << 6) + +/* COMG: Capture/compare control update generation */ +#define TIM_EGR_COMG (1 << 5) + +/* CC4G: Capture/compare 4 generation */ +#define TIM_EGR_CC4G (1 << 4) + +/* CC3G: Capture/compare 3 generation */ +#define TIM_EGR_CC3G (1 << 3) + +/* CC2G: Capture/compare 2 generation */ +#define TIM_EGR_CC2G (1 << 2) + +/* CC1G: Capture/compare 1 generation */ +#define TIM_EGR_CC1G (1 << 1) + +/* UG: Update generation */ +#define TIM_EGR_UG (1 << 0) + +/* --- TIMx_CCMR1 values --------------------------------------------------- */ + +/* --- Output compare mode --- */ + +/* OC2CE: Output compare 2 clear enable */ +#define TIM_CCMR1_OC2CE (1 << 15) + +/* OC2M[2:0]: Output compare 2 mode */ +#define TIM_CCMR1_OC2M_FROZEN (0x0 << 12) +#define TIM_CCMR1_OC2M_ACTIVE (0x1 << 12) +#define TIM_CCMR1_OC2M_INACTIVE (0x2 << 12) +#define TIM_CCMR1_OC2M_TOGGLE (0x3 << 12) +#define TIM_CCMR1_OC2M_FORCE_LOW (0x4 << 12) +#define TIM_CCMR1_OC2M_FORCE_HIGH (0x5 << 12) +#define TIM_CCMR1_OC2M_PWM1 (0x6 << 12) +#define TIM_CCMR1_OC2M_PWM2 (0x7 << 12) +#define TIM_CCMR1_OC2M_MASK (0x7 << 12) + +/* OC2PE: Output compare 2 preload enable */ +#define TIM_CCMR1_OC2PE (1 << 11) + +/* OC2FE: Output compare 2 fast enable */ +#define TIM_CCMR1_OC2FE (1 << 10) + +/* CC2S[1:0]: Capture/compare 2 selection */ +/* Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in + * TIMx_CCER). */ +#define TIM_CCMR1_CC2S_OUT (0x0 << 8) +#define TIM_CCMR1_CC2S_IN_TI2 (0x1 << 8) +#define TIM_CCMR1_CC2S_IN_TI1 (0x2 << 8) +#define TIM_CCMR1_CC2S_IN_TRC (0x3 << 8) +#define TIM_CCMR1_CC2S_MASK (0x3 << 8) + +/* OC1CE: Output compare 1 clear enable */ +#define TIM_CCMR1_OC1CE (1 << 7) + +/* OC1M[2:0]: Output compare 1 mode */ +#define TIM_CCMR1_OC1M_FROZEN (0x0 << 4) +#define TIM_CCMR1_OC1M_ACTIVE (0x1 << 4) +#define TIM_CCMR1_OC1M_INACTIVE (0x2 << 4) +#define TIM_CCMR1_OC1M_TOGGLE (0x3 << 4) +#define TIM_CCMR1_OC1M_FORCE_LOW (0x4 << 4) +#define TIM_CCMR1_OC1M_FORCE_HIGH (0x5 << 4) +#define TIM_CCMR1_OC1M_PWM1 (0x6 << 4) +#define TIM_CCMR1_OC1M_PWM2 (0x7 << 4) +#define TIM_CCMR1_OC1M_MASK (0x7 << 4) + +/* OC1PE: Output compare 1 preload enable */ +#define TIM_CCMR1_OC1PE (1 << 3) + +/* OC1FE: Output compare 1 fast enable */ +#define TIM_CCMR1_OC1FE (1 << 2) + +/* CC1S[1:0]: Capture/compare 1 selection */ +/* Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in + * TIMx_CCER). */ +#define TIM_CCMR1_CC1S_OUT (0x0 << 0) +#define TIM_CCMR1_CC1S_IN_TI2 (0x1 << 0) +#define TIM_CCMR1_CC1S_IN_TI1 (0x2 << 0) +#define TIM_CCMR1_CC1S_IN_TRC (0x3 << 0) +#define TIM_CCMR1_CC1S_MASK (0x3 << 0) + +/* --- Input capture mode --- */ + +/* IC2F[3:0]: Input capture 2 filter */ +#define TIM_CCMR1_IC2F_OFF (0x0 << 12) +#define TIM_CCMR1_IC2F_CK_INT_N_2 (0x1 << 12) +#define TIM_CCMR1_IC2F_CK_INT_N_4 (0x2 << 12) +#define TIM_CCMR1_IC2F_CK_INT_N_8 (0x3 << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_2_N_6 (0x4 << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_2_N_8 (0x5 << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_4_N_6 (0x6 << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_4_N_8 (0x7 << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_8_N_6 (0x8 << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_8_N_8 (0x9 << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_16_N_5 (0xA << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_16_N_6 (0xB << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_16_N_8 (0xC << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_32_N_5 (0xD << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_32_N_6 (0xE << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_32_N_8 (0xF << 12) +#define TIM_CCMR1_IC2F_MASK (0xF << 12) + +/* IC2PSC[1:0]: Input capture 2 prescaler */ +#define TIM_CCMR1_IC2PSC_OFF (0x0 << 10) +#define TIM_CCMR1_IC2PSC_2 (0x1 << 10) +#define TIM_CCMR1_IC2PSC_4 (0x2 << 10) +#define TIM_CCMR1_IC2PSC_8 (0x3 << 10) +#define TIM_CCMR1_IC2PSC_MASK (0x3 << 10) + +/* IC1F[3:0]: Input capture 1 filter */ +#define TIM_CCMR1_IC1F_OFF (0x0 << 4) +#define TIM_CCMR1_IC1F_CK_INT_N_2 (0x1 << 4) +#define TIM_CCMR1_IC1F_CK_INT_N_4 (0x2 << 4) +#define TIM_CCMR1_IC1F_CK_INT_N_8 (0x3 << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_2_N_6 (0x4 << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_2_N_8 (0x5 << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_4_N_6 (0x6 << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_4_N_8 (0x7 << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_8_N_6 (0x8 << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_8_N_8 (0x9 << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_16_N_5 (0xA << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_16_N_6 (0xB << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_16_N_8 (0xC << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_32_N_5 (0xD << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_32_N_6 (0xE << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_32_N_8 (0xF << 4) +#define TIM_CCMR1_IC1F_MASK (0xF << 4) + +/* IC1PSC[1:0]: Input capture 1 prescaler */ +#define TIM_CCMR1_IC1PSC_OFF (0x0 << 2) +#define TIM_CCMR1_IC1PSC_2 (0x1 << 2) +#define TIM_CCMR1_IC1PSC_4 (0x2 << 2) +#define TIM_CCMR1_IC1PSC_8 (0x3 << 2) +#define TIM_CCMR1_IC1PSC_MASK (0x3 << 2) + +/* --- TIMx_CCMR2 values --------------------------------------------------- */ + +/* --- Output compare mode --- */ + +/* OC4CE: Output compare 4 clear enable */ +#define TIM_CCMR2_OC4CE (1 << 15) + +/* OC4M[2:0]: Output compare 4 mode */ +#define TIM_CCMR2_OC4M_FROZEN (0x0 << 12) +#define TIM_CCMR2_OC4M_ACTIVE (0x1 << 12) +#define TIM_CCMR2_OC4M_INACTIVE (0x2 << 12) +#define TIM_CCMR2_OC4M_TOGGLE (0x3 << 12) +#define TIM_CCMR2_OC4M_FORCE_LOW (0x4 << 12) +#define TIM_CCMR2_OC4M_FORCE_HIGH (0x5 << 12) +#define TIM_CCMR2_OC4M_PWM1 (0x6 << 12) +#define TIM_CCMR2_OC4M_PWM2 (0x7 << 12) +#define TIM_CCMR2_OC4M_MASK (0x7 << 12) + +/* OC4PE: Output compare 4 preload enable */ +#define TIM_CCMR2_OC4PE (1 << 11) + +/* OC4FE: Output compare 4 fast enable */ +#define TIM_CCMR2_OC4FE (1 << 10) + +/* CC4S[1:0]: Capture/compare 4 selection */ +/* Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in + * TIMx_CCER). */ +#define TIM_CCMR2_CC4S_OUT (0x0 << 8) +#define TIM_CCMR2_CC4S_IN_TI2 (0x1 << 8) +#define TIM_CCMR2_CC4S_IN_TI1 (0x2 << 8) +#define TIM_CCMR2_CC4S_IN_TRC (0x3 << 8) +#define TIM_CCMR2_CC4S_MASK (0x3 << 8) + +/* OC3CE: Output compare 3 clear enable */ +#define TIM_CCMR2_OC3CE (1 << 7) + +/* OC3M[2:0]: Output compare 3 mode */ +#define TIM_CCMR2_OC3M_FROZEN (0x0 << 4) +#define TIM_CCMR2_OC3M_ACTIVE (0x1 << 4) +#define TIM_CCMR2_OC3M_INACTIVE (0x2 << 4) +#define TIM_CCMR2_OC3M_TOGGLE (0x3 << 4) +#define TIM_CCMR2_OC3M_FORCE_LOW (0x4 << 4) +#define TIM_CCMR2_OC3M_FORCE_HIGH (0x5 << 4) +#define TIM_CCMR2_OC3M_PWM1 (0x6 << 4) +#define TIM_CCMR2_OC3M_PWM2 (0x7 << 4) +#define TIM_CCMR2_OC3M_MASK (0x7 << 4) + +/* OC3PE: Output compare 3 preload enable */ +#define TIM_CCMR2_OC3PE (1 << 3) + +/* OC3FE: Output compare 3 fast enable */ +#define TIM_CCMR2_OC3FE (1 << 2) + +/* CC3S[1:0]: Capture/compare 3 selection */ +/* Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in + * TIMx_CCER). */ +#define TIM_CCMR2_CC3S_OUT (0x0 << 0) +#define TIM_CCMR2_CC3S_IN_TI2 (0x1 << 0) +#define TIM_CCMR2_CC3S_IN_TI1 (0x2 << 0) +#define TIM_CCMR2_CC3S_IN_TRC (0x3 << 0) +#define TIM_CCMR2_CC3S_MASK (0x3 << 0) + +/* --- Input capture mode --- */ + +/* IC4F[3:0]: Input capture 4 filter */ +#define TIM_CCMR2_IC4F_OFF (0x0 << 12) +#define TIM_CCMR2_IC4F_CK_INT_N_2 (0x1 << 12) +#define TIM_CCMR2_IC4F_CK_INT_N_4 (0x2 << 12) +#define TIM_CCMR2_IC4F_CK_INT_N_8 (0x3 << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_2_N_6 (0x4 << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_2_N_8 (0x5 << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_4_N_6 (0x6 << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_4_N_8 (0x7 << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_8_N_6 (0x8 << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_8_N_8 (0x9 << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_16_N_5 (0xA << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_16_N_6 (0xB << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_16_N_8 (0xC << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_32_N_5 (0xD << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_32_N_6 (0xE << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_32_N_8 (0xF << 12) +#define TIM_CCMR2_IC4F_MASK (0xF << 12) + +/* IC4PSC[1:0]: Input capture 4 prescaler */ +#define TIM_CCMR2_IC4PSC_OFF (0x0 << 10) +#define TIM_CCMR2_IC4PSC_2 (0x1 << 10) +#define TIM_CCMR2_IC4PSC_4 (0x2 << 10) +#define TIM_CCMR2_IC4PSC_8 (0x3 << 10) +#define TIM_CCMR2_IC4PSC_MASK (0x3 << 10) + +/* IC3F[3:0]: Input capture 3 filter */ +#define TIM_CCMR2_IC3F_OFF (0x0 << 4) +#define TIM_CCMR2_IC3F_CK_INT_N_2 (0x1 << 4) +#define TIM_CCMR2_IC3F_CK_INT_N_4 (0x2 << 4) +#define TIM_CCMR2_IC3F_CK_INT_N_8 (0x3 << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_2_N_6 (0x4 << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_2_N_8 (0x5 << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_4_N_6 (0x6 << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_4_N_8 (0x7 << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_8_N_6 (0x8 << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_8_N_8 (0x9 << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_16_N_5 (0xA << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_16_N_6 (0xB << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_16_N_8 (0xC << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_32_N_5 (0xD << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_32_N_6 (0xE << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_32_N_8 (0xF << 4) +#define TIM_CCMR2_IC3F_MASK (0xF << 4) + +/* IC3PSC[1:0]: Input capture 3 prescaler */ +#define TIM_CCMR2_IC3PSC_OFF (0x0 << 2) +#define TIM_CCMR2_IC3PSC_2 (0x1 << 2) +#define TIM_CCMR2_IC3PSC_4 (0x2 << 2) +#define TIM_CCMR2_IC3PSC_8 (0x3 << 2) +#define TIM_CCMR2_IC3PSC_MASK (0x3 << 2) + +/* --- TIMx_CCER values ---------------------------------------------------- */ + +/* CC4P: Capture/compare 4 output polarity */ +#define TIM_CCER_CC4P (1 << 13) + +/* CC4E: Capture/compare 4 output enable */ +#define TIM_CCER_CC4E (1 << 12) + +/* CC3NP: Capture/compare 3 complementary output polarity */ +#define TIM_CCER_CC3NP (1 << 11) + +/* CC3NE: Capture/compare 3 complementary output enable */ +#define TIM_CCER_CC3NE (1 << 10) + +/* CC3P: Capture/compare 3 output polarity */ +#define TIM_CCER_CC3P (1 << 9) + +/* CC3E: Capture/compare 3 output enable */ +#define TIM_CCER_CC3E (1 << 8) + +/* CC2NP: Capture/compare 2 complementary output polarity */ +#define TIM_CCER_CC2NP (1 << 7) + +/* CC2NE: Capture/compare 2 complementary output enable */ +#define TIM_CCER_CC2NE (1 << 6) + +/* CC2P: Capture/compare 2 output polarity */ +#define TIM_CCER_CC2P (1 << 5) + +/* CC2E: Capture/compare 2 output enable */ +#define TIM_CCER_CC2E (1 << 4) + +/* CC1NP: Capture/compare 1 complementary output polarity */ +#define TIM_CCER_CC1NP (1 << 3) + +/* CC1NE: Capture/compare 1 complementary output enable */ +#define TIM_CCER_CC1NE (1 << 2) + +/* CC1P: Capture/compare 1 output polarity */ +#define TIM_CCER_CC1P (1 << 1) + +/* CC1E: Capture/compare 1 output enable */ +#define TIM_CCER_CC1E (1 << 0) + +/* --- TIMx_CNT values ----------------------------------------------------- */ + +/* CNT[15:0]: Counter value */ + +/* --- TIMx_PSC values ----------------------------------------------------- */ + +/* PSC[15:0]: Prescaler value */ + +/* --- TIMx_ARR values ----------------------------------------------------- */ + +/* ARR[15:0]: Prescaler value */ + +/* --- TIMx_RCR values ----------------------------------------------------- */ + +/* REP[15:0]: Repetition counter value */ + +/* --- TIMx_CCR1 values ---------------------------------------------------- */ + +/* CCR1[15:0]: Capture/compare 1 value */ + +/* --- TIMx_CCR2 values ---------------------------------------------------- */ + +/* CCR2[15:0]: Capture/compare 2 value */ + +/* --- TIMx_CCR3 values ---------------------------------------------------- */ + +/* CCR3[15:0]: Capture/compare 3 value */ + +/* --- TIMx_CCR4 values ---------------------------------------------------- */ + +/* CCR4[15:0]: Capture/compare 4 value */ + +/* --- TIMx_BDTR values ---------------------------------------------------- */ + +/* MOE: Main output enable */ +#define TIM_BDTR_MOE (1 << 15) + +/* AOE: Automatic output enable */ +#define TIM_BDTR_AOE (1 << 14) + +/* BKP: Break polarity */ +#define TIM_BDTR_BKP (1 << 13) + +/* BKE: Break enable */ +#define TIM_BDTR_BKE (1 << 12) + +/* OSSR: Off-state selection of run mode */ +#define TIM_BDTR_OSSR (1 << 11) + +/* OSSI: Off-state selection of idle mode */ +#define TIM_BDTR_OSSI (1 << 10) + +/* LOCK[1:0]: Lock configuration */ +#define TIM_BDTR_LOCK_OFF (0x0 << 8) +#define TIM_BDTR_LOCK_LEVEL_1 (0x1 << 8) +#define TIM_BDTR_LOCK_LEVEL_2 (0x2 << 8) +#define TIM_BDTR_LOCK_LEVEL_3 (0x3 << 8) +#define TIM_BDTR_LOCK_MASK (0x3 << 8) + +/* DTG[7:0]: Dead-time generator set-up */ +#define TIM_BDTR_DTG_MASK 0x00FF + +/* --- TIMx_DCR values ----------------------------------------------------- */ + +/* DBL[4:0]: DMA burst length */ +#define TIM_BDTR_DBL_MASK (0x1F << 8) + +/* DBA[4:0]: DMA base address */ +#define TIM_BDTR_DBA_MASK (0x1F << 0) + +/* --- TIMx_DMAR values ---------------------------------------------------- */ + +/* DMAB[15:0]: DMA register for burst accesses */ + +/* --- TIMx convenience defines -------------------------------------------- */ + +/* Output Compare channel designators */ +enum tim_oc_id { + TIM_OC1=0, + TIM_OC1N, + TIM_OC2, + TIM_OC2N, + TIM_OC3, + TIM_OC3N, + TIM_OC4, +}; + +/* Output Compare mode designators */ +enum tim_oc_mode { + TIM_OCM_FROZEN, + TIM_OCM_ACTIVE, + TIM_OCM_INACTIVE, + TIM_OCM_TOGGLE, + TIM_OCM_FORCE_LOW, + TIM_OCM_FORCE_HIGH, + TIM_OCM_PWM1, + TIM_OCM_PWM2, +}; + +/* --- TIM functions ------------------------------------------------------- */ +void timer_reset(u32 timer_peripheral); +void timer_enable_irq(u32 timer_peripheral, u32 irq); +void timer_disable_irq(u32 timer_peripheral, u32 irq); +bool timer_get_flag(u32 timer_peripheral, u32 flag); +void timer_clear_flag(u32 timer_peripheral, u32 flag); +void timer_set_mode(u32 timer_peripheral, u8 clock_div, + u8 alignment, u8 direction); +void timer_set_clock_division(u32 timer_peripheral, u32 clock_div); +void timer_enable_preload(u32 timer_peripheral); +void timer_disable_preload(u32 timer_peripheral); +void timer_set_alignment(u32 timer_peripheral, u32 alignment); +void timer_direction_up(u32 timer_peripheral); +void timer_direction_down(u32 timer_peripheral); +void timer_one_shot_mode(u32 timer_peripheral); +void timer_continuous_mode(u32 timer_peripheral); +void timer_update_on_any(u32 timer_peripheral); +void timer_update_on_overflow(u32 timer_peripheral); +void timer_enable_update_event(u32 timer_peripheral); +void timer_disable_update_event(u32 timer_peripheral); +void timer_enable_counter(u32 timer_peripheral); +void timer_disable_counter(u32 timer_peripheral); +void timer_set_output_idle_state(u32 timer_peripheral, u32 outputs); +void timer_reset_output_idle_state(u32 timer_peripheral, u32 outputs); +void timer_set_ti1_ch123_xor(u32 timer_peripheral); +void timer_set_ti1_ch1(u32 timer_peripheral); +void timer_set_master_mode(u32 timer_peripheral, u32 mode); +void timer_set_dma_on_compare_event(u32 timer_peripheral); +void timer_set_dma_on_update_event(u32 timer_peripheral); +void timer_enable_compare_control_update_on_trigger(u32 timer_peripheral); +void timer_disable_compare_control_update_on_trigger(u32 timer_peripheral); +void timer_enable_preload_complementry_enable_bits(u32 timer_peripheral); +void timer_disable_preload_complementry_enable_bits(u32 timer_peripheral); +void timer_set_prescaler(u32 timer_peripheral, u32 value); +void timer_set_repetition_counter(u32 timer_peripheral, u32 value); +void timer_set_period(u32 timer_peripheral, u32 period); +void timer_enable_oc_clear(u32 timer_peripheral, enum tim_oc_id oc_id); +void timer_disable_oc_clear(u32 timer_peripheral, enum tim_oc_id oc_id); +void timer_set_oc_fast_mode(u32 timer_peripheral, enum tim_oc_id oc_id); +void timer_set_oc_slow_mode(u32 timer_peripheral, enum tim_oc_id oc_id); +void timer_set_oc_mode(u32 timer_peripheral, enum tim_oc_id oc_id, enum tim_oc_mode oc_mode); +void timer_enable_oc_preload(u32 timer_peripheral, enum tim_oc_id oc_id); +void timer_disable_oc_preload(u32 timer_peripheral, enum tim_oc_id oc_id); +void timer_set_oc_polarity_high(u32 timer_peripheral, enum tim_oc_id oc_id); +void timer_set_oc_polarity_low(u32 timer_peripheral, enum tim_oc_id oc_id); +void timer_enable_oc_output(u32 timer_peripheral, enum tim_oc_id oc_id); +void timer_disable_oc_output(u32 timer_peripheral, enum tim_oc_id oc_id); +void timer_set_oc_idle_state_set(u32 timer_peripheral, enum tim_oc_id oc_id); +void timer_set_oc_idle_state_unset(u32 timer_peripheral, enum tim_oc_id oc_id); +void timer_set_oc_value(u32 timer_peripheral, enum tim_oc_id oc_id, u32 value); +void timer_enable_break_main_output(u32 timer_peripheral); +void timer_disable_break_main_output(u32 timer_peripheral); +void timer_enable_break_automatic_output(u32 timer_peripheral); +void timer_disable_break_automatic_output(u32 timer_peripheral); +void timer_set_break_polarity_high(u32 timer_peripheral); +void timer_set_break_polarity_low(u32 timer_peripheral); +void timer_enable_break(u32 timer_peripheral); +void timer_disable_break(u32 timer_peripheral); +void timer_set_enabled_off_state_in_run_mode(u32 timer_peripheral); +void timer_set_disabled_off_state_in_run_mode(u32 timer_peripheral); +void timer_set_enabled_off_state_in_idle_mode(u32 timer_peripheral); +void timer_set_disabled_off_state_in_idle_mode(u32 timer_peripheral); +void timer_set_break_lock(u32 timer_peripheral, u32 lock); +void timer_set_deadtime(u32 timer_peripheral, u32 deadtime); +void timer_generate_event(u32 timer_peripheral, u32 event); +u32 timer_get_counter(u32 timer_peripheral); + +#endif diff --git a/include/libopencm3/stm32/usart.h b/include/libopencm3/stm32/usart.h new file mode 100644 index 0000000..df6bc08 --- /dev/null +++ b/include/libopencm3/stm32/usart.h @@ -0,0 +1,312 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_USART_H +#define LIBOPENCM3_USART_H + +#include +#include + +/* --- Convenience macros -------------------------------------------------- */ + +#define USART1 USART1_BASE +#define USART2 USART2_BASE +#define USART3 USART3_BASE +#define UART4 UART4_BASE +#define UART5 UART5_BASE + +/* --- USART registers ----------------------------------------------------- */ + +/* Status register (USARTx_SR) */ +#define USART_SR(usart_base) MMIO32(usart_base + 0x00) +#define USART1_SR USART_SR(USART1_BASE) +#define USART2_SR USART_SR(USART2_BASE) +#define USART3_SR USART_SR(USART3_BASE) +#define UART4_SR USART_SR(UART4_BASE) +#define UART5_SR USART_SR(UART5_BASE) + +/* Data register (USARTx_DR) */ +#define USART_DR(usart_base) MMIO32(usart_base + 0x04) +#define USART1_DR USART_DR(USART1_BASE) +#define USART2_DR USART_DR(USART2_BASE) +#define USART3_DR USART_DR(USART3_BASE) +#define UART4_DR USART_DR(UART4_BASE) +#define UART5_DR USART_DR(UART5_BASE) + +/* Baud rate register (USARTx_BRR) */ +#define USART_BRR(usart_base) MMIO32(usart_base + 0x08) +#define USART1_BRR USART_BRR(USART1_BASE) +#define USART2_BRR USART_BRR(USART2_BASE) +#define USART3_BRR USART_BRR(USART3_BASE) +#define UART4_BRR USART_BRR(UART4_BASE) +#define UART5_BRR USART_BRR(UART5_BASE) + +/* Control register 1 (USARTx_CR1) */ +#define USART_CR1(usart_base) MMIO32(usart_base + 0x0c) +#define USART1_CR1 USART_CR1(USART1_BASE) +#define USART2_CR1 USART_CR1(USART2_BASE) +#define USART3_CR1 USART_CR1(USART3_BASE) +#define UART4_CR1 USART_CR1(UART4_BASE) +#define UART5_CR1 USART_CR1(UART5_BASE) + +/* Control register 2 (USARTx_CR2) */ +#define USART_CR2(usart_base) MMIO32(usart_base + 0x10) +#define USART1_CR2 USART_CR2(USART1_BASE) +#define USART2_CR2 USART_CR2(USART2_BASE) +#define USART3_CR2 USART_CR2(USART3_BASE) +#define UART4_CR2 USART_CR2(UART4_BASE) +#define UART5_CR2 USART_CR2(UART5_BASE) + +/* Control register 3 (USARTx_CR3) */ +#define USART_CR3(usart_base) MMIO32(usart_base + 0x14) +#define USART1_CR3 USART_CR3(USART1_BASE) +#define USART2_CR3 USART_CR3(USART2_BASE) +#define USART3_CR3 USART_CR3(USART3_BASE) +#define UART4_CR3 USART_CR3(UART4_BASE) +#define UART5_CR3 USART_CR3(UART5_BASE) + +/* Guard time and prescaler register (USARTx_GTPR) */ +#define USART_GTPR(usart_base) MMIO32(usart_base + 0x18) +#define USART1_GTPR USART_GTPR(USART1_BASE) +#define USART2_GTPR USART_GTPR(USART2_BASE) +#define USART3_GTPR USART_GTPR(USART3_BASE) +#define UART4_GTPR USART_GTPR(UART4_BASE) +#define UART5_GTPR USART_GTPR(UART5_BASE) + +/* --- USART_SR values ----------------------------------------------------- */ + +/* CTS: CTS flag */ +/* Note: N/A on UART4/5 */ +#define USART_SR_CTS (1 << 9) + +/* LBD: LIN break detection flag */ +#define USART_SR_LBD (1 << 8) + +/* TXE: Transmit data buffer empty */ +#define USART_SR_TXE (1 << 7) + +/* TC: Transmission complete */ +#define USART_SR_TC (1 << 6) + +/* RXNE: Read data register not empty */ +#define USART_SR_RXNE (1 << 5) + +/* IDLE: Idle line detected */ +#define USART_SR_IDLE (1 << 4) + +/* ORE: Overrun error */ +#define USART_SR_ORE (1 << 3) + +/* NE: Noise error flag */ +#define USART_SR_NE (1 << 2) + +/* FE: Framing error */ +#define USART_SR_FE (1 << 1) + +/* PE: Parity error */ +#define USART_SR_PE (1 << 0) + +/* --- USART_DR values ----------------------------------------------------- */ + +/* USART_DR[8:0]: DR[8:0]: Data value */ +#define USART_DR_MASK 0x1FF + +/* --- USART_BRR values ---------------------------------------------------- */ + +/* DIV_Mantissa[11:0]: mantissa of USARTDIV */ +#define USART_BRR_DIV_MANTISSA_MASK (0xFFF << 4) +/* DIV_Fraction[3:0]: fraction of USARTDIV */ +#define USART_BRR_DIV_FRACTION_MASK 0xF + +/* --- USART_CR1 values ---------------------------------------------------- */ + +/* UE: USART enable */ +#define USART_CR1_UE (1 << 13) + +/* M: Word length */ +#define USART_CR1_M (1 << 12) + +/* WAKE: Wakeup method */ +#define USART_CR1_WAKE (1 << 11) + +/* PCE: Parity control enable */ +#define USART_CR1_PCE (1 << 10) + +/* PS: Parity selection */ +#define USART_CR1_PS (1 << 9) + +/* PEIE: PE interrupt enable */ +#define USART_CR1_PEIE (1 << 8) + +/* TXEIE: TXE interrupt enable */ +#define USART_CR1_TXEIE (1 << 7) + +/* TCIE: Transmission complete interrupt enable */ +#define USART_CR1_TCIE (1 << 6) + +/* RXNEIE: RXNE interrupt enable */ +#define USART_CR1_RXNEIE (1 << 5) + +/* IDLEIE: IDLE interrupt enable */ +#define USART_CR1_IDLEIE (1 << 4) + +/* TE: Transmitter enable */ +#define USART_CR1_TE (1 << 3) + +/* RE: Receiver enable */ +#define USART_CR1_RE (1 << 2) + +/* RWU: Receiver wakeup */ +#define USART_CR1_RWU (1 << 1) + +/* SBK: Send break */ +#define USART_CR1_SBK (1 << 0) + +/* --- USART_CR2 values ---------------------------------------------------- */ + +/* LINEN: LIN mode enable */ +#define USART_CR2_LINEN (1 << 14) + +/* STOP[13:12]: STOP bits */ +#define USART_CR2_STOPBITS_1 (0x00 << 12) /* 1 stop bit */ +#define USART_CR2_STOPBITS_0_5 (0x01 << 12) /* 0.5 stop bits */ +#define USART_CR2_STOPBITS_2 (0x02 << 12) /* 2 stop bits */ +#define USART_CR2_STOPBITS_1_5 (0x03 << 12) /* 1.5 stop bits */ +#define USART_CR2_STOPBITS_MASK (0x03 << 12) +#define USART_CR2_STOPBITS_SHIFT 12 + +/* CLKEN: Clock enable */ +#define USART_CR2_CLKEN (1 << 11) + +/* CPOL: Clock polarity */ +#define USART_CR2_CPOL (1 << 10) + +/* CPHA: Clock phase */ +#define USART_CR2_CPHA (1 << 9) + +/* LBCL: Last bit clock pulse */ +#define USART_CR2_LBCL (1 << 8) + +/* LBDIE: LIN break detection interrupt enable */ +#define USART_CR2_LBDIE (1 << 6) + +/* LBDL: LIN break detection length */ +#define USART_CR2_LBDL (1 << 5) + +/* ADD[3:0]: Addres of the usart node */ +#define USART_CR2_ADD_MASK 0xF + +/* --- USART_CR3 values ---------------------------------------------------- */ + +/* CTSIE: CTS interrupt enable */ +/* Note: N/A on UART4 & UART5 */ +#define USART_CR3_CTSIE (1 << 10) + +/* CTSE: CTS enable */ +/* Note: N/A on UART4 & UART5 */ +#define USART_CR3_CTSE (1 << 9) + +/* RTSE: RTS enable */ +/* Note: N/A on UART4 & UART5 */ +#define USART_CR3_RTSE (1 << 8) + +/* DMAT: DMA enable transmitter */ +/* Note: N/A on UART5 */ +#define USART_CR3_DMAT (1 << 7) + +/* DMAR: DMA enable receiver */ +/* Note: N/A on UART5 */ +#define USART_CR3_DMAR (1 << 6) + +/* SCEN: Smartcard mode enable */ +/* Note: N/A on UART4 & UART5 */ +#define USART_CR3_SCEN (1 << 5) + +/* NACK: Smartcard NACK enable */ +/* Note: N/A on UART4 & UART5 */ +#define USART_CR3_NACK (1 << 4) + +/* HDSEL: Half-duplex selection */ +#define USART_CR3_HDSEL (1 << 3) + +/* IRLP: IrDA low-power */ +#define USART_CR3_IRLP (1 << 2) + +/* IREN: IrDA mode enable */ +#define USART_CR3_IREN (1 << 1) + +/* EIE: Error interrupt enable */ +#define USART_CR3_EIE (1 << 0) + +/* --- USART_GTPR values --------------------------------------------------- */ + +/* GT[7:0]: Guard time value */ +/* Note: N/A on UART4 & UART5 */ +#define USART_GTPR_GT_MASK (0xFF << 8) + +/* PSC[7:0]: Prescaler value */ +/* Note: N/A on UART4/5 */ +#define USART_GTPR_PSC_MASK 0xFF + +/* TODO */ /* Note to Uwe: what needs to be done here? */ + +/* --- Convenience defines ------------------------------------------------- */ + +/* CR1_PCE / CR1_PS combined values */ +#define USART_PARITY_NONE 0x00 +#define USART_PARITY_ODD USART_CR1_PS +#define USART_PARITY_EVEN (USART_CR1_PS | USART_CR1_PCE) +#define USART_PARITY_MASK (USART_CR1_PS | USART_CR1_PCE) + +/* CR1_TE/CR1_RE combined values */ +#define USART_MODE_RX USART_CR1_RE +#define USART_MODE_TX USART_CR1_TE +#define USART_MODE_TX_RX (USART_CR1_RE | USART_CR1_TE) +#define USART_MODE_MASK (USART_CR1_RE | USART_CR1_TE) + +#define USART_STOPBITS_1 USART_CR2_STOPBITS_1 /* 1 stop bit */ +#define USART_STOPBITS_0_5 USART_CR2_STOPBITS_0_5 /* 0.5 stop bits */ +#define USART_STOPBITS_2 USART_CR2_STOPBITS_2 /* 2 stop bits */ +#define USART_STOPBITS_1_5 USART_CR2_STOPBITS_1_5 /* 1.5 stop bits */ + +/* CR3_CTSE/CR3_RTSE combined values */ +#define USART_FLOWCONTROL_NONE 0x00 +#define USART_FLOWCONTROL_RTS USART_CR3_RTSE +#define USART_FLOWCONTROL_CTS USART_CR3_CTSE +#define USART_FLOWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) +#define USART_FLOWCONTROL_MASK (USART_CR3_RTSE | USART_CR3_CTSE) + +/* --- Function prototypes ------------------------------------------------- */ + +void usart_set_baudrate(u32 usart, u32 baud); +void usart_set_databits(u32 usart, u32 bits); +void usart_set_stopbits(u32 usart, u32 stopbits); +void usart_set_parity(u32 usart, u32 parity); +void usart_set_mode(u32 usart, u32 mode); +void usart_set_flow_control(u32 usart, u32 flowcontrol); +void usart_enable(u32 usart); +void usart_disable(u32 usart); +void usart_send(u32 usart, u16 data); +u16 usart_recv(u32 usart); +void usart_wait_send_ready(u32 usart); +void usart_wait_recv_ready(u32 usart); +void usart_send_blocking(u32 usart, u16 data); +u16 usart_recv_blocking(u32 usart); + +#endif diff --git a/include/libopencm3/stm32/wwdg.h b/include/libopencm3/stm32/wwdg.h new file mode 100644 index 0000000..552d02e --- /dev/null +++ b/include/libopencm3/stm32/wwdg.h @@ -0,0 +1,74 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_WWDG_H +#define LIBOPENCM3_WWDG_H + +#include +#include + +/* --- WWDG registers ------------------------------------------------------ */ + +/* Control register (WWDG_CR) */ +#define WWDG_CR MMIO32(WWDG_BASE + 0x00) + +/* Configuration register (WWDG_CFR) */ +#define WWDG_CFR MMIO32(WWDG_BASE + 0x04) + +/* Status register (WWDG_SR) */ +#define WWDG_SR MMIO32(WWDG_BASE + 0x08) + +/* --- WWDG_CR values ------------------------------------------------------ */ + +/* WDGA: Activation bit */ +#define WWDG_CR_WDGA (1 << 7) + +/* T[6:0]: 7-bit counter (MSB to LSB) */ +#define WWDG_CR_T_LSB 0 +#define WWDG_CR_T0 (1 << 0) +#define WWDG_CR_T1 (1 << 1) +#define WWDG_CR_T2 (1 << 2) +#define WWDG_CR_T3 (1 << 3) +#define WWDG_CR_T4 (1 << 4) +#define WWDG_CR_T5 (1 << 5) +#define WWDG_CR_T6 (1 << 6) + +/* --- WWDG_CFR values ----------------------------------------------------- */ + +/* EWI: Early wakeup interrupt */ +#define WWDG_CFR_EWI (1 << 9) + +/* WDGTB[8:7]: Timer base */ +#define WWDG_CFR_WDGTB_LSB 7 +#define WWDG_CFR_WDGTB_CK_DIV1 0x0 +#define WWDG_CFR_WDGTB_CK_DIV2 0x1 +#define WWDG_CFR_WDGTB_CK_DIV4 0x2 +#define WWDG_CFR_WDGTB_CK_DIV8 0x3 + +/* W[6:0]: 7-bit window value */ +#define WWDG_CFG_W_LSB 0 + +/* --- WWDG_SR values ------------------------------------------------------ */ + +/* EWIF: Early wakeup interrupt flag */ +#define WWDG_SR_EWIF (1 << 0) + +/* --- WWDG funtion prototypes---------------------------------------------- */ + +#endif diff --git a/include/libopencm3/stm32_common/can.h b/include/libopencm3/stm32_common/can.h deleted file mode 100644 index eeac5d8..0000000 --- a/include/libopencm3/stm32_common/can.h +++ /dev/null @@ -1,642 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_CAN_H -#define LIBOPENCM3_CAN_H - -#include -#include - -/* --- Convenience macros -------------------------------------------------- */ - -/* CAN register base adresses (for convenience) */ -#define CAN1 BX_CAN1_BASE -#define CAN2 BX_CAN2_BASE - -/* --- CAN registers ------------------------------------------------------- */ - -/* CAN master control register (CAN_MCR) */ -#define CAN_MCR(can_base) MMIO32(can_base + 0x000) -/* CAN master status register (CAN_MSR) */ -#define CAN_MSR(can_base) MMIO32(can_base + 0x004) -/* CAN transmit status register (CAN_TSR) */ -#define CAN_TSR(can_base) MMIO32(can_base + 0x008) - -/* CAN receive FIFO 0 register (CAN_RF0R) */ -#define CAN_RF0R(can_base) MMIO32(can_base + 0x00C) -/* CAN receive FIFO 1 register (CAN_RF1R) */ -#define CAN_RF1R(can_base) MMIO32(can_base + 0x010) - -/* CAN interrupt enable register (CAN_IER) */ -#define CAN_IER(can_base) MMIO32(can_base + 0x014) -/* CAN error status register (CAN_ESR) */ -#define CAN_ESR(can_base) MMIO32(can_base + 0x018) -/* CAN bit timing register (CAN_BTR) */ -#define CAN_BTR(can_base) MMIO32(can_base + 0x01C) - -/* Registers in the offset range 0x020 to 0x17F are reserved. */ - -/* --- CAN mailbox registers ----------------------------------------------- */ - -/* CAN mailbox / FIFO register offsets */ -#define CAN_MBOX0 0x180 -#define CAN_MBOX1 0x190 -#define CAN_MBOX2 0x1A0 -#define CAN_FIFO0 0x1B0 -#define CAN_FIFO1 0x1C0 - -/* CAN TX mailbox identifier register (CAN_TIxR) */ -#define CAN_TIxR(can_base, mbox) MMIO32(can_base + mbox + 0x0) -#define CAN_TI0R(can_base) CAN_TIxR(can_base, CAN_MBOX0) -#define CAN_TI1R(can_base) CAN_TIxR(can_base, CAN_MBOX1) -#define CAN_TI2R(can_base) CAN_TIxR(can_base, CAN_MBOX2) - -/* CAN mailbox data length control and time stamp register (CAN_TDTxR) */ -#define CAN_TDTxR(can_base, mbox) MMIO32(can_base + mbox + 0x4) -#define CAN_TDT0R(can_base) CAN_TDTxR(can_base, CAN_MBOX0) -#define CAN_TDT1R(can_base) CAN_TDTxR(can_base, CAN_MBOX1) -#define CAN_TDT2R(can_base) CAN_TDTxR(can_base, CAN_MBOX2) - -/* CAN mailbox data low register (CAN_TDLxR) */ -#define CAN_TDLxR(can_base, mbox) MMIO32(can_base + mbox + 0x8) -#define CAN_TDL0R(can_base) CAN_TDLxR(can_base, CAN_MBOX0) -#define CAN_TDL1R(can_base) CAN_TDLxR(can_base, CAN_MBOX1) -#define CAN_TDL2R(can_base) CAN_TDLxR(can_base, CAN_MBOX2) - -/* CAN mailbox data high register (CAN_TDHxR) */ -#define CAN_TDHxR(can_base, mbox) MMIO32(can_base + mbox + 0xC) -#define CAN_TDH0R(can_base) CAN_TDHxR(can_base, CAN_MBOX0) -#define CAN_TDH1R(can_base) CAN_TDHxR(can_base, CAN_MBOX1) -#define CAN_TDH2R(can_base) CAN_TDHxR(can_base, CAN_MBOX2) - -/* CAN RX FIFO identifier register (CAN_RIxR) */ -#define CAN_RIxR(can_base, fifo) MMIO32(can_base + fifo + 0x0) -#define CAN_RI0R(can_base) CAN_RIxR(can_base, CAN_FIFO0) -#define CAN_RI1R(can_base) CAN_RIxR(can_base, CAN_FIFO1) - -/* CAN RX FIFO mailbox data length control & time stamp register (CAN_RDTxR) */ -#define CAN_RDTxR(can_base, fifo) MMIO32(can_base + fifo + 0x4) -#define CAN_RDT0R(can_base) CAN_RDTxR(can_base, CAN_FIFO0) -#define CAN_RDT1R(can_base) CAN_RDTxR(can_base, CAN_FIFO1) - -/* CAN RX FIFO mailbox data low register (CAN_RDLxR) */ -#define CAN_RDLxR(can_base, fifo) MMIO32(can_base + fifo + 0x8) -#define CAN_RDL0R(can_base) CAN_RDLxR(can_base, CAN_FIFO0) -#define CAN_RDL1R(can_base) CAN_RDLxR(can_base, CAN_FIFO1) - -/* CAN RX FIFO mailbox data high register (CAN_RDHxR) */ -#define CAN_RDHxR(can_base, fifo) MMIO32(can_base + fifo + 0xC) -#define CAN_RDH0R(can_base) CAN_RDHxR(can_base, CAN_FIFO0) -#define CAN_RDH1R(can_base) CAN_RDHxR(can_base, CAN_FIFO1) - -/* --- CAN filter registers ------------------------------------------------ */ - -/* CAN filter master register (CAN_FMR) */ -#define CAN_FMR(can_base) MMIO32(can_base + 0x200) - -/* CAN filter mode register (CAN_FM1R) */ -#define CAN_FM1R(can_base) MMIO32(can_base + 0x204) - -/* Register offset 0x208 is reserved. */ - -/* CAN filter scale register (CAN_FS1R) */ -#define CAN_FS1R(can_base) MMIO32(can_base + 0x20C) - -/* Register offset 0x210 is reserved. */ - -/* CAN filter FIFO assignement register (CAN_FFA1R) */ -#define CAN_FFA1R(can_base) MMIO32(can_base + 0x214) - -/* Register offset 0x218 is reserved. */ - -/* CAN filter activation register (CAN_FA1R) */ -#define CAN_FA1R(can_base) MMIO32(can_base + 0x21C) - -/* Register offset 0x220 is reserved. */ - -/* Registers with offset 0x224 to 0x23F are reserved. */ - -/* CAN filter bank registers (CAN_FiRx) */ -/* - * Connectivity line devices have 28 banks so the bank ID spans 0..27 - * all other devices have 14 banks so the bank ID spans 0..13. - */ -#define CAN_FiR1(can_base, bank) MMIO32(can_base + 0x240 + (bank * 0x8) + 0x0) -#define CAN_FiR2(can_base, bank) MMIO32(can_base + 0x240 + (bank * 0x8) + 0x4) - -/* --- CAN_MCR values ------------------------------------------------------ */ - -/* 31:17 Reserved, forced by hardware to 0 */ - -/* DBF: Debug freeze */ -#define CAN_MCR_DBF (1 << 16) - -/* RESET: bxCAN software master reset */ -#define CAN_MCR_RESET (1 << 15) - -/* 14:8 Reserved, forced by hardware to 0 */ - -/* TTCM: Time triggered communication mode */ -#define CAN_MCR_TTCM (1 << 7) - -/* ABOM: Automatic bus-off management */ -#define CAN_MCR_ABOM (1 << 6) - -/* AWUM: Automatic wakeup mode */ -#define CAN_MCR_AWUM (1 << 5) - -/* NART: No automatic retransmission */ -#define CAN_MCR_NART (1 << 4) - -/* RFLM: Receive FIFO locked mode */ -#define CAN_MCR_RFLM (1 << 3) - -/* TXFP: Transmit FIFO priority */ -#define CAN_MCR_TXFP (1 << 2) - -/* SLEEP: Sleep mode request */ -#define CAN_MCR_SLEEP (1 << 1) - -/* INRQ: Initialization request */ -#define CAN_MCR_INRQ (1 << 0) - -/* --- CAN_MSR values ------------------------------------------------------ */ - -/* 31:12 Reserved, forced by hardware to 0 */ - -/* RX: CAN Rx signal */ -#define CAN_MSR_RX (1 << 11) - -/* SAMP: Last sample point */ -#define CAN_MSR_SAMP (1 << 10) - -/* RXM: Receive mode */ -#define CAN_MSR_RXM (1 << 9) - -/* TXM: Transmit mode */ -#define CAN_MSR_TXM (1 << 8) - -/* 7:5 Reserved, forced by hardware to 0 */ - -/* SLAKI: Sleep acknowledge interrupt */ -#define CAN_MSR_SLAKI (1 << 4) - -/* WKUI: Wakeup interrupt */ -#define CAN_MSR_WKUI (1 << 3) - -/* ERRI: Error interrupt */ -#define CAN_MSR_ERRI (1 << 2) - -/* SLAK: Sleep acknowledge */ -#define CAN_MSR_SLAK (1 << 1) - -/* INAK: Initialization acknowledge */ -#define CAN_MSR_INAK (1 << 0) - -/* --- CAN_TSR values ------------------------------------------------------ */ - -/* LOW2: Lowest priority flag for mailbox 2 */ -#define CAN_TSR_LOW2 (1 << 31) - -/* LOW1: Lowest priority flag for mailbox 1 */ -#define CAN_TSR_LOW1 (1 << 30) - -/* LOW0: Lowest priority flag for mailbox 0 */ -#define CAN_TSR_LOW0 (1 << 29) - -/* TME2: Transmit mailbox 2 empty */ -#define CAN_TSR_TME2 (1 << 28) - -/* TME1: Transmit mailbox 1 empty */ -#define CAN_TSR_TME1 (1 << 27) - -/* TME0: Transmit mailbox 0 empty */ -#define CAN_TSR_TME0 (1 << 26) - -/* CODE[1:0]: Mailbox code */ -#define CAN_TSR_CODE_MASK (0x3 << 24) - -/* ABRQ2: Abort request for mailbox 2 */ -#define CAN_TSR_TABRQ2 (1 << 23) - -/* 22:20 Reserved, forced by hardware to 0 */ - -/* TERR2: Transmission error for mailbox 2 */ -#define CAN_TSR_TERR2 (1 << 19) - -/* ALST2: Arbitration lost for mailbox 2 */ -#define CAN_TSR_ALST2 (1 << 18) - -/* TXOK2: Transmission OK for mailbox 2 */ -#define CAN_TSR_TXOK2 (1 << 17) - -/* RQCP2: Request completed mailbox 2 */ -#define CAN_TSR_RQCP2 (1 << 16) - -/* ABRQ1: Abort request for mailbox 1 */ -#define CAN_TSR_ABRQ1 (1 << 15) - -/* 14:12 Reserved, forced by hardware to 0 */ - -/* TERR1: Transmission error for mailbox 1 */ -#define CAN_TSR_TERR1 (1 << 11) - -/* ALST1: Arbitration lost for mailbox 1 */ -#define CAN_TSR_ALST1 (1 << 10) - -/* TXOK1: Transmission OK for mailbox 1 */ -#define CAN_TSR_TXOK1 (1 << 9) - -/* RQCP1: Request completed mailbox 1 */ -#define CAN_TSR_RQCP1 (1 << 8) - -/* ABRQ0: Abort request for mailbox 0 */ -#define CAN_TSR_ABRQ0 (1 << 7) - -/* 6:4 Reserved, forced by hardware to 0 */ - -/* TERR0: Transmission error for mailbox 0 */ -#define CAN_TSR_TERR0 (1 << 3) - -/* ALST0: Arbitration lost for mailbox 0 */ -#define CAN_TSR_ALST0 (1 << 2) - -/* TXOK0: Transmission OK for mailbox 0 */ -#define CAN_TSR_TXOK0 (1 << 1) - -/* RQCP0: Request completed mailbox 0 */ -#define CAN_TSR_RQCP0 (1 << 0) - -/* --- CAN_RF0R values ----------------------------------------------------- */ - -/* 31:6 Reserved, forced by hardware to 0 */ - -/* RFOM0: Release FIFO 0 output mailbox */ -#define CAN_RF0R_RFOM0 (1 << 5) - -/* FOVR0: FIFO 0 overrun */ -#define CAN_RF0R_FAVR0 (1 << 4) - -/* FULL0: FIFO 0 full */ -#define CAN_RF0R_FULL0 (1 << 3) - -/* 2 Reserved, forced by hardware to 0 */ - -/* FMP0[1:0]: FIFO 0 message pending */ -#define CAN_RF0R_FMP0_MASK (0x3 << 0) - -/* --- CAN_RF1R values ----------------------------------------------------- */ - -/* 31:6 Reserved, forced by hardware to 0 */ - -/* RFOM1: Release FIFO 1 output mailbox */ -#define CAN_RF1R_RFOM1 (1 << 5) - -/* FOVR1: FIFO 1 overrun */ -#define CAN_RF1R_FAVR1 (1 << 4) - -/* FULL1: FIFO 1 full */ -#define CAN_RF1R_FULL1 (1 << 3) - -/* 2 Reserved, forced by hardware to 0 */ - -/* FMP1[1:0]: FIFO 1 message pending */ -#define CAN_RF1R_FMP1_MASK (0x3 << 0) - -/* --- CAN_IER values ------------------------------------------------------ */ - -/* 32:18 Reserved, forced by hardware to 0 */ - -/* SLKIE: Sleep interrupt enable */ -#define CAN_IER_SLKIE (1 << 17) - -/* WKUIE: Wakeup interrupt enable */ -#define CAN_IER_WKUIE (1 << 16) - -/* ERRIE: Error interrupt enable */ -#define CAN_IER_ERRIE (1 << 15) - -/* 14:12 Reserved, forced by hardware to 0 */ - -/* LECIE: Last error code interrupt enable */ -#define CAN_IER_LECIE (1 << 11) - -/* BOFIE: Bus-off interrupt enable */ -#define CAN_IER_BOFIE (1 << 10) - -/* EPVIE: Error passive interrupt enable */ -#define CAN_IER_EPVIE (1 << 9) - -/* EWGIE: Error warning interrupt enable */ -#define CAN_IER_EWGIE (1 << 8) - -/* 7 Reserved, forced by hardware to 0 */ - -/* FOVIE1: FIFO overrun interrupt enable */ -#define CAN_IER_FOVIE1 (1 << 6) - -/* FFIE1: FIFO full interrupt enable */ -#define CAN_IER_FFIE1 (1 << 5) - -/* FMPIE1: FIFO message pending interrupt enable */ -#define CAN_IER_FMPIE1 (1 << 4) - -/* FOVIE0: FIFO overrun interrupt enable */ -#define CAN_IER_FOVIE0 (1 << 3) - -/* FFIE0: FIFO full interrupt enable */ -#define CAN_IER_FFIE0 (1 << 2) - -/* FMPIE0: FIFO message pending interrupt enable */ -#define CAN_IER_FMPIE0 (1 << 1) - -/* TMEIE: Transmit mailbox empty interrupt enable */ -#define CAN_IER_TMEIE (1 << 0) - -/* --- CAN_ESR values ------------------------------------------------------ */ - -/* REC[7:0]: Receive error counter */ -#define CAN_ESR_REC_MASK (0xF << 24) - -/* TEC[7:0]: Least significant byte of the 9-bit transmit error counter */ -#define CAN_ESR_TEC_MASK (0xF << 16) - -/* 15:7 Reserved, forced by hardware to 0 */ - -/* LEC[2:0]: Last error code */ -#define CAN_ESR_LEC_NO_ERROR (0x0 << 4) -#define CAN_ESR_LEC_STUFF_ERROR (0x1 << 4) -#define CAN_ESR_LEC_FORM_ERROR (0x2 << 4) -#define CAN_ESR_LEC_ACK_ERROR (0x3 << 4) -#define CAN_ESR_LEC_REC_ERROR (0x4 << 4) -#define CAN_ESR_LEC_DOM_ERROR (0x5 << 4) -#define CAN_ESR_LEC_CRC_ERROR (0x6 << 4) -#define CAN_ESR_LEC_SOFT_ERROR (0x7 << 4) -#define CAN_ESR_LEC_MASK (0x7 << 4) - -/* 3 Reserved, forced by hardware to 0 */ - -/* BOFF: Bus-off flag */ -#define CAN_ESR_BOFF (1 << 2) - -/* EPVF: Error passive flag */ -#define CAN_ESR_EPVF (1 << 1) - -/* EWGF: Error warning flag */ -#define CAN_ESR_EWGF (1 << 0) - -/* --- CAN_BTR values ------------------------------------------------------ */ - -/* SILM: Silent mode (debug) */ -#define CAN_BTR_SILM (1 << 31) - -/* LBKM: Loop back mode (debug) */ -#define CAN_BTR_LBKM (1 << 30) - -/* 29:26 Reserved, forced by hardware to 0 */ - -/* SJW[1:0]: Resynchronization jump width */ -#define CAN_BTR_SJW_1TQ (0x0 << 24) -#define CAN_BTR_SJW_2TQ (0x1 << 24) -#define CAN_BTR_SJW_3TQ (0x2 << 24) -#define CAN_BTR_SJW_4TQ (0x3 << 24) -#define CAN_BTR_SJW_MASK (0x3 << 24) - -/* 23 Reserved, forced by hardware to 0 */ - -/* TS2[2:0]: Time segment 2 */ -#define CAN_BTR_TS2_1TQ (0x0 << 20) -#define CAN_BTR_TS2_2TQ (0x1 << 20) -#define CAN_BTR_TS2_3TQ (0x2 << 20) -#define CAN_BTR_TS2_4TQ (0x3 << 20) -#define CAN_BTR_TS2_5TQ (0x4 << 20) -#define CAN_BTR_TS2_6TQ (0x5 << 20) -#define CAN_BTR_TS2_7TQ (0x6 << 20) -#define CAN_BTR_TS2_8TQ (0x7 << 20) -#define CAN_BTR_TS2_MASK (0x7 << 20) - -/* TS1[3:0]: Time segment 1 */ -#define CAN_BTR_TS1_1TQ (0x0 << 16) -#define CAN_BTR_TS1_2TQ (0x1 << 16) -#define CAN_BTR_TS1_3TQ (0x2 << 16) -#define CAN_BTR_TS1_4TQ (0x3 << 16) -#define CAN_BTR_TS1_5TQ (0x4 << 16) -#define CAN_BTR_TS1_6TQ (0x5 << 16) -#define CAN_BTR_TS1_7TQ (0x6 << 16) -#define CAN_BTR_TS1_8TQ (0x7 << 16) -#define CAN_BTR_TS1_9TQ (0x8 << 16) -#define CAN_BTR_TS1_10TQ (0x9 << 16) -#define CAN_BTR_TS1_11TQ (0xA << 16) -#define CAN_BTR_TS1_12TQ (0xB << 16) -#define CAN_BTR_TS1_13TQ (0xC << 16) -#define CAN_BTR_TS1_14TQ (0xD << 16) -#define CAN_BTR_TS1_15TQ (0xE << 16) -#define CAN_BTR_TS1_16TQ (0xF << 16) -#define CAN_BTR_TS1_MASK (0xF << 16) - -/* 15:10 Reserved, forced by hardware to 0 */ - -/* BRP[9:0]: Baud rate prescaler */ -#define CAN_BTR_BRP_MASK (0x1FF << 0) - -/* --- CAN_TIxR values ------------------------------------------------------ */ - -/* STID[10:0]: Standard identifier */ -#define CAN_TIxR_STID_MASK (0x3FF << 21) -#define CAN_TIxR_STID_SHIFT 21 - -/* EXID[15:0]: Extended identifier */ -#define CAN_TIxR_EXID_MASK (0x1FFFFFF << 3) -#define CAN_TIxR_EXID_SHIFT 3 - -/* IDE: Identifier extension */ -#define CAN_TIxR_IDE (1 << 2) - -/* RTR: Remote transmission request */ -#define CAN_TIxR_RTR (1 << 1) - -/* TXRQ: Transmit mailbox request */ -#define CAN_TIxR_TXRQ (1 << 0) - -/* --- CAN_TDTxR values ----------------------------------------------------- */ - -/* TIME[15:0]: Message time stamp */ -#define CAN_TDTxR_TIME_MASK (0xFFFF << 15) -#define CAN_TDTxR_TIME_SHIFT 15 - -/* 15:6 Reserved, forced by hardware to 0 */ - -/* TGT: Transmit global time */ -#define CAN_TDTxR_TGT (1 << 5) - -/* 7:4 Reserved, forced by hardware to 0 */ - -/* DLC[3:0]: Data length code */ -#define CAN_TDTxR_DLC_MASK (0xF << 0) -#define CAN_TDTxR_DLC_SHIFT 0 - -/* --- CAN_TDLxR values ----------------------------------------------------- */ - -/* DATA3[7:0]: Data byte 3 */ -/* DATA2[7:0]: Data byte 2 */ -/* DATA1[7:0]: Data byte 1 */ -/* DATA0[7:0]: Data byte 0 */ - -/* --- CAN_TDHxR values ----------------------------------------------------- */ - -/* DATA7[7:0]: Data byte 7 */ -/* DATA6[7:0]: Data byte 6 */ -/* DATA5[7:0]: Data byte 5 */ -/* DATA4[7:0]: Data byte 4 */ - -/* --- CAN_RIxR values ------------------------------------------------------ */ - -/* STID[10:0]: Standard identifier */ -#define CAN_RIxR_STID_MASK (0x3FF << 21) -#define CAN_RIxR_STID_SHIFT 21 - -/* EXID[15:0]: Extended identifier */ -#define CAN_RIxR_EXID_MASK (0x1FFFFFF << 3) -#define CAN_RIxR_EXID_SHIFT 3 - -/* IDE: Identifier extension */ -#define CAN_RIxR_IDE (1 << 2) - -/* RTR: Remote transmission request */ -#define CAN_RIxR_RTR (1 << 1) - -/* 0 Reserved */ - -/* --- CAN_RDTxR values ----------------------------------------------------- */ - -/* TIME[15:0]: Message time stamp */ -#define CAN_RDTxR_TIME_MASK (0xFFFF << 15) -#define CAN_RDTxR_TIME_SHIFT 15 - -/* FMI[7:0]: Filter match index */ -#define CAN_RDTxR_FMI_MASK (0xFF << 8) -#define CAN_RDTxR_FMI_SHIFT 8 - -/* 7:4 Reserved, forced by hardware to 0 */ - -/* DLC[3:0]: Data length code */ -#define CAN_RDTxR_DLC_MASK (0xF << 0) -#define CAN_RDTxR_DLC_SHIFT 0 - -/* --- CAN_RDLxR values ----------------------------------------------------- */ - -/* DATA3[7:0]: Data byte 3 */ -/* DATA2[7:0]: Data byte 2 */ -/* DATA1[7:0]: Data byte 1 */ -/* DATA0[7:0]: Data byte 0 */ - -/* --- CAN_RDHxR values ----------------------------------------------------- */ - -/* DATA7[7:0]: Data byte 7 */ -/* DATA6[7:0]: Data byte 6 */ -/* DATA5[7:0]: Data byte 5 */ -/* DATA4[7:0]: Data byte 4 */ - -/* --- CAN_FMR values ------------------------------------------------------- */ - -/* 31:14 Reserved, forced to reset value */ - -/* - * CAN2SB[5:0]: CAN2 start bank - * (only on connectivity line devices otherwise reserved) - */ -#define CAN_FMR_CAN2SB_MASK (0x3F << 8) -#define CAN_FMR_CAN2SB_SHIFT 15 - -/* 7:1 Reserved, forced to reset value */ - -/* FINIT: Filter init mode */ -#define CAN_FMR_FINIT (1 << 0) - -/* --- CAN_FM1R values ------------------------------------------------------ */ - -/* 31:28 Reserved, forced by hardware to 0 */ - -/* - * FBMx: Filter mode - * x is 0..27 should be calculated by a helper function making so many macros - * seems like an overkill? - */ - -/* --- CAN_FS1R values ------------------------------------------------------ */ - -/* 31:28 Reserved, forced by hardware to 0 */ - -/* - * FSCx: Filter scale configuration - * x is 0..27 should be calculated by a helper function making so many macros - * seems like an overkill? - */ - -/* --- CAN_FFA1R values ----------------------------------------------------- */ - -/* 31:28 Reserved, forced by hardware to 0 */ - -/* - * FFAx: Filter scale configuration - * x is 0..27 should be calculated by a helper function making so many macros - * seems like an overkill? - */ - -/* --- CAN_FA1R values ------------------------------------------------------ */ - -/* 31:28 Reserved, forced by hardware to 0 */ - -/* - * FACTx: Filter active - * x is 0..27 should be calculated by a helper function making so many macros - * seems like an overkill? - */ - -/* --- CAN_FiRx values ------------------------------------------------------ */ - -/* FB[31:0]: Filter bits */ - -/* --- CAN functions -------------------------------------------------------- */ - -void can_reset(u32 canport); -int can_init(u32 canport, bool ttcm, bool abom, bool awum, bool nart, - bool rflm, bool txfp, u32 sjw, u32 ts1, u32 ts2, u32 brp); - -void can_filter_init(u32 canport, u32 nr, bool scale_32bit, bool id_list_mode, - u32 fr1, u32 fr2, u32 fifo, bool enable); -void can_filter_id_mask_16bit_init(u32 canport, u32 nr, u16 id1, u16 mask1, - u16 id2, u16 mask2, u32 fifo, bool enable); -void can_filter_id_mask_32bit_init(u32 canport, u32 nr, u32 id, u32 mask, - u32 fifo, bool enable); -void can_filter_id_list_16bit_init(u32 canport, u32 nr, u16 id1, u16 id2, - u16 id3, u16 id4, u32 fifo, bool enable); -void can_filter_id_list_32bit_init(u32 canport, u32 nr, u32 id1, u32 id2, - u32 fifo, bool enable); - -void can_enable_irq(u32 canport, u32 irq); -void can_disable_irq(u32 canport, u32 irq); - -int can_transmit(u32 canport, u32 id, bool ext, bool rtr, u8 length, u8 *data); -void can_receive(u32 canport, u8 fifo, bool release, u32 *id, bool *ext, - bool *rtr, u32 *fmi, u8 *length, u8 *data); - -void can_fifo_release(u32 canport, u8 fifo); - -#endif diff --git a/include/libopencm3/stm32_common/crc.h b/include/libopencm3/stm32_common/crc.h deleted file mode 100644 index a5bc35a..0000000 --- a/include/libopencm3/stm32_common/crc.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_CRC_H -#define LIBOPENCM3_CRC_H - -#include -#include - -/* --- CRC registers ------------------------------------------------------- */ - -/* Data register (CRC_DR) */ -#define CRC_DR MMIO32(CRC_BASE + 0x00) - -/* Independent data register (CRC_IDR) */ -#define CRC_IDR MMIO32(CRC_BASE + 0x04) - -/* Control register (CRC_CR) */ -#define CRC_CR MMIO32(CRC_BASE + 0x08) - -/* --- CRC_DR values ------------------------------------------------------- */ - -/* Bits[31:0] Data register */ - -/* --- CRC_IDR values ------------------------------------------------------ */ - -/* Bits[7:0] General-purpose 8-bit data register bits */ - -/* --- CRC_CR values ------------------------------------------------------- */ - -/* RESET bit */ -#define CRC_CR_RESET (1 << 0) - -/* --- CRC function prototypes --------------------------------------------- */ - -#endif diff --git a/include/libopencm3/stm32_common/dbgmcu.h b/include/libopencm3/stm32_common/dbgmcu.h deleted file mode 100644 index e6771a2..0000000 --- a/include/libopencm3/stm32_common/dbgmcu.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Gareth McMullin - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_STM32_DBGMCU_H -#define LIBOPENCM3_STM32_DBGMCU_H - -#include -#include - -/* --- DBGMCU registers ---------------------------------------------------- */ - -#define DBGMCU_IDCODE MMIO32(DBGMCU_BASE + 0x00) -#define DBGMCU_CR MMIO32(DBGMCU_BASE + 0x04) - -/* DBGMCU_CR bits */ -#define DBGMCU_CR_SLEEP 0x00000001 -#define DBGMCU_CR_STOP 0x00000002 -#define DBGMCU_CR_STANDBY 0x00000004 -#define DBGMCU_CR_TRACE_IOEN 0x00000020 -#define DBGMCU_CR_TRACE_MODE_MASK 0x000000C0 -#define DBGMCU_CR_TRACE_MODE_ASYNC 0x00000000 -#define DBGMCU_CR_TRACE_MODE_SYNC_1 0x00000040 -#define DBGMCU_CR_TRACE_MODE_SYNC_2 0x00000080 -#define DBGMCU_CR_TRACE_MODE_SYNC_4 0x000000C0 -#define DBGMCU_CR_IWDG_STOP 0x00000100 -#define DBGMCU_CR_WWDG_STOP 0x00000200 -#define DBGMCU_CR_TIM1_STOP 0x00000400 -#define DBGMCU_CR_TIM2_STOP 0x00000800 -#define DBGMCU_CR_TIM3_STOP 0x00001000 -#define DBGMCU_CR_TIM4_STOP 0x00002000 -#define DBGMCU_CR_CAN1_STOP 0x00004000 -#define DBGMCU_CR_I2C1_SMBUS_TIMEOUT 0x00008000 -#define DBGMCU_CR_I2C2_SMBUS_TIMEOUT 0x00010000 -#define DBGMCU_CR_TIM8_STOP 0x00020000 -#define DBGMCU_CR_TIM5_STOP 0x00040000 -#define DBGMCU_CR_TIM6_STOP 0x00080000 -#define DBGMCU_CR_TIM7_STOP 0x00100000 -#define DBGMCU_CR_CAN2_STOP 0x00200000 - -/* DBGMCU_IDCODE bits */ -#define DBGMCU_IDCODE_DEV_ID_MASK 0x00000fff -#define DBGMCU_IDCODE_REV_ID_MASK 0xffff0000 - -#endif diff --git a/include/libopencm3/stm32_common/exti.h b/include/libopencm3/stm32_common/exti.h deleted file mode 100644 index caecee5..0000000 --- a/include/libopencm3/stm32_common/exti.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Mark Butler - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_EXTI_H -#define LIBOPENCM3_EXTI_H - -#include -#include - -/* --- EXTI registers ------------------------------------------------------ */ - -#define EXTI_IMR MMIO32(EXTI_BASE + 0x00) -#define EXTI_EMR MMIO32(EXTI_BASE + 0x04) -#define EXTI_RTSR MMIO32(EXTI_BASE + 0x08) -#define EXTI_FTSR MMIO32(EXTI_BASE + 0x0c) -#define EXTI_SWIER MMIO32(EXTI_BASE + 0x10) -#define EXTI_PR MMIO32(EXTI_BASE + 0x14) - -/* EXTI number definitions */ -#define EXTI0 (1 << 0) -#define EXTI1 (1 << 1) -#define EXTI2 (1 << 2) -#define EXTI3 (1 << 3) -#define EXTI4 (1 << 4) -#define EXTI5 (1 << 5) -#define EXTI6 (1 << 6) -#define EXTI7 (1 << 7) -#define EXTI8 (1 << 8) -#define EXTI9 (1 << 9) -#define EXTI10 (1 << 10) -#define EXTI11 (1 << 11) -#define EXTI12 (1 << 12) -#define EXTI13 (1 << 13) -#define EXTI14 (1 << 14) -#define EXTI15 (1 << 15) -#define EXTI16 (1 << 16) -#define EXTI17 (1 << 17) -#define EXTI18 (1 << 18) -#define EXTI19 (1 << 19) - -/* Trigger types */ -typedef enum trigger_e { - EXTI_TRIGGER_RISING, - EXTI_TRIGGER_FALLING, - EXTI_TRIGGER_BOTH, -} exti_trigger_type; - -void exti_set_trigger(u32 extis, exti_trigger_type trig); -void exti_enable_request(u32 extis); -void exti_disable_request(u32 extis); -void exti_reset_request(u32 extis); -void exti_select_source(u32 exti, u32 gpioport); - -#endif diff --git a/include/libopencm3/stm32_common/fsmc.h b/include/libopencm3/stm32_common/fsmc.h deleted file mode 100644 index 5ccd1d1..0000000 --- a/include/libopencm3/stm32_common/fsmc.h +++ /dev/null @@ -1,284 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_FSMC_H -#define LIBOPENCM3_FSMC_H - -#include -#include - -/* --- Convenience macros -------------------------------------------------- */ - -/* TODO: Move to memorymap.h? */ -#define FSMC_BASE 0xa0000000 - -#define FSMC_BANK1_BASE 0x60000000 /* NOR / PSRAM */ -#define FSMC_BANK2_BASE 0x70000000 /* NAND flash */ -#define FSMC_BANK3_BASE 0x80000000 /* NAND flash */ -#define FSMC_BANK4_BASE 0x90000000 /* PC card */ - -/* --- FSMC registers ------------------------------------------------------ */ - -/* SRAM/NOR-Flash chip-select control registers 1..4 (FSMC_BCRx) */ -#define FSMC_BCR(x) MMIO32(FSMC_BASE + 0x00 + 8 * x) -#define FSMC_BCR1 FSMC_BCR(0) -#define FSMC_BCR2 FSMC_BCR(1) -#define FSMC_BCR3 FSMC_BCR(2) -#define FSMC_BCR4 FSMC_BCR(3) - -/* SRAM/NOR-Flash chip-select timing registers 1..4 (FSMC_BTRx) */ -#define FSMC_BTR(x) MMIO32(FSMC_BASE + 0x04 + 8 * x) -#define FSMC_BTR1 FSMC_BTR(0) -#define FSMC_BTR2 FSMC_BTR(1) -#define FSMC_BTR3 FSMC_BTR(2) -#define FSMC_BTR4 FSMC_BTR(3) - -/* SRAM/NOR-Flash write timing registers 1..4 (FSMC_BWTRx) */ -#define FSMC_BWTR(x) MMIO32(FSMC_BASE + 0x104 + 8 * x) -#define FSMC_BWTR1 FSMC_BWTR(0) -#define FSMC_BWTR2 FSMC_BWTR(1) -#define FSMC_BWTR3 FSMC_BWTR(2) -#define FSMC_BWTR4 FSMC_BWTR(3) - -/* PC Card/NAND Flash control registers 2..4 (FSMC_PCRx) */ -#define FSMC_PCR(x) MMIO32(FSMC_BASE + 0x40 + 0x20 * x) -#define FSMC_PCR2 FSMC_PCR(1) -#define FSMC_PCR3 FSMC_PCR(2) -#define FSMC_PCR4 FSMC_PCR(3) - -/* FIFO status and interrupt registers 2..4 (FSMC_SRx) */ -#define FSMC_SR(x) MMIO32(FSMC_BASE + 0x44 + 0x20 * x) -#define FSMC_SR2 FSMC_SR(1) -#define FSMC_SR3 FSMC_SR(2) -#define FSMC_SR4 FSMC_SR(3) - -/* Common memory space timing registers 2..4 (FSMC_PMEMx) */ -#define FSMC_PMEM(x) MMIO32(FSMC_BASE + 0x48 + 0x20 * x) -#define FSMC_PMEM2 FSMC_PMEM(1) -#define FSMC_PMEM3 FSMC_PMEM(2) -#define FSMC_PMEM4 FSMC_PMEM(3) - -/* Attribute memory space timing registers 2..4 (FSMC_PATTx) */ -#define FSMC_PATT(x) MMIO32(FSMC_BASE + 0x4c + 0x20 * x) -#define FSMC_PATT2 FSMC_PATT(1) -#define FSMC_PATT3 FSMC_PATT(2) -#define FSMC_PATT4 FSMC_PATT(3) - -/* I/O space timing register 4 (FSMC_PIO4) */ -#define FSMC_PIO4 MMIO32(FSMC_BASE + 0xb0) - -/* ECC result registers 2/3 (FSMC_ECCRx) */ -#define FSMC_ECCR(x) MMIO32(FSMC_BASE + 0x54 + 0x20 * x) -#define FSMC_ECCR2 FSMC_ECCR(1) -#define FSMC_ECCR3 FSMC_ECCR(2) - -/* --- FSMC_BCRx values ---------------------------------------------------- */ - -/* CBURSTRW: Write burst enable */ -#define FSMC_BCR_CBURSTRW (1 << 19) - -/* Bits 18..16: Reserved. */ - -/* ASYNCWAIT: Wait signal during asynchronous transfers */ -#define FSMC_BCR_ASYNCWAIT (1 << 15) - -/* EXTMOD: Extended mode enable */ -#define FSMC_BCR_EXTMOD (1 << 14) - -/* WAITEN: Wait enable bit */ -#define FSMC_BCR_WAITEN (1 << 13) - -/* WREN: Write enable bit */ -#define FSMC_BCR_WREN (1 << 12) - -/* WAITCFG: Wait timing configuration */ -#define FSMC_BCR_WAITCFG (1 << 11) - -/* WRAPMOD: Wrapped burst mode support */ -#define FSMC_BCR_WRAPMOD (1 << 10) - -/* WAITPOL: Wait signal polarity bit */ -#define FSMC_BCR_WAITPOL (1 << 9) - -/* BURSTEN: Burst enable bit */ -#define FSMC_BCR_BURSTEN (1 << 8) - -/* Bit 7: Reserved. */ - -/* FACCEN: Flash access enable */ -#define FSMC_BCR_FACCEN (1 << 6) - -/* MWID[5:4]: Memory databus width */ -#define FSMC_BCR_MWID (1 << 4) - -/* MTYP[3:2]: Memory type */ -#define FSMC_BCR_MTYP (1 << 2) - -/* MUXEN: Address/data multiplexing enable bit */ -#define FSMC_BCR_MUXEN (1 << 1) - -/* MBKEN: Memory bank enable bit */ -#define FSMC_BCR_MBKEN (1 << 0) - -/* --- FSMC_BTRx values ---------------------------------------------------- */ - -/* ACCMOD[29:28]: Access mode */ -#define FSMC_BTR_ACCMOD (1 << 28) - -/* DATLAT[27:24]: Data latency (for synchronous burst NOR flash) */ -#define FSMC_BTR_DATLAT (1 << 24) - -/* CLKDIV[23:20]: Clock divide ratio (for CLK signal) */ -#define FSMC_BTR_CLKDIV (1 << 20) - -/* BUSTURN[19:16]: Bus turnaround phase duration */ -#define FSMC_BTR_BUSTURN (1 << 16) - -/* DATAST[15:8]: Data-phase duration */ -#define FSMC_BTR_DATAST (1 << 8) - -/* ADDHLD[7:4]: Address-hold phase duration */ -#define FSMC_BTR_ADDHLD (1 << 4) - -/* ADDSET[3:0]: Address setup phase duration */ -#define FSMC_BTR_ADDSET (1 << 0) - -/* --- FSMC_BWTRx values --------------------------------------------------- */ - -/* ACCMOD[29:28]: Access mode */ -#define FSMC_BWTR_ACCMOD (1 << 28) - -/* DATLAT[27:24]: Data latency (for synchronous burst NOR Flash) */ -#define FSMC_BWTR_DATLAT (1 << 24) - -/* CLKDIV[23:20]: Clock divide ratio (for CLK signal) */ -#define FSMC_BWTR_CLKDIV (1 << 20) - -/* Bits 19..16: Reserved. */ - -/* DATAST[15:8]: Data-phase duration */ -#define FSMC_BWTR_DATAST (1 << 8) - -/* ADDHLD[7:4]: Address-hold phase duration */ -#define FSMC_BWTR_ADDHLD (1 << 4) - -/* ADDSET[3:0]: Address setup phase duration */ -#define FSMC_BWTR_ADDSET (1 << 0) - -/* --- FSMC_PCRx values ---------------------------------------------------- */ - -/* ECCPS[19:17]: ECC page size */ -#define FSMC_PCR_ECCPS (1 << 17) - -/* TAR[16:13]: ALE to RE delay */ -#define FSMC_PCR_TAR (1 << 13) - -/* TCLR[12:9]: CLE to RE delay */ -#define FSMC_PCR_TCLR (1 << 9) - -/* Bits 8..7: Reserved. */ - -/* ECCEN: ECC computation logic enable bit */ -#define FSMC_PCR_ECCEN (1 << 6) - -/* PWID[5:4]: Databus width */ -#define FSMC_PCR_PWID (1 << 4) - -/* PTYP: Memory type */ -#define FSMC_PCR_PTYP (1 << 3) - -/* PBKEN: PC Card/NAND Flash memory bank enable bit */ -#define FSMC_PCR_PBKEN (1 << 2) - -/* PWAITEN: Wait feature enable bit */ -#define FSMC_PCR_PWAITEN (1 << 1) - -/* Bit 0: Reserved. */ - -/* --- FSMC_SRx values ----------------------------------------------------- */ - -/* FEMPT: FIFO empty */ -#define FSMC_SR_FEMPT (1 << 6) - -/* IFEN: Interrupt falling edge detection enable bit */ -#define FSMC_SR_IFEN (1 << 5) - -/* ILEN: Interrupt high-level detection enable bit */ -#define FSMC_SR_ILEN (1 << 4) - -/* IREN: Interrupt rising edge detection enable bit */ -#define FSMC_SR_IREN (1 << 3) - -/* IFS: Interrupt falling edge status */ -#define FSMC_SR_IFS (1 << 2) - -/* ILS: Interrupt high-level status */ -#define FSMC_SR_ILS (1 << 1) - -/* IRS: Interrupt rising edge status */ -#define FSMC_SR_IRS (1 << 0) - -/* --- FSMC_PMEMx values --------------------------------------------------- */ - -/* MEMHIZx[31:24]: Common memory x databus HiZ time */ -#define FSMC_PMEM_MEMHIZX (1 << 24) - -/* MEMHOLDx[23:16]: Common memory x hold time */ -#define FSMC_PMEM_MEMHOLDX (1 << 16) - -/* MEMWAITx[15:8]: Common memory x wait time */ -#define FSMC_PMEM_MEMHOLDX (1 << 8) - -/* MEMSETx[7:0]: Common memory x setup time */ -#define FSMC_PMEM_MEMSETX (1 << 0) - -/* --- FSMC_PATTx values --------------------------------------------------- */ - -/* ATTHIZx[31:24]: Attribute memory x databus HiZ time */ -#define FSMC_PATT_ATTHIZX (1 << 24) - -/* ATTHOLDx[23:16]: Attribute memory x hold time */ -#define FSMC_PATT_ATTHOLDX (1 << 16) - -/* ATTWAITx[15:8]: Attribute memory x wait time */ -#define FSMC_PATT_ATTWAITX (1 << 8) - -/* ATTSETx[7:0]: Attribute memory x setup time */ -#define FSMC_PATT_ATTSETX (1 << 0) - -/* --- FSMC_PIO4 values ---------------------------------------------------- */ - -/* IOHIZx[31:24]: I/O x databus HiZ time */ -#define FSMC_PIO4_IOHIZX (1 << 24) - -/* IOHOLDx[23:16]: I/O x hold time */ -#define FSMC_PIO4_IOHOLDX (1 << 16) - -/* IOWAITx[15:8]: I/O x wait time */ -#define FSMC_PIO4_IOWAITX (1 << 8) - -/* IOSETx[7:0]: I/O x setup time */ -#define FSMC_PIO4_IOSETX (1 << 0) - -/* --- FSMC_ECCRx values --------------------------------------------------- */ - -/* ECCx[31:0]: ECC result */ -#define FSMC_ECCR_ECCX (1 << 0) - -#endif diff --git a/include/libopencm3/stm32_common/i2c.h b/include/libopencm3/stm32_common/i2c.h deleted file mode 100644 index 1fa4f37..0000000 --- a/include/libopencm3/stm32_common/i2c.h +++ /dev/null @@ -1,333 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_I2C_H -#define LIBOPENCM3_I2C_H - -#include -#include - -/* --- Convenience macros -------------------------------------------------- */ - -/* I2C register base adresses (for convenience) */ -#define I2C1 I2C1_BASE -#define I2C2 I2C2_BASE - -/* --- I2C registers ------------------------------------------------------- */ - -/* Control register 1 (I2Cx_CR1) */ -#define I2C_CR1(i2c_base) MMIO32(i2c_base + 0x00) -#define I2C1_CR1 I2C_CR1(I2C1) -#define I2C2_CR1 I2C_CR1(I2C2) - -/* Control register 2 (I2Cx_CR2) */ -#define I2C_CR2(i2c_base) MMIO32(i2c_base + 0x04) -#define I2C1_CR2 I2C_CR2(I2C1) -#define I2C2_CR2 I2C_CR2(I2C2) - -/* Own address register 1 (I2Cx_OAR1) */ -#define I2C_OAR1(i2c_base) MMIO32(i2c_base + 0x08) -#define I2C1_OAR1 I2C_OAR1(I2C1) -#define I2C2_OAR1 I2C_OAR1(I2C2) - -/* Own address register 2 (I2Cx_OAR2) */ -#define I2C_OAR2(i2c_base) MMIO32(i2c_base + 0x0c) -#define I2C1_OAR2 I2C_OAR2(I2C1) -#define I2C2_OAR2 I2C_OAR2(I2C2) - -/* Data register (I2Cx_DR) */ -#define I2C_DR(i2c_base) MMIO32(i2c_base + 0x10) -#define I2C1_DR I2C_DR(I2C1) -#define I2C2_DR I2C_DR(I2C2) - -/* Status register 1 (I2Cx_SR1) */ -#define I2C_SR1(i2c_base) MMIO32(i2c_base + 0x14) -#define I2C1_SR1 I2C_SR1(I2C1) -#define I2C2_SR1 I2C_SR1(I2C2) - -/* Status register 2 (I2Cx_SR2) */ -#define I2C_SR2(i2c_base) MMIO32(i2c_base + 0x18) -#define I2C1_SR2 I2C_SR2(I2C1) -#define I2C2_SR2 I2C_SR2(I2C2) - -/* Clock control register (I2Cx_CCR) */ -#define I2C_CCR(i2c_base) MMIO32(i2c_base + 0x1c) -#define I2C1_CCR I2C_CCR(I2C1) -#define I2C2_CCR I2C_CCR(I2C2) - -/* TRISE register (I2Cx_CCR) */ -#define I2C_TRISE(i2c_base) MMIO32(i2c_base + 0x20) -#define I2C1_TRISE I2C_TRISE(I2C1) -#define I2C2_TRISE I2C_TRISE(I2C2) - -/* --- I2Cx_CR1 values ----------------------------------------------------- */ - -/* SWRST: Software reset */ -#define I2C_CR1_SWRST (1 << 15) - -/* Note: Bit 14 is reserved, and forced to 0 by hardware. */ - -/* ALERT: SMBus alert */ -#define I2C_CR1_ALERT (1 << 13) - -/* PEC: Packet error checking */ -#define I2C_CR1_PEC (1 << 12) - -/* POS: Acknowledge / PEC postition */ -#define I2C_CR1_POS (1 << 11) - -/* ACK: Acknowledge enable */ -#define I2C_CR1_ACK (1 << 10) - -/* STOP: STOP generation */ -#define I2C_CR1_STOP (1 << 9) - -/* START: START generation */ -#define I2C_CR1_START (1 << 8) - -/* NOSTRETCH: Clock stretching disable (slave mode) */ -#define I2C_CR1_NOSTRETCH (1 << 7) - -/* ENGC: General call enable */ -#define I2C_CR1_ENGC (1 << 6) - -/* ENPEC: Enable PEC */ -#define I2C_CR1_ENPEC (1 << 5) - -/* ENARP: ARP enable */ -#define I2C_CR1_ENARP (1 << 4) - -/* SMBTYPE: SMBus type */ -#define I2C_CR1_SMBTYPE (1 << 3) - -/* Note: Bit 2 is reserved, and forced to 0 by hardware. */ - -/* SMBUS: SMBus mode */ -#define I2C_CR1_SMBUS (1 << 1) - -/* PE: Peripheral enable */ -#define I2C_CR1_PE (1 << 0) - -/* --- I2Cx_CR2 values ----------------------------------------------------- */ - -/* Note: Bits [15:13] are reserved, and forced to 0 by hardware. */ - -/* LAST: DMA last transfer */ -#define I2C_CR2_LAST (1 << 12) - -/* DMAEN: DMA requests enable */ -#define I2C_CR2_DMAEN (1 << 11) - -/* ITBUFEN: Buffer interrupt enable */ -#define I2C_CR2_ITBUFEN (1 << 10) - -/* ITEVTEN: Event interrupt enable */ -#define I2C_CR2_ITEVTEN (1 << 9) - -/* ITERREN: Error interrupt enable */ -#define I2C_CR2_ITERREN (1 << 8) - -/* Note: Bits [7:6] are reserved, and forced to 0 by hardware. */ - -/* FREQ[5:0]: Peripheral clock frequency (valid values: 2-36 MHz) */ -#define I2C_CR2_FREQ_2MHZ 0x02 -#define I2C_CR2_FREQ_3MHZ 0x03 -#define I2C_CR2_FREQ_4MHZ 0x04 -#define I2C_CR2_FREQ_5MHZ 0x05 -#define I2C_CR2_FREQ_6MHZ 0x06 -#define I2C_CR2_FREQ_7MHZ 0x07 -#define I2C_CR2_FREQ_8MHZ 0x08 -#define I2C_CR2_FREQ_9MHZ 0x09 -#define I2C_CR2_FREQ_10MHZ 0x0a -#define I2C_CR2_FREQ_11MHZ 0x0b -#define I2C_CR2_FREQ_12MHZ 0x0c -#define I2C_CR2_FREQ_13MHZ 0x0d -#define I2C_CR2_FREQ_14MHZ 0x0e -#define I2C_CR2_FREQ_15MHZ 0x0f -#define I2C_CR2_FREQ_16MHZ 0x10 -#define I2C_CR2_FREQ_17MHZ 0x11 -#define I2C_CR2_FREQ_18MHZ 0x12 -#define I2C_CR2_FREQ_19MHZ 0x13 -#define I2C_CR2_FREQ_20MHZ 0x14 -#define I2C_CR2_FREQ_21MHZ 0x15 -#define I2C_CR2_FREQ_22MHZ 0x16 -#define I2C_CR2_FREQ_23MHZ 0x17 -#define I2C_CR2_FREQ_24MHZ 0x18 -#define I2C_CR2_FREQ_25MHZ 0x19 -#define I2C_CR2_FREQ_26MHZ 0x1a -#define I2C_CR2_FREQ_27MHZ 0x1b -#define I2C_CR2_FREQ_28MHZ 0x1c -#define I2C_CR2_FREQ_29MHZ 0x1d -#define I2C_CR2_FREQ_30MHZ 0x1e -#define I2C_CR2_FREQ_31MHZ 0x1f -#define I2C_CR2_FREQ_32MHZ 0x20 -#define I2C_CR2_FREQ_33MHZ 0x21 -#define I2C_CR2_FREQ_34MHZ 0x22 -#define I2C_CR2_FREQ_35MHZ 0x23 -#define I2C_CR2_FREQ_36MHZ 0x24 - -/* --- I2Cx_OAR1 values ---------------------------------------------------- */ - -/* ADDMODE: Addressing mode (slave mode) */ -#define I2C_OAR1_ADDMODE (1 << 15) -#define I2C_OAR1_ADDMODE_7BIT 0 -#define I2C_OAR1_ADDMODE_10BIT 1 - -/* Note: Bit 14 should always be kept at 1 by software! */ - -/* Note: Bits [13:10] are reserved, and forced to 0 by hardware. */ - -/* ADD: Address bits: [7:1] in 7-bit mode, bits [9:0] in 10-bit mode */ - -/* --- I2Cx_OAR2 values ---------------------------------------------------- */ - -/* Note: Bits [15:8] are reserved, and forced to 0 by hardware. */ - -/* ADD2[7:1]: Interface address (bits [7:1] in dual addressing mode) */ - -/* ENDUAL: Dual addressing mode enable */ -#define I2C_OAR2_ENDUAL (1 << 0) - -/* --- I2Cx_DR values ------------------------------------------------------ */ - -/* Note: Bits [15:8] are reserved, and forced to 0 by hardware. */ - -/* DR[7:0] 8-bit data register */ - -/* --- I2Cx_SR1 values ----------------------------------------------------- */ - -/* SMBALERT: SMBus alert */ -#define I2C_SR1_SMBALERT (1 << 15) - -/* TIMEOUT: Timeout or Tlow Error */ -#define I2C_SR1_TIMEOUT (1 << 14) - -/* Note: Bit 13 is reserved, and forced to 0 by hardware. */ - -/* PECERR: PEC Error in reception */ -#define I2C_SR1_PECERR (1 << 12) - -/* OVR: Overrun/Underrun */ -#define I2C_SR1_OVR (1 << 11) - -/* AF: Acknowledge failure */ -#define I2C_SR1_AF (1 << 10) - -/* ARLO: Arbitration lost (master mode) */ -#define I2C_SR1_ARLO (1 << 9) - -/* BERR: Bus error */ -#define I2C_SR1_BERR (1 << 8) - -/* TxE: Data register empty (transmitters) */ -#define I2C_SR1_TxE (1 << 7) - -/* RxNE: Data register not empty (receivers) */ -#define I2C_SR1_RxNE (1 << 6) - -/* Note: Bit 5 is reserved, and forced to 0 by hardware. */ - -/* STOPF: STOP detection (slave mode) */ -#define I2C_SR1_STOPF (1 << 4) - -/* ADD10: 10-bit header sent (master mode) */ -#define I2C_SR1_ADD10 (1 << 3) - -/* BTF: Byte transfer finished */ -#define I2C_SR1_BTF (1 << 2) - -/* ADDR: Address sent (master mode) / address matched (slave mode) */ -#define I2C_SR1_ADDR (1 << 1) - -/* SB: Start bit (master mode) */ -#define I2C_SR1_SB (1 << 0) - -/* --- I2Cx_SR2 values ----------------------------------------------------- */ - -/* Bits [15:8]: PEC[7:0]: Packet error checking register */ - -/* DUALF: Dual flag (slave mode) */ -#define I2C_SR2_DUALF (1 << 7) - -/* SMBHOST: SMBus host header (slave mode) */ -#define I2C_SR2_SMBHOST (1 << 6) - -/* SMBDEFAULT: SMBus device default address (slave mode) */ -#define I2C_SR2_SMBDEFAULT (1 << 5) - -/* GENCALL: General call address (slave mode) */ -#define I2C_SR2_GENCALL (1 << 4) - -/* Note: Bit 3 is reserved, and forced to 0 by hardware. */ - -/* TRA: Transmitter / receiver */ -#define I2C_SR2_TRA (1 << 2) - -/* BUSY: Bus busy */ -#define I2C_SR2_BUSY (1 << 1) - -/* MSL: Master / slave */ -#define I2C_SR2_MSL (1 << 0) - -/* --- I2Cx_CCR values ----------------------------------------------------- */ - -/* F/S: I2C Master mode selection (fast / standard) */ -#define I2C_CCR_FS (1 << 15) - -/* DUTY: Fast Mode Duty Cycle */ -#define I2C_CCR_DUTY (1 << 14) - -/* Note: Bits [13:12] are reserved, and forced to 0 by hardware. */ - -/* - * Bits [11:0]: - * CCR[11:0]: Clock control register in Fast/Standard mode (master mode) - */ - -/* --- I2Cx_TRISE values --------------------------------------------------- */ - -/* Note: Bits [15:6] are reserved, and forced to 0 by hardware. */ - -/* - * Bits [5:0]: - * TRISE[5:0]: Maximum rise time in Fast/Standard mode (master mode) - */ - -/* --- I2C const definitions ----------------------------------------------- */ - -#define I2C_WRITE 0 -#define I2C_READ 1 - -/* --- I2C funtion prototypes----------------------------------------------- */ - -void i2c_peripheral_enable(u32 i2c); -void i2c_peripheral_disable(u32 i2c); -void i2c_send_start(u32 i2c); -void i2c_send_stop(u32 i2c); -void i2c_set_own_7bit_slave_address(u32 i2c, u8 slave); -void i2c_set_own_10bit_slave_address(u32 i2c, u16 slave); -void i2c_set_fast_mode(u32 i2c); -void i2c_set_standard_mode(u32 i2c); -void i2c_set_clock_frequency(u32 i2c, u8 freq); -void i2c_set_ccr(u32 i2c, u16 freq); -void i2c_set_trise(u32 i2c, u16 trise); -void i2c_send_7bit_address(u32 i2c, u8 slave, u8 readwrite); -void i2c_send_data(u32 i2c, u8 data); - -#endif diff --git a/include/libopencm3/stm32_common/iwdg.h b/include/libopencm3/stm32_common/iwdg.h deleted file mode 100644 index 67f2961..0000000 --- a/include/libopencm3/stm32_common/iwdg.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_IWDG_H -#define LIBOPENCM3_IWDG_H - -#include -#include - -/* --- IWDG registers ------------------------------------------------------ */ - -/* Key Register (IWDG_KR) */ -#define IWDG_KR MMIO32(IWDG_BASE + 0x00) - -/* Prescaler register (IWDG_PR) */ -#define IWDG_PR MMIO32(IWDG_BASE + 0x04) - -/* Reload register (IWDG_RLR) */ -#define IWDG_RLR MMIO32(IWDG_BASE + 0x08) - -/* Status register (IWDG_SR) */ -#define IWDG_SR MMIO32(IWDG_BASE + 0x0C) - -/* --- IWDG_KR values ------------------------------------------------------ */ - -/* KEY[15:0]: Key value */ -#define IWDG_KR_RESET 0xAAAA -#define IWDG_KR_UNLOCK 0x5555 -#define IWDG_KR_START 0xCCCC - -/* --- IWDG_PR values ------------------------------------------------------ */ - -/* PR[2:0]: Prescaler divider */ -#define IWDG_PR_LSB 0 -#define IWDG_PR_DIV4 0x0 -#define IWDG_PR_DIV8 0x1 -#define IWDG_PR_DIV16 0x2 -#define IWDG_PR_DIV32 0x3 -#define IWDG_PR_DIV64 0x4 -#define IWDG_PR_DIV128 0x5 -#define IWDG_PR_DIV256 0x6 -/* Double definition: 0x06 and 0x07 both mean DIV256 as per datasheet. */ -/* #define IWDG_PR_DIV256 0x7 */ - -/* --- IWDG_RLR values ----------------------------------------------------- */ - -/* RL[11:0]: Watchdog counter reload value */ - -/* --- IWDG_SR values ------------------------------------------------------ */ - -/* RVU: Watchdog counter reload value update */ -#define IWDG_SR_RVU (1 << 1) - -/* PVU: Watchdog prescaler value update */ -#define IWDG_SR_PVU (1 << 0) - -/* --- IWDG funtion prototypes---------------------------------------------- */ - -#endif diff --git a/include/libopencm3/stm32_common/memorymap.h b/include/libopencm3/stm32_common/memorymap.h deleted file mode 100644 index 0d0c60f..0000000 --- a/include/libopencm3/stm32_common/memorymap.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Fergus Noble - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_MEMORYMAP_COMMON_H -#define LIBOPENCM3_MEMORYMAP_COMMON_H - -#include - -#ifdef STM32F1 -#include -#else -#ifdef STM32F1 -#include -#else -#error "stm32 family not defined." -#endif -#endif - -#endif diff --git a/include/libopencm3/stm32_common/pwr.h b/include/libopencm3/stm32_common/pwr.h deleted file mode 100644 index 4af8480..0000000 --- a/include/libopencm3/stm32_common/pwr.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_PWR_H -#define LIBOPENCM3_PWR_H - -#include -#include - -/* --- PWR registers ------------------------------------------------------- */ - -/* Power control register (PWR_CR) */ -#define PWR_CR MMIO32(POWER_CONTROL_BASE + 0x00) - -/* Power control/status register (PWR_CSR) */ -#define PWR_CSR MMIO32(POWER_CONTROL_BASE + 0x04) - -/* --- PWR_CR values ------------------------------------------------------- */ - -/* DBP: Disable backup domain write protection */ -#define PWR_CR_DBP (1 << 8) - -/* PLS[7:5]: PVD level selection */ -#define PWR_CR_PLS_LSB 5 -#define PWR_CR_PLS_2V2 0x0 -#define PWR_CR_PLS_2V3 0x1 -#define PWR_CR_PLS_2V4 0x2 -#define PWR_CR_PLS_2V5 0x3 -#define PWR_CR_PLS_2V6 0x4 -#define PWR_CR_PLS_2V7 0x5 -#define PWR_CR_PLS_2V8 0x6 -#define PWR_CR_PLS_2V9 0x7 - -/* PVDE: Power voltage detector enable */ -#define PWR_CR_PVDE (1 << 4) - -/* CSBF: Clear standby flag */ -#define PWR_CR_CSBF (1 << 3) - -/* CWUF: Clear wakeup flag */ -#define PWR_CR_CWUF (1 << 2) - -/* PDDS: Power down deepsleep */ -#define PWR_CR_PDDS (1 << 1) - -/* LPDS: Low-power deepsleep */ -#define PWR_CR_LPDS (1 << 0) - -/* --- PWR_CSR values ------------------------------------------------------ */ - -/* EWUP: Enable WKUP pin */ -#define PWR_CSR_EWUP (1 << 8) - -/* PVDO: PVD output */ -#define PWR_CSR_PVDO (1 << 2) - -/* SBF: Standby flag */ -#define PWR_CSR_SBF (1 << 1) - -/* WUF: Wakeup flag */ -#define PWR_CSR_WUF (1 << 0) - -/* --- PWR function prototypes ------------------------------------------- */ - -#endif diff --git a/include/libopencm3/stm32_common/spi.h b/include/libopencm3/stm32_common/spi.h deleted file mode 100644 index 3249457..0000000 --- a/include/libopencm3/stm32_common/spi.h +++ /dev/null @@ -1,331 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_SPI_H -#define LIBOPENCM3_SPI_H - -#include -#include - -/* Registers can be accessed as 16bit or 32bit values. */ - -/* --- Convenience macros -------------------------------------------------- */ - -#define SPI1 SPI1_BASE -#define SPI2 SPI2_I2S_BASE -#define SPI3 SPI3_I2S_BASE - -/* --- SPI registers ------------------------------------------------------- */ - -/* Control register 1 (SPIx_CR1) */ -#define SPI_CR1(spi_base) MMIO32(spi_base + 0x00) -#define SPI1_CR1 SPI_CR1(SPI1_BASE) -#define SPI2_CR1 SPI_CR1(SPI2_I2S_BASE) -#define SPI3_CR1 SPI_CR1(SPI3_I2S_BASE) - -/* Control register 2 (SPIx_CR2) */ -#define SPI_CR2(spi_base) MMIO32(spi_base + 0x04) -#define SPI1_CR2 SPI_CR2(SPI1_BASE) -#define SPI2_CR2 SPI_CR2(SPI2_I2S_BASE) -#define SPI3_CR2 SPI_CR2(SPI3_I2S_BASE) - -/* Status register (SPIx_SR) */ -#define SPI_SR(spi_base) MMIO32(spi_base + 0x08) -#define SPI1_SR SPI_SR(SPI1_BASE) -#define SPI2_SR SPI_SR(SPI2_I2S_BASE) -#define SPI3_SR SPI_SR(SPI3_I2S_BASE) - -/* Data register (SPIx_DR) */ -#define SPI_DR(spi_base) MMIO32(spi_base + 0x0c) -#define SPI1_DR SPI_DR(SPI1_BASE) -#define SPI2_DR SPI_DR(SPI2_I2S_BASE) -#define SPI3_DR SPI_DR(SPI3_I2S_BASE) - -/* CRC polynomial register (SPIx_CRCPR) */ -/* Note: Not used in I2S mode. */ -#define SPI_CRCPR(spi_base) MMIO32(spi_base + 0x10) -#define SPI1_CRCPR SPI_CRCPR(SPI1_BASE) -#define SPI2_CRCPR SPI_CRCPR(SPI2_I2S_BASE) -#define SPI3_CRCPR SPI_CRCPR(SPI3_I2S_BASE) - -/* RX CRC register (SPIx_RXCRCR) */ -/* Note: Not used in I2S mode. */ -#define SPI_RXCRCR(spi_base) MMIO32(spi_base + 0x14) -#define SPI1_RXCRCR SPI_RXCRCR(SPI1_BASE) -#define SPI2_RXCRCR SPI_RXCRCR(SPI2_I2S_BASE) -#define SPI3_RXCRCR SPI_RXCRCR(SPI3_I2S_BASE) - -/* TX CRC register (SPIx_RXCRCR) */ -/* Note: Not used in I2S mode. */ -#define SPI_TXCRCR(spi_base) MMIO32(spi_base + 0x18) -#define SPI1_TXCRCR SPI_TXCRCR(SPI1_BASE) -#define SPI2_TXCRCR SPI_TXCRCR(SPI2_I2S_BASE) -#define SPI3_TXCRCR SPI_TXCRCR(SPI3_I2S_BASE) - -/* I2S configuration register (SPIx_I2SCFGR) */ -#define SPI_I2SCFGR(spi_base) MMIO32(spi_base + 0x1c) -#define SPI1_I2SCFGR SPI_I2SCFGR(SPI1_BASE) -#define SPI2_I2SCFGR SPI_I2SCFGR(SPI2_I2S_BASE) -#define SPI3_I2SCFGR SPI_I2SCFGR(SPI3_I2S_BASE) - -/* I2S prescaler register (SPIx_I2SPR) */ -#define SPI_I2SPR(spi_base) MMIO32(spi_base + 0x20) -#define SPI1_I2SPR SPI_I2SPR(SPI1_BASE) -#define SPI2_I2SPR SPI_I2SPR(SPI2_I2S_BASE) -#define SPI3_I2SPR SPI_I2SPR(SPI3_I2S_BASE) - -/* --- SPI_CR1 values ------------------------------------------------------ */ - -/* Note: None of the CR1 bits are used in I2S mode. */ - -/* BIDIMODE: Bidirectional data mode enable */ -#define SPI_CR1_BIDIMODE_2LINE_UNIDIR (0 << 15) -#define SPI_CR1_BIDIMODE_1LINE_BIDIR (1 << 15) -#define SPI_CR1_BIDIMODE (1 << 15) - -/* BIDIOE: Output enable in bidirectional mode */ -#define SPI_CR1_BIDIOE (1 << 14) - -/* CRCEN: Hardware CRC calculation enable */ -#define SPI_CR1_CRCEN (1 << 13) - -/* CRCNEXT: Transmit CRC next */ -#define SPI_CR1_CRCNEXT (1 << 12) - -/* DFF: Data frame format */ -#define SPI_CR1_DFF_8BIT (0 << 11) -#define SPI_CR1_DFF_16BIT (1 << 11) -#define SPI_CR1_DFF (1 << 11) - -/* RXONLY: Receive only */ -#define SPI_CR1_RXONLY (1 << 10) - -/* SSM: Software slave management */ -#define SPI_CR1_SSM (1 << 9) - -/* SSI: Internal slave select */ -#define SPI_CR1_SSI (1 << 8) - -/* LSBFIRST: Frame format */ -#define SPI_CR1_MSBFIRST (0 << 7) -#define SPI_CR1_LSBFIRST (1 << 7) - -/* SPE: SPI enable */ -#define SPI_CR1_SPE (1 << 6) - -/* BR[2:0]: Baud rate control */ -#define SPI_CR1_BAUDRATE_FPCLK_DIV_2 (0x00 << 3) -#define SPI_CR1_BAUDRATE_FPCLK_DIV_4 (0x01 << 3) -#define SPI_CR1_BAUDRATE_FPCLK_DIV_8 (0x02 << 3) -#define SPI_CR1_BAUDRATE_FPCLK_DIV_16 (0x03 << 3) -#define SPI_CR1_BAUDRATE_FPCLK_DIV_32 (0x04 << 3) -#define SPI_CR1_BAUDRATE_FPCLK_DIV_64 (0x05 << 3) -#define SPI_CR1_BAUDRATE_FPCLK_DIV_128 (0x06 << 3) -#define SPI_CR1_BAUDRATE_FPCLK_DIV_256 (0x07 << 3) -#define SPI_CR1_BR_FPCLK_DIV_2 0x0 -#define SPI_CR1_BR_FPCLK_DIV_4 0x1 -#define SPI_CR1_BR_FPCLK_DIV_8 0x2 -#define SPI_CR1_BR_FPCLK_DIV_16 0x3 -#define SPI_CR1_BR_FPCLK_DIV_32 0x4 -#define SPI_CR1_BR_FPCLK_DIV_64 0x5 -#define SPI_CR1_BR_FPCLK_DIV_128 0x6 -#define SPI_CR1_BR_FPCLK_DIV_256 0x7 - -/* MSTR: Master selection */ -#define SPI_CR1_MSTR (1 << 2) - -/* CPOL: Clock polarity */ -#define SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE (0 << 1) -#define SPI_CR1_CPOL_CLK_TO_1_WHEN_IDLE (1 << 1) -#define SPI_CR1_CPOL (1 << 1) - -/* CPHA: Clock phase */ -#define SPI_CR1_CPHA_CLK_TRANSITION_1 (0 << 0) -#define SPI_CR1_CPHA_CLK_TRANSITION_2 (1 << 0) -#define SPI_CR1_CPHA (1 << 0) - -/* --- SPI_CR2 values ------------------------------------------------------ */ - -/* Bits [15:8]: Reserved. Forced to 0 by hardware. */ - -/* TXEIE: Tx buffer empty interrupt enable */ -#define SPI_CR2_TXEIE (1 << 7) - -/* RXNEIE: RX buffer not empty interrupt enable */ -#define SPI_CR2_RXNEIE (1 << 6) - -/* ERRIE: Error interrupt enable */ -#define SPI_CR2_ERRIE (1 << 5) - -/* Bits [4:3]: Reserved. Forced to 0 by hardware. */ - -/* SSOE: SS output enable */ -#define SPI_CR2_SSOE (1 << 2) - -/* TXDMAEN: Tx buffer DMA enable */ -#define SPI_CR2_TXDMAEN (1 << 1) - -/* RXDMAEN: Rx buffer DMA enable */ -#define SPI_CR2_RXDMAEN (1 << 0) - -/* --- SPI_SR values ------------------------------------------------------- */ - -/* Bits [15:8]: Reserved. Forced to 0 by hardware. */ - -/* BSY: Busy flag */ -#define SPI_SR_BSY (1 << 7) - -/* OVR: Overrun flag */ -#define SPI_SR_OVR (1 << 6) - -/* MODF: Mode fault */ -#define SPI_SR_MODF (1 << 5) - -/* CRCERR: CRC error flag */ -#define SPI_SR_CRCERR (1 << 4) - -/* UDR: Underrun flag */ -#define SPI_SR_UDR (1 << 3) - -/* CHSIDE: Channel side */ -#define SPI_SR_CHSIDE (1 << 2) - -/* TXE: Transmit buffer empty */ -#define SPI_SR_TXE (1 << 1) - -/* RXNE: Receive buffer not empty */ -#define SPI_SR_RXNE (1 << 0) - -/* --- SPI_DR values ------------------------------------------------------- */ - -/* SPI_DR[15:0]: Data Register. */ - -/* --- SPI_CRCPR values ---------------------------------------------------- */ - -/* SPI_CRCPR [15:0]: CRC Polynomial Register. */ - -/* --- SPI_RXCRCR values --------------------------------------------------- */ - -/* SPI_RXCRCR [15:0]: RX CRC Register. */ - -/* --- SPI_TXCRCR values --------------------------------------------------- */ - -/* SPI_TXCRCR [15:0]: TX CRC Register. */ - -/* --- SPI_I2SCFGR values -------------------------------------------------- */ - -/* Bits [15:12]: Reserved. Forced to 0 by hardware. */ - -/* I2SMOD: I2S mode selection */ -#define SPI_I2SCFGR_I2SMOD (1 << 11) - -/* I2SE: I2S Enable */ -#define SPI_I2SCFGR_I2SE (1 << 10) - -/* I2SCFG[9:8]: I2S configuration mode */ -#define SPI_I2SCFGR_I2SCFG_LSB 8 -#define SPI_I2SCFGR_I2SCFG_SLAVE_TRANSMIT 0x0 -#define SPI_I2SCFGR_I2SCFG_SLAVE_RECEIVE 0x1 -#define SPI_I2SCFGR_I2SCFG_MASTER_TRANSMIT 0x2 -#define SPI_I2SCFGR_I2SCFG_MASTER_RECEIVE 0x3 - -/* PCMSYNC: PCM frame synchronization */ -#define SPI_I2SCFGR_PCMSYNC (1 << 7) - -/* Bit 6: Reserved. Forced to 0 by hardware. */ - -/* I2SSTD[5:4]: I2S standard selection */ -#define SPI_I2SCFGR_I2SSTD_LSB 4 -#define SPI_I2SCFGR_I2SSTD_I2S_PHILLIPS 0x0 -#define SPI_I2SCFGR_I2SSTD_MSB_JUSTIFIED 0x1 -#define SPI_I2SCFGR_I2SSTD_LSB_JUSTIFIED 0x2 -#define SPI_I2SCFGR_I2SSTD_PCM 0x3 - -/* CKPOL: Steady state clock polarity */ -#define SPI_I2SCFGR_CKPOL (1 << 3) - -/* DATLEN[2:1]: Data length to be transferred */ -#define SPI_I2SCFGR_DATLEN_LSB 1 -#define SPI_I2SCFGR_DATLEN_16BIT 0x0 -#define SPI_I2SCFGR_DATLEN_24BIT 0x1 -#define SPI_I2SCFGR_DATLEN_32BIT 0x2 - -/* CHLEN: Channel length */ -#define SPI_I2SCFGR_CHLEN (1 << 0) - -/* --- SPI_I2SPR values ---------------------------------------------------- */ - -/* Bits [15:10]: Reserved. Forced to 0 by hardware. */ - -/* MCKOE: Master clock output enable */ -#define SPI_I2SPR_MCKOE (1 << 9) - -/* ODD: Odd factor for the prescaler */ -#define SPI_I2SPR_ODD (1 << 8) - -/* I2SDIV[7:0]: I2S Linear prescaler */ -/* 0 and 1 are forbidden values */ - -/* --- Function prototypes ------------------------------------------------- */ - -int spi_init_master(u32 spi, u32 br, u32 cpol, u32 cpha, u32 dff, u32 lsbfirst); -void spi_enable(u32 spi); -void spi_disable(u32 spi); -void spi_write(u32 spi, u16 data); -void spi_send(u32 spi, u16 data); -u16 spi_read(u32 spi); -void spi_set_bidirectional_mode(u32 spi); -void spi_set_unidirectional_mode(u32 spi); -void spi_set_bidirectional_receive_only_mode(u32 spi); -void spi_set_bidirectional_transmit_only_mode(u32 spi); -void spi_enable_crc(u32 spi); -void spi_disable_crc(u32 spi); -void spi_set_next_tx_from_buffer(u32 spi); -void spi_set_next_tx_from_crc(u32 spi); -void spi_set_dff_8bit(u32 spi); -void spi_set_dff_16bit(u32 spi); -void spi_set_full_duplex_mode(u32 spi); -void spi_set_receive_only_mode(u32 spi); -void spi_disable_software_slave_management(u32 spi); -void spi_enable_software_slave_management(u32 spi); -void spi_set_nss_high(u32 spi); -void spi_set_nss_low(u32 spi); -void spi_send_lsb_first(u32 spi); -void spi_send_msb_first(u32 spi); -void spi_set_baudrate_prescaler(u32 spi, u8 baudrate); -void spi_set_master_mode(u32 spi); -void spi_set_slave_mode(u32 spi); -void spi_set_clock_polarity_1(u32 spi); -void spi_set_clock_polarity_0(u32 spi); -void spi_set_clock_phase_1(u32 spi); -void spi_set_clock_phase_0(u32 spi); -void spi_enable_tx_buffer_empty_interrupt(u32 spi); -void spi_disable_tx_buffer_empty_interrupt(u32 spi); -void spi_enable_rx_buffer_not_empty_interrupt(u32 spi); -void spi_disable_rx_buffer_not_empty_interrupt(u32 spi); -void spi_enable_error_interrupt(u32 spi); -void spi_disable_error_interrupt(u32 spi); -void spi_enable_ss_output(u32 spi); -void spi_disable_ss_output(u32 spi); -void spi_enable_tx_dma(u32 spi); -void spi_disable_tx_dma(u32 spi); -void spi_enable_rx_dma(u32 spi); -void spi_disable_rx_dma(u32 spi); - -#endif diff --git a/include/libopencm3/stm32_common/timer.h b/include/libopencm3/stm32_common/timer.h deleted file mode 100644 index c1eac99..0000000 --- a/include/libopencm3/stm32_common/timer.h +++ /dev/null @@ -1,921 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Piotr Esden-Tempski - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_TIMER_H -#define LIBOPENCM3_TIMER_H - -#include -#include - -/* --- Convenience macros -------------------------------------------------- */ - -/* Timer register base adresses (for convenience) */ -#define TIM1 TIM1_BASE -#define TIM2 TIM2_BASE -#define TIM3 TIM3_BASE -#define TIM4 TIM4_BASE -#define TIM5 TIM5_BASE -#define TIM6 TIM6_BASE -#define TIM7 TIM7_BASE -#define TIM8 TIM8_BASE - -/* --- Timer registers ----------------------------------------------------- */ - -/* Control register 1 (TIMx_CR1) */ -#define TIM_CR1(tim_base) MMIO32(tim_base + 0x00) -#define TIM1_CR1 TIM_CR1(TIM1) -#define TIM2_CR1 TIM_CR1(TIM2) -#define TIM3_CR1 TIM_CR1(TIM3) -#define TIM4_CR1 TIM_CR1(TIM4) -#define TIM5_CR1 TIM_CR1(TIM5) -#define TIM6_CR1 TIM_CR1(TIM6) -#define TIM7_CR1 TIM_CR1(TIM7) -#define TIM8_CR1 TIM_CR1(TIM8) - -/* Control register 2 (TIMx_CR2) */ -#define TIM_CR2(tim_base) MMIO32(tim_base + 0x04) -#define TIM1_CR2 TIM_CR2(TIM1) -#define TIM2_CR2 TIM_CR2(TIM2) -#define TIM3_CR2 TIM_CR2(TIM3) -#define TIM4_CR2 TIM_CR2(TIM4) -#define TIM5_CR2 TIM_CR2(TIM5) -#define TIM6_CR2 TIM_CR2(TIM6) -#define TIM7_CR2 TIM_CR2(TIM7) -#define TIM8_CR2 TIM_CR2(TIM8) - -/* Slave mode control register (TIMx_SMCR) */ -#define TIM_SMCR(tim_base) MMIO32(tim_base + 0x08) -#define TIM1_SMCR TIM_SMCR(TIM1) -#define TIM2_SMCR TIM_SMCR(TIM2) -#define TIM3_SMCR TIM_SMCR(TIM3) -#define TIM4_SMCR TIM_SMCR(TIM4) -#define TIM5_SMCR TIM_SMCR(TIM5) -#define TIM8_SMCR TIM_SMCR(TIM8) - -/* DMA/Interrupt enable register (TIMx_DIER) */ -#define TIM_DIER(tim_base) MMIO32(tim_base + 0x0C) -#define TIM1_DIER TIM_DIER(TIM1) -#define TIM2_DIER TIM_DIER(TIM2) -#define TIM3_DIER TIM_DIER(TIM3) -#define TIM4_DIER TIM_DIER(TIM4) -#define TIM5_DIER TIM_DIER(TIM5) -#define TIM6_DIER TIM_DIER(TIM6) -#define TIM7_DIER TIM_DIER(TIM7) -#define TIM8_DIER TIM_DIER(TIM8) - -/* Status register (TIMx_SR) */ -#define TIM_SR(tim_base) MMIO32(tim_base + 0x10) -#define TIM1_SR TIM_SR(TIM1) -#define TIM2_SR TIM_SR(TIM2) -#define TIM3_SR TIM_SR(TIM3) -#define TIM4_SR TIM_SR(TIM4) -#define TIM5_SR TIM_SR(TIM5) -#define TIM6_SR TIM_SR(TIM6) -#define TIM7_SR TIM_SR(TIM7) -#define TIM8_SR TIM_SR(TIM8) - -/* Event generation register (TIMx_EGR) */ -#define TIM_EGR(tim_base) MMIO32(tim_base + 0x14) -#define TIM1_EGR TIM_EGR(TIM1) -#define TIM2_EGR TIM_EGR(TIM2) -#define TIM3_EGR TIM_EGR(TIM3) -#define TIM4_EGR TIM_EGR(TIM4) -#define TIM5_EGR TIM_EGR(TIM5) -#define TIM6_EGR TIM_EGR(TIM6) -#define TIM7_EGR TIM_EGR(TIM7) -#define TIM8_EGR TIM_EGR(TIM8) - -/* Capture/compare mode register 1 (TIMx_CCMR1) */ -#define TIM_CCMR1(tim_base) MMIO32(tim_base + 0x18) -#define TIM1_CCMR1 TIM_CCMR1(TIM1) -#define TIM2_CCMR1 TIM_CCMR1(TIM2) -#define TIM3_CCMR1 TIM_CCMR1(TIM3) -#define TIM4_CCMR1 TIM_CCMR1(TIM4) -#define TIM5_CCMR1 TIM_CCMR1(TIM5) -#define TIM8_CCMR1 TIM_CCMR1(TIM8) - -/* Capture/compare mode register 2 (TIMx_CCMR2) */ -#define TIM_CCMR2(tim_base) MMIO32(tim_base + 0x1C) -#define TIM1_CCMR2 TIM_CCMR2(TIM1) -#define TIM2_CCMR2 TIM_CCMR2(TIM2) -#define TIM3_CCMR2 TIM_CCMR2(TIM3) -#define TIM4_CCMR2 TIM_CCMR2(TIM4) -#define TIM5_CCMR2 TIM_CCMR2(TIM5) -#define TIM8_CCMR2 TIM_CCMR2(TIM8) - -/* Capture/compare enable register (TIMx_CCER) */ -#define TIM_CCER(tim_base) MMIO32(tim_base + 0x20) -#define TIM1_CCER TIM_CCER(TIM1) -#define TIM2_CCER TIM_CCER(TIM2) -#define TIM3_CCER TIM_CCER(TIM3) -#define TIM4_CCER TIM_CCER(TIM4) -#define TIM5_CCER TIM_CCER(TIM5) -#define TIM8_CCER TIM_CCER(TIM8) - -/* Counter (TIMx_CNT) */ -#define TIM_CNT(tim_base) MMIO32(tim_base + 0x24) -#define TIM1_CNT TIM_CNT(TIM1) -#define TIM2_CNT TIM_CNT(TIM2) -#define TIM3_CNT TIM_CNT(TIM3) -#define TIM4_CNT TIM_CNT(TIM4) -#define TIM5_CNT TIM_CNT(TIM5) -#define TIM6_CNT TIM_CNT(TIM6) -#define TIM7_CNT TIM_CNT(TIM7) -#define TIM8_CNT TIM_CNT(TIM8) - -/* Prescaler (TIMx_PSC) */ -#define TIM_PSC(tim_base) MMIO32(tim_base + 0x28) -#define TIM1_PSC TIM_PSC(TIM1) -#define TIM2_PSC TIM_PSC(TIM2) -#define TIM3_PSC TIM_PSC(TIM3) -#define TIM4_PSC TIM_PSC(TIM4) -#define TIM5_PSC TIM_PSC(TIM5) -#define TIM6_PSC TIM_PSC(TIM6) -#define TIM7_PSC TIM_PSC(TIM7) -#define TIM8_PSC TIM_PSC(TIM8) - -/* Auto-reload register (TIMx_ARR) */ -#define TIM_ARR(tim_base) MMIO32(tim_base + 0x2C) -#define TIM1_ARR TIM_ARR(TIM1) -#define TIM2_ARR TIM_ARR(TIM2) -#define TIM3_ARR TIM_ARR(TIM3) -#define TIM4_ARR TIM_ARR(TIM4) -#define TIM5_ARR TIM_ARR(TIM5) -#define TIM6_ARR TIM_ARR(TIM6) -#define TIM7_ARR TIM_ARR(TIM7) -#define TIM8_ARR TIM_ARR(TIM8) - -/* Repetition counter register (TIMx_RCR) */ -#define TIM_RCR(tim_base) MMIO32(tim_base + 0x30) -#define TIM1_RCR TIM_RCR(TIM1) -#define TIM8_RCR TIM_RCR(TIM8) - -/* Capture/compare register 1 (TIMx_CCR1) */ -#define TIM_CCR1(tim_base) MMIO32(tim_base + 0x34) -#define TIM1_CCR1 TIM_CCR1(TIM1) -#define TIM2_CCR1 TIM_CCR1(TIM2) -#define TIM3_CCR1 TIM_CCR1(TIM3) -#define TIM4_CCR1 TIM_CCR1(TIM4) -#define TIM5_CCR1 TIM_CCR1(TIM5) -#define TIM8_CCR1 TIM_CCR1(TIM8) - -/* Capture/compare register 2 (TIMx_CCR2) */ -#define TIM_CCR2(tim_base) MMIO32(tim_base + 0x38) -#define TIM1_CCR2 TIM_CCR2(TIM1) -#define TIM2_CCR2 TIM_CCR2(TIM2) -#define TIM3_CCR2 TIM_CCR2(TIM3) -#define TIM4_CCR2 TIM_CCR2(TIM4) -#define TIM5_CCR2 TIM_CCR2(TIM5) -#define TIM8_CCR2 TIM_CCR2(TIM8) - -/* Capture/compare register 3 (TIMx_CCR3) */ -#define TIM_CCR3(tim_base) MMIO32(tim_base + 0x3C) -#define TIM1_CCR3 TIM_CCR3(TIM1) -#define TIM2_CCR3 TIM_CCR3(TIM2) -#define TIM3_CCR3 TIM_CCR3(TIM3) -#define TIM4_CCR3 TIM_CCR3(TIM4) -#define TIM5_CCR3 TIM_CCR3(TIM5) -#define TIM8_CCR3 TIM_CCR3(TIM8) - -/* Capture/compare register 4 (TIMx_CCR4) */ -#define TIM_CCR4(tim_base) MMIO32(tim_base + 0x40) -#define TIM1_CCR4 TIM_CCR4(TIM1) -#define TIM2_CCR4 TIM_CCR4(TIM2) -#define TIM3_CCR4 TIM_CCR4(TIM3) -#define TIM4_CCR4 TIM_CCR4(TIM4) -#define TIM5_CCR4 TIM_CCR4(TIM5) -#define TIM8_CCR4 TIM_CCR4(TIM8) - -/* Break and dead-time register (TIMx_BDTR) */ -#define TIM_BDTR(tim_base) MMIO32(tim_base + 0x44) -#define TIM1_BDTR TIM_BDTR(TIM1) -#define TIM8_BDTR TIM_BDTR(TIM8) - -/* DMA control register (TIMx_DCR) */ -#define TIM_DCR(tim_base) MMIO32(tim_base + 0x48) -#define TIM1_DCR TIM_DCR(TIM1) -#define TIM2_DCR TIM_DCR(TIM2) -#define TIM3_DCR TIM_DCR(TIM3) -#define TIM4_DCR TIM_DCR(TIM4) -#define TIM5_DCR TIM_DCR(TIM5) -#define TIM8_DCR TIM_DCR(TIM8) - -/* DMA address for full transfer (TIMx_DMAR) */ -#define TIM_DMAR(tim_base) MMIO32(tim_base + 0x4C) -#define TIM1_DMAR TIM_DMAR(TIM1) -#define TIM2_DMAR TIM_DMAR(TIM2) -#define TIM3_DMAR TIM_DMAR(TIM3) -#define TIM4_DMAR TIM_DMAR(TIM4) -#define TIM5_DMAR TIM_DMAR(TIM5) -#define TIM8_DMAR TIM_DMAR(TIM8) - -/* --- TIMx_CR1 values ----------------------------------------------------- */ - -/* CKD[1:0]: Clock division */ -#define TIM_CR1_CKD_CK_INT (0x0 << 8) -#define TIM_CR1_CKD_CK_INT_MUL_2 (0x1 << 8) -#define TIM_CR1_CKD_CK_INT_MUL_4 (0x2 << 8) -#define TIM_CR1_CKD_CK_INT_MASK (0x3 << 8) - -/* ARPE: Auto-reload preload enable */ -#define TIM_CR1_ARPE (1 << 7) - -/* CMS[1:0]: Center-aligned mode selection */ -#define TIM_CR1_CMS_EDGE (0x0 << 5) -#define TIM_CR1_CMS_CENTER_1 (0x1 << 5) -#define TIM_CR1_CMS_CENTER_2 (0x2 << 5) -#define TIM_CR1_CMS_CENTER_3 (0x3 << 5) -#define TIM_CR1_CMS_MASK (0x3 << 5) - -/* DIR: Direction */ -#define TIM_CR1_DIR_UP (0 << 4) -#define TIM_CR1_DIR_DOWN (1 << 4) - -/* OPM: One pulse mode */ -#define TIM_CR1_OPM (1 << 3) - -/* URS: Update request source */ -#define TIM_CR1_URS (1 << 2) - -/* UDIS: Update disable */ -#define TIM_CR1_UDIS (1 << 1) - -/* CEN: Counter enable */ -#define TIM_CR1_CEN (1 << 0) - -/* --- TIMx_CR2 values ----------------------------------------------------- */ - -/* OIS4: Output idle state 4 (OC4 output) */ -#define TIM_CR2_OIS4 (1 << 14) - -/* OIS3N: Output idle state 3 (OC3N output) */ -#define TIM_CR2_OIS3N (1 << 13) - -/* OIS3: Output idle state 3 (OC3 output) */ -#define TIM_CR2_OIS3 (1 << 12) - -/* OIS2N: Output idle state 2 (OC2N output) */ -#define TIM_CR2_OIS2N (1 << 11) - -/* OIS2: Output idle state 2 (OC2 output) */ -#define TIM_CR2_OIS2 (1 << 10) - -/* OIS1N: Output idle state 1 (OC1N output) */ -#define TIM_CR2_OIS1N (1 << 9) - -/* OIS1: Output idle state 1 (OC1 output) */ -#define TIM_CR2_OIS1 (1 << 8) -#define TIM_CR2_OIS_MASK (0x7f << 8) - -/* TI1S: TI1 selection */ -#define TIM_CR2_TI1S (1 << 7) - -/* MMS[2:0]: Master mode selection */ -#define TIM_CR2_MMS_RESET (0x0 << 4) -#define TIM_CR2_MMS_ENABLE (0x1 << 4) -#define TIM_CR2_MMS_UPDATE (0x2 << 4) -#define TIM_CR2_MMS_COMPARE_PULSE (0x3 << 4) -#define TIM_CR2_MMS_COMPARE_OC1REF (0x4 << 4) -#define TIM_CR2_MMS_COMPARE_OC2REF (0x5 << 4) -#define TIM_CR2_MMS_COMPARE_OC3REF (0x6 << 4) -#define TIM_CR2_MMS_COMPARE_OC4REF (0x7 << 4) -#define TIM_CR2_MMS_MASK (0x7 << 4) - -/* CCDS: Capture/compare DMA selection */ -#define TIM_CR2_CCDS (1 << 3) - -/* CCUS: Capture/compare control update selection */ -#define TIM_CR2_CCUS (1 << 2) - -/* CCPC: Capture/compare preload control */ -#define TIM_CR2_CCPC (1 << 0) - -/* --- TIMx_SMCR values ---------------------------------------------------- */ - -/* ETP: External trigger polarity */ -#define TIM_SMCR_ETP (1 << 15) - -/* ECE: External clock enable */ -#define TIM_SMCR_ECE (1 << 14) - -/* ETPS[1:0]: External trigger prescaler */ -#define TIM_SMCR_ETPS_OFF (0x0 << 12) -#define TIM_SMCR_ETPS_ETRP_DIV_2 (0x1 << 12) -#define TIM_SMCR_ETPS_ETRP_DIV_4 (0x2 << 12) -#define TIM_SMCR_ETPS_ETRP_DIV_8 (0x3 << 12) -#define TIM_SMCR_ETPS_MASK (0X3 << 12) - -/* ETF[3:0]: External trigger filter */ -#define TIM_SMCR_ETF_OFF (0x0 << 8) -#define TIM_SMCR_ETF_CK_INT_N_2 (0x1 << 8) -#define TIM_SMCR_ETF_CK_INT_N_4 (0x2 << 8) -#define TIM_SMCR_ETF_CK_INT_N_8 (0x3 << 8) -#define TIM_SMCR_ETF_DTS_DIV_2_N_6 (0x4 << 8) -#define TIM_SMCR_ETF_DTS_DIV_2_N_8 (0x5 << 8) -#define TIM_SMCR_ETF_DTS_DIV_4_N_6 (0x6 << 8) -#define TIM_SMCR_ETF_DTS_DIV_4_N_8 (0x7 << 8) -#define TIM_SMCR_ETF_DTS_DIV_8_N_6 (0x8 << 8) -#define TIM_SMCR_ETF_DTS_DIV_8_N_8 (0x9 << 8) -#define TIM_SMCR_ETF_DTS_DIV_16_N_5 (0xA << 8) -#define TIM_SMCR_ETF_DTS_DIV_16_N_6 (0xB << 8) -#define TIM_SMCR_ETF_DTS_DIV_16_N_8 (0xC << 8) -#define TIM_SMCR_ETF_DTS_DIV_32_N_5 (0xD << 8) -#define TIM_SMCR_ETF_DTS_DIV_32_N_6 (0xE << 8) -#define TIM_SMCR_ETF_DTS_DIV_32_N_8 (0xF << 8) -#define TIM_SMCR_ETF_MASK (0xF << 8) - -/* MSM: Master/slave mode */ -#define TIM_SMCR_MSM (1 << 7) - -/* TS[2:0]: Trigger selection */ -#define TIM_SMCR_TS_ITR0 (0x0 << 4) -#define TIM_SMCR_TS_ITR1 (0x1 << 4) -#define TIM_SMCR_TS_ITR2 (0x2 << 4) -#define TIM_SMCR_TS_ITR3 (0x3 << 4) -#define TIM_SMCR_TS_IT1F_ED (0x4 << 4) -#define TIM_SMCR_TS_IT1FP1 (0x5 << 4) -#define TIM_SMCR_TS_IT1FP2 (0x6 << 4) -#define TIM_SMCR_TS_ETRF (0x7 << 4) -#define TIM_SMCR_TS_MASK (0x7 << 4) - -/* SMS[2:0]: Slave mode selection */ -#define TIM_SMCR_SMS_OFF (0x0 << 0) -#define TIM_SMCR_SMS_EM1 (0x1 << 0) -#define TIM_SMCR_SMS_EM2 (0x2 << 0) -#define TIM_SMCR_SMS_EM3 (0x3 << 0) -#define TIM_SMCR_SMS_RM (0x4 << 0) -#define TIM_SMCR_SMS_GM (0x5 << 0) -#define TIM_SMCR_SMS_TM (0x6 << 0) -#define TIM_SMCR_SMS_ECM1 (0x7 << 0) -#define TIM_SMCR_SMS_MASK (0x7 << 0) - -/* --- TIMx_DIER values ---------------------------------------------------- */ - -/* TDE: Trigger DMA request enable */ -#define TIM_DIER_TDE (1 << 14) - -/* COMDE: COM DMA request enable */ -#define TIM_DIER_COMDE (1 << 13) - -/* CC4DE: Capture/Compare 4 DMA request enable */ -#define TIM_DIER_CC4DE (1 << 12) - -/* CC3DE: Capture/Compare 3 DMA request enable */ -#define TIM_DIER_CC3DE (1 << 11) - -/* CC2DE: Capture/Compare 2 DMA request enable */ -#define TIM_DIER_CC2DE (1 << 10) - -/* CC1DE: Capture/Compare 1 DMA request enable */ -#define TIM_DIER_CC1DE (1 << 9) - -/* UDE: Update DMA request enable */ -#define TIM_DIER_UDE (1 << 8) - -/* BIE: Break interrupt enable */ -#define TIM_DIER_BIE (1 << 7) - -/* TIE: Trigger interrupt enable */ -#define TIM_DIER_TIE (1 << 6) - -/* COMIE: COM interrupt enable */ -#define TIM_DIER_COMIE (1 << 5) - -/* CC4IE: Capture/compare 4 interrupt enable */ -#define TIM_DIER_CC4IE (1 << 4) - -/* CC3IE: Capture/compare 3 interrupt enable */ -#define TIM_DIER_CC3IE (1 << 3) - -/* CC2IE: Capture/compare 2 interrupt enable */ -#define TIM_DIER_CC2IE (1 << 2) - -/* CC1IE: Capture/compare 1 interrupt enable */ -#define TIM_DIER_CC1IE (1 << 1) - -/* UIE: Update interrupt enable */ -#define TIM_DIER_UIE (1 << 0) - -/* --- TIMx_SR values ------------------------------------------------------ */ - -/* CC4OF: Capture/compare 4 overcapture flag */ -#define TIM_SR_CC4OF (1 << 12) - -/* CC3OF: Capture/compare 3 overcapture flag */ -#define TIM_SR_CC3OF (1 << 11) - -/* CC2OF: Capture/compare 2 overcapture flag */ -#define TIM_SR_CC2OF (1 << 10) - -/* CC1OF: Capture/compare 1 overcapture flag */ -#define TIM_SR_CC1OF (1 << 9) - -/* BIF: Break interrupt flag */ -#define TIM_SR_BIF (1 << 7) - -/* TIF: Trigger interrupt flag */ -#define TIM_SR_TIF (1 << 6) - -/* COMIF: COM interrupt flag */ -#define TIM_SR_COMIF (1 << 5) - -/* CC4IF: Capture/compare 4 interrupt flag */ -#define TIM_SR_CC4IF (1 << 4) - -/* CC3IF: Capture/compare 3 interrupt flag */ -#define TIM_SR_CC3IF (1 << 3) - -/* CC2IF: Capture/compare 2 interrupt flag */ -#define TIM_SR_CC2IF (1 << 2) - -/* CC1IF: Capture/compare 1 interrupt flag */ -#define TIM_SR_CC1IF (1 << 1) - -/* UIF: Update interrupt flag */ -#define TIM_SR_UIF (1 << 0) - -/* --- TIMx_EGR values ----------------------------------------------------- */ - -/* BG: Break generation */ -#define TIM_EGR_BG (1 << 7) - -/* TG: Trigger generation */ -#define TIM_EGR_TG (1 << 6) - -/* COMG: Capture/compare control update generation */ -#define TIM_EGR_COMG (1 << 5) - -/* CC4G: Capture/compare 4 generation */ -#define TIM_EGR_CC4G (1 << 4) - -/* CC3G: Capture/compare 3 generation */ -#define TIM_EGR_CC3G (1 << 3) - -/* CC2G: Capture/compare 2 generation */ -#define TIM_EGR_CC2G (1 << 2) - -/* CC1G: Capture/compare 1 generation */ -#define TIM_EGR_CC1G (1 << 1) - -/* UG: Update generation */ -#define TIM_EGR_UG (1 << 0) - -/* --- TIMx_CCMR1 values --------------------------------------------------- */ - -/* --- Output compare mode --- */ - -/* OC2CE: Output compare 2 clear enable */ -#define TIM_CCMR1_OC2CE (1 << 15) - -/* OC2M[2:0]: Output compare 2 mode */ -#define TIM_CCMR1_OC2M_FROZEN (0x0 << 12) -#define TIM_CCMR1_OC2M_ACTIVE (0x1 << 12) -#define TIM_CCMR1_OC2M_INACTIVE (0x2 << 12) -#define TIM_CCMR1_OC2M_TOGGLE (0x3 << 12) -#define TIM_CCMR1_OC2M_FORCE_LOW (0x4 << 12) -#define TIM_CCMR1_OC2M_FORCE_HIGH (0x5 << 12) -#define TIM_CCMR1_OC2M_PWM1 (0x6 << 12) -#define TIM_CCMR1_OC2M_PWM2 (0x7 << 12) -#define TIM_CCMR1_OC2M_MASK (0x7 << 12) - -/* OC2PE: Output compare 2 preload enable */ -#define TIM_CCMR1_OC2PE (1 << 11) - -/* OC2FE: Output compare 2 fast enable */ -#define TIM_CCMR1_OC2FE (1 << 10) - -/* CC2S[1:0]: Capture/compare 2 selection */ -/* Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in - * TIMx_CCER). */ -#define TIM_CCMR1_CC2S_OUT (0x0 << 8) -#define TIM_CCMR1_CC2S_IN_TI2 (0x1 << 8) -#define TIM_CCMR1_CC2S_IN_TI1 (0x2 << 8) -#define TIM_CCMR1_CC2S_IN_TRC (0x3 << 8) -#define TIM_CCMR1_CC2S_MASK (0x3 << 8) - -/* OC1CE: Output compare 1 clear enable */ -#define TIM_CCMR1_OC1CE (1 << 7) - -/* OC1M[2:0]: Output compare 1 mode */ -#define TIM_CCMR1_OC1M_FROZEN (0x0 << 4) -#define TIM_CCMR1_OC1M_ACTIVE (0x1 << 4) -#define TIM_CCMR1_OC1M_INACTIVE (0x2 << 4) -#define TIM_CCMR1_OC1M_TOGGLE (0x3 << 4) -#define TIM_CCMR1_OC1M_FORCE_LOW (0x4 << 4) -#define TIM_CCMR1_OC1M_FORCE_HIGH (0x5 << 4) -#define TIM_CCMR1_OC1M_PWM1 (0x6 << 4) -#define TIM_CCMR1_OC1M_PWM2 (0x7 << 4) -#define TIM_CCMR1_OC1M_MASK (0x7 << 4) - -/* OC1PE: Output compare 1 preload enable */ -#define TIM_CCMR1_OC1PE (1 << 3) - -/* OC1FE: Output compare 1 fast enable */ -#define TIM_CCMR1_OC1FE (1 << 2) - -/* CC1S[1:0]: Capture/compare 1 selection */ -/* Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in - * TIMx_CCER). */ -#define TIM_CCMR1_CC1S_OUT (0x0 << 0) -#define TIM_CCMR1_CC1S_IN_TI2 (0x1 << 0) -#define TIM_CCMR1_CC1S_IN_TI1 (0x2 << 0) -#define TIM_CCMR1_CC1S_IN_TRC (0x3 << 0) -#define TIM_CCMR1_CC1S_MASK (0x3 << 0) - -/* --- Input capture mode --- */ - -/* IC2F[3:0]: Input capture 2 filter */ -#define TIM_CCMR1_IC2F_OFF (0x0 << 12) -#define TIM_CCMR1_IC2F_CK_INT_N_2 (0x1 << 12) -#define TIM_CCMR1_IC2F_CK_INT_N_4 (0x2 << 12) -#define TIM_CCMR1_IC2F_CK_INT_N_8 (0x3 << 12) -#define TIM_CCMR1_IC2F_DTF_DIV_2_N_6 (0x4 << 12) -#define TIM_CCMR1_IC2F_DTF_DIV_2_N_8 (0x5 << 12) -#define TIM_CCMR1_IC2F_DTF_DIV_4_N_6 (0x6 << 12) -#define TIM_CCMR1_IC2F_DTF_DIV_4_N_8 (0x7 << 12) -#define TIM_CCMR1_IC2F_DTF_DIV_8_N_6 (0x8 << 12) -#define TIM_CCMR1_IC2F_DTF_DIV_8_N_8 (0x9 << 12) -#define TIM_CCMR1_IC2F_DTF_DIV_16_N_5 (0xA << 12) -#define TIM_CCMR1_IC2F_DTF_DIV_16_N_6 (0xB << 12) -#define TIM_CCMR1_IC2F_DTF_DIV_16_N_8 (0xC << 12) -#define TIM_CCMR1_IC2F_DTF_DIV_32_N_5 (0xD << 12) -#define TIM_CCMR1_IC2F_DTF_DIV_32_N_6 (0xE << 12) -#define TIM_CCMR1_IC2F_DTF_DIV_32_N_8 (0xF << 12) -#define TIM_CCMR1_IC2F_MASK (0xF << 12) - -/* IC2PSC[1:0]: Input capture 2 prescaler */ -#define TIM_CCMR1_IC2PSC_OFF (0x0 << 10) -#define TIM_CCMR1_IC2PSC_2 (0x1 << 10) -#define TIM_CCMR1_IC2PSC_4 (0x2 << 10) -#define TIM_CCMR1_IC2PSC_8 (0x3 << 10) -#define TIM_CCMR1_IC2PSC_MASK (0x3 << 10) - -/* IC1F[3:0]: Input capture 1 filter */ -#define TIM_CCMR1_IC1F_OFF (0x0 << 4) -#define TIM_CCMR1_IC1F_CK_INT_N_2 (0x1 << 4) -#define TIM_CCMR1_IC1F_CK_INT_N_4 (0x2 << 4) -#define TIM_CCMR1_IC1F_CK_INT_N_8 (0x3 << 4) -#define TIM_CCMR1_IC1F_DTF_DIV_2_N_6 (0x4 << 4) -#define TIM_CCMR1_IC1F_DTF_DIV_2_N_8 (0x5 << 4) -#define TIM_CCMR1_IC1F_DTF_DIV_4_N_6 (0x6 << 4) -#define TIM_CCMR1_IC1F_DTF_DIV_4_N_8 (0x7 << 4) -#define TIM_CCMR1_IC1F_DTF_DIV_8_N_6 (0x8 << 4) -#define TIM_CCMR1_IC1F_DTF_DIV_8_N_8 (0x9 << 4) -#define TIM_CCMR1_IC1F_DTF_DIV_16_N_5 (0xA << 4) -#define TIM_CCMR1_IC1F_DTF_DIV_16_N_6 (0xB << 4) -#define TIM_CCMR1_IC1F_DTF_DIV_16_N_8 (0xC << 4) -#define TIM_CCMR1_IC1F_DTF_DIV_32_N_5 (0xD << 4) -#define TIM_CCMR1_IC1F_DTF_DIV_32_N_6 (0xE << 4) -#define TIM_CCMR1_IC1F_DTF_DIV_32_N_8 (0xF << 4) -#define TIM_CCMR1_IC1F_MASK (0xF << 4) - -/* IC1PSC[1:0]: Input capture 1 prescaler */ -#define TIM_CCMR1_IC1PSC_OFF (0x0 << 2) -#define TIM_CCMR1_IC1PSC_2 (0x1 << 2) -#define TIM_CCMR1_IC1PSC_4 (0x2 << 2) -#define TIM_CCMR1_IC1PSC_8 (0x3 << 2) -#define TIM_CCMR1_IC1PSC_MASK (0x3 << 2) - -/* --- TIMx_CCMR2 values --------------------------------------------------- */ - -/* --- Output compare mode --- */ - -/* OC4CE: Output compare 4 clear enable */ -#define TIM_CCMR2_OC4CE (1 << 15) - -/* OC4M[2:0]: Output compare 4 mode */ -#define TIM_CCMR2_OC4M_FROZEN (0x0 << 12) -#define TIM_CCMR2_OC4M_ACTIVE (0x1 << 12) -#define TIM_CCMR2_OC4M_INACTIVE (0x2 << 12) -#define TIM_CCMR2_OC4M_TOGGLE (0x3 << 12) -#define TIM_CCMR2_OC4M_FORCE_LOW (0x4 << 12) -#define TIM_CCMR2_OC4M_FORCE_HIGH (0x5 << 12) -#define TIM_CCMR2_OC4M_PWM1 (0x6 << 12) -#define TIM_CCMR2_OC4M_PWM2 (0x7 << 12) -#define TIM_CCMR2_OC4M_MASK (0x7 << 12) - -/* OC4PE: Output compare 4 preload enable */ -#define TIM_CCMR2_OC4PE (1 << 11) - -/* OC4FE: Output compare 4 fast enable */ -#define TIM_CCMR2_OC4FE (1 << 10) - -/* CC4S[1:0]: Capture/compare 4 selection */ -/* Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in - * TIMx_CCER). */ -#define TIM_CCMR2_CC4S_OUT (0x0 << 8) -#define TIM_CCMR2_CC4S_IN_TI2 (0x1 << 8) -#define TIM_CCMR2_CC4S_IN_TI1 (0x2 << 8) -#define TIM_CCMR2_CC4S_IN_TRC (0x3 << 8) -#define TIM_CCMR2_CC4S_MASK (0x3 << 8) - -/* OC3CE: Output compare 3 clear enable */ -#define TIM_CCMR2_OC3CE (1 << 7) - -/* OC3M[2:0]: Output compare 3 mode */ -#define TIM_CCMR2_OC3M_FROZEN (0x0 << 4) -#define TIM_CCMR2_OC3M_ACTIVE (0x1 << 4) -#define TIM_CCMR2_OC3M_INACTIVE (0x2 << 4) -#define TIM_CCMR2_OC3M_TOGGLE (0x3 << 4) -#define TIM_CCMR2_OC3M_FORCE_LOW (0x4 << 4) -#define TIM_CCMR2_OC3M_FORCE_HIGH (0x5 << 4) -#define TIM_CCMR2_OC3M_PWM1 (0x6 << 4) -#define TIM_CCMR2_OC3M_PWM2 (0x7 << 4) -#define TIM_CCMR2_OC3M_MASK (0x7 << 4) - -/* OC3PE: Output compare 3 preload enable */ -#define TIM_CCMR2_OC3PE (1 << 3) - -/* OC3FE: Output compare 3 fast enable */ -#define TIM_CCMR2_OC3FE (1 << 2) - -/* CC3S[1:0]: Capture/compare 3 selection */ -/* Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in - * TIMx_CCER). */ -#define TIM_CCMR2_CC3S_OUT (0x0 << 0) -#define TIM_CCMR2_CC3S_IN_TI2 (0x1 << 0) -#define TIM_CCMR2_CC3S_IN_TI1 (0x2 << 0) -#define TIM_CCMR2_CC3S_IN_TRC (0x3 << 0) -#define TIM_CCMR2_CC3S_MASK (0x3 << 0) - -/* --- Input capture mode --- */ - -/* IC4F[3:0]: Input capture 4 filter */ -#define TIM_CCMR2_IC4F_OFF (0x0 << 12) -#define TIM_CCMR2_IC4F_CK_INT_N_2 (0x1 << 12) -#define TIM_CCMR2_IC4F_CK_INT_N_4 (0x2 << 12) -#define TIM_CCMR2_IC4F_CK_INT_N_8 (0x3 << 12) -#define TIM_CCMR2_IC4F_DTF_DIV_2_N_6 (0x4 << 12) -#define TIM_CCMR2_IC4F_DTF_DIV_2_N_8 (0x5 << 12) -#define TIM_CCMR2_IC4F_DTF_DIV_4_N_6 (0x6 << 12) -#define TIM_CCMR2_IC4F_DTF_DIV_4_N_8 (0x7 << 12) -#define TIM_CCMR2_IC4F_DTF_DIV_8_N_6 (0x8 << 12) -#define TIM_CCMR2_IC4F_DTF_DIV_8_N_8 (0x9 << 12) -#define TIM_CCMR2_IC4F_DTF_DIV_16_N_5 (0xA << 12) -#define TIM_CCMR2_IC4F_DTF_DIV_16_N_6 (0xB << 12) -#define TIM_CCMR2_IC4F_DTF_DIV_16_N_8 (0xC << 12) -#define TIM_CCMR2_IC4F_DTF_DIV_32_N_5 (0xD << 12) -#define TIM_CCMR2_IC4F_DTF_DIV_32_N_6 (0xE << 12) -#define TIM_CCMR2_IC4F_DTF_DIV_32_N_8 (0xF << 12) -#define TIM_CCMR2_IC4F_MASK (0xF << 12) - -/* IC4PSC[1:0]: Input capture 4 prescaler */ -#define TIM_CCMR2_IC4PSC_OFF (0x0 << 10) -#define TIM_CCMR2_IC4PSC_2 (0x1 << 10) -#define TIM_CCMR2_IC4PSC_4 (0x2 << 10) -#define TIM_CCMR2_IC4PSC_8 (0x3 << 10) -#define TIM_CCMR2_IC4PSC_MASK (0x3 << 10) - -/* IC3F[3:0]: Input capture 3 filter */ -#define TIM_CCMR2_IC3F_OFF (0x0 << 4) -#define TIM_CCMR2_IC3F_CK_INT_N_2 (0x1 << 4) -#define TIM_CCMR2_IC3F_CK_INT_N_4 (0x2 << 4) -#define TIM_CCMR2_IC3F_CK_INT_N_8 (0x3 << 4) -#define TIM_CCMR2_IC3F_DTF_DIV_2_N_6 (0x4 << 4) -#define TIM_CCMR2_IC3F_DTF_DIV_2_N_8 (0x5 << 4) -#define TIM_CCMR2_IC3F_DTF_DIV_4_N_6 (0x6 << 4) -#define TIM_CCMR2_IC3F_DTF_DIV_4_N_8 (0x7 << 4) -#define TIM_CCMR2_IC3F_DTF_DIV_8_N_6 (0x8 << 4) -#define TIM_CCMR2_IC3F_DTF_DIV_8_N_8 (0x9 << 4) -#define TIM_CCMR2_IC3F_DTF_DIV_16_N_5 (0xA << 4) -#define TIM_CCMR2_IC3F_DTF_DIV_16_N_6 (0xB << 4) -#define TIM_CCMR2_IC3F_DTF_DIV_16_N_8 (0xC << 4) -#define TIM_CCMR2_IC3F_DTF_DIV_32_N_5 (0xD << 4) -#define TIM_CCMR2_IC3F_DTF_DIV_32_N_6 (0xE << 4) -#define TIM_CCMR2_IC3F_DTF_DIV_32_N_8 (0xF << 4) -#define TIM_CCMR2_IC3F_MASK (0xF << 4) - -/* IC3PSC[1:0]: Input capture 3 prescaler */ -#define TIM_CCMR2_IC3PSC_OFF (0x0 << 2) -#define TIM_CCMR2_IC3PSC_2 (0x1 << 2) -#define TIM_CCMR2_IC3PSC_4 (0x2 << 2) -#define TIM_CCMR2_IC3PSC_8 (0x3 << 2) -#define TIM_CCMR2_IC3PSC_MASK (0x3 << 2) - -/* --- TIMx_CCER values ---------------------------------------------------- */ - -/* CC4P: Capture/compare 4 output polarity */ -#define TIM_CCER_CC4P (1 << 13) - -/* CC4E: Capture/compare 4 output enable */ -#define TIM_CCER_CC4E (1 << 12) - -/* CC3NP: Capture/compare 3 complementary output polarity */ -#define TIM_CCER_CC3NP (1 << 11) - -/* CC3NE: Capture/compare 3 complementary output enable */ -#define TIM_CCER_CC3NE (1 << 10) - -/* CC3P: Capture/compare 3 output polarity */ -#define TIM_CCER_CC3P (1 << 9) - -/* CC3E: Capture/compare 3 output enable */ -#define TIM_CCER_CC3E (1 << 8) - -/* CC2NP: Capture/compare 2 complementary output polarity */ -#define TIM_CCER_CC2NP (1 << 7) - -/* CC2NE: Capture/compare 2 complementary output enable */ -#define TIM_CCER_CC2NE (1 << 6) - -/* CC2P: Capture/compare 2 output polarity */ -#define TIM_CCER_CC2P (1 << 5) - -/* CC2E: Capture/compare 2 output enable */ -#define TIM_CCER_CC2E (1 << 4) - -/* CC1NP: Capture/compare 1 complementary output polarity */ -#define TIM_CCER_CC1NP (1 << 3) - -/* CC1NE: Capture/compare 1 complementary output enable */ -#define TIM_CCER_CC1NE (1 << 2) - -/* CC1P: Capture/compare 1 output polarity */ -#define TIM_CCER_CC1P (1 << 1) - -/* CC1E: Capture/compare 1 output enable */ -#define TIM_CCER_CC1E (1 << 0) - -/* --- TIMx_CNT values ----------------------------------------------------- */ - -/* CNT[15:0]: Counter value */ - -/* --- TIMx_PSC values ----------------------------------------------------- */ - -/* PSC[15:0]: Prescaler value */ - -/* --- TIMx_ARR values ----------------------------------------------------- */ - -/* ARR[15:0]: Prescaler value */ - -/* --- TIMx_RCR values ----------------------------------------------------- */ - -/* REP[15:0]: Repetition counter value */ - -/* --- TIMx_CCR1 values ---------------------------------------------------- */ - -/* CCR1[15:0]: Capture/compare 1 value */ - -/* --- TIMx_CCR2 values ---------------------------------------------------- */ - -/* CCR2[15:0]: Capture/compare 2 value */ - -/* --- TIMx_CCR3 values ---------------------------------------------------- */ - -/* CCR3[15:0]: Capture/compare 3 value */ - -/* --- TIMx_CCR4 values ---------------------------------------------------- */ - -/* CCR4[15:0]: Capture/compare 4 value */ - -/* --- TIMx_BDTR values ---------------------------------------------------- */ - -/* MOE: Main output enable */ -#define TIM_BDTR_MOE (1 << 15) - -/* AOE: Automatic output enable */ -#define TIM_BDTR_AOE (1 << 14) - -/* BKP: Break polarity */ -#define TIM_BDTR_BKP (1 << 13) - -/* BKE: Break enable */ -#define TIM_BDTR_BKE (1 << 12) - -/* OSSR: Off-state selection of run mode */ -#define TIM_BDTR_OSSR (1 << 11) - -/* OSSI: Off-state selection of idle mode */ -#define TIM_BDTR_OSSI (1 << 10) - -/* LOCK[1:0]: Lock configuration */ -#define TIM_BDTR_LOCK_OFF (0x0 << 8) -#define TIM_BDTR_LOCK_LEVEL_1 (0x1 << 8) -#define TIM_BDTR_LOCK_LEVEL_2 (0x2 << 8) -#define TIM_BDTR_LOCK_LEVEL_3 (0x3 << 8) -#define TIM_BDTR_LOCK_MASK (0x3 << 8) - -/* DTG[7:0]: Dead-time generator set-up */ -#define TIM_BDTR_DTG_MASK 0x00FF - -/* --- TIMx_DCR values ----------------------------------------------------- */ - -/* DBL[4:0]: DMA burst length */ -#define TIM_BDTR_DBL_MASK (0x1F << 8) - -/* DBA[4:0]: DMA base address */ -#define TIM_BDTR_DBA_MASK (0x1F << 0) - -/* --- TIMx_DMAR values ---------------------------------------------------- */ - -/* DMAB[15:0]: DMA register for burst accesses */ - -/* --- TIMx convenience defines -------------------------------------------- */ - -/* Output Compare channel designators */ -enum tim_oc_id { - TIM_OC1=0, - TIM_OC1N, - TIM_OC2, - TIM_OC2N, - TIM_OC3, - TIM_OC3N, - TIM_OC4, -}; - -/* Output Compare mode designators */ -enum tim_oc_mode { - TIM_OCM_FROZEN, - TIM_OCM_ACTIVE, - TIM_OCM_INACTIVE, - TIM_OCM_TOGGLE, - TIM_OCM_FORCE_LOW, - TIM_OCM_FORCE_HIGH, - TIM_OCM_PWM1, - TIM_OCM_PWM2, -}; - -/* --- TIM functions ------------------------------------------------------- */ -void timer_reset(u32 timer_peripheral); -void timer_enable_irq(u32 timer_peripheral, u32 irq); -void timer_disable_irq(u32 timer_peripheral, u32 irq); -bool timer_get_flag(u32 timer_peripheral, u32 flag); -void timer_clear_flag(u32 timer_peripheral, u32 flag); -void timer_set_mode(u32 timer_peripheral, u8 clock_div, - u8 alignment, u8 direction); -void timer_set_clock_division(u32 timer_peripheral, u32 clock_div); -void timer_enable_preload(u32 timer_peripheral); -void timer_disable_preload(u32 timer_peripheral); -void timer_set_alignment(u32 timer_peripheral, u32 alignment); -void timer_direction_up(u32 timer_peripheral); -void timer_direction_down(u32 timer_peripheral); -void timer_one_shot_mode(u32 timer_peripheral); -void timer_continuous_mode(u32 timer_peripheral); -void timer_update_on_any(u32 timer_peripheral); -void timer_update_on_overflow(u32 timer_peripheral); -void timer_enable_update_event(u32 timer_peripheral); -void timer_disable_update_event(u32 timer_peripheral); -void timer_enable_counter(u32 timer_peripheral); -void timer_disable_counter(u32 timer_peripheral); -void timer_set_output_idle_state(u32 timer_peripheral, u32 outputs); -void timer_reset_output_idle_state(u32 timer_peripheral, u32 outputs); -void timer_set_ti1_ch123_xor(u32 timer_peripheral); -void timer_set_ti1_ch1(u32 timer_peripheral); -void timer_set_master_mode(u32 timer_peripheral, u32 mode); -void timer_set_dma_on_compare_event(u32 timer_peripheral); -void timer_set_dma_on_update_event(u32 timer_peripheral); -void timer_enable_compare_control_update_on_trigger(u32 timer_peripheral); -void timer_disable_compare_control_update_on_trigger(u32 timer_peripheral); -void timer_enable_preload_complementry_enable_bits(u32 timer_peripheral); -void timer_disable_preload_complementry_enable_bits(u32 timer_peripheral); -void timer_set_prescaler(u32 timer_peripheral, u32 value); -void timer_set_repetition_counter(u32 timer_peripheral, u32 value); -void timer_set_period(u32 timer_peripheral, u32 period); -void timer_enable_oc_clear(u32 timer_peripheral, enum tim_oc_id oc_id); -void timer_disable_oc_clear(u32 timer_peripheral, enum tim_oc_id oc_id); -void timer_set_oc_fast_mode(u32 timer_peripheral, enum tim_oc_id oc_id); -void timer_set_oc_slow_mode(u32 timer_peripheral, enum tim_oc_id oc_id); -void timer_set_oc_mode(u32 timer_peripheral, enum tim_oc_id oc_id, enum tim_oc_mode oc_mode); -void timer_enable_oc_preload(u32 timer_peripheral, enum tim_oc_id oc_id); -void timer_disable_oc_preload(u32 timer_peripheral, enum tim_oc_id oc_id); -void timer_set_oc_polarity_high(u32 timer_peripheral, enum tim_oc_id oc_id); -void timer_set_oc_polarity_low(u32 timer_peripheral, enum tim_oc_id oc_id); -void timer_enable_oc_output(u32 timer_peripheral, enum tim_oc_id oc_id); -void timer_disable_oc_output(u32 timer_peripheral, enum tim_oc_id oc_id); -void timer_set_oc_idle_state_set(u32 timer_peripheral, enum tim_oc_id oc_id); -void timer_set_oc_idle_state_unset(u32 timer_peripheral, enum tim_oc_id oc_id); -void timer_set_oc_value(u32 timer_peripheral, enum tim_oc_id oc_id, u32 value); -void timer_enable_break_main_output(u32 timer_peripheral); -void timer_disable_break_main_output(u32 timer_peripheral); -void timer_enable_break_automatic_output(u32 timer_peripheral); -void timer_disable_break_automatic_output(u32 timer_peripheral); -void timer_set_break_polarity_high(u32 timer_peripheral); -void timer_set_break_polarity_low(u32 timer_peripheral); -void timer_enable_break(u32 timer_peripheral); -void timer_disable_break(u32 timer_peripheral); -void timer_set_enabled_off_state_in_run_mode(u32 timer_peripheral); -void timer_set_disabled_off_state_in_run_mode(u32 timer_peripheral); -void timer_set_enabled_off_state_in_idle_mode(u32 timer_peripheral); -void timer_set_disabled_off_state_in_idle_mode(u32 timer_peripheral); -void timer_set_break_lock(u32 timer_peripheral, u32 lock); -void timer_set_deadtime(u32 timer_peripheral, u32 deadtime); -void timer_generate_event(u32 timer_peripheral, u32 event); -u32 timer_get_counter(u32 timer_peripheral); - -#endif diff --git a/include/libopencm3/stm32_common/usart.h b/include/libopencm3/stm32_common/usart.h deleted file mode 100644 index 0a1ed36..0000000 --- a/include/libopencm3/stm32_common/usart.h +++ /dev/null @@ -1,312 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_USART_H -#define LIBOPENCM3_USART_H - -#include -#include - -/* --- Convenience macros -------------------------------------------------- */ - -#define USART1 USART1_BASE -#define USART2 USART2_BASE -#define USART3 USART3_BASE -#define UART4 UART4_BASE -#define UART5 UART5_BASE - -/* --- USART registers ----------------------------------------------------- */ - -/* Status register (USARTx_SR) */ -#define USART_SR(usart_base) MMIO32(usart_base + 0x00) -#define USART1_SR USART_SR(USART1_BASE) -#define USART2_SR USART_SR(USART2_BASE) -#define USART3_SR USART_SR(USART3_BASE) -#define UART4_SR USART_SR(UART4_BASE) -#define UART5_SR USART_SR(UART5_BASE) - -/* Data register (USARTx_DR) */ -#define USART_DR(usart_base) MMIO32(usart_base + 0x04) -#define USART1_DR USART_DR(USART1_BASE) -#define USART2_DR USART_DR(USART2_BASE) -#define USART3_DR USART_DR(USART3_BASE) -#define UART4_DR USART_DR(UART4_BASE) -#define UART5_DR USART_DR(UART5_BASE) - -/* Baud rate register (USARTx_BRR) */ -#define USART_BRR(usart_base) MMIO32(usart_base + 0x08) -#define USART1_BRR USART_BRR(USART1_BASE) -#define USART2_BRR USART_BRR(USART2_BASE) -#define USART3_BRR USART_BRR(USART3_BASE) -#define UART4_BRR USART_BRR(UART4_BASE) -#define UART5_BRR USART_BRR(UART5_BASE) - -/* Control register 1 (USARTx_CR1) */ -#define USART_CR1(usart_base) MMIO32(usart_base + 0x0c) -#define USART1_CR1 USART_CR1(USART1_BASE) -#define USART2_CR1 USART_CR1(USART2_BASE) -#define USART3_CR1 USART_CR1(USART3_BASE) -#define UART4_CR1 USART_CR1(UART4_BASE) -#define UART5_CR1 USART_CR1(UART5_BASE) - -/* Control register 2 (USARTx_CR2) */ -#define USART_CR2(usart_base) MMIO32(usart_base + 0x10) -#define USART1_CR2 USART_CR2(USART1_BASE) -#define USART2_CR2 USART_CR2(USART2_BASE) -#define USART3_CR2 USART_CR2(USART3_BASE) -#define UART4_CR2 USART_CR2(UART4_BASE) -#define UART5_CR2 USART_CR2(UART5_BASE) - -/* Control register 3 (USARTx_CR3) */ -#define USART_CR3(usart_base) MMIO32(usart_base + 0x14) -#define USART1_CR3 USART_CR3(USART1_BASE) -#define USART2_CR3 USART_CR3(USART2_BASE) -#define USART3_CR3 USART_CR3(USART3_BASE) -#define UART4_CR3 USART_CR3(UART4_BASE) -#define UART5_CR3 USART_CR3(UART5_BASE) - -/* Guard time and prescaler register (USARTx_GTPR) */ -#define USART_GTPR(usart_base) MMIO32(usart_base + 0x18) -#define USART1_GTPR USART_GTPR(USART1_BASE) -#define USART2_GTPR USART_GTPR(USART2_BASE) -#define USART3_GTPR USART_GTPR(USART3_BASE) -#define UART4_GTPR USART_GTPR(UART4_BASE) -#define UART5_GTPR USART_GTPR(UART5_BASE) - -/* --- USART_SR values ----------------------------------------------------- */ - -/* CTS: CTS flag */ -/* Note: N/A on UART4/5 */ -#define USART_SR_CTS (1 << 9) - -/* LBD: LIN break detection flag */ -#define USART_SR_LBD (1 << 8) - -/* TXE: Transmit data buffer empty */ -#define USART_SR_TXE (1 << 7) - -/* TC: Transmission complete */ -#define USART_SR_TC (1 << 6) - -/* RXNE: Read data register not empty */ -#define USART_SR_RXNE (1 << 5) - -/* IDLE: Idle line detected */ -#define USART_SR_IDLE (1 << 4) - -/* ORE: Overrun error */ -#define USART_SR_ORE (1 << 3) - -/* NE: Noise error flag */ -#define USART_SR_NE (1 << 2) - -/* FE: Framing error */ -#define USART_SR_FE (1 << 1) - -/* PE: Parity error */ -#define USART_SR_PE (1 << 0) - -/* --- USART_DR values ----------------------------------------------------- */ - -/* USART_DR[8:0]: DR[8:0]: Data value */ -#define USART_DR_MASK 0x1FF - -/* --- USART_BRR values ---------------------------------------------------- */ - -/* DIV_Mantissa[11:0]: mantissa of USARTDIV */ -#define USART_BRR_DIV_MANTISSA_MASK (0xFFF << 4) -/* DIV_Fraction[3:0]: fraction of USARTDIV */ -#define USART_BRR_DIV_FRACTION_MASK 0xF - -/* --- USART_CR1 values ---------------------------------------------------- */ - -/* UE: USART enable */ -#define USART_CR1_UE (1 << 13) - -/* M: Word length */ -#define USART_CR1_M (1 << 12) - -/* WAKE: Wakeup method */ -#define USART_CR1_WAKE (1 << 11) - -/* PCE: Parity control enable */ -#define USART_CR1_PCE (1 << 10) - -/* PS: Parity selection */ -#define USART_CR1_PS (1 << 9) - -/* PEIE: PE interrupt enable */ -#define USART_CR1_PEIE (1 << 8) - -/* TXEIE: TXE interrupt enable */ -#define USART_CR1_TXEIE (1 << 7) - -/* TCIE: Transmission complete interrupt enable */ -#define USART_CR1_TCIE (1 << 6) - -/* RXNEIE: RXNE interrupt enable */ -#define USART_CR1_RXNEIE (1 << 5) - -/* IDLEIE: IDLE interrupt enable */ -#define USART_CR1_IDLEIE (1 << 4) - -/* TE: Transmitter enable */ -#define USART_CR1_TE (1 << 3) - -/* RE: Receiver enable */ -#define USART_CR1_RE (1 << 2) - -/* RWU: Receiver wakeup */ -#define USART_CR1_RWU (1 << 1) - -/* SBK: Send break */ -#define USART_CR1_SBK (1 << 0) - -/* --- USART_CR2 values ---------------------------------------------------- */ - -/* LINEN: LIN mode enable */ -#define USART_CR2_LINEN (1 << 14) - -/* STOP[13:12]: STOP bits */ -#define USART_CR2_STOPBITS_1 (0x00 << 12) /* 1 stop bit */ -#define USART_CR2_STOPBITS_0_5 (0x01 << 12) /* 0.5 stop bits */ -#define USART_CR2_STOPBITS_2 (0x02 << 12) /* 2 stop bits */ -#define USART_CR2_STOPBITS_1_5 (0x03 << 12) /* 1.5 stop bits */ -#define USART_CR2_STOPBITS_MASK (0x03 << 12) -#define USART_CR2_STOPBITS_SHIFT 12 - -/* CLKEN: Clock enable */ -#define USART_CR2_CLKEN (1 << 11) - -/* CPOL: Clock polarity */ -#define USART_CR2_CPOL (1 << 10) - -/* CPHA: Clock phase */ -#define USART_CR2_CPHA (1 << 9) - -/* LBCL: Last bit clock pulse */ -#define USART_CR2_LBCL (1 << 8) - -/* LBDIE: LIN break detection interrupt enable */ -#define USART_CR2_LBDIE (1 << 6) - -/* LBDL: LIN break detection length */ -#define USART_CR2_LBDL (1 << 5) - -/* ADD[3:0]: Addres of the usart node */ -#define USART_CR2_ADD_MASK 0xF - -/* --- USART_CR3 values ---------------------------------------------------- */ - -/* CTSIE: CTS interrupt enable */ -/* Note: N/A on UART4 & UART5 */ -#define USART_CR3_CTSIE (1 << 10) - -/* CTSE: CTS enable */ -/* Note: N/A on UART4 & UART5 */ -#define USART_CR3_CTSE (1 << 9) - -/* RTSE: RTS enable */ -/* Note: N/A on UART4 & UART5 */ -#define USART_CR3_RTSE (1 << 8) - -/* DMAT: DMA enable transmitter */ -/* Note: N/A on UART5 */ -#define USART_CR3_DMAT (1 << 7) - -/* DMAR: DMA enable receiver */ -/* Note: N/A on UART5 */ -#define USART_CR3_DMAR (1 << 6) - -/* SCEN: Smartcard mode enable */ -/* Note: N/A on UART4 & UART5 */ -#define USART_CR3_SCEN (1 << 5) - -/* NACK: Smartcard NACK enable */ -/* Note: N/A on UART4 & UART5 */ -#define USART_CR3_NACK (1 << 4) - -/* HDSEL: Half-duplex selection */ -#define USART_CR3_HDSEL (1 << 3) - -/* IRLP: IrDA low-power */ -#define USART_CR3_IRLP (1 << 2) - -/* IREN: IrDA mode enable */ -#define USART_CR3_IREN (1 << 1) - -/* EIE: Error interrupt enable */ -#define USART_CR3_EIE (1 << 0) - -/* --- USART_GTPR values --------------------------------------------------- */ - -/* GT[7:0]: Guard time value */ -/* Note: N/A on UART4 & UART5 */ -#define USART_GTPR_GT_MASK (0xFF << 8) - -/* PSC[7:0]: Prescaler value */ -/* Note: N/A on UART4/5 */ -#define USART_GTPR_PSC_MASK 0xFF - -/* TODO */ /* Note to Uwe: what needs to be done here? */ - -/* --- Convenience defines ------------------------------------------------- */ - -/* CR1_PCE / CR1_PS combined values */ -#define USART_PARITY_NONE 0x00 -#define USART_PARITY_ODD USART_CR1_PS -#define USART_PARITY_EVEN (USART_CR1_PS | USART_CR1_PCE) -#define USART_PARITY_MASK (USART_CR1_PS | USART_CR1_PCE) - -/* CR1_TE/CR1_RE combined values */ -#define USART_MODE_RX USART_CR1_RE -#define USART_MODE_TX USART_CR1_TE -#define USART_MODE_TX_RX (USART_CR1_RE | USART_CR1_TE) -#define USART_MODE_MASK (USART_CR1_RE | USART_CR1_TE) - -#define USART_STOPBITS_1 USART_CR2_STOPBITS_1 /* 1 stop bit */ -#define USART_STOPBITS_0_5 USART_CR2_STOPBITS_0_5 /* 0.5 stop bits */ -#define USART_STOPBITS_2 USART_CR2_STOPBITS_2 /* 2 stop bits */ -#define USART_STOPBITS_1_5 USART_CR2_STOPBITS_1_5 /* 1.5 stop bits */ - -/* CR3_CTSE/CR3_RTSE combined values */ -#define USART_FLOWCONTROL_NONE 0x00 -#define USART_FLOWCONTROL_RTS USART_CR3_RTSE -#define USART_FLOWCONTROL_CTS USART_CR3_CTSE -#define USART_FLOWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) -#define USART_FLOWCONTROL_MASK (USART_CR3_RTSE | USART_CR3_CTSE) - -/* --- Function prototypes ------------------------------------------------- */ - -void usart_set_baudrate(u32 usart, u32 baud); -void usart_set_databits(u32 usart, u32 bits); -void usart_set_stopbits(u32 usart, u32 stopbits); -void usart_set_parity(u32 usart, u32 parity); -void usart_set_mode(u32 usart, u32 mode); -void usart_set_flow_control(u32 usart, u32 flowcontrol); -void usart_enable(u32 usart); -void usart_disable(u32 usart); -void usart_send(u32 usart, u16 data); -u16 usart_recv(u32 usart); -void usart_wait_send_ready(u32 usart); -void usart_wait_recv_ready(u32 usart); -void usart_send_blocking(u32 usart, u16 data); -u16 usart_recv_blocking(u32 usart); - -#endif diff --git a/include/libopencm3/stm32_common/wwdg.h b/include/libopencm3/stm32_common/wwdg.h deleted file mode 100644 index e1787c8..0000000 --- a/include/libopencm3/stm32_common/wwdg.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_WWDG_H -#define LIBOPENCM3_WWDG_H - -#include -#include - -/* --- WWDG registers ------------------------------------------------------ */ - -/* Control register (WWDG_CR) */ -#define WWDG_CR MMIO32(WWDG_BASE + 0x00) - -/* Configuration register (WWDG_CFR) */ -#define WWDG_CFR MMIO32(WWDG_BASE + 0x04) - -/* Status register (WWDG_SR) */ -#define WWDG_SR MMIO32(WWDG_BASE + 0x08) - -/* --- WWDG_CR values ------------------------------------------------------ */ - -/* WDGA: Activation bit */ -#define WWDG_CR_WDGA (1 << 7) - -/* T[6:0]: 7-bit counter (MSB to LSB) */ -#define WWDG_CR_T_LSB 0 -#define WWDG_CR_T0 (1 << 0) -#define WWDG_CR_T1 (1 << 1) -#define WWDG_CR_T2 (1 << 2) -#define WWDG_CR_T3 (1 << 3) -#define WWDG_CR_T4 (1 << 4) -#define WWDG_CR_T5 (1 << 5) -#define WWDG_CR_T6 (1 << 6) - -/* --- WWDG_CFR values ----------------------------------------------------- */ - -/* EWI: Early wakeup interrupt */ -#define WWDG_CFR_EWI (1 << 9) - -/* WDGTB[8:7]: Timer base */ -#define WWDG_CFR_WDGTB_LSB 7 -#define WWDG_CFR_WDGTB_CK_DIV1 0x0 -#define WWDG_CFR_WDGTB_CK_DIV2 0x1 -#define WWDG_CFR_WDGTB_CK_DIV4 0x2 -#define WWDG_CFR_WDGTB_CK_DIV8 0x3 - -/* W[6:0]: 7-bit window value */ -#define WWDG_CFG_W_LSB 0 - -/* --- WWDG_SR values ------------------------------------------------------ */ - -/* EWIF: Early wakeup interrupt flag */ -#define WWDG_SR_EWIF (1 << 0) - -/* --- WWDG funtion prototypes---------------------------------------------- */ - -#endif diff --git a/include/libopencm3/stm32f1/adc.h b/include/libopencm3/stm32f1/adc.h deleted file mode 100644 index 6e35d59..0000000 --- a/include/libopencm3/stm32f1/adc.h +++ /dev/null @@ -1,418 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Edward Cheeseman - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_ADC_H -#define LIBOPENCM3_ADC_H - -#include -#include - -/* --- Convenience macros -------------------------------------------------- */ - -/* ADC port base addresses (for convenience) */ -#define ADC1 ADC1_BASE -#define ADC2 ADC2_BASE -#define ADC3 ADC3_BASE - -/* --- ADC registers ------------------------------------------------------- */ - -/* ADC status register (ADC_SR) */ -#define ADC_SR(block) MMIO32(block + 0x00) -#define ADC1_SR ADC_SR(ADC1) -#define ADC2_SR ADC_SR(ADC2) -#define ADC3_SR ADC_SR(ADC3) - -/* ADC control register 1 (ADC_CR1) */ -#define ADC_CR1(block) MMIO32(block + 0x04) -#define ADC1_CR1 ADC_CR1(ADC1) -#define ADC2_CR1 ADC_CR1(ADC2) -#define ADC3_CR1 ADC_CR1(ADC3) - -/* ADC control register 2 (ADC_CR2) */ -#define ADC_CR2(block) MMIO32(block + 0x08) -#define ADC1_CR2 ADC_CR2(ADC1) -#define ADC2_CR2 ADC_CR2(ADC2) -#define ADC3_CR2 ADC_CR2(ADC3) - -/* ADC sample time register 1 (ADC_SMPR1) */ -#define ADC_SMPR1(block) MMIO32(block + 0x0c) -#define ADC1_SMPR1 ADC_SMPR1(ADC1) -#define ADC2_SMPR1 ADC_SMPR1(ADC2) -#define ADC3_SMPR1 ADC_SMPR1(ADC3) - -/* ADC sample time register 2 (ADC_SMPR2) */ -#define ADC_SMPR2(block) MMIO32(block + 0x10) -#define ADC1_SMPR2 ADC_SMPR2(ADC1) -#define ADC2_SMPR2 ADC_SMPR2(ADC2) -#define ADC3_SMPR2 ADC_SMPR2(ADC3) - -/* ADC injected channel data offset register x (ADC_JOFRx) (x=1..4) */ -#define ADC_JOFR1(block) MMIO32(block + 0x14) -#define ADC_JOFR2(block) MMIO32(block + 0x18) -#define ADC_JOFR3(block) MMIO32(block + 0x1c) -#define ADC_JOFR4(block) MMIO32(block + 0x20) -#define ADC1_JOFR1 ADC_JOFR1(ADC1) -#define ADC2_JOFR1 ADC_JOFR1(ADC2) -#define ADC3_JOFR1 ADC_JOFR1(ADC3) -#define ADC1_JOFR2 ADC_JOFR2(ADC1) -#define ADC2_JOFR2 ADC_JOFR2(ADC2) -#define ADC3_JOFR2 ADC_JOFR2(ADC3) -#define ADC1_JOFR3 ADC_JOFR3(ADC1) -#define ADC2_JOFR3 ADC_JOFR3(ADC2) -#define ADC3_JOFR3 ADC_JOFR3(ADC3) -#define ADC1_JOFR4 ADC_JOFR4(ADC1) -#define ADC2_JOFR4 ADC_JOFR4(ADC2) -#define ADC3_JOFR4 ADC_JOFR4(ADC3) - -/* ADC watchdog high threshold register (ADC_HTR) */ -#define ADC_HTR(block) MMIO32(block + 0x24) -#define ADC1_HTR ADC_HTR(ADC1) -#define ADC2_HTR ADC_HTR(ADC2) -#define ADC3_HTR ADC_HTR(ADC3) - -/* ADC watchdog low threshold register (ADC_LTR) */ -#define ADC_LTR(block) MMIO32(block + 0x28) -#define ADC1_LTR ADC_LTR(ADC1_BASE) -#define ADC2_LTR ADC_LTR(ADC2_BASE) -#define ADC3_LTR ADC_LTR(ADC3_BASE) - -/* ADC regular sequence register 1 (ADC_SQR1) */ -#define ADC_SQR1(block) MMIO32(block + 0x2c) -#define ADC1_SQR1 ADC_SQR1(ADC1) -#define ADC2_SQR1 ADC_SQR1(ADC2) -#define ADC3_SQR1 ADC_SQR1(ADC3) - -/* ADC regular sequence register 2 (ADC_SQR2) */ -#define ADC_SQR2(block) MMIO32(block + 0x30) -#define ADC1_SQR2 ADC_SQR2(ADC1) -#define ADC2_SQR2 ADC_SQR2(ADC2) -#define ADC3_SQR2 ADC_SQR2(ADC3) - -/* ADC regular sequence register 3 (ADC_SQR3) */ -#define ADC_SQR3(block) MMIO32(block + 0x34) -#define ADC1_SQR3 ADC_SQR3(ADC1) -#define ADC2_SQR3 ADC_SQR3(ADC2) -#define ADC3_SQR3 ADC_SQR3(ADC3) - -/* ADC injected sequence register (ADC_JSQR) */ -#define ADC_JSQR(block) MMIO32(block + 0x38) -#define ADC1_JSQR ADC_JSQR(ADC1_BASE) -#define ADC2_JSQR ADC_JSQR(ADC2_BASE) -#define ADC3_JSQR ADC_JSQR(ADC3_BASE) - -/* ADC injected data register x (ADC_JDRx) (x=1..4) */ -#define ADC_JDR1(block) MMIO32(block + 0x3c) -#define ADC_JDR2(block) MMIO32(block + 0x40) -#define ADC_JDR3(block) MMIO32(block + 0x44) -#define ADC_JDR4(block) MMIO32(block + 0x48) -#define ADC1_JDR1 ADC_JDR1(ADC1) -#define ADC2_JDR1 ADC_JDR1(ADC2) -#define ADC3_JDR1 ADC_JDR1(ADC3) -#define ADC1_JDR2 ADC_JDR2(ADC1) -#define ADC2_JDR2 ADC_JDR2(ADC2) -#define ADC3_JDR2 ADC_JDR2(ADC3) -#define ADC1_JDR3 ADC_JDR3(ADC1) -#define ADC2_JDR3 ADC_JDR3(ADC2) -#define ADC3_JDR3 ADC_JDR3(ADC3) -#define ADC1_JDR4 ADC_JDR4(ADC1) -#define ADC2_JDR4 ADC_JDR4(ADC2) -#define ADC3_JDR4 ADC_JDR4(ADC3) - -/* ADC regular data register (ADC_DR) */ -#define ADC_DR(block) MMIO32(block + 0x4c) -#define ADC1_DR ADC_DR(ADC1) -#define ADC2_DR ADC_DR(ADC2) -#define ADC3_DR ADC_DR(ADC3) - -/* --- ADC_SR values ------------------------------------------------------- */ - -#define ADC_SR_STRT (1 << 4) -#define ADC_SR_JSTRT (1 << 3) -#define ADC_SR_JEOC (1 << 2) -#define ADC_SR_EOC (1 << 1) -#define ADC_SR_AWD (1 << 0) - -/* --- ADC_CR1 values ------------------------------------------------------ */ - -#define ADC_CR1_AWDEN (1 << 23) -#define ADC_CR1_JAWDEN (1 << 22) -#define ADC_CR1_DUALMOD_LSB 16 -#define ADC_CR1_DUALMOD_MSK (0xf << ADC_DUALMOD_LSB) /* ADC1 only */ -#define ADC_CR1_DISCNUM_LSB 13 -#define ADC_CR1_DISCNUM_MSK (0x7 << ADC_DISCNUM_LSB) -#define ADC_CR1_JDISCEN (1 << 12) -#define ADC_CR1_DISCEN (1 << 11) -#define ADC_CR1_JAUTO (1 << 10) -#define ADC_CR1_AWDSGL (1 << 9) -#define ADC_CR1_SCAN (1 << 8) -#define ADC_CR1_JEOCIE (1 << 7) -#define ADC_CR1_AWDIE (1 << 6) -#define ADC_CR1_EOCIE (1 << 5) -#define ADC_CR1_AWDCH_LSB 0 -#define ADC_CR1_AWDCH_MSK (0x1f << ADC_AWDCH_LSB) - -/* --- ADC_CR2 values ------------------------------------------------------ */ - -#define ADC_CR2_TSVREFE (1 << 23) /* ADC1 only! */ -#define ADC_CR2_SWSTART (1 << 22) -#define ADC_CR2_JSWSTART (1 << 21) -#define ADC_CR2_EXTTRIG (1 << 20) -#define ADC_CR2_EXTSEL_LSB 17 -#define ADC_CR2_EXTSEL_MSK (0x7 << ADC_EXTSEL_LSB) -/* The following are only valid for ADC1 and ADC2. */ -#define ADC_CR2_EXTSEL_TIM1_CC1 0x0 -#define ADC_CR2_EXTSEL_TIM1_CC2 0x1 -#define ADC_CR2_EXTSEL_TIM1_CC3 0x2 -#define ADC_CR2_EXTSEL_TIM2_CC2 0x3 -#define ADC_CR2_EXTSEL_TIM3_TRGO 0x4 -#define ADC_CR2_EXTSEL_TIM4_CC4 0x5 -#define ADC_CR2_EXTSEL_EXTI11 0x6 -#define ADC_CR2_EXTSEL_SWSTART 0x7 - -/* The following are only valid for ADC3 */ -#define ADC_CR2_EXTSEL_TIM3_CC1 0x0 -#define ADC_CR2_EXTSEL_TIM2_CC3 0x1 -#define ADC_CR2_EXTSEL_TIM8_CC1 0x3 -#define ADC_CR2_EXTSEL_TIM8_TRGO 0x4 -#define ADC_CR2_EXTSEL_TIM5_CC1 0x5 -#define ADC_CR2_EXTSEL_TIM5_CC3 0x6 - -/* Bit 16: reserved, must be kept cleared */ -#define ADC_CR2_JEXTTRIG (1 << 15) -#define ADC_CR2_JEXTSEL_LSB 12 -#define ADC_CR2_JEXTSEL_MSK (0x7 << ADC_JEXTSEL_LSB) -/* The following are only valid for ADC1 and ADC2. */ -#define ADC_CR2_JEXTSEL_TIM1_TRGO 0x0 -#define ADC_CR2_JEXTSEL_TIM1_CC4 0x1 -#define ADC_CR2_JEXTSEL_TIM2_TRGO 0x2 -#define ADC_CR2_JEXTSEL_TIM2_CC1 0x3 -#define ADC_CR2_JEXTSEL_TIM3_CC4 0x4 -#define ADC_CR2_JEXTSEL_TIM4_TRGO 0x5 -#define ADC_CR2_JEXTSEL_EXTI15 0x6 -#define ADC_CR2_JEXTSEL_JSWSTART 0x7 - -/* The following are the different meanings for ADC3 only. */ -#define ADC_CR2_JEXTSEL_TIM4_CC3 0x2 -#define ADC_CR2_JEXTSEL_TIM8_CC2 0x3 -#define ADC_CR2_JEXTSEL_TIM8_CC4 0x4 -#define ADC_CR2_JEXTSEL_TIM5_TRGO 0x5 -#define ADC_CR2_JEXTSEL_TIM5_CC4 0x6 - -#define ADC_CR2_ALIGN (1 << 11) -#define ADC_CR2_DMA (1 << 8) /* ADC 1 & 3 only! */ -/* Bits [7:4] have to be kept 0. */ -#define ADC_CR2_RSTCAL (1 << 3) -#define ADC_CR2_CAL (1 << 2) -#define ADC_CR2_CONT (1 << 1) -#define ADC_CR2_ADON (1 << 0) /* Must be separately written. */ - -/* --- ADC_SMPR1 values ---------------------------------------------------- */ - -#define ADC_SMPR1_SMP17_LSB 21 -#define ADC_SMPR1_SMP16_LSB 18 -#define ADC_SMPR1_SMP15_LSB 15 -#define ADC_SMPR1_SMP14_LSB 12 -#define ADC_SMPR1_SMP13_LSB 9 -#define ADC_SMPR1_SMP12_LSB 6 -#define ADC_SMPR1_SMP11_LSB 3 -#define ADC_SMPR1_SMP10_LSB 0 -#define ADC_SMPR1_SMP17_MSK (0x7 << ADC_SMP17_LSB) -#define ADC_SMPR1_SMP16_MSK (0x7 << ADC_SMP16_LSB) -#define ADC_SMPR1_SMP15_MSK (0x7 << ADC_SMP15_LSB) -#define ADC_SMPR1_SMP14_MSK (0x7 << ADC_SMP14_LSB) -#define ADC_SMPR1_SMP13_MSK (0x7 << ADC_SMP13_LSB) -#define ADC_SMPR1_SMP12_MSK (0x7 << ADC_SMP12_LSB) -#define ADC_SMPR1_SMP11_MSK (0x7 << ADC_SMP11_LSB) -#define ADC_SMPR1_SMP10_MSK (0x7 << ADC_SMP10_LSB) -#define ADC_SMPR1_SMP_1DOT5CYC 0x0 -#define ADC_SMPR1_SMP_7DOT5CYC 0x1 -#define ADC_SMPR1_SMP_13DOT5CYC 0x2 -#define ADC_SMPR1_SMP_28DOT5CYC 0x3 -#define ADC_SMPR1_SMP_41DOT5CYC 0x4 -#define ADC_SMPR1_SMP_55DOT5CYC 0x5 -#define ADC_SMPR1_SMP_71DOT5CYC 0x6 -#define ADC_SMPR1_SMP_239DOT5CYC 0x7 - -/* --- ADC_SMPR2 values ---------------------------------------------------- */ - -#define ADC_SMPR2_SMP9_LSB 27 -#define ADC_SMPR2_SMP8_LSB 24 -#define ADC_SMPR2_SMP7_LSB 21 -#define ADC_SMPR2_SMP6_LSB 18 -#define ADC_SMPR2_SMP5_LSB 15 -#define ADC_SMPR2_SMP4_LSB 12 -#define ADC_SMPR2_SMP3_LSB 9 -#define ADC_SMPR2_SMP2_LSB 6 -#define ADC_SMPR2_SMP1_LSB 3 -#define ADC_SMPR2_SMP0_LSB 0 -#define ADC_SMPR2_SMP9_MSK (0x7 << ADC_SMP9_LSB) -#define ADC_SMPR2_SMP8_MSK (0x7 << ADC_SMP8_LSB) -#define ADC_SMPR2_SMP7_MSK (0x7 << ADC_SMP7_LSB) -#define ADC_SMPR2_SMP6_MSK (0x7 << ADC_SMP6_LSB) -#define ADC_SMPR2_SMP5_MSK (0x7 << ADC_SMP5_LSB) -#define ADC_SMPR2_SMP4_MSK (0x7 << ADC_SMP4_LSB) -#define ADC_SMPR2_SMP3_MSK (0x7 << ADC_SMP3_LSB) -#define ADC_SMPR2_SMP2_MSK (0x7 << ADC_SMP2_LSB) -#define ADC_SMPR2_SMP1_MSK (0x7 << ADC_SMP1_LSB) -#define ADC_SMPR2_SMP0_MSK (0x7 << ADC_SMP0_LSB) -#define ADC_SMPR2_SMP_1DOT5CYC 0x0 -#define ADC_SMPR2_SMP_7DOT5CYC 0x1 -#define ADC_SMPR2_SMP_13DOT5CYC 0x2 -#define ADC_SMPR2_SMP_28DOT5CYC 0x3 -#define ADC_SMPR2_SMP_41DOT5CYC 0x4 -#define ADC_SMPR2_SMP_55DOT5CYC 0x5 -#define ADC_SMPR2_SMP_71DOT5CYC 0x6 -#define ADC_SMPR2_SMP_239DOT5CYC 0x7 - -/* --- ADC_SMPRx generic values -------------------------------------------- */ - -#define ADC_SMPR_SMP_1DOT5CYC 0x0 -#define ADC_SMPR_SMP_7DOT5CYC 0x1 -#define ADC_SMPR_SMP_13DOT5CYC 0x2 -#define ADC_SMPR_SMP_28DOT5CYC 0x3 -#define ADC_SMPR_SMP_41DOT5CYC 0x4 -#define ADC_SMPR_SMP_55DOT5CYC 0x5 -#define ADC_SMPR_SMP_71DOT5CYC 0x6 -#define ADC_SMPR_SMP_239DOT5CYC 0x7 - -/* --- ADC_JOFRx, ADC_HTR, ADC_LTR values ---------------------------------- */ - -#define ADC_JOFFSET_LSB 0 -#define ADC_JOFFSET_MSK (0x7ff << 0) -#define ADC_HT_LSB 0 -#define ADC_HT_MSK (0x7ff << 0) -#define ADC_LT_LSB 0 -#define ADC_LT_MSK (0x7ff << 0) - -/* --- ADC_SQR1 values ----------------------------------------------------- */ - -#define ADC_SQR1_L_LSB 20 -#define ADC_SQR1_SQ16_LSB 15 -#define ADC_SQR1_SQ15_LSB 10 -#define ADC_SQR1_SQ14_LSB 5 -#define ADC_SQR1_SQ13_LSB 0 -#define ADC_SQR1_L_MSK (0xf << ADC_L_LSB) -#define ADC_SQR1_SQ16_MSK (0x1f << ADC_SQ16_LSB) -#define ADC_SQR1_SQ15_MSK (0x1f << ADC_SQ15_LSB) -#define ADC_SQR1_SQ14_MSK (0x1f << ADC_SQ14_LSB) -#define ADC_SQR1_SQ13_MSK (0x1f << ADC_SQ13_LSB) - -/* --- ADC_SQR2 values ----------------------------------------------------- */ - -#define ADC_SQR2_SQ12_LSB 25 -#define ADC_SQR2_SQ11_LSB 20 -#define ADC_SQR2_SQ10_LSB 15 -#define ADC_SQR2_SQ9_LSB 10 -#define ADC_SQR2_SQ8_LSB 5 -#define ADC_SQR2_SQ7_LSB 0 -#define ADC_SQR2_SQ12_MSK (0x1f << ADC_SQ12_LSB) -#define ADC_SQR2_SQ11_MSK (0x1f << ADC_SQ11_LSB) -#define ADC_SQR2_SQ10_MSK (0x1f << ADC_SQ10_LSB) -#define ADC_SQR2_SQ9_MSK (0x1f << ADC_SQ9_LSB) -#define ADC_SQR2_SQ8_MSK (0x1f << ADC_SQ8_LSB) -#define ADC_SQR2_SQ7_MSK (0x1f << ADC_SQ7_LSB) - -/* --- ADC_SQR3 values ----------------------------------------------------- */ - -#define ADC_SQR3_SQ6_LSB 25 -#define ADC_SQR3_SQ5_LSB 20 -#define ADC_SQR3_SQ4_LSB 15 -#define ADC_SQR3_SQ3_LSB 10 -#define ADC_SQR3_SQ2_LSB 5 -#define ADC_SQR3_SQ1_LSB 0 -#define ADC_SQR3_SQ6_MSK (0x1f << ADC_SQ6_LSB) -#define ADC_SQR3_SQ5_MSK (0x1f << ADC_SQ5_LSB) -#define ADC_SQR3_SQ4_MSK (0x1f << ADC_SQ4_LSB) -#define ADC_SQR3_SQ3_MSK (0x1f << ADC_SQ3_LSB) -#define ADC_SQR3_SQ2_MSK (0x1f << ADC_SQ2_LSB) -#define ADC_SQR3_SQ1_MSK (0x1f << ADC_SQ1_LSB) - -/* --- ADC_JSQR values ----------------------------------------------------- */ - -#define ADC_JSQR_JL_LSB 20 -#define ADC_JSQR_JSQ4_LSB 15 -#define ADC_JSQR_JSQ3_LSB 10 -#define ADC_JSQR_JSQ2_LSB 5 -#define ADC_JSQR_JSQ1_LSB 0 -#define ADC_JSQR_JL_MSK (0x2 << ADC_JL_LSB) -#define ADC_JSQR_JSQ4_MSK (0x1f << ADC_JSQ4_LSB) -#define ADC_JSQR_JSQ3_MSK (0x1f << ADC_JSQ3_LSB) -#define ADC_JSQR_JSQ2_MSK (0x1f << ADC_JSQ2_LSB) -#define ADC_JSQR_JSQ1_MSK (0x1f << ADC_JSQ1_LSB) - -/* --- ADC_JDRx, ADC_DR values --------------------------------------------- */ - -#define ADC_JDATA_LSB 0 -#define ADC_DATA_LSB 0 -#define ADC_ADC2DATA_LSB 16 /* ADC1 only (dual mode) */ -#define ADC_JDATA_MSK (0xffff << ADC_JDATA_LSB) -#define ADC_DATA_MSK (0xffff << ADC_DA) -#define ADC_ADC2DATA_MSK (0xffff << ADC_ADC2DATA_LSB) - /* ADC1 only (dual mode) */ - -/* --- Function prototypes ------------------------------------------------- */ - - -/* TODO */ -void adc_enable_analog_watchdog_regular(u32 adc); -void adc_disable_analog_watchdog_regular(u32 adc); -void adc_enable_analog_watchdog_injected(u32 adc); -void adc_disable_analog_watchdog_injected(u32 adc); -void adc_enable_discontinous_mode_regular(u32 adc); -void adc_disable_discontinous_mode_regular(u32 adc); -void adc_enable_discontinous_mode_injected(u32 adc); -void adc_disable_discontinous_mode_injected(u32 adc); -void adc_enable_automatic_injected_group_conversion(u32 adc); -void adc_disable_automatic_injected_group_conversion(u32 adc); -void adc_enable_analog_watchdog_on_all_channels(u32 adc); -void adc_enable_analog_watchdog_on_selected_channel(u32 adc, u8 channel); -void adc_enable_scan_mode(u32 adc); -void adc_disable_scan_mode(u32 adc); -void adc_enable_jeoc_interrupt(u32 adc); -void adc_disable_jeoc_interrupt(u32 adc); -void adc_enable_awd_interrupt(u32 adc); -void adc_disable_awd_interrupt(u32 adc); -void adc_enable_eoc_interrupt(u32 adc); -void adc_disable_eoc_interrupt(u32 adc); -void adc_enable_temperature_sensor(u32 adc); -void adc_disable_temperature_sensor(u32 adc); -void adc_start_conversion_regular(u32 adc); -void adc_start_conversion_injected(u32 adc); -void adc_enable_external_trigger_regular(u32 adc, u8 trigger); -void adc_disable_external_trigger_regular(u32 adc); -void adc_enable_external_trigger_injected(u32 adc, u8 trigger); -void adc_disable_external_trigger_injected(u32 adc); -void adc_set_left_aligned(u32 adc); -void adc_set_right_aligned(u32 adc); -void adc_enable_dma(u32 adc); -void adc_disable_dma(u32 adc); -void adc_reset_calibration(u32 adc); -void adc_calibration(u32 adc); -void adc_set_continous_conversion_mode(u32 adc); -void adc_set_single_conversion_mode(u32 adc); -void adc_on(u32 adc); -void adc_off(u32 adc); -void adc_set_conversion_time(u32 adc, u8 channel, u8 time); -void adc_set_conversion_time_on_all_channels(u32 adc, u8 time); -void adc_set_watchdog_high_threshold(u32 adc, u16 threshold); -void adc_set_watchdog_low_threshold(u32 adc, u16 threshold); -void adc_set_regular_sequence(u32 adc, u8 length, u8 channel[]); -void adc_set_injected_sequence(u32 adc, u8 length, u8 channel[]); - -#endif diff --git a/include/libopencm3/stm32f1/bkp.h b/include/libopencm3/stm32f1/bkp.h deleted file mode 100644 index d700f9b..0000000 --- a/include/libopencm3/stm32f1/bkp.h +++ /dev/null @@ -1,208 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_BKP_H -#define LIBOPENCM3_BKP_H - -#include -#include - -/* --- BKP registers ------------------------------------------------------- */ - -/* Backup data register 1 (BKP_DR1) */ -#define BKP_DR1 MMIO32(BACKUP_REGS_BASE + 0x04) - -/* Backup data register 2 (BKP_DR2) */ -#define BKP_DR2 MMIO32(BACKUP_REGS_BASE + 0x08) - -/* Backup data register 3 (BKP_DR3) */ -#define BKP_DR3 MMIO32(BACKUP_REGS_BASE + 0x0C) - -/* Backup data register 4 (BKP_DR4) */ -#define BKP_DR4 MMIO32(BACKUP_REGS_BASE + 0x10) - -/* Backup data register 5 (BKP_DR5) */ -#define BKP_DR5 MMIO32(BACKUP_REGS_BASE + 0x14) - -/* Backup data register 6 (BKP_DR6) */ -#define BKP_DR6 MMIO32(BACKUP_REGS_BASE + 0x18) - -/* Backup data register 7 (BKP_DR7) */ -#define BKP_DR7 MMIO32(BACKUP_REGS_BASE + 0x1C) - -/* Backup data register 8 (BKP_DR8) */ -#define BKP_DR8 MMIO32(BACKUP_REGS_BASE + 0x20) - -/* Backup data register 9 (BKP_DR9) */ -#define BKP_DR9 MMIO32(BACKUP_REGS_BASE + 0x24) - -/* Backup data register 10 (BKP_DR10) */ -#define BKP_DR10 MMIO32(BACKUP_REGS_BASE + 0x28) - -/* RTC clock calibration register (BKP_RTCCR) */ -#define BKP_RTCCR MMIO32(BACKUP_REGS_BASE + 0x2C) - -/* Backup control register (BKP_CR) */ -#define BKP_CR MMIO32(BACKUP_REGS_BASE + 0x30) - -/* Backup control/status register (BKP_CSR) */ -#define BKP_CSR MMIO32(BACKUP_REGS_BASE + 0x34) - -/* Backup data register 11 (BKP_DR11) */ -#define BKP_DR11 MMIO32(BACKUP_REGS_BASE + 0x40) - -/* Backup data register 12 (BKP_DR12) */ -#define BKP_DR12 MMIO32(BACKUP_REGS_BASE + 0x44) - -/* Backup data register 13 (BKP_DR13) */ -#define BKP_DR13 MMIO32(BACKUP_REGS_BASE + 0x48) - -/* Backup data register 14 (BKP_DR14) */ -#define BKP_DR14 MMIO32(BACKUP_REGS_BASE + 0x4C) - -/* Backup data register 15 (BKP_DR15) */ -#define BKP_DR15 MMIO32(BACKUP_REGS_BASE + 0x50) - -/* Backup data register 16 (BKP_DR16) */ -#define BKP_DR16 MMIO32(BACKUP_REGS_BASE + 0x54) - -/* Backup data register 17 (BKP_DR17) */ -#define BKP_DR17 MMIO32(BACKUP_REGS_BASE + 0x58) - -/* Backup data register 18 (BKP_DR18) */ -#define BKP_DR18 MMIO32(BACKUP_REGS_BASE + 0x5C) - -/* Backup data register 19 (BKP_DR19) */ -#define BKP_DR19 MMIO32(BACKUP_REGS_BASE + 0x60) - -/* Backup data register 20 (BKP_DR20) */ -#define BKP_DR20 MMIO32(BACKUP_REGS_BASE + 0x64) - -/* Backup data register 21 (BKP_DR21) */ -#define BKP_DR21 MMIO32(BACKUP_REGS_BASE + 0x68) - -/* Backup data register 22 (BKP_DR22) */ -#define BKP_DR22 MMIO32(BACKUP_REGS_BASE + 0x6C) - -/* Backup data register 23 (BKP_DR23) */ -#define BKP_DR23 MMIO32(BACKUP_REGS_BASE + 0x70) - -/* Backup data register 24 (BKP_DR24) */ -#define BKP_DR24 MMIO32(BACKUP_REGS_BASE + 0x74) - -/* Backup data register 25 (BKP_DR25) */ -#define BKP_DR25 MMIO32(BACKUP_REGS_BASE + 0x78) - -/* Backup data register 26 (BKP_DR26) */ -#define BKP_DR26 MMIO32(BACKUP_REGS_BASE + 0x7C) - -/* Backup data register 27 (BKP_DR27) */ -#define BKP_DR27 MMIO32(BACKUP_REGS_BASE + 0x80) - -/* Backup data register 28 (BKP_DR28) */ -#define BKP_DR28 MMIO32(BACKUP_REGS_BASE + 0x84) - -/* Backup data register 29 (BKP_DR29) */ -#define BKP_DR29 MMIO32(BACKUP_REGS_BASE + 0x88) - -/* Backup data register 30 (BKP_DR30) */ -#define BKP_DR30 MMIO32(BACKUP_REGS_BASE + 0x8C) - -/* Backup data register 31 (BKP_DR31) */ -#define BKP_DR31 MMIO32(BACKUP_REGS_BASE + 0x90) - -/* Backup data register 32 (BKP_DR32) */ -#define BKP_DR32 MMIO32(BACKUP_REGS_BASE + 0x94) - -/* Backup data register 33 (BKP_DR33) */ -#define BKP_DR33 MMIO32(BACKUP_REGS_BASE + 0x98) - -/* Backup data register 34 (BKP_DR34) */ -#define BKP_DR34 MMIO32(BACKUP_REGS_BASE + 0x9C) - -/* Backup data register 35 (BKP_DR35) */ -#define BKP_DR35 MMIO32(BACKUP_REGS_BASE + 0xA0) - -/* Backup data register 36 (BKP_DR36) */ -#define BKP_DR36 MMIO32(BACKUP_REGS_BASE + 0xA4) - -/* Backup data register 37 (BKP_DR37) */ -#define BKP_DR37 MMIO32(BACKUP_REGS_BASE + 0xA8) - -/* Backup data register 38 (BKP_DR38) */ -#define BKP_DR38 MMIO32(BACKUP_REGS_BASE + 0xAC) - -/* Backup data register 39 (BKP_DR39) */ -#define BKP_DR39 MMIO32(BACKUP_REGS_BASE + 0xB0) - -/* Backup data register 40 (BKP_DR40) */ -#define BKP_DR40 MMIO32(BACKUP_REGS_BASE + 0xB4) - -/* Backup data register 41 (BKP_DR41) */ -#define BKP_DR41 MMIO32(BACKUP_REGS_BASE + 0xB8) - -/* Backup data register 42 (BKP_DR42) */ -#define BKP_DR42 MMIO32(BACKUP_REGS_BASE + 0xBC) - -/* --- BKP_RTCCR values ---------------------------------------------------- */ - -/* ASOS: Alarm or second output selection */ -#define BKP_RTCCR_ASOS (1 << 9) - -/* ASOE: Alarm or second output enable */ -#define BKP_RTCCR_ASOE (1 << 8) - -/* CCO: Calibration clock output */ -#define BKP_RTCCR_CCO (1 << 7) - -/* CAL[6:0]: Calibration value */ -#define BKP_RTCCR_CAL_LSB 0 - -/* --- BKP_CR values ------------------------------------------------------- */ - -/* TPAL: TAMPER pin active level */ -#define BKP_CR_TAL (1 << 1) - -/* TPE: TAMPER pin enable */ -#define BKP_CR_TPE (1 << 0) - -/* --- BKP_CSR values ------------------------------------------------------ */ - -/* TIF: Tamper interrupt flag */ -#define BKP_CSR_TIF (1 << 9) - -/* TEF: Tamper event flag */ -#define BKP_CSR_TEF (1 << 8) - -/* TPIE: TAMPER pin interrupt enable */ -#define BKP_CSR_TPIE (1 << 2) - -/* CTI: Clear tamper interrupt */ -#define BKP_CSR_CTI (1 << 1) - -/* CTE: Clear tamper event */ -#define BKP_CSR_CTE (1 << 0) - -/* --- BKP_DRx values ------------------------------------------------------ */ - -/* Bits[15:0]: Backup data */ - -/* --- BKP function prototypes --------------------------------------------- */ - -#endif diff --git a/include/libopencm3/stm32f1/dma.h b/include/libopencm3/stm32f1/dma.h deleted file mode 100644 index 7d0a856..0000000 --- a/include/libopencm3/stm32f1/dma.h +++ /dev/null @@ -1,723 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_DMA_H -#define LIBOPENCM3_DMA_H - -#include -#include - -/* --- Convenience macros -------------------------------------------------- */ - -/* DMA register base adresses (for convenience) */ -#define DMA1 DMA1_BASE -#define DMA2 DMA2_BASE - -/* --- DMA registers ------------------------------------------------------- */ - -/* DMA interrupt status register (DMAx_ISR) */ -#define DMA_ISR(dma_base) MMIO32(dma_base + 0x00) -#define DMA1_ISR DMA_ISR(DMA1) -#define DMA2_ISR DMA_ISR(DMA2) - -/* DMA interrupt flag clear register (DMAx_IFCR) */ -#define DMA_IFCR(dma_base) MMIO32(dma_base + 0x04) -#define DMA1_IFCR DMA_IFCR(DMA1) -#define DMA2_IFCR DMA_IFCR(DMA2) - -/* DMA channel 1 configuration register (DMAx_CCR1) */ -#define DMA_CCR1(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 0) -#define DMA1_CCR1 DMA_CCR1(DMA1) -#define DMA2_CCR1 DMA_CCR1(DMA2) - -/* DMA channel 2 configuration register (DMAx_CCR2) */ -#define DMA_CCR2(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 1) -#define DMA1_CCR2 DMA_CCR2(DMA1) -#define DMA2_CCR2 DMA_CCR2(DMA2) - -/* DMA channel 3 configuration register (DMAx_CCR3) */ -#define DMA_CCR3(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 2) -#define DMA1_CCR3 DMA_CCR3(DMA1) -#define DMA2_CCR3 DMA_CCR3(DMA2) - -/* DMA channel 4 configuration register (DMAx_CCR4) */ -#define DMA_CCR4(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 3) -#define DMA1_CCR4 DMA_CCR4(DMA1) -#define DMA2_CCR4 DMA_CCR4(DMA2) - -/* DMA channel 5 configuration register (DMAx_CCR5) */ -#define DMA_CCR5(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 4) -#define DMA1_CCR5 DMA_CCR5(DMA1) -#define DMA2_CCR5 DMA_CCR5(DMA2) - -/* DMA channel 6 configuration register (DMAx_CCR6) */ -#define DMA_CCR6(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 5) -#define DMA1_CCR6 DMA_CCR6(DMA1) - -/* DMA channel 7 configuration register (DMAx_CCR7) */ -#define DMA_CCR7(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 6) -#define DMA1_CCR7 DMA_CCR7(DMA1) - -/* DMA channel 1 number of data register (DMAx_CNDTR1) */ -#define DMA_CNDTR1(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 0) -#define DMA1_CNDTR1 DMA_CNDTR1(DMA1) -#define DMA2_CNDTR1 DMA_CNDTR1(DMA2) - -/* DMA channel 2 number of data register (DMAx_CNDTR2) */ -#define DMA_CNDTR2(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 1) -#define DMA1_CNDTR2 DMA_CNDTR2(DMA1) -#define DMA2_CNDTR2 DMA_CNDTR2(DMA2) - -/* DMA channel 3 number of data register (DMAx_CNDTR3) */ -#define DMA_CNDTR3(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 2) -#define DMA1_CNDTR3 DMA_CNDTR3(DMA1) -#define DMA2_CNDTR3 DMA_CNDTR3(DMA2) - -/* DMA channel 4 number of data register (DMAx_CNDTR4) */ -#define DMA_CNDTR4(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 3) -#define DMA1_CNDTR4 DMA_CNDTR4(DMA1) -#define DMA2_CNDTR4 DMA_CNDTR4(DMA2) - -/* DMA channel 5 number of data register (DMAx_CNDTR5) */ -#define DMA_CNDTR5(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 4) -#define DMA1_CNDTR5 DMA_CNDTR5(DMA1) -#define DMA2_CNDTR5 DMA_CNDTR5(DMA2) - -/* DMA channel 6 number of data register (DMAx_CNDTR6) */ -#define DMA_CNDTR6(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 5) -#define DMA1_CNDTR6 DMA_CNDTR6(DMA1) - -/* DMA channel 7 number of data register (DMAx_CNDTR7) */ -#define DMA_CNDTR7(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 6) -#define DMA1_CNDTR7 DMA_CNDTR7(DMA1) - -/* DMA channel 1 peripheral address register (DMAx_CPAR1) */ -#define DMA_CPAR1(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 0) -#define DMA1_CPAR1 DMA_CPAR1(DMA1) -#define DMA2_CPAR1 DMA_CPAR1(DMA2) - -/* DMA channel 2 peripheral address register (DMAx_CPAR2) */ -#define DMA_CPAR2(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 1) -#define DMA1_CPAR2 DMA_CPAR2(DMA1) -#define DMA2_CPAR2 DMA_CPAR2(DMA2) - -/* DMA channel 3 peripheral address register (DMAx_CPAR3) */ -#define DMA_CPAR3(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 2) -#define DMA1_CPAR3 DMA_CPAR3(DMA1) -#define DMA2_CPAR3 DMA_CPAR3(DMA2) - -/* DMA channel 4 peripheral address register (DMAx_CPAR4) */ -#define DMA_CPAR4(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 3) -#define DMA1_CPAR4 DMA_CPAR4(DMA1) -#define DMA2_CPAR4 DMA_CPAR4(DMA2) - -/* DMA channel 5 peripheral address register (DMAx_CPAR5) */ -#define DMA_CPAR5(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 4) -#define DMA1_CPAR5 DMA_CPAR5(DMA1) -#define DMA2_CPAR5 DMA_CPAR5(DMA2) - -/* DMA channel 6 peripheral address register (DMAx_CPAR6) */ -#define DMA_CPAR6(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 5) -#define DMA1_CPAR6 DMA_CPAR6(DMA1) - -/* DMA channel 7 peripheral address register (DMAx_CPAR7) */ -#define DMA_CPAR7(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 6) -#define DMA1_CPAR7 DMA_CPAR7(DMA1) - -/* DMA channel 1 memory address register (DMAx_CMAR1) */ -#define DMA_CMAR1(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 0) -#define DMA1_CMAR1 DMA_CMAR1(DMA1) -#define DMA2_CMAR1 DMA_CMAR1(DMA2) - -/* DMA channel 2 memory address register (DMAx_CMAR2) */ -#define DMA_CMAR2(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 1) -#define DMA1_CMAR2 DMA_CMAR2(DMA1) -#define DMA2_CMAR2 DMA_CMAR2(DMA2) - -/* DMA channel 3 memory address register (DMAx_CMAR3) */ -#define DMA_CMAR3(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 2) -#define DMA1_CMAR3 DMA_CMAR3(DMA1) -#define DMA2_CMAR3 DMA_CMAR3(DMA2) - -/* DMA channel 4 memory address register (DMAx_CMAR4) */ -#define DMA_CMAR4(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 3) -#define DMA1_CMAR4 DMA_CMAR4(DMA1) -#define DMA2_CMAR4 DMA_CMAR4(DMA2) - -/* DMA channel 5 memory address register (DMAx_CMAR5) */ -#define DMA_CMAR5(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 4) -#define DMA1_CMAR5 DMA_CMAR5(DMA1) -#define DMA2_CMAR5 DMA_CMAR5(DMA2) - -/* DMA channel 6 memory address register (DMAx_CMAR6) */ -#define DMA_CMAR6(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 5) -#define DMA1_CMAR6 DMA_CMAR6(DMA1) - -/* DMA channel 7 memory address register (DMAx_CMAR7) */ -#define DMA_CMAR7(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 6) -#define DMA1_CMAR7 DMA_CMAR7(DMA1) - -/* --- DMA_ISR values ------------------------------------------------------ */ - -/* TEIF7: Channel 7 transfer error flag */ -#define DMA_ISR_TEIF7 (1 << 27) -/* HTIF7: Channel 7 half transfer flag */ -#define DMA_ISR_HTIF7 (1 << 26) -/* TCIF7: Channel 7 transfer complete flag */ -#define DMA_ISR_TCIF7 (1 << 25) -/* GIF7: Channel 7 global interrupt flag */ -#define DMA_ISR_GIF7 (1 << 24) -/* TEIF6: Channel 6 transfer error flag */ -#define DMA_ISR_TEIF6 (1 << 23) -/* HTIF6: Channel 6 half transfer flag */ -#define DMA_ISR_HTIF6 (1 << 22) -/* TCIF6: Channel 6 transfer complete flag */ -#define DMA_ISR_TCIF6 (1 << 21) -/* GIF6: Channel 6 global interrupt flag */ -#define DMA_ISR_GIF6 (1 << 20) -/* TEIF5: Channel 5 transfer error flag */ -#define DMA_ISR_TEIF5 (1 << 19) -/* HTIF5: Channel 5 half transfer flag */ -#define DMA_ISR_HTIF5 (1 << 18) -/* TCIF5: Channel 5 transfer complete flag */ -#define DMA_ISR_TCIF5 (1 << 17) -/* GIF5: Channel 5 global interrupt flag */ -#define DMA_ISR_GIF5 (1 << 16) -/* TEIF4: Channel 4 transfer error flag */ -#define DMA_ISR_TEIF4 (1 << 15) -/* HTIF4: Channel 4 half transfer flag */ -#define DMA_ISR_HTIF4 (1 << 14) -/* TCIF4: Channel 4 transfer complete flag */ -#define DMA_ISR_TCIF4 (1 << 13) -/* GIF4: Channel 4 global interrupt flag */ -#define DMA_ISR_GIF4 (1 << 12) -/* TEIF3: Channel 3 transfer error flag */ -#define DMA_ISR_TEIF3 (1 << 11) -/* HTIF3: Channel 3 half transfer flag */ -#define DMA_ISR_HTIF3 (1 << 10) -/* TCIF3: Channel 3 transfer complete flag */ -#define DMA_ISR_TCIF3 (1 << 9) -/* GIF3: Channel 3 global interrupt flag */ -#define DMA_ISR_GIF3 (1 << 8) -/* TEIF2: Channel 2 transfer error flag */ -#define DMA_ISR_TEIF2 (1 << 7) -/* HTIF2: Channel 23 half transfer flag */ -#define DMA_ISR_HTIF2 (1 << 6) -/* TCIF2: Channel 2 transfer complete flag */ -#define DMA_ISR_TCIF2 (1 << 5) -/* GIF2: Channel 2 global interrupt flag */ -#define DMA_ISR_GIF2 (1 << 4) -/* TEIF1: Channel 1 transfer error flag */ -#define DMA_ISR_TEIF1 (1 << 3) -/* HTIF1: Channel 1 half transfer flag */ -#define DMA_ISR_HTIF1 (1 << 2) -/* TCIF1: Channel 1 transfer complete flag */ -#define DMA_ISR_TCIF1 (1 << 1) -/* GIF1: Channel 1 global interrupt flag */ -#define DMA_ISR_GIF1 (1 << 0) - -/* --- DMA_IFCR values ----------------------------------------------------- */ - -/* CTEIF7: Channel 7 transfer error clear */ -#define DMA_IFCR_CTEIF7 (1 << 27) -/* CHTIF7: Channel 7 half transfer clear */ -#define DMA_IFCR_CHTIF7 (1 << 26) -/* CTCIF7: Channel 7 transfer complete clear */ -#define DMA_IFCR_CTCIF7 (1 << 25) -/* CGIF7: Channel 7 global interrupt clear */ -#define DMA_IFCR_CGIF7 (1 << 24) -/* CTEIF6: Channel 6 transfer error clear */ -#define DMA_IFCR_CTEIF6 (1 << 23) -/* CHTIF6: Channel 6 half transfer clear */ -#define DMA_IFCR_CHTIF6 (1 << 22) -/* CTCIF6: Channel 6 transfer complete clear */ -#define DMA_IFCR_CTCIF6 (1 << 21) -/* CGIF6: Channel 6 global interrupt clear */ -#define DMA_IFCR_CGIF6 (1 << 20) -/* CTEIF5: Channel 5 transfer error clear */ -#define DMA_IFCR_CTEIF5 (1 << 19) -/* CHTIF5: Channel 5 half transfer clear */ -#define DMA_IFCR_CHTIF5 (1 << 18) -/* CTCIF5: Channel 5 transfer complete clear */ -#define DMA_IFCR_CTCIF5 (1 << 17) -/* CGIF5: Channel 5 global interrupt clear */ -#define DMA_IFCR_CGIF5 (1 << 16) -/* CTEIF4: Channel 4 transfer error clear */ -#define DMA_IFCR_CTEIF4 (1 << 15) -/* CHTIF4: Channel 4 half transfer clear */ -#define DMA_IFCR_CHTIF4 (1 << 14) -/* CTCIF4: Channel 4 transfer complete clear */ -#define DMA_IFCR_CTCIF4 (1 << 13) -/* CGIF4: Channel 4 global interrupt clear */ -#define DMA_IFCR_CGIF4 (1 << 12) -/* CTEIF3: Channel 3 transfer error clear */ -#define DMA_IFCR_CTEIF3 (1 << 11) -/* CHTIF3: Channel 3 half transfer clear */ -#define DMA_IFCR_CHTIF3 (1 << 10) -/* CTCIF3: Channel 3 transfer complete clear */ -#define DMA_IFCR_CTCIF3 (1 << 9) -/* CGIF3: Channel 3 global interrupt clear */ -#define DMA_IFCR_CGIF3 (1 << 8) -/* CTEIF2: Channel 2 transfer error clear */ -#define DMA_IFCR_CTEIF2 (1 << 7) -/* CHTIF2: Channel 2 half transfer clear */ -#define DMA_IFCR_CHTIF2 (1 << 6) -/* CTCIF2: Channel 2 transfer complete clear */ -#define DMA_IFCR_CTCIF2 (1 << 5) -/* CGIF2: Channel 2 global interrupt clear */ -#define DMA_IFCR_CGIF2 (1 << 4) -/* CTEIF1: Channel 1 transfer error clear */ -#define DMA_IFCR_CTEIF1 (1 << 3) -/* CHTIF1: Channel 1 half transfer clear */ -#define DMA_IFCR_CHTIF1 (1 << 2) -/* CTCIF1: Channel 1 transfer complete clear */ -#define DMA_IFCR_CTCIF1 (1 << 1) -/* CGIF1: Channel 1 global interrupt clear */ -#define DMA_IFCR_CGIF1 (1 << 0) - -/* --- DMA_CCR1 values ----------------------------------------------------- */ - -/* MEM2MEM: Memory to memory mode */ -#define DMA_CCR1_MEM2MEM (1 << 14) - -/* PL[13:12]: Channel priority level */ -#define DMA_CCR1_PL_LSB 12 -#define DMA_CCR1_PL_LOW 0x0 -#define DMA_CCR1_PL_MEDIUM 0x1 -#define DMA_CCR1_PL_HIGH 0x2 -#define DMA_CCR1_PL_VERY_HIGH 0x3 - -/* MSIZE[11:10]: Memory size */ -#define DMA_CCR1_MSIZE_LSB 10 -#define DMA_CCR1_MSIZE_8BIT 0x0 -#define DMA_CCR1_MSIZE_16BIT 0x1 -#define DMA_CCR1_MSIZE_32BIT 0x2 - -/* PSIZE[9:8]: Peripheral size */ -#define DMA_CCR1_PSIZE_LSB 8 -#define DMA_CCR1_PSIZE_8BIT 0x0 -#define DMA_CCR1_PSIZE_16BIT 0x1 -#define DMA_CCR1_PSIZE_32BIT 0x2 - -/* MINC: Memory increment mode */ -#define DMA_CCR1_MINC (1 << 7) - -/* PINC: Peripheral increment mode */ -#define DMA_CCR1_PINC (1 << 6) - -/* CIRC: Circular mode */ -#define DMA_CCR1_CIRC (1 << 5) - -/* DIR: Data transfer direction */ -#define DMA_CCR1_DIR (1 << 4) - -/* TEIE: Transfer error interrupt enable */ -#define DMA_CCR1_TEIE (1 << 3) - -/* HTIE: Half transfer interrupt enable */ -#define DMA_CCR1_HTIE (1 << 2) - -/* TCIE: Transfer complete interrupt enable */ -#define DMA_CCR1_TCIE (1 << 1) - -/* EN: Channel enable */ -#define DMA_CCR1_EN (1 << 0) - -/* --- DMA_CCR2 values ----------------------------------------------------- */ - -/* MEM2MEM: Memory to memory mode */ -#define DMA_CCR2_MEM2MEM (1 << 14) - -/* PL[13:12]: Channel priority level */ -#define DMA_CCR2_PL_LSB 12 -#define DMA_CCR2_PL_LOW 0x0 -#define DMA_CCR2_PL_MEDIUM 0x1 -#define DMA_CCR2_PL_HIGH 0x2 -#define DMA_CCR2_PL_VERY_HIGH 0x3 - -/* MSIZE[11:10]: Memory size */ -#define DMA_CCR2_MSIZE_LSB 10 -#define DMA_CCR2_MSIZE_8BIT 0x0 -#define DMA_CCR2_MSIZE_16BIT 0x1 -#define DMA_CCR2_MSIZE_32BIT 0x2 - -/* PSIZE[9:8]: Peripheral size */ -#define DMA_CCR2_PSIZE_LSB 8 -#define DMA_CCR2_PSIZE_8BIT 0x0 -#define DMA_CCR2_PSIZE_16BIT 0x1 -#define DMA_CCR2_PSIZE_32BIT 0x2 - -/* MINC: Memory increment mode */ -#define DMA_CCR2_MINC (1 << 7) - -/* PINC: Peripheral increment mode */ -#define DMA_CCR2_PINC (1 << 6) - -/* CIRC: Circular mode */ -#define DMA_CCR2_CIRC (1 << 5) - -/* DIR: Data transfer direction */ -#define DMA_CCR2_DIR (1 << 4) - -/* TEIE: Transfer error interrupt enable */ -#define DMA_CCR2_TEIE (1 << 3) - -/* HTIE: Half transfer interrupt enable */ -#define DMA_CCR2_HTIE (1 << 2) - -/* TCIE: Transfer complete interrupt enable */ -#define DMA_CCR2_TCIE (1 << 1) - -/* EN: Channel enable */ -#define DMA_CCR2_EN (1 << 0) - -/* --- DMA_CCR3 values ----------------------------------------------------- */ - -/* MEM2MEM: Memory to memory mode */ -#define DMA_CCR3_MEM2MEM (1 << 14) - -/* PL[13:12]: Channel priority level */ -#define DMA_CCR3_PL_LSB 12 -#define DMA_CCR3_PL_LOW 0x0 -#define DMA_CCR3_PL_MEDIUM 0x1 -#define DMA_CCR3_PL_HIGH 0x2 -#define DMA_CCR3_PL_VERY_HIGH 0x3 - -/* MSIZE[11:10]: Memory size */ -#define DMA_CCR3_MSIZE_LSB 10 -#define DMA_CCR3_MSIZE_8BIT 0x0 -#define DMA_CCR31_MSIZE_16BIT 0x1 -#define DMA_CCR3_MSIZE_32BIT 0x2 - -/* PSIZE[9:8]: Peripheral size */ -#define DMA_CCR3_PSIZE_LSB 8 -#define DMA_CCR3_PSIZE_8BIT 0x0 -#define DMA_CCR3_PSIZE_16BIT 0x1 -#define DMA_CCR3_PSIZE_32BIT 0x2 - -/* MINC: Memory increment mode */ -#define DMA_CCR3_MINC (1 << 7) - -/* PINC: Peripheral increment mode */ -#define DMA_CCR3_PINC (1 << 6) - -/* CIRC: Circular mode */ -#define DMA_CCR3_CIRC (1 << 5) - -/* DIR: Data transfer direction */ -#define DMA_CCR3_DIR (1 << 4) - -/* TEIE: Transfer error interrupt enable */ -#define DMA_CCR3_TEIE (1 << 3) - -/* HTIE: Half transfer interrupt enable */ -#define DMA_CCR3_HTIE (1 << 2) - -/* TCIE: Transfer complete interrupt enable */ -#define DMA_CCR3_TCIE (1 << 1) - -/* EN: Channel enable */ -#define DMA_CCR3_EN (1 << 0) - -/* --- DMA_CCR4 values ----------------------------------------------------- */ - -/* MEM2MEM: Memory to memory mode */ -#define DMA_CCR4_MEM2MEM (1 << 14) - -/* PL[13:12]: Channel priority level */ -#define DMA_CCR4_PL_LSB 12 -#define DMA_CCR4_PL_LOW 0x0 -#define DMA_CCR4_PL_MEDIUM 0x1 -#define DMA_CCR4_PL_HIGH 0x2 -#define DMA_CCR4_PL_VERY_HIGH 0x3 - -/* MSIZE[11:10]: Memory size */ -#define DMA_CCR4_MSIZE_LSB 10 -#define DMA_CCR4_MSIZE_8BIT 0x0 -#define DMA_CCR4_MSIZE_16BIT 0x1 -#define DMA_CCR4_MSIZE_32BIT 0x2 - -/* PSIZE[9:8]: Peripheral size */ -#define DMA_CCR4_PSIZE_LSB 8 -#define DMA_CCR4_PSIZE_8BIT 0x0 -#define DMA_CCR4_PSIZE_16BIT 0x1 -#define DMA_CCR4_PSIZE_32BIT 0x2 - -/* MINC: Memory increment mode */ -#define DMA_CCR4_MINC (1 << 7) - -/* PINC: Peripheral increment mode */ -#define DMA_CCR4_PINC (1 << 6) - -/* CIRC: Circular mode */ -#define DMA_CCR4_CIRC (1 << 5) - -/* DIR: Data transfer direction */ -#define DMA_CCR4_DIR (1 << 4) - -/* TEIE: Transfer error interrupt enable */ -#define DMA_CCR4_TEIE (1 << 3) - -/* HTIE: Half transfer interrupt enable */ -#define DMA_CCR4_HTIE (1 << 2) - -/* TCIE: Transfer complete interrupt enable */ -#define DMA_CCR4_TCIE (1 << 1) - -/* EN: Channel enable */ -#define DMA_CCR4_EN (1 << 0) - -/* --- DMA_CCR5 values ----------------------------------------------------- */ - -/* MEM2MEM: Memory to memory mode */ -#define DMA_CCR5_MEM2MEM (1 << 14) - -/* PL[13:12]: Channel priority level */ -#define DMA_CCR5_PL_LSB 12 -#define DMA_CCR5_PL_LOW 0x0 -#define DMA_CCR5_PL_MEDIUM 0x1 -#define DMA_CCR5_PL_HIGH 0x2 -#define DMA_CCR5_PL_VERY_HIGH 0x3 - -/* MSIZE[11:10]: Memory size */ -#define DMA_CCR5_MSIZE_LSB 10 -#define DMA_CCR5_MSIZE_8BIT 0x0 -#define DMA_CCR5_MSIZE_16BIT 0x1 -#define DMA_CCR5_MSIZE_32BIT 0x2 - -/* PSIZE[9:8]: Peripheral size */ -#define DMA_CCR5_PSIZE_LSB 8 -#define DMA_CCR5_PSIZE_8BIT 0x0 -#define DMA_CCR5_PSIZE_16BIT 0x1 -#define DMA_CCR5_PSIZE_32BIT 0x2 - -/* MINC: Memory increment mode */ -#define DMA_CCR5_MINC (1 << 7) - -/* PINC: Peripheral increment mode */ -#define DMA_CCR5_PINC (1 << 6) - -/* CIRC: Circular mode */ -#define DMA_CCR5_CIRC (1 << 5) - -/* DIR: Data transfer direction */ -#define DMA_CCR5_DIR (1 << 4) - -/* TEIE: Transfer error interrupt enable */ -#define DMA_CCR5_TEIE (1 << 3) - -/* HTIE: Half transfer interrupt enable */ -#define DMA_CCR5_HTIE (1 << 2) - -/* TCIE: Transfer complete interrupt enable */ -#define DMA_CCR5_TCIE (1 << 1) - -/* EN: Channel enable */ -#define DMA_CCR5_EN (1 << 0) - -/* --- DMA_CCR6 values ----------------------------------------------------- */ - -/* MEM2MEM: Memory to memory mode */ -#define DMA_CCR6_MEM2MEM (1 << 14) - -/* PL[13:12]: Channel priority level */ -#define DMA_CCR6_PL_LSB 12 -#define DMA_CCR6_PL_LOW 0x0 -#define DMA_CCR6_PL_MEDIUM 0x1 -#define DMA_CCR6_PL_HIGH 0x2 -#define DMA_CCR6_PL_VERY_HIGH 0x3 - -/* MSIZE[11:10]: Memory size */ -#define DMA_CCR6_MSIZE_LSB 10 -#define DMA_CCR6_MSIZE_8BIT 0x0 -#define DMA_CCR6_MSIZE_16BIT 0x1 -#define DMA_CCR6_MSIZE_32BIT 0x2 - -/* PSIZE[9:8]: Peripheral size */ -#define DMA_CCR6_PSIZE_LSB 8 -#define DMA_CCR6_PSIZE_8BIT 0x0 -#define DMA_CCR6_PSIZE_16BIT 0x1 -#define DMA_CCR6_PSIZE_32BIT 0x2 - -/* MINC: Memory increment mode */ -#define DMA_CCR6_MINC (1 << 7) - -/* PINC: Peripheral increment mode */ -#define DMA_CCR6_PINC (1 << 6) - -/* CIRC: Circular mode */ -#define DMA_CCR6_CIRC (1 << 5) - -/* DIR: Data transfer direction */ -#define DMA_CCR6_DIR (1 << 4) - -/* TEIE: Transfer error interrupt enable */ -#define DMA_CCR6_TEIE (1 << 3) - -/* HTIE: Half transfer interrupt enable */ -#define DMA_CCR6_HTIE (1 << 2) - -/* TCIE: Transfer complete interrupt enable */ -#define DMA_CCR6_TCIE (1 << 1) - -/* EN: Channel enable */ -#define DMA_CCR6_EN (1 << 0) - -/* --- DMA_CCR7 values ----------------------------------------------------- */ - -/* MEM2MEM: Memory to memory mode */ -#define DMA_CCR7_MEM2MEM (1 << 14) - -/* PL[13:12]: Channel priority level */ -#define DMA_CCR7_PL_LSB 12 -#define DMA_CCR7_PL_LOW 0x0 -#define DMA_CCR7_PL_MEDIUM 0x1 -#define DMA_CCR7_PL_HIGH 0x2 -#define DMA_CCR7_PL_VERY_HIGH 0x3 - -/* MSIZE[11:10]: Memory size */ -#define DMA_CCR7_MSIZE_LSB 10 -#define DMA_CCR7_MSIZE_8BIT 0x0 -#define DMA_CCR7_MSIZE_16BIT 0x1 -#define DMA_CCR7_MSIZE_32BIT 0x2 - -/* PSIZE[9:8]: Peripheral size */ -#define DMA_CCR7_PSIZE_LSB 8 -#define DMA_CCR7_PSIZE_8BIT 0x0 -#define DMA_CCR7_PSIZE_16BIT 0x1 -#define DMA_CCR7_PSIZE_32BIT 0x2 - -/* MINC: Memory increment mode */ -#define DMA_CCR7_MINC (1 << 7) - -/* PINC: Peripheral increment mode */ -#define DMA_CCR7_PINC (1 << 6) - -/* CIRC: Circular mode */ -#define DMA_CCR7_CIRC (1 << 5) - -/* DIR: Data transfer direction */ -#define DMA_CCR7_DIR (1 << 4) - -/* TEIE: Transfer error interrupt enable */ -#define DMA_CCR7_TEIE (1 << 3) - -/* HTIE: Half transfer interrupt enable */ -#define DMA_CCR7_HTIE (1 << 2) - -/* TCIE: Transfer complete interrupt enable */ -#define DMA_CCR7_TCIE (1 << 1) - -/* EN: Channel enable */ -#define DMA_CCR7_EN (1 << 0) - -/* --- DMA_CCRx generic values --------------------------------------------- */ - -/* MEM2MEM: Memory to memory mode */ -#define DMA_CCR_MEM2MEM (1 << 14) - -/* PL[13:12]: Channel priority level */ -#define DMA_CCR_PL_LSB 12 -#define DMA_CCR_PL_LOW 0x0 -#define DMA_CCR_PL_MEDIUM 0x1 -#define DMA_CCR_PL_HIGH 0x2 -#define DMA_CCR_PL_VERY_HIGH 0x3 - -/* MSIZE[11:10]: Memory size */ -#define DMA_CCR_MSIZE_LSB 10 -#define DMA_CCR_MSIZE_8BIT 0x0 -#define DMA_CCR_MSIZE_16BIT 0x1 -#define DMA_CCR_MSIZE_32BIT 0x2 - -/* PSIZE[9:8]: Peripheral size */ -#define DMA_CCR_PSIZE_LSB 8 -#define DMA_CCR_PSIZE_8BIT 0x0 -#define DMA_CCR_PSIZE_16BIT 0x1 -#define DMA_CCR_PSIZE_32BIT 0x2 - -/* MINC: Memory increment mode */ -#define DMA_CCR_MINC (1 << 7) - -/* PINC: Peripheral increment mode */ -#define DMA_CCR_PINC (1 << 6) - -/* CIRC: Circular mode */ -#define DMA_CCR_CIRC (1 << 5) - -/* DIR: Data transfer direction */ -#define DMA_CCR_DIR (1 << 4) - -/* TEIE: Transfer error interrupt enable */ -#define DMA_CCR_TEIE (1 << 3) - -/* HTIE: Half transfer interrupt enable */ -#define DMA_CCR_HTIE (1 << 2) - -/* TCIE: Transfer complete interrupt enable */ -#define DMA_CCR_TCIE (1 << 1) - -/* EN: Channel enable */ -#define DMA_CCR_EN (1 << 0) - -/* --- DMA_CNDTRx values --------------------------------------------------- */ - -/* NDT[15:0]: Number of data to transfer */ - -/* --- DMA_CPARx values ---------------------------------------------------- */ - -/* PA[31:0]: Peripheral address */ - -/* --- DMA_CMARx values ---------------------------------------------------- */ - -/* MA[31:0]: Memory address */ - -/* --- Generic values ------------------------------------------------------ */ - -#define DMA_CHANNEL1 1 -#define DMA_CHANNEL2 2 -#define DMA_CHANNEL3 3 -#define DMA_CHANNEL4 4 -#define DMA_CHANNEL5 5 -#define DMA_CHANNEL6 6 -#define DMA_CHANNEL7 7 - -/* --- function prototypes ------------------------------------------------- */ - -void dma_enable_mem2mem_mode(u32 dma, u8 channel); -void dma_set_priority(u32 dma, u8 channel, u8 prio); -void dma_set_memory_size(u32 dma, u8 channel, u8 mem_size); -void dma_set_peripheral_size(u32 dma, u8 channel, u8 peripheral_size); -void dma_enable_memory_increment_mode(u32 dma, u8 channel); -void dma_enable_peripheral_increment_mode(u32 dma, u8 channel); -void dma_enable_circular_mode(u32 dma, u8 channel); -void dma_set_read_from_peripheral(u32 dma, u8 channel); -void dma_set_read_from_memory(u32 dma, u8 channel); -void dma_enable_transfer_error_interrupt(u32 dma, u8 channel); -void dma_disable_transfer_error_interrupt(u32 dma, u8 channel); -void dma_enable_half_transfer_interrupt(u32 dma, u8 channel); -void dma_disable_half_transfer_interrupt(u32 dma, u8 channel); -void dma_enable_transfer_complete_interrupt(u32 dma, u8 channel); -void dma_disable_transfer_complete_interrupt(u32 dma, u8 channel); -void dma_enable_channel(u32 dma, u8 channel); -void dma_disable_channel(u32 dma, u8 channel); -void dma_set_peripheral_address(u32 dma, u8 channel, u32 address); -void dma_set_memory_address(u32 dma, u8 channel, u32 address); -void dma_set_number_of_data(u32 dma, u8 channel, u16 number); - -#endif diff --git a/include/libopencm3/stm32f1/ethernet.h b/include/libopencm3/stm32f1/ethernet.h deleted file mode 100644 index 3d7f1ee..0000000 --- a/include/libopencm3/stm32f1/ethernet.h +++ /dev/null @@ -1,203 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Gareth McMullin - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_ETHERNET_H -#define LIBOPENCM3_ETHERNET_H - -#include -#include - -/* Ethernet MAC registers */ -#define ETH_MACCR MMIO32(ETHERNET_BASE + 0x00) -#define ETH_MACFFR MMIO32(ETHERNET_BASE + 0x04) -#define ETH_MACHTHR MMIO32(ETHERNET_BASE + 0x08) -#define ETH_MACHTLR MMIO32(ETHERNET_BASE + 0x0C) -#define ETH_MACMIIAR MMIO32(ETHERNET_BASE + 0x10) -#define ETH_MACMIIDR MMIO32(ETHERNET_BASE + 0x14) -#define ETH_MACFCR MMIO32(ETHERNET_BASE + 0x18) -#define ETH_MACVLANTR MMIO32(ETHERNET_BASE + 0x1C) -#define ETH_MACRWUFFR MMIO32(ETHERNET_BASE + 0x28) -#define ETH_MACPMTCSR MMIO32(ETHERNET_BASE + 0x2C) -#define ETH_MACSR MMIO32(ETHERNET_BASE + 0x38) -#define ETH_MACIMR MMIO32(ETHERNET_BASE + 0x3C) -#define ETH_MACA0HR MMIO32(ETHERNET_BASE + 0x40) -#define ETH_MACA0LR MMIO32(ETHERNET_BASE + 0x44) -#define ETH_MACA1HR MMIO32(ETHERNET_BASE + 0x48) -#define ETH_MACA1LR MMIO32(ETHERNET_BASE + 0x4C) -#define ETH_MACA2HR MMIO32(ETHERNET_BASE + 0x50) -#define ETH_MACA2LR MMIO32(ETHERNET_BASE + 0x54) -#define ETH_MACA3HR MMIO32(ETHERNET_BASE + 0x58) -#define ETH_MACA3LR MMIO32(ETHERNET_BASE + 0x5C) - -/* Ethernet MMC registers */ -#define ETH_MMCCR MMIO32(ETHERNET_BASE + 0x100) -#define ETH_MMCRIR MMIO32(ETHERNET_BASE + 0x104) -#define ETH_MMCTIR MMIO32(ETHERNET_BASE + 0x108) -#define ETH_MMCRIMR MMIO32(ETHERNET_BASE + 0x10C) -#define ETH_MMCTIMR MMIO32(ETHERNET_BASE + 0x110) -#define ETH_MMCTGFSCCR MMIO32(ETHERNET_BASE + 0x14C) -#define ETH_MMCTGFMSCCR MMIO32(ETHERNET_BASE + 0x150) -#define ETH_MMCTGFCR MMIO32(ETHERNET_BASE + 0x168) -#define ETH_MMCRFCECR MMIO32(ETHERNET_BASE + 0x194) -#define ETH_MMCRFAECR MMIO32(ETHERNET_BASE + 0x198) -#define ETH_MMCRGUFCR MMIO32(ETHERNET_BASE + 0x1C4) - -/* Ethrenet IEEE 1588 time stamp registers */ -#define ETH_PTPTSCR MMIO32(ETHERNET_BASE + 0x700) -#define ETH_PTPSSIR MMIO32(ETHERNET_BASE + 0x704) -#define ETH_PTPTSHR MMIO32(ETHERNET_BASE + 0x708) -#define ETH_PTPTSLR MMIO32(ETHERNET_BASE + 0x70C) -#define ETH_PTPTSHUR MMIO32(ETHERNET_BASE + 0x710) -#define ETH_PTPTSLUR MMIO32(ETHERNET_BASE + 0x714) -#define ETH_PTPTSAR MMIO32(ETHERNET_BASE + 0x718) -#define ETH_PTPTTHR MMIO32(ETHERNET_BASE + 0x71C) -#define ETH_PTPTTLR MMIO32(ETHERNET_BASE + 0x720) - -/* Ethernet DMA registers */ -#define ETH_DMABMR MMIO32(ETHERNET_BASE + 0x1000) -#define ETH_DMATPDR MMIO32(ETHERNET_BASE + 0x1004) -#define ETH_DMARPDR MMIO32(ETHERNET_BASE + 0x1008) -#define ETH_DMARDLAR MMIO32(ETHERNET_BASE + 0x100C) -#define ETH_DMATDLAR MMIO32(ETHERNET_BASE + 0x1010) -#define ETH_DMATDLAR MMIO32(ETHERNET_BASE + 0x1010) -#define ETH_DMASR MMIO32(ETHERNET_BASE + 0x1014) -#define ETH_DMAOMR MMIO32(ETHERNET_BASE + 0x1018) -#define ETH_DMAIER MMIO32(ETHERNET_BASE + 0x101C) -#define ETH_DMAMFBOCR MMIO32(ETHERNET_BASE + 0x1020) -#define ETH_DMACHTDR MMIO32(ETHERNET_BASE + 0x1048) -#define ETH_DMACHRDR MMIO32(ETHERNET_BASE + 0x104C) -#define ETH_DMACHTBAR MMIO32(ETHERNET_BASE + 0x1050) -#define ETH_DMACHRBAR MMIO32(ETHERNET_BASE + 0x1054) - -/* Ethernet MAC Register bit definitions */ -/* Ethernet MAC configuration register ETH_MACCR bits */ -#define ETH_MACCR_RE 0x00000004 -#define ETH_MACCR_TE 0x00000008 -#define ETH_MACCR_DC 0x00000010 -#define ETH_MACCR_BL 0x00000060 -#define ETH_MACCR_APCS 0x00000080 -#define ETH_MACCR_RD 0x00000200 -#define ETH_MACCR_IPCO 0x00000400 -#define ETH_MACCR_DM 0x00000800 -#define ETH_MACCR_LM 0x00001000 -#define ETH_MACCR_ROD 0x00002000 -#define ETH_MACCR_FES 0x00004000 -#define ETH_MACCR_CSD 0x00010000 -#define ETH_MACCR_IFG 0x000E0000 -#define ETH_MACCR_JD 0x00400000 -#define ETH_MACCR_WD 0x00800000 - -/* Ethernet MAC frame filter register ETH_MACFFR bits */ -#define ETH_MACFFR_PM 0x00000001 -#define ETH_MACFFR_HU 0x00000002 -#define ETH_MACFFR_HM 0x00000004 -#define ETH_MACFFR_DAIF 0x00000008 -#define ETH_MACFFR_PAM 0x00000010 -#define ETH_MACFFR_BFD 0x00000020 -#define ETH_MACFFR_PCF 0x000000C0 -#define ETH_MACFFR_SAIF 0x00000100 -#define ETH_MACFFR_SAF 0x00000200 -#define ETH_MACFFR_HPF 0x00000400 -#define ETH_MACFFR_PA 0x80000000 - -/* Ethernet MAC MII address register ETH_MACMIIAR bits */ -#define ETH_MACMIIAR_MB 0x0001 -#define ETH_MACMIIAR_MW 0x0002 -/* Clock Range for MDC frequency */ -#define ETH_MACMIIAR_CR_MASK 0x001C -#define ETH_MACMIIAR_CR_HCLK_DIV_42 0x0000 /* For HCLK 60-72 MHz */ -#define ETH_MACMIIAR_CR_HCLK_DIV_16 0x0008 /* For HCLK 20-35 MHz */ -#define ETH_MACMIIAR_CR_HCLK_DIV_24 0x000C /* For HCLK 35-60 MHz */ -#define ETH_MACMIIAR_MR 0x07C0 -#define ETH_MACMIIAR_PA 0xF800 - -/* Ethernet MAC flow control register ETH_MACFCR bits */ -#define ETH_MACFCR_FCB 0x00000001 -#define ETH_MACFCR_BPA 0x00000001 -#define ETH_MACFCR_TFCE 0x00000002 -#define ETH_MACFCR_RFCE 0x00000004 -#define ETH_MACFCR_UPFD 0x00000008 -#define ETH_MACFCR_PLT 0x00000030 -#define ETH_MACFCR_ZQPD 0x00000080 -#define ETH_MACFCR_PT 0xFFFF0000 - -/* Ethernet MAC interrupt status regster ETH_MACSR bits */ -#define ETH_MACSR_PMTS 0x0008 -#define ETH_MACSR_MMCS 0x0010 -#define ETH_MACSR_MMCRS 0x0020 -#define ETH_MACSR_MMCTS 0x0040 -#define ETH_MACSR_TSTS 0x0200 - -/* Ethernet MAC interrupt mask regster ETH_MACIMR bits */ -#define ETH_MACIMR_PMTIM 0x0008 -#define ETH_MACIMR_TSTIM 0x0200 - -/* Ethernet DMA Register bit definitions */ -/* Ethernet DMA bus mode register ETH_DMABMR bits */ -#define ETH_DMABMR_SR 0x00000001 -#define ETH_DMABMR_DA 0x00000002 -#define ETH_DMABMR_DSL_MASK 0x0000007C -#define ETH_DMABMR_PBL_MASK 0x00003F00 -#define ETH_DMABMR_RTPR_MASK 0x0000C000 -#define ETH_DMABMR_RTPR_1TO1 0x00000000 -#define ETH_DMABMR_RTPR_2TO1 0x00004000 -#define ETH_DMABMR_RTPR_3TO1 0x00008000 -#define ETH_DMABMR_RTPR_4TO1 0x0000C000 -#define ETH_DMABMR_FB 0x00010000 -#define ETH_DMABMR_RDP_MASK 0x007E0000 -#define ETH_DMABMR_USP 0x00800000 -#define ETH_DMABMR_FPM 0x01000000 -#define ETH_DMABMR_AAB 0x02000000 - -/* Ethernet DMA operation mode register ETH_DMAOMR bits */ -#define ETH_DMAOMR_SR 0x00000002 -#define ETH_DMAOMR_OSF 0x00000004 -#define ETH_DMAOMR_RTC_MASK 0x00000018 -#define ETH_DMAOMR_RTC_64 0x00000000 -#define ETH_DMAOMR_RTC_32 0x00000008 -#define ETH_DMAOMR_RTC_96 0x00000010 -#define ETH_DMAOMR_RTC_128 0x00000018 -#define ETH_DMAOMR_FUGF 0x00000040 -#define ETH_DMAOMR_FEF 0x00000080 -#define ETH_DMAOMR_ST 0x00002000 -#define ETH_DMAOMR_TTC_MASK 0x0001C000 -#define ETH_DMAOMR_FTF 0x00100000 -#define ETH_DMAOMR_TSF 0x00200000 -#define ETH_DMAOMR_DFRF 0x01000000 -#define ETH_DMAOMR_RSF 0x02000000 -#define ETH_DMAOMR_DTCEFD 0x04000000 - -/* Ethernet DMA interrupt enable register ETH_DMAIER bits */ -#define ETH_DMAIER_TIE 0x00000001 -#define ETH_DMAIER_TPSIE 0x00000002 -#define ETH_DMAIER_TBUIE 0x00000004 -#define ETH_DMAIER_TJTIE 0x00000008 -#define ETH_DMAIER_ROIE 0x00000010 -#define ETH_DMAIER_TUIE 0x00000020 -#define ETH_DMAIER_RIE 0x00000040 -#define ETH_DMAIER_RBUIE 0x00000080 -#define ETH_DMAIER_RPSIE 0x00000100 -#define ETH_DMAIER_RWTIE 0x00000200 -#define ETH_DMAIER_ETIE 0x00000400 -#define ETH_DMAIER_FBEIE 0x00002000 -#define ETH_DMAIER_ERIE 0x00004000 -#define ETH_DMAIER_AISE 0x00008000 -#define ETH_DMAIER_NSIE 0x00010000 - -#endif diff --git a/include/libopencm3/stm32f1/flash.h b/include/libopencm3/stm32f1/flash.h deleted file mode 100644 index f9b2aa9..0000000 --- a/include/libopencm3/stm32f1/flash.h +++ /dev/null @@ -1,113 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * Copyright (C) 2010 Mark Butler - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* - * For details see: - * PM0042 Programming manual: STM32F10xxx Flash programming - * October 2009, Doc ID 13259 Rev 7 - * http://www.st.com/stonline/products/literature/pm/13259.pdf - */ - -#ifndef LIBOPENCM3_FLASH_H -#define LIBOPENCM3_FLASH_H - -#include -#include - -/* --- FLASH registers ----------------------------------------------------- */ - -#define FLASH_ACR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x00) -#define FLASH_KEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x04) -#define FLASH_OPTKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x08) -#define FLASH_SR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x0C) -#define FLASH_CR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x10) -#define FLASH_AR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14) -#define FLASH_OBR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x1C) -#define FLASH_WRPR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x20) - -/* --- FLASH_ACR values ---------------------------------------------------- */ - -#define FLASH_PRFTBS (1 << 5) -#define FLASH_PRFTBE (1 << 4) -#define FLASH_HLFCYA (1 << 3) -#define FLASH_LATENCY_0WS 0x00 -#define FLASH_LATENCY_1WS 0x01 -#define FLASH_LATENCY_2WS 0x02 - -/* --- FLASH_SR values ----------------------------------------------------- */ - -#define FLASH_EOP (1 << 5) -#define FLASH_WRPRTERR (1 << 4) -#define FLASH_PGERR (1 << 2) -#define FLASH_BSY (1 << 0) - -/* --- FLASH_CR values ----------------------------------------------------- */ - -#define FLASH_EOPIE (1 << 12) -#define FLASH_ERRIE (1 << 10) -#define FLASH_OPTWRE (1 << 9) -#define FLASH_LOCK (1 << 7) -#define FLASH_STRT (1 << 6) -#define FLASH_OPTER (1 << 5) -#define FLASH_OPTPG (1 << 4) -#define FLASH_MER (1 << 2) -#define FLASH_PER (1 << 1) -#define FLASH_PG (1 << 0) - -/* --- FLASH_OBR values ---------------------------------------------------- */ - -/* FLASH_OBR[25:18]: Data1 */ -/* FLASH_OBR[17:10]: Data0 */ -#define FLASH_NRST_STDBY (1 << 4) -#define FLASH_NRST_STOP (1 << 3) -#define FLASH_WDG_SW (1 << 2) -#define FLASH_RDPRT (1 << 1) -#define FLASH_OPTERR (1 << 0) - -/* --- FLASH Keys -----------------------------------------------------------*/ - -#define RDP_KEY ((u16)0x00a5) -#define FLASH_KEY1 ((u32)0x45670123) -#define FLASH_KEY2 ((u32)0xcdef89ab) - -/* --- Function prototypes ------------------------------------------------- */ - -void flash_prefetch_buffer_enable(void); -void flash_prefetch_buffer_disable(void); -void flash_halfcycle_enable(void); -void flash_halfcycle_disable(void); -void flash_set_ws(u32 ws); -void flash_unlock(void); -void flash_lock(void); -void flash_clear_pgerr_flag(void); -void flash_clear_eop_flag(void); -void flash_clear_wrprterr_flag(void); -void flash_clear_bsy_flag(void); -void flash_clear_status_flags(void); -void flash_unlock_option_bytes(void); -void flash_erase_all_pages(void); -void flash_erase_page(u32 page_address); -void flash_program_word(u32 address, u32 data); -void flash_program_half_word(u32 address, u16 data); -void flash_wait_for_last_operation(void); -void flash_erase_option_bytes(void); -void flash_program_option_bytes(u32 address, u16 data); - -#endif diff --git a/include/libopencm3/stm32f1/gpio.h b/include/libopencm3/stm32f1/gpio.h deleted file mode 100644 index f1463a3..0000000 --- a/include/libopencm3/stm32f1/gpio.h +++ /dev/null @@ -1,555 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_GPIO_H -#define LIBOPENCM3_GPIO_H - -#include -#include - -/* --- Convenience macros -------------------------------------------------- */ - -/* GPIO port base addresses (for convenience) */ -#define GPIOA GPIO_PORT_A_BASE -#define GPIOB GPIO_PORT_B_BASE -#define GPIOC GPIO_PORT_C_BASE -#define GPIOD GPIO_PORT_D_BASE -#define GPIOE GPIO_PORT_E_BASE -#define GPIOF GPIO_PORT_F_BASE -#define GPIOG GPIO_PORT_G_BASE - -/* GPIO number definitions (for convenience) */ -#define GPIO0 (1 << 0) -#define GPIO1 (1 << 1) -#define GPIO2 (1 << 2) -#define GPIO3 (1 << 3) -#define GPIO4 (1 << 4) -#define GPIO5 (1 << 5) -#define GPIO6 (1 << 6) -#define GPIO7 (1 << 7) -#define GPIO8 (1 << 8) -#define GPIO9 (1 << 9) -#define GPIO10 (1 << 10) -#define GPIO11 (1 << 11) -#define GPIO12 (1 << 12) -#define GPIO13 (1 << 13) -#define GPIO14 (1 << 14) -#define GPIO15 (1 << 15) -#define GPIO_ALL 0xffff - -/* --- Alternate function GPIOs -------------------------------------------- */ - -/* Default alternate functions of some pins (with and without remapping) */ - -/* CAN1 / CAN */ -#define GPIO_CAN1_RX GPIO11 /* PA11 */ -#define GPIO_CAN1_TX GPIO12 /* PA12 */ -#define GPIO_CAN_RX GPIO_CAN1_RX /* Alias */ -#define GPIO_CAN_TX GPIO_CAN1_TX /* Alias */ - -#define GPIO_CAN_PB_RX GPIO8 /* PB8 */ -#define GPIO_CAN_PB_TX GPIO9 /* PB9 */ -#define GPIO_CAN1_PB_RX GPIO_CAN_PB_RX /* Alias */ -#define GPIO_CAN1_PB_TX GPIO_CAN_PB_TX /* Alias */ - -#define GPIO_CAN_PD_RX GPIO0 /* PD0 */ -#define GPIO_CAN_PD_TX GPIO1 /* PD1 */ -#define GPIO_CAN1_PD_RX GPIO_CAN_PD_RX /* Alias */ -#define GPIO_CAN1_PD_TX GPIO_CAN_PD_TX /* Alias */ - -/* CAN2 */ -#define GPIO_CAN2_RX GPIO12 /* PB12 */ -#define GPIO_CAN2_TX GPIO13 /* PB13 */ - -#define GPIO_CAN2_RE_RX GPIO5 /* PB5 */ -#define GPIO_CAN2_RE_TX GPIO6 /* PB6 */ - -/* JTAG/SWD */ -#define GPIO_JTMS_SWDIO GPIO13 /* PA13 */ -#define GPIO_JTCK_SWCLK GPIO14 /* PA14 */ -#define GPIO_JTDI GPIO15 /* PA15 */ -#define GPIO_JTDO_TRACESWO GPIO3 /* PB3 */ -#define GPIO_JNTRST GPIO4 /* PB4 */ -#define GPIO_TRACECK GPIO2 /* PE2 */ -#define GPIO_TRACED0 GPIO3 /* PE3 */ -#define GPIO_TRACED1 GPIO4 /* PE4 */ -#define GPIO_TRACED2 GPIO5 /* PE5 */ -#define GPIO_TRACED3 GPIO6 /* PE6 */ - -/* Timer5 */ -#define GPIO_TIM5_CH4 GPIO3 /* PA3 */ - -/* Timer4 */ -#define GPIO_TIM4_CH1 GPIO6 /* PB6 */ -#define GPIO_TIM4_CH2 GPIO7 /* PB7 */ -#define GPIO_TIM4_CH3 GPIO8 /* PB8 */ -#define GPIO_TIM4_CH4 GPIO9 /* PB9 */ - -#define GPIO_TIM4_RE_CH1 GPIO12 /* PD12 */ -#define GPIO_TIM4_RE_CH2 GPIO13 /* PD13 */ -#define GPIO_TIM4_RE_CH3 GPIO14 /* PD14 */ -#define GPIO_TIM4_RE_CH4 GPIO15 /* PD15 */ - -/* Timer3 */ -#define GPIO_TIM3_CH1 GPIO6 /* PA6 */ -#define GPIO_TIM3_CH2 GPIO7 /* PA7 */ -#define GPIO_TIM3_CH3 GPIO0 /* PB0 */ -#define GPIO_TIM3_CH4 GPIO1 /* PB1 */ - -#define GPIO_TIM3_PR_CH1 GPIO4 /* PB4 */ -#define GPIO_TIM3_PR_CH2 GPIO5 /* PB5 */ -#define GPIO_TIM3_PR_CH3 GPIO0 /* PB0 */ -#define GPIO_TIM3_PR_CH4 GPIO1 /* PB1 */ - -#define GPIO_TIM3_FR_CH1 GPIO6 /* PC6 */ -#define GPIO_TIM3_FR_CH2 GPIO7 /* PC7 */ -#define GPIO_TIM3_FR_CH3 GPIO8 /* PC8 */ -#define GPIO_TIM3_FR_CH4 GPIO9 /* PC9 */ - -/* Timer2 */ -#define GPIO_TIM2_CH1_ETR GPIO0 /* PA0 */ -#define GPIO_TIM2_CH2 GPIO1 /* PA1 */ -#define GPIO_TIM2_CH3 GPIO2 /* PA2 */ -#define GPIO_TIM2_CH4 GPIO3 /* PA3 */ - -#define GPIO_TIM2_PR1_CH1_ETR GPIO15 /* PA15 */ -#define GPIO_TIM2_PR1_CH2 GPIO3 /* PB3 */ -#define GPIO_TIM2_PR1_CH3 GPIO2 /* PA2 */ -#define GPIO_TIM2_PR1_CH4 GPIO3 /* PA3 */ - -#define GPIO_TIM2_PR2_CH1_ETR GPIO0 /* PA0 */ -#define GPIO_TIM2_PR2_CH2 GPIO1 /* PA1 */ -#define GPIO_TIM2_PR2_CH3 GPIO10 /* PB10 */ -#define GPIO_TIM2_PR2_CH4 GPIO11 /* PB11 */ - -#define GPIO_TIM2_FR_CH1_ETR GPIO15 /* PA15 */ -#define GPIO_TIM2_FR_CH2 GPIO3 /* PB3 */ -#define GPIO_TIM2_FR_CH3 GPIO10 /* PB10 */ -#define GPIO_TIM2_FR_CH4 GPIO11 /* PB11 */ - -/* Timer1 */ -#define GPIO_TIM1_ETR GPIO12 /* PA12 */ -#define GPIO_TIM1_CH1 GPIO8 /* PA8 */ -#define GPIO_TIM1_CH2 GPIO9 /* PA9 */ -#define GPIO_TIM1_CH3 GPIO10 /* PA10 */ -#define GPIO_TIM1_CH4 GPIO11 /* PA11 */ -#define GPIO_TIM1_BKIN GPIO12 /* PB12 */ -#define GPIO_TIM1_CH1N GPIO13 /* PB13 */ -#define GPIO_TIM1_CH2N GPIO14 /* PB14 */ -#define GPIO_TIM1_CH3N GPIO15 /* PB15 */ - -#define GPIO_TIM1_PR_ETR GPIO12 /* PA12 */ -#define GPIO_TIM1_PR_CH1 GPIO8 /* PA8 */ -#define GPIO_TIM1_PR_CH2 GPIO9 /* PA9 */ -#define GPIO_TIM1_PR_CH3 GPIO10 /* PA10 */ -#define GPIO_TIM1_PR_CH4 GPIO11 /* PA11 */ -#define GPIO_TIM1_PR_BKIN GPIO6 /* PA6 */ -#define GPIO_TIM1_PR_CH1N GPIO7 /* PA7 */ -#define GPIO_TIM1_PR_CH2N GPIO0 /* PB0 */ -#define GPIO_TIM1_PR_CH3N GPIO1 /* PB1 */ - -#define GPIO_TIM1_FR_ETR GPIO7 /* PE7 */ -#define GPIO_TIM1_FR_CH1 GPIO9 /* PE9 */ -#define GPIO_TIM1_FR_CH2 GPIO11 /* PE11 */ -#define GPIO_TIM1_FR_CH3 GPIO13 /* PE13 */ -#define GPIO_TIM1_FR_CH4 GPIO14 /* PE14 */ -#define GPIO_TIM1_FR_BKIN GPIO15 /* PE15 */ -#define GPIO_TIM1_FR_CH1N GPIO8 /* PE8 */ -#define GPIO_TIM1_FR_CH2N GPIO10 /* PE10 */ -#define GPIO_TIM1_FR_CH3N GPIO12 /* PE12 */ - -/* USART3 */ -#define GPIO_USART3_TX GPIO10 /* PB10 */ -#define GPIO_USART3_RX GPIO11 /* PB11 */ -#define GPIO_USART3_CK GPIO12 /* PB12 */ -#define GPIO_USART3_CTS GPIO13 /* PB13 */ -#define GPIO_USART3_RTS GPIO14 /* PB14 */ - -#define GPIO_USART3_PR_TX GPIO10 /* PC10 */ -#define GPIO_USART3_PR_RX GPIO11 /* PC11 */ -#define GPIO_USART3_PR_CK GPIO12 /* PC12 */ -#define GPIO_USART3_PR_CTS GPIO13 /* PB13 */ -#define GPIO_USART3_PR_RTS GPIO14 /* PB14 */ - -#define GPIO_USART3_FR_TX GPIO8 /* PD8 */ -#define GPIO_USART3_FR_RX GPIO9 /* PD9 */ -#define GPIO_USART3_FR_CK GPIO10 /* PD10 */ -#define GPIO_USART3_FR_CTS GPIO11 /* PD11 */ -#define GPIO_USART3_FR_RTS GPIO12 /* PD12 */ - -/* USART2 */ -#define GPIO_USART2_CTS GPIO0 /* PA0 */ -#define GPIO_USART2_RTS GPIO1 /* PA1 */ -#define GPIO_USART2_TX GPIO2 /* PA2 */ -#define GPIO_USART2_RX GPIO3 /* PA3 */ -#define GPIO_USART2_CK GPIO4 /* PA4 */ - -#define GPIO_USART2_RE_CTS GPIO3 /* PD3 */ -#define GPIO_USART2_RE_RTS GPIO4 /* PD4 */ -#define GPIO_USART2_RE_TX GPIO5 /* PD5 */ -#define GPIO_USART2_RE_RX GPIO6 /* PD6 */ -#define GPIO_USART2_RE_CK GPIO7 /* PD7 */ - -/* USART1 */ -#define GPIO_USART1_TX GPIO9 /* PA9 */ -#define GPIO_USART1_RX GPIO10 /* PA10 */ - -#define GPIO_USART1_RE_TX GPIO6 /* PB6 */ -#define GPIO_USART1_RE_RX GPIO7 /* PB7 */ - -/* I2C1 */ -#define GPIO_I2C1_SMBAI GPIO5 /* PB5 */ -#define GPIO_I2C1_SCL GPIO6 /* PB6 */ -#define GPIO_I2C1_SDA GPIO7 /* PB7 */ - -#define GPIO_I2C1_RE_SMBAI GPIO5 /* PB5 */ -#define GPIO_I2C1_RE_SCL GPIO8 /* PB8 */ -#define GPIO_I2C1_RE_SDA GPIO9 /* PB9 */ - -/* I2C2 */ -#define GPIO_I2C2_SCL GPIO10 /* PB10 */ -#define GPIO_I2C2_SDA GPIO11 /* PB11 */ -#define GPIO_I2C2_SMBAI GPIO12 /* PB12 */ - -/* SPI1 */ -#define GPIO_SPI1_NSS GPIO4 /* PA4 */ -#define GPIO_SPI1_SCK GPIO5 /* PA5 */ -#define GPIO_SPI1_MISO GPIO6 /* PA6 */ -#define GPIO_SPI1_MOSI GPIO7 /* PA7 */ - -#define GPIO_SPI1_RE_NSS GPIO15 /* PA15 */ -#define GPIO_SPI1_RE_SCK GPIO3 /* PB3 */ -#define GPIO_SPI1_RE_MISO GPIO4 /* PB4 */ -#define GPIO_SPI1_RE_MOSI GPIO5 /* PB5 */ - -/* SPI2 */ -#define GPIO_SPI2_NSS GPIO12 /* PB12 */ -#define GPIO_SPI2_SCK GPIO13 /* PB13 */ -#define GPIO_SPI2_MISO GPIO14 /* PB14 */ -#define GPIO_SPI2_MOSI GPIO15 /* PB15 */ - -/* SPI3 */ -#define GPIO_SPI3_NSS GPIO15 /* PA15 */ -#define GPIO_SPI3_SCK GPIO3 /* PB3 */ -#define GPIO_SPI3_MISO GPIO4 /* PB4 */ -#define GPIO_SPI3_MOSI GPIO5 /* PB5 */ - -#define GPIO_SPI3_RE_NSS GPIO4 /* PA4 */ -#define GPIO_SPI3_RE_SCK GPIO10 /* PC10 */ -#define GPIO_SPI3_RE_MISO GPIO11 /* PC11 */ -#define GPIO_SPI3_RE_MOSI GPIO12 /* PC12 */ - -/* ETH */ -#define GPIO_ETH_RX_DV_CRS_DV GPIO7 /* PA7 */ -#define GPIO_ETH_RXD0 GPIO4 /* PC4 */ -#define GPIO_ETH_RXD1 GPIO5 /* PC5 */ -#define GPIO_ETH_RXD2 GPIO0 /* PB0 */ -#define GPIO_ETH_RXD3 GPIO1 /* PB1 */ - -#define GPIO_ETH_RE_RX_DV_CRS_DV GPIO8 /* PD8 */ -#define GPIO_ETH_RE_RXD0 GPIO9 /* PD9 */ -#define GPIO_ETH_RE_RXD1 GPIO10 /* PD10 */ -#define GPIO_ETH_RE_RXD2 GPIO11 /* PD11 */ -#define GPIO_ETH_RE_RXD3 GPIO12 /* PD12 */ - -/* --- GPIO registers ------------------------------------------------------ */ - -/* Port configuration register low (GPIOx_CRL) */ -#define GPIO_CRL(port) MMIO32(port + 0x00) -#define GPIOA_CRL GPIO_CRL(GPIOA) -#define GPIOB_CRL GPIO_CRL(GPIOB) -#define GPIOC_CRL GPIO_CRL(GPIOC) -#define GPIOD_CRL GPIO_CRL(GPIOD) -#define GPIOE_CRL GPIO_CRL(GPIOE) -#define GPIOF_CRL GPIO_CRL(GPIOF) -#define GPIOG_CRL GPIO_CRL(GPIOG) - -/* Port configuration register low (GPIOx_CRH) */ -#define GPIO_CRH(port) MMIO32(port + 0x04) -#define GPIOA_CRH GPIO_CRH(GPIOA) -#define GPIOB_CRH GPIO_CRH(GPIOB) -#define GPIOC_CRH GPIO_CRH(GPIOC) -#define GPIOD_CRH GPIO_CRH(GPIOD) -#define GPIOE_CRH GPIO_CRH(GPIOE) -#define GPIOF_CRH GPIO_CRH(GPIOF) -#define GPIOG_CRH GPIO_CRH(GPIOG) - -/* Port input data register (GPIOx_IDR) */ -#define GPIO_IDR(port) MMIO32(port + 0x08) -#define GPIOA_IDR GPIO_IDR(GPIOA) -#define GPIOB_IDR GPIO_IDR(GPIOB) -#define GPIOC_IDR GPIO_IDR(GPIOC) -#define GPIOD_IDR GPIO_IDR(GPIOD) -#define GPIOE_IDR GPIO_IDR(GPIOE) -#define GPIOF_IDR GPIO_IDR(GPIOF) -#define GPIOG_IDR GPIO_IDR(GPIOG) - -/* Port output data register (GPIOx_ODR) */ -#define GPIO_ODR(port) MMIO32(port + 0x0c) -#define GPIOA_ODR GPIO_ODR(GPIOA) -#define GPIOB_ODR GPIO_ODR(GPIOB) -#define GPIOC_ODR GPIO_ODR(GPIOC) -#define GPIOD_ODR GPIO_ODR(GPIOD) -#define GPIOE_ODR GPIO_ODR(GPIOE) -#define GPIOF_ODR GPIO_ODR(GPIOF) -#define GPIOG_ODR GPIO_ODR(GPIOG) - -/* Port bit set/reset register (GPIOx_BSRR) */ -#define GPIO_BSRR(port) MMIO32(port + 0x10) -#define GPIOA_BSRR GPIO_BSRR(GPIOA) -#define GPIOB_BSRR GPIO_BSRR(GPIOB) -#define GPIOC_BSRR GPIO_BSRR(GPIOC) -#define GPIOD_BSRR GPIO_BSRR(GPIOD) -#define GPIOE_BSRR GPIO_BSRR(GPIOE) -#define GPIOF_BSRR GPIO_BSRR(GPIOF) -#define GPIOG_BSRR GPIO_BSRR(GPIOG) - -/* Port bit reset register (GPIOx_BRR) */ -#define GPIO_BRR(port) MMIO16(port + 0x14) -#define GPIOA_BRR GPIO_BRR(GPIOA) -#define GPIOB_BRR GPIO_BRR(GPIOB) -#define GPIOC_BRR GPIO_BRR(GPIOC) -#define GPIOD_BRR GPIO_BRR(GPIOD) -#define GPIOE_BRR GPIO_BRR(GPIOE) -#define GPIOF_BRR GPIO_BRR(GPIOF) -#define GPIOG_BRR GPIO_BRR(GPIOG) - -/* Port configuration lock register (GPIOx_LCKR) */ -#define GPIO_LCKR(port) MMIO32(port + 0x18) -#define GPIOA_LCKR GPIO_LCKR(GPIOA) -#define GPIOB_LCKR GPIO_LCKR(GPIOB) -#define GPIOC_LCKR GPIO_LCKR(GPIOC) -#define GPIOD_LCKR GPIO_LCKR(GPIOD) -#define GPIOE_LCKR GPIO_LCKR(GPIOE) -#define GPIOF_LCKR GPIO_LCKR(GPIOF) -#define GPIOG_LCKR GPIO_LCKR(GPIOG) - -/* --- GPIO_CRL/GPIO_CRH values -------------------------------------------- */ - -/* CNF[1:0] values when MODE[1:0] is 00 (input mode) */ -#define GPIO_CNF_INPUT_ANALOG 0x00 -#define GPIO_CNF_INPUT_FLOAT 0x01 /* Default */ -#define GPIO_CNF_INPUT_PULL_UPDOWN 0x02 - -/* Output mode (MODE[1:0]) values */ -#define GPIO_MODE_INPUT 0x00 /* Default */ -#define GPIO_MODE_OUTPUT_10_MHZ 0x01 -#define GPIO_MODE_OUTPUT_2_MHZ 0x02 -#define GPIO_MODE_OUTPUT_50_MHZ 0x03 - -/* CNF[1:0] values when MODE[1:0] is != 00 (one of the output modes) */ -#define GPIO_CNF_OUTPUT_PUSHPULL 0x00 -#define GPIO_CNF_OUTPUT_OPENDRAIN 0x01 -#define GPIO_CNF_OUTPUT_ALTFN_PUSHPULL 0x02 -#define GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN 0x03 - -/* --- GPIO_IDR values ----------------------------------------------------- */ - -/* GPIO_IDR[15:0]: IDRy[15:0]: Port input data (y = 0..15) */ - -/* --- GPIO_ODR values ----------------------------------------------------- */ - -/* GPIO_ODR[15:0]: ODRy[15:0]: Port output data (y = 0..15) */ - -/* --- GPIO_BSRR values ---------------------------------------------------- */ - -/* GPIO_BSRR[31:16]: BRy: Port x reset bit y (y = 0..15) */ -/* GPIO_BSRR[15:0]: BSy: Port x set bit y (y = 0..15) */ - -/* --- GPIO_BRR values ----------------------------------------------------- */ - -/* GPIO_BRR[15:0]: BRy: Port x reset bit y (y = 0..15) */ - -/* --- GPIO_LCKR values ---------------------------------------------------- */ - -#define GPIO_LCKK (1 << 16) -/* GPIO_LCKR[15:0]: LCKy: Port x lock bit y (y = 0..15) */ - -/* --- AFIO registers ------------------------------------------------------ */ - -/* Event control register (AFIO_EVCR) */ -#define AFIO_EVCR MMIO32(AFIO_BASE + 0x00) - -/* AF remap and debug I/O configuration register (AFIO_MAPR) */ -#define AFIO_MAPR MMIO32(AFIO_BASE + 0x04) - -/* External interrupt configuration register 1 (AFIO_EXTICR1) */ -#define AFIO_EXTICR1 MMIO32(AFIO_BASE + 0x08) - -/* External interrupt configuration register 2 (AFIO_EXTICR2) */ -#define AFIO_EXTICR2 MMIO32(AFIO_BASE + 0x0c) - -/* External interrupt configuration register 3 (AFIO_EXTICR3) */ -#define AFIO_EXTICR3 MMIO32(AFIO_BASE + 0x10) - -/* External interrupt configuration register 4 (AFIO_EXTICR4) */ -#define AFIO_EXTICR4 MMIO32(AFIO_BASE + 0x14) - -/* --- AFIO_EVCR values ---------------------------------------------------- */ - -/* EVOE: Event output enable */ -#define AFIO_EVCR_EVOE (1 << 7) - -/* PORT[2:0]: Port selection */ -#define AFIO_EVCR_PORT_PA (0x0 << 4) -#define AFIO_EVCR_PORT_PB (0x1 << 4) -#define AFIO_EVCR_PORT_PC (0x2 << 4) -#define AFIO_EVCR_PORT_PD (0x3 << 4) -#define AFIO_EVCR_PORT_PE (0x4 << 4) - -/* PIN[3:0]: Pin selection */ -#define AFIO_EVCR_PIN_Px0 (0x0 << 0) -#define AFIO_EVCR_PIN_Px1 (0x1 << 0) -#define AFIO_EVCR_PIN_Px2 (0x2 << 0) -#define AFIO_EVCR_PIN_Px3 (0x3 << 0) -#define AFIO_EVCR_PIN_Px4 (0x4 << 0) -#define AFIO_EVCR_PIN_Px5 (0x5 << 0) -#define AFIO_EVCR_PIN_Px6 (0x6 << 0) -#define AFIO_EVCR_PIN_Px7 (0x7 << 0) -#define AFIO_EVCR_PIN_Px8 (0x8 << 0) -#define AFIO_EVCR_PIN_Px9 (0x9 << 0) -#define AFIO_EVCR_PIN_Px10 (0xA << 0) -#define AFIO_EVCR_PIN_Px11 (0xB << 0) -#define AFIO_EVCR_PIN_Px12 (0xC << 0) -#define AFIO_EVCR_PIN_Px13 (0xD << 0) -#define AFIO_EVCR_PIN_Px14 (0xE << 0) -#define AFIO_EVCR_PIN_Px15 (0xF << 0) - -/* --- AFIO_MAPR values ---------------------------------------------------- */ - -/* 31 reserved */ - -/* PTP_PPS_REMAP: Ethernet PTP PPS remapping - * (only connectivity line devices) */ -#define AFIO_MAPR_PTP_PPS_REMAP (1 << 30) - -/* TIM2ITR1_IREMAP: TIM2 internal trigger 1 remapping - * (only connectivity line devices) */ -#define AFIO_MAPR_TIM2ITR1_IREMAP (1 << 29) - -/* SPI3_REMAP: SPI3/I2S3 remapping - * (only connectivity line devices) */ -#define AFIO_MAPR_SPI3_REMAP (1 << 28) - -/* 27 reserved */ - -/* SWJ_CFG[2:0]: Serial wire JTAG configuration */ -#define AFIO_MAPR_SWJ_CFG_FULL_SWJ (0x0 << 24) -#define AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_JNTRST (0x1 << 24) -#define AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_ON (0x2 << 24) -#define AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_OFF (0x4 << 24) - -/* MII_REMAP: MII or RMII selection - * (only connectivity line devices) */ -#define AFIO_MAPR_MII_RMII_SEL (1 << 23) - -/* CAN2_REMAP: CAN2 I/O remapping - * (only connectivity line devices) */ -#define AFIO_MAPR_CAN2_REMAP (1 << 22) - -/* ETH_REMAP: Ethernet MAC I/O remapping - * (only connectivity line devices) */ -#define AFIO_MAPR_ETH_REMAP (1 << 21) - -/* ADC2_ETRGREG_REMAP: ADC2 external trigger regulator conversion remapping - * (only low-, medium-, high- and XL-densitiy devices) */ -#define AFIO_MAPR_ADC2_ETRGREG_REMAP (1 << 20) - -/* ADC2_ETRGINJ_REMAP: ADC2 external trigger injected conversion remapping - * (only low-, medium-, high- and XL-densitiy devices) */ -#define AFIO_MAPR_ADC2_ETRGINJ_REMAP (1 << 19) - -/* ADC1_ETRGREG_REMAP: ADC1 external trigger regulator conversion remapping - * (only low-, medium-, high- and XL-densitiy devices) */ -#define AFIO_MAPR_ADC1_ETRGREG_REMAP (1 << 18) - -/* ADC1_ETRGINJ_REMAP: ADC1 external trigger injected conversion remapping - * (only low-, medium-, high- and XL-densitiy devices) */ -#define AFIO_MAPR_ADC1_ETRGINJ_REMAP (1 << 17) - -/* TIM5CH4_IREMAP: TIM5 channel4 internal remap */ -#define AFIO_MAPR_TIM5CH4_IREMAP (1 << 16) - -/* PD01_REMAP: Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ -#define AFIO_MAPR_PD01_REMAP (1 << 15) - -/* CAN_REMAP[1:0]: CAN1 alternate function remapping */ -#define AFIO_MAPR_CAN1_REMAP_PORTA (0x0 << 13) -#define AFIO_MAPR_CAN1_REMAP_PORTB (0x2 << 13) /* Not on 36pin pkg */ -#define AFIO_MAPR_CAN1_REMAP_PORTD (0x3 << 13) - -/* TIM4_REMAP: TIM4 remapping */ -#define AFIO_MAPR_TIM4_REMAP (1 << 12) - -/* TIM3_REMAP[1:0]: TIM3 remapping */ -#define AFIO_MAPR_TIM3_REMAP_NO_REMAP (0x0 << 10) -#define AFIO_MAPR_TIM3_REMAP_PARTIAL_REMAP (0x2 << 10) -#define AFIO_MAPR_TIM3_REMAP_FULL_REMAP (0x3 << 10) - -/* TIM2_REMAP[1:0]: TIM2 remapping */ -#define AFIO_MAPR_TIM2_REMAP_NO_REMAP (0x0 << 8) -#define AFIO_MAPR_TIM2_REMAP_PARTIAL_REMAP1 (0x1 << 8) -#define AFIO_MAPR_TIM2_REMAP_PARTIAL_REMAP2 (0x2 << 8) -#define AFIO_MAPR_TIM2_REMAP_FULL_REMAP (0x3 << 8) - -/* TIM1_REMAP[1:0]: TIM1 remapping */ -#define AFIO_MAPR_TIM1_REMAP_NO_REMAP (0x0 << 6) -#define AFIO_MAPR_TIM1_REMAP_PARTIAL_REMAP (0x1 << 6) -#define AFIO_MAPR_TIM1_REMAP_FULL_REMAP (0x3 << 6) - -/* USART3_REMAP[1:0]: USART3 remapping */ -#define AFIO_MAPR_USART3_REMAP_NO_REMAP (0x0 << 4) -#define AFIO_MAPR_USART3_REMAP_PARTIAL_REMAP (0x1 << 4) -#define AFIO_MAPR_USART3_REMAP_FULL_REMAP (0x3 << 4) - -/* USART2_REMAP[1:0]: USART2 remapping */ -#define AFIO_MAPR_USART2_REMAP (1 << 3) - -/* USART1_REMAP[1:0]: USART1 remapping */ -#define AFIO_MAPR_USART1_REMAP (1 << 2) - -/* I2C1_REMAP[1:0]: I2C1 remapping */ -#define AFIO_MAPR_I2C1_REMAP (1 << 1) - -/* SPI1_REMAP[1:0]: SPI1 remapping */ -#define AFIO_MAPR_SPI1_REMAP (1 << 0) - -/* --- AFIO_EXTICR1 values ------------------------------------------------- */ -/* --- AFIO_EXTICR2 values ------------------------------------------------- */ -/* --- AFIO_EXTICR3 values ------------------------------------------------- */ -/* --- AFIO_EXTICR4 values ------------------------------------------------- */ - -/* EXTI0 - EXTI15 interrupt source selection registers */ - -/* Note: For using them we should define a function that calculates the right - * registers, using definitions is probably not a good idea. - */ - -/* --- Function prototypes ------------------------------------------------- */ - -void gpio_set_mode(u32 gpioport, u8 mode, u8 cnf, u16 gpios); -void gpio_set(u32 gpioport, u16 gpios); -void gpio_clear(u32 gpioport, u16 gpios); -u16 gpio_get(u32 gpioport, u16 gpios); -void gpio_toggle(u32 gpioport, u16 gpios); -u16 gpio_port_read(u32 gpioport); -void gpio_port_write(u32 gpioport, u16 data); -void gpio_port_config_lock(u32 gpioport, u16 gpios); - -#endif diff --git a/include/libopencm3/stm32f1/memorymap.h b/include/libopencm3/stm32f1/memorymap.h deleted file mode 100644 index e3c57c8..0000000 --- a/include/libopencm3/stm32f1/memorymap.h +++ /dev/null @@ -1,113 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_MEMORYMAP_H -#define LIBOPENCM3_MEMORYMAP_H - -#include - -/* --- STM32 specific peripheral definitions ------------------------------- */ - -/* Memory map for all busses */ -#define PERIPH_BASE 0x40000000 -#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000) -#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000) -#define PERIPH_BASE_AHB (PERIPH_BASE + 0x18000) - -/* Register boundary addresses */ - -/* APB1 */ -#define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000) -#define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400) -#define TIM4_BASE (PERIPH_BASE_APB1 + 0x0800) -#define TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00) -#define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000) -#define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400) -#define TIM12_BASE (PERIPH_BASE_APB1 + 0x1800) -#define TIM13_BASE (PERIPH_BASE_APB1 + 0x1c00) -#define TIM14_BASE (PERIPH_BASE_APB1 + 0x2000) -/* PERIPH_BASE_APB1 + 0x2400 (0x4000 2400 - 0x4000 27FF): Reserved */ -#define RTC_BASE (PERIPH_BASE_APB1 + 0x2800) -#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00) -#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000) -/* PERIPH_BASE_APB1 + 0x3400 (0x4000 3400 - 0x4000 37FF): Reserved */ -#define SPI2_I2S_BASE (PERIPH_BASE_APB1 + 0x3800) -#define SPI3_I2S_BASE (PERIPH_BASE_APB1 + 0x3c00) -/* PERIPH_BASE_APB1 + 0x4000 (0x4000 4000 - 0x4000 3FFF): Reserved */ -#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400) -#define USART3_BASE (PERIPH_BASE_APB1 + 0x4800) -#define UART4_BASE (PERIPH_BASE_APB1 + 0x4c00) -#define UART5_BASE (PERIPH_BASE_APB1 + 0x5000) -#define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400) -#define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800) -#define USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x5c00) -#define USB_CAN_SRAM_BASE (PERIPH_BASE_APB1 + 0x6000) -#define BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400) -#define BX_CAN2_BASE (PERIPH_BASE_APB1 + 0x6800) -/* PERIPH_BASE_APB1 + 0x6800 (0x4000 6800 - 0x4000 6BFF): Reserved? Typo? */ -#define BACKUP_REGS_BASE (PERIPH_BASE_APB1 + 0x6c00) -#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000) -#define DAC_BASE (PERIPH_BASE_APB1 + 0x7400) -/* PERIPH_BASE_APB1 + 0x7800 (0x4000 7800 - 0x4000 FFFF): Reserved */ - -/* APB2 */ -#define AFIO_BASE (PERIPH_BASE_APB2 + 0x0000) -#define EXTI_BASE (PERIPH_BASE_APB2 + 0x0400) -#define GPIO_PORT_A_BASE (PERIPH_BASE_APB2 + 0x0800) -#define GPIO_PORT_B_BASE (PERIPH_BASE_APB2 + 0x0c00) -#define GPIO_PORT_C_BASE (PERIPH_BASE_APB2 + 0x1000) -#define GPIO_PORT_D_BASE (PERIPH_BASE_APB2 + 0x1400) -#define GPIO_PORT_E_BASE (PERIPH_BASE_APB2 + 0x1800) -#define GPIO_PORT_F_BASE (PERIPH_BASE_APB2 + 0x1c00) -#define GPIO_PORT_G_BASE (PERIPH_BASE_APB2 + 0x2000) -#define ADC1_BASE (PERIPH_BASE_APB2 + 0x2400) -#define ADC2_BASE (PERIPH_BASE_APB2 + 0x2800) -#define TIM1_BASE (PERIPH_BASE_APB2 + 0x2c00) -#define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000) -#define TIM8_BASE (PERIPH_BASE_APB2 + 0x3400) -#define USART1_BASE (PERIPH_BASE_APB2 + 0x3800) -#define ADC3_BASE (PERIPH_BASE_APB2 + 0x3c00) -/* PERIPH_BASE_APB2 + 0x4000 (0x4001 4000 - 0x4001 4FFF): Reserved */ -#define TIM9_BASE (PERIPH_BASE_APB2 + 0x4c00) -#define TIM10_BASE (PERIPH_BASE_APB2 + 0x5000) -#define TIM11_BASE (PERIPH_BASE_APB2 + 0x5400) -/* PERIPH_BASE_APB2 + 0x5800 (0x4001 5800 - 0x4001 7FFF): Reserved */ - -/* AHB */ -#define SDIO_BASE (PERIPH_BASE_AHB + 0x00000) -/* PERIPH_BASE_AHB + 0x0400 (0x4001 8400 - 0x4001 7FFF): Reserved */ -#define DMA1_BASE (PERIPH_BASE_AHB + 0x08000) -#define DMA2_BASE (PERIPH_BASE_AHB + 0x08400) -/* PERIPH_BASE_AHB + 0x8800 (0x4002 0800 - 0x4002 0FFF): Reserved */ -#define RCC_BASE (PERIPH_BASE_AHB + 0x09000) -/* PERIPH_BASE_AHB + 0x9400 (0x4002 1400 - 0x4002 1FFF): Reserved */ -#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB + 0x0a000) -#define CRC_BASE (PERIPH_BASE_AHB + 0x0b000) -/* PERIPH_BASE_AHB + 0xb400 (0x4002 3400 - 0x4002 7FFF): Reserved */ -#define ETHERNET_BASE (PERIPH_BASE_AHB + 0x10000) -/* PERIPH_BASE_AHB + 0x18000 (0x4003 0000 - 0x4FFF FFFF): Reserved */ -#define USB_OTG_FS_BASE (PERIPH_BASE_AHB + 0xffe8000) - -/* PPIB */ -#define DBGMCU_BASE (PPBI_BASE + 0x00042000) - -/* FSMC */ -#define FSMC_BASE (PERIPH_BASE + 0x60000000) - -#endif diff --git a/include/libopencm3/stm32f1/nvic.h b/include/libopencm3/stm32f1/nvic.h deleted file mode 100644 index d29c425..0000000 --- a/include/libopencm3/stm32f1/nvic.h +++ /dev/null @@ -1,162 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_NVIC_H -#define LIBOPENCM3_NVIC_H - -#include -#include - -/* --- NVIC Registers ------------------------------------------------------ */ - -/* ISER: Interrupt Set Enable Registers */ -/* Note: 8 32bit Registers */ -#define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + (iser_id * 4)) - -/* NVIC_BASE + 0x020 (0xE000 E120 - 0xE000 E17F): Reserved */ - -/* ICER: Interrupt Clear Enable Registers */ -/* Note: 8 32bit Registers */ -#define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + (icer_id * 4)) - -/* NVIC_BASE + 0x0A0 (0xE000 E1A0 - 0xE000 E1FF): Reserved */ - -/* ISPR: Interrupt Set Pending Registers */ -/* Note: 8 32bit Registers */ -#define NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + (ispr_id * 4)) - -/* NVIC_BASE + 0x120 (0xE000 E220 - 0xE000 E27F): Reserved */ - -/* ICPR: Interrupt Clear Pending Registers */ -/* Note: 8 32bit Registers */ -#define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + (icpr_id * 4)) - -/* NVIC_BASE + 0x1A0 (0xE000 E2A0 - 0xE00 E2FF): Reserved */ - -/* IABR: Interrupt Active Bit Register */ -/* Note: 8 32bit Registers */ -#define NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + (iabr_id * 4)) - -/* NVIC_BASE + 0x220 (0xE000 E320 - 0xE000 E3FF): Reserved */ - -/* IPR: Interrupt Priority Registers */ -/* Note: 240 8bit Registers */ -#define NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + ipr_id) - -/* STIR: Software Trigger Interrupt Register */ -#define NVIC_STIR MMIO32(STIR_BASE) - -/* --- IRQ channel numbers-------------------------------------------------- */ - -/* Cortex M3 System Interrupts */ -#define NVIC_NMI_IRQ -14 -#define NVIC_HARD_FAULT_IRQ -13 -#define NVIC_MEM_MANAGE_IRQ -12 -#define NVIC_BUS_FAULT_IRQ -11 -#define NVIC_USAGE_FAULT_IRQ -10 -/* irq numbers -6 to -9 are reserved */ -#define NVIC_SV_CALL_IRQ -5 -#define DEBUG_MONITOR_IRQ -4 -/* irq number -3 reserved */ -#define NVIC_PENDSV_IRQ -2 -#define NVIC_SYSTICK_IRQ -1 - -/* User Interrupts */ -#define NVIC_WWDG_IRQ 0 -#define NVIC_PVD_IRQ 1 -#define NVIC_TAMPER_IRQ 2 -#define NVIC_RTC_IRQ 3 -#define NVIC_FLASH_IRQ 4 -#define NVIC_RCC_IRQ 5 -#define NVIC_EXTI0_IRQ 6 -#define NVIC_EXTI1_IRQ 7 -#define NVIC_EXTI2_IRQ 8 -#define NVIC_EXTI3_IRQ 9 -#define NVIC_EXTI4_IRQ 10 -#define NVIC_DMA1_CHANNEL1_IRQ 11 -#define NVIC_DMA1_CHANNEL2_IRQ 12 -#define NVIC_DMA1_CHANNEL3_IRQ 13 -#define NVIC_DMA1_CHANNEL4_IRQ 14 -#define NVIC_DMA1_CHANNEL5_IRQ 15 -#define NVIC_DMA1_CHANNEL6_IRQ 16 -#define NVIC_DMA1_CHANNEL7_IRQ 17 -#define NVIC_ADC1_2_IRQ 18 -#define NVIC_USB_HP_CAN_TX_IRQ 19 -#define NVIC_USB_LP_CAN_RX0_IRQ 20 -#define NVIC_CAN_RX1_IRQ 21 -#define NVIC_CAN_SCE_IRQ 22 -#define NVIC_EXTI9_5_IRQ 23 -#define NVIC_TIM1_BRK_IRQ 24 -#define NVIC_TIM1_UP_IRQ 25 -#define NVIC_TIM1_TRG_COM_IRQ 26 -#define NVIC_TIM1_CC_IRQ 27 -#define NVIC_TIM2_IRQ 28 -#define NVIC_TIM3_IRQ 29 -#define NVIC_TIM4_IRQ 30 -#define NVIC_I2C1_EV_IRQ 31 -#define NVIC_I2C1_ER_IRQ 32 -#define NVIC_I2C2_EV_IRQ 33 -#define NVIC_I2C2_ER_IRQ 34 -#define NVIC_SPI1_IRQ 35 -#define NVIC_SPI2_IRQ 36 -#define NVIC_USART1_IRQ 37 -#define NVIC_USART2_IRQ 38 -#define NVIC_USART3_IRQ 39 -#define NVIC_EXTI15_10_IRQ 40 -#define NVIC_RTC_ALARM_IRQ 41 -#define NVIC_USB_WAKEUP_IRQ 42 -#define NVIC_TIM8_BRK_IRQ 43 -#define NVIC_TIM8_UP_IRQ 44 -#define NVIC_TIM8_TRG_COM_IRQ 45 -#define NVIC_TIM8_CC_IRQ 46 -#define NVIC_ADC3_IRQ 47 -#define NVIC_FSMC_IRQ 48 -#define NVIC_SDIO_IRQ 49 -#define NVIC_TIM5_IRQ 50 -#define NVIC_SPI3_IRQ 51 -#define NVIC_USART4_IRQ 52 -#define NVIC_USART5_IRQ 53 -#define NVIC_TIM6_IRQ 54 -#define NVIC_TIM7_IRQ 55 -#define NVIC_DMA2_CHANNEL1_IRQ 56 -#define NVIC_DMA2_CHANNEL2_IRQ 57 -#define NVIC_DMA2_CHANNEL3_IRQ 58 -#define NVIC_DMA2_CHANNEL4_5_IRQ 59 -#define NVIC_DMA2_CHANNEL5_IRQ 60 -#define NVIC_ETH_IRQ 61 -#define NVIC_ETH_WKUP_IRQ 62 -#define NVIC_CAN2_TX_IRQ 63 -#define NVIC_CAN2_RX0_IRQ 64 -#define NVIC_CAN2_RX1_IRQ 65 -#define NVIC_CAN2_SCE_IRQ 66 -#define NVIC_OTG_FS_IRQ 67 - -/* --- NVIC functions ------------------------------------------------------ */ - -void nvic_enable_irq(u8 irqn); -void nvic_disable_irq(u8 irqn); -u8 nvic_get_pending_irq(u8 irqn); -void nvic_set_pending_irq(u8 irqn); -void nvic_clear_pending_irq(u8 irqn); -u8 nvic_get_active_irq(u8 irqn); -u8 nvic_get_irq_enabled(u8 irqn); -void nvic_set_priority(u8 irqn, u8 priority); -void nvic_generate_software_interrupt(u8 irqn); - -#endif diff --git a/include/libopencm3/stm32f1/otg_fs.h b/include/libopencm3/stm32f1/otg_fs.h deleted file mode 100644 index e1d7a6a..0000000 --- a/include/libopencm3/stm32f1/otg_fs.h +++ /dev/null @@ -1,324 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Gareth McMullin - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_OTG_FS_H -#define LIBOPENCM3_OTG_FS_H - -#include -#include - -/* Core Global Control and Status Registers */ -#define OTG_FS_OTGCTL MMIO32(USB_OTG_FS_BASE + 0x000) -#define OTG_FS_GOTGINT MMIO32(USB_OTG_FS_BASE + 0x004) -#define OTG_FS_GAHBCFG MMIO32(USB_OTG_FS_BASE + 0x008) -#define OTG_FS_GUSBCFG MMIO32(USB_OTG_FS_BASE + 0x00C) -#define OTG_FS_GRSTCTL MMIO32(USB_OTG_FS_BASE + 0x010) -#define OTG_FS_GINTSTS MMIO32(USB_OTG_FS_BASE + 0x014) -#define OTG_FS_GINTMSK MMIO32(USB_OTG_FS_BASE + 0x018) -#define OTG_FS_GRXSTSR MMIO32(USB_OTG_FS_BASE + 0x01C) -#define OTG_FS_GRXSTSP MMIO32(USB_OTG_FS_BASE + 0x020) -#define OTG_FS_GRXFSIZ MMIO32(USB_OTG_FS_BASE + 0x024) -#define OTG_FS_GNPTXFSIZ MMIO32(USB_OTG_FS_BASE + 0x028) -#define OTG_FS_GNPTXSTS MMIO32(USB_OTG_FS_BASE + 0x02C) -#define OTG_FS_GCCFG MMIO32(USB_OTG_FS_BASE + 0x038) -#define OTG_FS_CID MMIO32(USB_OTG_FS_BASE + 0x03C) -#define OTG_FS_HPTXFSIZ MMIO32(USB_OTG_FS_BASE + 0x100) -#define OTG_FS_DIEPTXF(x) MMIO32(USB_OTG_FS_BASE + 0x104 + 4*(x)) - -/* Host-mode Control and Status Registers */ -#define OTG_FS_HCFG MMIO32(USB_OTG_FS_BASE + 0x400) -#define OTG_FS_HFIR MMIO32(USB_OTG_FS_BASE + 0x404) -#define OTG_FS_HFNUM MMIO32(USB_OTG_FS_BASE + 0x408) -#define OTG_FS_HPTXSTS MMIO32(USB_OTG_FS_BASE + 0x410) -#define OTG_FS_HAINT MMIO32(USB_OTG_FS_BASE + 0x414) -#define OTG_FS_HAINTMSK MMIO32(USB_OTG_FS_BASE + 0x418) -#define OTG_FS_HPRT MMIO32(USB_OTG_FS_BASE + 0x440) -#define OTG_FS_HCCHARx MMIO32(USB_OTG_FS_BASE + 0x500) -#define OTG_FS_HCINTx MMIO32(USB_OTG_FS_BASE + 0x508) -#define OTG_FS_HCINTMSKx MMIO32(USB_OTG_FS_BASE + 0x50C) -#define OTG_FS_HCTSIZx MMIO32(USB_OTG_FS_BASE + 0x510) - -/* Device-mode Control and Status Registers */ -#define OTG_FS_DCFG MMIO32(USB_OTG_FS_BASE + 0x800) -#define OTG_FS_DCTL MMIO32(USB_OTG_FS_BASE + 0x804) -#define OTG_FS_DSTS MMIO32(USB_OTG_FS_BASE + 0x808) -#define OTG_FS_DIEPMSK MMIO32(USB_OTG_FS_BASE + 0x810) -#define OTG_FS_DOEPMSK MMIO32(USB_OTG_FS_BASE + 0x814) -#define OTG_FS_DAINT MMIO32(USB_OTG_FS_BASE + 0x818) -#define OTG_FS_DAINTMSK MMIO32(USB_OTG_FS_BASE + 0x81C) -#define OTG_FS_DVBUSDIS MMIO32(USB_OTG_FS_BASE + 0x828) -#define OTG_FS_DVBUSPULSE MMIO32(USB_OTG_FS_BASE + 0x82C) -#define OTG_FS_DIEPEMPMSK MMIO32(USB_OTG_FS_BASE + 0x834) -#define OTG_FS_DIEPCTL0 MMIO32(USB_OTG_FS_BASE + 0x900) -#define OTG_FS_DIEPCTL(x) MMIO32(USB_OTG_FS_BASE + 0x900 + 0x20*(x)) -#define OTG_FS_DOEPCTL0 MMIO32(USB_OTG_FS_BASE + 0xB00) -#define OTG_FS_DOEPCTL(x) MMIO32(USB_OTG_FS_BASE + 0xB00 + 0x20*(x)) -#define OTG_FS_DIEPINT(x) MMIO32(USB_OTG_FS_BASE + 0x908 + 0x20*(x)) -#define OTG_FS_DOEPINT(x) MMIO32(USB_OTG_FS_BASE + 0xB08 + 0x20*(x)) -#define OTG_FS_DIEPTSIZ0 MMIO32(USB_OTG_FS_BASE + 0x910) -#define OTG_FS_DOEPTSIZ0 MMIO32(USB_OTG_FS_BASE + 0xB10) -#define OTG_FS_DIEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + 0x910 + 0x20*(x)) -#define OTG_FS_DTXFSTS(x) MMIO32(USB_OTG_FS_BASE + 0x918 + 0x20*(x)) -#define OTG_FS_DOEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + 0xB10 + 0x20*(x)) - -/* Power and clock gating control and status register */ -#define OTG_FS_PCGCCTL MMIO32(USB_OTG_FS_BASE + 0xE00) - -/* Data FIFO */ -#define OTG_FS_FIFO(x) ((u32*)(USB_OTG_FS_BASE + (((x) + 1) << 12))) - -/* Global CSRs */ -/* OTG_FS AHB configuration register (OTG_FS_GAHBCFG) */ -#define OTG_FS_GAHBCFG_GINT 0x0001 -#define OTG_FS_GAHBCFG_TXFELVL 0x0080 -#define OTG_FS_GAHBCFG_PTXFELVL 0x0100 - -/* OTG_FS USB configuration register (OTG_FS_GUSBCFG) */ -#define OTG_FS_GUSBCFG_TOCAL 0x00000003 -#define OTG_FS_GUSBCFG_SRPCAP 0x00000100 -#define OTG_FS_GUSBCFG_HNPCAP 0x00000200 -#define OTG_FS_GUSBCFG_TRDT_MASK (0xf << 10) -#define OTG_FS_GUSBCFG_TRDT_16BIT (0x5 << 10) -#define OTG_FS_GUSBCFG_TRDT_8BIT (0x9 << 10) -#define OTG_FS_GUSBCFG_NPTXRWEN 0x00004000 -#define OTG_FS_GUSBCFG_FHMOD 0x20000000 -#define OTG_FS_GUSBCFG_FDMOD 0x40000000 -#define OTG_FS_GUSBCFG_CTXPKT 0x80000000 -/* WARNING: not in reference manual */ -#define OTG_FS_GUSBCFG_PHYSEL (1 << 6) - -/* OTG_FS reset register (OTG_FS_GRSTCTL) */ -#define OTG_FS_GRSTCTL_AHBIDL (1 << 31) -/* Bits 30:11 - Reserved */ -#define OTG_FS_GRSTCTL_TXFNUM_MASK (0x1f << 6) -#define OTG_FS_GRSTCTL_TXFFLSH (1 << 5) -#define OTG_FS_GRSTCTL_RXFFLSH (1 << 4) -/* Bit 3 - Reserved */ -#define OTG_FS_GRSTCTL_FCRST (1 << 2) -#define OTG_FS_GRSTCTL_HSRST (1 << 1) -#define OTG_FS_GRSTCTL_CSRST (1 << 0) - -/* OTG_FS interrupt status register (OTG_FS_GINTSTS) */ -#define OTG_FS_GINTSTS_WKUPINT (1 << 31) -#define OTG_FS_GINTSTS_SRQINT (1 << 30) -#define OTG_FS_GINTSTS_DISCINT (1 << 29) -#define OTG_FS_GINTSTS_CIDSCHG (1 << 28) -/* Bit 27 - Reserved */ -#define OTG_FS_GINTSTS_PTXFE (1 << 26) -#define OTG_FS_GINTSTS_HCINT (1 << 25) -#define OTG_FS_GINTSTS_HPRTINT (1 << 24) -/* Bits 23:22 - Reserved */ -#define OTG_FS_GINTSTS_IPXFR (1 << 21) -#define OTG_FS_GINTSTS_INCOMPISOOUT (1 << 21) -#define OTG_FS_GINTSTS_IISOIXFR (1 << 20) -#define OTG_FS_GINTSTS_OEPINT (1 << 19) -#define OTG_FS_GINTSTS_IEPINT (1 << 18) -/* Bits 17:16 - Reserved */ -#define OTG_FS_GINTSTS_EOPF (1 << 15) -#define OTG_FS_GINTSTS_ISOODRP (1 << 14) -#define OTG_FS_GINTSTS_ENUMDNE (1 << 13) -#define OTG_FS_GINTSTS_USBRST (1 << 12) -#define OTG_FS_GINTSTS_USBSUSP (1 << 11) -#define OTG_FS_GINTSTS_ESUSP (1 << 10) -/* Bits 9:8 - Reserved */ -#define OTG_FS_GINTSTS_GONAKEFF (1 << 7) -#define OTG_FS_GINTSTS_GINAKEFF (1 << 6) -#define OTG_FS_GINTSTS_NPTXFE (1 << 5) -#define OTG_FS_GINTSTS_RXFLVL (1 << 4) -#define OTG_FS_GINTSTS_SOF (1 << 3) -#define OTG_FS_GINTSTS_OTGINT (1 << 2) -#define OTG_FS_GINTSTS_MMIS (1 << 1) -#define OTG_FS_GINTSTS_CMOD (1 << 0) - -/* OTG_FS interrupt mask register (OTG_FS_GINTMSK) */ -#define OTG_FS_GINTMSK_MMISM 0x00000002 -#define OTG_FS_GINTMSK_OTGINT 0x00000004 -#define OTG_FS_GINTMSK_SOFM 0x00000008 -#define OTG_FS_GINTMSK_RXFLVLM 0x00000010 -#define OTG_FS_GINTMSK_NPTXFEM 0x00000020 -#define OTG_FS_GINTMSK_GINAKEFFM 0x00000040 -#define OTG_FS_GINTMSK_GONAKEFFM 0x00000080 -#define OTG_FS_GINTMSK_ESUSPM 0x00000400 -#define OTG_FS_GINTMSK_USBSUSPM 0x00000800 -#define OTG_FS_GINTMSK_USBRST 0x00001000 -#define OTG_FS_GINTMSK_ENUMDNEM 0x00002000 -#define OTG_FS_GINTMSK_ISOODRPM 0x00004000 -#define OTG_FS_GINTMSK_EOPFM 0x00008000 -#define OTG_FS_GINTMSK_EPMISM 0x00020000 -#define OTG_FS_GINTMSK_IEPINT 0x00040000 -#define OTG_FS_GINTMSK_OEPINT 0x00080000 -#define OTG_FS_GINTMSK_IISOIXFRM 0x00100000 -#define OTG_FS_GINTMSK_IISOOXFRM 0x00200000 -#define OTG_FS_GINTMSK_IPXFRM 0x00200000 -#define OTG_FS_GINTMSK_PRTIM 0x01000000 -#define OTG_FS_GINTMSK_HCIM 0x02000000 -#define OTG_FS_GINTMSK_PTXFEM 0x04000000 -#define OTG_FS_GINTMSK_CIDSCHGM 0x10000000 -#define OTG_FS_GINTMSK_DISCINT 0x20000000 -#define OTG_FS_GINTMSK_SRQIM 0x40000000 -#define OTG_FS_GINTMSK_WUIM 0x80000000 - -/* OTG_FS Receive Status Pop Register (OTG_FS_GRXSTSP) */ -/* Bits 31:25 - Reserved */ -#define OTG_FS_GRXSTSP_FRMNUM_MASK (0xf << 21) -#define OTG_FS_GRXSTSP_PKTSTS_MASK (0xf << 17) -#define OTG_FS_GRXSTSP_PKTSTS_GOUTNAK (0x1 << 17) -#define OTG_FS_GRXSTSP_PKTSTS_OUT (0x2 << 17) -#define OTG_FS_GRXSTSP_PKTSTS_OUT_COMP (0x3 << 17) -#define OTG_FS_GRXSTSP_PKTSTS_SETUP_COMP (0x4 << 17) -#define OTG_FS_GRXSTSP_PKTSTS_SETUP (0x6 << 17) -#define OTG_FS_GRXSTSP_DPID_MASK (0x3 << 15) -#define OTG_FS_GRXSTSP_DPID_DATA0 (0x0 << 15) -#define OTG_FS_GRXSTSP_DPID_DATA1 (0x2 << 15) -#define OTG_FS_GRXSTSP_DPID_DATA2 (0x1 << 15) -#define OTG_FS_GRXSTSP_DPID_MDATA (0x3 << 15) -#define OTG_FS_GRXSTSP_BCNT_MASK (0x7ff << 4) -#define OTG_FS_GRXSTSP_EPNUM_MASK (0xf << 0) - -/* OTG_FS general core configuration register (OTG_FS_GCCFG) */ -/* Bits 31:21 - Reserved */ -#define OTG_FS_GCCFG_SOFOUTEN (1 << 20) -#define OTG_FS_GCCFG_VBUSBSEN (1 << 19) -#define OTG_FS_GCCFG_VBUSASEN (1 << 18) -/* Bit 17 - Reserved */ -#define OTG_FS_GCCFG_PWRDWN (1 << 16) -/* Bits 15:0 - Reserved */ - - -/* Device-mode CSRs */ -/* OTG_FS device control register (OTG_FS_DCTL) */ -/* Bits 31:12 - Reserved */ -#define OTG_FS_DCTL_POPRGDNE (1 << 11) -#define OTG_FS_DCTL_CGONAK (1 << 10) -#define OTG_FS_DCTL_SGONAK (1 << 9) -#define OTG_FS_DCTL_SGINAK (1 << 8) -#define OTG_FS_DCTL_TCTL_MASK (7 << 4) -#define OTG_FS_DCTL_GONSTS (1 << 3) -#define OTG_FS_DCTL_GINSTS (1 << 2) -#define OTG_FS_DCTL_SDIS (1 << 1) -#define OTG_FS_DCTL_RWUSIG (1 << 0) - -/* OTG_FS device configuration register (OTG_FS_DCFG) */ -#define OTG_FS_DCFG_DSPD 0x0003 -#define OTG_FS_DCFG_NZLSOHSK 0x0004 -#define OTG_FS_DCFG_DAD 0x07F0 -#define OTG_FS_DCFG_PFIVL 0x1800 - -/* OTG_FS Device IN Endpoint Common Interrupt Mask Register (OTG_FS_DIEPMSK) */ -/* Bits 31:10 - Reserved */ -#define OTG_FS_DIEPMSK_BIM (1 << 9) -#define OTG_FS_DIEPMSK_TXFURM (1 << 8) -/* Bit 7 - Reserved */ -#define OTG_FS_DIEPMSK_INEPNEM (1 << 6) -#define OTG_FS_DIEPMSK_INEPNMM (1 << 5) -#define OTG_FS_DIEPMSK_ITTXFEMSK (1 << 4) -#define OTG_FS_DIEPMSK_TOM (1 << 3) -/* Bit 2 - Reserved */ -#define OTG_FS_DIEPMSK_EPDM (1 << 1) -#define OTG_FS_DIEPMSK_XFRCM (1 << 0) - -/* OTG_FS Device OUT Endpoint Common Interrupt Mask Register (OTG_FS_DOEPMSK) */ -/* Bits 31:10 - Reserved */ -#define OTG_FS_DOEPMSK_BOIM (1 << 9) -#define OTG_FS_DOEPMSK_OPEM (1 << 8) -/* Bit 7 - Reserved */ -#define OTG_FS_DOEPMSK_B2BSTUP (1 << 6) -/* Bit 5 - Reserved */ -#define OTG_FS_DOEPMSK_OTEPDM (1 << 4) -#define OTG_FS_DOEPMSK_STUPM (1 << 3) -/* Bit 2 - Reserved */ -#define OTG_FS_DOEPMSK_EPDM (1 << 1) -#define OTG_FS_DOEPMSK_XFRCM (1 << 0) - -/* OTG_FS Device Control IN Endpoint 0 Control Register (OTG_FS_DIEPCTL0) */ -#define OTG_FS_DIEPCTL0_EPENA (1 << 31) -#define OTG_FS_DIEPCTL0_EPDIS (1 << 30) -/* Bits 29:28 - Reserved */ -#define OTG_FS_DIEPCTLX_SD0PID (1 << 28) -#define OTG_FS_DIEPCTL0_SNAK (1 << 27) -#define OTG_FS_DIEPCTL0_CNAK (1 << 26) -#define OTG_FS_DIEPCTL0_TXFNUM_MASK (0xf << 22) -#define OTG_FS_DIEPCTL0_STALL (1 << 21) -/* Bit 20 - Reserved */ -#define OTG_FS_DIEPCTL0_EPTYP_MASK (0x3 << 18) -#define OTG_FS_DIEPCTL0_NAKSTS (1 << 17) -/* Bit 16 - Reserved */ -#define OTG_FS_DIEPCTL0_USBAEP (1 << 15) -/* Bits 14:2 - Reserved */ -#define OTG_FS_DIEPCTL0_MPSIZ_MASK (0x3 << 0) -#define OTG_FS_DIEPCTL0_MPSIZ_64 (0x0 << 0) -#define OTG_FS_DIEPCTL0_MPSIZ_32 (0x1 << 0) -#define OTG_FS_DIEPCTL0_MPSIZ_16 (0x2 << 0) -#define OTG_FS_DIEPCTL0_MPSIZ_8 (0x3 << 0) - -/* OTG_FS Device Control OUT Endpoint 0 Control Register (OTG_FS_DOEPCTL0) */ -#define OTG_FS_DOEPCTL0_EPENA (1 << 31) -#define OTG_FS_DOEPCTL0_EPDIS (1 << 30) -/* Bits 29:28 - Reserved */ -#define OTG_FS_DOEPCTLX_SD0PID (1 << 28) -#define OTG_FS_DOEPCTL0_SNAK (1 << 27) -#define OTG_FS_DOEPCTL0_CNAK (1 << 26) -/* Bits 25:22 - Reserved */ -#define OTG_FS_DOEPCTL0_STALL (1 << 21) -#define OTG_FS_DOEPCTL0_SNPM (1 << 20) -#define OTG_FS_DOEPCTL0_EPTYP_MASK (0x3 << 18) -#define OTG_FS_DOEPCTL0_NAKSTS (1 << 17) -/* Bit 16 - Reserved */ -#define OTG_FS_DOEPCTL0_USBAEP (1 << 15) -/* Bits 14:2 - Reserved */ -#define OTG_FS_DOEPCTL0_MPSIZ_MASK (0x3 << 0) -#define OTG_FS_DOEPCTL0_MPSIZ_64 (0x0 << 0) -#define OTG_FS_DOEPCTL0_MPSIZ_32 (0x1 << 0) -#define OTG_FS_DOEPCTL0_MPSIZ_16 (0x2 << 0) -#define OTG_FS_DOEPCTL0_MPSIZ_8 (0x3 << 0) - -/* OTG_FS Device IN Endpoint Interrupt Register (OTG_FS_DIEPINTx) */ -/* Bits 31:8 - Reserved */ -#define OTG_FS_DIEPINTX_TXFE (1 << 7) -#define OTG_FS_DIEPINTX_INEPNE (1 << 6) -/* Bit 5 - Reserved */ -#define OTG_FS_DIEPINTX_ITTXFE (1 << 4) -#define OTG_FS_DIEPINTX_TOC (1 << 3) -/* Bit 2 - Reserved */ -#define OTG_FS_DIEPINTX_EPDISD (1 << 1) -#define OTG_FS_DIEPINTX_XFRC (1 << 0) - -/* OTG_FS Device IN Endpoint Interrupt Register (OTG_FS_DOEPINTx) */ -/* Bits 31:7 - Reserved */ -#define OTG_FS_DOEPINTX_B2BSTUP (1 << 6) -/* Bit 5 - Reserved */ -#define OTG_FS_DOEPINTX_OTEPDIS (1 << 4) -#define OTG_FS_DOEPINTX_STUP (1 << 3) -/* Bit 2 - Reserved */ -#define OTG_FS_DOEPINTX_EPDISD (1 << 1) -#define OTG_FS_DOEPINTX_XFRC (1 << 0) - -/* OTG_FS Device OUT Endpoint 0 Transfer Size Regsiter (OTG_FS_DOEPTSIZ0) */ -/* Bit 31 - Reserved */ -#define OTG_FS_DIEPSIZ0_STUPCNT_1 (0x1 << 29) -#define OTG_FS_DIEPSIZ0_STUPCNT_2 (0x2 << 29) -#define OTG_FS_DIEPSIZ0_STUPCNT_3 (0x3 << 29) -#define OTG_FS_DIEPSIZ0_STUPCNT_MASK (0x3 << 29) -/* Bits 28:20 - Reserved */ -#define OTG_FS_DIEPSIZ0_PKTCNT (1 << 19) -/* Bits 18:7 - Reserved */ -#define OTG_FS_DIEPSIZ0_XFRSIZ_MASK (0x7f << 0) - -#endif - diff --git a/include/libopencm3/stm32f1/rcc.h b/include/libopencm3/stm32f1/rcc.h deleted file mode 100644 index 1072445..0000000 --- a/include/libopencm3/stm32f1/rcc.h +++ /dev/null @@ -1,417 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * Copyright (C) 2009 Federico Ruiz-Ugalde - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_RCC_H -#define LIBOPENCM3_RCC_H - -#include -#include - -/* Note: Regs/bits marked (**) only exist in "connectivity line" STM32s. */ -/* Note: Regs/bits marked (XX) do NOT exist in "connectivity line" STM32s. */ - -/* --- RCC registers ------------------------------------------------------- */ - -#define RCC_CR MMIO32(RCC_BASE + 0x00) -#define RCC_CFGR MMIO32(RCC_BASE + 0x04) -#define RCC_CIR MMIO32(RCC_BASE + 0x08) -#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x0c) -#define RCC_APB1RSTR MMIO32(RCC_BASE + 0x10) -#define RCC_AHBENR MMIO32(RCC_BASE + 0x14) -#define RCC_APB2ENR MMIO32(RCC_BASE + 0x18) -#define RCC_APB1ENR MMIO32(RCC_BASE + 0x1c) -#define RCC_BDCR MMIO32(RCC_BASE + 0x20) -#define RCC_CSR MMIO32(RCC_BASE + 0x24) -#define RCC_AHBRSTR MMIO32(RCC_BASE + 0x28) /* (**) */ -#define RCC_CFGR2 MMIO32(RCC_BASE + 0x2c) /* (**) */ - -/* --- RCC_CR values ------------------------------------------------------- */ - -#define RCC_CR_PLL3RDY (1 << 29) /* (**) */ -#define RCC_CR_PLL3ON (1 << 28) /* (**) */ -#define RCC_CR_PLL2RDY (1 << 27) /* (**) */ -#define RCC_CR_PLL2ON (1 << 26) /* (**) */ -#define RCC_CR_PLLRDY (1 << 25) -#define RCC_CR_PLLON (1 << 24) -#define RCC_CR_CSSON (1 << 19) -#define RCC_CR_HSEBYP (1 << 18) -#define RCC_CR_HSERDY (1 << 17) -#define RCC_CR_HSEON (1 << 16) -/* HSICAL: [15:8] */ -/* HSITRIM: [7:3] */ -#define RCC_CR_HSIRDY (1 << 1) -#define RCC_CR_HSION (1 << 0) - -/* --- RCC_CFGR values ----------------------------------------------------- */ - -/* MCO: Microcontroller clock output */ -#define RCC_CFGR_MCO_NOCLK 0x0 -#define RCC_CFGR_MCO_SYSCLK 0x4 -#define RCC_CFGR_MCO_HSICLK 0x5 -#define RCC_CFGR_MCO_HSECLK 0x6 -#define RCC_CFGR_RMCO_PLLCLK_DIV2 0x7 -#define RCC_CFGR_MCO_PLL2CLK 0x8 /* (**) */ -#define RCC_CFGR_MCO_PLL3CLK_DIV2 0x9 /* (**) */ -#define RCC_CFGR_MCO_XT1 0xa /* (**) */ -#define RCC_CFGR_MCO_PLL3 0xb /* (**) */ - -/* USBPRE: USB prescaler (RCC_CFGR[22]) */ -#define RCC_CFGR_USBPRE_PLL_CLK_DIV1_5 0x0 -#define RCC_CFGR_USBPRE_PLL_CLK_NODIV 0x1 - -/* OTGFSPRE: USB OTG FS prescaler (RCC_CFGR[22]; only in conn. line STM32s) */ -#define RCC_CFGR_USBPRE_PLL_VCO_CLK_DIV3 0x0 -#define RCC_CFGR_USBPRE_PLL_VCO_CLK_DIV2 0x1 - -/* PLLMUL: PLL multiplication factor */ -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL2 0x0 /* (XX) */ -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL3 0x1 /* (XX) */ -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL4 0x2 -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL5 0x3 -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL6 0x4 -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL7 0x5 -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL8 0x6 -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL9 0x7 -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL10 0x8 /* (XX) */ -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL11 0x9 /* (XX) */ -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL12 0xa /* (XX) */ -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL13 0xb /* (XX) */ -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL14 0xc /* (XX) */ -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL15 0xd /* 0xd: PLL x 15 */ -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL6_5 0xd /* 0xd: PLL x 6.5 for conn. line */ -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL16 0xe /* (XX) */ -// #define PLLMUL_PLL_CLK_MUL16 0xf /* (XX) */ /* Errata? 17? */ - -/* TODO: conn. line differs. */ -/* PLLXTPRE: HSE divider for PLL entry */ -#define RCC_CFGR_PLLXTPRE_HSE_CLK 0x0 -#define RCC_CFGR_PLLXTPRE_HSE_CLK_DIV2 0x1 - -/* PLLSRC: PLL entry clock source */ -#define RCC_CFGR_PLLSRC_HSI_CLK_DIV2 0x0 -#define RCC_CFGR_PLLSRC_HSE_CLK 0x1 -#define RCC_CFGR_PLLSRC_PREDIV1_CLK 0x1 /* On conn. line */ - -/* ADCPRE: ADC prescaler */ -#define RCC_CFGR_ADCPRE_PCLK2_DIV2 0x0 -#define RCC_CFGR_ADCPRE_PCLK2_DIV4 0x1 -#define RCC_CFGR_ADCPRE_PCLK2_DIV6 0x2 -#define RCC_CFGR_ADCPRE_PCLK2_DIV8 0x3 - -/* PPRE2: APB high-speed prescaler (APB2) */ -#define RCC_CFGR_PPRE2_HCLK_NODIV 0x0 -#define RCC_CFGR_PPRE2_HCLK_DIV2 0x4 -#define RCC_CFGR_PPRE2_HCLK_DIV4 0x5 -#define RCC_CFGR_PPRE2_HCLK_DIV8 0x6 -#define RCC_CFGR_PPRE2_HCLK_DIV16 0x7 - -/* PPRE1: APB low-speed prescaler (APB1) */ -#define RCC_CFGR_PPRE1_HCLK_NODIV 0x0 -#define RCC_CFGR_PPRE1_HCLK_DIV2 0x4 -#define RCC_CFGR_PPRE1_HCLK_DIV4 0x5 -#define RCC_CFGR_PPRE1_HCLK_DIV8 0x6 -#define RCC_CFGR_PPRE1_HCLK_DIV16 0x7 - -/* HPRE: AHB prescaler */ -#define RCC_CFGR_HPRE_SYSCLK_NODIV 0x0 -#define RCC_CFGR_HPRE_SYSCLK_DIV2 0x8 -#define RCC_CFGR_HPRE_SYSCLK_DIV4 0x9 -#define RCC_CFGR_HPRE_SYSCLK_DIV8 0xa -#define RCC_CFGR_HPRE_SYSCLK_DIV16 0xb -#define RCC_CFGR_HPRE_SYSCLK_DIV64 0xc -#define RCC_CFGR_HPRE_SYSCLK_DIV128 0xd -#define RCC_CFGR_HPRE_SYSCLK_DIV256 0xe -#define RCC_CFGR_HPRE_SYSCLK_DIV512 0xf - -/* SWS: System clock switch status */ -#define RCC_CFGR_SWS_SYSCLKSEL_HSICLK 0x0 -#define RCC_CFGR_SWS_SYSCLKSEL_HSECLK 0x1 -#define RCC_CFGR_SWS_SYSCLKSEL_PLLCLK 0x2 - -/* SW: System clock switch */ -#define RCC_CFGR_SW_SYSCLKSEL_HSICLK 0x0 -#define RCC_CFGR_SW_SYSCLKSEL_HSECLK 0x1 -#define RCC_CFGR_SW_SYSCLKSEL_PLLCLK 0x2 - -/* --- RCC_CIR values ------------------------------------------------------ */ - -/* Clock security system interrupt clear bit */ -#define RCC_CIR_CSSC (1 << 23) - -/* OSC ready interrupt clear bits */ -#define RCC_CIR_PLL3RDYC (1 << 22) /* (**) */ -#define RCC_CIR_PLL2RDYC (1 << 21) /* (**) */ -#define RCC_CIR_PLLRDYC (1 << 20) -#define RCC_CIR_HSERDYC (1 << 19) -#define RCC_CIR_HSIRDYC (1 << 18) -#define RCC_CIR_LSERDYC (1 << 17) -#define RCC_CIR_LSIRDYC (1 << 16) - -/* OSC ready interrupt enable bits */ -#define RCC_CIR_PLL3RDYIE (1 << 14) /* (**) */ -#define RCC_CIR_PLL2RDYIE (1 << 13) /* (**) */ -#define RCC_CIR_PLLRDYIE (1 << 12) -#define RCC_CIR_HSERDYIE (1 << 11) -#define RCC_CIR_HSIRDYIE (1 << 10) -#define RCC_CIR_LSERDYIE (1 << 9) -#define RCC_CIR_LSIRDYIE (1 << 8) - -/* Clock security system interrupt flag bit */ -#define RCC_CIR_CSSF (1 << 7) - -/* OSC ready interrupt flag bits */ -#define RCC_CIR_PLL3RDYF (1 << 6) /* (**) */ -#define RCC_CIR_PLL2RDYF (1 << 5) /* (**) */ -#define RCC_CIR_PLLRDYF (1 << 4) -#define RCC_CIR_HSERDYF (1 << 3) -#define RCC_CIR_HSIRDYF (1 << 2) -#define RCC_CIR_LSERDYF (1 << 1) -#define RCC_CIR_LSIRDYF (1 << 0) - -/* --- RCC_APB2RSTR values ------------------------------------------------- */ - -#define RCC_APB2RSTR_ADC3RST (1 << 15) /* (XX) */ -#define RCC_APB2RSTR_USART1RST (1 << 14) -#define RCC_APB2RSTR_TIM8RST (1 << 13) /* (XX) */ -#define RCC_APB2RSTR_SPI1RST (1 << 12) -#define RCC_APB2RSTR_TIM1RST (1 << 11) -#define RCC_APB2RSTR_ADC2RST (1 << 10) -#define RCC_APB2RSTR_ADC1RST (1 << 9) -#define RCC_APB2RSTR_IOPGRST (1 << 8) /* (XX) */ -#define RCC_APB2RSTR_IOPFRST (1 << 7) /* (XX) */ -#define RCC_APB2RSTR_IOPERST (1 << 6) -#define RCC_APB2RSTR_IOPDRST (1 << 5) -#define RCC_APB2RSTR_IOPCRST (1 << 4) -#define RCC_APB2RSTR_IOPBRST (1 << 3) -#define RCC_APB2RSTR_IOPARST (1 << 2) -#define RCC_APB2RSTR_AFIORST (1 << 0) - -/* --- RCC_APB1RSTR values ------------------------------------------------- */ - -#define RCC_APB1RSTR_DACRST (1 << 29) -#define RCC_APB1RSTR_PWRRST (1 << 28) -#define RCC_APB1RSTR_BKPRST (1 << 27) -#define RCC_APB1RSTR_CAN2RST (1 << 26) /* (**) */ -#define RCC_APB1RSTR_CAN1RST (1 << 25) /* (**) */ -#define RCC_APB1RSTR_CANRST (1 << 25) /* (XX) Alias for CAN1RST */ -#define RCC_APB1RSTR_USBRST (1 << 23) /* (XX) */ -#define RCC_APB1RSTR_I2C2RST (1 << 22) -#define RCC_APB1RSTR_I2C1RST (1 << 21) -#define RCC_APB1RSTR_USART5RST (1 << 20) -#define RCC_APB1RSTR_USART4RST (1 << 19) -#define RCC_APB1RSTR_USART3RST (1 << 18) -#define RCC_APB1RSTR_USART2RST (1 << 17) -#define RCC_APB1RSTR_SPI3RST (1 << 15) -#define RCC_APB1RSTR_SPI2RST (1 << 14) -#define RCC_APB1RSTR_WWDGRST (1 << 11) -#define RCC_APB1RSTR_TIM7RST (1 << 5) -#define RCC_APB1RSTR_TIM6RST (1 << 4) -#define RCC_APB1RSTR_TIM5RST (1 << 3) -#define RCC_APB1RSTR_TIM4RST (1 << 2) -#define RCC_APB1RSTR_TIM3RST (1 << 1) -#define RCC_APB1RSTR_TIM2RST (1 << 0) - -/* --- RCC_AHBENR values --------------------------------------------------- */ - -#define RCC_AHBENR_ETHMACENRX (1 << 16) -#define RCC_AHBENR_ETHMACENTX (1 << 15) -#define RCC_AHBENR_ETHMACEN (1 << 14) -#define RCC_AHBENR_OTGFSEN (1 << 12) -#define RCC_AHBENR_SDIOEN (1 << 10) -#define RCC_AHBENR_FSMCEN (1 << 8) -#define RCC_AHBENR_CRCEN (1 << 6) -#define RCC_AHBENR_FLITFEN (1 << 4) -#define RCC_AHBENR_SRAMEN (1 << 2) -#define RCC_AHBENR_DMA2EN (1 << 1) -#define RCC_AHBENR_DMA1EN (1 << 0) - -/* --- RCC_APB2ENR values -------------------------------------------------- */ - -#define RCC_APB2ENR_ADC3EN (1 << 15) /* (XX) */ -#define RCC_APB2ENR_USART1EN (1 << 14) -#define RCC_APB2ENR_TIM8EN (1 << 13) /* (XX) */ -#define RCC_APB2ENR_SPI1EN (1 << 12) -#define RCC_APB2ENR_TIM1EN (1 << 11) -#define RCC_APB2ENR_ADC2EN (1 << 10) -#define RCC_APB2ENR_ADC1EN (1 << 9) -#define RCC_APB2ENR_IOPGEN (1 << 8) /* (XX) */ -#define RCC_APB2ENR_IOPFEN (1 << 7) /* (XX) */ -#define RCC_APB2ENR_IOPEEN (1 << 6) -#define RCC_APB2ENR_IOPDEN (1 << 5) -#define RCC_APB2ENR_IOPCEN (1 << 4) -#define RCC_APB2ENR_IOPBEN (1 << 3) -#define RCC_APB2ENR_IOPAEN (1 << 2) -#define RCC_APB2ENR_AFIOEN (1 << 0) - -/* --- RCC_APB1ENR values -------------------------------------------------- */ - -#define RCC_APB1ENR_DACEN (1 << 29) -#define RCC_APB1ENR_PWREN (1 << 28) -#define RCC_APB1ENR_BKPEN (1 << 27) -#define RCC_APB1ENR_CAN2EN (1 << 26) /* (**) */ -#define RCC_APB1ENR_CAN1EN (1 << 25) /* (**) */ -#define RCC_APB1ENR_CANEN (1 << 25) /* (XX) Alias for CAN1EN */ -#define RCC_APB1ENR_USBEN (1 << 23) /* (XX) */ -#define RCC_APB1ENR_I2C2EN (1 << 22) -#define RCC_APB1ENR_I2C1EN (1 << 21) -#define RCC_APB1ENR_USART5EN (1 << 20) -#define RCC_APB1ENR_USART4EN (1 << 19) -#define RCC_APB1ENR_USART3EN (1 << 18) -#define RCC_APB1ENR_USART2EN (1 << 17) -#define RCC_APB1ENR_SPI3EN (1 << 15) -#define RCC_APB1ENR_SPI2EN (1 << 14) -#define RCC_APB1ENR_WWDGEN (1 << 11) -#define RCC_APB1ENR_TIM7EN (1 << 5) -#define RCC_APB1ENR_TIM6EN (1 << 4) -#define RCC_APB1ENR_TIM5EN (1 << 3) -#define RCC_APB1ENR_TIM4EN (1 << 2) -#define RCC_APB1ENR_TIM3EN (1 << 1) -#define RCC_APB1ENR_TIM2EN (1 << 0) - -/* --- RCC_BDCR values ----------------------------------------------------- */ - -#define RCC_BDCR_BDRST (1 << 16) -#define RCC_BDCR_RTCEN (1 << 15) -/* RCC_BDCR[9:8]: RTCSEL */ -#define RCC_BDCR_LSEBYP (1 << 2) -#define RCC_BDCR_LSERDY (1 << 1) -#define RCC_BDCR_LSEON (1 << 0) - -/* --- RCC_CSR values ------------------------------------------------------ */ - -#define RCC_CSR_LPWRRSTF (1 << 31) -#define RCC_CSR_WWDGRSTF (1 << 30) -#define RCC_CSR_IWDGRSTF (1 << 29) -#define RCC_CSR_SFTRSTF (1 << 28) -#define RCC_CSR_PORRSTF (1 << 27) -#define RCC_CSR_PINRSTF (1 << 26) -#define RCC_CSR_RMVF (1 << 24) -#define RCC_CSR_LSIRDY (1 << 1) -#define RCC_CSR_LSION (1 << 0) - -/* --- RCC_AHBRSTR values -------------------------------------------------- */ - -#define RCC_AHBRSTR_ETHMACRST (1 << 14) -#define RCC_AHBRSTR_OTGFSRST (1 << 12) - -/* --- RCC_CFGR2 values ---------------------------------------------------- */ - -/* I2S3SRC: I2S3 clock source */ -#define RCC_CFGR2_I2S3SRC_SYSCLK 0x0 -#define RCC_CFGR2_I2S3SRC_PLL3_VCO_CLK 0x1 - -/* I2S2SRC: I2S2 clock source */ -#define RCC_CFGR2_I2S2SRC_SYSCLK 0x0 -#define RCC_CFGR2_I2S2SRC_PLL3_VCO_CLK 0x1 - -/* PREDIV1SRC: PREDIV1 entry clock source */ -#define RCC_CFGR2_PREDIV1SRC_HSE_CLK 0x0 -#define RCC_CFGR2_PREDIV1SRC_PLL2_CLK 0x1 - -#define RCC_CFGR2_PLL2MUL (1 << 0) -#define RCC_CFGR2_PREDIV2 (1 << 0) -#define RCC_CFGR2_PREDIV1 (1 << 0) - -/* PLL3MUL: PLL3 multiplication factor */ -#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL8 0x6 -#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL9 0x7 -#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL10 0x8 -#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL11 0x9 -#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL12 0xa -#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL13 0xb -#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL14 0xc -#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL16 0xe -#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL20 0xf - -/* PLL2MUL: PLL2 multiplication factor */ -#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL8 0x6 -#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL9 0x7 -#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL10 0x8 -#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL11 0x9 -#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL12 0xa -#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL13 0xb -#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL14 0xc -#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL16 0xe -#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL20 0xf - -/* PREDIV2: PREDIV2 division factor */ -#define RCC_CFGR2_PREDIV2_NODIV 0x0 -#define RCC_CFGR2_PREDIV2_DIV2 0x1 -#define RCC_CFGR2_PREDIV2_DIV3 0x2 -#define RCC_CFGR2_PREDIV2_DIV4 0x3 -#define RCC_CFGR2_PREDIV2_DIV5 0x4 -#define RCC_CFGR2_PREDIV2_DIV6 0x5 -#define RCC_CFGR2_PREDIV2_DIV7 0x6 -#define RCC_CFGR2_PREDIV2_DIV8 0x7 -#define RCC_CFGR2_PREDIV2_DIV9 0x8 -#define RCC_CFGR2_PREDIV2_DIV10 0x9 -#define RCC_CFGR2_PREDIV2_DIV11 0xa -#define RCC_CFGR2_PREDIV2_DIV12 0xb -#define RCC_CFGR2_PREDIV2_DIV13 0xc -#define RCC_CFGR2_PREDIV2_DIV14 0xd -#define RCC_CFGR2_PREDIV2_DIV15 0xe -#define RCC_CFGR2_PREDIV2_DIV16 0xf - -/* --- Variable definitions ------------------------------------------------ */ -extern u32 rcc_ppre1_frequency; -extern u32 rcc_ppre2_frequency; - -/* --- Function prototypes ------------------------------------------------- */ - -typedef enum { - PLL, HSE, HSI, LSE, LSI -} osc_t; - -void rcc_osc_ready_int_clear(osc_t osc); -void rcc_osc_ready_int_enable(osc_t osc); -void rcc_osc_ready_int_disable(osc_t osc); -int rcc_osc_ready_int_flag(osc_t osc); -void rcc_css_int_clear(void); -int rcc_css_int_flag(void); -void rcc_wait_for_osc_ready(osc_t osc); -void rcc_osc_on(osc_t osc); -void rcc_osc_off(osc_t osc); -void rcc_css_enable(void); -void rcc_css_disable(void); -void rcc_osc_bypass_enable(osc_t osc); -void rcc_osc_bypass_disable(osc_t osc); -void rcc_peripheral_enable_clock(volatile u32 *reg, u32 en); -void rcc_peripheral_disable_clock(volatile u32 *reg, u32 en); -void rcc_peripheral_reset(volatile u32 *reg, u32 reset); -void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset); -void rcc_set_sysclk_source(u32 clk); -void rcc_set_pll_multiplication_factor(u32 mul); -void rcc_set_pll_source(u32 pllsrc); -void rcc_set_pllxtpre(u32 pllxtpre); -void rcc_set_adcpre(u32 adcpre); -void rcc_set_ppre2(u32 ppre2); -void rcc_set_ppre1(u32 ppre1); -void rcc_set_hpre(u32 hpre); -void rcc_set_usbpre(u32 usbpre); -u32 rcc_get_system_clock_source(int i); -void rcc_clock_setup_in_hsi_out_64mhz(void); -void rcc_clock_setup_in_hsi_out_48mhz(void); -void rcc_clock_setup_in_hse_8mhz_out_24mhz(void); -void rcc_clock_setup_in_hse_8mhz_out_72mhz(void); -void rcc_clock_setup_in_hse_12mhz_out_72mhz(void); -void rcc_clock_setup_in_hse_16mhz_out_72mhz(void); -void rcc_backupdomain_reset(void); - -#endif diff --git a/include/libopencm3/stm32f1/rtc.h b/include/libopencm3/stm32f1/rtc.h deleted file mode 100644 index b71525e..0000000 --- a/include/libopencm3/stm32f1/rtc.h +++ /dev/null @@ -1,146 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_RTC_H -#define LIBOPENCM3_RTC_H - -#include -#include -#include - -/* --- RTC registers ------------------------------------------------------- */ - -/* RTC control register high (RTC_CRH) */ -#define RTC_CRH MMIO32(RTC_BASE + 0x00) - -/* RTC control register low (RTC_CRL) */ -#define RTC_CRL MMIO32(RTC_BASE + 0x04) - -/* RTC prescaler load register (RTC_PRLH / RTC_PRLL) */ -#define RTC_PRLH MMIO32(RTC_BASE + 0x08) -#define RTC_PRLL MMIO32(RTC_BASE + 0x0c) - -/* RTC prescaler divider register (RTC_DIVH / RTC_DIVL) */ -#define RTC_DIVH MMIO32(RTC_BASE + 0x10) -#define RTC_DIVL MMIO32(RTC_BASE + 0x14) - -/* RTC counter register (RTC_CNTH / RTC_CNTL) */ -#define RTC_CNTH MMIO32(RTC_BASE + 0x18) -#define RTC_CNTL MMIO32(RTC_BASE + 0x1c) - -/* RTC alarm register high (RTC_ALRH / RTC_ALRL) */ -#define RTC_ALRH MMIO32(RTC_BASE + 0x20) -#define RTC_ALRL MMIO32(RTC_BASE + 0x24) - -/* --- RTC_CRH values -------------------------------------------------------*/ - -/* Note: Bits [15:3] are reserved, and forced to 0 by hardware. */ - -/* OWIE: Overflow interrupt enable */ -#define RTC_CRH_OWIE (1 << 2) - -/* ALRIE: Alarm interrupt enable */ -#define RTC_CRH_ALRIE (1 << 1) - -/* SECIE: Second interrupt enable */ -#define RTC_CRH_SECIE (1 << 0) - -/* --- RTC_CRL values -------------------------------------------------------*/ - -/* Note: Bits [15:6] are reserved, and forced to 0 by hardware. */ - -/* RTOFF: RTC operation OFF */ -#define RTC_CRL_RTOFF (1 << 5) - -/* CNF: Configuration flag */ -#define RTC_CRL_CNF (1 << 4) - -/* RSF: Registers synchronized flag */ -#define RTC_CRL_RSF (1 << 3) - -/* OWF: Overflow flag */ -#define RTC_CRL_OWF (1 << 2) - -/* ALRF: Alarm flag */ -#define RTC_CRL_ALRF (1 << 1) - -/* SECF: Second flag */ -#define RTC_CRL_SECF (1 << 0) - -/* --- RTC_PRLH values ------------------------------------------------------*/ - -/* Note: Bits [15:4] are reserved, and forced to 0 by hardware. */ - -/* TODO */ - -/* --- RTC_PRLL values ------------------------------------------------------*/ - -/* TODO */ - -/* --- RTC_DIVH values ------------------------------------------------------*/ - -/* Bits [15:4] are reserved. */ - -/* TODO */ - -/* --- RTC_DIVL values ------------------------------------------------------*/ - -/* TODO */ - -/* --- RTC_CNTH values ------------------------------------------------------*/ - -/* TODO */ - -/* --- RTC_CNTL values ------------------------------------------------------*/ - -/* TODO */ - -/* --- RTC_ALRH values ------------------------------------------------------*/ - -/* TODO */ - -/* --- RTC_ALRL values ------------------------------------------------------*/ - -/* TODO */ - -/* --- Function prototypes --------------------------------------------------*/ - -typedef enum { - RTC_SEC, RTC_ALR, RTC_OW, -} rtcflag_t; - -void rtc_awake_from_off(osc_t clock_source); -void rtc_enter_config_mode(void); -void rtc_exit_config_mode(void); -void rtc_set_alarm_time(u32 alarm_time); -void rtc_enable_alarm(void); -void rtc_disable_alarm(void); -void rtc_set_prescale_val(u32 prescale_val); -u32 rtc_get_counter_val(void); -u32 rtc_get_prescale_div_val(void); -u32 rtc_get_alarm_val(void); -void rtc_set_counter_val(u32 counter_val); -void rtc_interrupt_enable(rtcflag_t flag_val); -void rtc_interrupt_disable(rtcflag_t flag_val); -void rtc_clear_flag(rtcflag_t flag_val); -u32 rtc_check_flag(rtcflag_t flag_val); -void rtc_awake_from_standby(void); -void rtc_auto_awake(osc_t clock_source, u32 prescale_val); - -#endif diff --git a/include/libopencm3/stm32f1/scb.h b/include/libopencm3/stm32f1/scb.h deleted file mode 100644 index 9594cf1..0000000 --- a/include/libopencm3/stm32f1/scb.h +++ /dev/null @@ -1,300 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_SCB_H -#define LIBOPENCM3_SCB_H - -#include -#include - -/* --- SCB: Registers ------------------------------------------------------ */ - -/* CPUID: CPUID base register */ -#define SCB_CPUID MMIO32(SCB_BASE + 0x00) - -/* ICSR: Interrupt Control State Register */ -#define SCB_ICSR MMIO32(SCB_BASE + 0x04) - -/* VTOR: Vector Table Offset Register */ -#define SCB_VTOR MMIO32(SCB_BASE + 0x08) - -/* AIRCR: Application Interrupt and Reset Control Register */ -#define SCB_AIRCR MMIO32(SCB_BASE + 0x0C) - -/* SCR: System Control Register */ -#define SCB_SCR MMIO32(SCB_BASE + 0x10) - -/* CCR: Configuration Control Register */ -#define SCB_CCR MMIO32(SCB_BASE + 0x14) - -/* SHP: System Handler Priority Registers */ -/* Note: 12 8bit registers */ -#define SCB_SHPR(shpr_id) MMIO8(SCB_BASE + 0x18 + shpr_id) -#define SCB_SHPR1 MMIO8(SCB_BASE + 0x18 + 1) -#define SCB_SHPR2 MMIO8(SCB_BASE + 0x18 + 2) -#define SCB_SHPR3 MMIO8(SCB_BASE + 0x18 + 3) - -/* SHCSR: System Handler Control and State Register */ -#define SCB_SHCSR MMIO32(SCB_BASE + 0x24) - -/* CFSR: Configurable Fault Status Registers */ -#define SCB_CFSR MMIO32(SCB_BASE + 0x28) - -/* HFSR: Hard Fault Status Register */ -#define SCB_HFSR MMIO32(SCB_BASE + 0x2C) - -/* DFSR: Debug Fault Status Register */ -#define SCB_DFSR MMIO32(SCB_BASE + 0x30) - -/* MMFAR: Memory Manage Fault Address Register */ -#define SCB_MMFAR MMIO32(SCB_BASE + 0x34) - -/* BFAR: Bus Fault Address Register */ -#define SCB_BFAR MMIO32(SCB_BASE + 0x38) - -/* AFSR: Auxiliary Fault Status Register */ -#define SCB_AFSR MMIO32(SCB_BASE + 0x3C) - -/* --- SCB values ---------------------------------------------------------- */ - -/* --- SCB_CPUID values ---------------------------------------------------- */ - -/* Implementer[31:24]: Implementer code */ -#define SCP_CPUID_IMPLEMENTER_LSB 24 -/* Variant[23:20]: Variant number */ -#define SCP_CPUID_VARIANT_LSB 20 -/* Constant[19:16]: Reads as 0xF */ -#define SCP_CPUID_CONSTANT_LSB 16 -/* PartNo[15:4]: Part number of the processor */ -#define SCP_CPUID_PARTNO_LSB 4 -/* Revision[3:0]: Revision number */ -#define SCP_CPUID_REVISION_LSB 0 - -/* --- SCB_ICSR values ----------------------------------------------------- */ - -/* NMIPENDSET: NMI set-pending bit */ -#define SCB_ICSR_NMIPENDSET (1 << 31) -/* Bits [30:29]: reserved - must be kept cleared */ -/* PENDSVSET: PendSV set-pending bit */ -#define SCB_ICSR_PENDSVSET (1 << 28) -/* PENDSVCLR: PendSV clear-pending bit */ -#define SCB_ICSR_PENDSVCLR (1 << 27) -/* PENDSTSET: SysTick exception set-pending bit */ -#define SCB_ICSR_PENDSTSET (1 << 26) -/* PENDSTCLR: SysTick exception clear-pending bit */ -#define SCB_ICSR_PENDSTCLR (1 << 25) -/* Bit 24: reserved - must be kept cleared */ -/* Bit 23: reserved for debug - reads as 0 when not in debug mode */ -/* ISRPENDING: Interrupt pending flag, excluding NMI and Faults */ -#define SCB_ICSR_ISRPENDING (1 << 22) -/* VECTPENDING[21:12] Pending vector */ -#define SCB_ICSR_VECTPENDING_LSB 12 -/* RETOBASE: Return to base level */ -#define SCB_ICSR_RETOBASE (1 << 11) -/* Bits [10:9]: reserved - must be kept cleared */ -/* VECTACTIVE[8:0] Active vector */ -#define SCB_ICSR_VECTACTIVE_LSB 0 - -/* --- SCB_VTOR values ----------------------------------------------------- */ - -/* Bits [31:30]: reserved - must be kept cleared */ -/* TBLOFF[29:9]: Vector table base offset field */ -#define SCB_VTOR_TBLOFF_LSB 9 /* inconsistent datasheet - LSB could be 11 */ - -/* --- SCB_AIRCR values ---------------------------------------------------- */ - -/* VECTKEYSTAT[31:16]/ VECTKEY[31:16] Register key */ -#define SCB_AIRCR_VECTKEYSTAT_LSB 16 -#define SCB_AIRCR_VECTKEY 0x05FA0000 -/* ENDIANESS Data endianness bit */ -#define SCB_AIRCR_ENDIANESS (1 << 15) -/* Bits [14:11]: reserved - must be kept cleared */ -/* PRIGROUP[10:8]: Interrupt priority grouping field */ -#define SCB_AIRCR_PRIGROUP_LSB 8 -#define SCB_AIRCR_PRIGROUP_GROUP16_NOSUB 0x3 -#define SCB_AIRCR_PRIGROUP_GROUP8_SUB2 0x4 -#define SCB_AIRCR_PRIGROUP_GROUP4_SUB4 0x5 -#define SCB_AIRCR_PRIGROUP_GROUP2_SUB8 0x6 -#define SCB_AIRCR_PRIGROUP_NOGROUP_SUB16 0x7 -/* Bits [7:3]: reserved - must be kept cleared */ -/* SYSRESETREQ System reset request */ -#define SCB_AIRCR_SYSRESETREQ (1 << 2) -/* VECTCLRACTIVE */ -#define SCB_AIRCR_VECTCLRACTIVE (1 << 1) -/* VECTRESET */ -#define SCB_AIRCR_VECTRESET (1 << 0) - -/* --- SCB_SCR values ------------------------------------------------------ */ - -/* Bits [31:5]: reserved - must be kept cleared */ -/* SEVEONPEND Send Event on Pending bit */ -#define SCB_SCR_SEVEONPEND (1 << 4) -/* Bit 3: reserved - must be kept cleared */ -/* SLEEPDEEP */ -#define SCB_SCR_SLEEPDEEP (1 << 2) -/* SLEEPONEXIT */ -#define SCB_SCR_SLEEPONEXIT (1 << 1) -/* Bit 0: reserved - must be kept cleared */ - -/* --- SCB_CCR values ------------------------------------------------------ */ - -/* Bits [31:10]: reserved - must be kept cleared */ -/* STKALIGN */ -#define SCB_CCR_STKALIGN (1 << 9) -/* BFHFNMIGN */ -#define SCB_CCR_BFHFNMIGN (1 << 8) -/* Bits [7:5]: reserved - must be kept cleared */ -/* DIV_0_TRP */ -#define SCB_CCR_DIV_0_TRP (1 << 4) -/* UNALIGN_TRP */ -#define SCB_CCR_UNALIGN_TRP (1 << 3) -/* Bit 2: reserved - must be kept cleared */ -/* USERSETMPEND */ -#define SCB_CCR_USERSETMPEND (1 << 1) -/* NONBASETHRDENA */ -#define SCB_CCR_NONBASETHRDENA (1 << 0) - -/* --- SCB_SHPR1 values ---------------------------------------------------- */ - -/* Bits [31:24]: reserved - must be kept cleared */ -/* PRI_6[23:16]: Priority of system handler 6, usage fault */ -#define SCB_SHPR1_PRI_6_LSB 16 -/* PRI_5[15:8]: Priority of system handler 5, bus fault */ -#define SCB_SHPR1_PRI_5_LSB 8 -/* PRI_4[7:0]: Priority of system handler 4, memory management fault */ -#define SCB_SHPR1_PRI_4_LSB 0 - -/* --- SCB_SHPR2 values ---------------------------------------------------- */ - -/* PRI_11[31:24]: Priority of system handler 11, SVCall */ -#define SCB_SHPR2_PRI_11_LSB 24 -/* Bits [23:0]: reserved - must be kept cleared */ - -/* --- SCB_SHPR3 values ---------------------------------------------------- */ - -/* PRI_15[31:24]: Priority of system handler 15, SysTick exception */ -#define SCB_SHPR3_PRI_15_LSB 24 -/* PRI_14[23:16]: Priority of system handler 14, PendSV */ -#define SCB_SHPR3_PRI_14_LSB 16 -/* Bits [15:0]: reserved - must be kept cleared */ - -/* --- SCB_SHCSR values ---------------------------------------------------- */ - -/* Bits [31:19]: reserved - must be kept cleared */ -/* USGFAULTENA: Usage fault enable */ -#define SCB_SHCSR_USGFAULTENA (1 << 18) -/* BUSFAULTENA: Bus fault enable */ -#define SCB_SHCSR_BUSFAULTENA (1 << 17) -/* MEMFAULTENA: Memory management fault enable */ -#define SCB_SHCSR_MEMFAULTENA (1 << 16) -/* SVCALLPENDED: SVC call pending */ -#define SCB_SHCSR_SVCALLPENDED (1 << 15) -/* BUSFAULTPENDED: Bus fault exception pending */ -#define SCB_SHCSR_BUSFAULTPENDED (1 << 14) -/* MEMFAULTPENDED: Memory management fault exception pending */ -#define SCB_SHCSR_MEMFAULTPENDED (1 << 13) -/* USGFAULTPENDED: Usage fault exception pending */ -#define SCB_SHCSR_USGFAULTPENDED (1 << 12) -/* SYSTICKACT: SysTick exception active */ -#define SCB_SHCSR_SYSTICKACT (1 << 11) -/* PENDSVACT: PendSV exception active */ -#define SCB_SHCSR_PENDSVACT (1 << 10) -/* Bit 9: reserved - must be kept cleared */ -/* MONITORACT: Debug monitor active */ -#define SCB_SHCSR_MONITORACT (1 << 8) -/* SVCALLACT: SVC call active */ -#define SCB_SHCSR_SVCALLACT (1 << 7) -/* Bits [6:4]: reserved - must be kept cleared */ -/* USGFAULTACT: Usage fault exception active */ -#define SCB_SHCSR_USGFAULTACT (1 << 3) -/* Bit 2: reserved - must be kept cleared */ -/* BUSFAULTACT: Bus fault exception active */ -#define SCB_SHCSR_BUSFAULTACT (1 << 1) -/* MEMFAULTACT: Memory management fault exception active */ -#define SCB_SHCSR_MEMFAULTACT (1 << 0) - -/* --- SCB_CFSR values ----------------------------------------------------- */ - -/* Bits [31:26]: reserved - must be kept cleared */ -/* DIVBYZERO: Divide by zero usage fault */ -#define SCB_CFSR_DIVBYZERO (1 << 25) -/* UNALIGNED: Unaligned access usage fault */ -#define SCB_CFSR_UNALIGNED (1 << 24) -/* Bits [23:20]: reserved - must be kept cleared */ -/* NOCP: No coprocessor usage fault */ -#define SCB_CFSR_NOCP (1 << 19) -/* INVPC: Invalid PC load usage fault */ -#define SCB_CFSR_INVPC (1 << 18) -/* INVSTATE: Invalid state usage fault */ -#define SCB_CFSR_INVSTATE (1 << 17) -/* UNDEFINSTR: Undefined instruction usage fault */ -#define SCB_CFSR_UNDEFINSTR (1 << 16) -/* BFARVALID: Bus Fault Address Register (BFAR) valid flag */ -#define SCB_CFSR_BFARVALID (1 << 15) -/* Bits [14:13]: reserved - must be kept cleared */ -/* STKERR: Bus fault on stacking for exception entry */ -#define SCB_CFSR_STKERR (1 << 12) -/* UNSTKERR: Bus fault on unstacking for a return from exception */ -#define SCB_CFSR_UNSTKERR (1 << 11) -/* IMPRECISERR: Imprecise data bus error */ -#define SCB_CFSR_IMPRECISERR (1 << 10) -/* PRECISERR: Precise data bus error */ -#define SCB_CFSR_PRECISERR (1 << 9) -/* IBUSERR: Instruction bus error */ -#define SCB_CFSR_IBUSERR (1 << 8) -/* MMARVALID: Memory Management Fault Address Register (MMAR) valid flag */ -#define SCB_CFSR_MMARVALID (1 << 7) -/* Bits [6:5]: reserved - must be kept cleared */ -/* MSTKERR: Memory manager fault on stacking for exception entry */ -#define SCB_CFSR_MSTKERR (1 << 4) -/* MUNSTKERR: Memory manager fault on unstacking for a return from exception */ -#define SCB_CFSR_MUNSTKERR (1 << 3) -/* Bit 2: reserved - must be kept cleared */ -/* DACCVIOL: Data access violation flag */ -#define SCB_CFSR_DACCVIOL (1 << 1) -/* IACCVIOL: Instruction access violation flag */ -#define SCB_CFSR_IACCVIOL (1 << 0) - -/* --- SCB_HFSR values ----------------------------------------------------- */ - -/* DEBUG_VT: reserved for debug use */ -#define SCB_HFSR_DEBUG_VT (1 << 31) -/* FORCED: Forced hard fault */ -#define SCB_HFSR_FORCED (1 << 30) -/* Bits [29:2]: reserved - must be kept cleared */ -/* VECTTBL: Vector table hard fault */ -#define SCB_HFSR_VECTTBL (1 << 1) -/* Bit 0: reserved - must be kept cleared */ - -/* --- SCB_MMFAR values ---------------------------------------------------- */ - -/* MMFAR [31:0]: Memory management fault address */ - -/* --- SCB_BFAR values ----------------------------------------------------- */ - -/* BFAR [31:0]: Bus fault address */ - -/* --- SCB functions ------------------------------------------------------- */ -void scb_reset_core(void); -void scb_reset_system(void); - -/* TODO: */ - -#endif diff --git a/include/libopencm3/stm32f1/systick.h b/include/libopencm3/stm32f1/systick.h deleted file mode 100644 index 7c2c9a3..0000000 --- a/include/libopencm3/stm32f1/systick.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_SYSTICK_H -#define LIBOPENCM3_SYSTICK_H - -#include -#include - -/* --- SYSTICK registers --------------------------------------------------- */ - -/* Control and status register (STK_CTRL) */ -#define STK_CTRL MMIO32(SYS_TICK_BASE + 0x00) - -/* reload value register (STK_LOAD) */ -#define STK_LOAD MMIO32(SYS_TICK_BASE + 0x04) - -/* current value register (STK_VAL) */ -#define STK_VAL MMIO32(SYS_TICK_BASE + 0x08) - -/* calibration value register (STK_CALIB) */ -#define STK_CALIB MMIO32(SYS_TICK_BASE + 0x0C) - -/* --- STK_CTRL values ----------------------------------------------------- */ -/* Bits [31:17] Reserved, must be kept cleared. */ -/* COUNTFLAG: */ -#define STK_CTRL_COUNTFLAG (1 << 16) -/* Bits [15:3] Reserved, must be kept cleared. */ -/* CLKSOURCE: Clock source selection */ -#define STK_CTRL_CLKSOURCE (1 << 2) -#define STK_CTRL_CLKSOURCE_LSB 2 -#define STK_CTRL_CLKSOURCE_AHB_DIV8 0 -#define STK_CTRL_CLKSOURCE_AHB 1 -/* TICKINT: SysTick exception request enable */ -#define STK_CTRL_TICKINT (1 << 1) -/* ENABLE: Counter enable */ -#define STK_CTRL_ENABLE (1 << 0) - -/* --- STK_LOAD values ----------------------------------------------------- */ -/* Bits [31:24] Reserved, must be kept cleared. */ -/* RELOAD[23:0]: RELOAD value */ - -/* --- STK_VAL values ------------------------------------------------------ */ -/* Bits [31:24] Reserved, must be kept cleared. */ -/* CURRENT[23:0]: Current counter value */ - -/* --- STK_CALIB values ---------------------------------------------------- */ -/* NOREF: NOREF flag */ -#define STK_CALIB_NOREF (1 << 31) -/* SKEW: SKEW flag */ -#define STK_CALIB_SKEW (1 << 30) -/* Bits [29:24] Reserved, must be kept cleared. */ -/* TENMS[23:0]: Calibration value */ - -/* --- Function Prototypes ------------------------------------------------- */ - -void systick_set_reload(u32 value); -u32 systick_get_value(void); -void systick_set_clocksource(u8 clocksource); -void systick_interrupt_enable(void); -void systick_interrupt_disable(void); -void systick_counter_enable(void); -void systick_counter_disable(void); -u8 systick_get_countflag(void); - -#endif diff --git a/include/libopencm3/stm32f1/tools.h b/include/libopencm3/stm32f1/tools.h deleted file mode 100644 index ac7f0bf..0000000 --- a/include/libopencm3/stm32f1/tools.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Piotr Esden-Tempski - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_TOOLS_H -#define LIBOPENCM3_TOOLS_H - -/* - * Register accessors / manipulators - */ - -/* Get register content. */ -#define GET_REG(REG) ((u16) *REG) - -/* Set register content. */ -#define SET_REG(REG, VAL) (*REG = (u16)VAL) - -/* Clear register bit. */ -#define CLR_REG_BIT(REG, BIT) SET_REG(REG, (~BIT)) - -/* Clear register bit masking out some bits that must not be touched. */ -#define CLR_REG_BIT_MSK(REG, MSK, BIT) \ - SET_REG(REG, (GET_REG(REG) & MSK & (~BIT))) - -/* Get masked out bit value. */ -#define GET_REG_BIT(REG, BIT) (GET_REG(REG) & BIT) - -/* - * Set/reset a bit in a masked window by using toggle mechanism. - * - * This means that we look at the bits in the bit window designated by - * the mask. If the bit in the masked window is not matching the - * bitmask BIT then we write 1 and if the bit in the masked window is - * matching the bitmask BIT we write 0. - * - * TODO: We may need a faster implementation of that one? - */ -#define TOG_SET_REG_BIT_MSK(REG, MSK, BIT) \ -do { \ - register u16 toggle_mask = GET_REG(REG) & (MSK); \ - register u16 bit_selector; \ - for (bit_selector = 1; bit_selector; bit_selector <<= 1) { \ - if ((bit_selector & (BIT)) != 0) \ - toggle_mask ^= bit_selector; \ - } \ - SET_REG(REG, toggle_mask); \ -} while(0) - -#endif diff --git a/include/libopencm3/stm32f1/usb.h b/include/libopencm3/stm32f1/usb.h deleted file mode 100644 index e35075d..0000000 --- a/include/libopencm3/stm32f1/usb.h +++ /dev/null @@ -1,258 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Piotr Esden-Tempski - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_USB_H -#define LIBOPENCM3_USB_H - -#include -#include -#include - -/* --- USB base addresses -------------------------------------------------- */ - -#define USB_PMA_BASE 0x40006000L /* USB packet buffer memory base addr. */ - -/* --- USB general registers ----------------------------------------------- */ - -/* USB Control register */ -#define USB_CNTR_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x40)) -/* USB Interrupt status register */ -#define USB_ISTR_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x44)) -/* USB Frame number register */ -#define USB_FNR_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x48)) -/* USB Device address register */ -#define USB_DADDR_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x4C)) -/* USB Buffer table address register */ -#define USB_BTABLE_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x50)) -/* USB EP register */ -#define USB_EP_REG(EP) ((volatile u32 *)(USB_DEV_FS_BASE) + (EP)) - -/* --- USB control register masks / bits ----------------------------------- */ - -/* Interrupt mask bits, set to 1 to enable interrupt generation */ -#define USB_CNTR_CTRM 0x8000 -#define USB_CNTR_PMAOVRM 0x4000 -#define USB_CNTR_ERRM 0x2000 -#define USB_CNTR_WKUPM 0x1000 -#define USB_CNTR_SUSPM 0x0800 -#define USB_CNTR_RESETM 0x0400 -#define USB_CNTR_SOFM 0x0200 -#define USB_CNTR_ESOFM 0x0100 - -/* Request/Force bits */ -#define USB_CNTR_RESUME 0x0010 /* Resume request */ -#define USB_CNTR_FSUSP 0x0008 /* Force suspend */ -#define USB_CNTR_LP_MODE 0x0004 /* Low-power mode */ -#define USB_CNTR_PWDN 0x0002 /* Power down */ -#define USB_CNTR_FRES 0x0001 /* Force reset */ - -/* --- USB interrupt status register masks / bits -------------------------- */ - -#define USB_ISTR_CTR 0x8000 /* Correct Transfer */ -#define USB_ISTR_PMAOVR 0x4000 /* Packet Memory Area Over / Underrun */ -#define USB_ISTR_ERR 0x2000 /* Error */ -#define USB_ISTR_WKUP 0x1000 /* Wake up */ -#define USB_ISTR_SUSP 0x0800 /* Suspend mode request */ -#define USB_ISTR_RESET 0x0400 /* USB RESET request */ -#define USB_ISTR_SOF 0x0200 /* Start Of Frame */ -#define USB_ISTR_ESOF 0x0100 /* Expected Start Of Frame */ -#define USB_ISTR_DIR 0x0010 /* Direction of transaction */ -#define USB_ISTR_EP_ID 0x000F /* Endpoint Identifier */ - -/* --- USB interrupt status register manipulators -------------------------- */ - -/* Note: CTR is read only! */ -#define USB_CLR_ISTR_PMAOVR() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_PMAOVR) -#define USB_CLR_ISTR_ERR() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_ERR) -#define USB_CLR_ISTR_WKUP() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_WKUP) -#define USB_CLR_ISTR_SUSP() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_SUSP) -#define USB_CLR_ISTR_RESET() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_RESET) -#define USB_CLR_ISTR_SOF() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_SOF) -#define USB_CLR_ISTR_ESOF() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_ESOF) - -/* --- USB device addres register masks / bits ----------------------------- */ - -#define USB_DADDR_ENABLE 0x0080 -#define USB_DADDR_ADDR 0x007F - -/* --- USB device addres register manipulators ----------------------------- */ - -/* --- USB endpoint register offsets --------------------------------------- */ - -#define USB_EP0 0 -#define USB_EP1 1 -#define USB_EP2 2 -#define USB_EP3 3 -#define USB_EP4 4 -#define USB_EP5 5 -#define USB_EP6 6 -#define USB_EP7 7 - -/* --- USB endpoint register masks / bits ---------------------------------- */ - -/* Masks and toggle bits */ -#define USB_EP_RX_CTR 0x8000 /* Correct transfer RX */ -#define USB_EP_RX_DTOG 0x4000 /* Data toggle RX */ -#define USB_EP_RX_STAT 0x3000 /* Endpoint status for RX */ - -#define USB_EP_SETUP 0x0800 /* Setup transaction completed */ -#define USB_EP_TYPE 0x0600 /* Endpoint type */ -#define USB_EP_KIND 0x0100 /* Endpoint kind. - * When set and type=bulk -> double buffer - * When set and type=control -> status out - */ - -#define USB_EP_TX_CTR 0x0080 /* Correct transfer TX */ -#define USB_EP_TX_DTOG 0x0040 /* Data toggle TX */ -#define USB_EP_TX_STAT 0x0030 /* Endpoint status for TX */ - -#define USB_EP_ADDR 0x000F /* Endpoint Address */ - -/* Masking all toggle bits */ -#define USB_EP_NTOGGLE_MSK (USB_EP_RX_CTR | \ - USB_EP_SETUP | \ - USB_EP_TYPE | \ - USB_EP_KIND | \ - USB_EP_TX_CTR | \ - USB_EP_ADDR) - -/* All non toggle bits plus EP_RX toggle bits */ -#define USB_EP_RX_STAT_TOG_MSK (USB_EP_RX_STAT | USB_EP_NTOGGLE_MSK) -/* All non toggle bits plus EP_TX toggle bits */ -#define USB_EP_TX_STAT_TOG_MSK (USB_EP_TX_STAT | USB_EP_NTOGGLE_MSK) - -/* Endpoint status bits for USB_EP_RX_STAT bit field */ -#define USB_EP_RX_STAT_DISABLED 0x0000 -#define USB_EP_RX_STAT_STALL 0x1000 -#define USB_EP_RX_STAT_NAK 0x2000 -#define USB_EP_RX_STAT_VALID 0x3000 - -/* Endpoint status bits for USB_EP_TX_STAT bit field */ -#define USB_EP_TX_STAT_DISABLED 0x0000 -#define USB_EP_TX_STAT_STALL 0x0010 -#define USB_EP_TX_STAT_NAK 0x0020 -#define USB_EP_TX_STAT_VALID 0x0030 - -/* Endpoint type bits for USB_EP_TYPE bit field */ -#define USB_EP_TYPE_BULK 0x0000 -#define USB_EP_TYPE_CONTROL 0x0200 -#define USB_EP_TYPE_ISO 0x0400 -#define USB_EP_TYPE_INTERRUPT 0x0600 - -/* --- USB endpoint register manipulators ---------------------------------- */ - -/* - * Set USB endpoint tx/rx status. - * - * USB status field is changed using an awkward toggle mechanism, that - * is why we use some helper macros for that. - */ -#define USB_SET_EP_RX_STAT(EP, STAT) \ - TOG_SET_REG_BIT_MSK(USB_EP_REG(EP), USB_EP_RX_STAT_TOG_MSK, STAT) - -#define USB_SET_EP_TX_STAT(EP, STAT) \ - TOG_SET_REG_BIT_MSK(USB_EP_REG(EP), USB_EP_TX_STAT_TOG_MSK, STAT) - -/* - * Macros for clearing and setting USB endpoint register bits that do - * not use the toggle mechanism. - * - * Because the register contains some bits that use the toggle - * mechanism we need a helper macro here. Otherwise the code gets really messy. - */ -#define USB_CLR_EP_NTOGGLE_BIT(EP, BIT) \ - CLR_REG_BIT_MSK(USB_EP_REG(EP), USB_EP_NTOGGLE_MSK, BIT) - -#define USB_CLR_EP_RX_CTR(EP) \ - USB_CLR_EP_NTOGGLE_BIT(EP, USB_EP_RX_CTR) - -#define USB_CLR_EP_TX_CTR(EP) \ - USB_CLR_EP_NTOGGLE_BIT(EP, USB_EP_TX_CTR) - -#define USB_SET_EP_TYPE(EP, TYPE) \ - SET_REG(USB_EP_REG(EP), \ - (GET_REG(USB_EP_REG(EP)) & \ - (USB_EP_NTOGGLE_MSK & \ - (~USB_EP_TYPE))) | TYPE) - -#define USB_SET_EP_KIND(EP) \ - SET_REG(USB_EP_REG(EP), \ - (GET_REG(USB_EP_REG(EP)) & \ - (USB_EP_NTOGGLE_MSK & \ - (~USB_EP_KIND))) | USB_EP_KIND) - -#define USB_CLR_EP_KIND(EP) \ - SET_REG(USB_EP_REG(EP), \ - (GET_REG(USB_EP_REG(EP)) & \ - (USB_EP_NTOGGLE_MSK & (~USB_EP_KIND)))) - -#define USB_SET_EP_STAT_OUT(EP) USB_SET_EP_KIND(EP) -#define USB_CLR_EP_STAT_OUT(EP) USB_CLR_EP_KIND(EP) - -#define USB_SET_EP_ADDR(EP, ADDR) \ - SET_REG(USB_EP_REG(EP), \ - ((GET_REG(USB_EP_REG(EP)) & \ - (USB_EP_NTOGGLE_MSK & \ - (~USB_EP_ADDR))) | ADDR)) - -/* Macros for clearing DTOG bits */ -#define USB_CLR_EP_TX_DTOG(EP) \ - SET_REG(USB_EP_REG(EP), \ - GET_REG(USB_EP_REG(EP)) & \ - (USB_EP_NTOGGLE_MSK | USB_EP_TX_DTOG)) - -#define USB_CLR_EP_RX_DTOG(EP) \ - SET_REG(USB_EP_REG(EP), \ - GET_REG(USB_EP_REG(EP)) & \ - (USB_EP_NTOGGLE_MSK | USB_EP_RX_DTOG)) - -/* --- USB BTABLE registers ------------------------------------------------ */ - -#define USB_GET_BTABLE GET_REG(USB_BTABLE_REG) - -#define USB_EP_TX_ADDR(EP) \ - ((u32 *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 0) * 2)) - -#define USB_EP_TX_COUNT(EP) \ - ((u32 *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 2) * 2)) - -#define USB_EP_RX_ADDR(EP) \ - ((u32 *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 4) * 2)) - -#define USB_EP_RX_COUNT(EP) \ - ((u32 *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 6) * 2)) - -/* --- USB BTABLE manipulators --------------------------------------------- */ - -#define USB_GET_EP_TX_ADDR(EP) GET_REG(USB_EP_TX_ADDR(EP)) -#define USB_GET_EP_TX_COUNT(EP) GET_REG(USB_EP_TX_COUNT(EP)) -#define USB_GET_EP_RX_ADDR(EP) GET_REG(USB_EP_RX_ADDR(EP)) -#define USB_GET_EP_RX_COUNT(EP) GET_REG(USB_EP_RX_COUNT(EP)) -#define USB_SET_EP_TX_ADDR(EP, ADDR) SET_REG(USB_EP_TX_ADDR(EP), ADDR) -#define USB_SET_EP_TX_COUNT(EP, COUNT) SET_REG(USB_EP_TX_COUNT(EP), COUNT) -#define USB_SET_EP_RX_ADDR(EP, ADDR) SET_REG(USB_EP_RX_ADDR(EP), ADDR) -#define USB_SET_EP_RX_COUNT(EP, COUNT) SET_REG(USB_EP_RX_COUNT(EP), COUNT) - -#define USB_GET_EP_TX_BUFF(EP) \ - (USB_PMA_BASE + (u8 *)(USB_GET_EP_TX_ADDR(EP) * 2)) - -#define USB_GET_EP_RX_BUFF(EP) \ - (USB_PMA_BASE + (u8 *)(USB_GET_EP_RX_ADDR(EP) * 2)) - -#endif diff --git a/include/libopencm3/stm32f1/usb_desc.h b/include/libopencm3/stm32f1/usb_desc.h deleted file mode 100644 index da99bb0..0000000 --- a/include/libopencm3/stm32f1/usb_desc.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Piotr Esden-Tempski - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_USB_DESC -#define LIBOPENCM3_USB_DESC - -/* Descriptor types */ -#define USB_DT_DEVICE 0x01 -#define USB_DT_CONF 0x02 -#define USB_DT_STRING 0x03 -#define USB_DT_INTERFACE 0x04 -#define USB_DT_ENDPOINT 0x05 - -struct usb_desc_head { - u8 length; /* Descriptor size 0x012 */ - u8 type; /* Descriptor type ID */ -}; - -struct usb_device_desc { - struct usb_desc_head h; /* Size 0x12, ID 0x01 */ - u16 bcd_usb; /* USB Version */ - u8 class; /* Device class */ - u8 sub_class; /* Subclass code */ - u8 protocol; /* Protocol code */ - u8 max_psize; /* Maximum packet size -> 64bytes */ - u16 vendor; /* Vendor number */ - u16 product; /* Device number */ - u16 bcd_dev; /* Device version */ - u8 man_desc; /* Index of manufacturer string desc */ - u8 prod_desc; /* Index of product string desc */ - u8 sn_desc; /* Index of serial number string desc */ - u8 num_conf; /* Number of possible configurations */ -}; - -struct usb_conf_desc_header { - struct usb_desc_head h; /* Size 0x09, Id 0x02 */ - u16 tot_leng; /* Total length of data */ - u8 num_int; /* Number of interfaces */ - u8 conf_val; /* Configuration selector */ - u8 conf_desc; /* Index of conf string desc */ - u8 attr; /* Attribute bitmap: - * 7 : Bus powered - * 6 : Self powered - * 5 : Remote wakeup - * 4..0 : Reserved -> 0000 - */ - u8 max_power; /* Maximum power consumption in 2mA steps */ -}; - -struct usb_int_desc_header { - struct usb_desc_head h; /* Size 0x09, Id 0x04 */ - u8 iface_num; /* Interface id number */ - u8 alt_setting; /* Alternative setting selector */ - u8 num_endp; /* Endpoints used */ - u8 class; /* Interface class */ - u8 sub_class; /* Subclass code */ - u8 protocol; /* Protocol code */ - u8 iface_desc; /* Index of interface string desc */ -}; - -struct usb_ep_desc { - struct usb_desc_head h; /* Size 0x07, Id 0x05 */ - u8 ep_addr; /* Endpoint address: - 0..3 : Endpoint Number - 4..6 : Reserved -> 0 - 7 : Direction 0=out 1=in */ - u8 ep_attr; /* Endpoint attributes */ - u16 max_psize; /* Maximum packet size -> 64bytes */ - u8 interval; /* Interval for polling endpoint - data. Ignored for bulk & control - endpoints. */ -}; - -struct usb_conf_desc { - struct usb_conf_desc_header cdh; - struct usb_int_desc_header idh; - struct usb_ep_desc ep[]; -}; - -struct usb_string_desc { - struct usb_desc_head h; /* Size > 0x02, Id 0x03 */ - u16 string[]; /* String UTF16 encoded */ -}; - -#endif diff --git a/include/libopencm3/stm32f2/memorymap.h b/include/libopencm3/stm32f2/memorymap.h deleted file mode 100644 index 9fe77fa..0000000 --- a/include/libopencm3/stm32f2/memorymap.h +++ /dev/null @@ -1,131 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Fergus Noble - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_MEMORYMAP_H -#define LIBOPENCM3_MEMORYMAP_H - -#include - -/* --- STM32F20x specific peripheral definitions ------------------------------- */ - -/* Memory map for all busses */ -#define PERIPH_BASE 0x40000000 -#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000) -#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000) -#define PERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000) -#define PERIPH_BASE_AHB2 0x50000000 -#define PERIPH_BASE_AHB3 0x60000000 - -/* Register boundary addresses */ - -/* APB1 */ -#define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000) -#define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400) -#define TIM4_BASE (PERIPH_BASE_APB1 + 0x0800) -#define TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00) -#define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000) -#define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400) -#define TIM12_BASE (PERIPH_BASE_APB1 + 0x1800) -#define TIM13_BASE (PERIPH_BASE_APB1 + 0x1c00) -#define TIM14_BASE (PERIPH_BASE_APB1 + 0x2000) -/* PERIPH_BASE_APB1 + 0x2400 (0x4000 2400 - 0x4000 27FF): Reserved */ -#define RTC_BASE (PERIPH_BASE_APB1 + 0x2800) -#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00) -#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000) -/* PERIPH_BASE_APB1 + 0x3400 (0x4000 3400 - 0x4000 37FF): Reserved */ -#define SPI2_I2S_BASE (PERIPH_BASE_APB1 + 0x3800) -#define SPI3_I2S_BASE (PERIPH_BASE_APB1 + 0x3c00) -/* PERIPH_BASE_APB1 + 0x4000 (0x4000 4000 - 0x4000 3FFF): Reserved */ -#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400) -#define USART3_BASE (PERIPH_BASE_APB1 + 0x4800) -#define UART4_BASE (PERIPH_BASE_APB1 + 0x4c00) -#define UART5_BASE (PERIPH_BASE_APB1 + 0x5000) -#define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400) -#define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800) -#define I2C3_BASE (PERIPH_BASE_APB1 + 0x5C00) -/* PERIPH_BASE_APB1 + 0x6000 (0x4000 6000 - 0x4000 63FF): Reserved */ -#define BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400) -#define BX_CAN2_BASE (PERIPH_BASE_APB1 + 0x6800) -/* PERIPH_BASE_APB1 + 0x6C00 (0x4000 6C00 - 0x4000 6FFF): Reserved */ -#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000) -#define DAC_BASE (PERIPH_BASE_APB1 + 0x7400) -/* PERIPH_BASE_APB1 + 0x7800 (0x4000 7800 - 0x4000 FFFF): Reserved */ - -/* APB2 */ -#define TIM1_BASE (PERIPH_BASE_APB2 + 0x0000) -#define TIM8_BASE (PERIPH_BASE_APB2 + 0x0400) -/* PERIPH_BASE_APB2 + 0x0800 (0x4001 0800 - 0x4001 0FFF): Reserved */ -#define USART1_BASE (PERIPH_BASE_APB2 + 0x1000) -#define USART6_BASE (PERIPH_BASE_APB2 + 0x1400) -/* PERIPH_BASE_APB2 + 0x1800 (0x4001 1800 - 0x4001 1FFF): Reserved */ -#define ADC1_BASE (PERIPH_BASE_APB2 + 0x2000) -#define ADC2_BASE (PERIPH_BASE_APB2 + 0x2000) -#define ADC3_BASE (PERIPH_BASE_APB2 + 0x2000) -/* PERIPH_BASE_APB2 + 0x2400 (0x4001 2400 - 0x4001 27FF): Reserved */ -#define SDIO_BASE (PERIPH_BASE_APB2 + 0x2800) -/* PERIPH_BASE_APB2 + 0x2C00 (0x4001 2C00 - 0x4001 2FFF): Reserved */ -#define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000) -/* PERIPH_BASE_APB2 + 0x3400 (0x4001 3400 - 0x4001 37FF): Reserved */ -#define SYSCFG_BASE (PERIPH_BASE_APB2 + 0x3800) -#define EXTI_BASE (PERIPH_BASE_APB2 + 0x3C00) -#define TIM9_BASE (PERIPH_BASE_APB2 + 0x4000) -#define TIM10_BASE (PERIPH_BASE_APB2 + 0x4400) -#define TIM11_BASE (PERIPH_BASE_APB2 + 0x4800) -/* PERIPH_BASE_APB2 + 0x4C00 (0x4001 4C00 - 0x4001 FFFF): Reserved */ - -/* AHB1 */ -#define GPIO_PORT_A_BASE (PERIPH_BASE_AHB1 + 0x0000) -#define GPIO_PORT_B_BASE (PERIPH_BASE_AHB1 + 0x0400) -#define GPIO_PORT_C_BASE (PERIPH_BASE_AHB1 + 0x0800) -#define GPIO_PORT_D_BASE (PERIPH_BASE_AHB1 + 0x0C00) -#define GPIO_PORT_E_BASE (PERIPH_BASE_AHB1 + 0x1000) -#define GPIO_PORT_F_BASE (PERIPH_BASE_AHB1 + 0x1400) -#define GPIO_PORT_G_BASE (PERIPH_BASE_AHB1 + 0x1800) -#define GPIO_PORT_H_BASE (PERIPH_BASE_AHB1 + 0x1C00) -#define GPIO_PORT_I_BASE (PERIPH_BASE_AHB1 + 0x2000) -/* PERIPH_BASE_AHB1 + 0x2400 (0x4002 2400 - 0x4002 2FFF): Reserved */ -#define CRC_BASE (PERIPH_BASE_AHB1 + 0x3000) -/* PERIPH_BASE_AHB1 + 0x3400 (0x4002 3400 - 0x4002 37FF): Reserved */ -#define RCC_BASE (PERIPH_BASE_AHB1 + 0x3800) -#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x3C00) -#define BKPSRAM_BASE (PERIPH_BASE_AHB1 + 0x4000) -/* PERIPH_BASE_AHB1 + 0x5000 (0x4002 5000 - 0x4002 5FFF): Reserved */ -#define DMA1_BASE (PERIPH_BASE_AHB1 + 0x6000) -#define DMA2_BASE (PERIPH_BASE_AHB1 + 0x6400) -/* PERIPH_BASE_AHB1 + 0x6800 (0x4002 6800 - 0x4002 7FFF): Reserved */ -#define ETHERNET_BASE (PERIPH_BASE_AHB1 + 0x8000) -/* PERIPH_BASE_AHB1 + 0x9400 (0x4002 9400 - 0x4003 FFFF): Reserved */ -#define USB_OTG_HS_BASE (PERIPH_BASE_AHB1 + 0x20000) -/* PERIPH_BASE_AHB1 + 0x60000 (0x4008 0000 - 0x4FFF FFFF): Reserved */ - -/* AHB2 */ -#define USB_OTG_FS_BASE (PERIPH_BASE_AHB2 + 0x0000) -/* PERIPH_BASE_AHB2 + 0x40000 (0x5004 0000 - 0x5004 FFFF): Reserved */ -#define DCMI_BASE (PERIPH_BASE_AHB2 + 0x50000) -/* PERIPH_BASE_AHB2 + 0x50400 (0x5005 0400 - 0x5006 07FF): Reserved */ -#define RNG_BASE (PERIPH_BASE_AHB2 + 0x60800) -/* PERIPH_BASE_AHB2 + 0x61000 (0x5006 1000 - 0x5FFF FFFF): Reserved */ - -/* AHB3 */ -#define FSMC_BASE (PERIPH_BASE_AHB3 + 0x40000000) - -/* PPIB */ -#define DBGMCU_BASE (PPBI_BASE + 0x00042000) - -#endif diff --git a/include/libopencm3/stm32f2/pwr.h b/include/libopencm3/stm32f2/pwr.h deleted file mode 100644 index 49b3383..0000000 --- a/include/libopencm3/stm32f2/pwr.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Fergus Noble - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_PWR_F2_H -#define LIBOPENCM3_PWR_F2_H - -#include - -/* - * This file extends the version in stm_common with definitions only - * applicable to the STM32F2 series of devices. - */ - -/* --- PWR_CR values ------------------------------------------------------- */ - -/* FPDS: Flash power down in stop mode, only available in F2 family devices. */ -#define PWR_CR_FPDS (1 << 9) - -/* --- PWR_CSR values ------------------------------------------------------ */ - -/* BRE: Backup regulator enable */ -#define PWR_CSR_BRE (1 << 9) - -#endif diff --git a/include/libopencm3/stm32f2/spi.h b/include/libopencm3/stm32f2/spi.h deleted file mode 100644 index d4aa02e..0000000 --- a/include/libopencm3/stm32f2/spi.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Fergus Noble - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_SPI_F2_H -#define LIBOPENCM3_SPI_F2_H - -#include - -/* - * This file extends the version in stm_common with definitions only - * applicable to the STM32F2 series of devices. - */ - -/* --- SPI_CR2 values ------------------------------------------------------ */ - -/* FRF: Frame format. */ -#define SPI_CR2_FRF (1 << 4) -#define SPI_CR2_FRF_TI (1 << 4) -#define SPI_CR2_FRF_MOTOROLA (1 << 4) - -/* --- SPI_SR values ------------------------------------------------------- */ - -/* TIFRFE: TI frame format error. */ -#define SPI_SR_RXNE (1 << 0) - -#endif diff --git a/include/libopencm3/stm32f2/timer.h b/include/libopencm3/stm32f2/timer.h deleted file mode 100644 index f7c82ae..0000000 --- a/include/libopencm3/stm32f2/timer.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Fergus Noble - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_TIMER_F2_H -#define LIBOPENCM3_TIMER_F2_H - -#include - - -/* - * TIM2 and TIM5 are now 32bit and the following registers are now 32-bit wide: - * CNT, ARR, CCR1, CCR2, CCR3, CCR4 - */ - -/* Timer 2/5 option register (TIMx_OR) */ -#define TIM_OR(tim_base) MMIO32(tim_base + 0x50) -#define TIM2_OR TIM_OR(TIM2) -#define TIM5_OR TIM_OR(TIM5) - -/* --- TIM2_OR values ---------------------------------------------------- */ - -/* MOE: Main output enable */ -#define TIM2_OR_ITR1_RMP_TIM8_TRGOUT (0x0 << 10) -#define TIM2_OR_ITR1_RMP_PTP (0x1 << 10) -#define TIM2_OR_ITR1_RMP_OTG_FS_SOF (0x2 << 10) -#define TIM2_OR_ITR1_RMP_OTG_HS_SOF (0x3 << 10) -#define TIM2_OR_ITR1_RMP_MASK (0x3 << 10) - -/* --- TIM5_OR values ---------------------------------------------------- */ - -/* MOE: Main output enable */ -#define TIM5_OR_TI4_RMP_GPIO (0x0 << 6) -#define TIM5_OR_TI4_RMP_LSI (0x1 << 6) -#define TIM5_OR_TI4_RMP_LSE (0x2 << 6) -#define TIM5_OR_TI4_RMP_RTC (0x3 << 6) -#define TIM5_OR_TI4_RMP_MASK (0x3 << 6) - -#endif diff --git a/include/libopencm3/stm32f2/usart.h b/include/libopencm3/stm32f2/usart.h deleted file mode 100644 index 8d1caca..0000000 --- a/include/libopencm3/stm32f2/usart.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Fergus Noble - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_USART_F2_H -#define LIBOPENCM3_USART_F2_H - -#include - -/* --- USART_CR1 values ---------------------------------------------------- */ - -/* OVER8: Oversampling mode */ -#define USART_CR1_OVER8 (1 << 15) - -/* --- USART_CR3 values ---------------------------------------------------- */ - -/* ONEBIT: One sample bit method enable */ -#define USART_CR3_ONEBIT (1 << 11) - -#endif -- cgit v1.2.3 From 95d4532595369b09bd48e9f7706b0ddef3149985 Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Wed, 14 Sep 2011 22:36:15 -0700 Subject: Initial import of F2 GPIO peripheral header file. --- include/libopencm3/stm32/f2/gpio.h | 274 +++++++++++++++++++++++++++++++++++++ 1 file changed, 274 insertions(+) create mode 100644 include/libopencm3/stm32/f2/gpio.h diff --git a/include/libopencm3/stm32/f2/gpio.h b/include/libopencm3/stm32/f2/gpio.h new file mode 100644 index 0000000..3339311 --- /dev/null +++ b/include/libopencm3/stm32/f2/gpio.h @@ -0,0 +1,274 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Fergus Noble + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_GPIO_H +#define LIBOPENCM3_GPIO_H + +#include +#include + +/* --- Convenience macros -------------------------------------------------- */ + +/* GPIO port base addresses (for convenience) */ +#define GPIOA GPIO_PORT_A_BASE +#define GPIOB GPIO_PORT_B_BASE +#define GPIOC GPIO_PORT_C_BASE +#define GPIOD GPIO_PORT_D_BASE +#define GPIOE GPIO_PORT_E_BASE +#define GPIOF GPIO_PORT_F_BASE +#define GPIOG GPIO_PORT_G_BASE +#define GPIOH GPIO_PORT_H_BASE +#define GPIOI GPIO_PORT_I_BASE + +/* GPIO number definitions (for convenience) */ +#define GPIO0 (1 << 0) +#define GPIO1 (1 << 1) +#define GPIO2 (1 << 2) +#define GPIO3 (1 << 3) +#define GPIO4 (1 << 4) +#define GPIO5 (1 << 5) +#define GPIO6 (1 << 6) +#define GPIO7 (1 << 7) +#define GPIO8 (1 << 8) +#define GPIO9 (1 << 9) +#define GPIO10 (1 << 10) +#define GPIO11 (1 << 11) +#define GPIO12 (1 << 12) +#define GPIO13 (1 << 13) +#define GPIO14 (1 << 14) +#define GPIO15 (1 << 15) +#define GPIO_ALL 0xffff + +/* --- GPIO registers ------------------------------------------------------ */ + +/* Port mode register (GPIOx_MODER) */ +#define GPIO_MODER(port) MMIO32(port + 0x00) +#define GPIOA_MODER GPIO_MODER(GPIOA) +#define GPIOB_MODER GPIO_MODER(GPIOB) +#define GPIOC_MODER GPIO_MODER(GPIOC) +#define GPIOD_MODER GPIO_MODER(GPIOD) +#define GPIOE_MODER GPIO_MODER(GPIOE) +#define GPIOF_MODER GPIO_MODER(GPIOF) +#define GPIOG_MODER GPIO_MODER(GPIOG) +#define GPIOH_MODER GPIO_MODER(GPIOH) +#define GPIOI_MODER GPIO_MODER(GPIOI) + +/* Port output type register (GPIOx_OTYPER) */ +#define GPIO_OTYPER(port) MMIO32(port + 0x04) +#define GPIOA_OTYPER GPIO_OTYPER(GPIOA) +#define GPIOB_OTYPER GPIO_OTYPER(GPIOB) +#define GPIOC_OTYPER GPIO_OTYPER(GPIOC) +#define GPIOD_OTYPER GPIO_OTYPER(GPIOD) +#define GPIOE_OTYPER GPIO_OTYPER(GPIOE) +#define GPIOF_OTYPER GPIO_OTYPER(GPIOF) +#define GPIOG_OTYPER GPIO_OTYPER(GPIOG) +#define GPIOH_OTYPER GPIO_OTYPER(GPIOH) +#define GPIOI_OTYPER GPIO_OTYPER(GPIOI) + +/* Port output speed register (GPIOx_OSPEEDR) */ +#define GPIO_OSPEEDR(port) MMIO32(port + 0x08) +#define GPIOA_OSPEEDR GPIO_OSPEEDR(GPIOA) +#define GPIOB_OSPEEDR GPIO_OSPEEDR(GPIOB) +#define GPIOC_OSPEEDR GPIO_OSPEEDR(GPIOC) +#define GPIOD_OSPEEDR GPIO_OSPEEDR(GPIOD) +#define GPIOE_OSPEEDR GPIO_OSPEEDR(GPIOE) +#define GPIOF_OSPEEDR GPIO_OSPEEDR(GPIOF) +#define GPIOG_OSPEEDR GPIO_OSPEEDR(GPIOG) +#define GPIOH_OSPEEDR GPIO_OSPEEDR(GPIOH) +#define GPIOI_OSPEEDR GPIO_OSPEEDR(GPIOI) + +/* Port pull-up/pull-down register (GPIOx_PUPDR) */ +#define GPIO_PUPDR(port) MMIO32(port + 0x0C) +#define GPIOA_PUPDR GPIO_PUPDR(GPIOA) +#define GPIOB_PUPDR GPIO_PUPDR(GPIOB) +#define GPIOC_PUPDR GPIO_PUPDR(GPIOC) +#define GPIOD_PUPDR GPIO_PUPDR(GPIOD) +#define GPIOE_PUPDR GPIO_PUPDR(GPIOE) +#define GPIOF_PUPDR GPIO_PUPDR(GPIOF) +#define GPIOG_PUPDR GPIO_PUPDR(GPIOG) +#define GPIOH_PUPDR GPIO_PUPDR(GPIOH) +#define GPIOI_PUPDR GPIO_PUPDR(GPIOI) + +/* Port input data register (GPIOx_IDR) */ +#define GPIO_IDR(port) MMIO32(port + 0x10) +#define GPIOA_IDR GPIO_IDR(GPIOA) +#define GPIOB_IDR GPIO_IDR(GPIOB) +#define GPIOC_IDR GPIO_IDR(GPIOC) +#define GPIOD_IDR GPIO_IDR(GPIOD) +#define GPIOE_IDR GPIO_IDR(GPIOE) +#define GPIOF_IDR GPIO_IDR(GPIOF) +#define GPIOG_IDR GPIO_IDR(GPIOG) +#define GPIOH_IDR GPIO_IDR(GPIOH) +#define GPIOI_IDR GPIO_IDR(GPIOI) + +/* Port output data register (GPIOx_ODR) */ +#define GPIO_ODR(port) MMIO32(port + 0x14) +#define GPIOA_ODR GPIO_ODR(GPIOA) +#define GPIOB_ODR GPIO_ODR(GPIOB) +#define GPIOC_ODR GPIO_ODR(GPIOC) +#define GPIOD_ODR GPIO_ODR(GPIOD) +#define GPIOE_ODR GPIO_ODR(GPIOE) +#define GPIOF_ODR GPIO_ODR(GPIOF) +#define GPIOG_ODR GPIO_ODR(GPIOG) +#define GPIOH_ODR GPIO_ODR(GPIOH) +#define GPIOI_ODR GPIO_ODR(GPIOI) + +/* Port bit set/reset register (GPIOx_BSRR) */ +#define GPIO_BSRR(port) MMIO32(port + 0x18) +#define GPIOA_BSRR GPIO_BSRR(GPIOA) +#define GPIOB_BSRR GPIO_BSRR(GPIOB) +#define GPIOC_BSRR GPIO_BSRR(GPIOC) +#define GPIOD_BSRR GPIO_BSRR(GPIOD) +#define GPIOE_BSRR GPIO_BSRR(GPIOE) +#define GPIOF_BSRR GPIO_BSRR(GPIOF) +#define GPIOG_BSRR GPIO_BSRR(GPIOG) +#define GPIOH_BSRR GPIO_BSRR(GPIOH) +#define GPIOI_BSRR GPIO_BSRR(GPIOI) + +/* Port configuration lock register (GPIOx_LCKR) */ +#define GPIO_LCKR(port) MMIO32(port + 0x1C) +#define GPIOA_LCKR GPIO_LCKR(GPIOA) +#define GPIOB_LCKR GPIO_LCKR(GPIOB) +#define GPIOC_LCKR GPIO_LCKR(GPIOC) +#define GPIOD_LCKR GPIO_LCKR(GPIOD) +#define GPIOE_LCKR GPIO_LCKR(GPIOE) +#define GPIOF_LCKR GPIO_LCKR(GPIOF) +#define GPIOG_LCKR GPIO_LCKR(GPIOG) +#define GPIOH_LCKR GPIO_LCKR(GPIOH) +#define GPIOI_LCKR GPIO_LCKR(GPIOI) + +/* Alternate function low register (GPIOx_AFRL) */ +#define GPIO_AFRL(port) MMIO32(port + 0x20) +#define GPIOA_AFRL GPIO_AFRL(GPIOA) +#define GPIOB_AFRL GPIO_AFRL(GPIOB) +#define GPIOC_AFRL GPIO_AFRL(GPIOC) +#define GPIOD_AFRL GPIO_AFRL(GPIOD) +#define GPIOE_AFRL GPIO_AFRL(GPIOE) +#define GPIOF_AFRL GPIO_AFRL(GPIOF) +#define GPIOG_AFRL GPIO_AFRL(GPIOG) +#define GPIOH_AFRL GPIO_AFRL(GPIOH) +#define GPIOI_AFRL GPIO_AFRL(GPIOI) + +/* Alternate function high register (GPIOx_AFRH) */ +#define GPIO_AFRH(port) MMIO32(port + 0x24) +#define GPIOA_AFRH GPIO_AFRH(GPIOA) +#define GPIOB_AFRH GPIO_AFRH(GPIOB) +#define GPIOC_AFRH GPIO_AFRH(GPIOC) +#define GPIOD_AFRH GPIO_AFRH(GPIOD) +#define GPIOE_AFRH GPIO_AFRH(GPIOE) +#define GPIOF_AFRH GPIO_AFRH(GPIOF) +#define GPIOG_AFRH GPIO_AFRH(GPIOG) +#define GPIOH_AFRH GPIO_AFRH(GPIOH) +#define GPIOI_AFRH GPIO_AFRH(GPIOI) + +/* --- GPIOx_MODER values -------------------------------------------------- */ + +#define GPIO_MODE(n, mode) (mode << (2*n)) +#define GPIO_MODE_INPUT 0x0 +#define GPIO_MODE_OUTPUT 0x1 +#define GPIO_MODE_AF 0x2 +#define GPIO_MODE_ANALOG 0x3 + +/* --- GPIOx_OTYPER values ------------------------------------------------- */ + +#define GPIO_OTYPE_PP 0x0 +#define GPIO_OTYPE_OD 0x1 + +/* --- GPIOx_OSPEEDR values ------------------------------------------------ */ + +#define GPIO_OSPEED(n, speed) (speed << (2*n)) +#define GPIO_OSPEED_2MHZ 0x0 +#define GPIO_OSPEED_25MHZ 0x1 +#define GPIO_OSPEED_50MHZ 0x2 +#define GPIO_OSPEED_100MHZ 0x3 + +/* --- GPIOx_PUPDR values -------------------------------------------------- */ + +#define GPIO_PUPD(n, pupd) (pupd << (2*n)) +#define GPIO_PUPD_NONE 0x0 +#define GPIO_PUPD_PULLUP 0x1 +#define GPIO_PUPD_PULLDOWN 0x2 + +/* --- GPIOx_IDR values ---------------------------------------------------- */ + +/* GPIOx_IDR[15:0]: IDRy[15:0]: Port input data (y = 0..15) */ + +/* --- GPIOx_ODR values ---------------------------------------------------- */ + +/* GPIOx_ODR[15:0]: ODRy[15:0]: Port output data (y = 0..15) */ + +/* --- GPIOx_BSRR values --------------------------------------------------- */ + +/* GPIOx_BSRR[31:16]: BRy: Port x reset bit y (y = 0..15) */ +/* GPIOx_BSRR[15:0]: BSy: Port x set bit y (y = 0..15) */ + +/* --- GPIOx_LCKR values --------------------------------------------------- */ + +#define GPIO_LCKK (1 << 16) +/* GPIOx_LCKR[15:0]: LCKy: Port x lock bit y (y = 0..15) */ + +/* --- GPIOx_AFRL/H values ------------------------------------------------- */ + +/* Note: AFRL is used for bits 0..7, AFRH is used for 8..15 */ +/* See Datasheet Table 6 (pg. 48) for alternate function mappings. */ + +#define GPIO_AFR(n, af) (af << (n*4)) +#define GPIO_AF0 0x0 +#define GPIO_AF1 0x1 +#define GPIO_AF2 0x2 +#define GPIO_AF3 0x3 +#define GPIO_AF4 0x4 +#define GPIO_AF5 0x5 +#define GPIO_AF6 0x6 +#define GPIO_AF7 0x7 +#define GPIO_AF8 0x8 +#define GPIO_AF9 0x9 +#define GPIO_AF10 0xA +#define GPIO_AF11 0xB +#define GPIO_AF12 0xC +#define GPIO_AF13 0xD +#define GPIO_AF14 0xE +#define GPIO_AF15 0xF + +/* Note: EXTI source selection is now in the SYSCFG peripheral. */ + +/* --- Function prototypes ------------------------------------------------- */ + +/* + * Note: The F2 series has a completely new GPIO peripheral with different + * configuration options. Here we implement a different API partly to more + * closely match the peripheral capabilities and also to deliberately break + * compatibility with old F1 code so there is no confusion with similar + * sounding functions that have very different functionality. + */ + +void gpio_mode_setup(u32 gpioport, u8 mode, u8 pull_up_down, u16 gpios); +void gpio_set_output_options(u32 gpioport, u8 otype, u8 speed, u16 gpios); +void gpio_set_af(u32 gpioport, u8 alt_func_num, u16 gpios); + +/* This part of the API is compatible with the F1 series */ +void gpio_set(u32 gpioport, u16 gpios); +void gpio_clear(u32 gpioport, u16 gpios); +u16 gpio_get(u32 gpioport, u16 gpios); +void gpio_toggle(u32 gpioport, u16 gpios); +u16 gpio_port_read(u32 gpioport); +void gpio_port_write(u32 gpioport, u16 data); +void gpio_port_config_lock(u32 gpioport, u16 gpios); + +#endif -- cgit v1.2.3 From 60dcacccb7ae8f80ca224e38abdfca1236d1871e Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Wed, 14 Sep 2011 23:57:43 -0700 Subject: Some updates to the F2 GPIO header plus implementation of GPIO convenience functions. --- include/libopencm3/stm32/f2/gpio.h | 14 ++-- lib/stm32f2/gpio.c | 156 +++++++++++++++++++++++++++++++++++++ 2 files changed, 165 insertions(+), 5 deletions(-) create mode 100644 lib/stm32f2/gpio.c diff --git a/include/libopencm3/stm32/f2/gpio.h b/include/libopencm3/stm32/f2/gpio.h index 3339311..b4fb4f3 100644 --- a/include/libopencm3/stm32/f2/gpio.h +++ b/include/libopencm3/stm32/f2/gpio.h @@ -179,7 +179,8 @@ /* --- GPIOx_MODER values -------------------------------------------------- */ -#define GPIO_MODE(n, mode) (mode << (2*n)) +#define GPIO_MODE(n, mode) (mode << (2*(n))) +#define GPIO_MODE_MASK(n) (0x3 << (2*(n))) #define GPIO_MODE_INPUT 0x0 #define GPIO_MODE_OUTPUT 0x1 #define GPIO_MODE_AF 0x2 @@ -192,7 +193,8 @@ /* --- GPIOx_OSPEEDR values ------------------------------------------------ */ -#define GPIO_OSPEED(n, speed) (speed << (2*n)) +#define GPIO_OSPEED(n, speed) (speed << (2*(n))) +#define GPIO_OSPEED_MASK(n) (0x3 << (2*(n))) #define GPIO_OSPEED_2MHZ 0x0 #define GPIO_OSPEED_25MHZ 0x1 #define GPIO_OSPEED_50MHZ 0x2 @@ -200,7 +202,8 @@ /* --- GPIOx_PUPDR values -------------------------------------------------- */ -#define GPIO_PUPD(n, pupd) (pupd << (2*n)) +#define GPIO_PUPD(n, pupd) (pupd << (2*(n))) +#define GPIO_PUPD_MASK(n) (0x3 << (2*(n))) #define GPIO_PUPD_NONE 0x0 #define GPIO_PUPD_PULLUP 0x1 #define GPIO_PUPD_PULLDOWN 0x2 @@ -228,7 +231,8 @@ /* Note: AFRL is used for bits 0..7, AFRH is used for 8..15 */ /* See Datasheet Table 6 (pg. 48) for alternate function mappings. */ -#define GPIO_AFR(n, af) (af << (n*4)) +#define GPIO_AFR(n, af) (af << ((n)*4)) +#define GPIO_AFR_MASK(n) (0xF << ((n)*4)) #define GPIO_AF0 0x0 #define GPIO_AF1 0x1 #define GPIO_AF2 0x2 @@ -262,7 +266,7 @@ void gpio_mode_setup(u32 gpioport, u8 mode, u8 pull_up_down, u16 gpios); void gpio_set_output_options(u32 gpioport, u8 otype, u8 speed, u16 gpios); void gpio_set_af(u32 gpioport, u8 alt_func_num, u16 gpios); -/* This part of the API is compatible with the F1 series */ +/* This part of the API is compatible with the F1 series ------------------- */ void gpio_set(u32 gpioport, u16 gpios); void gpio_clear(u32 gpioport, u16 gpios); u16 gpio_get(u32 gpioport, u16 gpios); diff --git a/lib/stm32f2/gpio.c b/lib/stm32f2/gpio.c new file mode 100644 index 0000000..f2ea55a --- /dev/null +++ b/lib/stm32f2/gpio.c @@ -0,0 +1,156 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Fergus Noble + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* + * Basic GPIO handling API. + * + * Examples: + * gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_2_MHZ, + * GPIO_CNF_OUTPUT_PUSHPULL, GPIO12); + * gpio_set(GPIOB, GPIO4); + * gpio_clear(GPIOG, GPIO2 | GPIO9); + * gpio_get(GPIOC, GPIO1); + * gpio_toggle(GPIOA, GPIO7 | GPIO8); + * reg16 = gpio_port_read(GPIOD); + * gpio_port_write(GPIOF, 0xc8fe); + * + * TODO: + * - GPIO remapping support + */ + +#include + +void gpio_mode_setup(u32 gpioport, u8 mode, u8 pull_up_down, u16 gpios) +{ + u16 i; + u16 moder, pupd; + + /* + * We want to set the config only for the pins mentioned in gpios, + * but keeping the others, so read out the actual config first. + */ + moder = GPIO_MODER(gpioport); + pupd = GPIO_PUPDR(gpioport); + + for (i = 0; i < 16; i++) { + if (!((1 << i) & gpios)) + continue; + + moder &= ~GPIO_MODE_MASK(i); + moder |= GPIO_MODE(i, mode); + pupd &= ~GPIO_PUPD_MASK(i); + pupd |= GPIO_PUPD(i, pull_up_down); + } + + /* Set mode and pull up/down control registers. */ + GPIO_MODER(gpioport) = moder; + GPIO_PUPDR(gpioport) = pupd; +} + +void gpio_set_output_options(u32 gpioport, u8 otype, u8 speed, u16 gpios) +{ + u16 i; + u16 ospeedr; + + if (otype == 0x1) + GPIO_OTYPER(gpioport) |= gpios; + else + GPIO_OTYPER(gpioport) &= ~gpios; + + ospeedr = GPIO_OSPEEDR(gpioport); + + for (i = 0; i < 16; i++) { + if (!((1 << i) & gpios)) + continue + ospeedr &= ~GPIO_OSPEEDR_MASK(i); + ospeedr |= GPIO_OSPEEDR(i, mode); + } + + GPIO_OSPEEDR(gpioport) = ospeedr; +} + +void gpio_set_af(u32 gpioport, u8 alt_func_num, u16 gpios) +{ + u16 i; + u16 afrl, afrh; + + afrl = GPIO_AFRL(gpioport); + afrh = GPIO_AFRH(gpioport); + + for (i = 0; i < 8; i++) { + if (!((1 << i) & gpios)) + continue + afrl &= GPIO_AFR_MASK(i); + afrl |= GPIO_AFR(i, alt_func_num); + } + + for (i = 8; i < 16; i++) { + if (!((1 << i) & gpios)) + continue + afrl &= GPIO_AFR_MASK(i-8); + afrh |= GPIO_AFR(i-8, alt_func_num); + } + + GPIO_AFRL(gpioport) = afrl; + GPIO_AFRH(gpioport) = afrh; +} + +void gpio_set(u32 gpioport, u16 gpios) +{ + GPIO_BSRR(gpioport) = gpios; +} + +void gpio_clear(u32 gpioport, u16 gpios) +{ + GPIO_BSRR(gpioport) = gpios << 16; +} + +u16 gpio_get(u32 gpioport, u16 gpios) +{ + return gpio_port_read(gpioport) & gpios; +} + +void gpio_toggle(u32 gpioport, u16 gpios) +{ + GPIO_ODR(gpioport) = GPIO_IDR(gpioport) ^ gpios; +} + +u16 gpio_port_read(u32 gpioport) +{ + return (u16)GPIO_IDR(gpioport); +} + +void gpio_port_write(u32 gpioport, u16 data) +{ + GPIO_ODR(gpioport) = data; +} + +void gpio_port_config_lock(u32 gpioport, u16 gpios) +{ + u32 reg32; + + /* Special "Lock Key Writing Sequence", see datasheet. */ + GPIO_LCKR(gpioport) = GPIO_LCKK | gpios; /* Set LCKK. */ + GPIO_LCKR(gpioport) = ~GPIO_LCKK & gpios; /* Clear LCKK. */ + GPIO_LCKR(gpioport) = GPIO_LCKK | gpios; /* Set LCKK. */ + reg32 = GPIO_LCKR(gpioport); /* Read LCKK. */ + reg32 = GPIO_LCKR(gpioport); /* Read LCKK again. */ + + /* If (reg32 & GPIO_LCKK) is true, the lock is now active. */ +} -- cgit v1.2.3 From 8da449679988e32d35359fa8a952ec8d2ed07297 Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Thu, 15 Sep 2011 00:05:57 -0700 Subject: Adding stm32f2 target in top level Makefile and renaming f1 target. --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index fe06961..e693516 100644 --- a/Makefile +++ b/Makefile @@ -25,7 +25,7 @@ LIBDIR = $(DESTDIR)/$(PREFIX)/lib SHAREDIR = $(DESTDIR)/$(PREFIX)/share/libopencm3/scripts INSTALL = install -TARGETS = stm32 lpc13xx lm3s +TARGETS = stm32f1 stm32f2 lpc13xx lm3s # Be silent per default, but 'make V=1' will show all compiler calls. ifneq ($(V),1) -- cgit v1.2.3 From 775288bc1326e7a6a03a1b60db6dac88e26f0c5a Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Thu, 15 Sep 2011 00:06:35 -0700 Subject: Renaming things in the F1 target Makefile. --- lib/stm32f1/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/stm32f1/Makefile b/lib/stm32f1/Makefile index 5f26c29..3d154aa 100644 --- a/lib/stm32f1/Makefile +++ b/lib/stm32f1/Makefile @@ -17,7 +17,7 @@ ## along with this program. If not, see . ## -LIBNAME = libopencm3_stm32 +LIBNAME = libopencm3_stm32f1 PREFIX ?= arm-none-eabi #PREFIX ?= arm-elf @@ -51,7 +51,7 @@ $(LIBNAME).a: $(OBJS) $(Q)$(CC) $(CFLAGS) -o $@ -c $< clean: - @printf " CLEAN lib/stm32\n" + @printf " CLEAN lib/stm32f1\n" $(Q)rm -f *.o *.d $(Q)rm -f $(LIBNAME).a -- cgit v1.2.3 From 8a2cf9dd4b1ff3d14a67ee1545f1f58644170240 Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Thu, 15 Sep 2011 00:07:14 -0700 Subject: Copying F1 linker script over to the F2 target, hopefully it should be the same! --- lib/stm32f2/libopencm3_stm32f2.ld | 63 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) create mode 100644 lib/stm32f2/libopencm3_stm32f2.ld diff --git a/lib/stm32f2/libopencm3_stm32f2.ld b/lib/stm32f2/libopencm3_stm32f2.ld new file mode 100644 index 0000000..fda7d02 --- /dev/null +++ b/lib/stm32f2/libopencm3_stm32f2.ld @@ -0,0 +1,63 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Generic linker script for STM32 targets using libopencm3. */ + +/* Memory regions must be defined in the ld script which includes this one. */ + +/* Enforce emmition of the vector table. */ +EXTERN (vector_table) + +/* Define sections. */ +SECTIONS +{ + . = ORIGIN(rom); + + .text : { + *(.vectors) /* Vector table */ + *(.text*) /* Program code */ + *(.rodata*) /* Read-only data */ + _etext = .; + } >rom + + . = ORIGIN(ram); + + .data : { + _data = .; + *(.data*) /* Read-write initialized data */ + _edata = .; + } >ram AT >rom + + .bss : { + *(.bss*) /* Read-write zero initialized data */ + *(COMMON) + _ebss = .; + } >ram AT >rom + + /* + * The .eh_frame section appears to be used for C++ exception handling. + * You may need to fix this if you're using C++. + */ + /DISCARD/ : { *(.eh_frame) } + + end = .; +} + +PROVIDE(_stack = 0x20000800); + -- cgit v1.2.3 From 7524b0f4c56e4b9785eac47ffe0fcbc4553d349e Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Thu, 15 Sep 2011 00:59:30 -0700 Subject: Adding vector table for F2. --- lib/stm32f2/vector.c | 336 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 336 insertions(+) create mode 100644 lib/stm32f2/vector.c diff --git a/lib/stm32f2/vector.c b/lib/stm32f2/vector.c new file mode 100644 index 0000000..d6f70f8 --- /dev/null +++ b/lib/stm32f2/vector.c @@ -0,0 +1,336 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Piotr Esden-Tempski + * Copyright (C) 2011 Fergus Noble + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#define WEAK __attribute__ ((weak)) + +/* Symbols exported by linker script */ +extern unsigned _etext, _data, _edata, _ebss, _stack; + +void main(void); +void reset_handler(void); +void blocking_handler(void); +void null_handler(void); + +void WEAK reset_handler(void); +void WEAK nmi_handler(void); +void WEAK hard_fault_handler(void); +void WEAK mem_manage_handler(void); +void WEAK bus_fault_handler(void); +void WEAK usage_fault_handler(void); +void WEAK sv_call_handler(void); +void WEAK debug_monitor_handler(void); +void WEAK pend_sv_handler(void); +void WEAK sys_tick_handler(void); +void WEAK wwdg_isr(void); +void WEAK pvd_isr(void); +void WEAK tamp_stamp_isr(void); +void WEAK rtc_wkup_isr(void); +void WEAK flash_isr(void); +void WEAK rcc_isr(void); +void WEAK exti0_isr(void); +void WEAK exti1_isr(void); +void WEAK exti2_isr(void); +void WEAK exti3_isr(void); +void WEAK exti4_isr(void); +void WEAK dma1_stream0_isr(void); +void WEAK dma1_stream1_isr(void); +void WEAK dma1_stream2_isr(void); +void WEAK dma1_stream3_isr(void); +void WEAK dma1_stream4_isr(void); +void WEAK dma1_stream5_isr(void); +void WEAK dma1_stream6_isr(void); +void WEAK adc_isr(void); +void WEAK can1_tx_isr(void); +void WEAK can1_rx0_isr(void); +void WEAK can1_rx1_isr(void); +void WEAK can1_sce_isr(void); +void WEAK exti9_5_isr(void); +void WEAK tim1_brk_tim9_isr(void); +void WEAK tim1_up_tim10_isr(void); +void WEAK tim1_trg_com_tim11_isr(void); +void WEAK tim1_cc_isr(void); +void WEAK tim2_isr(void); +void WEAK tim3_isr(void); +void WEAK tim4_isr(void); +void WEAK i2c1_ev_isr(void); +void WEAK i2c1_er_isr(void); +void WEAK i2c2_ev_isr(void); +void WEAK i2c2_er_isr(void); +void WEAK spi1_isr(void); +void WEAK spi2_isr(void); +void WEAK usart1_isr(void); +void WEAK usart2_isr(void); +void WEAK usart3_isr(void); +void WEAK exti15_10_isr(void); +void WEAK rtc_alarm_isr(void); +void WEAK usb_fs_wkup_isr(void); +void WEAK tim8_brk_tim12_isr(void); +void WEAK tim8_up_tim13_isr(void); +void WEAK tim8_trg_com_tim14_isr(void); +void WEAK tim8_cc_isr(void); +void WEAK dma1_stream7_isr(void); +void WEAK fsmc_isr(void); +void WEAK sdio_isr(void); +void WEAK tim5_isr(void); +void WEAK spi3_isr(void); +void WEAK usart4_isr(void); +void WEAK usart5_isr(void); +void WEAK tim6_dac_isr(void); +void WEAK tim7_isr(void); +void WEAK dma2_stream0_isr(void); +void WEAK dma2_stream1_isr(void); +void WEAK dma2_stream2_isr(void); +void WEAK dma2_stream3_isr(void); +void WEAK dma2_stream4_isr(void); +void WEAK eth_isr(void); +void WEAK eth_wkup_isr(void); +void WEAK can2_tx_isr(void); +void WEAK can2_rx0_isr(void); +void WEAK can2_rx1_isr(void); +void WEAK can2_sce_isr(void); +void WEAK otg_fs_isr(void); +void WEAK dma2_stream5_isr(void); +void WEAK dma2_stream6_isr(void); +void WEAK dma2_stream7_isr(void); +void WEAK usart6_isr(void); +void WEAK i2c3_ev_isr(void); +void WEAK i2c3_er_isr(void); +void WEAK otg_hs_ep1_out_isr(void); +void WEAK otg_hs_ep1_in_isr(void); +void WEAK otg_hs_wkup_isr(void); +void WEAK otg_hs_isr(void); +void WEAK dcmi_isr(void); +void WEAK cryp_isr(void); +void WEAK hash_rng_isr(void); + +__attribute__ ((section(".vectors"))) +void (*const vector_table[]) (void) = { + (void*)&_stack, + reset_handler, + nmi_handler, + hard_fault_handler, + mem_manage_handler, + bus_fault_handler, + usage_fault_handler, + 0, 0, 0, 0, /* Reserved */ + sv_call_handler, + debug_monitor_handler, + 0, /* Reserved */ + pend_sv_handler, + sys_tick_handler, + wwdg_isr, + pvd_isr, + tamp_stamp_isr, + rtc_wkup_isr, + flash_isr, + rcc_isr, + exti0_isr, + exti1_isr, + exti2_isr, + exti3_isr, + exti4_isr, + dma1_stream0_isr, + dma1_stream1_isr, + dma1_stream2_isr, + dma1_stream3_isr, + dma1_stream4_isr, + dma1_stream5_isr, + dma1_stream6_isr, + adc_isr, + can1_tx_isr, + can1_rx0_isr, + can1_rx1_isr, + can1_sce_isr, + exti9_5_isr, + tim1_brk_tim9_isr, + tim1_up_tim10_isr, + tim1_trg_com_tim11_isr, + tim1_cc_isr, + tim2_isr, + tim3_isr, + tim4_isr, + i2c1_ev_isr, + i2c1_er_isr, + i2c2_ev_isr, + i2c2_er_isr, + spi1_isr, + spi2_isr, + usart1_isr, + usart2_isr, + usart3_isr, + exti15_10_isr, + rtc_alarm_isr, + usb_fs_wkup_isr, + tim8_brk_tim12_isr, + tim8_up_tim13_isr, + tim8_trg_com_tim14_isr, + tim8_cc_isr, + dma1_stream7_isr, + fsmc_isr, + sdio_isr, + tim5_isr, + spi3_isr, + usart4_isr, + usart5_isr, + tim6_dac_isr, + tim7_isr, + dma2_stream0_isr, + dma2_stream1_isr, + dma2_stream2_isr, + dma2_stream3_isr, + dma2_stream4_isr, + eth_isr, + eth_wkup_isr, + can2_tx_isr, + can2_rx0_isr, + can2_rx1_isr, + can2_sce_isr, + otg_fs_isr, + dma2_stream5_isr, + dma2_stream6_isr, + dma2_stream7_isr, + usart6_isr, + i2c3_ev_isr, + i2c3_er_isr, + otg_hs_ep1_out_isr, + otg_hs_ep1_in_isr, + otg_hs_wkup_isr, + otg_hs_isr, + dcmi_isr, + cryp_isr, + hash_rng_isr, +}; + +void reset_handler(void) +{ + volatile unsigned *src, *dest; + asm("MSR msp, %0" : : "r"(&_stack)); + + for (src = &_etext, dest = &_data; dest < &_edata; src++, dest++) + *dest = *src; + + while (dest < &_ebss) + *dest++ = 0; + + /* Call the application's entry point. */ + main(); +} + +void blocking_handler(void) +{ + while (1) ; +} + +void null_handler(void) +{ + /* Do nothing. */ +} + +#pragma weak nmi_handler = null_handler +#pragma weak hard_fault_handler = blocking_handler +#pragma weak mem_manage_handler = blocking_handler +#pragma weak bus_fault_handler = blocking_handler +#pragma weak usage_fault_handler = blocking_handler +#pragma weak sv_call_handler = null_handler +#pragma weak debug_monitor_handler = null_handler +#pragma weak pend_sv_handler = null_handler +#pragma weak sys_tick_handler = null_handler +#pragma weak wwdg_isr = null_handler +#pragma weak pvd_isr = null_handler +#pragma weak tamp_stamp_isr = null_handler +#pragma weak rtc_wkup_isr = null_handler +#pragma weak flash_isr = null_handler +#pragma weak rcc_isr = null_handler +#pragma weak exti0_isr = null_handler +#pragma weak exti1_isr = null_handler +#pragma weak exti2_isr = null_handler +#pragma weak exti3_isr = null_handler +#pragma weak exti4_isr = null_handler +#pragma weak dma1_stream0_isr = null_handler +#pragma weak dma1_stream1_isr = null_handler +#pragma weak dma1_stream2_isr = null_handler +#pragma weak dma1_stream3_isr = null_handler +#pragma weak dma1_stream4_isr = null_handler +#pragma weak dma1_stream5_isr = null_handler +#pragma weak dma1_stream6_isr = null_handler +#pragma weak adc_isr = null_handler +#pragma weak can1_tx_isr = null_handler +#pragma weak can1_rx0_isr = null_handler +#pragma weak can1_rx1_isr = null_handler +#pragma weak can1_sce_isr = null_handler +#pragma weak exti9_5_isr = null_handler +#pragma weak tim1_brk_tim9_isr = null_handler +#pragma weak tim1_up_tim10_isr = null_handler +#pragma weak tim1_trg_com_tim11_isr = null_handler +#pragma weak tim1_cc_isr = null_handler +#pragma weak tim2_isr = null_handler +#pragma weak tim3_isr = null_handler +#pragma weak tim4_isr = null_handler +#pragma weak i2c1_ev_isr = null_handler +#pragma weak i2c1_er_isr = null_handler +#pragma weak i2c2_ev_isr = null_handler +#pragma weak i2c2_er_isr = null_handler +#pragma weak spi1_isr = null_handler +#pragma weak spi2_isr = null_handler +#pragma weak usart1_isr = null_handler +#pragma weak usart2_isr = null_handler +#pragma weak usart3_isr = null_handler +#pragma weak exti15_10_isr = null_handler +#pragma weak rtc_alarm_isr = null_handler +#pragma weak usb_fs_wkup_isr = null_handler +#pragma weak tim8_brk_tim12_isr = null_handler +#pragma weak tim8_up_tim13_isr = null_handler +#pragma weak tim8_trg_com_tim14_isr = null_handler +#pragma weak tim8_cc_isr = null_handler +#pragma weak dma1_stream7_isr = null_handler +#pragma weak fsmc_isr = null_handler +#pragma weak sdio_isr = null_handler +#pragma weak tim5_isr = null_handler +#pragma weak spi3_isr = null_handler +#pragma weak usart4_isr = null_handler +#pragma weak usart5_isr = null_handler +#pragma weak tim6_dac_isr = null_handler +#pragma weak tim7_isr = null_handler +#pragma weak dma2_stream0_isr = null_handler +#pragma weak dma2_stream1_isr = null_handler +#pragma weak dma2_stream2_isr = null_handler +#pragma weak dma2_stream3_isr = null_handler +#pragma weak dma2_stream4_isr = null_handler +#pragma weak eth_isr = null_handler +#pragma weak eth_wkup_isr = null_handler +#pragma weak can2_tx_isr = null_handler +#pragma weak can2_rx0_isr = null_handler +#pragma weak can2_rx1_isr = null_handler +#pragma weak can2_sce_isr = null_handler +#pragma weak otg_fs_isr = null_handler +#pragma weak dma2_stream5_isr = null_handler +#pragma weak dma2_stream6_isr = null_handler +#pragma weak dma2_stream7_isr = null_handler +#pragma weak usart6_isr = null_handler +#pragma weak i2c3_ev_isr = null_handler +#pragma weak i2c3_er_isr = null_handler +#pragma weak otg_hs_ep1_out_isr = null_handler +#pragma weak otg_hs_ep1_in_isr = null_handler +#pragma weak otg_hs_wkup_isr = null_handler +#pragma weak otg_hs_isr = null_handler +#pragma weak dcmi_isr = null_handler +#pragma weak cryp_isr = null_handler +#pragma weak hash_rng_isr = null_handler + -- cgit v1.2.3 From 666b8f12d56cf478b0c9594009004b88917dec64 Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Thu, 15 Sep 2011 01:17:45 -0700 Subject: Fixing something I forgot to update after restructuring the include directories. --- include/libopencm3/stm32/memorymap.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/libopencm3/stm32/memorymap.h b/include/libopencm3/stm32/memorymap.h index 17a919e..63f2ef0 100644 --- a/include/libopencm3/stm32/memorymap.h +++ b/include/libopencm3/stm32/memorymap.h @@ -21,10 +21,10 @@ #define LIBOPENCM3_MEMORYMAP_COMMON_H #ifdef STM32F1 -#include +#include #else -#ifdef STM32F1 -#include +#ifdef STM32F2 +#include #else #error "stm32 family not defined." #endif -- cgit v1.2.3 From a4935eef571191f7c9170723943f1327d39656a1 Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Thu, 15 Sep 2011 01:18:26 -0700 Subject: Add family define for the F1 Makefile and add a Makefile for the F2. --- lib/stm32f1/Makefile | 2 +- lib/stm32f2/Makefile | 58 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 59 insertions(+), 1 deletion(-) create mode 100644 lib/stm32f2/Makefile diff --git a/lib/stm32f1/Makefile b/lib/stm32f1/Makefile index 3d154aa..fa4dad1 100644 --- a/lib/stm32f1/Makefile +++ b/lib/stm32f1/Makefile @@ -25,7 +25,7 @@ CC = $(PREFIX)-gcc AR = $(PREFIX)-ar CFLAGS = -Os -g -Wall -Wextra -I../../include -fno-common \ -mcpu=cortex-m3 -mthumb -Wstrict-prototypes \ - -ffunction-sections -fdata-sections -MD + -ffunction-sections -fdata-sections -MD -DSTM32F1 # ARFLAGS = rcsv ARFLAGS = rcs OBJS = vector.o rcc.o gpio.o usart.o adc.o spi.o flash.o nvic.o \ diff --git a/lib/stm32f2/Makefile b/lib/stm32f2/Makefile new file mode 100644 index 0000000..1f08089 --- /dev/null +++ b/lib/stm32f2/Makefile @@ -0,0 +1,58 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +## + +LIBNAME = libopencm3_stm32f2 + +# PREFIX ?= arm-none-eabi +PREFIX ?= arm-elf +CC = $(PREFIX)-gcc +AR = $(PREFIX)-ar +CFLAGS = -Os -g -Wall -Wextra -I../../include -fno-common \ + -mcpu=cortex-m3 -mthumb -Wstrict-prototypes \ + -ffunction-sections -fdata-sections -MD -DSTM32F2 +# ARFLAGS = rcsv +ARFLAGS = rcs +OBJS = vector.o gpio.o + +#VPATH += ../usb + +# Be silent per default, but 'make V=1' will show all compiler calls. +ifneq ($(V),1) +Q := @ +endif + +all: $(LIBNAME).a + +$(LIBNAME).a: $(OBJS) + @printf " AR $(subst $(shell pwd)/,,$(@))\n" + $(Q)$(AR) $(ARFLAGS) $@ $^ + +%.o: %.c + @printf " CC $(subst $(shell pwd)/,,$(@))\n" + $(Q)$(CC) $(CFLAGS) -o $@ -c $< + +clean: + @printf " CLEAN lib/stm32f2\n" + $(Q)rm -f *.o *.d + $(Q)rm -f $(LIBNAME).a + +.PHONY: clean + +-include $(OBJS:.o=.d) + -- cgit v1.2.3 From ce7dd46aef9153c4f98a983977ce7bd2a905134d Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Thu, 15 Sep 2011 01:18:49 -0700 Subject: Update F1 libs with new header file locations. --- lib/stm32f1/adc.c | 2 +- lib/stm32f1/can.c | 2 +- lib/stm32f1/dma.c | 2 +- lib/stm32f1/ethernet.c | 2 +- lib/stm32f1/exti.c | 2 +- lib/stm32f1/flash.c | 2 +- lib/stm32f1/gpio.c | 2 +- lib/stm32f1/nvic.c | 2 +- lib/stm32f1/rcc.c | 4 ++-- lib/stm32f1/rtc.c | 4 ++-- lib/stm32f1/systick.c | 2 +- lib/stm32f1/timer.c | 2 +- lib/stm32f1/usart.c | 2 +- lib/stm32f2/gpio.c | 10 +++++----- 14 files changed, 20 insertions(+), 20 deletions(-) diff --git a/lib/stm32f1/adc.c b/lib/stm32f1/adc.c index 058837c..31e4cbf 100644 --- a/lib/stm32f1/adc.c +++ b/lib/stm32f1/adc.c @@ -31,7 +31,7 @@ * reg16 = adc_read(ADC1, ADC_CH_0); */ -#include +#include void rcc_set_adc_clk(u32 prescaler) { diff --git a/lib/stm32f1/can.c b/lib/stm32f1/can.c index e571f8a..8c5d7ec 100644 --- a/lib/stm32f1/can.c +++ b/lib/stm32f1/can.c @@ -18,7 +18,7 @@ */ #include -#include +#include void can_reset(u32 canport) { diff --git a/lib/stm32f1/dma.c b/lib/stm32f1/dma.c index 8feb2c9..4f0af6f 100644 --- a/lib/stm32f1/dma.c +++ b/lib/stm32f1/dma.c @@ -17,7 +17,7 @@ * along with this program. If not, see . */ -#include +#include void dma_enable_mem2mem_mode(u32 dma, u8 channel) { diff --git a/lib/stm32f1/ethernet.c b/lib/stm32f1/ethernet.c index 4a4d080..fc65ec2 100644 --- a/lib/stm32f1/ethernet.c +++ b/lib/stm32f1/ethernet.c @@ -17,7 +17,7 @@ * along with this program. If not, see . */ -#include +#include void eth_smi_write(u8 phy, u8 reg, u16 data) { diff --git a/lib/stm32f1/exti.c b/lib/stm32f1/exti.c index de037e7..969cae4 100644 --- a/lib/stm32f1/exti.c +++ b/lib/stm32f1/exti.c @@ -18,7 +18,7 @@ */ #include -#include +#include void exti_set_trigger(u32 extis, exti_trigger_type trig) { diff --git a/lib/stm32f1/flash.c b/lib/stm32f1/flash.c index 98f7777..b8b3d52 100644 --- a/lib/stm32f1/flash.c +++ b/lib/stm32f1/flash.c @@ -18,7 +18,7 @@ * along with this program. If not, see . */ -#include +#include void flash_prefetch_buffer_enable(void) { diff --git a/lib/stm32f1/gpio.c b/lib/stm32f1/gpio.c index 52c0c66..cd6be9b 100644 --- a/lib/stm32f1/gpio.c +++ b/lib/stm32f1/gpio.c @@ -34,7 +34,7 @@ * - GPIO remapping support */ -#include +#include void gpio_set_mode(u32 gpioport, u8 mode, u8 cnf, u16 gpios) { diff --git a/lib/stm32f1/nvic.c b/lib/stm32f1/nvic.c index cf77cc3..f45b601 100644 --- a/lib/stm32f1/nvic.c +++ b/lib/stm32f1/nvic.c @@ -17,7 +17,7 @@ * along with this program. If not, see . */ -#include +#include void nvic_enable_irq(u8 irqn) { diff --git a/lib/stm32f1/rcc.c b/lib/stm32f1/rcc.c index f646168..689cabb 100644 --- a/lib/stm32f1/rcc.c +++ b/lib/stm32f1/rcc.c @@ -19,8 +19,8 @@ * along with this program. If not, see . */ -#include -#include +#include +#include /* Set the default ppre1 and ppre2 peripheral clock frequencies after reset */ u32 rcc_ppre1_frequency = 8000000; diff --git a/lib/stm32f1/rtc.c b/lib/stm32f1/rtc.c index 4495641..c187be9 100644 --- a/lib/stm32f1/rtc.c +++ b/lib/stm32f1/rtc.c @@ -18,8 +18,8 @@ * along with this program. If not, see . */ -#include -#include +#include +#include #include void rtc_awake_from_off(osc_t clock_source) diff --git a/lib/stm32f1/systick.c b/lib/stm32f1/systick.c index 882601d..3308413 100644 --- a/lib/stm32f1/systick.c +++ b/lib/stm32f1/systick.c @@ -17,7 +17,7 @@ * along with this program. If not, see . */ -#include +#include void systick_set_reload(u32 value) { diff --git a/lib/stm32f1/timer.c b/lib/stm32f1/timer.c index 32e240d..a61f67f 100644 --- a/lib/stm32f1/timer.c +++ b/lib/stm32f1/timer.c @@ -26,7 +26,7 @@ */ #include -#include +#include void timer_reset(u32 timer_peripheral) { diff --git a/lib/stm32f1/usart.c b/lib/stm32f1/usart.c index ead0ef7..73e450b 100644 --- a/lib/stm32f1/usart.c +++ b/lib/stm32f1/usart.c @@ -17,7 +17,7 @@ * along with this program. If not, see . */ -#include +#include #include diff --git a/lib/stm32f2/gpio.c b/lib/stm32f2/gpio.c index f2ea55a..2330628 100644 --- a/lib/stm32f2/gpio.c +++ b/lib/stm32f2/gpio.c @@ -77,9 +77,9 @@ void gpio_set_output_options(u32 gpioport, u8 otype, u8 speed, u16 gpios) for (i = 0; i < 16; i++) { if (!((1 << i) & gpios)) - continue - ospeedr &= ~GPIO_OSPEEDR_MASK(i); - ospeedr |= GPIO_OSPEEDR(i, mode); + continue; + ospeedr &= ~GPIO_OSPEED_MASK(i); + ospeedr |= GPIO_OSPEED(i, speed); } GPIO_OSPEEDR(gpioport) = ospeedr; @@ -95,14 +95,14 @@ void gpio_set_af(u32 gpioport, u8 alt_func_num, u16 gpios) for (i = 0; i < 8; i++) { if (!((1 << i) & gpios)) - continue + continue; afrl &= GPIO_AFR_MASK(i); afrl |= GPIO_AFR(i, alt_func_num); } for (i = 8; i < 16; i++) { if (!((1 << i) & gpios)) - continue + continue; afrl &= GPIO_AFR_MASK(i-8); afrh |= GPIO_AFR(i-8, alt_func_num); } -- cgit v1.2.3 From cff706e3ca3823ffb388a4e87c4ef8bf925945c4 Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Thu, 15 Sep 2011 01:20:45 -0700 Subject: Rename F1 examples folder. --- examples/stm32/lisa-m/fancyblink/Makefile | 23 - examples/stm32/lisa-m/fancyblink/fancyblink.c | 67 --- examples/stm32/lisa-m/fancyblink/fancyblink.ld | 31 -- examples/stm32/lisa-m/usb_dfu/Makefile | 23 - examples/stm32/lisa-m/usb_dfu/README | 7 - examples/stm32/lisa-m/usb_dfu/usbdfu.c | 270 ----------- examples/stm32/lisa-m/usb_dfu/usbdfu.ld | 29 -- examples/stm32/lisa-m/usb_hid/Makefile | 23 - examples/stm32/lisa-m/usb_hid/README | 7 - examples/stm32/lisa-m/usb_hid/usbhid.c | 289 ------------ examples/stm32/lisa-m/usb_hid/usbhid.ld | 31 -- examples/stm32/mb525/fancyblink/Makefile | 23 - examples/stm32/mb525/fancyblink/README | 10 - examples/stm32/mb525/fancyblink/fancyblink.c | 76 ---- examples/stm32/mb525/fancyblink/fancyblink.ld | 31 -- examples/stm32/mb525/pwmleds/Makefile | 23 - examples/stm32/mb525/pwmleds/README | 10 - examples/stm32/mb525/pwmleds/pwmleds.c | 496 --------------------- examples/stm32/mb525/pwmleds/pwmleds.ld | 31 -- examples/stm32/obldc/can/Makefile | 23 - examples/stm32/obldc/can/can.c | 216 --------- examples/stm32/obldc/can/can.ld | 31 -- examples/stm32/obldc/led/Makefile | 23 - examples/stm32/obldc/led/led.c | 71 --- examples/stm32/obldc/led/led.ld | 31 -- examples/stm32/obldc/pwmleds/Makefile | 23 - examples/stm32/obldc/pwmleds/pwmleds.c | 485 -------------------- examples/stm32/obldc/pwmleds/pwmleds.ld | 31 -- examples/stm32/obldc/systick/Makefile | 23 - examples/stm32/obldc/systick/systick.c | 90 ---- examples/stm32/obldc/systick/systick.ld | 31 -- examples/stm32/obldc/usart/Makefile | 23 - examples/stm32/obldc/usart/usart.c | 90 ---- examples/stm32/obldc/usart/usart.ld | 31 -- examples/stm32/obldc/usart_irq/Makefile | 25 -- examples/stm32/obldc/usart_irq/usart_irq.c | 120 ----- examples/stm32/obldc/usart_irq/usart_irq.ld | 31 -- .../stm32/other/adc_temperature_sensor/Makefile | 23 - examples/stm32/other/adc_temperature_sensor/README | 10 - examples/stm32/other/adc_temperature_sensor/adc.c | 155 ------- examples/stm32/other/adc_temperature_sensor/adc.ld | 31 -- examples/stm32/other/dma_mem2mem/Makefile | 23 - examples/stm32/other/dma_mem2mem/README | 11 - examples/stm32/other/dma_mem2mem/dma.c | 133 ------ examples/stm32/other/dma_mem2mem/dma.ld | 31 -- examples/stm32/other/dogm128/Makefile | 25 -- examples/stm32/other/dogm128/README | 7 - examples/stm32/other/dogm128/dogm128.c | 291 ------------ examples/stm32/other/dogm128/dogm128.h | 86 ---- examples/stm32/other/dogm128/main.c | 110 ----- examples/stm32/other/dogm128/main.ld | 31 -- examples/stm32/other/i2c_stts75_sensor/Makefile | 25 -- examples/stm32/other/i2c_stts75_sensor/README | 13 - .../other/i2c_stts75_sensor/i2c_stts75_sensor.c | 146 ------ .../other/i2c_stts75_sensor/i2c_stts75_sensor.ld | 31 -- examples/stm32/other/i2c_stts75_sensor/stts75.c | 186 -------- examples/stm32/other/i2c_stts75_sensor/stts75.h | 39 -- examples/stm32/other/rtc/Makefile | 23 - examples/stm32/other/rtc/README | 6 - examples/stm32/other/rtc/rtc.c | 116 ----- examples/stm32/other/rtc/rtc.ld | 31 -- examples/stm32/other/systick/Makefile | 23 - examples/stm32/other/systick/README | 7 - examples/stm32/other/systick/systick.c | 75 ---- examples/stm32/other/systick/systick.ld | 31 -- examples/stm32/other/timer_interrupt/Makefile | 23 - examples/stm32/other/timer_interrupt/README | 7 - examples/stm32/other/timer_interrupt/timer.c | 85 ---- examples/stm32/other/timer_interrupt/timer.ld | 31 -- examples/stm32/other/usb_cdcacm/Makefile | 23 - examples/stm32/other/usb_cdcacm/README | 7 - examples/stm32/other/usb_cdcacm/cdcacm.c | 245 ---------- examples/stm32/other/usb_cdcacm/cdcacm.ld | 29 -- examples/stm32/other/usb_dfu/Makefile | 23 - examples/stm32/other/usb_dfu/README | 7 - examples/stm32/other/usb_dfu/usbdfu.c | 270 ----------- examples/stm32/other/usb_dfu/usbdfu.ld | 29 -- examples/stm32/other/usb_hid/Makefile | 23 - examples/stm32/other/usb_hid/README | 7 - examples/stm32/other/usb_hid/usbhid.c | 272 ----------- examples/stm32/other/usb_hid/usbhid.ld | 29 -- examples/stm32/stm32-discovery/button/Makefile | 23 - examples/stm32/stm32-discovery/button/README | 8 - examples/stm32/stm32-discovery/button/button.c | 76 ---- examples/stm32/stm32-discovery/button/button.ld | 31 -- examples/stm32/stm32-discovery/fancyblink/Makefile | 23 - examples/stm32/stm32-discovery/fancyblink/README | 9 - .../stm32/stm32-discovery/fancyblink/fancyblink.c | 61 --- .../stm32/stm32-discovery/fancyblink/fancyblink.ld | 31 -- examples/stm32/stm32-discovery/miniblink/Makefile | 23 - examples/stm32/stm32-discovery/miniblink/README | 9 - .../stm32/stm32-discovery/miniblink/miniblink.c | 71 --- .../stm32/stm32-discovery/miniblink/miniblink.ld | 31 -- examples/stm32/stm32-discovery/rtc/Makefile | 23 - examples/stm32/stm32-discovery/rtc/README | 9 - examples/stm32/stm32-discovery/rtc/rtc.c | 129 ------ examples/stm32/stm32-discovery/rtc/rtc.ld | 31 -- examples/stm32/stm32-discovery/usart/Makefile | 23 - examples/stm32/stm32-discovery/usart/README | 12 - examples/stm32/stm32-discovery/usart/usart.c | 87 ---- examples/stm32/stm32-discovery/usart/usart.ld | 31 -- examples/stm32/stm32-h103/button/Makefile | 23 - examples/stm32/stm32-h103/button/button.c | 79 ---- examples/stm32/stm32-h103/button/button.ld | 31 -- examples/stm32/stm32-h103/exti_both/Makefile | 23 - examples/stm32/stm32-h103/exti_both/exti_both.c | 92 ---- examples/stm32/stm32-h103/exti_both/exti_both.ld | 31 -- .../stm32/stm32-h103/exti_rising_falling/Makefile | 23 - .../exti_rising_falling/exti_rising_falling.c | 98 ---- .../exti_rising_falling/exti_rising_falling.ld | 31 -- examples/stm32/stm32-h103/fancyblink/Makefile | 23 - examples/stm32/stm32-h103/fancyblink/README | 10 - examples/stm32/stm32-h103/fancyblink/fancyblink.c | 55 --- examples/stm32/stm32-h103/fancyblink/fancyblink.ld | 31 -- examples/stm32/stm32-h103/led_stripe/Makefile | 23 - examples/stm32/stm32-h103/led_stripe/led_stripe.c | 234 ---------- examples/stm32/stm32-h103/led_stripe/led_stripe.ld | 31 -- examples/stm32/stm32-h103/miniblink/Makefile | 23 - examples/stm32/stm32-h103/miniblink/README | 10 - examples/stm32/stm32-h103/miniblink/miniblink.c | 71 --- examples/stm32/stm32-h103/miniblink/miniblink.ld | 31 -- examples/stm32/stm32-h103/pwm_6step/Makefile | 23 - examples/stm32/stm32-h103/pwm_6step/pwm_6step.c | 409 ----------------- examples/stm32/stm32-h103/pwm_6step/pwm_6step.ld | 31 -- examples/stm32/stm32-h103/spi/Makefile | 23 - examples/stm32/stm32-h103/spi/README | 8 - examples/stm32/stm32-h103/spi/spi.c | 50 --- examples/stm32/stm32-h103/spi/spi.ld | 31 -- examples/stm32/stm32-h103/timer/Makefile | 23 - examples/stm32/stm32-h103/timer/timer.c | 183 -------- examples/stm32/stm32-h103/timer/timer.ld | 31 -- examples/stm32/stm32-h103/traceswo/Makefile | 23 - examples/stm32/stm32-h103/traceswo/README | 11 - examples/stm32/stm32-h103/traceswo/traceswo.c | 100 ----- examples/stm32/stm32-h103/traceswo/traceswo.ld | 31 -- examples/stm32/stm32-h103/usart/Makefile | 23 - examples/stm32/stm32-h103/usart/README | 13 - examples/stm32/stm32-h103/usart/usart.c | 119 ----- examples/stm32/stm32-h103/usart/usart.ld | 31 -- examples/stm32/stm32-h103/usart_irq/Makefile | 23 - examples/stm32/stm32-h103/usart_irq/usart_irq.c | 119 ----- examples/stm32/stm32-h103/usart_irq/usart_irq.ld | 31 -- .../stm32/stm32-h103/usart_irq_printf/Makefile | 23 - .../stm32-h103/usart_irq_printf/usart_irq_printf.c | 272 ----------- .../usart_irq_printf/usart_irq_printf.ld | 31 -- examples/stm32/stm32-h103/usart_printf/Makefile | 23 - .../stm32/stm32-h103/usart_printf/usart_printf.c | 108 ----- .../stm32/stm32-h103/usart_printf/usart_printf.ld | 31 -- examples/stm32/stm32-h103/usb_cdcacm/Makefile | 23 - examples/stm32/stm32-h103/usb_cdcacm/README | 7 - examples/stm32/stm32-h103/usb_cdcacm/cdcacm.c | 246 ---------- examples/stm32/stm32-h103/usb_cdcacm/cdcacm.ld | 31 -- examples/stm32/stm32-h103/usb_dfu/Makefile | 23 - examples/stm32/stm32-h103/usb_dfu/README | 7 - examples/stm32/stm32-h103/usb_dfu/usbdfu.c | 270 ----------- examples/stm32/stm32-h103/usb_dfu/usbdfu.ld | 29 -- examples/stm32/stm32-h103/usb_hid/Makefile | 23 - examples/stm32/stm32-h103/usb_hid/README | 7 - examples/stm32/stm32-h103/usb_hid/usbhid.c | 272 ----------- examples/stm32/stm32-h103/usb_hid/usbhid.ld | 31 -- examples/stm32/stm32-h103/usb_iap/Makefile | 23 - examples/stm32/stm32-h103/usb_iap/README | 8 - examples/stm32/stm32-h103/usb_iap/usbiap.c | 270 ----------- examples/stm32/stm32-h103/usb_iap/usbiap.ld | 31 -- examples/stm32/stm32-h107/fancyblink/Makefile | 23 - examples/stm32/stm32-h107/fancyblink/README | 10 - examples/stm32/stm32-h107/fancyblink/fancyblink.c | 58 --- examples/stm32/stm32-h107/fancyblink/fancyblink.ld | 31 -- examples/stm32/stm32-h107/usb_simple/Makefile | 23 - examples/stm32/stm32-h107/usb_simple/README | 10 - examples/stm32/stm32-h107/usb_simple/usb_simple.c | 117 ----- examples/stm32/stm32-h107/usb_simple/usb_simple.ld | 31 -- examples/stm32f1/Makefile.include | 127 ++++++ examples/stm32f1/lisa-m/fancyblink/Makefile | 23 + examples/stm32f1/lisa-m/fancyblink/fancyblink.c | 67 +++ examples/stm32f1/lisa-m/fancyblink/fancyblink.ld | 31 ++ examples/stm32f1/lisa-m/usb_dfu/Makefile | 23 + examples/stm32f1/lisa-m/usb_dfu/README | 7 + examples/stm32f1/lisa-m/usb_dfu/usbdfu.c | 270 +++++++++++ examples/stm32f1/lisa-m/usb_dfu/usbdfu.ld | 29 ++ examples/stm32f1/lisa-m/usb_hid/Makefile | 23 + examples/stm32f1/lisa-m/usb_hid/README | 7 + examples/stm32f1/lisa-m/usb_hid/usbhid.c | 289 ++++++++++++ examples/stm32f1/lisa-m/usb_hid/usbhid.ld | 31 ++ examples/stm32f1/mb525/fancyblink/Makefile | 23 + examples/stm32f1/mb525/fancyblink/README | 10 + examples/stm32f1/mb525/fancyblink/fancyblink.c | 76 ++++ examples/stm32f1/mb525/fancyblink/fancyblink.ld | 31 ++ examples/stm32f1/mb525/pwmleds/Makefile | 23 + examples/stm32f1/mb525/pwmleds/README | 10 + examples/stm32f1/mb525/pwmleds/pwmleds.c | 496 +++++++++++++++++++++ examples/stm32f1/mb525/pwmleds/pwmleds.ld | 31 ++ examples/stm32f1/obldc/can/Makefile | 23 + examples/stm32f1/obldc/can/can.c | 216 +++++++++ examples/stm32f1/obldc/can/can.ld | 31 ++ examples/stm32f1/obldc/led/Makefile | 23 + examples/stm32f1/obldc/led/led.c | 71 +++ examples/stm32f1/obldc/led/led.ld | 31 ++ examples/stm32f1/obldc/pwmleds/Makefile | 23 + examples/stm32f1/obldc/pwmleds/pwmleds.c | 485 ++++++++++++++++++++ examples/stm32f1/obldc/pwmleds/pwmleds.ld | 31 ++ examples/stm32f1/obldc/systick/Makefile | 23 + examples/stm32f1/obldc/systick/systick.c | 90 ++++ examples/stm32f1/obldc/systick/systick.ld | 31 ++ examples/stm32f1/obldc/usart/Makefile | 23 + examples/stm32f1/obldc/usart/usart.c | 90 ++++ examples/stm32f1/obldc/usart/usart.ld | 31 ++ examples/stm32f1/obldc/usart_irq/Makefile | 25 ++ examples/stm32f1/obldc/usart_irq/usart_irq.c | 120 +++++ examples/stm32f1/obldc/usart_irq/usart_irq.ld | 31 ++ .../stm32f1/other/adc_temperature_sensor/Makefile | 23 + .../stm32f1/other/adc_temperature_sensor/README | 10 + .../stm32f1/other/adc_temperature_sensor/adc.c | 155 +++++++ .../stm32f1/other/adc_temperature_sensor/adc.ld | 31 ++ examples/stm32f1/other/dma_mem2mem/Makefile | 23 + examples/stm32f1/other/dma_mem2mem/README | 11 + examples/stm32f1/other/dma_mem2mem/dma.c | 133 ++++++ examples/stm32f1/other/dma_mem2mem/dma.ld | 31 ++ examples/stm32f1/other/dogm128/Makefile | 25 ++ examples/stm32f1/other/dogm128/README | 7 + examples/stm32f1/other/dogm128/dogm128.c | 291 ++++++++++++ examples/stm32f1/other/dogm128/dogm128.h | 86 ++++ examples/stm32f1/other/dogm128/main.c | 110 +++++ examples/stm32f1/other/dogm128/main.ld | 31 ++ examples/stm32f1/other/i2c_stts75_sensor/Makefile | 25 ++ examples/stm32f1/other/i2c_stts75_sensor/README | 13 + .../other/i2c_stts75_sensor/i2c_stts75_sensor.c | 146 ++++++ .../other/i2c_stts75_sensor/i2c_stts75_sensor.ld | 31 ++ examples/stm32f1/other/i2c_stts75_sensor/stts75.c | 186 ++++++++ examples/stm32f1/other/i2c_stts75_sensor/stts75.h | 39 ++ examples/stm32f1/other/rtc/Makefile | 23 + examples/stm32f1/other/rtc/README | 6 + examples/stm32f1/other/rtc/rtc.c | 116 +++++ examples/stm32f1/other/rtc/rtc.ld | 31 ++ examples/stm32f1/other/systick/Makefile | 23 + examples/stm32f1/other/systick/README | 7 + examples/stm32f1/other/systick/systick.c | 75 ++++ examples/stm32f1/other/systick/systick.ld | 31 ++ examples/stm32f1/other/timer_interrupt/Makefile | 23 + examples/stm32f1/other/timer_interrupt/README | 7 + examples/stm32f1/other/timer_interrupt/timer.c | 85 ++++ examples/stm32f1/other/timer_interrupt/timer.ld | 31 ++ examples/stm32f1/other/usb_cdcacm/Makefile | 23 + examples/stm32f1/other/usb_cdcacm/README | 7 + examples/stm32f1/other/usb_cdcacm/cdcacm.c | 245 ++++++++++ examples/stm32f1/other/usb_cdcacm/cdcacm.ld | 29 ++ examples/stm32f1/other/usb_dfu/Makefile | 23 + examples/stm32f1/other/usb_dfu/README | 7 + examples/stm32f1/other/usb_dfu/usbdfu.c | 270 +++++++++++ examples/stm32f1/other/usb_dfu/usbdfu.ld | 29 ++ examples/stm32f1/other/usb_hid/Makefile | 23 + examples/stm32f1/other/usb_hid/README | 7 + examples/stm32f1/other/usb_hid/usbhid.c | 272 +++++++++++ examples/stm32f1/other/usb_hid/usbhid.ld | 29 ++ examples/stm32f1/stm32-discovery/button/Makefile | 23 + examples/stm32f1/stm32-discovery/button/README | 8 + examples/stm32f1/stm32-discovery/button/button.c | 76 ++++ examples/stm32f1/stm32-discovery/button/button.ld | 31 ++ .../stm32f1/stm32-discovery/fancyblink/Makefile | 23 + examples/stm32f1/stm32-discovery/fancyblink/README | 9 + .../stm32-discovery/fancyblink/fancyblink.c | 61 +++ .../stm32-discovery/fancyblink/fancyblink.ld | 31 ++ .../stm32f1/stm32-discovery/miniblink/Makefile | 23 + examples/stm32f1/stm32-discovery/miniblink/README | 9 + .../stm32f1/stm32-discovery/miniblink/miniblink.c | 71 +++ .../stm32f1/stm32-discovery/miniblink/miniblink.ld | 31 ++ examples/stm32f1/stm32-discovery/rtc/Makefile | 23 + examples/stm32f1/stm32-discovery/rtc/README | 9 + examples/stm32f1/stm32-discovery/rtc/rtc.c | 129 ++++++ examples/stm32f1/stm32-discovery/rtc/rtc.ld | 31 ++ examples/stm32f1/stm32-discovery/usart/Makefile | 23 + examples/stm32f1/stm32-discovery/usart/README | 12 + examples/stm32f1/stm32-discovery/usart/usart.c | 87 ++++ examples/stm32f1/stm32-discovery/usart/usart.ld | 31 ++ examples/stm32f1/stm32-h103/button/Makefile | 23 + examples/stm32f1/stm32-h103/button/button.c | 79 ++++ examples/stm32f1/stm32-h103/button/button.ld | 31 ++ examples/stm32f1/stm32-h103/exti_both/Makefile | 23 + examples/stm32f1/stm32-h103/exti_both/exti_both.c | 92 ++++ examples/stm32f1/stm32-h103/exti_both/exti_both.ld | 31 ++ .../stm32-h103/exti_rising_falling/Makefile | 23 + .../exti_rising_falling/exti_rising_falling.c | 98 ++++ .../exti_rising_falling/exti_rising_falling.ld | 31 ++ examples/stm32f1/stm32-h103/fancyblink/Makefile | 23 + examples/stm32f1/stm32-h103/fancyblink/README | 10 + .../stm32f1/stm32-h103/fancyblink/fancyblink.c | 55 +++ .../stm32f1/stm32-h103/fancyblink/fancyblink.ld | 31 ++ examples/stm32f1/stm32-h103/led_stripe/Makefile | 23 + .../stm32f1/stm32-h103/led_stripe/led_stripe.c | 234 ++++++++++ .../stm32f1/stm32-h103/led_stripe/led_stripe.ld | 31 ++ examples/stm32f1/stm32-h103/miniblink/Makefile | 23 + examples/stm32f1/stm32-h103/miniblink/README | 10 + examples/stm32f1/stm32-h103/miniblink/miniblink.c | 71 +++ examples/stm32f1/stm32-h103/miniblink/miniblink.ld | 31 ++ examples/stm32f1/stm32-h103/pwm_6step/Makefile | 23 + examples/stm32f1/stm32-h103/pwm_6step/pwm_6step.c | 409 +++++++++++++++++ examples/stm32f1/stm32-h103/pwm_6step/pwm_6step.ld | 31 ++ examples/stm32f1/stm32-h103/spi/Makefile | 23 + examples/stm32f1/stm32-h103/spi/README | 8 + examples/stm32f1/stm32-h103/spi/spi.c | 50 +++ examples/stm32f1/stm32-h103/spi/spi.ld | 31 ++ examples/stm32f1/stm32-h103/timer/Makefile | 23 + examples/stm32f1/stm32-h103/timer/timer.c | 183 ++++++++ examples/stm32f1/stm32-h103/timer/timer.ld | 31 ++ examples/stm32f1/stm32-h103/traceswo/Makefile | 23 + examples/stm32f1/stm32-h103/traceswo/README | 11 + examples/stm32f1/stm32-h103/traceswo/traceswo.c | 100 +++++ examples/stm32f1/stm32-h103/traceswo/traceswo.ld | 31 ++ examples/stm32f1/stm32-h103/usart/Makefile | 23 + examples/stm32f1/stm32-h103/usart/README | 13 + examples/stm32f1/stm32-h103/usart/usart.c | 119 +++++ examples/stm32f1/stm32-h103/usart/usart.ld | 31 ++ examples/stm32f1/stm32-h103/usart_irq/Makefile | 23 + examples/stm32f1/stm32-h103/usart_irq/usart_irq.c | 119 +++++ examples/stm32f1/stm32-h103/usart_irq/usart_irq.ld | 31 ++ .../stm32f1/stm32-h103/usart_irq_printf/Makefile | 23 + .../stm32-h103/usart_irq_printf/usart_irq_printf.c | 272 +++++++++++ .../usart_irq_printf/usart_irq_printf.ld | 31 ++ examples/stm32f1/stm32-h103/usart_printf/Makefile | 23 + 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create mode 100644 examples/stm32f1/stm32-h103/usb_iap/Makefile create mode 100644 examples/stm32f1/stm32-h103/usb_iap/README create mode 100644 examples/stm32f1/stm32-h103/usb_iap/usbiap.c create mode 100644 examples/stm32f1/stm32-h103/usb_iap/usbiap.ld create mode 100644 examples/stm32f1/stm32-h107/fancyblink/Makefile create mode 100644 examples/stm32f1/stm32-h107/fancyblink/README create mode 100644 examples/stm32f1/stm32-h107/fancyblink/fancyblink.c create mode 100644 examples/stm32f1/stm32-h107/fancyblink/fancyblink.ld create mode 100644 examples/stm32f1/stm32-h107/usb_simple/Makefile create mode 100644 examples/stm32f1/stm32-h107/usb_simple/README create mode 100644 examples/stm32f1/stm32-h107/usb_simple/usb_simple.c create mode 100644 examples/stm32f1/stm32-h107/usb_simple/usb_simple.ld diff --git a/examples/stm32/lisa-m/fancyblink/Makefile b/examples/stm32/lisa-m/fancyblink/Makefile deleted file mode 100644 index 1baec4d..0000000 --- a/examples/stm32/lisa-m/fancyblink/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2009 Uwe Hermann -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program. If not, see . -## - -BINARY = fancyblink - -include ../../Makefile.include - diff --git a/examples/stm32/lisa-m/fancyblink/fancyblink.c b/examples/stm32/lisa-m/fancyblink/fancyblink.c deleted file mode 100644 index 5987bdf..0000000 --- a/examples/stm32/lisa-m/fancyblink/fancyblink.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * Copyright (C) 2011 Piotr Esden-Tempski - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include - -/* Set STM32 to 72 MHz. */ -void clock_setup(void) -{ - rcc_clock_setup_in_hse_12mhz_out_72mhz(); - - /* Enable GPIOC clock. */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPBEN); - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_AFIOEN); - -} - -void gpio_setup(void) -{ - /* Set GPIO12 (in GPIO port C) to 'output push-pull'. */ - gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO13); - gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO4); - - AFIO_MAPR |= AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_JNTRST; - - /* preconfigure the led's */ - gpio_set(GPIOB, GPIO4); /* switch off led */ - gpio_clear(GPIOC, GPIO13); /* switch on led */ -} - -int main(void) -{ - int i; - - clock_setup(); - gpio_setup(); - - /* Blink the LED (PC12) on the board. */ - while (1) { - gpio_toggle(GPIOC, GPIO13); /* LED on/off */ - gpio_toggle(GPIOB, GPIO4); /* LED on/off */ - for (i = 0; i < 800000; i++) /* Wait a bit. */ - __asm__("nop"); - } - - return 0; -} diff --git a/examples/stm32/lisa-m/fancyblink/fancyblink.ld b/examples/stm32/lisa-m/fancyblink/fancyblink.ld deleted file mode 100644 index 7ea2b92..0000000 --- a/examples/stm32/lisa-m/fancyblink/fancyblink.ld +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* Linker script for Olimex STM32-H103 (STM32F103RBT6, 128K flash, 20K RAM). */ - -/* Define memory regions. */ -MEMORY -{ - rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K -} - -/* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld - diff --git a/examples/stm32/lisa-m/usb_dfu/Makefile b/examples/stm32/lisa-m/usb_dfu/Makefile deleted file mode 100644 index 48e2d6b..0000000 --- a/examples/stm32/lisa-m/usb_dfu/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2009 Uwe Hermann -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program. If not, see . -## - -BINARY = usbdfu - -include ../../Makefile.include - diff --git a/examples/stm32/lisa-m/usb_dfu/README b/examples/stm32/lisa-m/usb_dfu/README deleted file mode 100644 index 9c0169a..0000000 --- a/examples/stm32/lisa-m/usb_dfu/README +++ /dev/null @@ -1,7 +0,0 @@ ------------------------------------------------------------------------------- -README ------------------------------------------------------------------------------- - -This example implements a USB Device Firmware Upgrade (DFU) bootloader -to demonstrate the use of the USB device stack. - diff --git a/examples/stm32/lisa-m/usb_dfu/usbdfu.c b/examples/stm32/lisa-m/usb_dfu/usbdfu.c deleted file mode 100644 index 7ffbc74..0000000 --- a/examples/stm32/lisa-m/usb_dfu/usbdfu.c +++ /dev/null @@ -1,270 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Gareth McMullin - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include -#include -#include -#include -#include - -#define APP_ADDRESS 0x08002000 - -/* Commands sent with wBlockNum == 0 as per ST implementation. */ -#define CMD_SETADDR 0x21 -#define CMD_ERASE 0x41 - -/* We need a special large control buffer for this device: */ -u8 usbd_control_buffer[1024]; - -static enum dfu_state usbdfu_state = STATE_DFU_IDLE; - -static struct { - u8 buf[sizeof(usbd_control_buffer)]; - u16 len; - u32 addr; - u16 blocknum; -} prog; - -const struct usb_device_descriptor dev = { - .bLength = USB_DT_DEVICE_SIZE, - .bDescriptorType = USB_DT_DEVICE, - .bcdUSB = 0x0200, - .bDeviceClass = 0, - .bDeviceSubClass = 0, - .bDeviceProtocol = 0, - .bMaxPacketSize0 = 64, - .idVendor = 0x0483, - .idProduct = 0xDF11, - .bcdDevice = 0x0200, - .iManufacturer = 1, - .iProduct = 2, - .iSerialNumber = 3, - .bNumConfigurations = 1, -}; - -const struct usb_dfu_descriptor dfu_function = { - .bLength = sizeof(struct usb_dfu_descriptor), - .bDescriptorType = DFU_FUNCTIONAL, - .bmAttributes = USB_DFU_CAN_DOWNLOAD | USB_DFU_WILL_DETACH, - .wDetachTimeout = 255, - .wTransferSize = 1024, - .bcdDFUVersion = 0x011A, -}; - -const struct usb_interface_descriptor iface = { - .bLength = USB_DT_INTERFACE_SIZE, - .bDescriptorType = USB_DT_INTERFACE, - .bInterfaceNumber = 0, - .bAlternateSetting = 0, - .bNumEndpoints = 0, - .bInterfaceClass = 0xFE, /* Device Firmware Upgrade */ - .bInterfaceSubClass = 1, - .bInterfaceProtocol = 2, - - /* The ST Microelectronics DfuSe application needs this string. - * The format isn't documented... */ - .iInterface = 4, - - .extra = &dfu_function, - .extralen = sizeof(dfu_function), -}; - -const struct usb_interface ifaces[] = {{ - .num_altsetting = 1, - .altsetting = &iface, -}}; - -const struct usb_config_descriptor config = { - .bLength = USB_DT_CONFIGURATION_SIZE, - .bDescriptorType = USB_DT_CONFIGURATION, - .wTotalLength = 0, - .bNumInterfaces = 1, - .bConfigurationValue = 1, - .iConfiguration = 0, - .bmAttributes = 0xC0, - .bMaxPower = 0x32, - - .interface = ifaces, -}; - -static const char *usb_strings[] = { - "x", - "Black Sphere Technologies", - "DFU Demo", - "DEMO", - /* This string is used by ST Microelectronics' DfuSe utility */ - "@Internal Flash /0x08000000/8*001Ka,56*001Kg" -}; - -static u8 usbdfu_getstatus(u32 *bwPollTimeout) -{ - switch(usbdfu_state) { - case STATE_DFU_DNLOAD_SYNC: - usbdfu_state = STATE_DFU_DNBUSY; - *bwPollTimeout = 100; - return DFU_STATUS_OK; - - case STATE_DFU_MANIFEST_SYNC: - /* Device will reset when read is complete */ - usbdfu_state = STATE_DFU_MANIFEST; - return DFU_STATUS_OK; - - default: - return DFU_STATUS_OK; - } -} - -static void usbdfu_getstatus_complete(struct usb_setup_data *req) -{ - int i; - (void)req; - - switch(usbdfu_state) { - case STATE_DFU_DNBUSY: - - flash_unlock(); - if(prog.blocknum == 0) { - switch(prog.buf[0]) { - case CMD_ERASE: - flash_erase_page(*(u32*)(prog.buf+1)); - case CMD_SETADDR: - prog.addr = *(u32*)(prog.buf+1); - } - } else { - u32 baseaddr = prog.addr + - ((prog.blocknum - 2) * - dfu_function.wTransferSize); - for(i = 0; i < prog.len; i += 2) - flash_program_half_word(baseaddr + i, - *(u16*)(prog.buf+i)); - } - flash_lock(); - - /* We jump straight to dfuDNLOAD-IDLE, - * skipping dfuDNLOAD-SYNC - */ - usbdfu_state = STATE_DFU_DNLOAD_IDLE; - return; - - case STATE_DFU_MANIFEST: - /* USB device must detach, we just reset... */ - scb_reset_system(); - return; /* Will never return */ - default: - return; - } -} - -static int usbdfu_control_request(struct usb_setup_data *req, u8 **buf, - u16 *len, void (**complete)(struct usb_setup_data *req)) -{ - - if((req->bmRequestType & 0x7F) != 0x21) - return 0; /* Only accept class request */ - - switch(req->bRequest) { - case DFU_DNLOAD: - if((len == NULL) || (*len == 0)) { - usbdfu_state = STATE_DFU_MANIFEST_SYNC; - return 1; - } else { - /* Copy download data for use on GET_STATUS */ - prog.blocknum = req->wValue; - prog.len = *len; - memcpy(prog.buf, *buf, *len); - usbdfu_state = STATE_DFU_DNLOAD_SYNC; - return 1; - } - case DFU_CLRSTATUS: - /* Clear error and return to dfuIDLE */ - if(usbdfu_state == STATE_DFU_ERROR) - usbdfu_state = STATE_DFU_IDLE; - return 1; - case DFU_ABORT: - /* Abort returns to dfuIDLE state */ - usbdfu_state = STATE_DFU_IDLE; - return 1; - case DFU_UPLOAD: - /* Upload not supported for now */ - return 0; - case DFU_GETSTATUS: { - u32 bwPollTimeout = 0; /* 24-bit integer in DFU class spec */ - - (*buf)[0] = usbdfu_getstatus(&bwPollTimeout); - (*buf)[1] = bwPollTimeout & 0xFF; - (*buf)[2] = (bwPollTimeout >> 8) & 0xFF; - (*buf)[3] = (bwPollTimeout >> 16) & 0xFF; - (*buf)[4] = usbdfu_state; - (*buf)[5] = 0; /* iString not used here */ - *len = 6; - - *complete = usbdfu_getstatus_complete; - - return 1; - } - case DFU_GETSTATE: - /* Return state with no state transision */ - *buf[0] = usbdfu_state; - *len = 1; - return 1; - } - - return 0; -} - -int main(void) -{ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); - if(!gpio_get(GPIOA, GPIO10)) { - /* Boot the application if it's valid */ - if((*(volatile u32*)APP_ADDRESS & 0x2FFE0000) == 0x20000000) { - /* Set vector table base address */ - SCB_VTOR = APP_ADDRESS & 0xFFFF; - /* Initialise master stack pointer */ - asm volatile ("msr msp, %0"::"g" - (*(volatile u32*)APP_ADDRESS)); - /* Jump to application */ - (*(void(**)())(APP_ADDRESS + 4))(); - } - } - - rcc_clock_setup_in_hsi_out_48mhz(); - - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_AFIOEN); - - AFIO_MAPR |= AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_ON; - gpio_set_mode(GPIOA, GPIO_MODE_INPUT, 0, GPIO15); - - usbd_init(&stm32f103_usb_driver, &dev, &config, usb_strings); - usbd_set_control_buffer_size(sizeof(usbd_control_buffer)); - usbd_register_control_callback( - USB_REQ_TYPE_CLASS | USB_REQ_TYPE_INTERFACE, - USB_REQ_TYPE_TYPE | USB_REQ_TYPE_RECIPIENT, - usbdfu_control_request); - - gpio_set(GPIOA, GPIO15); - gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_2_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO15); - - while (1) - usbd_poll(); -} diff --git a/examples/stm32/lisa-m/usb_dfu/usbdfu.ld b/examples/stm32/lisa-m/usb_dfu/usbdfu.ld deleted file mode 100644 index 54e5dac..0000000 --- a/examples/stm32/lisa-m/usb_dfu/usbdfu.ld +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* Define memory regions. */ -MEMORY -{ - rom (rx) : ORIGIN = 0x08000000, LENGTH = 8K - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 4K -} - -/* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld - diff --git a/examples/stm32/lisa-m/usb_hid/Makefile b/examples/stm32/lisa-m/usb_hid/Makefile deleted file mode 100644 index d831e9e..0000000 --- a/examples/stm32/lisa-m/usb_hid/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2009 Uwe Hermann -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program. If not, see . -## - -BINARY = usbhid - -include ../../Makefile.include - diff --git a/examples/stm32/lisa-m/usb_hid/README b/examples/stm32/lisa-m/usb_hid/README deleted file mode 100644 index 48a9b39..0000000 --- a/examples/stm32/lisa-m/usb_hid/README +++ /dev/null @@ -1,7 +0,0 @@ ------------------------------------------------------------------------------- -README ------------------------------------------------------------------------------- - -This example implements a USB Human Interface Device (HID) -to demonstrate the use of the USB device stack. - diff --git a/examples/stm32/lisa-m/usb_hid/usbhid.c b/examples/stm32/lisa-m/usb_hid/usbhid.c deleted file mode 100644 index f42454b..0000000 --- a/examples/stm32/lisa-m/usb_hid/usbhid.c +++ /dev/null @@ -1,289 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Gareth McMullin - * Copyright (C) 2011 Piotr Esden-Tempski - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include -#include -#include -#include -#include - -/* Define this to include the DFU APP interface. */ -#define INCLUDE_DFU_INTERFACE - -#ifdef INCLUDE_DFU_INTERFACE -#include -#include -#endif - -const struct usb_device_descriptor dev = { - .bLength = USB_DT_DEVICE_SIZE, - .bDescriptorType = USB_DT_DEVICE, - .bcdUSB = 0x0200, - .bDeviceClass = 0, - .bDeviceSubClass = 0, - .bDeviceProtocol = 0, - .bMaxPacketSize0 = 64, - .idVendor = 0x0483, - .idProduct = 0x5710, - .bcdDevice = 0x0200, - .iManufacturer = 1, - .iProduct = 2, - .iSerialNumber = 3, - .bNumConfigurations = 1, -}; - -/* I have no idea what this means. I haven't read the HID spec. */ -static const u8 hid_report_descriptor[] = { - 0x05, 0x01, 0x09, 0x02, 0xA1, 0x01, 0x09, 0x01, - 0xA1, 0x00, 0x05, 0x09, 0x19, 0x01, 0x29, 0x03, - 0x15, 0x00, 0x25, 0x01, 0x95, 0x03, 0x75, 0x01, - 0x81, 0x02, 0x95, 0x01, 0x75, 0x05, 0x81, 0x01, - 0x05, 0x01, 0x09, 0x30, 0x09, 0x31, 0x09, 0x38, - 0x15, 0x81, 0x25, 0x7F, 0x75, 0x08, 0x95, 0x03, - 0x81, 0x06, 0xC0, 0x09, 0x3c, 0x05, 0xff, 0x09, - 0x01, 0x15, 0x00, 0x25, 0x01, 0x75, 0x01, 0x95, - 0x02, 0xb1, 0x22, 0x75, 0x06, 0x95, 0x01, 0xb1, - 0x01, 0xc0 -}; - -static const struct { - struct usb_hid_descriptor hid_descriptor; - struct { - u8 bReportDescriptorType; - u16 wDescriptorLength; - } __attribute__((packed)) hid_report; -} __attribute__((packed)) hid_function = { - .hid_descriptor = { - .bLength = sizeof(hid_function), - .bDescriptorType = USB_DT_HID, - .bcdHID = 0x0100, - .bCountryCode = 0, - .bNumDescriptors = 1, - }, - .hid_report = { - .bReportDescriptorType = USB_DT_REPORT, - .wDescriptorLength = sizeof(hid_report_descriptor), - } -}; - -const struct usb_endpoint_descriptor hid_endpoint = { - .bLength = USB_DT_ENDPOINT_SIZE, - .bDescriptorType = USB_DT_ENDPOINT, - .bEndpointAddress = 0x81, - .bmAttributes = USB_ENDPOINT_ATTR_INTERRUPT, - .wMaxPacketSize = 4, - .bInterval = 0x20, -}; - -const struct usb_interface_descriptor hid_iface = { - .bLength = USB_DT_INTERFACE_SIZE, - .bDescriptorType = USB_DT_INTERFACE, - .bInterfaceNumber = 0, - .bAlternateSetting = 0, - .bNumEndpoints = 1, - .bInterfaceClass = USB_CLASS_HID, - .bInterfaceSubClass = 1, /* boot */ - .bInterfaceProtocol = 2, /* mouse */ - .iInterface = 0, - - .endpoint = &hid_endpoint, - - .extra = &hid_function, - .extralen = sizeof(hid_function), -}; - -#ifdef INCLUDE_DFU_INTERFACE -const struct usb_dfu_descriptor dfu_function = { - .bLength = sizeof(struct usb_dfu_descriptor), - .bDescriptorType = DFU_FUNCTIONAL, - .bmAttributes = USB_DFU_CAN_DOWNLOAD | USB_DFU_WILL_DETACH, - .wDetachTimeout = 255, - .wTransferSize = 1024, - .bcdDFUVersion = 0x011A, -}; - -const struct usb_interface_descriptor dfu_iface = { - .bLength = USB_DT_INTERFACE_SIZE, - .bDescriptorType = USB_DT_INTERFACE, - .bInterfaceNumber = 1, - .bAlternateSetting = 0, - .bNumEndpoints = 0, - .bInterfaceClass = 0xFE, - .bInterfaceSubClass = 1, - .bInterfaceProtocol = 1, - .iInterface = 0, - - .extra = &dfu_function, - .extralen = sizeof(dfu_function), -}; -#endif - -const struct usb_interface ifaces[] = {{ - .num_altsetting = 1, - .altsetting = &hid_iface, -#ifdef INCLUDE_DFU_INTERFACE -}, { - .num_altsetting = 1, - .altsetting = &dfu_iface, -#endif -}}; - -const struct usb_config_descriptor config = { - .bLength = USB_DT_CONFIGURATION_SIZE, - .bDescriptorType = USB_DT_CONFIGURATION, - .wTotalLength = 0, -#ifdef INCLUDE_DFU_INTERFACE - .bNumInterfaces = 2, -#else - .bNumInterfaces = 1, -#endif - .bConfigurationValue = 1, - .iConfiguration = 0, - .bmAttributes = 0xC0, - .bMaxPower = 0x32, - - .interface = ifaces, -}; - -static const char *usb_strings[] = { - "x", - "Black Sphere Technologies", - "HID Demo", - "DEMO", -}; - -static int hid_control_request(struct usb_setup_data *req, u8 **buf, u16 *len, - void (**complete)(struct usb_setup_data *req)) -{ - (void)complete; - - if((req->bmRequestType != 0x81) || - (req->bRequest != USB_REQ_GET_DESCRIPTOR) || - (req->wValue != 0x2200)) - return 0; - - /* Handle the HID report descriptor */ - *buf = (u8*)hid_report_descriptor; - *len = sizeof(hid_report_descriptor); - - return 1; -} - -#ifdef INCLUDE_DFU_INTERFACE -static void dfu_detach_complete(struct usb_setup_data *req) -{ - (void)req; - - gpio_set_mode(GPIOA, GPIO_MODE_INPUT, 0, GPIO15); - gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_2_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO10); - gpio_set(GPIOA, GPIO10); - scb_reset_core(); -} - -static int dfu_control_request(struct usb_setup_data *req, u8 **buf, u16 *len, - void (**complete)(struct usb_setup_data *req)) -{ - (void)buf; - (void)len; - - if((req->bmRequestType != 0x21) || (req->bRequest != DFU_DETACH)) - return 0; /* Only accept class request */ - - *complete = dfu_detach_complete; - - return 1; -} -#endif - -static void hid_set_config(u16 wValue) -{ - (void)wValue; - - usbd_ep_setup(0x81, USB_ENDPOINT_ATTR_INTERRUPT, 4, NULL); - - usbd_register_control_callback( - USB_REQ_TYPE_STANDARD | USB_REQ_TYPE_INTERFACE, - USB_REQ_TYPE_TYPE | USB_REQ_TYPE_RECIPIENT, - hid_control_request); -#ifdef INCLUDE_DFU_INTERFACE - usbd_register_control_callback( - USB_REQ_TYPE_CLASS | USB_REQ_TYPE_INTERFACE, - USB_REQ_TYPE_TYPE | USB_REQ_TYPE_RECIPIENT, - dfu_control_request); -#endif - - systick_set_clocksource(STK_CTRL_CLKSOURCE_AHB_DIV8); - systick_set_reload(100000); - systick_interrupt_enable(); - systick_counter_enable(); -} - -int main(void) -{ - int usb_connect_blink = 0; - rcc_clock_setup_in_hse_12mhz_out_72mhz(); - - - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); - - /* USB_DETECT as input */ - gpio_set_mode(GPIOA, GPIO_MODE_INPUT, - GPIO_CNF_INPUT_FLOAT, GPIO8); - - /* green LED off, as output */ - gpio_set(GPIOC, GPIO2); - gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_2_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO2); - - - usbd_init(&stm32f107_usb_driver, &dev, &config, usb_strings); - usbd_register_set_config_callback(hid_set_config); - - /* delay some seconds to show that pull-up switch works */ - {int i; for (i=0;i<0x800000;i++) asm("nop");} - - /* wait for USB Vbus */ - while(gpio_get(GPIOA, GPIO8) == 0) asm("nop"); - - /* green LED on, connect USB */ - gpio_clear(GPIOC, GPIO2); - //OTG_FS_GCCFG &= ~OTG_FS_GCCFG_VBUSBSEN; - - while (1) - usbd_poll(); -} - -void sys_tick_handler(void) -{ - static int x = 0; - static int dir = 1; - u8 buf[4] = {0, 0, 0, 0}; - - buf[1] = dir; - x += dir; - if(x > 30) dir = -dir; - if(x < -30) dir = -dir; - - usbd_ep_write_packet(0x81, buf, 4); -} diff --git a/examples/stm32/lisa-m/usb_hid/usbhid.ld b/examples/stm32/lisa-m/usb_hid/usbhid.ld deleted file mode 100644 index 928c898..0000000 --- a/examples/stm32/lisa-m/usb_hid/usbhid.ld +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* Linker script for Olimex STM32-H103 (STM32F103RBT6, 128K flash, 20K RAM). */ - -/* Define memory regions. */ -MEMORY -{ - rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K -} - -/* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld - diff --git a/examples/stm32/mb525/fancyblink/Makefile b/examples/stm32/mb525/fancyblink/Makefile deleted file mode 100644 index 1baec4d..0000000 --- a/examples/stm32/mb525/fancyblink/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2009 Uwe Hermann -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program. If not, see . -## - -BINARY = fancyblink - -include ../../Makefile.include - diff --git a/examples/stm32/mb525/fancyblink/README b/examples/stm32/mb525/fancyblink/README deleted file mode 100644 index 226cb21..0000000 --- a/examples/stm32/mb525/fancyblink/README +++ /dev/null @@ -1,10 +0,0 @@ ------------------------------------------------------------------------------- -README ------------------------------------------------------------------------------- - -This is a blink example program using libopencm3. - -It's intended for the ST STM32-based MB525 eval board (see -http://www.st.com/stonline/products/literature/um/13472.htm for details). -It should blink the LED on the board. - diff --git a/examples/stm32/mb525/fancyblink/fancyblink.c b/examples/stm32/mb525/fancyblink/fancyblink.c deleted file mode 100644 index e9a3564..0000000 --- a/examples/stm32/mb525/fancyblink/fancyblink.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann , - * Copyright (C) 2010 Piotr Esden-Tempski - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include - -void clock_setup(void) -{ - rcc_clock_setup_in_hse_8mhz_out_72mhz(); - - /* Enable GPIOC clock. */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); -} - -void gpio_setup(void) -{ - /* Set GPIO6 (in GPIO port C) to 'output push-pull'. */ - gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO6 | GPIO7 | GPIO8 | GPIO9); -} - -int main(void) -{ - int i; - - clock_setup(); - gpio_setup(); - - /* Blink the LED (PC12) on the board. */ - gpio_set(GPIOC, GPIO6); - while (1) { - gpio_toggle(GPIOC, GPIO6); /* LED on/off */ - gpio_toggle(GPIOC, GPIO7); /* LED on/off */ - for (i = 0; i < 4000000; i++) /* Wait a bit. */ - __asm__("nop"); - gpio_toggle(GPIOC, GPIO7); /* LED on/off */ - gpio_toggle(GPIOC, GPIO8); /* LED on/off */ - for (i = 0; i < 4000000; i++) /* Wait a bit. */ - __asm__("nop"); - gpio_toggle(GPIOC, GPIO8); /* LED on/off */ - gpio_toggle(GPIOC, GPIO9); /* LED on/off */ - for (i = 0; i < 4000000; i++) /* Wait a bit. */ - __asm__("nop"); - gpio_toggle(GPIOC, GPIO8); /* LED on/off */ - gpio_toggle(GPIOC, GPIO9); /* LED on/off */ - for (i = 0; i < 4000000; i++) /* Wait a bit. */ - __asm__("nop"); - gpio_toggle(GPIOC, GPIO7); /* LED on/off */ - gpio_toggle(GPIOC, GPIO8); /* LED on/off */ - for (i = 0; i < 4000000; i++) /* Wait a bit. */ - __asm__("nop"); - gpio_toggle(GPIOC, GPIO6); /* LED on/off */ - gpio_toggle(GPIOC, GPIO7); /* LED on/off */ - for (i = 0; i < 4000000; i++) /* Wait a bit. */ - __asm__("nop"); - } - - return 0; -} diff --git a/examples/stm32/mb525/fancyblink/fancyblink.ld b/examples/stm32/mb525/fancyblink/fancyblink.ld deleted file mode 100644 index 7ea2b92..0000000 --- a/examples/stm32/mb525/fancyblink/fancyblink.ld +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* Linker script for Olimex STM32-H103 (STM32F103RBT6, 128K flash, 20K RAM). */ - -/* Define memory regions. */ -MEMORY -{ - rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K -} - -/* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld - diff --git a/examples/stm32/mb525/pwmleds/Makefile b/examples/stm32/mb525/pwmleds/Makefile deleted file mode 100644 index 8ae74d6..0000000 --- a/examples/stm32/mb525/pwmleds/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2009 Uwe Hermann -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program. If not, see . -## - -BINARY = pwmleds - -include ../../Makefile.include - diff --git a/examples/stm32/mb525/pwmleds/README b/examples/stm32/mb525/pwmleds/README deleted file mode 100644 index b2a6d95..0000000 --- a/examples/stm32/mb525/pwmleds/README +++ /dev/null @@ -1,10 +0,0 @@ ------------------------------------------------------------------------------- -README ------------------------------------------------------------------------------- - -This is a PWM based LED fading example using libopencm3. - -It's intended for the ST STM32-based MB525 eval board (see -http://www.st.com/stonline/products/literature/um/13472.htm for details). -It should blink the LED on the board. - diff --git a/examples/stm32/mb525/pwmleds/pwmleds.c b/examples/stm32/mb525/pwmleds/pwmleds.c deleted file mode 100644 index 393928f..0000000 --- a/examples/stm32/mb525/pwmleds/pwmleds.c +++ /dev/null @@ -1,496 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include - -// #define COMPARE -// #define MOVING_FADE -#define KITT - -#ifdef COMPARE -#define GAMMA_LINEAR -#define GAMMA_1_3 -#define GAMMA_2_5 -#define GAMMA_3_0 -#endif - -#ifdef MOVING_FADE -#define GAMMA_2_2 -#define GAMMA_TABLE gamma_table_2_2 -#endif - -#ifdef KITT -#define GAMMA_2_5 -#define GAMMA_TABLE gamma_table_2_5 -#endif - -/* - * Gamma correction table - * - * The nonlinear tables are calculating with the function: - * Iout = Iin ** gamma - */ -#ifdef GAMMA_LINEAR -static const u16 gamma_table_linear[] = { - 1, 4, 9, 17, 26, 37, 51, 67, - 84, 104, 126, 149, 175, 203, 233, 265, - 299, 334, 372, 412, 454, 499, 545, 593, - 643, 695, 749, 805, 864, 924, 986, 1050, - 1116, 1185, 1255, 1327, 1402, 1478, 1556, 1637, - 1719, 1803, 1890, 1978, 2068, 2161, 2255, 2352, - 2450, 2550, 2653, 2757, 2864, 2972, 3082, 3195, - 3309, 3426, 3544, 3664, 3787, 3911, 4038, 4166, - 4296, 4429, 4563, 4700, 4838, 4978, 5121, 5265, - 5411, 5560, 5710, 5862, 6017, 6173, 6331, 6492, - 6654, 6818, 6985, 7153, 7323, 7495, 7670, 7846, - 8024, 8204, 8387, 8571, 8757, 8945, 9135, 9327, - 9521, 9718, 9916, 10116, 10318, 10522, 10728, 10936, - 11146, 11358, 11572, 11788, 12006, 12226, 12448, 12672, - 12897, 13125, 13355, 13587, 13821, 14057, 14294, 14534, - 14776, 15020, 15265, 15513, 15763, 16014, 16268, 16524, - 16781, 17041, 17302, 17566, 17831, 18099, 18368, 18640, - 18913, 19189, 19466, 19745, 20027, 20310, 20595, 20883, - 21172, 21463, 21756, 22051, 22349, 22648, 22949, 23252, - 23557, 23864, 24173, 24484, 24797, 25112, 25429, 25748, - 26069, 26391, 26716, 27043, 27372, 27702, 28035, 28370, - 28707, 29045, 29386, 29728, 30073, 30419, 30768, 31118, - 31471, 31825, 32182, 32540, 32900, 33263, 33627, 33993, - 34361, 34731, 35104, 35478, 35854, 36232, 36612, 36994, - 37378, 37764, 38152, 38542, 38933, 39327, 39723, 40121, - 40521, 40922, 41326, 41732, 42139, 42549, 42960, 43374, - 43789, 44207, 44626, 45048, 45471, 45896, 46324, 46753, - 47184, 47617, 48052, 48490, 48929, 49370, 49813, 50258, - 50705, 51154, 51604, 52057, 52512, 52969, 53428, 53888, - 54351, 54816, 55282, 55751, 56222, 56694, 57169, 57645, - 58123, 58604, 59086, 59570, 60057, 60545, 61035, 61527, - 62021, 62517, 63016, 63516, 64018, 64521, 65027, 65535, -}; -#endif - -#ifdef GAMMA_1_3 -static const u16 gamma_table_1_3[] = { - /* Gamma 1.3 */ - 0, 49, 120, 203, 296, 395, 501, 612, - 728, 848, 973, 1101, 1233, 1368, 1506, 1648, - 1792, 1939, 2088, 2241, 2395, 2552, 2711, 2872, - 3036, 3201, 3369, 3538, 3709, 3882, 4057, 4234, - 4412, 4592, 4774, 4957, 5142, 5329, 5517, 5706, - 5897, 6090, 6283, 6479, 6675, 6873, 7072, 7273, - 7475, 7678, 7882, 8088, 8294, 8502, 8711, 8922, - 9133, 9346, 9559, 9774, 9990, 10207, 10425, 10644, - 10864, 11086, 11308, 11531, 11755, 11981, 12207, 12434, - 12662, 12891, 13121, 13352, 13584, 13817, 14051, 14285, - 14521, 14757, 14994, 15233, 15472, 15712, 15952, 16194, - 16436, 16679, 16923, 17168, 17414, 17660, 17908, 18156, - 18405, 18654, 18905, 19156, 19408, 19660, 19914, 20168, - 20423, 20679, 20935, 21192, 21450, 21708, 21968, 22228, - 22488, 22750, 23012, 23275, 23538, 23802, 24067, 24332, - 24599, 24865, 25133, 25401, 25670, 25939, 26209, 26480, - 26751, 27023, 27296, 27569, 27843, 28118, 28393, 28669, - 28945, 29222, 29500, 29778, 30057, 30336, 30616, 30897, - 31178, 31460, 31742, 32025, 32308, 32592, 32877, 33162, - 33448, 33734, 34021, 34309, 34597, 34885, 35175, 35464, - 35754, 36045, 36337, 36628, 36921, 37214, 37507, 37801, - 38096, 38391, 38686, 38982, 39279, 39576, 39874, 40172, - 40471, 40770, 41070, 41370, 41670, 41972, 42273, 42576, - 42878, 43181, 43485, 43789, 44094, 44399, 44705, 45011, - 45317, 45625, 45932, 46240, 46549, 46858, 47167, 47477, - 47787, 48098, 48409, 48721, 49034, 49346, 49659, 49973, - 50287, 50602, 50917, 51232, 51548, 51864, 52181, 52498, - 52816, 53134, 53452, 53771, 54091, 54411, 54731, 55052, - 55373, 55694, 56016, 56339, 56662, 56985, 57309, 57633, - 57957, 58282, 58608, 58933, 59260, 59586, 59913, 60241, - 60569, 60897, 61226, 61555, 61884, 62214, 62545, 62875, - 63206, 63538, 63870, 64202, 64535, 64868, 65201, 65535, -}; -#endif - -#ifdef GAMMA_2_2 -static const u16 gamma_table_2_2[] = { - 0, 0, 2, 4, 7, 11, 17, 24, - 32, 42, 53, 65, 79, 94, 111, 129, - 148, 169, 192, 216, 242, 270, 299, 330, - 362, 396, 432, 469, 508, 549, 591, 635, - 681, 729, 779, 830, 883, 938, 995, 1053, - 1113, 1175, 1239, 1305, 1373, 1443, 1514, 1587, - 1663, 1740, 1819, 1900, 1983, 2068, 2155, 2243, - 2334, 2427, 2521, 2618, 2717, 2817, 2920, 3024, - 3131, 3240, 3350, 3463, 3578, 3694, 3813, 3934, - 4057, 4182, 4309, 4438, 4570, 4703, 4838, 4976, - 5115, 5257, 5401, 5547, 5695, 5845, 5998, 6152, - 6309, 6468, 6629, 6792, 6957, 7124, 7294, 7466, - 7640, 7816, 7994, 8175, 8358, 8543, 8730, 8919, - 9111, 9305, 9501, 9699, 9900, 10102, 10307, 10515, - 10724, 10936, 11150, 11366, 11585, 11806, 12029, 12254, - 12482, 12712, 12944, 13179, 13416, 13655, 13896, 14140, - 14386, 14635, 14885, 15138, 15394, 15652, 15912, 16174, - 16439, 16706, 16975, 17247, 17521, 17798, 18077, 18358, - 18642, 18928, 19216, 19507, 19800, 20095, 20393, 20694, - 20996, 21301, 21609, 21919, 22231, 22546, 22863, 23182, - 23504, 23829, 24156, 24485, 24817, 25151, 25487, 25826, - 26168, 26512, 26858, 27207, 27558, 27912, 28268, 28627, - 28988, 29351, 29717, 30086, 30457, 30830, 31206, 31585, - 31966, 32349, 32735, 33124, 33514, 33908, 34304, 34702, - 35103, 35507, 35913, 36321, 36732, 37146, 37562, 37981, - 38402, 38825, 39252, 39680, 40112, 40546, 40982, 41421, - 41862, 42306, 42753, 43202, 43654, 44108, 44565, 45025, - 45487, 45951, 46418, 46888, 47360, 47835, 48313, 48793, - 49275, 49761, 50249, 50739, 51232, 51728, 52226, 52727, - 53230, 53736, 54245, 54756, 55270, 55787, 56306, 56828, - 57352, 57879, 58409, 58941, 59476, 60014, 60554, 61097, - 61642, 62190, 62741, 63295, 63851, 64410, 64971, 65535 -}; -#endif - -#ifdef GAMMA_2_5 -static const u16 gamma_table_2_5[] = { - /* gamma = 2.5 */ - 0, 0, 0, 1, 2, 4, 6, 8, - 11, 15, 20, 25, 31, 38, 46, 55, - 65, 75, 87, 99, 113, 128, 143, 160, - 178, 197, 218, 239, 262, 286, 311, 338, - 366, 395, 425, 457, 491, 526, 562, 599, - 639, 679, 722, 765, 811, 857, 906, 956, - 1007, 1061, 1116, 1172, 1231, 1291, 1352, 1416, - 1481, 1548, 1617, 1688, 1760, 1834, 1910, 1988, - 2068, 2150, 2233, 2319, 2407, 2496, 2587, 2681, - 2776, 2874, 2973, 3075, 3178, 3284, 3391, 3501, - 3613, 3727, 3843, 3961, 4082, 4204, 4329, 4456, - 4585, 4716, 4850, 4986, 5124, 5264, 5407, 5552, - 5699, 5849, 6001, 6155, 6311, 6470, 6632, 6795, - 6962, 7130, 7301, 7475, 7650, 7829, 8009, 8193, - 8379, 8567, 8758, 8951, 9147, 9345, 9546, 9750, - 9956, 10165, 10376, 10590, 10806, 11025, 11247, 11472, - 11699, 11929, 12161, 12397, 12634, 12875, 13119, 13365, - 13614, 13865, 14120, 14377, 14637, 14899, 15165, 15433, - 15705, 15979, 16256, 16535, 16818, 17104, 17392, 17683, - 17978, 18275, 18575, 18878, 19184, 19493, 19805, 20119, - 20437, 20758, 21082, 21409, 21739, 22072, 22407, 22746, - 23089, 23434, 23782, 24133, 24487, 24845, 25206, 25569, - 25936, 26306, 26679, 27055, 27435, 27818, 28203, 28592, - 28985, 29380, 29779, 30181, 30586, 30994, 31406, 31820, - 32239, 32660, 33085, 33513, 33944, 34379, 34817, 35258, - 35702, 36150, 36602, 37056, 37514, 37976, 38441, 38909, - 39380, 39856, 40334, 40816, 41301, 41790, 42282, 42778, - 43277, 43780, 44286, 44795, 45308, 45825, 46345, 46869, - 47396, 47927, 48461, 48999, 49540, 50085, 50634, 51186, - 51742, 52301, 52864, 53431, 54001, 54575, 55153, 55734, - 56318, 56907, 57499, 58095, 58695, 59298, 59905, 60515, - 61130, 61748, 62370, 62995, 63624, 64258, 64894, 65535, -}; -#endif - -#ifdef GAMMA_3_0 -static const u16 gamma_table_3_0[] = { - /* gamma = 3.0 */ - 0, 0, 0, 0, 0, 0, 1, 1, - 2, 3, 4, 5, 7, 9, 11, 13, - 16, 19, 23, 27, 32, 37, 42, 48, - 55, 62, 69, 78, 87, 96, 107, 118, - 130, 142, 155, 169, 184, 200, 217, 234, - 253, 272, 293, 314, 337, 360, 385, 410, - 437, 465, 494, 524, 556, 588, 622, 658, - 694, 732, 771, 812, 854, 897, 942, 988, - 1036, 1085, 1136, 1189, 1243, 1298, 1356, 1415, - 1475, 1538, 1602, 1667, 1735, 1804, 1876, 1949, - 2024, 2100, 2179, 2260, 2343, 2427, 2514, 2603, - 2693, 2786, 2881, 2978, 3078, 3179, 3283, 3389, - 3497, 3607, 3720, 3835, 3952, 4072, 4194, 4319, - 4446, 4575, 4707, 4842, 4979, 5118, 5261, 5405, - 5553, 5703, 5856, 6011, 6169, 6330, 6494, 6660, - 6830, 7002, 7177, 7355, 7536, 7719, 7906, 8096, - 8289, 8484, 8683, 8885, 9090, 9298, 9510, 9724, - 9942, 10163, 10387, 10614, 10845, 11079, 11317, 11557, - 11802, 12049, 12300, 12555, 12813, 13074, 13339, 13608, - 13880, 14156, 14435, 14718, 15005, 15295, 15589, 15887, - 16189, 16494, 16803, 17117, 17433, 17754, 18079, 18408, - 18740, 19077, 19418, 19762, 20111, 20464, 20821, 21182, - 21547, 21917, 22290, 22668, 23050, 23436, 23827, 24222, - 24621, 25025, 25433, 25845, 26262, 26683, 27109, 27539, - 27974, 28413, 28857, 29306, 29759, 30217, 30680, 31147, - 31619, 32095, 32577, 33063, 33554, 34050, 34551, 35056, - 35567, 36082, 36602, 37128, 37658, 38194, 38734, 39280, - 39830, 40386, 40947, 41513, 42084, 42661, 43243, 43830, - 44422, 45019, 45622, 46231, 46844, 47463, 48088, 48718, - 49353, 49994, 50641, 51293, 51950, 52614, 53282, 53957, - 54637, 55323, 56014, 56712, 57415, 58123, 58838, 59558, - 60285, 61017, 61755, 62499, 63249, 64005, 64767, 65535, -}; -#endif - -void clock_setup(void) -{ - rcc_clock_setup_in_hse_8mhz_out_72mhz(); - - /* Enable TIM1 clock. */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_TIM1EN); - - /* Enable GPIOC, Alternate Function clocks. */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, - RCC_APB2ENR_IOPAEN | RCC_APB2ENR_AFIOEN); -} - -void gpio_setup(void) -{ - /* - * Set GPIO6 (in GPIO port C) to - * 'output alternate function push-pull'. - */ - gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, - GPIO_TIM1_CH1 | - GPIO_TIM1_CH2 | - GPIO_TIM1_CH3 | - GPIO_TIM1_CH4); - - /* Remap TIM1: - * CH1 -> PC6 - * CH2 -> PC7 - * CH3 -> PC8 - * CH4 -> PC9 - */ - //AFIO_MAPR |= AFIO_MAPR_TIM3_REMAP_FULL_REMAP; -} -void tim_setup(void) -{ -#if 0 - TIM1_CR1 = TIM_CR1_CMS_CENTER_1 | TIM_CR1_ARPE; - TIM1_CCMR1 = TIM_CCMR1_OC1M_PWM1 | TIM_CCMR1_OC1PE | TIM_CCMR1_OC2M_PWM1 | TIM_CCMR1_OC2PE; - TIM1_CCMR2 = TIM_CCMR2_OC3M_PWM1 | TIM_CCMR2_OC3PE; - - TIM1_CCER &= ~TIM_CCER_CC1P; -#endif -#if 1 - TIM1_SMCR &= ~TIM_SMCR_SMS_MASK; - TIM1_CR1 &= ~TIM_CR1_CEN; - - /* Clock division and mode */ - TIM1_CR1 = TIM_CR1_CKD_CK_INT | TIM_CR1_CMS_EDGE; - /* Period */ - TIM1_ARR = 65535; - /* Prescaler */ - TIM1_PSC = 2; - TIM1_EGR = TIM_EGR_UG; - - /* ---- */ - /* Output compare 1 mode and preload */ - TIM1_CCMR1 |= TIM_CCMR1_OC1M_PWM1 | TIM_CCMR1_OC1PE; - - /* Polarity and state */ - // TIM1_CCER = TIM_CCER_CC1P | TIM_CCER_CC1E; - TIM1_CCER |= TIM_CCER_CC1E; - - /* Capture compare value */ - TIM1_CCR1 = 1000; - - /* ---- */ - /* Output compare 2 mode and preload */ - TIM1_CCMR1 |= TIM_CCMR1_OC2M_PWM1 | TIM_CCMR1_OC2PE; - - /* Polarity and state */ - // TIM1_CCER = TIM_CCER_CC1P | TIM_CCER_CC1E; - TIM1_CCER |= TIM_CCER_CC2E; - - /* Capture compare value */ - TIM1_CCR2 = 1000; - - /* ---- */ - /* Output compare 3 mode and preload */ - TIM1_CCMR2 |= TIM_CCMR2_OC3M_PWM1 | TIM_CCMR2_OC3PE; - - /* Polarity and state */ - // TIM1_CCER = TIM_CCER_CC1P | TIM_CCER_CC1E; - TIM1_CCER |= TIM_CCER_CC3E; - - /* Capture compare value */ - TIM1_CCR3 = 1000; - - /* ---- */ - /* Output compare 4 mode and preload */ - TIM1_CCMR2 |= TIM_CCMR2_OC4M_PWM1 | TIM_CCMR2_OC4PE; - - /* Polarity and state */ - // TIM1_CCER = TIM_CCER_CC1P | TIM_CCER_CC1E; - TIM1_CCER |= TIM_CCER_CC4E; - - /* Capture compare value */ - TIM1_CCR4 = 1000; - - /* ---- */ - /* ARR reload enable */ - TIM1_CR1 |= TIM_CR1_ARPE; - - TIM1_BDTR |= TIM_BDTR_MOE; - - /* Counter enable */ - TIM1_CR1 |= TIM_CR1_CEN; -#endif -} - -int main(void) -{ - int i, j0, j1, j2, j3, d0, d1, d2, d3, j, k, kd; - - clock_setup(); - gpio_setup(); - tim_setup(); - -#ifdef COMPARE - j0 = 0; - d0 = 1; - j1 = 0; - d1 = 1; - j2 = 0; - d2 = 1; - j3 = 0; - d3 = 1; - while (1) { - TIM1_CCR1 = gamma_table_linear[j0]; - j0 += d0; - if (j0 == 255) - d0 =- 1; - if (j0 == 0) - d0 = 1; - TIM1_CCR2 = gamma_table_1_3[j1]; - j1 += d1; - if (j1 == 255) - d1 =- 1; - if (j1 == 0) - d1 = 1; - TIM1_CCR3 = gamma_table_2_5[j2]; - j2 += d2; - if (j2 == 255) - d2 =- 1; - if (j2 == 0) - d2 = 1; - TIM1_CCR4= gamma_table_3_0[j3]; - j3 += d3; - if (j3 == 255) - d3 =- 1; - if (j3 == 0) - d3 = 1; - for (i = 0; i < 50000; i++); - } -#endif - -#ifdef MOVING_FADE - j0 = 0; - d0 = 1; - j1 = 128; - d1 = 1; - j2 = 255; - d2 = -1; - j3 = 128; - d3 = -1; - while (1) { - TIM1_CCR1 = GAMMA_TABLE[j0]; - j0 += d0; - if (j0 == 255) - d0 =- 1; - if (j0 == 0) - d0 = 1; - TIM1_CCR2 = GAMMA_TABLE[j1]; - j1 += d1; - if (j1 == 255) - d1 =- 1; - if (j1 == 0) - d1 = 1; - TIM1_CCR3 = GAMMA_TABLE[j2]; - j2 += d2; - if (j2 == 255) - d2 =- 1; - if (j2 == 0) - d2 = 1; - TIM1_CCR4 = GAMMA_TABLE[j3]; - j3 += d3; - if (j3 == 255) - d3 =- 1; - if (j3 == 0) - d3 = 1; - for (i = 0; i < 10000; i++); - } -#endif - -#ifdef KITT - j0 = 255; - d0 = -1; - j1 = 20; - d1 = -1; - j2 = 20; - d2 = -1; - j3 = 20; - d3 = -1; - j = 0; - k = 0; - kd = 1; - while (1) { - TIM1_CCR1 = GAMMA_TABLE[j0]; - j0 += d0; - if (j0 == 255) - d0 =- 1; - if (j0 == 19) - j0 = 20; - TIM1_CCR2 = GAMMA_TABLE[j1]; - j1 += d1; - if (j1 == 255) - d1 =- 1; - if (j1 == 19) - j1 = 20; - TIM1_CCR3 = GAMMA_TABLE[j2]; - j2 += d2; - if (j2 == 255) - d2 =- 1; - if (j2 == 19) - j2 = 20; - TIM1_CCR4 = GAMMA_TABLE[j3]; - j3 += d3; - if (j3 == 255) - d3 =- 1; - if (j3 == 19) - j3 = 20; - for (i = 0; i < 5000; i++); - j++; - if (j == 100) { - j = 0; - switch (k += kd) { - case 0: - j0 = 255; - break; - case 1: - j1 = 255; - break; - case 2: - j2 = 255; - break; - case 3: - j3 = 255; - break; - } - if (k == 3) - kd =- 1; - if (k == 0) - kd = 1; - } - } -#endif - - return 0; -} diff --git a/examples/stm32/mb525/pwmleds/pwmleds.ld b/examples/stm32/mb525/pwmleds/pwmleds.ld deleted file mode 100644 index 7ea2b92..0000000 --- a/examples/stm32/mb525/pwmleds/pwmleds.ld +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* Linker script for Olimex STM32-H103 (STM32F103RBT6, 128K flash, 20K RAM). */ - -/* Define memory regions. */ -MEMORY -{ - rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K -} - -/* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld - diff --git a/examples/stm32/obldc/can/Makefile b/examples/stm32/obldc/can/Makefile deleted file mode 100644 index 20a4b90..0000000 --- a/examples/stm32/obldc/can/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2009 Uwe Hermann -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program. If not, see . -## - -BINARY = can - -include ../../Makefile.include - diff --git a/examples/stm32/obldc/can/can.c b/examples/stm32/obldc/can/can.c deleted file mode 100644 index 6c63c48..0000000 --- a/examples/stm32/obldc/can/can.c +++ /dev/null @@ -1,216 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * Copyright (C) 2010 Piotr Esden-Tempski - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include -#include -#include -#include - -struct can_tx_msg { - u32 std_id; - u32 ext_id; - u8 ide; - u8 rtr; - u8 dlc; - u8 data[8]; -}; - -struct can_rx_msg { - u32 std_id; - u32 ext_id; - u8 ide; - u8 rtr; - u8 dlc; - u8 data[8]; - u8 fmi; -}; - -struct can_tx_msg can_tx_msg; -struct can_rx_msg can_rx_msg; - -void gpio_setup(void) -{ - /* Enable GPIOA clock. */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); - - /* Enable GPIOB clock. */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPBEN); - - gpio_set(GPIOA, GPIO6); /* LED0 off */ - gpio_set(GPIOA, GPIO7); /* LED1 off */ - gpio_set(GPIOB, GPIO0); /* LED2 off */ - gpio_set(GPIOB, GPIO1); /* LED3 off */ - - /* Set GPIO6/7 (in GPIO port A) to 'output push-pull' for the LEDs. */ - gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO6); - gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO7); - - /* Set GPIO6/7 (in GPIO port B) to 'output push-pull' for the LEDs. */ - gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO0); - gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO1); -} - -void systick_setup(void) -{ - /* 72MHz / 8 => 9000000 counts per second */ - systick_set_clocksource(STK_CTRL_CLKSOURCE_AHB_DIV8); - - /* 9000000/9000 = 1000 overflows per second - every 1ms one interrupt */ - systick_set_reload(9000); - - systick_interrupt_enable(); - - /* Start counting. */ - systick_counter_enable(); -} - -void can_setup(void) -{ - /* Enable peripheral clocks. */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_AFIOEN); - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); - rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_CANEN); - - /* Configure CAN pin: RX (input pull-up). */ - gpio_set_mode(GPIOA, GPIO_MODE_INPUT, - GPIO_CNF_INPUT_PULL_UPDOWN, GPIO_CAN_RX); - gpio_set(GPIOA, GPIO_CAN_RX); - - /* Configure CAN pin: TX. */ - gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_CAN_TX); - - /* NVIC setup. */ - nvic_enable_irq(NVIC_USB_LP_CAN_RX0_IRQ); - nvic_set_priority(NVIC_USB_LP_CAN_RX0_IRQ, 1); - - /* Reset CAN. */ - can_reset(CAN1); - - /* CAN cell init. */ - if (can_init(CAN1, - false, /* TTCM: Time triggered comm mode? */ - true, /* ABOM: Automatic bus-off management? */ - false, /* AWUM: Automatic wakeup mode? */ - false, /* NART: No automatic retransmission? */ - false, /* RFLM: Receive FIFO locked mode? */ - false, /* TXFP: Transmit FIFO priority? */ - CAN_BTR_SJW_1TQ, - CAN_BTR_TS1_3TQ, - CAN_BTR_TS2_4TQ, - 12)) /* BRP+1: Baud rate prescaler */ - { - gpio_set(GPIOA, GPIO6); /* LED0 off */ - gpio_set(GPIOA, GPIO7); /* LED1 off */ - gpio_set(GPIOB, GPIO0); /* LED2 off */ - gpio_clear(GPIOB, GPIO1); /* LED3 on */ - - /* Die because we failed to initialize. */ - while (1) - __asm__("nop"); - } - - /* CAN filter 0 init. */ - can_filter_id_mask_32bit_init(CAN1, - 0, /* Filter ID */ - 0, /* CAN ID */ - 0, /* CAN ID mask */ - 0, /* FIFO assignment (here: FIFO0) */ - true); /* Enable the filter. */ - - /* Enable CAN RX interrupt. */ - can_enable_irq(CAN1, CAN_IER_FMPIE0); -} - -void sys_tick_handler(void) -{ - static int temp32 = 0; - static u8 data[8] = {0, 1, 2, 0, 0, 0, 0, 0}; - - /* We call this handler every 1ms so 1000ms = 1s on/off. */ - if (++temp32 != 1000) - return; - - temp32 = 0; - - /* Transmit CAN frame. */ - data[0]++; - if (can_transmit(CAN1, - 0, /* (EX/ST)ID: CAN ID */ - false, /* IDE: CAN ID extended? */ - false, /* RTR: Request transmit? */ - 8, /* DLC: Data length */ - data) == -1) - { - gpio_set(GPIOA, GPIO6); /* LED0 off */ - gpio_set(GPIOA, GPIO7); /* LED1 off */ - gpio_clear(GPIOB, GPIO0); /* LED2 on */ - gpio_set(GPIOB, GPIO1); /* LED3 off */ - } -} - -void usb_lp_can_rx0_isr(void) -{ - u32 id, fmi; - bool ext, rtr; - u8 length, data[8]; - - can_receive(CAN1, 0, false, &id, &ext, &rtr, &fmi, &length, data); - - if (data[0] & 1) - gpio_clear(GPIOA, GPIO6); - else - gpio_set(GPIOA, GPIO6); - - if (data[0] & 2) - gpio_clear(GPIOA, GPIO7); - else - gpio_set(GPIOA, GPIO7); - - if (data[0] & 4) - gpio_clear(GPIOB, GPIO0); - else - gpio_set(GPIOB, GPIO0); - - if (data[0] & 8) - gpio_clear(GPIOB, GPIO1); - else - gpio_set(GPIOB, GPIO1); - - can_fifo_release(CAN1, 0); -} - -int main(void) -{ - rcc_clock_setup_in_hse_8mhz_out_72mhz(); - gpio_setup(); - can_setup(); - systick_setup(); - - while (1); /* Halt. */ - - return 0; -} diff --git a/examples/stm32/obldc/can/can.ld b/examples/stm32/obldc/can/can.ld deleted file mode 100644 index c076521..0000000 --- a/examples/stm32/obldc/can/can.ld +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* Linker script for an STM32F103RBT6 board (128K flash, 20K RAM). */ - -/* Define memory regions. */ -MEMORY -{ - rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K -} - -/* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld - diff --git a/examples/stm32/obldc/led/Makefile b/examples/stm32/obldc/led/Makefile deleted file mode 100644 index 8e1618a..0000000 --- a/examples/stm32/obldc/led/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2009 Uwe Hermann -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program. If not, see . -## - -BINARY = led - -include ../../Makefile.include - diff --git a/examples/stm32/obldc/led/led.c b/examples/stm32/obldc/led/led.c deleted file mode 100644 index 09ae89d..0000000 --- a/examples/stm32/obldc/led/led.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * Copyright (C) 2010 Piotr Esden-Tempski - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include - -/* Set STM32 to 72 MHz. */ -void clock_setup(void) -{ - rcc_clock_setup_in_hse_8mhz_out_72mhz(); - - /* Enable GPIOA clock. */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); - - /* Enable GPIOB clock. */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPBEN); -} - -void gpio_setup(void) -{ - /* Set GPIO6 and 7 (in GPIO port A) to 'output push-pull'. */ - gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO6 | GPIO7); - - /* Set GPIO0 and 1 (in GPIO port B) to 'output push-pull'. */ - gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO0 | GPIO1); -} - -int main(void) -{ - int i; - - clock_setup(); - gpio_setup(); - - /* Blink the LEDs on the board. */ - while (1) { - gpio_toggle(GPIOA, GPIO6); /* LED on/off */ - for (i = 0; i < 8000000; i++) /* Wait a bit. */ - __asm__("nop"); - gpio_toggle(GPIOA, GPIO7); /* LED on/off */ - for (i = 0; i < 8000000; i++) /* Wait a bit. */ - __asm__("nop"); - gpio_toggle(GPIOB, GPIO0); /* LED on/off */ - for (i = 0; i < 8000000; i++) /* Wait a bit. */ - __asm__("nop"); - gpio_toggle(GPIOB, GPIO1); /* LED on/off */ - for (i = 0; i < 8000000; i++) /* Wait a bit. */ - __asm__("nop"); - } - - return 0; -} diff --git a/examples/stm32/obldc/led/led.ld b/examples/stm32/obldc/led/led.ld deleted file mode 100644 index 7899773..0000000 --- a/examples/stm32/obldc/led/led.ld +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* Linker script for Open-BLDC (STM32F103CBT6, 128K flash, 20K RAM). */ - -/* Define memory regions. */ -MEMORY -{ - rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K -} - -/* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld - diff --git a/examples/stm32/obldc/pwmleds/Makefile b/examples/stm32/obldc/pwmleds/Makefile deleted file mode 100644 index 8ae74d6..0000000 --- a/examples/stm32/obldc/pwmleds/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2009 Uwe Hermann -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program. If not, see . -## - -BINARY = pwmleds - -include ../../Makefile.include - diff --git a/examples/stm32/obldc/pwmleds/pwmleds.c b/examples/stm32/obldc/pwmleds/pwmleds.c deleted file mode 100644 index 146bb56..0000000 --- a/examples/stm32/obldc/pwmleds/pwmleds.c +++ /dev/null @@ -1,485 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include - -// #define COMPARE -// #define MOVING_FADE -#define KITT - -#ifdef COMPARE -#define GAMMA_LINEAR -#define GAMMA_1_3 -#define GAMMA_2_5 -#define GAMMA_3_0 -#endif - -#ifdef MOVING_FADE -#define GAMMA_2_2 -#define GAMMA_TABLE gamma_table_2_2 -#endif - -#ifdef KITT -#define GAMMA_2_5 -#define GAMMA_TABLE gamma_table_2_5 -#endif - -/* - * Gamma correction table - * - * The nonlinear tables are calculating with the function: - * Iout = Iin ** gamma - */ -#ifdef GAMMA_LINEAR -static const u16 gamma_table_linear[] = { - 1, 4, 9, 17, 26, 37, 51, 67, - 84, 104, 126, 149, 175, 203, 233, 265, - 299, 334, 372, 412, 454, 499, 545, 593, - 643, 695, 749, 805, 864, 924, 986, 1050, - 1116, 1185, 1255, 1327, 1402, 1478, 1556, 1637, - 1719, 1803, 1890, 1978, 2068, 2161, 2255, 2352, - 2450, 2550, 2653, 2757, 2864, 2972, 3082, 3195, - 3309, 3426, 3544, 3664, 3787, 3911, 4038, 4166, - 4296, 4429, 4563, 4700, 4838, 4978, 5121, 5265, - 5411, 5560, 5710, 5862, 6017, 6173, 6331, 6492, - 6654, 6818, 6985, 7153, 7323, 7495, 7670, 7846, - 8024, 8204, 8387, 8571, 8757, 8945, 9135, 9327, - 9521, 9718, 9916, 10116, 10318, 10522, 10728, 10936, - 11146, 11358, 11572, 11788, 12006, 12226, 12448, 12672, - 12897, 13125, 13355, 13587, 13821, 14057, 14294, 14534, - 14776, 15020, 15265, 15513, 15763, 16014, 16268, 16524, - 16781, 17041, 17302, 17566, 17831, 18099, 18368, 18640, - 18913, 19189, 19466, 19745, 20027, 20310, 20595, 20883, - 21172, 21463, 21756, 22051, 22349, 22648, 22949, 23252, - 23557, 23864, 24173, 24484, 24797, 25112, 25429, 25748, - 26069, 26391, 26716, 27043, 27372, 27702, 28035, 28370, - 28707, 29045, 29386, 29728, 30073, 30419, 30768, 31118, - 31471, 31825, 32182, 32540, 32900, 33263, 33627, 33993, - 34361, 34731, 35104, 35478, 35854, 36232, 36612, 36994, - 37378, 37764, 38152, 38542, 38933, 39327, 39723, 40121, - 40521, 40922, 41326, 41732, 42139, 42549, 42960, 43374, - 43789, 44207, 44626, 45048, 45471, 45896, 46324, 46753, - 47184, 47617, 48052, 48490, 48929, 49370, 49813, 50258, - 50705, 51154, 51604, 52057, 52512, 52969, 53428, 53888, - 54351, 54816, 55282, 55751, 56222, 56694, 57169, 57645, - 58123, 58604, 59086, 59570, 60057, 60545, 61035, 61527, - 62021, 62517, 63016, 63516, 64018, 64521, 65027, 65535, -}; -#endif - -#ifdef GAMMA_1_3 -static const u16 gamma_table_1_3[] = { - /* Gamma 1.3 */ - 0, 49, 120, 203, 296, 395, 501, 612, - 728, 848, 973, 1101, 1233, 1368, 1506, 1648, - 1792, 1939, 2088, 2241, 2395, 2552, 2711, 2872, - 3036, 3201, 3369, 3538, 3709, 3882, 4057, 4234, - 4412, 4592, 4774, 4957, 5142, 5329, 5517, 5706, - 5897, 6090, 6283, 6479, 6675, 6873, 7072, 7273, - 7475, 7678, 7882, 8088, 8294, 8502, 8711, 8922, - 9133, 9346, 9559, 9774, 9990, 10207, 10425, 10644, - 10864, 11086, 11308, 11531, 11755, 11981, 12207, 12434, - 12662, 12891, 13121, 13352, 13584, 13817, 14051, 14285, - 14521, 14757, 14994, 15233, 15472, 15712, 15952, 16194, - 16436, 16679, 16923, 17168, 17414, 17660, 17908, 18156, - 18405, 18654, 18905, 19156, 19408, 19660, 19914, 20168, - 20423, 20679, 20935, 21192, 21450, 21708, 21968, 22228, - 22488, 22750, 23012, 23275, 23538, 23802, 24067, 24332, - 24599, 24865, 25133, 25401, 25670, 25939, 26209, 26480, - 26751, 27023, 27296, 27569, 27843, 28118, 28393, 28669, - 28945, 29222, 29500, 29778, 30057, 30336, 30616, 30897, - 31178, 31460, 31742, 32025, 32308, 32592, 32877, 33162, - 33448, 33734, 34021, 34309, 34597, 34885, 35175, 35464, - 35754, 36045, 36337, 36628, 36921, 37214, 37507, 37801, - 38096, 38391, 38686, 38982, 39279, 39576, 39874, 40172, - 40471, 40770, 41070, 41370, 41670, 41972, 42273, 42576, - 42878, 43181, 43485, 43789, 44094, 44399, 44705, 45011, - 45317, 45625, 45932, 46240, 46549, 46858, 47167, 47477, - 47787, 48098, 48409, 48721, 49034, 49346, 49659, 49973, - 50287, 50602, 50917, 51232, 51548, 51864, 52181, 52498, - 52816, 53134, 53452, 53771, 54091, 54411, 54731, 55052, - 55373, 55694, 56016, 56339, 56662, 56985, 57309, 57633, - 57957, 58282, 58608, 58933, 59260, 59586, 59913, 60241, - 60569, 60897, 61226, 61555, 61884, 62214, 62545, 62875, - 63206, 63538, 63870, 64202, 64535, 64868, 65201, 65535, -}; -#endif - -#ifdef GAMMA_2_2 -static const u16 gamma_table_2_2[] = { - 0, 0, 2, 4, 7, 11, 17, 24, - 32, 42, 53, 65, 79, 94, 111, 129, - 148, 169, 192, 216, 242, 270, 299, 330, - 362, 396, 432, 469, 508, 549, 591, 635, - 681, 729, 779, 830, 883, 938, 995, 1053, - 1113, 1175, 1239, 1305, 1373, 1443, 1514, 1587, - 1663, 1740, 1819, 1900, 1983, 2068, 2155, 2243, - 2334, 2427, 2521, 2618, 2717, 2817, 2920, 3024, - 3131, 3240, 3350, 3463, 3578, 3694, 3813, 3934, - 4057, 4182, 4309, 4438, 4570, 4703, 4838, 4976, - 5115, 5257, 5401, 5547, 5695, 5845, 5998, 6152, - 6309, 6468, 6629, 6792, 6957, 7124, 7294, 7466, - 7640, 7816, 7994, 8175, 8358, 8543, 8730, 8919, - 9111, 9305, 9501, 9699, 9900, 10102, 10307, 10515, - 10724, 10936, 11150, 11366, 11585, 11806, 12029, 12254, - 12482, 12712, 12944, 13179, 13416, 13655, 13896, 14140, - 14386, 14635, 14885, 15138, 15394, 15652, 15912, 16174, - 16439, 16706, 16975, 17247, 17521, 17798, 18077, 18358, - 18642, 18928, 19216, 19507, 19800, 20095, 20393, 20694, - 20996, 21301, 21609, 21919, 22231, 22546, 22863, 23182, - 23504, 23829, 24156, 24485, 24817, 25151, 25487, 25826, - 26168, 26512, 26858, 27207, 27558, 27912, 28268, 28627, - 28988, 29351, 29717, 30086, 30457, 30830, 31206, 31585, - 31966, 32349, 32735, 33124, 33514, 33908, 34304, 34702, - 35103, 35507, 35913, 36321, 36732, 37146, 37562, 37981, - 38402, 38825, 39252, 39680, 40112, 40546, 40982, 41421, - 41862, 42306, 42753, 43202, 43654, 44108, 44565, 45025, - 45487, 45951, 46418, 46888, 47360, 47835, 48313, 48793, - 49275, 49761, 50249, 50739, 51232, 51728, 52226, 52727, - 53230, 53736, 54245, 54756, 55270, 55787, 56306, 56828, - 57352, 57879, 58409, 58941, 59476, 60014, 60554, 61097, - 61642, 62190, 62741, 63295, 63851, 64410, 64971, 65535 -}; -#endif - -#ifdef GAMMA_2_5 -static const u16 gamma_table_2_5[] = { - /* gamma = 2.5 */ - 0, 0, 0, 1, 2, 4, 6, 8, - 11, 15, 20, 25, 31, 38, 46, 55, - 65, 75, 87, 99, 113, 128, 143, 160, - 178, 197, 218, 239, 262, 286, 311, 338, - 366, 395, 425, 457, 491, 526, 562, 599, - 639, 679, 722, 765, 811, 857, 906, 956, - 1007, 1061, 1116, 1172, 1231, 1291, 1352, 1416, - 1481, 1548, 1617, 1688, 1760, 1834, 1910, 1988, - 2068, 2150, 2233, 2319, 2407, 2496, 2587, 2681, - 2776, 2874, 2973, 3075, 3178, 3284, 3391, 3501, - 3613, 3727, 3843, 3961, 4082, 4204, 4329, 4456, - 4585, 4716, 4850, 4986, 5124, 5264, 5407, 5552, - 5699, 5849, 6001, 6155, 6311, 6470, 6632, 6795, - 6962, 7130, 7301, 7475, 7650, 7829, 8009, 8193, - 8379, 8567, 8758, 8951, 9147, 9345, 9546, 9750, - 9956, 10165, 10376, 10590, 10806, 11025, 11247, 11472, - 11699, 11929, 12161, 12397, 12634, 12875, 13119, 13365, - 13614, 13865, 14120, 14377, 14637, 14899, 15165, 15433, - 15705, 15979, 16256, 16535, 16818, 17104, 17392, 17683, - 17978, 18275, 18575, 18878, 19184, 19493, 19805, 20119, - 20437, 20758, 21082, 21409, 21739, 22072, 22407, 22746, - 23089, 23434, 23782, 24133, 24487, 24845, 25206, 25569, - 25936, 26306, 26679, 27055, 27435, 27818, 28203, 28592, - 28985, 29380, 29779, 30181, 30586, 30994, 31406, 31820, - 32239, 32660, 33085, 33513, 33944, 34379, 34817, 35258, - 35702, 36150, 36602, 37056, 37514, 37976, 38441, 38909, - 39380, 39856, 40334, 40816, 41301, 41790, 42282, 42778, - 43277, 43780, 44286, 44795, 45308, 45825, 46345, 46869, - 47396, 47927, 48461, 48999, 49540, 50085, 50634, 51186, - 51742, 52301, 52864, 53431, 54001, 54575, 55153, 55734, - 56318, 56907, 57499, 58095, 58695, 59298, 59905, 60515, - 61130, 61748, 62370, 62995, 63624, 64258, 64894, 65535, -}; -#endif - -#ifdef GAMMA_3_0 -static const u16 gamma_table_3_0[] = { - /* gamma = 3.0 */ - 0, 0, 0, 0, 0, 0, 1, 1, - 2, 3, 4, 5, 7, 9, 11, 13, - 16, 19, 23, 27, 32, 37, 42, 48, - 55, 62, 69, 78, 87, 96, 107, 118, - 130, 142, 155, 169, 184, 200, 217, 234, - 253, 272, 293, 314, 337, 360, 385, 410, - 437, 465, 494, 524, 556, 588, 622, 658, - 694, 732, 771, 812, 854, 897, 942, 988, - 1036, 1085, 1136, 1189, 1243, 1298, 1356, 1415, - 1475, 1538, 1602, 1667, 1735, 1804, 1876, 1949, - 2024, 2100, 2179, 2260, 2343, 2427, 2514, 2603, - 2693, 2786, 2881, 2978, 3078, 3179, 3283, 3389, - 3497, 3607, 3720, 3835, 3952, 4072, 4194, 4319, - 4446, 4575, 4707, 4842, 4979, 5118, 5261, 5405, - 5553, 5703, 5856, 6011, 6169, 6330, 6494, 6660, - 6830, 7002, 7177, 7355, 7536, 7719, 7906, 8096, - 8289, 8484, 8683, 8885, 9090, 9298, 9510, 9724, - 9942, 10163, 10387, 10614, 10845, 11079, 11317, 11557, - 11802, 12049, 12300, 12555, 12813, 13074, 13339, 13608, - 13880, 14156, 14435, 14718, 15005, 15295, 15589, 15887, - 16189, 16494, 16803, 17117, 17433, 17754, 18079, 18408, - 18740, 19077, 19418, 19762, 20111, 20464, 20821, 21182, - 21547, 21917, 22290, 22668, 23050, 23436, 23827, 24222, - 24621, 25025, 25433, 25845, 26262, 26683, 27109, 27539, - 27974, 28413, 28857, 29306, 29759, 30217, 30680, 31147, - 31619, 32095, 32577, 33063, 33554, 34050, 34551, 35056, - 35567, 36082, 36602, 37128, 37658, 38194, 38734, 39280, - 39830, 40386, 40947, 41513, 42084, 42661, 43243, 43830, - 44422, 45019, 45622, 46231, 46844, 47463, 48088, 48718, - 49353, 49994, 50641, 51293, 51950, 52614, 53282, 53957, - 54637, 55323, 56014, 56712, 57415, 58123, 58838, 59558, - 60285, 61017, 61755, 62499, 63249, 64005, 64767, 65535, -}; -#endif - -void clock_setup(void) -{ - rcc_clock_setup_in_hse_8mhz_out_72mhz(); - - /* Enable TIM3 clock. */ - rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_TIM3EN); - - /* Enable GPIOC, Alternate Function clocks. */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, - RCC_APB2ENR_IOPAEN | - RCC_APB2ENR_IOPBEN | - RCC_APB2ENR_AFIOEN); -} - -void gpio_setup(void) -{ - /* - * Set GPIO6 and 7 (in GPIO port A) to - * 'output alternate function push-pull'. - */ - gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, - GPIO_TIM3_CH1 | - GPIO_TIM3_CH2); - - /* - * Set GPIO0 and 1 (in GPIO port B) to - * 'output alternate function push-pull'. - */ - gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, - GPIO_TIM3_CH3 | - GPIO_TIM3_CH4); - -} -void tim_setup(void) -{ - /* Clock division and mode */ - TIM3_CR1 = TIM_CR1_CKD_CK_INT | TIM_CR1_CMS_EDGE; - /* Period */ - TIM3_ARR = 65535; - /* Prescaler */ - TIM3_PSC = 0; - TIM3_EGR = TIM_EGR_UG; - - /* ---- */ - /* Output compare 1 mode and preload */ - TIM3_CCMR1 |= TIM_CCMR1_OC1M_PWM1 | TIM_CCMR1_OC1PE; - - /* Polarity and state */ - TIM3_CCER |= TIM_CCER_CC1P | TIM_CCER_CC1E; - //TIM3_CCER |= TIM_CCER_CC1E; - - /* Capture compare value */ - TIM3_CCR1 = 0; - - /* ---- */ - /* Output compare 2 mode and preload */ - TIM3_CCMR1 |= TIM_CCMR1_OC2M_PWM1 | TIM_CCMR1_OC2PE; - - /* Polarity and state */ - TIM3_CCER |= TIM_CCER_CC2P | TIM_CCER_CC2E; - //TIM3_CCER |= TIM_CCER_CC2E; - - /* Capture compare value */ - TIM3_CCR2 = 0; - - /* ---- */ - /* Output compare 3 mode and preload */ - TIM3_CCMR2 |= TIM_CCMR2_OC3M_PWM1 | TIM_CCMR2_OC3PE; - - /* Polarity and state */ - TIM3_CCER |= TIM_CCER_CC3P | TIM_CCER_CC3E; - //TIM3_CCER |= TIM_CCER_CC3E; - - /* Capture compare value */ - TIM3_CCR3 = 0; - - /* ---- */ - /* Output compare 4 mode and preload */ - TIM3_CCMR2 |= TIM_CCMR2_OC4M_PWM1 | TIM_CCMR2_OC4PE; - - /* Polarity and state */ - TIM3_CCER |= TIM_CCER_CC4P | TIM_CCER_CC4E; - //TIM3_CCER |= TIM_CCER_CC4E; - - /* Capture compare value */ - TIM3_CCR4 = 0; - - /* ---- */ - /* ARR reload enable */ - TIM3_CR1 |= TIM_CR1_ARPE; - - /* Counter enable */ - TIM3_CR1 |= TIM_CR1_CEN; -} - -int main(void) -{ - int i, j0, j1, j2, j3, d0, d1, d2, d3, j, k, kd; - - clock_setup(); - gpio_setup(); - tim_setup(); - -#ifdef COMPARE - j0 = 0; - d0 = 1; - j1 = 0; - d1 = 1; - j2 = 0; - d2 = 1; - j3 = 0; - d3 = 1; - while (1) { - TIM3_CCR1 = gamma_table_linear[j0]; - j0 += d0; - if (j0 == 255) - d0 =- 1; - if (j0 == 0) - d0 = 1; - TIM3_CCR2 = gamma_table_1_3[j1]; - j1 += d1; - if (j1 == 255) - d1 =- 1; - if (j1 == 0) - d1 = 1; - TIM3_CCR3 = gamma_table_2_5[j2]; - j2 += d2; - if (j2 == 255) - d2 =- 1; - if (j2 == 0) - d2 = 1; - TIM3_CCR4= gamma_table_3_0[j3]; - j3 += d3; - if (j3 == 255) - d3 =- 1; - if (j3 == 0) - d3 = 1; - for (i = 0; i < 50000; i++); - } -#endif - -#ifdef MOVING_FADE - j0 = 0; - d0 = 1; - j1 = 128; - d1 = 1; - j2 = 255; - d2 = -1; - j3 = 128; - d3 = -1; - while (1) { - TIM3_CCR1 = GAMMA_TABLE[j0]; - j0 += d0; - if (j0 == 255) - d0 =- 1; - if (j0 == 0) - d0 = 1; - TIM3_CCR2 = GAMMA_TABLE[j1]; - j1 += d1; - if (j1 == 255) - d1 =- 1; - if (j1 == 0) - d1 = 1; - TIM3_CCR3 = GAMMA_TABLE[j2]; - j2 += d2; - if (j2 == 255) - d2 =- 1; - if (j2 == 0) - d2 = 1; - TIM3_CCR4 = GAMMA_TABLE[j3]; - j3 += d3; - if (j3 == 255) - d3 =- 1; - if (j3 == 0) - d3 = 1; - for (i = 0; i < 10000; i++); - } -#endif - -#ifdef KITT - j0 = 255; - d0 = -1; - j1 = 20; - d1 = -1; - j2 = 20; - d2 = -1; - j3 = 20; - d3 = -1; - j = 0; - k = 0; - kd = 1; - while (1) { - TIM3_CCR1 = GAMMA_TABLE[j0]; - j0 += d0; - if (j0 == 255) - d0 =- 1; - if (j0 == 19) - j0 = 20; - TIM3_CCR2 = GAMMA_TABLE[j1]; - j1 += d1; - if (j1 == 255) - d1 =- 1; - if (j1 == 19) - j1 = 20; - TIM3_CCR3 = GAMMA_TABLE[j2]; - j2 += d2; - if (j2 == 255) - d2 =- 1; - if (j2 == 19) - j2 = 20; - TIM3_CCR4 = GAMMA_TABLE[j3]; - j3 += d3; - if (j3 == 255) - d3 =- 1; - if (j3 == 19) - j3 = 20; - for (i = 0; i < 15000; i++) - __asm__("nop"); - j++; - if (j == 100) { - j = 0; - switch (k += kd) { - case 0: - j0 = 255; - break; - case 1: - j1 = 255; - break; - case 2: - j2 = 255; - break; - case 3: - j3 = 255; - break; - } - if (k == 3) - kd =- 1; - if (k == 0) - kd = 1; - } - } -#endif - - return 0; -} diff --git a/examples/stm32/obldc/pwmleds/pwmleds.ld b/examples/stm32/obldc/pwmleds/pwmleds.ld deleted file mode 100644 index 7ea2b92..0000000 --- a/examples/stm32/obldc/pwmleds/pwmleds.ld +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* Linker script for Olimex STM32-H103 (STM32F103RBT6, 128K flash, 20K RAM). */ - -/* Define memory regions. */ -MEMORY -{ - rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K -} - -/* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld - diff --git a/examples/stm32/obldc/systick/Makefile b/examples/stm32/obldc/systick/Makefile deleted file mode 100644 index 91b5cb5..0000000 --- a/examples/stm32/obldc/systick/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2009 Uwe Hermann -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program. If not, see . -## - -BINARY = systick - -include ../../Makefile.include - diff --git a/examples/stm32/obldc/systick/systick.c b/examples/stm32/obldc/systick/systick.c deleted file mode 100644 index 3d75c4a..0000000 --- a/examples/stm32/obldc/systick/systick.c +++ /dev/null @@ -1,90 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * Copyright (C) 2010 Piotr Esden-Tempski - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include -#include -#include - -u32 temp32; - -void gpio_setup(void) -{ - /* Enable GPIOA clock. */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); - - /* Enable GPIOB clock. */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPBEN); - - gpio_set(GPIOA, GPIO6); /* LED0 off */ - gpio_set(GPIOA, GPIO7); /* LED1 off */ - gpio_set(GPIOB, GPIO0); /* LED2 off */ - gpio_set(GPIOB, GPIO1); /* LED3 off */ - - /* Set GPIO6/7 (in GPIO port A) to 'output push-pull' for the LEDs. */ - gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO6); - gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO7); - - /* Set GPIO6/7 (in GPIO port B) to 'output push-pull' for the LEDs. */ - gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO0); - gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO1); -} - -void sys_tick_handler(void) -{ - temp32++; - - /* We call this handler every 1ms so 1000ms = 1s on/off. */ - if (temp32 == 1000) { - gpio_toggle(GPIOA, GPIO6); /* LED2 on/off */ - temp32 = 0; - } -} - -int main(void) -{ - rcc_clock_setup_in_hse_8mhz_out_72mhz(); - gpio_setup(); - - gpio_clear(GPIOA, GPIO7); /* LED1 on */ - gpio_set(GPIOA, GPIO6); /* LED2 off */ - - temp32 = 0; - - /* 72MHz / 8 => 9000000 counts per second */ - systick_set_clocksource(STK_CTRL_CLKSOURCE_AHB_DIV8); - - /* 9000000/9000 = 1000 overflows per second - every 1ms one interrupt */ - systick_set_reload(9000); - - systick_interrupt_enable(); - - /* Start counting. */ - systick_counter_enable(); - - while (1); /* Halt. */ - - return 0; -} diff --git a/examples/stm32/obldc/systick/systick.ld b/examples/stm32/obldc/systick/systick.ld deleted file mode 100644 index da4f2b3..0000000 --- a/examples/stm32/obldc/systick/systick.ld +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* Linker script for an STM32F103CBT6 board (128K flash, 20K RAM). */ - -/* Define memory regions. */ -MEMORY -{ - rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K -} - -/* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld - diff --git a/examples/stm32/obldc/usart/Makefile b/examples/stm32/obldc/usart/Makefile deleted file mode 100644 index 2c1e1b1..0000000 --- a/examples/stm32/obldc/usart/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2009 Uwe Hermann -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program. If not, see . -## - -BINARY = usart - -include ../../Makefile.include - diff --git a/examples/stm32/obldc/usart/usart.c b/examples/stm32/obldc/usart/usart.c deleted file mode 100644 index ea5ec0e..0000000 --- a/examples/stm32/obldc/usart/usart.c +++ /dev/null @@ -1,90 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include - -void clock_setup(void) -{ - rcc_clock_setup_in_hse_8mhz_out_72mhz(); - - /* Enable GPIOA clock (for LED GPIOs). */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); - - /* Enable clocks for GPIO port B (for GPIO_USART1_TX) and USART1. */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPBEN); - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_AFIOEN); - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_USART1EN); -} - -void usart_setup(void) -{ - /* Setup GPIO6 (in GPIO port A) to 'output push-pull' for LED use. */ - gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO6); - - AFIO_MAPR |= AFIO_MAPR_USART1_REMAP; - - /* Setup GPIO pin GPIO_USART3_TX/GPIO10 on GPIO port B for transmit. */ - gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_USART1_RE_TX); - - /* Setup UART parameters. */ - usart_set_baudrate(USART1, 230400); - usart_set_databits(USART1, 8); - usart_set_stopbits(USART1, USART_STOPBITS_1); - usart_set_mode(USART1, USART_MODE_TX); - usart_set_parity(USART1, USART_PARITY_NONE); - usart_set_flow_control(USART1, USART_FLOWCONTROL_NONE); - - /* Finally enable the USART. */ - usart_enable(USART1); -} - -void gpio_setup(void) -{ - /* Set GPIO12 (in GPIO port C) to 'output push-pull'. */ - gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO6); -} - -int main(void) -{ - int i, j = 0, c = 0; - - clock_setup(); - gpio_setup(); - usart_setup(); - - /* Blink the LED (PC12) on the board with every transmitted byte. */ - while (1) { - gpio_toggle(GPIOA, GPIO6); /* LED on/off */ - usart_send_blocking(USART1, c + '0'); /* Send a byte. */ - c = (c == 9) ? 0 : c + 1; /* Increment c. */ - if ((j++ % 80) == 0) { /* Newline after line full. */ - usart_send_blocking(USART1, '\r'); - usart_send_blocking(USART1, '\n'); - } - for (i = 0; i < 800000; i++) /* Wait a bit. */ - __asm__("nop"); - } - - return 0; -} diff --git a/examples/stm32/obldc/usart/usart.ld b/examples/stm32/obldc/usart/usart.ld deleted file mode 100644 index 7899773..0000000 --- a/examples/stm32/obldc/usart/usart.ld +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* Linker script for Open-BLDC (STM32F103CBT6, 128K flash, 20K RAM). */ - -/* Define memory regions. */ -MEMORY -{ - rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K -} - -/* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld - diff --git a/examples/stm32/obldc/usart_irq/Makefile b/examples/stm32/obldc/usart_irq/Makefile deleted file mode 100644 index 2ab46a0..0000000 --- a/examples/stm32/obldc/usart_irq/Makefile +++ /dev/null @@ -1,25 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2009 Uwe Hermann -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program. If not, see . -## - -BINARY = usart_irq - -OOCD_BOARD = open-bldc - -include ../../Makefile.include - diff --git a/examples/stm32/obldc/usart_irq/usart_irq.c b/examples/stm32/obldc/usart_irq/usart_irq.c deleted file mode 100644 index 82320c1..0000000 --- a/examples/stm32/obldc/usart_irq/usart_irq.c +++ /dev/null @@ -1,120 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include -#include - -void clock_setup(void) -{ - rcc_clock_setup_in_hse_8mhz_out_72mhz(); - - /* Enable GPIOA clock (for LED GPIOs). */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); - - /* Enable clocks for GPIO port B (for GPIO_USART1_TX) and USART1. */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPBEN); - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_AFIOEN); - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_USART1EN); -} - -void usart_setup(void) -{ - /* Enable the USART1 interrupt. */ - nvic_enable_irq(NVIC_USART1_IRQ); - - /* enable USART1 pin software remapping */ - AFIO_MAPR |= AFIO_MAPR_USART1_REMAP; - - /* Setup GPIO pin GPIO_USART1_RE_TX on GPIO port B for transmit. */ - gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_USART1_RE_TX); - - /* Setup GPIO pin GPIO_USART1_RE_RX on GPIO port B for receive. */ - gpio_set_mode(GPIOB, GPIO_MODE_INPUT, - GPIO_CNF_INPUT_FLOAT, GPIO_USART1_RE_RX); - - /* Setup UART parameters. */ - usart_set_baudrate(USART1, 230400); - usart_set_databits(USART1, 8); - usart_set_stopbits(USART1, USART_STOPBITS_1); - usart_set_parity(USART1, USART_PARITY_NONE); - usart_set_flow_control(USART1, USART_FLOWCONTROL_NONE); - usart_set_mode(USART1, USART_MODE_TX_RX); - - /* Enable USART1 Receive interrupt. */ - USART_CR1(USART1) |= USART_CR1_RXNEIE; - - /* Finally enable the USART. */ - usart_enable(USART1); -} - -void gpio_setup(void) -{ - gpio_set(GPIOA, GPIO6 | GPIO7); - - /* Setup GPIO6 and 7 (in GPIO port A) for led use. */ - gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO6 | GPIO7); -} - -void usart1_isr(void) -{ - static u8 data = 'A'; - - /* Check if we were called because of RXNE. */ - if (((USART_CR1(USART1) & USART_CR1_RXNEIE) != 0) && - ((USART_SR(USART1) & USART_SR_RXNE) != 0)) { - /* Indicate that we got data. */ - gpio_toggle(GPIOA, GPIO6); - - /* Retrieve the data from the peripheral. */ - data = usart_recv(USART1); - - /* Enable transmit interrupt so it sends back the data. */ - USART_CR1(USART1) |= USART_CR1_TXEIE; - } - - /* Check if we were called because of TXE. */ - if (((USART_CR1(USART1) & USART_CR1_TXEIE) != 0) && - ((USART_SR(USART1) & USART_SR_TXE) != 0)) { - /* Indicate that we are sending out data. */ - gpio_toggle(GPIOA, GPIO7); - - /* Put data into the transmit register. */ - usart_send(USART1, data); - - /* Disable the TXE interrupt as we don't need it anymore. */ - USART_CR1(USART1) &= ~USART_CR1_TXEIE; - } -} - -int main(void) -{ - clock_setup(); - gpio_setup(); - usart_setup(); - - /* Wait forever and do nothing. */ - while (1) - __asm__("nop"); - - return 0; -} diff --git a/examples/stm32/obldc/usart_irq/usart_irq.ld b/examples/stm32/obldc/usart_irq/usart_irq.ld deleted file mode 100644 index 7899773..0000000 --- a/examples/stm32/obldc/usart_irq/usart_irq.ld +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* Linker script for Open-BLDC (STM32F103CBT6, 128K flash, 20K RAM). */ - -/* Define memory regions. */ -MEMORY -{ - rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K -} - -/* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld - diff --git a/examples/stm32/other/adc_temperature_sensor/Makefile b/examples/stm32/other/adc_temperature_sensor/Makefile deleted file mode 100644 index f3f65c4..0000000 --- a/examples/stm32/other/adc_temperature_sensor/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2009 Uwe Hermann -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program. If not, see . -## - -BINARY = adc - -include ../../Makefile.include - diff --git a/examples/stm32/other/adc_temperature_sensor/README b/examples/stm32/other/adc_temperature_sensor/README deleted file mode 100644 index aa00ef0..0000000 --- a/examples/stm32/other/adc_temperature_sensor/README +++ /dev/null @@ -1,10 +0,0 @@ ------------------------------------------------------------------------------- -README ------------------------------------------------------------------------------- - -This example program sends some characters on USART1. -Afterwards it read out the internal temperature sensor of the STM32 and -sends the value read out from the ADC to the USART1. - -The terminal settings for the receiving device/PC are 115200 8n1. - diff --git a/examples/stm32/other/adc_temperature_sensor/adc.c b/examples/stm32/other/adc_temperature_sensor/adc.c deleted file mode 100644 index 6c0e828..0000000 --- a/examples/stm32/other/adc_temperature_sensor/adc.c +++ /dev/null @@ -1,155 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include -#include -#include - -void usart_setup(void) -{ - /* Enable clocks for GPIO port A (for GPIO_USART1_TX) and USART1. */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_USART1EN); - - /* Setup GPIO pin GPIO_USART1_TX/GPIO9 on GPIO port A for transmit. */ - gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_USART1_TX); - - /* Setup UART parameters. */ - usart_set_baudrate(USART1, 115200); - usart_set_databits(USART1, 8); - usart_set_stopbits(USART1, USART_STOPBITS_1); - usart_set_mode(USART1, USART_MODE_TX_RX); - usart_set_parity(USART1, USART_PARITY_NONE); - usart_set_flow_control(USART1, USART_FLOWCONTROL_NONE); - - /* Finally enable the USART. */ - usart_enable(USART1); -} - -void gpio_setup(void) -{ - /* Enable GPIOB clock. */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPBEN); - - /* Set GPIO6/7 (in GPIO port B) to 'output push-pull' for the LEDs. */ - gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_2_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO6); - gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_2_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO7); -} - -void adc_setup(void) -{ - int i; - - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_ADC1EN); - - /* Make shure it doesn't run during config. */ - adc_off(ADC1); - - /* We configure everything for one single conversion. */ - adc_disable_scan_mode(ADC1); - adc_set_single_conversion_mode(ADC1); - adc_enable_discontinous_mode_regular(ADC1); - adc_disable_external_trigger_regular(ADC1); - adc_set_right_aligned(ADC1); - /* We want to read the temperature sensor, so we have to enable it. */ - adc_enable_temperature_sensor(ADC1); - adc_set_conversion_time_on_all_channels(ADC1, ADC_SMPR_SMP_28DOT5CYC); - - adc_on(ADC1); - - /* Wait for ADC starting up. */ - for (i = 0; i < 800000; i++) /* Wait a bit. */ - __asm__("nop"); - - adc_reset_calibration(ADC1); - adc_calibration(ADC1); -} - -void my_usart_print_int(u32 usart, int value) -{ - s8 i; - u8 nr_digits = 0; - char buffer[25]; - - if (value < 0) { - usart_send(usart, '-'); - value = value * -1; - } - - while (value > 0) { - buffer[nr_digits++] = "0123456789"[value % 10]; - value /= 10; - } - - for (i = nr_digits; i >= 0; i--) - usart_send(usart, buffer[i]); -} - -int main(void) -{ - u8 channel_array[16]; - u16 temperature; - - rcc_clock_setup_in_hse_16mhz_out_72mhz(); - gpio_setup(); - usart_setup(); - adc_setup(); - - gpio_clear(GPIOB, GPIO7); /* LED1 on */ - gpio_set(GPIOB, GPIO6); /* LED2 off */ - - /* Send a message on USART1. */ - usart_send(USART1, 's'); - usart_send(USART1, 't'); - usart_send(USART1, 'm'); - usart_send(USART1, '\r'); - usart_send(USART1, '\n'); - - /* Select the channel we want to convert. 16=temperature_sensor. */ - channel_array[0] = 16; - adc_set_regular_sequence(ADC1, 1, channel_array); - - /* - * If the ADC_CR2_ON bit is already set -> setting it another time - * starts the conversion. - */ - adc_on(ADC1); - - /* Wait for end of conversion. */ - while (!(ADC_SR(ADC1) & ADC_SR_EOC)); - - temperature = ADC_DR(ADC1); - - /* - * That's actually not the real temperature - you have to compute it - * as described in the datasheet. - */ - my_usart_print_int(USART1, temperature); - - gpio_clear(GPIOB, GPIO6); /* LED2 on */ - - while(1); /* Halt. */ - - return 0; -} diff --git a/examples/stm32/other/adc_temperature_sensor/adc.ld b/examples/stm32/other/adc_temperature_sensor/adc.ld deleted file mode 100644 index c076521..0000000 --- a/examples/stm32/other/adc_temperature_sensor/adc.ld +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* Linker script for an STM32F103RBT6 board (128K flash, 20K RAM). */ - -/* Define memory regions. */ -MEMORY -{ - rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K -} - -/* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld - diff --git a/examples/stm32/other/dma_mem2mem/Makefile b/examples/stm32/other/dma_mem2mem/Makefile deleted file mode 100644 index c43650d..0000000 --- a/examples/stm32/other/dma_mem2mem/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2009 Uwe Hermann -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program. If not, see . -## - -BINARY = dma - -include ../../Makefile.include - diff --git a/examples/stm32/other/dma_mem2mem/README b/examples/stm32/other/dma_mem2mem/README deleted file mode 100644 index 2e61e5a..0000000 --- a/examples/stm32/other/dma_mem2mem/README +++ /dev/null @@ -1,11 +0,0 @@ ------------------------------------------------------------------------------- -README ------------------------------------------------------------------------------- - -This program demonstrates a little DMA MEM2MEM transfer. A string is send out -to USART1 and afterwards copied by DMA to another memory location. To check -if the transfer was successful we send the destination string also out to -USART1. - -The terminal settings for the receiving device/PC are 115200 8n1. - diff --git a/examples/stm32/other/dma_mem2mem/dma.c b/examples/stm32/other/dma_mem2mem/dma.c deleted file mode 100644 index e43fe0d..0000000 --- a/examples/stm32/other/dma_mem2mem/dma.c +++ /dev/null @@ -1,133 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include -#include -#include - -void usart_setup(void) -{ - /* Enable clocks for GPIO port A (for GPIO_USART1_TX) and USART1. */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_USART1EN); - - /* Setup GPIO pin GPIO_USART1_TX/GPIO9 on GPIO port A for transmit. */ - gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_USART1_TX); - - /* Setup UART parameters. */ - usart_set_baudrate(USART1, 115200); - usart_set_databits(USART1, 8); - usart_set_stopbits(USART1, USART_STOPBITS_1); - usart_set_mode(USART1, USART_MODE_TX_RX); - usart_set_parity(USART1, USART_PARITY_NONE); - usart_set_flow_control(USART1, USART_FLOWCONTROL_NONE); - - /* Finally enable the USART. */ - usart_enable(USART1); -} - -void gpio_setup(void) -{ - /* Enable GPIOB clock. */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPBEN); - - /* Set GPIO6/7 (in GPIO port B) to 'output push-pull' for the LEDs. */ - gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_2_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO6); - gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_2_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO7); -} - -void my_usart_print_string(u32 usart, char * s) -{ - while (*s != 0) { - usart_send(usart, *s); - s++; - } -} - -int main(void) -{ - /* Exactly 20 bytes including '0' at the end. - We want to transfer 32bit * 5 so it should fit */ - char s1[20] = "Hello STM MEM2MEM\r\n"; - char s2[20]; - - rcc_clock_setup_in_hse_16mhz_out_72mhz(); - gpio_setup(); - usart_setup(); - - gpio_clear(GPIOB, GPIO7); /* LED1 on */ - gpio_set(GPIOB, GPIO6); /* LED2 off */ - - my_usart_print_string(USART1, "s1 "); - my_usart_print_string(USART1, s1); - - rcc_peripheral_enable_clock(&RCC_AHBENR, RCC_AHBENR_DMA1EN); - - /* MEM2MEM mode for channel 1. */ - dma_enable_mem2mem_mode(DMA1, DMA_CHANNEL1); - - /* Highest priority. */ - dma_set_priority(DMA1, DMA_CHANNEL1, DMA_CCR1_PL_VERY_HIGH); - - /* 32Bit wide transfer for source and destination. */ - dma_set_memory_size(DMA1, DMA_CHANNEL1, DMA_CCR1_MSIZE_32BIT); - dma_set_peripheral_size(DMA1, DMA_CHANNEL1, DMA_CCR1_PSIZE_32BIT); - - /* After each 32Bit we have to increase the addres because we use RAM. */ - dma_enable_memory_increment_mode(DMA1, DMA_CHANNEL1); - dma_enable_peripheral_increment_mode(DMA1, DMA_CHANNEL1); - - /* We define the source as peripheral. */ - dma_set_read_from_peripheral(DMA1, DMA_CHANNEL1); - - /* We want to transfer string s1. */ - dma_set_peripheral_address(DMA1, DMA_CHANNEL1, (u32) &s1); - - /* Destination should be string s2. */ - dma_set_memory_address(DMA1, DMA_CHANNEL1, (u32) &s2); - - /* Set number of DATA to transfer. - Remember that this means not necessary bytes but MSIZE or PSIZE - depending from your source device. */ - dma_set_number_of_data(DMA1, DMA_CHANNEL1, 5); - - /* Start DMA transfer. */ - dma_enable_channel(DMA1, DMA_CHANNEL1); - - /* TODO: write a function to get the interrupt flags. */ - while(!(DMA_ISR(DMA1) & 0x0000001)) - { - } - - dma_disable_channel(DMA1, DMA_CHANNEL1); - - /* String s1 should now already be transferred to s2. */ - my_usart_print_string(USART1, "s2 "); - my_usart_print_string(USART1, s2); - - gpio_clear(GPIOB, GPIO6); /* LED2 on */ - while(1); /* Halt. */ - - return 0; -} diff --git a/examples/stm32/other/dma_mem2mem/dma.ld b/examples/stm32/other/dma_mem2mem/dma.ld deleted file mode 100644 index c076521..0000000 --- a/examples/stm32/other/dma_mem2mem/dma.ld +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* Linker script for an STM32F103RBT6 board (128K flash, 20K RAM). */ - -/* Define memory regions. */ -MEMORY -{ - rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K -} - -/* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld - diff --git a/examples/stm32/other/dogm128/Makefile b/examples/stm32/other/dogm128/Makefile deleted file mode 100644 index 97a012e..0000000 --- a/examples/stm32/other/dogm128/Makefile +++ /dev/null @@ -1,25 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2009 Uwe Hermann -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program. If not, see . -## - -BINARY = main - -OBJS = dogm128.o - -include ../../Makefile.include - diff --git a/examples/stm32/other/dogm128/README b/examples/stm32/other/dogm128/README deleted file mode 100644 index dbf82a0..0000000 --- a/examples/stm32/other/dogm128/README +++ /dev/null @@ -1,7 +0,0 @@ ------------------------------------------------------------------------------- -README ------------------------------------------------------------------------------- - -This example program writes some text on an DOGM128 LCD display connected -to SPI2. - diff --git a/examples/stm32/other/dogm128/dogm128.c b/examples/stm32/other/dogm128/dogm128.c deleted file mode 100644 index c78a275..0000000 --- a/examples/stm32/other/dogm128/dogm128.c +++ /dev/null @@ -1,291 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include "./dogm128.h" - -u8 dogm128_ram[1024]; -u8 dogm128_cursor_x; -u8 dogm128_cursor_y; - -void dogm128_send_command(u8 command) -{ - u32 counter; - - gpio_clear(DOGM128_A0_PORT, DOGM128_A0_PIN); /* A0 low for commands */ - spi_send(DOGM128_SPI, command); - - for (counter = 0; counter<=500; counter++) /* wait */ - {} -} - -void dogm128_send_data(u8 data) -{ - u32 counter; - - gpio_set(DOGM128_A0_PORT, DOGM128_A0_PIN); /* A0 high for data */ - spi_send(DOGM128_SPI, data); - - for (counter = 0; counter<=500; counter++) /* wait */ - {} -} - -void dogm128_init() -{ - u32 counter; - - /* reset the display */ - gpio_clear(DOGM128_RESET_PORT, DOGM128_RESET_PIN); /* reset low for dogm128 */ - for (counter = 0; counter<=60000; counter++) /* wait */ - {} - gpio_set(DOGM128_RESET_PORT, DOGM128_RESET_PIN); /* reset high for dogm128 */ - - for (counter = 0; counter<=60000; counter++) /* wait */ - {} - - gpio_clear(DOGM128_A0_PORT, DOGM128_A0_PIN); /* A0 low for init */ - - /* tell the display that we want to start */ - spi_set_nss_low(DOGM128_SPI); - - /* init sequence */ - dogm128_send_command(DOGM128_DISPLAY_START_ADDRESS_BASE + 0); - dogm128_send_command(DOGM128_ADC_REVERSE); - dogm128_send_command(DOGM128_COM_OUTPUT_SCAN_NORMAL); - dogm128_send_command(DOGM128_DISPLAY_NORMAL); - dogm128_send_command(DOGM128_BIAS_19); - dogm128_send_command(DOGM128_POWER_CONTROL_BASE + 0x07); - dogm128_send_command(DOGM128_BOOSTER_RATIO_SET); - dogm128_send_command(0x00); /* Booster x4 */ - dogm128_send_command(DOGM128_V0_OUTPUT_RESISTOR_BASE + 0x07); - dogm128_send_command(DOGM128_ELECTRONIC_VOLUME_MODE_SET); - dogm128_send_command(0x16); /* Contrast */ - dogm128_send_command(DOGM128_STATIC_INDICATOR_OFF); - dogm128_send_command(0x00); /* Flashing OFF */ - dogm128_send_command(DOGM128_DISPLAY_ON); - - /* end transfer */ - spi_set_nss_high(DOGM128_SPI); -} - -void dogm128_print_char(u8 data) -{ - u8 i; - u8 page; - u8 shift; - u8 xcoord; - u8 ycoord; - - xcoord = dogm128_cursor_x; - ycoord = dogm128_cursor_y; - - page = (63 - ycoord) / 8; /* the display consists of 8 lines a 8 dots each. */ - shift = (7 -((63 - ycoord) % 8)); /* vertical shift */ - - /* font is 8x5 so iterate each column of the character */ - for (i = 0; i <= 5; i++) { - /* right border reached? */ - if ((xcoord + i) > 127) - return; - dogm128_cursor_x++; - - /* 0xAA = end of character - no dots in this line */ - if (dogm128_font[data - 0x20][i] == 0xAA) { - dogm128_ram[(page * 128) + xcoord + i] &= ~(0xFF >> shift); /* clear area */ - if ((shift > 0) && (page > 0)) - dogm128_ram[((page - 1) * 128) + xcoord + i] &= ~(0xFF << (8 - shift)); /* clear area */ - return; - } - - /* lower part */ - dogm128_ram[(page * 128) + xcoord + i] &= ~(0xFF >> shift); /* clear area */ - dogm128_ram[(page * 128) + xcoord + i] = (dogm128_font[data - 0x20][i] >> shift); - /* higher part if needed */ - if ((shift > 0) && (page > 0)) { - dogm128_ram[((page - 1) * 128) + xcoord + i] &= ~(0xFF << (8 - shift)); /* clear area */ - dogm128_ram[((page - 1) * 128) + xcoord + i] = (dogm128_font[data - 0x20][i] << (8 - shift)); - } - } -} - -void dogm128_set_cursor(u8 xcoord, u8 ycoord) -{ - dogm128_cursor_x = xcoord; - dogm128_cursor_y = ycoord; -} - -void dogm128_print_string(char * s) -{ - while (*s != 0) { - dogm128_print_char(*s); - s++; - } -} - -void dogm128_set_dot(u8 xcoord, u8 ycoord) -{ - dogm128_ram[(((63 - ycoord) / 8) * 128) + xcoord] |= (1 << ((63 - ycoord) % 8)); -} - -void dogm128_clear_dot(u8 xcoord, u8 ycoord) -{ - dogm128_ram[(((63 - ycoord) / 8) * 128) + xcoord] &= ~(1 << ((63 - ycoord) % 8)); -} - -void dogm128_update_display() -{ - u8 page; - u8 column; - - /* tell the display that we want to start */ - spi_set_nss_low(DOGM128_SPI); - - for (page = 0; page <= 7; page++) { - dogm128_send_command(0xB0 + page); /* set page */ - dogm128_send_command(0x10); /* set column upper address to 0 */ - dogm128_send_command(0x00); /* set column lower address to 0 */ - - for (column = 0; column <= 127; column++) { - dogm128_send_data(dogm128_ram[(page * 128) + column]); - } - } - - spi_set_nss_high(DOGM128_SPI); -} - -void dogm128_clear() -{ - u16 i; - - for (i = 0; i<=1023; i++) { - dogm128_ram[i] = 0; - } - dogm128_update_display(); -} - -/* This is a non-monospace font definition (upside down for better handling). - * 0xAA is the end of the character so its not space efficient in your memory, but on your display. - * We are starting with " " as the first printable character at 0x20, so we have to substract 0x20 later. - * Its the only defined to 127/0x7F so if you have german umlauts or other special characters from above - * you have to expand this definition a little bit. */ - -const u8 dogm128_font[96][6] = { - - /* 20 SPACE */ {0x00, 0x00, 0x00, 0xAA, 0xAA, 0xAA}, - /* 21 ! */ {0x5E, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA}, - /* 22 " */ {0x66, 0x00, 0x66, 0xAA, 0xAA, 0xAA}, - /* 23 # */ {0x28, 0x7C, 0x28, 0x7C, 0x28, 0xAA}, - /* 24 $ */ {0x24, 0x2A, 0x7F, 0x2A, 0x10, 0xAA}, - /* 25 % */ {0x62, 0x18, 0x46, 0xAA, 0xAA, 0xAA}, - /* 26 & */ {0x30, 0x4C, 0x5A, 0x24, 0x50, 0xAA}, - /* 27 ' */ {0x06, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA}, - /* 28 ( */ {0x3E, 0x41, 0xAA, 0xAA, 0xAA, 0xAA}, - /* 29 ) */ {0x41, 0x3E, 0xAA, 0xAA, 0xAA, 0xAA}, - /* 2A * */ {0x28, 0x10, 0x7C, 0x10, 0x28, 0xAA}, - /* 2B + */ {0x10, 0x38, 0x10, 0xAA, 0xAA, 0xAA}, - /* 2C , */ {0xC0, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA}, - /* 2D - */ {0x10, 0x10, 0x10, 0xAA, 0xAA, 0xAA}, - /* 2E . */ {0x40, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA}, - /* 2F / */ {0x60, 0x18, 0x06, 0xAA, 0xAA, 0xAA}, - - /* 30 0 */ {0x3C, 0x42, 0x42, 0x3C, 0xAA, 0xAA}, - /* 31 1 */ {0x44, 0x7E, 0x40, 0xAA, 0xAA, 0xAA}, - /* 32 2 */ {0x44, 0x62, 0x52, 0x4C, 0xAA, 0xAA}, - /* 33 3 */ {0x4A, 0x4A, 0x34, 0xAA, 0xAA, 0xAA}, - /* 34 4 */ {0x1E, 0x10, 0x78, 0x10, 0xAA, 0xAA}, - /* 35 5 */ {0x4E, 0x4A, 0x32, 0xAA, 0xAA, 0xAA}, - /* 36 6 */ {0x3C, 0x4A, 0x4A, 0x30, 0xAA, 0xAA}, - /* 37 7 */ {0x62, 0x12, 0x0E, 0xAA, 0xAA, 0xAA}, - /* 38 8 */ {0x34, 0x4A, 0x4A, 0x34, 0xAA, 0xAA}, - /* 39 9 */ {0x0C, 0x52, 0x52, 0x3C, 0xAA, 0xAA}, - /* 3A : */ {0x28, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA}, - /* 3B ; */ {0xC8, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA}, - /* 3C < */ {0x10, 0x28, 0x44, 0xAA, 0xAA, 0xAA}, - /* 3D = */ {0x28, 0x28, 0x28, 0xAA, 0xAA, 0xAA}, - /* 3E > */ {0x44, 0x28, 0x10, 0xAA, 0xAA, 0xAA}, - /* 3F ? */ {0x02, 0x52, 0x0C, 0xAA, 0xAA, 0xAA}, - - /* 40 @ */ {0x3C, 0x42, 0x12, 0x2A, 0x3C, 0xAA}, - /* 41 A */ {0x7C, 0x12, 0x12, 0x7C, 0xAA, 0xAA}, - /* 42 B */ {0x7E, 0x4A, 0x4A, 0x34, 0xAA, 0xAA}, - /* 43 C */ {0x3C, 0x42, 0x42, 0x24, 0xAA, 0xAA}, - /* 44 D */ {0x7E, 0x42, 0x42, 0x3C, 0xAA, 0xAA}, - /* 45 E */ {0x7E, 0x4A, 0x4A, 0xAA, 0xAA, 0xAA}, - /* 46 F */ {0x7E, 0x0A, 0x0A, 0xAA, 0xAA, 0xAA}, - /* 47 G */ {0x3C, 0x42, 0x52, 0x34, 0xAA, 0xAA}, - /* 48 H */ {0x7E, 0x08, 0x08, 0x7E, 0xAA, 0xAA}, - /* 49 I */ {0x42, 0x7E, 0x42, 0xAA, 0xAA, 0xAA}, - /* 4A J */ {0x42, 0x42, 0x3E, 0xAA, 0xAA, 0xAA}, - /* 4B K */ {0x7E, 0x08, 0x14, 0x62, 0xAA, 0xAA}, - /* 4C L */ {0x7E, 0x40, 0x40, 0xAA, 0xAA, 0xAA}, - /* 4D M */ {0x7E, 0x04, 0x08, 0x04, 0x7E, 0xAA}, - /* 4E N */ {0x7E, 0x04, 0x18, 0x20, 0x7E, 0xAA}, - /* 4F O */ {0x3C, 0x42, 0x42, 0x3C, 0xAA, 0xAA}, - - /* 50 P */ {0x7E, 0x12, 0x12, 0x0C, 0xAA, 0xAA}, - /* 51 Q */ {0x3C, 0x42, 0x42, 0xBC, 0xAA, 0xAA}, - /* 52 R */ {0x7E, 0x12, 0x12, 0x6C, 0xAA, 0xAA}, - /* 53 S */ {0x44, 0x4A, 0x4A, 0x30, 0xAA, 0xAA}, - /* 54 T */ {0x02, 0x7E, 0x02, 0xAA, 0xAA, 0xAA}, - /* 55 U */ {0x3E, 0x40, 0x40, 0x3E, 0xAA, 0xAA}, - /* 56 V */ {0x06, 0x18, 0x60, 0x18, 0x06, 0xAA}, - /* 57 W */ {0x3E, 0x40, 0x3E, 0x40, 0x3E, 0xAA}, - /* 58 X */ {0x42, 0x24, 0x18, 0x24, 0x42, 0xAA}, - /* 59 Y */ {0x9E, 0xA0, 0xA0, 0x7E, 0xAA, 0xAA}, - /* 5A Z */ {0x62, 0x52, 0x4A, 0x46, 0xAA, 0xAA}, - /* 5B [ */ {0x7E, 0x42, 0xAA, 0xAA, 0xAA, 0xAA}, - /* 5C \ */ {0x06, 0x18, 0x60, 0xAA, 0xAA, 0xAA}, - /* 5D ] */ {0x42, 0x7E, 0xAA, 0xAA, 0xAA, 0xAA}, - /* 5E ^ */ {0x04, 0x02, 0x04, 0xAA, 0xAA, 0xAA}, - /* 5F _ */ {0x40, 0x40, 0x40, 0xAA, 0xAA, 0xAA}, - - /* 60 ` */ {0x02, 0x04, 0xAA, 0xAA, 0xAA, 0xAA}, - /* 61 a */ {0x20, 0x54, 0x54, 0x78, 0xAA, 0xAA}, - /* 62 b */ {0x7E, 0x44, 0x44, 0x38, 0xAA, 0xAA}, - /* 63 c */ {0x38, 0x44, 0x44, 0x28, 0xAA, 0xAA}, - /* 64 d */ {0x38, 0x44, 0x44, 0x7E, 0xAA, 0xAA}, - /* 65 e */ {0x38, 0x54, 0x54, 0x58, 0xAA, 0xAA}, - /* 66 f */ {0x7C, 0x0A, 0xAA, 0xAA, 0xAA, 0xAA}, - /* 67 g */ {0x98, 0xA4, 0xA4, 0x7C, 0xAA, 0xAA}, - /* 68 h */ {0x7E, 0x04, 0x04, 0x78, 0xAA, 0xAA}, - /* 69 i */ {0x7A, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA}, - /* 6A j */ {0x40, 0x3A, 0xAA, 0xAA, 0xAA, 0xAA}, - /* 6B k */ {0x7E, 0x10, 0x28, 0x44, 0xAA, 0xAA}, - /* 6C l */ {0x7E, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA}, - /* 6D m */ {0x7C, 0x04, 0x78, 0x04, 0x78, 0xAA}, - /* 6E n */ {0x7C, 0x04, 0x04, 0x78, 0xAA, 0xAA}, - /* 6F o */ {0x38, 0x44, 0x44, 0x38, 0xAA, 0xAA}, - - /* 70 p */ {0xFC, 0x24, 0x24, 0x18, 0xAA, 0xAA}, - /* 71 q */ {0x18, 0x24, 0x24, 0xFC, 0xAA, 0xAA}, - /* 72 r */ {0x78, 0x04, 0xAA, 0xAA, 0xAA, 0xAA}, - /* 73 s */ {0x48, 0x54, 0x54, 0x20, 0xAA, 0xAA}, - /* 74 t */ {0x04, 0x3E, 0x44, 0xAA, 0xAA, 0xAA}, - /* 75 u */ {0x3C, 0x40, 0x40, 0x3C, 0xAA, 0xAA}, - /* 76 v */ {0x0C, 0x30, 0x40, 0x30, 0x0C, 0xAA}, - /* 77 w */ {0x3C, 0x40, 0x3C, 0x40, 0x3C, 0xAA}, - /* 78 x */ {0x44, 0x28, 0x10, 0x28, 0x44, 0xAA}, - /* 79 y */ {0x1C, 0xA0, 0xA0, 0x7C, 0xAA, 0xAA}, - /* 7A z */ {0x64, 0x54, 0x4C, 0xAA, 0xAA, 0xAA}, - /* 7B { */ {0x08, 0x36, 0x41, 0xAA, 0xAA, 0xAA}, - /* 7C | */ {0x7E, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA}, - /* 7D } */ {0x41, 0x36, 0x08, 0xAA, 0xAA, 0xAA}, - /* 7E ~ */ {0x20, 0x10, 0x20, 0x10, 0xAA, 0xAA}, - /* 7F DEL */ {0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA} -}; - diff --git a/examples/stm32/other/dogm128/dogm128.h b/examples/stm32/other/dogm128/dogm128.h deleted file mode 100644 index ed514ab..0000000 --- a/examples/stm32/other/dogm128/dogm128.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef DOGM128_H -#define DOGM128_H - -#include -#include -#include - -/* PB10 GPIO - ~RESET - * PB12 SPI2_NSS - ~CS1 - * PB13 SPI2_SCK - SCL - * PB14 SPI2_MISO - A0 - * PB15 SPI2_MOSI - SI */ - -#define DOGM128_SPI SPI2 -#define DOGM128_RESET_PIN GPIO10 -#define DOGM128_RESET_PORT GPIOB -#define DOGM128_A0_PIN GPIO14 -#define DOGM128_A0_PORT GPIOB - -/* DOGM128 display commands */ -#define DOGM128_PAGE_BASE 0xB0 -#define DOGM128_PAGE0 0xB0 -#define DOGM128_PAGE1 0xB1 -#define DOGM128_PAGE2 0xB2 -#define DOGM128_PAGE3 0xB3 -#define DOGM128_PAGE4 0xB4 -#define DOGM128_PAGE5 0xB5 -#define DOGM128_PAGE6 0xB6 -#define DOGM128_PAGE7 0xB7 -#define DOGM128_DISPLAY_ON 0xAF -#define DOGM128_DISPLAY_OFF 0xAE -#define DOGM128_DISPLAY_START_ADDRESS_BASE 0x40 -#define DOGM128_ADC_NORMAL 0xA0 -#define DOGM128_ADC_REVERSE 0xA1 -#define DOGM128_DISPLAY_NORMAL 0xA6 -#define DOGM128_DISPLAY_REVERSE 0xA7 -#define DOGM128_ALL_POINTS_ON 0xA5 -#define DOGM128_ALL_POINTS_OFF 0xA4 -#define DOGM128_BIAS_19 0xA2 -#define DOGM128_BIAS_17 0xA3 -#define DOGM128_INTERNAL_RESET 0xE2 -#define DOGM128_COM_OUTPUT_SCAN_NORMAL 0xC0 -#define DOGM128_COM_OUTPUT_SCAN_REVERSE 0xC8 -#define DOGM128_POWER_CONTROL_BASE 0x28 -#define DOGM128_V0_OUTPUT_RESISTOR_BASE 0x20 -#define DOGM128_ELECTRONIC_VOLUME_MODE_SET 0x81 -#define DOGM128_STATIC_INDICATOR_OFF 0xAC -#define DOGM128_STATIC_INDICATOR_ON 0xAD -#define DOGM128_BOOSTER_RATIO_SET 0xF8 - -extern const u8 dogm128_font[96][6]; -extern u8 dogm128_ram[1024]; -extern u8 dogm128_cursor_x; -extern u8 dogm128_cursor_y; - -void dogm128_send_command(u8 command); -void dogm128_set_cursor(u8 xcoord, u8 ycoord); -void dogm128_print_char(u8 data); -void dogm128_print_string(char * s); -void dogm128_set_dot(u8 xcoord, u8 ycoord); -void dogm128_clear_dot(u8 xcoord, u8 ycoord); -void dogm128_send_data(u8 data); -void dogm128_init(); -void dogm128_update_display(); -void dogm128_clear(); - -#endif diff --git a/examples/stm32/other/dogm128/main.c b/examples/stm32/other/dogm128/main.c deleted file mode 100644 index b12a36d..0000000 --- a/examples/stm32/other/dogm128/main.c +++ /dev/null @@ -1,110 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include -#include -#include -#include -#include -#include "./dogm128.h" - -void gpio_setup(void) -{ - /* Enable GPIOB clock. */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPBEN); - - /* Set GPIO6/7 (in GPIO port B) to 'output push-pull' for the LEDs. */ - gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_2_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO6); - gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_2_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO7); - - /* A0 of DOGM128 */ - gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO14); - /*reset of DOGM128 */ - gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO10); - - /* DOGM128/SPI2 clock and MOSI and NSS(CS1) */ - gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO12); - gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO13); - gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO15); -} - -void spi_setup() -{ - /* the DOGM128 display is connected to SPI2, so initialise it correctly */ - - rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_SPI2EN); - - spi_set_unidirectional_mode(DOGM128_SPI); /* we want to send only */ - spi_disable_crc(DOGM128_SPI); /* no CRC for this slave */ - spi_set_dff_8bit(DOGM128_SPI); /* 8-bit dataword-length */ - spi_set_full_duplex_mode(DOGM128_SPI); /* not receive-only */ - spi_enable_software_slave_management(DOGM128_SPI); /* we want to handle the CS signal in software */ - spi_set_nss_high(DOGM128_SPI); - spi_set_baudrate_prescaler(DOGM128_SPI, SPI_CR1_BR_FPCLK_DIV_256); /* PCLOCK/256 as clock */ - spi_set_master_mode(DOGM128_SPI); /* we want to control everything and generate the clock -> master */ - spi_set_clock_polarity_1(DOGM128_SPI); /* sck idle state high */ - spi_set_clock_phase_1(DOGM128_SPI); /* bit is taken on the second (rising edge) of sck */ - spi_enable_ss_output(DOGM128_SPI); - spi_enable(DOGM128_SPI); -} - -int main(void) -{ - rcc_clock_setup_in_hse_16mhz_out_72mhz(); - gpio_setup(); - spi_setup(); - - gpio_clear(GPIOB, GPIO7); /* LED1 on */ - gpio_set(GPIOB, GPIO6); /* LED2 off */ - - dogm128_init(); - dogm128_clear(); - - dogm128_set_cursor(0, 56); - dogm128_print_string("ABCDEFGHIJKLMNOPQRSTUVWXYZ"); - dogm128_set_cursor(0, 48); - dogm128_print_string("abcdefghijklmnopqrstuvwxyz"); - dogm128_set_cursor(0, 40); - dogm128_print_string(" !#$%&'()*+,-./0123456789"); - dogm128_set_cursor(0, 32); - dogm128_print_string(":;<=>?@[\\]^_`{|}~"); - - dogm128_set_dot(10, 10); - dogm128_set_dot(20, 10); - dogm128_set_dot(30, 10); - dogm128_set_dot(40, 10); - dogm128_set_dot(50, 10); - - dogm128_update_display(); - - gpio_set(GPIOB, GPIO7); /* LED1 off */ - while(1); /* Halt. */ - - return 0; -} - diff --git a/examples/stm32/other/dogm128/main.ld b/examples/stm32/other/dogm128/main.ld deleted file mode 100644 index c076521..0000000 --- a/examples/stm32/other/dogm128/main.ld +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* Linker script for an STM32F103RBT6 board (128K flash, 20K RAM). */ - -/* Define memory regions. */ -MEMORY -{ - rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K -} - -/* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld - diff --git a/examples/stm32/other/i2c_stts75_sensor/Makefile b/examples/stm32/other/i2c_stts75_sensor/Makefile deleted file mode 100644 index d0f6ddf..0000000 --- a/examples/stm32/other/i2c_stts75_sensor/Makefile +++ /dev/null @@ -1,25 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2009 Uwe Hermann -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program. If not, see . -## - -BINARY = i2c_stts75_sensor - -OBJS = stts75.o - -include ../../Makefile.include - diff --git a/examples/stm32/other/i2c_stts75_sensor/README b/examples/stm32/other/i2c_stts75_sensor/README deleted file mode 100644 index 91e3ff6..0000000 --- a/examples/stm32/other/i2c_stts75_sensor/README +++ /dev/null @@ -1,13 +0,0 @@ ------------------------------------------------------------------------------- -README ------------------------------------------------------------------------------- - -This example program sends some characters on USART1. -Afterwards it connects to an STTS75 sensor (ST LM75 compatible) -at adress A0/1/2=0 and sets reverse polarity, 26 degree Tos and Thyst. - -It reads out the temperature and submits the temperature over USART1 in -binary format (ASCII 0/1). - -The terminal settings for the receiving device/PC are 115200 8n1. - diff --git a/examples/stm32/other/i2c_stts75_sensor/i2c_stts75_sensor.c b/examples/stm32/other/i2c_stts75_sensor/i2c_stts75_sensor.c deleted file mode 100644 index f70c80d..0000000 --- a/examples/stm32/other/i2c_stts75_sensor/i2c_stts75_sensor.c +++ /dev/null @@ -1,146 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include -#include -#include -#include "stts75.h" - -void usart_setup(void) -{ - /* Enable clocks for GPIO port A (for GPIO_USART1_TX) and USART1. */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_USART1EN); - - /* Setup GPIO pin GPIO_USART1_TX/GPIO9 on GPIO port A for transmit. */ - gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_USART1_TX); - - /* Setup UART parameters. */ - usart_set_baudrate(USART1, 115200); - usart_set_databits(USART1, 8); - usart_set_stopbits(USART1, USART_STOPBITS_1); - usart_set_mode(USART1, USART_MODE_TX_RX); - usart_set_parity(USART1, USART_PARITY_NONE); - usart_set_flow_control(USART1, USART_FLOWCONTROL_NONE); - - /* Finally enable the USART. */ - usart_enable(USART1); -} - -void gpio_setup(void) -{ - /* Enable GPIOB clock. */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPBEN); - - /* Set GPIO6/7 (in GPIO port B) to 'output push-pull' for the LEDs. */ - gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_2_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO6); - gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_2_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO7); -} - -void i2c_setup(void) -{ - /* Enable clocks for I2C2 and AFIO. */ - rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_I2C2EN); - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_AFIOEN); - - /* Set alternate functions for the SCL and SDA pins of I2C2. */ - gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN, - GPIO_I2C2_SCL | GPIO_I2C2_SDA); - - /* Disable the I2C before changing any configuration. */ - i2c_peripheral_disable(I2C2); - - /* APB1 is running at 36MHz. */ - i2c_set_clock_frequency(I2C2, I2C_CR2_FREQ_36MHZ); - - /* 400KHz - I2C Fast Mode */ - i2c_set_fast_mode(I2C2); - - /* - * fclock for I2C is 36MHz APB2 -> cycle time 28ns, low time at 400KHz - * incl trise -> Thigh= 1600ns; CCR= tlow/tcycle= 0x1C,9; - * datasheet suggests 0x1e. - */ - i2c_set_ccr(I2C2, 0x1e); - - /* - * fclock for I2C is 36MHz -> cycle time 28ns, rise time for - * 400KHz => 300ns and 100KHz => 1000ns; 300ns/28ns = 10; - * incremented by 1 -> 11. - */ - i2c_set_trise(I2C2, 0x0b); - - /* - * This is our slave address - needed only if we want to receive from - * other masters. - */ - i2c_set_own_7bit_slave_address(I2C2, 0x32); - - /* If everything is configured -> enable the peripheral. */ - i2c_peripheral_enable(I2C2); -} - -int main(void) -{ - int i = 0; - u16 temperature; - - rcc_clock_setup_in_hse_16mhz_out_72mhz(); - gpio_setup(); - usart_setup(); - i2c_setup(); - - gpio_clear(GPIOB, GPIO7); /* LED1 on */ - gpio_set(GPIOB, GPIO6); /* LED2 off */ - - /* Send a message on USART1. */ - usart_send(USART1, 's'); - usart_send(USART1, 't'); - usart_send(USART1, 'm'); - usart_send(USART1, '\r'); - usart_send(USART1, '\n'); - - stts75_write_config(I2C2, STTS75_SENSOR0); - stts75_write_temp_os(I2C2, STTS75_SENSOR0, 0x1a00); /* 26 degrees */ - stts75_write_temp_hyst(I2C2, STTS75_SENSOR0, 0x1a00); - temperature = stts75_read_temperature(I2C2, STTS75_SENSOR0); - - /* Send the temperature as binary over USART1. */ - for (i = 15; i >= 0 ; i--) { - if (temperature & (1 << i)) - usart_send(USART1, '1'); - else - usart_send(USART1, '0'); - } - - usart_send(USART1, '\r'); - usart_send(USART1, '\n'); - - gpio_clear(GPIOB, GPIO6); /* LED2 on */ - - while(1); /* Halt. */ - - return 0; -} diff --git a/examples/stm32/other/i2c_stts75_sensor/i2c_stts75_sensor.ld b/examples/stm32/other/i2c_stts75_sensor/i2c_stts75_sensor.ld deleted file mode 100644 index c076521..0000000 --- a/examples/stm32/other/i2c_stts75_sensor/i2c_stts75_sensor.ld +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* Linker script for an STM32F103RBT6 board (128K flash, 20K RAM). */ - -/* Define memory regions. */ -MEMORY -{ - rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K -} - -/* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld - diff --git a/examples/stm32/other/i2c_stts75_sensor/stts75.c b/examples/stm32/other/i2c_stts75_sensor/stts75.c deleted file mode 100644 index f28019c..0000000 --- a/examples/stm32/other/i2c_stts75_sensor/stts75.c +++ /dev/null @@ -1,186 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include "stts75.h" - -void stts75_write_config(u32 i2c, u8 sensor) -{ - u32 reg32; - - /* Send START condition. */ - i2c_send_start(i2c); - - /* Waiting for START is send and switched to master mode. */ - while (!((I2C_SR1(i2c) & I2C_SR1_SB) - & (I2C_SR2(i2c) & (I2C_SR2_MSL | I2C_SR2_BUSY)))); - - /* Send destination address. */ - i2c_send_7bit_address(i2c, sensor, I2C_WRITE); - - /* Waiting for address is transferred. */ - while (!(I2C_SR1(i2c) & I2C_SR1_ADDR)); - - /* Cleaning ADDR condition sequence. */ - reg32 = I2C_SR2(i2c); - - /* Sending the data. */ - i2c_send_data(i2c, 0x1); /* stts75 config register */ - while (!(I2C_SR1(i2c) & I2C_SR1_BTF)); /* Await ByteTransferedFlag. */ - i2c_send_data(i2c, 0x4); /* pol reverse - LED glows if temp is below Tos/Thyst */ - while (!(I2C_SR1(i2c) & (I2C_SR1_BTF | I2C_SR1_TxE))); - - /* Send STOP condition. */ - i2c_send_stop(i2c); -} - -void stts75_write_temp_os(u32 i2c, u8 sensor, u16 temp_os) -{ - u32 reg32; - - /* Send START condition. */ - i2c_send_start(i2c); - - /* Waiting for START is send and switched to master mode. */ - while (!((I2C_SR1(i2c) & I2C_SR1_SB) - & (I2C_SR2(i2c) & (I2C_SR2_MSL | I2C_SR2_BUSY)))); - - /* Send destination address. */ - i2c_send_7bit_address(i2c, sensor, I2C_WRITE); - - /* Waiting for address is transferred. */ - while (!(I2C_SR1(i2c) & I2C_SR1_ADDR)); - - /* Cleaning ADDR condition sequence. */ - reg32 = I2C_SR2(i2c); - - /* Sending the data. */ - i2c_send_data(i2c, 0x3); /* OvertemperatureShutdown register */ - while (!(I2C_SR1(i2c) & I2C_SR1_BTF)); - i2c_send_data(i2c, (u8)(temp_os >> 8)); /* MSB */ - while (!(I2C_SR1(i2c) & I2C_SR1_BTF)); - i2c_send_data(i2c, (u8)(temp_os & 0xff00)); /* LSB */ - while (!(I2C_SR1(i2c) & (I2C_SR1_BTF | I2C_SR1_TxE))); /* After the last byte we have to wait for TxE too. */ - - /* Send STOP condition. */ - i2c_send_stop(i2c); -} - -void stts75_write_temp_hyst(u32 i2c, u8 sensor, u16 temp_hyst) -{ - u32 reg32; - - /* Send START condition. */ - i2c_send_start(i2c); - - /* Waiting for START is send and therefore switched to master mode. */ - while (!((I2C_SR1(i2c) & I2C_SR1_SB) - & (I2C_SR2(i2c) & (I2C_SR2_MSL | I2C_SR2_BUSY)))); - - /* Say to what address we want to talk to. */ - i2c_send_7bit_address(i2c, sensor, I2C_WRITE); - - /* Waiting for address is transferred. */ - while (!(I2C_SR1(i2c) & I2C_SR1_ADDR)); - - /* Cleaning ADDR condition sequence. */ - reg32 = I2C_SR2(i2c); - - /* Sending the data. */ - i2c_send_data(i2c, 0x2); /* TemperatureHysteresis register */ - while (!(I2C_SR1(i2c) & I2C_SR1_BTF)); - i2c_send_data(i2c, (u8)(temp_hyst >> 8)); /* MSB */ - while (!(I2C_SR1(i2c) & I2C_SR1_BTF)); - i2c_send_data(i2c, (u8)(temp_hyst & 0xff00)); /* LSB */ - while (!(I2C_SR1(i2c) & (I2C_SR1_BTF | I2C_SR1_TxE))); /* After the last byte we have to wait for TxE too. */ - - /* Send STOP condition. */ - i2c_send_stop(i2c); -} - -u16 stts75_read_temperature(u32 i2c, u8 sensor) -{ - u32 reg32; - u16 temperature; - - /* Send START condition. */ - i2c_send_start(i2c); - - /* Waiting for START is send and switched to master mode. */ - while (!((I2C_SR1(i2c) & I2C_SR1_SB) - & (I2C_SR2(i2c) & (I2C_SR2_MSL | I2C_SR2_BUSY)))); - - /* Say to what address we want to talk to. */ - /* Yes, WRITE is correct - for selecting register in STTS75. */ - i2c_send_7bit_address(i2c, sensor, I2C_WRITE); - - /* Waiting for address is transferred. */ - while (!(I2C_SR1(i2c) & I2C_SR1_ADDR)); - - /* Cleaning ADDR condition sequence. */ - reg32 = I2C_SR2(i2c); - - i2c_send_data(i2c, 0x0); /* temperature register */ - while (!(I2C_SR1(i2c) & (I2C_SR1_BTF|I2C_SR1_TxE))); - - /* - * Now we transferred that we want to ACCESS the temperature register. - * Now we send another START condition (repeated START) and then - * transfer the destination but with flag READ. - */ - - /* Send START condition. */ - i2c_send_start(i2c); - - /* Waiting for START is send and switched to master mode. */ - while (!((I2C_SR1(i2c) & I2C_SR1_SB) - & (I2C_SR2(i2c) & (I2C_SR2_MSL | I2C_SR2_BUSY)))); - - /* Say to what address we want to talk to. */ - i2c_send_7bit_address(i2c, sensor, I2C_READ); - - /* 2-byte receive is a special case. See datasheet POS bit. */ - I2C_CR1(i2c) |= (I2C_CR1_POS | I2C_CR1_ACK); - - /* Waiting for address is transferred. */ - while (!(I2C_SR1(i2c) & I2C_SR1_ADDR)); - - /* Cleaning ADDR condition sequence. */ - reg32 = I2C_SR2(i2c); - - /* Cleaning I2C_SR1_ACK. */ - I2C_CR1(i2c) &= ~ I2C_CR1_ACK; - - /* Now the slave should begin to send us the first byte. Await BTF. */ - while (!(I2C_SR1(i2c) & I2C_SR1_BTF)); - temperature = (u16)(I2C_DR(i2c) << 8); /* MSB */ - - /* - * Yes they mean it: we have to generate the STOP condition before - * saving the 1st byte. - */ - I2C_CR1(i2c) |= I2C_CR1_STOP; - - temperature |= I2C_DR(i2c); /* LSB */ - - /* Original state. */ - I2C_CR1(i2c) &= ~I2C_CR1_POS; - - return temperature; -} diff --git a/examples/stm32/other/i2c_stts75_sensor/stts75.h b/examples/stm32/other/i2c_stts75_sensor/stts75.h deleted file mode 100644 index 57f6190..0000000 --- a/examples/stm32/other/i2c_stts75_sensor/stts75.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef STTS75_H -#define STTS75_H - -#include - -#define STTS75_SENSOR0 0x48 -#define STTS75_SENSOR1 0x49 -#define STTS75_SENSOR2 0x4a -#define STTS75_SENSOR3 0x4b -#define STTS75_SENSOR4 0x4c -#define STTS75_SENSOR5 0x4d -#define STTS75_SENSOR6 0x4e -#define STTS75_SENSOR7 0x4f - -void stts75_write_config(u32 i2c, u8 sensor); -void stts75_write_temp_os(u32 i2c, u8 sensor, u16 temp_os); -void stts75_write_temp_hyst(u32 i2c, u8 sensor, u16 temp_hyst); -u16 stts75_read_temperature(u32 i2c, u8 sensor); - -#endif diff --git a/examples/stm32/other/rtc/Makefile b/examples/stm32/other/rtc/Makefile deleted file mode 100644 index 1efa7ac..0000000 --- a/examples/stm32/other/rtc/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2009 Uwe Hermann -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program. If not, see . -## - -BINARY = rtc - -include ../../Makefile.include - diff --git a/examples/stm32/other/rtc/README b/examples/stm32/other/rtc/README deleted file mode 100644 index f1e3975..0000000 --- a/examples/stm32/other/rtc/README +++ /dev/null @@ -1,6 +0,0 @@ ------------------------------------------------------------------------------- -README ------------------------------------------------------------------------------- - -This is a small RTC example project. - diff --git a/examples/stm32/other/rtc/rtc.c b/examples/stm32/other/rtc/rtc.c deleted file mode 100644 index c447534..0000000 --- a/examples/stm32/other/rtc/rtc.c +++ /dev/null @@ -1,116 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Lord James - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include -#include -#include -#include - -void clock_setup(void) -{ - rcc_clock_setup_in_hse_8mhz_out_72mhz(); - - /* Enable GPIOC clock. */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); - - /* Enable clocks for GPIO port A (for GPIO_USART1_TX) and USART1. */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_USART1EN); -} - -void usart_setup(void) -{ - /* Setup GPIO pin GPIO_USART1_TX/GPIO9 on GPIO port A for transmit. */ - gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_USART1_TX); - - /* Setup UART parameters. */ - usart_set_baudrate(USART1, 38400); - usart_set_databits(USART1, 8); - usart_set_stopbits(USART1, USART_STOPBITS_1); - usart_set_mode(USART1, USART_MODE_TX); - usart_set_parity(USART1, USART_PARITY_NONE); - usart_set_flow_control(USART1, USART_FLOWCONTROL_NONE); - - /* Finally enable the USART. */ - usart_enable(USART1); -} - -void gpio_setup(void) -{ - /* Set GPIO12 (in GPIO port C) to 'output push-pull'. */ - gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_2_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO12); -} - -void nvic_setup(void) -{ - /* Without this the RTC interrupt routine will never be called. */ - nvic_enable_irq(NVIC_RTC_IRQ); - nvic_set_priority(NVIC_RTC_IRQ, 1); -} - -void rtc_isr(void) -{ - volatile u32 j = 0, c = 0; - - /* The interrupt flag isn't cleared by hardware, we have to do it. */ - rtc_clear_flag(RTC_SEC); - - /* Visual output. */ - gpio_toggle(GPIOC, GPIO12); - - c = rtc_get_counter_val(); - - /* Display the current counter value in binary via USART1. */ - for (j = 0; j < 32; j++) { - if ((c & (0x80000000 >> j)) != 0) { - usart_send(USART1, '1'); - } else { - usart_send(USART1, '0'); - } - } - usart_send(USART1, '\n'); -} - -int main(void) -{ - clock_setup(); - gpio_setup(); - usart_setup(); - - /* - * If the RTC is pre-configured just allow access, don't reconfigure. - * Otherwise enable it with the LSE as clock source and 0x7fff as - * prescale value. - */ - rtc_auto_awake(LSE, 0x7fff); - - /* Setup the RTC interrupt. */ - nvic_setup(); - - /* Enable the RTC interrupt to occur off the SEC flag. */ - rtc_interrupt_enable(RTC_SEC); - - while(1); - - return 0; -} diff --git a/examples/stm32/other/rtc/rtc.ld b/examples/stm32/other/rtc/rtc.ld deleted file mode 100644 index 7ea2b92..0000000 --- a/examples/stm32/other/rtc/rtc.ld +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* Linker script for Olimex STM32-H103 (STM32F103RBT6, 128K flash, 20K RAM). */ - -/* Define memory regions. */ -MEMORY -{ - rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K -} - -/* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld - diff --git a/examples/stm32/other/systick/Makefile b/examples/stm32/other/systick/Makefile deleted file mode 100644 index 91b5cb5..0000000 --- a/examples/stm32/other/systick/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2009 Uwe Hermann -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program. If not, see . -## - -BINARY = systick - -include ../../Makefile.include - diff --git a/examples/stm32/other/systick/README b/examples/stm32/other/systick/README deleted file mode 100644 index affb4b8..0000000 --- a/examples/stm32/other/systick/README +++ /dev/null @@ -1,7 +0,0 @@ ------------------------------------------------------------------------------- -README ------------------------------------------------------------------------------- - -This example program blinks a LED on PortB Pin 6. 1 second on / 1 second off. -Blinking is done via the systick timer interrupt. - diff --git a/examples/stm32/other/systick/systick.c b/examples/stm32/other/systick/systick.c deleted file mode 100644 index c05aff7..0000000 --- a/examples/stm32/other/systick/systick.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include -#include -#include - -u32 temp32; - -void gpio_setup(void) -{ - /* Enable GPIOB clock. */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPBEN); - - /* Set GPIO6/7 (in GPIO port B) to 'output push-pull' for the LEDs. */ - gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_2_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO6); - gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_2_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO7); -} - -void sys_tick_handler() -{ - temp32++; - - /* we call this handler every 1ms so 1000ms = 1s on/off */ - if (temp32 == 1000) { - gpio_toggle(GPIOB, GPIO6); /* LED2 on/off */ - temp32 = 0; - } -} - -int main(void) -{ - rcc_clock_setup_in_hse_16mhz_out_72mhz(); - gpio_setup(); - - gpio_clear(GPIOB, GPIO7); /* LED1 on */ - gpio_set(GPIOB, GPIO6); /* LED2 off */ - - temp32 = 0; - - /* 72MHz / 8 => 9000000 counts per second */ - systick_set_clocksource(STK_CTRL_CLKSOURCE_AHB_DIV8); - - /* 9000000/9000 = 1000 overflows per second - every 1ms one interrupt */ - systick_set_reload(9000); - - systick_interrupt_enable(); - - /* start counting */ - systick_counter_enable(); - - while(1); /* Halt. */ - - return 0; -} diff --git a/examples/stm32/other/systick/systick.ld b/examples/stm32/other/systick/systick.ld deleted file mode 100644 index c076521..0000000 --- a/examples/stm32/other/systick/systick.ld +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* Linker script for an STM32F103RBT6 board (128K flash, 20K RAM). */ - -/* Define memory regions. */ -MEMORY -{ - rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K -} - -/* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld - diff --git a/examples/stm32/other/timer_interrupt/Makefile b/examples/stm32/other/timer_interrupt/Makefile deleted file mode 100644 index 86aced4..0000000 --- a/examples/stm32/other/timer_interrupt/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2009 Uwe Hermann -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program. If not, see . -## - -BINARY = timer - -include ../../Makefile.include - diff --git a/examples/stm32/other/timer_interrupt/README b/examples/stm32/other/timer_interrupt/README deleted file mode 100644 index e6a22c4..0000000 --- a/examples/stm32/other/timer_interrupt/README +++ /dev/null @@ -1,7 +0,0 @@ ------------------------------------------------------------------------------- -README ------------------------------------------------------------------------------- - -This example program blinks a LED on PortB Pin 6. 1 second on / 1 second off. -Blinking is made only with the timer interrupt of the TIM2 timer. - diff --git a/examples/stm32/other/timer_interrupt/timer.c b/examples/stm32/other/timer_interrupt/timer.c deleted file mode 100644 index aa2cdb6..0000000 --- a/examples/stm32/other/timer_interrupt/timer.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include -#include -#include - -void gpio_setup(void) -{ - /* Enable GPIOB clock. */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPBEN); - - /* Set GPIO6/7 (in GPIO port B) to 'output push-pull' for the LEDs. */ - gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_2_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO6); - gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_2_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO7); -} - -void nvic_setup() -{ - /* without this the timer interrupt routine will never be called */ - nvic_enable_irq(NVIC_TIM2_IRQ); - nvic_set_priority(NVIC_TIM2_IRQ, 1); -} - -void tim2_isr() -{ - /* LED2 on/off */ - gpio_toggle(GPIOB, GPIO6); - - /* clear interrrupt flag */ - TIM_SR(TIM2) &= ~TIM_SR_UIF; -} - -int main(void) -{ - rcc_clock_setup_in_hse_16mhz_out_72mhz(); - gpio_setup(); - nvic_setup(); - - gpio_clear(GPIOB, GPIO7); /* LED1 on */ - gpio_set(GPIOB, GPIO6); /* LED2 off */ - - rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_TIM2EN); - - /* the goal is to let the LED2 glow for a second and then be off for a second */ - - /* Set timer start value */ - TIM_CNT(TIM2) = 1; - - /* Set timer prescaler. 72MHz/1440 => 50000 counts per second */ - TIM_PSC(TIM2) = 1440; - - /* End timer value. If this value is reached an interrupt is generated */ - TIM_ARR(TIM2) = 50000; - - /* Update interrupt enable */ - TIM_DIER(TIM2) |= TIM_DIER_UIE; - - /* Start timer */ - TIM_CR1(TIM2) |= TIM_CR1_CEN; - - while(1); /* Halt. */ - - return 0; -} diff --git a/examples/stm32/other/timer_interrupt/timer.ld b/examples/stm32/other/timer_interrupt/timer.ld deleted file mode 100644 index c076521..0000000 --- a/examples/stm32/other/timer_interrupt/timer.ld +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* Linker script for an STM32F103RBT6 board (128K flash, 20K RAM). */ - -/* Define memory regions. */ -MEMORY -{ - rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K -} - -/* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld - diff --git a/examples/stm32/other/usb_cdcacm/Makefile b/examples/stm32/other/usb_cdcacm/Makefile deleted file mode 100644 index 38179e3..0000000 --- a/examples/stm32/other/usb_cdcacm/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2009 Uwe Hermann -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program. If not, see . -## - -BINARY = cdcacm - -include ../../Makefile.include - diff --git a/examples/stm32/other/usb_cdcacm/README b/examples/stm32/other/usb_cdcacm/README deleted file mode 100644 index 2f1ee4b..0000000 --- a/examples/stm32/other/usb_cdcacm/README +++ /dev/null @@ -1,7 +0,0 @@ ------------------------------------------------------------------------------- -README ------------------------------------------------------------------------------- - -This example implements a USB CDC-ACM device (aka Virtual Serial Port) -to demonstrate the use of the USB device stack. - diff --git a/examples/stm32/other/usb_cdcacm/cdcacm.c b/examples/stm32/other/usb_cdcacm/cdcacm.c deleted file mode 100644 index fdc92e2..0000000 --- a/examples/stm32/other/usb_cdcacm/cdcacm.c +++ /dev/null @@ -1,245 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Gareth McMullin - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include -#include -#include - -static const struct usb_device_descriptor dev = { - .bLength = USB_DT_DEVICE_SIZE, - .bDescriptorType = USB_DT_DEVICE, - .bcdUSB = 0x0200, - .bDeviceClass = USB_CLASS_CDC, - .bDeviceSubClass = 0, - .bDeviceProtocol = 0, - .bMaxPacketSize0 = 64, - .idVendor = 0x0483, - .idProduct = 0x5740, - .bcdDevice = 0x0200, - .iManufacturer = 1, - .iProduct = 2, - .iSerialNumber = 3, - .bNumConfigurations = 1, -}; - -/* This notification endpoint isn't implemented. According to CDC spec its - * optional, but its absence causes a NULL pointer dereference in Linux cdc_acm - * driver. */ -static const struct usb_endpoint_descriptor comm_endp[] = {{ - .bLength = USB_DT_ENDPOINT_SIZE, - .bDescriptorType = USB_DT_ENDPOINT, - .bEndpointAddress = 0x83, - .bmAttributes = USB_ENDPOINT_ATTR_INTERRUPT, - .wMaxPacketSize = 16, - .bInterval = 255, -}}; - -static const struct usb_endpoint_descriptor data_endp[] = {{ - .bLength = USB_DT_ENDPOINT_SIZE, - .bDescriptorType = USB_DT_ENDPOINT, - .bEndpointAddress = 0x01, - .bmAttributes = USB_ENDPOINT_ATTR_BULK, - .wMaxPacketSize = 64, - .bInterval = 1, -}, { - .bLength = USB_DT_ENDPOINT_SIZE, - .bDescriptorType = USB_DT_ENDPOINT, - .bEndpointAddress = 0x82, - .bmAttributes = USB_ENDPOINT_ATTR_BULK, - .wMaxPacketSize = 64, - .bInterval = 1, -}}; - -static const struct { - struct usb_cdc_header_descriptor header; - struct usb_cdc_call_management_descriptor call_mgmt; - struct usb_cdc_acm_descriptor acm; - struct usb_cdc_union_descriptor cdc_union; -} __attribute__((packed)) cdcacm_functional_descriptors = { - .header = { - .bFunctionLength = sizeof(struct usb_cdc_header_descriptor), - .bDescriptorType = CS_INTERFACE, - .bDescriptorSubtype = USB_CDC_TYPE_HEADER, - .bcdCDC = 0x0110, - }, - .call_mgmt = { - .bFunctionLength = - sizeof(struct usb_cdc_call_management_descriptor), - .bDescriptorType = CS_INTERFACE, - .bDescriptorSubtype = USB_CDC_TYPE_CALL_MANAGEMENT, - .bmCapabilities = 0, - .bDataInterface = 1, - }, - .acm = { - .bFunctionLength = sizeof(struct usb_cdc_acm_descriptor), - .bDescriptorType = CS_INTERFACE, - .bDescriptorSubtype = USB_CDC_TYPE_ACM, - .bmCapabilities = 0, - }, - .cdc_union = { - .bFunctionLength = sizeof(struct usb_cdc_union_descriptor), - .bDescriptorType = CS_INTERFACE, - .bDescriptorSubtype = USB_CDC_TYPE_UNION, - .bControlInterface = 0, - .bSubordinateInterface0 = 1, - } -}; - -static const struct usb_interface_descriptor comm_iface[] = {{ - .bLength = USB_DT_INTERFACE_SIZE, - .bDescriptorType = USB_DT_INTERFACE, - .bInterfaceNumber = 0, - .bAlternateSetting = 0, - .bNumEndpoints = 1, - .bInterfaceClass = USB_CLASS_CDC, - .bInterfaceSubClass = USB_CDC_SUBCLASS_ACM, - .bInterfaceProtocol = USB_CDC_PROTOCOL_AT, - .iInterface = 0, - - .endpoint = comm_endp, - - .extra = &cdcacm_functional_descriptors, - .extralen = sizeof(cdcacm_functional_descriptors) -}}; - -static const struct usb_interface_descriptor data_iface[] = {{ - .bLength = USB_DT_INTERFACE_SIZE, - .bDescriptorType = USB_DT_INTERFACE, - .bInterfaceNumber = 1, - .bAlternateSetting = 0, - .bNumEndpoints = 2, - .bInterfaceClass = USB_CLASS_DATA, - .bInterfaceSubClass = 0, - .bInterfaceProtocol = 0, - .iInterface = 0, - - .endpoint = data_endp, -}}; - -static const struct usb_interface ifaces[] = {{ - .num_altsetting = 1, - .altsetting = comm_iface, -}, { - .num_altsetting = 1, - .altsetting = data_iface, -}}; - -static const struct usb_config_descriptor config = { - .bLength = USB_DT_CONFIGURATION_SIZE, - .bDescriptorType = USB_DT_CONFIGURATION, - .wTotalLength = 0, - .bNumInterfaces = 2, - .bConfigurationValue = 1, - .iConfiguration = 0, - .bmAttributes = 0x80, - .bMaxPower = 0x32, - - .interface = ifaces, -}; - -static const char *usb_strings[] = { - "x", - "Black Sphere Technologies", - "CDC-ACM Demo", - "DEMO" -}; - -static int cdcacm_control_request(struct usb_setup_data *req, u8 **buf, - u16 *len, void (**complete)(struct usb_setup_data *req)) -{ - (void)complete; - (void)buf; - - switch(req->bRequest) { - case USB_CDC_REQ_SET_CONTROL_LINE_STATE: { - /* This Linux cdc_acm driver requires this to be implemented - * even though it's optional in the CDC spec, and we don't - * advertise it in the ACM functional descriptor. */ - char buf[10]; - struct usb_cdc_notification *notif = (void*)buf; - - /* We echo signals back to host as notification */ - notif->bmRequestType = 0xA1; - notif->bNotification = USB_CDC_NOTIFY_SERIAL_STATE; - notif->wValue = 0; - notif->wIndex = 0; - notif->wLength = 2; - buf[8] = req->wValue & 3; - buf[9] = 0; - //usbd_ep_write_packet(0x83, buf, 10); - return 1; - } - case USB_CDC_REQ_SET_LINE_CODING: - if(*len < sizeof(struct usb_cdc_line_coding)) - return 0; - - return 1; - } - return 0; -} - -static void cdcacm_data_rx_cb(u8 ep) -{ - (void)ep; - - char buf[64]; - int len = usbd_ep_read_packet(0x01, buf, 64); - if(len) { - usbd_ep_write_packet(0x82, buf, len); - buf[len] = 0; - } -} - -static void cdcacm_set_config(u16 wValue) -{ - (void)wValue; - - usbd_ep_setup(0x01, USB_ENDPOINT_ATTR_BULK, 64, cdcacm_data_rx_cb); - usbd_ep_setup(0x82, USB_ENDPOINT_ATTR_BULK, 64, NULL); - usbd_ep_setup(0x83, USB_ENDPOINT_ATTR_INTERRUPT, 16, NULL); - - usbd_register_control_callback( - USB_REQ_TYPE_CLASS | USB_REQ_TYPE_INTERFACE, - USB_REQ_TYPE_TYPE | USB_REQ_TYPE_RECIPIENT, - cdcacm_control_request); -} - -int main(void) -{ - rcc_clock_setup_in_hsi_out_48mhz(); - - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_AFIOEN); - - AFIO_MAPR |= AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_ON; - - gpio_set_mode(GPIOA, GPIO_MODE_INPUT, 0, GPIO15); - - usbd_init(&stm32f103_usb_driver, &dev, &config, usb_strings); - usbd_register_set_config_callback(cdcacm_set_config); - - gpio_set(GPIOA, GPIO15); - gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_2_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO15); - - while (1) - usbd_poll(); -} diff --git a/examples/stm32/other/usb_cdcacm/cdcacm.ld b/examples/stm32/other/usb_cdcacm/cdcacm.ld deleted file mode 100644 index 1c20282..0000000 --- a/examples/stm32/other/usb_cdcacm/cdcacm.ld +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* Define memory regions. */ -MEMORY -{ - rom (rx) : ORIGIN = 0x08000000, LENGTH = 64K - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K -} - -/* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld - diff --git a/examples/stm32/other/usb_dfu/Makefile b/examples/stm32/other/usb_dfu/Makefile deleted file mode 100644 index 48e2d6b..0000000 --- a/examples/stm32/other/usb_dfu/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2009 Uwe Hermann -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program. If not, see . -## - -BINARY = usbdfu - -include ../../Makefile.include - diff --git a/examples/stm32/other/usb_dfu/README b/examples/stm32/other/usb_dfu/README deleted file mode 100644 index 9c0169a..0000000 --- a/examples/stm32/other/usb_dfu/README +++ /dev/null @@ -1,7 +0,0 @@ ------------------------------------------------------------------------------- -README ------------------------------------------------------------------------------- - -This example implements a USB Device Firmware Upgrade (DFU) bootloader -to demonstrate the use of the USB device stack. - diff --git a/examples/stm32/other/usb_dfu/usbdfu.c b/examples/stm32/other/usb_dfu/usbdfu.c deleted file mode 100644 index 7ffbc74..0000000 --- a/examples/stm32/other/usb_dfu/usbdfu.c +++ /dev/null @@ -1,270 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Gareth McMullin - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include -#include -#include -#include -#include - -#define APP_ADDRESS 0x08002000 - -/* Commands sent with wBlockNum == 0 as per ST implementation. */ -#define CMD_SETADDR 0x21 -#define CMD_ERASE 0x41 - -/* We need a special large control buffer for this device: */ -u8 usbd_control_buffer[1024]; - -static enum dfu_state usbdfu_state = STATE_DFU_IDLE; - -static struct { - u8 buf[sizeof(usbd_control_buffer)]; - u16 len; - u32 addr; - u16 blocknum; -} prog; - -const struct usb_device_descriptor dev = { - .bLength = USB_DT_DEVICE_SIZE, - .bDescriptorType = USB_DT_DEVICE, - .bcdUSB = 0x0200, - .bDeviceClass = 0, - .bDeviceSubClass = 0, - .bDeviceProtocol = 0, - .bMaxPacketSize0 = 64, - .idVendor = 0x0483, - .idProduct = 0xDF11, - .bcdDevice = 0x0200, - .iManufacturer = 1, - .iProduct = 2, - .iSerialNumber = 3, - .bNumConfigurations = 1, -}; - -const struct usb_dfu_descriptor dfu_function = { - .bLength = sizeof(struct usb_dfu_descriptor), - .bDescriptorType = DFU_FUNCTIONAL, - .bmAttributes = USB_DFU_CAN_DOWNLOAD | USB_DFU_WILL_DETACH, - .wDetachTimeout = 255, - .wTransferSize = 1024, - .bcdDFUVersion = 0x011A, -}; - -const struct usb_interface_descriptor iface = { - .bLength = USB_DT_INTERFACE_SIZE, - .bDescriptorType = USB_DT_INTERFACE, - .bInterfaceNumber = 0, - .bAlternateSetting = 0, - .bNumEndpoints = 0, - .bInterfaceClass = 0xFE, /* Device Firmware Upgrade */ - .bInterfaceSubClass = 1, - .bInterfaceProtocol = 2, - - /* The ST Microelectronics DfuSe application needs this string. - * The format isn't documented... */ - .iInterface = 4, - - .extra = &dfu_function, - .extralen = sizeof(dfu_function), -}; - -const struct usb_interface ifaces[] = {{ - .num_altsetting = 1, - .altsetting = &iface, -}}; - -const struct usb_config_descriptor config = { - .bLength = USB_DT_CONFIGURATION_SIZE, - .bDescriptorType = USB_DT_CONFIGURATION, - .wTotalLength = 0, - .bNumInterfaces = 1, - .bConfigurationValue = 1, - .iConfiguration = 0, - .bmAttributes = 0xC0, - .bMaxPower = 0x32, - - .interface = ifaces, -}; - -static const char *usb_strings[] = { - "x", - "Black Sphere Technologies", - "DFU Demo", - "DEMO", - /* This string is used by ST Microelectronics' DfuSe utility */ - "@Internal Flash /0x08000000/8*001Ka,56*001Kg" -}; - -static u8 usbdfu_getstatus(u32 *bwPollTimeout) -{ - switch(usbdfu_state) { - case STATE_DFU_DNLOAD_SYNC: - usbdfu_state = STATE_DFU_DNBUSY; - *bwPollTimeout = 100; - return DFU_STATUS_OK; - - case STATE_DFU_MANIFEST_SYNC: - /* Device will reset when read is complete */ - usbdfu_state = STATE_DFU_MANIFEST; - return DFU_STATUS_OK; - - default: - return DFU_STATUS_OK; - } -} - -static void usbdfu_getstatus_complete(struct usb_setup_data *req) -{ - int i; - (void)req; - - switch(usbdfu_state) { - case STATE_DFU_DNBUSY: - - flash_unlock(); - if(prog.blocknum == 0) { - switch(prog.buf[0]) { - case CMD_ERASE: - flash_erase_page(*(u32*)(prog.buf+1)); - case CMD_SETADDR: - prog.addr = *(u32*)(prog.buf+1); - } - } else { - u32 baseaddr = prog.addr + - ((prog.blocknum - 2) * - dfu_function.wTransferSize); - for(i = 0; i < prog.len; i += 2) - flash_program_half_word(baseaddr + i, - *(u16*)(prog.buf+i)); - } - flash_lock(); - - /* We jump straight to dfuDNLOAD-IDLE, - * skipping dfuDNLOAD-SYNC - */ - usbdfu_state = STATE_DFU_DNLOAD_IDLE; - return; - - case STATE_DFU_MANIFEST: - /* USB device must detach, we just reset... */ - scb_reset_system(); - return; /* Will never return */ - default: - return; - } -} - -static int usbdfu_control_request(struct usb_setup_data *req, u8 **buf, - u16 *len, void (**complete)(struct usb_setup_data *req)) -{ - - if((req->bmRequestType & 0x7F) != 0x21) - return 0; /* Only accept class request */ - - switch(req->bRequest) { - case DFU_DNLOAD: - if((len == NULL) || (*len == 0)) { - usbdfu_state = STATE_DFU_MANIFEST_SYNC; - return 1; - } else { - /* Copy download data for use on GET_STATUS */ - prog.blocknum = req->wValue; - prog.len = *len; - memcpy(prog.buf, *buf, *len); - usbdfu_state = STATE_DFU_DNLOAD_SYNC; - return 1; - } - case DFU_CLRSTATUS: - /* Clear error and return to dfuIDLE */ - if(usbdfu_state == STATE_DFU_ERROR) - usbdfu_state = STATE_DFU_IDLE; - return 1; - case DFU_ABORT: - /* Abort returns to dfuIDLE state */ - usbdfu_state = STATE_DFU_IDLE; - return 1; - case DFU_UPLOAD: - /* Upload not supported for now */ - return 0; - case DFU_GETSTATUS: { - u32 bwPollTimeout = 0; /* 24-bit integer in DFU class spec */ - - (*buf)[0] = usbdfu_getstatus(&bwPollTimeout); - (*buf)[1] = bwPollTimeout & 0xFF; - (*buf)[2] = (bwPollTimeout >> 8) & 0xFF; - (*buf)[3] = (bwPollTimeout >> 16) & 0xFF; - (*buf)[4] = usbdfu_state; - (*buf)[5] = 0; /* iString not used here */ - *len = 6; - - *complete = usbdfu_getstatus_complete; - - return 1; - } - case DFU_GETSTATE: - /* Return state with no state transision */ - *buf[0] = usbdfu_state; - *len = 1; - return 1; - } - - return 0; -} - -int main(void) -{ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); - if(!gpio_get(GPIOA, GPIO10)) { - /* Boot the application if it's valid */ - if((*(volatile u32*)APP_ADDRESS & 0x2FFE0000) == 0x20000000) { - /* Set vector table base address */ - SCB_VTOR = APP_ADDRESS & 0xFFFF; - /* Initialise master stack pointer */ - asm volatile ("msr msp, %0"::"g" - (*(volatile u32*)APP_ADDRESS)); - /* Jump to application */ - (*(void(**)())(APP_ADDRESS + 4))(); - } - } - - rcc_clock_setup_in_hsi_out_48mhz(); - - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_AFIOEN); - - AFIO_MAPR |= AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_ON; - gpio_set_mode(GPIOA, GPIO_MODE_INPUT, 0, GPIO15); - - usbd_init(&stm32f103_usb_driver, &dev, &config, usb_strings); - usbd_set_control_buffer_size(sizeof(usbd_control_buffer)); - usbd_register_control_callback( - USB_REQ_TYPE_CLASS | USB_REQ_TYPE_INTERFACE, - USB_REQ_TYPE_TYPE | USB_REQ_TYPE_RECIPIENT, - usbdfu_control_request); - - gpio_set(GPIOA, GPIO15); - gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_2_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO15); - - while (1) - usbd_poll(); -} diff --git a/examples/stm32/other/usb_dfu/usbdfu.ld b/examples/stm32/other/usb_dfu/usbdfu.ld deleted file mode 100644 index 54e5dac..0000000 --- a/examples/stm32/other/usb_dfu/usbdfu.ld +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* Define memory regions. */ -MEMORY -{ - rom (rx) : ORIGIN = 0x08000000, LENGTH = 8K - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 4K -} - -/* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld - diff --git a/examples/stm32/other/usb_hid/Makefile b/examples/stm32/other/usb_hid/Makefile deleted file mode 100644 index d831e9e..0000000 --- a/examples/stm32/other/usb_hid/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2009 Uwe Hermann -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program. If not, see . -## - -BINARY = usbhid - -include ../../Makefile.include - diff --git a/examples/stm32/other/usb_hid/README b/examples/stm32/other/usb_hid/README deleted file mode 100644 index 92645c9..0000000 --- a/examples/stm32/other/usb_hid/README +++ /dev/null @@ -1,7 +0,0 @@ ------------------------------------------------------------------------------- -README ------------------------------------------------------------------------------- - -This example implements a USB Human Interface Device (HID) -to demonstrate the use of the USB device stack. - diff --git a/examples/stm32/other/usb_hid/usbhid.c b/examples/stm32/other/usb_hid/usbhid.c deleted file mode 100644 index 8f08aac..0000000 --- a/examples/stm32/other/usb_hid/usbhid.c +++ /dev/null @@ -1,272 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Gareth McMullin - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include -#include -#include -#include - -/* Define this to include the DFU APP interface. */ -#define INCLUDE_DFU_INTERFACE - -#ifdef INCLUDE_DFU_INTERFACE -#include -#include -#endif - -const struct usb_device_descriptor dev = { - .bLength = USB_DT_DEVICE_SIZE, - .bDescriptorType = USB_DT_DEVICE, - .bcdUSB = 0x0200, - .bDeviceClass = 0, - .bDeviceSubClass = 0, - .bDeviceProtocol = 0, - .bMaxPacketSize0 = 64, - .idVendor = 0x0483, - .idProduct = 0x5710, - .bcdDevice = 0x0200, - .iManufacturer = 1, - .iProduct = 2, - .iSerialNumber = 3, - .bNumConfigurations = 1, -}; - -/* I have no idea what this means. I haven't read the HID spec. */ -static const u8 hid_report_descriptor[] = { - 0x05, 0x01, 0x09, 0x02, 0xA1, 0x01, 0x09, 0x01, - 0xA1, 0x00, 0x05, 0x09, 0x19, 0x01, 0x29, 0x03, - 0x15, 0x00, 0x25, 0x01, 0x95, 0x03, 0x75, 0x01, - 0x81, 0x02, 0x95, 0x01, 0x75, 0x05, 0x81, 0x01, - 0x05, 0x01, 0x09, 0x30, 0x09, 0x31, 0x09, 0x38, - 0x15, 0x81, 0x25, 0x7F, 0x75, 0x08, 0x95, 0x03, - 0x81, 0x06, 0xC0, 0x09, 0x3c, 0x05, 0xff, 0x09, - 0x01, 0x15, 0x00, 0x25, 0x01, 0x75, 0x01, 0x95, - 0x02, 0xb1, 0x22, 0x75, 0x06, 0x95, 0x01, 0xb1, - 0x01, 0xc0 -}; - -static const struct { - struct usb_hid_descriptor hid_descriptor; - struct { - u8 bReportDescriptorType; - u16 wDescriptorLength; - } __attribute__((packed)) hid_report; -} __attribute__((packed)) hid_function = { - .hid_descriptor = { - .bLength = sizeof(hid_function), - .bDescriptorType = USB_DT_HID, - .bcdHID = 0x0100, - .bCountryCode = 0, - .bNumDescriptors = 1, - }, - .hid_report = { - .bReportDescriptorType = USB_DT_REPORT, - .wDescriptorLength = sizeof(hid_report_descriptor), - } -}; - -const struct usb_endpoint_descriptor hid_endpoint = { - .bLength = USB_DT_ENDPOINT_SIZE, - .bDescriptorType = USB_DT_ENDPOINT, - .bEndpointAddress = 0x81, - .bmAttributes = USB_ENDPOINT_ATTR_INTERRUPT, - .wMaxPacketSize = 4, - .bInterval = 0x20, -}; - -const struct usb_interface_descriptor hid_iface = { - .bLength = USB_DT_INTERFACE_SIZE, - .bDescriptorType = USB_DT_INTERFACE, - .bInterfaceNumber = 0, - .bAlternateSetting = 0, - .bNumEndpoints = 1, - .bInterfaceClass = USB_CLASS_HID, - .bInterfaceSubClass = 1, /* boot */ - .bInterfaceProtocol = 2, /* mouse */ - .iInterface = 0, - - .endpoint = &hid_endpoint, - - .extra = &hid_function, - .extralen = sizeof(hid_function), -}; - -#ifdef INCLUDE_DFU_INTERFACE -const struct usb_dfu_descriptor dfu_function = { - .bLength = sizeof(struct usb_dfu_descriptor), - .bDescriptorType = DFU_FUNCTIONAL, - .bmAttributes = USB_DFU_CAN_DOWNLOAD | USB_DFU_WILL_DETACH, - .wDetachTimeout = 255, - .wTransferSize = 1024, - .bcdDFUVersion = 0x011A, -}; - -const struct usb_interface_descriptor dfu_iface = { - .bLength = USB_DT_INTERFACE_SIZE, - .bDescriptorType = USB_DT_INTERFACE, - .bInterfaceNumber = 1, - .bAlternateSetting = 0, - .bNumEndpoints = 0, - .bInterfaceClass = 0xFE, - .bInterfaceSubClass = 1, - .bInterfaceProtocol = 1, - .iInterface = 0, - - .extra = &dfu_function, - .extralen = sizeof(dfu_function), -}; -#endif - -const struct usb_interface ifaces[] = {{ - .num_altsetting = 1, - .altsetting = &hid_iface, -#ifdef INCLUDE_DFU_INTERFACE -}, { - .num_altsetting = 1, - .altsetting = &dfu_iface, -#endif -}}; - -const struct usb_config_descriptor config = { - .bLength = USB_DT_CONFIGURATION_SIZE, - .bDescriptorType = USB_DT_CONFIGURATION, - .wTotalLength = 0, -#ifdef INCLUDE_DFU_INTERFACE - .bNumInterfaces = 2, -#else - .bNumInterfaces = 1, -#endif - .bConfigurationValue = 1, - .iConfiguration = 0, - .bmAttributes = 0xC0, - .bMaxPower = 0x32, - - .interface = ifaces, -}; - -static const char *usb_strings[] = { - "x", - "Black Sphere Technologies", - "HID Demo", - "DEMO", -}; - -static int hid_control_request(struct usb_setup_data *req, u8 **buf, u16 *len, - void (**complete)(struct usb_setup_data *req)) -{ - (void)complete; - - if((req->bmRequestType != 0x81) || - (req->bRequest != USB_REQ_GET_DESCRIPTOR) || - (req->wValue != 0x2200)) - return 0; - - /* Handle the HID report descriptor */ - *buf = (u8*)hid_report_descriptor; - *len = sizeof(hid_report_descriptor); - - return 1; -} - -#ifdef INCLUDE_DFU_INTERFACE -static void dfu_detach_complete(struct usb_setup_data *req) -{ - (void)req; - - gpio_set_mode(GPIOA, GPIO_MODE_INPUT, 0, GPIO15); - gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_2_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO10); - gpio_set(GPIOA, GPIO10); - scb_reset_core(); -} - -static int dfu_control_request(struct usb_setup_data *req, u8 **buf, u16 *len, - void (**complete)(struct usb_setup_data *req)) -{ - (void)buf; - (void)len; - - if((req->bmRequestType != 0x21) || (req->bRequest != DFU_DETACH)) - return 0; /* Only accept class request */ - - *complete = dfu_detach_complete; - - return 1; -} -#endif - -static void hid_set_config(u16 wValue) -{ - (void)wValue; - - usbd_ep_setup(0x81, USB_ENDPOINT_ATTR_INTERRUPT, 4, NULL); - - usbd_register_control_callback( - USB_REQ_TYPE_STANDARD | USB_REQ_TYPE_INTERFACE, - USB_REQ_TYPE_TYPE | USB_REQ_TYPE_RECIPIENT, - hid_control_request); -#ifdef INCLUDE_DFU_INTERFACE - usbd_register_control_callback( - USB_REQ_TYPE_CLASS | USB_REQ_TYPE_INTERFACE, - USB_REQ_TYPE_TYPE | USB_REQ_TYPE_RECIPIENT, - dfu_control_request); -#endif - - systick_set_clocksource(STK_CTRL_CLKSOURCE_AHB_DIV8); - systick_set_reload(100000); - systick_interrupt_enable(); - systick_counter_enable(); -} - -int main(void) -{ - rcc_clock_setup_in_hsi_out_48mhz(); - - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_AFIOEN); - - AFIO_MAPR |= AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_ON; - gpio_set_mode(GPIOA, GPIO_MODE_INPUT, 0, GPIO15); - - usbd_init(&stm32f103_usb_driver, &dev, &config, usb_strings); - usbd_register_set_config_callback(hid_set_config); - - gpio_set(GPIOA, GPIO15); - gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_2_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO15); - - while (1) - usbd_poll(); -} - -void sys_tick_handler(void) -{ - static int x = 0; - static int dir = 1; - u8 buf[4] = {0, 0, 0, 0}; - - buf[1] = dir; - x += dir; - if(x > 30) dir = -dir; - if(x < -30) dir = -dir; - - usbd_ep_write_packet(0x81, buf, 4); -} diff --git a/examples/stm32/other/usb_hid/usbhid.ld b/examples/stm32/other/usb_hid/usbhid.ld deleted file mode 100644 index 1c20282..0000000 --- a/examples/stm32/other/usb_hid/usbhid.ld +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* Define memory regions. */ -MEMORY -{ - rom (rx) : ORIGIN = 0x08000000, LENGTH = 64K - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K -} - -/* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld - diff --git a/examples/stm32/stm32-discovery/button/Makefile b/examples/stm32/stm32-discovery/button/Makefile deleted file mode 100644 index 96731c2..0000000 --- a/examples/stm32/stm32-discovery/button/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2009 Uwe Hermann -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program. If not, see . -## - -BINARY = button - -include ../../Makefile.include - diff --git a/examples/stm32/stm32-discovery/button/README b/examples/stm32/stm32-discovery/button/README deleted file mode 100644 index 38bc1ea..0000000 --- a/examples/stm32/stm32-discovery/button/README +++ /dev/null @@ -1,8 +0,0 @@ ------------------------------------------------------------------------------- -README ------------------------------------------------------------------------------- - -This example blinks the green LED on the ST STM32VLDISCOVERY eval board. - -When you press the 'USER' button, the blinking is slower. - diff --git a/examples/stm32/stm32-discovery/button/button.c b/examples/stm32/stm32-discovery/button/button.c deleted file mode 100644 index b84f074..0000000 --- a/examples/stm32/stm32-discovery/button/button.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann , - * Copyright (C) 2010 Piotr Esden-Tempski - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include - -u16 exti_line_state; - -/* Set STM32 to 24 MHz. */ -void clock_setup(void) -{ - rcc_clock_setup_in_hse_8mhz_out_24mhz(); -} - -void gpio_setup(void) -{ - /* Enable GPIOC clock. */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); - - /* Set GPIO9 (in GPIO port C) to 'output push-pull'. */ - gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO9); -} - -void button_setup(void) -{ - /* Enable GPIOA clock. */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); - - /* Set GPIO0 (in GPIO port A) to 'input open-drain'. */ - gpio_set_mode(GPIOA, GPIO_MODE_INPUT, - GPIO_CNF_INPUT_FLOAT, GPIO0); -} - -int main(void) -{ - int i; - - clock_setup(); - gpio_setup(); - button_setup(); - - /* Blink the LED (PC9) on the board. */ - while (1) { - gpio_toggle(GPIOC, GPIO9); - - /* Upon button press, blink more slowly. */ - exti_line_state = GPIOA_IDR; - if ((exti_line_state & (1 << 0)) != 0) { - for (i = 0; i < 800000; i++) /* Wait a bit. */ - __asm__("nop"); - } - - for (i = 0; i < 800000; i++) /* Wait a bit. */ - __asm__("nop"); - } - - return 0; -} diff --git a/examples/stm32/stm32-discovery/button/button.ld b/examples/stm32/stm32-discovery/button/button.ld deleted file mode 100644 index b03f90f..0000000 --- a/examples/stm32/stm32-discovery/button/button.ld +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* Linker script for ST STM32VLDISCOVERY (STM32F100RB, 128K flash, 8K RAM). */ - -/* Define memory regions. */ -MEMORY -{ - rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 8K -} - -/* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld - diff --git a/examples/stm32/stm32-discovery/fancyblink/Makefile b/examples/stm32/stm32-discovery/fancyblink/Makefile deleted file mode 100644 index 1baec4d..0000000 --- a/examples/stm32/stm32-discovery/fancyblink/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2009 Uwe Hermann -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program. If not, see . -## - -BINARY = fancyblink - -include ../../Makefile.include - diff --git a/examples/stm32/stm32-discovery/fancyblink/README b/examples/stm32/stm32-discovery/fancyblink/README deleted file mode 100644 index b5d794c..0000000 --- a/examples/stm32/stm32-discovery/fancyblink/README +++ /dev/null @@ -1,9 +0,0 @@ ------------------------------------------------------------------------------- -README ------------------------------------------------------------------------------- - -This is the smallest-possible example program using libopencm3. - -It's intended for the ST STM32VLDISCOVERY eval board. It should blink -the LEDs on the board. - diff --git a/examples/stm32/stm32-discovery/fancyblink/fancyblink.c b/examples/stm32/stm32-discovery/fancyblink/fancyblink.c deleted file mode 100644 index d40fb7b..0000000 --- a/examples/stm32/stm32-discovery/fancyblink/fancyblink.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * Copyright (C) 2011 Damjan Marion - * Copyright (C) 2011 Mark Panajotovic - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include - -/* Set STM32 to 24 MHz. */ -void clock_setup(void) -{ - rcc_clock_setup_in_hse_8mhz_out_24mhz(); - - /* Enable GPIOC clock. */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); -} - -void gpio_setup(void) -{ - /* Set GPIO8/9 (in GPIO port C) to 'output push-pull'. */ - gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO8); - gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO9); -} - -int main(void) -{ - int i; - - clock_setup(); - gpio_setup(); - - /* Set one LED for wigwag effect when toggling. */ - gpio_set(GPIOC, GPIO8); - - /* Blink the LEDs (PC8 and PC9) on the board. */ - while (1) { - gpio_toggle(GPIOC, GPIO8 | GPIO9); /* Toggle LEDs. */ - for (i = 0; i < 2000000; i++) /* Wait a bit. */ - __asm__("nop"); - } - - return 0; -} diff --git a/examples/stm32/stm32-discovery/fancyblink/fancyblink.ld b/examples/stm32/stm32-discovery/fancyblink/fancyblink.ld deleted file mode 100644 index b03f90f..0000000 --- a/examples/stm32/stm32-discovery/fancyblink/fancyblink.ld +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* Linker script for ST STM32VLDISCOVERY (STM32F100RB, 128K flash, 8K RAM). */ - -/* Define memory regions. */ -MEMORY -{ - rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 8K -} - -/* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld - diff --git a/examples/stm32/stm32-discovery/miniblink/Makefile b/examples/stm32/stm32-discovery/miniblink/Makefile deleted file mode 100644 index 24a478b..0000000 --- a/examples/stm32/stm32-discovery/miniblink/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2009 Uwe Hermann -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program. If not, see . -## - -BINARY = miniblink - -include ../../Makefile.include - diff --git a/examples/stm32/stm32-discovery/miniblink/README b/examples/stm32/stm32-discovery/miniblink/README deleted file mode 100644 index cffce60..0000000 --- a/examples/stm32/stm32-discovery/miniblink/README +++ /dev/null @@ -1,9 +0,0 @@ ------------------------------------------------------------------------------- -README ------------------------------------------------------------------------------- - -This is the smallest-possible example program using libopencm3. - -It's intended for the ST STM32VLDISCOVERY eval board. It should blink -the blue LED on the board. - diff --git a/examples/stm32/stm32-discovery/miniblink/miniblink.c b/examples/stm32/stm32-discovery/miniblink/miniblink.c deleted file mode 100644 index a05f957..0000000 --- a/examples/stm32/stm32-discovery/miniblink/miniblink.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include - -void gpio_setup(void) -{ - /* Enable GPIOC clock. */ - /* Manually: */ - // RCC_APB2ENR |= RCC_APB2ENR_IOPCEN; - /* Using API functions: */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); - - /* Set GPIO8 (in GPIO port C) to 'output push-pull'. */ - /* Manually: */ - // GPIOC_CRH = (GPIO_CNF_OUTPUT_PUSHPULL << (((8 - 8) * 4) + 2)); - // GPIOC_CRH |= (GPIO_MODE_OUTPUT_2_MHZ << ((8 - 8) * 4)); - /* Using API functions: */ - gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_2_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO8); -} - -int main(void) -{ - int i; - - gpio_setup(); - - /* Blink the LED (PC8) on the board. */ - while (1) { - /* Manually: */ - // GPIOC_BSRR = GPIO8; /* LED off */ - // for (i = 0; i < 800000; i++) /* Wait a bit. */ - // __asm__("nop"); - // GPIOC_BRR = GPIO8; /* LED on */ - // for (i = 0; i < 800000; i++) /* Wait a bit. */ - // __asm__("nop"); - - /* Using API functions gpio_set()/gpio_clear(): */ - // gpio_set(GPIOC, GPIO8); /* LED off */ - // for (i = 0; i < 800000; i++) /* Wait a bit. */ - // __asm__("nop"); - // gpio_clear(GPIOC, GPIO8); /* LED on */ - // for (i = 0; i < 800000; i++) /* Wait a bit. */ - // __asm__("nop"); - - /* Using API function gpio_toggle(): */ - gpio_toggle(GPIOC, GPIO8); /* LED on/off */ - for (i = 0; i < 800000; i++) /* Wait a bit. */ - __asm__("nop"); - } - - return 0; -} diff --git a/examples/stm32/stm32-discovery/miniblink/miniblink.ld b/examples/stm32/stm32-discovery/miniblink/miniblink.ld deleted file mode 100644 index b03f90f..0000000 --- a/examples/stm32/stm32-discovery/miniblink/miniblink.ld +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* Linker script for ST STM32VLDISCOVERY (STM32F100RB, 128K flash, 8K RAM). */ - -/* Define memory regions. */ -MEMORY -{ - rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 8K -} - -/* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld - diff --git a/examples/stm32/stm32-discovery/rtc/Makefile b/examples/stm32/stm32-discovery/rtc/Makefile deleted file mode 100644 index 1efa7ac..0000000 --- a/examples/stm32/stm32-discovery/rtc/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2009 Uwe Hermann -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program. If not, see . -## - -BINARY = rtc - -include ../../Makefile.include - diff --git a/examples/stm32/stm32-discovery/rtc/README b/examples/stm32/stm32-discovery/rtc/README deleted file mode 100644 index d4509e4..0000000 --- a/examples/stm32/stm32-discovery/rtc/README +++ /dev/null @@ -1,9 +0,0 @@ ------------------------------------------------------------------------------- -README ------------------------------------------------------------------------------- - -This is a small RTC example project. - -It blinks the ST STM32VLDISCOVERY's blue LED at 1Hz, and sends the value of -the RTC counter register down the serial line (PA9) at 38400,8N1. - diff --git a/examples/stm32/stm32-discovery/rtc/rtc.c b/examples/stm32/stm32-discovery/rtc/rtc.c deleted file mode 100644 index c99920f..0000000 --- a/examples/stm32/stm32-discovery/rtc/rtc.c +++ /dev/null @@ -1,129 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Lord James - * Copyright (C) 2011 Mark Panajotovic - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include -#include -#include -#include - -void clock_setup(void) -{ - rcc_clock_setup_in_hse_8mhz_out_24mhz(); - - /* Enable GPIOC clock. */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); - - /* Enable clocks for GPIO port A (for GPIO_USART1_TX) and USART1. */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_USART1EN); -} - -void usart_setup(void) -{ - /* Setup GPIO pin GPIO_USART1_TX/GPIO9 on GPIO port A for transmit. */ - gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_USART1_TX); - - /* Setup UART parameters. */ - // usart_set_baudrate(USART1, 38400); - /* TODO usart_set_baudrate() doesn't support 24MHz clock (yet). */ - /* This is the equivalent: */ - USART_BRR(USART1) = (u16)((24000000 << 4) / (38400 * 16)); - - usart_set_databits(USART1, 8); - usart_set_stopbits(USART1, USART_STOPBITS_1); - usart_set_mode(USART1, USART_MODE_TX); - usart_set_parity(USART1, USART_PARITY_NONE); - usart_set_flow_control(USART1, USART_FLOWCONTROL_NONE); - - /* Finally enable the USART. */ - usart_enable(USART1); -} - -void gpio_setup(void) -{ - /* Set GPIO8 (in GPIO port C) to 'output push-pull'. */ - /* This drives the blue LED on the STM32VLDISCOVERY. */ - gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_2_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO8); -} - -void nvic_setup(void) -{ - /* Without this the RTC interrupt routine will never be called. */ - nvic_enable_irq(NVIC_RTC_IRQ); - nvic_set_priority(NVIC_RTC_IRQ, 1); -} - -void rtc_isr(void) -{ - volatile u32 j = 0, c = 0; - - /* The interrupt flag isn't cleared by hardware, we have to do it. */ - rtc_clear_flag(RTC_SEC); - - /* Visual output. */ - gpio_toggle(GPIOC, GPIO8); - - c = rtc_get_counter_val(); - - /* Display the current counter value in binary via USART1. */ - for (j = 0; j < 32; j++) { - if ((c & (0x80000000 >> j)) != 0) - usart_send_blocking(USART1, '1'); - else - usart_send_blocking(USART1, '0'); - } - usart_send_blocking(USART1, '\n'); - usart_send_blocking(USART1, '\r'); -} - -int main(void) -{ - clock_setup(); - gpio_setup(); - usart_setup(); - - /* - * If the RTC is pre-configured just allow access, don't reconfigure. - * Otherwise enable it with the LSE as clock source and 0x7fff as - * prescale value. - */ - rtc_auto_awake(LSE, 0x7fff); - - /* The above mode will not reset the RTC when you press the RST button. - * It will also continue to count while the MCU is held in reset. If - * you want it to reset, comment out the above and use the following: - */ - // rtc_awake_from_off(LSE); - // rtc_set_prescale_val(0x7fff); - - /* Setup the RTC interrupt. */ - nvic_setup(); - - /* Enable the RTC interrupt to occur off the SEC flag. */ - rtc_interrupt_enable(RTC_SEC); - - while(1); - - return 0; -} diff --git a/examples/stm32/stm32-discovery/rtc/rtc.ld b/examples/stm32/stm32-discovery/rtc/rtc.ld deleted file mode 100644 index b03f90f..0000000 --- a/examples/stm32/stm32-discovery/rtc/rtc.ld +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* Linker script for ST STM32VLDISCOVERY (STM32F100RB, 128K flash, 8K RAM). */ - -/* Define memory regions. */ -MEMORY -{ - rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 8K -} - -/* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld - diff --git a/examples/stm32/stm32-discovery/usart/Makefile b/examples/stm32/stm32-discovery/usart/Makefile deleted file mode 100644 index 2c1e1b1..0000000 --- a/examples/stm32/stm32-discovery/usart/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2009 Uwe Hermann -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program. If not, see . -## - -BINARY = usart - -include ../../Makefile.include - diff --git a/examples/stm32/stm32-discovery/usart/README b/examples/stm32/stm32-discovery/usart/README deleted file mode 100644 index 6d09139..0000000 --- a/examples/stm32/stm32-discovery/usart/README +++ /dev/null @@ -1,12 +0,0 @@ ------------------------------------------------------------------------------- -README ------------------------------------------------------------------------------- - -This example program sends some characters on USART1 on the -ST STM32VLDISCOVERY eval board. - -The terminal settings for the receiving device/PC are 38400 8n1. - -The sending is done in a blocking way in the code, see the usart_irq example -for a more elaborate USART example. - diff --git a/examples/stm32/stm32-discovery/usart/usart.c b/examples/stm32/stm32-discovery/usart/usart.c deleted file mode 100644 index 05d0312..0000000 --- a/examples/stm32/stm32-discovery/usart/usart.c +++ /dev/null @@ -1,87 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include - -void clock_setup(void) -{ - rcc_clock_setup_in_hse_8mhz_out_24mhz(); - - /* Enable GPIOC clock. */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); - - /* Enable clocks for GPIO port A (for GPIO_USART1_TX) and USART1. */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_USART1EN); -} - -void usart_setup(void) -{ - /* Setup GPIO pin GPIO_USART1_TX/GPIO9 on GPIO port A for transmit. */ - gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_USART1_TX); - - /* Setup UART parameters. */ - // usart_set_baudrate(USART1, 38400); - /* TODO usart_set_baudrate() doesn't support 24MHz clock (yet). */ - /* This is the equivalent: */ - USART_BRR(USART1) = (u16)((24000000 << 4) / (38400 * 16)); - - usart_set_databits(USART1, 8); - usart_set_stopbits(USART1, USART_STOPBITS_1); - usart_set_mode(USART1, USART_MODE_TX); - usart_set_parity(USART1, USART_PARITY_NONE); - usart_set_flow_control(USART1, USART_FLOWCONTROL_NONE); - - /* Finally enable the USART. */ - usart_enable(USART1); -} - -void gpio_setup(void) -{ - /* Set GPIO9 (in GPIO port C) to 'output push-pull'. [LED] */ - gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_2_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO9); -} - -int main(void) -{ - int i, j = 0, c = 0; - - clock_setup(); - gpio_setup(); - usart_setup(); - - /* Blink the LED (PC9) on the board with every transmitted byte. */ - while (1) { - gpio_toggle(GPIOC, GPIO9); /* LED on/off */ - usart_send_blocking(USART1, c + '0'); /* USART1: Send byte. */ - c = (c == 9) ? 0 : c + 1; /* Increment c. */ - if ((j++ % 80) == 0) { /* Newline after line full. */ - usart_send_blocking(USART1, '\r'); - usart_send_blocking(USART1, '\n'); - } - for (i = 0; i < 800000; i++) /* Wait a bit. */ - __asm__("NOP"); - } - - return 0; -} diff --git a/examples/stm32/stm32-discovery/usart/usart.ld b/examples/stm32/stm32-discovery/usart/usart.ld deleted file mode 100644 index b03f90f..0000000 --- a/examples/stm32/stm32-discovery/usart/usart.ld +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* Linker script for ST STM32VLDISCOVERY (STM32F100RB, 128K flash, 8K RAM). */ - -/* Define memory regions. */ -MEMORY -{ - rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 8K -} - -/* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld - diff --git a/examples/stm32/stm32-h103/button/Makefile b/examples/stm32/stm32-h103/button/Makefile deleted file mode 100644 index 96731c2..0000000 --- a/examples/stm32/stm32-h103/button/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2009 Uwe Hermann -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program. If not, see . -## - -BINARY = button - -include ../../Makefile.include - diff --git a/examples/stm32/stm32-h103/button/button.c b/examples/stm32/stm32-h103/button/button.c deleted file mode 100644 index 63f3274..0000000 --- a/examples/stm32/stm32-h103/button/button.c +++ /dev/null @@ -1,79 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann , - * 2010 Piotr Esden-Tempski - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include -#include - -u16 exti_line_state; - -/* Set STM32 to 72 MHz. */ -void clock_setup(void) -{ - rcc_clock_setup_in_hse_8mhz_out_72mhz(); - -} - -void gpio_setup(void) -{ - /* Enable GPIOC clock. */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); - - /* Set GPIO12 (in GPIO port C) to 'output push-pull'. */ - gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO12); -} - -void button_setup(void) -{ - /* Enable GPIOA clock. */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); - - /* Set GPIO0 (in GPIO port A) to 'input open-drain'. */ - gpio_set_mode(GPIOA, GPIO_MODE_INPUT, - GPIO_CNF_INPUT_FLOAT, GPIO0); - -} - -int main(void) -{ - int i; - - clock_setup(); - gpio_setup(); - button_setup(); - - /* Blink the LED (PC12) on the board. */ - while (1) { - gpio_toggle(GPIOC, GPIO12); - - exti_line_state = GPIOA_IDR; - if ((exti_line_state & (1 << 0)) != 0) { - for (i = 0; i < 800000; i++) /* Wait a bit. */ - __asm__("nop"); - } - - for (i = 0; i < 800000; i++) /* Wait a bit. */ - __asm__("nop"); - } - - return 0; -} diff --git a/examples/stm32/stm32-h103/button/button.ld b/examples/stm32/stm32-h103/button/button.ld deleted file mode 100644 index 7ea2b92..0000000 --- a/examples/stm32/stm32-h103/button/button.ld +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* Linker script for Olimex STM32-H103 (STM32F103RBT6, 128K flash, 20K RAM). */ - -/* Define memory regions. */ -MEMORY -{ - rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K -} - -/* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld - diff --git a/examples/stm32/stm32-h103/exti_both/Makefile b/examples/stm32/stm32-h103/exti_both/Makefile deleted file mode 100644 index 39e305b..0000000 --- a/examples/stm32/stm32-h103/exti_both/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2009 Uwe Hermann -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program. If not, see . -## - -BINARY = exti_both - -include ../../Makefile.include - diff --git a/examples/stm32/stm32-h103/exti_both/exti_both.c b/examples/stm32/stm32-h103/exti_both/exti_both.c deleted file mode 100644 index edfc676..0000000 --- a/examples/stm32/stm32-h103/exti_both/exti_both.c +++ /dev/null @@ -1,92 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann , - * 2010 Piotr Esden-Tempski - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include -#include - -u16 exti_line_state; - -/* Set STM32 to 72 MHz. */ -void clock_setup(void) -{ - rcc_clock_setup_in_hse_8mhz_out_72mhz(); - -} - -void gpio_setup(void) -{ - /* Enable GPIOC clock. */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); - - /* Set GPIO12 (in GPIO port C) to 'output push-pull'. */ - gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO12); -} - -void exti_setup(void) -{ - /* Enable GPIOA clock. */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); - - /* Enable AFIO clock. */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_AFIOEN); - - /* Enable EXTI0 interrupt */ - nvic_enable_irq(NVIC_EXTI0_IRQ); - - /* Set GPIO0 (in GPIO port A) to 'input float'. */ - gpio_set_mode(GPIOA, GPIO_MODE_INPUT, - GPIO_CNF_INPUT_FLOAT, GPIO0); - - /* configure EXTI subsystem */ - exti_select_source(EXTI0, GPIOA); - exti_set_trigger(EXTI0, EXTI_TRIGGER_BOTH); - exti_enable_request(EXTI0); -} - -void exti0_isr() -{ - exti_line_state = GPIOA_IDR; - - if ((exti_line_state & (1 << 0)) != 0) { - gpio_clear(GPIOC, GPIO12); - } else { - gpio_set(GPIOC, GPIO12); - } - - exti_reset_request(EXTI0); -} - -int main(void) -{ - - clock_setup(); - gpio_setup(); - exti_setup(); - - /* Blink the LED (PC12) on the board. */ - while (1) { - __asm("nop"); - } - - return 0; -} diff --git a/examples/stm32/stm32-h103/exti_both/exti_both.ld b/examples/stm32/stm32-h103/exti_both/exti_both.ld deleted file mode 100644 index 7ea2b92..0000000 --- a/examples/stm32/stm32-h103/exti_both/exti_both.ld +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* Linker script for Olimex STM32-H103 (STM32F103RBT6, 128K flash, 20K RAM). */ - -/* Define memory regions. */ -MEMORY -{ - rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K -} - -/* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld - diff --git a/examples/stm32/stm32-h103/exti_rising_falling/Makefile b/examples/stm32/stm32-h103/exti_rising_falling/Makefile deleted file mode 100644 index fc603a6..0000000 --- a/examples/stm32/stm32-h103/exti_rising_falling/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2009 Uwe Hermann -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program. If not, see . -## - -BINARY = exti_rising_falling - -include ../../Makefile.include - diff --git a/examples/stm32/stm32-h103/exti_rising_falling/exti_rising_falling.c b/examples/stm32/stm32-h103/exti_rising_falling/exti_rising_falling.c deleted file mode 100644 index af1268d..0000000 --- a/examples/stm32/stm32-h103/exti_rising_falling/exti_rising_falling.c +++ /dev/null @@ -1,98 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann , - * 2010 Piotr Esden-Tempski - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include -#include - -#define FALLING 0 -#define RISING 1 - -u16 exti_direction = FALLING; - -/* Set STM32 to 72 MHz. */ -void clock_setup(void) -{ - rcc_clock_setup_in_hse_8mhz_out_72mhz(); - -} - -void gpio_setup(void) -{ - /* Enable GPIOC clock. */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); - - /* Set GPIO12 (in GPIO port C) to 'output push-pull'. */ - gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO12); -} - -void exti_setup(void) -{ - /* Enable GPIOA clock. */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); - - /* Enable AFIO clock. */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_AFIOEN); - - /* Enable EXTI0 interrupt */ - nvic_enable_irq(NVIC_EXTI0_IRQ); - - /* Set GPIO0 (in GPIO port A) to 'input open-drain'. */ - gpio_set_mode(GPIOA, GPIO_MODE_INPUT, - GPIO_CNF_INPUT_FLOAT, GPIO0); - - /* configure EXTI subsystem */ - exti_select_source(EXTI0, GPIOA); - exti_direction = FALLING; - exti_set_trigger(EXTI0, EXTI_TRIGGER_FALLING); - exti_enable_request(EXTI0); -} - -void exti0_isr() -{ - exti_reset_request(EXTI0); - - if (exti_direction == FALLING) { - gpio_set(GPIOC, GPIO12); - exti_direction = RISING; - exti_set_trigger(EXTI0, EXTI_TRIGGER_RISING); - } else { - gpio_clear(GPIOC, GPIO12); - exti_direction = FALLING; - exti_set_trigger(EXTI0, EXTI_TRIGGER_FALLING); - } -} - -int main(void) -{ - - clock_setup(); - gpio_setup(); - exti_setup(); - - /* Blink the LED (PC12) on the board. */ - while (1) { - __asm("nop"); - } - - return 0; -} diff --git a/examples/stm32/stm32-h103/exti_rising_falling/exti_rising_falling.ld b/examples/stm32/stm32-h103/exti_rising_falling/exti_rising_falling.ld deleted file mode 100644 index 7ea2b92..0000000 --- a/examples/stm32/stm32-h103/exti_rising_falling/exti_rising_falling.ld +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* Linker script for Olimex STM32-H103 (STM32F103RBT6, 128K flash, 20K RAM). */ - -/* Define memory regions. */ -MEMORY -{ - rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K -} - -/* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld - diff --git a/examples/stm32/stm32-h103/fancyblink/Makefile b/examples/stm32/stm32-h103/fancyblink/Makefile deleted file mode 100644 index 1baec4d..0000000 --- a/examples/stm32/stm32-h103/fancyblink/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2009 Uwe Hermann -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program. If not, see . -## - -BINARY = fancyblink - -include ../../Makefile.include - diff --git a/examples/stm32/stm32-h103/fancyblink/README b/examples/stm32/stm32-h103/fancyblink/README deleted file mode 100644 index bdb6ec8..0000000 --- a/examples/stm32/stm32-h103/fancyblink/README +++ /dev/null @@ -1,10 +0,0 @@ ------------------------------------------------------------------------------- -README ------------------------------------------------------------------------------- - -This is small LED blinking example program using libopencm3. - -It's intended for the ST STM32-based Olimex STM32-H103 eval board (see -http://olimex.com/dev/stm32-h103.html for details). It should blink -the LED on the board. - diff --git a/examples/stm32/stm32-h103/fancyblink/fancyblink.c b/examples/stm32/stm32-h103/fancyblink/fancyblink.c deleted file mode 100644 index eeb3f34..0000000 --- a/examples/stm32/stm32-h103/fancyblink/fancyblink.c +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include - -/* Set STM32 to 72 MHz. */ -void clock_setup(void) -{ - rcc_clock_setup_in_hse_8mhz_out_72mhz(); - - /* Enable GPIOC clock. */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); - -} - -void gpio_setup(void) -{ - /* Set GPIO12 (in GPIO port C) to 'output push-pull'. */ - gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO12); -} - -int main(void) -{ - int i; - - clock_setup(); - gpio_setup(); - - /* Blink the LED (PC12) on the board. */ - while (1) { - gpio_toggle(GPIOC, GPIO12); /* LED on/off */ - for (i = 0; i < 800000; i++) /* Wait a bit. */ - __asm__("nop"); - } - - return 0; -} diff --git a/examples/stm32/stm32-h103/fancyblink/fancyblink.ld b/examples/stm32/stm32-h103/fancyblink/fancyblink.ld deleted file mode 100644 index 7ea2b92..0000000 --- a/examples/stm32/stm32-h103/fancyblink/fancyblink.ld +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* Linker script for Olimex STM32-H103 (STM32F103RBT6, 128K flash, 20K RAM). */ - -/* Define memory regions. */ -MEMORY -{ - rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K -} - -/* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld - diff --git a/examples/stm32/stm32-h103/led_stripe/Makefile b/examples/stm32/stm32-h103/led_stripe/Makefile deleted file mode 100644 index 60fd1ef..0000000 --- a/examples/stm32/stm32-h103/led_stripe/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2009 Uwe Hermann -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program. If not, see . -## - -BINARY = led_stripe - -include ../../Makefile.include - diff --git a/examples/stm32/stm32-h103/led_stripe/led_stripe.c b/examples/stm32/stm32-h103/led_stripe/led_stripe.c deleted file mode 100644 index 9cf9d4f..0000000 --- a/examples/stm32/stm32-h103/led_stripe/led_stripe.c +++ /dev/null @@ -1,234 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Piotr Esden-Tempski - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* - * This example is implementing the protocol of ZJ168 addressable led - * strips. These strips use the LPD6803 controller. You may be able to - * find the datasheet here: - * http://www.adafruit.com/datasheets/LPD6803.pdf - */ - -#include - -#include -#include - -#define SPI_BANK GPIOB -#define SCLK_PIN GPIO13 -#define MOSI_PIN GPIO15 - -#define SMALL_DELAY_VALUE 0 - -#define COLOR_COUNT 50 - -#define SCLK(VAL) \ - if (VAL) { \ - gpio_set(SPI_BANK, SCLK_PIN); \ - } else { \ - gpio_clear(SPI_BANK, SCLK_PIN); \ - } - -#define MOSI(VAL) \ - if (VAL) { \ - gpio_set(SPI_BANK, MOSI_PIN); \ - } else { \ - gpio_clear(SPI_BANK, MOSI_PIN); \ - } - -#define SMALL_DELAY() { \ - int j; \ - for (j = 0; j < SMALL_DELAY_VALUE; j++) \ - __asm__("nop"); \ - } - -struct color { - u8 r; - u8 g; - u8 b; -}; - -/* Set STM32 to 72 MHz. */ -void clock_setup(void) -{ - rcc_clock_setup_in_hse_8mhz_out_72mhz(); - - /* Enable GPIOC clock. */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPBEN); - -} - -void gpio_setup(void) -{ - /* Set GPIO12 (in GPIO port C) to 'output push-pull'. */ - gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO12); - gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO13); - gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO15); -} - -void send_colors(struct color *colors, int count) { - int i, k; - - /* initialize spi pins */ - SCLK(0); - MOSI(0); - - /* start frame */ - for (i=0; i<32; i++) { - SCLK(1); - SMALL_DELAY(); - SCLK(0); - SMALL_DELAY(); - } - - /* color cell output */ - for (k = 0; k < count; k++) { - /* Start bit */ - MOSI(1); - SCLK(1); - SMALL_DELAY(); - SCLK(0); - SMALL_DELAY(); - - /* Blue */ - for (i=0; i<5; i++) { - MOSI(((colors[k].b & ((1 << 4) >> i)) != 0)); - SCLK(1); - SMALL_DELAY(); - SCLK(0); - SMALL_DELAY(); - } - /* Red */ - for (i=0; i<5; i++) { - MOSI(((colors[k].r & ((1 << 4) >> i)) != 0)); - SCLK(1); - SMALL_DELAY(); - SCLK(0); - SMALL_DELAY(); - } - /* Green */ - for (i=0; i<5; i++) { - MOSI(((colors[k].g & ((1 << 4) >> i)) != 0)); - SCLK(1); - SMALL_DELAY(); - SCLK(0); - SMALL_DELAY(); - } - } - - /* End frame */ - MOSI(0); - for (k=0; k < count; k++) { - SCLK(1); - SMALL_DELAY(); - SCLK(0); - SMALL_DELAY(); - } -} - -void reset_colors(struct color *colors, int count) { - int i; - - for (i=0; i - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* Linker script for Olimex STM32-H103 (STM32F103RBT6, 128K flash, 20K RAM). */ - -/* Define memory regions. */ -MEMORY -{ - rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K -} - -/* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld - diff --git a/examples/stm32/stm32-h103/miniblink/Makefile b/examples/stm32/stm32-h103/miniblink/Makefile deleted file mode 100644 index 24a478b..0000000 --- a/examples/stm32/stm32-h103/miniblink/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2009 Uwe Hermann -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program. If not, see . -## - -BINARY = miniblink - -include ../../Makefile.include - diff --git a/examples/stm32/stm32-h103/miniblink/README b/examples/stm32/stm32-h103/miniblink/README deleted file mode 100644 index 0e046f2..0000000 --- a/examples/stm32/stm32-h103/miniblink/README +++ /dev/null @@ -1,10 +0,0 @@ ------------------------------------------------------------------------------- -README ------------------------------------------------------------------------------- - -This is the smallest-possible example program using libopencm3. - -It's intended for the ST STM32-based Olimex STM32-H103 eval board (see -http://olimex.com/dev/stm32-h103.html for details). It should blink -the LED on the board. - diff --git a/examples/stm32/stm32-h103/miniblink/miniblink.c b/examples/stm32/stm32-h103/miniblink/miniblink.c deleted file mode 100644 index 6f8bc2c..0000000 --- a/examples/stm32/stm32-h103/miniblink/miniblink.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include - -void gpio_setup(void) -{ - /* Enable GPIOC clock. */ - /* Manually: */ - // RCC_APB2ENR |= RCC_APB2ENR_IOPCEN; - /* Using API functions: */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); - - /* Set GPIO12 (in GPIO port C) to 'output push-pull'. */ - /* Manually: */ - // GPIOC_CRH = (GPIO_CNF_OUTPUT_PUSHPULL << (((12 - 8) * 4) + 2)); - // GPIOC_CRH |= (GPIO_MODE_OUTPUT_2_MHZ << ((12 - 8) * 4)); - /* Using API functions: */ - gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_2_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO12); -} - -int main(void) -{ - int i; - - gpio_setup(); - - /* Blink the LED (PC12) on the board. */ - while (1) { - /* Manually: */ - // GPIOC_BSRR = GPIO12; /* LED off */ - // for (i = 0; i < 800000; i++) /* Wait a bit. */ - // __asm__("nop"); - // GPIOC_BRR = GPIO12; /* LED on */ - // for (i = 0; i < 800000; i++) /* Wait a bit. */ - // __asm__("nop"); - - /* Using API functions gpio_set()/gpio_clear(): */ - // gpio_set(GPIOC, GPIO12); /* LED off */ - // for (i = 0; i < 800000; i++) /* Wait a bit. */ - // __asm__("nop"); - // gpio_clear(GPIOC, GPIO12); /* LED on */ - // for (i = 0; i < 800000; i++) /* Wait a bit. */ - // __asm__("nop"); - - /* Using API function gpio_toggle(): */ - gpio_toggle(GPIOC, GPIO12); /* LED on/off */ - for (i = 0; i < 800000; i++) /* Wait a bit. */ - __asm__("nop"); - } - - return 0; -} diff --git a/examples/stm32/stm32-h103/miniblink/miniblink.ld b/examples/stm32/stm32-h103/miniblink/miniblink.ld deleted file mode 100644 index 7ea2b92..0000000 --- a/examples/stm32/stm32-h103/miniblink/miniblink.ld +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* Linker script for Olimex STM32-H103 (STM32F103RBT6, 128K flash, 20K RAM). */ - -/* Define memory regions. */ -MEMORY -{ - rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K -} - -/* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld - diff --git a/examples/stm32/stm32-h103/pwm_6step/Makefile b/examples/stm32/stm32-h103/pwm_6step/Makefile deleted file mode 100644 index 2360082..0000000 --- a/examples/stm32/stm32-h103/pwm_6step/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2009 Uwe Hermann -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program. If not, see . -## - -BINARY = pwm_6step - -include ../../Makefile.include - diff --git a/examples/stm32/stm32-h103/pwm_6step/pwm_6step.c b/examples/stm32/stm32-h103/pwm_6step/pwm_6step.c deleted file mode 100644 index bda8ff7..0000000 --- a/examples/stm32/stm32-h103/pwm_6step/pwm_6step.c +++ /dev/null @@ -1,409 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Piotr Esden-Tempski - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include -#include -#include - -#define FALLING 0 -#define RISING 1 - -u16 exti_direction = FALLING; - -void clock_setup(void) -{ - rcc_clock_setup_in_hse_8mhz_out_72mhz(); - -} - -void gpio_setup(void) -{ - /* Enable GPIOC clock. */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); - - /* - * Set GPIO12 (PORTC) (led) to - * 'output alternate function push-pull'. - */ - gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO12); - -} - -void exti_setup(void) -{ - /* Enable GPIOA clock. */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); - - /* Enable AFIO clock. */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_AFIOEN); - - /* Enable EXTI0 interrupt */ - nvic_enable_irq(NVIC_EXTI0_IRQ); - - /* Set GPIO0 (in GPIO port A) to 'input open-drain'. */ - gpio_set_mode(GPIOA, GPIO_MODE_INPUT, - GPIO_CNF_INPUT_FLOAT, GPIO0); - - /* configure EXTI subsystem */ - exti_select_source(EXTI0, GPIOA); - exti_direction = FALLING; - exti_set_trigger(EXTI0, EXTI_TRIGGER_FALLING); - exti_enable_request(EXTI0); -} - -void exti0_isr() -{ - exti_reset_request(EXTI0); - - if (exti_direction == FALLING) { - //gpio_toggle(GPIOA, GPIO12); - exti_direction = RISING; - exti_set_trigger(EXTI0, EXTI_TRIGGER_RISING); - } else { - //gpio_toggle(GPIOA, GPIO12); - timer_generate_event(TIM1, TIM_EGR_COMG); - exti_direction = FALLING; - exti_set_trigger(EXTI0, EXTI_TRIGGER_FALLING); - } -} - -void tim_setup(void) -{ - - /* Enable TIM1 clock. */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_TIM1EN); - - /* Enable GPIOA, GPIOB and Alternate Function clocks. */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, - RCC_APB2ENR_IOPAEN | - RCC_APB2ENR_IOPBEN | - RCC_APB2ENR_AFIOEN); - - /* - * Set TIM1 chanel output pins to - * 'output alternate function push-pull'. - */ - gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, - GPIO_TIM1_CH1 | - GPIO_TIM1_CH2 | - GPIO_TIM1_CH3); - - /* - * Set TIM1 complementary chanel output pins to - * 'output alternate function push-pull'. - */ - gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, - GPIO_TIM1_CH1N | - GPIO_TIM1_CH2N | - GPIO_TIM1_CH3N); - - /* Enable TIM1 commutation interrupt. */ - nvic_enable_irq(NVIC_TIM1_TRG_COM_IRQ); - - /* Reset TIM1 peripheral */ - timer_reset(TIM1); - - /* Timer global mode: - * - No divider - * - alignment edge - * - direction up - */ - timer_set_mode(TIM1, TIM_CR1_CKD_CK_INT, - TIM_CR1_CMS_EDGE, - TIM_CR1_DIR_UP); - - /* Reset prescaler value. */ - timer_set_prescaler(TIM1, 0); - - /* Reset repetition counter value. */ - timer_set_repetition_counter(TIM1, 0); - - /* Enable preload. */ - timer_enable_preload(TIM1); - - /* Continous mode. */ - timer_continuous_mode(TIM1); - - /* Period (32kHz) */ - timer_set_period(TIM1, 72000000 / 32000); - - /* Configure break and deadtime */ - timer_set_deadtime(TIM1, 10); - timer_set_enabled_off_state_in_idle_mode(TIM1); - timer_set_enabled_off_state_in_run_mode(TIM1); - timer_disable_break(TIM1); - timer_set_break_polarity_high(TIM1); - timer_disable_break_automatic_output(TIM1); - timer_set_break_lock(TIM1, TIM_BDTR_LOCK_OFF); - - /* -- OC1 and OC1N configuration -- */ - - /* Disable outputs. */ - timer_disable_oc_output(TIM1, TIM_OC1); - timer_disable_oc_output(TIM1, TIM_OC1N); - - /* Configure global mode of line 1. */ - timer_disable_oc_clear(TIM1, TIM_OC1); - timer_enable_oc_preload(TIM1, TIM_OC1); - timer_set_oc_slow_mode(TIM1, TIM_OC1); - timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_PWM1); - - /* Configure OC1. */ - timer_set_oc_polarity_high(TIM1, TIM_OC1); - timer_set_oc_idle_state_set(TIM1, TIM_OC1); - - /* Configure OC1N. */ - timer_set_oc_polarity_high(TIM1, TIM_OC1N); - timer_set_oc_idle_state_set(TIM1, TIM_OC1N); - - /* Set the capture compare value for OC1. */ - timer_set_oc_value(TIM1, TIM_OC1, 100); - - /* Reenable outputs. */ - timer_enable_oc_output(TIM1, TIM_OC1); - timer_enable_oc_output(TIM1, TIM_OC1N); - - /* -- OC2 and OC2N configuration -- */ - - /* Disable outputs. */ - timer_disable_oc_output(TIM1, TIM_OC2); - timer_disable_oc_output(TIM1, TIM_OC2N); - - /* Configure global mode of line 2. */ - timer_disable_oc_clear(TIM1, TIM_OC2); - timer_enable_oc_preload(TIM1, TIM_OC2); - timer_set_oc_slow_mode(TIM1, TIM_OC2); - timer_set_oc_mode(TIM1, TIM_OC2, TIM_OCM_PWM1); - - /* Configure OC2. */ - timer_set_oc_polarity_high(TIM1, TIM_OC2); - timer_set_oc_idle_state_set(TIM1, TIM_OC2); - - /* Configure OC2N. */ - timer_set_oc_polarity_high(TIM1, TIM_OC2N); - timer_set_oc_idle_state_set(TIM1, TIM_OC2N); - - /* Set the capture compare value for OC1. */ - timer_set_oc_value(TIM1, TIM_OC2, 100); - - /* Reenable outputs. */ - timer_enable_oc_output(TIM1, TIM_OC2); - timer_enable_oc_output(TIM1, TIM_OC2N); - - /* -- OC3 and OC3N configuration -- */ - - /* Disable outputs. */ - timer_disable_oc_output(TIM1, TIM_OC3); - timer_disable_oc_output(TIM1, TIM_OC3N); - - /* Configure global mode of line 3. */ - timer_disable_oc_clear(TIM1, TIM_OC3); - timer_enable_oc_preload(TIM1, TIM_OC3); - timer_set_oc_slow_mode(TIM1, TIM_OC3); - timer_set_oc_mode(TIM1, TIM_OC3, TIM_OCM_PWM1); - - /* Configure OC3. */ - timer_set_oc_polarity_high(TIM1, TIM_OC3); - timer_set_oc_idle_state_set(TIM1, TIM_OC3); - - /* Configure OC3N. */ - timer_set_oc_polarity_high(TIM1, TIM_OC3N); - timer_set_oc_idle_state_set(TIM1, TIM_OC3N); - - /* Set the capture compare value for OC3. */ - timer_set_oc_value(TIM1, TIM_OC3, 100); - - /* Reenable outputs. */ - timer_enable_oc_output(TIM1, TIM_OC3); - timer_enable_oc_output(TIM1, TIM_OC3N); - - /* ---- */ - /* ARR reload enable */ - timer_enable_preload(TIM1); - - /* Enable preload of complementary channel configurations and update on COM event */ - timer_enable_preload_complementry_enable_bits(TIM1); - - /* Enable outputs in the break subsystem */ - timer_enable_break_main_output(TIM1); - - /* Counter enable */ - timer_enable_counter(TIM1); - - /* Enable commutation interrupt */ - timer_enable_irq(TIM1, TIM_DIER_COMIE); -} - -void tim1_trg_com_isr(void) -{ - static int step = 0; - - /* Clear the COM trigger interrupt flag. */ - timer_clear_flag(TIM1, TIM_SR_COMIF); - - /* A simplified and inefficient implementation of PWM On - * scheme. Look at the implementation in Open-BLDC on - * http://open-bldc.org for the proper implementation. This - * one only serves as an example. - * - * Table of the pwm scheme zone configurations when driving: - * @verbatim - * | 1| 2| 3| 4| 5| 6| - * -+--+--+--+--+--+--+ - * A|p+|++| |p-|--| | - * -+--+--+--+--+--+--+ - * B| |p-|--| |p+|++| - * -+--+--+--+--+--+--+ - * C|--| |p+|++| |p-| - * -+--+--+--+--+--+--+ - * | | | | | | '- 360 Deg - * | | | | | '---- 300 Deg - * | | | | '------- 240 Deg - * | | | '---------- 180 Deg - * | | '------------- 120 Deg - * | '---------------- 60 Deg - * '------------------- 0 Deg - * - * Legend: - * p+: PWM on the high side - * p-: PWM on the low side - * --: Low side on - * ++: High side on - * : Floating/NC - * @endverbatim - */ - switch (step) { - case 0: /* A PWM HIGH, B OFF, C LOW */ - timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_PWM1); - timer_set_oc_mode(TIM1, TIM_OC2, TIM_OCM_FROZEN); - timer_set_oc_mode(TIM1, TIM_OC3, TIM_OCM_FORCE_LOW); - - timer_enable_oc_output(TIM1, TIM_OC1); - timer_disable_oc_output(TIM1, TIM_OC1N); - - timer_disable_oc_output(TIM1, TIM_OC2); - timer_disable_oc_output(TIM1, TIM_OC2N); - - timer_enable_oc_output(TIM1, TIM_OC3); - timer_enable_oc_output(TIM1, TIM_OC3N); - - step++; - break; - case 1: /* A HIGH, B PWM LOW, C OFF */ - timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_FORCE_HIGH); - timer_set_oc_mode(TIM1, TIM_OC2, TIM_OCM_PWM1); - timer_set_oc_mode(TIM1, TIM_OC3, TIM_OCM_FROZEN); - - timer_enable_oc_output(TIM1, TIM_OC1); - timer_enable_oc_output(TIM1, TIM_OC1N); - - timer_disable_oc_output(TIM1, TIM_OC2); - timer_enable_oc_output(TIM1, TIM_OC2N); - - timer_disable_oc_output(TIM1, TIM_OC3); - timer_disable_oc_output(TIM1, TIM_OC3N); - - step++; - break; - case 2: /* A OFF, B LOW, C PWM HIGH */ - timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_FROZEN); - timer_set_oc_mode(TIM1, TIM_OC2, TIM_OCM_FORCE_LOW); - timer_set_oc_mode(TIM1, TIM_OC3, TIM_OCM_PWM1); - - timer_disable_oc_output(TIM1, TIM_OC1); - timer_disable_oc_output(TIM1, TIM_OC1N); - - timer_enable_oc_output(TIM1, TIM_OC2); - timer_enable_oc_output(TIM1, TIM_OC2N); - - timer_enable_oc_output(TIM1, TIM_OC3); - timer_disable_oc_output(TIM1, TIM_OC3N); - - step++; - break; - case 3: /* A PWM LOW, B OFF, C HIGH */ - timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_PWM1); - timer_set_oc_mode(TIM1, TIM_OC2, TIM_OCM_FROZEN); - timer_set_oc_mode(TIM1, TIM_OC3, TIM_OCM_FORCE_HIGH); - - timer_disable_oc_output(TIM1, TIM_OC1); - timer_enable_oc_output(TIM1, TIM_OC1N); - - timer_disable_oc_output(TIM1, TIM_OC2); - timer_disable_oc_output(TIM1, TIM_OC2N); - - timer_enable_oc_output(TIM1, TIM_OC3); - timer_enable_oc_output(TIM1, TIM_OC3N); - - step++; - break; - case 4: /* A LOW, B PWM HIGH, C OFF */ - timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_FORCE_LOW); - timer_set_oc_mode(TIM1, TIM_OC2, TIM_OCM_PWM1); - timer_set_oc_mode(TIM1, TIM_OC3, TIM_OCM_FROZEN); - - timer_enable_oc_output(TIM1, TIM_OC1); - timer_enable_oc_output(TIM1, TIM_OC1N); - - timer_enable_oc_output(TIM1, TIM_OC2); - timer_disable_oc_output(TIM1, TIM_OC2N); - - timer_disable_oc_output(TIM1, TIM_OC3); - timer_disable_oc_output(TIM1, TIM_OC3N); - - step++; - break; - case 5: /* A OFF, B HIGH, C PWM LOW */ - timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_FROZEN); - timer_set_oc_mode(TIM1, TIM_OC2, TIM_OCM_FORCE_HIGH); - timer_set_oc_mode(TIM1, TIM_OC3, TIM_OCM_PWM1); - - timer_disable_oc_output(TIM1, TIM_OC1); - timer_disable_oc_output(TIM1, TIM_OC1N); - - timer_enable_oc_output(TIM1, TIM_OC2); - timer_enable_oc_output(TIM1, TIM_OC2N); - - timer_disable_oc_output(TIM1, TIM_OC3); - timer_enable_oc_output(TIM1, TIM_OC3N); - - step=0; - break; - } - gpio_toggle(GPIOC, GPIO12); -} - -int main(void) -{ - clock_setup(); - gpio_setup(); - tim_setup(); - exti_setup(); - - while (1) { - __asm("nop"); - } - - return 0; -} diff --git a/examples/stm32/stm32-h103/pwm_6step/pwm_6step.ld b/examples/stm32/stm32-h103/pwm_6step/pwm_6step.ld deleted file mode 100644 index 7ea2b92..0000000 --- a/examples/stm32/stm32-h103/pwm_6step/pwm_6step.ld +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* Linker script for Olimex STM32-H103 (STM32F103RBT6, 128K flash, 20K RAM). */ - -/* Define memory regions. */ -MEMORY -{ - rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K -} - -/* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld - diff --git a/examples/stm32/stm32-h103/spi/Makefile b/examples/stm32/stm32-h103/spi/Makefile deleted file mode 100644 index 7d3cb72..0000000 --- a/examples/stm32/stm32-h103/spi/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2010 Uwe Hermann -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program. If not, see . -## - -BINARY = spi - -include ../../Makefile.include - diff --git a/examples/stm32/stm32-h103/spi/README b/examples/stm32/stm32-h103/spi/README deleted file mode 100644 index d4714c2..0000000 --- a/examples/stm32/stm32-h103/spi/README +++ /dev/null @@ -1,8 +0,0 @@ -------------------------------------------------------------------------------- -README -------------------------------------------------------------------------------- - -This example program repeatedly sends characters on SPI1 on the ST STM32-based -Olimex STM32-H103 eval board (see http://olimex.com/dev/stm32-h103.html -for details). - diff --git a/examples/stm32/stm32-h103/spi/spi.c b/examples/stm32/stm32-h103/spi/spi.c deleted file mode 100644 index 5a36bb8..0000000 --- a/examples/stm32/stm32-h103/spi/spi.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include - -void clock_setup(void) -{ - rcc_clock_setup_in_hse_8mhz_out_72mhz(); -} - -void spi_setup(void) -{ - /* TODO */ -} - -void gpio_setup(void) -{ - /* TODO */ -} - -int main(void) -{ - clock_setup(); - gpio_setup(); - spi_setup(); - - while (1) { - spi_write(SPI1, 0xaa); - spi_write(SPI1, 0x55); - } - - return 0; -} diff --git a/examples/stm32/stm32-h103/spi/spi.ld b/examples/stm32/stm32-h103/spi/spi.ld deleted file mode 100644 index 25806f8..0000000 --- a/examples/stm32/stm32-h103/spi/spi.ld +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* Linker script for Olimex STM32-H103 (STM32F103RBT6, 128K flash, 20K RAM). */ - -/* Define memory regions. */ -MEMORY -{ - rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K -} - -/* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld - diff --git a/examples/stm32/stm32-h103/timer/Makefile b/examples/stm32/stm32-h103/timer/Makefile deleted file mode 100644 index 86aced4..0000000 --- a/examples/stm32/stm32-h103/timer/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2009 Uwe Hermann -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program. If not, see . -## - -BINARY = timer - -include ../../Makefile.include - diff --git a/examples/stm32/stm32-h103/timer/timer.c b/examples/stm32/stm32-h103/timer/timer.c deleted file mode 100644 index ea64c86..0000000 --- a/examples/stm32/stm32-h103/timer/timer.c +++ /dev/null @@ -1,183 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Piotr Esden-Tempski - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include -#include -#include - -u16 frequency_sequence[18] = { - 1000, - 500, - 1000, - 500, - 1000, - 500, - 2000, - 500, - 2000, - 500, - 2000, - 500, - 1000, - 500, - 1000, - 500, - 1000, - 5000 -}; - - -int frequency_sel = 0; - -u16 compare_time; -u16 new_time; -u16 frequency; -int debug = 0; - -void clock_setup(void) -{ - rcc_clock_setup_in_hse_8mhz_out_72mhz(); - -} - -void gpio_setup(void) -{ - /* Enable GPIOC clock. */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); - - /* - * Set GPIO12 (PORTC) (led) to - * 'output alternate function push-pull'. - */ - gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO12); - - gpio_set(GPIOC, GPIO12); - -} - -void tim_setup(void) -{ - - /* Enable TIM2 clock. */ - rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_TIM2EN); - - - /* Enable TIM2 interrupt. */ - nvic_enable_irq(NVIC_TIM2_IRQ); - - /* Reset TIM2 peripheral */ - timer_reset(TIM2); - - /* Timer global mode: - * - No divider - * - alignment edge - * - direction up - */ - timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT, - TIM_CR1_CMS_EDGE, - TIM_CR1_DIR_UP); - - /* Reset prescaler value. */ - timer_set_prescaler(TIM2, 36000); - - /* Enable preload. */ - timer_disable_preload(TIM2); - - /* Continous mode. */ - timer_continuous_mode(TIM2); - - /* Period (36kHz) */ - timer_set_period(TIM2, 65535); - - /* Disable outputs. */ - timer_disable_oc_output(TIM2, TIM_OC1); - timer_disable_oc_output(TIM2, TIM_OC2); - timer_disable_oc_output(TIM2, TIM_OC3); - timer_disable_oc_output(TIM2, TIM_OC4); - - /* -- OC1 configuration -- */ - - /* Configure global mode of line 1. */ - timer_disable_oc_clear(TIM2, TIM_OC1); - timer_disable_oc_preload(TIM2, TIM_OC1); - timer_set_oc_slow_mode(TIM2, TIM_OC1); - timer_set_oc_mode(TIM2, TIM_OC1, TIM_OCM_FROZEN); - - /* Set the capture compare value for OC1. */ - timer_set_oc_value(TIM2, TIM_OC1, 1000); - - /* ---- */ - /* ARR reload enable */ - timer_disable_preload(TIM2); - - /* Counter enable */ - timer_enable_counter(TIM2); - - /* Enable commutation interrupt */ - timer_enable_irq(TIM2, TIM_DIER_CC1IE); -} - -void tim2_isr(void) -{ - - if (timer_get_flag(TIM2, TIM_SR_CC1IF)) { - - /* Clear compare interrupt flag. */ - timer_clear_flag(TIM2, TIM_SR_CC1IF); - - /* - * Get current timer value to calculate next - * compare register value - */ - compare_time = timer_get_counter(TIM2); - - /* - * Calculate and set the next compare value. - */ - frequency = frequency_sequence[frequency_sel++]; - new_time = compare_time + frequency; - - timer_set_oc_value(TIM2, TIM_OC1, - new_time); - if (frequency_sel == 18) { - frequency_sel = 0; - } - - /* Toggle led to indicate compare event */ - gpio_toggle(GPIOC, GPIO12); - - } -} - -int main(void) -{ - - clock_setup(); - gpio_setup(); - tim_setup(); - - while (1) { - __asm("nop"); - } - - return 0; -} diff --git a/examples/stm32/stm32-h103/timer/timer.ld b/examples/stm32/stm32-h103/timer/timer.ld deleted file mode 100644 index 7ea2b92..0000000 --- a/examples/stm32/stm32-h103/timer/timer.ld +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* Linker script for Olimex STM32-H103 (STM32F103RBT6, 128K flash, 20K RAM). */ - -/* Define memory regions. */ -MEMORY -{ - rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K -} - -/* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld - diff --git a/examples/stm32/stm32-h103/traceswo/Makefile b/examples/stm32/stm32-h103/traceswo/Makefile deleted file mode 100644 index 37510d5..0000000 --- a/examples/stm32/stm32-h103/traceswo/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2009 Uwe Hermann -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program. If not, see . -## - -BINARY = traceswo - -include ../../Makefile.include - diff --git a/examples/stm32/stm32-h103/traceswo/README b/examples/stm32/stm32-h103/traceswo/README deleted file mode 100644 index 34b5227..0000000 --- a/examples/stm32/stm32-h103/traceswo/README +++ /dev/null @@ -1,11 +0,0 @@ ------------------------------------------------------------------------------- -README ------------------------------------------------------------------------------- - -This experimental program sends some characters on the TRACESWO pin using -the Instrumentation Trace Macrocell (ITM) and Trace Port Interface -Unit (TPIU). - -The SWJ-DP port must be in SWD mode and not JTAG mode for the output -to be visible. - diff --git a/examples/stm32/stm32-h103/traceswo/traceswo.c b/examples/stm32/stm32-h103/traceswo/traceswo.c deleted file mode 100644 index ac461bb..0000000 --- a/examples/stm32/stm32-h103/traceswo/traceswo.c +++ /dev/null @@ -1,100 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include - -#include -#include -#include -#include - -void clock_setup(void) -{ - rcc_clock_setup_in_hse_8mhz_out_72mhz(); - - /* Enable GPIOC clock. */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); -} - -void trace_setup(void) -{ - /* Enable trace subsystem (we'll use ITM and TPIU) */ - SCS_DEMCR |= SCS_DEMCR_TRCENA; - - /* Use Manchester code for asynchronous transmission */ - TPIU_SPPR = TPIU_SPPR_ASYNC_MANCHESTER; - TPIU_ACPR = 7; - - /* Data width is 1 byte */ - TPIU_CSPSR = TPIU_CSPSR_BYTE; - - /* Formatter and flush control */ - TPIU_FFCR &= ~TPIU_FFCR_ENFCONT; - - /* Enable TRACESWO pin for async mode */ - DBGMCU_CR = DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_ASYNC; - - /* Unlock access to ITM registers */ - /* FIXME: Magic numbers... Is this Cortex-M3 generic? */ - *((volatile uint32_t*)0xE0000FB0) = 0xC5ACCE55; - - /* Enable ITM with ID = 1 */ - ITM_TCR = (1 << 16) | ITM_TCR_ITMENA; - /* Enable stimulus port 1 */ - ITM_TER[0] = 1; - -} - -void gpio_setup(void) -{ - /* Set GPIO12 (in GPIO port C) to 'output push-pull'. */ - gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_2_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO12); -} - -void trace_send_blocking(char c) -{ - while(!(ITM_STIM[0] & ITM_STIM_FIFOREADY)); - ITM_STIM[0] = c; -} - -int main(void) -{ - int i, j = 0, c = 0; - - clock_setup(); - gpio_setup(); - trace_setup(); - - /* Blink the LED (PC12) on the board with every transmitted byte. */ - while (1) { - gpio_toggle(GPIOC, GPIO12); /* LED on/off */ - trace_send_blocking(c + '0'); - c = (c == 9) ? 0 : c + 1; /* Increment c. */ - if ((j++ % 80) == 0) { /* Newline after line full. */ - trace_send_blocking('\r'); - trace_send_blocking('\n'); - } - for (i = 0; i < 800000; i++) /* Wait a bit. */ - __asm__("NOP"); - } - - return 0; -} diff --git a/examples/stm32/stm32-h103/traceswo/traceswo.ld b/examples/stm32/stm32-h103/traceswo/traceswo.ld deleted file mode 100644 index 7ea2b92..0000000 --- a/examples/stm32/stm32-h103/traceswo/traceswo.ld +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* Linker script for Olimex STM32-H103 (STM32F103RBT6, 128K flash, 20K RAM). */ - -/* Define memory regions. */ -MEMORY -{ - rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K -} - -/* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld - diff --git a/examples/stm32/stm32-h103/usart/Makefile b/examples/stm32/stm32-h103/usart/Makefile deleted file mode 100644 index 2c1e1b1..0000000 --- a/examples/stm32/stm32-h103/usart/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2009 Uwe Hermann -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program. If not, see . -## - -BINARY = usart - -include ../../Makefile.include - diff --git a/examples/stm32/stm32-h103/usart/README b/examples/stm32/stm32-h103/usart/README deleted file mode 100644 index ecd7269..0000000 --- a/examples/stm32/stm32-h103/usart/README +++ /dev/null @@ -1,13 +0,0 @@ ------------------------------------------------------------------------------- -README ------------------------------------------------------------------------------- - -This example program sends some characters on USART3 on the ST STM32-based -Olimex STM32-H103 eval board (see http://olimex.com/dev/stm32-h103.html -for details). - -The terminal settings for the receiving device/PC are 38400 8n1. - -The sending is done in a blocking way in the code, see the usart_irq example -for a more elaborate USART example. - diff --git a/examples/stm32/stm32-h103/usart/usart.c b/examples/stm32/stm32-h103/usart/usart.c deleted file mode 100644 index 9692d61..0000000 --- a/examples/stm32/stm32-h103/usart/usart.c +++ /dev/null @@ -1,119 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include - -void clock_setup(void) -{ - rcc_clock_setup_in_hse_8mhz_out_72mhz(); - - /* Enable GPIOC clock. */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | RCC_APB2ENR_IOPCEN); - - /* Enable clocks for GPIO port B (for GPIO_USART3_TX) and USART3. */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_USART1EN); - rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_USART2EN | RCC_APB1ENR_USART3EN); -} - -void usart_setup(void) -{ - /* Setup GPIO pin GPIO_USART1_TX. */ - gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_USART1_TX); - - /* Setup UART parameters. */ - usart_set_baudrate(USART1, 38400); - usart_set_databits(USART1, 8); - usart_set_stopbits(USART1, USART_STOPBITS_1); - usart_set_mode(USART1, USART_MODE_TX); - usart_set_parity(USART1, USART_PARITY_NONE); - usart_set_flow_control(USART1, USART_FLOWCONTROL_NONE); - - /* Finally enable the USART. */ - usart_enable(USART1); - - /* Setup GPIO pin GPIO_USART2_TX. */ - gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_USART2_TX); - - /* Setup UART parameters. */ - usart_set_baudrate(USART2, 38400); - usart_set_databits(USART2, 8); - usart_set_stopbits(USART2, USART_STOPBITS_1); - usart_set_mode(USART2, USART_MODE_TX); - usart_set_parity(USART2, USART_PARITY_NONE); - usart_set_flow_control(USART2, USART_FLOWCONTROL_NONE); - - /* Finally enable the USART. */ - usart_enable(USART2); - - /* Setup GPIO pin GPIO_USART3_TX/GPIO10 on GPIO port B for transmit. */ - gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_USART3_TX); - - /* Setup UART parameters. */ - usart_set_baudrate(USART3, 38400); - usart_set_databits(USART3, 8); - usart_set_stopbits(USART3, USART_STOPBITS_1); - usart_set_mode(USART3, USART_MODE_TX); - usart_set_parity(USART3, USART_PARITY_NONE); - usart_set_flow_control(USART3, USART_FLOWCONTROL_NONE); - - /* Finally enable the USART. */ - usart_enable(USART3); -} - -void gpio_setup(void) -{ - /* Set GPIO12 (in GPIO port C) to 'output push-pull'. */ - gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_2_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO12); -} - -int main(void) -{ - int i, j = 0, c = 0; - - clock_setup(); - gpio_setup(); - usart_setup(); - - /* Blink the LED (PC12) on the board with every transmitted byte. */ - while (1) { - gpio_toggle(GPIOC, GPIO12); /* LED on/off */ - usart_send_blocking(USART1, c + '0'); /* USART1: Send byte. */ - usart_send_blocking(USART2, c + '0'); /* USART2: Send byte. */ - usart_send_blocking(USART3, c + '0'); /* USART3: Send byte. */ - c = (c == 9) ? 0 : c + 1; /* Increment c. */ - if ((j++ % 80) == 0) { /* Newline after line full. */ - usart_send_blocking(USART1, '\r'); - usart_send_blocking(USART1, '\n'); - usart_send_blocking(USART2, '\r'); - usart_send_blocking(USART2, '\n'); - usart_send_blocking(USART3, '\r'); - usart_send_blocking(USART3, '\n'); - } - for (i = 0; i < 800000; i++) /* Wait a bit. */ - __asm__("NOP"); - } - - return 0; -} diff --git a/examples/stm32/stm32-h103/usart/usart.ld b/examples/stm32/stm32-h103/usart/usart.ld deleted file mode 100644 index 7ea2b92..0000000 --- a/examples/stm32/stm32-h103/usart/usart.ld +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* Linker script for Olimex STM32-H103 (STM32F103RBT6, 128K flash, 20K RAM). */ - -/* Define memory regions. */ -MEMORY -{ - rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K -} - -/* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld - diff --git a/examples/stm32/stm32-h103/usart_irq/Makefile b/examples/stm32/stm32-h103/usart_irq/Makefile deleted file mode 100644 index 6ee93bd..0000000 --- a/examples/stm32/stm32-h103/usart_irq/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2009 Uwe Hermann -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program. If not, see . -## - -BINARY = usart_irq - -include ../../Makefile.include - diff --git a/examples/stm32/stm32-h103/usart_irq/usart_irq.c b/examples/stm32/stm32-h103/usart_irq/usart_irq.c deleted file mode 100644 index 9b957dc..0000000 --- a/examples/stm32/stm32-h103/usart_irq/usart_irq.c +++ /dev/null @@ -1,119 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include -#include - -void clock_setup(void) -{ - rcc_clock_setup_in_hse_8mhz_out_72mhz(); - - /* Enable GPIOA clock (for LED GPIOs). */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); - - /* Enable clocks for GPIO port A (for GPIO_USART1_TX) and USART1. */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN | - RCC_APB2ENR_AFIOEN | - RCC_APB2ENR_USART1EN); -} - -void usart_setup(void) -{ - /* Enable the USART1 interrupt. */ - nvic_enable_irq(NVIC_USART1_IRQ); - - /* Setup GPIO pin GPIO_USART1_RE_TX on GPIO port B for transmit. */ - gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_USART1_TX); - - /* Setup GPIO pin GPIO_USART1_RE_RX on GPIO port B for receive. */ - gpio_set_mode(GPIOA, GPIO_MODE_INPUT, - GPIO_CNF_INPUT_FLOAT, GPIO_USART1_RX); - - /* Setup UART parameters. */ - usart_set_baudrate(USART1, 230400); - usart_set_databits(USART1, 8); - usart_set_stopbits(USART1, USART_STOPBITS_1); - usart_set_parity(USART1, USART_PARITY_NONE); - usart_set_flow_control(USART1, USART_FLOWCONTROL_NONE); - usart_set_mode(USART1, USART_MODE_TX_RX); - - /* Enable USART1 Receive interrupt. */ - USART_CR1(USART1) |= USART_CR1_RXNEIE; - - /* Finally enable the USART. */ - usart_enable(USART1); -} - -void gpio_setup(void) -{ - gpio_set(GPIOC, GPIO12); - - /* Setup GPIO6 and 7 (in GPIO port A) for led use. */ - gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO12); -} - -void usart1_isr(void) -{ - static u8 data = 'A'; - - /* Check if we were called because of RXNE. */ - if (((USART_CR1(USART1) & USART_CR1_RXNEIE) != 0) && - ((USART_SR(USART1) & USART_SR_RXNE) != 0)) { - - /* Indicate that we got data. */ - gpio_toggle(GPIOC, GPIO12); - - /* Retrieve the data from the peripheral. */ - data = usart_recv(USART1); - - /* Enable transmit interrupt so it sends back the data. */ - USART_CR1(USART1) |= USART_CR1_TXEIE; - } - - /* Check if we were called because of TXE. */ - if (((USART_CR1(USART1) & USART_CR1_TXEIE) != 0) && - ((USART_SR(USART1) & USART_SR_TXE) != 0)) { - - /* Indicate that we are sending out data. */ - //gpio_toggle(GPIOA, GPIO7); - - /* Put data into the transmit register. */ - usart_send(USART1, data); - - /* Disable the TXE interrupt as we don't need it anymore. */ - USART_CR1(USART1) &= ~USART_CR1_TXEIE; - } -} - -int main(void) -{ - clock_setup(); - gpio_setup(); - usart_setup(); - - /* Wait forever and do nothing. */ - while (1) - __asm__("nop"); - - return 0; -} diff --git a/examples/stm32/stm32-h103/usart_irq/usart_irq.ld b/examples/stm32/stm32-h103/usart_irq/usart_irq.ld deleted file mode 100644 index 7899773..0000000 --- a/examples/stm32/stm32-h103/usart_irq/usart_irq.ld +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* Linker script for Open-BLDC (STM32F103CBT6, 128K flash, 20K RAM). */ - -/* Define memory regions. */ -MEMORY -{ - rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K -} - -/* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld - diff --git a/examples/stm32/stm32-h103/usart_irq_printf/Makefile b/examples/stm32/stm32-h103/usart_irq_printf/Makefile deleted file mode 100644 index 2917a7d..0000000 --- a/examples/stm32/stm32-h103/usart_irq_printf/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2009 Uwe Hermann -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program. If not, see . -## - -BINARY = usart_irq_printf - -include ../../Makefile.include - diff --git a/examples/stm32/stm32-h103/usart_irq_printf/usart_irq_printf.c b/examples/stm32/stm32-h103/usart_irq_printf/usart_irq_printf.c deleted file mode 100644 index 42a7472..0000000 --- a/examples/stm32/stm32-h103/usart_irq_printf/usart_irq_printf.c +++ /dev/null @@ -1,272 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann , - * 2011 Piotr Esden-Tempski - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include -#include -#include - -#include -#include - -/****************************************************************************** - * Simple ringbuffer implementation from open-bldc's libgovernor that - * you can find at: - * https://github.com/open-bldc/open-bldc/tree/master/source/libgovernor - ******************************************************************************/ - -typedef s32 ring_size_t; - -struct ring { - u8 *data; - ring_size_t size; - u32 begin; - u32 end; -}; - -#define RING_SIZE(RING) ((RING)->size - 1) -#define RING_DATA(RING) (RING)->data -#define RING_EMPTY(RING) ((RING)->begin == (RING)->end) - -void ring_init(struct ring *ring, u8 * buf, ring_size_t size) -{ - ring->data = buf; - ring->size = size; - ring->begin = 0; - ring->end = 0; -} - -s32 ring_write_ch(struct ring *ring, u8 ch) -{ - if (((ring->end + 1) % ring->size) != ring->begin) { - ring->data[ring->end++] = ch; - ring->end %= ring->size; - return (u32) ch; - } - - return -1; -} - -s32 ring_write(struct ring * ring, u8 * data, ring_size_t size) -{ - s32 i; - - for (i = 0; i < size; i++) { - if (ring_write_ch(ring, data[i]) < 0) { - return -i; - } - } - - return i; -} - -s32 ring_read_ch(struct ring * ring, u8 * ch) -{ - s32 ret = -1; - - if (ring->begin != ring->end) { - ret = ring->data[ring->begin++]; - ring->begin %= ring->size; - if (ch) - *ch = ret; - } - - return ret; -} - -s32 ring_read(struct ring * ring, u8 * data, ring_size_t size) -{ - s32 i; - - for (i = 0; i < size; i++) { - if (ring_read_ch(ring, data + i) < 0) { - return i; - } - } - - return -i; -} - -/****************************************************************************** - * The example implementation - ******************************************************************************/ - -#define BUFFER_SIZE 1024 - -struct ring output_ring; -u8 output_ring_buffer[BUFFER_SIZE]; - -void clock_setup(void) -{ - rcc_clock_setup_in_hse_8mhz_out_72mhz(); - - /* Enable GPIOA clock (for LED GPIOs). */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); - - /* Enable clocks for GPIO port A (for GPIO_USART1_TX) and USART1. */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN | - RCC_APB2ENR_AFIOEN | - RCC_APB2ENR_USART1EN); -} - -void usart_setup(void) -{ - - /* Initialize output ring buffer */ - ring_init(&output_ring, output_ring_buffer, BUFFER_SIZE); - - /* Enable the USART1 interrupt. */ - nvic_enable_irq(NVIC_USART1_IRQ); - - /* Setup GPIO pin GPIO_USART1_RE_TX on GPIO port B for transmit. */ - gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_USART1_TX); - - /* Setup GPIO pin GPIO_USART1_RE_RX on GPIO port B for receive. */ - gpio_set_mode(GPIOA, GPIO_MODE_INPUT, - GPIO_CNF_INPUT_FLOAT, GPIO_USART1_RX); - - /* Setup UART parameters. */ - usart_set_baudrate(USART1, 230400); - usart_set_databits(USART1, 8); - usart_set_stopbits(USART1, USART_STOPBITS_1); - usart_set_parity(USART1, USART_PARITY_NONE); - usart_set_flow_control(USART1, USART_FLOWCONTROL_NONE); - usart_set_mode(USART1, USART_MODE_TX_RX); - - /* Enable USART1 Receive interrupt. */ - USART_CR1(USART1) |= USART_CR1_RXNEIE; - - /* Finally enable the USART. */ - usart_enable(USART1); -} - -void gpio_setup(void) -{ - gpio_set(GPIOC, GPIO12); - - /* Setup GPIO6 and 7 (in GPIO port A) for led use. */ - gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO12); -} - -void usart1_isr(void) -{ - /* Check if we were called because of RXNE. */ - if (((USART_CR1(USART1) & USART_CR1_RXNEIE) != 0) && - ((USART_SR(USART1) & USART_SR_RXNE) != 0)) { - - /* Indicate that we got data. */ - gpio_toggle(GPIOC, GPIO12); - - /* Retrieve the data from the peripheral. */ - ring_write_ch(&output_ring, usart_recv(USART1)); - - /* Enable transmit interrupt so it sends back the data. */ - USART_CR1(USART1) |= USART_CR1_TXEIE; - } - - /* Check if we were called because of TXE. */ - if (((USART_CR1(USART1) & USART_CR1_TXEIE) != 0) && - ((USART_SR(USART1) & USART_SR_TXE) != 0)) { - - s32 data; - - data = ring_read_ch(&output_ring, NULL); - - if (data == -1) { - /* Disable the TXE interrupt as we don't need it anymore. */ - USART_CR1(USART1) &= ~USART_CR1_TXEIE; - } else { - /* Put data into the transmit register. */ - usart_send(USART1, data); - } - } -} - -int _write (int file, char *ptr, int len) -{ - int ret; - - if (file == 1) { - ret = ring_write(&output_ring, (u8 *)ptr, len); - - if (ret < 0) ret = -ret; - - USART_CR1(USART1) |= USART_CR1_TXEIE; - - return ret; - } - - errno = EIO; - return -1; -} - -void systick_setup(void) { - - /* 72MHz / 8 => 9000000 counts per second */ - systick_set_clocksource(STK_CTRL_CLKSOURCE_AHB_DIV8); - - /* 9000000/9000 = 1000 overflows per second - every 1ms one interrupt */ - systick_set_reload(9000); - - systick_interrupt_enable(); - - /* Start counting. */ - systick_counter_enable(); - -} - -void sys_tick_handler(void) -{ - static int counter = 0; - static float fcounter = 0.0; - static double dcounter = 0.0; - - static u32 temp32 = 0; - - temp32++; - - /* We call this handler every 1ms so we are sending hello world every 10ms / 100Hz. */ - if (temp32 == 10) { - printf("Hello World! %i %f %f\r\n", counter, fcounter, dcounter); - counter++; - fcounter+=0.01; - dcounter+=0.01; - - temp32 = 0; - } -} - -int main(void) -{ - - clock_setup(); - gpio_setup(); - usart_setup(); - systick_setup(); - - while (1) { - __asm__("nop"); - } - - return 0; -} diff --git a/examples/stm32/stm32-h103/usart_irq_printf/usart_irq_printf.ld b/examples/stm32/stm32-h103/usart_irq_printf/usart_irq_printf.ld deleted file mode 100644 index 7899773..0000000 --- a/examples/stm32/stm32-h103/usart_irq_printf/usart_irq_printf.ld +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* Linker script for Open-BLDC (STM32F103CBT6, 128K flash, 20K RAM). */ - -/* Define memory regions. */ -MEMORY -{ - rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K -} - -/* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld - diff --git a/examples/stm32/stm32-h103/usart_printf/Makefile b/examples/stm32/stm32-h103/usart_printf/Makefile deleted file mode 100644 index fb26208..0000000 --- a/examples/stm32/stm32-h103/usart_printf/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2009 Uwe Hermann -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program. If not, see . -## - -BINARY = usart_printf - -include ../../Makefile.include - diff --git a/examples/stm32/stm32-h103/usart_printf/usart_printf.c b/examples/stm32/stm32-h103/usart_printf/usart_printf.c deleted file mode 100644 index 26fcee6..0000000 --- a/examples/stm32/stm32-h103/usart_printf/usart_printf.c +++ /dev/null @@ -1,108 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann , - * 2011 Piotr Esden-Tempski - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include -#include - -#include -#include - -void clock_setup(void) -{ - rcc_clock_setup_in_hse_8mhz_out_72mhz(); - - /* Enable GPIOA clock (for LED GPIOs). */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); - - /* Enable clocks for GPIO port A (for GPIO_USART1_TX) and USART1. */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN | - RCC_APB2ENR_AFIOEN | - RCC_APB2ENR_USART1EN); -} - -void usart_setup(void) -{ - /* Setup GPIO pin GPIO_USART1_RE_TX on GPIO port B for transmit. */ - gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_USART1_TX); - - /* Setup UART parameters. */ - usart_set_baudrate(USART1, 230400); - usart_set_databits(USART1, 8); - usart_set_stopbits(USART1, USART_STOPBITS_1); - usart_set_parity(USART1, USART_PARITY_NONE); - usart_set_flow_control(USART1, USART_FLOWCONTROL_NONE); - usart_set_mode(USART1, USART_MODE_TX); - - /* Finally enable the USART. */ - usart_enable(USART1); -} - -void gpio_setup(void) -{ - gpio_set(GPIOC, GPIO12); - - /* Setup GPIO6 and 7 (in GPIO port A) for led use. */ - gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO12); -} - -int _write (int file, char *ptr, int len) -{ - int i; - - if (file == 1) { - for (i = 0; i < len; i++){ - usart_send_blocking(USART1, ptr[i]); - } - - return i; - } - - errno = EIO; - return -1; -} - -int main(void) -{ - int counter = 0; - float fcounter = 0.0; - double dcounter = 0.0; - - clock_setup(); - gpio_setup(); - usart_setup(); - - /* - * Write Hello World an integer, float and double all over - * again while incrementing the numbers. - */ - while (1) { - gpio_toggle(GPIOC, GPIO12); - printf("Hello World! %i %f %f\r\n", counter, fcounter, dcounter); - counter++; - fcounter+=0.01; - dcounter+=0.01; - } - - return 0; -} diff --git a/examples/stm32/stm32-h103/usart_printf/usart_printf.ld b/examples/stm32/stm32-h103/usart_printf/usart_printf.ld deleted file mode 100644 index 7899773..0000000 --- a/examples/stm32/stm32-h103/usart_printf/usart_printf.ld +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* Linker script for Open-BLDC (STM32F103CBT6, 128K flash, 20K RAM). */ - -/* Define memory regions. */ -MEMORY -{ - rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K -} - -/* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld - diff --git a/examples/stm32/stm32-h103/usb_cdcacm/Makefile b/examples/stm32/stm32-h103/usb_cdcacm/Makefile deleted file mode 100644 index 38179e3..0000000 --- a/examples/stm32/stm32-h103/usb_cdcacm/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2009 Uwe Hermann -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program. If not, see . -## - -BINARY = cdcacm - -include ../../Makefile.include - diff --git a/examples/stm32/stm32-h103/usb_cdcacm/README b/examples/stm32/stm32-h103/usb_cdcacm/README deleted file mode 100644 index 2f1ee4b..0000000 --- a/examples/stm32/stm32-h103/usb_cdcacm/README +++ /dev/null @@ -1,7 +0,0 @@ ------------------------------------------------------------------------------- -README ------------------------------------------------------------------------------- - -This example implements a USB CDC-ACM device (aka Virtual Serial Port) -to demonstrate the use of the USB device stack. - diff --git a/examples/stm32/stm32-h103/usb_cdcacm/cdcacm.c b/examples/stm32/stm32-h103/usb_cdcacm/cdcacm.c deleted file mode 100644 index 4b90640..0000000 --- a/examples/stm32/stm32-h103/usb_cdcacm/cdcacm.c +++ /dev/null @@ -1,246 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Gareth McMullin - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include -#include -#include - -static const struct usb_device_descriptor dev = { - .bLength = USB_DT_DEVICE_SIZE, - .bDescriptorType = USB_DT_DEVICE, - .bcdUSB = 0x0200, - .bDeviceClass = USB_CLASS_CDC, - .bDeviceSubClass = 0, - .bDeviceProtocol = 0, - .bMaxPacketSize0 = 64, - .idVendor = 0x0483, - .idProduct = 0x5740, - .bcdDevice = 0x0200, - .iManufacturer = 1, - .iProduct = 2, - .iSerialNumber = 3, - .bNumConfigurations = 1, -}; - -/* This notification endpoint isn't implemented. According to CDC spec its - * optional, but its absence causes a NULL pointer dereference in Linux cdc_acm - * driver. */ -static const struct usb_endpoint_descriptor comm_endp[] = {{ - .bLength = USB_DT_ENDPOINT_SIZE, - .bDescriptorType = USB_DT_ENDPOINT, - .bEndpointAddress = 0x83, - .bmAttributes = USB_ENDPOINT_ATTR_INTERRUPT, - .wMaxPacketSize = 16, - .bInterval = 255, -}}; - -static const struct usb_endpoint_descriptor data_endp[] = {{ - .bLength = USB_DT_ENDPOINT_SIZE, - .bDescriptorType = USB_DT_ENDPOINT, - .bEndpointAddress = 0x01, - .bmAttributes = USB_ENDPOINT_ATTR_BULK, - .wMaxPacketSize = 64, - .bInterval = 1, -}, { - .bLength = USB_DT_ENDPOINT_SIZE, - .bDescriptorType = USB_DT_ENDPOINT, - .bEndpointAddress = 0x82, - .bmAttributes = USB_ENDPOINT_ATTR_BULK, - .wMaxPacketSize = 64, - .bInterval = 1, -}}; - -static const struct { - struct usb_cdc_header_descriptor header; - struct usb_cdc_call_management_descriptor call_mgmt; - struct usb_cdc_acm_descriptor acm; - struct usb_cdc_union_descriptor cdc_union; -} __attribute__((packed)) cdcacm_functional_descriptors = { - .header = { - .bFunctionLength = sizeof(struct usb_cdc_header_descriptor), - .bDescriptorType = CS_INTERFACE, - .bDescriptorSubtype = USB_CDC_TYPE_HEADER, - .bcdCDC = 0x0110, - }, - .call_mgmt = { - .bFunctionLength = - sizeof(struct usb_cdc_call_management_descriptor), - .bDescriptorType = CS_INTERFACE, - .bDescriptorSubtype = USB_CDC_TYPE_CALL_MANAGEMENT, - .bmCapabilities = 0, - .bDataInterface = 1, - }, - .acm = { - .bFunctionLength = sizeof(struct usb_cdc_acm_descriptor), - .bDescriptorType = CS_INTERFACE, - .bDescriptorSubtype = USB_CDC_TYPE_ACM, - .bmCapabilities = 0, - }, - .cdc_union = { - .bFunctionLength = sizeof(struct usb_cdc_union_descriptor), - .bDescriptorType = CS_INTERFACE, - .bDescriptorSubtype = USB_CDC_TYPE_UNION, - .bControlInterface = 0, - .bSubordinateInterface0 = 1, - } -}; - -static const struct usb_interface_descriptor comm_iface[] = {{ - .bLength = USB_DT_INTERFACE_SIZE, - .bDescriptorType = USB_DT_INTERFACE, - .bInterfaceNumber = 0, - .bAlternateSetting = 0, - .bNumEndpoints = 1, - .bInterfaceClass = USB_CLASS_CDC, - .bInterfaceSubClass = USB_CDC_SUBCLASS_ACM, - .bInterfaceProtocol = USB_CDC_PROTOCOL_AT, - .iInterface = 0, - - .endpoint = comm_endp, - - .extra = &cdcacm_functional_descriptors, - .extralen = sizeof(cdcacm_functional_descriptors) -}}; - -static const struct usb_interface_descriptor data_iface[] = {{ - .bLength = USB_DT_INTERFACE_SIZE, - .bDescriptorType = USB_DT_INTERFACE, - .bInterfaceNumber = 1, - .bAlternateSetting = 0, - .bNumEndpoints = 2, - .bInterfaceClass = USB_CLASS_DATA, - .bInterfaceSubClass = 0, - .bInterfaceProtocol = 0, - .iInterface = 0, - - .endpoint = data_endp, -}}; - -static const struct usb_interface ifaces[] = {{ - .num_altsetting = 1, - .altsetting = comm_iface, -}, { - .num_altsetting = 1, - .altsetting = data_iface, -}}; - -static const struct usb_config_descriptor config = { - .bLength = USB_DT_CONFIGURATION_SIZE, - .bDescriptorType = USB_DT_CONFIGURATION, - .wTotalLength = 0, - .bNumInterfaces = 2, - .bConfigurationValue = 1, - .iConfiguration = 0, - .bmAttributes = 0x80, - .bMaxPower = 0x32, - - .interface = ifaces, -}; - -static const char *usb_strings[] = { - "x", - "Black Sphere Technologies", - "CDC-ACM Demo", - "DEMO" -}; - -static int cdcacm_control_request(struct usb_setup_data *req, u8 **buf, - u16 *len, void (**complete)(struct usb_setup_data *req)) -{ - (void)complete; - (void)buf; - - switch(req->bRequest) { - case USB_CDC_REQ_SET_CONTROL_LINE_STATE: { - /* This Linux cdc_acm driver requires this to be implemented - * even though it's optional in the CDC spec, and we don't - * advertise it in the ACM functional descriptor. */ - char buf[10]; - struct usb_cdc_notification *notif = (void*)buf; - - /* We echo signals back to host as notification */ - notif->bmRequestType = 0xA1; - notif->bNotification = USB_CDC_NOTIFY_SERIAL_STATE; - notif->wValue = 0; - notif->wIndex = 0; - notif->wLength = 2; - buf[8] = req->wValue & 3; - buf[9] = 0; - //usbd_ep_write_packet(0x83, buf, 10); - return 1; - } - case USB_CDC_REQ_SET_LINE_CODING: - if(*len < sizeof(struct usb_cdc_line_coding)) - return 0; - - return 1; - } - return 0; -} - -static void cdcacm_data_rx_cb(u8 ep) -{ - (void)ep; - - char buf[64]; - int len = usbd_ep_read_packet(0x01, buf, 64); - if(len) { - usbd_ep_write_packet(0x82, buf, len); - buf[len] = 0; - } -} - -static void cdcacm_set_config(u16 wValue) -{ - (void)wValue; - - usbd_ep_setup(0x01, USB_ENDPOINT_ATTR_BULK, 64, cdcacm_data_rx_cb); - usbd_ep_setup(0x82, USB_ENDPOINT_ATTR_BULK, 64, NULL); - usbd_ep_setup(0x83, USB_ENDPOINT_ATTR_INTERRUPT, 16, NULL); - - usbd_register_control_callback( - USB_REQ_TYPE_CLASS | USB_REQ_TYPE_INTERFACE, - USB_REQ_TYPE_TYPE | USB_REQ_TYPE_RECIPIENT, - cdcacm_control_request); -} - -int main(void) -{ - int i; - - rcc_clock_setup_in_hsi_out_48mhz(); - - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); - - gpio_set(GPIOC, GPIO11); - gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_2_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO11); - - usbd_init(&stm32f103_usb_driver, &dev, &config, usb_strings); - usbd_register_set_config_callback(cdcacm_set_config); - - for (i = 0; i < 0x800000; i++) - __asm__("nop"); - gpio_clear(GPIOC, GPIO11); - - while (1) - usbd_poll(); -} diff --git a/examples/stm32/stm32-h103/usb_cdcacm/cdcacm.ld b/examples/stm32/stm32-h103/usb_cdcacm/cdcacm.ld deleted file mode 100644 index 928c898..0000000 --- a/examples/stm32/stm32-h103/usb_cdcacm/cdcacm.ld +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* Linker script for Olimex STM32-H103 (STM32F103RBT6, 128K flash, 20K RAM). */ - -/* Define memory regions. */ -MEMORY -{ - rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K -} - -/* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld - diff --git a/examples/stm32/stm32-h103/usb_dfu/Makefile b/examples/stm32/stm32-h103/usb_dfu/Makefile deleted file mode 100644 index 48e2d6b..0000000 --- a/examples/stm32/stm32-h103/usb_dfu/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2009 Uwe Hermann -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program. If not, see . -## - -BINARY = usbdfu - -include ../../Makefile.include - diff --git a/examples/stm32/stm32-h103/usb_dfu/README b/examples/stm32/stm32-h103/usb_dfu/README deleted file mode 100644 index 9c0169a..0000000 --- a/examples/stm32/stm32-h103/usb_dfu/README +++ /dev/null @@ -1,7 +0,0 @@ ------------------------------------------------------------------------------- -README ------------------------------------------------------------------------------- - -This example implements a USB Device Firmware Upgrade (DFU) bootloader -to demonstrate the use of the USB device stack. - diff --git a/examples/stm32/stm32-h103/usb_dfu/usbdfu.c b/examples/stm32/stm32-h103/usb_dfu/usbdfu.c deleted file mode 100644 index 7ffbc74..0000000 --- a/examples/stm32/stm32-h103/usb_dfu/usbdfu.c +++ /dev/null @@ -1,270 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Gareth McMullin - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include -#include -#include -#include -#include - -#define APP_ADDRESS 0x08002000 - -/* Commands sent with wBlockNum == 0 as per ST implementation. */ -#define CMD_SETADDR 0x21 -#define CMD_ERASE 0x41 - -/* We need a special large control buffer for this device: */ -u8 usbd_control_buffer[1024]; - -static enum dfu_state usbdfu_state = STATE_DFU_IDLE; - -static struct { - u8 buf[sizeof(usbd_control_buffer)]; - u16 len; - u32 addr; - u16 blocknum; -} prog; - -const struct usb_device_descriptor dev = { - .bLength = USB_DT_DEVICE_SIZE, - .bDescriptorType = USB_DT_DEVICE, - .bcdUSB = 0x0200, - .bDeviceClass = 0, - .bDeviceSubClass = 0, - .bDeviceProtocol = 0, - .bMaxPacketSize0 = 64, - .idVendor = 0x0483, - .idProduct = 0xDF11, - .bcdDevice = 0x0200, - .iManufacturer = 1, - .iProduct = 2, - .iSerialNumber = 3, - .bNumConfigurations = 1, -}; - -const struct usb_dfu_descriptor dfu_function = { - .bLength = sizeof(struct usb_dfu_descriptor), - .bDescriptorType = DFU_FUNCTIONAL, - .bmAttributes = USB_DFU_CAN_DOWNLOAD | USB_DFU_WILL_DETACH, - .wDetachTimeout = 255, - .wTransferSize = 1024, - .bcdDFUVersion = 0x011A, -}; - -const struct usb_interface_descriptor iface = { - .bLength = USB_DT_INTERFACE_SIZE, - .bDescriptorType = USB_DT_INTERFACE, - .bInterfaceNumber = 0, - .bAlternateSetting = 0, - .bNumEndpoints = 0, - .bInterfaceClass = 0xFE, /* Device Firmware Upgrade */ - .bInterfaceSubClass = 1, - .bInterfaceProtocol = 2, - - /* The ST Microelectronics DfuSe application needs this string. - * The format isn't documented... */ - .iInterface = 4, - - .extra = &dfu_function, - .extralen = sizeof(dfu_function), -}; - -const struct usb_interface ifaces[] = {{ - .num_altsetting = 1, - .altsetting = &iface, -}}; - -const struct usb_config_descriptor config = { - .bLength = USB_DT_CONFIGURATION_SIZE, - .bDescriptorType = USB_DT_CONFIGURATION, - .wTotalLength = 0, - .bNumInterfaces = 1, - .bConfigurationValue = 1, - .iConfiguration = 0, - .bmAttributes = 0xC0, - .bMaxPower = 0x32, - - .interface = ifaces, -}; - -static const char *usb_strings[] = { - "x", - "Black Sphere Technologies", - "DFU Demo", - "DEMO", - /* This string is used by ST Microelectronics' DfuSe utility */ - "@Internal Flash /0x08000000/8*001Ka,56*001Kg" -}; - -static u8 usbdfu_getstatus(u32 *bwPollTimeout) -{ - switch(usbdfu_state) { - case STATE_DFU_DNLOAD_SYNC: - usbdfu_state = STATE_DFU_DNBUSY; - *bwPollTimeout = 100; - return DFU_STATUS_OK; - - case STATE_DFU_MANIFEST_SYNC: - /* Device will reset when read is complete */ - usbdfu_state = STATE_DFU_MANIFEST; - return DFU_STATUS_OK; - - default: - return DFU_STATUS_OK; - } -} - -static void usbdfu_getstatus_complete(struct usb_setup_data *req) -{ - int i; - (void)req; - - switch(usbdfu_state) { - case STATE_DFU_DNBUSY: - - flash_unlock(); - if(prog.blocknum == 0) { - switch(prog.buf[0]) { - case CMD_ERASE: - flash_erase_page(*(u32*)(prog.buf+1)); - case CMD_SETADDR: - prog.addr = *(u32*)(prog.buf+1); - } - } else { - u32 baseaddr = prog.addr + - ((prog.blocknum - 2) * - dfu_function.wTransferSize); - for(i = 0; i < prog.len; i += 2) - flash_program_half_word(baseaddr + i, - *(u16*)(prog.buf+i)); - } - flash_lock(); - - /* We jump straight to dfuDNLOAD-IDLE, - * skipping dfuDNLOAD-SYNC - */ - usbdfu_state = STATE_DFU_DNLOAD_IDLE; - return; - - case STATE_DFU_MANIFEST: - /* USB device must detach, we just reset... */ - scb_reset_system(); - return; /* Will never return */ - default: - return; - } -} - -static int usbdfu_control_request(struct usb_setup_data *req, u8 **buf, - u16 *len, void (**complete)(struct usb_setup_data *req)) -{ - - if((req->bmRequestType & 0x7F) != 0x21) - return 0; /* Only accept class request */ - - switch(req->bRequest) { - case DFU_DNLOAD: - if((len == NULL) || (*len == 0)) { - usbdfu_state = STATE_DFU_MANIFEST_SYNC; - return 1; - } else { - /* Copy download data for use on GET_STATUS */ - prog.blocknum = req->wValue; - prog.len = *len; - memcpy(prog.buf, *buf, *len); - usbdfu_state = STATE_DFU_DNLOAD_SYNC; - return 1; - } - case DFU_CLRSTATUS: - /* Clear error and return to dfuIDLE */ - if(usbdfu_state == STATE_DFU_ERROR) - usbdfu_state = STATE_DFU_IDLE; - return 1; - case DFU_ABORT: - /* Abort returns to dfuIDLE state */ - usbdfu_state = STATE_DFU_IDLE; - return 1; - case DFU_UPLOAD: - /* Upload not supported for now */ - return 0; - case DFU_GETSTATUS: { - u32 bwPollTimeout = 0; /* 24-bit integer in DFU class spec */ - - (*buf)[0] = usbdfu_getstatus(&bwPollTimeout); - (*buf)[1] = bwPollTimeout & 0xFF; - (*buf)[2] = (bwPollTimeout >> 8) & 0xFF; - (*buf)[3] = (bwPollTimeout >> 16) & 0xFF; - (*buf)[4] = usbdfu_state; - (*buf)[5] = 0; /* iString not used here */ - *len = 6; - - *complete = usbdfu_getstatus_complete; - - return 1; - } - case DFU_GETSTATE: - /* Return state with no state transision */ - *buf[0] = usbdfu_state; - *len = 1; - return 1; - } - - return 0; -} - -int main(void) -{ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); - if(!gpio_get(GPIOA, GPIO10)) { - /* Boot the application if it's valid */ - if((*(volatile u32*)APP_ADDRESS & 0x2FFE0000) == 0x20000000) { - /* Set vector table base address */ - SCB_VTOR = APP_ADDRESS & 0xFFFF; - /* Initialise master stack pointer */ - asm volatile ("msr msp, %0"::"g" - (*(volatile u32*)APP_ADDRESS)); - /* Jump to application */ - (*(void(**)())(APP_ADDRESS + 4))(); - } - } - - rcc_clock_setup_in_hsi_out_48mhz(); - - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_AFIOEN); - - AFIO_MAPR |= AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_ON; - gpio_set_mode(GPIOA, GPIO_MODE_INPUT, 0, GPIO15); - - usbd_init(&stm32f103_usb_driver, &dev, &config, usb_strings); - usbd_set_control_buffer_size(sizeof(usbd_control_buffer)); - usbd_register_control_callback( - USB_REQ_TYPE_CLASS | USB_REQ_TYPE_INTERFACE, - USB_REQ_TYPE_TYPE | USB_REQ_TYPE_RECIPIENT, - usbdfu_control_request); - - gpio_set(GPIOA, GPIO15); - gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_2_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO15); - - while (1) - usbd_poll(); -} diff --git a/examples/stm32/stm32-h103/usb_dfu/usbdfu.ld b/examples/stm32/stm32-h103/usb_dfu/usbdfu.ld deleted file mode 100644 index 54e5dac..0000000 --- a/examples/stm32/stm32-h103/usb_dfu/usbdfu.ld +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* Define memory regions. */ -MEMORY -{ - rom (rx) : ORIGIN = 0x08000000, LENGTH = 8K - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 4K -} - -/* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld - diff --git a/examples/stm32/stm32-h103/usb_hid/Makefile b/examples/stm32/stm32-h103/usb_hid/Makefile deleted file mode 100644 index d831e9e..0000000 --- a/examples/stm32/stm32-h103/usb_hid/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2009 Uwe Hermann -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program. If not, see . -## - -BINARY = usbhid - -include ../../Makefile.include - diff --git a/examples/stm32/stm32-h103/usb_hid/README b/examples/stm32/stm32-h103/usb_hid/README deleted file mode 100644 index 48a9b39..0000000 --- a/examples/stm32/stm32-h103/usb_hid/README +++ /dev/null @@ -1,7 +0,0 @@ ------------------------------------------------------------------------------- -README ------------------------------------------------------------------------------- - -This example implements a USB Human Interface Device (HID) -to demonstrate the use of the USB device stack. - diff --git a/examples/stm32/stm32-h103/usb_hid/usbhid.c b/examples/stm32/stm32-h103/usb_hid/usbhid.c deleted file mode 100644 index a21fce6..0000000 --- a/examples/stm32/stm32-h103/usb_hid/usbhid.c +++ /dev/null @@ -1,272 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Gareth McMullin - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include -#include -#include -#include - -/* Define this to include the DFU APP interface. */ -#define INCLUDE_DFU_INTERFACE - -#ifdef INCLUDE_DFU_INTERFACE -#include -#include -#endif - -const struct usb_device_descriptor dev = { - .bLength = USB_DT_DEVICE_SIZE, - .bDescriptorType = USB_DT_DEVICE, - .bcdUSB = 0x0200, - .bDeviceClass = 0, - .bDeviceSubClass = 0, - .bDeviceProtocol = 0, - .bMaxPacketSize0 = 64, - .idVendor = 0x0483, - .idProduct = 0x5710, - .bcdDevice = 0x0200, - .iManufacturer = 1, - .iProduct = 2, - .iSerialNumber = 3, - .bNumConfigurations = 1, -}; - -/* I have no idea what this means. I haven't read the HID spec. */ -static const u8 hid_report_descriptor[] = { - 0x05, 0x01, 0x09, 0x02, 0xA1, 0x01, 0x09, 0x01, - 0xA1, 0x00, 0x05, 0x09, 0x19, 0x01, 0x29, 0x03, - 0x15, 0x00, 0x25, 0x01, 0x95, 0x03, 0x75, 0x01, - 0x81, 0x02, 0x95, 0x01, 0x75, 0x05, 0x81, 0x01, - 0x05, 0x01, 0x09, 0x30, 0x09, 0x31, 0x09, 0x38, - 0x15, 0x81, 0x25, 0x7F, 0x75, 0x08, 0x95, 0x03, - 0x81, 0x06, 0xC0, 0x09, 0x3c, 0x05, 0xff, 0x09, - 0x01, 0x15, 0x00, 0x25, 0x01, 0x75, 0x01, 0x95, - 0x02, 0xb1, 0x22, 0x75, 0x06, 0x95, 0x01, 0xb1, - 0x01, 0xc0 -}; - -static const struct { - struct usb_hid_descriptor hid_descriptor; - struct { - u8 bReportDescriptorType; - u16 wDescriptorLength; - } __attribute__((packed)) hid_report; -} __attribute__((packed)) hid_function = { - .hid_descriptor = { - .bLength = sizeof(hid_function), - .bDescriptorType = USB_DT_HID, - .bcdHID = 0x0100, - .bCountryCode = 0, - .bNumDescriptors = 1, - }, - .hid_report = { - .bReportDescriptorType = USB_DT_REPORT, - .wDescriptorLength = sizeof(hid_report_descriptor), - } -}; - -const struct usb_endpoint_descriptor hid_endpoint = { - .bLength = USB_DT_ENDPOINT_SIZE, - .bDescriptorType = USB_DT_ENDPOINT, - .bEndpointAddress = 0x81, - .bmAttributes = USB_ENDPOINT_ATTR_INTERRUPT, - .wMaxPacketSize = 4, - .bInterval = 0x20, -}; - -const struct usb_interface_descriptor hid_iface = { - .bLength = USB_DT_INTERFACE_SIZE, - .bDescriptorType = USB_DT_INTERFACE, - .bInterfaceNumber = 0, - .bAlternateSetting = 0, - .bNumEndpoints = 1, - .bInterfaceClass = USB_CLASS_HID, - .bInterfaceSubClass = 1, /* boot */ - .bInterfaceProtocol = 2, /* mouse */ - .iInterface = 0, - - .endpoint = &hid_endpoint, - - .extra = &hid_function, - .extralen = sizeof(hid_function), -}; - -#ifdef INCLUDE_DFU_INTERFACE -const struct usb_dfu_descriptor dfu_function = { - .bLength = sizeof(struct usb_dfu_descriptor), - .bDescriptorType = DFU_FUNCTIONAL, - .bmAttributes = USB_DFU_CAN_DOWNLOAD | USB_DFU_WILL_DETACH, - .wDetachTimeout = 255, - .wTransferSize = 1024, - .bcdDFUVersion = 0x011A, -}; - -const struct usb_interface_descriptor dfu_iface = { - .bLength = USB_DT_INTERFACE_SIZE, - .bDescriptorType = USB_DT_INTERFACE, - .bInterfaceNumber = 1, - .bAlternateSetting = 0, - .bNumEndpoints = 0, - .bInterfaceClass = 0xFE, - .bInterfaceSubClass = 1, - .bInterfaceProtocol = 1, - .iInterface = 0, - - .extra = &dfu_function, - .extralen = sizeof(dfu_function), -}; -#endif - -const struct usb_interface ifaces[] = {{ - .num_altsetting = 1, - .altsetting = &hid_iface, -#ifdef INCLUDE_DFU_INTERFACE -}, { - .num_altsetting = 1, - .altsetting = &dfu_iface, -#endif -}}; - -const struct usb_config_descriptor config = { - .bLength = USB_DT_CONFIGURATION_SIZE, - .bDescriptorType = USB_DT_CONFIGURATION, - .wTotalLength = 0, -#ifdef INCLUDE_DFU_INTERFACE - .bNumInterfaces = 2, -#else - .bNumInterfaces = 1, -#endif - .bConfigurationValue = 1, - .iConfiguration = 0, - .bmAttributes = 0xC0, - .bMaxPower = 0x32, - - .interface = ifaces, -}; - -static const char *usb_strings[] = { - "x", - "Black Sphere Technologies", - "HID Demo", - "DEMO", -}; - -static int hid_control_request(struct usb_setup_data *req, u8 **buf, u16 *len, - void (**complete)(struct usb_setup_data *req)) -{ - (void)complete; - - if((req->bmRequestType != 0x81) || - (req->bRequest != USB_REQ_GET_DESCRIPTOR) || - (req->wValue != 0x2200)) - return 0; - - /* Handle the HID report descriptor */ - *buf = (u8*)hid_report_descriptor; - *len = sizeof(hid_report_descriptor); - - return 1; -} - -#ifdef INCLUDE_DFU_INTERFACE -static void dfu_detach_complete(struct usb_setup_data *req) -{ - (void)req; - - gpio_set_mode(GPIOA, GPIO_MODE_INPUT, 0, GPIO15); - gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_2_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO10); - gpio_set(GPIOA, GPIO10); - scb_reset_core(); -} - -static int dfu_control_request(struct usb_setup_data *req, u8 **buf, u16 *len, - void (**complete)(struct usb_setup_data *req)) -{ - (void)buf; - (void)len; - - if((req->bmRequestType != 0x21) || (req->bRequest != DFU_DETACH)) - return 0; /* Only accept class request */ - - *complete = dfu_detach_complete; - - return 1; -} -#endif - -static void hid_set_config(u16 wValue) -{ - (void)wValue; - - usbd_ep_setup(0x81, USB_ENDPOINT_ATTR_INTERRUPT, 4, NULL); - - usbd_register_control_callback( - USB_REQ_TYPE_STANDARD | USB_REQ_TYPE_INTERFACE, - USB_REQ_TYPE_TYPE | USB_REQ_TYPE_RECIPIENT, - hid_control_request); -#ifdef INCLUDE_DFU_INTERFACE - usbd_register_control_callback( - USB_REQ_TYPE_CLASS | USB_REQ_TYPE_INTERFACE, - USB_REQ_TYPE_TYPE | USB_REQ_TYPE_RECIPIENT, - dfu_control_request); -#endif - - systick_set_clocksource(STK_CTRL_CLKSOURCE_AHB_DIV8); - systick_set_reload(100000); - systick_interrupt_enable(); - systick_counter_enable(); -} - -int main(void) -{ - rcc_clock_setup_in_hsi_out_48mhz(); - - - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); - - gpio_set(GPIOC, GPIO11); - gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_2_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO11); - - usbd_init(&stm32f103_usb_driver, &dev, &config, usb_strings); - usbd_register_set_config_callback(hid_set_config); - - {int i; for (i=0;i<0x80000;i++);} - gpio_clear(GPIOC, GPIO11); - - while (1) - usbd_poll(); -} - -void sys_tick_handler(void) -{ - static int x = 0; - static int dir = 1; - u8 buf[4] = {0, 0, 0, 0}; - - buf[1] = dir; - x += dir; - if(x > 30) dir = -dir; - if(x < -30) dir = -dir; - - usbd_ep_write_packet(0x81, buf, 4); -} diff --git a/examples/stm32/stm32-h103/usb_hid/usbhid.ld b/examples/stm32/stm32-h103/usb_hid/usbhid.ld deleted file mode 100644 index 928c898..0000000 --- a/examples/stm32/stm32-h103/usb_hid/usbhid.ld +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* Linker script for Olimex STM32-H103 (STM32F103RBT6, 128K flash, 20K RAM). */ - -/* Define memory regions. */ -MEMORY -{ - rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K -} - -/* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld - diff --git a/examples/stm32/stm32-h103/usb_iap/Makefile b/examples/stm32/stm32-h103/usb_iap/Makefile deleted file mode 100644 index bed9908..0000000 --- a/examples/stm32/stm32-h103/usb_iap/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2009 Uwe Hermann -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program. If not, see . -## - -BINARY = usbiap - -include ../../Makefile.include - diff --git a/examples/stm32/stm32-h103/usb_iap/README b/examples/stm32/stm32-h103/usb_iap/README deleted file mode 100644 index 2966684..0000000 --- a/examples/stm32/stm32-h103/usb_iap/README +++ /dev/null @@ -1,8 +0,0 @@ ------------------------------------------------------------------------------- -README ------------------------------------------------------------------------------- - -This example implements a USB bootloader for the Paparazzi project. - -TODO: Move to examples/lisa-m? - diff --git a/examples/stm32/stm32-h103/usb_iap/usbiap.c b/examples/stm32/stm32-h103/usb_iap/usbiap.c deleted file mode 100644 index 7ffbc74..0000000 --- a/examples/stm32/stm32-h103/usb_iap/usbiap.c +++ /dev/null @@ -1,270 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Gareth McMullin - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include -#include -#include -#include -#include - -#define APP_ADDRESS 0x08002000 - -/* Commands sent with wBlockNum == 0 as per ST implementation. */ -#define CMD_SETADDR 0x21 -#define CMD_ERASE 0x41 - -/* We need a special large control buffer for this device: */ -u8 usbd_control_buffer[1024]; - -static enum dfu_state usbdfu_state = STATE_DFU_IDLE; - -static struct { - u8 buf[sizeof(usbd_control_buffer)]; - u16 len; - u32 addr; - u16 blocknum; -} prog; - -const struct usb_device_descriptor dev = { - .bLength = USB_DT_DEVICE_SIZE, - .bDescriptorType = USB_DT_DEVICE, - .bcdUSB = 0x0200, - .bDeviceClass = 0, - .bDeviceSubClass = 0, - .bDeviceProtocol = 0, - .bMaxPacketSize0 = 64, - .idVendor = 0x0483, - .idProduct = 0xDF11, - .bcdDevice = 0x0200, - .iManufacturer = 1, - .iProduct = 2, - .iSerialNumber = 3, - .bNumConfigurations = 1, -}; - -const struct usb_dfu_descriptor dfu_function = { - .bLength = sizeof(struct usb_dfu_descriptor), - .bDescriptorType = DFU_FUNCTIONAL, - .bmAttributes = USB_DFU_CAN_DOWNLOAD | USB_DFU_WILL_DETACH, - .wDetachTimeout = 255, - .wTransferSize = 1024, - .bcdDFUVersion = 0x011A, -}; - -const struct usb_interface_descriptor iface = { - .bLength = USB_DT_INTERFACE_SIZE, - .bDescriptorType = USB_DT_INTERFACE, - .bInterfaceNumber = 0, - .bAlternateSetting = 0, - .bNumEndpoints = 0, - .bInterfaceClass = 0xFE, /* Device Firmware Upgrade */ - .bInterfaceSubClass = 1, - .bInterfaceProtocol = 2, - - /* The ST Microelectronics DfuSe application needs this string. - * The format isn't documented... */ - .iInterface = 4, - - .extra = &dfu_function, - .extralen = sizeof(dfu_function), -}; - -const struct usb_interface ifaces[] = {{ - .num_altsetting = 1, - .altsetting = &iface, -}}; - -const struct usb_config_descriptor config = { - .bLength = USB_DT_CONFIGURATION_SIZE, - .bDescriptorType = USB_DT_CONFIGURATION, - .wTotalLength = 0, - .bNumInterfaces = 1, - .bConfigurationValue = 1, - .iConfiguration = 0, - .bmAttributes = 0xC0, - .bMaxPower = 0x32, - - .interface = ifaces, -}; - -static const char *usb_strings[] = { - "x", - "Black Sphere Technologies", - "DFU Demo", - "DEMO", - /* This string is used by ST Microelectronics' DfuSe utility */ - "@Internal Flash /0x08000000/8*001Ka,56*001Kg" -}; - -static u8 usbdfu_getstatus(u32 *bwPollTimeout) -{ - switch(usbdfu_state) { - case STATE_DFU_DNLOAD_SYNC: - usbdfu_state = STATE_DFU_DNBUSY; - *bwPollTimeout = 100; - return DFU_STATUS_OK; - - case STATE_DFU_MANIFEST_SYNC: - /* Device will reset when read is complete */ - usbdfu_state = STATE_DFU_MANIFEST; - return DFU_STATUS_OK; - - default: - return DFU_STATUS_OK; - } -} - -static void usbdfu_getstatus_complete(struct usb_setup_data *req) -{ - int i; - (void)req; - - switch(usbdfu_state) { - case STATE_DFU_DNBUSY: - - flash_unlock(); - if(prog.blocknum == 0) { - switch(prog.buf[0]) { - case CMD_ERASE: - flash_erase_page(*(u32*)(prog.buf+1)); - case CMD_SETADDR: - prog.addr = *(u32*)(prog.buf+1); - } - } else { - u32 baseaddr = prog.addr + - ((prog.blocknum - 2) * - dfu_function.wTransferSize); - for(i = 0; i < prog.len; i += 2) - flash_program_half_word(baseaddr + i, - *(u16*)(prog.buf+i)); - } - flash_lock(); - - /* We jump straight to dfuDNLOAD-IDLE, - * skipping dfuDNLOAD-SYNC - */ - usbdfu_state = STATE_DFU_DNLOAD_IDLE; - return; - - case STATE_DFU_MANIFEST: - /* USB device must detach, we just reset... */ - scb_reset_system(); - return; /* Will never return */ - default: - return; - } -} - -static int usbdfu_control_request(struct usb_setup_data *req, u8 **buf, - u16 *len, void (**complete)(struct usb_setup_data *req)) -{ - - if((req->bmRequestType & 0x7F) != 0x21) - return 0; /* Only accept class request */ - - switch(req->bRequest) { - case DFU_DNLOAD: - if((len == NULL) || (*len == 0)) { - usbdfu_state = STATE_DFU_MANIFEST_SYNC; - return 1; - } else { - /* Copy download data for use on GET_STATUS */ - prog.blocknum = req->wValue; - prog.len = *len; - memcpy(prog.buf, *buf, *len); - usbdfu_state = STATE_DFU_DNLOAD_SYNC; - return 1; - } - case DFU_CLRSTATUS: - /* Clear error and return to dfuIDLE */ - if(usbdfu_state == STATE_DFU_ERROR) - usbdfu_state = STATE_DFU_IDLE; - return 1; - case DFU_ABORT: - /* Abort returns to dfuIDLE state */ - usbdfu_state = STATE_DFU_IDLE; - return 1; - case DFU_UPLOAD: - /* Upload not supported for now */ - return 0; - case DFU_GETSTATUS: { - u32 bwPollTimeout = 0; /* 24-bit integer in DFU class spec */ - - (*buf)[0] = usbdfu_getstatus(&bwPollTimeout); - (*buf)[1] = bwPollTimeout & 0xFF; - (*buf)[2] = (bwPollTimeout >> 8) & 0xFF; - (*buf)[3] = (bwPollTimeout >> 16) & 0xFF; - (*buf)[4] = usbdfu_state; - (*buf)[5] = 0; /* iString not used here */ - *len = 6; - - *complete = usbdfu_getstatus_complete; - - return 1; - } - case DFU_GETSTATE: - /* Return state with no state transision */ - *buf[0] = usbdfu_state; - *len = 1; - return 1; - } - - return 0; -} - -int main(void) -{ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); - if(!gpio_get(GPIOA, GPIO10)) { - /* Boot the application if it's valid */ - if((*(volatile u32*)APP_ADDRESS & 0x2FFE0000) == 0x20000000) { - /* Set vector table base address */ - SCB_VTOR = APP_ADDRESS & 0xFFFF; - /* Initialise master stack pointer */ - asm volatile ("msr msp, %0"::"g" - (*(volatile u32*)APP_ADDRESS)); - /* Jump to application */ - (*(void(**)())(APP_ADDRESS + 4))(); - } - } - - rcc_clock_setup_in_hsi_out_48mhz(); - - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_AFIOEN); - - AFIO_MAPR |= AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_ON; - gpio_set_mode(GPIOA, GPIO_MODE_INPUT, 0, GPIO15); - - usbd_init(&stm32f103_usb_driver, &dev, &config, usb_strings); - usbd_set_control_buffer_size(sizeof(usbd_control_buffer)); - usbd_register_control_callback( - USB_REQ_TYPE_CLASS | USB_REQ_TYPE_INTERFACE, - USB_REQ_TYPE_TYPE | USB_REQ_TYPE_RECIPIENT, - usbdfu_control_request); - - gpio_set(GPIOA, GPIO15); - gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_2_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO15); - - while (1) - usbd_poll(); -} diff --git a/examples/stm32/stm32-h103/usb_iap/usbiap.ld b/examples/stm32/stm32-h103/usb_iap/usbiap.ld deleted file mode 100644 index 928c898..0000000 --- a/examples/stm32/stm32-h103/usb_iap/usbiap.ld +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* Linker script for Olimex STM32-H103 (STM32F103RBT6, 128K flash, 20K RAM). */ - -/* Define memory regions. */ -MEMORY -{ - rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K -} - -/* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld - diff --git a/examples/stm32/stm32-h107/fancyblink/Makefile b/examples/stm32/stm32-h107/fancyblink/Makefile deleted file mode 100644 index 1baec4d..0000000 --- a/examples/stm32/stm32-h107/fancyblink/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2009 Uwe Hermann -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program. If not, see . -## - -BINARY = fancyblink - -include ../../Makefile.include - diff --git a/examples/stm32/stm32-h107/fancyblink/README b/examples/stm32/stm32-h107/fancyblink/README deleted file mode 100644 index 6f1ac39..0000000 --- a/examples/stm32/stm32-h107/fancyblink/README +++ /dev/null @@ -1,10 +0,0 @@ ------------------------------------------------------------------------------- -README ------------------------------------------------------------------------------- - -This is small LED blinking example program using libopencm3. - -It's intended for the ST STM32-based Olimex STM32-H107 eval board (see -http://olimex.com/dev/stm32-h107.html for details). It should blink -the LED on the board. - diff --git a/examples/stm32/stm32-h107/fancyblink/fancyblink.c b/examples/stm32/stm32-h107/fancyblink/fancyblink.c deleted file mode 100644 index c73d3d4..0000000 --- a/examples/stm32/stm32-h107/fancyblink/fancyblink.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * Copyright (c) 2011 Damjan Marion - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include - -/* Set STM32 to 72 MHz. */ -void clock_setup(void) -{ - rcc_clock_setup_in_hse_8mhz_out_72mhz(); - - /* Enable GPIOC clock. */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); -} - -void gpio_setup(void) -{ - /* Set GPIO6/7 (in GPIO port C) to 'output push-pull'. */ - gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO6); - gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO7); -} - -int main(void) -{ - int i; - - clock_setup(); - gpio_setup(); - - /* Blink the LEDs (PC6 and PC7) on the board. */ - while (1) { - gpio_toggle(GPIOC, GPIO6); /* STAT1 LED on/off */ - gpio_toggle(GPIOC, GPIO7); /* STAT2 LED on/off */ - for (i = 0; i < 8000000; i++) /* Wait a bit. */ - __asm__("nop"); - } - - return 0; -} diff --git a/examples/stm32/stm32-h107/fancyblink/fancyblink.ld b/examples/stm32/stm32-h107/fancyblink/fancyblink.ld deleted file mode 100644 index 6c9c766..0000000 --- a/examples/stm32/stm32-h107/fancyblink/fancyblink.ld +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* Linker script for Olimex STM32-H107 (STM32F107VCT6, 256K flash, 64K RAM). */ - -/* Define memory regions. */ -MEMORY -{ - rom (rx) : ORIGIN = 0x08000000, LENGTH = 256K - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K -} - -/* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld - diff --git a/examples/stm32/stm32-h107/usb_simple/Makefile b/examples/stm32/stm32-h107/usb_simple/Makefile deleted file mode 100644 index 2d954e2..0000000 --- a/examples/stm32/stm32-h107/usb_simple/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2009 Uwe Hermann -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program. If not, see . -## - -BINARY = usb_simple - -include ../../Makefile.include - diff --git a/examples/stm32/stm32-h107/usb_simple/README b/examples/stm32/stm32-h107/usb_simple/README deleted file mode 100644 index 93d4f03..0000000 --- a/examples/stm32/stm32-h107/usb_simple/README +++ /dev/null @@ -1,10 +0,0 @@ ------------------------------------------------------------------------------- -README ------------------------------------------------------------------------------- - -This is small USB controlled LED blinking example program using libopencm3. - -It's intended for the ST STM32-based Olimex STM32-H107 eval board (see -http://olimex.com/dev/stm32-h107.html for details). The usbtest.py -script in this directory maybe used to control the LED. - diff --git a/examples/stm32/stm32-h107/usb_simple/usb_simple.c b/examples/stm32/stm32-h107/usb_simple/usb_simple.c deleted file mode 100644 index 85f67df..0000000 --- a/examples/stm32/stm32-h107/usb_simple/usb_simple.c +++ /dev/null @@ -1,117 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Gareth McMullin - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include - -#include - -const struct usb_device_descriptor dev = { - .bLength = USB_DT_DEVICE_SIZE, - .bDescriptorType = USB_DT_DEVICE, - .bcdUSB = 0x0200, - .bDeviceClass = 0xFF, - .bDeviceSubClass = 0, - .bDeviceProtocol = 0, - .bMaxPacketSize0 = 64, - .idVendor = 0xCAFE, - .idProduct = 0xCAFE, - .bcdDevice = 0x0200, - .iManufacturer = 1, - .iProduct = 2, - .iSerialNumber = 3, - .bNumConfigurations = 1, -}; - -const struct usb_interface_descriptor iface = { - .bLength = USB_DT_INTERFACE_SIZE, - .bDescriptorType = USB_DT_INTERFACE, - .bInterfaceNumber = 0, - .bAlternateSetting = 0, - .bNumEndpoints = 0, - .bInterfaceClass = 0xFF, - .bInterfaceSubClass = 0, - .bInterfaceProtocol = 0, - .iInterface = 0, -}; - -const struct usb_interface ifaces[] = {{ - .num_altsetting = 1, - .altsetting = &iface, -}}; - -const struct usb_config_descriptor config = { - .bLength = USB_DT_CONFIGURATION_SIZE, - .bDescriptorType = USB_DT_CONFIGURATION, - .wTotalLength = 0, - .bNumInterfaces = 1, - .bConfigurationValue = 1, - .iConfiguration = 0, - .bmAttributes = 0x80, - .bMaxPower = 0x32, - - .interface = ifaces, -}; - -const char *usb_strings[] = { - "x", - "Black Sphere Technologies", - "Simple Device", - "1001" -}; - -static int simple_control_callback(struct usb_setup_data *req, u8 **buf, - u16 *len, void (**complete)(struct usb_setup_data *req)) -{ - (void)buf; - (void)len; - (void)complete; - - if(req->bmRequestType != 0x40) - return 0; /* Only accept vendor request */ - - if(req->wValue & 1) - gpio_set(GPIOC, GPIO6); - else - gpio_clear(GPIOC, GPIO6); - - return 1; -} - -int main(void) -{ - rcc_clock_setup_in_hse_8mhz_out_72mhz(); - - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); - - /* LED output */ - gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_2_MHZ, - GPIO_CNF_OUTPUT_PUSHPULL, GPIO6); - - usbd_init(&stm32f107_usb_driver, &dev, &config, usb_strings); - usbd_register_control_callback( - USB_REQ_TYPE_VENDOR, - USB_REQ_TYPE_TYPE, - simple_control_callback); - - while (1) - usbd_poll(); -} - diff --git a/examples/stm32/stm32-h107/usb_simple/usb_simple.ld b/examples/stm32/stm32-h107/usb_simple/usb_simple.ld deleted file mode 100644 index 6c9c766..0000000 --- a/examples/stm32/stm32-h107/usb_simple/usb_simple.ld +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* Linker script for Olimex STM32-H107 (STM32F107VCT6, 256K flash, 64K RAM). */ - -/* Define memory regions. */ -MEMORY -{ - rom (rx) : ORIGIN = 0x08000000, LENGTH = 256K - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K -} - -/* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld - diff --git a/examples/stm32f1/Makefile.include b/examples/stm32f1/Makefile.include new file mode 100644 index 0000000..221ebae --- /dev/null +++ b/examples/stm32f1/Makefile.include @@ -0,0 +1,127 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## Copyright (C) 2010 Piotr Esden-Tempski +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +## + +PREFIX ?= arm-none-eabi +#PREFIX ?= arm-elf +CC = $(PREFIX)-gcc +LD = $(PREFIX)-gcc +OBJCOPY = $(PREFIX)-objcopy +OBJDUMP = $(PREFIX)-objdump +# Uncomment this line if you want to use the installed (not local) library. +TOOLCHAIN_DIR := $(shell dirname `which $(CC)`)/../$(PREFIX) +#TOOLCHAIN_DIR = ../../../.. +CFLAGS += -Os -g -Wall -Wextra -I$(TOOLCHAIN_DIR)/include \ + -fno-common -mcpu=cortex-m3 -mthumb -msoft-float -MD +LDSCRIPT = $(BINARY).ld +LDFLAGS += -lc -lnosys -L$(TOOLCHAIN_DIR)/lib -L$(TOOLCHAIN_DIR)/lib/stm32 \ + -T$(LDSCRIPT) -nostartfiles -Wl,--gc-sections \ + -mthumb -march=armv7 -mfix-cortex-m3-ldrd -msoft-float +OBJS += $(BINARY).o + +OOCD ?= openocd +OOCD_INTERFACE ?= flossjtag +OOCD_BOARD ?= olimex_stm32_h103 + +# Be silent per default, but 'make V=1' will show all compiler calls. +ifneq ($(V),1) +Q := @ +NULL := 2>/dev/null +else +LDFLAGS += -Wl,--print-gc-sections +endif + +.SUFFIXES: .elf .bin .hex .srec .list .images +.SECONDEXPANSION: +.SECONDARY: + +all: images + +images: $(BINARY).images +flash: $(BINARY).flash + +%.images: %.bin %.hex %.srec %.list + @#echo "*** $* images generated ***" + +%.bin: %.elf + @#printf " OBJCOPY $(*).bin\n" + $(Q)$(OBJCOPY) -Obinary $(*).elf $(*).bin + +%.hex: %.elf + @#printf " OBJCOPY $(*).hex\n" + $(Q)$(OBJCOPY) -Oihex $(*).elf $(*).hex + +%.srec: %.elf + @#printf " OBJCOPY $(*).srec\n" + $(Q)$(OBJCOPY) -Osrec $(*).elf $(*).srec + +%.list: %.elf + @#printf " OBJDUMP $(*).list\n" + $(Q)$(OBJDUMP) -S $(*).elf > $(*).list + +foo.elf: $(OBJS) $(LDSCRIPT) $(TOOLCHAIN_DIR)/lib/libopencm3_stm32.a + @#printf " LD $(subst $(shell pwd)/,,$(@))\n" + $(Q)$(LD) -o foo.elf $(OBJS) -lopencm3_stm32 $(LDFLAGS) + +%.elf: $(OBJS) $(LDSCRIPT) $(TOOLCHAIN_DIR)/lib/libopencm3_stm32.a + @#printf " LD $(subst $(shell pwd)/,,$(@))\n" + $(Q)$(LD) -o $(*).elf $(OBJS) -lopencm3_stm32 $(LDFLAGS) + +%.o: %.c Makefile + @#printf " CC $(subst $(shell pwd)/,,$(@))\n" + $(Q)$(CC) $(CFLAGS) -o $@ -c $< + +clean: + $(Q)rm -f *.o + $(Q)rm -f *.d + $(Q)rm -f *.elf + $(Q)rm -f *.bin + $(Q)rm -f *.hex + $(Q)rm -f *.srec + $(Q)rm -f *.list + +ifeq ($(OOCD_SERIAL),) +%.flash: %.hex + @printf " FLASH $<\n" + @# IMPORTANT: Don't use "resume", only "reset" will work correctly! + $(Q)$(OOCD) -f interface/$(OOCD_INTERFACE).cfg \ + -f board/$(OOCD_BOARD).cfg \ + -c "init" -c "reset init" \ + -c "stm32x mass_erase 0" \ + -c "flash write_image $(*).hex" \ + -c "reset" \ + -c "shutdown" $(NULL) +else +%.flash: %.hex + @printf " FLASH $<\n" + @# IMPORTANT: Don't use "resume", only "reset" will work correctly! + $(Q)$(OOCD) -f interface/$(OOCD_INTERFACE).cfg \ + -f board/$(OOCD_BOARD).cfg \ + -c "ft2232_serial $(OOCD_SERIAL)" \ + -c "init" -c "reset init" \ + -c "stm32x mass_erase 0" \ + -c "flash write_image $(*).hex" \ + -c "reset" \ + -c "shutdown" $(NULL) +endif + +.PHONY: images clean + +-include $(OBJS:.o=.d) + diff --git a/examples/stm32f1/lisa-m/fancyblink/Makefile b/examples/stm32f1/lisa-m/fancyblink/Makefile new file mode 100644 index 0000000..1baec4d --- /dev/null +++ b/examples/stm32f1/lisa-m/fancyblink/Makefile @@ -0,0 +1,23 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +## + +BINARY = fancyblink + +include ../../Makefile.include + diff --git a/examples/stm32f1/lisa-m/fancyblink/fancyblink.c b/examples/stm32f1/lisa-m/fancyblink/fancyblink.c new file mode 100644 index 0000000..5987bdf --- /dev/null +++ b/examples/stm32f1/lisa-m/fancyblink/fancyblink.c @@ -0,0 +1,67 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * Copyright (C) 2011 Piotr Esden-Tempski + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include + +/* Set STM32 to 72 MHz. */ +void clock_setup(void) +{ + rcc_clock_setup_in_hse_12mhz_out_72mhz(); + + /* Enable GPIOC clock. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPBEN); + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_AFIOEN); + +} + +void gpio_setup(void) +{ + /* Set GPIO12 (in GPIO port C) to 'output push-pull'. */ + gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO13); + gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO4); + + AFIO_MAPR |= AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_JNTRST; + + /* preconfigure the led's */ + gpio_set(GPIOB, GPIO4); /* switch off led */ + gpio_clear(GPIOC, GPIO13); /* switch on led */ +} + +int main(void) +{ + int i; + + clock_setup(); + gpio_setup(); + + /* Blink the LED (PC12) on the board. */ + while (1) { + gpio_toggle(GPIOC, GPIO13); /* LED on/off */ + gpio_toggle(GPIOB, GPIO4); /* LED on/off */ + for (i = 0; i < 800000; i++) /* Wait a bit. */ + __asm__("nop"); + } + + return 0; +} diff --git a/examples/stm32f1/lisa-m/fancyblink/fancyblink.ld b/examples/stm32f1/lisa-m/fancyblink/fancyblink.ld new file mode 100644 index 0000000..7ea2b92 --- /dev/null +++ b/examples/stm32f1/lisa-m/fancyblink/fancyblink.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Linker script for Olimex STM32-H103 (STM32F103RBT6, 128K flash, 20K RAM). */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32.ld + diff --git a/examples/stm32f1/lisa-m/usb_dfu/Makefile b/examples/stm32f1/lisa-m/usb_dfu/Makefile new file mode 100644 index 0000000..48e2d6b --- /dev/null +++ b/examples/stm32f1/lisa-m/usb_dfu/Makefile @@ -0,0 +1,23 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +## + +BINARY = usbdfu + +include ../../Makefile.include + diff --git a/examples/stm32f1/lisa-m/usb_dfu/README b/examples/stm32f1/lisa-m/usb_dfu/README new file mode 100644 index 0000000..9c0169a --- /dev/null +++ b/examples/stm32f1/lisa-m/usb_dfu/README @@ -0,0 +1,7 @@ +------------------------------------------------------------------------------ +README +------------------------------------------------------------------------------ + +This example implements a USB Device Firmware Upgrade (DFU) bootloader +to demonstrate the use of the USB device stack. + diff --git a/examples/stm32f1/lisa-m/usb_dfu/usbdfu.c b/examples/stm32f1/lisa-m/usb_dfu/usbdfu.c new file mode 100644 index 0000000..7ffbc74 --- /dev/null +++ b/examples/stm32f1/lisa-m/usb_dfu/usbdfu.c @@ -0,0 +1,270 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Gareth McMullin + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include +#include +#include + +#define APP_ADDRESS 0x08002000 + +/* Commands sent with wBlockNum == 0 as per ST implementation. */ +#define CMD_SETADDR 0x21 +#define CMD_ERASE 0x41 + +/* We need a special large control buffer for this device: */ +u8 usbd_control_buffer[1024]; + +static enum dfu_state usbdfu_state = STATE_DFU_IDLE; + +static struct { + u8 buf[sizeof(usbd_control_buffer)]; + u16 len; + u32 addr; + u16 blocknum; +} prog; + +const struct usb_device_descriptor dev = { + .bLength = USB_DT_DEVICE_SIZE, + .bDescriptorType = USB_DT_DEVICE, + .bcdUSB = 0x0200, + .bDeviceClass = 0, + .bDeviceSubClass = 0, + .bDeviceProtocol = 0, + .bMaxPacketSize0 = 64, + .idVendor = 0x0483, + .idProduct = 0xDF11, + .bcdDevice = 0x0200, + .iManufacturer = 1, + .iProduct = 2, + .iSerialNumber = 3, + .bNumConfigurations = 1, +}; + +const struct usb_dfu_descriptor dfu_function = { + .bLength = sizeof(struct usb_dfu_descriptor), + .bDescriptorType = DFU_FUNCTIONAL, + .bmAttributes = USB_DFU_CAN_DOWNLOAD | USB_DFU_WILL_DETACH, + .wDetachTimeout = 255, + .wTransferSize = 1024, + .bcdDFUVersion = 0x011A, +}; + +const struct usb_interface_descriptor iface = { + .bLength = USB_DT_INTERFACE_SIZE, + .bDescriptorType = USB_DT_INTERFACE, + .bInterfaceNumber = 0, + .bAlternateSetting = 0, + .bNumEndpoints = 0, + .bInterfaceClass = 0xFE, /* Device Firmware Upgrade */ + .bInterfaceSubClass = 1, + .bInterfaceProtocol = 2, + + /* The ST Microelectronics DfuSe application needs this string. + * The format isn't documented... */ + .iInterface = 4, + + .extra = &dfu_function, + .extralen = sizeof(dfu_function), +}; + +const struct usb_interface ifaces[] = {{ + .num_altsetting = 1, + .altsetting = &iface, +}}; + +const struct usb_config_descriptor config = { + .bLength = USB_DT_CONFIGURATION_SIZE, + .bDescriptorType = USB_DT_CONFIGURATION, + .wTotalLength = 0, + .bNumInterfaces = 1, + .bConfigurationValue = 1, + .iConfiguration = 0, + .bmAttributes = 0xC0, + .bMaxPower = 0x32, + + .interface = ifaces, +}; + +static const char *usb_strings[] = { + "x", + "Black Sphere Technologies", + "DFU Demo", + "DEMO", + /* This string is used by ST Microelectronics' DfuSe utility */ + "@Internal Flash /0x08000000/8*001Ka,56*001Kg" +}; + +static u8 usbdfu_getstatus(u32 *bwPollTimeout) +{ + switch(usbdfu_state) { + case STATE_DFU_DNLOAD_SYNC: + usbdfu_state = STATE_DFU_DNBUSY; + *bwPollTimeout = 100; + return DFU_STATUS_OK; + + case STATE_DFU_MANIFEST_SYNC: + /* Device will reset when read is complete */ + usbdfu_state = STATE_DFU_MANIFEST; + return DFU_STATUS_OK; + + default: + return DFU_STATUS_OK; + } +} + +static void usbdfu_getstatus_complete(struct usb_setup_data *req) +{ + int i; + (void)req; + + switch(usbdfu_state) { + case STATE_DFU_DNBUSY: + + flash_unlock(); + if(prog.blocknum == 0) { + switch(prog.buf[0]) { + case CMD_ERASE: + flash_erase_page(*(u32*)(prog.buf+1)); + case CMD_SETADDR: + prog.addr = *(u32*)(prog.buf+1); + } + } else { + u32 baseaddr = prog.addr + + ((prog.blocknum - 2) * + dfu_function.wTransferSize); + for(i = 0; i < prog.len; i += 2) + flash_program_half_word(baseaddr + i, + *(u16*)(prog.buf+i)); + } + flash_lock(); + + /* We jump straight to dfuDNLOAD-IDLE, + * skipping dfuDNLOAD-SYNC + */ + usbdfu_state = STATE_DFU_DNLOAD_IDLE; + return; + + case STATE_DFU_MANIFEST: + /* USB device must detach, we just reset... */ + scb_reset_system(); + return; /* Will never return */ + default: + return; + } +} + +static int usbdfu_control_request(struct usb_setup_data *req, u8 **buf, + u16 *len, void (**complete)(struct usb_setup_data *req)) +{ + + if((req->bmRequestType & 0x7F) != 0x21) + return 0; /* Only accept class request */ + + switch(req->bRequest) { + case DFU_DNLOAD: + if((len == NULL) || (*len == 0)) { + usbdfu_state = STATE_DFU_MANIFEST_SYNC; + return 1; + } else { + /* Copy download data for use on GET_STATUS */ + prog.blocknum = req->wValue; + prog.len = *len; + memcpy(prog.buf, *buf, *len); + usbdfu_state = STATE_DFU_DNLOAD_SYNC; + return 1; + } + case DFU_CLRSTATUS: + /* Clear error and return to dfuIDLE */ + if(usbdfu_state == STATE_DFU_ERROR) + usbdfu_state = STATE_DFU_IDLE; + return 1; + case DFU_ABORT: + /* Abort returns to dfuIDLE state */ + usbdfu_state = STATE_DFU_IDLE; + return 1; + case DFU_UPLOAD: + /* Upload not supported for now */ + return 0; + case DFU_GETSTATUS: { + u32 bwPollTimeout = 0; /* 24-bit integer in DFU class spec */ + + (*buf)[0] = usbdfu_getstatus(&bwPollTimeout); + (*buf)[1] = bwPollTimeout & 0xFF; + (*buf)[2] = (bwPollTimeout >> 8) & 0xFF; + (*buf)[3] = (bwPollTimeout >> 16) & 0xFF; + (*buf)[4] = usbdfu_state; + (*buf)[5] = 0; /* iString not used here */ + *len = 6; + + *complete = usbdfu_getstatus_complete; + + return 1; + } + case DFU_GETSTATE: + /* Return state with no state transision */ + *buf[0] = usbdfu_state; + *len = 1; + return 1; + } + + return 0; +} + +int main(void) +{ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); + if(!gpio_get(GPIOA, GPIO10)) { + /* Boot the application if it's valid */ + if((*(volatile u32*)APP_ADDRESS & 0x2FFE0000) == 0x20000000) { + /* Set vector table base address */ + SCB_VTOR = APP_ADDRESS & 0xFFFF; + /* Initialise master stack pointer */ + asm volatile ("msr msp, %0"::"g" + (*(volatile u32*)APP_ADDRESS)); + /* Jump to application */ + (*(void(**)())(APP_ADDRESS + 4))(); + } + } + + rcc_clock_setup_in_hsi_out_48mhz(); + + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_AFIOEN); + + AFIO_MAPR |= AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_ON; + gpio_set_mode(GPIOA, GPIO_MODE_INPUT, 0, GPIO15); + + usbd_init(&stm32f103_usb_driver, &dev, &config, usb_strings); + usbd_set_control_buffer_size(sizeof(usbd_control_buffer)); + usbd_register_control_callback( + USB_REQ_TYPE_CLASS | USB_REQ_TYPE_INTERFACE, + USB_REQ_TYPE_TYPE | USB_REQ_TYPE_RECIPIENT, + usbdfu_control_request); + + gpio_set(GPIOA, GPIO15); + gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_2_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO15); + + while (1) + usbd_poll(); +} diff --git a/examples/stm32f1/lisa-m/usb_dfu/usbdfu.ld b/examples/stm32f1/lisa-m/usb_dfu/usbdfu.ld new file mode 100644 index 0000000..54e5dac --- /dev/null +++ b/examples/stm32f1/lisa-m/usb_dfu/usbdfu.ld @@ -0,0 +1,29 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 8K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 4K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32.ld + diff --git a/examples/stm32f1/lisa-m/usb_hid/Makefile b/examples/stm32f1/lisa-m/usb_hid/Makefile new file mode 100644 index 0000000..d831e9e --- /dev/null +++ b/examples/stm32f1/lisa-m/usb_hid/Makefile @@ -0,0 +1,23 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +## + +BINARY = usbhid + +include ../../Makefile.include + diff --git a/examples/stm32f1/lisa-m/usb_hid/README b/examples/stm32f1/lisa-m/usb_hid/README new file mode 100644 index 0000000..48a9b39 --- /dev/null +++ b/examples/stm32f1/lisa-m/usb_hid/README @@ -0,0 +1,7 @@ +------------------------------------------------------------------------------ +README +------------------------------------------------------------------------------ + +This example implements a USB Human Interface Device (HID) +to demonstrate the use of the USB device stack. + diff --git a/examples/stm32f1/lisa-m/usb_hid/usbhid.c b/examples/stm32f1/lisa-m/usb_hid/usbhid.c new file mode 100644 index 0000000..f42454b --- /dev/null +++ b/examples/stm32f1/lisa-m/usb_hid/usbhid.c @@ -0,0 +1,289 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Gareth McMullin + * Copyright (C) 2011 Piotr Esden-Tempski + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include +#include +#include + +/* Define this to include the DFU APP interface. */ +#define INCLUDE_DFU_INTERFACE + +#ifdef INCLUDE_DFU_INTERFACE +#include +#include +#endif + +const struct usb_device_descriptor dev = { + .bLength = USB_DT_DEVICE_SIZE, + .bDescriptorType = USB_DT_DEVICE, + .bcdUSB = 0x0200, + .bDeviceClass = 0, + .bDeviceSubClass = 0, + .bDeviceProtocol = 0, + .bMaxPacketSize0 = 64, + .idVendor = 0x0483, + .idProduct = 0x5710, + .bcdDevice = 0x0200, + .iManufacturer = 1, + .iProduct = 2, + .iSerialNumber = 3, + .bNumConfigurations = 1, +}; + +/* I have no idea what this means. I haven't read the HID spec. */ +static const u8 hid_report_descriptor[] = { + 0x05, 0x01, 0x09, 0x02, 0xA1, 0x01, 0x09, 0x01, + 0xA1, 0x00, 0x05, 0x09, 0x19, 0x01, 0x29, 0x03, + 0x15, 0x00, 0x25, 0x01, 0x95, 0x03, 0x75, 0x01, + 0x81, 0x02, 0x95, 0x01, 0x75, 0x05, 0x81, 0x01, + 0x05, 0x01, 0x09, 0x30, 0x09, 0x31, 0x09, 0x38, + 0x15, 0x81, 0x25, 0x7F, 0x75, 0x08, 0x95, 0x03, + 0x81, 0x06, 0xC0, 0x09, 0x3c, 0x05, 0xff, 0x09, + 0x01, 0x15, 0x00, 0x25, 0x01, 0x75, 0x01, 0x95, + 0x02, 0xb1, 0x22, 0x75, 0x06, 0x95, 0x01, 0xb1, + 0x01, 0xc0 +}; + +static const struct { + struct usb_hid_descriptor hid_descriptor; + struct { + u8 bReportDescriptorType; + u16 wDescriptorLength; + } __attribute__((packed)) hid_report; +} __attribute__((packed)) hid_function = { + .hid_descriptor = { + .bLength = sizeof(hid_function), + .bDescriptorType = USB_DT_HID, + .bcdHID = 0x0100, + .bCountryCode = 0, + .bNumDescriptors = 1, + }, + .hid_report = { + .bReportDescriptorType = USB_DT_REPORT, + .wDescriptorLength = sizeof(hid_report_descriptor), + } +}; + +const struct usb_endpoint_descriptor hid_endpoint = { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = 0x81, + .bmAttributes = USB_ENDPOINT_ATTR_INTERRUPT, + .wMaxPacketSize = 4, + .bInterval = 0x20, +}; + +const struct usb_interface_descriptor hid_iface = { + .bLength = USB_DT_INTERFACE_SIZE, + .bDescriptorType = USB_DT_INTERFACE, + .bInterfaceNumber = 0, + .bAlternateSetting = 0, + .bNumEndpoints = 1, + .bInterfaceClass = USB_CLASS_HID, + .bInterfaceSubClass = 1, /* boot */ + .bInterfaceProtocol = 2, /* mouse */ + .iInterface = 0, + + .endpoint = &hid_endpoint, + + .extra = &hid_function, + .extralen = sizeof(hid_function), +}; + +#ifdef INCLUDE_DFU_INTERFACE +const struct usb_dfu_descriptor dfu_function = { + .bLength = sizeof(struct usb_dfu_descriptor), + .bDescriptorType = DFU_FUNCTIONAL, + .bmAttributes = USB_DFU_CAN_DOWNLOAD | USB_DFU_WILL_DETACH, + .wDetachTimeout = 255, + .wTransferSize = 1024, + .bcdDFUVersion = 0x011A, +}; + +const struct usb_interface_descriptor dfu_iface = { + .bLength = USB_DT_INTERFACE_SIZE, + .bDescriptorType = USB_DT_INTERFACE, + .bInterfaceNumber = 1, + .bAlternateSetting = 0, + .bNumEndpoints = 0, + .bInterfaceClass = 0xFE, + .bInterfaceSubClass = 1, + .bInterfaceProtocol = 1, + .iInterface = 0, + + .extra = &dfu_function, + .extralen = sizeof(dfu_function), +}; +#endif + +const struct usb_interface ifaces[] = {{ + .num_altsetting = 1, + .altsetting = &hid_iface, +#ifdef INCLUDE_DFU_INTERFACE +}, { + .num_altsetting = 1, + .altsetting = &dfu_iface, +#endif +}}; + +const struct usb_config_descriptor config = { + .bLength = USB_DT_CONFIGURATION_SIZE, + .bDescriptorType = USB_DT_CONFIGURATION, + .wTotalLength = 0, +#ifdef INCLUDE_DFU_INTERFACE + .bNumInterfaces = 2, +#else + .bNumInterfaces = 1, +#endif + .bConfigurationValue = 1, + .iConfiguration = 0, + .bmAttributes = 0xC0, + .bMaxPower = 0x32, + + .interface = ifaces, +}; + +static const char *usb_strings[] = { + "x", + "Black Sphere Technologies", + "HID Demo", + "DEMO", +}; + +static int hid_control_request(struct usb_setup_data *req, u8 **buf, u16 *len, + void (**complete)(struct usb_setup_data *req)) +{ + (void)complete; + + if((req->bmRequestType != 0x81) || + (req->bRequest != USB_REQ_GET_DESCRIPTOR) || + (req->wValue != 0x2200)) + return 0; + + /* Handle the HID report descriptor */ + *buf = (u8*)hid_report_descriptor; + *len = sizeof(hid_report_descriptor); + + return 1; +} + +#ifdef INCLUDE_DFU_INTERFACE +static void dfu_detach_complete(struct usb_setup_data *req) +{ + (void)req; + + gpio_set_mode(GPIOA, GPIO_MODE_INPUT, 0, GPIO15); + gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_2_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO10); + gpio_set(GPIOA, GPIO10); + scb_reset_core(); +} + +static int dfu_control_request(struct usb_setup_data *req, u8 **buf, u16 *len, + void (**complete)(struct usb_setup_data *req)) +{ + (void)buf; + (void)len; + + if((req->bmRequestType != 0x21) || (req->bRequest != DFU_DETACH)) + return 0; /* Only accept class request */ + + *complete = dfu_detach_complete; + + return 1; +} +#endif + +static void hid_set_config(u16 wValue) +{ + (void)wValue; + + usbd_ep_setup(0x81, USB_ENDPOINT_ATTR_INTERRUPT, 4, NULL); + + usbd_register_control_callback( + USB_REQ_TYPE_STANDARD | USB_REQ_TYPE_INTERFACE, + USB_REQ_TYPE_TYPE | USB_REQ_TYPE_RECIPIENT, + hid_control_request); +#ifdef INCLUDE_DFU_INTERFACE + usbd_register_control_callback( + USB_REQ_TYPE_CLASS | USB_REQ_TYPE_INTERFACE, + USB_REQ_TYPE_TYPE | USB_REQ_TYPE_RECIPIENT, + dfu_control_request); +#endif + + systick_set_clocksource(STK_CTRL_CLKSOURCE_AHB_DIV8); + systick_set_reload(100000); + systick_interrupt_enable(); + systick_counter_enable(); +} + +int main(void) +{ + int usb_connect_blink = 0; + rcc_clock_setup_in_hse_12mhz_out_72mhz(); + + + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); + + /* USB_DETECT as input */ + gpio_set_mode(GPIOA, GPIO_MODE_INPUT, + GPIO_CNF_INPUT_FLOAT, GPIO8); + + /* green LED off, as output */ + gpio_set(GPIOC, GPIO2); + gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_2_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO2); + + + usbd_init(&stm32f107_usb_driver, &dev, &config, usb_strings); + usbd_register_set_config_callback(hid_set_config); + + /* delay some seconds to show that pull-up switch works */ + {int i; for (i=0;i<0x800000;i++) asm("nop");} + + /* wait for USB Vbus */ + while(gpio_get(GPIOA, GPIO8) == 0) asm("nop"); + + /* green LED on, connect USB */ + gpio_clear(GPIOC, GPIO2); + //OTG_FS_GCCFG &= ~OTG_FS_GCCFG_VBUSBSEN; + + while (1) + usbd_poll(); +} + +void sys_tick_handler(void) +{ + static int x = 0; + static int dir = 1; + u8 buf[4] = {0, 0, 0, 0}; + + buf[1] = dir; + x += dir; + if(x > 30) dir = -dir; + if(x < -30) dir = -dir; + + usbd_ep_write_packet(0x81, buf, 4); +} diff --git a/examples/stm32f1/lisa-m/usb_hid/usbhid.ld b/examples/stm32f1/lisa-m/usb_hid/usbhid.ld new file mode 100644 index 0000000..928c898 --- /dev/null +++ b/examples/stm32f1/lisa-m/usb_hid/usbhid.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Linker script for Olimex STM32-H103 (STM32F103RBT6, 128K flash, 20K RAM). */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32.ld + diff --git a/examples/stm32f1/mb525/fancyblink/Makefile b/examples/stm32f1/mb525/fancyblink/Makefile new file mode 100644 index 0000000..1baec4d --- /dev/null +++ b/examples/stm32f1/mb525/fancyblink/Makefile @@ -0,0 +1,23 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +## + +BINARY = fancyblink + +include ../../Makefile.include + diff --git a/examples/stm32f1/mb525/fancyblink/README b/examples/stm32f1/mb525/fancyblink/README new file mode 100644 index 0000000..226cb21 --- /dev/null +++ b/examples/stm32f1/mb525/fancyblink/README @@ -0,0 +1,10 @@ +------------------------------------------------------------------------------ +README +------------------------------------------------------------------------------ + +This is a blink example program using libopencm3. + +It's intended for the ST STM32-based MB525 eval board (see +http://www.st.com/stonline/products/literature/um/13472.htm for details). +It should blink the LED on the board. + diff --git a/examples/stm32f1/mb525/fancyblink/fancyblink.c b/examples/stm32f1/mb525/fancyblink/fancyblink.c new file mode 100644 index 0000000..e9a3564 --- /dev/null +++ b/examples/stm32f1/mb525/fancyblink/fancyblink.c @@ -0,0 +1,76 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann , + * Copyright (C) 2010 Piotr Esden-Tempski + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include + +void clock_setup(void) +{ + rcc_clock_setup_in_hse_8mhz_out_72mhz(); + + /* Enable GPIOC clock. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); +} + +void gpio_setup(void) +{ + /* Set GPIO6 (in GPIO port C) to 'output push-pull'. */ + gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO6 | GPIO7 | GPIO8 | GPIO9); +} + +int main(void) +{ + int i; + + clock_setup(); + gpio_setup(); + + /* Blink the LED (PC12) on the board. */ + gpio_set(GPIOC, GPIO6); + while (1) { + gpio_toggle(GPIOC, GPIO6); /* LED on/off */ + gpio_toggle(GPIOC, GPIO7); /* LED on/off */ + for (i = 0; i < 4000000; i++) /* Wait a bit. */ + __asm__("nop"); + gpio_toggle(GPIOC, GPIO7); /* LED on/off */ + gpio_toggle(GPIOC, GPIO8); /* LED on/off */ + for (i = 0; i < 4000000; i++) /* Wait a bit. */ + __asm__("nop"); + gpio_toggle(GPIOC, GPIO8); /* LED on/off */ + gpio_toggle(GPIOC, GPIO9); /* LED on/off */ + for (i = 0; i < 4000000; i++) /* Wait a bit. */ + __asm__("nop"); + gpio_toggle(GPIOC, GPIO8); /* LED on/off */ + gpio_toggle(GPIOC, GPIO9); /* LED on/off */ + for (i = 0; i < 4000000; i++) /* Wait a bit. */ + __asm__("nop"); + gpio_toggle(GPIOC, GPIO7); /* LED on/off */ + gpio_toggle(GPIOC, GPIO8); /* LED on/off */ + for (i = 0; i < 4000000; i++) /* Wait a bit. */ + __asm__("nop"); + gpio_toggle(GPIOC, GPIO6); /* LED on/off */ + gpio_toggle(GPIOC, GPIO7); /* LED on/off */ + for (i = 0; i < 4000000; i++) /* Wait a bit. */ + __asm__("nop"); + } + + return 0; +} diff --git a/examples/stm32f1/mb525/fancyblink/fancyblink.ld b/examples/stm32f1/mb525/fancyblink/fancyblink.ld new file mode 100644 index 0000000..7ea2b92 --- /dev/null +++ b/examples/stm32f1/mb525/fancyblink/fancyblink.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Linker script for Olimex STM32-H103 (STM32F103RBT6, 128K flash, 20K RAM). */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32.ld + diff --git a/examples/stm32f1/mb525/pwmleds/Makefile b/examples/stm32f1/mb525/pwmleds/Makefile new file mode 100644 index 0000000..8ae74d6 --- /dev/null +++ b/examples/stm32f1/mb525/pwmleds/Makefile @@ -0,0 +1,23 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +## + +BINARY = pwmleds + +include ../../Makefile.include + diff --git a/examples/stm32f1/mb525/pwmleds/README b/examples/stm32f1/mb525/pwmleds/README new file mode 100644 index 0000000..b2a6d95 --- /dev/null +++ b/examples/stm32f1/mb525/pwmleds/README @@ -0,0 +1,10 @@ +------------------------------------------------------------------------------ +README +------------------------------------------------------------------------------ + +This is a PWM based LED fading example using libopencm3. + +It's intended for the ST STM32-based MB525 eval board (see +http://www.st.com/stonline/products/literature/um/13472.htm for details). +It should blink the LED on the board. + diff --git a/examples/stm32f1/mb525/pwmleds/pwmleds.c b/examples/stm32f1/mb525/pwmleds/pwmleds.c new file mode 100644 index 0000000..393928f --- /dev/null +++ b/examples/stm32f1/mb525/pwmleds/pwmleds.c @@ -0,0 +1,496 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Piotr Esden-Tempski + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include + +// #define COMPARE +// #define MOVING_FADE +#define KITT + +#ifdef COMPARE +#define GAMMA_LINEAR +#define GAMMA_1_3 +#define GAMMA_2_5 +#define GAMMA_3_0 +#endif + +#ifdef MOVING_FADE +#define GAMMA_2_2 +#define GAMMA_TABLE gamma_table_2_2 +#endif + +#ifdef KITT +#define GAMMA_2_5 +#define GAMMA_TABLE gamma_table_2_5 +#endif + +/* + * Gamma correction table + * + * The nonlinear tables are calculating with the function: + * Iout = Iin ** gamma + */ +#ifdef GAMMA_LINEAR +static const u16 gamma_table_linear[] = { + 1, 4, 9, 17, 26, 37, 51, 67, + 84, 104, 126, 149, 175, 203, 233, 265, + 299, 334, 372, 412, 454, 499, 545, 593, + 643, 695, 749, 805, 864, 924, 986, 1050, + 1116, 1185, 1255, 1327, 1402, 1478, 1556, 1637, + 1719, 1803, 1890, 1978, 2068, 2161, 2255, 2352, + 2450, 2550, 2653, 2757, 2864, 2972, 3082, 3195, + 3309, 3426, 3544, 3664, 3787, 3911, 4038, 4166, + 4296, 4429, 4563, 4700, 4838, 4978, 5121, 5265, + 5411, 5560, 5710, 5862, 6017, 6173, 6331, 6492, + 6654, 6818, 6985, 7153, 7323, 7495, 7670, 7846, + 8024, 8204, 8387, 8571, 8757, 8945, 9135, 9327, + 9521, 9718, 9916, 10116, 10318, 10522, 10728, 10936, + 11146, 11358, 11572, 11788, 12006, 12226, 12448, 12672, + 12897, 13125, 13355, 13587, 13821, 14057, 14294, 14534, + 14776, 15020, 15265, 15513, 15763, 16014, 16268, 16524, + 16781, 17041, 17302, 17566, 17831, 18099, 18368, 18640, + 18913, 19189, 19466, 19745, 20027, 20310, 20595, 20883, + 21172, 21463, 21756, 22051, 22349, 22648, 22949, 23252, + 23557, 23864, 24173, 24484, 24797, 25112, 25429, 25748, + 26069, 26391, 26716, 27043, 27372, 27702, 28035, 28370, + 28707, 29045, 29386, 29728, 30073, 30419, 30768, 31118, + 31471, 31825, 32182, 32540, 32900, 33263, 33627, 33993, + 34361, 34731, 35104, 35478, 35854, 36232, 36612, 36994, + 37378, 37764, 38152, 38542, 38933, 39327, 39723, 40121, + 40521, 40922, 41326, 41732, 42139, 42549, 42960, 43374, + 43789, 44207, 44626, 45048, 45471, 45896, 46324, 46753, + 47184, 47617, 48052, 48490, 48929, 49370, 49813, 50258, + 50705, 51154, 51604, 52057, 52512, 52969, 53428, 53888, + 54351, 54816, 55282, 55751, 56222, 56694, 57169, 57645, + 58123, 58604, 59086, 59570, 60057, 60545, 61035, 61527, + 62021, 62517, 63016, 63516, 64018, 64521, 65027, 65535, +}; +#endif + +#ifdef GAMMA_1_3 +static const u16 gamma_table_1_3[] = { + /* Gamma 1.3 */ + 0, 49, 120, 203, 296, 395, 501, 612, + 728, 848, 973, 1101, 1233, 1368, 1506, 1648, + 1792, 1939, 2088, 2241, 2395, 2552, 2711, 2872, + 3036, 3201, 3369, 3538, 3709, 3882, 4057, 4234, + 4412, 4592, 4774, 4957, 5142, 5329, 5517, 5706, + 5897, 6090, 6283, 6479, 6675, 6873, 7072, 7273, + 7475, 7678, 7882, 8088, 8294, 8502, 8711, 8922, + 9133, 9346, 9559, 9774, 9990, 10207, 10425, 10644, + 10864, 11086, 11308, 11531, 11755, 11981, 12207, 12434, + 12662, 12891, 13121, 13352, 13584, 13817, 14051, 14285, + 14521, 14757, 14994, 15233, 15472, 15712, 15952, 16194, + 16436, 16679, 16923, 17168, 17414, 17660, 17908, 18156, + 18405, 18654, 18905, 19156, 19408, 19660, 19914, 20168, + 20423, 20679, 20935, 21192, 21450, 21708, 21968, 22228, + 22488, 22750, 23012, 23275, 23538, 23802, 24067, 24332, + 24599, 24865, 25133, 25401, 25670, 25939, 26209, 26480, + 26751, 27023, 27296, 27569, 27843, 28118, 28393, 28669, + 28945, 29222, 29500, 29778, 30057, 30336, 30616, 30897, + 31178, 31460, 31742, 32025, 32308, 32592, 32877, 33162, + 33448, 33734, 34021, 34309, 34597, 34885, 35175, 35464, + 35754, 36045, 36337, 36628, 36921, 37214, 37507, 37801, + 38096, 38391, 38686, 38982, 39279, 39576, 39874, 40172, + 40471, 40770, 41070, 41370, 41670, 41972, 42273, 42576, + 42878, 43181, 43485, 43789, 44094, 44399, 44705, 45011, + 45317, 45625, 45932, 46240, 46549, 46858, 47167, 47477, + 47787, 48098, 48409, 48721, 49034, 49346, 49659, 49973, + 50287, 50602, 50917, 51232, 51548, 51864, 52181, 52498, + 52816, 53134, 53452, 53771, 54091, 54411, 54731, 55052, + 55373, 55694, 56016, 56339, 56662, 56985, 57309, 57633, + 57957, 58282, 58608, 58933, 59260, 59586, 59913, 60241, + 60569, 60897, 61226, 61555, 61884, 62214, 62545, 62875, + 63206, 63538, 63870, 64202, 64535, 64868, 65201, 65535, +}; +#endif + +#ifdef GAMMA_2_2 +static const u16 gamma_table_2_2[] = { + 0, 0, 2, 4, 7, 11, 17, 24, + 32, 42, 53, 65, 79, 94, 111, 129, + 148, 169, 192, 216, 242, 270, 299, 330, + 362, 396, 432, 469, 508, 549, 591, 635, + 681, 729, 779, 830, 883, 938, 995, 1053, + 1113, 1175, 1239, 1305, 1373, 1443, 1514, 1587, + 1663, 1740, 1819, 1900, 1983, 2068, 2155, 2243, + 2334, 2427, 2521, 2618, 2717, 2817, 2920, 3024, + 3131, 3240, 3350, 3463, 3578, 3694, 3813, 3934, + 4057, 4182, 4309, 4438, 4570, 4703, 4838, 4976, + 5115, 5257, 5401, 5547, 5695, 5845, 5998, 6152, + 6309, 6468, 6629, 6792, 6957, 7124, 7294, 7466, + 7640, 7816, 7994, 8175, 8358, 8543, 8730, 8919, + 9111, 9305, 9501, 9699, 9900, 10102, 10307, 10515, + 10724, 10936, 11150, 11366, 11585, 11806, 12029, 12254, + 12482, 12712, 12944, 13179, 13416, 13655, 13896, 14140, + 14386, 14635, 14885, 15138, 15394, 15652, 15912, 16174, + 16439, 16706, 16975, 17247, 17521, 17798, 18077, 18358, + 18642, 18928, 19216, 19507, 19800, 20095, 20393, 20694, + 20996, 21301, 21609, 21919, 22231, 22546, 22863, 23182, + 23504, 23829, 24156, 24485, 24817, 25151, 25487, 25826, + 26168, 26512, 26858, 27207, 27558, 27912, 28268, 28627, + 28988, 29351, 29717, 30086, 30457, 30830, 31206, 31585, + 31966, 32349, 32735, 33124, 33514, 33908, 34304, 34702, + 35103, 35507, 35913, 36321, 36732, 37146, 37562, 37981, + 38402, 38825, 39252, 39680, 40112, 40546, 40982, 41421, + 41862, 42306, 42753, 43202, 43654, 44108, 44565, 45025, + 45487, 45951, 46418, 46888, 47360, 47835, 48313, 48793, + 49275, 49761, 50249, 50739, 51232, 51728, 52226, 52727, + 53230, 53736, 54245, 54756, 55270, 55787, 56306, 56828, + 57352, 57879, 58409, 58941, 59476, 60014, 60554, 61097, + 61642, 62190, 62741, 63295, 63851, 64410, 64971, 65535 +}; +#endif + +#ifdef GAMMA_2_5 +static const u16 gamma_table_2_5[] = { + /* gamma = 2.5 */ + 0, 0, 0, 1, 2, 4, 6, 8, + 11, 15, 20, 25, 31, 38, 46, 55, + 65, 75, 87, 99, 113, 128, 143, 160, + 178, 197, 218, 239, 262, 286, 311, 338, + 366, 395, 425, 457, 491, 526, 562, 599, + 639, 679, 722, 765, 811, 857, 906, 956, + 1007, 1061, 1116, 1172, 1231, 1291, 1352, 1416, + 1481, 1548, 1617, 1688, 1760, 1834, 1910, 1988, + 2068, 2150, 2233, 2319, 2407, 2496, 2587, 2681, + 2776, 2874, 2973, 3075, 3178, 3284, 3391, 3501, + 3613, 3727, 3843, 3961, 4082, 4204, 4329, 4456, + 4585, 4716, 4850, 4986, 5124, 5264, 5407, 5552, + 5699, 5849, 6001, 6155, 6311, 6470, 6632, 6795, + 6962, 7130, 7301, 7475, 7650, 7829, 8009, 8193, + 8379, 8567, 8758, 8951, 9147, 9345, 9546, 9750, + 9956, 10165, 10376, 10590, 10806, 11025, 11247, 11472, + 11699, 11929, 12161, 12397, 12634, 12875, 13119, 13365, + 13614, 13865, 14120, 14377, 14637, 14899, 15165, 15433, + 15705, 15979, 16256, 16535, 16818, 17104, 17392, 17683, + 17978, 18275, 18575, 18878, 19184, 19493, 19805, 20119, + 20437, 20758, 21082, 21409, 21739, 22072, 22407, 22746, + 23089, 23434, 23782, 24133, 24487, 24845, 25206, 25569, + 25936, 26306, 26679, 27055, 27435, 27818, 28203, 28592, + 28985, 29380, 29779, 30181, 30586, 30994, 31406, 31820, + 32239, 32660, 33085, 33513, 33944, 34379, 34817, 35258, + 35702, 36150, 36602, 37056, 37514, 37976, 38441, 38909, + 39380, 39856, 40334, 40816, 41301, 41790, 42282, 42778, + 43277, 43780, 44286, 44795, 45308, 45825, 46345, 46869, + 47396, 47927, 48461, 48999, 49540, 50085, 50634, 51186, + 51742, 52301, 52864, 53431, 54001, 54575, 55153, 55734, + 56318, 56907, 57499, 58095, 58695, 59298, 59905, 60515, + 61130, 61748, 62370, 62995, 63624, 64258, 64894, 65535, +}; +#endif + +#ifdef GAMMA_3_0 +static const u16 gamma_table_3_0[] = { + /* gamma = 3.0 */ + 0, 0, 0, 0, 0, 0, 1, 1, + 2, 3, 4, 5, 7, 9, 11, 13, + 16, 19, 23, 27, 32, 37, 42, 48, + 55, 62, 69, 78, 87, 96, 107, 118, + 130, 142, 155, 169, 184, 200, 217, 234, + 253, 272, 293, 314, 337, 360, 385, 410, + 437, 465, 494, 524, 556, 588, 622, 658, + 694, 732, 771, 812, 854, 897, 942, 988, + 1036, 1085, 1136, 1189, 1243, 1298, 1356, 1415, + 1475, 1538, 1602, 1667, 1735, 1804, 1876, 1949, + 2024, 2100, 2179, 2260, 2343, 2427, 2514, 2603, + 2693, 2786, 2881, 2978, 3078, 3179, 3283, 3389, + 3497, 3607, 3720, 3835, 3952, 4072, 4194, 4319, + 4446, 4575, 4707, 4842, 4979, 5118, 5261, 5405, + 5553, 5703, 5856, 6011, 6169, 6330, 6494, 6660, + 6830, 7002, 7177, 7355, 7536, 7719, 7906, 8096, + 8289, 8484, 8683, 8885, 9090, 9298, 9510, 9724, + 9942, 10163, 10387, 10614, 10845, 11079, 11317, 11557, + 11802, 12049, 12300, 12555, 12813, 13074, 13339, 13608, + 13880, 14156, 14435, 14718, 15005, 15295, 15589, 15887, + 16189, 16494, 16803, 17117, 17433, 17754, 18079, 18408, + 18740, 19077, 19418, 19762, 20111, 20464, 20821, 21182, + 21547, 21917, 22290, 22668, 23050, 23436, 23827, 24222, + 24621, 25025, 25433, 25845, 26262, 26683, 27109, 27539, + 27974, 28413, 28857, 29306, 29759, 30217, 30680, 31147, + 31619, 32095, 32577, 33063, 33554, 34050, 34551, 35056, + 35567, 36082, 36602, 37128, 37658, 38194, 38734, 39280, + 39830, 40386, 40947, 41513, 42084, 42661, 43243, 43830, + 44422, 45019, 45622, 46231, 46844, 47463, 48088, 48718, + 49353, 49994, 50641, 51293, 51950, 52614, 53282, 53957, + 54637, 55323, 56014, 56712, 57415, 58123, 58838, 59558, + 60285, 61017, 61755, 62499, 63249, 64005, 64767, 65535, +}; +#endif + +void clock_setup(void) +{ + rcc_clock_setup_in_hse_8mhz_out_72mhz(); + + /* Enable TIM1 clock. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_TIM1EN); + + /* Enable GPIOC, Alternate Function clocks. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, + RCC_APB2ENR_IOPAEN | RCC_APB2ENR_AFIOEN); +} + +void gpio_setup(void) +{ + /* + * Set GPIO6 (in GPIO port C) to + * 'output alternate function push-pull'. + */ + gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, + GPIO_TIM1_CH1 | + GPIO_TIM1_CH2 | + GPIO_TIM1_CH3 | + GPIO_TIM1_CH4); + + /* Remap TIM1: + * CH1 -> PC6 + * CH2 -> PC7 + * CH3 -> PC8 + * CH4 -> PC9 + */ + //AFIO_MAPR |= AFIO_MAPR_TIM3_REMAP_FULL_REMAP; +} +void tim_setup(void) +{ +#if 0 + TIM1_CR1 = TIM_CR1_CMS_CENTER_1 | TIM_CR1_ARPE; + TIM1_CCMR1 = TIM_CCMR1_OC1M_PWM1 | TIM_CCMR1_OC1PE | TIM_CCMR1_OC2M_PWM1 | TIM_CCMR1_OC2PE; + TIM1_CCMR2 = TIM_CCMR2_OC3M_PWM1 | TIM_CCMR2_OC3PE; + + TIM1_CCER &= ~TIM_CCER_CC1P; +#endif +#if 1 + TIM1_SMCR &= ~TIM_SMCR_SMS_MASK; + TIM1_CR1 &= ~TIM_CR1_CEN; + + /* Clock division and mode */ + TIM1_CR1 = TIM_CR1_CKD_CK_INT | TIM_CR1_CMS_EDGE; + /* Period */ + TIM1_ARR = 65535; + /* Prescaler */ + TIM1_PSC = 2; + TIM1_EGR = TIM_EGR_UG; + + /* ---- */ + /* Output compare 1 mode and preload */ + TIM1_CCMR1 |= TIM_CCMR1_OC1M_PWM1 | TIM_CCMR1_OC1PE; + + /* Polarity and state */ + // TIM1_CCER = TIM_CCER_CC1P | TIM_CCER_CC1E; + TIM1_CCER |= TIM_CCER_CC1E; + + /* Capture compare value */ + TIM1_CCR1 = 1000; + + /* ---- */ + /* Output compare 2 mode and preload */ + TIM1_CCMR1 |= TIM_CCMR1_OC2M_PWM1 | TIM_CCMR1_OC2PE; + + /* Polarity and state */ + // TIM1_CCER = TIM_CCER_CC1P | TIM_CCER_CC1E; + TIM1_CCER |= TIM_CCER_CC2E; + + /* Capture compare value */ + TIM1_CCR2 = 1000; + + /* ---- */ + /* Output compare 3 mode and preload */ + TIM1_CCMR2 |= TIM_CCMR2_OC3M_PWM1 | TIM_CCMR2_OC3PE; + + /* Polarity and state */ + // TIM1_CCER = TIM_CCER_CC1P | TIM_CCER_CC1E; + TIM1_CCER |= TIM_CCER_CC3E; + + /* Capture compare value */ + TIM1_CCR3 = 1000; + + /* ---- */ + /* Output compare 4 mode and preload */ + TIM1_CCMR2 |= TIM_CCMR2_OC4M_PWM1 | TIM_CCMR2_OC4PE; + + /* Polarity and state */ + // TIM1_CCER = TIM_CCER_CC1P | TIM_CCER_CC1E; + TIM1_CCER |= TIM_CCER_CC4E; + + /* Capture compare value */ + TIM1_CCR4 = 1000; + + /* ---- */ + /* ARR reload enable */ + TIM1_CR1 |= TIM_CR1_ARPE; + + TIM1_BDTR |= TIM_BDTR_MOE; + + /* Counter enable */ + TIM1_CR1 |= TIM_CR1_CEN; +#endif +} + +int main(void) +{ + int i, j0, j1, j2, j3, d0, d1, d2, d3, j, k, kd; + + clock_setup(); + gpio_setup(); + tim_setup(); + +#ifdef COMPARE + j0 = 0; + d0 = 1; + j1 = 0; + d1 = 1; + j2 = 0; + d2 = 1; + j3 = 0; + d3 = 1; + while (1) { + TIM1_CCR1 = gamma_table_linear[j0]; + j0 += d0; + if (j0 == 255) + d0 =- 1; + if (j0 == 0) + d0 = 1; + TIM1_CCR2 = gamma_table_1_3[j1]; + j1 += d1; + if (j1 == 255) + d1 =- 1; + if (j1 == 0) + d1 = 1; + TIM1_CCR3 = gamma_table_2_5[j2]; + j2 += d2; + if (j2 == 255) + d2 =- 1; + if (j2 == 0) + d2 = 1; + TIM1_CCR4= gamma_table_3_0[j3]; + j3 += d3; + if (j3 == 255) + d3 =- 1; + if (j3 == 0) + d3 = 1; + for (i = 0; i < 50000; i++); + } +#endif + +#ifdef MOVING_FADE + j0 = 0; + d0 = 1; + j1 = 128; + d1 = 1; + j2 = 255; + d2 = -1; + j3 = 128; + d3 = -1; + while (1) { + TIM1_CCR1 = GAMMA_TABLE[j0]; + j0 += d0; + if (j0 == 255) + d0 =- 1; + if (j0 == 0) + d0 = 1; + TIM1_CCR2 = GAMMA_TABLE[j1]; + j1 += d1; + if (j1 == 255) + d1 =- 1; + if (j1 == 0) + d1 = 1; + TIM1_CCR3 = GAMMA_TABLE[j2]; + j2 += d2; + if (j2 == 255) + d2 =- 1; + if (j2 == 0) + d2 = 1; + TIM1_CCR4 = GAMMA_TABLE[j3]; + j3 += d3; + if (j3 == 255) + d3 =- 1; + if (j3 == 0) + d3 = 1; + for (i = 0; i < 10000; i++); + } +#endif + +#ifdef KITT + j0 = 255; + d0 = -1; + j1 = 20; + d1 = -1; + j2 = 20; + d2 = -1; + j3 = 20; + d3 = -1; + j = 0; + k = 0; + kd = 1; + while (1) { + TIM1_CCR1 = GAMMA_TABLE[j0]; + j0 += d0; + if (j0 == 255) + d0 =- 1; + if (j0 == 19) + j0 = 20; + TIM1_CCR2 = GAMMA_TABLE[j1]; + j1 += d1; + if (j1 == 255) + d1 =- 1; + if (j1 == 19) + j1 = 20; + TIM1_CCR3 = GAMMA_TABLE[j2]; + j2 += d2; + if (j2 == 255) + d2 =- 1; + if (j2 == 19) + j2 = 20; + TIM1_CCR4 = GAMMA_TABLE[j3]; + j3 += d3; + if (j3 == 255) + d3 =- 1; + if (j3 == 19) + j3 = 20; + for (i = 0; i < 5000; i++); + j++; + if (j == 100) { + j = 0; + switch (k += kd) { + case 0: + j0 = 255; + break; + case 1: + j1 = 255; + break; + case 2: + j2 = 255; + break; + case 3: + j3 = 255; + break; + } + if (k == 3) + kd =- 1; + if (k == 0) + kd = 1; + } + } +#endif + + return 0; +} diff --git a/examples/stm32f1/mb525/pwmleds/pwmleds.ld b/examples/stm32f1/mb525/pwmleds/pwmleds.ld new file mode 100644 index 0000000..7ea2b92 --- /dev/null +++ b/examples/stm32f1/mb525/pwmleds/pwmleds.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Linker script for Olimex STM32-H103 (STM32F103RBT6, 128K flash, 20K RAM). */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32.ld + diff --git a/examples/stm32f1/obldc/can/Makefile b/examples/stm32f1/obldc/can/Makefile new file mode 100644 index 0000000..20a4b90 --- /dev/null +++ b/examples/stm32f1/obldc/can/Makefile @@ -0,0 +1,23 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +## + +BINARY = can + +include ../../Makefile.include + diff --git a/examples/stm32f1/obldc/can/can.c b/examples/stm32f1/obldc/can/can.c new file mode 100644 index 0000000..6c63c48 --- /dev/null +++ b/examples/stm32f1/obldc/can/can.c @@ -0,0 +1,216 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * Copyright (C) 2010 Piotr Esden-Tempski + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include +#include + +struct can_tx_msg { + u32 std_id; + u32 ext_id; + u8 ide; + u8 rtr; + u8 dlc; + u8 data[8]; +}; + +struct can_rx_msg { + u32 std_id; + u32 ext_id; + u8 ide; + u8 rtr; + u8 dlc; + u8 data[8]; + u8 fmi; +}; + +struct can_tx_msg can_tx_msg; +struct can_rx_msg can_rx_msg; + +void gpio_setup(void) +{ + /* Enable GPIOA clock. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); + + /* Enable GPIOB clock. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPBEN); + + gpio_set(GPIOA, GPIO6); /* LED0 off */ + gpio_set(GPIOA, GPIO7); /* LED1 off */ + gpio_set(GPIOB, GPIO0); /* LED2 off */ + gpio_set(GPIOB, GPIO1); /* LED3 off */ + + /* Set GPIO6/7 (in GPIO port A) to 'output push-pull' for the LEDs. */ + gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO6); + gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO7); + + /* Set GPIO6/7 (in GPIO port B) to 'output push-pull' for the LEDs. */ + gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO0); + gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO1); +} + +void systick_setup(void) +{ + /* 72MHz / 8 => 9000000 counts per second */ + systick_set_clocksource(STK_CTRL_CLKSOURCE_AHB_DIV8); + + /* 9000000/9000 = 1000 overflows per second - every 1ms one interrupt */ + systick_set_reload(9000); + + systick_interrupt_enable(); + + /* Start counting. */ + systick_counter_enable(); +} + +void can_setup(void) +{ + /* Enable peripheral clocks. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_AFIOEN); + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); + rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_CANEN); + + /* Configure CAN pin: RX (input pull-up). */ + gpio_set_mode(GPIOA, GPIO_MODE_INPUT, + GPIO_CNF_INPUT_PULL_UPDOWN, GPIO_CAN_RX); + gpio_set(GPIOA, GPIO_CAN_RX); + + /* Configure CAN pin: TX. */ + gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_CAN_TX); + + /* NVIC setup. */ + nvic_enable_irq(NVIC_USB_LP_CAN_RX0_IRQ); + nvic_set_priority(NVIC_USB_LP_CAN_RX0_IRQ, 1); + + /* Reset CAN. */ + can_reset(CAN1); + + /* CAN cell init. */ + if (can_init(CAN1, + false, /* TTCM: Time triggered comm mode? */ + true, /* ABOM: Automatic bus-off management? */ + false, /* AWUM: Automatic wakeup mode? */ + false, /* NART: No automatic retransmission? */ + false, /* RFLM: Receive FIFO locked mode? */ + false, /* TXFP: Transmit FIFO priority? */ + CAN_BTR_SJW_1TQ, + CAN_BTR_TS1_3TQ, + CAN_BTR_TS2_4TQ, + 12)) /* BRP+1: Baud rate prescaler */ + { + gpio_set(GPIOA, GPIO6); /* LED0 off */ + gpio_set(GPIOA, GPIO7); /* LED1 off */ + gpio_set(GPIOB, GPIO0); /* LED2 off */ + gpio_clear(GPIOB, GPIO1); /* LED3 on */ + + /* Die because we failed to initialize. */ + while (1) + __asm__("nop"); + } + + /* CAN filter 0 init. */ + can_filter_id_mask_32bit_init(CAN1, + 0, /* Filter ID */ + 0, /* CAN ID */ + 0, /* CAN ID mask */ + 0, /* FIFO assignment (here: FIFO0) */ + true); /* Enable the filter. */ + + /* Enable CAN RX interrupt. */ + can_enable_irq(CAN1, CAN_IER_FMPIE0); +} + +void sys_tick_handler(void) +{ + static int temp32 = 0; + static u8 data[8] = {0, 1, 2, 0, 0, 0, 0, 0}; + + /* We call this handler every 1ms so 1000ms = 1s on/off. */ + if (++temp32 != 1000) + return; + + temp32 = 0; + + /* Transmit CAN frame. */ + data[0]++; + if (can_transmit(CAN1, + 0, /* (EX/ST)ID: CAN ID */ + false, /* IDE: CAN ID extended? */ + false, /* RTR: Request transmit? */ + 8, /* DLC: Data length */ + data) == -1) + { + gpio_set(GPIOA, GPIO6); /* LED0 off */ + gpio_set(GPIOA, GPIO7); /* LED1 off */ + gpio_clear(GPIOB, GPIO0); /* LED2 on */ + gpio_set(GPIOB, GPIO1); /* LED3 off */ + } +} + +void usb_lp_can_rx0_isr(void) +{ + u32 id, fmi; + bool ext, rtr; + u8 length, data[8]; + + can_receive(CAN1, 0, false, &id, &ext, &rtr, &fmi, &length, data); + + if (data[0] & 1) + gpio_clear(GPIOA, GPIO6); + else + gpio_set(GPIOA, GPIO6); + + if (data[0] & 2) + gpio_clear(GPIOA, GPIO7); + else + gpio_set(GPIOA, GPIO7); + + if (data[0] & 4) + gpio_clear(GPIOB, GPIO0); + else + gpio_set(GPIOB, GPIO0); + + if (data[0] & 8) + gpio_clear(GPIOB, GPIO1); + else + gpio_set(GPIOB, GPIO1); + + can_fifo_release(CAN1, 0); +} + +int main(void) +{ + rcc_clock_setup_in_hse_8mhz_out_72mhz(); + gpio_setup(); + can_setup(); + systick_setup(); + + while (1); /* Halt. */ + + return 0; +} diff --git a/examples/stm32f1/obldc/can/can.ld b/examples/stm32f1/obldc/can/can.ld new file mode 100644 index 0000000..c076521 --- /dev/null +++ b/examples/stm32f1/obldc/can/can.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Linker script for an STM32F103RBT6 board (128K flash, 20K RAM). */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32.ld + diff --git a/examples/stm32f1/obldc/led/Makefile b/examples/stm32f1/obldc/led/Makefile new file mode 100644 index 0000000..8e1618a --- /dev/null +++ b/examples/stm32f1/obldc/led/Makefile @@ -0,0 +1,23 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +## + +BINARY = led + +include ../../Makefile.include + diff --git a/examples/stm32f1/obldc/led/led.c b/examples/stm32f1/obldc/led/led.c new file mode 100644 index 0000000..09ae89d --- /dev/null +++ b/examples/stm32f1/obldc/led/led.c @@ -0,0 +1,71 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * Copyright (C) 2010 Piotr Esden-Tempski + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include + +/* Set STM32 to 72 MHz. */ +void clock_setup(void) +{ + rcc_clock_setup_in_hse_8mhz_out_72mhz(); + + /* Enable GPIOA clock. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); + + /* Enable GPIOB clock. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPBEN); +} + +void gpio_setup(void) +{ + /* Set GPIO6 and 7 (in GPIO port A) to 'output push-pull'. */ + gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO6 | GPIO7); + + /* Set GPIO0 and 1 (in GPIO port B) to 'output push-pull'. */ + gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO0 | GPIO1); +} + +int main(void) +{ + int i; + + clock_setup(); + gpio_setup(); + + /* Blink the LEDs on the board. */ + while (1) { + gpio_toggle(GPIOA, GPIO6); /* LED on/off */ + for (i = 0; i < 8000000; i++) /* Wait a bit. */ + __asm__("nop"); + gpio_toggle(GPIOA, GPIO7); /* LED on/off */ + for (i = 0; i < 8000000; i++) /* Wait a bit. */ + __asm__("nop"); + gpio_toggle(GPIOB, GPIO0); /* LED on/off */ + for (i = 0; i < 8000000; i++) /* Wait a bit. */ + __asm__("nop"); + gpio_toggle(GPIOB, GPIO1); /* LED on/off */ + for (i = 0; i < 8000000; i++) /* Wait a bit. */ + __asm__("nop"); + } + + return 0; +} diff --git a/examples/stm32f1/obldc/led/led.ld b/examples/stm32f1/obldc/led/led.ld new file mode 100644 index 0000000..7899773 --- /dev/null +++ b/examples/stm32f1/obldc/led/led.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Linker script for Open-BLDC (STM32F103CBT6, 128K flash, 20K RAM). */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32.ld + diff --git a/examples/stm32f1/obldc/pwmleds/Makefile b/examples/stm32f1/obldc/pwmleds/Makefile new file mode 100644 index 0000000..8ae74d6 --- /dev/null +++ b/examples/stm32f1/obldc/pwmleds/Makefile @@ -0,0 +1,23 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +## + +BINARY = pwmleds + +include ../../Makefile.include + diff --git a/examples/stm32f1/obldc/pwmleds/pwmleds.c b/examples/stm32f1/obldc/pwmleds/pwmleds.c new file mode 100644 index 0000000..146bb56 --- /dev/null +++ b/examples/stm32f1/obldc/pwmleds/pwmleds.c @@ -0,0 +1,485 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Piotr Esden-Tempski + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include + +// #define COMPARE +// #define MOVING_FADE +#define KITT + +#ifdef COMPARE +#define GAMMA_LINEAR +#define GAMMA_1_3 +#define GAMMA_2_5 +#define GAMMA_3_0 +#endif + +#ifdef MOVING_FADE +#define GAMMA_2_2 +#define GAMMA_TABLE gamma_table_2_2 +#endif + +#ifdef KITT +#define GAMMA_2_5 +#define GAMMA_TABLE gamma_table_2_5 +#endif + +/* + * Gamma correction table + * + * The nonlinear tables are calculating with the function: + * Iout = Iin ** gamma + */ +#ifdef GAMMA_LINEAR +static const u16 gamma_table_linear[] = { + 1, 4, 9, 17, 26, 37, 51, 67, + 84, 104, 126, 149, 175, 203, 233, 265, + 299, 334, 372, 412, 454, 499, 545, 593, + 643, 695, 749, 805, 864, 924, 986, 1050, + 1116, 1185, 1255, 1327, 1402, 1478, 1556, 1637, + 1719, 1803, 1890, 1978, 2068, 2161, 2255, 2352, + 2450, 2550, 2653, 2757, 2864, 2972, 3082, 3195, + 3309, 3426, 3544, 3664, 3787, 3911, 4038, 4166, + 4296, 4429, 4563, 4700, 4838, 4978, 5121, 5265, + 5411, 5560, 5710, 5862, 6017, 6173, 6331, 6492, + 6654, 6818, 6985, 7153, 7323, 7495, 7670, 7846, + 8024, 8204, 8387, 8571, 8757, 8945, 9135, 9327, + 9521, 9718, 9916, 10116, 10318, 10522, 10728, 10936, + 11146, 11358, 11572, 11788, 12006, 12226, 12448, 12672, + 12897, 13125, 13355, 13587, 13821, 14057, 14294, 14534, + 14776, 15020, 15265, 15513, 15763, 16014, 16268, 16524, + 16781, 17041, 17302, 17566, 17831, 18099, 18368, 18640, + 18913, 19189, 19466, 19745, 20027, 20310, 20595, 20883, + 21172, 21463, 21756, 22051, 22349, 22648, 22949, 23252, + 23557, 23864, 24173, 24484, 24797, 25112, 25429, 25748, + 26069, 26391, 26716, 27043, 27372, 27702, 28035, 28370, + 28707, 29045, 29386, 29728, 30073, 30419, 30768, 31118, + 31471, 31825, 32182, 32540, 32900, 33263, 33627, 33993, + 34361, 34731, 35104, 35478, 35854, 36232, 36612, 36994, + 37378, 37764, 38152, 38542, 38933, 39327, 39723, 40121, + 40521, 40922, 41326, 41732, 42139, 42549, 42960, 43374, + 43789, 44207, 44626, 45048, 45471, 45896, 46324, 46753, + 47184, 47617, 48052, 48490, 48929, 49370, 49813, 50258, + 50705, 51154, 51604, 52057, 52512, 52969, 53428, 53888, + 54351, 54816, 55282, 55751, 56222, 56694, 57169, 57645, + 58123, 58604, 59086, 59570, 60057, 60545, 61035, 61527, + 62021, 62517, 63016, 63516, 64018, 64521, 65027, 65535, +}; +#endif + +#ifdef GAMMA_1_3 +static const u16 gamma_table_1_3[] = { + /* Gamma 1.3 */ + 0, 49, 120, 203, 296, 395, 501, 612, + 728, 848, 973, 1101, 1233, 1368, 1506, 1648, + 1792, 1939, 2088, 2241, 2395, 2552, 2711, 2872, + 3036, 3201, 3369, 3538, 3709, 3882, 4057, 4234, + 4412, 4592, 4774, 4957, 5142, 5329, 5517, 5706, + 5897, 6090, 6283, 6479, 6675, 6873, 7072, 7273, + 7475, 7678, 7882, 8088, 8294, 8502, 8711, 8922, + 9133, 9346, 9559, 9774, 9990, 10207, 10425, 10644, + 10864, 11086, 11308, 11531, 11755, 11981, 12207, 12434, + 12662, 12891, 13121, 13352, 13584, 13817, 14051, 14285, + 14521, 14757, 14994, 15233, 15472, 15712, 15952, 16194, + 16436, 16679, 16923, 17168, 17414, 17660, 17908, 18156, + 18405, 18654, 18905, 19156, 19408, 19660, 19914, 20168, + 20423, 20679, 20935, 21192, 21450, 21708, 21968, 22228, + 22488, 22750, 23012, 23275, 23538, 23802, 24067, 24332, + 24599, 24865, 25133, 25401, 25670, 25939, 26209, 26480, + 26751, 27023, 27296, 27569, 27843, 28118, 28393, 28669, + 28945, 29222, 29500, 29778, 30057, 30336, 30616, 30897, + 31178, 31460, 31742, 32025, 32308, 32592, 32877, 33162, + 33448, 33734, 34021, 34309, 34597, 34885, 35175, 35464, + 35754, 36045, 36337, 36628, 36921, 37214, 37507, 37801, + 38096, 38391, 38686, 38982, 39279, 39576, 39874, 40172, + 40471, 40770, 41070, 41370, 41670, 41972, 42273, 42576, + 42878, 43181, 43485, 43789, 44094, 44399, 44705, 45011, + 45317, 45625, 45932, 46240, 46549, 46858, 47167, 47477, + 47787, 48098, 48409, 48721, 49034, 49346, 49659, 49973, + 50287, 50602, 50917, 51232, 51548, 51864, 52181, 52498, + 52816, 53134, 53452, 53771, 54091, 54411, 54731, 55052, + 55373, 55694, 56016, 56339, 56662, 56985, 57309, 57633, + 57957, 58282, 58608, 58933, 59260, 59586, 59913, 60241, + 60569, 60897, 61226, 61555, 61884, 62214, 62545, 62875, + 63206, 63538, 63870, 64202, 64535, 64868, 65201, 65535, +}; +#endif + +#ifdef GAMMA_2_2 +static const u16 gamma_table_2_2[] = { + 0, 0, 2, 4, 7, 11, 17, 24, + 32, 42, 53, 65, 79, 94, 111, 129, + 148, 169, 192, 216, 242, 270, 299, 330, + 362, 396, 432, 469, 508, 549, 591, 635, + 681, 729, 779, 830, 883, 938, 995, 1053, + 1113, 1175, 1239, 1305, 1373, 1443, 1514, 1587, + 1663, 1740, 1819, 1900, 1983, 2068, 2155, 2243, + 2334, 2427, 2521, 2618, 2717, 2817, 2920, 3024, + 3131, 3240, 3350, 3463, 3578, 3694, 3813, 3934, + 4057, 4182, 4309, 4438, 4570, 4703, 4838, 4976, + 5115, 5257, 5401, 5547, 5695, 5845, 5998, 6152, + 6309, 6468, 6629, 6792, 6957, 7124, 7294, 7466, + 7640, 7816, 7994, 8175, 8358, 8543, 8730, 8919, + 9111, 9305, 9501, 9699, 9900, 10102, 10307, 10515, + 10724, 10936, 11150, 11366, 11585, 11806, 12029, 12254, + 12482, 12712, 12944, 13179, 13416, 13655, 13896, 14140, + 14386, 14635, 14885, 15138, 15394, 15652, 15912, 16174, + 16439, 16706, 16975, 17247, 17521, 17798, 18077, 18358, + 18642, 18928, 19216, 19507, 19800, 20095, 20393, 20694, + 20996, 21301, 21609, 21919, 22231, 22546, 22863, 23182, + 23504, 23829, 24156, 24485, 24817, 25151, 25487, 25826, + 26168, 26512, 26858, 27207, 27558, 27912, 28268, 28627, + 28988, 29351, 29717, 30086, 30457, 30830, 31206, 31585, + 31966, 32349, 32735, 33124, 33514, 33908, 34304, 34702, + 35103, 35507, 35913, 36321, 36732, 37146, 37562, 37981, + 38402, 38825, 39252, 39680, 40112, 40546, 40982, 41421, + 41862, 42306, 42753, 43202, 43654, 44108, 44565, 45025, + 45487, 45951, 46418, 46888, 47360, 47835, 48313, 48793, + 49275, 49761, 50249, 50739, 51232, 51728, 52226, 52727, + 53230, 53736, 54245, 54756, 55270, 55787, 56306, 56828, + 57352, 57879, 58409, 58941, 59476, 60014, 60554, 61097, + 61642, 62190, 62741, 63295, 63851, 64410, 64971, 65535 +}; +#endif + +#ifdef GAMMA_2_5 +static const u16 gamma_table_2_5[] = { + /* gamma = 2.5 */ + 0, 0, 0, 1, 2, 4, 6, 8, + 11, 15, 20, 25, 31, 38, 46, 55, + 65, 75, 87, 99, 113, 128, 143, 160, + 178, 197, 218, 239, 262, 286, 311, 338, + 366, 395, 425, 457, 491, 526, 562, 599, + 639, 679, 722, 765, 811, 857, 906, 956, + 1007, 1061, 1116, 1172, 1231, 1291, 1352, 1416, + 1481, 1548, 1617, 1688, 1760, 1834, 1910, 1988, + 2068, 2150, 2233, 2319, 2407, 2496, 2587, 2681, + 2776, 2874, 2973, 3075, 3178, 3284, 3391, 3501, + 3613, 3727, 3843, 3961, 4082, 4204, 4329, 4456, + 4585, 4716, 4850, 4986, 5124, 5264, 5407, 5552, + 5699, 5849, 6001, 6155, 6311, 6470, 6632, 6795, + 6962, 7130, 7301, 7475, 7650, 7829, 8009, 8193, + 8379, 8567, 8758, 8951, 9147, 9345, 9546, 9750, + 9956, 10165, 10376, 10590, 10806, 11025, 11247, 11472, + 11699, 11929, 12161, 12397, 12634, 12875, 13119, 13365, + 13614, 13865, 14120, 14377, 14637, 14899, 15165, 15433, + 15705, 15979, 16256, 16535, 16818, 17104, 17392, 17683, + 17978, 18275, 18575, 18878, 19184, 19493, 19805, 20119, + 20437, 20758, 21082, 21409, 21739, 22072, 22407, 22746, + 23089, 23434, 23782, 24133, 24487, 24845, 25206, 25569, + 25936, 26306, 26679, 27055, 27435, 27818, 28203, 28592, + 28985, 29380, 29779, 30181, 30586, 30994, 31406, 31820, + 32239, 32660, 33085, 33513, 33944, 34379, 34817, 35258, + 35702, 36150, 36602, 37056, 37514, 37976, 38441, 38909, + 39380, 39856, 40334, 40816, 41301, 41790, 42282, 42778, + 43277, 43780, 44286, 44795, 45308, 45825, 46345, 46869, + 47396, 47927, 48461, 48999, 49540, 50085, 50634, 51186, + 51742, 52301, 52864, 53431, 54001, 54575, 55153, 55734, + 56318, 56907, 57499, 58095, 58695, 59298, 59905, 60515, + 61130, 61748, 62370, 62995, 63624, 64258, 64894, 65535, +}; +#endif + +#ifdef GAMMA_3_0 +static const u16 gamma_table_3_0[] = { + /* gamma = 3.0 */ + 0, 0, 0, 0, 0, 0, 1, 1, + 2, 3, 4, 5, 7, 9, 11, 13, + 16, 19, 23, 27, 32, 37, 42, 48, + 55, 62, 69, 78, 87, 96, 107, 118, + 130, 142, 155, 169, 184, 200, 217, 234, + 253, 272, 293, 314, 337, 360, 385, 410, + 437, 465, 494, 524, 556, 588, 622, 658, + 694, 732, 771, 812, 854, 897, 942, 988, + 1036, 1085, 1136, 1189, 1243, 1298, 1356, 1415, + 1475, 1538, 1602, 1667, 1735, 1804, 1876, 1949, + 2024, 2100, 2179, 2260, 2343, 2427, 2514, 2603, + 2693, 2786, 2881, 2978, 3078, 3179, 3283, 3389, + 3497, 3607, 3720, 3835, 3952, 4072, 4194, 4319, + 4446, 4575, 4707, 4842, 4979, 5118, 5261, 5405, + 5553, 5703, 5856, 6011, 6169, 6330, 6494, 6660, + 6830, 7002, 7177, 7355, 7536, 7719, 7906, 8096, + 8289, 8484, 8683, 8885, 9090, 9298, 9510, 9724, + 9942, 10163, 10387, 10614, 10845, 11079, 11317, 11557, + 11802, 12049, 12300, 12555, 12813, 13074, 13339, 13608, + 13880, 14156, 14435, 14718, 15005, 15295, 15589, 15887, + 16189, 16494, 16803, 17117, 17433, 17754, 18079, 18408, + 18740, 19077, 19418, 19762, 20111, 20464, 20821, 21182, + 21547, 21917, 22290, 22668, 23050, 23436, 23827, 24222, + 24621, 25025, 25433, 25845, 26262, 26683, 27109, 27539, + 27974, 28413, 28857, 29306, 29759, 30217, 30680, 31147, + 31619, 32095, 32577, 33063, 33554, 34050, 34551, 35056, + 35567, 36082, 36602, 37128, 37658, 38194, 38734, 39280, + 39830, 40386, 40947, 41513, 42084, 42661, 43243, 43830, + 44422, 45019, 45622, 46231, 46844, 47463, 48088, 48718, + 49353, 49994, 50641, 51293, 51950, 52614, 53282, 53957, + 54637, 55323, 56014, 56712, 57415, 58123, 58838, 59558, + 60285, 61017, 61755, 62499, 63249, 64005, 64767, 65535, +}; +#endif + +void clock_setup(void) +{ + rcc_clock_setup_in_hse_8mhz_out_72mhz(); + + /* Enable TIM3 clock. */ + rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_TIM3EN); + + /* Enable GPIOC, Alternate Function clocks. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, + RCC_APB2ENR_IOPAEN | + RCC_APB2ENR_IOPBEN | + RCC_APB2ENR_AFIOEN); +} + +void gpio_setup(void) +{ + /* + * Set GPIO6 and 7 (in GPIO port A) to + * 'output alternate function push-pull'. + */ + gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, + GPIO_TIM3_CH1 | + GPIO_TIM3_CH2); + + /* + * Set GPIO0 and 1 (in GPIO port B) to + * 'output alternate function push-pull'. + */ + gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, + GPIO_TIM3_CH3 | + GPIO_TIM3_CH4); + +} +void tim_setup(void) +{ + /* Clock division and mode */ + TIM3_CR1 = TIM_CR1_CKD_CK_INT | TIM_CR1_CMS_EDGE; + /* Period */ + TIM3_ARR = 65535; + /* Prescaler */ + TIM3_PSC = 0; + TIM3_EGR = TIM_EGR_UG; + + /* ---- */ + /* Output compare 1 mode and preload */ + TIM3_CCMR1 |= TIM_CCMR1_OC1M_PWM1 | TIM_CCMR1_OC1PE; + + /* Polarity and state */ + TIM3_CCER |= TIM_CCER_CC1P | TIM_CCER_CC1E; + //TIM3_CCER |= TIM_CCER_CC1E; + + /* Capture compare value */ + TIM3_CCR1 = 0; + + /* ---- */ + /* Output compare 2 mode and preload */ + TIM3_CCMR1 |= TIM_CCMR1_OC2M_PWM1 | TIM_CCMR1_OC2PE; + + /* Polarity and state */ + TIM3_CCER |= TIM_CCER_CC2P | TIM_CCER_CC2E; + //TIM3_CCER |= TIM_CCER_CC2E; + + /* Capture compare value */ + TIM3_CCR2 = 0; + + /* ---- */ + /* Output compare 3 mode and preload */ + TIM3_CCMR2 |= TIM_CCMR2_OC3M_PWM1 | TIM_CCMR2_OC3PE; + + /* Polarity and state */ + TIM3_CCER |= TIM_CCER_CC3P | TIM_CCER_CC3E; + //TIM3_CCER |= TIM_CCER_CC3E; + + /* Capture compare value */ + TIM3_CCR3 = 0; + + /* ---- */ + /* Output compare 4 mode and preload */ + TIM3_CCMR2 |= TIM_CCMR2_OC4M_PWM1 | TIM_CCMR2_OC4PE; + + /* Polarity and state */ + TIM3_CCER |= TIM_CCER_CC4P | TIM_CCER_CC4E; + //TIM3_CCER |= TIM_CCER_CC4E; + + /* Capture compare value */ + TIM3_CCR4 = 0; + + /* ---- */ + /* ARR reload enable */ + TIM3_CR1 |= TIM_CR1_ARPE; + + /* Counter enable */ + TIM3_CR1 |= TIM_CR1_CEN; +} + +int main(void) +{ + int i, j0, j1, j2, j3, d0, d1, d2, d3, j, k, kd; + + clock_setup(); + gpio_setup(); + tim_setup(); + +#ifdef COMPARE + j0 = 0; + d0 = 1; + j1 = 0; + d1 = 1; + j2 = 0; + d2 = 1; + j3 = 0; + d3 = 1; + while (1) { + TIM3_CCR1 = gamma_table_linear[j0]; + j0 += d0; + if (j0 == 255) + d0 =- 1; + if (j0 == 0) + d0 = 1; + TIM3_CCR2 = gamma_table_1_3[j1]; + j1 += d1; + if (j1 == 255) + d1 =- 1; + if (j1 == 0) + d1 = 1; + TIM3_CCR3 = gamma_table_2_5[j2]; + j2 += d2; + if (j2 == 255) + d2 =- 1; + if (j2 == 0) + d2 = 1; + TIM3_CCR4= gamma_table_3_0[j3]; + j3 += d3; + if (j3 == 255) + d3 =- 1; + if (j3 == 0) + d3 = 1; + for (i = 0; i < 50000; i++); + } +#endif + +#ifdef MOVING_FADE + j0 = 0; + d0 = 1; + j1 = 128; + d1 = 1; + j2 = 255; + d2 = -1; + j3 = 128; + d3 = -1; + while (1) { + TIM3_CCR1 = GAMMA_TABLE[j0]; + j0 += d0; + if (j0 == 255) + d0 =- 1; + if (j0 == 0) + d0 = 1; + TIM3_CCR2 = GAMMA_TABLE[j1]; + j1 += d1; + if (j1 == 255) + d1 =- 1; + if (j1 == 0) + d1 = 1; + TIM3_CCR3 = GAMMA_TABLE[j2]; + j2 += d2; + if (j2 == 255) + d2 =- 1; + if (j2 == 0) + d2 = 1; + TIM3_CCR4 = GAMMA_TABLE[j3]; + j3 += d3; + if (j3 == 255) + d3 =- 1; + if (j3 == 0) + d3 = 1; + for (i = 0; i < 10000; i++); + } +#endif + +#ifdef KITT + j0 = 255; + d0 = -1; + j1 = 20; + d1 = -1; + j2 = 20; + d2 = -1; + j3 = 20; + d3 = -1; + j = 0; + k = 0; + kd = 1; + while (1) { + TIM3_CCR1 = GAMMA_TABLE[j0]; + j0 += d0; + if (j0 == 255) + d0 =- 1; + if (j0 == 19) + j0 = 20; + TIM3_CCR2 = GAMMA_TABLE[j1]; + j1 += d1; + if (j1 == 255) + d1 =- 1; + if (j1 == 19) + j1 = 20; + TIM3_CCR3 = GAMMA_TABLE[j2]; + j2 += d2; + if (j2 == 255) + d2 =- 1; + if (j2 == 19) + j2 = 20; + TIM3_CCR4 = GAMMA_TABLE[j3]; + j3 += d3; + if (j3 == 255) + d3 =- 1; + if (j3 == 19) + j3 = 20; + for (i = 0; i < 15000; i++) + __asm__("nop"); + j++; + if (j == 100) { + j = 0; + switch (k += kd) { + case 0: + j0 = 255; + break; + case 1: + j1 = 255; + break; + case 2: + j2 = 255; + break; + case 3: + j3 = 255; + break; + } + if (k == 3) + kd =- 1; + if (k == 0) + kd = 1; + } + } +#endif + + return 0; +} diff --git a/examples/stm32f1/obldc/pwmleds/pwmleds.ld b/examples/stm32f1/obldc/pwmleds/pwmleds.ld new file mode 100644 index 0000000..7ea2b92 --- /dev/null +++ b/examples/stm32f1/obldc/pwmleds/pwmleds.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Linker script for Olimex STM32-H103 (STM32F103RBT6, 128K flash, 20K RAM). */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32.ld + diff --git a/examples/stm32f1/obldc/systick/Makefile b/examples/stm32f1/obldc/systick/Makefile new file mode 100644 index 0000000..91b5cb5 --- /dev/null +++ b/examples/stm32f1/obldc/systick/Makefile @@ -0,0 +1,23 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +## + +BINARY = systick + +include ../../Makefile.include + diff --git a/examples/stm32f1/obldc/systick/systick.c b/examples/stm32f1/obldc/systick/systick.c new file mode 100644 index 0000000..3d75c4a --- /dev/null +++ b/examples/stm32f1/obldc/systick/systick.c @@ -0,0 +1,90 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * Copyright (C) 2010 Piotr Esden-Tempski + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include + +u32 temp32; + +void gpio_setup(void) +{ + /* Enable GPIOA clock. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); + + /* Enable GPIOB clock. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPBEN); + + gpio_set(GPIOA, GPIO6); /* LED0 off */ + gpio_set(GPIOA, GPIO7); /* LED1 off */ + gpio_set(GPIOB, GPIO0); /* LED2 off */ + gpio_set(GPIOB, GPIO1); /* LED3 off */ + + /* Set GPIO6/7 (in GPIO port A) to 'output push-pull' for the LEDs. */ + gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO6); + gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO7); + + /* Set GPIO6/7 (in GPIO port B) to 'output push-pull' for the LEDs. */ + gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO0); + gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO1); +} + +void sys_tick_handler(void) +{ + temp32++; + + /* We call this handler every 1ms so 1000ms = 1s on/off. */ + if (temp32 == 1000) { + gpio_toggle(GPIOA, GPIO6); /* LED2 on/off */ + temp32 = 0; + } +} + +int main(void) +{ + rcc_clock_setup_in_hse_8mhz_out_72mhz(); + gpio_setup(); + + gpio_clear(GPIOA, GPIO7); /* LED1 on */ + gpio_set(GPIOA, GPIO6); /* LED2 off */ + + temp32 = 0; + + /* 72MHz / 8 => 9000000 counts per second */ + systick_set_clocksource(STK_CTRL_CLKSOURCE_AHB_DIV8); + + /* 9000000/9000 = 1000 overflows per second - every 1ms one interrupt */ + systick_set_reload(9000); + + systick_interrupt_enable(); + + /* Start counting. */ + systick_counter_enable(); + + while (1); /* Halt. */ + + return 0; +} diff --git a/examples/stm32f1/obldc/systick/systick.ld b/examples/stm32f1/obldc/systick/systick.ld new file mode 100644 index 0000000..da4f2b3 --- /dev/null +++ b/examples/stm32f1/obldc/systick/systick.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Linker script for an STM32F103CBT6 board (128K flash, 20K RAM). */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32.ld + diff --git a/examples/stm32f1/obldc/usart/Makefile b/examples/stm32f1/obldc/usart/Makefile new file mode 100644 index 0000000..2c1e1b1 --- /dev/null +++ b/examples/stm32f1/obldc/usart/Makefile @@ -0,0 +1,23 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +## + +BINARY = usart + +include ../../Makefile.include + diff --git a/examples/stm32f1/obldc/usart/usart.c b/examples/stm32f1/obldc/usart/usart.c new file mode 100644 index 0000000..ea5ec0e --- /dev/null +++ b/examples/stm32f1/obldc/usart/usart.c @@ -0,0 +1,90 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include + +void clock_setup(void) +{ + rcc_clock_setup_in_hse_8mhz_out_72mhz(); + + /* Enable GPIOA clock (for LED GPIOs). */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); + + /* Enable clocks for GPIO port B (for GPIO_USART1_TX) and USART1. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPBEN); + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_AFIOEN); + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_USART1EN); +} + +void usart_setup(void) +{ + /* Setup GPIO6 (in GPIO port A) to 'output push-pull' for LED use. */ + gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO6); + + AFIO_MAPR |= AFIO_MAPR_USART1_REMAP; + + /* Setup GPIO pin GPIO_USART3_TX/GPIO10 on GPIO port B for transmit. */ + gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_USART1_RE_TX); + + /* Setup UART parameters. */ + usart_set_baudrate(USART1, 230400); + usart_set_databits(USART1, 8); + usart_set_stopbits(USART1, USART_STOPBITS_1); + usart_set_mode(USART1, USART_MODE_TX); + usart_set_parity(USART1, USART_PARITY_NONE); + usart_set_flow_control(USART1, USART_FLOWCONTROL_NONE); + + /* Finally enable the USART. */ + usart_enable(USART1); +} + +void gpio_setup(void) +{ + /* Set GPIO12 (in GPIO port C) to 'output push-pull'. */ + gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO6); +} + +int main(void) +{ + int i, j = 0, c = 0; + + clock_setup(); + gpio_setup(); + usart_setup(); + + /* Blink the LED (PC12) on the board with every transmitted byte. */ + while (1) { + gpio_toggle(GPIOA, GPIO6); /* LED on/off */ + usart_send_blocking(USART1, c + '0'); /* Send a byte. */ + c = (c == 9) ? 0 : c + 1; /* Increment c. */ + if ((j++ % 80) == 0) { /* Newline after line full. */ + usart_send_blocking(USART1, '\r'); + usart_send_blocking(USART1, '\n'); + } + for (i = 0; i < 800000; i++) /* Wait a bit. */ + __asm__("nop"); + } + + return 0; +} diff --git a/examples/stm32f1/obldc/usart/usart.ld b/examples/stm32f1/obldc/usart/usart.ld new file mode 100644 index 0000000..7899773 --- /dev/null +++ b/examples/stm32f1/obldc/usart/usart.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Linker script for Open-BLDC (STM32F103CBT6, 128K flash, 20K RAM). */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32.ld + diff --git a/examples/stm32f1/obldc/usart_irq/Makefile b/examples/stm32f1/obldc/usart_irq/Makefile new file mode 100644 index 0000000..2ab46a0 --- /dev/null +++ b/examples/stm32f1/obldc/usart_irq/Makefile @@ -0,0 +1,25 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +## + +BINARY = usart_irq + +OOCD_BOARD = open-bldc + +include ../../Makefile.include + diff --git a/examples/stm32f1/obldc/usart_irq/usart_irq.c b/examples/stm32f1/obldc/usart_irq/usart_irq.c new file mode 100644 index 0000000..82320c1 --- /dev/null +++ b/examples/stm32f1/obldc/usart_irq/usart_irq.c @@ -0,0 +1,120 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include + +void clock_setup(void) +{ + rcc_clock_setup_in_hse_8mhz_out_72mhz(); + + /* Enable GPIOA clock (for LED GPIOs). */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); + + /* Enable clocks for GPIO port B (for GPIO_USART1_TX) and USART1. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPBEN); + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_AFIOEN); + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_USART1EN); +} + +void usart_setup(void) +{ + /* Enable the USART1 interrupt. */ + nvic_enable_irq(NVIC_USART1_IRQ); + + /* enable USART1 pin software remapping */ + AFIO_MAPR |= AFIO_MAPR_USART1_REMAP; + + /* Setup GPIO pin GPIO_USART1_RE_TX on GPIO port B for transmit. */ + gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_USART1_RE_TX); + + /* Setup GPIO pin GPIO_USART1_RE_RX on GPIO port B for receive. */ + gpio_set_mode(GPIOB, GPIO_MODE_INPUT, + GPIO_CNF_INPUT_FLOAT, GPIO_USART1_RE_RX); + + /* Setup UART parameters. */ + usart_set_baudrate(USART1, 230400); + usart_set_databits(USART1, 8); + usart_set_stopbits(USART1, USART_STOPBITS_1); + usart_set_parity(USART1, USART_PARITY_NONE); + usart_set_flow_control(USART1, USART_FLOWCONTROL_NONE); + usart_set_mode(USART1, USART_MODE_TX_RX); + + /* Enable USART1 Receive interrupt. */ + USART_CR1(USART1) |= USART_CR1_RXNEIE; + + /* Finally enable the USART. */ + usart_enable(USART1); +} + +void gpio_setup(void) +{ + gpio_set(GPIOA, GPIO6 | GPIO7); + + /* Setup GPIO6 and 7 (in GPIO port A) for led use. */ + gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO6 | GPIO7); +} + +void usart1_isr(void) +{ + static u8 data = 'A'; + + /* Check if we were called because of RXNE. */ + if (((USART_CR1(USART1) & USART_CR1_RXNEIE) != 0) && + ((USART_SR(USART1) & USART_SR_RXNE) != 0)) { + /* Indicate that we got data. */ + gpio_toggle(GPIOA, GPIO6); + + /* Retrieve the data from the peripheral. */ + data = usart_recv(USART1); + + /* Enable transmit interrupt so it sends back the data. */ + USART_CR1(USART1) |= USART_CR1_TXEIE; + } + + /* Check if we were called because of TXE. */ + if (((USART_CR1(USART1) & USART_CR1_TXEIE) != 0) && + ((USART_SR(USART1) & USART_SR_TXE) != 0)) { + /* Indicate that we are sending out data. */ + gpio_toggle(GPIOA, GPIO7); + + /* Put data into the transmit register. */ + usart_send(USART1, data); + + /* Disable the TXE interrupt as we don't need it anymore. */ + USART_CR1(USART1) &= ~USART_CR1_TXEIE; + } +} + +int main(void) +{ + clock_setup(); + gpio_setup(); + usart_setup(); + + /* Wait forever and do nothing. */ + while (1) + __asm__("nop"); + + return 0; +} diff --git a/examples/stm32f1/obldc/usart_irq/usart_irq.ld b/examples/stm32f1/obldc/usart_irq/usart_irq.ld new file mode 100644 index 0000000..7899773 --- /dev/null +++ b/examples/stm32f1/obldc/usart_irq/usart_irq.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Linker script for Open-BLDC (STM32F103CBT6, 128K flash, 20K RAM). */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32.ld + diff --git a/examples/stm32f1/other/adc_temperature_sensor/Makefile b/examples/stm32f1/other/adc_temperature_sensor/Makefile new file mode 100644 index 0000000..f3f65c4 --- /dev/null +++ b/examples/stm32f1/other/adc_temperature_sensor/Makefile @@ -0,0 +1,23 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +## + +BINARY = adc + +include ../../Makefile.include + diff --git a/examples/stm32f1/other/adc_temperature_sensor/README b/examples/stm32f1/other/adc_temperature_sensor/README new file mode 100644 index 0000000..aa00ef0 --- /dev/null +++ b/examples/stm32f1/other/adc_temperature_sensor/README @@ -0,0 +1,10 @@ +------------------------------------------------------------------------------ +README +------------------------------------------------------------------------------ + +This example program sends some characters on USART1. +Afterwards it read out the internal temperature sensor of the STM32 and +sends the value read out from the ADC to the USART1. + +The terminal settings for the receiving device/PC are 115200 8n1. + diff --git a/examples/stm32f1/other/adc_temperature_sensor/adc.c b/examples/stm32f1/other/adc_temperature_sensor/adc.c new file mode 100644 index 0000000..6c0e828 --- /dev/null +++ b/examples/stm32f1/other/adc_temperature_sensor/adc.c @@ -0,0 +1,155 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include + +void usart_setup(void) +{ + /* Enable clocks for GPIO port A (for GPIO_USART1_TX) and USART1. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_USART1EN); + + /* Setup GPIO pin GPIO_USART1_TX/GPIO9 on GPIO port A for transmit. */ + gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_USART1_TX); + + /* Setup UART parameters. */ + usart_set_baudrate(USART1, 115200); + usart_set_databits(USART1, 8); + usart_set_stopbits(USART1, USART_STOPBITS_1); + usart_set_mode(USART1, USART_MODE_TX_RX); + usart_set_parity(USART1, USART_PARITY_NONE); + usart_set_flow_control(USART1, USART_FLOWCONTROL_NONE); + + /* Finally enable the USART. */ + usart_enable(USART1); +} + +void gpio_setup(void) +{ + /* Enable GPIOB clock. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPBEN); + + /* Set GPIO6/7 (in GPIO port B) to 'output push-pull' for the LEDs. */ + gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_2_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO6); + gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_2_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO7); +} + +void adc_setup(void) +{ + int i; + + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_ADC1EN); + + /* Make shure it doesn't run during config. */ + adc_off(ADC1); + + /* We configure everything for one single conversion. */ + adc_disable_scan_mode(ADC1); + adc_set_single_conversion_mode(ADC1); + adc_enable_discontinous_mode_regular(ADC1); + adc_disable_external_trigger_regular(ADC1); + adc_set_right_aligned(ADC1); + /* We want to read the temperature sensor, so we have to enable it. */ + adc_enable_temperature_sensor(ADC1); + adc_set_conversion_time_on_all_channels(ADC1, ADC_SMPR_SMP_28DOT5CYC); + + adc_on(ADC1); + + /* Wait for ADC starting up. */ + for (i = 0; i < 800000; i++) /* Wait a bit. */ + __asm__("nop"); + + adc_reset_calibration(ADC1); + adc_calibration(ADC1); +} + +void my_usart_print_int(u32 usart, int value) +{ + s8 i; + u8 nr_digits = 0; + char buffer[25]; + + if (value < 0) { + usart_send(usart, '-'); + value = value * -1; + } + + while (value > 0) { + buffer[nr_digits++] = "0123456789"[value % 10]; + value /= 10; + } + + for (i = nr_digits; i >= 0; i--) + usart_send(usart, buffer[i]); +} + +int main(void) +{ + u8 channel_array[16]; + u16 temperature; + + rcc_clock_setup_in_hse_16mhz_out_72mhz(); + gpio_setup(); + usart_setup(); + adc_setup(); + + gpio_clear(GPIOB, GPIO7); /* LED1 on */ + gpio_set(GPIOB, GPIO6); /* LED2 off */ + + /* Send a message on USART1. */ + usart_send(USART1, 's'); + usart_send(USART1, 't'); + usart_send(USART1, 'm'); + usart_send(USART1, '\r'); + usart_send(USART1, '\n'); + + /* Select the channel we want to convert. 16=temperature_sensor. */ + channel_array[0] = 16; + adc_set_regular_sequence(ADC1, 1, channel_array); + + /* + * If the ADC_CR2_ON bit is already set -> setting it another time + * starts the conversion. + */ + adc_on(ADC1); + + /* Wait for end of conversion. */ + while (!(ADC_SR(ADC1) & ADC_SR_EOC)); + + temperature = ADC_DR(ADC1); + + /* + * That's actually not the real temperature - you have to compute it + * as described in the datasheet. + */ + my_usart_print_int(USART1, temperature); + + gpio_clear(GPIOB, GPIO6); /* LED2 on */ + + while(1); /* Halt. */ + + return 0; +} diff --git a/examples/stm32f1/other/adc_temperature_sensor/adc.ld b/examples/stm32f1/other/adc_temperature_sensor/adc.ld new file mode 100644 index 0000000..c076521 --- /dev/null +++ b/examples/stm32f1/other/adc_temperature_sensor/adc.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Linker script for an STM32F103RBT6 board (128K flash, 20K RAM). */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32.ld + diff --git a/examples/stm32f1/other/dma_mem2mem/Makefile b/examples/stm32f1/other/dma_mem2mem/Makefile new file mode 100644 index 0000000..c43650d --- /dev/null +++ b/examples/stm32f1/other/dma_mem2mem/Makefile @@ -0,0 +1,23 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +## + +BINARY = dma + +include ../../Makefile.include + diff --git a/examples/stm32f1/other/dma_mem2mem/README b/examples/stm32f1/other/dma_mem2mem/README new file mode 100644 index 0000000..2e61e5a --- /dev/null +++ b/examples/stm32f1/other/dma_mem2mem/README @@ -0,0 +1,11 @@ +------------------------------------------------------------------------------ +README +------------------------------------------------------------------------------ + +This program demonstrates a little DMA MEM2MEM transfer. A string is send out +to USART1 and afterwards copied by DMA to another memory location. To check +if the transfer was successful we send the destination string also out to +USART1. + +The terminal settings for the receiving device/PC are 115200 8n1. + diff --git a/examples/stm32f1/other/dma_mem2mem/dma.c b/examples/stm32f1/other/dma_mem2mem/dma.c new file mode 100644 index 0000000..e43fe0d --- /dev/null +++ b/examples/stm32f1/other/dma_mem2mem/dma.c @@ -0,0 +1,133 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include + +void usart_setup(void) +{ + /* Enable clocks for GPIO port A (for GPIO_USART1_TX) and USART1. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_USART1EN); + + /* Setup GPIO pin GPIO_USART1_TX/GPIO9 on GPIO port A for transmit. */ + gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_USART1_TX); + + /* Setup UART parameters. */ + usart_set_baudrate(USART1, 115200); + usart_set_databits(USART1, 8); + usart_set_stopbits(USART1, USART_STOPBITS_1); + usart_set_mode(USART1, USART_MODE_TX_RX); + usart_set_parity(USART1, USART_PARITY_NONE); + usart_set_flow_control(USART1, USART_FLOWCONTROL_NONE); + + /* Finally enable the USART. */ + usart_enable(USART1); +} + +void gpio_setup(void) +{ + /* Enable GPIOB clock. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPBEN); + + /* Set GPIO6/7 (in GPIO port B) to 'output push-pull' for the LEDs. */ + gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_2_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO6); + gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_2_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO7); +} + +void my_usart_print_string(u32 usart, char * s) +{ + while (*s != 0) { + usart_send(usart, *s); + s++; + } +} + +int main(void) +{ + /* Exactly 20 bytes including '0' at the end. + We want to transfer 32bit * 5 so it should fit */ + char s1[20] = "Hello STM MEM2MEM\r\n"; + char s2[20]; + + rcc_clock_setup_in_hse_16mhz_out_72mhz(); + gpio_setup(); + usart_setup(); + + gpio_clear(GPIOB, GPIO7); /* LED1 on */ + gpio_set(GPIOB, GPIO6); /* LED2 off */ + + my_usart_print_string(USART1, "s1 "); + my_usart_print_string(USART1, s1); + + rcc_peripheral_enable_clock(&RCC_AHBENR, RCC_AHBENR_DMA1EN); + + /* MEM2MEM mode for channel 1. */ + dma_enable_mem2mem_mode(DMA1, DMA_CHANNEL1); + + /* Highest priority. */ + dma_set_priority(DMA1, DMA_CHANNEL1, DMA_CCR1_PL_VERY_HIGH); + + /* 32Bit wide transfer for source and destination. */ + dma_set_memory_size(DMA1, DMA_CHANNEL1, DMA_CCR1_MSIZE_32BIT); + dma_set_peripheral_size(DMA1, DMA_CHANNEL1, DMA_CCR1_PSIZE_32BIT); + + /* After each 32Bit we have to increase the addres because we use RAM. */ + dma_enable_memory_increment_mode(DMA1, DMA_CHANNEL1); + dma_enable_peripheral_increment_mode(DMA1, DMA_CHANNEL1); + + /* We define the source as peripheral. */ + dma_set_read_from_peripheral(DMA1, DMA_CHANNEL1); + + /* We want to transfer string s1. */ + dma_set_peripheral_address(DMA1, DMA_CHANNEL1, (u32) &s1); + + /* Destination should be string s2. */ + dma_set_memory_address(DMA1, DMA_CHANNEL1, (u32) &s2); + + /* Set number of DATA to transfer. + Remember that this means not necessary bytes but MSIZE or PSIZE + depending from your source device. */ + dma_set_number_of_data(DMA1, DMA_CHANNEL1, 5); + + /* Start DMA transfer. */ + dma_enable_channel(DMA1, DMA_CHANNEL1); + + /* TODO: write a function to get the interrupt flags. */ + while(!(DMA_ISR(DMA1) & 0x0000001)) + { + } + + dma_disable_channel(DMA1, DMA_CHANNEL1); + + /* String s1 should now already be transferred to s2. */ + my_usart_print_string(USART1, "s2 "); + my_usart_print_string(USART1, s2); + + gpio_clear(GPIOB, GPIO6); /* LED2 on */ + while(1); /* Halt. */ + + return 0; +} diff --git a/examples/stm32f1/other/dma_mem2mem/dma.ld b/examples/stm32f1/other/dma_mem2mem/dma.ld new file mode 100644 index 0000000..c076521 --- /dev/null +++ b/examples/stm32f1/other/dma_mem2mem/dma.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Linker script for an STM32F103RBT6 board (128K flash, 20K RAM). */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32.ld + diff --git a/examples/stm32f1/other/dogm128/Makefile b/examples/stm32f1/other/dogm128/Makefile new file mode 100644 index 0000000..97a012e --- /dev/null +++ b/examples/stm32f1/other/dogm128/Makefile @@ -0,0 +1,25 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +## + +BINARY = main + +OBJS = dogm128.o + +include ../../Makefile.include + diff --git a/examples/stm32f1/other/dogm128/README b/examples/stm32f1/other/dogm128/README new file mode 100644 index 0000000..dbf82a0 --- /dev/null +++ b/examples/stm32f1/other/dogm128/README @@ -0,0 +1,7 @@ +------------------------------------------------------------------------------ +README +------------------------------------------------------------------------------ + +This example program writes some text on an DOGM128 LCD display connected +to SPI2. + diff --git a/examples/stm32f1/other/dogm128/dogm128.c b/examples/stm32f1/other/dogm128/dogm128.c new file mode 100644 index 0000000..c78a275 --- /dev/null +++ b/examples/stm32f1/other/dogm128/dogm128.c @@ -0,0 +1,291 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "./dogm128.h" + +u8 dogm128_ram[1024]; +u8 dogm128_cursor_x; +u8 dogm128_cursor_y; + +void dogm128_send_command(u8 command) +{ + u32 counter; + + gpio_clear(DOGM128_A0_PORT, DOGM128_A0_PIN); /* A0 low for commands */ + spi_send(DOGM128_SPI, command); + + for (counter = 0; counter<=500; counter++) /* wait */ + {} +} + +void dogm128_send_data(u8 data) +{ + u32 counter; + + gpio_set(DOGM128_A0_PORT, DOGM128_A0_PIN); /* A0 high for data */ + spi_send(DOGM128_SPI, data); + + for (counter = 0; counter<=500; counter++) /* wait */ + {} +} + +void dogm128_init() +{ + u32 counter; + + /* reset the display */ + gpio_clear(DOGM128_RESET_PORT, DOGM128_RESET_PIN); /* reset low for dogm128 */ + for (counter = 0; counter<=60000; counter++) /* wait */ + {} + gpio_set(DOGM128_RESET_PORT, DOGM128_RESET_PIN); /* reset high for dogm128 */ + + for (counter = 0; counter<=60000; counter++) /* wait */ + {} + + gpio_clear(DOGM128_A0_PORT, DOGM128_A0_PIN); /* A0 low for init */ + + /* tell the display that we want to start */ + spi_set_nss_low(DOGM128_SPI); + + /* init sequence */ + dogm128_send_command(DOGM128_DISPLAY_START_ADDRESS_BASE + 0); + dogm128_send_command(DOGM128_ADC_REVERSE); + dogm128_send_command(DOGM128_COM_OUTPUT_SCAN_NORMAL); + dogm128_send_command(DOGM128_DISPLAY_NORMAL); + dogm128_send_command(DOGM128_BIAS_19); + dogm128_send_command(DOGM128_POWER_CONTROL_BASE + 0x07); + dogm128_send_command(DOGM128_BOOSTER_RATIO_SET); + dogm128_send_command(0x00); /* Booster x4 */ + dogm128_send_command(DOGM128_V0_OUTPUT_RESISTOR_BASE + 0x07); + dogm128_send_command(DOGM128_ELECTRONIC_VOLUME_MODE_SET); + dogm128_send_command(0x16); /* Contrast */ + dogm128_send_command(DOGM128_STATIC_INDICATOR_OFF); + dogm128_send_command(0x00); /* Flashing OFF */ + dogm128_send_command(DOGM128_DISPLAY_ON); + + /* end transfer */ + spi_set_nss_high(DOGM128_SPI); +} + +void dogm128_print_char(u8 data) +{ + u8 i; + u8 page; + u8 shift; + u8 xcoord; + u8 ycoord; + + xcoord = dogm128_cursor_x; + ycoord = dogm128_cursor_y; + + page = (63 - ycoord) / 8; /* the display consists of 8 lines a 8 dots each. */ + shift = (7 -((63 - ycoord) % 8)); /* vertical shift */ + + /* font is 8x5 so iterate each column of the character */ + for (i = 0; i <= 5; i++) { + /* right border reached? */ + if ((xcoord + i) > 127) + return; + dogm128_cursor_x++; + + /* 0xAA = end of character - no dots in this line */ + if (dogm128_font[data - 0x20][i] == 0xAA) { + dogm128_ram[(page * 128) + xcoord + i] &= ~(0xFF >> shift); /* clear area */ + if ((shift > 0) && (page > 0)) + dogm128_ram[((page - 1) * 128) + xcoord + i] &= ~(0xFF << (8 - shift)); /* clear area */ + return; + } + + /* lower part */ + dogm128_ram[(page * 128) + xcoord + i] &= ~(0xFF >> shift); /* clear area */ + dogm128_ram[(page * 128) + xcoord + i] = (dogm128_font[data - 0x20][i] >> shift); + /* higher part if needed */ + if ((shift > 0) && (page > 0)) { + dogm128_ram[((page - 1) * 128) + xcoord + i] &= ~(0xFF << (8 - shift)); /* clear area */ + dogm128_ram[((page - 1) * 128) + xcoord + i] = (dogm128_font[data - 0x20][i] << (8 - shift)); + } + } +} + +void dogm128_set_cursor(u8 xcoord, u8 ycoord) +{ + dogm128_cursor_x = xcoord; + dogm128_cursor_y = ycoord; +} + +void dogm128_print_string(char * s) +{ + while (*s != 0) { + dogm128_print_char(*s); + s++; + } +} + +void dogm128_set_dot(u8 xcoord, u8 ycoord) +{ + dogm128_ram[(((63 - ycoord) / 8) * 128) + xcoord] |= (1 << ((63 - ycoord) % 8)); +} + +void dogm128_clear_dot(u8 xcoord, u8 ycoord) +{ + dogm128_ram[(((63 - ycoord) / 8) * 128) + xcoord] &= ~(1 << ((63 - ycoord) % 8)); +} + +void dogm128_update_display() +{ + u8 page; + u8 column; + + /* tell the display that we want to start */ + spi_set_nss_low(DOGM128_SPI); + + for (page = 0; page <= 7; page++) { + dogm128_send_command(0xB0 + page); /* set page */ + dogm128_send_command(0x10); /* set column upper address to 0 */ + dogm128_send_command(0x00); /* set column lower address to 0 */ + + for (column = 0; column <= 127; column++) { + dogm128_send_data(dogm128_ram[(page * 128) + column]); + } + } + + spi_set_nss_high(DOGM128_SPI); +} + +void dogm128_clear() +{ + u16 i; + + for (i = 0; i<=1023; i++) { + dogm128_ram[i] = 0; + } + dogm128_update_display(); +} + +/* This is a non-monospace font definition (upside down for better handling). + * 0xAA is the end of the character so its not space efficient in your memory, but on your display. + * We are starting with " " as the first printable character at 0x20, so we have to substract 0x20 later. + * Its the only defined to 127/0x7F so if you have german umlauts or other special characters from above + * you have to expand this definition a little bit. */ + +const u8 dogm128_font[96][6] = { + + /* 20 SPACE */ {0x00, 0x00, 0x00, 0xAA, 0xAA, 0xAA}, + /* 21 ! */ {0x5E, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA}, + /* 22 " */ {0x66, 0x00, 0x66, 0xAA, 0xAA, 0xAA}, + /* 23 # */ {0x28, 0x7C, 0x28, 0x7C, 0x28, 0xAA}, + /* 24 $ */ {0x24, 0x2A, 0x7F, 0x2A, 0x10, 0xAA}, + /* 25 % */ {0x62, 0x18, 0x46, 0xAA, 0xAA, 0xAA}, + /* 26 & */ {0x30, 0x4C, 0x5A, 0x24, 0x50, 0xAA}, + /* 27 ' */ {0x06, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA}, + /* 28 ( */ {0x3E, 0x41, 0xAA, 0xAA, 0xAA, 0xAA}, + /* 29 ) */ {0x41, 0x3E, 0xAA, 0xAA, 0xAA, 0xAA}, + /* 2A * */ {0x28, 0x10, 0x7C, 0x10, 0x28, 0xAA}, + /* 2B + */ {0x10, 0x38, 0x10, 0xAA, 0xAA, 0xAA}, + /* 2C , */ {0xC0, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA}, + /* 2D - */ {0x10, 0x10, 0x10, 0xAA, 0xAA, 0xAA}, + /* 2E . */ {0x40, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA}, + /* 2F / */ {0x60, 0x18, 0x06, 0xAA, 0xAA, 0xAA}, + + /* 30 0 */ {0x3C, 0x42, 0x42, 0x3C, 0xAA, 0xAA}, + /* 31 1 */ {0x44, 0x7E, 0x40, 0xAA, 0xAA, 0xAA}, + /* 32 2 */ {0x44, 0x62, 0x52, 0x4C, 0xAA, 0xAA}, + /* 33 3 */ {0x4A, 0x4A, 0x34, 0xAA, 0xAA, 0xAA}, + /* 34 4 */ {0x1E, 0x10, 0x78, 0x10, 0xAA, 0xAA}, + /* 35 5 */ {0x4E, 0x4A, 0x32, 0xAA, 0xAA, 0xAA}, + /* 36 6 */ {0x3C, 0x4A, 0x4A, 0x30, 0xAA, 0xAA}, + /* 37 7 */ {0x62, 0x12, 0x0E, 0xAA, 0xAA, 0xAA}, + /* 38 8 */ {0x34, 0x4A, 0x4A, 0x34, 0xAA, 0xAA}, + /* 39 9 */ {0x0C, 0x52, 0x52, 0x3C, 0xAA, 0xAA}, + /* 3A : */ {0x28, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA}, + /* 3B ; */ {0xC8, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA}, + /* 3C < */ {0x10, 0x28, 0x44, 0xAA, 0xAA, 0xAA}, + /* 3D = */ {0x28, 0x28, 0x28, 0xAA, 0xAA, 0xAA}, + /* 3E > */ {0x44, 0x28, 0x10, 0xAA, 0xAA, 0xAA}, + /* 3F ? */ {0x02, 0x52, 0x0C, 0xAA, 0xAA, 0xAA}, + + /* 40 @ */ {0x3C, 0x42, 0x12, 0x2A, 0x3C, 0xAA}, + /* 41 A */ {0x7C, 0x12, 0x12, 0x7C, 0xAA, 0xAA}, + /* 42 B */ {0x7E, 0x4A, 0x4A, 0x34, 0xAA, 0xAA}, + /* 43 C */ {0x3C, 0x42, 0x42, 0x24, 0xAA, 0xAA}, + /* 44 D */ {0x7E, 0x42, 0x42, 0x3C, 0xAA, 0xAA}, + /* 45 E */ {0x7E, 0x4A, 0x4A, 0xAA, 0xAA, 0xAA}, + /* 46 F */ {0x7E, 0x0A, 0x0A, 0xAA, 0xAA, 0xAA}, + /* 47 G */ {0x3C, 0x42, 0x52, 0x34, 0xAA, 0xAA}, + /* 48 H */ {0x7E, 0x08, 0x08, 0x7E, 0xAA, 0xAA}, + /* 49 I */ {0x42, 0x7E, 0x42, 0xAA, 0xAA, 0xAA}, + /* 4A J */ {0x42, 0x42, 0x3E, 0xAA, 0xAA, 0xAA}, + /* 4B K */ {0x7E, 0x08, 0x14, 0x62, 0xAA, 0xAA}, + /* 4C L */ {0x7E, 0x40, 0x40, 0xAA, 0xAA, 0xAA}, + /* 4D M */ {0x7E, 0x04, 0x08, 0x04, 0x7E, 0xAA}, + /* 4E N */ {0x7E, 0x04, 0x18, 0x20, 0x7E, 0xAA}, + /* 4F O */ {0x3C, 0x42, 0x42, 0x3C, 0xAA, 0xAA}, + + /* 50 P */ {0x7E, 0x12, 0x12, 0x0C, 0xAA, 0xAA}, + /* 51 Q */ {0x3C, 0x42, 0x42, 0xBC, 0xAA, 0xAA}, + /* 52 R */ {0x7E, 0x12, 0x12, 0x6C, 0xAA, 0xAA}, + /* 53 S */ {0x44, 0x4A, 0x4A, 0x30, 0xAA, 0xAA}, + /* 54 T */ {0x02, 0x7E, 0x02, 0xAA, 0xAA, 0xAA}, + /* 55 U */ {0x3E, 0x40, 0x40, 0x3E, 0xAA, 0xAA}, + /* 56 V */ {0x06, 0x18, 0x60, 0x18, 0x06, 0xAA}, + /* 57 W */ {0x3E, 0x40, 0x3E, 0x40, 0x3E, 0xAA}, + /* 58 X */ {0x42, 0x24, 0x18, 0x24, 0x42, 0xAA}, + /* 59 Y */ {0x9E, 0xA0, 0xA0, 0x7E, 0xAA, 0xAA}, + /* 5A Z */ {0x62, 0x52, 0x4A, 0x46, 0xAA, 0xAA}, + /* 5B [ */ {0x7E, 0x42, 0xAA, 0xAA, 0xAA, 0xAA}, + /* 5C \ */ {0x06, 0x18, 0x60, 0xAA, 0xAA, 0xAA}, + /* 5D ] */ {0x42, 0x7E, 0xAA, 0xAA, 0xAA, 0xAA}, + /* 5E ^ */ {0x04, 0x02, 0x04, 0xAA, 0xAA, 0xAA}, + /* 5F _ */ {0x40, 0x40, 0x40, 0xAA, 0xAA, 0xAA}, + + /* 60 ` */ {0x02, 0x04, 0xAA, 0xAA, 0xAA, 0xAA}, + /* 61 a */ {0x20, 0x54, 0x54, 0x78, 0xAA, 0xAA}, + /* 62 b */ {0x7E, 0x44, 0x44, 0x38, 0xAA, 0xAA}, + /* 63 c */ {0x38, 0x44, 0x44, 0x28, 0xAA, 0xAA}, + /* 64 d */ {0x38, 0x44, 0x44, 0x7E, 0xAA, 0xAA}, + /* 65 e */ {0x38, 0x54, 0x54, 0x58, 0xAA, 0xAA}, + /* 66 f */ {0x7C, 0x0A, 0xAA, 0xAA, 0xAA, 0xAA}, + /* 67 g */ {0x98, 0xA4, 0xA4, 0x7C, 0xAA, 0xAA}, + /* 68 h */ {0x7E, 0x04, 0x04, 0x78, 0xAA, 0xAA}, + /* 69 i */ {0x7A, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA}, + /* 6A j */ {0x40, 0x3A, 0xAA, 0xAA, 0xAA, 0xAA}, + /* 6B k */ {0x7E, 0x10, 0x28, 0x44, 0xAA, 0xAA}, + /* 6C l */ {0x7E, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA}, + /* 6D m */ {0x7C, 0x04, 0x78, 0x04, 0x78, 0xAA}, + /* 6E n */ {0x7C, 0x04, 0x04, 0x78, 0xAA, 0xAA}, + /* 6F o */ {0x38, 0x44, 0x44, 0x38, 0xAA, 0xAA}, + + /* 70 p */ {0xFC, 0x24, 0x24, 0x18, 0xAA, 0xAA}, + /* 71 q */ {0x18, 0x24, 0x24, 0xFC, 0xAA, 0xAA}, + /* 72 r */ {0x78, 0x04, 0xAA, 0xAA, 0xAA, 0xAA}, + /* 73 s */ {0x48, 0x54, 0x54, 0x20, 0xAA, 0xAA}, + /* 74 t */ {0x04, 0x3E, 0x44, 0xAA, 0xAA, 0xAA}, + /* 75 u */ {0x3C, 0x40, 0x40, 0x3C, 0xAA, 0xAA}, + /* 76 v */ {0x0C, 0x30, 0x40, 0x30, 0x0C, 0xAA}, + /* 77 w */ {0x3C, 0x40, 0x3C, 0x40, 0x3C, 0xAA}, + /* 78 x */ {0x44, 0x28, 0x10, 0x28, 0x44, 0xAA}, + /* 79 y */ {0x1C, 0xA0, 0xA0, 0x7C, 0xAA, 0xAA}, + /* 7A z */ {0x64, 0x54, 0x4C, 0xAA, 0xAA, 0xAA}, + /* 7B { */ {0x08, 0x36, 0x41, 0xAA, 0xAA, 0xAA}, + /* 7C | */ {0x7E, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA}, + /* 7D } */ {0x41, 0x36, 0x08, 0xAA, 0xAA, 0xAA}, + /* 7E ~ */ {0x20, 0x10, 0x20, 0x10, 0xAA, 0xAA}, + /* 7F DEL */ {0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA} +}; + diff --git a/examples/stm32f1/other/dogm128/dogm128.h b/examples/stm32f1/other/dogm128/dogm128.h new file mode 100644 index 0000000..ed514ab --- /dev/null +++ b/examples/stm32f1/other/dogm128/dogm128.h @@ -0,0 +1,86 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef DOGM128_H +#define DOGM128_H + +#include +#include +#include + +/* PB10 GPIO - ~RESET + * PB12 SPI2_NSS - ~CS1 + * PB13 SPI2_SCK - SCL + * PB14 SPI2_MISO - A0 + * PB15 SPI2_MOSI - SI */ + +#define DOGM128_SPI SPI2 +#define DOGM128_RESET_PIN GPIO10 +#define DOGM128_RESET_PORT GPIOB +#define DOGM128_A0_PIN GPIO14 +#define DOGM128_A0_PORT GPIOB + +/* DOGM128 display commands */ +#define DOGM128_PAGE_BASE 0xB0 +#define DOGM128_PAGE0 0xB0 +#define DOGM128_PAGE1 0xB1 +#define DOGM128_PAGE2 0xB2 +#define DOGM128_PAGE3 0xB3 +#define DOGM128_PAGE4 0xB4 +#define DOGM128_PAGE5 0xB5 +#define DOGM128_PAGE6 0xB6 +#define DOGM128_PAGE7 0xB7 +#define DOGM128_DISPLAY_ON 0xAF +#define DOGM128_DISPLAY_OFF 0xAE +#define DOGM128_DISPLAY_START_ADDRESS_BASE 0x40 +#define DOGM128_ADC_NORMAL 0xA0 +#define DOGM128_ADC_REVERSE 0xA1 +#define DOGM128_DISPLAY_NORMAL 0xA6 +#define DOGM128_DISPLAY_REVERSE 0xA7 +#define DOGM128_ALL_POINTS_ON 0xA5 +#define DOGM128_ALL_POINTS_OFF 0xA4 +#define DOGM128_BIAS_19 0xA2 +#define DOGM128_BIAS_17 0xA3 +#define DOGM128_INTERNAL_RESET 0xE2 +#define DOGM128_COM_OUTPUT_SCAN_NORMAL 0xC0 +#define DOGM128_COM_OUTPUT_SCAN_REVERSE 0xC8 +#define DOGM128_POWER_CONTROL_BASE 0x28 +#define DOGM128_V0_OUTPUT_RESISTOR_BASE 0x20 +#define DOGM128_ELECTRONIC_VOLUME_MODE_SET 0x81 +#define DOGM128_STATIC_INDICATOR_OFF 0xAC +#define DOGM128_STATIC_INDICATOR_ON 0xAD +#define DOGM128_BOOSTER_RATIO_SET 0xF8 + +extern const u8 dogm128_font[96][6]; +extern u8 dogm128_ram[1024]; +extern u8 dogm128_cursor_x; +extern u8 dogm128_cursor_y; + +void dogm128_send_command(u8 command); +void dogm128_set_cursor(u8 xcoord, u8 ycoord); +void dogm128_print_char(u8 data); +void dogm128_print_string(char * s); +void dogm128_set_dot(u8 xcoord, u8 ycoord); +void dogm128_clear_dot(u8 xcoord, u8 ycoord); +void dogm128_send_data(u8 data); +void dogm128_init(); +void dogm128_update_display(); +void dogm128_clear(); + +#endif diff --git a/examples/stm32f1/other/dogm128/main.c b/examples/stm32f1/other/dogm128/main.c new file mode 100644 index 0000000..b12a36d --- /dev/null +++ b/examples/stm32f1/other/dogm128/main.c @@ -0,0 +1,110 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include +#include +#include +#include "./dogm128.h" + +void gpio_setup(void) +{ + /* Enable GPIOB clock. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPBEN); + + /* Set GPIO6/7 (in GPIO port B) to 'output push-pull' for the LEDs. */ + gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_2_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO6); + gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_2_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO7); + + /* A0 of DOGM128 */ + gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO14); + /*reset of DOGM128 */ + gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO10); + + /* DOGM128/SPI2 clock and MOSI and NSS(CS1) */ + gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO12); + gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO13); + gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO15); +} + +void spi_setup() +{ + /* the DOGM128 display is connected to SPI2, so initialise it correctly */ + + rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_SPI2EN); + + spi_set_unidirectional_mode(DOGM128_SPI); /* we want to send only */ + spi_disable_crc(DOGM128_SPI); /* no CRC for this slave */ + spi_set_dff_8bit(DOGM128_SPI); /* 8-bit dataword-length */ + spi_set_full_duplex_mode(DOGM128_SPI); /* not receive-only */ + spi_enable_software_slave_management(DOGM128_SPI); /* we want to handle the CS signal in software */ + spi_set_nss_high(DOGM128_SPI); + spi_set_baudrate_prescaler(DOGM128_SPI, SPI_CR1_BR_FPCLK_DIV_256); /* PCLOCK/256 as clock */ + spi_set_master_mode(DOGM128_SPI); /* we want to control everything and generate the clock -> master */ + spi_set_clock_polarity_1(DOGM128_SPI); /* sck idle state high */ + spi_set_clock_phase_1(DOGM128_SPI); /* bit is taken on the second (rising edge) of sck */ + spi_enable_ss_output(DOGM128_SPI); + spi_enable(DOGM128_SPI); +} + +int main(void) +{ + rcc_clock_setup_in_hse_16mhz_out_72mhz(); + gpio_setup(); + spi_setup(); + + gpio_clear(GPIOB, GPIO7); /* LED1 on */ + gpio_set(GPIOB, GPIO6); /* LED2 off */ + + dogm128_init(); + dogm128_clear(); + + dogm128_set_cursor(0, 56); + dogm128_print_string("ABCDEFGHIJKLMNOPQRSTUVWXYZ"); + dogm128_set_cursor(0, 48); + dogm128_print_string("abcdefghijklmnopqrstuvwxyz"); + dogm128_set_cursor(0, 40); + dogm128_print_string(" !#$%&'()*+,-./0123456789"); + dogm128_set_cursor(0, 32); + dogm128_print_string(":;<=>?@[\\]^_`{|}~"); + + dogm128_set_dot(10, 10); + dogm128_set_dot(20, 10); + dogm128_set_dot(30, 10); + dogm128_set_dot(40, 10); + dogm128_set_dot(50, 10); + + dogm128_update_display(); + + gpio_set(GPIOB, GPIO7); /* LED1 off */ + while(1); /* Halt. */ + + return 0; +} + diff --git a/examples/stm32f1/other/dogm128/main.ld b/examples/stm32f1/other/dogm128/main.ld new file mode 100644 index 0000000..c076521 --- /dev/null +++ b/examples/stm32f1/other/dogm128/main.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Linker script for an STM32F103RBT6 board (128K flash, 20K RAM). */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32.ld + diff --git a/examples/stm32f1/other/i2c_stts75_sensor/Makefile b/examples/stm32f1/other/i2c_stts75_sensor/Makefile new file mode 100644 index 0000000..d0f6ddf --- /dev/null +++ b/examples/stm32f1/other/i2c_stts75_sensor/Makefile @@ -0,0 +1,25 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +## + +BINARY = i2c_stts75_sensor + +OBJS = stts75.o + +include ../../Makefile.include + diff --git a/examples/stm32f1/other/i2c_stts75_sensor/README b/examples/stm32f1/other/i2c_stts75_sensor/README new file mode 100644 index 0000000..91e3ff6 --- /dev/null +++ b/examples/stm32f1/other/i2c_stts75_sensor/README @@ -0,0 +1,13 @@ +------------------------------------------------------------------------------ +README +------------------------------------------------------------------------------ + +This example program sends some characters on USART1. +Afterwards it connects to an STTS75 sensor (ST LM75 compatible) +at adress A0/1/2=0 and sets reverse polarity, 26 degree Tos and Thyst. + +It reads out the temperature and submits the temperature over USART1 in +binary format (ASCII 0/1). + +The terminal settings for the receiving device/PC are 115200 8n1. + diff --git a/examples/stm32f1/other/i2c_stts75_sensor/i2c_stts75_sensor.c b/examples/stm32f1/other/i2c_stts75_sensor/i2c_stts75_sensor.c new file mode 100644 index 0000000..f70c80d --- /dev/null +++ b/examples/stm32f1/other/i2c_stts75_sensor/i2c_stts75_sensor.c @@ -0,0 +1,146 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include +#include "stts75.h" + +void usart_setup(void) +{ + /* Enable clocks for GPIO port A (for GPIO_USART1_TX) and USART1. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_USART1EN); + + /* Setup GPIO pin GPIO_USART1_TX/GPIO9 on GPIO port A for transmit. */ + gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_USART1_TX); + + /* Setup UART parameters. */ + usart_set_baudrate(USART1, 115200); + usart_set_databits(USART1, 8); + usart_set_stopbits(USART1, USART_STOPBITS_1); + usart_set_mode(USART1, USART_MODE_TX_RX); + usart_set_parity(USART1, USART_PARITY_NONE); + usart_set_flow_control(USART1, USART_FLOWCONTROL_NONE); + + /* Finally enable the USART. */ + usart_enable(USART1); +} + +void gpio_setup(void) +{ + /* Enable GPIOB clock. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPBEN); + + /* Set GPIO6/7 (in GPIO port B) to 'output push-pull' for the LEDs. */ + gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_2_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO6); + gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_2_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO7); +} + +void i2c_setup(void) +{ + /* Enable clocks for I2C2 and AFIO. */ + rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_I2C2EN); + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_AFIOEN); + + /* Set alternate functions for the SCL and SDA pins of I2C2. */ + gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN, + GPIO_I2C2_SCL | GPIO_I2C2_SDA); + + /* Disable the I2C before changing any configuration. */ + i2c_peripheral_disable(I2C2); + + /* APB1 is running at 36MHz. */ + i2c_set_clock_frequency(I2C2, I2C_CR2_FREQ_36MHZ); + + /* 400KHz - I2C Fast Mode */ + i2c_set_fast_mode(I2C2); + + /* + * fclock for I2C is 36MHz APB2 -> cycle time 28ns, low time at 400KHz + * incl trise -> Thigh= 1600ns; CCR= tlow/tcycle= 0x1C,9; + * datasheet suggests 0x1e. + */ + i2c_set_ccr(I2C2, 0x1e); + + /* + * fclock for I2C is 36MHz -> cycle time 28ns, rise time for + * 400KHz => 300ns and 100KHz => 1000ns; 300ns/28ns = 10; + * incremented by 1 -> 11. + */ + i2c_set_trise(I2C2, 0x0b); + + /* + * This is our slave address - needed only if we want to receive from + * other masters. + */ + i2c_set_own_7bit_slave_address(I2C2, 0x32); + + /* If everything is configured -> enable the peripheral. */ + i2c_peripheral_enable(I2C2); +} + +int main(void) +{ + int i = 0; + u16 temperature; + + rcc_clock_setup_in_hse_16mhz_out_72mhz(); + gpio_setup(); + usart_setup(); + i2c_setup(); + + gpio_clear(GPIOB, GPIO7); /* LED1 on */ + gpio_set(GPIOB, GPIO6); /* LED2 off */ + + /* Send a message on USART1. */ + usart_send(USART1, 's'); + usart_send(USART1, 't'); + usart_send(USART1, 'm'); + usart_send(USART1, '\r'); + usart_send(USART1, '\n'); + + stts75_write_config(I2C2, STTS75_SENSOR0); + stts75_write_temp_os(I2C2, STTS75_SENSOR0, 0x1a00); /* 26 degrees */ + stts75_write_temp_hyst(I2C2, STTS75_SENSOR0, 0x1a00); + temperature = stts75_read_temperature(I2C2, STTS75_SENSOR0); + + /* Send the temperature as binary over USART1. */ + for (i = 15; i >= 0 ; i--) { + if (temperature & (1 << i)) + usart_send(USART1, '1'); + else + usart_send(USART1, '0'); + } + + usart_send(USART1, '\r'); + usart_send(USART1, '\n'); + + gpio_clear(GPIOB, GPIO6); /* LED2 on */ + + while(1); /* Halt. */ + + return 0; +} diff --git a/examples/stm32f1/other/i2c_stts75_sensor/i2c_stts75_sensor.ld b/examples/stm32f1/other/i2c_stts75_sensor/i2c_stts75_sensor.ld new file mode 100644 index 0000000..c076521 --- /dev/null +++ b/examples/stm32f1/other/i2c_stts75_sensor/i2c_stts75_sensor.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Linker script for an STM32F103RBT6 board (128K flash, 20K RAM). */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32.ld + diff --git a/examples/stm32f1/other/i2c_stts75_sensor/stts75.c b/examples/stm32f1/other/i2c_stts75_sensor/stts75.c new file mode 100644 index 0000000..f28019c --- /dev/null +++ b/examples/stm32f1/other/i2c_stts75_sensor/stts75.c @@ -0,0 +1,186 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include "stts75.h" + +void stts75_write_config(u32 i2c, u8 sensor) +{ + u32 reg32; + + /* Send START condition. */ + i2c_send_start(i2c); + + /* Waiting for START is send and switched to master mode. */ + while (!((I2C_SR1(i2c) & I2C_SR1_SB) + & (I2C_SR2(i2c) & (I2C_SR2_MSL | I2C_SR2_BUSY)))); + + /* Send destination address. */ + i2c_send_7bit_address(i2c, sensor, I2C_WRITE); + + /* Waiting for address is transferred. */ + while (!(I2C_SR1(i2c) & I2C_SR1_ADDR)); + + /* Cleaning ADDR condition sequence. */ + reg32 = I2C_SR2(i2c); + + /* Sending the data. */ + i2c_send_data(i2c, 0x1); /* stts75 config register */ + while (!(I2C_SR1(i2c) & I2C_SR1_BTF)); /* Await ByteTransferedFlag. */ + i2c_send_data(i2c, 0x4); /* pol reverse - LED glows if temp is below Tos/Thyst */ + while (!(I2C_SR1(i2c) & (I2C_SR1_BTF | I2C_SR1_TxE))); + + /* Send STOP condition. */ + i2c_send_stop(i2c); +} + +void stts75_write_temp_os(u32 i2c, u8 sensor, u16 temp_os) +{ + u32 reg32; + + /* Send START condition. */ + i2c_send_start(i2c); + + /* Waiting for START is send and switched to master mode. */ + while (!((I2C_SR1(i2c) & I2C_SR1_SB) + & (I2C_SR2(i2c) & (I2C_SR2_MSL | I2C_SR2_BUSY)))); + + /* Send destination address. */ + i2c_send_7bit_address(i2c, sensor, I2C_WRITE); + + /* Waiting for address is transferred. */ + while (!(I2C_SR1(i2c) & I2C_SR1_ADDR)); + + /* Cleaning ADDR condition sequence. */ + reg32 = I2C_SR2(i2c); + + /* Sending the data. */ + i2c_send_data(i2c, 0x3); /* OvertemperatureShutdown register */ + while (!(I2C_SR1(i2c) & I2C_SR1_BTF)); + i2c_send_data(i2c, (u8)(temp_os >> 8)); /* MSB */ + while (!(I2C_SR1(i2c) & I2C_SR1_BTF)); + i2c_send_data(i2c, (u8)(temp_os & 0xff00)); /* LSB */ + while (!(I2C_SR1(i2c) & (I2C_SR1_BTF | I2C_SR1_TxE))); /* After the last byte we have to wait for TxE too. */ + + /* Send STOP condition. */ + i2c_send_stop(i2c); +} + +void stts75_write_temp_hyst(u32 i2c, u8 sensor, u16 temp_hyst) +{ + u32 reg32; + + /* Send START condition. */ + i2c_send_start(i2c); + + /* Waiting for START is send and therefore switched to master mode. */ + while (!((I2C_SR1(i2c) & I2C_SR1_SB) + & (I2C_SR2(i2c) & (I2C_SR2_MSL | I2C_SR2_BUSY)))); + + /* Say to what address we want to talk to. */ + i2c_send_7bit_address(i2c, sensor, I2C_WRITE); + + /* Waiting for address is transferred. */ + while (!(I2C_SR1(i2c) & I2C_SR1_ADDR)); + + /* Cleaning ADDR condition sequence. */ + reg32 = I2C_SR2(i2c); + + /* Sending the data. */ + i2c_send_data(i2c, 0x2); /* TemperatureHysteresis register */ + while (!(I2C_SR1(i2c) & I2C_SR1_BTF)); + i2c_send_data(i2c, (u8)(temp_hyst >> 8)); /* MSB */ + while (!(I2C_SR1(i2c) & I2C_SR1_BTF)); + i2c_send_data(i2c, (u8)(temp_hyst & 0xff00)); /* LSB */ + while (!(I2C_SR1(i2c) & (I2C_SR1_BTF | I2C_SR1_TxE))); /* After the last byte we have to wait for TxE too. */ + + /* Send STOP condition. */ + i2c_send_stop(i2c); +} + +u16 stts75_read_temperature(u32 i2c, u8 sensor) +{ + u32 reg32; + u16 temperature; + + /* Send START condition. */ + i2c_send_start(i2c); + + /* Waiting for START is send and switched to master mode. */ + while (!((I2C_SR1(i2c) & I2C_SR1_SB) + & (I2C_SR2(i2c) & (I2C_SR2_MSL | I2C_SR2_BUSY)))); + + /* Say to what address we want to talk to. */ + /* Yes, WRITE is correct - for selecting register in STTS75. */ + i2c_send_7bit_address(i2c, sensor, I2C_WRITE); + + /* Waiting for address is transferred. */ + while (!(I2C_SR1(i2c) & I2C_SR1_ADDR)); + + /* Cleaning ADDR condition sequence. */ + reg32 = I2C_SR2(i2c); + + i2c_send_data(i2c, 0x0); /* temperature register */ + while (!(I2C_SR1(i2c) & (I2C_SR1_BTF|I2C_SR1_TxE))); + + /* + * Now we transferred that we want to ACCESS the temperature register. + * Now we send another START condition (repeated START) and then + * transfer the destination but with flag READ. + */ + + /* Send START condition. */ + i2c_send_start(i2c); + + /* Waiting for START is send and switched to master mode. */ + while (!((I2C_SR1(i2c) & I2C_SR1_SB) + & (I2C_SR2(i2c) & (I2C_SR2_MSL | I2C_SR2_BUSY)))); + + /* Say to what address we want to talk to. */ + i2c_send_7bit_address(i2c, sensor, I2C_READ); + + /* 2-byte receive is a special case. See datasheet POS bit. */ + I2C_CR1(i2c) |= (I2C_CR1_POS | I2C_CR1_ACK); + + /* Waiting for address is transferred. */ + while (!(I2C_SR1(i2c) & I2C_SR1_ADDR)); + + /* Cleaning ADDR condition sequence. */ + reg32 = I2C_SR2(i2c); + + /* Cleaning I2C_SR1_ACK. */ + I2C_CR1(i2c) &= ~ I2C_CR1_ACK; + + /* Now the slave should begin to send us the first byte. Await BTF. */ + while (!(I2C_SR1(i2c) & I2C_SR1_BTF)); + temperature = (u16)(I2C_DR(i2c) << 8); /* MSB */ + + /* + * Yes they mean it: we have to generate the STOP condition before + * saving the 1st byte. + */ + I2C_CR1(i2c) |= I2C_CR1_STOP; + + temperature |= I2C_DR(i2c); /* LSB */ + + /* Original state. */ + I2C_CR1(i2c) &= ~I2C_CR1_POS; + + return temperature; +} diff --git a/examples/stm32f1/other/i2c_stts75_sensor/stts75.h b/examples/stm32f1/other/i2c_stts75_sensor/stts75.h new file mode 100644 index 0000000..57f6190 --- /dev/null +++ b/examples/stm32f1/other/i2c_stts75_sensor/stts75.h @@ -0,0 +1,39 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef STTS75_H +#define STTS75_H + +#include + +#define STTS75_SENSOR0 0x48 +#define STTS75_SENSOR1 0x49 +#define STTS75_SENSOR2 0x4a +#define STTS75_SENSOR3 0x4b +#define STTS75_SENSOR4 0x4c +#define STTS75_SENSOR5 0x4d +#define STTS75_SENSOR6 0x4e +#define STTS75_SENSOR7 0x4f + +void stts75_write_config(u32 i2c, u8 sensor); +void stts75_write_temp_os(u32 i2c, u8 sensor, u16 temp_os); +void stts75_write_temp_hyst(u32 i2c, u8 sensor, u16 temp_hyst); +u16 stts75_read_temperature(u32 i2c, u8 sensor); + +#endif diff --git a/examples/stm32f1/other/rtc/Makefile b/examples/stm32f1/other/rtc/Makefile new file mode 100644 index 0000000..1efa7ac --- /dev/null +++ b/examples/stm32f1/other/rtc/Makefile @@ -0,0 +1,23 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +## + +BINARY = rtc + +include ../../Makefile.include + diff --git a/examples/stm32f1/other/rtc/README b/examples/stm32f1/other/rtc/README new file mode 100644 index 0000000..f1e3975 --- /dev/null +++ b/examples/stm32f1/other/rtc/README @@ -0,0 +1,6 @@ +------------------------------------------------------------------------------ +README +------------------------------------------------------------------------------ + +This is a small RTC example project. + diff --git a/examples/stm32f1/other/rtc/rtc.c b/examples/stm32f1/other/rtc/rtc.c new file mode 100644 index 0000000..c447534 --- /dev/null +++ b/examples/stm32f1/other/rtc/rtc.c @@ -0,0 +1,116 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Lord James + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include +#include + +void clock_setup(void) +{ + rcc_clock_setup_in_hse_8mhz_out_72mhz(); + + /* Enable GPIOC clock. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); + + /* Enable clocks for GPIO port A (for GPIO_USART1_TX) and USART1. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_USART1EN); +} + +void usart_setup(void) +{ + /* Setup GPIO pin GPIO_USART1_TX/GPIO9 on GPIO port A for transmit. */ + gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_USART1_TX); + + /* Setup UART parameters. */ + usart_set_baudrate(USART1, 38400); + usart_set_databits(USART1, 8); + usart_set_stopbits(USART1, USART_STOPBITS_1); + usart_set_mode(USART1, USART_MODE_TX); + usart_set_parity(USART1, USART_PARITY_NONE); + usart_set_flow_control(USART1, USART_FLOWCONTROL_NONE); + + /* Finally enable the USART. */ + usart_enable(USART1); +} + +void gpio_setup(void) +{ + /* Set GPIO12 (in GPIO port C) to 'output push-pull'. */ + gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_2_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO12); +} + +void nvic_setup(void) +{ + /* Without this the RTC interrupt routine will never be called. */ + nvic_enable_irq(NVIC_RTC_IRQ); + nvic_set_priority(NVIC_RTC_IRQ, 1); +} + +void rtc_isr(void) +{ + volatile u32 j = 0, c = 0; + + /* The interrupt flag isn't cleared by hardware, we have to do it. */ + rtc_clear_flag(RTC_SEC); + + /* Visual output. */ + gpio_toggle(GPIOC, GPIO12); + + c = rtc_get_counter_val(); + + /* Display the current counter value in binary via USART1. */ + for (j = 0; j < 32; j++) { + if ((c & (0x80000000 >> j)) != 0) { + usart_send(USART1, '1'); + } else { + usart_send(USART1, '0'); + } + } + usart_send(USART1, '\n'); +} + +int main(void) +{ + clock_setup(); + gpio_setup(); + usart_setup(); + + /* + * If the RTC is pre-configured just allow access, don't reconfigure. + * Otherwise enable it with the LSE as clock source and 0x7fff as + * prescale value. + */ + rtc_auto_awake(LSE, 0x7fff); + + /* Setup the RTC interrupt. */ + nvic_setup(); + + /* Enable the RTC interrupt to occur off the SEC flag. */ + rtc_interrupt_enable(RTC_SEC); + + while(1); + + return 0; +} diff --git a/examples/stm32f1/other/rtc/rtc.ld b/examples/stm32f1/other/rtc/rtc.ld new file mode 100644 index 0000000..7ea2b92 --- /dev/null +++ b/examples/stm32f1/other/rtc/rtc.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Linker script for Olimex STM32-H103 (STM32F103RBT6, 128K flash, 20K RAM). */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32.ld + diff --git a/examples/stm32f1/other/systick/Makefile b/examples/stm32f1/other/systick/Makefile new file mode 100644 index 0000000..91b5cb5 --- /dev/null +++ b/examples/stm32f1/other/systick/Makefile @@ -0,0 +1,23 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +## + +BINARY = systick + +include ../../Makefile.include + diff --git a/examples/stm32f1/other/systick/README b/examples/stm32f1/other/systick/README new file mode 100644 index 0000000..affb4b8 --- /dev/null +++ b/examples/stm32f1/other/systick/README @@ -0,0 +1,7 @@ +------------------------------------------------------------------------------ +README +------------------------------------------------------------------------------ + +This example program blinks a LED on PortB Pin 6. 1 second on / 1 second off. +Blinking is done via the systick timer interrupt. + diff --git a/examples/stm32f1/other/systick/systick.c b/examples/stm32f1/other/systick/systick.c new file mode 100644 index 0000000..c05aff7 --- /dev/null +++ b/examples/stm32f1/other/systick/systick.c @@ -0,0 +1,75 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include + +u32 temp32; + +void gpio_setup(void) +{ + /* Enable GPIOB clock. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPBEN); + + /* Set GPIO6/7 (in GPIO port B) to 'output push-pull' for the LEDs. */ + gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_2_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO6); + gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_2_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO7); +} + +void sys_tick_handler() +{ + temp32++; + + /* we call this handler every 1ms so 1000ms = 1s on/off */ + if (temp32 == 1000) { + gpio_toggle(GPIOB, GPIO6); /* LED2 on/off */ + temp32 = 0; + } +} + +int main(void) +{ + rcc_clock_setup_in_hse_16mhz_out_72mhz(); + gpio_setup(); + + gpio_clear(GPIOB, GPIO7); /* LED1 on */ + gpio_set(GPIOB, GPIO6); /* LED2 off */ + + temp32 = 0; + + /* 72MHz / 8 => 9000000 counts per second */ + systick_set_clocksource(STK_CTRL_CLKSOURCE_AHB_DIV8); + + /* 9000000/9000 = 1000 overflows per second - every 1ms one interrupt */ + systick_set_reload(9000); + + systick_interrupt_enable(); + + /* start counting */ + systick_counter_enable(); + + while(1); /* Halt. */ + + return 0; +} diff --git a/examples/stm32f1/other/systick/systick.ld b/examples/stm32f1/other/systick/systick.ld new file mode 100644 index 0000000..c076521 --- /dev/null +++ b/examples/stm32f1/other/systick/systick.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Linker script for an STM32F103RBT6 board (128K flash, 20K RAM). */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32.ld + diff --git a/examples/stm32f1/other/timer_interrupt/Makefile b/examples/stm32f1/other/timer_interrupt/Makefile new file mode 100644 index 0000000..86aced4 --- /dev/null +++ b/examples/stm32f1/other/timer_interrupt/Makefile @@ -0,0 +1,23 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +## + +BINARY = timer + +include ../../Makefile.include + diff --git a/examples/stm32f1/other/timer_interrupt/README b/examples/stm32f1/other/timer_interrupt/README new file mode 100644 index 0000000..e6a22c4 --- /dev/null +++ b/examples/stm32f1/other/timer_interrupt/README @@ -0,0 +1,7 @@ +------------------------------------------------------------------------------ +README +------------------------------------------------------------------------------ + +This example program blinks a LED on PortB Pin 6. 1 second on / 1 second off. +Blinking is made only with the timer interrupt of the TIM2 timer. + diff --git a/examples/stm32f1/other/timer_interrupt/timer.c b/examples/stm32f1/other/timer_interrupt/timer.c new file mode 100644 index 0000000..aa2cdb6 --- /dev/null +++ b/examples/stm32f1/other/timer_interrupt/timer.c @@ -0,0 +1,85 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include + +void gpio_setup(void) +{ + /* Enable GPIOB clock. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPBEN); + + /* Set GPIO6/7 (in GPIO port B) to 'output push-pull' for the LEDs. */ + gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_2_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO6); + gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_2_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO7); +} + +void nvic_setup() +{ + /* without this the timer interrupt routine will never be called */ + nvic_enable_irq(NVIC_TIM2_IRQ); + nvic_set_priority(NVIC_TIM2_IRQ, 1); +} + +void tim2_isr() +{ + /* LED2 on/off */ + gpio_toggle(GPIOB, GPIO6); + + /* clear interrrupt flag */ + TIM_SR(TIM2) &= ~TIM_SR_UIF; +} + +int main(void) +{ + rcc_clock_setup_in_hse_16mhz_out_72mhz(); + gpio_setup(); + nvic_setup(); + + gpio_clear(GPIOB, GPIO7); /* LED1 on */ + gpio_set(GPIOB, GPIO6); /* LED2 off */ + + rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_TIM2EN); + + /* the goal is to let the LED2 glow for a second and then be off for a second */ + + /* Set timer start value */ + TIM_CNT(TIM2) = 1; + + /* Set timer prescaler. 72MHz/1440 => 50000 counts per second */ + TIM_PSC(TIM2) = 1440; + + /* End timer value. If this value is reached an interrupt is generated */ + TIM_ARR(TIM2) = 50000; + + /* Update interrupt enable */ + TIM_DIER(TIM2) |= TIM_DIER_UIE; + + /* Start timer */ + TIM_CR1(TIM2) |= TIM_CR1_CEN; + + while(1); /* Halt. */ + + return 0; +} diff --git a/examples/stm32f1/other/timer_interrupt/timer.ld b/examples/stm32f1/other/timer_interrupt/timer.ld new file mode 100644 index 0000000..c076521 --- /dev/null +++ b/examples/stm32f1/other/timer_interrupt/timer.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Linker script for an STM32F103RBT6 board (128K flash, 20K RAM). */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32.ld + diff --git a/examples/stm32f1/other/usb_cdcacm/Makefile b/examples/stm32f1/other/usb_cdcacm/Makefile new file mode 100644 index 0000000..38179e3 --- /dev/null +++ b/examples/stm32f1/other/usb_cdcacm/Makefile @@ -0,0 +1,23 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +## + +BINARY = cdcacm + +include ../../Makefile.include + diff --git a/examples/stm32f1/other/usb_cdcacm/README b/examples/stm32f1/other/usb_cdcacm/README new file mode 100644 index 0000000..2f1ee4b --- /dev/null +++ b/examples/stm32f1/other/usb_cdcacm/README @@ -0,0 +1,7 @@ +------------------------------------------------------------------------------ +README +------------------------------------------------------------------------------ + +This example implements a USB CDC-ACM device (aka Virtual Serial Port) +to demonstrate the use of the USB device stack. + diff --git a/examples/stm32f1/other/usb_cdcacm/cdcacm.c b/examples/stm32f1/other/usb_cdcacm/cdcacm.c new file mode 100644 index 0000000..fdc92e2 --- /dev/null +++ b/examples/stm32f1/other/usb_cdcacm/cdcacm.c @@ -0,0 +1,245 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Gareth McMullin + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include + +static const struct usb_device_descriptor dev = { + .bLength = USB_DT_DEVICE_SIZE, + .bDescriptorType = USB_DT_DEVICE, + .bcdUSB = 0x0200, + .bDeviceClass = USB_CLASS_CDC, + .bDeviceSubClass = 0, + .bDeviceProtocol = 0, + .bMaxPacketSize0 = 64, + .idVendor = 0x0483, + .idProduct = 0x5740, + .bcdDevice = 0x0200, + .iManufacturer = 1, + .iProduct = 2, + .iSerialNumber = 3, + .bNumConfigurations = 1, +}; + +/* This notification endpoint isn't implemented. According to CDC spec its + * optional, but its absence causes a NULL pointer dereference in Linux cdc_acm + * driver. */ +static const struct usb_endpoint_descriptor comm_endp[] = {{ + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = 0x83, + .bmAttributes = USB_ENDPOINT_ATTR_INTERRUPT, + .wMaxPacketSize = 16, + .bInterval = 255, +}}; + +static const struct usb_endpoint_descriptor data_endp[] = {{ + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = 0x01, + .bmAttributes = USB_ENDPOINT_ATTR_BULK, + .wMaxPacketSize = 64, + .bInterval = 1, +}, { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = 0x82, + .bmAttributes = USB_ENDPOINT_ATTR_BULK, + .wMaxPacketSize = 64, + .bInterval = 1, +}}; + +static const struct { + struct usb_cdc_header_descriptor header; + struct usb_cdc_call_management_descriptor call_mgmt; + struct usb_cdc_acm_descriptor acm; + struct usb_cdc_union_descriptor cdc_union; +} __attribute__((packed)) cdcacm_functional_descriptors = { + .header = { + .bFunctionLength = sizeof(struct usb_cdc_header_descriptor), + .bDescriptorType = CS_INTERFACE, + .bDescriptorSubtype = USB_CDC_TYPE_HEADER, + .bcdCDC = 0x0110, + }, + .call_mgmt = { + .bFunctionLength = + sizeof(struct usb_cdc_call_management_descriptor), + .bDescriptorType = CS_INTERFACE, + .bDescriptorSubtype = USB_CDC_TYPE_CALL_MANAGEMENT, + .bmCapabilities = 0, + .bDataInterface = 1, + }, + .acm = { + .bFunctionLength = sizeof(struct usb_cdc_acm_descriptor), + .bDescriptorType = CS_INTERFACE, + .bDescriptorSubtype = USB_CDC_TYPE_ACM, + .bmCapabilities = 0, + }, + .cdc_union = { + .bFunctionLength = sizeof(struct usb_cdc_union_descriptor), + .bDescriptorType = CS_INTERFACE, + .bDescriptorSubtype = USB_CDC_TYPE_UNION, + .bControlInterface = 0, + .bSubordinateInterface0 = 1, + } +}; + +static const struct usb_interface_descriptor comm_iface[] = {{ + .bLength = USB_DT_INTERFACE_SIZE, + .bDescriptorType = USB_DT_INTERFACE, + .bInterfaceNumber = 0, + .bAlternateSetting = 0, + .bNumEndpoints = 1, + .bInterfaceClass = USB_CLASS_CDC, + .bInterfaceSubClass = USB_CDC_SUBCLASS_ACM, + .bInterfaceProtocol = USB_CDC_PROTOCOL_AT, + .iInterface = 0, + + .endpoint = comm_endp, + + .extra = &cdcacm_functional_descriptors, + .extralen = sizeof(cdcacm_functional_descriptors) +}}; + +static const struct usb_interface_descriptor data_iface[] = {{ + .bLength = USB_DT_INTERFACE_SIZE, + .bDescriptorType = USB_DT_INTERFACE, + .bInterfaceNumber = 1, + .bAlternateSetting = 0, + .bNumEndpoints = 2, + .bInterfaceClass = USB_CLASS_DATA, + .bInterfaceSubClass = 0, + .bInterfaceProtocol = 0, + .iInterface = 0, + + .endpoint = data_endp, +}}; + +static const struct usb_interface ifaces[] = {{ + .num_altsetting = 1, + .altsetting = comm_iface, +}, { + .num_altsetting = 1, + .altsetting = data_iface, +}}; + +static const struct usb_config_descriptor config = { + .bLength = USB_DT_CONFIGURATION_SIZE, + .bDescriptorType = USB_DT_CONFIGURATION, + .wTotalLength = 0, + .bNumInterfaces = 2, + .bConfigurationValue = 1, + .iConfiguration = 0, + .bmAttributes = 0x80, + .bMaxPower = 0x32, + + .interface = ifaces, +}; + +static const char *usb_strings[] = { + "x", + "Black Sphere Technologies", + "CDC-ACM Demo", + "DEMO" +}; + +static int cdcacm_control_request(struct usb_setup_data *req, u8 **buf, + u16 *len, void (**complete)(struct usb_setup_data *req)) +{ + (void)complete; + (void)buf; + + switch(req->bRequest) { + case USB_CDC_REQ_SET_CONTROL_LINE_STATE: { + /* This Linux cdc_acm driver requires this to be implemented + * even though it's optional in the CDC spec, and we don't + * advertise it in the ACM functional descriptor. */ + char buf[10]; + struct usb_cdc_notification *notif = (void*)buf; + + /* We echo signals back to host as notification */ + notif->bmRequestType = 0xA1; + notif->bNotification = USB_CDC_NOTIFY_SERIAL_STATE; + notif->wValue = 0; + notif->wIndex = 0; + notif->wLength = 2; + buf[8] = req->wValue & 3; + buf[9] = 0; + //usbd_ep_write_packet(0x83, buf, 10); + return 1; + } + case USB_CDC_REQ_SET_LINE_CODING: + if(*len < sizeof(struct usb_cdc_line_coding)) + return 0; + + return 1; + } + return 0; +} + +static void cdcacm_data_rx_cb(u8 ep) +{ + (void)ep; + + char buf[64]; + int len = usbd_ep_read_packet(0x01, buf, 64); + if(len) { + usbd_ep_write_packet(0x82, buf, len); + buf[len] = 0; + } +} + +static void cdcacm_set_config(u16 wValue) +{ + (void)wValue; + + usbd_ep_setup(0x01, USB_ENDPOINT_ATTR_BULK, 64, cdcacm_data_rx_cb); + usbd_ep_setup(0x82, USB_ENDPOINT_ATTR_BULK, 64, NULL); + usbd_ep_setup(0x83, USB_ENDPOINT_ATTR_INTERRUPT, 16, NULL); + + usbd_register_control_callback( + USB_REQ_TYPE_CLASS | USB_REQ_TYPE_INTERFACE, + USB_REQ_TYPE_TYPE | USB_REQ_TYPE_RECIPIENT, + cdcacm_control_request); +} + +int main(void) +{ + rcc_clock_setup_in_hsi_out_48mhz(); + + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_AFIOEN); + + AFIO_MAPR |= AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_ON; + + gpio_set_mode(GPIOA, GPIO_MODE_INPUT, 0, GPIO15); + + usbd_init(&stm32f103_usb_driver, &dev, &config, usb_strings); + usbd_register_set_config_callback(cdcacm_set_config); + + gpio_set(GPIOA, GPIO15); + gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_2_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO15); + + while (1) + usbd_poll(); +} diff --git a/examples/stm32f1/other/usb_cdcacm/cdcacm.ld b/examples/stm32f1/other/usb_cdcacm/cdcacm.ld new file mode 100644 index 0000000..1c20282 --- /dev/null +++ b/examples/stm32f1/other/usb_cdcacm/cdcacm.ld @@ -0,0 +1,29 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 64K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32.ld + diff --git a/examples/stm32f1/other/usb_dfu/Makefile b/examples/stm32f1/other/usb_dfu/Makefile new file mode 100644 index 0000000..48e2d6b --- /dev/null +++ b/examples/stm32f1/other/usb_dfu/Makefile @@ -0,0 +1,23 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +## + +BINARY = usbdfu + +include ../../Makefile.include + diff --git a/examples/stm32f1/other/usb_dfu/README b/examples/stm32f1/other/usb_dfu/README new file mode 100644 index 0000000..9c0169a --- /dev/null +++ b/examples/stm32f1/other/usb_dfu/README @@ -0,0 +1,7 @@ +------------------------------------------------------------------------------ +README +------------------------------------------------------------------------------ + +This example implements a USB Device Firmware Upgrade (DFU) bootloader +to demonstrate the use of the USB device stack. + diff --git a/examples/stm32f1/other/usb_dfu/usbdfu.c b/examples/stm32f1/other/usb_dfu/usbdfu.c new file mode 100644 index 0000000..7ffbc74 --- /dev/null +++ b/examples/stm32f1/other/usb_dfu/usbdfu.c @@ -0,0 +1,270 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Gareth McMullin + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include +#include +#include + +#define APP_ADDRESS 0x08002000 + +/* Commands sent with wBlockNum == 0 as per ST implementation. */ +#define CMD_SETADDR 0x21 +#define CMD_ERASE 0x41 + +/* We need a special large control buffer for this device: */ +u8 usbd_control_buffer[1024]; + +static enum dfu_state usbdfu_state = STATE_DFU_IDLE; + +static struct { + u8 buf[sizeof(usbd_control_buffer)]; + u16 len; + u32 addr; + u16 blocknum; +} prog; + +const struct usb_device_descriptor dev = { + .bLength = USB_DT_DEVICE_SIZE, + .bDescriptorType = USB_DT_DEVICE, + .bcdUSB = 0x0200, + .bDeviceClass = 0, + .bDeviceSubClass = 0, + .bDeviceProtocol = 0, + .bMaxPacketSize0 = 64, + .idVendor = 0x0483, + .idProduct = 0xDF11, + .bcdDevice = 0x0200, + .iManufacturer = 1, + .iProduct = 2, + .iSerialNumber = 3, + .bNumConfigurations = 1, +}; + +const struct usb_dfu_descriptor dfu_function = { + .bLength = sizeof(struct usb_dfu_descriptor), + .bDescriptorType = DFU_FUNCTIONAL, + .bmAttributes = USB_DFU_CAN_DOWNLOAD | USB_DFU_WILL_DETACH, + .wDetachTimeout = 255, + .wTransferSize = 1024, + .bcdDFUVersion = 0x011A, +}; + +const struct usb_interface_descriptor iface = { + .bLength = USB_DT_INTERFACE_SIZE, + .bDescriptorType = USB_DT_INTERFACE, + .bInterfaceNumber = 0, + .bAlternateSetting = 0, + .bNumEndpoints = 0, + .bInterfaceClass = 0xFE, /* Device Firmware Upgrade */ + .bInterfaceSubClass = 1, + .bInterfaceProtocol = 2, + + /* The ST Microelectronics DfuSe application needs this string. + * The format isn't documented... */ + .iInterface = 4, + + .extra = &dfu_function, + .extralen = sizeof(dfu_function), +}; + +const struct usb_interface ifaces[] = {{ + .num_altsetting = 1, + .altsetting = &iface, +}}; + +const struct usb_config_descriptor config = { + .bLength = USB_DT_CONFIGURATION_SIZE, + .bDescriptorType = USB_DT_CONFIGURATION, + .wTotalLength = 0, + .bNumInterfaces = 1, + .bConfigurationValue = 1, + .iConfiguration = 0, + .bmAttributes = 0xC0, + .bMaxPower = 0x32, + + .interface = ifaces, +}; + +static const char *usb_strings[] = { + "x", + "Black Sphere Technologies", + "DFU Demo", + "DEMO", + /* This string is used by ST Microelectronics' DfuSe utility */ + "@Internal Flash /0x08000000/8*001Ka,56*001Kg" +}; + +static u8 usbdfu_getstatus(u32 *bwPollTimeout) +{ + switch(usbdfu_state) { + case STATE_DFU_DNLOAD_SYNC: + usbdfu_state = STATE_DFU_DNBUSY; + *bwPollTimeout = 100; + return DFU_STATUS_OK; + + case STATE_DFU_MANIFEST_SYNC: + /* Device will reset when read is complete */ + usbdfu_state = STATE_DFU_MANIFEST; + return DFU_STATUS_OK; + + default: + return DFU_STATUS_OK; + } +} + +static void usbdfu_getstatus_complete(struct usb_setup_data *req) +{ + int i; + (void)req; + + switch(usbdfu_state) { + case STATE_DFU_DNBUSY: + + flash_unlock(); + if(prog.blocknum == 0) { + switch(prog.buf[0]) { + case CMD_ERASE: + flash_erase_page(*(u32*)(prog.buf+1)); + case CMD_SETADDR: + prog.addr = *(u32*)(prog.buf+1); + } + } else { + u32 baseaddr = prog.addr + + ((prog.blocknum - 2) * + dfu_function.wTransferSize); + for(i = 0; i < prog.len; i += 2) + flash_program_half_word(baseaddr + i, + *(u16*)(prog.buf+i)); + } + flash_lock(); + + /* We jump straight to dfuDNLOAD-IDLE, + * skipping dfuDNLOAD-SYNC + */ + usbdfu_state = STATE_DFU_DNLOAD_IDLE; + return; + + case STATE_DFU_MANIFEST: + /* USB device must detach, we just reset... */ + scb_reset_system(); + return; /* Will never return */ + default: + return; + } +} + +static int usbdfu_control_request(struct usb_setup_data *req, u8 **buf, + u16 *len, void (**complete)(struct usb_setup_data *req)) +{ + + if((req->bmRequestType & 0x7F) != 0x21) + return 0; /* Only accept class request */ + + switch(req->bRequest) { + case DFU_DNLOAD: + if((len == NULL) || (*len == 0)) { + usbdfu_state = STATE_DFU_MANIFEST_SYNC; + return 1; + } else { + /* Copy download data for use on GET_STATUS */ + prog.blocknum = req->wValue; + prog.len = *len; + memcpy(prog.buf, *buf, *len); + usbdfu_state = STATE_DFU_DNLOAD_SYNC; + return 1; + } + case DFU_CLRSTATUS: + /* Clear error and return to dfuIDLE */ + if(usbdfu_state == STATE_DFU_ERROR) + usbdfu_state = STATE_DFU_IDLE; + return 1; + case DFU_ABORT: + /* Abort returns to dfuIDLE state */ + usbdfu_state = STATE_DFU_IDLE; + return 1; + case DFU_UPLOAD: + /* Upload not supported for now */ + return 0; + case DFU_GETSTATUS: { + u32 bwPollTimeout = 0; /* 24-bit integer in DFU class spec */ + + (*buf)[0] = usbdfu_getstatus(&bwPollTimeout); + (*buf)[1] = bwPollTimeout & 0xFF; + (*buf)[2] = (bwPollTimeout >> 8) & 0xFF; + (*buf)[3] = (bwPollTimeout >> 16) & 0xFF; + (*buf)[4] = usbdfu_state; + (*buf)[5] = 0; /* iString not used here */ + *len = 6; + + *complete = usbdfu_getstatus_complete; + + return 1; + } + case DFU_GETSTATE: + /* Return state with no state transision */ + *buf[0] = usbdfu_state; + *len = 1; + return 1; + } + + return 0; +} + +int main(void) +{ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); + if(!gpio_get(GPIOA, GPIO10)) { + /* Boot the application if it's valid */ + if((*(volatile u32*)APP_ADDRESS & 0x2FFE0000) == 0x20000000) { + /* Set vector table base address */ + SCB_VTOR = APP_ADDRESS & 0xFFFF; + /* Initialise master stack pointer */ + asm volatile ("msr msp, %0"::"g" + (*(volatile u32*)APP_ADDRESS)); + /* Jump to application */ + (*(void(**)())(APP_ADDRESS + 4))(); + } + } + + rcc_clock_setup_in_hsi_out_48mhz(); + + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_AFIOEN); + + AFIO_MAPR |= AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_ON; + gpio_set_mode(GPIOA, GPIO_MODE_INPUT, 0, GPIO15); + + usbd_init(&stm32f103_usb_driver, &dev, &config, usb_strings); + usbd_set_control_buffer_size(sizeof(usbd_control_buffer)); + usbd_register_control_callback( + USB_REQ_TYPE_CLASS | USB_REQ_TYPE_INTERFACE, + USB_REQ_TYPE_TYPE | USB_REQ_TYPE_RECIPIENT, + usbdfu_control_request); + + gpio_set(GPIOA, GPIO15); + gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_2_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO15); + + while (1) + usbd_poll(); +} diff --git a/examples/stm32f1/other/usb_dfu/usbdfu.ld b/examples/stm32f1/other/usb_dfu/usbdfu.ld new file mode 100644 index 0000000..54e5dac --- /dev/null +++ b/examples/stm32f1/other/usb_dfu/usbdfu.ld @@ -0,0 +1,29 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 8K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 4K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32.ld + diff --git a/examples/stm32f1/other/usb_hid/Makefile b/examples/stm32f1/other/usb_hid/Makefile new file mode 100644 index 0000000..d831e9e --- /dev/null +++ b/examples/stm32f1/other/usb_hid/Makefile @@ -0,0 +1,23 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +## + +BINARY = usbhid + +include ../../Makefile.include + diff --git a/examples/stm32f1/other/usb_hid/README b/examples/stm32f1/other/usb_hid/README new file mode 100644 index 0000000..92645c9 --- /dev/null +++ b/examples/stm32f1/other/usb_hid/README @@ -0,0 +1,7 @@ +------------------------------------------------------------------------------ +README +------------------------------------------------------------------------------ + +This example implements a USB Human Interface Device (HID) +to demonstrate the use of the USB device stack. + diff --git a/examples/stm32f1/other/usb_hid/usbhid.c b/examples/stm32f1/other/usb_hid/usbhid.c new file mode 100644 index 0000000..8f08aac --- /dev/null +++ b/examples/stm32f1/other/usb_hid/usbhid.c @@ -0,0 +1,272 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Gareth McMullin + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include +#include + +/* Define this to include the DFU APP interface. */ +#define INCLUDE_DFU_INTERFACE + +#ifdef INCLUDE_DFU_INTERFACE +#include +#include +#endif + +const struct usb_device_descriptor dev = { + .bLength = USB_DT_DEVICE_SIZE, + .bDescriptorType = USB_DT_DEVICE, + .bcdUSB = 0x0200, + .bDeviceClass = 0, + .bDeviceSubClass = 0, + .bDeviceProtocol = 0, + .bMaxPacketSize0 = 64, + .idVendor = 0x0483, + .idProduct = 0x5710, + .bcdDevice = 0x0200, + .iManufacturer = 1, + .iProduct = 2, + .iSerialNumber = 3, + .bNumConfigurations = 1, +}; + +/* I have no idea what this means. I haven't read the HID spec. */ +static const u8 hid_report_descriptor[] = { + 0x05, 0x01, 0x09, 0x02, 0xA1, 0x01, 0x09, 0x01, + 0xA1, 0x00, 0x05, 0x09, 0x19, 0x01, 0x29, 0x03, + 0x15, 0x00, 0x25, 0x01, 0x95, 0x03, 0x75, 0x01, + 0x81, 0x02, 0x95, 0x01, 0x75, 0x05, 0x81, 0x01, + 0x05, 0x01, 0x09, 0x30, 0x09, 0x31, 0x09, 0x38, + 0x15, 0x81, 0x25, 0x7F, 0x75, 0x08, 0x95, 0x03, + 0x81, 0x06, 0xC0, 0x09, 0x3c, 0x05, 0xff, 0x09, + 0x01, 0x15, 0x00, 0x25, 0x01, 0x75, 0x01, 0x95, + 0x02, 0xb1, 0x22, 0x75, 0x06, 0x95, 0x01, 0xb1, + 0x01, 0xc0 +}; + +static const struct { + struct usb_hid_descriptor hid_descriptor; + struct { + u8 bReportDescriptorType; + u16 wDescriptorLength; + } __attribute__((packed)) hid_report; +} __attribute__((packed)) hid_function = { + .hid_descriptor = { + .bLength = sizeof(hid_function), + .bDescriptorType = USB_DT_HID, + .bcdHID = 0x0100, + .bCountryCode = 0, + .bNumDescriptors = 1, + }, + .hid_report = { + .bReportDescriptorType = USB_DT_REPORT, + .wDescriptorLength = sizeof(hid_report_descriptor), + } +}; + +const struct usb_endpoint_descriptor hid_endpoint = { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = 0x81, + .bmAttributes = USB_ENDPOINT_ATTR_INTERRUPT, + .wMaxPacketSize = 4, + .bInterval = 0x20, +}; + +const struct usb_interface_descriptor hid_iface = { + .bLength = USB_DT_INTERFACE_SIZE, + .bDescriptorType = USB_DT_INTERFACE, + .bInterfaceNumber = 0, + .bAlternateSetting = 0, + .bNumEndpoints = 1, + .bInterfaceClass = USB_CLASS_HID, + .bInterfaceSubClass = 1, /* boot */ + .bInterfaceProtocol = 2, /* mouse */ + .iInterface = 0, + + .endpoint = &hid_endpoint, + + .extra = &hid_function, + .extralen = sizeof(hid_function), +}; + +#ifdef INCLUDE_DFU_INTERFACE +const struct usb_dfu_descriptor dfu_function = { + .bLength = sizeof(struct usb_dfu_descriptor), + .bDescriptorType = DFU_FUNCTIONAL, + .bmAttributes = USB_DFU_CAN_DOWNLOAD | USB_DFU_WILL_DETACH, + .wDetachTimeout = 255, + .wTransferSize = 1024, + .bcdDFUVersion = 0x011A, +}; + +const struct usb_interface_descriptor dfu_iface = { + .bLength = USB_DT_INTERFACE_SIZE, + .bDescriptorType = USB_DT_INTERFACE, + .bInterfaceNumber = 1, + .bAlternateSetting = 0, + .bNumEndpoints = 0, + .bInterfaceClass = 0xFE, + .bInterfaceSubClass = 1, + .bInterfaceProtocol = 1, + .iInterface = 0, + + .extra = &dfu_function, + .extralen = sizeof(dfu_function), +}; +#endif + +const struct usb_interface ifaces[] = {{ + .num_altsetting = 1, + .altsetting = &hid_iface, +#ifdef INCLUDE_DFU_INTERFACE +}, { + .num_altsetting = 1, + .altsetting = &dfu_iface, +#endif +}}; + +const struct usb_config_descriptor config = { + .bLength = USB_DT_CONFIGURATION_SIZE, + .bDescriptorType = USB_DT_CONFIGURATION, + .wTotalLength = 0, +#ifdef INCLUDE_DFU_INTERFACE + .bNumInterfaces = 2, +#else + .bNumInterfaces = 1, +#endif + .bConfigurationValue = 1, + .iConfiguration = 0, + .bmAttributes = 0xC0, + .bMaxPower = 0x32, + + .interface = ifaces, +}; + +static const char *usb_strings[] = { + "x", + "Black Sphere Technologies", + "HID Demo", + "DEMO", +}; + +static int hid_control_request(struct usb_setup_data *req, u8 **buf, u16 *len, + void (**complete)(struct usb_setup_data *req)) +{ + (void)complete; + + if((req->bmRequestType != 0x81) || + (req->bRequest != USB_REQ_GET_DESCRIPTOR) || + (req->wValue != 0x2200)) + return 0; + + /* Handle the HID report descriptor */ + *buf = (u8*)hid_report_descriptor; + *len = sizeof(hid_report_descriptor); + + return 1; +} + +#ifdef INCLUDE_DFU_INTERFACE +static void dfu_detach_complete(struct usb_setup_data *req) +{ + (void)req; + + gpio_set_mode(GPIOA, GPIO_MODE_INPUT, 0, GPIO15); + gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_2_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO10); + gpio_set(GPIOA, GPIO10); + scb_reset_core(); +} + +static int dfu_control_request(struct usb_setup_data *req, u8 **buf, u16 *len, + void (**complete)(struct usb_setup_data *req)) +{ + (void)buf; + (void)len; + + if((req->bmRequestType != 0x21) || (req->bRequest != DFU_DETACH)) + return 0; /* Only accept class request */ + + *complete = dfu_detach_complete; + + return 1; +} +#endif + +static void hid_set_config(u16 wValue) +{ + (void)wValue; + + usbd_ep_setup(0x81, USB_ENDPOINT_ATTR_INTERRUPT, 4, NULL); + + usbd_register_control_callback( + USB_REQ_TYPE_STANDARD | USB_REQ_TYPE_INTERFACE, + USB_REQ_TYPE_TYPE | USB_REQ_TYPE_RECIPIENT, + hid_control_request); +#ifdef INCLUDE_DFU_INTERFACE + usbd_register_control_callback( + USB_REQ_TYPE_CLASS | USB_REQ_TYPE_INTERFACE, + USB_REQ_TYPE_TYPE | USB_REQ_TYPE_RECIPIENT, + dfu_control_request); +#endif + + systick_set_clocksource(STK_CTRL_CLKSOURCE_AHB_DIV8); + systick_set_reload(100000); + systick_interrupt_enable(); + systick_counter_enable(); +} + +int main(void) +{ + rcc_clock_setup_in_hsi_out_48mhz(); + + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_AFIOEN); + + AFIO_MAPR |= AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_ON; + gpio_set_mode(GPIOA, GPIO_MODE_INPUT, 0, GPIO15); + + usbd_init(&stm32f103_usb_driver, &dev, &config, usb_strings); + usbd_register_set_config_callback(hid_set_config); + + gpio_set(GPIOA, GPIO15); + gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_2_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO15); + + while (1) + usbd_poll(); +} + +void sys_tick_handler(void) +{ + static int x = 0; + static int dir = 1; + u8 buf[4] = {0, 0, 0, 0}; + + buf[1] = dir; + x += dir; + if(x > 30) dir = -dir; + if(x < -30) dir = -dir; + + usbd_ep_write_packet(0x81, buf, 4); +} diff --git a/examples/stm32f1/other/usb_hid/usbhid.ld b/examples/stm32f1/other/usb_hid/usbhid.ld new file mode 100644 index 0000000..1c20282 --- /dev/null +++ b/examples/stm32f1/other/usb_hid/usbhid.ld @@ -0,0 +1,29 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 64K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32.ld + diff --git a/examples/stm32f1/stm32-discovery/button/Makefile b/examples/stm32f1/stm32-discovery/button/Makefile new file mode 100644 index 0000000..96731c2 --- /dev/null +++ b/examples/stm32f1/stm32-discovery/button/Makefile @@ -0,0 +1,23 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +## + +BINARY = button + +include ../../Makefile.include + diff --git a/examples/stm32f1/stm32-discovery/button/README b/examples/stm32f1/stm32-discovery/button/README new file mode 100644 index 0000000..38bc1ea --- /dev/null +++ b/examples/stm32f1/stm32-discovery/button/README @@ -0,0 +1,8 @@ +------------------------------------------------------------------------------ +README +------------------------------------------------------------------------------ + +This example blinks the green LED on the ST STM32VLDISCOVERY eval board. + +When you press the 'USER' button, the blinking is slower. + diff --git a/examples/stm32f1/stm32-discovery/button/button.c b/examples/stm32f1/stm32-discovery/button/button.c new file mode 100644 index 0000000..b84f074 --- /dev/null +++ b/examples/stm32f1/stm32-discovery/button/button.c @@ -0,0 +1,76 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann , + * Copyright (C) 2010 Piotr Esden-Tempski + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include + +u16 exti_line_state; + +/* Set STM32 to 24 MHz. */ +void clock_setup(void) +{ + rcc_clock_setup_in_hse_8mhz_out_24mhz(); +} + +void gpio_setup(void) +{ + /* Enable GPIOC clock. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); + + /* Set GPIO9 (in GPIO port C) to 'output push-pull'. */ + gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO9); +} + +void button_setup(void) +{ + /* Enable GPIOA clock. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); + + /* Set GPIO0 (in GPIO port A) to 'input open-drain'. */ + gpio_set_mode(GPIOA, GPIO_MODE_INPUT, + GPIO_CNF_INPUT_FLOAT, GPIO0); +} + +int main(void) +{ + int i; + + clock_setup(); + gpio_setup(); + button_setup(); + + /* Blink the LED (PC9) on the board. */ + while (1) { + gpio_toggle(GPIOC, GPIO9); + + /* Upon button press, blink more slowly. */ + exti_line_state = GPIOA_IDR; + if ((exti_line_state & (1 << 0)) != 0) { + for (i = 0; i < 800000; i++) /* Wait a bit. */ + __asm__("nop"); + } + + for (i = 0; i < 800000; i++) /* Wait a bit. */ + __asm__("nop"); + } + + return 0; +} diff --git a/examples/stm32f1/stm32-discovery/button/button.ld b/examples/stm32f1/stm32-discovery/button/button.ld new file mode 100644 index 0000000..b03f90f --- /dev/null +++ b/examples/stm32f1/stm32-discovery/button/button.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Linker script for ST STM32VLDISCOVERY (STM32F100RB, 128K flash, 8K RAM). */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 8K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32.ld + diff --git a/examples/stm32f1/stm32-discovery/fancyblink/Makefile b/examples/stm32f1/stm32-discovery/fancyblink/Makefile new file mode 100644 index 0000000..1baec4d --- /dev/null +++ b/examples/stm32f1/stm32-discovery/fancyblink/Makefile @@ -0,0 +1,23 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +## + +BINARY = fancyblink + +include ../../Makefile.include + diff --git a/examples/stm32f1/stm32-discovery/fancyblink/README b/examples/stm32f1/stm32-discovery/fancyblink/README new file mode 100644 index 0000000..b5d794c --- /dev/null +++ b/examples/stm32f1/stm32-discovery/fancyblink/README @@ -0,0 +1,9 @@ +------------------------------------------------------------------------------ +README +------------------------------------------------------------------------------ + +This is the smallest-possible example program using libopencm3. + +It's intended for the ST STM32VLDISCOVERY eval board. It should blink +the LEDs on the board. + diff --git a/examples/stm32f1/stm32-discovery/fancyblink/fancyblink.c b/examples/stm32f1/stm32-discovery/fancyblink/fancyblink.c new file mode 100644 index 0000000..d40fb7b --- /dev/null +++ b/examples/stm32f1/stm32-discovery/fancyblink/fancyblink.c @@ -0,0 +1,61 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * Copyright (C) 2011 Damjan Marion + * Copyright (C) 2011 Mark Panajotovic + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include + +/* Set STM32 to 24 MHz. */ +void clock_setup(void) +{ + rcc_clock_setup_in_hse_8mhz_out_24mhz(); + + /* Enable GPIOC clock. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); +} + +void gpio_setup(void) +{ + /* Set GPIO8/9 (in GPIO port C) to 'output push-pull'. */ + gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO8); + gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO9); +} + +int main(void) +{ + int i; + + clock_setup(); + gpio_setup(); + + /* Set one LED for wigwag effect when toggling. */ + gpio_set(GPIOC, GPIO8); + + /* Blink the LEDs (PC8 and PC9) on the board. */ + while (1) { + gpio_toggle(GPIOC, GPIO8 | GPIO9); /* Toggle LEDs. */ + for (i = 0; i < 2000000; i++) /* Wait a bit. */ + __asm__("nop"); + } + + return 0; +} diff --git a/examples/stm32f1/stm32-discovery/fancyblink/fancyblink.ld b/examples/stm32f1/stm32-discovery/fancyblink/fancyblink.ld new file mode 100644 index 0000000..b03f90f --- /dev/null +++ b/examples/stm32f1/stm32-discovery/fancyblink/fancyblink.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Linker script for ST STM32VLDISCOVERY (STM32F100RB, 128K flash, 8K RAM). */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 8K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32.ld + diff --git a/examples/stm32f1/stm32-discovery/miniblink/Makefile b/examples/stm32f1/stm32-discovery/miniblink/Makefile new file mode 100644 index 0000000..24a478b --- /dev/null +++ b/examples/stm32f1/stm32-discovery/miniblink/Makefile @@ -0,0 +1,23 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +## + +BINARY = miniblink + +include ../../Makefile.include + diff --git a/examples/stm32f1/stm32-discovery/miniblink/README b/examples/stm32f1/stm32-discovery/miniblink/README new file mode 100644 index 0000000..cffce60 --- /dev/null +++ b/examples/stm32f1/stm32-discovery/miniblink/README @@ -0,0 +1,9 @@ +------------------------------------------------------------------------------ +README +------------------------------------------------------------------------------ + +This is the smallest-possible example program using libopencm3. + +It's intended for the ST STM32VLDISCOVERY eval board. It should blink +the blue LED on the board. + diff --git a/examples/stm32f1/stm32-discovery/miniblink/miniblink.c b/examples/stm32f1/stm32-discovery/miniblink/miniblink.c new file mode 100644 index 0000000..a05f957 --- /dev/null +++ b/examples/stm32f1/stm32-discovery/miniblink/miniblink.c @@ -0,0 +1,71 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include + +void gpio_setup(void) +{ + /* Enable GPIOC clock. */ + /* Manually: */ + // RCC_APB2ENR |= RCC_APB2ENR_IOPCEN; + /* Using API functions: */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); + + /* Set GPIO8 (in GPIO port C) to 'output push-pull'. */ + /* Manually: */ + // GPIOC_CRH = (GPIO_CNF_OUTPUT_PUSHPULL << (((8 - 8) * 4) + 2)); + // GPIOC_CRH |= (GPIO_MODE_OUTPUT_2_MHZ << ((8 - 8) * 4)); + /* Using API functions: */ + gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_2_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO8); +} + +int main(void) +{ + int i; + + gpio_setup(); + + /* Blink the LED (PC8) on the board. */ + while (1) { + /* Manually: */ + // GPIOC_BSRR = GPIO8; /* LED off */ + // for (i = 0; i < 800000; i++) /* Wait a bit. */ + // __asm__("nop"); + // GPIOC_BRR = GPIO8; /* LED on */ + // for (i = 0; i < 800000; i++) /* Wait a bit. */ + // __asm__("nop"); + + /* Using API functions gpio_set()/gpio_clear(): */ + // gpio_set(GPIOC, GPIO8); /* LED off */ + // for (i = 0; i < 800000; i++) /* Wait a bit. */ + // __asm__("nop"); + // gpio_clear(GPIOC, GPIO8); /* LED on */ + // for (i = 0; i < 800000; i++) /* Wait a bit. */ + // __asm__("nop"); + + /* Using API function gpio_toggle(): */ + gpio_toggle(GPIOC, GPIO8); /* LED on/off */ + for (i = 0; i < 800000; i++) /* Wait a bit. */ + __asm__("nop"); + } + + return 0; +} diff --git a/examples/stm32f1/stm32-discovery/miniblink/miniblink.ld b/examples/stm32f1/stm32-discovery/miniblink/miniblink.ld new file mode 100644 index 0000000..b03f90f --- /dev/null +++ b/examples/stm32f1/stm32-discovery/miniblink/miniblink.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Linker script for ST STM32VLDISCOVERY (STM32F100RB, 128K flash, 8K RAM). */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 8K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32.ld + diff --git a/examples/stm32f1/stm32-discovery/rtc/Makefile b/examples/stm32f1/stm32-discovery/rtc/Makefile new file mode 100644 index 0000000..1efa7ac --- /dev/null +++ b/examples/stm32f1/stm32-discovery/rtc/Makefile @@ -0,0 +1,23 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +## + +BINARY = rtc + +include ../../Makefile.include + diff --git a/examples/stm32f1/stm32-discovery/rtc/README b/examples/stm32f1/stm32-discovery/rtc/README new file mode 100644 index 0000000..d4509e4 --- /dev/null +++ b/examples/stm32f1/stm32-discovery/rtc/README @@ -0,0 +1,9 @@ +------------------------------------------------------------------------------ +README +------------------------------------------------------------------------------ + +This is a small RTC example project. + +It blinks the ST STM32VLDISCOVERY's blue LED at 1Hz, and sends the value of +the RTC counter register down the serial line (PA9) at 38400,8N1. + diff --git a/examples/stm32f1/stm32-discovery/rtc/rtc.c b/examples/stm32f1/stm32-discovery/rtc/rtc.c new file mode 100644 index 0000000..c99920f --- /dev/null +++ b/examples/stm32f1/stm32-discovery/rtc/rtc.c @@ -0,0 +1,129 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Lord James + * Copyright (C) 2011 Mark Panajotovic + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include +#include + +void clock_setup(void) +{ + rcc_clock_setup_in_hse_8mhz_out_24mhz(); + + /* Enable GPIOC clock. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); + + /* Enable clocks for GPIO port A (for GPIO_USART1_TX) and USART1. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_USART1EN); +} + +void usart_setup(void) +{ + /* Setup GPIO pin GPIO_USART1_TX/GPIO9 on GPIO port A for transmit. */ + gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_USART1_TX); + + /* Setup UART parameters. */ + // usart_set_baudrate(USART1, 38400); + /* TODO usart_set_baudrate() doesn't support 24MHz clock (yet). */ + /* This is the equivalent: */ + USART_BRR(USART1) = (u16)((24000000 << 4) / (38400 * 16)); + + usart_set_databits(USART1, 8); + usart_set_stopbits(USART1, USART_STOPBITS_1); + usart_set_mode(USART1, USART_MODE_TX); + usart_set_parity(USART1, USART_PARITY_NONE); + usart_set_flow_control(USART1, USART_FLOWCONTROL_NONE); + + /* Finally enable the USART. */ + usart_enable(USART1); +} + +void gpio_setup(void) +{ + /* Set GPIO8 (in GPIO port C) to 'output push-pull'. */ + /* This drives the blue LED on the STM32VLDISCOVERY. */ + gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_2_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO8); +} + +void nvic_setup(void) +{ + /* Without this the RTC interrupt routine will never be called. */ + nvic_enable_irq(NVIC_RTC_IRQ); + nvic_set_priority(NVIC_RTC_IRQ, 1); +} + +void rtc_isr(void) +{ + volatile u32 j = 0, c = 0; + + /* The interrupt flag isn't cleared by hardware, we have to do it. */ + rtc_clear_flag(RTC_SEC); + + /* Visual output. */ + gpio_toggle(GPIOC, GPIO8); + + c = rtc_get_counter_val(); + + /* Display the current counter value in binary via USART1. */ + for (j = 0; j < 32; j++) { + if ((c & (0x80000000 >> j)) != 0) + usart_send_blocking(USART1, '1'); + else + usart_send_blocking(USART1, '0'); + } + usart_send_blocking(USART1, '\n'); + usart_send_blocking(USART1, '\r'); +} + +int main(void) +{ + clock_setup(); + gpio_setup(); + usart_setup(); + + /* + * If the RTC is pre-configured just allow access, don't reconfigure. + * Otherwise enable it with the LSE as clock source and 0x7fff as + * prescale value. + */ + rtc_auto_awake(LSE, 0x7fff); + + /* The above mode will not reset the RTC when you press the RST button. + * It will also continue to count while the MCU is held in reset. If + * you want it to reset, comment out the above and use the following: + */ + // rtc_awake_from_off(LSE); + // rtc_set_prescale_val(0x7fff); + + /* Setup the RTC interrupt. */ + nvic_setup(); + + /* Enable the RTC interrupt to occur off the SEC flag. */ + rtc_interrupt_enable(RTC_SEC); + + while(1); + + return 0; +} diff --git a/examples/stm32f1/stm32-discovery/rtc/rtc.ld b/examples/stm32f1/stm32-discovery/rtc/rtc.ld new file mode 100644 index 0000000..b03f90f --- /dev/null +++ b/examples/stm32f1/stm32-discovery/rtc/rtc.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Linker script for ST STM32VLDISCOVERY (STM32F100RB, 128K flash, 8K RAM). */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 8K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32.ld + diff --git a/examples/stm32f1/stm32-discovery/usart/Makefile b/examples/stm32f1/stm32-discovery/usart/Makefile new file mode 100644 index 0000000..2c1e1b1 --- /dev/null +++ b/examples/stm32f1/stm32-discovery/usart/Makefile @@ -0,0 +1,23 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +## + +BINARY = usart + +include ../../Makefile.include + diff --git a/examples/stm32f1/stm32-discovery/usart/README b/examples/stm32f1/stm32-discovery/usart/README new file mode 100644 index 0000000..6d09139 --- /dev/null +++ b/examples/stm32f1/stm32-discovery/usart/README @@ -0,0 +1,12 @@ +------------------------------------------------------------------------------ +README +------------------------------------------------------------------------------ + +This example program sends some characters on USART1 on the +ST STM32VLDISCOVERY eval board. + +The terminal settings for the receiving device/PC are 38400 8n1. + +The sending is done in a blocking way in the code, see the usart_irq example +for a more elaborate USART example. + diff --git a/examples/stm32f1/stm32-discovery/usart/usart.c b/examples/stm32f1/stm32-discovery/usart/usart.c new file mode 100644 index 0000000..05d0312 --- /dev/null +++ b/examples/stm32f1/stm32-discovery/usart/usart.c @@ -0,0 +1,87 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include + +void clock_setup(void) +{ + rcc_clock_setup_in_hse_8mhz_out_24mhz(); + + /* Enable GPIOC clock. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); + + /* Enable clocks for GPIO port A (for GPIO_USART1_TX) and USART1. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_USART1EN); +} + +void usart_setup(void) +{ + /* Setup GPIO pin GPIO_USART1_TX/GPIO9 on GPIO port A for transmit. */ + gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_USART1_TX); + + /* Setup UART parameters. */ + // usart_set_baudrate(USART1, 38400); + /* TODO usart_set_baudrate() doesn't support 24MHz clock (yet). */ + /* This is the equivalent: */ + USART_BRR(USART1) = (u16)((24000000 << 4) / (38400 * 16)); + + usart_set_databits(USART1, 8); + usart_set_stopbits(USART1, USART_STOPBITS_1); + usart_set_mode(USART1, USART_MODE_TX); + usart_set_parity(USART1, USART_PARITY_NONE); + usart_set_flow_control(USART1, USART_FLOWCONTROL_NONE); + + /* Finally enable the USART. */ + usart_enable(USART1); +} + +void gpio_setup(void) +{ + /* Set GPIO9 (in GPIO port C) to 'output push-pull'. [LED] */ + gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_2_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO9); +} + +int main(void) +{ + int i, j = 0, c = 0; + + clock_setup(); + gpio_setup(); + usart_setup(); + + /* Blink the LED (PC9) on the board with every transmitted byte. */ + while (1) { + gpio_toggle(GPIOC, GPIO9); /* LED on/off */ + usart_send_blocking(USART1, c + '0'); /* USART1: Send byte. */ + c = (c == 9) ? 0 : c + 1; /* Increment c. */ + if ((j++ % 80) == 0) { /* Newline after line full. */ + usart_send_blocking(USART1, '\r'); + usart_send_blocking(USART1, '\n'); + } + for (i = 0; i < 800000; i++) /* Wait a bit. */ + __asm__("NOP"); + } + + return 0; +} diff --git a/examples/stm32f1/stm32-discovery/usart/usart.ld b/examples/stm32f1/stm32-discovery/usart/usart.ld new file mode 100644 index 0000000..b03f90f --- /dev/null +++ b/examples/stm32f1/stm32-discovery/usart/usart.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Linker script for ST STM32VLDISCOVERY (STM32F100RB, 128K flash, 8K RAM). */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 8K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32.ld + diff --git a/examples/stm32f1/stm32-h103/button/Makefile b/examples/stm32f1/stm32-h103/button/Makefile new file mode 100644 index 0000000..96731c2 --- /dev/null +++ b/examples/stm32f1/stm32-h103/button/Makefile @@ -0,0 +1,23 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +## + +BINARY = button + +include ../../Makefile.include + diff --git a/examples/stm32f1/stm32-h103/button/button.c b/examples/stm32f1/stm32-h103/button/button.c new file mode 100644 index 0000000..63f3274 --- /dev/null +++ b/examples/stm32f1/stm32-h103/button/button.c @@ -0,0 +1,79 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann , + * 2010 Piotr Esden-Tempski + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include + +u16 exti_line_state; + +/* Set STM32 to 72 MHz. */ +void clock_setup(void) +{ + rcc_clock_setup_in_hse_8mhz_out_72mhz(); + +} + +void gpio_setup(void) +{ + /* Enable GPIOC clock. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); + + /* Set GPIO12 (in GPIO port C) to 'output push-pull'. */ + gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO12); +} + +void button_setup(void) +{ + /* Enable GPIOA clock. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); + + /* Set GPIO0 (in GPIO port A) to 'input open-drain'. */ + gpio_set_mode(GPIOA, GPIO_MODE_INPUT, + GPIO_CNF_INPUT_FLOAT, GPIO0); + +} + +int main(void) +{ + int i; + + clock_setup(); + gpio_setup(); + button_setup(); + + /* Blink the LED (PC12) on the board. */ + while (1) { + gpio_toggle(GPIOC, GPIO12); + + exti_line_state = GPIOA_IDR; + if ((exti_line_state & (1 << 0)) != 0) { + for (i = 0; i < 800000; i++) /* Wait a bit. */ + __asm__("nop"); + } + + for (i = 0; i < 800000; i++) /* Wait a bit. */ + __asm__("nop"); + } + + return 0; +} diff --git a/examples/stm32f1/stm32-h103/button/button.ld b/examples/stm32f1/stm32-h103/button/button.ld new file mode 100644 index 0000000..7ea2b92 --- /dev/null +++ b/examples/stm32f1/stm32-h103/button/button.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Linker script for Olimex STM32-H103 (STM32F103RBT6, 128K flash, 20K RAM). */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32.ld + diff --git a/examples/stm32f1/stm32-h103/exti_both/Makefile b/examples/stm32f1/stm32-h103/exti_both/Makefile new file mode 100644 index 0000000..39e305b --- /dev/null +++ b/examples/stm32f1/stm32-h103/exti_both/Makefile @@ -0,0 +1,23 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +## + +BINARY = exti_both + +include ../../Makefile.include + diff --git a/examples/stm32f1/stm32-h103/exti_both/exti_both.c b/examples/stm32f1/stm32-h103/exti_both/exti_both.c new file mode 100644 index 0000000..edfc676 --- /dev/null +++ b/examples/stm32f1/stm32-h103/exti_both/exti_both.c @@ -0,0 +1,92 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann , + * 2010 Piotr Esden-Tempski + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include + +u16 exti_line_state; + +/* Set STM32 to 72 MHz. */ +void clock_setup(void) +{ + rcc_clock_setup_in_hse_8mhz_out_72mhz(); + +} + +void gpio_setup(void) +{ + /* Enable GPIOC clock. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); + + /* Set GPIO12 (in GPIO port C) to 'output push-pull'. */ + gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO12); +} + +void exti_setup(void) +{ + /* Enable GPIOA clock. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); + + /* Enable AFIO clock. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_AFIOEN); + + /* Enable EXTI0 interrupt */ + nvic_enable_irq(NVIC_EXTI0_IRQ); + + /* Set GPIO0 (in GPIO port A) to 'input float'. */ + gpio_set_mode(GPIOA, GPIO_MODE_INPUT, + GPIO_CNF_INPUT_FLOAT, GPIO0); + + /* configure EXTI subsystem */ + exti_select_source(EXTI0, GPIOA); + exti_set_trigger(EXTI0, EXTI_TRIGGER_BOTH); + exti_enable_request(EXTI0); +} + +void exti0_isr() +{ + exti_line_state = GPIOA_IDR; + + if ((exti_line_state & (1 << 0)) != 0) { + gpio_clear(GPIOC, GPIO12); + } else { + gpio_set(GPIOC, GPIO12); + } + + exti_reset_request(EXTI0); +} + +int main(void) +{ + + clock_setup(); + gpio_setup(); + exti_setup(); + + /* Blink the LED (PC12) on the board. */ + while (1) { + __asm("nop"); + } + + return 0; +} diff --git a/examples/stm32f1/stm32-h103/exti_both/exti_both.ld b/examples/stm32f1/stm32-h103/exti_both/exti_both.ld new file mode 100644 index 0000000..7ea2b92 --- /dev/null +++ b/examples/stm32f1/stm32-h103/exti_both/exti_both.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Linker script for Olimex STM32-H103 (STM32F103RBT6, 128K flash, 20K RAM). */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32.ld + diff --git a/examples/stm32f1/stm32-h103/exti_rising_falling/Makefile b/examples/stm32f1/stm32-h103/exti_rising_falling/Makefile new file mode 100644 index 0000000..fc603a6 --- /dev/null +++ b/examples/stm32f1/stm32-h103/exti_rising_falling/Makefile @@ -0,0 +1,23 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +## + +BINARY = exti_rising_falling + +include ../../Makefile.include + diff --git a/examples/stm32f1/stm32-h103/exti_rising_falling/exti_rising_falling.c b/examples/stm32f1/stm32-h103/exti_rising_falling/exti_rising_falling.c new file mode 100644 index 0000000..af1268d --- /dev/null +++ b/examples/stm32f1/stm32-h103/exti_rising_falling/exti_rising_falling.c @@ -0,0 +1,98 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann , + * 2010 Piotr Esden-Tempski + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include + +#define FALLING 0 +#define RISING 1 + +u16 exti_direction = FALLING; + +/* Set STM32 to 72 MHz. */ +void clock_setup(void) +{ + rcc_clock_setup_in_hse_8mhz_out_72mhz(); + +} + +void gpio_setup(void) +{ + /* Enable GPIOC clock. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); + + /* Set GPIO12 (in GPIO port C) to 'output push-pull'. */ + gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO12); +} + +void exti_setup(void) +{ + /* Enable GPIOA clock. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); + + /* Enable AFIO clock. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_AFIOEN); + + /* Enable EXTI0 interrupt */ + nvic_enable_irq(NVIC_EXTI0_IRQ); + + /* Set GPIO0 (in GPIO port A) to 'input open-drain'. */ + gpio_set_mode(GPIOA, GPIO_MODE_INPUT, + GPIO_CNF_INPUT_FLOAT, GPIO0); + + /* configure EXTI subsystem */ + exti_select_source(EXTI0, GPIOA); + exti_direction = FALLING; + exti_set_trigger(EXTI0, EXTI_TRIGGER_FALLING); + exti_enable_request(EXTI0); +} + +void exti0_isr() +{ + exti_reset_request(EXTI0); + + if (exti_direction == FALLING) { + gpio_set(GPIOC, GPIO12); + exti_direction = RISING; + exti_set_trigger(EXTI0, EXTI_TRIGGER_RISING); + } else { + gpio_clear(GPIOC, GPIO12); + exti_direction = FALLING; + exti_set_trigger(EXTI0, EXTI_TRIGGER_FALLING); + } +} + +int main(void) +{ + + clock_setup(); + gpio_setup(); + exti_setup(); + + /* Blink the LED (PC12) on the board. */ + while (1) { + __asm("nop"); + } + + return 0; +} diff --git a/examples/stm32f1/stm32-h103/exti_rising_falling/exti_rising_falling.ld b/examples/stm32f1/stm32-h103/exti_rising_falling/exti_rising_falling.ld new file mode 100644 index 0000000..7ea2b92 --- /dev/null +++ b/examples/stm32f1/stm32-h103/exti_rising_falling/exti_rising_falling.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Linker script for Olimex STM32-H103 (STM32F103RBT6, 128K flash, 20K RAM). */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32.ld + diff --git a/examples/stm32f1/stm32-h103/fancyblink/Makefile b/examples/stm32f1/stm32-h103/fancyblink/Makefile new file mode 100644 index 0000000..1baec4d --- /dev/null +++ b/examples/stm32f1/stm32-h103/fancyblink/Makefile @@ -0,0 +1,23 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +## + +BINARY = fancyblink + +include ../../Makefile.include + diff --git a/examples/stm32f1/stm32-h103/fancyblink/README b/examples/stm32f1/stm32-h103/fancyblink/README new file mode 100644 index 0000000..bdb6ec8 --- /dev/null +++ b/examples/stm32f1/stm32-h103/fancyblink/README @@ -0,0 +1,10 @@ +------------------------------------------------------------------------------ +README +------------------------------------------------------------------------------ + +This is small LED blinking example program using libopencm3. + +It's intended for the ST STM32-based Olimex STM32-H103 eval board (see +http://olimex.com/dev/stm32-h103.html for details). It should blink +the LED on the board. + diff --git a/examples/stm32f1/stm32-h103/fancyblink/fancyblink.c b/examples/stm32f1/stm32-h103/fancyblink/fancyblink.c new file mode 100644 index 0000000..eeb3f34 --- /dev/null +++ b/examples/stm32f1/stm32-h103/fancyblink/fancyblink.c @@ -0,0 +1,55 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include + +/* Set STM32 to 72 MHz. */ +void clock_setup(void) +{ + rcc_clock_setup_in_hse_8mhz_out_72mhz(); + + /* Enable GPIOC clock. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); + +} + +void gpio_setup(void) +{ + /* Set GPIO12 (in GPIO port C) to 'output push-pull'. */ + gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO12); +} + +int main(void) +{ + int i; + + clock_setup(); + gpio_setup(); + + /* Blink the LED (PC12) on the board. */ + while (1) { + gpio_toggle(GPIOC, GPIO12); /* LED on/off */ + for (i = 0; i < 800000; i++) /* Wait a bit. */ + __asm__("nop"); + } + + return 0; +} diff --git a/examples/stm32f1/stm32-h103/fancyblink/fancyblink.ld b/examples/stm32f1/stm32-h103/fancyblink/fancyblink.ld new file mode 100644 index 0000000..7ea2b92 --- /dev/null +++ b/examples/stm32f1/stm32-h103/fancyblink/fancyblink.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Linker script for Olimex STM32-H103 (STM32F103RBT6, 128K flash, 20K RAM). */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32.ld + diff --git a/examples/stm32f1/stm32-h103/led_stripe/Makefile b/examples/stm32f1/stm32-h103/led_stripe/Makefile new file mode 100644 index 0000000..60fd1ef --- /dev/null +++ b/examples/stm32f1/stm32-h103/led_stripe/Makefile @@ -0,0 +1,23 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +## + +BINARY = led_stripe + +include ../../Makefile.include + diff --git a/examples/stm32f1/stm32-h103/led_stripe/led_stripe.c b/examples/stm32f1/stm32-h103/led_stripe/led_stripe.c new file mode 100644 index 0000000..9cf9d4f --- /dev/null +++ b/examples/stm32f1/stm32-h103/led_stripe/led_stripe.c @@ -0,0 +1,234 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Piotr Esden-Tempski + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* + * This example is implementing the protocol of ZJ168 addressable led + * strips. These strips use the LPD6803 controller. You may be able to + * find the datasheet here: + * http://www.adafruit.com/datasheets/LPD6803.pdf + */ + +#include + +#include +#include + +#define SPI_BANK GPIOB +#define SCLK_PIN GPIO13 +#define MOSI_PIN GPIO15 + +#define SMALL_DELAY_VALUE 0 + +#define COLOR_COUNT 50 + +#define SCLK(VAL) \ + if (VAL) { \ + gpio_set(SPI_BANK, SCLK_PIN); \ + } else { \ + gpio_clear(SPI_BANK, SCLK_PIN); \ + } + +#define MOSI(VAL) \ + if (VAL) { \ + gpio_set(SPI_BANK, MOSI_PIN); \ + } else { \ + gpio_clear(SPI_BANK, MOSI_PIN); \ + } + +#define SMALL_DELAY() { \ + int j; \ + for (j = 0; j < SMALL_DELAY_VALUE; j++) \ + __asm__("nop"); \ + } + +struct color { + u8 r; + u8 g; + u8 b; +}; + +/* Set STM32 to 72 MHz. */ +void clock_setup(void) +{ + rcc_clock_setup_in_hse_8mhz_out_72mhz(); + + /* Enable GPIOC clock. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPBEN); + +} + +void gpio_setup(void) +{ + /* Set GPIO12 (in GPIO port C) to 'output push-pull'. */ + gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO12); + gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO13); + gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO15); +} + +void send_colors(struct color *colors, int count) { + int i, k; + + /* initialize spi pins */ + SCLK(0); + MOSI(0); + + /* start frame */ + for (i=0; i<32; i++) { + SCLK(1); + SMALL_DELAY(); + SCLK(0); + SMALL_DELAY(); + } + + /* color cell output */ + for (k = 0; k < count; k++) { + /* Start bit */ + MOSI(1); + SCLK(1); + SMALL_DELAY(); + SCLK(0); + SMALL_DELAY(); + + /* Blue */ + for (i=0; i<5; i++) { + MOSI(((colors[k].b & ((1 << 4) >> i)) != 0)); + SCLK(1); + SMALL_DELAY(); + SCLK(0); + SMALL_DELAY(); + } + /* Red */ + for (i=0; i<5; i++) { + MOSI(((colors[k].r & ((1 << 4) >> i)) != 0)); + SCLK(1); + SMALL_DELAY(); + SCLK(0); + SMALL_DELAY(); + } + /* Green */ + for (i=0; i<5; i++) { + MOSI(((colors[k].g & ((1 << 4) >> i)) != 0)); + SCLK(1); + SMALL_DELAY(); + SCLK(0); + SMALL_DELAY(); + } + } + + /* End frame */ + MOSI(0); + for (k=0; k < count; k++) { + SCLK(1); + SMALL_DELAY(); + SCLK(0); + SMALL_DELAY(); + } +} + +void reset_colors(struct color *colors, int count) { + int i; + + for (i=0; i + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Linker script for Olimex STM32-H103 (STM32F103RBT6, 128K flash, 20K RAM). */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32.ld + diff --git a/examples/stm32f1/stm32-h103/miniblink/Makefile b/examples/stm32f1/stm32-h103/miniblink/Makefile new file mode 100644 index 0000000..24a478b --- /dev/null +++ b/examples/stm32f1/stm32-h103/miniblink/Makefile @@ -0,0 +1,23 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +## + +BINARY = miniblink + +include ../../Makefile.include + diff --git a/examples/stm32f1/stm32-h103/miniblink/README b/examples/stm32f1/stm32-h103/miniblink/README new file mode 100644 index 0000000..0e046f2 --- /dev/null +++ b/examples/stm32f1/stm32-h103/miniblink/README @@ -0,0 +1,10 @@ +------------------------------------------------------------------------------ +README +------------------------------------------------------------------------------ + +This is the smallest-possible example program using libopencm3. + +It's intended for the ST STM32-based Olimex STM32-H103 eval board (see +http://olimex.com/dev/stm32-h103.html for details). It should blink +the LED on the board. + diff --git a/examples/stm32f1/stm32-h103/miniblink/miniblink.c b/examples/stm32f1/stm32-h103/miniblink/miniblink.c new file mode 100644 index 0000000..6f8bc2c --- /dev/null +++ b/examples/stm32f1/stm32-h103/miniblink/miniblink.c @@ -0,0 +1,71 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include + +void gpio_setup(void) +{ + /* Enable GPIOC clock. */ + /* Manually: */ + // RCC_APB2ENR |= RCC_APB2ENR_IOPCEN; + /* Using API functions: */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); + + /* Set GPIO12 (in GPIO port C) to 'output push-pull'. */ + /* Manually: */ + // GPIOC_CRH = (GPIO_CNF_OUTPUT_PUSHPULL << (((12 - 8) * 4) + 2)); + // GPIOC_CRH |= (GPIO_MODE_OUTPUT_2_MHZ << ((12 - 8) * 4)); + /* Using API functions: */ + gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_2_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO12); +} + +int main(void) +{ + int i; + + gpio_setup(); + + /* Blink the LED (PC12) on the board. */ + while (1) { + /* Manually: */ + // GPIOC_BSRR = GPIO12; /* LED off */ + // for (i = 0; i < 800000; i++) /* Wait a bit. */ + // __asm__("nop"); + // GPIOC_BRR = GPIO12; /* LED on */ + // for (i = 0; i < 800000; i++) /* Wait a bit. */ + // __asm__("nop"); + + /* Using API functions gpio_set()/gpio_clear(): */ + // gpio_set(GPIOC, GPIO12); /* LED off */ + // for (i = 0; i < 800000; i++) /* Wait a bit. */ + // __asm__("nop"); + // gpio_clear(GPIOC, GPIO12); /* LED on */ + // for (i = 0; i < 800000; i++) /* Wait a bit. */ + // __asm__("nop"); + + /* Using API function gpio_toggle(): */ + gpio_toggle(GPIOC, GPIO12); /* LED on/off */ + for (i = 0; i < 800000; i++) /* Wait a bit. */ + __asm__("nop"); + } + + return 0; +} diff --git a/examples/stm32f1/stm32-h103/miniblink/miniblink.ld b/examples/stm32f1/stm32-h103/miniblink/miniblink.ld new file mode 100644 index 0000000..7ea2b92 --- /dev/null +++ b/examples/stm32f1/stm32-h103/miniblink/miniblink.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Linker script for Olimex STM32-H103 (STM32F103RBT6, 128K flash, 20K RAM). */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32.ld + diff --git a/examples/stm32f1/stm32-h103/pwm_6step/Makefile b/examples/stm32f1/stm32-h103/pwm_6step/Makefile new file mode 100644 index 0000000..2360082 --- /dev/null +++ b/examples/stm32f1/stm32-h103/pwm_6step/Makefile @@ -0,0 +1,23 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +## + +BINARY = pwm_6step + +include ../../Makefile.include + diff --git a/examples/stm32f1/stm32-h103/pwm_6step/pwm_6step.c b/examples/stm32f1/stm32-h103/pwm_6step/pwm_6step.c new file mode 100644 index 0000000..bda8ff7 --- /dev/null +++ b/examples/stm32f1/stm32-h103/pwm_6step/pwm_6step.c @@ -0,0 +1,409 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Piotr Esden-Tempski + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include + +#define FALLING 0 +#define RISING 1 + +u16 exti_direction = FALLING; + +void clock_setup(void) +{ + rcc_clock_setup_in_hse_8mhz_out_72mhz(); + +} + +void gpio_setup(void) +{ + /* Enable GPIOC clock. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); + + /* + * Set GPIO12 (PORTC) (led) to + * 'output alternate function push-pull'. + */ + gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO12); + +} + +void exti_setup(void) +{ + /* Enable GPIOA clock. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); + + /* Enable AFIO clock. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_AFIOEN); + + /* Enable EXTI0 interrupt */ + nvic_enable_irq(NVIC_EXTI0_IRQ); + + /* Set GPIO0 (in GPIO port A) to 'input open-drain'. */ + gpio_set_mode(GPIOA, GPIO_MODE_INPUT, + GPIO_CNF_INPUT_FLOAT, GPIO0); + + /* configure EXTI subsystem */ + exti_select_source(EXTI0, GPIOA); + exti_direction = FALLING; + exti_set_trigger(EXTI0, EXTI_TRIGGER_FALLING); + exti_enable_request(EXTI0); +} + +void exti0_isr() +{ + exti_reset_request(EXTI0); + + if (exti_direction == FALLING) { + //gpio_toggle(GPIOA, GPIO12); + exti_direction = RISING; + exti_set_trigger(EXTI0, EXTI_TRIGGER_RISING); + } else { + //gpio_toggle(GPIOA, GPIO12); + timer_generate_event(TIM1, TIM_EGR_COMG); + exti_direction = FALLING; + exti_set_trigger(EXTI0, EXTI_TRIGGER_FALLING); + } +} + +void tim_setup(void) +{ + + /* Enable TIM1 clock. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_TIM1EN); + + /* Enable GPIOA, GPIOB and Alternate Function clocks. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, + RCC_APB2ENR_IOPAEN | + RCC_APB2ENR_IOPBEN | + RCC_APB2ENR_AFIOEN); + + /* + * Set TIM1 chanel output pins to + * 'output alternate function push-pull'. + */ + gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, + GPIO_TIM1_CH1 | + GPIO_TIM1_CH2 | + GPIO_TIM1_CH3); + + /* + * Set TIM1 complementary chanel output pins to + * 'output alternate function push-pull'. + */ + gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, + GPIO_TIM1_CH1N | + GPIO_TIM1_CH2N | + GPIO_TIM1_CH3N); + + /* Enable TIM1 commutation interrupt. */ + nvic_enable_irq(NVIC_TIM1_TRG_COM_IRQ); + + /* Reset TIM1 peripheral */ + timer_reset(TIM1); + + /* Timer global mode: + * - No divider + * - alignment edge + * - direction up + */ + timer_set_mode(TIM1, TIM_CR1_CKD_CK_INT, + TIM_CR1_CMS_EDGE, + TIM_CR1_DIR_UP); + + /* Reset prescaler value. */ + timer_set_prescaler(TIM1, 0); + + /* Reset repetition counter value. */ + timer_set_repetition_counter(TIM1, 0); + + /* Enable preload. */ + timer_enable_preload(TIM1); + + /* Continous mode. */ + timer_continuous_mode(TIM1); + + /* Period (32kHz) */ + timer_set_period(TIM1, 72000000 / 32000); + + /* Configure break and deadtime */ + timer_set_deadtime(TIM1, 10); + timer_set_enabled_off_state_in_idle_mode(TIM1); + timer_set_enabled_off_state_in_run_mode(TIM1); + timer_disable_break(TIM1); + timer_set_break_polarity_high(TIM1); + timer_disable_break_automatic_output(TIM1); + timer_set_break_lock(TIM1, TIM_BDTR_LOCK_OFF); + + /* -- OC1 and OC1N configuration -- */ + + /* Disable outputs. */ + timer_disable_oc_output(TIM1, TIM_OC1); + timer_disable_oc_output(TIM1, TIM_OC1N); + + /* Configure global mode of line 1. */ + timer_disable_oc_clear(TIM1, TIM_OC1); + timer_enable_oc_preload(TIM1, TIM_OC1); + timer_set_oc_slow_mode(TIM1, TIM_OC1); + timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_PWM1); + + /* Configure OC1. */ + timer_set_oc_polarity_high(TIM1, TIM_OC1); + timer_set_oc_idle_state_set(TIM1, TIM_OC1); + + /* Configure OC1N. */ + timer_set_oc_polarity_high(TIM1, TIM_OC1N); + timer_set_oc_idle_state_set(TIM1, TIM_OC1N); + + /* Set the capture compare value for OC1. */ + timer_set_oc_value(TIM1, TIM_OC1, 100); + + /* Reenable outputs. */ + timer_enable_oc_output(TIM1, TIM_OC1); + timer_enable_oc_output(TIM1, TIM_OC1N); + + /* -- OC2 and OC2N configuration -- */ + + /* Disable outputs. */ + timer_disable_oc_output(TIM1, TIM_OC2); + timer_disable_oc_output(TIM1, TIM_OC2N); + + /* Configure global mode of line 2. */ + timer_disable_oc_clear(TIM1, TIM_OC2); + timer_enable_oc_preload(TIM1, TIM_OC2); + timer_set_oc_slow_mode(TIM1, TIM_OC2); + timer_set_oc_mode(TIM1, TIM_OC2, TIM_OCM_PWM1); + + /* Configure OC2. */ + timer_set_oc_polarity_high(TIM1, TIM_OC2); + timer_set_oc_idle_state_set(TIM1, TIM_OC2); + + /* Configure OC2N. */ + timer_set_oc_polarity_high(TIM1, TIM_OC2N); + timer_set_oc_idle_state_set(TIM1, TIM_OC2N); + + /* Set the capture compare value for OC1. */ + timer_set_oc_value(TIM1, TIM_OC2, 100); + + /* Reenable outputs. */ + timer_enable_oc_output(TIM1, TIM_OC2); + timer_enable_oc_output(TIM1, TIM_OC2N); + + /* -- OC3 and OC3N configuration -- */ + + /* Disable outputs. */ + timer_disable_oc_output(TIM1, TIM_OC3); + timer_disable_oc_output(TIM1, TIM_OC3N); + + /* Configure global mode of line 3. */ + timer_disable_oc_clear(TIM1, TIM_OC3); + timer_enable_oc_preload(TIM1, TIM_OC3); + timer_set_oc_slow_mode(TIM1, TIM_OC3); + timer_set_oc_mode(TIM1, TIM_OC3, TIM_OCM_PWM1); + + /* Configure OC3. */ + timer_set_oc_polarity_high(TIM1, TIM_OC3); + timer_set_oc_idle_state_set(TIM1, TIM_OC3); + + /* Configure OC3N. */ + timer_set_oc_polarity_high(TIM1, TIM_OC3N); + timer_set_oc_idle_state_set(TIM1, TIM_OC3N); + + /* Set the capture compare value for OC3. */ + timer_set_oc_value(TIM1, TIM_OC3, 100); + + /* Reenable outputs. */ + timer_enable_oc_output(TIM1, TIM_OC3); + timer_enable_oc_output(TIM1, TIM_OC3N); + + /* ---- */ + /* ARR reload enable */ + timer_enable_preload(TIM1); + + /* Enable preload of complementary channel configurations and update on COM event */ + timer_enable_preload_complementry_enable_bits(TIM1); + + /* Enable outputs in the break subsystem */ + timer_enable_break_main_output(TIM1); + + /* Counter enable */ + timer_enable_counter(TIM1); + + /* Enable commutation interrupt */ + timer_enable_irq(TIM1, TIM_DIER_COMIE); +} + +void tim1_trg_com_isr(void) +{ + static int step = 0; + + /* Clear the COM trigger interrupt flag. */ + timer_clear_flag(TIM1, TIM_SR_COMIF); + + /* A simplified and inefficient implementation of PWM On + * scheme. Look at the implementation in Open-BLDC on + * http://open-bldc.org for the proper implementation. This + * one only serves as an example. + * + * Table of the pwm scheme zone configurations when driving: + * @verbatim + * | 1| 2| 3| 4| 5| 6| + * -+--+--+--+--+--+--+ + * A|p+|++| |p-|--| | + * -+--+--+--+--+--+--+ + * B| |p-|--| |p+|++| + * -+--+--+--+--+--+--+ + * C|--| |p+|++| |p-| + * -+--+--+--+--+--+--+ + * | | | | | | '- 360 Deg + * | | | | | '---- 300 Deg + * | | | | '------- 240 Deg + * | | | '---------- 180 Deg + * | | '------------- 120 Deg + * | '---------------- 60 Deg + * '------------------- 0 Deg + * + * Legend: + * p+: PWM on the high side + * p-: PWM on the low side + * --: Low side on + * ++: High side on + * : Floating/NC + * @endverbatim + */ + switch (step) { + case 0: /* A PWM HIGH, B OFF, C LOW */ + timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_PWM1); + timer_set_oc_mode(TIM1, TIM_OC2, TIM_OCM_FROZEN); + timer_set_oc_mode(TIM1, TIM_OC3, TIM_OCM_FORCE_LOW); + + timer_enable_oc_output(TIM1, TIM_OC1); + timer_disable_oc_output(TIM1, TIM_OC1N); + + timer_disable_oc_output(TIM1, TIM_OC2); + timer_disable_oc_output(TIM1, TIM_OC2N); + + timer_enable_oc_output(TIM1, TIM_OC3); + timer_enable_oc_output(TIM1, TIM_OC3N); + + step++; + break; + case 1: /* A HIGH, B PWM LOW, C OFF */ + timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_FORCE_HIGH); + timer_set_oc_mode(TIM1, TIM_OC2, TIM_OCM_PWM1); + timer_set_oc_mode(TIM1, TIM_OC3, TIM_OCM_FROZEN); + + timer_enable_oc_output(TIM1, TIM_OC1); + timer_enable_oc_output(TIM1, TIM_OC1N); + + timer_disable_oc_output(TIM1, TIM_OC2); + timer_enable_oc_output(TIM1, TIM_OC2N); + + timer_disable_oc_output(TIM1, TIM_OC3); + timer_disable_oc_output(TIM1, TIM_OC3N); + + step++; + break; + case 2: /* A OFF, B LOW, C PWM HIGH */ + timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_FROZEN); + timer_set_oc_mode(TIM1, TIM_OC2, TIM_OCM_FORCE_LOW); + timer_set_oc_mode(TIM1, TIM_OC3, TIM_OCM_PWM1); + + timer_disable_oc_output(TIM1, TIM_OC1); + timer_disable_oc_output(TIM1, TIM_OC1N); + + timer_enable_oc_output(TIM1, TIM_OC2); + timer_enable_oc_output(TIM1, TIM_OC2N); + + timer_enable_oc_output(TIM1, TIM_OC3); + timer_disable_oc_output(TIM1, TIM_OC3N); + + step++; + break; + case 3: /* A PWM LOW, B OFF, C HIGH */ + timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_PWM1); + timer_set_oc_mode(TIM1, TIM_OC2, TIM_OCM_FROZEN); + timer_set_oc_mode(TIM1, TIM_OC3, TIM_OCM_FORCE_HIGH); + + timer_disable_oc_output(TIM1, TIM_OC1); + timer_enable_oc_output(TIM1, TIM_OC1N); + + timer_disable_oc_output(TIM1, TIM_OC2); + timer_disable_oc_output(TIM1, TIM_OC2N); + + timer_enable_oc_output(TIM1, TIM_OC3); + timer_enable_oc_output(TIM1, TIM_OC3N); + + step++; + break; + case 4: /* A LOW, B PWM HIGH, C OFF */ + timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_FORCE_LOW); + timer_set_oc_mode(TIM1, TIM_OC2, TIM_OCM_PWM1); + timer_set_oc_mode(TIM1, TIM_OC3, TIM_OCM_FROZEN); + + timer_enable_oc_output(TIM1, TIM_OC1); + timer_enable_oc_output(TIM1, TIM_OC1N); + + timer_enable_oc_output(TIM1, TIM_OC2); + timer_disable_oc_output(TIM1, TIM_OC2N); + + timer_disable_oc_output(TIM1, TIM_OC3); + timer_disable_oc_output(TIM1, TIM_OC3N); + + step++; + break; + case 5: /* A OFF, B HIGH, C PWM LOW */ + timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_FROZEN); + timer_set_oc_mode(TIM1, TIM_OC2, TIM_OCM_FORCE_HIGH); + timer_set_oc_mode(TIM1, TIM_OC3, TIM_OCM_PWM1); + + timer_disable_oc_output(TIM1, TIM_OC1); + timer_disable_oc_output(TIM1, TIM_OC1N); + + timer_enable_oc_output(TIM1, TIM_OC2); + timer_enable_oc_output(TIM1, TIM_OC2N); + + timer_disable_oc_output(TIM1, TIM_OC3); + timer_enable_oc_output(TIM1, TIM_OC3N); + + step=0; + break; + } + gpio_toggle(GPIOC, GPIO12); +} + +int main(void) +{ + clock_setup(); + gpio_setup(); + tim_setup(); + exti_setup(); + + while (1) { + __asm("nop"); + } + + return 0; +} diff --git a/examples/stm32f1/stm32-h103/pwm_6step/pwm_6step.ld b/examples/stm32f1/stm32-h103/pwm_6step/pwm_6step.ld new file mode 100644 index 0000000..7ea2b92 --- /dev/null +++ b/examples/stm32f1/stm32-h103/pwm_6step/pwm_6step.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Linker script for Olimex STM32-H103 (STM32F103RBT6, 128K flash, 20K RAM). */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32.ld + diff --git a/examples/stm32f1/stm32-h103/spi/Makefile b/examples/stm32f1/stm32-h103/spi/Makefile new file mode 100644 index 0000000..7d3cb72 --- /dev/null +++ b/examples/stm32f1/stm32-h103/spi/Makefile @@ -0,0 +1,23 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2010 Uwe Hermann +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +## + +BINARY = spi + +include ../../Makefile.include + diff --git a/examples/stm32f1/stm32-h103/spi/README b/examples/stm32f1/stm32-h103/spi/README new file mode 100644 index 0000000..d4714c2 --- /dev/null +++ b/examples/stm32f1/stm32-h103/spi/README @@ -0,0 +1,8 @@ +------------------------------------------------------------------------------- +README +------------------------------------------------------------------------------- + +This example program repeatedly sends characters on SPI1 on the ST STM32-based +Olimex STM32-H103 eval board (see http://olimex.com/dev/stm32-h103.html +for details). + diff --git a/examples/stm32f1/stm32-h103/spi/spi.c b/examples/stm32f1/stm32-h103/spi/spi.c new file mode 100644 index 0000000..5a36bb8 --- /dev/null +++ b/examples/stm32f1/stm32-h103/spi/spi.c @@ -0,0 +1,50 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include + +void clock_setup(void) +{ + rcc_clock_setup_in_hse_8mhz_out_72mhz(); +} + +void spi_setup(void) +{ + /* TODO */ +} + +void gpio_setup(void) +{ + /* TODO */ +} + +int main(void) +{ + clock_setup(); + gpio_setup(); + spi_setup(); + + while (1) { + spi_write(SPI1, 0xaa); + spi_write(SPI1, 0x55); + } + + return 0; +} diff --git a/examples/stm32f1/stm32-h103/spi/spi.ld b/examples/stm32f1/stm32-h103/spi/spi.ld new file mode 100644 index 0000000..25806f8 --- /dev/null +++ b/examples/stm32f1/stm32-h103/spi/spi.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Linker script for Olimex STM32-H103 (STM32F103RBT6, 128K flash, 20K RAM). */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32.ld + diff --git a/examples/stm32f1/stm32-h103/timer/Makefile b/examples/stm32f1/stm32-h103/timer/Makefile new file mode 100644 index 0000000..86aced4 --- /dev/null +++ b/examples/stm32f1/stm32-h103/timer/Makefile @@ -0,0 +1,23 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +## + +BINARY = timer + +include ../../Makefile.include + diff --git a/examples/stm32f1/stm32-h103/timer/timer.c b/examples/stm32f1/stm32-h103/timer/timer.c new file mode 100644 index 0000000..ea64c86 --- /dev/null +++ b/examples/stm32f1/stm32-h103/timer/timer.c @@ -0,0 +1,183 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Piotr Esden-Tempski + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include + +u16 frequency_sequence[18] = { + 1000, + 500, + 1000, + 500, + 1000, + 500, + 2000, + 500, + 2000, + 500, + 2000, + 500, + 1000, + 500, + 1000, + 500, + 1000, + 5000 +}; + + +int frequency_sel = 0; + +u16 compare_time; +u16 new_time; +u16 frequency; +int debug = 0; + +void clock_setup(void) +{ + rcc_clock_setup_in_hse_8mhz_out_72mhz(); + +} + +void gpio_setup(void) +{ + /* Enable GPIOC clock. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); + + /* + * Set GPIO12 (PORTC) (led) to + * 'output alternate function push-pull'. + */ + gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO12); + + gpio_set(GPIOC, GPIO12); + +} + +void tim_setup(void) +{ + + /* Enable TIM2 clock. */ + rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_TIM2EN); + + + /* Enable TIM2 interrupt. */ + nvic_enable_irq(NVIC_TIM2_IRQ); + + /* Reset TIM2 peripheral */ + timer_reset(TIM2); + + /* Timer global mode: + * - No divider + * - alignment edge + * - direction up + */ + timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT, + TIM_CR1_CMS_EDGE, + TIM_CR1_DIR_UP); + + /* Reset prescaler value. */ + timer_set_prescaler(TIM2, 36000); + + /* Enable preload. */ + timer_disable_preload(TIM2); + + /* Continous mode. */ + timer_continuous_mode(TIM2); + + /* Period (36kHz) */ + timer_set_period(TIM2, 65535); + + /* Disable outputs. */ + timer_disable_oc_output(TIM2, TIM_OC1); + timer_disable_oc_output(TIM2, TIM_OC2); + timer_disable_oc_output(TIM2, TIM_OC3); + timer_disable_oc_output(TIM2, TIM_OC4); + + /* -- OC1 configuration -- */ + + /* Configure global mode of line 1. */ + timer_disable_oc_clear(TIM2, TIM_OC1); + timer_disable_oc_preload(TIM2, TIM_OC1); + timer_set_oc_slow_mode(TIM2, TIM_OC1); + timer_set_oc_mode(TIM2, TIM_OC1, TIM_OCM_FROZEN); + + /* Set the capture compare value for OC1. */ + timer_set_oc_value(TIM2, TIM_OC1, 1000); + + /* ---- */ + /* ARR reload enable */ + timer_disable_preload(TIM2); + + /* Counter enable */ + timer_enable_counter(TIM2); + + /* Enable commutation interrupt */ + timer_enable_irq(TIM2, TIM_DIER_CC1IE); +} + +void tim2_isr(void) +{ + + if (timer_get_flag(TIM2, TIM_SR_CC1IF)) { + + /* Clear compare interrupt flag. */ + timer_clear_flag(TIM2, TIM_SR_CC1IF); + + /* + * Get current timer value to calculate next + * compare register value + */ + compare_time = timer_get_counter(TIM2); + + /* + * Calculate and set the next compare value. + */ + frequency = frequency_sequence[frequency_sel++]; + new_time = compare_time + frequency; + + timer_set_oc_value(TIM2, TIM_OC1, + new_time); + if (frequency_sel == 18) { + frequency_sel = 0; + } + + /* Toggle led to indicate compare event */ + gpio_toggle(GPIOC, GPIO12); + + } +} + +int main(void) +{ + + clock_setup(); + gpio_setup(); + tim_setup(); + + while (1) { + __asm("nop"); + } + + return 0; +} diff --git a/examples/stm32f1/stm32-h103/timer/timer.ld b/examples/stm32f1/stm32-h103/timer/timer.ld new file mode 100644 index 0000000..7ea2b92 --- /dev/null +++ b/examples/stm32f1/stm32-h103/timer/timer.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Linker script for Olimex STM32-H103 (STM32F103RBT6, 128K flash, 20K RAM). */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32.ld + diff --git a/examples/stm32f1/stm32-h103/traceswo/Makefile b/examples/stm32f1/stm32-h103/traceswo/Makefile new file mode 100644 index 0000000..37510d5 --- /dev/null +++ b/examples/stm32f1/stm32-h103/traceswo/Makefile @@ -0,0 +1,23 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +## + +BINARY = traceswo + +include ../../Makefile.include + diff --git a/examples/stm32f1/stm32-h103/traceswo/README b/examples/stm32f1/stm32-h103/traceswo/README new file mode 100644 index 0000000..34b5227 --- /dev/null +++ b/examples/stm32f1/stm32-h103/traceswo/README @@ -0,0 +1,11 @@ +------------------------------------------------------------------------------ +README +------------------------------------------------------------------------------ + +This experimental program sends some characters on the TRACESWO pin using +the Instrumentation Trace Macrocell (ITM) and Trace Port Interface +Unit (TPIU). + +The SWJ-DP port must be in SWD mode and not JTAG mode for the output +to be visible. + diff --git a/examples/stm32f1/stm32-h103/traceswo/traceswo.c b/examples/stm32f1/stm32-h103/traceswo/traceswo.c new file mode 100644 index 0000000..ac461bb --- /dev/null +++ b/examples/stm32f1/stm32-h103/traceswo/traceswo.c @@ -0,0 +1,100 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include + +#include +#include +#include +#include + +void clock_setup(void) +{ + rcc_clock_setup_in_hse_8mhz_out_72mhz(); + + /* Enable GPIOC clock. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); +} + +void trace_setup(void) +{ + /* Enable trace subsystem (we'll use ITM and TPIU) */ + SCS_DEMCR |= SCS_DEMCR_TRCENA; + + /* Use Manchester code for asynchronous transmission */ + TPIU_SPPR = TPIU_SPPR_ASYNC_MANCHESTER; + TPIU_ACPR = 7; + + /* Data width is 1 byte */ + TPIU_CSPSR = TPIU_CSPSR_BYTE; + + /* Formatter and flush control */ + TPIU_FFCR &= ~TPIU_FFCR_ENFCONT; + + /* Enable TRACESWO pin for async mode */ + DBGMCU_CR = DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_ASYNC; + + /* Unlock access to ITM registers */ + /* FIXME: Magic numbers... Is this Cortex-M3 generic? */ + *((volatile uint32_t*)0xE0000FB0) = 0xC5ACCE55; + + /* Enable ITM with ID = 1 */ + ITM_TCR = (1 << 16) | ITM_TCR_ITMENA; + /* Enable stimulus port 1 */ + ITM_TER[0] = 1; + +} + +void gpio_setup(void) +{ + /* Set GPIO12 (in GPIO port C) to 'output push-pull'. */ + gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_2_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO12); +} + +void trace_send_blocking(char c) +{ + while(!(ITM_STIM[0] & ITM_STIM_FIFOREADY)); + ITM_STIM[0] = c; +} + +int main(void) +{ + int i, j = 0, c = 0; + + clock_setup(); + gpio_setup(); + trace_setup(); + + /* Blink the LED (PC12) on the board with every transmitted byte. */ + while (1) { + gpio_toggle(GPIOC, GPIO12); /* LED on/off */ + trace_send_blocking(c + '0'); + c = (c == 9) ? 0 : c + 1; /* Increment c. */ + if ((j++ % 80) == 0) { /* Newline after line full. */ + trace_send_blocking('\r'); + trace_send_blocking('\n'); + } + for (i = 0; i < 800000; i++) /* Wait a bit. */ + __asm__("NOP"); + } + + return 0; +} diff --git a/examples/stm32f1/stm32-h103/traceswo/traceswo.ld b/examples/stm32f1/stm32-h103/traceswo/traceswo.ld new file mode 100644 index 0000000..7ea2b92 --- /dev/null +++ b/examples/stm32f1/stm32-h103/traceswo/traceswo.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Linker script for Olimex STM32-H103 (STM32F103RBT6, 128K flash, 20K RAM). */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32.ld + diff --git a/examples/stm32f1/stm32-h103/usart/Makefile b/examples/stm32f1/stm32-h103/usart/Makefile new file mode 100644 index 0000000..2c1e1b1 --- /dev/null +++ b/examples/stm32f1/stm32-h103/usart/Makefile @@ -0,0 +1,23 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +## + +BINARY = usart + +include ../../Makefile.include + diff --git a/examples/stm32f1/stm32-h103/usart/README b/examples/stm32f1/stm32-h103/usart/README new file mode 100644 index 0000000..ecd7269 --- /dev/null +++ b/examples/stm32f1/stm32-h103/usart/README @@ -0,0 +1,13 @@ +------------------------------------------------------------------------------ +README +------------------------------------------------------------------------------ + +This example program sends some characters on USART3 on the ST STM32-based +Olimex STM32-H103 eval board (see http://olimex.com/dev/stm32-h103.html +for details). + +The terminal settings for the receiving device/PC are 38400 8n1. + +The sending is done in a blocking way in the code, see the usart_irq example +for a more elaborate USART example. + diff --git a/examples/stm32f1/stm32-h103/usart/usart.c b/examples/stm32f1/stm32-h103/usart/usart.c new file mode 100644 index 0000000..9692d61 --- /dev/null +++ b/examples/stm32f1/stm32-h103/usart/usart.c @@ -0,0 +1,119 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include + +void clock_setup(void) +{ + rcc_clock_setup_in_hse_8mhz_out_72mhz(); + + /* Enable GPIOC clock. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | RCC_APB2ENR_IOPCEN); + + /* Enable clocks for GPIO port B (for GPIO_USART3_TX) and USART3. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_USART1EN); + rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_USART2EN | RCC_APB1ENR_USART3EN); +} + +void usart_setup(void) +{ + /* Setup GPIO pin GPIO_USART1_TX. */ + gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_USART1_TX); + + /* Setup UART parameters. */ + usart_set_baudrate(USART1, 38400); + usart_set_databits(USART1, 8); + usart_set_stopbits(USART1, USART_STOPBITS_1); + usart_set_mode(USART1, USART_MODE_TX); + usart_set_parity(USART1, USART_PARITY_NONE); + usart_set_flow_control(USART1, USART_FLOWCONTROL_NONE); + + /* Finally enable the USART. */ + usart_enable(USART1); + + /* Setup GPIO pin GPIO_USART2_TX. */ + gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_USART2_TX); + + /* Setup UART parameters. */ + usart_set_baudrate(USART2, 38400); + usart_set_databits(USART2, 8); + usart_set_stopbits(USART2, USART_STOPBITS_1); + usart_set_mode(USART2, USART_MODE_TX); + usart_set_parity(USART2, USART_PARITY_NONE); + usart_set_flow_control(USART2, USART_FLOWCONTROL_NONE); + + /* Finally enable the USART. */ + usart_enable(USART2); + + /* Setup GPIO pin GPIO_USART3_TX/GPIO10 on GPIO port B for transmit. */ + gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_USART3_TX); + + /* Setup UART parameters. */ + usart_set_baudrate(USART3, 38400); + usart_set_databits(USART3, 8); + usart_set_stopbits(USART3, USART_STOPBITS_1); + usart_set_mode(USART3, USART_MODE_TX); + usart_set_parity(USART3, USART_PARITY_NONE); + usart_set_flow_control(USART3, USART_FLOWCONTROL_NONE); + + /* Finally enable the USART. */ + usart_enable(USART3); +} + +void gpio_setup(void) +{ + /* Set GPIO12 (in GPIO port C) to 'output push-pull'. */ + gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_2_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO12); +} + +int main(void) +{ + int i, j = 0, c = 0; + + clock_setup(); + gpio_setup(); + usart_setup(); + + /* Blink the LED (PC12) on the board with every transmitted byte. */ + while (1) { + gpio_toggle(GPIOC, GPIO12); /* LED on/off */ + usart_send_blocking(USART1, c + '0'); /* USART1: Send byte. */ + usart_send_blocking(USART2, c + '0'); /* USART2: Send byte. */ + usart_send_blocking(USART3, c + '0'); /* USART3: Send byte. */ + c = (c == 9) ? 0 : c + 1; /* Increment c. */ + if ((j++ % 80) == 0) { /* Newline after line full. */ + usart_send_blocking(USART1, '\r'); + usart_send_blocking(USART1, '\n'); + usart_send_blocking(USART2, '\r'); + usart_send_blocking(USART2, '\n'); + usart_send_blocking(USART3, '\r'); + usart_send_blocking(USART3, '\n'); + } + for (i = 0; i < 800000; i++) /* Wait a bit. */ + __asm__("NOP"); + } + + return 0; +} diff --git a/examples/stm32f1/stm32-h103/usart/usart.ld b/examples/stm32f1/stm32-h103/usart/usart.ld new file mode 100644 index 0000000..7ea2b92 --- /dev/null +++ b/examples/stm32f1/stm32-h103/usart/usart.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Linker script for Olimex STM32-H103 (STM32F103RBT6, 128K flash, 20K RAM). */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32.ld + diff --git a/examples/stm32f1/stm32-h103/usart_irq/Makefile b/examples/stm32f1/stm32-h103/usart_irq/Makefile new file mode 100644 index 0000000..6ee93bd --- /dev/null +++ b/examples/stm32f1/stm32-h103/usart_irq/Makefile @@ -0,0 +1,23 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +## + +BINARY = usart_irq + +include ../../Makefile.include + diff --git a/examples/stm32f1/stm32-h103/usart_irq/usart_irq.c b/examples/stm32f1/stm32-h103/usart_irq/usart_irq.c new file mode 100644 index 0000000..9b957dc --- /dev/null +++ b/examples/stm32f1/stm32-h103/usart_irq/usart_irq.c @@ -0,0 +1,119 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include + +void clock_setup(void) +{ + rcc_clock_setup_in_hse_8mhz_out_72mhz(); + + /* Enable GPIOA clock (for LED GPIOs). */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); + + /* Enable clocks for GPIO port A (for GPIO_USART1_TX) and USART1. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN | + RCC_APB2ENR_AFIOEN | + RCC_APB2ENR_USART1EN); +} + +void usart_setup(void) +{ + /* Enable the USART1 interrupt. */ + nvic_enable_irq(NVIC_USART1_IRQ); + + /* Setup GPIO pin GPIO_USART1_RE_TX on GPIO port B for transmit. */ + gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_USART1_TX); + + /* Setup GPIO pin GPIO_USART1_RE_RX on GPIO port B for receive. */ + gpio_set_mode(GPIOA, GPIO_MODE_INPUT, + GPIO_CNF_INPUT_FLOAT, GPIO_USART1_RX); + + /* Setup UART parameters. */ + usart_set_baudrate(USART1, 230400); + usart_set_databits(USART1, 8); + usart_set_stopbits(USART1, USART_STOPBITS_1); + usart_set_parity(USART1, USART_PARITY_NONE); + usart_set_flow_control(USART1, USART_FLOWCONTROL_NONE); + usart_set_mode(USART1, USART_MODE_TX_RX); + + /* Enable USART1 Receive interrupt. */ + USART_CR1(USART1) |= USART_CR1_RXNEIE; + + /* Finally enable the USART. */ + usart_enable(USART1); +} + +void gpio_setup(void) +{ + gpio_set(GPIOC, GPIO12); + + /* Setup GPIO6 and 7 (in GPIO port A) for led use. */ + gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO12); +} + +void usart1_isr(void) +{ + static u8 data = 'A'; + + /* Check if we were called because of RXNE. */ + if (((USART_CR1(USART1) & USART_CR1_RXNEIE) != 0) && + ((USART_SR(USART1) & USART_SR_RXNE) != 0)) { + + /* Indicate that we got data. */ + gpio_toggle(GPIOC, GPIO12); + + /* Retrieve the data from the peripheral. */ + data = usart_recv(USART1); + + /* Enable transmit interrupt so it sends back the data. */ + USART_CR1(USART1) |= USART_CR1_TXEIE; + } + + /* Check if we were called because of TXE. */ + if (((USART_CR1(USART1) & USART_CR1_TXEIE) != 0) && + ((USART_SR(USART1) & USART_SR_TXE) != 0)) { + + /* Indicate that we are sending out data. */ + //gpio_toggle(GPIOA, GPIO7); + + /* Put data into the transmit register. */ + usart_send(USART1, data); + + /* Disable the TXE interrupt as we don't need it anymore. */ + USART_CR1(USART1) &= ~USART_CR1_TXEIE; + } +} + +int main(void) +{ + clock_setup(); + gpio_setup(); + usart_setup(); + + /* Wait forever and do nothing. */ + while (1) + __asm__("nop"); + + return 0; +} diff --git a/examples/stm32f1/stm32-h103/usart_irq/usart_irq.ld b/examples/stm32f1/stm32-h103/usart_irq/usart_irq.ld new file mode 100644 index 0000000..7899773 --- /dev/null +++ b/examples/stm32f1/stm32-h103/usart_irq/usart_irq.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Linker script for Open-BLDC (STM32F103CBT6, 128K flash, 20K RAM). */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32.ld + diff --git a/examples/stm32f1/stm32-h103/usart_irq_printf/Makefile b/examples/stm32f1/stm32-h103/usart_irq_printf/Makefile new file mode 100644 index 0000000..2917a7d --- /dev/null +++ b/examples/stm32f1/stm32-h103/usart_irq_printf/Makefile @@ -0,0 +1,23 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +## + +BINARY = usart_irq_printf + +include ../../Makefile.include + diff --git a/examples/stm32f1/stm32-h103/usart_irq_printf/usart_irq_printf.c b/examples/stm32f1/stm32-h103/usart_irq_printf/usart_irq_printf.c new file mode 100644 index 0000000..42a7472 --- /dev/null +++ b/examples/stm32f1/stm32-h103/usart_irq_printf/usart_irq_printf.c @@ -0,0 +1,272 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann , + * 2011 Piotr Esden-Tempski + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include + +#include +#include + +/****************************************************************************** + * Simple ringbuffer implementation from open-bldc's libgovernor that + * you can find at: + * https://github.com/open-bldc/open-bldc/tree/master/source/libgovernor + ******************************************************************************/ + +typedef s32 ring_size_t; + +struct ring { + u8 *data; + ring_size_t size; + u32 begin; + u32 end; +}; + +#define RING_SIZE(RING) ((RING)->size - 1) +#define RING_DATA(RING) (RING)->data +#define RING_EMPTY(RING) ((RING)->begin == (RING)->end) + +void ring_init(struct ring *ring, u8 * buf, ring_size_t size) +{ + ring->data = buf; + ring->size = size; + ring->begin = 0; + ring->end = 0; +} + +s32 ring_write_ch(struct ring *ring, u8 ch) +{ + if (((ring->end + 1) % ring->size) != ring->begin) { + ring->data[ring->end++] = ch; + ring->end %= ring->size; + return (u32) ch; + } + + return -1; +} + +s32 ring_write(struct ring * ring, u8 * data, ring_size_t size) +{ + s32 i; + + for (i = 0; i < size; i++) { + if (ring_write_ch(ring, data[i]) < 0) { + return -i; + } + } + + return i; +} + +s32 ring_read_ch(struct ring * ring, u8 * ch) +{ + s32 ret = -1; + + if (ring->begin != ring->end) { + ret = ring->data[ring->begin++]; + ring->begin %= ring->size; + if (ch) + *ch = ret; + } + + return ret; +} + +s32 ring_read(struct ring * ring, u8 * data, ring_size_t size) +{ + s32 i; + + for (i = 0; i < size; i++) { + if (ring_read_ch(ring, data + i) < 0) { + return i; + } + } + + return -i; +} + +/****************************************************************************** + * The example implementation + ******************************************************************************/ + +#define BUFFER_SIZE 1024 + +struct ring output_ring; +u8 output_ring_buffer[BUFFER_SIZE]; + +void clock_setup(void) +{ + rcc_clock_setup_in_hse_8mhz_out_72mhz(); + + /* Enable GPIOA clock (for LED GPIOs). */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); + + /* Enable clocks for GPIO port A (for GPIO_USART1_TX) and USART1. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN | + RCC_APB2ENR_AFIOEN | + RCC_APB2ENR_USART1EN); +} + +void usart_setup(void) +{ + + /* Initialize output ring buffer */ + ring_init(&output_ring, output_ring_buffer, BUFFER_SIZE); + + /* Enable the USART1 interrupt. */ + nvic_enable_irq(NVIC_USART1_IRQ); + + /* Setup GPIO pin GPIO_USART1_RE_TX on GPIO port B for transmit. */ + gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_USART1_TX); + + /* Setup GPIO pin GPIO_USART1_RE_RX on GPIO port B for receive. */ + gpio_set_mode(GPIOA, GPIO_MODE_INPUT, + GPIO_CNF_INPUT_FLOAT, GPIO_USART1_RX); + + /* Setup UART parameters. */ + usart_set_baudrate(USART1, 230400); + usart_set_databits(USART1, 8); + usart_set_stopbits(USART1, USART_STOPBITS_1); + usart_set_parity(USART1, USART_PARITY_NONE); + usart_set_flow_control(USART1, USART_FLOWCONTROL_NONE); + usart_set_mode(USART1, USART_MODE_TX_RX); + + /* Enable USART1 Receive interrupt. */ + USART_CR1(USART1) |= USART_CR1_RXNEIE; + + /* Finally enable the USART. */ + usart_enable(USART1); +} + +void gpio_setup(void) +{ + gpio_set(GPIOC, GPIO12); + + /* Setup GPIO6 and 7 (in GPIO port A) for led use. */ + gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO12); +} + +void usart1_isr(void) +{ + /* Check if we were called because of RXNE. */ + if (((USART_CR1(USART1) & USART_CR1_RXNEIE) != 0) && + ((USART_SR(USART1) & USART_SR_RXNE) != 0)) { + + /* Indicate that we got data. */ + gpio_toggle(GPIOC, GPIO12); + + /* Retrieve the data from the peripheral. */ + ring_write_ch(&output_ring, usart_recv(USART1)); + + /* Enable transmit interrupt so it sends back the data. */ + USART_CR1(USART1) |= USART_CR1_TXEIE; + } + + /* Check if we were called because of TXE. */ + if (((USART_CR1(USART1) & USART_CR1_TXEIE) != 0) && + ((USART_SR(USART1) & USART_SR_TXE) != 0)) { + + s32 data; + + data = ring_read_ch(&output_ring, NULL); + + if (data == -1) { + /* Disable the TXE interrupt as we don't need it anymore. */ + USART_CR1(USART1) &= ~USART_CR1_TXEIE; + } else { + /* Put data into the transmit register. */ + usart_send(USART1, data); + } + } +} + +int _write (int file, char *ptr, int len) +{ + int ret; + + if (file == 1) { + ret = ring_write(&output_ring, (u8 *)ptr, len); + + if (ret < 0) ret = -ret; + + USART_CR1(USART1) |= USART_CR1_TXEIE; + + return ret; + } + + errno = EIO; + return -1; +} + +void systick_setup(void) { + + /* 72MHz / 8 => 9000000 counts per second */ + systick_set_clocksource(STK_CTRL_CLKSOURCE_AHB_DIV8); + + /* 9000000/9000 = 1000 overflows per second - every 1ms one interrupt */ + systick_set_reload(9000); + + systick_interrupt_enable(); + + /* Start counting. */ + systick_counter_enable(); + +} + +void sys_tick_handler(void) +{ + static int counter = 0; + static float fcounter = 0.0; + static double dcounter = 0.0; + + static u32 temp32 = 0; + + temp32++; + + /* We call this handler every 1ms so we are sending hello world every 10ms / 100Hz. */ + if (temp32 == 10) { + printf("Hello World! %i %f %f\r\n", counter, fcounter, dcounter); + counter++; + fcounter+=0.01; + dcounter+=0.01; + + temp32 = 0; + } +} + +int main(void) +{ + + clock_setup(); + gpio_setup(); + usart_setup(); + systick_setup(); + + while (1) { + __asm__("nop"); + } + + return 0; +} diff --git a/examples/stm32f1/stm32-h103/usart_irq_printf/usart_irq_printf.ld b/examples/stm32f1/stm32-h103/usart_irq_printf/usart_irq_printf.ld new file mode 100644 index 0000000..7899773 --- /dev/null +++ b/examples/stm32f1/stm32-h103/usart_irq_printf/usart_irq_printf.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Linker script for Open-BLDC (STM32F103CBT6, 128K flash, 20K RAM). */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32.ld + diff --git a/examples/stm32f1/stm32-h103/usart_printf/Makefile b/examples/stm32f1/stm32-h103/usart_printf/Makefile new file mode 100644 index 0000000..fb26208 --- /dev/null +++ b/examples/stm32f1/stm32-h103/usart_printf/Makefile @@ -0,0 +1,23 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +## + +BINARY = usart_printf + +include ../../Makefile.include + diff --git a/examples/stm32f1/stm32-h103/usart_printf/usart_printf.c b/examples/stm32f1/stm32-h103/usart_printf/usart_printf.c new file mode 100644 index 0000000..26fcee6 --- /dev/null +++ b/examples/stm32f1/stm32-h103/usart_printf/usart_printf.c @@ -0,0 +1,108 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann , + * 2011 Piotr Esden-Tempski + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include + +#include +#include + +void clock_setup(void) +{ + rcc_clock_setup_in_hse_8mhz_out_72mhz(); + + /* Enable GPIOA clock (for LED GPIOs). */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); + + /* Enable clocks for GPIO port A (for GPIO_USART1_TX) and USART1. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN | + RCC_APB2ENR_AFIOEN | + RCC_APB2ENR_USART1EN); +} + +void usart_setup(void) +{ + /* Setup GPIO pin GPIO_USART1_RE_TX on GPIO port B for transmit. */ + gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_USART1_TX); + + /* Setup UART parameters. */ + usart_set_baudrate(USART1, 230400); + usart_set_databits(USART1, 8); + usart_set_stopbits(USART1, USART_STOPBITS_1); + usart_set_parity(USART1, USART_PARITY_NONE); + usart_set_flow_control(USART1, USART_FLOWCONTROL_NONE); + usart_set_mode(USART1, USART_MODE_TX); + + /* Finally enable the USART. */ + usart_enable(USART1); +} + +void gpio_setup(void) +{ + gpio_set(GPIOC, GPIO12); + + /* Setup GPIO6 and 7 (in GPIO port A) for led use. */ + gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO12); +} + +int _write (int file, char *ptr, int len) +{ + int i; + + if (file == 1) { + for (i = 0; i < len; i++){ + usart_send_blocking(USART1, ptr[i]); + } + + return i; + } + + errno = EIO; + return -1; +} + +int main(void) +{ + int counter = 0; + float fcounter = 0.0; + double dcounter = 0.0; + + clock_setup(); + gpio_setup(); + usart_setup(); + + /* + * Write Hello World an integer, float and double all over + * again while incrementing the numbers. + */ + while (1) { + gpio_toggle(GPIOC, GPIO12); + printf("Hello World! %i %f %f\r\n", counter, fcounter, dcounter); + counter++; + fcounter+=0.01; + dcounter+=0.01; + } + + return 0; +} diff --git a/examples/stm32f1/stm32-h103/usart_printf/usart_printf.ld b/examples/stm32f1/stm32-h103/usart_printf/usart_printf.ld new file mode 100644 index 0000000..7899773 --- /dev/null +++ b/examples/stm32f1/stm32-h103/usart_printf/usart_printf.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Linker script for Open-BLDC (STM32F103CBT6, 128K flash, 20K RAM). */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32.ld + diff --git a/examples/stm32f1/stm32-h103/usb_cdcacm/Makefile b/examples/stm32f1/stm32-h103/usb_cdcacm/Makefile new file mode 100644 index 0000000..38179e3 --- /dev/null +++ b/examples/stm32f1/stm32-h103/usb_cdcacm/Makefile @@ -0,0 +1,23 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +## + +BINARY = cdcacm + +include ../../Makefile.include + diff --git a/examples/stm32f1/stm32-h103/usb_cdcacm/README b/examples/stm32f1/stm32-h103/usb_cdcacm/README new file mode 100644 index 0000000..2f1ee4b --- /dev/null +++ b/examples/stm32f1/stm32-h103/usb_cdcacm/README @@ -0,0 +1,7 @@ +------------------------------------------------------------------------------ +README +------------------------------------------------------------------------------ + +This example implements a USB CDC-ACM device (aka Virtual Serial Port) +to demonstrate the use of the USB device stack. + diff --git a/examples/stm32f1/stm32-h103/usb_cdcacm/cdcacm.c b/examples/stm32f1/stm32-h103/usb_cdcacm/cdcacm.c new file mode 100644 index 0000000..4b90640 --- /dev/null +++ b/examples/stm32f1/stm32-h103/usb_cdcacm/cdcacm.c @@ -0,0 +1,246 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Gareth McMullin + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include + +static const struct usb_device_descriptor dev = { + .bLength = USB_DT_DEVICE_SIZE, + .bDescriptorType = USB_DT_DEVICE, + .bcdUSB = 0x0200, + .bDeviceClass = USB_CLASS_CDC, + .bDeviceSubClass = 0, + .bDeviceProtocol = 0, + .bMaxPacketSize0 = 64, + .idVendor = 0x0483, + .idProduct = 0x5740, + .bcdDevice = 0x0200, + .iManufacturer = 1, + .iProduct = 2, + .iSerialNumber = 3, + .bNumConfigurations = 1, +}; + +/* This notification endpoint isn't implemented. According to CDC spec its + * optional, but its absence causes a NULL pointer dereference in Linux cdc_acm + * driver. */ +static const struct usb_endpoint_descriptor comm_endp[] = {{ + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = 0x83, + .bmAttributes = USB_ENDPOINT_ATTR_INTERRUPT, + .wMaxPacketSize = 16, + .bInterval = 255, +}}; + +static const struct usb_endpoint_descriptor data_endp[] = {{ + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = 0x01, + .bmAttributes = USB_ENDPOINT_ATTR_BULK, + .wMaxPacketSize = 64, + .bInterval = 1, +}, { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = 0x82, + .bmAttributes = USB_ENDPOINT_ATTR_BULK, + .wMaxPacketSize = 64, + .bInterval = 1, +}}; + +static const struct { + struct usb_cdc_header_descriptor header; + struct usb_cdc_call_management_descriptor call_mgmt; + struct usb_cdc_acm_descriptor acm; + struct usb_cdc_union_descriptor cdc_union; +} __attribute__((packed)) cdcacm_functional_descriptors = { + .header = { + .bFunctionLength = sizeof(struct usb_cdc_header_descriptor), + .bDescriptorType = CS_INTERFACE, + .bDescriptorSubtype = USB_CDC_TYPE_HEADER, + .bcdCDC = 0x0110, + }, + .call_mgmt = { + .bFunctionLength = + sizeof(struct usb_cdc_call_management_descriptor), + .bDescriptorType = CS_INTERFACE, + .bDescriptorSubtype = USB_CDC_TYPE_CALL_MANAGEMENT, + .bmCapabilities = 0, + .bDataInterface = 1, + }, + .acm = { + .bFunctionLength = sizeof(struct usb_cdc_acm_descriptor), + .bDescriptorType = CS_INTERFACE, + .bDescriptorSubtype = USB_CDC_TYPE_ACM, + .bmCapabilities = 0, + }, + .cdc_union = { + .bFunctionLength = sizeof(struct usb_cdc_union_descriptor), + .bDescriptorType = CS_INTERFACE, + .bDescriptorSubtype = USB_CDC_TYPE_UNION, + .bControlInterface = 0, + .bSubordinateInterface0 = 1, + } +}; + +static const struct usb_interface_descriptor comm_iface[] = {{ + .bLength = USB_DT_INTERFACE_SIZE, + .bDescriptorType = USB_DT_INTERFACE, + .bInterfaceNumber = 0, + .bAlternateSetting = 0, + .bNumEndpoints = 1, + .bInterfaceClass = USB_CLASS_CDC, + .bInterfaceSubClass = USB_CDC_SUBCLASS_ACM, + .bInterfaceProtocol = USB_CDC_PROTOCOL_AT, + .iInterface = 0, + + .endpoint = comm_endp, + + .extra = &cdcacm_functional_descriptors, + .extralen = sizeof(cdcacm_functional_descriptors) +}}; + +static const struct usb_interface_descriptor data_iface[] = {{ + .bLength = USB_DT_INTERFACE_SIZE, + .bDescriptorType = USB_DT_INTERFACE, + .bInterfaceNumber = 1, + .bAlternateSetting = 0, + .bNumEndpoints = 2, + .bInterfaceClass = USB_CLASS_DATA, + .bInterfaceSubClass = 0, + .bInterfaceProtocol = 0, + .iInterface = 0, + + .endpoint = data_endp, +}}; + +static const struct usb_interface ifaces[] = {{ + .num_altsetting = 1, + .altsetting = comm_iface, +}, { + .num_altsetting = 1, + .altsetting = data_iface, +}}; + +static const struct usb_config_descriptor config = { + .bLength = USB_DT_CONFIGURATION_SIZE, + .bDescriptorType = USB_DT_CONFIGURATION, + .wTotalLength = 0, + .bNumInterfaces = 2, + .bConfigurationValue = 1, + .iConfiguration = 0, + .bmAttributes = 0x80, + .bMaxPower = 0x32, + + .interface = ifaces, +}; + +static const char *usb_strings[] = { + "x", + "Black Sphere Technologies", + "CDC-ACM Demo", + "DEMO" +}; + +static int cdcacm_control_request(struct usb_setup_data *req, u8 **buf, + u16 *len, void (**complete)(struct usb_setup_data *req)) +{ + (void)complete; + (void)buf; + + switch(req->bRequest) { + case USB_CDC_REQ_SET_CONTROL_LINE_STATE: { + /* This Linux cdc_acm driver requires this to be implemented + * even though it's optional in the CDC spec, and we don't + * advertise it in the ACM functional descriptor. */ + char buf[10]; + struct usb_cdc_notification *notif = (void*)buf; + + /* We echo signals back to host as notification */ + notif->bmRequestType = 0xA1; + notif->bNotification = USB_CDC_NOTIFY_SERIAL_STATE; + notif->wValue = 0; + notif->wIndex = 0; + notif->wLength = 2; + buf[8] = req->wValue & 3; + buf[9] = 0; + //usbd_ep_write_packet(0x83, buf, 10); + return 1; + } + case USB_CDC_REQ_SET_LINE_CODING: + if(*len < sizeof(struct usb_cdc_line_coding)) + return 0; + + return 1; + } + return 0; +} + +static void cdcacm_data_rx_cb(u8 ep) +{ + (void)ep; + + char buf[64]; + int len = usbd_ep_read_packet(0x01, buf, 64); + if(len) { + usbd_ep_write_packet(0x82, buf, len); + buf[len] = 0; + } +} + +static void cdcacm_set_config(u16 wValue) +{ + (void)wValue; + + usbd_ep_setup(0x01, USB_ENDPOINT_ATTR_BULK, 64, cdcacm_data_rx_cb); + usbd_ep_setup(0x82, USB_ENDPOINT_ATTR_BULK, 64, NULL); + usbd_ep_setup(0x83, USB_ENDPOINT_ATTR_INTERRUPT, 16, NULL); + + usbd_register_control_callback( + USB_REQ_TYPE_CLASS | USB_REQ_TYPE_INTERFACE, + USB_REQ_TYPE_TYPE | USB_REQ_TYPE_RECIPIENT, + cdcacm_control_request); +} + +int main(void) +{ + int i; + + rcc_clock_setup_in_hsi_out_48mhz(); + + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); + + gpio_set(GPIOC, GPIO11); + gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_2_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO11); + + usbd_init(&stm32f103_usb_driver, &dev, &config, usb_strings); + usbd_register_set_config_callback(cdcacm_set_config); + + for (i = 0; i < 0x800000; i++) + __asm__("nop"); + gpio_clear(GPIOC, GPIO11); + + while (1) + usbd_poll(); +} diff --git a/examples/stm32f1/stm32-h103/usb_cdcacm/cdcacm.ld b/examples/stm32f1/stm32-h103/usb_cdcacm/cdcacm.ld new file mode 100644 index 0000000..928c898 --- /dev/null +++ b/examples/stm32f1/stm32-h103/usb_cdcacm/cdcacm.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Linker script for Olimex STM32-H103 (STM32F103RBT6, 128K flash, 20K RAM). */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32.ld + diff --git a/examples/stm32f1/stm32-h103/usb_dfu/Makefile b/examples/stm32f1/stm32-h103/usb_dfu/Makefile new file mode 100644 index 0000000..48e2d6b --- /dev/null +++ b/examples/stm32f1/stm32-h103/usb_dfu/Makefile @@ -0,0 +1,23 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +## + +BINARY = usbdfu + +include ../../Makefile.include + diff --git a/examples/stm32f1/stm32-h103/usb_dfu/README b/examples/stm32f1/stm32-h103/usb_dfu/README new file mode 100644 index 0000000..9c0169a --- /dev/null +++ b/examples/stm32f1/stm32-h103/usb_dfu/README @@ -0,0 +1,7 @@ +------------------------------------------------------------------------------ +README +------------------------------------------------------------------------------ + +This example implements a USB Device Firmware Upgrade (DFU) bootloader +to demonstrate the use of the USB device stack. + diff --git a/examples/stm32f1/stm32-h103/usb_dfu/usbdfu.c b/examples/stm32f1/stm32-h103/usb_dfu/usbdfu.c new file mode 100644 index 0000000..7ffbc74 --- /dev/null +++ b/examples/stm32f1/stm32-h103/usb_dfu/usbdfu.c @@ -0,0 +1,270 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Gareth McMullin + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include +#include +#include + +#define APP_ADDRESS 0x08002000 + +/* Commands sent with wBlockNum == 0 as per ST implementation. */ +#define CMD_SETADDR 0x21 +#define CMD_ERASE 0x41 + +/* We need a special large control buffer for this device: */ +u8 usbd_control_buffer[1024]; + +static enum dfu_state usbdfu_state = STATE_DFU_IDLE; + +static struct { + u8 buf[sizeof(usbd_control_buffer)]; + u16 len; + u32 addr; + u16 blocknum; +} prog; + +const struct usb_device_descriptor dev = { + .bLength = USB_DT_DEVICE_SIZE, + .bDescriptorType = USB_DT_DEVICE, + .bcdUSB = 0x0200, + .bDeviceClass = 0, + .bDeviceSubClass = 0, + .bDeviceProtocol = 0, + .bMaxPacketSize0 = 64, + .idVendor = 0x0483, + .idProduct = 0xDF11, + .bcdDevice = 0x0200, + .iManufacturer = 1, + .iProduct = 2, + .iSerialNumber = 3, + .bNumConfigurations = 1, +}; + +const struct usb_dfu_descriptor dfu_function = { + .bLength = sizeof(struct usb_dfu_descriptor), + .bDescriptorType = DFU_FUNCTIONAL, + .bmAttributes = USB_DFU_CAN_DOWNLOAD | USB_DFU_WILL_DETACH, + .wDetachTimeout = 255, + .wTransferSize = 1024, + .bcdDFUVersion = 0x011A, +}; + +const struct usb_interface_descriptor iface = { + .bLength = USB_DT_INTERFACE_SIZE, + .bDescriptorType = USB_DT_INTERFACE, + .bInterfaceNumber = 0, + .bAlternateSetting = 0, + .bNumEndpoints = 0, + .bInterfaceClass = 0xFE, /* Device Firmware Upgrade */ + .bInterfaceSubClass = 1, + .bInterfaceProtocol = 2, + + /* The ST Microelectronics DfuSe application needs this string. + * The format isn't documented... */ + .iInterface = 4, + + .extra = &dfu_function, + .extralen = sizeof(dfu_function), +}; + +const struct usb_interface ifaces[] = {{ + .num_altsetting = 1, + .altsetting = &iface, +}}; + +const struct usb_config_descriptor config = { + .bLength = USB_DT_CONFIGURATION_SIZE, + .bDescriptorType = USB_DT_CONFIGURATION, + .wTotalLength = 0, + .bNumInterfaces = 1, + .bConfigurationValue = 1, + .iConfiguration = 0, + .bmAttributes = 0xC0, + .bMaxPower = 0x32, + + .interface = ifaces, +}; + +static const char *usb_strings[] = { + "x", + "Black Sphere Technologies", + "DFU Demo", + "DEMO", + /* This string is used by ST Microelectronics' DfuSe utility */ + "@Internal Flash /0x08000000/8*001Ka,56*001Kg" +}; + +static u8 usbdfu_getstatus(u32 *bwPollTimeout) +{ + switch(usbdfu_state) { + case STATE_DFU_DNLOAD_SYNC: + usbdfu_state = STATE_DFU_DNBUSY; + *bwPollTimeout = 100; + return DFU_STATUS_OK; + + case STATE_DFU_MANIFEST_SYNC: + /* Device will reset when read is complete */ + usbdfu_state = STATE_DFU_MANIFEST; + return DFU_STATUS_OK; + + default: + return DFU_STATUS_OK; + } +} + +static void usbdfu_getstatus_complete(struct usb_setup_data *req) +{ + int i; + (void)req; + + switch(usbdfu_state) { + case STATE_DFU_DNBUSY: + + flash_unlock(); + if(prog.blocknum == 0) { + switch(prog.buf[0]) { + case CMD_ERASE: + flash_erase_page(*(u32*)(prog.buf+1)); + case CMD_SETADDR: + prog.addr = *(u32*)(prog.buf+1); + } + } else { + u32 baseaddr = prog.addr + + ((prog.blocknum - 2) * + dfu_function.wTransferSize); + for(i = 0; i < prog.len; i += 2) + flash_program_half_word(baseaddr + i, + *(u16*)(prog.buf+i)); + } + flash_lock(); + + /* We jump straight to dfuDNLOAD-IDLE, + * skipping dfuDNLOAD-SYNC + */ + usbdfu_state = STATE_DFU_DNLOAD_IDLE; + return; + + case STATE_DFU_MANIFEST: + /* USB device must detach, we just reset... */ + scb_reset_system(); + return; /* Will never return */ + default: + return; + } +} + +static int usbdfu_control_request(struct usb_setup_data *req, u8 **buf, + u16 *len, void (**complete)(struct usb_setup_data *req)) +{ + + if((req->bmRequestType & 0x7F) != 0x21) + return 0; /* Only accept class request */ + + switch(req->bRequest) { + case DFU_DNLOAD: + if((len == NULL) || (*len == 0)) { + usbdfu_state = STATE_DFU_MANIFEST_SYNC; + return 1; + } else { + /* Copy download data for use on GET_STATUS */ + prog.blocknum = req->wValue; + prog.len = *len; + memcpy(prog.buf, *buf, *len); + usbdfu_state = STATE_DFU_DNLOAD_SYNC; + return 1; + } + case DFU_CLRSTATUS: + /* Clear error and return to dfuIDLE */ + if(usbdfu_state == STATE_DFU_ERROR) + usbdfu_state = STATE_DFU_IDLE; + return 1; + case DFU_ABORT: + /* Abort returns to dfuIDLE state */ + usbdfu_state = STATE_DFU_IDLE; + return 1; + case DFU_UPLOAD: + /* Upload not supported for now */ + return 0; + case DFU_GETSTATUS: { + u32 bwPollTimeout = 0; /* 24-bit integer in DFU class spec */ + + (*buf)[0] = usbdfu_getstatus(&bwPollTimeout); + (*buf)[1] = bwPollTimeout & 0xFF; + (*buf)[2] = (bwPollTimeout >> 8) & 0xFF; + (*buf)[3] = (bwPollTimeout >> 16) & 0xFF; + (*buf)[4] = usbdfu_state; + (*buf)[5] = 0; /* iString not used here */ + *len = 6; + + *complete = usbdfu_getstatus_complete; + + return 1; + } + case DFU_GETSTATE: + /* Return state with no state transision */ + *buf[0] = usbdfu_state; + *len = 1; + return 1; + } + + return 0; +} + +int main(void) +{ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); + if(!gpio_get(GPIOA, GPIO10)) { + /* Boot the application if it's valid */ + if((*(volatile u32*)APP_ADDRESS & 0x2FFE0000) == 0x20000000) { + /* Set vector table base address */ + SCB_VTOR = APP_ADDRESS & 0xFFFF; + /* Initialise master stack pointer */ + asm volatile ("msr msp, %0"::"g" + (*(volatile u32*)APP_ADDRESS)); + /* Jump to application */ + (*(void(**)())(APP_ADDRESS + 4))(); + } + } + + rcc_clock_setup_in_hsi_out_48mhz(); + + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_AFIOEN); + + AFIO_MAPR |= AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_ON; + gpio_set_mode(GPIOA, GPIO_MODE_INPUT, 0, GPIO15); + + usbd_init(&stm32f103_usb_driver, &dev, &config, usb_strings); + usbd_set_control_buffer_size(sizeof(usbd_control_buffer)); + usbd_register_control_callback( + USB_REQ_TYPE_CLASS | USB_REQ_TYPE_INTERFACE, + USB_REQ_TYPE_TYPE | USB_REQ_TYPE_RECIPIENT, + usbdfu_control_request); + + gpio_set(GPIOA, GPIO15); + gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_2_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO15); + + while (1) + usbd_poll(); +} diff --git a/examples/stm32f1/stm32-h103/usb_dfu/usbdfu.ld b/examples/stm32f1/stm32-h103/usb_dfu/usbdfu.ld new file mode 100644 index 0000000..54e5dac --- /dev/null +++ b/examples/stm32f1/stm32-h103/usb_dfu/usbdfu.ld @@ -0,0 +1,29 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 8K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 4K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32.ld + diff --git a/examples/stm32f1/stm32-h103/usb_hid/Makefile b/examples/stm32f1/stm32-h103/usb_hid/Makefile new file mode 100644 index 0000000..d831e9e --- /dev/null +++ b/examples/stm32f1/stm32-h103/usb_hid/Makefile @@ -0,0 +1,23 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +## + +BINARY = usbhid + +include ../../Makefile.include + diff --git a/examples/stm32f1/stm32-h103/usb_hid/README b/examples/stm32f1/stm32-h103/usb_hid/README new file mode 100644 index 0000000..48a9b39 --- /dev/null +++ b/examples/stm32f1/stm32-h103/usb_hid/README @@ -0,0 +1,7 @@ +------------------------------------------------------------------------------ +README +------------------------------------------------------------------------------ + +This example implements a USB Human Interface Device (HID) +to demonstrate the use of the USB device stack. + diff --git a/examples/stm32f1/stm32-h103/usb_hid/usbhid.c b/examples/stm32f1/stm32-h103/usb_hid/usbhid.c new file mode 100644 index 0000000..a21fce6 --- /dev/null +++ b/examples/stm32f1/stm32-h103/usb_hid/usbhid.c @@ -0,0 +1,272 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Gareth McMullin + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include +#include + +/* Define this to include the DFU APP interface. */ +#define INCLUDE_DFU_INTERFACE + +#ifdef INCLUDE_DFU_INTERFACE +#include +#include +#endif + +const struct usb_device_descriptor dev = { + .bLength = USB_DT_DEVICE_SIZE, + .bDescriptorType = USB_DT_DEVICE, + .bcdUSB = 0x0200, + .bDeviceClass = 0, + .bDeviceSubClass = 0, + .bDeviceProtocol = 0, + .bMaxPacketSize0 = 64, + .idVendor = 0x0483, + .idProduct = 0x5710, + .bcdDevice = 0x0200, + .iManufacturer = 1, + .iProduct = 2, + .iSerialNumber = 3, + .bNumConfigurations = 1, +}; + +/* I have no idea what this means. I haven't read the HID spec. */ +static const u8 hid_report_descriptor[] = { + 0x05, 0x01, 0x09, 0x02, 0xA1, 0x01, 0x09, 0x01, + 0xA1, 0x00, 0x05, 0x09, 0x19, 0x01, 0x29, 0x03, + 0x15, 0x00, 0x25, 0x01, 0x95, 0x03, 0x75, 0x01, + 0x81, 0x02, 0x95, 0x01, 0x75, 0x05, 0x81, 0x01, + 0x05, 0x01, 0x09, 0x30, 0x09, 0x31, 0x09, 0x38, + 0x15, 0x81, 0x25, 0x7F, 0x75, 0x08, 0x95, 0x03, + 0x81, 0x06, 0xC0, 0x09, 0x3c, 0x05, 0xff, 0x09, + 0x01, 0x15, 0x00, 0x25, 0x01, 0x75, 0x01, 0x95, + 0x02, 0xb1, 0x22, 0x75, 0x06, 0x95, 0x01, 0xb1, + 0x01, 0xc0 +}; + +static const struct { + struct usb_hid_descriptor hid_descriptor; + struct { + u8 bReportDescriptorType; + u16 wDescriptorLength; + } __attribute__((packed)) hid_report; +} __attribute__((packed)) hid_function = { + .hid_descriptor = { + .bLength = sizeof(hid_function), + .bDescriptorType = USB_DT_HID, + .bcdHID = 0x0100, + .bCountryCode = 0, + .bNumDescriptors = 1, + }, + .hid_report = { + .bReportDescriptorType = USB_DT_REPORT, + .wDescriptorLength = sizeof(hid_report_descriptor), + } +}; + +const struct usb_endpoint_descriptor hid_endpoint = { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = 0x81, + .bmAttributes = USB_ENDPOINT_ATTR_INTERRUPT, + .wMaxPacketSize = 4, + .bInterval = 0x20, +}; + +const struct usb_interface_descriptor hid_iface = { + .bLength = USB_DT_INTERFACE_SIZE, + .bDescriptorType = USB_DT_INTERFACE, + .bInterfaceNumber = 0, + .bAlternateSetting = 0, + .bNumEndpoints = 1, + .bInterfaceClass = USB_CLASS_HID, + .bInterfaceSubClass = 1, /* boot */ + .bInterfaceProtocol = 2, /* mouse */ + .iInterface = 0, + + .endpoint = &hid_endpoint, + + .extra = &hid_function, + .extralen = sizeof(hid_function), +}; + +#ifdef INCLUDE_DFU_INTERFACE +const struct usb_dfu_descriptor dfu_function = { + .bLength = sizeof(struct usb_dfu_descriptor), + .bDescriptorType = DFU_FUNCTIONAL, + .bmAttributes = USB_DFU_CAN_DOWNLOAD | USB_DFU_WILL_DETACH, + .wDetachTimeout = 255, + .wTransferSize = 1024, + .bcdDFUVersion = 0x011A, +}; + +const struct usb_interface_descriptor dfu_iface = { + .bLength = USB_DT_INTERFACE_SIZE, + .bDescriptorType = USB_DT_INTERFACE, + .bInterfaceNumber = 1, + .bAlternateSetting = 0, + .bNumEndpoints = 0, + .bInterfaceClass = 0xFE, + .bInterfaceSubClass = 1, + .bInterfaceProtocol = 1, + .iInterface = 0, + + .extra = &dfu_function, + .extralen = sizeof(dfu_function), +}; +#endif + +const struct usb_interface ifaces[] = {{ + .num_altsetting = 1, + .altsetting = &hid_iface, +#ifdef INCLUDE_DFU_INTERFACE +}, { + .num_altsetting = 1, + .altsetting = &dfu_iface, +#endif +}}; + +const struct usb_config_descriptor config = { + .bLength = USB_DT_CONFIGURATION_SIZE, + .bDescriptorType = USB_DT_CONFIGURATION, + .wTotalLength = 0, +#ifdef INCLUDE_DFU_INTERFACE + .bNumInterfaces = 2, +#else + .bNumInterfaces = 1, +#endif + .bConfigurationValue = 1, + .iConfiguration = 0, + .bmAttributes = 0xC0, + .bMaxPower = 0x32, + + .interface = ifaces, +}; + +static const char *usb_strings[] = { + "x", + "Black Sphere Technologies", + "HID Demo", + "DEMO", +}; + +static int hid_control_request(struct usb_setup_data *req, u8 **buf, u16 *len, + void (**complete)(struct usb_setup_data *req)) +{ + (void)complete; + + if((req->bmRequestType != 0x81) || + (req->bRequest != USB_REQ_GET_DESCRIPTOR) || + (req->wValue != 0x2200)) + return 0; + + /* Handle the HID report descriptor */ + *buf = (u8*)hid_report_descriptor; + *len = sizeof(hid_report_descriptor); + + return 1; +} + +#ifdef INCLUDE_DFU_INTERFACE +static void dfu_detach_complete(struct usb_setup_data *req) +{ + (void)req; + + gpio_set_mode(GPIOA, GPIO_MODE_INPUT, 0, GPIO15); + gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_2_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO10); + gpio_set(GPIOA, GPIO10); + scb_reset_core(); +} + +static int dfu_control_request(struct usb_setup_data *req, u8 **buf, u16 *len, + void (**complete)(struct usb_setup_data *req)) +{ + (void)buf; + (void)len; + + if((req->bmRequestType != 0x21) || (req->bRequest != DFU_DETACH)) + return 0; /* Only accept class request */ + + *complete = dfu_detach_complete; + + return 1; +} +#endif + +static void hid_set_config(u16 wValue) +{ + (void)wValue; + + usbd_ep_setup(0x81, USB_ENDPOINT_ATTR_INTERRUPT, 4, NULL); + + usbd_register_control_callback( + USB_REQ_TYPE_STANDARD | USB_REQ_TYPE_INTERFACE, + USB_REQ_TYPE_TYPE | USB_REQ_TYPE_RECIPIENT, + hid_control_request); +#ifdef INCLUDE_DFU_INTERFACE + usbd_register_control_callback( + USB_REQ_TYPE_CLASS | USB_REQ_TYPE_INTERFACE, + USB_REQ_TYPE_TYPE | USB_REQ_TYPE_RECIPIENT, + dfu_control_request); +#endif + + systick_set_clocksource(STK_CTRL_CLKSOURCE_AHB_DIV8); + systick_set_reload(100000); + systick_interrupt_enable(); + systick_counter_enable(); +} + +int main(void) +{ + rcc_clock_setup_in_hsi_out_48mhz(); + + + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); + + gpio_set(GPIOC, GPIO11); + gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_2_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO11); + + usbd_init(&stm32f103_usb_driver, &dev, &config, usb_strings); + usbd_register_set_config_callback(hid_set_config); + + {int i; for (i=0;i<0x80000;i++);} + gpio_clear(GPIOC, GPIO11); + + while (1) + usbd_poll(); +} + +void sys_tick_handler(void) +{ + static int x = 0; + static int dir = 1; + u8 buf[4] = {0, 0, 0, 0}; + + buf[1] = dir; + x += dir; + if(x > 30) dir = -dir; + if(x < -30) dir = -dir; + + usbd_ep_write_packet(0x81, buf, 4); +} diff --git a/examples/stm32f1/stm32-h103/usb_hid/usbhid.ld b/examples/stm32f1/stm32-h103/usb_hid/usbhid.ld new file mode 100644 index 0000000..928c898 --- /dev/null +++ b/examples/stm32f1/stm32-h103/usb_hid/usbhid.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Linker script for Olimex STM32-H103 (STM32F103RBT6, 128K flash, 20K RAM). */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32.ld + diff --git a/examples/stm32f1/stm32-h103/usb_iap/Makefile b/examples/stm32f1/stm32-h103/usb_iap/Makefile new file mode 100644 index 0000000..bed9908 --- /dev/null +++ b/examples/stm32f1/stm32-h103/usb_iap/Makefile @@ -0,0 +1,23 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +## + +BINARY = usbiap + +include ../../Makefile.include + diff --git a/examples/stm32f1/stm32-h103/usb_iap/README b/examples/stm32f1/stm32-h103/usb_iap/README new file mode 100644 index 0000000..2966684 --- /dev/null +++ b/examples/stm32f1/stm32-h103/usb_iap/README @@ -0,0 +1,8 @@ +------------------------------------------------------------------------------ +README +------------------------------------------------------------------------------ + +This example implements a USB bootloader for the Paparazzi project. + +TODO: Move to examples/lisa-m? + diff --git a/examples/stm32f1/stm32-h103/usb_iap/usbiap.c b/examples/stm32f1/stm32-h103/usb_iap/usbiap.c new file mode 100644 index 0000000..7ffbc74 --- /dev/null +++ b/examples/stm32f1/stm32-h103/usb_iap/usbiap.c @@ -0,0 +1,270 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Gareth McMullin + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include +#include +#include + +#define APP_ADDRESS 0x08002000 + +/* Commands sent with wBlockNum == 0 as per ST implementation. */ +#define CMD_SETADDR 0x21 +#define CMD_ERASE 0x41 + +/* We need a special large control buffer for this device: */ +u8 usbd_control_buffer[1024]; + +static enum dfu_state usbdfu_state = STATE_DFU_IDLE; + +static struct { + u8 buf[sizeof(usbd_control_buffer)]; + u16 len; + u32 addr; + u16 blocknum; +} prog; + +const struct usb_device_descriptor dev = { + .bLength = USB_DT_DEVICE_SIZE, + .bDescriptorType = USB_DT_DEVICE, + .bcdUSB = 0x0200, + .bDeviceClass = 0, + .bDeviceSubClass = 0, + .bDeviceProtocol = 0, + .bMaxPacketSize0 = 64, + .idVendor = 0x0483, + .idProduct = 0xDF11, + .bcdDevice = 0x0200, + .iManufacturer = 1, + .iProduct = 2, + .iSerialNumber = 3, + .bNumConfigurations = 1, +}; + +const struct usb_dfu_descriptor dfu_function = { + .bLength = sizeof(struct usb_dfu_descriptor), + .bDescriptorType = DFU_FUNCTIONAL, + .bmAttributes = USB_DFU_CAN_DOWNLOAD | USB_DFU_WILL_DETACH, + .wDetachTimeout = 255, + .wTransferSize = 1024, + .bcdDFUVersion = 0x011A, +}; + +const struct usb_interface_descriptor iface = { + .bLength = USB_DT_INTERFACE_SIZE, + .bDescriptorType = USB_DT_INTERFACE, + .bInterfaceNumber = 0, + .bAlternateSetting = 0, + .bNumEndpoints = 0, + .bInterfaceClass = 0xFE, /* Device Firmware Upgrade */ + .bInterfaceSubClass = 1, + .bInterfaceProtocol = 2, + + /* The ST Microelectronics DfuSe application needs this string. + * The format isn't documented... */ + .iInterface = 4, + + .extra = &dfu_function, + .extralen = sizeof(dfu_function), +}; + +const struct usb_interface ifaces[] = {{ + .num_altsetting = 1, + .altsetting = &iface, +}}; + +const struct usb_config_descriptor config = { + .bLength = USB_DT_CONFIGURATION_SIZE, + .bDescriptorType = USB_DT_CONFIGURATION, + .wTotalLength = 0, + .bNumInterfaces = 1, + .bConfigurationValue = 1, + .iConfiguration = 0, + .bmAttributes = 0xC0, + .bMaxPower = 0x32, + + .interface = ifaces, +}; + +static const char *usb_strings[] = { + "x", + "Black Sphere Technologies", + "DFU Demo", + "DEMO", + /* This string is used by ST Microelectronics' DfuSe utility */ + "@Internal Flash /0x08000000/8*001Ka,56*001Kg" +}; + +static u8 usbdfu_getstatus(u32 *bwPollTimeout) +{ + switch(usbdfu_state) { + case STATE_DFU_DNLOAD_SYNC: + usbdfu_state = STATE_DFU_DNBUSY; + *bwPollTimeout = 100; + return DFU_STATUS_OK; + + case STATE_DFU_MANIFEST_SYNC: + /* Device will reset when read is complete */ + usbdfu_state = STATE_DFU_MANIFEST; + return DFU_STATUS_OK; + + default: + return DFU_STATUS_OK; + } +} + +static void usbdfu_getstatus_complete(struct usb_setup_data *req) +{ + int i; + (void)req; + + switch(usbdfu_state) { + case STATE_DFU_DNBUSY: + + flash_unlock(); + if(prog.blocknum == 0) { + switch(prog.buf[0]) { + case CMD_ERASE: + flash_erase_page(*(u32*)(prog.buf+1)); + case CMD_SETADDR: + prog.addr = *(u32*)(prog.buf+1); + } + } else { + u32 baseaddr = prog.addr + + ((prog.blocknum - 2) * + dfu_function.wTransferSize); + for(i = 0; i < prog.len; i += 2) + flash_program_half_word(baseaddr + i, + *(u16*)(prog.buf+i)); + } + flash_lock(); + + /* We jump straight to dfuDNLOAD-IDLE, + * skipping dfuDNLOAD-SYNC + */ + usbdfu_state = STATE_DFU_DNLOAD_IDLE; + return; + + case STATE_DFU_MANIFEST: + /* USB device must detach, we just reset... */ + scb_reset_system(); + return; /* Will never return */ + default: + return; + } +} + +static int usbdfu_control_request(struct usb_setup_data *req, u8 **buf, + u16 *len, void (**complete)(struct usb_setup_data *req)) +{ + + if((req->bmRequestType & 0x7F) != 0x21) + return 0; /* Only accept class request */ + + switch(req->bRequest) { + case DFU_DNLOAD: + if((len == NULL) || (*len == 0)) { + usbdfu_state = STATE_DFU_MANIFEST_SYNC; + return 1; + } else { + /* Copy download data for use on GET_STATUS */ + prog.blocknum = req->wValue; + prog.len = *len; + memcpy(prog.buf, *buf, *len); + usbdfu_state = STATE_DFU_DNLOAD_SYNC; + return 1; + } + case DFU_CLRSTATUS: + /* Clear error and return to dfuIDLE */ + if(usbdfu_state == STATE_DFU_ERROR) + usbdfu_state = STATE_DFU_IDLE; + return 1; + case DFU_ABORT: + /* Abort returns to dfuIDLE state */ + usbdfu_state = STATE_DFU_IDLE; + return 1; + case DFU_UPLOAD: + /* Upload not supported for now */ + return 0; + case DFU_GETSTATUS: { + u32 bwPollTimeout = 0; /* 24-bit integer in DFU class spec */ + + (*buf)[0] = usbdfu_getstatus(&bwPollTimeout); + (*buf)[1] = bwPollTimeout & 0xFF; + (*buf)[2] = (bwPollTimeout >> 8) & 0xFF; + (*buf)[3] = (bwPollTimeout >> 16) & 0xFF; + (*buf)[4] = usbdfu_state; + (*buf)[5] = 0; /* iString not used here */ + *len = 6; + + *complete = usbdfu_getstatus_complete; + + return 1; + } + case DFU_GETSTATE: + /* Return state with no state transision */ + *buf[0] = usbdfu_state; + *len = 1; + return 1; + } + + return 0; +} + +int main(void) +{ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); + if(!gpio_get(GPIOA, GPIO10)) { + /* Boot the application if it's valid */ + if((*(volatile u32*)APP_ADDRESS & 0x2FFE0000) == 0x20000000) { + /* Set vector table base address */ + SCB_VTOR = APP_ADDRESS & 0xFFFF; + /* Initialise master stack pointer */ + asm volatile ("msr msp, %0"::"g" + (*(volatile u32*)APP_ADDRESS)); + /* Jump to application */ + (*(void(**)())(APP_ADDRESS + 4))(); + } + } + + rcc_clock_setup_in_hsi_out_48mhz(); + + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_AFIOEN); + + AFIO_MAPR |= AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_ON; + gpio_set_mode(GPIOA, GPIO_MODE_INPUT, 0, GPIO15); + + usbd_init(&stm32f103_usb_driver, &dev, &config, usb_strings); + usbd_set_control_buffer_size(sizeof(usbd_control_buffer)); + usbd_register_control_callback( + USB_REQ_TYPE_CLASS | USB_REQ_TYPE_INTERFACE, + USB_REQ_TYPE_TYPE | USB_REQ_TYPE_RECIPIENT, + usbdfu_control_request); + + gpio_set(GPIOA, GPIO15); + gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_2_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO15); + + while (1) + usbd_poll(); +} diff --git a/examples/stm32f1/stm32-h103/usb_iap/usbiap.ld b/examples/stm32f1/stm32-h103/usb_iap/usbiap.ld new file mode 100644 index 0000000..928c898 --- /dev/null +++ b/examples/stm32f1/stm32-h103/usb_iap/usbiap.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Linker script for Olimex STM32-H103 (STM32F103RBT6, 128K flash, 20K RAM). */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32.ld + diff --git a/examples/stm32f1/stm32-h107/fancyblink/Makefile b/examples/stm32f1/stm32-h107/fancyblink/Makefile new file mode 100644 index 0000000..1baec4d --- /dev/null +++ b/examples/stm32f1/stm32-h107/fancyblink/Makefile @@ -0,0 +1,23 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +## + +BINARY = fancyblink + +include ../../Makefile.include + diff --git a/examples/stm32f1/stm32-h107/fancyblink/README b/examples/stm32f1/stm32-h107/fancyblink/README new file mode 100644 index 0000000..6f1ac39 --- /dev/null +++ b/examples/stm32f1/stm32-h107/fancyblink/README @@ -0,0 +1,10 @@ +------------------------------------------------------------------------------ +README +------------------------------------------------------------------------------ + +This is small LED blinking example program using libopencm3. + +It's intended for the ST STM32-based Olimex STM32-H107 eval board (see +http://olimex.com/dev/stm32-h107.html for details). It should blink +the LED on the board. + diff --git a/examples/stm32f1/stm32-h107/fancyblink/fancyblink.c b/examples/stm32f1/stm32-h107/fancyblink/fancyblink.c new file mode 100644 index 0000000..c73d3d4 --- /dev/null +++ b/examples/stm32f1/stm32-h107/fancyblink/fancyblink.c @@ -0,0 +1,58 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * Copyright (c) 2011 Damjan Marion + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include + +/* Set STM32 to 72 MHz. */ +void clock_setup(void) +{ + rcc_clock_setup_in_hse_8mhz_out_72mhz(); + + /* Enable GPIOC clock. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); +} + +void gpio_setup(void) +{ + /* Set GPIO6/7 (in GPIO port C) to 'output push-pull'. */ + gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO6); + gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO7); +} + +int main(void) +{ + int i; + + clock_setup(); + gpio_setup(); + + /* Blink the LEDs (PC6 and PC7) on the board. */ + while (1) { + gpio_toggle(GPIOC, GPIO6); /* STAT1 LED on/off */ + gpio_toggle(GPIOC, GPIO7); /* STAT2 LED on/off */ + for (i = 0; i < 8000000; i++) /* Wait a bit. */ + __asm__("nop"); + } + + return 0; +} diff --git a/examples/stm32f1/stm32-h107/fancyblink/fancyblink.ld b/examples/stm32f1/stm32-h107/fancyblink/fancyblink.ld new file mode 100644 index 0000000..6c9c766 --- /dev/null +++ b/examples/stm32f1/stm32-h107/fancyblink/fancyblink.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Linker script for Olimex STM32-H107 (STM32F107VCT6, 256K flash, 64K RAM). */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 256K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32.ld + diff --git a/examples/stm32f1/stm32-h107/usb_simple/Makefile b/examples/stm32f1/stm32-h107/usb_simple/Makefile new file mode 100644 index 0000000..2d954e2 --- /dev/null +++ b/examples/stm32f1/stm32-h107/usb_simple/Makefile @@ -0,0 +1,23 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +## + +BINARY = usb_simple + +include ../../Makefile.include + diff --git a/examples/stm32f1/stm32-h107/usb_simple/README b/examples/stm32f1/stm32-h107/usb_simple/README new file mode 100644 index 0000000..93d4f03 --- /dev/null +++ b/examples/stm32f1/stm32-h107/usb_simple/README @@ -0,0 +1,10 @@ +------------------------------------------------------------------------------ +README +------------------------------------------------------------------------------ + +This is small USB controlled LED blinking example program using libopencm3. + +It's intended for the ST STM32-based Olimex STM32-H107 eval board (see +http://olimex.com/dev/stm32-h107.html for details). The usbtest.py +script in this directory maybe used to control the LED. + diff --git a/examples/stm32f1/stm32-h107/usb_simple/usb_simple.c b/examples/stm32f1/stm32-h107/usb_simple/usb_simple.c new file mode 100644 index 0000000..85f67df --- /dev/null +++ b/examples/stm32f1/stm32-h107/usb_simple/usb_simple.c @@ -0,0 +1,117 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Gareth McMullin + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include + +#include + +const struct usb_device_descriptor dev = { + .bLength = USB_DT_DEVICE_SIZE, + .bDescriptorType = USB_DT_DEVICE, + .bcdUSB = 0x0200, + .bDeviceClass = 0xFF, + .bDeviceSubClass = 0, + .bDeviceProtocol = 0, + .bMaxPacketSize0 = 64, + .idVendor = 0xCAFE, + .idProduct = 0xCAFE, + .bcdDevice = 0x0200, + .iManufacturer = 1, + .iProduct = 2, + .iSerialNumber = 3, + .bNumConfigurations = 1, +}; + +const struct usb_interface_descriptor iface = { + .bLength = USB_DT_INTERFACE_SIZE, + .bDescriptorType = USB_DT_INTERFACE, + .bInterfaceNumber = 0, + .bAlternateSetting = 0, + .bNumEndpoints = 0, + .bInterfaceClass = 0xFF, + .bInterfaceSubClass = 0, + .bInterfaceProtocol = 0, + .iInterface = 0, +}; + +const struct usb_interface ifaces[] = {{ + .num_altsetting = 1, + .altsetting = &iface, +}}; + +const struct usb_config_descriptor config = { + .bLength = USB_DT_CONFIGURATION_SIZE, + .bDescriptorType = USB_DT_CONFIGURATION, + .wTotalLength = 0, + .bNumInterfaces = 1, + .bConfigurationValue = 1, + .iConfiguration = 0, + .bmAttributes = 0x80, + .bMaxPower = 0x32, + + .interface = ifaces, +}; + +const char *usb_strings[] = { + "x", + "Black Sphere Technologies", + "Simple Device", + "1001" +}; + +static int simple_control_callback(struct usb_setup_data *req, u8 **buf, + u16 *len, void (**complete)(struct usb_setup_data *req)) +{ + (void)buf; + (void)len; + (void)complete; + + if(req->bmRequestType != 0x40) + return 0; /* Only accept vendor request */ + + if(req->wValue & 1) + gpio_set(GPIOC, GPIO6); + else + gpio_clear(GPIOC, GPIO6); + + return 1; +} + +int main(void) +{ + rcc_clock_setup_in_hse_8mhz_out_72mhz(); + + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); + + /* LED output */ + gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_2_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO6); + + usbd_init(&stm32f107_usb_driver, &dev, &config, usb_strings); + usbd_register_control_callback( + USB_REQ_TYPE_VENDOR, + USB_REQ_TYPE_TYPE, + simple_control_callback); + + while (1) + usbd_poll(); +} + diff --git a/examples/stm32f1/stm32-h107/usb_simple/usb_simple.ld b/examples/stm32f1/stm32-h107/usb_simple/usb_simple.ld new file mode 100644 index 0000000..6c9c766 --- /dev/null +++ b/examples/stm32f1/stm32-h107/usb_simple/usb_simple.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Linker script for Olimex STM32-H107 (STM32F107VCT6, 256K flash, 64K RAM). */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 256K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32.ld + -- cgit v1.2.3 From 023b0a169581d2e7e640134035b505eda597dda3 Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Thu, 15 Sep 2011 02:52:37 -0700 Subject: Remove orphaned file in git. --- examples/stm32/Makefile.include | 136 ---------------------------------------- 1 file changed, 136 deletions(-) delete mode 100644 examples/stm32/Makefile.include diff --git a/examples/stm32/Makefile.include b/examples/stm32/Makefile.include deleted file mode 100644 index 3e30638..0000000 --- a/examples/stm32/Makefile.include +++ /dev/null @@ -1,136 +0,0 @@ -## -## This file is part of the libopencm3 project. -## -## Copyright (C) 2009 Uwe Hermann -## Copyright (C) 2010 Piotr Esden-Tempski -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 3 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program. If not, see . -## - -PREFIX ?= arm-none-eabi -#PREFIX ?= arm-elf -CC = $(PREFIX)-gcc -LD = $(PREFIX)-gcc -OBJCOPY = $(PREFIX)-objcopy -OBJDUMP = $(PREFIX)-objdump -GDB = $(PREFIX)-gdb -# Uncomment this line if you want to use the installed (not local) library. -# TOOLCHAIN_DIR := $(shell dirname `which $(CC)`)/../$(PREFIX) -TOOLCHAIN_DIR = ../../../.. -CFLAGS += -Os -g -Wall -Wextra -I$(TOOLCHAIN_DIR)/include \ - -fno-common -mcpu=cortex-m3 -mthumb -msoft-float -MD -LDSCRIPT = $(BINARY).ld -LDFLAGS += -lc -lnosys -L$(TOOLCHAIN_DIR)/lib -L$(TOOLCHAIN_DIR)/lib/stm32 \ - -T$(LDSCRIPT) -nostartfiles -Wl,--gc-sections \ - -mthumb -march=armv7 -mfix-cortex-m3-ldrd -msoft-float -OBJS += $(BINARY).o - -OOCD ?= openocd -OOCD_INTERFACE ?= flossjtag -OOCD_BOARD ?= olimex_stm32_h103 -# Black magic probe specific variables -# Set the BMP_PORT to a serial port and then BMP is used for flashing -BMP_PORT ?= - -# Be silent per default, but 'make V=1' will show all compiler calls. -ifneq ($(V),1) -Q := @ -NULL := 2>/dev/null -else -LDFLAGS += -Wl,--print-gc-sections -endif - -.SUFFIXES: .elf .bin .hex .srec .list .images -.SECONDEXPANSION: -.SECONDARY: - -all: images - -images: $(BINARY).images -flash: $(BINARY).flash - -%.images: %.bin %.hex %.srec %.list - @#echo "*** $* images generated ***" - -%.bin: %.elf - @#printf " OBJCOPY $(*).bin\n" - $(Q)$(OBJCOPY) -Obinary $(*).elf $(*).bin - -%.hex: %.elf - @#printf " OBJCOPY $(*).hex\n" - $(Q)$(OBJCOPY) -Oihex $(*).elf $(*).hex - -%.srec: %.elf - @#printf " OBJCOPY $(*).srec\n" - $(Q)$(OBJCOPY) -Osrec $(*).elf $(*).srec - -%.list: %.elf - @#printf " OBJDUMP $(*).list\n" - $(Q)$(OBJDUMP) -S $(*).elf > $(*).list - -%.elf: $(OBJS) $(LDSCRIPT) $(TOOLCHAIN_DIR)/lib/stm32/libopencm3_stm32.a - @#printf " LD $(subst $(shell pwd)/,,$(@))\n" - $(Q)$(LD) -o $(*).elf $(OBJS) -lopencm3_stm32 $(LDFLAGS) - -%.o: %.c Makefile - @#printf " CC $(subst $(shell pwd)/,,$(@))\n" - $(Q)$(CC) $(CFLAGS) -o $@ -c $< - -clean: - $(Q)rm -f *.o - $(Q)rm -f *.d - $(Q)rm -f *.elf - $(Q)rm -f *.bin - $(Q)rm -f *.hex - $(Q)rm -f *.srec - $(Q)rm -f *.list - -ifeq ($(BMP_PORT),) -ifeq ($(OOCD_SERIAL),) -%.flash: %.hex - @printf " FLASH $<\n" - @# IMPORTANT: Don't use "resume", only "reset" will work correctly! - $(Q)$(OOCD) -f interface/$(OOCD_INTERFACE).cfg \ - -f board/$(OOCD_BOARD).cfg \ - -c "init" -c "reset init" \ - -c "stm32x mass_erase 0" \ - -c "flash write_image $(*).hex" \ - -c "reset" \ - -c "shutdown" $(NULL) -else -%.flash: %.hex - @printf " FLASH $<\n" - @# IMPORTANT: Don't use "resume", only "reset" will work correctly! - $(Q)$(OOCD) -f interface/$(OOCD_INTERFACE).cfg \ - -f board/$(OOCD_BOARD).cfg \ - -c "ft2232_serial $(OOCD_SERIAL)" \ - -c "init" -c "reset init" \ - -c "stm32x mass_erase 0" \ - -c "flash write_image $(*).hex" \ - -c "reset" \ - -c "shutdown" $(NULL) -endif -else -%.flash: %.elf - @echo " GDB $(*).elf (flash)" - $(Q)$(GDB) --batch \ - -ex 'target extended-remote $(BMP_PORT)' \ - -x $(TOOLCHAIN_DIR)/scripts/black_magic_probe_flash.scr \ - $(*).elf -endif - -.PHONY: images clean - --include $(OBJS:.o=.d) - -- cgit v1.2.3 From cadbc0145bf2eb407f24987620636f4e52b293d4 Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Thu, 15 Sep 2011 02:53:16 -0700 Subject: First F2 example working! --- examples/stm32f2/Makefile.include | 129 ++++++++++++++++++++++++ examples/stm32f2/jobygps/miniblink/Makefile | 23 +++++ examples/stm32f2/jobygps/miniblink/README | 6 ++ examples/stm32f2/jobygps/miniblink/miniblink.c | 77 ++++++++++++++ examples/stm32f2/jobygps/miniblink/miniblink.ld | 31 ++++++ 5 files changed, 266 insertions(+) create mode 100644 examples/stm32f2/Makefile.include create mode 100644 examples/stm32f2/jobygps/miniblink/Makefile create mode 100644 examples/stm32f2/jobygps/miniblink/README create mode 100644 examples/stm32f2/jobygps/miniblink/miniblink.c create mode 100644 examples/stm32f2/jobygps/miniblink/miniblink.ld diff --git a/examples/stm32f2/Makefile.include b/examples/stm32f2/Makefile.include new file mode 100644 index 0000000..6ec9f65 --- /dev/null +++ b/examples/stm32f2/Makefile.include @@ -0,0 +1,129 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## Copyright (C) 2010 Piotr Esden-Tempski +## Copyright (C) 2011 Fergus Noble +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +## + +PREFIX ?= arm-none-eabi +#PREFIX ?= arm-elf +CC = $(PREFIX)-gcc +LD = $(PREFIX)-gcc +OBJCOPY = $(PREFIX)-objcopy +OBJDUMP = $(PREFIX)-objdump +# Uncomment this line if you want to use the installed (not local) library. +#TOOLCHAIN_DIR := $(shell dirname `which $(CC)`)/../$(PREFIX) +TOOLCHAIN_DIR = ../../../.. +CFLAGS += -Os -g -Wall -Wextra -I$(TOOLCHAIN_DIR)/include \ + -fno-common -mcpu=cortex-m3 -mthumb -msoft-float -MD -DSTM32F2 +LDSCRIPT = $(BINARY).ld +LDFLAGS += -lc -lnosys -L$(TOOLCHAIN_DIR)/lib \ + -L$(TOOLCHAIN_DIR)/lib/stm32f2 \ + -T$(LDSCRIPT) -nostartfiles -Wl,--gc-sections \ + -mthumb -march=armv7 -mfix-cortex-m3-ldrd -msoft-float +OBJS += $(BINARY).o + +OOCD ?= openocd +OOCD_INTERFACE ?= flossjtag +OOCD_BOARD ?= olimex_stm32_h103 + +# Be silent per default, but 'make V=1' will show all compiler calls. +ifneq ($(V),1) +Q := @ +NULL := 2>/dev/null +else +LDFLAGS += -Wl,--print-gc-sections +endif + +.SUFFIXES: .elf .bin .hex .srec .list .images +.SECONDEXPANSION: +.SECONDARY: + +all: images + +images: $(BINARY).images +flash: $(BINARY).flash + +%.images: %.bin %.hex %.srec %.list + @#echo "*** $* images generated ***" + +%.bin: %.elf + @#printf " OBJCOPY $(*).bin\n" + $(Q)$(OBJCOPY) -Obinary $(*).elf $(*).bin + +%.hex: %.elf + @#printf " OBJCOPY $(*).hex\n" + $(Q)$(OBJCOPY) -Oihex $(*).elf $(*).hex + +%.srec: %.elf + @#printf " OBJCOPY $(*).srec\n" + $(Q)$(OBJCOPY) -Osrec $(*).elf $(*).srec + +%.list: %.elf + @#printf " OBJDUMP $(*).list\n" + $(Q)$(OBJDUMP) -S $(*).elf > $(*).list + +foo.elf: $(OBJS) $(LDSCRIPT) $(TOOLCHAIN_DIR)/lib/stm32f2/libopencm3_stm32f2.a + @#printf " LD $(subst $(shell pwd)/,,$(@))\n" + $(Q)$(LD) -o foo.elf $(OBJS) -lopencm3_stm32f2 $(LDFLAGS) + +%.elf: $(OBJS) $(LDSCRIPT) $(TOOLCHAIN_DIR)/lib/stm32f2/libopencm3_stm32f2.a + @#printf " LD $(subst $(shell pwd)/,,$(@))\n" + $(Q)$(LD) -o $(*).elf $(OBJS) -lopencm3_stm32f2 $(LDFLAGS) + +%.o: %.c Makefile + @#printf " CC $(subst $(shell pwd)/,,$(@))\n" + $(Q)$(CC) $(CFLAGS) -o $@ -c $< + +clean: + $(Q)rm -f *.o + $(Q)rm -f *.d + $(Q)rm -f *.elf + $(Q)rm -f *.bin + $(Q)rm -f *.hex + $(Q)rm -f *.srec + $(Q)rm -f *.list + +ifeq ($(OOCD_SERIAL),) +%.flash: %.hex + @printf " FLASH $<\n" + @# IMPORTANT: Don't use "resume", only "reset" will work correctly! + $(Q)$(OOCD) -f interface/$(OOCD_INTERFACE).cfg \ + -f board/$(OOCD_BOARD).cfg \ + -c "init" -c "reset init" \ + -c "stm32x mass_erase 0" \ + -c "flash write_image $(*).hex" \ + -c "reset" \ + -c "shutdown" $(NULL) +else +%.flash: %.hex + @printf " FLASH $<\n" + @# IMPORTANT: Don't use "resume", only "reset" will work correctly! + $(Q)$(OOCD) -f interface/$(OOCD_INTERFACE).cfg \ + -f board/$(OOCD_BOARD).cfg \ + -c "ft2232_serial $(OOCD_SERIAL)" \ + -c "init" -c "reset init" \ + -c "stm32x mass_erase 0" \ + -c "flash write_image $(*).hex" \ + -c "reset" \ + -c "shutdown" $(NULL) +endif + +.PHONY: images clean + +-include $(OBJS:.o=.d) + diff --git a/examples/stm32f2/jobygps/miniblink/Makefile b/examples/stm32f2/jobygps/miniblink/Makefile new file mode 100644 index 0000000..24a478b --- /dev/null +++ b/examples/stm32f2/jobygps/miniblink/Makefile @@ -0,0 +1,23 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +## + +BINARY = miniblink + +include ../../Makefile.include + diff --git a/examples/stm32f2/jobygps/miniblink/README b/examples/stm32f2/jobygps/miniblink/README new file mode 100644 index 0000000..0130112 --- /dev/null +++ b/examples/stm32f2/jobygps/miniblink/README @@ -0,0 +1,6 @@ +------------------------------------------------------------------------------ +README +------------------------------------------------------------------------------ + +This is the smallest-possible example program using libopencm3. + diff --git a/examples/stm32f2/jobygps/miniblink/miniblink.c b/examples/stm32f2/jobygps/miniblink/miniblink.c new file mode 100644 index 0000000..2927df5 --- /dev/null +++ b/examples/stm32f2/jobygps/miniblink/miniblink.c @@ -0,0 +1,77 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +//#include +#include + +void gpio_setup(void) +{ + /* Enable GPIOC clock. */ + /* Manually: */ + // RCC_APB2ENR |= RCC_APB2ENR_IOPCEN; + /* Using API functions: */ + //rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); + + /* Set GPIO12 (in GPIO port C) to 'output push-pull'. */ + /* Manually: */ + // GPIOC_CRH = (GPIO_CNF_OUTPUT_PUSHPULL << (((12 - 8) * 4) + 2)); + // GPIOC_CRH |= (GPIO_MODE_OUTPUT_2_MHZ << ((12 - 8) * 4)); + /* Using API functions: */ + MMIO32(RCC_BASE+0x30) |= (1<<2); + gpio_mode_setup(GPIOC, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO3|GPIO4); +} + +int main(void) +{ + int i; + + gpio_setup(); + + /* Blink the LED (PC12) on the board. */ + while (1) { + /* Manually: */ + // GPIOC_BSRR = GPIO12; /* LED off */ + // for (i = 0; i < 800000; i++) /* Wait a bit. */ + // __asm__("nop"); + // GPIOC_BRR = GPIO12; /* LED on */ + // for (i = 0; i < 800000; i++) /* Wait a bit. */ + // __asm__("nop"); + + /* Using API functions gpio_set()/gpio_clear(): */ + // gpio_set(GPIOC, GPIO12); /* LED off */ + // for (i = 0; i < 800000; i++) /* Wait a bit. */ + // __asm__("nop"); + // gpio_clear(GPIOC, GPIO12); /* LED on */ + // for (i = 0; i < 800000; i++) /* Wait a bit. */ + // __asm__("nop"); + + /* Using API function gpio_toggle(): */ + //gpio_toggle(GPIOC, GPIO3); /* LED on/off */ + gpio_set(GPIOC, GPIO3); + gpio_clear(GPIOC, GPIO4); + for (i = 0; i < 800000; i++) /* Wait a bit. */ + __asm__("nop"); + gpio_clear(GPIOC, GPIO3); + gpio_set(GPIOC, GPIO4); + for (i = 0; i < 800000; i++) /* Wait a bit. */ + __asm__("nop"); + } + + return 0; +} diff --git a/examples/stm32f2/jobygps/miniblink/miniblink.ld b/examples/stm32f2/jobygps/miniblink/miniblink.ld new file mode 100644 index 0000000..cfe9ab7 --- /dev/null +++ b/examples/stm32f2/jobygps/miniblink/miniblink.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Linker script for Olimex STM32-H103 (STM32F103RBT6, 128K flash, 20K RAM). */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 256K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32f2.ld + -- cgit v1.2.3 From ca412a9ed2ab3bf5f4bdf54b7b300290931ab39b Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Thu, 15 Sep 2011 14:59:55 -0700 Subject: Move systick to stm32 common. --- include/libopencm3/stm32/f1/systick.h | 82 ----------------------------------- include/libopencm3/stm32/systick.h | 82 +++++++++++++++++++++++++++++++++++ lib/stm32_common/systick.c | 64 +++++++++++++++++++++++++++ lib/stm32f1/Makefile | 2 +- lib/stm32f1/systick.c | 64 --------------------------- lib/stm32f2/Makefile | 3 +- 6 files changed, 149 insertions(+), 148 deletions(-) delete mode 100644 include/libopencm3/stm32/f1/systick.h create mode 100644 include/libopencm3/stm32/systick.h create mode 100644 lib/stm32_common/systick.c delete mode 100644 lib/stm32f1/systick.c diff --git a/include/libopencm3/stm32/f1/systick.h b/include/libopencm3/stm32/f1/systick.h deleted file mode 100644 index 7c2c9a3..0000000 --- a/include/libopencm3/stm32/f1/systick.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_SYSTICK_H -#define LIBOPENCM3_SYSTICK_H - -#include -#include - -/* --- SYSTICK registers --------------------------------------------------- */ - -/* Control and status register (STK_CTRL) */ -#define STK_CTRL MMIO32(SYS_TICK_BASE + 0x00) - -/* reload value register (STK_LOAD) */ -#define STK_LOAD MMIO32(SYS_TICK_BASE + 0x04) - -/* current value register (STK_VAL) */ -#define STK_VAL MMIO32(SYS_TICK_BASE + 0x08) - -/* calibration value register (STK_CALIB) */ -#define STK_CALIB MMIO32(SYS_TICK_BASE + 0x0C) - -/* --- STK_CTRL values ----------------------------------------------------- */ -/* Bits [31:17] Reserved, must be kept cleared. */ -/* COUNTFLAG: */ -#define STK_CTRL_COUNTFLAG (1 << 16) -/* Bits [15:3] Reserved, must be kept cleared. */ -/* CLKSOURCE: Clock source selection */ -#define STK_CTRL_CLKSOURCE (1 << 2) -#define STK_CTRL_CLKSOURCE_LSB 2 -#define STK_CTRL_CLKSOURCE_AHB_DIV8 0 -#define STK_CTRL_CLKSOURCE_AHB 1 -/* TICKINT: SysTick exception request enable */ -#define STK_CTRL_TICKINT (1 << 1) -/* ENABLE: Counter enable */ -#define STK_CTRL_ENABLE (1 << 0) - -/* --- STK_LOAD values ----------------------------------------------------- */ -/* Bits [31:24] Reserved, must be kept cleared. */ -/* RELOAD[23:0]: RELOAD value */ - -/* --- STK_VAL values ------------------------------------------------------ */ -/* Bits [31:24] Reserved, must be kept cleared. */ -/* CURRENT[23:0]: Current counter value */ - -/* --- STK_CALIB values ---------------------------------------------------- */ -/* NOREF: NOREF flag */ -#define STK_CALIB_NOREF (1 << 31) -/* SKEW: SKEW flag */ -#define STK_CALIB_SKEW (1 << 30) -/* Bits [29:24] Reserved, must be kept cleared. */ -/* TENMS[23:0]: Calibration value */ - -/* --- Function Prototypes ------------------------------------------------- */ - -void systick_set_reload(u32 value); -u32 systick_get_value(void); -void systick_set_clocksource(u8 clocksource); -void systick_interrupt_enable(void); -void systick_interrupt_disable(void); -void systick_counter_enable(void); -void systick_counter_disable(void); -u8 systick_get_countflag(void); - -#endif diff --git a/include/libopencm3/stm32/systick.h b/include/libopencm3/stm32/systick.h new file mode 100644 index 0000000..7c2c9a3 --- /dev/null +++ b/include/libopencm3/stm32/systick.h @@ -0,0 +1,82 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_SYSTICK_H +#define LIBOPENCM3_SYSTICK_H + +#include +#include + +/* --- SYSTICK registers --------------------------------------------------- */ + +/* Control and status register (STK_CTRL) */ +#define STK_CTRL MMIO32(SYS_TICK_BASE + 0x00) + +/* reload value register (STK_LOAD) */ +#define STK_LOAD MMIO32(SYS_TICK_BASE + 0x04) + +/* current value register (STK_VAL) */ +#define STK_VAL MMIO32(SYS_TICK_BASE + 0x08) + +/* calibration value register (STK_CALIB) */ +#define STK_CALIB MMIO32(SYS_TICK_BASE + 0x0C) + +/* --- STK_CTRL values ----------------------------------------------------- */ +/* Bits [31:17] Reserved, must be kept cleared. */ +/* COUNTFLAG: */ +#define STK_CTRL_COUNTFLAG (1 << 16) +/* Bits [15:3] Reserved, must be kept cleared. */ +/* CLKSOURCE: Clock source selection */ +#define STK_CTRL_CLKSOURCE (1 << 2) +#define STK_CTRL_CLKSOURCE_LSB 2 +#define STK_CTRL_CLKSOURCE_AHB_DIV8 0 +#define STK_CTRL_CLKSOURCE_AHB 1 +/* TICKINT: SysTick exception request enable */ +#define STK_CTRL_TICKINT (1 << 1) +/* ENABLE: Counter enable */ +#define STK_CTRL_ENABLE (1 << 0) + +/* --- STK_LOAD values ----------------------------------------------------- */ +/* Bits [31:24] Reserved, must be kept cleared. */ +/* RELOAD[23:0]: RELOAD value */ + +/* --- STK_VAL values ------------------------------------------------------ */ +/* Bits [31:24] Reserved, must be kept cleared. */ +/* CURRENT[23:0]: Current counter value */ + +/* --- STK_CALIB values ---------------------------------------------------- */ +/* NOREF: NOREF flag */ +#define STK_CALIB_NOREF (1 << 31) +/* SKEW: SKEW flag */ +#define STK_CALIB_SKEW (1 << 30) +/* Bits [29:24] Reserved, must be kept cleared. */ +/* TENMS[23:0]: Calibration value */ + +/* --- Function Prototypes ------------------------------------------------- */ + +void systick_set_reload(u32 value); +u32 systick_get_value(void); +void systick_set_clocksource(u8 clocksource); +void systick_interrupt_enable(void); +void systick_interrupt_disable(void); +void systick_counter_enable(void); +void systick_counter_disable(void); +u8 systick_get_countflag(void); + +#endif diff --git a/lib/stm32_common/systick.c b/lib/stm32_common/systick.c new file mode 100644 index 0000000..882601d --- /dev/null +++ b/lib/stm32_common/systick.c @@ -0,0 +1,64 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include + +void systick_set_reload(u32 value) +{ + STK_LOAD = (value & 0x00FFFFFF); +} + +u32 systick_get_value(void) +{ + return STK_VAL; +} + +void systick_set_clocksource(u8 clocksource) +{ + if (clocksource < 2) + STK_CTRL |= (clocksource << STK_CTRL_CLKSOURCE_LSB); +} + +void systick_interrupt_enable(void) +{ + STK_CTRL |= STK_CTRL_TICKINT; +} + +void systick_interrupt_disable(void) +{ + STK_CTRL &= ~STK_CTRL_TICKINT; +} + +void systick_counter_enable(void) +{ + STK_CTRL |= STK_CTRL_ENABLE; +} + +void systick_counter_disable(void) +{ + STK_CTRL &= ~STK_CTRL_ENABLE; +} + +u8 systick_get_countflag(void) +{ + if (STK_CTRL & STK_CTRL_COUNTFLAG) + return 1; + else + return 0; +} diff --git a/lib/stm32f1/Makefile b/lib/stm32f1/Makefile index fa4dad1..bd9fca2 100644 --- a/lib/stm32f1/Makefile +++ b/lib/stm32f1/Makefile @@ -33,7 +33,7 @@ OBJS = vector.o rcc.o gpio.o usart.o adc.o spi.o flash.o nvic.o \ usb_f103.o usb.o usb_control.o usb_standard.o can.o \ timer.o usb_f107.o -VPATH += ../usb +VPATH += ../usb:../stm32_common # Be silent per default, but 'make V=1' will show all compiler calls. ifneq ($(V),1) diff --git a/lib/stm32f1/systick.c b/lib/stm32f1/systick.c deleted file mode 100644 index 3308413..0000000 --- a/lib/stm32f1/systick.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include - -void systick_set_reload(u32 value) -{ - STK_LOAD = (value & 0x00FFFFFF); -} - -u32 systick_get_value(void) -{ - return STK_VAL; -} - -void systick_set_clocksource(u8 clocksource) -{ - if (clocksource < 2) - STK_CTRL |= (clocksource << STK_CTRL_CLKSOURCE_LSB); -} - -void systick_interrupt_enable(void) -{ - STK_CTRL |= STK_CTRL_TICKINT; -} - -void systick_interrupt_disable(void) -{ - STK_CTRL &= ~STK_CTRL_TICKINT; -} - -void systick_counter_enable(void) -{ - STK_CTRL |= STK_CTRL_ENABLE; -} - -void systick_counter_disable(void) -{ - STK_CTRL &= ~STK_CTRL_ENABLE; -} - -u8 systick_get_countflag(void) -{ - if (STK_CTRL & STK_CTRL_COUNTFLAG) - return 1; - else - return 0; -} diff --git a/lib/stm32f2/Makefile b/lib/stm32f2/Makefile index 1f08089..d52525b 100644 --- a/lib/stm32f2/Makefile +++ b/lib/stm32f2/Makefile @@ -28,9 +28,10 @@ CFLAGS = -Os -g -Wall -Wextra -I../../include -fno-common \ -ffunction-sections -fdata-sections -MD -DSTM32F2 # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = vector.o gpio.o +OBJS = vector.o gpio.o systick.o #VPATH += ../usb +VPATH += ../stm32_common # Be silent per default, but 'make V=1' will show all compiler calls. ifneq ($(V),1) -- cgit v1.2.3 From 72baa300ab82c184e156e170cae0dcd1fd665d12 Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Thu, 15 Sep 2011 15:06:28 -0700 Subject: Moved I2C to stm32 common. --- lib/stm32_common/i2c.c | 93 ++++++++++++++++++++++++++++++++++++++++++++++++++ lib/stm32f1/i2c.c | 93 -------------------------------------------------- lib/stm32f2/Makefile | 2 +- 3 files changed, 94 insertions(+), 94 deletions(-) create mode 100644 lib/stm32_common/i2c.c delete mode 100644 lib/stm32f1/i2c.c diff --git a/lib/stm32_common/i2c.c b/lib/stm32_common/i2c.c new file mode 100644 index 0000000..e1a3b84 --- /dev/null +++ b/lib/stm32_common/i2c.c @@ -0,0 +1,93 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include + +void i2c_peripheral_enable(u32 i2c) +{ + I2C_CR1(i2c) |= I2C_CR1_PE; +} + +void i2c_peripheral_disable(u32 i2c) +{ + I2C_CR1(i2c) &= ~I2C_CR1_PE; +} + +void i2c_send_start(u32 i2c) +{ + I2C_CR1(i2c) |= I2C_CR1_START; +} + +void i2c_send_stop(u32 i2c) +{ + I2C_CR1(i2c) |= I2C_CR1_STOP; +} + +void i2c_set_own_7bit_slave_address(u32 i2c, u8 slave) +{ + I2C_OAR1(i2c) = (u16)(slave << 1); + I2C_OAR1(i2c) &= ~I2C_OAR1_ADDMODE; + I2C_OAR1(i2c) |= (1 << 14); /* Datasheet: always keep 1 by software. */ +} + +void i2c_set_own_10bit_slave_address(u32 i2c, u16 slave) +{ + I2C_OAR1(i2c) = (u16)(I2C_OAR1_ADDMODE | slave); +} + +void i2c_set_fast_mode(u32 i2c) +{ + I2C_CCR(i2c) |= I2C_CCR_FS; +} + +void i2c_set_standard_mode(u32 i2c) +{ + I2C_CCR(i2c) &= ~I2C_CCR_FS; +} + +void i2c_set_clock_frequency(u32 i2c, u8 freq) +{ + u16 reg16; + reg16 = I2C_CR2(i2c) & 0xffc0; /* Clear bits [5:0]. */ + reg16 |= freq; + I2C_CR2(i2c) = reg16; +} + +void i2c_set_ccr(u32 i2c, u16 freq) +{ + u16 reg16; + reg16 = I2C_CCR(i2c) & 0xf000; /* Clear bits [11:0]. */ + reg16 |= freq; + I2C_CCR(i2c) = reg16; +} + +void i2c_set_trise(u32 i2c, u16 trise) +{ + I2C_TRISE(i2c) = trise; +} + +void i2c_send_7bit_address(u32 i2c, u8 slave, u8 readwrite) +{ + I2C_DR(i2c) = (u8)((slave << 1) | readwrite); +} + +void i2c_send_data(u32 i2c, u8 data) +{ + I2C_DR(i2c) = data; +} diff --git a/lib/stm32f1/i2c.c b/lib/stm32f1/i2c.c deleted file mode 100644 index e1a3b84..0000000 --- a/lib/stm32f1/i2c.c +++ /dev/null @@ -1,93 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include - -void i2c_peripheral_enable(u32 i2c) -{ - I2C_CR1(i2c) |= I2C_CR1_PE; -} - -void i2c_peripheral_disable(u32 i2c) -{ - I2C_CR1(i2c) &= ~I2C_CR1_PE; -} - -void i2c_send_start(u32 i2c) -{ - I2C_CR1(i2c) |= I2C_CR1_START; -} - -void i2c_send_stop(u32 i2c) -{ - I2C_CR1(i2c) |= I2C_CR1_STOP; -} - -void i2c_set_own_7bit_slave_address(u32 i2c, u8 slave) -{ - I2C_OAR1(i2c) = (u16)(slave << 1); - I2C_OAR1(i2c) &= ~I2C_OAR1_ADDMODE; - I2C_OAR1(i2c) |= (1 << 14); /* Datasheet: always keep 1 by software. */ -} - -void i2c_set_own_10bit_slave_address(u32 i2c, u16 slave) -{ - I2C_OAR1(i2c) = (u16)(I2C_OAR1_ADDMODE | slave); -} - -void i2c_set_fast_mode(u32 i2c) -{ - I2C_CCR(i2c) |= I2C_CCR_FS; -} - -void i2c_set_standard_mode(u32 i2c) -{ - I2C_CCR(i2c) &= ~I2C_CCR_FS; -} - -void i2c_set_clock_frequency(u32 i2c, u8 freq) -{ - u16 reg16; - reg16 = I2C_CR2(i2c) & 0xffc0; /* Clear bits [5:0]. */ - reg16 |= freq; - I2C_CR2(i2c) = reg16; -} - -void i2c_set_ccr(u32 i2c, u16 freq) -{ - u16 reg16; - reg16 = I2C_CCR(i2c) & 0xf000; /* Clear bits [11:0]. */ - reg16 |= freq; - I2C_CCR(i2c) = reg16; -} - -void i2c_set_trise(u32 i2c, u16 trise) -{ - I2C_TRISE(i2c) = trise; -} - -void i2c_send_7bit_address(u32 i2c, u8 slave, u8 readwrite) -{ - I2C_DR(i2c) = (u8)((slave << 1) | readwrite); -} - -void i2c_send_data(u32 i2c, u8 data) -{ - I2C_DR(i2c) = data; -} diff --git a/lib/stm32f2/Makefile b/lib/stm32f2/Makefile index d52525b..f3d6ff7 100644 --- a/lib/stm32f2/Makefile +++ b/lib/stm32f2/Makefile @@ -28,7 +28,7 @@ CFLAGS = -Os -g -Wall -Wextra -I../../include -fno-common \ -ffunction-sections -fdata-sections -MD -DSTM32F2 # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = vector.o gpio.o systick.o +OBJS = vector.o gpio.o systick.o i2c.o #VPATH += ../usb VPATH += ../stm32_common -- cgit v1.2.3 From 010ee532982ae8329f712967e7e3759fa432ce76 Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Thu, 15 Sep 2011 15:07:07 -0700 Subject: Moved SPI to stm32 common. --- lib/stm32_common/spi.c | 290 +++++++++++++++++++++++++++++++++++++++++++++++++ lib/stm32f1/spi.c | 290 ------------------------------------------------- lib/stm32f2/Makefile | 2 +- 3 files changed, 291 insertions(+), 291 deletions(-) create mode 100644 lib/stm32_common/spi.c delete mode 100644 lib/stm32f1/spi.c diff --git a/lib/stm32_common/spi.c b/lib/stm32_common/spi.c new file mode 100644 index 0000000..733a1bc --- /dev/null +++ b/lib/stm32_common/spi.c @@ -0,0 +1,290 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include + +/* + * SPI and I2S code. + * + * Examples: + * spi_init_master(SPI1, 1000000, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE, + * SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT, + * SPI_CR1_LSBFIRST); + * spi_write(SPI1, 0x55); // 8-bit write + * spi_write(SPI1, 0xaa88); // 16-bit write + * reg8 = spi_read(SPI1); // 8-bit read + * reg16 = spi_read(SPI1); // 16-bit read + */ + +int spi_init_master(u32 spi, u32 br, u32 cpol, u32 cpha, u32 dff, u32 lsbfirst) +{ + u32 reg32 = 0; + + reg32 |= SPI_CR1_MSTR; /* Configure SPI as master. */ + + reg32 |= br; /* Set BAUD rate bits. */ + reg32 |= cpol; /* Set CPOL value. */ + reg32 |= cpha; /* Set CPHA value. */ + reg32 |= dff; /* Set data format (8 or 16 bits). */ + reg32 |= lsbfirst; /* Set frame format (LSB- or MSB-first). */ + + /* TODO: NSS pin handling. */ + + SPI_CR1(spi) = reg32; + + return 0; /* TODO */ +} + +/* TODO: Error handling? */ +void spi_enable(u32 spi) +{ + u32 reg32; + + reg32 = SPI_CR1(spi); + reg32 |= SPI_CR1_SPE; /* Enable SPI. */ + SPI_CR1(spi) = reg32; +} + +/* TODO: Error handling? */ +void spi_disable(u32 spi) +{ + u32 reg32; + + /* TODO: Follow procedure from section 23.3.8 in the techref manual. */ + reg32 = SPI_CR1(spi); + reg32 &= ~(SPI_CR1_SPE); /* Disable SPI. */ + SPI_CR1(spi) = reg32; +} + +void spi_write(u32 spi, u16 data) +{ + /* Write data (8 or 16 bits, depending on DFF) into DR. */ + SPI_DR(spi) = data; +} + +void spi_send(u32 spi, u16 data) +{ + /* Write data (8 or 16 bits, depending on DFF) into DR. */ + SPI_DR(spi) = data; + + /* wait for transfer finished */ + while (SPI_SR(spi) & SPI_SR_BSY ) + { + } +} + +u16 spi_read(u32 spi) +{ + /* Read the data (8 or 16 bits, depending on DFF bit) from DR. */ + return SPI_DR(spi); +} + +void spi_set_bidirectional_mode(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_BIDIMODE; +} + +void spi_set_unidirectional_mode(u32 spi) +{ + SPI_CR1(spi) &= ~SPI_CR1_BIDIMODE; +} + +void spi_set_bidirectional_receive_only_mode(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_BIDIMODE; + SPI_CR1(spi) &= ~SPI_CR1_BIDIOE; +} + +void spi_set_bidirectional_transmit_only_mode(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_BIDIMODE; + SPI_CR1(spi) |= SPI_CR1_BIDIOE; +} + +void spi_enable_crc(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_CRCEN; +} + +void spi_disable_crc(u32 spi) +{ + SPI_CR1(spi) &= ~SPI_CR1_CRCEN; +} + +void spi_set_next_tx_from_buffer(u32 spi) +{ + SPI_CR1(spi) &= ~SPI_CR1_CRCNEXT; +} + +void spi_set_next_tx_from_crc(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_CRCNEXT; +} + +void spi_set_dff_8bit(u32 spi) +{ + SPI_CR1(spi) &= ~SPI_CR1_DFF; +} + +void spi_set_dff_16bit(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_DFF; +} + +void spi_set_full_duplex_mode(u32 spi) +{ + SPI_CR1(spi) &= ~SPI_CR1_RXONLY; +} + +void spi_set_receive_only_mode(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_RXONLY; +} + +void spi_disable_software_slave_management(u32 spi) +{ + SPI_CR1(spi) &= ~SPI_CR1_SSM; +} + +void spi_enable_software_slave_management(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_SSM; +} + +void spi_set_nss_high(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_SSI; +} + +void spi_set_nss_low(u32 spi) +{ + SPI_CR1(spi) &= ~SPI_CR1_SSI; +} + +void spi_send_lsb_first(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_LSBFIRST; +} + +void spi_send_msb_first(u32 spi) +{ + SPI_CR1(spi) &= ~SPI_CR1_LSBFIRST; +} + +void spi_set_baudrate_prescaler(u32 spi, u8 baudrate) +{ + u32 reg32; + + if (baudrate > 7) + return; + + reg32 = ( SPI_CR1(spi) & 0xffc7 ); /* clear bits [5:3] */ + reg32 |= (baudrate << 3); + SPI_CR1(spi) = reg32; +} + +void spi_set_master_mode(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_MSTR; +} + +void spi_set_slave_mode(u32 spi) +{ + SPI_CR1(spi) &= ~SPI_CR1_MSTR; +} + +void spi_set_clock_polarity_1(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_CPOL; +} + +void spi_set_clock_polarity_0(u32 spi) +{ + SPI_CR1(spi) &= ~SPI_CR1_CPOL; +} + +void spi_set_clock_phase_1(u32 spi) +{ + SPI_CR1(spi) |= SPI_CR1_CPHA; +} + +void spi_set_clock_phase_0(u32 spi) +{ + SPI_CR1(spi) &= ~SPI_CR1_CPHA; +} + +void spi_enable_tx_buffer_empty_interrupt(u32 spi) +{ + SPI_CR2(spi) |= SPI_CR2_TXEIE; +} + +void spi_disable_tx_buffer_empty_interrupt(u32 spi) +{ + SPI_CR2(spi) &= ~SPI_CR2_TXEIE; +} + +void spi_enable_rx_buffer_not_empty_interrupt(u32 spi) +{ + SPI_CR2(spi) |= SPI_CR2_RXNEIE; +} + +void spi_disable_rx_buffer_not_empty_interrupt(u32 spi) +{ + SPI_CR2(spi) &= ~SPI_CR2_RXNEIE; +} + +void spi_enable_error_interrupt(u32 spi) +{ + SPI_CR2(spi) |= SPI_CR2_ERRIE; +} + +void spi_disable_error_interrupt(u32 spi) +{ + SPI_CR2(spi) &= ~SPI_CR2_ERRIE; +} + +void spi_enable_ss_output(u32 spi) +{ + SPI_CR2(spi) |= SPI_CR2_SSOE; +} + +void spi_disable_ss_output(u32 spi) +{ + SPI_CR2(spi) &= ~SPI_CR2_SSOE; +} + +void spi_enable_tx_dma(u32 spi) +{ + SPI_CR2(spi) |= SPI_CR2_TXDMAEN; +} + +void spi_disable_tx_dma(u32 spi) +{ + SPI_CR2(spi) &= ~SPI_CR2_TXDMAEN; +} + +void spi_enable_rx_dma(u32 spi) +{ + SPI_CR2(spi) |= SPI_CR2_RXDMAEN; +} + +void spi_disable_rx_dma(u32 spi) +{ + SPI_CR2(spi) &= ~SPI_CR2_RXDMAEN; +} diff --git a/lib/stm32f1/spi.c b/lib/stm32f1/spi.c deleted file mode 100644 index 733a1bc..0000000 --- a/lib/stm32f1/spi.c +++ /dev/null @@ -1,290 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include - -/* - * SPI and I2S code. - * - * Examples: - * spi_init_master(SPI1, 1000000, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE, - * SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT, - * SPI_CR1_LSBFIRST); - * spi_write(SPI1, 0x55); // 8-bit write - * spi_write(SPI1, 0xaa88); // 16-bit write - * reg8 = spi_read(SPI1); // 8-bit read - * reg16 = spi_read(SPI1); // 16-bit read - */ - -int spi_init_master(u32 spi, u32 br, u32 cpol, u32 cpha, u32 dff, u32 lsbfirst) -{ - u32 reg32 = 0; - - reg32 |= SPI_CR1_MSTR; /* Configure SPI as master. */ - - reg32 |= br; /* Set BAUD rate bits. */ - reg32 |= cpol; /* Set CPOL value. */ - reg32 |= cpha; /* Set CPHA value. */ - reg32 |= dff; /* Set data format (8 or 16 bits). */ - reg32 |= lsbfirst; /* Set frame format (LSB- or MSB-first). */ - - /* TODO: NSS pin handling. */ - - SPI_CR1(spi) = reg32; - - return 0; /* TODO */ -} - -/* TODO: Error handling? */ -void spi_enable(u32 spi) -{ - u32 reg32; - - reg32 = SPI_CR1(spi); - reg32 |= SPI_CR1_SPE; /* Enable SPI. */ - SPI_CR1(spi) = reg32; -} - -/* TODO: Error handling? */ -void spi_disable(u32 spi) -{ - u32 reg32; - - /* TODO: Follow procedure from section 23.3.8 in the techref manual. */ - reg32 = SPI_CR1(spi); - reg32 &= ~(SPI_CR1_SPE); /* Disable SPI. */ - SPI_CR1(spi) = reg32; -} - -void spi_write(u32 spi, u16 data) -{ - /* Write data (8 or 16 bits, depending on DFF) into DR. */ - SPI_DR(spi) = data; -} - -void spi_send(u32 spi, u16 data) -{ - /* Write data (8 or 16 bits, depending on DFF) into DR. */ - SPI_DR(spi) = data; - - /* wait for transfer finished */ - while (SPI_SR(spi) & SPI_SR_BSY ) - { - } -} - -u16 spi_read(u32 spi) -{ - /* Read the data (8 or 16 bits, depending on DFF bit) from DR. */ - return SPI_DR(spi); -} - -void spi_set_bidirectional_mode(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_BIDIMODE; -} - -void spi_set_unidirectional_mode(u32 spi) -{ - SPI_CR1(spi) &= ~SPI_CR1_BIDIMODE; -} - -void spi_set_bidirectional_receive_only_mode(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_BIDIMODE; - SPI_CR1(spi) &= ~SPI_CR1_BIDIOE; -} - -void spi_set_bidirectional_transmit_only_mode(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_BIDIMODE; - SPI_CR1(spi) |= SPI_CR1_BIDIOE; -} - -void spi_enable_crc(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_CRCEN; -} - -void spi_disable_crc(u32 spi) -{ - SPI_CR1(spi) &= ~SPI_CR1_CRCEN; -} - -void spi_set_next_tx_from_buffer(u32 spi) -{ - SPI_CR1(spi) &= ~SPI_CR1_CRCNEXT; -} - -void spi_set_next_tx_from_crc(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_CRCNEXT; -} - -void spi_set_dff_8bit(u32 spi) -{ - SPI_CR1(spi) &= ~SPI_CR1_DFF; -} - -void spi_set_dff_16bit(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_DFF; -} - -void spi_set_full_duplex_mode(u32 spi) -{ - SPI_CR1(spi) &= ~SPI_CR1_RXONLY; -} - -void spi_set_receive_only_mode(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_RXONLY; -} - -void spi_disable_software_slave_management(u32 spi) -{ - SPI_CR1(spi) &= ~SPI_CR1_SSM; -} - -void spi_enable_software_slave_management(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_SSM; -} - -void spi_set_nss_high(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_SSI; -} - -void spi_set_nss_low(u32 spi) -{ - SPI_CR1(spi) &= ~SPI_CR1_SSI; -} - -void spi_send_lsb_first(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_LSBFIRST; -} - -void spi_send_msb_first(u32 spi) -{ - SPI_CR1(spi) &= ~SPI_CR1_LSBFIRST; -} - -void spi_set_baudrate_prescaler(u32 spi, u8 baudrate) -{ - u32 reg32; - - if (baudrate > 7) - return; - - reg32 = ( SPI_CR1(spi) & 0xffc7 ); /* clear bits [5:3] */ - reg32 |= (baudrate << 3); - SPI_CR1(spi) = reg32; -} - -void spi_set_master_mode(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_MSTR; -} - -void spi_set_slave_mode(u32 spi) -{ - SPI_CR1(spi) &= ~SPI_CR1_MSTR; -} - -void spi_set_clock_polarity_1(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_CPOL; -} - -void spi_set_clock_polarity_0(u32 spi) -{ - SPI_CR1(spi) &= ~SPI_CR1_CPOL; -} - -void spi_set_clock_phase_1(u32 spi) -{ - SPI_CR1(spi) |= SPI_CR1_CPHA; -} - -void spi_set_clock_phase_0(u32 spi) -{ - SPI_CR1(spi) &= ~SPI_CR1_CPHA; -} - -void spi_enable_tx_buffer_empty_interrupt(u32 spi) -{ - SPI_CR2(spi) |= SPI_CR2_TXEIE; -} - -void spi_disable_tx_buffer_empty_interrupt(u32 spi) -{ - SPI_CR2(spi) &= ~SPI_CR2_TXEIE; -} - -void spi_enable_rx_buffer_not_empty_interrupt(u32 spi) -{ - SPI_CR2(spi) |= SPI_CR2_RXNEIE; -} - -void spi_disable_rx_buffer_not_empty_interrupt(u32 spi) -{ - SPI_CR2(spi) &= ~SPI_CR2_RXNEIE; -} - -void spi_enable_error_interrupt(u32 spi) -{ - SPI_CR2(spi) |= SPI_CR2_ERRIE; -} - -void spi_disable_error_interrupt(u32 spi) -{ - SPI_CR2(spi) &= ~SPI_CR2_ERRIE; -} - -void spi_enable_ss_output(u32 spi) -{ - SPI_CR2(spi) |= SPI_CR2_SSOE; -} - -void spi_disable_ss_output(u32 spi) -{ - SPI_CR2(spi) &= ~SPI_CR2_SSOE; -} - -void spi_enable_tx_dma(u32 spi) -{ - SPI_CR2(spi) |= SPI_CR2_TXDMAEN; -} - -void spi_disable_tx_dma(u32 spi) -{ - SPI_CR2(spi) &= ~SPI_CR2_TXDMAEN; -} - -void spi_enable_rx_dma(u32 spi) -{ - SPI_CR2(spi) |= SPI_CR2_RXDMAEN; -} - -void spi_disable_rx_dma(u32 spi) -{ - SPI_CR2(spi) &= ~SPI_CR2_RXDMAEN; -} diff --git a/lib/stm32f2/Makefile b/lib/stm32f2/Makefile index f3d6ff7..ba0ae04 100644 --- a/lib/stm32f2/Makefile +++ b/lib/stm32f2/Makefile @@ -28,7 +28,7 @@ CFLAGS = -Os -g -Wall -Wextra -I../../include -fno-common \ -ffunction-sections -fdata-sections -MD -DSTM32F2 # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = vector.o gpio.o systick.o i2c.o +OBJS = vector.o gpio.o systick.o i2c.o spi.o #VPATH += ../usb VPATH += ../stm32_common -- cgit v1.2.3 From 4d02d36d6b16e96eda731c9adbbbadd694371700 Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Thu, 15 Sep 2011 16:26:39 -0700 Subject: Moving nvic code to common, adding F1 and F2 specific user interrupt definition headers. --- include/libopencm3/stm32/f1/nvic.h | 162 ---------------------------------- include/libopencm3/stm32/f1/nvic_f1.h | 99 +++++++++++++++++++++ include/libopencm3/stm32/f2/nvic_f2.h | 112 +++++++++++++++++++++++ include/libopencm3/stm32/nvic.h | 108 +++++++++++++++++++++++ lib/stm32_common/nvic.c | 106 ++++++++++++++++++++++ lib/stm32f1/nvic.c | 106 ---------------------- lib/stm32f2/Makefile | 2 +- 7 files changed, 426 insertions(+), 269 deletions(-) delete mode 100644 include/libopencm3/stm32/f1/nvic.h create mode 100644 include/libopencm3/stm32/f1/nvic_f1.h create mode 100644 include/libopencm3/stm32/f2/nvic_f2.h create mode 100644 include/libopencm3/stm32/nvic.h create mode 100644 lib/stm32_common/nvic.c delete mode 100644 lib/stm32f1/nvic.c diff --git a/include/libopencm3/stm32/f1/nvic.h b/include/libopencm3/stm32/f1/nvic.h deleted file mode 100644 index d29c425..0000000 --- a/include/libopencm3/stm32/f1/nvic.h +++ /dev/null @@ -1,162 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_NVIC_H -#define LIBOPENCM3_NVIC_H - -#include -#include - -/* --- NVIC Registers ------------------------------------------------------ */ - -/* ISER: Interrupt Set Enable Registers */ -/* Note: 8 32bit Registers */ -#define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + (iser_id * 4)) - -/* NVIC_BASE + 0x020 (0xE000 E120 - 0xE000 E17F): Reserved */ - -/* ICER: Interrupt Clear Enable Registers */ -/* Note: 8 32bit Registers */ -#define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + (icer_id * 4)) - -/* NVIC_BASE + 0x0A0 (0xE000 E1A0 - 0xE000 E1FF): Reserved */ - -/* ISPR: Interrupt Set Pending Registers */ -/* Note: 8 32bit Registers */ -#define NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + (ispr_id * 4)) - -/* NVIC_BASE + 0x120 (0xE000 E220 - 0xE000 E27F): Reserved */ - -/* ICPR: Interrupt Clear Pending Registers */ -/* Note: 8 32bit Registers */ -#define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + (icpr_id * 4)) - -/* NVIC_BASE + 0x1A0 (0xE000 E2A0 - 0xE00 E2FF): Reserved */ - -/* IABR: Interrupt Active Bit Register */ -/* Note: 8 32bit Registers */ -#define NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + (iabr_id * 4)) - -/* NVIC_BASE + 0x220 (0xE000 E320 - 0xE000 E3FF): Reserved */ - -/* IPR: Interrupt Priority Registers */ -/* Note: 240 8bit Registers */ -#define NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + ipr_id) - -/* STIR: Software Trigger Interrupt Register */ -#define NVIC_STIR MMIO32(STIR_BASE) - -/* --- IRQ channel numbers-------------------------------------------------- */ - -/* Cortex M3 System Interrupts */ -#define NVIC_NMI_IRQ -14 -#define NVIC_HARD_FAULT_IRQ -13 -#define NVIC_MEM_MANAGE_IRQ -12 -#define NVIC_BUS_FAULT_IRQ -11 -#define NVIC_USAGE_FAULT_IRQ -10 -/* irq numbers -6 to -9 are reserved */ -#define NVIC_SV_CALL_IRQ -5 -#define DEBUG_MONITOR_IRQ -4 -/* irq number -3 reserved */ -#define NVIC_PENDSV_IRQ -2 -#define NVIC_SYSTICK_IRQ -1 - -/* User Interrupts */ -#define NVIC_WWDG_IRQ 0 -#define NVIC_PVD_IRQ 1 -#define NVIC_TAMPER_IRQ 2 -#define NVIC_RTC_IRQ 3 -#define NVIC_FLASH_IRQ 4 -#define NVIC_RCC_IRQ 5 -#define NVIC_EXTI0_IRQ 6 -#define NVIC_EXTI1_IRQ 7 -#define NVIC_EXTI2_IRQ 8 -#define NVIC_EXTI3_IRQ 9 -#define NVIC_EXTI4_IRQ 10 -#define NVIC_DMA1_CHANNEL1_IRQ 11 -#define NVIC_DMA1_CHANNEL2_IRQ 12 -#define NVIC_DMA1_CHANNEL3_IRQ 13 -#define NVIC_DMA1_CHANNEL4_IRQ 14 -#define NVIC_DMA1_CHANNEL5_IRQ 15 -#define NVIC_DMA1_CHANNEL6_IRQ 16 -#define NVIC_DMA1_CHANNEL7_IRQ 17 -#define NVIC_ADC1_2_IRQ 18 -#define NVIC_USB_HP_CAN_TX_IRQ 19 -#define NVIC_USB_LP_CAN_RX0_IRQ 20 -#define NVIC_CAN_RX1_IRQ 21 -#define NVIC_CAN_SCE_IRQ 22 -#define NVIC_EXTI9_5_IRQ 23 -#define NVIC_TIM1_BRK_IRQ 24 -#define NVIC_TIM1_UP_IRQ 25 -#define NVIC_TIM1_TRG_COM_IRQ 26 -#define NVIC_TIM1_CC_IRQ 27 -#define NVIC_TIM2_IRQ 28 -#define NVIC_TIM3_IRQ 29 -#define NVIC_TIM4_IRQ 30 -#define NVIC_I2C1_EV_IRQ 31 -#define NVIC_I2C1_ER_IRQ 32 -#define NVIC_I2C2_EV_IRQ 33 -#define NVIC_I2C2_ER_IRQ 34 -#define NVIC_SPI1_IRQ 35 -#define NVIC_SPI2_IRQ 36 -#define NVIC_USART1_IRQ 37 -#define NVIC_USART2_IRQ 38 -#define NVIC_USART3_IRQ 39 -#define NVIC_EXTI15_10_IRQ 40 -#define NVIC_RTC_ALARM_IRQ 41 -#define NVIC_USB_WAKEUP_IRQ 42 -#define NVIC_TIM8_BRK_IRQ 43 -#define NVIC_TIM8_UP_IRQ 44 -#define NVIC_TIM8_TRG_COM_IRQ 45 -#define NVIC_TIM8_CC_IRQ 46 -#define NVIC_ADC3_IRQ 47 -#define NVIC_FSMC_IRQ 48 -#define NVIC_SDIO_IRQ 49 -#define NVIC_TIM5_IRQ 50 -#define NVIC_SPI3_IRQ 51 -#define NVIC_USART4_IRQ 52 -#define NVIC_USART5_IRQ 53 -#define NVIC_TIM6_IRQ 54 -#define NVIC_TIM7_IRQ 55 -#define NVIC_DMA2_CHANNEL1_IRQ 56 -#define NVIC_DMA2_CHANNEL2_IRQ 57 -#define NVIC_DMA2_CHANNEL3_IRQ 58 -#define NVIC_DMA2_CHANNEL4_5_IRQ 59 -#define NVIC_DMA2_CHANNEL5_IRQ 60 -#define NVIC_ETH_IRQ 61 -#define NVIC_ETH_WKUP_IRQ 62 -#define NVIC_CAN2_TX_IRQ 63 -#define NVIC_CAN2_RX0_IRQ 64 -#define NVIC_CAN2_RX1_IRQ 65 -#define NVIC_CAN2_SCE_IRQ 66 -#define NVIC_OTG_FS_IRQ 67 - -/* --- NVIC functions ------------------------------------------------------ */ - -void nvic_enable_irq(u8 irqn); -void nvic_disable_irq(u8 irqn); -u8 nvic_get_pending_irq(u8 irqn); -void nvic_set_pending_irq(u8 irqn); -void nvic_clear_pending_irq(u8 irqn); -u8 nvic_get_active_irq(u8 irqn); -u8 nvic_get_irq_enabled(u8 irqn); -void nvic_set_priority(u8 irqn, u8 priority); -void nvic_generate_software_interrupt(u8 irqn); - -#endif diff --git a/include/libopencm3/stm32/f1/nvic_f1.h b/include/libopencm3/stm32/f1/nvic_f1.h new file mode 100644 index 0000000..b0b32a0 --- /dev/null +++ b/include/libopencm3/stm32/f1/nvic_f1.h @@ -0,0 +1,99 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Piotr Esden-Tempski + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_NVIC_F1_H +#define LIBOPENCM3_NVIC_F1_H + +/* --- IRQ channel numbers-------------------------------------------------- */ + +/* Note: These F1 specific user interrupt definitions supplement the + * general NVIC definitions in ../nvic.h + */ + +/* User Interrupts */ +#define NVIC_WWDG_IRQ 0 +#define NVIC_PVD_IRQ 1 +#define NVIC_TAMPER_IRQ 2 +#define NVIC_RTC_IRQ 3 +#define NVIC_FLASH_IRQ 4 +#define NVIC_RCC_IRQ 5 +#define NVIC_EXTI0_IRQ 6 +#define NVIC_EXTI1_IRQ 7 +#define NVIC_EXTI2_IRQ 8 +#define NVIC_EXTI3_IRQ 9 +#define NVIC_EXTI4_IRQ 10 +#define NVIC_DMA1_CHANNEL1_IRQ 11 +#define NVIC_DMA1_CHANNEL2_IRQ 12 +#define NVIC_DMA1_CHANNEL3_IRQ 13 +#define NVIC_DMA1_CHANNEL4_IRQ 14 +#define NVIC_DMA1_CHANNEL5_IRQ 15 +#define NVIC_DMA1_CHANNEL6_IRQ 16 +#define NVIC_DMA1_CHANNEL7_IRQ 17 +#define NVIC_ADC1_2_IRQ 18 +#define NVIC_USB_HP_CAN_TX_IRQ 19 +#define NVIC_USB_LP_CAN_RX0_IRQ 20 +#define NVIC_CAN_RX1_IRQ 21 +#define NVIC_CAN_SCE_IRQ 22 +#define NVIC_EXTI9_5_IRQ 23 +#define NVIC_TIM1_BRK_IRQ 24 +#define NVIC_TIM1_UP_IRQ 25 +#define NVIC_TIM1_TRG_COM_IRQ 26 +#define NVIC_TIM1_CC_IRQ 27 +#define NVIC_TIM2_IRQ 28 +#define NVIC_TIM3_IRQ 29 +#define NVIC_TIM4_IRQ 30 +#define NVIC_I2C1_EV_IRQ 31 +#define NVIC_I2C1_ER_IRQ 32 +#define NVIC_I2C2_EV_IRQ 33 +#define NVIC_I2C2_ER_IRQ 34 +#define NVIC_SPI1_IRQ 35 +#define NVIC_SPI2_IRQ 36 +#define NVIC_USART1_IRQ 37 +#define NVIC_USART2_IRQ 38 +#define NVIC_USART3_IRQ 39 +#define NVIC_EXTI15_10_IRQ 40 +#define NVIC_RTC_ALARM_IRQ 41 +#define NVIC_USB_WAKEUP_IRQ 42 +#define NVIC_TIM8_BRK_IRQ 43 +#define NVIC_TIM8_UP_IRQ 44 +#define NVIC_TIM8_TRG_COM_IRQ 45 +#define NVIC_TIM8_CC_IRQ 46 +#define NVIC_ADC3_IRQ 47 +#define NVIC_FSMC_IRQ 48 +#define NVIC_SDIO_IRQ 49 +#define NVIC_TIM5_IRQ 50 +#define NVIC_SPI3_IRQ 51 +#define NVIC_USART4_IRQ 52 +#define NVIC_USART5_IRQ 53 +#define NVIC_TIM6_IRQ 54 +#define NVIC_TIM7_IRQ 55 +#define NVIC_DMA2_CHANNEL1_IRQ 56 +#define NVIC_DMA2_CHANNEL2_IRQ 57 +#define NVIC_DMA2_CHANNEL3_IRQ 58 +#define NVIC_DMA2_CHANNEL4_5_IRQ 59 +#define NVIC_DMA2_CHANNEL5_IRQ 60 +#define NVIC_ETH_IRQ 61 +#define NVIC_ETH_WKUP_IRQ 62 +#define NVIC_CAN2_TX_IRQ 63 +#define NVIC_CAN2_RX0_IRQ 64 +#define NVIC_CAN2_RX1_IRQ 65 +#define NVIC_CAN2_SCE_IRQ 66 +#define NVIC_OTG_FS_IRQ 67 + +#endif diff --git a/include/libopencm3/stm32/f2/nvic_f2.h b/include/libopencm3/stm32/f2/nvic_f2.h new file mode 100644 index 0000000..2545f0a --- /dev/null +++ b/include/libopencm3/stm32/f2/nvic_f2.h @@ -0,0 +1,112 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Fergus Noble + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_NVIC_F2_H +#define LIBOPENCM3_NVIC_F2_H + +/* --- IRQ channel numbers-------------------------------------------------- */ + +/* Note: These F2 specific user interrupt definitions supplement the + * general NVIC definitions in ../nvic.h + */ + +/* User Interrupts */ +#define NVIC_WWDG_IRQ 0 +#define PVD_IRQ 1 +#define TAMP_STAMP_IRQ 2 +#define RTC_WKUP_IRQ 3 +#define FLASH_IRQ 4 +#define RCC_IRQ 5 +#define EXTI0_IRQ 6 +#define EXTI1_IRQ 7 +#define EXTI2_IRQ 8 +#define EXTI3_IRQ 9 +#define EXTI4_IRQ 10 +#define DMA1_STREAM0_IRQ 11 +#define DMA1_STREAM1_IRQ 12 +#define DMA1_STREAM2_IRQ 13 +#define DMA1_STREAM3_IRQ 14 +#define DMA1_STREAM4_IRQ 15 +#define DMA1_STREAM5_IRQ 16 +#define DMA1_STREAM6_IRQ 17 +#define ADC_IRQ 18 +#define CAN1_TX_IRQ 19 +#define CAN1_RX0_IRQ 20 +#define CAN1_RX1_IRQ 21 +#define CAN1_SCE_IRQ 22 +#define EXTI9_5_IRQ 23 +#define TIM1_BRK_TIM9_IRQ 24 +#define TIM1_UP_TIM10_IRQ 25 +#define TIM1_TRG_COM_TIM11_IRQ 26 +#define TIM1_CC_IRQ 27 +#define TIM2_IRQ 28 +#define TIM3_IRQ 29 +#define TIM4_IRQ 30 +#define I2C1_EV_IRQ 31 +#define I2C1_ER_IRQ 32 +#define I2C2_EV_IRQ 33 +#define I2C2_ER_IRQ 34 +#define SPI1_IRQ 35 +#define SPI2_IRQ 36 +#define USART1_IRQ 37 +#define USART2_IRQ 38 +#define USART3_IRQ 39 +#define EXTI15_10_IRQ 40 +#define RTC_ALARM_IRQ 41 +#define USB_FS_WKUP_IRQ 42 +#define TIM8_BRK_TIM12_IRQ 43 +#define TIM8_UP_TIM13_IRQ 44 +#define TIM8_TRG_COM_TIM14_IRQ 45 +#define TIM8_CC_IRQ 46 +#define DMA1_STREAM7_IRQ 47 +#define FSMC_IRQ 48 +#define SDIO_IRQ 49 +#define TIM5_IRQ 50 +#define SPI3_IRQ 51 +#define USART4_IRQ 52 +#define USART5_IRQ 53 +#define TIM6_DAC_IRQ 54 +#define TIM7_IRQ 55 +#define DMA2_STREAM0_IRQ 56 +#define DMA2_STREAM1_IRQ 57 +#define DMA2_STREAM2_IRQ 58 +#define DMA2_STREAM3_IRQ 59 +#define DMA2_STREAM4_IRQ 60 +#define ETH_IRQ 61 +#define ETH_WKUP_IRQ 62 +#define CAN2_TX_IRQ 63 +#define CAN2_RX0_IRQ 64 +#define CAN2_RX1_IRQ 65 +#define CAN2_SCE_IRQ 66 +#define OTG_FS_IRQ 67 +#define DMA2_STREAM5_IRQ 68 +#define DMA2_STREAM6_IRQ 69 +#define DMA2_STREAM7_IRQ 70 +#define USART6_IRQ 71 +#define I2C3_EV_IRQ 72 +#define I2C3_ER_IRQ 73 +#define OTG_HS_EP1_OUT_IRQ 74 +#define OTG_HS_EP1_IN_IRQ 75 +#define OTG_HS_WKUP_IRQ 76 +#define OTG_HS_IRQ 77 +#define DCMI_IRQ 78 +#define CRYP_IRQ 79 +#define HASH_RNG_IRQ 80 + +#endif diff --git a/include/libopencm3/stm32/nvic.h b/include/libopencm3/stm32/nvic.h new file mode 100644 index 0000000..339a159 --- /dev/null +++ b/include/libopencm3/stm32/nvic.h @@ -0,0 +1,108 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Piotr Esden-Tempski + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_NVIC_H +#define LIBOPENCM3_NVIC_H + +#include +#include + +/* --- NVIC Registers ------------------------------------------------------ */ + +/* ISER: Interrupt Set Enable Registers */ +/* Note: 8 32bit Registers */ +#define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + (iser_id * 4)) + +/* NVIC_BASE + 0x020 (0xE000 E120 - 0xE000 E17F): Reserved */ + +/* ICER: Interrupt Clear Enable Registers */ +/* Note: 8 32bit Registers */ +#define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + (icer_id * 4)) + +/* NVIC_BASE + 0x0A0 (0xE000 E1A0 - 0xE000 E1FF): Reserved */ + +/* ISPR: Interrupt Set Pending Registers */ +/* Note: 8 32bit Registers */ +#define NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + (ispr_id * 4)) + +/* NVIC_BASE + 0x120 (0xE000 E220 - 0xE000 E27F): Reserved */ + +/* ICPR: Interrupt Clear Pending Registers */ +/* Note: 8 32bit Registers */ +#define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + (icpr_id * 4)) + +/* NVIC_BASE + 0x1A0 (0xE000 E2A0 - 0xE00 E2FF): Reserved */ + +/* IABR: Interrupt Active Bit Register */ +/* Note: 8 32bit Registers */ +#define NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + (iabr_id * 4)) + +/* NVIC_BASE + 0x220 (0xE000 E320 - 0xE000 E3FF): Reserved */ + +/* IPR: Interrupt Priority Registers */ +/* Note: 240 8bit Registers */ +#define NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + ipr_id) + +/* STIR: Software Trigger Interrupt Register */ +#define NVIC_STIR MMIO32(STIR_BASE) + +/* --- IRQ channel numbers-------------------------------------------------- */ + +/* Cortex M3 System Interrupts */ +#define NVIC_NMI_IRQ -14 +#define NVIC_HARD_FAULT_IRQ -13 +#define NVIC_MEM_MANAGE_IRQ -12 +#define NVIC_BUS_FAULT_IRQ -11 +#define NVIC_USAGE_FAULT_IRQ -10 +/* irq numbers -6 to -9 are reserved */ +#define NVIC_SV_CALL_IRQ -5 +#define DEBUG_MONITOR_IRQ -4 +/* irq number -3 reserved */ +#define NVIC_PENDSV_IRQ -2 +#define NVIC_SYSTICK_IRQ -1 + + +/* Note: User interrupts are family specific and are defined in a familiy + * specific header file in the corresponding subfolder. + */ + +#ifdef STM32F1 +#include +#else +#ifdef STM32F2 +#include +#else +#error "stm32 family not defined." +#endif +#endif + + +/* --- NVIC functions ------------------------------------------------------ */ + +void nvic_enable_irq(u8 irqn); +void nvic_disable_irq(u8 irqn); +u8 nvic_get_pending_irq(u8 irqn); +void nvic_set_pending_irq(u8 irqn); +void nvic_clear_pending_irq(u8 irqn); +u8 nvic_get_active_irq(u8 irqn); +u8 nvic_get_irq_enabled(u8 irqn); +void nvic_set_priority(u8 irqn, u8 priority); +void nvic_generate_software_interrupt(u8 irqn); + +#endif diff --git a/lib/stm32_common/nvic.c b/lib/stm32_common/nvic.c new file mode 100644 index 0000000..cf77cc3 --- /dev/null +++ b/lib/stm32_common/nvic.c @@ -0,0 +1,106 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include + +void nvic_enable_irq(u8 irqn) +{ + if (irqn < 32) + NVIC_ISER(0) |= (1 << irqn); + if ((irqn >= 32) & (irqn < 64)) + NVIC_ISER(1) |= (1 << (irqn - 32)); + if ((irqn >= 64) & (irqn < 68)) + NVIC_ISER(2) |= (1 << (irqn - 64)); +} + +void nvic_disable_irq(u8 irqn) +{ + if (irqn < 32) + NVIC_ICER(0) |= (1 << irqn); + if ((irqn >= 32) & (irqn < 64)) + NVIC_ICER(1) |= (1 << (irqn - 32)); + if ((irqn >= 64) & (irqn < 68)) + NVIC_ICER(2) |= (1 << (irqn - 64)); +} + +u8 nvic_get_pending_irq(u8 irqn) +{ + if (irqn < 32) + return (NVIC_ISPR(0) & (1 << irqn)); + if ((irqn >= 32) & (irqn < 64)) + return (NVIC_ISPR(1) & (1 << (irqn - 32))); + if ((irqn >= 64) & (irqn < 68)) + return (NVIC_ISPR(2) & (1 << (irqn - 64))); + return 0; +} + +void nvic_set_pending_irq(u8 irqn) +{ + if (irqn < 32) + NVIC_ISPR(0) |= (1 << irqn); + if ((irqn >= 32) & (irqn < 64)) + NVIC_ISPR(1) |= (1 << (irqn - 32)); + if ((irqn >= 64) & (irqn < 68)) + NVIC_ISPR(2) |= (1 << (irqn - 64)); +} + +void nvic_clear_pending_irq(u8 irqn) +{ + if (irqn < 32) + NVIC_ICPR(0) |= (1 << irqn); + if ((irqn >= 32) & (irqn < 64)) + NVIC_ICPR(1) |= (1 << (irqn - 32)); + if ((irqn >= 64) & (irqn < 68)) + NVIC_ICPR(2) |= (1 << (irqn - 64)); +} + +u8 nvic_get_active_irq(u8 irqn) +{ + if (irqn < 32) + return (NVIC_IABR(0) & (1 << irqn)); + if ((irqn >= 32) & (irqn < 64)) + return (NVIC_IABR(1) & (1 << (irqn - 32))); + if ((irqn >= 64) & (irqn < 68)) + return (NVIC_IABR(2) & (1 << (irqn - 64))); + return 0; +} + +u8 nvic_get_irq_enabled(u8 irqn) +{ + if (irqn < 32) + return (NVIC_ISER(0) & (1 << irqn)); + if ((irqn >= 32) & (irqn < 64)) + return (NVIC_ISER(1) & (1 << (irqn - 32))); + if ((irqn >= 64) & (irqn < 68)) + return (NVIC_ISER(2) & (1 << (irqn - 64))); + return 0; +} + +void nvic_set_priority(u8 irqn, u8 priority) +{ + NVIC_IPR(irqn/4) |= (priority << ((irqn % 4) * 8)); +} + +void nvic_generate_software_interrupt(u8 irqn) +{ + if (irqn <= 239) + NVIC_STIR |= irqn; +} + + diff --git a/lib/stm32f1/nvic.c b/lib/stm32f1/nvic.c deleted file mode 100644 index f45b601..0000000 --- a/lib/stm32f1/nvic.c +++ /dev/null @@ -1,106 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include - -void nvic_enable_irq(u8 irqn) -{ - if (irqn < 32) - NVIC_ISER(0) |= (1 << irqn); - if ((irqn >= 32) & (irqn < 64)) - NVIC_ISER(1) |= (1 << (irqn - 32)); - if ((irqn >= 64) & (irqn < 68)) - NVIC_ISER(2) |= (1 << (irqn - 64)); -} - -void nvic_disable_irq(u8 irqn) -{ - if (irqn < 32) - NVIC_ICER(0) |= (1 << irqn); - if ((irqn >= 32) & (irqn < 64)) - NVIC_ICER(1) |= (1 << (irqn - 32)); - if ((irqn >= 64) & (irqn < 68)) - NVIC_ICER(2) |= (1 << (irqn - 64)); -} - -u8 nvic_get_pending_irq(u8 irqn) -{ - if (irqn < 32) - return (NVIC_ISPR(0) & (1 << irqn)); - if ((irqn >= 32) & (irqn < 64)) - return (NVIC_ISPR(1) & (1 << (irqn - 32))); - if ((irqn >= 64) & (irqn < 68)) - return (NVIC_ISPR(2) & (1 << (irqn - 64))); - return 0; -} - -void nvic_set_pending_irq(u8 irqn) -{ - if (irqn < 32) - NVIC_ISPR(0) |= (1 << irqn); - if ((irqn >= 32) & (irqn < 64)) - NVIC_ISPR(1) |= (1 << (irqn - 32)); - if ((irqn >= 64) & (irqn < 68)) - NVIC_ISPR(2) |= (1 << (irqn - 64)); -} - -void nvic_clear_pending_irq(u8 irqn) -{ - if (irqn < 32) - NVIC_ICPR(0) |= (1 << irqn); - if ((irqn >= 32) & (irqn < 64)) - NVIC_ICPR(1) |= (1 << (irqn - 32)); - if ((irqn >= 64) & (irqn < 68)) - NVIC_ICPR(2) |= (1 << (irqn - 64)); -} - -u8 nvic_get_active_irq(u8 irqn) -{ - if (irqn < 32) - return (NVIC_IABR(0) & (1 << irqn)); - if ((irqn >= 32) & (irqn < 64)) - return (NVIC_IABR(1) & (1 << (irqn - 32))); - if ((irqn >= 64) & (irqn < 68)) - return (NVIC_IABR(2) & (1 << (irqn - 64))); - return 0; -} - -u8 nvic_get_irq_enabled(u8 irqn) -{ - if (irqn < 32) - return (NVIC_ISER(0) & (1 << irqn)); - if ((irqn >= 32) & (irqn < 64)) - return (NVIC_ISER(1) & (1 << (irqn - 32))); - if ((irqn >= 64) & (irqn < 68)) - return (NVIC_ISER(2) & (1 << (irqn - 64))); - return 0; -} - -void nvic_set_priority(u8 irqn, u8 priority) -{ - NVIC_IPR(irqn/4) |= (priority << ((irqn % 4) * 8)); -} - -void nvic_generate_software_interrupt(u8 irqn) -{ - if (irqn <= 239) - NVIC_STIR |= irqn; -} - - diff --git a/lib/stm32f2/Makefile b/lib/stm32f2/Makefile index ba0ae04..cd50c4b 100644 --- a/lib/stm32f2/Makefile +++ b/lib/stm32f2/Makefile @@ -28,7 +28,7 @@ CFLAGS = -Os -g -Wall -Wextra -I../../include -fno-common \ -ffunction-sections -fdata-sections -MD -DSTM32F2 # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = vector.o gpio.o systick.o i2c.o spi.o +OBJS = vector.o gpio.o systick.o i2c.o spi.o nvic.o #VPATH += ../usb VPATH += ../stm32_common -- cgit v1.2.3 From 0565cb837815f4086b03ddf090dcada82f30e9c4 Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Fri, 16 Sep 2011 17:34:08 -0700 Subject: RCC header file for F2 implemented, no convenience functions so far. --- include/libopencm3/stm32/f2/rcc.h | 453 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 453 insertions(+) create mode 100644 include/libopencm3/stm32/f2/rcc.h diff --git a/include/libopencm3/stm32/f2/rcc.h b/include/libopencm3/stm32/f2/rcc.h new file mode 100644 index 0000000..430ce77 --- /dev/null +++ b/include/libopencm3/stm32/f2/rcc.h @@ -0,0 +1,453 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * Copyright (C) 2009 Federico Ruiz-Ugalde + * Copyright (C) 2011 Fergus Noble + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_RCC_H +#define LIBOPENCM3_RCC_H + +#include +#include + +/* --- RCC registers ------------------------------------------------------- */ + +#define RCC_CR MMIO32(RCC_BASE + 0x00) +#define RCC_PLLCFGR MMIO32(RCC_BASE + 0x04) +#define RCC_CFGR MMIO32(RCC_BASE + 0x08) +#define RCC_CIR MMIO32(RCC_BASE + 0x0c) +#define RCC_AHB1RSTR MMIO32(RCC_BASE + 0x10) +#define RCC_AHB2RSTR MMIO32(RCC_BASE + 0x14) +#define RCC_AHB3RSTR MMIO32(RCC_BASE + 0x18) +/* RCC_BASE + 0x1C Reserved */ +#define RCC_APB1RSTR MMIO32(RCC_BASE + 0x20) +#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x24) +/* RCC_BASE + 0x28 Reserved */ +/* RCC_BASE + 0x2C Reserved */ +#define RCC_AHB1ENR MMIO32(RCC_BASE + 0x30) +#define RCC_AHB2ENR MMIO32(RCC_BASE + 0x34) +#define RCC_AHB3ENR MMIO32(RCC_BASE + 0x38) +/* RCC_BASE + 0x3C Reserved */ +#define RCC_APB1ENR MMIO32(RCC_BASE + 0x40) +#define RCC_APB2ENR MMIO32(RCC_BASE + 0x44) +/* RCC_BASE + 0x48 Reserved */ +/* RCC_BASE + 0x4C Reserved */ +#define RCC_AHB1LPENR MMIO32(RCC_BASE + 0x50) +#define RCC_AHB2LPENR MMIO32(RCC_BASE + 0x54) +#define RCC_AHB3LPENR MMIO32(RCC_BASE + 0x58) +/* RCC_BASE + 0x5C Reserved */ +#define RCC_APB1LPENR MMIO32(RCC_BASE + 0x60) +#define RCC_APB2LPENR MMIO32(RCC_BASE + 0x64) +/* RCC_BASE + 0x68 Reserved */ +/* RCC_BASE + 0x6C Reserved */ +#define RCC_BDCR MMIO32(RCC_BASE + 0x70) +#define RCC_CSR MMIO32(RCC_BASE + 0x74) +/* RCC_BASE + 0x78 Reserved */ +/* RCC_BASE + 0x7C Reserved */ +#define RCC_SSCGR MMIO32(RCC_BASE + 0x80) +#define RCC_PLLI2SCFGR MMIO32(RCC_BASE + 0x84) + +/* --- RCC_CR values ------------------------------------------------------- */ + +#define RCC_CR_PLLI2SRDY (1 << 27) +#define RCC_CR_PLLI2SON (1 << 26) +#define RCC_CR_PLLRDY (1 << 25) +#define RCC_CR_PLLON (1 << 24) +#define RCC_CR_CSSON (1 << 19) +#define RCC_CR_HSEBYP (1 << 18) +#define RCC_CR_HSERDY (1 << 17) +#define RCC_CR_HSEON (1 << 16) +/* HSICAL: [15:8] */ +/* HSITRIM: [7:3] */ +#define RCC_CR_HSIRDY (1 << 1) +#define RCC_CR_HSION (1 << 0) + +/* --- RCC_PLLCFGR values ------------------------------------------------------- */ + +/* PLLQ: [27:24] */ +#define RCC_PLLCFGR_PLLQ_SHIFT 24 +#define RCC_PLLCFGR_PLLSRC (1 << 22) +/* PLLP: [17:16] */ +#define RCC_PLLCFGR_PLLP_SHIFT 16 +/* PLLN: [14:6] */ +#define RCC_PLLCFGR_PLLN_SHIFT 6 +/* PLLM: [5:0] */ +#define RCC_PLLCFGR_PLLM_SHIFT 0 + +/* --- RCC_CFGR values ----------------------------------------------------- */ + +/* MCO2: Microcontroller clock output 2 */ +#define RCC_CFGR_MCO2_SHIFT 30 +#define RCC_CFGR_MCO2_SYSCLK 0x0 +#define RCC_CFGR_MCO2_PLLI2S 0x1 +#define RCC_CFGR_MCO2_HSE 0x2 +#define RCC_CFGR_MCO2_PLL 0x3 + +/* MCO1/2PRE: MCO Prescalers */ +#define RCC_CFGR_MCO2PRE_SHIFT 27 +#define RCC_CFGR_MCO1PRE_SHIFT 24 +#define RCC_CFGR_MCOPRE_DIV_NONE 0x0 +#define RCC_CFGR_MCOPRE_DIV_2 0x4 +#define RCC_CFGR_MCOPRE_DIV_3 0x5 +#define RCC_CFGR_MCOPRE_DIV_4 0x6 +#define RCC_CFGR_MCOPRE_DIV_5 0x7 + +/* I2SSRC: I2S clock selection */ +#define RCC_CFGR_I2SSRC (1 << 23) + +/* MCO1: Microcontroller clock output 1 */ +#define RCC_CFGR_MCO1_SHIFT 21 +#define RCC_CFGR_MCO1_HSI 0x0 +#define RCC_CFGR_MCO1_LSE 0x1 +#define RCC_CFGR_MCO1_HSE 0x2 +#define RCC_CFGR_MCO1_PLL 0x3 + +/* RTCPRE: HSE division factor for RTC clock */ +#define RCC_CFGR_RTCPRE_SHIFT 21 + +/* PPRE1/2: APB high-speed prescalers */ +#define RCC_CFGR_PPRE2_SHIFT 13 +#define RCC_CFGR_PPRE1_SHIFT 10 +#define RCC_CFGR_PPRE_DIV_NONE 0x0 +#define RCC_CFGR_PPRE_DIV_2 0x4 +#define RCC_CFGR_PPRE_DIV_4 0x5 +#define RCC_CFGR_PPRE_DIV_8 0x6 +#define RCC_CFGR_PPRE_DIV_16 0x7 + +/* HPRE: AHB high-speed prescaler */ +#define RCC_CFGR_HPRE_SHIFT 4 +#define RCC_CFGR_HPRE_DIV_NONE 0x0 +#define RCC_CFGR_HPRE_DIV_2 (0x8+0) +#define RCC_CFGR_HPRE_DIV_4 (0x8+1) +#define RCC_CFGR_HPRE_DIV_8 (0x8+2) +#define RCC_CFGR_HPRE_DIV_16 (0x8+3) +#define RCC_CFGR_HPRE_DIV_64 (0x8+4) +#define RCC_CFGR_HPRE_DIV_128 (0x8+5) +#define RCC_CFGR_HPRE_DIV_256 (0x8+6) +#define RCC_CFGR_HPRE_DIV_512 (0x8+7) + +/* SWS: System clock switch status */ +#define RCC_CFGR_SWS_SHIFT 2 +#define RCC_CFGR_SWS_HSI 0x0 +#define RCC_CFGR_SWS_HSE 0x1 +#define RCC_CFGR_SWS_PLL 0x2 + +/* SW: System clock switch */ +#define RCC_CFGR_SW_SHIFT 0 +#define RCC_CFGR_SW_HSI 0x0 +#define RCC_CFGR_SW_HSE 0x1 +#define RCC_CFGR_SW_PLL 0x2 + +/* --- RCC_CIR values ------------------------------------------------------ */ + +/* Clock security system interrupt clear bit */ +#define RCC_CIR_CSSC (1 << 23) + +/* OSC ready interrupt clear bits */ +#define RCC_CIR_PLLI2SRDYC (1 << 21) +#define RCC_CIR_PLLRDYC (1 << 20) +#define RCC_CIR_HSERDYC (1 << 19) +#define RCC_CIR_HSIRDYC (1 << 18) +#define RCC_CIR_LSERDYC (1 << 17) +#define RCC_CIR_LSIRDYC (1 << 16) + +/* OSC ready interrupt enable bits */ +#define RCC_CIR_PLLI2SRDYIE (1 << 13) +#define RCC_CIR_PLLRDYIE (1 << 12) +#define RCC_CIR_HSERDYIE (1 << 11) +#define RCC_CIR_HSIRDYIE (1 << 10) +#define RCC_CIR_LSERDYIE (1 << 9) +#define RCC_CIR_LSIRDYIE (1 << 8) + +/* Clock security system interrupt flag bit */ +#define RCC_CIR_CSSF (1 << 7) + +/* OSC ready interrupt flag bits */ +#define RCC_CIR_PLLI2SRDYF (1 << 5) +#define RCC_CIR_PLLRDYF (1 << 4) +#define RCC_CIR_HSERDYF (1 << 3) +#define RCC_CIR_HSIRDYF (1 << 2) +#define RCC_CIR_LSERDYF (1 << 1) +#define RCC_CIR_LSIRDYF (1 << 0) + +/* --- RCC_AHB1RSTR values ------------------------------------------------- */ + +#define RCC_AHB1RSTR_OTGHSRST (1 << 29) +#define RCC_AHB1RSTR_ETHMACRST (1 << 25) +#define RCC_AHB1RSTR_DMA2RST (1 << 22) +#define RCC_AHB1RSTR_DMA1RST (1 << 21) +#define RCC_AHB1RSTR_CRCRST (1 << 12) +#define RCC_AHB1RSTR_GPIOIRST (1 << 8) +#define RCC_AHB1RSTR_GPIOHRST (1 << 7) +#define RCC_AHB1RSTR_GPIOGRST (1 << 6) +#define RCC_AHB1RSTR_GPIOFRST (1 << 5) +#define RCC_AHB1RSTR_GPIOERST (1 << 4) +#define RCC_AHB1RSTR_GPIODRST (1 << 3) +#define RCC_AHB1RSTR_GPIOCRST (1 << 2) +#define RCC_AHB1RSTR_GPIOBRST (1 << 1) +#define RCC_AHB1RSTR_GPIOARST (1 << 0) + +/* --- RCC_AHB2RSTR values ------------------------------------------------- */ + +#define RCC_AHB2RSTR_OTGFSRST (1 << 7) +#define RCC_AHB2RSTR_RNGRST (1 << 6) +#define RCC_AHB2RSTR_HASHRST (1 << 5) +#define RCC_AHB2RSTR_CRYPRST (1 << 4) +#define RCC_AHB2RSTR_DCMIRST (1 << 0) + +/* --- RCC_AHB3RSTR values ------------------------------------------------- */ + +#define RCC_AHB3RSTR_FSMCRST (1 << 0) + +/* --- RCC_APB1RSTR values ------------------------------------------------- */ + +#define RCC_APB1RSTR_DACRST (1 << 29) +#define RCC_APB1RSTR_PWRRST (1 << 28) +#define RCC_APB1RSTR_CAN2RST (1 << 26) +#define RCC_APB1RSTR_CAN1RST (1 << 25) +#define RCC_APB1RSTR_I2C3RST (1 << 23) +#define RCC_APB1RSTR_I2C2RST (1 << 22) +#define RCC_APB1RSTR_I2C1RST (1 << 21) +#define RCC_APB1RSTR_USART5RST (1 << 20) +#define RCC_APB1RSTR_USART4RST (1 << 19) +#define RCC_APB1RSTR_USART3RST (1 << 18) +#define RCC_APB1RSTR_USART2RST (1 << 17) +#define RCC_APB1RSTR_SPI3RST (1 << 15) +#define RCC_APB1RSTR_SPI2RST (1 << 14) +#define RCC_APB1RSTR_WWDGRST (1 << 11) +#define RCC_APB1RSTR_TIM14RST (1 << 8) +#define RCC_APB1RSTR_TIM13RST (1 << 7) +#define RCC_APB1RSTR_TIM12RST (1 << 6) +#define RCC_APB1RSTR_TIM7RST (1 << 5) +#define RCC_APB1RSTR_TIM6RST (1 << 4) +#define RCC_APB1RSTR_TIM5RST (1 << 3) +#define RCC_APB1RSTR_TIM4RST (1 << 2) +#define RCC_APB1RSTR_TIM3RST (1 << 1) +#define RCC_APB1RSTR_TIM2RST (1 << 0) + +/* --- RCC_APB2RSTR values ------------------------------------------------- */ + +#define RCC_APB2RSTR_TIM11RST (1 << 18) +#define RCC_APB2RSTR_TIM10RST (1 << 17) +#define RCC_APB2RSTR_TIM9RST (1 << 16) +#define RCC_APB2RSTR_SYSCFGRST (1 << 14) +#define RCC_APB2RSTR_SPI1RST (1 << 12) +#define RCC_APB2RSTR_SDIORST (1 << 11) +#define RCC_APB2RSTR_ADCRST (1 << 8) +#define RCC_APB2RSTR_USART6RST (1 << 5) +#define RCC_APB2RSTR_USART1RST (1 << 4) +#define RCC_APB2RSTR_TIM8RST (1 << 1) +#define RCC_APB2RSTR_TIM1RST (1 << 0) + +/* --- RCC_AHB1ENR values ------------------------------------------------- */ + +#define RCC_AHB1ENR_OTGHSULPIEN (1 << 30) +#define RCC_AHB1ENR_OTGHSEN (1 << 29) +#define RCC_AHB1ENR_ETHMACPTPEN (1 << 28) +#define RCC_AHB1ENR_ETHMACRXEN (1 << 27) +#define RCC_AHB1ENR_ETHMACTXEN (1 << 26) +#define RCC_AHB1ENR_ETHMACEN (1 << 25) +#define RCC_AHB1ENR_DMA2EN (1 << 22) +#define RCC_AHB1ENR_DMA1EN (1 << 21) +#define RCC_AHB1ENR_BKPSRAMEN (1 << 18) +#define RCC_AHB1ENR_CRCEN (1 << 12) +#define RCC_AHB1ENR_GPIOIEN (1 << 8) +#define RCC_AHB1ENR_GPIOHEN (1 << 7) +#define RCC_AHB1ENR_GPIOGEN (1 << 6) +#define RCC_AHB1ENR_GPIOFEN (1 << 5) +#define RCC_AHB1ENR_GPIOEEN (1 << 4) +#define RCC_AHB1ENR_GPIODEN (1 << 3) +#define RCC_AHB1ENR_GPIOCEN (1 << 2) +#define RCC_AHB1ENR_GPIOBEN (1 << 1) +#define RCC_AHB1ENR_GPIOAEN (1 << 0) + +/* --- RCC_AHB2ENR values ------------------------------------------------- */ + +#define RCC_AHB2ENR_OTGFSEN (1 << 7) +#define RCC_AHB2ENR_RNGEN (1 << 6) +#define RCC_AHB2ENR_HASHEN (1 << 5) +#define RCC_AHB2ENR_CRYPEN (1 << 4) +#define RCC_AHB2ENR_DCMIEN (1 << 0) + +/* --- RCC_AHB3ENR values ------------------------------------------------- */ + +#define RCC_AHB3ENR_FSMCEN (1 << 0) + +/* --- RCC_APB1ENR values ------------------------------------------------- */ + +#define RCC_APB1ENR_DACEN (1 << 29) +#define RCC_APB1ENR_PWREN (1 << 28) +#define RCC_APB1ENR_CAN2EN (1 << 26) +#define RCC_APB1ENR_CAN1EN (1 << 25) +#define RCC_APB1ENR_I2C3EN (1 << 23) +#define RCC_APB1ENR_I2C2EN (1 << 22) +#define RCC_APB1ENR_I2C1EN (1 << 21) +#define RCC_APB1ENR_USART5EN (1 << 20) +#define RCC_APB1ENR_USART4EN (1 << 19) +#define RCC_APB1ENR_USART3EN (1 << 18) +#define RCC_APB1ENR_USART2EN (1 << 17) +#define RCC_APB1ENR_SPI3EN (1 << 15) +#define RCC_APB1ENR_SPI2EN (1 << 14) +#define RCC_APB1ENR_WWDGEN (1 << 11) +#define RCC_APB1ENR_TIM14EN (1 << 8) +#define RCC_APB1ENR_TIM13EN (1 << 7) +#define RCC_APB1ENR_TIM12EN (1 << 6) +#define RCC_APB1ENR_TIM7EN (1 << 5) +#define RCC_APB1ENR_TIM6EN (1 << 4) +#define RCC_APB1ENR_TIM5EN (1 << 3) +#define RCC_APB1ENR_TIM4EN (1 << 2) +#define RCC_APB1ENR_TIM3EN (1 << 1) +#define RCC_APB1ENR_TIM2EN (1 << 0) + +/* --- RCC_APB2ENR values ------------------------------------------------- */ + +#define RCC_APB2ENR_TIM11EN (1 << 18) +#define RCC_APB2ENR_TIM10EN (1 << 17) +#define RCC_APB2ENR_TIM9EN (1 << 16) +#define RCC_APB2ENR_SYSCFGEN (1 << 14) +#define RCC_APB2ENR_SPI1EN (1 << 12) +#define RCC_APB2ENR_SDIOEN (1 << 11) +#define RCC_APB2ENR_ADC3EN (1 << 10) +#define RCC_APB2ENR_ADC2EN (1 << 9) +#define RCC_APB2ENR_ADC1EN (1 << 8) +#define RCC_APB2ENR_USART6EN (1 << 5) +#define RCC_APB2ENR_USART1EN (1 << 4) +#define RCC_APB2ENR_TIM8EN (1 << 1) +#define RCC_APB2ENR_TIM1EN (1 << 0) + +/* --- RCC_AHB1LPENR values ------------------------------------------------- */ + +#define RCC_AHB1LPENR_OTGHSULPILPEN (1 << 30) +#define RCC_AHB1LPENR_OTGHSLPEN (1 << 29) +#define RCC_AHB1LPENR_ETHMACPTPLPEN (1 << 28) +#define RCC_AHB1LPENR_ETHMACRXLPEN (1 << 27) +#define RCC_AHB1LPENR_ETHMACTXLPEN (1 << 26) +#define RCC_AHB1LPENR_ETHMACLPEN (1 << 25) +#define RCC_AHB1LPENR_DMA2LPEN (1 << 22) +#define RCC_AHB1LPENR_DMA1LPEN (1 << 21) +#define RCC_AHB1LPENR_BKPSRAMLPEN (1 << 18) +#define RCC_AHB1LPENR_SRAM2LPEN (1 << 17) +#define RCC_AHB1LPENR_SRAM1LPEN (1 << 16) +#define RCC_AHB1LPENR_FLITFLPEN (1 << 15) +#define RCC_AHB1LPENR_CRCLPEN (1 << 12) +#define RCC_AHB1LPENR_GPIOILPEN (1 << 8) +#define RCC_AHB1LPENR_GPIOHLPEN (1 << 7) +#define RCC_AHB1LPENR_GPIOGLPEN (1 << 6) +#define RCC_AHB1LPENR_GPIOFLPEN (1 << 5) +#define RCC_AHB1LPENR_GPIOELPEN (1 << 4) +#define RCC_AHB1LPENR_GPIODLPEN (1 << 3) +#define RCC_AHB1LPENR_GPIOCLPEN (1 << 2) +#define RCC_AHB1LPENR_GPIOBLPEN (1 << 1) +#define RCC_AHB1LPENR_GPIOALPEN (1 << 0) + +/* --- RCC_AHB2LPENR values ------------------------------------------------- */ + +#define RCC_AHB2LPENR_OTGFSLPEN (1 << 7) +#define RCC_AHB2LPENR_RNGLPEN (1 << 6) +#define RCC_AHB2LPENR_HASHLPEN (1 << 5) +#define RCC_AHB2LPENR_CRYPLPEN (1 << 4) +#define RCC_AHB2LPENR_DCMILPEN (1 << 0) + +/* --- RCC_AHB3LPENR values ------------------------------------------------- */ + +#define RCC_AHB3LPENR_FSMCLPEN (1 << 0) + +/* --- RCC_APB1LPENR values ------------------------------------------------- */ + +#define RCC_APB1LPENR_DACLPEN (1 << 29) +#define RCC_APB1LPENR_PWRLPEN (1 << 28) +#define RCC_APB1LPENR_CAN2LPEN (1 << 26) +#define RCC_APB1LPENR_CAN1LPEN (1 << 25) +#define RCC_APB1LPENR_I2C3LPEN (1 << 23) +#define RCC_APB1LPENR_I2C2LPEN (1 << 22) +#define RCC_APB1LPENR_I2C1LPEN (1 << 21) +#define RCC_APB1LPENR_USART5LPEN (1 << 20) +#define RCC_APB1LPENR_USART4LPEN (1 << 19) +#define RCC_APB1LPENR_USART3LPEN (1 << 18) +#define RCC_APB1LPENR_USART2LPEN (1 << 17) +#define RCC_APB1LPENR_SPI3LPEN (1 << 15) +#define RCC_APB1LPENR_SPI2LPEN (1 << 14) +#define RCC_APB1LPENR_WWDGLPEN (1 << 11) +#define RCC_APB1LPENR_TIM14LPEN (1 << 8) +#define RCC_APB1LPENR_TIM13LPEN (1 << 7) +#define RCC_APB1LPENR_TIM12LPEN (1 << 6) +#define RCC_APB1LPENR_TIM7LPEN (1 << 5) +#define RCC_APB1LPENR_TIM6LPEN (1 << 4) +#define RCC_APB1LPENR_TIM5LPEN (1 << 3) +#define RCC_APB1LPENR_TIM4LPEN (1 << 2) +#define RCC_APB1LPENR_TIM3LPEN (1 << 1) +#define RCC_APB1LPENR_TIM2LPEN (1 << 0) + +/* --- RCC_APB2LPENR values ------------------------------------------------- */ + +#define RCC_APB2LPENR_TIM11LPEN (1 << 18) +#define RCC_APB2LPENR_TIM10LPEN (1 << 17) +#define RCC_APB2LPENR_TIM9LPEN (1 << 16) +#define RCC_APB2LPENR_SYSCFGLPEN (1 << 14) +#define RCC_APB2LPENR_SPI1LPEN (1 << 12) +#define RCC_APB2LPENR_SDIOLPEN (1 << 11) +#define RCC_APB2LPENR_ADC3LPEN (1 << 10) +#define RCC_APB2LPENR_ADC2LPEN (1 << 9) +#define RCC_APB2LPENR_ADC1LPEN (1 << 8) +#define RCC_APB2LPENR_USART6LPEN (1 << 5) +#define RCC_APB2LPENR_USART1LPEN (1 << 4) +#define RCC_APB2LPENR_TIM8LPEN (1 << 1) +#define RCC_APB2LPENR_TIM1LPEN (1 << 0) + +/* --- RCC_BDCR values ----------------------------------------------------- */ + +#define RCC_BDCR_BDRST (1 << 16) +#define RCC_BDCR_RTCEN (1 << 15) +/* RCC_BDCR[9:8]: RTCSEL */ +#define RCC_BDCR_LSEBYP (1 << 2) +#define RCC_BDCR_LSERDY (1 << 1) +#define RCC_BDCR_LSEON (1 << 0) + +/* --- RCC_CSR values ------------------------------------------------------ */ + +#define RCC_CSR_LPWRRSTF (1 << 31) +#define RCC_CSR_WWDGRSTF (1 << 30) +#define RCC_CSR_IWDGRSTF (1 << 29) +#define RCC_CSR_SFTRSTF (1 << 28) +#define RCC_CSR_PORRSTF (1 << 27) +#define RCC_CSR_PINRSTF (1 << 26) +#define RCC_CSR_BORRSTF (1 << 26) +#define RCC_CSR_RMVF (1 << 24) +#define RCC_CSR_LSIRDY (1 << 1) +#define RCC_CSR_LSION (1 << 0) + +/* --- RCC_SSCGR values ---------------------------------------------------- */ + +/* PLL spread spectrum clock generation documented in Datasheet. */ + +#define RCC_SSCGR_SSCGEN (1 << 31) +#define RCC_SSCGR_SPREADSEL (1 << 30) +/* RCC_SSCGR[27:16]: INCSTEP */ +#define RCC_SSCGR_INCSTEP_SHIFT 16 +/* RCC_SSCGR[15:0]: MODPER */ +#define RCC_SSCGR_MODPER_SHIFT 15 + +/* --- RCC_PLLI2SCFGR values ----------------------------------------------- */ + +/* RCC_PLLI2SCFGR[30:28]: PLLI2SR */ +#define RCC_PLLI2SCFGR_PLLI2SR_SHIFT 28 +/* RCC_PLLI2SCFGR[14:6]: PLLI2SN */ +#define RCC_PLLI2SCFGR_PLLI2SN_SHIFT 6 + + +#endif -- cgit v1.2.3 From 7133e792398b87695fa73bb344c8d3d0cb08bb23 Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Fri, 16 Sep 2011 23:14:07 -0700 Subject: Change default prefix in Makefiles to arm-none-eabi for compatability with summon toolchain out the box. --- examples/stm32f2/Makefile.include | 2 +- lib/stm32f2/Makefile | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/examples/stm32f2/Makefile.include b/examples/stm32f2/Makefile.include index 6ec9f65..9cec6e7 100644 --- a/examples/stm32f2/Makefile.include +++ b/examples/stm32f2/Makefile.include @@ -20,7 +20,7 @@ ## PREFIX ?= arm-none-eabi -#PREFIX ?= arm-elf +# PREFIX ?= arm-elf CC = $(PREFIX)-gcc LD = $(PREFIX)-gcc OBJCOPY = $(PREFIX)-objcopy diff --git a/lib/stm32f2/Makefile b/lib/stm32f2/Makefile index cd50c4b..5da64ab 100644 --- a/lib/stm32f2/Makefile +++ b/lib/stm32f2/Makefile @@ -19,8 +19,8 @@ LIBNAME = libopencm3_stm32f2 -# PREFIX ?= arm-none-eabi -PREFIX ?= arm-elf +PREFIX ?= arm-none-eabi +# PREFIX ?= arm-elf CC = $(PREFIX)-gcc AR = $(PREFIX)-ar CFLAGS = -Os -g -Wall -Wextra -I../../include -fno-common \ @@ -28,7 +28,7 @@ CFLAGS = -Os -g -Wall -Wextra -I../../include -fno-common \ -ffunction-sections -fdata-sections -MD -DSTM32F2 # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = vector.o gpio.o systick.o i2c.o spi.o nvic.o +OBJS = vector.o gpio.o systick.o i2c.o spi.o nvic.o usart.o #VPATH += ../usb VPATH += ../stm32_common -- cgit v1.2.3 From d1272acaad8bb7dc41b81bd0c7a9728b7d308422 Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Thu, 22 Sep 2011 13:52:43 -0700 Subject: Initial move of USART code to common, still needs some work. --- include/libopencm3/stm32/usart.h | 2 +- lib/stm32_common/usart.c | 129 ++++++++++++++++++++++++++++++++++++++ lib/stm32f1/usart.c | 131 --------------------------------------- 3 files changed, 130 insertions(+), 132 deletions(-) create mode 100644 lib/stm32_common/usart.c delete mode 100644 lib/stm32f1/usart.c diff --git a/include/libopencm3/stm32/usart.h b/include/libopencm3/stm32/usart.h index df6bc08..51b96f2 100644 --- a/include/libopencm3/stm32/usart.h +++ b/include/libopencm3/stm32/usart.h @@ -294,7 +294,7 @@ /* --- Function prototypes ------------------------------------------------- */ -void usart_set_baudrate(u32 usart, u32 baud); +void usart_set_baudrate(u32 usart, u32 baud, u32 clock); void usart_set_databits(u32 usart, u32 bits); void usart_set_stopbits(u32 usart, u32 stopbits); void usart_set_parity(u32 usart, u32 parity); diff --git a/lib/stm32_common/usart.c b/lib/stm32_common/usart.c new file mode 100644 index 0000000..026af3a --- /dev/null +++ b/lib/stm32_common/usart.c @@ -0,0 +1,129 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include + +void usart_set_baudrate(u32 usart, u32 baud, u32 clock) +{ + //u32 clock = rcc_ppre1_frequency; + + //if (usart == USART1) { + // clock = rcc_ppre2_frequency; + //} + + /* yes it is as simple as that. The reference manual is + * talking about factional calculation but it seems to be only + * marketting bable to sound awesome. It is nothing else but a + * simple divider to generate the correct baudrate. >_< If I + * am wrong feel free to correct me on that. :) (esden) + */ + USART_BRR(usart) = clock/baud; +} + +void usart_set_databits(u32 usart, u32 bits) +{ + if (bits == 8) + USART_CR1(usart) &= ~USART_CR1_M; /* 8 data bits */ + else + USART_CR1(usart) |= USART_CR1_M; /* 9 data bits */ +} + +void usart_set_stopbits(u32 usart, u32 stopbits) +{ + u32 reg32; + + reg32 = USART_CR2(usart); + reg32 = (reg32 & ~USART_CR2_STOPBITS_MASK) | stopbits; + USART_CR2(usart) = reg32; +} + +void usart_set_parity(u32 usart, u32 parity) +{ + u32 reg32; + + reg32 = USART_CR1(usart); + reg32 = (reg32 & ~USART_PARITY_MASK) | parity; + USART_CR1(usart) = reg32; +} + +void usart_set_mode(u32 usart, u32 mode) +{ + u32 reg32; + + reg32 = USART_CR1(usart); + reg32 = (reg32 & ~USART_MODE_MASK) | mode; + USART_CR1(usart) = reg32; +} + +void usart_set_flow_control(u32 usart, u32 flowcontrol) +{ + u32 reg32; + + reg32 = USART_CR3(usart); + reg32 = (reg32 & ~USART_FLOWCONTROL_MASK) | flowcontrol; + USART_CR3(usart) = reg32; +} + +void usart_enable(u32 usart) +{ + USART_CR1(usart) |= USART_CR1_UE; +} + +void usart_disable(u32 usart) +{ + USART_CR1(usart) &= ~USART_CR1_UE; +} + +void usart_send(u32 usart, u16 data) +{ + /* Send data. */ + USART_DR(usart) = (data & USART_DR_MASK); +} + +u16 usart_recv(u32 usart) +{ + /* Receive data. */ + return USART_DR(usart) & USART_DR_MASK; +} + +void usart_wait_send_ready(u32 usart) +{ + /* Wait until the data has been transferred into the shift register. */ + while ((USART_SR(usart) & USART_SR_TXE) == 0); +} + +void usart_wait_recv_ready(u32 usart) +{ + /* Wait until the data is ready to be received. */ + while ((USART_SR(usart) & USART_SR_RXNE) == 0); +} + +void usart_send_blocking(u32 usart, u16 data) +{ + usart_send(usart, data); + + usart_wait_send_ready(usart); +} + +u16 usart_recv_blocking(u32 usart) +{ + usart_wait_recv_ready(usart); + + return usart_recv(usart); +} diff --git a/lib/stm32f1/usart.c b/lib/stm32f1/usart.c deleted file mode 100644 index 73e450b..0000000 --- a/lib/stm32f1/usart.c +++ /dev/null @@ -1,131 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include - -#include - -void usart_set_baudrate(u32 usart, u32 baud) -{ - u32 clock = rcc_ppre1_frequency; - - if (usart == USART1) { - clock = rcc_ppre2_frequency; - } - - /* yes it is as simple as that. The reference manual is - * talking about factional calculation but it seems to be only - * marketting bable to sound awesome. It is nothing else but a - * simple divider to generate the correct baudrate. >_< If I - * am wrong feel free to correct me on that. :) (esden) - */ - USART_BRR(usart) = clock/baud; -} - -void usart_set_databits(u32 usart, u32 bits) -{ - if (bits == 8) - USART_CR1(usart) &= ~USART_CR1_M; /* 8 data bits */ - else - USART_CR1(usart) |= USART_CR1_M; /* 9 data bits */ -} - -void usart_set_stopbits(u32 usart, u32 stopbits) -{ - u32 reg32; - - reg32 = USART_CR2(usart); - reg32 = (reg32 & ~USART_CR2_STOPBITS_MASK) | stopbits; - USART_CR2(usart) = reg32; -} - -void usart_set_parity(u32 usart, u32 parity) -{ - u32 reg32; - - reg32 = USART_CR1(usart); - reg32 = (reg32 & ~USART_PARITY_MASK) | parity; - USART_CR1(usart) = reg32; -} - -void usart_set_mode(u32 usart, u32 mode) -{ - u32 reg32; - - reg32 = USART_CR1(usart); - reg32 = (reg32 & ~USART_MODE_MASK) | mode; - USART_CR1(usart) = reg32; -} - -void usart_set_flow_control(u32 usart, u32 flowcontrol) -{ - u32 reg32; - - reg32 = USART_CR3(usart); - reg32 = (reg32 & ~USART_FLOWCONTROL_MASK) | flowcontrol; - USART_CR3(usart) = reg32; -} - -void usart_enable(u32 usart) -{ - USART_CR1(usart) |= USART_CR1_UE; -} - -void usart_disable(u32 usart) -{ - USART_CR1(usart) &= ~USART_CR1_UE; -} - -void usart_send(u32 usart, u16 data) -{ - /* Send data. */ - USART_DR(usart) = (data & USART_DR_MASK); -} - -u16 usart_recv(u32 usart) -{ - /* Receive data. */ - return USART_DR(usart) & USART_DR_MASK; -} - -void usart_wait_send_ready(u32 usart) -{ - /* Wait until the data has been transferred into the shift register. */ - while ((USART_SR(usart) & USART_SR_TXE) == 0); -} - -void usart_wait_recv_ready(u32 usart) -{ - /* Wait until the data is ready to be received. */ - while ((USART_SR(usart) & USART_SR_RXNE) == 0); -} - -void usart_send_blocking(u32 usart, u16 data) -{ - usart_send(usart, data); - - usart_wait_send_ready(usart); -} - -u16 usart_recv_blocking(u32 usart) -{ - usart_wait_recv_ready(usart); - - return usart_recv(usart); -} -- cgit v1.2.3 From fae6f83bb96bbe0b69b433d42253081574bcabc4 Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Thu, 22 Sep 2011 13:53:10 -0700 Subject: Adding jobygps usart example. --- examples/stm32f2/jobygps/usart_printf/Makefile | 23 +++++ .../stm32f2/jobygps/usart_printf/usart_printf.c | 110 +++++++++++++++++++++ .../stm32f2/jobygps/usart_printf/usart_printf.ld | 31 ++++++ 3 files changed, 164 insertions(+) create mode 100644 examples/stm32f2/jobygps/usart_printf/Makefile create mode 100644 examples/stm32f2/jobygps/usart_printf/usart_printf.c create mode 100644 examples/stm32f2/jobygps/usart_printf/usart_printf.ld diff --git a/examples/stm32f2/jobygps/usart_printf/Makefile b/examples/stm32f2/jobygps/usart_printf/Makefile new file mode 100644 index 0000000..fb26208 --- /dev/null +++ b/examples/stm32f2/jobygps/usart_printf/Makefile @@ -0,0 +1,23 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +## + +BINARY = usart_printf + +include ../../Makefile.include + diff --git a/examples/stm32f2/jobygps/usart_printf/usart_printf.c b/examples/stm32f2/jobygps/usart_printf/usart_printf.c new file mode 100644 index 0000000..b03b842 --- /dev/null +++ b/examples/stm32f2/jobygps/usart_printf/usart_printf.c @@ -0,0 +1,110 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann , + * 2011 Piotr Esden-Tempski + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include + +#include +#include + +void clock_setup(void) +{ + //rcc_clock_setup_in_hse_8mhz_out_72mhz(); + + /* Enable GPIOA clock (for LED GPIOs). */ + //rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); + + /* Enable clocks for GPIO port A (for GPIO_USART1_TX) and USART1. */ + //rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN | +// RCC_APB2ENR_AFIOEN | +// RCC_APB2ENR_USART1EN); + RCC_APB2ENR |= RCC_APB2ENR_USART1EN; + RCC_AHB1ENR |= RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIOAEN; +} + +void usart_setup(void) +{ + //gpio_mode_setup(GPIOA, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO9); + GPIO_MODER(GPIOA) |= GPIO_MODE(9, GPIO_MODE_AF); + gpio_set_af(GPIOA, GPIO_AF7, GPIO9|GPIO10); + + /* Setup UART parameters. */ + usart_set_baudrate(USART1, 9600, 16000000); + usart_set_databits(USART1, 8); + usart_set_stopbits(USART1, USART_STOPBITS_1); + usart_set_parity(USART1, USART_PARITY_NONE); + usart_set_flow_control(USART1, USART_FLOWCONTROL_NONE); + usart_set_mode(USART1, USART_MODE_TX); + + /* Finally enable the USART. */ + usart_enable(USART1); +} + +void gpio_setup(void) +{ + gpio_set(GPIOC, GPIO3); + + /* Setup GPIO6 and 7 (in GPIO port A) for led use. */ + gpio_mode_setup(GPIOC, GPIO_MODE_OUTPUT, + GPIO_MODE_OUTPUT, GPIO3); +} + +int _write (int file, char *ptr, int len) +{ + int i; + + if (file == 1) { + for (i = 0; i < len; i++){ + usart_send_blocking(USART1, ptr[i]); + } + + return i; + } + + errno = EIO; + return -1; +} + +int main(void) +{ + int counter = 0; + float fcounter = 0.0; + double dcounter = 0.0; + + clock_setup(); + gpio_setup(); + usart_setup(); + + /* + * Write Hello World an integer, float and double all over + * again while incrementing the numbers. + */ + while (1) { + gpio_toggle(GPIOC, GPIO3); + printf("Hello World! %i %f %f\r\n", counter, fcounter, dcounter); + counter++; + fcounter+=0.01; + dcounter+=0.01; + } + + return 0; +} diff --git a/examples/stm32f2/jobygps/usart_printf/usart_printf.ld b/examples/stm32f2/jobygps/usart_printf/usart_printf.ld new file mode 100644 index 0000000..7899773 --- /dev/null +++ b/examples/stm32f2/jobygps/usart_printf/usart_printf.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Linker script for Open-BLDC (STM32F103CBT6, 128K flash, 20K RAM). */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32.ld + -- cgit v1.2.3 From 1a555c9646ddfe2dd6ff67fbeb8d0324c129786f Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Thu, 22 Sep 2011 13:53:30 -0700 Subject: OpenOCD config file for JobyGPS. --- examples/stm32f2/jobygps/jobygps.cfg | 3 +++ 1 file changed, 3 insertions(+) create mode 100644 examples/stm32f2/jobygps/jobygps.cfg diff --git a/examples/stm32f2/jobygps/jobygps.cfg b/examples/stm32f2/jobygps/jobygps.cfg new file mode 100644 index 0000000..7ca449e --- /dev/null +++ b/examples/stm32f2/jobygps/jobygps.cfg @@ -0,0 +1,3 @@ +reset_config srst_only srst_push_pull +source [find target/stm32f2x.cfg] + -- cgit v1.2.3 From 53f1c75c53f856af7a46cebc3e68a68c0a89036d Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Thu, 22 Sep 2011 14:23:25 -0700 Subject: Fixed bug in F2 GPIO code. --- lib/stm32f2/gpio.c | 19 +------------------ 1 file changed, 1 insertion(+), 18 deletions(-) diff --git a/lib/stm32f2/gpio.c b/lib/stm32f2/gpio.c index 2330628..abb08c0 100644 --- a/lib/stm32f2/gpio.c +++ b/lib/stm32f2/gpio.c @@ -17,29 +17,12 @@ * along with this program. If not, see . */ -/* - * Basic GPIO handling API. - * - * Examples: - * gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_2_MHZ, - * GPIO_CNF_OUTPUT_PUSHPULL, GPIO12); - * gpio_set(GPIOB, GPIO4); - * gpio_clear(GPIOG, GPIO2 | GPIO9); - * gpio_get(GPIOC, GPIO1); - * gpio_toggle(GPIOA, GPIO7 | GPIO8); - * reg16 = gpio_port_read(GPIOD); - * gpio_port_write(GPIOF, 0xc8fe); - * - * TODO: - * - GPIO remapping support - */ - #include void gpio_mode_setup(u32 gpioport, u8 mode, u8 pull_up_down, u16 gpios) { u16 i; - u16 moder, pupd; + u32 moder, pupd; /* * We want to set the config only for the pins mentioned in gpios, -- cgit v1.2.3 From c4c9d6ca112b104301152fcdea3a487ed0e42bb9 Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Thu, 22 Sep 2011 14:23:49 -0700 Subject: Updating the usart example in jobygps to use fixed gpio code. --- examples/stm32f2/jobygps/usart_printf/usart_printf.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/examples/stm32f2/jobygps/usart_printf/usart_printf.c b/examples/stm32f2/jobygps/usart_printf/usart_printf.c index b03b842..f5a4cf5 100644 --- a/examples/stm32f2/jobygps/usart_printf/usart_printf.c +++ b/examples/stm32f2/jobygps/usart_printf/usart_printf.c @@ -43,8 +43,7 @@ void clock_setup(void) void usart_setup(void) { - //gpio_mode_setup(GPIOA, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO9); - GPIO_MODER(GPIOA) |= GPIO_MODE(9, GPIO_MODE_AF); + gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO9); gpio_set_af(GPIOA, GPIO_AF7, GPIO9|GPIO10); /* Setup UART parameters. */ -- cgit v1.2.3 From ef8f8d831e83fcba4573404b588142853dd226fb Mon Sep 17 00:00:00 2001 From: Henry Hallam Date: Thu, 22 Sep 2011 16:04:42 -0700 Subject: SPI test (untested) --- examples/stm32f2/jobygps/spi_test/Makefile | 23 +++++ examples/stm32f2/jobygps/spi_test/spi_test.c | 122 ++++++++++++++++++++++++++ examples/stm32f2/jobygps/spi_test/spi_test.ld | 31 +++++++ 3 files changed, 176 insertions(+) create mode 100644 examples/stm32f2/jobygps/spi_test/Makefile create mode 100644 examples/stm32f2/jobygps/spi_test/spi_test.c create mode 100644 examples/stm32f2/jobygps/spi_test/spi_test.ld diff --git a/examples/stm32f2/jobygps/spi_test/Makefile b/examples/stm32f2/jobygps/spi_test/Makefile new file mode 100644 index 0000000..de4c338 --- /dev/null +++ b/examples/stm32f2/jobygps/spi_test/Makefile @@ -0,0 +1,23 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +## + +BINARY = spi_test + +include ../../Makefile.include + diff --git a/examples/stm32f2/jobygps/spi_test/spi_test.c b/examples/stm32f2/jobygps/spi_test/spi_test.c new file mode 100644 index 0000000..2145165 --- /dev/null +++ b/examples/stm32f2/jobygps/spi_test/spi_test.c @@ -0,0 +1,122 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann , + * 2011 Piotr Esden-Tempski + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include + +#include +#include + +void clock_setup(void) +{ + //rcc_clock_setup_in_hse_8mhz_out_72mhz(); + + /* Enable GPIOA clock (for LED GPIOs). */ + //rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); + + /* Enable clocks for GPIO port A (for GPIO_USART1_TX) and USART1. */ + //rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN | +// RCC_APB2ENR_AFIOEN | +// RCC_APB2ENR_USART1EN); + RCC_APB1ENR |= RCC_APB1ENR_SPI2EN; + RCC_APB2ENR |= RCC_APB2ENR_USART1EN; + RCC_AHB1ENR |= RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIOAEN; // PORT B not enabled... + +} + +void spi_setup(void) +{ + gpio_mode_setup(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO12 | GPIO13 | GPIO14 | GPIO15); + + /* Setup SPI parameters. */ + spi_init_master(SPI2, SPI_CR1_BAUDRATE_FPCLK_DIV_256, SPI_CR1_CPOL, SPI_CR1_CPHA, SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST); + + /* Finally enable the SPI. */ + spi_enable(SPI2); +} + +void usart_setup(void) +{ + gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO9); + //GPIO_MODER(GPIOA) |= GPIO_MODE(9, GPIO_MODE_AF); + //gpio_set_af(GPIOA, GPIO_AF7, GPIO9|GPIO10); + + /* Setup UART parameters. */ + usart_set_baudrate(USART1, 9600, 16000000); + usart_set_databits(USART1, 8); + usart_set_stopbits(USART1, USART_STOPBITS_1); + usart_set_parity(USART1, USART_PARITY_NONE); + usart_set_flow_control(USART1, USART_FLOWCONTROL_NONE); + usart_set_mode(USART1, USART_MODE_TX); + + /* Finally enable the USART. */ + usart_enable(USART1); +} + +void gpio_setup(void) +{ + gpio_set(GPIOC, GPIO3); + + /* Setup GPIO6 and 7 (in GPIO port A) for led use. */ + gpio_mode_setup(GPIOC, GPIO_MODE_OUTPUT, + GPIO_MODE_OUTPUT, GPIO3); +} + +int _write (int file, char *ptr, int len) +{ + int i; + + if (file == 1) { + for (i = 0; i < len; i++){ + usart_send_blocking(USART1, ptr[i]); + } + + return i; + } + + errno = EIO; + return -1; +} + +int main(void) +{ + int counter = 0; + + clock_setup(); + gpio_setup(); + usart_setup(); + spi_setup(); + + /* + * Write Hello World an integer, float and double all over + * again while incrementing the numbers. + */ + while (1) { + gpio_toggle(GPIOC, GPIO3); + printf("Hello World! %i\r\n", counter); + counter++; + spi_send(SPI2,(u8)counter); + } + + return 0; +} diff --git a/examples/stm32f2/jobygps/spi_test/spi_test.ld b/examples/stm32f2/jobygps/spi_test/spi_test.ld new file mode 100644 index 0000000..7899773 --- /dev/null +++ b/examples/stm32f2/jobygps/spi_test/spi_test.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Linker script for Open-BLDC (STM32F103CBT6, 128K flash, 20K RAM). */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32.ld + -- cgit v1.2.3 From f0c153598d5eb8373770297e71732f8fcef4f8ef Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Fri, 23 Sep 2011 13:04:11 -0700 Subject: SPI test now working on F2! --- examples/stm32f2/jobygps/spi_test/spi_test.c | 49 +++++++++++---------------- examples/stm32f2/jobygps/spi_test/spi_test.ld | 8 ++--- 2 files changed, 24 insertions(+), 33 deletions(-) diff --git a/examples/stm32f2/jobygps/spi_test/spi_test.c b/examples/stm32f2/jobygps/spi_test/spi_test.c index 2145165..b45789c 100644 --- a/examples/stm32f2/jobygps/spi_test/spi_test.c +++ b/examples/stm32f2/jobygps/spi_test/spi_test.c @@ -1,8 +1,8 @@ /* * This file is part of the libopencm3 project. * - * Copyright (C) 2009 Uwe Hermann , - * 2011 Piotr Esden-Tempski + * Copyright (C) 2011 Fergus Noble + * Copyright (C) 2011 Henry Hallam * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -29,27 +29,21 @@ void clock_setup(void) { - //rcc_clock_setup_in_hse_8mhz_out_72mhz(); - - /* Enable GPIOA clock (for LED GPIOs). */ - //rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); - - /* Enable clocks for GPIO port A (for GPIO_USART1_TX) and USART1. */ - //rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN | -// RCC_APB2ENR_AFIOEN | -// RCC_APB2ENR_USART1EN); RCC_APB1ENR |= RCC_APB1ENR_SPI2EN; RCC_APB2ENR |= RCC_APB2ENR_USART1EN; - RCC_AHB1ENR |= RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIOAEN; // PORT B not enabled... + RCC_AHB1ENR |= RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN; } void spi_setup(void) { - gpio_mode_setup(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO12 | GPIO13 | GPIO14 | GPIO15); + gpio_mode_setup(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO13 | GPIO14 | GPIO15); + gpio_set_af(GPIOB, GPIO_AF5, GPIO13 | GPIO14 | GPIO15); /* Setup SPI parameters. */ - spi_init_master(SPI2, SPI_CR1_BAUDRATE_FPCLK_DIV_256, SPI_CR1_CPOL, SPI_CR1_CPHA, SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST); + spi_init_master(SPI2, SPI_CR1_BAUDRATE_FPCLK_DIV_256, SPI_CR1_CPOL, \ + SPI_CR1_CPHA, SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST); + spi_enable_ss_output(SPI2); /* Required, see 25.3.1 section about NSS */ /* Finally enable the SPI. */ spi_enable(SPI2); @@ -58,8 +52,7 @@ void spi_setup(void) void usart_setup(void) { gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO9); - //GPIO_MODER(GPIOA) |= GPIO_MODE(9, GPIO_MODE_AF); - //gpio_set_af(GPIOA, GPIO_AF7, GPIO9|GPIO10); + gpio_set_af(GPIOA, GPIO_AF7, GPIO9|GPIO10); /* Setup UART parameters. */ usart_set_baudrate(USART1, 9600, 16000000); @@ -77,46 +70,44 @@ void gpio_setup(void) { gpio_set(GPIOC, GPIO3); - /* Setup GPIO6 and 7 (in GPIO port A) for led use. */ + /* Setup GPIO3 (in GPIO port C) for led use. */ gpio_mode_setup(GPIOC, GPIO_MODE_OUTPUT, GPIO_MODE_OUTPUT, GPIO3); } int _write (int file, char *ptr, int len) { - int i; + int i; if (file == 1) { for (i = 0; i < len; i++){ usart_send_blocking(USART1, ptr[i]); } - return i; } - - errno = EIO; - return -1; + errno = EIO; + return -1; } int main(void) { int counter = 0; + volatile u16 dummy; clock_setup(); gpio_setup(); usart_setup(); spi_setup(); - /* - * Write Hello World an integer, float and double all over - * again while incrementing the numbers. - */ - while (1) { - gpio_toggle(GPIOC, GPIO3); - printf("Hello World! %i\r\n", counter); + while (1) + { counter++; + printf("Hello, world! %i\r\n", counter); + dummy = spi_read(SPI2); /* Stops RX buff overflow, but probably not needed */ spi_send(SPI2,(u8)counter); + gpio_toggle(GPIOC, GPIO3); } + while(1); return 0; } diff --git a/examples/stm32f2/jobygps/spi_test/spi_test.ld b/examples/stm32f2/jobygps/spi_test/spi_test.ld index 7899773..cfe9ab7 100644 --- a/examples/stm32f2/jobygps/spi_test/spi_test.ld +++ b/examples/stm32f2/jobygps/spi_test/spi_test.ld @@ -17,15 +17,15 @@ * along with this program. If not, see . */ -/* Linker script for Open-BLDC (STM32F103CBT6, 128K flash, 20K RAM). */ +/* Linker script for Olimex STM32-H103 (STM32F103RBT6, 128K flash, 20K RAM). */ /* Define memory regions. */ MEMORY { - rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K + rom (rx) : ORIGIN = 0x08000000, LENGTH = 256K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K } /* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld +INCLUDE libopencm3_stm32f2.ld -- cgit v1.2.3 From e7f909c50206f7a4cc467fa55633c70bbd384491 Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Fri, 23 Sep 2011 13:04:54 -0700 Subject: Minor fixes to the SPI code, mainly you should check that the TX buffer is empty before rather than after sending. --- lib/stm32_common/spi.c | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/lib/stm32_common/spi.c b/lib/stm32_common/spi.c index 733a1bc..7fb8711 100644 --- a/lib/stm32_common/spi.c +++ b/lib/stm32_common/spi.c @@ -54,11 +54,7 @@ int spi_init_master(u32 spi, u32 br, u32 cpol, u32 cpha, u32 dff, u32 lsbfirst) /* TODO: Error handling? */ void spi_enable(u32 spi) { - u32 reg32; - - reg32 = SPI_CR1(spi); - reg32 |= SPI_CR1_SPE; /* Enable SPI. */ - SPI_CR1(spi) = reg32; + SPI_CR1(spi) |= SPI_CR1_SPE; /* Enable SPI. */ } /* TODO: Error handling? */ @@ -80,13 +76,11 @@ void spi_write(u32 spi, u16 data) void spi_send(u32 spi, u16 data) { + /* wait for transfer finished */ + while (SPI_SR(spi) & SPI_SR_BSY ); + /* Write data (8 or 16 bits, depending on DFF) into DR. */ SPI_DR(spi) = data; - - /* wait for transfer finished */ - while (SPI_SR(spi) & SPI_SR_BSY ) - { - } } u16 spi_read(u32 spi) -- cgit v1.2.3 From e772992f4c56d79581e62607c27609e4eeaaae7e Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Fri, 23 Sep 2011 13:05:12 -0700 Subject: Some more silly bugs in GPIO fixed for F2. --- lib/stm32f2/gpio.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/stm32f2/gpio.c b/lib/stm32f2/gpio.c index abb08c0..6e1ef08 100644 --- a/lib/stm32f2/gpio.c +++ b/lib/stm32f2/gpio.c @@ -49,7 +49,7 @@ void gpio_mode_setup(u32 gpioport, u8 mode, u8 pull_up_down, u16 gpios) void gpio_set_output_options(u32 gpioport, u8 otype, u8 speed, u16 gpios) { u16 i; - u16 ospeedr; + u32 ospeedr; if (otype == 0x1) GPIO_OTYPER(gpioport) |= gpios; @@ -71,7 +71,7 @@ void gpio_set_output_options(u32 gpioport, u8 otype, u8 speed, u16 gpios) void gpio_set_af(u32 gpioport, u8 alt_func_num, u16 gpios) { u16 i; - u16 afrl, afrh; + u32 afrl, afrh; afrl = GPIO_AFRL(gpioport); afrh = GPIO_AFRH(gpioport); -- cgit v1.2.3 From 84b9f859416bb32ba7cf5f19b930445adb2aa41d Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Mon, 26 Sep 2011 14:21:42 -0700 Subject: Moving a couple more headers to stm common. --- include/libopencm3/stm32/f1/otg_fs.h | 324 ----------------------------------- include/libopencm3/stm32/f1/tools.h | 64 ------- include/libopencm3/stm32/otg_fs.h | 324 +++++++++++++++++++++++++++++++++++ include/libopencm3/stm32/tools.h | 64 +++++++ 4 files changed, 388 insertions(+), 388 deletions(-) delete mode 100644 include/libopencm3/stm32/f1/otg_fs.h delete mode 100644 include/libopencm3/stm32/f1/tools.h create mode 100644 include/libopencm3/stm32/otg_fs.h create mode 100644 include/libopencm3/stm32/tools.h diff --git a/include/libopencm3/stm32/f1/otg_fs.h b/include/libopencm3/stm32/f1/otg_fs.h deleted file mode 100644 index e1d7a6a..0000000 --- a/include/libopencm3/stm32/f1/otg_fs.h +++ /dev/null @@ -1,324 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Gareth McMullin - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_OTG_FS_H -#define LIBOPENCM3_OTG_FS_H - -#include -#include - -/* Core Global Control and Status Registers */ -#define OTG_FS_OTGCTL MMIO32(USB_OTG_FS_BASE + 0x000) -#define OTG_FS_GOTGINT MMIO32(USB_OTG_FS_BASE + 0x004) -#define OTG_FS_GAHBCFG MMIO32(USB_OTG_FS_BASE + 0x008) -#define OTG_FS_GUSBCFG MMIO32(USB_OTG_FS_BASE + 0x00C) -#define OTG_FS_GRSTCTL MMIO32(USB_OTG_FS_BASE + 0x010) -#define OTG_FS_GINTSTS MMIO32(USB_OTG_FS_BASE + 0x014) -#define OTG_FS_GINTMSK MMIO32(USB_OTG_FS_BASE + 0x018) -#define OTG_FS_GRXSTSR MMIO32(USB_OTG_FS_BASE + 0x01C) -#define OTG_FS_GRXSTSP MMIO32(USB_OTG_FS_BASE + 0x020) -#define OTG_FS_GRXFSIZ MMIO32(USB_OTG_FS_BASE + 0x024) -#define OTG_FS_GNPTXFSIZ MMIO32(USB_OTG_FS_BASE + 0x028) -#define OTG_FS_GNPTXSTS MMIO32(USB_OTG_FS_BASE + 0x02C) -#define OTG_FS_GCCFG MMIO32(USB_OTG_FS_BASE + 0x038) -#define OTG_FS_CID MMIO32(USB_OTG_FS_BASE + 0x03C) -#define OTG_FS_HPTXFSIZ MMIO32(USB_OTG_FS_BASE + 0x100) -#define OTG_FS_DIEPTXF(x) MMIO32(USB_OTG_FS_BASE + 0x104 + 4*(x)) - -/* Host-mode Control and Status Registers */ -#define OTG_FS_HCFG MMIO32(USB_OTG_FS_BASE + 0x400) -#define OTG_FS_HFIR MMIO32(USB_OTG_FS_BASE + 0x404) -#define OTG_FS_HFNUM MMIO32(USB_OTG_FS_BASE + 0x408) -#define OTG_FS_HPTXSTS MMIO32(USB_OTG_FS_BASE + 0x410) -#define OTG_FS_HAINT MMIO32(USB_OTG_FS_BASE + 0x414) -#define OTG_FS_HAINTMSK MMIO32(USB_OTG_FS_BASE + 0x418) -#define OTG_FS_HPRT MMIO32(USB_OTG_FS_BASE + 0x440) -#define OTG_FS_HCCHARx MMIO32(USB_OTG_FS_BASE + 0x500) -#define OTG_FS_HCINTx MMIO32(USB_OTG_FS_BASE + 0x508) -#define OTG_FS_HCINTMSKx MMIO32(USB_OTG_FS_BASE + 0x50C) -#define OTG_FS_HCTSIZx MMIO32(USB_OTG_FS_BASE + 0x510) - -/* Device-mode Control and Status Registers */ -#define OTG_FS_DCFG MMIO32(USB_OTG_FS_BASE + 0x800) -#define OTG_FS_DCTL MMIO32(USB_OTG_FS_BASE + 0x804) -#define OTG_FS_DSTS MMIO32(USB_OTG_FS_BASE + 0x808) -#define OTG_FS_DIEPMSK MMIO32(USB_OTG_FS_BASE + 0x810) -#define OTG_FS_DOEPMSK MMIO32(USB_OTG_FS_BASE + 0x814) -#define OTG_FS_DAINT MMIO32(USB_OTG_FS_BASE + 0x818) -#define OTG_FS_DAINTMSK MMIO32(USB_OTG_FS_BASE + 0x81C) -#define OTG_FS_DVBUSDIS MMIO32(USB_OTG_FS_BASE + 0x828) -#define OTG_FS_DVBUSPULSE MMIO32(USB_OTG_FS_BASE + 0x82C) -#define OTG_FS_DIEPEMPMSK MMIO32(USB_OTG_FS_BASE + 0x834) -#define OTG_FS_DIEPCTL0 MMIO32(USB_OTG_FS_BASE + 0x900) -#define OTG_FS_DIEPCTL(x) MMIO32(USB_OTG_FS_BASE + 0x900 + 0x20*(x)) -#define OTG_FS_DOEPCTL0 MMIO32(USB_OTG_FS_BASE + 0xB00) -#define OTG_FS_DOEPCTL(x) MMIO32(USB_OTG_FS_BASE + 0xB00 + 0x20*(x)) -#define OTG_FS_DIEPINT(x) MMIO32(USB_OTG_FS_BASE + 0x908 + 0x20*(x)) -#define OTG_FS_DOEPINT(x) MMIO32(USB_OTG_FS_BASE + 0xB08 + 0x20*(x)) -#define OTG_FS_DIEPTSIZ0 MMIO32(USB_OTG_FS_BASE + 0x910) -#define OTG_FS_DOEPTSIZ0 MMIO32(USB_OTG_FS_BASE + 0xB10) -#define OTG_FS_DIEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + 0x910 + 0x20*(x)) -#define OTG_FS_DTXFSTS(x) MMIO32(USB_OTG_FS_BASE + 0x918 + 0x20*(x)) -#define OTG_FS_DOEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + 0xB10 + 0x20*(x)) - -/* Power and clock gating control and status register */ -#define OTG_FS_PCGCCTL MMIO32(USB_OTG_FS_BASE + 0xE00) - -/* Data FIFO */ -#define OTG_FS_FIFO(x) ((u32*)(USB_OTG_FS_BASE + (((x) + 1) << 12))) - -/* Global CSRs */ -/* OTG_FS AHB configuration register (OTG_FS_GAHBCFG) */ -#define OTG_FS_GAHBCFG_GINT 0x0001 -#define OTG_FS_GAHBCFG_TXFELVL 0x0080 -#define OTG_FS_GAHBCFG_PTXFELVL 0x0100 - -/* OTG_FS USB configuration register (OTG_FS_GUSBCFG) */ -#define OTG_FS_GUSBCFG_TOCAL 0x00000003 -#define OTG_FS_GUSBCFG_SRPCAP 0x00000100 -#define OTG_FS_GUSBCFG_HNPCAP 0x00000200 -#define OTG_FS_GUSBCFG_TRDT_MASK (0xf << 10) -#define OTG_FS_GUSBCFG_TRDT_16BIT (0x5 << 10) -#define OTG_FS_GUSBCFG_TRDT_8BIT (0x9 << 10) -#define OTG_FS_GUSBCFG_NPTXRWEN 0x00004000 -#define OTG_FS_GUSBCFG_FHMOD 0x20000000 -#define OTG_FS_GUSBCFG_FDMOD 0x40000000 -#define OTG_FS_GUSBCFG_CTXPKT 0x80000000 -/* WARNING: not in reference manual */ -#define OTG_FS_GUSBCFG_PHYSEL (1 << 6) - -/* OTG_FS reset register (OTG_FS_GRSTCTL) */ -#define OTG_FS_GRSTCTL_AHBIDL (1 << 31) -/* Bits 30:11 - Reserved */ -#define OTG_FS_GRSTCTL_TXFNUM_MASK (0x1f << 6) -#define OTG_FS_GRSTCTL_TXFFLSH (1 << 5) -#define OTG_FS_GRSTCTL_RXFFLSH (1 << 4) -/* Bit 3 - Reserved */ -#define OTG_FS_GRSTCTL_FCRST (1 << 2) -#define OTG_FS_GRSTCTL_HSRST (1 << 1) -#define OTG_FS_GRSTCTL_CSRST (1 << 0) - -/* OTG_FS interrupt status register (OTG_FS_GINTSTS) */ -#define OTG_FS_GINTSTS_WKUPINT (1 << 31) -#define OTG_FS_GINTSTS_SRQINT (1 << 30) -#define OTG_FS_GINTSTS_DISCINT (1 << 29) -#define OTG_FS_GINTSTS_CIDSCHG (1 << 28) -/* Bit 27 - Reserved */ -#define OTG_FS_GINTSTS_PTXFE (1 << 26) -#define OTG_FS_GINTSTS_HCINT (1 << 25) -#define OTG_FS_GINTSTS_HPRTINT (1 << 24) -/* Bits 23:22 - Reserved */ -#define OTG_FS_GINTSTS_IPXFR (1 << 21) -#define OTG_FS_GINTSTS_INCOMPISOOUT (1 << 21) -#define OTG_FS_GINTSTS_IISOIXFR (1 << 20) -#define OTG_FS_GINTSTS_OEPINT (1 << 19) -#define OTG_FS_GINTSTS_IEPINT (1 << 18) -/* Bits 17:16 - Reserved */ -#define OTG_FS_GINTSTS_EOPF (1 << 15) -#define OTG_FS_GINTSTS_ISOODRP (1 << 14) -#define OTG_FS_GINTSTS_ENUMDNE (1 << 13) -#define OTG_FS_GINTSTS_USBRST (1 << 12) -#define OTG_FS_GINTSTS_USBSUSP (1 << 11) -#define OTG_FS_GINTSTS_ESUSP (1 << 10) -/* Bits 9:8 - Reserved */ -#define OTG_FS_GINTSTS_GONAKEFF (1 << 7) -#define OTG_FS_GINTSTS_GINAKEFF (1 << 6) -#define OTG_FS_GINTSTS_NPTXFE (1 << 5) -#define OTG_FS_GINTSTS_RXFLVL (1 << 4) -#define OTG_FS_GINTSTS_SOF (1 << 3) -#define OTG_FS_GINTSTS_OTGINT (1 << 2) -#define OTG_FS_GINTSTS_MMIS (1 << 1) -#define OTG_FS_GINTSTS_CMOD (1 << 0) - -/* OTG_FS interrupt mask register (OTG_FS_GINTMSK) */ -#define OTG_FS_GINTMSK_MMISM 0x00000002 -#define OTG_FS_GINTMSK_OTGINT 0x00000004 -#define OTG_FS_GINTMSK_SOFM 0x00000008 -#define OTG_FS_GINTMSK_RXFLVLM 0x00000010 -#define OTG_FS_GINTMSK_NPTXFEM 0x00000020 -#define OTG_FS_GINTMSK_GINAKEFFM 0x00000040 -#define OTG_FS_GINTMSK_GONAKEFFM 0x00000080 -#define OTG_FS_GINTMSK_ESUSPM 0x00000400 -#define OTG_FS_GINTMSK_USBSUSPM 0x00000800 -#define OTG_FS_GINTMSK_USBRST 0x00001000 -#define OTG_FS_GINTMSK_ENUMDNEM 0x00002000 -#define OTG_FS_GINTMSK_ISOODRPM 0x00004000 -#define OTG_FS_GINTMSK_EOPFM 0x00008000 -#define OTG_FS_GINTMSK_EPMISM 0x00020000 -#define OTG_FS_GINTMSK_IEPINT 0x00040000 -#define OTG_FS_GINTMSK_OEPINT 0x00080000 -#define OTG_FS_GINTMSK_IISOIXFRM 0x00100000 -#define OTG_FS_GINTMSK_IISOOXFRM 0x00200000 -#define OTG_FS_GINTMSK_IPXFRM 0x00200000 -#define OTG_FS_GINTMSK_PRTIM 0x01000000 -#define OTG_FS_GINTMSK_HCIM 0x02000000 -#define OTG_FS_GINTMSK_PTXFEM 0x04000000 -#define OTG_FS_GINTMSK_CIDSCHGM 0x10000000 -#define OTG_FS_GINTMSK_DISCINT 0x20000000 -#define OTG_FS_GINTMSK_SRQIM 0x40000000 -#define OTG_FS_GINTMSK_WUIM 0x80000000 - -/* OTG_FS Receive Status Pop Register (OTG_FS_GRXSTSP) */ -/* Bits 31:25 - Reserved */ -#define OTG_FS_GRXSTSP_FRMNUM_MASK (0xf << 21) -#define OTG_FS_GRXSTSP_PKTSTS_MASK (0xf << 17) -#define OTG_FS_GRXSTSP_PKTSTS_GOUTNAK (0x1 << 17) -#define OTG_FS_GRXSTSP_PKTSTS_OUT (0x2 << 17) -#define OTG_FS_GRXSTSP_PKTSTS_OUT_COMP (0x3 << 17) -#define OTG_FS_GRXSTSP_PKTSTS_SETUP_COMP (0x4 << 17) -#define OTG_FS_GRXSTSP_PKTSTS_SETUP (0x6 << 17) -#define OTG_FS_GRXSTSP_DPID_MASK (0x3 << 15) -#define OTG_FS_GRXSTSP_DPID_DATA0 (0x0 << 15) -#define OTG_FS_GRXSTSP_DPID_DATA1 (0x2 << 15) -#define OTG_FS_GRXSTSP_DPID_DATA2 (0x1 << 15) -#define OTG_FS_GRXSTSP_DPID_MDATA (0x3 << 15) -#define OTG_FS_GRXSTSP_BCNT_MASK (0x7ff << 4) -#define OTG_FS_GRXSTSP_EPNUM_MASK (0xf << 0) - -/* OTG_FS general core configuration register (OTG_FS_GCCFG) */ -/* Bits 31:21 - Reserved */ -#define OTG_FS_GCCFG_SOFOUTEN (1 << 20) -#define OTG_FS_GCCFG_VBUSBSEN (1 << 19) -#define OTG_FS_GCCFG_VBUSASEN (1 << 18) -/* Bit 17 - Reserved */ -#define OTG_FS_GCCFG_PWRDWN (1 << 16) -/* Bits 15:0 - Reserved */ - - -/* Device-mode CSRs */ -/* OTG_FS device control register (OTG_FS_DCTL) */ -/* Bits 31:12 - Reserved */ -#define OTG_FS_DCTL_POPRGDNE (1 << 11) -#define OTG_FS_DCTL_CGONAK (1 << 10) -#define OTG_FS_DCTL_SGONAK (1 << 9) -#define OTG_FS_DCTL_SGINAK (1 << 8) -#define OTG_FS_DCTL_TCTL_MASK (7 << 4) -#define OTG_FS_DCTL_GONSTS (1 << 3) -#define OTG_FS_DCTL_GINSTS (1 << 2) -#define OTG_FS_DCTL_SDIS (1 << 1) -#define OTG_FS_DCTL_RWUSIG (1 << 0) - -/* OTG_FS device configuration register (OTG_FS_DCFG) */ -#define OTG_FS_DCFG_DSPD 0x0003 -#define OTG_FS_DCFG_NZLSOHSK 0x0004 -#define OTG_FS_DCFG_DAD 0x07F0 -#define OTG_FS_DCFG_PFIVL 0x1800 - -/* OTG_FS Device IN Endpoint Common Interrupt Mask Register (OTG_FS_DIEPMSK) */ -/* Bits 31:10 - Reserved */ -#define OTG_FS_DIEPMSK_BIM (1 << 9) -#define OTG_FS_DIEPMSK_TXFURM (1 << 8) -/* Bit 7 - Reserved */ -#define OTG_FS_DIEPMSK_INEPNEM (1 << 6) -#define OTG_FS_DIEPMSK_INEPNMM (1 << 5) -#define OTG_FS_DIEPMSK_ITTXFEMSK (1 << 4) -#define OTG_FS_DIEPMSK_TOM (1 << 3) -/* Bit 2 - Reserved */ -#define OTG_FS_DIEPMSK_EPDM (1 << 1) -#define OTG_FS_DIEPMSK_XFRCM (1 << 0) - -/* OTG_FS Device OUT Endpoint Common Interrupt Mask Register (OTG_FS_DOEPMSK) */ -/* Bits 31:10 - Reserved */ -#define OTG_FS_DOEPMSK_BOIM (1 << 9) -#define OTG_FS_DOEPMSK_OPEM (1 << 8) -/* Bit 7 - Reserved */ -#define OTG_FS_DOEPMSK_B2BSTUP (1 << 6) -/* Bit 5 - Reserved */ -#define OTG_FS_DOEPMSK_OTEPDM (1 << 4) -#define OTG_FS_DOEPMSK_STUPM (1 << 3) -/* Bit 2 - Reserved */ -#define OTG_FS_DOEPMSK_EPDM (1 << 1) -#define OTG_FS_DOEPMSK_XFRCM (1 << 0) - -/* OTG_FS Device Control IN Endpoint 0 Control Register (OTG_FS_DIEPCTL0) */ -#define OTG_FS_DIEPCTL0_EPENA (1 << 31) -#define OTG_FS_DIEPCTL0_EPDIS (1 << 30) -/* Bits 29:28 - Reserved */ -#define OTG_FS_DIEPCTLX_SD0PID (1 << 28) -#define OTG_FS_DIEPCTL0_SNAK (1 << 27) -#define OTG_FS_DIEPCTL0_CNAK (1 << 26) -#define OTG_FS_DIEPCTL0_TXFNUM_MASK (0xf << 22) -#define OTG_FS_DIEPCTL0_STALL (1 << 21) -/* Bit 20 - Reserved */ -#define OTG_FS_DIEPCTL0_EPTYP_MASK (0x3 << 18) -#define OTG_FS_DIEPCTL0_NAKSTS (1 << 17) -/* Bit 16 - Reserved */ -#define OTG_FS_DIEPCTL0_USBAEP (1 << 15) -/* Bits 14:2 - Reserved */ -#define OTG_FS_DIEPCTL0_MPSIZ_MASK (0x3 << 0) -#define OTG_FS_DIEPCTL0_MPSIZ_64 (0x0 << 0) -#define OTG_FS_DIEPCTL0_MPSIZ_32 (0x1 << 0) -#define OTG_FS_DIEPCTL0_MPSIZ_16 (0x2 << 0) -#define OTG_FS_DIEPCTL0_MPSIZ_8 (0x3 << 0) - -/* OTG_FS Device Control OUT Endpoint 0 Control Register (OTG_FS_DOEPCTL0) */ -#define OTG_FS_DOEPCTL0_EPENA (1 << 31) -#define OTG_FS_DOEPCTL0_EPDIS (1 << 30) -/* Bits 29:28 - Reserved */ -#define OTG_FS_DOEPCTLX_SD0PID (1 << 28) -#define OTG_FS_DOEPCTL0_SNAK (1 << 27) -#define OTG_FS_DOEPCTL0_CNAK (1 << 26) -/* Bits 25:22 - Reserved */ -#define OTG_FS_DOEPCTL0_STALL (1 << 21) -#define OTG_FS_DOEPCTL0_SNPM (1 << 20) -#define OTG_FS_DOEPCTL0_EPTYP_MASK (0x3 << 18) -#define OTG_FS_DOEPCTL0_NAKSTS (1 << 17) -/* Bit 16 - Reserved */ -#define OTG_FS_DOEPCTL0_USBAEP (1 << 15) -/* Bits 14:2 - Reserved */ -#define OTG_FS_DOEPCTL0_MPSIZ_MASK (0x3 << 0) -#define OTG_FS_DOEPCTL0_MPSIZ_64 (0x0 << 0) -#define OTG_FS_DOEPCTL0_MPSIZ_32 (0x1 << 0) -#define OTG_FS_DOEPCTL0_MPSIZ_16 (0x2 << 0) -#define OTG_FS_DOEPCTL0_MPSIZ_8 (0x3 << 0) - -/* OTG_FS Device IN Endpoint Interrupt Register (OTG_FS_DIEPINTx) */ -/* Bits 31:8 - Reserved */ -#define OTG_FS_DIEPINTX_TXFE (1 << 7) -#define OTG_FS_DIEPINTX_INEPNE (1 << 6) -/* Bit 5 - Reserved */ -#define OTG_FS_DIEPINTX_ITTXFE (1 << 4) -#define OTG_FS_DIEPINTX_TOC (1 << 3) -/* Bit 2 - Reserved */ -#define OTG_FS_DIEPINTX_EPDISD (1 << 1) -#define OTG_FS_DIEPINTX_XFRC (1 << 0) - -/* OTG_FS Device IN Endpoint Interrupt Register (OTG_FS_DOEPINTx) */ -/* Bits 31:7 - Reserved */ -#define OTG_FS_DOEPINTX_B2BSTUP (1 << 6) -/* Bit 5 - Reserved */ -#define OTG_FS_DOEPINTX_OTEPDIS (1 << 4) -#define OTG_FS_DOEPINTX_STUP (1 << 3) -/* Bit 2 - Reserved */ -#define OTG_FS_DOEPINTX_EPDISD (1 << 1) -#define OTG_FS_DOEPINTX_XFRC (1 << 0) - -/* OTG_FS Device OUT Endpoint 0 Transfer Size Regsiter (OTG_FS_DOEPTSIZ0) */ -/* Bit 31 - Reserved */ -#define OTG_FS_DIEPSIZ0_STUPCNT_1 (0x1 << 29) -#define OTG_FS_DIEPSIZ0_STUPCNT_2 (0x2 << 29) -#define OTG_FS_DIEPSIZ0_STUPCNT_3 (0x3 << 29) -#define OTG_FS_DIEPSIZ0_STUPCNT_MASK (0x3 << 29) -/* Bits 28:20 - Reserved */ -#define OTG_FS_DIEPSIZ0_PKTCNT (1 << 19) -/* Bits 18:7 - Reserved */ -#define OTG_FS_DIEPSIZ0_XFRSIZ_MASK (0x7f << 0) - -#endif - diff --git a/include/libopencm3/stm32/f1/tools.h b/include/libopencm3/stm32/f1/tools.h deleted file mode 100644 index ac7f0bf..0000000 --- a/include/libopencm3/stm32/f1/tools.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Piotr Esden-Tempski - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef LIBOPENCM3_TOOLS_H -#define LIBOPENCM3_TOOLS_H - -/* - * Register accessors / manipulators - */ - -/* Get register content. */ -#define GET_REG(REG) ((u16) *REG) - -/* Set register content. */ -#define SET_REG(REG, VAL) (*REG = (u16)VAL) - -/* Clear register bit. */ -#define CLR_REG_BIT(REG, BIT) SET_REG(REG, (~BIT)) - -/* Clear register bit masking out some bits that must not be touched. */ -#define CLR_REG_BIT_MSK(REG, MSK, BIT) \ - SET_REG(REG, (GET_REG(REG) & MSK & (~BIT))) - -/* Get masked out bit value. */ -#define GET_REG_BIT(REG, BIT) (GET_REG(REG) & BIT) - -/* - * Set/reset a bit in a masked window by using toggle mechanism. - * - * This means that we look at the bits in the bit window designated by - * the mask. If the bit in the masked window is not matching the - * bitmask BIT then we write 1 and if the bit in the masked window is - * matching the bitmask BIT we write 0. - * - * TODO: We may need a faster implementation of that one? - */ -#define TOG_SET_REG_BIT_MSK(REG, MSK, BIT) \ -do { \ - register u16 toggle_mask = GET_REG(REG) & (MSK); \ - register u16 bit_selector; \ - for (bit_selector = 1; bit_selector; bit_selector <<= 1) { \ - if ((bit_selector & (BIT)) != 0) \ - toggle_mask ^= bit_selector; \ - } \ - SET_REG(REG, toggle_mask); \ -} while(0) - -#endif diff --git a/include/libopencm3/stm32/otg_fs.h b/include/libopencm3/stm32/otg_fs.h new file mode 100644 index 0000000..e1d7a6a --- /dev/null +++ b/include/libopencm3/stm32/otg_fs.h @@ -0,0 +1,324 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Gareth McMullin + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_OTG_FS_H +#define LIBOPENCM3_OTG_FS_H + +#include +#include + +/* Core Global Control and Status Registers */ +#define OTG_FS_OTGCTL MMIO32(USB_OTG_FS_BASE + 0x000) +#define OTG_FS_GOTGINT MMIO32(USB_OTG_FS_BASE + 0x004) +#define OTG_FS_GAHBCFG MMIO32(USB_OTG_FS_BASE + 0x008) +#define OTG_FS_GUSBCFG MMIO32(USB_OTG_FS_BASE + 0x00C) +#define OTG_FS_GRSTCTL MMIO32(USB_OTG_FS_BASE + 0x010) +#define OTG_FS_GINTSTS MMIO32(USB_OTG_FS_BASE + 0x014) +#define OTG_FS_GINTMSK MMIO32(USB_OTG_FS_BASE + 0x018) +#define OTG_FS_GRXSTSR MMIO32(USB_OTG_FS_BASE + 0x01C) +#define OTG_FS_GRXSTSP MMIO32(USB_OTG_FS_BASE + 0x020) +#define OTG_FS_GRXFSIZ MMIO32(USB_OTG_FS_BASE + 0x024) +#define OTG_FS_GNPTXFSIZ MMIO32(USB_OTG_FS_BASE + 0x028) +#define OTG_FS_GNPTXSTS MMIO32(USB_OTG_FS_BASE + 0x02C) +#define OTG_FS_GCCFG MMIO32(USB_OTG_FS_BASE + 0x038) +#define OTG_FS_CID MMIO32(USB_OTG_FS_BASE + 0x03C) +#define OTG_FS_HPTXFSIZ MMIO32(USB_OTG_FS_BASE + 0x100) +#define OTG_FS_DIEPTXF(x) MMIO32(USB_OTG_FS_BASE + 0x104 + 4*(x)) + +/* Host-mode Control and Status Registers */ +#define OTG_FS_HCFG MMIO32(USB_OTG_FS_BASE + 0x400) +#define OTG_FS_HFIR MMIO32(USB_OTG_FS_BASE + 0x404) +#define OTG_FS_HFNUM MMIO32(USB_OTG_FS_BASE + 0x408) +#define OTG_FS_HPTXSTS MMIO32(USB_OTG_FS_BASE + 0x410) +#define OTG_FS_HAINT MMIO32(USB_OTG_FS_BASE + 0x414) +#define OTG_FS_HAINTMSK MMIO32(USB_OTG_FS_BASE + 0x418) +#define OTG_FS_HPRT MMIO32(USB_OTG_FS_BASE + 0x440) +#define OTG_FS_HCCHARx MMIO32(USB_OTG_FS_BASE + 0x500) +#define OTG_FS_HCINTx MMIO32(USB_OTG_FS_BASE + 0x508) +#define OTG_FS_HCINTMSKx MMIO32(USB_OTG_FS_BASE + 0x50C) +#define OTG_FS_HCTSIZx MMIO32(USB_OTG_FS_BASE + 0x510) + +/* Device-mode Control and Status Registers */ +#define OTG_FS_DCFG MMIO32(USB_OTG_FS_BASE + 0x800) +#define OTG_FS_DCTL MMIO32(USB_OTG_FS_BASE + 0x804) +#define OTG_FS_DSTS MMIO32(USB_OTG_FS_BASE + 0x808) +#define OTG_FS_DIEPMSK MMIO32(USB_OTG_FS_BASE + 0x810) +#define OTG_FS_DOEPMSK MMIO32(USB_OTG_FS_BASE + 0x814) +#define OTG_FS_DAINT MMIO32(USB_OTG_FS_BASE + 0x818) +#define OTG_FS_DAINTMSK MMIO32(USB_OTG_FS_BASE + 0x81C) +#define OTG_FS_DVBUSDIS MMIO32(USB_OTG_FS_BASE + 0x828) +#define OTG_FS_DVBUSPULSE MMIO32(USB_OTG_FS_BASE + 0x82C) +#define OTG_FS_DIEPEMPMSK MMIO32(USB_OTG_FS_BASE + 0x834) +#define OTG_FS_DIEPCTL0 MMIO32(USB_OTG_FS_BASE + 0x900) +#define OTG_FS_DIEPCTL(x) MMIO32(USB_OTG_FS_BASE + 0x900 + 0x20*(x)) +#define OTG_FS_DOEPCTL0 MMIO32(USB_OTG_FS_BASE + 0xB00) +#define OTG_FS_DOEPCTL(x) MMIO32(USB_OTG_FS_BASE + 0xB00 + 0x20*(x)) +#define OTG_FS_DIEPINT(x) MMIO32(USB_OTG_FS_BASE + 0x908 + 0x20*(x)) +#define OTG_FS_DOEPINT(x) MMIO32(USB_OTG_FS_BASE + 0xB08 + 0x20*(x)) +#define OTG_FS_DIEPTSIZ0 MMIO32(USB_OTG_FS_BASE + 0x910) +#define OTG_FS_DOEPTSIZ0 MMIO32(USB_OTG_FS_BASE + 0xB10) +#define OTG_FS_DIEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + 0x910 + 0x20*(x)) +#define OTG_FS_DTXFSTS(x) MMIO32(USB_OTG_FS_BASE + 0x918 + 0x20*(x)) +#define OTG_FS_DOEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + 0xB10 + 0x20*(x)) + +/* Power and clock gating control and status register */ +#define OTG_FS_PCGCCTL MMIO32(USB_OTG_FS_BASE + 0xE00) + +/* Data FIFO */ +#define OTG_FS_FIFO(x) ((u32*)(USB_OTG_FS_BASE + (((x) + 1) << 12))) + +/* Global CSRs */ +/* OTG_FS AHB configuration register (OTG_FS_GAHBCFG) */ +#define OTG_FS_GAHBCFG_GINT 0x0001 +#define OTG_FS_GAHBCFG_TXFELVL 0x0080 +#define OTG_FS_GAHBCFG_PTXFELVL 0x0100 + +/* OTG_FS USB configuration register (OTG_FS_GUSBCFG) */ +#define OTG_FS_GUSBCFG_TOCAL 0x00000003 +#define OTG_FS_GUSBCFG_SRPCAP 0x00000100 +#define OTG_FS_GUSBCFG_HNPCAP 0x00000200 +#define OTG_FS_GUSBCFG_TRDT_MASK (0xf << 10) +#define OTG_FS_GUSBCFG_TRDT_16BIT (0x5 << 10) +#define OTG_FS_GUSBCFG_TRDT_8BIT (0x9 << 10) +#define OTG_FS_GUSBCFG_NPTXRWEN 0x00004000 +#define OTG_FS_GUSBCFG_FHMOD 0x20000000 +#define OTG_FS_GUSBCFG_FDMOD 0x40000000 +#define OTG_FS_GUSBCFG_CTXPKT 0x80000000 +/* WARNING: not in reference manual */ +#define OTG_FS_GUSBCFG_PHYSEL (1 << 6) + +/* OTG_FS reset register (OTG_FS_GRSTCTL) */ +#define OTG_FS_GRSTCTL_AHBIDL (1 << 31) +/* Bits 30:11 - Reserved */ +#define OTG_FS_GRSTCTL_TXFNUM_MASK (0x1f << 6) +#define OTG_FS_GRSTCTL_TXFFLSH (1 << 5) +#define OTG_FS_GRSTCTL_RXFFLSH (1 << 4) +/* Bit 3 - Reserved */ +#define OTG_FS_GRSTCTL_FCRST (1 << 2) +#define OTG_FS_GRSTCTL_HSRST (1 << 1) +#define OTG_FS_GRSTCTL_CSRST (1 << 0) + +/* OTG_FS interrupt status register (OTG_FS_GINTSTS) */ +#define OTG_FS_GINTSTS_WKUPINT (1 << 31) +#define OTG_FS_GINTSTS_SRQINT (1 << 30) +#define OTG_FS_GINTSTS_DISCINT (1 << 29) +#define OTG_FS_GINTSTS_CIDSCHG (1 << 28) +/* Bit 27 - Reserved */ +#define OTG_FS_GINTSTS_PTXFE (1 << 26) +#define OTG_FS_GINTSTS_HCINT (1 << 25) +#define OTG_FS_GINTSTS_HPRTINT (1 << 24) +/* Bits 23:22 - Reserved */ +#define OTG_FS_GINTSTS_IPXFR (1 << 21) +#define OTG_FS_GINTSTS_INCOMPISOOUT (1 << 21) +#define OTG_FS_GINTSTS_IISOIXFR (1 << 20) +#define OTG_FS_GINTSTS_OEPINT (1 << 19) +#define OTG_FS_GINTSTS_IEPINT (1 << 18) +/* Bits 17:16 - Reserved */ +#define OTG_FS_GINTSTS_EOPF (1 << 15) +#define OTG_FS_GINTSTS_ISOODRP (1 << 14) +#define OTG_FS_GINTSTS_ENUMDNE (1 << 13) +#define OTG_FS_GINTSTS_USBRST (1 << 12) +#define OTG_FS_GINTSTS_USBSUSP (1 << 11) +#define OTG_FS_GINTSTS_ESUSP (1 << 10) +/* Bits 9:8 - Reserved */ +#define OTG_FS_GINTSTS_GONAKEFF (1 << 7) +#define OTG_FS_GINTSTS_GINAKEFF (1 << 6) +#define OTG_FS_GINTSTS_NPTXFE (1 << 5) +#define OTG_FS_GINTSTS_RXFLVL (1 << 4) +#define OTG_FS_GINTSTS_SOF (1 << 3) +#define OTG_FS_GINTSTS_OTGINT (1 << 2) +#define OTG_FS_GINTSTS_MMIS (1 << 1) +#define OTG_FS_GINTSTS_CMOD (1 << 0) + +/* OTG_FS interrupt mask register (OTG_FS_GINTMSK) */ +#define OTG_FS_GINTMSK_MMISM 0x00000002 +#define OTG_FS_GINTMSK_OTGINT 0x00000004 +#define OTG_FS_GINTMSK_SOFM 0x00000008 +#define OTG_FS_GINTMSK_RXFLVLM 0x00000010 +#define OTG_FS_GINTMSK_NPTXFEM 0x00000020 +#define OTG_FS_GINTMSK_GINAKEFFM 0x00000040 +#define OTG_FS_GINTMSK_GONAKEFFM 0x00000080 +#define OTG_FS_GINTMSK_ESUSPM 0x00000400 +#define OTG_FS_GINTMSK_USBSUSPM 0x00000800 +#define OTG_FS_GINTMSK_USBRST 0x00001000 +#define OTG_FS_GINTMSK_ENUMDNEM 0x00002000 +#define OTG_FS_GINTMSK_ISOODRPM 0x00004000 +#define OTG_FS_GINTMSK_EOPFM 0x00008000 +#define OTG_FS_GINTMSK_EPMISM 0x00020000 +#define OTG_FS_GINTMSK_IEPINT 0x00040000 +#define OTG_FS_GINTMSK_OEPINT 0x00080000 +#define OTG_FS_GINTMSK_IISOIXFRM 0x00100000 +#define OTG_FS_GINTMSK_IISOOXFRM 0x00200000 +#define OTG_FS_GINTMSK_IPXFRM 0x00200000 +#define OTG_FS_GINTMSK_PRTIM 0x01000000 +#define OTG_FS_GINTMSK_HCIM 0x02000000 +#define OTG_FS_GINTMSK_PTXFEM 0x04000000 +#define OTG_FS_GINTMSK_CIDSCHGM 0x10000000 +#define OTG_FS_GINTMSK_DISCINT 0x20000000 +#define OTG_FS_GINTMSK_SRQIM 0x40000000 +#define OTG_FS_GINTMSK_WUIM 0x80000000 + +/* OTG_FS Receive Status Pop Register (OTG_FS_GRXSTSP) */ +/* Bits 31:25 - Reserved */ +#define OTG_FS_GRXSTSP_FRMNUM_MASK (0xf << 21) +#define OTG_FS_GRXSTSP_PKTSTS_MASK (0xf << 17) +#define OTG_FS_GRXSTSP_PKTSTS_GOUTNAK (0x1 << 17) +#define OTG_FS_GRXSTSP_PKTSTS_OUT (0x2 << 17) +#define OTG_FS_GRXSTSP_PKTSTS_OUT_COMP (0x3 << 17) +#define OTG_FS_GRXSTSP_PKTSTS_SETUP_COMP (0x4 << 17) +#define OTG_FS_GRXSTSP_PKTSTS_SETUP (0x6 << 17) +#define OTG_FS_GRXSTSP_DPID_MASK (0x3 << 15) +#define OTG_FS_GRXSTSP_DPID_DATA0 (0x0 << 15) +#define OTG_FS_GRXSTSP_DPID_DATA1 (0x2 << 15) +#define OTG_FS_GRXSTSP_DPID_DATA2 (0x1 << 15) +#define OTG_FS_GRXSTSP_DPID_MDATA (0x3 << 15) +#define OTG_FS_GRXSTSP_BCNT_MASK (0x7ff << 4) +#define OTG_FS_GRXSTSP_EPNUM_MASK (0xf << 0) + +/* OTG_FS general core configuration register (OTG_FS_GCCFG) */ +/* Bits 31:21 - Reserved */ +#define OTG_FS_GCCFG_SOFOUTEN (1 << 20) +#define OTG_FS_GCCFG_VBUSBSEN (1 << 19) +#define OTG_FS_GCCFG_VBUSASEN (1 << 18) +/* Bit 17 - Reserved */ +#define OTG_FS_GCCFG_PWRDWN (1 << 16) +/* Bits 15:0 - Reserved */ + + +/* Device-mode CSRs */ +/* OTG_FS device control register (OTG_FS_DCTL) */ +/* Bits 31:12 - Reserved */ +#define OTG_FS_DCTL_POPRGDNE (1 << 11) +#define OTG_FS_DCTL_CGONAK (1 << 10) +#define OTG_FS_DCTL_SGONAK (1 << 9) +#define OTG_FS_DCTL_SGINAK (1 << 8) +#define OTG_FS_DCTL_TCTL_MASK (7 << 4) +#define OTG_FS_DCTL_GONSTS (1 << 3) +#define OTG_FS_DCTL_GINSTS (1 << 2) +#define OTG_FS_DCTL_SDIS (1 << 1) +#define OTG_FS_DCTL_RWUSIG (1 << 0) + +/* OTG_FS device configuration register (OTG_FS_DCFG) */ +#define OTG_FS_DCFG_DSPD 0x0003 +#define OTG_FS_DCFG_NZLSOHSK 0x0004 +#define OTG_FS_DCFG_DAD 0x07F0 +#define OTG_FS_DCFG_PFIVL 0x1800 + +/* OTG_FS Device IN Endpoint Common Interrupt Mask Register (OTG_FS_DIEPMSK) */ +/* Bits 31:10 - Reserved */ +#define OTG_FS_DIEPMSK_BIM (1 << 9) +#define OTG_FS_DIEPMSK_TXFURM (1 << 8) +/* Bit 7 - Reserved */ +#define OTG_FS_DIEPMSK_INEPNEM (1 << 6) +#define OTG_FS_DIEPMSK_INEPNMM (1 << 5) +#define OTG_FS_DIEPMSK_ITTXFEMSK (1 << 4) +#define OTG_FS_DIEPMSK_TOM (1 << 3) +/* Bit 2 - Reserved */ +#define OTG_FS_DIEPMSK_EPDM (1 << 1) +#define OTG_FS_DIEPMSK_XFRCM (1 << 0) + +/* OTG_FS Device OUT Endpoint Common Interrupt Mask Register (OTG_FS_DOEPMSK) */ +/* Bits 31:10 - Reserved */ +#define OTG_FS_DOEPMSK_BOIM (1 << 9) +#define OTG_FS_DOEPMSK_OPEM (1 << 8) +/* Bit 7 - Reserved */ +#define OTG_FS_DOEPMSK_B2BSTUP (1 << 6) +/* Bit 5 - Reserved */ +#define OTG_FS_DOEPMSK_OTEPDM (1 << 4) +#define OTG_FS_DOEPMSK_STUPM (1 << 3) +/* Bit 2 - Reserved */ +#define OTG_FS_DOEPMSK_EPDM (1 << 1) +#define OTG_FS_DOEPMSK_XFRCM (1 << 0) + +/* OTG_FS Device Control IN Endpoint 0 Control Register (OTG_FS_DIEPCTL0) */ +#define OTG_FS_DIEPCTL0_EPENA (1 << 31) +#define OTG_FS_DIEPCTL0_EPDIS (1 << 30) +/* Bits 29:28 - Reserved */ +#define OTG_FS_DIEPCTLX_SD0PID (1 << 28) +#define OTG_FS_DIEPCTL0_SNAK (1 << 27) +#define OTG_FS_DIEPCTL0_CNAK (1 << 26) +#define OTG_FS_DIEPCTL0_TXFNUM_MASK (0xf << 22) +#define OTG_FS_DIEPCTL0_STALL (1 << 21) +/* Bit 20 - Reserved */ +#define OTG_FS_DIEPCTL0_EPTYP_MASK (0x3 << 18) +#define OTG_FS_DIEPCTL0_NAKSTS (1 << 17) +/* Bit 16 - Reserved */ +#define OTG_FS_DIEPCTL0_USBAEP (1 << 15) +/* Bits 14:2 - Reserved */ +#define OTG_FS_DIEPCTL0_MPSIZ_MASK (0x3 << 0) +#define OTG_FS_DIEPCTL0_MPSIZ_64 (0x0 << 0) +#define OTG_FS_DIEPCTL0_MPSIZ_32 (0x1 << 0) +#define OTG_FS_DIEPCTL0_MPSIZ_16 (0x2 << 0) +#define OTG_FS_DIEPCTL0_MPSIZ_8 (0x3 << 0) + +/* OTG_FS Device Control OUT Endpoint 0 Control Register (OTG_FS_DOEPCTL0) */ +#define OTG_FS_DOEPCTL0_EPENA (1 << 31) +#define OTG_FS_DOEPCTL0_EPDIS (1 << 30) +/* Bits 29:28 - Reserved */ +#define OTG_FS_DOEPCTLX_SD0PID (1 << 28) +#define OTG_FS_DOEPCTL0_SNAK (1 << 27) +#define OTG_FS_DOEPCTL0_CNAK (1 << 26) +/* Bits 25:22 - Reserved */ +#define OTG_FS_DOEPCTL0_STALL (1 << 21) +#define OTG_FS_DOEPCTL0_SNPM (1 << 20) +#define OTG_FS_DOEPCTL0_EPTYP_MASK (0x3 << 18) +#define OTG_FS_DOEPCTL0_NAKSTS (1 << 17) +/* Bit 16 - Reserved */ +#define OTG_FS_DOEPCTL0_USBAEP (1 << 15) +/* Bits 14:2 - Reserved */ +#define OTG_FS_DOEPCTL0_MPSIZ_MASK (0x3 << 0) +#define OTG_FS_DOEPCTL0_MPSIZ_64 (0x0 << 0) +#define OTG_FS_DOEPCTL0_MPSIZ_32 (0x1 << 0) +#define OTG_FS_DOEPCTL0_MPSIZ_16 (0x2 << 0) +#define OTG_FS_DOEPCTL0_MPSIZ_8 (0x3 << 0) + +/* OTG_FS Device IN Endpoint Interrupt Register (OTG_FS_DIEPINTx) */ +/* Bits 31:8 - Reserved */ +#define OTG_FS_DIEPINTX_TXFE (1 << 7) +#define OTG_FS_DIEPINTX_INEPNE (1 << 6) +/* Bit 5 - Reserved */ +#define OTG_FS_DIEPINTX_ITTXFE (1 << 4) +#define OTG_FS_DIEPINTX_TOC (1 << 3) +/* Bit 2 - Reserved */ +#define OTG_FS_DIEPINTX_EPDISD (1 << 1) +#define OTG_FS_DIEPINTX_XFRC (1 << 0) + +/* OTG_FS Device IN Endpoint Interrupt Register (OTG_FS_DOEPINTx) */ +/* Bits 31:7 - Reserved */ +#define OTG_FS_DOEPINTX_B2BSTUP (1 << 6) +/* Bit 5 - Reserved */ +#define OTG_FS_DOEPINTX_OTEPDIS (1 << 4) +#define OTG_FS_DOEPINTX_STUP (1 << 3) +/* Bit 2 - Reserved */ +#define OTG_FS_DOEPINTX_EPDISD (1 << 1) +#define OTG_FS_DOEPINTX_XFRC (1 << 0) + +/* OTG_FS Device OUT Endpoint 0 Transfer Size Regsiter (OTG_FS_DOEPTSIZ0) */ +/* Bit 31 - Reserved */ +#define OTG_FS_DIEPSIZ0_STUPCNT_1 (0x1 << 29) +#define OTG_FS_DIEPSIZ0_STUPCNT_2 (0x2 << 29) +#define OTG_FS_DIEPSIZ0_STUPCNT_3 (0x3 << 29) +#define OTG_FS_DIEPSIZ0_STUPCNT_MASK (0x3 << 29) +/* Bits 28:20 - Reserved */ +#define OTG_FS_DIEPSIZ0_PKTCNT (1 << 19) +/* Bits 18:7 - Reserved */ +#define OTG_FS_DIEPSIZ0_XFRSIZ_MASK (0x7f << 0) + +#endif + diff --git a/include/libopencm3/stm32/tools.h b/include/libopencm3/stm32/tools.h new file mode 100644 index 0000000..ac7f0bf --- /dev/null +++ b/include/libopencm3/stm32/tools.h @@ -0,0 +1,64 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Piotr Esden-Tempski + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef LIBOPENCM3_TOOLS_H +#define LIBOPENCM3_TOOLS_H + +/* + * Register accessors / manipulators + */ + +/* Get register content. */ +#define GET_REG(REG) ((u16) *REG) + +/* Set register content. */ +#define SET_REG(REG, VAL) (*REG = (u16)VAL) + +/* Clear register bit. */ +#define CLR_REG_BIT(REG, BIT) SET_REG(REG, (~BIT)) + +/* Clear register bit masking out some bits that must not be touched. */ +#define CLR_REG_BIT_MSK(REG, MSK, BIT) \ + SET_REG(REG, (GET_REG(REG) & MSK & (~BIT))) + +/* Get masked out bit value. */ +#define GET_REG_BIT(REG, BIT) (GET_REG(REG) & BIT) + +/* + * Set/reset a bit in a masked window by using toggle mechanism. + * + * This means that we look at the bits in the bit window designated by + * the mask. If the bit in the masked window is not matching the + * bitmask BIT then we write 1 and if the bit in the masked window is + * matching the bitmask BIT we write 0. + * + * TODO: We may need a faster implementation of that one? + */ +#define TOG_SET_REG_BIT_MSK(REG, MSK, BIT) \ +do { \ + register u16 toggle_mask = GET_REG(REG) & (MSK); \ + register u16 bit_selector; \ + for (bit_selector = 1; bit_selector; bit_selector <<= 1) { \ + if ((bit_selector & (BIT)) != 0) \ + toggle_mask ^= bit_selector; \ + } \ + SET_REG(REG, toggle_mask); \ +} while(0) + +#endif -- cgit v1.2.3 From 7518bc83c1b5b2f4f363ec43478b4d1320e0a8ef Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Tue, 27 Sep 2011 17:18:15 -0700 Subject: Fixing some header references --- lib/stm32f1/scb.c | 2 +- lib/usb/usb_f103.c | 2 +- lib/usb/usb_f107.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/lib/stm32f1/scb.c b/lib/stm32f1/scb.c index dfee6c3..54c5776 100644 --- a/lib/stm32f1/scb.c +++ b/lib/stm32f1/scb.c @@ -17,7 +17,7 @@ * along with this program. If not, see . */ -#include +#include void scb_reset_core(void) { diff --git a/lib/usb/usb_f103.c b/lib/usb/usb_f103.c index 594d3c6..274d4e9 100644 --- a/lib/usb/usb_f103.c +++ b/lib/usb/usb_f103.c @@ -17,7 +17,7 @@ * along with this program. If not, see . */ -#include +#include #include #include #include diff --git a/lib/usb/usb_f107.c b/lib/usb/usb_f107.c index 134b728..65c76b4 100644 --- a/lib/usb/usb_f107.c +++ b/lib/usb/usb_f107.c @@ -17,7 +17,7 @@ * along with this program. If not, see . */ -#include +#include #include #include #include -- cgit v1.2.3 From 14dcda91b06c517d5a7e5485ceac040d72978a31 Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Tue, 27 Sep 2011 17:19:24 -0700 Subject: Fixing some more header references --- lib/usb/usb_f103.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/usb/usb_f103.c b/lib/usb/usb_f103.c index 274d4e9..ea173d7 100644 --- a/lib/usb/usb_f103.c +++ b/lib/usb/usb_f103.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include #include "usb_private.h" -- cgit v1.2.3 From 878c0948719436f36862feef3908ed0c78cccbdd Mon Sep 17 00:00:00 2001 From: Fergus Noble Date: Tue, 4 Oct 2011 16:06:01 -0700 Subject: Added alternative function for doing an SPI transfer. --- include/libopencm3/stm32/spi.h | 1 + lib/stm32_common/spi.c | 16 +++++++++++++++- 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/include/libopencm3/stm32/spi.h b/include/libopencm3/stm32/spi.h index 3cadaf8..3036657 100644 --- a/include/libopencm3/stm32/spi.h +++ b/include/libopencm3/stm32/spi.h @@ -290,6 +290,7 @@ void spi_disable(u32 spi); void spi_write(u32 spi, u16 data); void spi_send(u32 spi, u16 data); u16 spi_read(u32 spi); +u16 spi_xfer(u32 spi, u16 data); void spi_set_bidirectional_mode(u32 spi); void spi_set_unidirectional_mode(u32 spi); void spi_set_bidirectional_receive_only_mode(u32 spi); diff --git a/lib/stm32_common/spi.c b/lib/stm32_common/spi.c index 7fb8711..71bb846 100644 --- a/lib/stm32_common/spi.c +++ b/lib/stm32_common/spi.c @@ -77,7 +77,7 @@ void spi_write(u32 spi, u16 data) void spi_send(u32 spi, u16 data) { /* wait for transfer finished */ - while (SPI_SR(spi) & SPI_SR_BSY ); + while (!(SPI_SR(spi) & SPI_SR_TXE )); /* Write data (8 or 16 bits, depending on DFF) into DR. */ SPI_DR(spi) = data; @@ -85,6 +85,20 @@ void spi_send(u32 spi, u16 data) u16 spi_read(u32 spi) { + /* wait for transfer finished */ + while (!(SPI_SR(spi) & SPI_SR_RXNE )); + + /* Read the data (8 or 16 bits, depending on DFF bit) from DR. */ + return SPI_DR(spi); +} + +u16 spi_xfer(u32 spi, u16 data) +{ + spi_write(spi, data); + + /* wait for transfer finished */ + while (!(SPI_SR(spi) & SPI_SR_RXNE )); + /* Read the data (8 or 16 bits, depending on DFF bit) from DR. */ return SPI_DR(spi); } -- cgit v1.2.3 From 8ceeb99902786041184800248eca4d7f3741d9bf Mon Sep 17 00:00:00 2001 From: Stephen Caudle Date: Wed, 12 Oct 2011 23:58:27 -0400 Subject: Fix stm32f1 filenames and path --- examples/stm32f1/Makefile.include | 16 ++++++++-------- examples/stm32f1/lisa-m/fancyblink/fancyblink.c | 4 ++-- examples/stm32f1/lisa-m/fancyblink/fancyblink.ld | 2 +- examples/stm32f1/lisa-m/usb_dfu/usbdfu.c | 8 ++++---- examples/stm32f1/lisa-m/usb_dfu/usbdfu.ld | 2 +- examples/stm32f1/lisa-m/usb_hid/usbhid.c | 6 +++--- examples/stm32f1/lisa-m/usb_hid/usbhid.ld | 2 +- examples/stm32f1/mb525/fancyblink/fancyblink.c | 4 ++-- examples/stm32f1/mb525/fancyblink/fancyblink.ld | 2 +- examples/stm32f1/mb525/pwmleds/pwmleds.c | 4 ++-- examples/stm32f1/mb525/pwmleds/pwmleds.ld | 2 +- examples/stm32f1/obldc/can/can.c | 6 +++--- examples/stm32f1/obldc/can/can.ld | 2 +- examples/stm32f1/obldc/led/led.c | 4 ++-- examples/stm32f1/obldc/led/led.ld | 2 +- examples/stm32f1/obldc/pwmleds/pwmleds.c | 4 ++-- examples/stm32f1/obldc/pwmleds/pwmleds.ld | 2 +- examples/stm32f1/obldc/systick/systick.c | 6 +++--- examples/stm32f1/obldc/systick/systick.ld | 2 +- examples/stm32f1/obldc/usart/usart.c | 6 +++--- examples/stm32f1/obldc/usart/usart.ld | 2 +- examples/stm32f1/obldc/usart_irq/usart_irq.c | 6 +++--- examples/stm32f1/obldc/usart_irq/usart_irq.ld | 2 +- examples/stm32f1/other/adc_temperature_sensor/adc.c | 10 +++++----- examples/stm32f1/other/adc_temperature_sensor/adc.ld | 2 +- examples/stm32f1/other/dma_mem2mem/dma.c | 10 +++++----- examples/stm32f1/other/dma_mem2mem/dma.ld | 2 +- examples/stm32f1/other/dogm128/dogm128.h | 2 +- examples/stm32f1/other/dogm128/main.c | 6 +++--- examples/stm32f1/other/dogm128/main.ld | 2 +- .../stm32f1/other/i2c_stts75_sensor/i2c_stts75_sensor.c | 8 ++++---- .../stm32f1/other/i2c_stts75_sensor/i2c_stts75_sensor.ld | 2 +- examples/stm32f1/other/rtc/rtc.c | 8 ++++---- examples/stm32f1/other/rtc/rtc.ld | 2 +- examples/stm32f1/other/systick/systick.c | 6 +++--- examples/stm32f1/other/systick/systick.ld | 2 +- examples/stm32f1/other/timer_interrupt/timer.c | 6 +++--- examples/stm32f1/other/timer_interrupt/timer.ld | 2 +- examples/stm32f1/other/usb_cdcacm/cdcacm.c | 4 ++-- examples/stm32f1/other/usb_cdcacm/cdcacm.ld | 2 +- examples/stm32f1/other/usb_dfu/usbdfu.c | 8 ++++---- examples/stm32f1/other/usb_dfu/usbdfu.ld | 2 +- examples/stm32f1/other/usb_hid/usbhid.c | 6 +++--- examples/stm32f1/other/usb_hid/usbhid.ld | 2 +- examples/stm32f1/stm32-discovery/button/button.c | 4 ++-- examples/stm32f1/stm32-discovery/button/button.ld | 2 +- examples/stm32f1/stm32-discovery/fancyblink/fancyblink.c | 4 ++-- .../stm32f1/stm32-discovery/fancyblink/fancyblink.ld | 2 +- examples/stm32f1/stm32-discovery/miniblink/miniblink.c | 4 ++-- examples/stm32f1/stm32-discovery/miniblink/miniblink.ld | 2 +- examples/stm32f1/stm32-discovery/rtc/rtc.c | 6 +++--- examples/stm32f1/stm32-discovery/rtc/rtc.ld | 2 +- examples/stm32f1/stm32-discovery/usart/usart.c | 4 ++-- examples/stm32f1/stm32-discovery/usart/usart.ld | 2 +- examples/stm32f1/stm32-h103/button/button.c | 4 ++-- examples/stm32f1/stm32-h103/button/button.ld | 2 +- examples/stm32f1/stm32-h103/exti_both/exti_both.c | 4 ++-- examples/stm32f1/stm32-h103/exti_both/exti_both.ld | 2 +- .../stm32-h103/exti_rising_falling/exti_rising_falling.c | 4 ++-- .../exti_rising_falling/exti_rising_falling.ld | 2 +- examples/stm32f1/stm32-h103/fancyblink/fancyblink.c | 4 ++-- examples/stm32f1/stm32-h103/fancyblink/fancyblink.ld | 2 +- examples/stm32f1/stm32-h103/led_stripe/led_stripe.c | 4 ++-- examples/stm32f1/stm32-h103/led_stripe/led_stripe.ld | 2 +- examples/stm32f1/stm32-h103/miniblink/miniblink.c | 4 ++-- examples/stm32f1/stm32-h103/miniblink/miniblink.ld | 2 +- examples/stm32f1/stm32-h103/pwm_6step/pwm_6step.c | 6 +++--- examples/stm32f1/stm32-h103/pwm_6step/pwm_6step.ld | 2 +- examples/stm32f1/stm32-h103/spi/spi.c | 2 +- examples/stm32f1/stm32-h103/spi/spi.ld | 2 +- examples/stm32f1/stm32-h103/timer/timer.c | 6 +++--- examples/stm32f1/stm32-h103/timer/timer.ld | 2 +- examples/stm32f1/stm32-h103/traceswo/traceswo.c | 4 ++-- examples/stm32f1/stm32-h103/traceswo/traceswo.ld | 2 +- examples/stm32f1/stm32-h103/usart/usart.c | 10 +++++----- examples/stm32f1/stm32-h103/usart/usart.ld | 2 +- examples/stm32f1/stm32-h103/usart_irq/usart_irq.c | 6 +++--- examples/stm32f1/stm32-h103/usart_irq/usart_irq.ld | 2 +- .../stm32-h103/usart_irq_printf/usart_irq_printf.c | 6 +++--- .../stm32-h103/usart_irq_printf/usart_irq_printf.ld | 2 +- examples/stm32f1/stm32-h103/usart_printf/usart_printf.c | 6 +++--- examples/stm32f1/stm32-h103/usart_printf/usart_printf.ld | 2 +- examples/stm32f1/stm32-h103/usb_cdcacm/cdcacm.c | 4 ++-- examples/stm32f1/stm32-h103/usb_cdcacm/cdcacm.ld | 2 +- examples/stm32f1/stm32-h103/usb_dfu/usbdfu.c | 8 ++++---- examples/stm32f1/stm32-h103/usb_dfu/usbdfu.ld | 2 +- examples/stm32f1/stm32-h103/usb_hid/usbhid.c | 6 +++--- examples/stm32f1/stm32-h103/usb_hid/usbhid.ld | 2 +- examples/stm32f1/stm32-h103/usb_iap/usbiap.c | 8 ++++---- examples/stm32f1/stm32-h103/usb_iap/usbiap.ld | 2 +- examples/stm32f1/stm32-h107/fancyblink/fancyblink.c | 4 ++-- examples/stm32f1/stm32-h107/fancyblink/fancyblink.ld | 2 +- examples/stm32f1/stm32-h107/usb_simple/usb_simple.c | 4 ++-- examples/stm32f1/stm32-h107/usb_simple/usb_simple.ld | 2 +- examples/stm32f2/jobygps/usart_printf/usart_printf.ld | 2 +- 95 files changed, 184 insertions(+), 184 deletions(-) diff --git a/examples/stm32f1/Makefile.include b/examples/stm32f1/Makefile.include index 221ebae..82e6d2a 100644 --- a/examples/stm32f1/Makefile.include +++ b/examples/stm32f1/Makefile.include @@ -25,12 +25,12 @@ LD = $(PREFIX)-gcc OBJCOPY = $(PREFIX)-objcopy OBJDUMP = $(PREFIX)-objdump # Uncomment this line if you want to use the installed (not local) library. -TOOLCHAIN_DIR := $(shell dirname `which $(CC)`)/../$(PREFIX) -#TOOLCHAIN_DIR = ../../../.. +#TOOLCHAIN_DIR := $(shell dirname `which $(CC)`)/../$(PREFIX) +TOOLCHAIN_DIR = ../../../.. CFLAGS += -Os -g -Wall -Wextra -I$(TOOLCHAIN_DIR)/include \ - -fno-common -mcpu=cortex-m3 -mthumb -msoft-float -MD + -fno-common -mcpu=cortex-m3 -mthumb -msoft-float -MD -DSTM32F1 LDSCRIPT = $(BINARY).ld -LDFLAGS += -lc -lnosys -L$(TOOLCHAIN_DIR)/lib -L$(TOOLCHAIN_DIR)/lib/stm32 \ +LDFLAGS += -lc -lnosys -L$(TOOLCHAIN_DIR)/lib -L$(TOOLCHAIN_DIR)/lib/stm32f1 \ -T$(LDSCRIPT) -nostartfiles -Wl,--gc-sections \ -mthumb -march=armv7 -mfix-cortex-m3-ldrd -msoft-float OBJS += $(BINARY).o @@ -75,13 +75,13 @@ flash: $(BINARY).flash @#printf " OBJDUMP $(*).list\n" $(Q)$(OBJDUMP) -S $(*).elf > $(*).list -foo.elf: $(OBJS) $(LDSCRIPT) $(TOOLCHAIN_DIR)/lib/libopencm3_stm32.a +foo.elf: $(OBJS) $(LDSCRIPT) $(TOOLCHAIN_DIR)/lib/stm32f1/libopencm3_stm32f1.a @#printf " LD $(subst $(shell pwd)/,,$(@))\n" - $(Q)$(LD) -o foo.elf $(OBJS) -lopencm3_stm32 $(LDFLAGS) + $(Q)$(LD) -o foo.elf $(OBJS) -lopencm3_stm32f1 $(LDFLAGS) -%.elf: $(OBJS) $(LDSCRIPT) $(TOOLCHAIN_DIR)/lib/libopencm3_stm32.a +%.elf: $(OBJS) $(LDSCRIPT) $(TOOLCHAIN_DIR)/lib/stm32f1/libopencm3_stm32f1.a @#printf " LD $(subst $(shell pwd)/,,$(@))\n" - $(Q)$(LD) -o $(*).elf $(OBJS) -lopencm3_stm32 $(LDFLAGS) + $(Q)$(LD) -o $(*).elf $(OBJS) -lopencm3_stm32f1 $(LDFLAGS) %.o: %.c Makefile @#printf " CC $(subst $(shell pwd)/,,$(@))\n" diff --git a/examples/stm32f1/lisa-m/fancyblink/fancyblink.c b/examples/stm32f1/lisa-m/fancyblink/fancyblink.c index 5987bdf..6d5fbe3 100644 --- a/examples/stm32f1/lisa-m/fancyblink/fancyblink.c +++ b/examples/stm32f1/lisa-m/fancyblink/fancyblink.c @@ -18,8 +18,8 @@ * along with this program. If not, see . */ -#include -#include +#include +#include /* Set STM32 to 72 MHz. */ void clock_setup(void) diff --git a/examples/stm32f1/lisa-m/fancyblink/fancyblink.ld b/examples/stm32f1/lisa-m/fancyblink/fancyblink.ld index 7ea2b92..3409b98 100644 --- a/examples/stm32f1/lisa-m/fancyblink/fancyblink.ld +++ b/examples/stm32f1/lisa-m/fancyblink/fancyblink.ld @@ -27,5 +27,5 @@ MEMORY } /* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld +INCLUDE libopencm3_stm32f1.ld diff --git a/examples/stm32f1/lisa-m/usb_dfu/usbdfu.c b/examples/stm32f1/lisa-m/usb_dfu/usbdfu.c index 7ffbc74..9d184f1 100644 --- a/examples/stm32f1/lisa-m/usb_dfu/usbdfu.c +++ b/examples/stm32f1/lisa-m/usb_dfu/usbdfu.c @@ -18,10 +18,10 @@ */ #include -#include -#include -#include -#include +#include +#include +#include +#include #include #include diff --git a/examples/stm32f1/lisa-m/usb_dfu/usbdfu.ld b/examples/stm32f1/lisa-m/usb_dfu/usbdfu.ld index 54e5dac..6a01797 100644 --- a/examples/stm32f1/lisa-m/usb_dfu/usbdfu.ld +++ b/examples/stm32f1/lisa-m/usb_dfu/usbdfu.ld @@ -25,5 +25,5 @@ MEMORY } /* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld +INCLUDE libopencm3_stm32f1.ld diff --git a/examples/stm32f1/lisa-m/usb_hid/usbhid.c b/examples/stm32f1/lisa-m/usb_hid/usbhid.c index f42454b..cd9d97d 100644 --- a/examples/stm32f1/lisa-m/usb_hid/usbhid.c +++ b/examples/stm32f1/lisa-m/usb_hid/usbhid.c @@ -19,8 +19,8 @@ */ #include -#include -#include +#include +#include #include #include #include @@ -30,7 +30,7 @@ #define INCLUDE_DFU_INTERFACE #ifdef INCLUDE_DFU_INTERFACE -#include +#include #include #endif diff --git a/examples/stm32f1/lisa-m/usb_hid/usbhid.ld b/examples/stm32f1/lisa-m/usb_hid/usbhid.ld index 928c898..d0df9e6 100644 --- a/examples/stm32f1/lisa-m/usb_hid/usbhid.ld +++ b/examples/stm32f1/lisa-m/usb_hid/usbhid.ld @@ -27,5 +27,5 @@ MEMORY } /* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld +INCLUDE libopencm3_stm32f1.ld diff --git a/examples/stm32f1/mb525/fancyblink/fancyblink.c b/examples/stm32f1/mb525/fancyblink/fancyblink.c index e9a3564..54ef47c 100644 --- a/examples/stm32f1/mb525/fancyblink/fancyblink.c +++ b/examples/stm32f1/mb525/fancyblink/fancyblink.c @@ -18,8 +18,8 @@ * along with this program. If not, see . */ -#include -#include +#include +#include void clock_setup(void) { diff --git a/examples/stm32f1/mb525/fancyblink/fancyblink.ld b/examples/stm32f1/mb525/fancyblink/fancyblink.ld index 7ea2b92..3409b98 100644 --- a/examples/stm32f1/mb525/fancyblink/fancyblink.ld +++ b/examples/stm32f1/mb525/fancyblink/fancyblink.ld @@ -27,5 +27,5 @@ MEMORY } /* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld +INCLUDE libopencm3_stm32f1.ld diff --git a/examples/stm32f1/mb525/pwmleds/pwmleds.c b/examples/stm32f1/mb525/pwmleds/pwmleds.c index 393928f..5505231 100644 --- a/examples/stm32f1/mb525/pwmleds/pwmleds.c +++ b/examples/stm32f1/mb525/pwmleds/pwmleds.c @@ -17,8 +17,8 @@ * along with this program. If not, see . */ -#include -#include +#include +#include #include // #define COMPARE diff --git a/examples/stm32f1/mb525/pwmleds/pwmleds.ld b/examples/stm32f1/mb525/pwmleds/pwmleds.ld index 7ea2b92..3409b98 100644 --- a/examples/stm32f1/mb525/pwmleds/pwmleds.ld +++ b/examples/stm32f1/mb525/pwmleds/pwmleds.ld @@ -27,5 +27,5 @@ MEMORY } /* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld +INCLUDE libopencm3_stm32f1.ld diff --git a/examples/stm32f1/obldc/can/can.c b/examples/stm32f1/obldc/can/can.c index 6c63c48..00a05dc 100644 --- a/examples/stm32f1/obldc/can/can.c +++ b/examples/stm32f1/obldc/can/can.c @@ -18,9 +18,9 @@ * along with this program. If not, see . */ -#include -#include -#include +#include +#include +#include #include #include #include diff --git a/examples/stm32f1/obldc/can/can.ld b/examples/stm32f1/obldc/can/can.ld index c076521..4f609a8 100644 --- a/examples/stm32f1/obldc/can/can.ld +++ b/examples/stm32f1/obldc/can/can.ld @@ -27,5 +27,5 @@ MEMORY } /* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld +INCLUDE libopencm3_stm32f1.ld diff --git a/examples/stm32f1/obldc/led/led.c b/examples/stm32f1/obldc/led/led.c index 09ae89d..db479b2 100644 --- a/examples/stm32f1/obldc/led/led.c +++ b/examples/stm32f1/obldc/led/led.c @@ -18,8 +18,8 @@ * along with this program. If not, see . */ -#include -#include +#include +#include /* Set STM32 to 72 MHz. */ void clock_setup(void) diff --git a/examples/stm32f1/obldc/led/led.ld b/examples/stm32f1/obldc/led/led.ld index 7899773..edb52c5 100644 --- a/examples/stm32f1/obldc/led/led.ld +++ b/examples/stm32f1/obldc/led/led.ld @@ -27,5 +27,5 @@ MEMORY } /* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld +INCLUDE libopencm3_stm32f1.ld diff --git a/examples/stm32f1/obldc/pwmleds/pwmleds.c b/examples/stm32f1/obldc/pwmleds/pwmleds.c index 146bb56..faa9aa0 100644 --- a/examples/stm32f1/obldc/pwmleds/pwmleds.c +++ b/examples/stm32f1/obldc/pwmleds/pwmleds.c @@ -17,8 +17,8 @@ * along with this program. If not, see . */ -#include -#include +#include +#include #include // #define COMPARE diff --git a/examples/stm32f1/obldc/pwmleds/pwmleds.ld b/examples/stm32f1/obldc/pwmleds/pwmleds.ld index 7ea2b92..3409b98 100644 --- a/examples/stm32f1/obldc/pwmleds/pwmleds.ld +++ b/examples/stm32f1/obldc/pwmleds/pwmleds.ld @@ -27,5 +27,5 @@ MEMORY } /* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld +INCLUDE libopencm3_stm32f1.ld diff --git a/examples/stm32f1/obldc/systick/systick.c b/examples/stm32f1/obldc/systick/systick.c index 3d75c4a..263230f 100644 --- a/examples/stm32f1/obldc/systick/systick.c +++ b/examples/stm32f1/obldc/systick/systick.c @@ -18,9 +18,9 @@ * along with this program. If not, see . */ -#include -#include -#include +#include +#include +#include #include #include diff --git a/examples/stm32f1/obldc/systick/systick.ld b/examples/stm32f1/obldc/systick/systick.ld index da4f2b3..a3195d2 100644 --- a/examples/stm32f1/obldc/systick/systick.ld +++ b/examples/stm32f1/obldc/systick/systick.ld @@ -27,5 +27,5 @@ MEMORY } /* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld +INCLUDE libopencm3_stm32f1.ld diff --git a/examples/stm32f1/obldc/usart/usart.c b/examples/stm32f1/obldc/usart/usart.c index ea5ec0e..b2efe71 100644 --- a/examples/stm32f1/obldc/usart/usart.c +++ b/examples/stm32f1/obldc/usart/usart.c @@ -17,8 +17,8 @@ * along with this program. If not, see . */ -#include -#include +#include +#include #include void clock_setup(void) @@ -47,7 +47,7 @@ void usart_setup(void) GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_USART1_RE_TX); /* Setup UART parameters. */ - usart_set_baudrate(USART1, 230400); + usart_set_baudrate(USART1, 230400, rcc_ppre2_frequency); usart_set_databits(USART1, 8); usart_set_stopbits(USART1, USART_STOPBITS_1); usart_set_mode(USART1, USART_MODE_TX); diff --git a/examples/stm32f1/obldc/usart/usart.ld b/examples/stm32f1/obldc/usart/usart.ld index 7899773..edb52c5 100644 --- a/examples/stm32f1/obldc/usart/usart.ld +++ b/examples/stm32f1/obldc/usart/usart.ld @@ -27,5 +27,5 @@ MEMORY } /* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld +INCLUDE libopencm3_stm32f1.ld diff --git a/examples/stm32f1/obldc/usart_irq/usart_irq.c b/examples/stm32f1/obldc/usart_irq/usart_irq.c index 82320c1..20ff0a1 100644 --- a/examples/stm32f1/obldc/usart_irq/usart_irq.c +++ b/examples/stm32f1/obldc/usart_irq/usart_irq.c @@ -17,8 +17,8 @@ * along with this program. If not, see . */ -#include -#include +#include +#include #include #include @@ -52,7 +52,7 @@ void usart_setup(void) GPIO_CNF_INPUT_FLOAT, GPIO_USART1_RE_RX); /* Setup UART parameters. */ - usart_set_baudrate(USART1, 230400); + usart_set_baudrate(USART1, 230400, rcc_ppre2_frequency); usart_set_databits(USART1, 8); usart_set_stopbits(USART1, USART_STOPBITS_1); usart_set_parity(USART1, USART_PARITY_NONE); diff --git a/examples/stm32f1/obldc/usart_irq/usart_irq.ld b/examples/stm32f1/obldc/usart_irq/usart_irq.ld index 7899773..edb52c5 100644 --- a/examples/stm32f1/obldc/usart_irq/usart_irq.ld +++ b/examples/stm32f1/obldc/usart_irq/usart_irq.ld @@ -27,5 +27,5 @@ MEMORY } /* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld +INCLUDE libopencm3_stm32f1.ld diff --git a/examples/stm32f1/other/adc_temperature_sensor/adc.c b/examples/stm32f1/other/adc_temperature_sensor/adc.c index 6c0e828..a87909c 100644 --- a/examples/stm32f1/other/adc_temperature_sensor/adc.c +++ b/examples/stm32f1/other/adc_temperature_sensor/adc.c @@ -17,11 +17,11 @@ * along with this program. If not, see . */ -#include -#include -#include +#include +#include +#include +#include #include -#include void usart_setup(void) { @@ -34,7 +34,7 @@ void usart_setup(void) GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_USART1_TX); /* Setup UART parameters. */ - usart_set_baudrate(USART1, 115200); + usart_set_baudrate(USART1, 115200, rcc_ppre2_frequency); usart_set_databits(USART1, 8); usart_set_stopbits(USART1, USART_STOPBITS_1); usart_set_mode(USART1, USART_MODE_TX_RX); diff --git a/examples/stm32f1/other/adc_temperature_sensor/adc.ld b/examples/stm32f1/other/adc_temperature_sensor/adc.ld index c076521..4f609a8 100644 --- a/examples/stm32f1/other/adc_temperature_sensor/adc.ld +++ b/examples/stm32f1/other/adc_temperature_sensor/adc.ld @@ -27,5 +27,5 @@ MEMORY } /* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld +INCLUDE libopencm3_stm32f1.ld diff --git a/examples/stm32f1/other/dma_mem2mem/dma.c b/examples/stm32f1/other/dma_mem2mem/dma.c index e43fe0d..0389412 100644 --- a/examples/stm32f1/other/dma_mem2mem/dma.c +++ b/examples/stm32f1/other/dma_mem2mem/dma.c @@ -17,11 +17,11 @@ * along with this program. If not, see . */ -#include -#include -#include +#include +#include +#include +#include #include -#include void usart_setup(void) { @@ -34,7 +34,7 @@ void usart_setup(void) GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_USART1_TX); /* Setup UART parameters. */ - usart_set_baudrate(USART1, 115200); + usart_set_baudrate(USART1, 115200, rcc_ppre2_frequency); usart_set_databits(USART1, 8); usart_set_stopbits(USART1, USART_STOPBITS_1); usart_set_mode(USART1, USART_MODE_TX_RX); diff --git a/examples/stm32f1/other/dma_mem2mem/dma.ld b/examples/stm32f1/other/dma_mem2mem/dma.ld index c076521..4f609a8 100644 --- a/examples/stm32f1/other/dma_mem2mem/dma.ld +++ b/examples/stm32f1/other/dma_mem2mem/dma.ld @@ -27,5 +27,5 @@ MEMORY } /* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld +INCLUDE libopencm3_stm32f1.ld diff --git a/examples/stm32f1/other/dogm128/dogm128.h b/examples/stm32f1/other/dogm128/dogm128.h index ed514ab..de43225 100644 --- a/examples/stm32f1/other/dogm128/dogm128.h +++ b/examples/stm32f1/other/dogm128/dogm128.h @@ -21,7 +21,7 @@ #define DOGM128_H #include -#include +#include #include /* PB10 GPIO - ~RESET diff --git a/examples/stm32f1/other/dogm128/main.c b/examples/stm32f1/other/dogm128/main.c index b12a36d..508971e 100644 --- a/examples/stm32f1/other/dogm128/main.c +++ b/examples/stm32f1/other/dogm128/main.c @@ -17,9 +17,9 @@ * along with this program. If not, see . */ -#include -#include -#include +#include +#include +#include #include #include #include diff --git a/examples/stm32f1/other/dogm128/main.ld b/examples/stm32f1/other/dogm128/main.ld index c076521..4f609a8 100644 --- a/examples/stm32f1/other/dogm128/main.ld +++ b/examples/stm32f1/other/dogm128/main.ld @@ -27,5 +27,5 @@ MEMORY } /* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld +INCLUDE libopencm3_stm32f1.ld diff --git a/examples/stm32f1/other/i2c_stts75_sensor/i2c_stts75_sensor.c b/examples/stm32f1/other/i2c_stts75_sensor/i2c_stts75_sensor.c index f70c80d..d8f2404 100644 --- a/examples/stm32f1/other/i2c_stts75_sensor/i2c_stts75_sensor.c +++ b/examples/stm32f1/other/i2c_stts75_sensor/i2c_stts75_sensor.c @@ -17,9 +17,9 @@ * along with this program. If not, see . */ -#include -#include -#include +#include +#include +#include #include #include #include "stts75.h" @@ -35,7 +35,7 @@ void usart_setup(void) GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_USART1_TX); /* Setup UART parameters. */ - usart_set_baudrate(USART1, 115200); + usart_set_baudrate(USART1, 115200, rcc_ppre2_frequency); usart_set_databits(USART1, 8); usart_set_stopbits(USART1, USART_STOPBITS_1); usart_set_mode(USART1, USART_MODE_TX_RX); diff --git a/examples/stm32f1/other/i2c_stts75_sensor/i2c_stts75_sensor.ld b/examples/stm32f1/other/i2c_stts75_sensor/i2c_stts75_sensor.ld index c076521..4f609a8 100644 --- a/examples/stm32f1/other/i2c_stts75_sensor/i2c_stts75_sensor.ld +++ b/examples/stm32f1/other/i2c_stts75_sensor/i2c_stts75_sensor.ld @@ -27,5 +27,5 @@ MEMORY } /* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld +INCLUDE libopencm3_stm32f1.ld diff --git a/examples/stm32f1/other/rtc/rtc.c b/examples/stm32f1/other/rtc/rtc.c index c447534..28ae24c 100644 --- a/examples/stm32f1/other/rtc/rtc.c +++ b/examples/stm32f1/other/rtc/rtc.c @@ -17,10 +17,10 @@ * along with this program. If not, see . */ -#include -#include +#include +#include +#include #include -#include #include #include @@ -43,7 +43,7 @@ void usart_setup(void) GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_USART1_TX); /* Setup UART parameters. */ - usart_set_baudrate(USART1, 38400); + usart_set_baudrate(USART1, 38400, rcc_ppre2_frequency); usart_set_databits(USART1, 8); usart_set_stopbits(USART1, USART_STOPBITS_1); usart_set_mode(USART1, USART_MODE_TX); diff --git a/examples/stm32f1/other/rtc/rtc.ld b/examples/stm32f1/other/rtc/rtc.ld index 7ea2b92..3409b98 100644 --- a/examples/stm32f1/other/rtc/rtc.ld +++ b/examples/stm32f1/other/rtc/rtc.ld @@ -27,5 +27,5 @@ MEMORY } /* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld +INCLUDE libopencm3_stm32f1.ld diff --git a/examples/stm32f1/other/systick/systick.c b/examples/stm32f1/other/systick/systick.c index c05aff7..173ff2a 100644 --- a/examples/stm32f1/other/systick/systick.c +++ b/examples/stm32f1/other/systick/systick.c @@ -17,9 +17,9 @@ * along with this program. If not, see . */ -#include -#include -#include +#include +#include +#include #include #include diff --git a/examples/stm32f1/other/systick/systick.ld b/examples/stm32f1/other/systick/systick.ld index c076521..4f609a8 100644 --- a/examples/stm32f1/other/systick/systick.ld +++ b/examples/stm32f1/other/systick/systick.ld @@ -27,5 +27,5 @@ MEMORY } /* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld +INCLUDE libopencm3_stm32f1.ld diff --git a/examples/stm32f1/other/timer_interrupt/timer.c b/examples/stm32f1/other/timer_interrupt/timer.c index aa2cdb6..422df88 100644 --- a/examples/stm32f1/other/timer_interrupt/timer.c +++ b/examples/stm32f1/other/timer_interrupt/timer.c @@ -17,9 +17,9 @@ * along with this program. If not, see . */ -#include -#include -#include +#include +#include +#include #include #include diff --git a/examples/stm32f1/other/timer_interrupt/timer.ld b/examples/stm32f1/other/timer_interrupt/timer.ld index c076521..4f609a8 100644 --- a/examples/stm32f1/other/timer_interrupt/timer.ld +++ b/examples/stm32f1/other/timer_interrupt/timer.ld @@ -27,5 +27,5 @@ MEMORY } /* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld +INCLUDE libopencm3_stm32f1.ld diff --git a/examples/stm32f1/other/usb_cdcacm/cdcacm.c b/examples/stm32f1/other/usb_cdcacm/cdcacm.c index fdc92e2..d26b898 100644 --- a/examples/stm32f1/other/usb_cdcacm/cdcacm.c +++ b/examples/stm32f1/other/usb_cdcacm/cdcacm.c @@ -18,8 +18,8 @@ */ #include -#include -#include +#include +#include #include #include diff --git a/examples/stm32f1/other/usb_cdcacm/cdcacm.ld b/examples/stm32f1/other/usb_cdcacm/cdcacm.ld index 1c20282..3cd6316 100644 --- a/examples/stm32f1/other/usb_cdcacm/cdcacm.ld +++ b/examples/stm32f1/other/usb_cdcacm/cdcacm.ld @@ -25,5 +25,5 @@ MEMORY } /* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld +INCLUDE libopencm3_stm32f1.ld diff --git a/examples/stm32f1/other/usb_dfu/usbdfu.c b/examples/stm32f1/other/usb_dfu/usbdfu.c index 7ffbc74..9d184f1 100644 --- a/examples/stm32f1/other/usb_dfu/usbdfu.c +++ b/examples/stm32f1/other/usb_dfu/usbdfu.c @@ -18,10 +18,10 @@ */ #include -#include -#include -#include -#include +#include +#include +#include +#include #include #include diff --git a/examples/stm32f1/other/usb_dfu/usbdfu.ld b/examples/stm32f1/other/usb_dfu/usbdfu.ld index 54e5dac..6a01797 100644 --- a/examples/stm32f1/other/usb_dfu/usbdfu.ld +++ b/examples/stm32f1/other/usb_dfu/usbdfu.ld @@ -25,5 +25,5 @@ MEMORY } /* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld +INCLUDE libopencm3_stm32f1.ld diff --git a/examples/stm32f1/other/usb_hid/usbhid.c b/examples/stm32f1/other/usb_hid/usbhid.c index 8f08aac..7c0186e 100644 --- a/examples/stm32f1/other/usb_hid/usbhid.c +++ b/examples/stm32f1/other/usb_hid/usbhid.c @@ -18,8 +18,8 @@ */ #include -#include -#include +#include +#include #include #include #include @@ -28,7 +28,7 @@ #define INCLUDE_DFU_INTERFACE #ifdef INCLUDE_DFU_INTERFACE -#include +#include #include #endif diff --git a/examples/stm32f1/other/usb_hid/usbhid.ld b/examples/stm32f1/other/usb_hid/usbhid.ld index 1c20282..3cd6316 100644 --- a/examples/stm32f1/other/usb_hid/usbhid.ld +++ b/examples/stm32f1/other/usb_hid/usbhid.ld @@ -25,5 +25,5 @@ MEMORY } /* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld +INCLUDE libopencm3_stm32f1.ld diff --git a/examples/stm32f1/stm32-discovery/button/button.c b/examples/stm32f1/stm32-discovery/button/button.c index b84f074..87ce5cc 100644 --- a/examples/stm32f1/stm32-discovery/button/button.c +++ b/examples/stm32f1/stm32-discovery/button/button.c @@ -18,8 +18,8 @@ * along with this program. If not, see . */ -#include -#include +#include +#include u16 exti_line_state; diff --git a/examples/stm32f1/stm32-discovery/button/button.ld b/examples/stm32f1/stm32-discovery/button/button.ld index b03f90f..157204a 100644 --- a/examples/stm32f1/stm32-discovery/button/button.ld +++ b/examples/stm32f1/stm32-discovery/button/button.ld @@ -27,5 +27,5 @@ MEMORY } /* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld +INCLUDE libopencm3_stm32f1.ld diff --git a/examples/stm32f1/stm32-discovery/fancyblink/fancyblink.c b/examples/stm32f1/stm32-discovery/fancyblink/fancyblink.c index d40fb7b..38a4c4b 100644 --- a/examples/stm32f1/stm32-discovery/fancyblink/fancyblink.c +++ b/examples/stm32f1/stm32-discovery/fancyblink/fancyblink.c @@ -19,8 +19,8 @@ * along with this program. If not, see . */ -#include -#include +#include +#include /* Set STM32 to 24 MHz. */ void clock_setup(void) diff --git a/examples/stm32f1/stm32-discovery/fancyblink/fancyblink.ld b/examples/stm32f1/stm32-discovery/fancyblink/fancyblink.ld index b03f90f..157204a 100644 --- a/examples/stm32f1/stm32-discovery/fancyblink/fancyblink.ld +++ b/examples/stm32f1/stm32-discovery/fancyblink/fancyblink.ld @@ -27,5 +27,5 @@ MEMORY } /* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld +INCLUDE libopencm3_stm32f1.ld diff --git a/examples/stm32f1/stm32-discovery/miniblink/miniblink.c b/examples/stm32f1/stm32-discovery/miniblink/miniblink.c index a05f957..973fab5 100644 --- a/examples/stm32f1/stm32-discovery/miniblink/miniblink.c +++ b/examples/stm32f1/stm32-discovery/miniblink/miniblink.c @@ -17,8 +17,8 @@ * along with this program. If not, see . */ -#include -#include +#include +#include void gpio_setup(void) { diff --git a/examples/stm32f1/stm32-discovery/miniblink/miniblink.ld b/examples/stm32f1/stm32-discovery/miniblink/miniblink.ld index b03f90f..157204a 100644 --- a/examples/stm32f1/stm32-discovery/miniblink/miniblink.ld +++ b/examples/stm32f1/stm32-discovery/miniblink/miniblink.ld @@ -27,5 +27,5 @@ MEMORY } /* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld +INCLUDE libopencm3_stm32f1.ld diff --git a/examples/stm32f1/stm32-discovery/rtc/rtc.c b/examples/stm32f1/stm32-discovery/rtc/rtc.c index c99920f..fa8a966 100644 --- a/examples/stm32f1/stm32-discovery/rtc/rtc.c +++ b/examples/stm32f1/stm32-discovery/rtc/rtc.c @@ -18,10 +18,10 @@ * along with this program. If not, see . */ -#include -#include +#include +#include +#include #include -#include #include #include diff --git a/examples/stm32f1/stm32-discovery/rtc/rtc.ld b/examples/stm32f1/stm32-discovery/rtc/rtc.ld index b03f90f..157204a 100644 --- a/examples/stm32f1/stm32-discovery/rtc/rtc.ld +++ b/examples/stm32f1/stm32-discovery/rtc/rtc.ld @@ -27,5 +27,5 @@ MEMORY } /* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld +INCLUDE libopencm3_stm32f1.ld diff --git a/examples/stm32f1/stm32-discovery/usart/usart.c b/examples/stm32f1/stm32-discovery/usart/usart.c index 05d0312..942805b 100644 --- a/examples/stm32f1/stm32-discovery/usart/usart.c +++ b/examples/stm32f1/stm32-discovery/usart/usart.c @@ -17,8 +17,8 @@ * along with this program. If not, see . */ -#include -#include +#include +#include #include void clock_setup(void) diff --git a/examples/stm32f1/stm32-discovery/usart/usart.ld b/examples/stm32f1/stm32-discovery/usart/usart.ld index b03f90f..157204a 100644 --- a/examples/stm32f1/stm32-discovery/usart/usart.ld +++ b/examples/stm32f1/stm32-discovery/usart/usart.ld @@ -27,5 +27,5 @@ MEMORY } /* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld +INCLUDE libopencm3_stm32f1.ld diff --git a/examples/stm32f1/stm32-h103/button/button.c b/examples/stm32f1/stm32-h103/button/button.c index 63f3274..2f3378c 100644 --- a/examples/stm32f1/stm32-h103/button/button.c +++ b/examples/stm32f1/stm32-h103/button/button.c @@ -18,9 +18,9 @@ * along with this program. If not, see . */ +#include +#include #include -#include -#include #include u16 exti_line_state; diff --git a/examples/stm32f1/stm32-h103/button/button.ld b/examples/stm32f1/stm32-h103/button/button.ld index 7ea2b92..3409b98 100644 --- a/examples/stm32f1/stm32-h103/button/button.ld +++ b/examples/stm32f1/stm32-h103/button/button.ld @@ -27,5 +27,5 @@ MEMORY } /* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld +INCLUDE libopencm3_stm32f1.ld diff --git a/examples/stm32f1/stm32-h103/exti_both/exti_both.c b/examples/stm32f1/stm32-h103/exti_both/exti_both.c index edfc676..7c6f9c7 100644 --- a/examples/stm32f1/stm32-h103/exti_both/exti_both.c +++ b/examples/stm32f1/stm32-h103/exti_both/exti_both.c @@ -18,9 +18,9 @@ * along with this program. If not, see . */ +#include +#include #include -#include -#include #include u16 exti_line_state; diff --git a/examples/stm32f1/stm32-h103/exti_both/exti_both.ld b/examples/stm32f1/stm32-h103/exti_both/exti_both.ld index 7ea2b92..3409b98 100644 --- a/examples/stm32f1/stm32-h103/exti_both/exti_both.ld +++ b/examples/stm32f1/stm32-h103/exti_both/exti_both.ld @@ -27,5 +27,5 @@ MEMORY } /* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld +INCLUDE libopencm3_stm32f1.ld diff --git a/examples/stm32f1/stm32-h103/exti_rising_falling/exti_rising_falling.c b/examples/stm32f1/stm32-h103/exti_rising_falling/exti_rising_falling.c index af1268d..b3c47ee 100644 --- a/examples/stm32f1/stm32-h103/exti_rising_falling/exti_rising_falling.c +++ b/examples/stm32f1/stm32-h103/exti_rising_falling/exti_rising_falling.c @@ -18,9 +18,9 @@ * along with this program. If not, see . */ +#include +#include #include -#include -#include #include #define FALLING 0 diff --git a/examples/stm32f1/stm32-h103/exti_rising_falling/exti_rising_falling.ld b/examples/stm32f1/stm32-h103/exti_rising_falling/exti_rising_falling.ld index 7ea2b92..3409b98 100644 --- a/examples/stm32f1/stm32-h103/exti_rising_falling/exti_rising_falling.ld +++ b/examples/stm32f1/stm32-h103/exti_rising_falling/exti_rising_falling.ld @@ -27,5 +27,5 @@ MEMORY } /* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld +INCLUDE libopencm3_stm32f1.ld diff --git a/examples/stm32f1/stm32-h103/fancyblink/fancyblink.c b/examples/stm32f1/stm32-h103/fancyblink/fancyblink.c index eeb3f34..1b2ad86 100644 --- a/examples/stm32f1/stm32-h103/fancyblink/fancyblink.c +++ b/examples/stm32f1/stm32-h103/fancyblink/fancyblink.c @@ -17,8 +17,8 @@ * along with this program. If not, see . */ -#include -#include +#include +#include /* Set STM32 to 72 MHz. */ void clock_setup(void) diff --git a/examples/stm32f1/stm32-h103/fancyblink/fancyblink.ld b/examples/stm32f1/stm32-h103/fancyblink/fancyblink.ld index 7ea2b92..3409b98 100644 --- a/examples/stm32f1/stm32-h103/fancyblink/fancyblink.ld +++ b/examples/stm32f1/stm32-h103/fancyblink/fancyblink.ld @@ -27,5 +27,5 @@ MEMORY } /* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld +INCLUDE libopencm3_stm32f1.ld diff --git a/examples/stm32f1/stm32-h103/led_stripe/led_stripe.c b/examples/stm32f1/stm32-h103/led_stripe/led_stripe.c index 9cf9d4f..1576866 100644 --- a/examples/stm32f1/stm32-h103/led_stripe/led_stripe.c +++ b/examples/stm32f1/stm32-h103/led_stripe/led_stripe.c @@ -26,8 +26,8 @@ #include -#include -#include +#include +#include #define SPI_BANK GPIOB #define SCLK_PIN GPIO13 diff --git a/examples/stm32f1/stm32-h103/led_stripe/led_stripe.ld b/examples/stm32f1/stm32-h103/led_stripe/led_stripe.ld index 7ea2b92..3409b98 100644 --- a/examples/stm32f1/stm32-h103/led_stripe/led_stripe.ld +++ b/examples/stm32f1/stm32-h103/led_stripe/led_stripe.ld @@ -27,5 +27,5 @@ MEMORY } /* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld +INCLUDE libopencm3_stm32f1.ld diff --git a/examples/stm32f1/stm32-h103/miniblink/miniblink.c b/examples/stm32f1/stm32-h103/miniblink/miniblink.c index 6f8bc2c..b003f9a 100644 --- a/examples/stm32f1/stm32-h103/miniblink/miniblink.c +++ b/examples/stm32f1/stm32-h103/miniblink/miniblink.c @@ -17,8 +17,8 @@ * along with this program. If not, see . */ -#include -#include +#include +#include void gpio_setup(void) { diff --git a/examples/stm32f1/stm32-h103/miniblink/miniblink.ld b/examples/stm32f1/stm32-h103/miniblink/miniblink.ld index 7ea2b92..3409b98 100644 --- a/examples/stm32f1/stm32-h103/miniblink/miniblink.ld +++ b/examples/stm32f1/stm32-h103/miniblink/miniblink.ld @@ -27,5 +27,5 @@ MEMORY } /* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld +INCLUDE libopencm3_stm32f1.ld diff --git a/examples/stm32f1/stm32-h103/pwm_6step/pwm_6step.c b/examples/stm32f1/stm32-h103/pwm_6step/pwm_6step.c index bda8ff7..9f9390a 100644 --- a/examples/stm32f1/stm32-h103/pwm_6step/pwm_6step.c +++ b/examples/stm32f1/stm32-h103/pwm_6step/pwm_6step.c @@ -17,10 +17,10 @@ * along with this program. If not, see . */ -#include -#include -#include +#include +#include #include +#include #include #define FALLING 0 diff --git a/examples/stm32f1/stm32-h103/pwm_6step/pwm_6step.ld b/examples/stm32f1/stm32-h103/pwm_6step/pwm_6step.ld index 7ea2b92..3409b98 100644 --- a/examples/stm32f1/stm32-h103/pwm_6step/pwm_6step.ld +++ b/examples/stm32f1/stm32-h103/pwm_6step/pwm_6step.ld @@ -27,5 +27,5 @@ MEMORY } /* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld +INCLUDE libopencm3_stm32f1.ld diff --git a/examples/stm32f1/stm32-h103/spi/spi.c b/examples/stm32f1/stm32-h103/spi/spi.c index 5a36bb8..89b8a68 100644 --- a/examples/stm32f1/stm32-h103/spi/spi.c +++ b/examples/stm32f1/stm32-h103/spi/spi.c @@ -17,7 +17,7 @@ * along with this program. If not, see . */ -#include +#include #include void clock_setup(void) diff --git a/examples/stm32f1/stm32-h103/spi/spi.ld b/examples/stm32f1/stm32-h103/spi/spi.ld index 25806f8..e2fb5b6 100644 --- a/examples/stm32f1/stm32-h103/spi/spi.ld +++ b/examples/stm32f1/stm32-h103/spi/spi.ld @@ -27,5 +27,5 @@ MEMORY } /* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld +INCLUDE libopencm3_stm32f1.ld diff --git a/examples/stm32f1/stm32-h103/timer/timer.c b/examples/stm32f1/stm32-h103/timer/timer.c index ea64c86..48cae12 100644 --- a/examples/stm32f1/stm32-h103/timer/timer.c +++ b/examples/stm32f1/stm32-h103/timer/timer.c @@ -17,10 +17,10 @@ * along with this program. If not, see . */ -#include -#include -#include +#include +#include #include +#include #include u16 frequency_sequence[18] = { diff --git a/examples/stm32f1/stm32-h103/timer/timer.ld b/examples/stm32f1/stm32-h103/timer/timer.ld index 7ea2b92..3409b98 100644 --- a/examples/stm32f1/stm32-h103/timer/timer.ld +++ b/examples/stm32f1/stm32-h103/timer/timer.ld @@ -27,5 +27,5 @@ MEMORY } /* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld +INCLUDE libopencm3_stm32f1.ld diff --git a/examples/stm32f1/stm32-h103/traceswo/traceswo.c b/examples/stm32f1/stm32-h103/traceswo/traceswo.c index ac461bb..8881447 100644 --- a/examples/stm32f1/stm32-h103/traceswo/traceswo.c +++ b/examples/stm32f1/stm32-h103/traceswo/traceswo.c @@ -17,8 +17,8 @@ * along with this program. If not, see . */ -#include -#include +#include +#include #include #include diff --git a/examples/stm32f1/stm32-h103/traceswo/traceswo.ld b/examples/stm32f1/stm32-h103/traceswo/traceswo.ld index 7ea2b92..3409b98 100644 --- a/examples/stm32f1/stm32-h103/traceswo/traceswo.ld +++ b/examples/stm32f1/stm32-h103/traceswo/traceswo.ld @@ -27,5 +27,5 @@ MEMORY } /* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld +INCLUDE libopencm3_stm32f1.ld diff --git a/examples/stm32f1/stm32-h103/usart/usart.c b/examples/stm32f1/stm32-h103/usart/usart.c index 9692d61..a221acb 100644 --- a/examples/stm32f1/stm32-h103/usart/usart.c +++ b/examples/stm32f1/stm32-h103/usart/usart.c @@ -17,8 +17,8 @@ * along with this program. If not, see . */ -#include -#include +#include +#include #include void clock_setup(void) @@ -40,7 +40,7 @@ void usart_setup(void) GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_USART1_TX); /* Setup UART parameters. */ - usart_set_baudrate(USART1, 38400); + usart_set_baudrate(USART1, 38400, rcc_ppre2_frequency); usart_set_databits(USART1, 8); usart_set_stopbits(USART1, USART_STOPBITS_1); usart_set_mode(USART1, USART_MODE_TX); @@ -55,7 +55,7 @@ void usart_setup(void) GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_USART2_TX); /* Setup UART parameters. */ - usart_set_baudrate(USART2, 38400); + usart_set_baudrate(USART2, 38400, rcc_ppre1_frequency); usart_set_databits(USART2, 8); usart_set_stopbits(USART2, USART_STOPBITS_1); usart_set_mode(USART2, USART_MODE_TX); @@ -70,7 +70,7 @@ void usart_setup(void) GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_USART3_TX); /* Setup UART parameters. */ - usart_set_baudrate(USART3, 38400); + usart_set_baudrate(USART3, 38400, rcc_ppre1_frequency); usart_set_databits(USART3, 8); usart_set_stopbits(USART3, USART_STOPBITS_1); usart_set_mode(USART3, USART_MODE_TX); diff --git a/examples/stm32f1/stm32-h103/usart/usart.ld b/examples/stm32f1/stm32-h103/usart/usart.ld index 7ea2b92..3409b98 100644 --- a/examples/stm32f1/stm32-h103/usart/usart.ld +++ b/examples/stm32f1/stm32-h103/usart/usart.ld @@ -27,5 +27,5 @@ MEMORY } /* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld +INCLUDE libopencm3_stm32f1.ld diff --git a/examples/stm32f1/stm32-h103/usart_irq/usart_irq.c b/examples/stm32f1/stm32-h103/usart_irq/usart_irq.c index 9b957dc..a2d8eef 100644 --- a/examples/stm32f1/stm32-h103/usart_irq/usart_irq.c +++ b/examples/stm32f1/stm32-h103/usart_irq/usart_irq.c @@ -17,8 +17,8 @@ * along with this program. If not, see . */ -#include -#include +#include +#include #include #include @@ -49,7 +49,7 @@ void usart_setup(void) GPIO_CNF_INPUT_FLOAT, GPIO_USART1_RX); /* Setup UART parameters. */ - usart_set_baudrate(USART1, 230400); + usart_set_baudrate(USART1, 230400, rcc_ppre2_frequency); usart_set_databits(USART1, 8); usart_set_stopbits(USART1, USART_STOPBITS_1); usart_set_parity(USART1, USART_PARITY_NONE); diff --git a/examples/stm32f1/stm32-h103/usart_irq/usart_irq.ld b/examples/stm32f1/stm32-h103/usart_irq/usart_irq.ld index 7899773..edb52c5 100644 --- a/examples/stm32f1/stm32-h103/usart_irq/usart_irq.ld +++ b/examples/stm32f1/stm32-h103/usart_irq/usart_irq.ld @@ -27,5 +27,5 @@ MEMORY } /* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld +INCLUDE libopencm3_stm32f1.ld diff --git a/examples/stm32f1/stm32-h103/usart_irq_printf/usart_irq_printf.c b/examples/stm32f1/stm32-h103/usart_irq_printf/usart_irq_printf.c index 42a7472..deee527 100644 --- a/examples/stm32f1/stm32-h103/usart_irq_printf/usart_irq_printf.c +++ b/examples/stm32f1/stm32-h103/usart_irq_printf/usart_irq_printf.c @@ -18,8 +18,8 @@ * along with this program. If not, see . */ -#include -#include +#include +#include #include #include #include @@ -145,7 +145,7 @@ void usart_setup(void) GPIO_CNF_INPUT_FLOAT, GPIO_USART1_RX); /* Setup UART parameters. */ - usart_set_baudrate(USART1, 230400); + usart_set_baudrate(USART1, 230400, rcc_ppre2_frequency); usart_set_databits(USART1, 8); usart_set_stopbits(USART1, USART_STOPBITS_1); usart_set_parity(USART1, USART_PARITY_NONE); diff --git a/examples/stm32f1/stm32-h103/usart_irq_printf/usart_irq_printf.ld b/examples/stm32f1/stm32-h103/usart_irq_printf/usart_irq_printf.ld index 7899773..edb52c5 100644 --- a/examples/stm32f1/stm32-h103/usart_irq_printf/usart_irq_printf.ld +++ b/examples/stm32f1/stm32-h103/usart_irq_printf/usart_irq_printf.ld @@ -27,5 +27,5 @@ MEMORY } /* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld +INCLUDE libopencm3_stm32f1.ld diff --git a/examples/stm32f1/stm32-h103/usart_printf/usart_printf.c b/examples/stm32f1/stm32-h103/usart_printf/usart_printf.c index 26fcee6..1eb067f 100644 --- a/examples/stm32f1/stm32-h103/usart_printf/usart_printf.c +++ b/examples/stm32f1/stm32-h103/usart_printf/usart_printf.c @@ -18,8 +18,8 @@ * along with this program. If not, see . */ -#include -#include +#include +#include #include #include @@ -46,7 +46,7 @@ void usart_setup(void) GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_USART1_TX); /* Setup UART parameters. */ - usart_set_baudrate(USART1, 230400); + usart_set_baudrate(USART1, 230400, rcc_ppre2_frequency); usart_set_databits(USART1, 8); usart_set_stopbits(USART1, USART_STOPBITS_1); usart_set_parity(USART1, USART_PARITY_NONE); diff --git a/examples/stm32f1/stm32-h103/usart_printf/usart_printf.ld b/examples/stm32f1/stm32-h103/usart_printf/usart_printf.ld index 7899773..edb52c5 100644 --- a/examples/stm32f1/stm32-h103/usart_printf/usart_printf.ld +++ b/examples/stm32f1/stm32-h103/usart_printf/usart_printf.ld @@ -27,5 +27,5 @@ MEMORY } /* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld +INCLUDE libopencm3_stm32f1.ld diff --git a/examples/stm32f1/stm32-h103/usb_cdcacm/cdcacm.c b/examples/stm32f1/stm32-h103/usb_cdcacm/cdcacm.c index 4b90640..f9e2527 100644 --- a/examples/stm32f1/stm32-h103/usb_cdcacm/cdcacm.c +++ b/examples/stm32f1/stm32-h103/usb_cdcacm/cdcacm.c @@ -18,8 +18,8 @@ */ #include -#include -#include +#include +#include #include #include diff --git a/examples/stm32f1/stm32-h103/usb_cdcacm/cdcacm.ld b/examples/stm32f1/stm32-h103/usb_cdcacm/cdcacm.ld index 928c898..d0df9e6 100644 --- a/examples/stm32f1/stm32-h103/usb_cdcacm/cdcacm.ld +++ b/examples/stm32f1/stm32-h103/usb_cdcacm/cdcacm.ld @@ -27,5 +27,5 @@ MEMORY } /* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld +INCLUDE libopencm3_stm32f1.ld diff --git a/examples/stm32f1/stm32-h103/usb_dfu/usbdfu.c b/examples/stm32f1/stm32-h103/usb_dfu/usbdfu.c index 7ffbc74..9d184f1 100644 --- a/examples/stm32f1/stm32-h103/usb_dfu/usbdfu.c +++ b/examples/stm32f1/stm32-h103/usb_dfu/usbdfu.c @@ -18,10 +18,10 @@ */ #include -#include -#include -#include -#include +#include +#include +#include +#include #include #include diff --git a/examples/stm32f1/stm32-h103/usb_dfu/usbdfu.ld b/examples/stm32f1/stm32-h103/usb_dfu/usbdfu.ld index 54e5dac..6a01797 100644 --- a/examples/stm32f1/stm32-h103/usb_dfu/usbdfu.ld +++ b/examples/stm32f1/stm32-h103/usb_dfu/usbdfu.ld @@ -25,5 +25,5 @@ MEMORY } /* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld +INCLUDE libopencm3_stm32f1.ld diff --git a/examples/stm32f1/stm32-h103/usb_hid/usbhid.c b/examples/stm32f1/stm32-h103/usb_hid/usbhid.c index a21fce6..a815573 100644 --- a/examples/stm32f1/stm32-h103/usb_hid/usbhid.c +++ b/examples/stm32f1/stm32-h103/usb_hid/usbhid.c @@ -18,8 +18,8 @@ */ #include -#include -#include +#include +#include #include #include #include @@ -28,7 +28,7 @@ #define INCLUDE_DFU_INTERFACE #ifdef INCLUDE_DFU_INTERFACE -#include +#include #include #endif diff --git a/examples/stm32f1/stm32-h103/usb_hid/usbhid.ld b/examples/stm32f1/stm32-h103/usb_hid/usbhid.ld index 928c898..d0df9e6 100644 --- a/examples/stm32f1/stm32-h103/usb_hid/usbhid.ld +++ b/examples/stm32f1/stm32-h103/usb_hid/usbhid.ld @@ -27,5 +27,5 @@ MEMORY } /* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld +INCLUDE libopencm3_stm32f1.ld diff --git a/examples/stm32f1/stm32-h103/usb_iap/usbiap.c b/examples/stm32f1/stm32-h103/usb_iap/usbiap.c index 7ffbc74..9d184f1 100644 --- a/examples/stm32f1/stm32-h103/usb_iap/usbiap.c +++ b/examples/stm32f1/stm32-h103/usb_iap/usbiap.c @@ -18,10 +18,10 @@ */ #include -#include -#include -#include -#include +#include +#include +#include +#include #include #include diff --git a/examples/stm32f1/stm32-h103/usb_iap/usbiap.ld b/examples/stm32f1/stm32-h103/usb_iap/usbiap.ld index 928c898..d0df9e6 100644 --- a/examples/stm32f1/stm32-h103/usb_iap/usbiap.ld +++ b/examples/stm32f1/stm32-h103/usb_iap/usbiap.ld @@ -27,5 +27,5 @@ MEMORY } /* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld +INCLUDE libopencm3_stm32f1.ld diff --git a/examples/stm32f1/stm32-h107/fancyblink/fancyblink.c b/examples/stm32f1/stm32-h107/fancyblink/fancyblink.c index c73d3d4..4d45829 100644 --- a/examples/stm32f1/stm32-h107/fancyblink/fancyblink.c +++ b/examples/stm32f1/stm32-h107/fancyblink/fancyblink.c @@ -18,8 +18,8 @@ * along with this program. If not, see . */ -#include -#include +#include +#include /* Set STM32 to 72 MHz. */ void clock_setup(void) diff --git a/examples/stm32f1/stm32-h107/fancyblink/fancyblink.ld b/examples/stm32f1/stm32-h107/fancyblink/fancyblink.ld index 6c9c766..d35c141 100644 --- a/examples/stm32f1/stm32-h107/fancyblink/fancyblink.ld +++ b/examples/stm32f1/stm32-h107/fancyblink/fancyblink.ld @@ -27,5 +27,5 @@ MEMORY } /* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld +INCLUDE libopencm3_stm32f1.ld diff --git a/examples/stm32f1/stm32-h107/usb_simple/usb_simple.c b/examples/stm32f1/stm32-h107/usb_simple/usb_simple.c index 85f67df..c30803c 100644 --- a/examples/stm32f1/stm32-h107/usb_simple/usb_simple.c +++ b/examples/stm32f1/stm32-h107/usb_simple/usb_simple.c @@ -17,8 +17,8 @@ * along with this program. If not, see . */ -#include -#include +#include +#include #include diff --git a/examples/stm32f1/stm32-h107/usb_simple/usb_simple.ld b/examples/stm32f1/stm32-h107/usb_simple/usb_simple.ld index 6c9c766..d35c141 100644 --- a/examples/stm32f1/stm32-h107/usb_simple/usb_simple.ld +++ b/examples/stm32f1/stm32-h107/usb_simple/usb_simple.ld @@ -27,5 +27,5 @@ MEMORY } /* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld +INCLUDE libopencm3_stm32f1.ld diff --git a/examples/stm32f2/jobygps/usart_printf/usart_printf.ld b/examples/stm32f2/jobygps/usart_printf/usart_printf.ld index 7899773..e80bdbd 100644 --- a/examples/stm32f2/jobygps/usart_printf/usart_printf.ld +++ b/examples/stm32f2/jobygps/usart_printf/usart_printf.ld @@ -27,5 +27,5 @@ MEMORY } /* Include the common ld script. */ -INCLUDE libopencm3_stm32.ld +INCLUDE libopencm3_stm32f2.ld -- cgit v1.2.3