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-rw-r--r--lib/Makefile.include2
-rw-r--r--lib/lm3s/libopencm3_lm3s.ld2
-rw-r--r--lib/stm32/crc.c46
-rw-r--r--lib/stm32/f1/Makefile2
-rw-r--r--lib/stm32/f1/adc.c233
-rw-r--r--lib/stm32/f1/pwr.c10
-rw-r--r--lib/stm32/f1/timer.c39
-rw-r--r--lib/stm32/f4/Makefile3
-rw-r--r--lib/stm32/f4/vector.c31
-rw-r--r--lib/stm32/i2c.c165
-rw-r--r--lib/stm32/spi.c408
-rw-r--r--lib/stm32/usart.c273
12 files changed, 1166 insertions, 48 deletions
diff --git a/lib/Makefile.include b/lib/Makefile.include
index f2f1f7b..9fbea24 100644
--- a/lib/Makefile.include
+++ b/lib/Makefile.include
@@ -40,7 +40,7 @@ $(SRCLIBDIR)/$(LIBNAME).ld: $(LIBNAME).ld
clean:
@printf " CLEAN lib/stm32/f1\n"
- $(Q)rm -f *.o *.d
+ $(Q)rm -f *.o *.d ../*.o ../*.d
$(Q)rm -f $(SRCLIBDIR)/$(LIBNAME).a
$(Q)rm -f $(SRCLIBDIR)/$(LIBNAME).ld
$(Q)rm -f $(SRCLIBDIR)/$(LIBNAME)_rom_to_ram.ld
diff --git a/lib/lm3s/libopencm3_lm3s.ld b/lib/lm3s/libopencm3_lm3s.ld
index ceb391a..4aaf4d9 100644
--- a/lib/lm3s/libopencm3_lm3s.ld
+++ b/lib/lm3s/libopencm3_lm3s.ld
@@ -77,6 +77,8 @@ SECTIONS
. = ALIGN(4);
end = .;
+ _end = .;
+ __end = .;
}
PROVIDE(_stack = ORIGIN(ram) + LENGTH(ram));
diff --git a/lib/stm32/crc.c b/lib/stm32/crc.c
index bbbe1fd..bd9e8d2 100644
--- a/lib/stm32/crc.c
+++ b/lib/stm32/crc.c
@@ -1,3 +1,17 @@
+/** @defgroup crc_file CRC
+
+@ingroup STM32F_files
+
+@brief <b>libopencm3 STM32Fxxx CRC</b>
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2012 Karl Palsson <karlp@remake.is>
+
+@date 15 October 2012
+
+LGPL License Terms @ref lgpl_license
+ */
/*
* This file is part of the libopencm3 project.
*
@@ -19,11 +33,30 @@
#include <libopencm3/stm32/crc.h>
+/**@{*/
+
+/*-----------------------------------------------------------------------------*/
+/** @brief CRC Reset.
+
+Reset the CRC unit and forces the data register to all 1s.
+
+*/
+
void crc_reset(void)
{
CRC_CR |= CRC_CR_RESET;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief CRC Calculate.
+
+Writes a data word to the register, the write operation stalling until the
+computation is complete.
+
+@param[in] data Unsigned int32.
+@returns int32 Computed CRC result
+*/
+
u32 crc_calculate(u32 data)
{
CRC_DR = data;
@@ -31,6 +64,16 @@ u32 crc_calculate(u32 data)
return CRC_DR;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief CRC Calculate of a Block of Data.
+
+Writes data words consecutively to the register, the write operation stalling
+until the computation of each word is complete.
+
+@param[in] datap Unsigned int32. pointer to an array of 32 bit data words.
+@returns int32 Final computed CRC result
+*/
+
u32 crc_calculate_block(u32 *datap, int size)
{
int i;
@@ -39,6 +82,5 @@ u32 crc_calculate_block(u32 *datap, int size)
}
return CRC_DR;
}
-
-
+/**@}*/
diff --git a/lib/stm32/f1/Makefile b/lib/stm32/f1/Makefile
index 4fdbf43..a2f7bf2 100644
--- a/lib/stm32/f1/Makefile
+++ b/lib/stm32/f1/Makefile
@@ -31,7 +31,7 @@ ARFLAGS = rcs
OBJS = vector.o rcc.o gpio.o usart.o adc.o spi.o flash.o nvic.o \
rtc.o i2c.o dma.o systick.o exti.o scb.o ethernet.o \
usb_f103.o usb.o usb_control.o usb_standard.o can.o \
- timer.o usb_f107.o desig.o crc.o assert.o
+ timer.o usb_f107.o desig.o crc.o assert.o dac.o iwdg.o pwr.o
VPATH += ../../usb:../:../../cm3
diff --git a/lib/stm32/f1/adc.c b/lib/stm32/f1/adc.c
index 433cdd2..0a05aac 100644
--- a/lib/stm32/f1/adc.c
+++ b/lib/stm32/f1/adc.c
@@ -44,12 +44,12 @@ conversion, which occurs after all channels have been scanned.
@section adc_api_ex Basic ADC Handling API.
Example 1: Simple single channel conversion polled. Enable the peripheral clock
-and ADC, reset ADC and set the prescaler divider. Set dual mode to independent.
+and ADC, reset ADC and set the prescaler divider. Set dual mode to independent
+(default). Enable triggering for a software trigger.
@code
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_ADC1EN);
- adc_power_on(ADC1);
- adc_calibration(ADC1);
+ adc_off(ADC1);
rcc_peripheral_reset(&RCC_APB2RSTR, RCC_APB2RSTR_ADC1RST);
rcc_peripheral_clear_reset(&RCC_APB2RSTR, RCC_APB2RSTR_ADC1RST);
rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV2);
@@ -58,6 +58,10 @@ and ADC, reset ADC and set the prescaler divider. Set dual mode to independent.
adc_set_single_conversion_mode(ADC1);
adc_set_sample_time(ADC1, ADC_CHANNEL0, ADC_SMPR1_SMP_1DOT5CYC);
adc_set_single_channel(ADC1, ADC_CHANNEL0);
+ adc_enable_trigger(ADC1, ADC_CR2_EXTSEL_SWSTART);
+ adc_power_on(ADC1);
+ adc_reset_calibration(ADC1);
+ adc_calibration(ADC1);
adc_start_conversion_regular(ADC1);
while (! adc_eoc(ADC1));
reg16 = adc_read_regular(ADC1);
@@ -102,38 +106,181 @@ LGPL License Terms @ref lgpl_license
#include <libopencm3/stm32/f1/adc.h>
-void rcc_set_adc_clk(u32 prescaler)
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Power On
+
+If the ADC is in power-down mode then it is powered up. The application needs
+to wait a time of about 3 microseconds for stabilization before using the ADC.
+If the ADC is already on this function call has no effect.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_power_on(u32 adc)
{
- /* TODO */
+ if (!(ADC_CR2(adc) & ADC_CR2_ADON))
+ ADC_CR2(adc) |= ADC_CR2_ADON;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Start a Conversion Without Trigger
+
+This initiates a conversion by software without a trigger. The ADC needs to be
+powered on before this is called, otherwise this function has no effect.
+
+Note that this is not available in other STM32F families. To ensure code compatibility,
+enable triggering and use a software trigger source @see adc_start_conversion_regular.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
- /* FIXME: QUICK HACK to prevent compiler warnings. */
- prescaler = prescaler;
+void adc_start_conversion_direct(u32 adc)
+{
+ if (ADC_CR2(adc) & ADC_CR2_ADON)
+ ADC_CR2(adc) |= ADC_CR2_ADON;
}
-void adc_set_mode(u32 block, /* TODO */ u8 mode)
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Set Dual A/D Mode
+
+The dual mode uses ADC1 as master and ADC2 in a slave arrangement. This setting
+is applied to ADC1 only. Start of conversion when triggered can cause simultaneous
+conversion with ADC2, or alternate conversion. Regular and injected conversions
+can be configured, each one being separately simultaneous or alternate.
+
+Fast interleaved mode starts ADC1 immediately on trigger, and ADC2 seven clock
+cycles later.
+
+Slow interleaved mode starts ADC1 immediately on trigger, and ADC2 fourteen clock
+cycles later, followed by ADC1 fourteen cycles later again. This can only be used
+on a single channel.
+
+Alternate trigger mode must occur on an injected channel group, and alternates
+between the ADCs on each trigger.
+
+Note that sampling must not overlap between ADCs on the same channel.
+
+Dual A/D converter modes possible:
+
+@li IND: Independent mode.
+@li CRSISM: Combined regular simultaneous + injected simultaneous mode.
+@li CRSATM: Combined regular simultaneous + alternate trigger mode.
+@li CISFIM: Combined injected simultaneous + fast interleaved mode.
+@li CISSIM: Combined injected simultaneous + slow interleaved mode.
+@li ISM: Injected simultaneous mode only.
+@li RSM: Regular simultaneous mode only.
+@li FIM: Fast interleaved mode only.
+@li SIM: Slow interleaved mode only.
+@li ATM: Alternate trigger mode only.
+
+@param[in] mode Unsigned int32. Dual mode selection from @ref adc_cr1_dualmod
+*/
+
+void adc_set_dual_mode(u32 mode)
{
- /* TODO */
+ ADC1_CR1 |= mode;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Read the End-of-Conversion Flag
+
+This flag is set after all channels of a regular or injected group have been
+converted.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@returns bool. End of conversion flag.
+*/
- /* FIXME: QUICK HACK to prevent compiler warnings. */
- block = block;
- mode = mode;
+bool adc_eoc(u32 adc)
+{
+ return ((ADC_SR(adc) & ADC_SR_EOC) != 0);
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Read the End-of-Conversion Flag for Injected Conversion
+
+This flag is set after all channels of an injected group have been converted.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@returns bool. End of conversion flag.
+*/
+
+bool adc_eoc_injected(u32 adc)
+{
+ return ((ADC_SR(adc) & ADC_SR_JEOC) != 0);
}
/*-----------------------------------------------------------------------------*/
-/** @brief ADC Read from a Conversion Result Register
+/** @brief ADC Read from the Regular Conversion Result Register
+
+The result read back is 12 bits, right or left aligned within the first 16 bits.
+For ADC1 only, the higher 16 bits will hold the result from ADC2 if
+an appropriate dual mode has been set @see adc_set_dual_mode.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@returns Unsigned int32 conversion result.
+*/
+
+u32 adc_read_regular(u32 adc)
+{
+ return ADC_DR(adc);
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Read from an Injected Conversion Result Register
+
+The result read back from the selected injected result register (one of four) is
+12 bits, right or left aligned within the first 16 bits. The result can have a
+negative value if the injected channel offset has been set @see adc_set_injected_offset.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@param[in] reg Unsigned int8. Register number (1 ... 4).
@returns Unsigned int32 conversion result.
*/
-void adc_read(u32 block, u32 channel)
+u32 adc_read_injected(u32 adc, u8 reg)
{
- /* TODO */
+ switch (reg) {
+ case 1:
+ return ADC_JDR1(adc);
+ case 2:
+ return ADC_JDR2(adc);
+ case 3:
+ return ADC_JDR3(adc);
+ case 4:
+ return ADC_JDR4(adc);
+ }
+ return 0;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Set the Injected Channel Data Offset
+
+This value is subtracted from the injected channel results after conversion
+is complete, and can result in negative results. A separate value can be specified
+for each injected data register.
- /* FIXME: QUICK HACK to prevent compiler warnings. */
- block = block;
- channel = channel;
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] reg Unsigned int8. Register number (1 ... 4).
+@param[in] offset Unsigned int32.
+*/
+
+void adc_set_injected_offset(u32 adc, u8 reg, u32 offset)
+{
+ switch (reg) {
+ case 1:
+ ADC_JOFR1(adc) = offset;
+ break;
+ case 2:
+ ADC_JOFR2(adc) = offset;
+ break;
+ case 3:
+ ADC_JOFR3(adc) = offset;
+ break;
+ case 4:
+ ADC_JOFR4(adc) = offset;
+ break;
+ }
}
/*-----------------------------------------------------------------------------*/
@@ -203,9 +350,11 @@ of the subgroup at the beginning of the whole group.
@param[in] length Unsigned int8. Number of channels in the group @ref adc_cr1_discnum
*/
-void adc_enable_discontinous_mode_regular(u32 adc)
+void adc_enable_discontinuous_mode_regular(u32 adc, u8 length)
{
- ADC_CR1(adc) |= ADC_CR1_DISCEN;
+ if ( (length-1) > 7 ) return;
+ ADC_CR1(adc) |= ADC_CR1_DISCEN;
+ ADC_CR2(adc) |= ((length-1) << ADC_CR1_DISCNUM_SHIFT);
}
/*-----------------------------------------------------------------------------*/
@@ -214,7 +363,7 @@ void adc_enable_discontinous_mode_regular(u32 adc)
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
-void adc_disable_discontinous_mode_regular(u32 adc)
+void adc_disable_discontinuous_mode_regular(u32 adc)
{
ADC_CR1(adc) &= ~ADC_CR1_DISCEN;
}
@@ -229,7 +378,7 @@ entire group has been converted.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
-void adc_enable_discontinous_mode_injected(u32 adc)
+void adc_enable_discontinuous_mode_injected(u32 adc)
{
ADC_CR1(adc) |= ADC_CR1_JDISCEN;
}
@@ -240,7 +389,7 @@ void adc_enable_discontinous_mode_injected(u32 adc)
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
-void adc_disable_discontinous_mode_injected(u32 adc)
+void adc_disable_discontinuous_mode_injected(u32 adc)
{
ADC_CR1(adc) &= ~ADC_CR1_JDISCEN;
}
@@ -257,6 +406,7 @@ channels is disabled as required.
void adc_enable_automatic_injected_group_conversion(u32 adc)
{
+ adc_disable_external_trigger_injected(adc);
ADC_CR1(adc) |= ADC_CR1_JAUTO;
}
@@ -288,7 +438,7 @@ disabled.
void adc_enable_analog_watchdog_on_all_channels(u32 adc)
{
- ADC_CR1(adc) |= ADC_CR1_AWDSGL;
+ ADC_CR1(adc) &= ~ADC_CR1_AWDSGL;
}
/*-----------------------------------------------------------------------------*/
@@ -315,7 +465,7 @@ void adc_enable_analog_watchdog_on_selected_channel(u32 adc, u8 channel)
if (channel < 18)
reg32 |= channel;
ADC_CR1(adc) = reg32;
- ADC_CR1(adc) &= ~ADC_CR1_AWDSGL;
+ ADC_CR1(adc) |= ADC_CR1_AWDSGL;
}
/*-----------------------------------------------------------------------------*/
@@ -350,7 +500,7 @@ void adc_disable_scan_mode(u32 adc)
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
-void adc_enable_jeoc_interrupt(u32 adc)
+void adc_enable_eoc_interrupt_injected(u32 adc)
{
ADC_CR1(adc) |= ADC_CR1_JEOCIE;
}
@@ -361,7 +511,7 @@ void adc_enable_jeoc_interrupt(u32 adc)
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
-void adc_disable_jeoc_interrupt(u32 adc)
+void adc_disable_eoc_interrupt_injected(u32 adc)
{
ADC_CR1(adc) &= ~ADC_CR1_JEOCIE;
}
@@ -519,8 +669,7 @@ void adc_enable_external_trigger_regular(u32 adc, u32 trigger)
u32 reg32;
reg32 = (ADC_CR2(adc) & ~(ADC_CR2_EXTSEL_MASK));
- if (trigger < 8)
- reg32 |= (trigger);
+ reg32 |= (trigger);
ADC_CR2(adc) = reg32;
ADC_CR2(adc) |= ADC_CR2_EXTTRIG;
}
@@ -565,14 +714,12 @@ For ADC3
@param[in] trigger Unsigned int8. Trigger identifier @ref adc_trigger_injected_12
for ADC1 and ADC2, or @ref adc_trigger_injected_3 for ADC3
*/
-
void adc_enable_external_trigger_injected(u32 adc, u32 trigger)
{
u32 reg32;
reg32 = (ADC_CR2(adc) & ~(ADC_CR2_JEXTSEL_MASK)); /* Clear bits [12:14]. */
- if (trigger < 8)
- reg32 |= (trigger);
+ reg32 |= (trigger);
ADC_CR2(adc) = reg32;
ADC_CR2(adc) |= ADC_CR2_JEXTTRIG;
}
@@ -681,7 +828,7 @@ group immediately following completion of the previous channel group conversion.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
-void adc_set_continous_conversion_mode(u32 adc)
+void adc_set_continuous_conversion_mode(u32 adc)
{
ADC_CR2(adc) |= ADC_CR2_CONT;
}
@@ -707,7 +854,7 @@ If the ADC is in power-down mode then it is powered up. The application needs
to wait a time of about 3 microseconds for stabilization before using the ADC.
If the ADC is already on this function call will initiate a conversion.
-@todo fix this.
+@deprecated to be removed in a later release
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
@@ -740,7 +887,7 @@ The sampling time can be selected in ADC clock cycles from 1.5 to 239.5.
@param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg
*/
-void adc_set_conversion_time(u32 adc, u8 channel, u8 time)
+void adc_set_sample_time(u32 adc, u8 channel, u8 time)
{
u32 reg32;
@@ -767,7 +914,7 @@ all channels.
@param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg
*/
-void adc_set_conversion_time_on_all_channels(u32 adc, u8 time)
+void adc_set_sample_time_on_all_channels(u32 adc, u8 time)
{
u8 i;
u32 reg32 = 0;
@@ -871,12 +1018,24 @@ void adc_set_injected_sequence(u32 adc, u8 length, u8 channel[])
return;
for (i = 1; i <= length; i++)
- reg32 |= (channel[i - 1] << ((i - 1) * 5));
+ reg32 |= (channel[4 - i] << ((4 - i) * 5));
reg32 |= ((length - 1) << ADC_JSQR_JL_LSB);
ADC_JSQR(adc) = reg32;
}
+/*-----------------------------------------------------------------------------*/
+
+/* Aliases */
+
+#ifdef __GNUC__
+void adc_set_continous_conversion_mode(u32 adc) __attribute__ ((alias("adc_set_continuous_conversion_mode")));
+void adc_set_conversion_time(u32 adc, u8 channel, u8 time) __attribute__ ((alias ("adc_set_sample_time")));
+void adc_set_conversion_time_on_all_channels(u32 adc, u8 time) __attribute__ ((alias ("adc_set_sample_time_on_all_channels")));
+void adc_enable_jeoc_interrupt(u32 adc) __attribute__ ((alias ("adc_enable_eoc_interrupt_injected")));
+void adc_disable_jeoc_interrupt(u32 adc) __attribute__ ((alias ("adc_disable_eoc_interrupt_injected")));
+#endif
+
/**@}*/
diff --git a/lib/stm32/f1/pwr.c b/lib/stm32/f1/pwr.c
index 83c3dba..451ed1c 100644
--- a/lib/stm32/f1/pwr.c
+++ b/lib/stm32/f1/pwr.c
@@ -157,7 +157,7 @@ The wakeup pin is used for waking the processor from standby mode.
void pwr_enable_wakeup_pin(void)
{
- PWR_CSR |= PWR_CR_EWUP;
+ PWR_CSR |= PWR_CSR_EWUP;
}
/*---------------------------------------------------------------------------*/
@@ -168,7 +168,7 @@ The wakeup pin is used for general purpose I/O.
void pwr_disable_wakeup_pin(void)
{
- PWR_CSR &= ~PWR_CR_EWUP;
+ PWR_CSR &= ~PWR_CSR_EWUP;
}
/*---------------------------------------------------------------------------*/
@@ -183,7 +183,7 @@ threshold.
bool pwr_voltage_high(void)
{
- return (PWR_CSR & PWR_CR_PVDO);
+ return (PWR_CSR & PWR_CSR_PVDO);
}
/*---------------------------------------------------------------------------*/
@@ -197,7 +197,7 @@ cleared by software (see @ref pwr_clear_standby_flag).
bool pwr_get_standby_flag(void)
{
- return (PWR_CSR & PWR_CR_SBF);
+ return (PWR_CSR & PWR_CSR_SBF);
}
/*---------------------------------------------------------------------------*/
@@ -211,7 +211,7 @@ cleared by software (see @ref pwr_clear_wakeup_flag).
bool pwr_get_wakeup_flag(void)
{
- return (PWR_CSR & PWR_CR_WUF);
+ return (PWR_CSR & PWR_CSR_WUF);
}
/**@}*/
diff --git a/lib/stm32/f1/timer.c b/lib/stm32/f1/timer.c
index c5ea921..384eaaf 100644
--- a/lib/stm32/f1/timer.c
+++ b/lib/stm32/f1/timer.c
@@ -199,6 +199,31 @@ void timer_disable_irq(u32 timer_peripheral, u32 irq)
}
/*---------------------------------------------------------------------------*/
+/** @brief Return Interrupt Source.
+
+Returns true if the specified interrupt flag (UIF, TIF or CCxIF, with BIF or COMIF
+for advanced timers) was set and the interrupt was enabled. If the specified flag
+is not an interrupt flag, the function returns false.
+
+@todo Timers 6-7, 9-14 have fewer interrupts, but invalid flags are not caught here.
+
+@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base
+@param[in] flag Unsigned int32. Status register flag @ref tim_sr_values.
+@returns boolean: flag set.
+*/
+
+bool timer_interrupt_source(u32 timer_peripheral, u32 flag)
+{
+/* flag not set or interrupt disabled or not an interrupt source */
+ if (((TIM_SR(timer_peripheral) & TIM_DIER(timer_peripheral) & flag) == 0) ||
+ (flag > TIM_SR_BIF)) return false;
+/* Only an interrupt source for advanced timers */
+ if ((flag == TIM_SR_BIF) || (flag == TIM_SR_COMIF))
+ return ((timer_peripheral == TIM1) || (timer_peripheral == TIM8));
+ return true;
+}
+
+/*---------------------------------------------------------------------------*/
/** @brief Read a Status Flag.
@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base
@@ -1672,6 +1697,20 @@ u32 timer_get_counter(u32 timer_peripheral)
}
/*---------------------------------------------------------------------------*/
+/** @brief Set Counter
+
+Set the value of a timer's counter register contents.
+
+@param[in] timer_peripheral Unsigned int32. Timer register address base
+@param[in] Unsigned int32. Counter value.
+*/
+
+void timer_set_counter(u32 timer_peripheral, u32 count)
+{
+ TIM_CNT(timer_peripheral) = count;
+}
+
+/*---------------------------------------------------------------------------*/
/** @brief Set Input Capture Filter Parameters
Set the input filter parameters for an input channel, specifying:
diff --git a/lib/stm32/f4/Makefile b/lib/stm32/f4/Makefile
index 85870a7..fd0b279 100644
--- a/lib/stm32/f4/Makefile
+++ b/lib/stm32/f4/Makefile
@@ -24,7 +24,8 @@ PREFIX ?= arm-none-eabi
CC = $(PREFIX)-gcc
AR = $(PREFIX)-ar
CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \
- -mcpu=cortex-m3 -mthumb -Wstrict-prototypes \
+ -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 \
+ -Wstrict-prototypes \
-ffunction-sections -fdata-sections -MD -DSTM32F4
# ARFLAGS = rcsv
ARFLAGS = rcs
diff --git a/lib/stm32/f4/vector.c b/lib/stm32/f4/vector.c
index 8d158a6..a5017b3 100644
--- a/lib/stm32/f4/vector.c
+++ b/lib/stm32/f4/vector.c
@@ -1,2 +1,33 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
+ * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
#include <libopencm3/stm32/f4/irq.h>
+#define reset_handler original_reset_handler
#include "../../cm3/vector.c"
+#undef reset_handler
+#include <libopencm3/stm32/f4/scb.h>
+
+void WEAK reset_handler(void)
+{
+ /* Enable access to Floating-Point coprocessor. */
+ SCB_CPACR |= SCB_CPACR_FULL * (SCB_CPACR_CP10 | SCB_CPACR_CP11);
+
+ original_reset_handler();
+}
diff --git a/lib/stm32/i2c.c b/lib/stm32/i2c.c
index 87d9061..e1d3a09 100644
--- a/lib/stm32/i2c.c
+++ b/lib/stm32/i2c.c
@@ -1,3 +1,28 @@
+/** @defgroup i2c_file I2C
+
+@ingroup STM32F_files
+
+@brief <b>libopencm3 STM32Fxxx I2C</b>
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 15 October 2012
+
+Devices can have up to two I2C peripherals. The peripherals support SMBus and
+PMBus variants.
+
+A peripheral begins after reset in Slave mode. To become a Master a start
+condition must be generated. The peripheral will remain in Master mode unless
+a multimaster contention is lost or a stop condition is generated.
+
+@todo all sorts of lovely stuff like DMA, Interrupts, SMBus variant, Status
+register access, Error conditions
+
+LGPL License Terms @ref lgpl_license
+ */
/*
* This file is part of the libopencm3 project.
*
@@ -20,6 +45,17 @@
#include <libopencm3/stm32/i2c.h>
#include <libopencm3/stm32/f4/rcc.h>
+/**@{*/
+
+/*-----------------------------------------------------------------------------*/
+/** @brief I2C Reset.
+
+The I2C peripheral and all its associated configuration registers are placed in the
+reset condition. The reset is effected via the RCC peripheral reset system.
+
+@param[in] i2c Unsigned int32. I2C peripheral identifier @ref i2c_reg_base.
+*/
+
void i2c_reset(u32 i2c)
{
switch (i2c) {
@@ -34,26 +70,69 @@ void i2c_reset(u32 i2c)
}
}
+/*-----------------------------------------------------------------------------*/
+/** @brief I2C Peripheral Enable.
+
+@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
+*/
+
void i2c_peripheral_enable(u32 i2c)
{
I2C_CR1(i2c) |= I2C_CR1_PE;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief I2C Peripheral Disable.
+
+This must not be reset while in Master mode until a communication has finished.
+In Slave mode, the peripheral is disabled only after communication has ended.
+
+@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
+*/
+
void i2c_peripheral_disable(u32 i2c)
{
I2C_CR1(i2c) &= ~I2C_CR1_PE;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief I2C Send Start Condition.
+
+If in Master mode this will cause a restart condition to occur at the end of the
+current transmission. If in Slave mode, this will initiate a start condition
+when the current bus activity is completed.
+
+@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
+*/
+
void i2c_send_start(u32 i2c)
{
I2C_CR1(i2c) |= I2C_CR1_START;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief I2C Send Stop Condition.
+
+After the current byte transfer this will initiate a stop condition if in Master
+mode, or simply release the bus if in Slave mode.
+
+@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
+*/
+
void i2c_send_stop(u32 i2c)
{
I2C_CR1(i2c) |= I2C_CR1_STOP;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief I2C Set the 7 bit Slave Address for the Peripheral.
+
+This sets an address for Slave mode operation, in 7 bit form.
+
+@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
+@param[in] slave Unsigned int8. Slave address 0...127.
+*/
+
void i2c_set_own_7bit_slave_address(u32 i2c, u8 slave)
{
I2C_OAR1(i2c) = (u16)(slave << 1);
@@ -61,21 +140,61 @@ void i2c_set_own_7bit_slave_address(u32 i2c, u8 slave)
I2C_OAR1(i2c) |= (1 << 14); /* Datasheet: always keep 1 by software. */
}
+/*-----------------------------------------------------------------------------*/
+/** @brief I2C Set the 10 bit Slave Address for the Peripheral.
+
+This sets an address for Slave mode operation, in 10 bit form.
+
+@todo add "I2C_OAR1(i2c) |= (1 << 14);" as above
+
+@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
+@param[in] slave Unsigned int16. Slave address 0...1023.
+*/
+
void i2c_set_own_10bit_slave_address(u32 i2c, u16 slave)
{
I2C_OAR1(i2c) = (u16)(I2C_OAR1_ADDMODE | slave);
}
+/*-----------------------------------------------------------------------------*/
+/** @brief I2C Set Fast Mode.
+
+Set the clock frequency to the high clock rate mode (up to 400kHz). The actual
+clock frequency must be set with @ref i2c_set_clock_frequency
+
+@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
+*/
+
void i2c_set_fast_mode(u32 i2c)
{
I2C_CCR(i2c) |= I2C_CCR_FS;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief I2C Set Standard Mode.
+
+Set the clock frequency to the standard clock rate mode (up to 100kHz). The actual
+clock frequency must be set with @ref i2c_set_clock_frequency
+
+@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
+*/
+
void i2c_set_standard_mode(u32 i2c)
{
I2C_CCR(i2c) &= ~I2C_CCR_FS;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief I2C Set Peripheral Clock Frequency.
+
+Set the peripheral clock frequency: 2MHz to 36MHz (the APB frequency). Note that
+this is <b> not </b> the I2C bus clock. This is set in conjunction with the Clock
+Control register to generate the Master bus clock, see @ref i2c_set_ccr
+
+@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
+@param[in] freq Unsigned int8. Clock Frequency Setting @ref i2c_clock.
+*/
+
void i2c_set_clock_frequency(u32 i2c, u8 freq)
{
u16 reg16;
@@ -84,6 +203,21 @@ void i2c_set_clock_frequency(u32 i2c, u8 freq)
I2C_CR2(i2c) = reg16;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief I2C Set Bus Clock Frequency.
+
+Set the bus clock frequency. This is a 12 bit number (0...4095) calculated
+from the formulae given in the STM32F1 reference manual in the description
+of the CCR field. It is a divisor of the peripheral clock frequency
+@ref i2c_set_clock_frequency modified by the fast mode setting
+@ref i2c_set_fast_mode
+
+@todo provide additional API assitance to set the clock, eg macros
+
+@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
+@param[in] freq Unsigned int16. Bus Clock Frequency Setting 0...4095.
+*/
+
void i2c_set_ccr(u32 i2c, u16 freq)
{
u16 reg16;
@@ -92,17 +226,48 @@ void i2c_set_ccr(u32 i2c, u16 freq)
I2C_CCR(i2c) = reg16;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief I2C Set the Rise Time.
+
+Set the maximum rise time on the bus according to the I2C specification, as 1
+more than the specified rise time in peripheral clock cycles. This is a 6 bit
+number.
+
+@todo provide additional APIP assistance.
+
+@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
+@param[in] trise Unsigned int16. Rise Time Setting 0...63.
+*/
+
void i2c_set_trise(u32 i2c, u16 trise)
{
I2C_TRISE(i2c) = trise;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief I2C Send the 7-bit Slave Address.
+
+@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
+@param[in] slave Unsigned int16. Slave address 0...1023.
+@param[in] readwrite Unsigned int8. Single bit to instruct slave to receive or send @ref i2c_rw.
+*/
+
void i2c_send_7bit_address(u32 i2c, u8 slave, u8 readwrite)
{
I2C_DR(i2c) = (u8)((slave << 1) | readwrite);
}
+/*-----------------------------------------------------------------------------*/
+/** @brief I2C Send Data.
+
+@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
+@param[in] data Unsigned int8. Byte to send.
+*/
+
void i2c_send_data(u32 i2c, u8 data)
{
I2C_DR(i2c) = data;
}
+
+/**@}*/
+
diff --git a/lib/stm32/spi.c b/lib/stm32/spi.c
index 828e123..90675b3 100644
--- a/lib/stm32/spi.c
+++ b/lib/stm32/spi.c
@@ -1,3 +1,43 @@
+/** @defgroup spi_file SPI
+
+@ingroup STM32F_files
+
+@brief <b>libopencm3 STM32Fxxx SPI</b>
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 15 October 2012
+
+Devices can have up to three SPI peripherals. The common 4-wire full-duplex
+mode of operation is supported, along with 3-wire variants using unidirectional
+communication modes or half-duplex bidirectional communication. A variety of
+options allows many of the SPI variants to be supported. Multimaster operation
+is also supported. A CRC can be generated and checked in hardware.
+
+@note Some JTAG pins need to be remapped if SPI is to be used.
+
+@note The I2S protocol shares the SPI hardware so the two protocols cannot be
+used at the same time on the same peripheral.
+
+Example: 1Mbps, positive clock polarity, leading edge trigger, 8-bit words,
+LSB first.
+@code
+ spi_init_master(SPI1, 1000000, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE,
+ SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT,
+ SPI_CR1_LSBFIRST);
+ spi_write(SPI1, 0x55); // 8-bit write
+ spi_write(SPI1, 0xaa88); // 16-bit write
+ reg8 = spi_read(SPI1); // 8-bit read
+ reg16 = spi_read(SPI1); // 16-bit read
+@endcode
+
+@todo need additional functions to aid ISRs in retrieving status
+
+LGPL License Terms @ref lgpl_license
+ */
/*
* This file is part of the libopencm3 project.
*
@@ -41,6 +81,17 @@
* reg16 = spi_read(SPI1); // 16-bit read
*/
+/**@{*/
+
+/*-----------------------------------------------------------------------------*/
+/** @brief SPI Reset.
+
+The SPI peripheral and all its associated configuration registers are placed in the
+reset condition. The reset is effected via the RCC peripheral reset system.
+
+@param[in] spi_peripheral Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
+*/
+
void spi_reset(u32 spi_peripheral)
{
switch (spi_peripheral) {
@@ -59,6 +110,25 @@ void spi_reset(u32 spi_peripheral)
}
}
+/*-----------------------------------------------------------------------------*/
+/** @brief Configure the SPI as Master.
+
+The SPI peripheral is configured as a master with communication parameters
+baudrate, data format 8/16 bits, frame format lsb/msb first, clock polarity
+and phase. The SPI enable, CRC enable and CRC next controls are not affected.
+These must be controlled separately.
+
+@todo NSS pin handling.
+
+@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
+@param[in] br Unsigned int32. Baudrate @ref spi_baudrate.
+@param[in] cpol Unsigned int32. Clock polarity @ref spi_cpol.
+@param[in] cpha Unsigned int32. Clock Phase @ref spi_cpha.
+@param[in] dff Unsigned int32. Data frame format 8/16 bits @ref spi_dff.
+@param[in] lsbfirst Unsigned int32. Frame format lsb/msb first @ref spi_lsbfirst.
+@returns int. Error code.
+*/
+
int spi_init_master(u32 spi, u32 br, u32 cpol, u32 cpha, u32 dff, u32 lsbfirst)
{
u32 reg32 = SPI_CR1(spi);
@@ -82,28 +152,66 @@ int spi_init_master(u32 spi, u32 br, u32 cpol, u32 cpha, u32 dff, u32 lsbfirst)
}
/* TODO: Error handling? */
+/*-----------------------------------------------------------------------------*/
+/** @brief SPI Enable.
+
+The SPI peripheral is enabled.
+
+@todo Error handling?
+
+@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
+*/
+
void spi_enable(u32 spi)
{
SPI_CR1(spi) |= SPI_CR1_SPE; /* Enable SPI. */
}
/* TODO: Error handling? */
+/*-----------------------------------------------------------------------------*/
+/** @brief SPI Disable.
+
+The SPI peripheral is disabled.
+
+@todo Follow procedure from section 23.3.8 in the TRM.
+(possibly create a "clean disable" function separately)
+
+@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
+*/
+
void spi_disable(u32 spi)
{
u32 reg32;
- /* TODO: Follow procedure from section 23.3.8 in the TRM. */
reg32 = SPI_CR1(spi);
reg32 &= ~(SPI_CR1_SPE); /* Disable SPI. */
SPI_CR1(spi) = reg32;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief SPI Data Write.
+
+Data is written to the SPI interface.
+
+@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
+@param[in] data Unsigned int16. 8 or 16 bit data to be written.
+*/
+
void spi_write(u32 spi, u16 data)
{
/* Write data (8 or 16 bits, depending on DFF) into DR. */
SPI_DR(spi) = data;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief SPI Data Write with Blocking.
+
+Data is written to the SPI interface after the previous write transfer has finished.
+
+@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
+@param[in] data Unsigned int16. 8 or 16 bit data to be written.
+*/
+
void spi_send(u32 spi, u16 data)
{
/* Wait for transfer finished. */
@@ -114,6 +222,15 @@ void spi_send(u32 spi, u16 data)
SPI_DR(spi) = data;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief SPI Data Read.
+
+Data is read from the SPI interface after the incoming transfer has finished.
+
+@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
+@returns data Unsigned int16. 8 or 16 bit data.
+*/
+
u16 spi_read(u32 spi)
{
/* Wait for transfer finished. */
@@ -124,6 +241,17 @@ u16 spi_read(u32 spi)
return SPI_DR(spi);
}
+/*-----------------------------------------------------------------------------*/
+/** @brief SPI Data Write and Read Exchange.
+
+Data is written to the SPI interface, then a read is done after the incoming transfer
+has finished.
+
+@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
+@param[in] data Unsigned int16. 8 or 16 bit data to be written.
+@returns data Unsigned int16. 8 or 16 bit data.
+*/
+
u16 spi_xfer(u32 spi, u16 data)
{
spi_write(spi, data);
@@ -136,98 +264,251 @@ u16 spi_xfer(u32 spi, u16 data)
return SPI_DR(spi);
}
+/*-----------------------------------------------------------------------------*/
+/** @brief SPI Set Bidirectional Simplex Mode.
+
+The SPI peripheral is set for bidirectional transfers in two-wire simplex mode
+(using a clock wire and a bidirectional data wire).
+
+@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
+*/
+
void spi_set_bidirectional_mode(u32 spi)
{
SPI_CR1(spi) |= SPI_CR1_BIDIMODE;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief SPI Set Unidirectional Mode.
+
+The SPI peripheral is set for unidirectional transfers. This is used in full duplex
+mode or when the SPI is placed in two-wire simplex mode that uses a clock wire and a
+unidirectional data wire.
+
+@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
+*/
+
void spi_set_unidirectional_mode(u32 spi)
{
SPI_CR1(spi) &= ~SPI_CR1_BIDIMODE;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief SPI Set Bidirectional Simplex Receive Only Mode.
+
+The SPI peripheral is set for bidirectional transfers in two-wire simplex mode
+(using a clock wire and a bidirectional data wire), and is placed in a receive state.
+
+@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
+*/
+
void spi_set_bidirectional_receive_only_mode(u32 spi)
{
SPI_CR1(spi) |= SPI_CR1_BIDIMODE;
SPI_CR1(spi) &= ~SPI_CR1_BIDIOE;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief SPI Set Bidirectional Simplex Receive Only Mode.
+
+The SPI peripheral is set for bidirectional transfers in two-wire simplex mode
+(using a clock wire and a bidirectional data wire), and is placed in a transmit state.
+
+@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
+*/
+
void spi_set_bidirectional_transmit_only_mode(u32 spi)
{
SPI_CR1(spi) |= SPI_CR1_BIDIMODE;
SPI_CR1(spi) |= SPI_CR1_BIDIOE;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief SPI Enable the CRC.
+
+The SPI peripheral is set to use a CRC field for transmit and receive.
+
+@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
+*/
+
void spi_enable_crc(u32 spi)
{
SPI_CR1(spi) |= SPI_CR1_CRCEN;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief SPI Disable the CRC.
+
+@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
+*/
+
void spi_disable_crc(u32 spi)
{
SPI_CR1(spi) &= ~SPI_CR1_CRCEN;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief SPI Next Transmit is a Data Word
+
+The next transmission to take place is a data word from the transmit buffer.
+This must be called before transmission to distinguish between sending
+of a data or CRC word.
+
+@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
+*/
+
void spi_set_next_tx_from_buffer(u32 spi)
{
SPI_CR1(spi) &= ~SPI_CR1_CRCNEXT;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief SPI Next Transmit is a CRC Word
+
+The next transmission to take place is a crc word from the hardware crc unit.
+This must be called before transmission to distinguish between sending
+of a data or CRC word.
+
+@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
+*/
+
void spi_set_next_tx_from_crc(u32 spi)
{
SPI_CR1(spi) |= SPI_CR1_CRCNEXT;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief SPI Set Data Frame Format to 8 bits
+
+@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
+*/
+
void spi_set_dff_8bit(u32 spi)
{
SPI_CR1(spi) &= ~SPI_CR1_DFF;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief SPI Set Data Frame Format to 16 bits
+
+@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
+*/
+
void spi_set_dff_16bit(u32 spi)
{
SPI_CR1(spi) |= SPI_CR1_DFF;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief SPI Set Full Duplex (3-wire) Mode
+
+@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
+*/
+
void spi_set_full_duplex_mode(u32 spi)
{
SPI_CR1(spi) &= ~SPI_CR1_RXONLY;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief SPI Set Receive Only Mode for Simplex (2-wire) Unidirectional Transfers
+
+@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
+*/
+
void spi_set_receive_only_mode(u32 spi)
{
SPI_CR1(spi) |= SPI_CR1_RXONLY;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief SPI Enable Slave Management by Hardware
+
+In slave mode the NSS hardware input is used as a select enable for the slave.
+
+@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
+*/
+
void spi_disable_software_slave_management(u32 spi)
{
SPI_CR1(spi) &= ~SPI_CR1_SSM;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief SPI Enable Slave Management by Software
+
+In slave mode the NSS hardware input is replaced by an internal software
+enable/disable of the slave (@ref spi_set_nss_high).
+
+@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
+*/
+
void spi_enable_software_slave_management(u32 spi)
{
SPI_CR1(spi) |= SPI_CR1_SSM;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief SPI Set the Software NSS Signal High
+
+In slave mode, and only when software slave management is used, this replaces
+the NSS signal with a slave select enable signal.
+
+@todo these should perhaps be combined with an SSM enable as it is meaningless otherwise
+
+@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
+*/
+
void spi_set_nss_high(u32 spi)
{
SPI_CR1(spi) |= SPI_CR1_SSI;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief SPI Set the Software NSS Signal Low
+
+In slave mode, and only when software slave management is used, this replaces
+the NSS signal with a slave select disable signal.
+
+@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
+*/
+
void spi_set_nss_low(u32 spi)
{
SPI_CR1(spi) &= ~SPI_CR1_SSI;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief SPI Set to Send LSB First
+
+@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
+*/
+
void spi_send_lsb_first(u32 spi)
{
SPI_CR1(spi) |= SPI_CR1_LSBFIRST;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief SPI Set to Send MSB First
+
+@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
+*/
+
void spi_send_msb_first(u32 spi)
{
SPI_CR1(spi) &= ~SPI_CR1_LSBFIRST;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief SPI Set the Baudrate Prescaler
+
+@todo Why is this specification different to the spi_init_master baudrate values?
+
+@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
+@param[in] baudrate Unsigned int8. Baudrate prescale value @ref spi_br_pre.
+*/
+
void spi_set_baudrate_prescaler(u32 spi, u8 baudrate)
{
u32 reg32;
@@ -240,92 +521,217 @@ void spi_set_baudrate_prescaler(u32 spi, u8 baudrate)
SPI_CR1(spi) = reg32;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief SPI Set to Master Mode
+
+@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
+*/
+
void spi_set_master_mode(u32 spi)
{
SPI_CR1(spi) |= SPI_CR1_MSTR;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief SPI Set to Slave Mode
+
+@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
+*/
+
void spi_set_slave_mode(u32 spi)
{
SPI_CR1(spi) &= ~SPI_CR1_MSTR;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief SPI Set the Clock Polarity to High when Idle
+
+@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
+*/
+
void spi_set_clock_polarity_1(u32 spi)
{
SPI_CR1(spi) |= SPI_CR1_CPOL;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief SPI Set the Clock Polarity to Low when Idle
+
+@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
+*/
+
void spi_set_clock_polarity_0(u32 spi)
{
SPI_CR1(spi) &= ~SPI_CR1_CPOL;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief SPI Set the Clock Phase to Capture on Trailing Edge
+
+@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
+*/
+
void spi_set_clock_phase_1(u32 spi)
{
SPI_CR1(spi) |= SPI_CR1_CPHA;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief SPI Set the Clock Phase to Capture on Leading Edge
+
+@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
+*/
+
void spi_set_clock_phase_0(u32 spi)
{
SPI_CR1(spi) &= ~SPI_CR1_CPHA;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief SPI Enable the Transmit Buffer Empty Interrupt
+
+@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
+*/
+
void spi_enable_tx_buffer_empty_interrupt(u32 spi)
{
SPI_CR2(spi) |= SPI_CR2_TXEIE;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief SPI Disable the Transmit Buffer Empty Interrupt
+
+@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
+*/
+
void spi_disable_tx_buffer_empty_interrupt(u32 spi)
{
SPI_CR2(spi) &= ~SPI_CR2_TXEIE;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief SPI Enable the Receive Buffer Ready Interrupt
+
+@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
+*/
+
void spi_enable_rx_buffer_not_empty_interrupt(u32 spi)
{
SPI_CR2(spi) |= SPI_CR2_RXNEIE;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief SPI Disable the Receive Buffer Ready Interrupt
+
+@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
+*/
+
void spi_disable_rx_buffer_not_empty_interrupt(u32 spi)
{
SPI_CR2(spi) &= ~SPI_CR2_RXNEIE;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief SPI Enable the Error Interrupt
+
+@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
+*/
+
void spi_enable_error_interrupt(u32 spi)
{
SPI_CR2(spi) |= SPI_CR2_ERRIE;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief SPI Disable the Error Interrupt
+
+@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
+*/
+
void spi_disable_error_interrupt(u32 spi)
{
SPI_CR2(spi) &= ~SPI_CR2_ERRIE;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief SPI Set the NSS Pin as an Output
+
+Normally used in master mode to allows the master to place all devices on the
+SPI bus into slave mode. Multimaster mode is not possible.
+
+@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
+*/
+
void spi_enable_ss_output(u32 spi)
{
SPI_CR2(spi) |= SPI_CR2_SSOE;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief SPI Set the NSS Pin as an Input
+
+In master mode this allows the master to sense the presence of other masters. If
+NSS is then pulled low the master is placed into slave mode. In slave mode NSS
+becomes a slave enable.
+
+@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
+*/
+
void spi_disable_ss_output(u32 spi)
{
SPI_CR2(spi) &= ~SPI_CR2_SSOE;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief SPI Enable Transmit Transfers via DMA
+
+This allows transmissions to proceed unattended using DMA to move data to the
+transmit buffer as it becomes available. The DMA channels provided for each
+SPI peripheral are given in the Technical Manual DMA section.
+
+@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
+*/
+
void spi_enable_tx_dma(u32 spi)
{
SPI_CR2(spi) |= SPI_CR2_TXDMAEN;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief SPI Disable Transmit Transfers via DMA
+
+@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
+*/
+
void spi_disable_tx_dma(u32 spi)
{
SPI_CR2(spi) &= ~SPI_CR2_TXDMAEN;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief SPI Enable Receive Transfers via DMA
+
+This allows received data streams to proceed unattended using DMA to move data from
+the receive buffer as data becomes available. The DMA channels provided for each
+SPI peripheral are given in the Technical Manual DMA section.
+
+@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
+*/
+
void spi_enable_rx_dma(u32 spi)
{
SPI_CR2(spi) |= SPI_CR2_RXDMAEN;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief SPI Disable Receive Transfers via DMA
+
+@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
+*/
+
void spi_disable_rx_dma(u32 spi)
{
SPI_CR2(spi) &= ~SPI_CR2_RXDMAEN;
}
+
+/**@}*/
diff --git a/lib/stm32/usart.c b/lib/stm32/usart.c
index 1d0ea9b..5cf861b 100644
--- a/lib/stm32/usart.c
+++ b/lib/stm32/usart.c
@@ -1,3 +1,22 @@
+/** @defgroup STM32F1xx_usart_file USART
+
+@ingroup STM32F_files
+
+@brief <b>libopencm3 STM32F USART</b>
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
+
+@date 30 August 2012
+
+This library supports the USART/UART in the STM32F series
+of ARM Cortex Microcontrollers by ST Microelectronics.
+
+Devices can have up to 3 USARTs and 2 UARTs.
+
+LGPL License Terms @ref lgpl_license
+ */
/*
* This file is part of the libopencm3 project.
*
@@ -17,6 +36,8 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
+/**@{*/
+
#include <libopencm3/stm32/usart.h>
#if defined(STM32F1)
@@ -29,6 +50,20 @@
# error "stm32 family not defined."
#endif
+/*-----------------------------------------------------------------------------*/
+/** @brief USART Set Baudrate.
+
+The baud rate is computed from the APB high-speed prescaler clock (for USART1)
+or the APB low-speed prescaler clock (for other USARTs). These values must
+be correctly set before calling this function (refer to the rcc_clock_setup-*
+functions in RCC).
+
+@todo Add support for USART6 and oversampling in F2/F4
+
+@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
+@param[in] baud unsigned 32 bit. Baud rate specified in Hz.
+*/
+
void usart_set_baudrate(u32 usart, u32 baud)
{
u32 clock = rcc_ppre1_frequency;
@@ -59,6 +94,16 @@ void usart_set_baudrate(u32 usart, u32 baud)
USART_BRR(usart) = ((2 * clock) + baud) / (2 * baud);
}
+/*-----------------------------------------------------------------------------*/
+/** @brief USART Set Word Length.
+
+The word length is set to 8 or 9 bits. Note that the last bit will be a parity bit
+if parity is enabled, in which case the data length will be 7 or 8 bits respectively.
+
+@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
+@param[in] bits unsigned 32 bit. Word length in bits 8 or 9.
+*/
+
void usart_set_databits(u32 usart, u32 bits)
{
if (bits == 8)
@@ -67,6 +112,15 @@ void usart_set_databits(u32 usart, u32 bits)
USART_CR1(usart) |= USART_CR1_M; /* 9 data bits */
}
+/*-----------------------------------------------------------------------------*/
+/** @brief USART Set Stop Bit(s).
+
+The stop bits are specified as 0.5, 1, 1.5 or 2.
+
+@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
+@param[in] stopbits unsigned 32 bit. Stop bits @ref usart_cr2_stopbits.
+*/
+
void usart_set_stopbits(u32 usart, u32 stopbits)
{
u32 reg32;
@@ -76,6 +130,15 @@ void usart_set_stopbits(u32 usart, u32 stopbits)
USART_CR2(usart) = reg32;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief USART Set Parity.
+
+The parity bit can be selected as none, even or odd.
+
+@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
+@param[in] parity unsigned 32 bit. Parity @ref usart_cr1_parity.
+*/
+
void usart_set_parity(u32 usart, u32 parity)
{
u32 reg32;
@@ -85,6 +148,15 @@ void usart_set_parity(u32 usart, u32 parity)
USART_CR1(usart) = reg32;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief USART Set Rx/Tx Mode.
+
+The mode can be selected as Rx only, Tx only or Rx+Tx.
+
+@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
+@param[in] mode unsigned 32 bit. Mode @ref usart_cr1_mode.
+*/
+
void usart_set_mode(u32 usart, u32 mode)
{
u32 reg32;
@@ -94,6 +166,15 @@ void usart_set_mode(u32 usart, u32 mode)
USART_CR1(usart) = reg32;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief USART Set Hardware Flow Control.
+
+The flow control bit can be selected as none, RTS, CTS or RTS+CTS.
+
+@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
+@param[in] flowcontrol unsigned 32 bit. Flowcontrol @ref usart_cr3_flowcontrol.
+*/
+
void usart_set_flow_control(u32 usart, u32 flowcontrol)
{
u32 reg32;
@@ -103,46 +184,112 @@ void usart_set_flow_control(u32 usart, u32 flowcontrol)
USART_CR3(usart) = reg32;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief USART Enable.
+
+@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
+*/
+
void usart_enable(u32 usart)
{
USART_CR1(usart) |= USART_CR1_UE;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief USART Disable.
+
+At the end of the current frame, the USART is disabled to reduce power.
+
+@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
+*/
+
void usart_disable(u32 usart)
{
USART_CR1(usart) &= ~USART_CR1_UE;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief USART Send a Data Word.
+
+@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
+@param[in] data unsigned 16 bit.
+*/
+
void usart_send(u32 usart, u16 data)
{
/* Send data. */
USART_DR(usart) = (data & USART_DR_MASK);
}
+/*-----------------------------------------------------------------------------*/
+/** @brief USART Read a Received Data Word.
+
+If parity is enabled the MSB (bit 7 or 8 depending on the word length) is the parity bit.
+
+@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
+@returns unsigned 16 bit data word.
+*/
+
u16 usart_recv(u32 usart)
{
/* Receive data. */
return USART_DR(usart) & USART_DR_MASK;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief USART Wait for Transmit Data Buffer Empty
+
+Blocks until the transmit data buffer becomes empty and is ready to accept the
+next data word.
+
+@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
+*/
+
void usart_wait_send_ready(u32 usart)
{
/* Wait until the data has been transferred into the shift register. */
while ((USART_SR(usart) & USART_SR_TXE) == 0);
}
+/*-----------------------------------------------------------------------------*/
+/** @brief USART Wait for Received Data Available
+
+Blocks until the receive data buffer holds a valid received data word.
+
+@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
+*/
+
void usart_wait_recv_ready(u32 usart)
{
/* Wait until the data is ready to be received. */
while ((USART_SR(usart) & USART_SR_RXNE) == 0);
}
+/*-----------------------------------------------------------------------------*/
+/** @brief USART Send Data Word with Blocking
+
+Blocks until the transmit data buffer becomes empty then writes the next data word
+for transmission.
+
+@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
+@param[in] data unsigned 16 bit.
+*/
+
void usart_send_blocking(u32 usart, u16 data)
{
usart_wait_send_ready(usart);
usart_send(usart, data);
}
+/*-----------------------------------------------------------------------------*/
+/** @brief USART Read a Received Data Word with Blocking.
+
+Wait until a data word has been received then return the word.
+
+@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
+@returns unsigned 16 bit data word.
+*/
+
u16 usart_recv_blocking(u32 usart)
{
usart_wait_recv_ready(usart);
@@ -150,22 +297,148 @@ u16 usart_recv_blocking(u32 usart)
return usart_recv(usart);
}
+/*-----------------------------------------------------------------------------*/
+/** @brief USART Receiver DMA Enable.
+
+DMA is available on:
+@li USART1 Rx DMA1 channel 5.
+@li USART2 Rx DMA1 channel 6.
+@li USART3 Rx DMA1 channel 3.
+@li UART4 Rx DMA2 channel 3.
+
+@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
+*/
+
void usart_enable_rx_dma(u32 usart)
{
USART_CR3(usart) |= USART_CR3_DMAR;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief USART Receiver DMA Disable.
+
+@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
+*/
+
void usart_disable_rx_dma(u32 usart)
{
USART_CR3(usart) &= ~USART_CR3_DMAR;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief USART Transmitter DMA Enable.
+
+DMA is available on:
+@li USART1 Tx DMA1 channel 4.
+@li USART2 Tx DMA1 channel 7.
+@li USART3 Tx DMA1 channel 2.
+@li UART4 Tx DMA2 channel 5.
+
+@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
+*/
+
void usart_enable_tx_dma(u32 usart)
{
USART_CR3(usart) |= USART_CR3_DMAT;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief USART Transmitter DMA Disable.
+
+@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
+*/
+
void usart_disable_tx_dma(u32 usart)
{
USART_CR3(usart) &= ~USART_CR3_DMAT;
}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief USART Receiver Interrupt Enable.
+
+@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
+*/
+
+void usart_enable_rx_interrupt(u32 usart)
+{
+ USART_CR1(usart) |= USART_CR1_RXNEIE;
+}
+
+
+/*-----------------------------------------------------------------------------*/
+/** @brief USART Receiver Interrupt Disable.
+
+@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
+*/
+
+void usart_disable_rx_interrupt(u32 usart)
+{
+ USART_CR1(usart) &= ~USART_CR1_RXNEIE;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief USART Transmitter Interrupt Enable.
+
+@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
+*/
+
+void usart_enable_tx_interrupt(u32 usart)
+{
+ USART_CR1(usart) |= USART_CR1_TXEIE;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief USART Transmitter Interrupt Disable.
+
+@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
+*/
+
+void usart_disable_tx_interrupt(u32 usart)
+{
+ USART_CR1(usart) &= ~USART_CR1_TXEIE;
+}
+
+
+/*---------------------------------------------------------------------------*/
+/** @brief USART Read a Status Flag.
+
+@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
+@param[in] flag Unsigned int32. Status register flag @ref usart_sr_flags.
+@returns boolean: flag set.
+*/
+
+bool usart_get_flag(u32 usart, u32 flag)
+{
+ return ((USART_SR(usart) & flag) != 0);
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief USART Return Interrupt Source.
+
+Returns true if the specified interrupt flag (IDLE, RXNE, TC, TXE or OE) was
+set and the interrupt was enabled. If the specified flag is not an interrupt
+flag, the function returns false.
+
+@todo These are the most important interrupts likely to be used. Others
+relating to LIN break, and error conditions in multibuffer communication, need
+to be added for completeness.
+
+@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
+@param[in] flag Unsigned int32. Status register flag @ref usart_sr_flags.
+@returns boolean: flag and interrupt enable both set.
+*/
+
+bool usart_get_interrupt_source(u32 usart, u32 flag)
+{
+u32 flag_set = (USART_SR(usart) & flag);
+/* IDLE, RXNE, TC, TXE interrupts */
+ if ((flag >= USART_SR_IDLE) && (flag <= USART_SR_TXE))
+ return ((flag_set & USART_CR1(usart)) != 0);
+/* Overrun error */
+ else if (flag == USART_SR_ORE)
+ return (flag_set && (USART_CR3(usart) & USART_CR3_CTSIE));
+ return (false);
+}
+
+/**@}*/
+