aboutsummaryrefslogtreecommitdiff
path: root/lib/stm32/f4
diff options
context:
space:
mode:
Diffstat (limited to 'lib/stm32/f4')
-rw-r--r--lib/stm32/f4/Makefile8
-rw-r--r--lib/stm32/f4/adc.c1027
-rw-r--r--lib/stm32/f4/dma.c772
-rw-r--r--lib/stm32/f4/exti.c146
-rw-r--r--lib/stm32/f4/gpio.c142
-rw-r--r--lib/stm32/f4/timer.c928
-rw-r--r--lib/stm32/f4/vector.c341
-rw-r--r--lib/stm32/f4/vector_chipset.c (renamed from lib/stm32/f4/scb.c)20
8 files changed, 1809 insertions, 1575 deletions
diff --git a/lib/stm32/f4/Makefile b/lib/stm32/f4/Makefile
index fd0b279..09fe573 100644
--- a/lib/stm32/f4/Makefile
+++ b/lib/stm32/f4/Makefile
@@ -29,10 +29,10 @@ CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \
-ffunction-sections -fdata-sections -MD -DSTM32F4
# ARFLAGS = rcsv
ARFLAGS = rcs
-OBJS = vector.o rcc.o gpio.o usart.o spi.o flash.o nvic.o \
- i2c.o systick.o exti.o scb.o pwr.o timer.o \
- usb.o usb_standard.o usb_control.o usb_f107.o \
- assert.o
+OBJS = rcc.o gpio2.o usart.o spi.o flash.o \
+ i2c.o exti2.o pwr.o timer.o \
+ usb.o usb_standard.o usb_control.o usb_fx07_common.o usb_f107.o \
+ usb_f207.o adc.o dma.o
VPATH += ../../usb:../:../../cm3
diff --git a/lib/stm32/f4/adc.c b/lib/stm32/f4/adc.c
new file mode 100644
index 0000000..7475fac
--- /dev/null
+++ b/lib/stm32/f4/adc.c
@@ -0,0 +1,1027 @@
+/** @defgroup STM32F4xx_adc_file ADC
+
+@ingroup STM32F4xx
+
+@brief <b>libopencm3 STM32F4xx Analog to Digital Converters</b>
+
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 30 August 2012
+
+This library supports the A/D Converter Control System in the STM32 series
+of ARM Cortex Microcontrollers by ST Microelectronics.
+
+Devices can have up to three A/D converters each with their own set of registers.
+However all the A/D converters share a common clock which is prescaled from the APB2
+clock by default by a minimum factor of 2 to a maximum of 8. The ADC resolution
+can be set to 12, 10, 8 or 6 bits.
+
+Each A/D converter has up to 19 channels:
+@li On ADC1 the analog channels 16 is internally connected to the temperature
+sensor, channel 17 to V<sub>REFINT</sub>, and channel 18 to V<sub>BATT</sub>.
+@li On ADC2 and ADC3 the analog channels 16 - 18 are not used.
+
+The conversions can occur as a one-off conversion whereby the process stops once
+conversion is complete. The conversions can also be continuous wherein a new
+conversion starts immediately the previous conversion has ended.
+
+Conversion can occur as a single channel conversion or a scan of a group of
+channels in either continuous or one-off mode. If more than one channel is converted
+in a scan group, DMA must be used to transfer the data as there is only one
+result register available. An interrupt can be set to occur at the end of
+conversion, which occurs after all channels have been scanned.
+
+A discontinuous mode allows a subgroup of group of a channels to be converted in
+bursts of a given length.
+
+Injected conversions allow a second group of channels to be converted separately
+from the regular group. An interrupt can be set to occur at the end of
+conversion, which occurs after all channels have been scanned.
+
+@section adc_f4_api_ex Basic ADC Handling API.
+
+Example 1: Simple single channel conversion polled. Enable the peripheral clock
+and ADC, reset ADC and set the prescaler divider. Set multiple mode to independent.
+
+@code
+gpio_mode_setup(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO1);
+rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_ADC1EN);
+adc_set_clk_prescale(RCC_CFGR_ADCPRE_BY2);
+adc_disable_scan_mode(ADC1);
+adc_set_single_conversion_mode(ADC1);
+adc_set_sample_time(ADC1, ADC_CHANNEL0, ADC_SMPR1_SMP_1DOT5CYC);
+u8 channels[] = ADC_CHANNEL0;
+adc_set_regular_sequence(ADC1, 1, channels);
+adc_set_multi_mode(ADC_CCR_MULTI_INDEPENDENT);
+adc_power_on(ADC1);
+adc_start_conversion_regular(ADC1);
+while (! adc_eoc(ADC1));
+reg16 = adc_read_regular(ADC1);
+@endcode
+
+LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Ken Sarkies <ksarkies@internode.on.net>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopencm3/stm32/f4/adc.h>
+
+/**@{*/
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Off
+
+Turn off the ADC to reduce power consumption to a few microamps.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_off(u32 adc)
+{
+ ADC_CR2(adc) &= ~ADC_CR2_ADON;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Enable Analog Watchdog for Regular Conversions
+
+The analog watchdog allows the monitoring of an analog signal between two threshold
+levels. The thresholds must be preset. Comparison is done before data alignment
+takes place, so the thresholds are left-aligned.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_enable_analog_watchdog_regular(u32 adc)
+{
+ ADC_CR1(adc) |= ADC_CR1_AWDEN;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Disable Analog Watchdog for Regular Conversions
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_disable_analog_watchdog_regular(u32 adc)
+{
+ ADC_CR1(adc) &= ~ADC_CR1_AWDEN;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Enable Analog Watchdog for Injected Conversions
+
+The analog watchdog allows the monitoring of an analog signal between two threshold
+levels. The thresholds must be preset. Comparison is done before data alignment
+takes place, so the thresholds are left-aligned.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_enable_analog_watchdog_injected(u32 adc)
+{
+ ADC_CR1(adc) |= ADC_CR1_JAWDEN;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Disable Analog Watchdog for Injected Conversions
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_disable_analog_watchdog_injected(u32 adc)
+{
+ ADC_CR1(adc) &= ~ADC_CR1_JAWDEN;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Enable Discontinuous Mode for Regular Conversions
+
+In this mode the ADC converts, on each trigger, a subgroup of up to 8 of the
+defined regular channel group. The subgroup is defined by the number of
+consecutive channels to be converted. After a subgroup has been converted
+the next trigger will start conversion of the immediately following subgroup
+of the same length or until the whole group has all been converted. When the
+the whole group has been converted, the next trigger will restart conversion
+of the subgroup at the beginning of the whole group.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] length Unsigned int8. Number of channels in the group @ref adc_cr1_discnum
+*/
+
+void adc_enable_discontinuous_mode_regular(u32 adc, u8 length)
+{
+ if ( (length-1) > 7 ) return;
+ ADC_CR1(adc) |= ADC_CR1_DISCEN;
+ ADC_CR2(adc) |= ((length-1) << ADC_CR1_DISCNUM_SHIFT);
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Disable Discontinuous Mode for Regular Conversions
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_disable_discontinuous_mode_regular(u32 adc)
+{
+ ADC_CR1(adc) &= ~ADC_CR1_DISCEN;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Enable Discontinuous Mode for Injected Conversions
+
+In this mode the ADC converts sequentially one channel of the defined group of
+injected channels, cycling back to the first channel in the group once the
+entire group has been converted.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_enable_discontinuous_mode_injected(u32 adc)
+{
+ ADC_CR1(adc) |= ADC_CR1_JDISCEN;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Disable Discontinuous Mode for Injected Conversions
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_disable_discontinuous_mode_injected(u32 adc)
+{
+ ADC_CR1(adc) &= ~ADC_CR1_JDISCEN;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Enable Automatic Injected Conversions
+
+The ADC converts a defined injected group of channels immediately after the
+regular channels have been converted. The external trigger on the injected
+channels is disabled as required.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_enable_automatic_injected_group_conversion(u32 adc)
+{
+ adc_disable_external_trigger_injected(adc);
+ ADC_CR1(adc) |= ADC_CR1_JAUTO;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Disable Automatic Injected Conversions
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_disable_automatic_injected_group_conversion(u32 adc)
+{
+ ADC_CR1(adc) &= ~ADC_CR1_JAUTO;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Enable Analog Watchdog for All Regular and/or Injected Channels
+
+The analog watchdog allows the monitoring of an analog signal between two threshold
+levels. The thresholds must be preset. Comparison is done before data alignment
+takes place, so the thresholds are left-aligned.
+
+@note The analog watchdog must be enabled for either or both of the regular or
+injected channels. If neither are enabled, the analog watchdog feature will be
+disabled.
+@ref adc_enable_analog_watchdog_injected, @ref adc_enable_analog_watchdog_regular.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_enable_analog_watchdog_on_all_channels(u32 adc)
+{
+ ADC_CR1(adc) &= ~ADC_CR1_AWDSGL;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Enable Analog Watchdog for a Selected Channel
+
+The analog watchdog allows the monitoring of an analog signal between two threshold
+levels. The thresholds must be preset. Comparison is done before data alignment
+takes place, so the thresholds are left-aligned.
+
+@note The analog watchdog must be enabled for either or both of the regular or
+injected channels. If neither are enabled, the analog watchdog feature will be
+disabled. If both are enabled, the same channel number is monitored.
+@ref adc_enable_analog_watchdog_injected, @ref adc_enable_analog_watchdog_regular.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] channel Unsigned int8. ADC channel number @ref adc_watchdog_channel
+*/
+
+void adc_enable_analog_watchdog_on_selected_channel(u32 adc, u8 channel)
+{
+ u32 reg32;
+
+ reg32 = (ADC_CR1(adc) & ~ADC_CR1_AWDCH_MASK); /* Clear bits [4:0]. */
+ if (channel < 18)
+ reg32 |= channel;
+ ADC_CR1(adc) = reg32;
+ ADC_CR1(adc) |= ADC_CR1_AWDSGL;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Set Scan Mode
+
+In this mode a conversion consists of a scan of the predefined set of channels,
+regular and injected, each channel conversion immediately following the
+previous one. It can use single, continuous or discontinuous mode.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_enable_scan_mode(u32 adc)
+{
+ ADC_CR1(adc) |= ADC_CR1_SCAN;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Disable Scan Mode
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_disable_scan_mode(u32 adc)
+{
+ ADC_CR1(adc) &= ~ADC_CR1_SCAN;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Enable Injected End-Of-Conversion Interrupt
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_enable_eoc_interrupt_injected(u32 adc)
+{
+ ADC_CR1(adc) |= ADC_CR1_JEOCIE;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Disable Injected End-Of-Conversion Interrupt
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_disable_eoc_interrupt_injected(u32 adc)
+{
+ ADC_CR1(adc) &= ~ADC_CR1_JEOCIE;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Enable Analog Watchdog Interrupt
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_enable_awd_interrupt(u32 adc)
+{
+ ADC_CR1(adc) |= ADC_CR1_AWDIE;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Disable Analog Watchdog Interrupt
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_disable_awd_interrupt(u32 adc)
+{
+ ADC_CR1(adc) &= ~ADC_CR1_AWDIE;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Enable Regular End-Of-Conversion Interrupt
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_enable_eoc_interrupt(u32 adc)
+{
+ ADC_CR1(adc) |= ADC_CR1_EOCIE;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Disable Regular End-Of-Conversion Interrupt
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_disable_eoc_interrupt(u32 adc)
+{
+ ADC_CR1(adc) &= ~ADC_CR1_EOCIE;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Software Triggered Conversion on Regular Channels
+
+This starts conversion on a set of defined regular channels. It is cleared by
+hardware once conversion starts.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_start_conversion_regular(u32 adc)
+{
+ /* Start conversion on regular channels. */
+ ADC_CR2(adc) |= ADC_CR2_SWSTART;
+
+ /* Wait until the ADC starts the conversion. */
+ while (ADC_CR2(adc) & ADC_CR2_SWSTART);
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Software Triggered Conversion on Injected Channels
+
+This starts conversion on a set of defined injected channels. It is cleared by
+hardware once conversion starts.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_start_conversion_injected(u32 adc)
+{
+ /* Start conversion on injected channels. */
+ ADC_CR2(adc) |= ADC_CR2_JSWSTART;
+
+ /* Wait until the ADC starts the conversion. */
+ while (ADC_CR2(adc) & ADC_CR2_JSWSTART);
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Set the Data as Left Aligned
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_set_left_aligned(u32 adc)
+{
+ ADC_CR2(adc) |= ADC_CR2_ALIGN;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Set the Data as Right Aligned
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_set_right_aligned(u32 adc)
+{
+ ADC_CR2(adc) &= ~ADC_CR2_ALIGN;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Enable DMA Transfers
+
+Only available for ADC1 through DMA1 channel1, and ADC3 through DMA2 channel5.
+ADC2 will use DMA if it is set as slave in dual mode with ADC1 in DMA transfer
+mode.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_enable_dma(u32 adc)
+{
+ if ((adc == ADC1) | (adc == ADC3))
+ ADC_CR2(adc) |= ADC_CR2_DMA;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Disable DMA Transfers
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_disable_dma(u32 adc)
+{
+ if ((adc == ADC1) | (adc == ADC3))
+ ADC_CR2(adc) &= ~ADC_CR2_DMA;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Enable Continuous Conversion Mode
+
+In this mode the ADC starts a new conversion of a single channel or a channel
+group immediately following completion of the previous channel group conversion.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_set_continuous_conversion_mode(u32 adc)
+{
+ ADC_CR2(adc) |= ADC_CR2_CONT;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Enable Single Conversion Mode
+
+In this mode the ADC performs a conversion of one channel or a channel group
+and stops.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_set_single_conversion_mode(u32 adc)
+{
+ ADC_CR2(adc) &= ~ADC_CR2_CONT;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Set the Sample Time for a Single Channel
+
+The sampling time can be selected in ADC clock cycles from 1.5 to 239.5.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] channel Unsigned int8. ADC Channel integer 0..18 or from @ref adc_channel
+@param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg
+*/
+
+void adc_set_sample_time(u32 adc, u8 channel, u8 time)
+{
+ u32 reg32;
+
+ if (channel < 10) {
+ reg32 = ADC_SMPR2(adc);
+ reg32 &= ~(0x7 << (channel * 3));
+ reg32 |= (time << (channel * 3));
+ ADC_SMPR2(adc) = reg32;
+ } else {
+ reg32 = ADC_SMPR1(adc);
+ reg32 &= ~(0x7 << ((channel - 10) * 3));
+ reg32 |= (time << ((channel - 10) * 3));
+ ADC_SMPR1(adc) = reg32;
+ }
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Set the Sample Time for All Channels
+
+The sampling time can be selected in ADC clock cycles from 1.5 to 239.5, same for
+all channels.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg
+*/
+
+void adc_set_sample_time_on_all_channels(u32 adc, u8 time)
+{
+ u8 i;
+ u32 reg32 = 0;
+
+ for (i = 0; i <= 9; i++)
+ reg32 |= (time << (i * 3));
+ ADC_SMPR2(adc) = reg32;
+
+ for (i = 10; i <= 17; i++)
+ reg32 |= (time << ((i - 10) * 3));
+ ADC_SMPR1(adc) = reg32;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Set Analog Watchdog Upper Threshold
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] threshold Unsigned int8. Upper threshold value
+*/
+
+void adc_set_watchdog_high_threshold(u32 adc, u16 threshold)
+{
+ u32 reg32 = 0;
+
+ reg32 = (u32)threshold;
+ reg32 &= ~0xfffff000; /* Clear all bits above 11. */
+ ADC_HTR(adc) = reg32;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Set Analog Watchdog Lower Threshold
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] threshold Unsigned int8. Lower threshold value
+*/
+
+void adc_set_watchdog_low_threshold(u32 adc, u16 threshold)
+{
+ u32 reg32 = 0;
+
+ reg32 = (u32)threshold;
+ reg32 &= ~0xfffff000; /* Clear all bits above 11. */
+ ADC_LTR(adc) = reg32;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Set a Regular Channel Conversion Sequence
+
+Define a sequence of channels to be converted as a regular group with a length
+from 1 to 16 channels. If this is called during conversion, the current conversion
+is reset and conversion begins again with the newly defined group.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] length Unsigned int8. Number of channels in the group.
+@param[in] channel Unsigned int8[]. Set of channels in sequence, integers 0..18.
+*/
+
+void adc_set_regular_sequence(u32 adc, u8 length, u8 channel[])
+{
+ u32 reg32_1 = 0, reg32_2 = 0, reg32_3 = 0;
+ u8 i = 0;
+
+ /* Maximum sequence length is 16 channels. */
+ if (length > 16)
+ return;
+
+ for (i = 1; i <= length; i++) {
+ if (i <= 6)
+ reg32_3 |= (channel[i - 1] << ((i - 1) * 5));
+ if ((i > 6) & (i <= 12))
+ reg32_2 |= (channel[i - 1] << ((i - 6 - 1) * 5));
+ if ((i > 12) & (i <= 16))
+ reg32_1 |= (channel[i - 1] << ((i - 12 - 1) * 5));
+ }
+ reg32_1 |= ((length -1) << ADC_SQR1_L_LSB);
+
+ ADC_SQR1(adc) = reg32_1;
+ ADC_SQR2(adc) = reg32_2;
+ ADC_SQR3(adc) = reg32_3;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Set an Injected Channel Conversion Sequence
+
+Defines a sequence of channels to be converted as an injected group with a length
+from 1 to 4 channels. If this is called during conversion, the current conversion
+is reset and conversion begins again with the newly defined group.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] length Unsigned int8. Number of channels in the group.
+@param[in] channel Unsigned int8[]. Set of channels in sequence, integers 0..18
+*/
+
+void adc_set_injected_sequence(u32 adc, u8 length, u8 channel[])
+{
+ u32 reg32 = 0;
+ u8 i = 0;
+
+ /* Maximum sequence length is 4 channels. */
+ if ((length-1) > 3)
+ return;
+
+ for (i = 1; i <= length; i++)
+ reg32 |= (channel[4 - i] << ((4 - i) * 5));
+
+ reg32 |= ((length - 1) << ADC_JSQR_JL_LSB);
+
+ ADC_JSQR(adc) = reg32;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Read the End-of-Conversion Flag
+
+This flag is set after all channels of a regular or injected group have been
+converted.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@returns bool. End of conversion flag.
+*/
+
+bool adc_eoc(u32 adc)
+{
+ return ((ADC_SR(adc) & ADC_SR_EOC) != 0);
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Read the End-of-Conversion Flag for Injected Conversion
+
+This flag is set after all channels of an injected group have been converted.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@returns bool. End of conversion flag.
+*/
+
+bool adc_eoc_injected(u32 adc)
+{
+ return ((ADC_SR(adc) & ADC_SR_JEOC) != 0);
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Read from the Regular Conversion Result Register
+
+The result read back is 12 bits, right or left aligned within the first 16 bits.
+For ADC1 only, the higher 16 bits will hold the result from ADC2 if
+an appropriate dual mode has been set @see adc_set_dual_mode.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@returns Unsigned int32 conversion result.
+*/
+
+u32 adc_read_regular(u32 adc)
+{
+ return ADC_DR(adc);
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Read from an Injected Conversion Result Register
+
+The result read back from the selected injected result register (one of four) is
+12 bits, right or left aligned within the first 16 bits. The result can have a
+negative value if the injected channel offset has been set @see adc_set_injected_offset.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] reg Unsigned int8. Register number (1 ... 4).
+@returns Unsigned int32 conversion result.
+*/
+
+u32 adc_read_injected(u32 adc, u8 reg)
+{
+ switch (reg) {
+ case 1:
+ return ADC_JDR1(adc);
+ case 2:
+ return ADC_JDR2(adc);
+ case 3:
+ return ADC_JDR3(adc);
+ case 4:
+ return ADC_JDR4(adc);
+ }
+ return 0;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Set the Injected Channel Data Offset
+
+This value is subtracted from the injected channel results after conversion
+is complete, and can result in negative results. A separate value can be specified
+for each injected data register.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] reg Unsigned int8. Register number (1 ... 4).
+@param[in] offset Unsigned int32.
+*/
+
+void adc_set_injected_offset(u32 adc, u8 reg, u32 offset)
+{
+ switch (reg) {
+ case 1:
+ ADC_JOFR1(adc) = offset;
+ break;
+ case 2:
+ ADC_JOFR2(adc) = offset;
+ break;
+ case 3:
+ ADC_JOFR3(adc) = offset;
+ break;
+ case 4:
+ ADC_JOFR4(adc) = offset;
+ break;
+ }
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Power On
+
+If the ADC is in power-down mode then it is powered up. The application needs
+to wait a time of about 3 microseconds for stabilization before using the ADC.
+If the ADC is already on this function call will have no effect.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_power_on(u32 adc)
+{
+ ADC_CR2(adc) |= ADC_CR2_ADON;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Set Clock Prescale
+
+The ADC clock taken from the APB2 clock can be scaled down by 2, 4, 6 or 8.
+
+@param[in] prescale Unsigned int32. Prescale value for ADC Clock @ref adc_ccr_adcpre
+*/
+
+void adc_set_clk_prescale(u32 prescale)
+{
+ u32 reg32 = ((ADC_CCR & ~ADC_CCR_ADCPRE_MASK) | prescale);
+ ADC_CCR = reg32;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Set Dual/Triple Mode
+
+The multiple mode uses ADC1 as master, ADC2 and optionally ADC3 in a slave
+arrangement. This setting is applied to ADC1 only.
+
+The various modes possible are described in the reference manual.
+
+@param[in] mode Unsigned int32. Multiple mode selection from @ref adc_multi_mode
+*/
+
+void adc_set_multi_mode(u32 mode)
+{
+ ADC_CCR |= mode;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Enable an External Trigger for Regular Channels
+
+This enables an external trigger for set of defined regular channels, and sets the
+polarity of the trigger event: rising or falling edge or both. Note that if the
+trigger polarity is zero, triggering is disabled.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] trigger Unsigned int32. Trigger identifier @ref adc_trigger_regular
+@param[in] polarity Unsigned int32. Trigger polarity @ref adc_trigger_polarity_regular
+*/
+
+void adc_enable_external_trigger_regular(u32 adc, u32 trigger, u32 polarity)
+{
+ u32 reg32 = ADC_CR2(adc);
+
+ reg32 &= ~(ADC_CR2_EXTSEL_MASK | ADC_CR2_EXTEN_MASK);
+ reg32 |= (trigger | polarity);
+ ADC_CR2(adc) = reg32;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Disable an External Trigger for Regular Channels
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_disable_external_trigger_regular(u32 adc)
+{
+ ADC_CR2(adc) &= ~ADC_CR2_EXTEN_MASK;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Enable an External Trigger for Injected Channels
+
+This enables an external trigger for set of defined injected channels, and sets the
+polarity of the trigger event: rising or falling edge or both.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] trigger Unsigned int8. Trigger identifier @ref adc_trigger_injected
+@param[in] polarity Unsigned int32. Trigger polarity @ref adc_trigger_polarity_injected
+*/
+
+void adc_enable_external_trigger_injected(u32 adc, u32 trigger, u32 polarity)
+{
+ u32 reg32 = ADC_CR2(adc);
+
+ reg32 &= ~(ADC_CR2_JEXTSEL_MASK | ADC_CR2_JEXTEN_MASK);
+ reg32 |= (trigger | polarity);
+ ADC_CR2(adc) = reg32;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Disable an External Trigger for Injected Channels
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_disable_external_trigger_injected(u32 adc)
+{
+ ADC_CR2(adc) &= ~ADC_CR2_JEXTEN_MASK;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Set Resolution
+
+ADC Resolution can be reduced from 12 bits to 10, 8 or 6 bits for a corresponding
+reduction in conversion time (resolution + 3 ADC clock cycles).
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] resolution Unsigned int8. Resolution value @ref adc_cr1_res
+*/
+
+void adc_set_resolution(u32 adc, u16 resolution)
+{
+ u32 reg32 = ADC_CR1(adc);
+
+ reg32 &= ~ADC_CR1_RES_MASK;
+ reg32 |= resolution;
+ ADC_CR1(adc) = reg32;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Enable the Overrun Interrupt
+
+The overrun interrupt is generated when data is not read from a result register
+before the next conversion is written. If DMA is enabled, all transfers are
+terminated and any conversion sequence is aborted.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_enable_overrun_interrupt(u32 adc)
+{
+ ADC_CR1(adc) |= ADC_CR1_OVRIE;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Disable the Overrun Interrupt
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_disable_overrun_interrupt(u32 adc)
+{
+ ADC_CR1(adc) &= ~ADC_CR1_OVRIE;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Read the Overrun Flag
+
+The overrun flag is set when data is not read from a result register before the next
+conversion is written. If DMA is enabled, all transfers are terminated and any
+conversion sequence is aborted.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@returns Unsigned int32 conversion result.
+*/
+
+bool adc_get_overrun_flag(u32 adc)
+{
+ return (ADC_SR(adc) & ADC_SR_OVR);
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Clear Overrun Flags
+
+The overrun flag is cleared. Note that if an overrun occurs, DMA is terminated.
+The flag must be cleared and the DMA stream and ADC reinitialised to resume
+conversions (see the reference manual).
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@returns Unsigned int32 conversion result.
+*/
+
+void adc_clear_overrun_flag(u32 adc)
+{
+/* need to write zero to clear this */
+ ADC_SR(adc) &= ~ADC_SR_OVR;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Enable an EOC for Each Conversion
+
+The EOC is set after each conversion in a sequence rather than at the end of the
+sequence. Overrun detection is enabled only if DMA is enabled.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_eoc_after_each(u32 adc)
+{
+ ADC_CR2(adc) |= ADC_CR2_EOCS;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Disable the EOC for Each Conversion
+
+The EOC is set at the end of each sequence rather than after each conversion in the
+sequence. Overrun detection is enabled always.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_eoc_after_group(u32 adc)
+{
+ ADC_CR2(adc) &= ~ADC_CR2_EOCS;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Set DMA to Continue
+
+This must be set to allow DMA to continue to operate after the last conversion in
+the DMA sequence. This allows DMA to be used in continuous circular mode.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_set_dma_continue(u32 adc)
+{
+ ADC_CR2(adc) |= ADC_CR2_DDS;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Set DMA to Terminate
+
+This must be set to allow DMA to terminate after the last conversion in the DMA
+sequence. This can avoid overrun errors.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_set_dma_terminate(u32 adc)
+{
+ ADC_CR2(adc) &= ~ADC_CR2_DDS;
+}
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Read the Analog Watchdog Flag
+
+This flag is set when the converted voltage crosses the high or low thresholds.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@returns bool. AWD flag.
+*/
+
+bool adc_awd(u32 adc)
+{
+ return (ADC_SR(adc) & ADC_SR_AWD);
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Enable The Temperature Sensor
+
+This enables both the sensor and the reference voltage measurements on channels
+16 and 17. These are only available on ADC1 channel 16 and 17 respectively.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_enable_temperature_sensor()
+{
+ ADC_CCR |= ADC_CCR_TSVREFE;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Disable The Temperature Sensor
+
+Disabling this will reduce power consumption from the sensor and the reference
+voltage measurements.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_disable_temperature_sensor()
+{
+ ADC_CCR &= ~ADC_CCR_TSVREFE;
+}
+
+/*-----------------------------------------------------------------------------*/
+
+/**@}*/
+
diff --git a/lib/stm32/f4/dma.c b/lib/stm32/f4/dma.c
new file mode 100644
index 0000000..7c80dcf
--- /dev/null
+++ b/lib/stm32/f4/dma.c
@@ -0,0 +1,772 @@
+/** @defgroup STM32F4xx-dma-file DMA
+
+@ingroup STM32F4xx
+
+@brief <b>libopencm3 STM32F4xx DMA Controller</b>
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 18 October 2012
+
+This library supports the DMA Control System in the STM32F2 and STM32F4
+series of ARM Cortex Microcontrollers by ST Microelectronics.
+
+Up to two DMA controllers are supported each with 8 streams, and each stream
+having up to 8 channels hardware dedicated to various peripheral DMA signals.
+
+DMA transfers can be configured to occur between peripheral and memory in
+either direction, and memory to memory. Peripheral to peripheral transfer
+is not supported. Circular mode transfers are also supported in transfers
+involving a peripheral. An arbiter is provided to resolve priority DMA
+requests. Transfers can be made with 8, 16 or 32 bit words.
+
+Each stream has access to a 4 word deep FIFO and can use double buffering
+by means of two memory pointers. When using the FIFO it is possible to
+configure transfers to occur in indivisible bursts.
+
+It is also possible to select a peripheral to control the flow of data rather
+than the DMA controller. This limits the functionality but is udeful when the
+number of transfers is unknown.
+
+LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Ken Sarkies <ksarkies@internode.on.net>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/**@{*/
+
+#include <libopencm3/stm32/f4/dma.h>
+
+/*-----------------------------------------------------------------------------*/
+/** @brief DMA Stream Reset
+
+The specified stream is disabled and configuration registers are cleared.
+
+@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
+@param[in] stream unsigned int8. Stream number: @ref dma_st_number
+*/
+
+void dma_stream_reset(u32 dma, u8 stream)
+{
+/* Disable stream (must be done before register is otherwise changed). */
+ DMA_SCR(dma, stream) &= ~DMA_SCR_EN;
+/* Reset all config bits. */
+ DMA_SCR(dma, stream) = 0;
+/* Reset data transfer number. */
+ DMA_SNDTR(dma, stream) = 0;
+/* Reset peripheral and memory addresses. */
+ DMA_SPAR(dma, stream) = 0;
+ DMA_SM0AR(dma, stream) = 0;
+ DMA_SM1AR(dma, stream) = 0;
+/* This is the default setting */
+ DMA_SFCR(dma, stream) = 0x21;
+/* Reset all stream interrupt flags using the interrupt flag clear register. */
+ u32 mask = DMA_ISR_MASK(stream);
+ if (stream < 4)
+ {
+ DMA_LIFCR(dma) |= mask;
+ }
+ else
+ {
+ DMA_HIFCR(dma) |= mask;
+ }
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief DMA Stream Clear Interrupt Flag
+
+The interrupt flag for the stream is cleared. More than one interrupt for the
+same stream may be cleared by using the logical OR of the interrupt flags.
+
+@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
+@param[in] stream unsigned int8. Stream number: @ref dma_st_number
+@param[in] interrupts unsigned int32. Logical OR of interrupt numbers: @ref dma_if_offset
+*/
+
+void dma_clear_interrupt_flags(u32 dma, u8 stream, u32 interrupts)
+{
+/* Get offset to interrupt flag location in stream field */
+ u32 flags = (interrupts << DMA_ISR_OFFSET(stream));
+/* First four streams are in low register. Flag clear must be set then reset. */
+ if (stream < 4)
+ {
+ DMA_LIFCR(dma) = flags;
+ }
+ else
+ {
+ DMA_HIFCR(dma) = flags;
+ }
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief DMA Stream Read Interrupt Flag
+
+The interrupt flag for the stream is returned.
+
+@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
+@param[in] stream unsigned int8. Stream number: @ref dma_st_number
+@param[in] interrupt unsigned int32. Interrupt number: @ref dma_if_offset
+@returns bool interrupt flag is set.
+*/
+
+bool dma_get_interrupt_flag(u32 dma, u8 stream, u32 interrupt)
+{
+/* get offset to interrupt flag location in stream field.
+Assumes stream and interrupt parameters are integers */
+ u32 flag = (interrupt << DMA_ISR_OFFSET(stream));
+/* First four streams are in low register */
+ if (stream < 4) return ((DMA_LISR(dma) & flag) > 0);
+ else return ((DMA_HISR(dma) & flag) > 0);
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief DMA Stream Enable Transfer Direction
+
+Set peripheral to memory, memory to peripheral or memory to memory. If memory
+to memory mode is selected, circular mode and double buffer modes are disabled.
+Ensure that these modes are not enabled at a later time.
+
+Ensure that the stream is disabled otherwise the setting will not be changed.
+
+@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
+@param[in] stream unsigned int8. Stream number: @ref dma_st_number
+@param[in] direction unsigned int32. Data transfer direction @ref dma_st_dir
+*/
+
+void dma_set_transfer_mode(u32 dma, u8 stream, u32 direction)
+{
+ u32 reg32 = (DMA_SCR(dma, stream) & ~DMA_SCR_DIR_MASK);
+/* Disable circular and double buffer modes if memory to memory transfers
+are in effect (Direct Mode is automatically disabled by hardware) */
+ if (direction == DMA_SCR_DIR_MEM2MEM)
+ {
+ reg32 &= ~(DMA_SCR_CIRC | DMA_SCR_DBM);
+ }
+ DMA_SCR(dma, stream) = (reg32 | direction);
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief DMA Stream Set Priority
+
+Stream Priority has four levels: low to very high. This has precedence over the
+hardware priority. In the event of equal software priority the lower numbered
+stream has priority.
+
+Ensure that the stream is disabled otherwise the setting will not be changed.
+
+@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
+@param[in] stream unsigned int8. Stream number: @ref dma_st_number
+@param[in] prio unsigned int32. Priority level @ref dma_st_pri.
+*/
+
+void dma_set_priority(u32 dma, u8 stream, u32 prio)
+{
+ DMA_SCR(dma, stream) &= ~(DMA_SCR_PL_MASK);
+ DMA_SCR(dma, stream) |= prio;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief DMA Stream Set Memory Word Width
+
+Set the memory word width 8 bits, 16 bits, or 32 bits. Refer to datasheet for
+alignment information if the source and destination widths do not match.
+
+Ensure that the stream is disabled otherwise the setting will not be changed.
+
+@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
+@param[in] stream unsigned int8. Stream number: @ref dma_st_number
+@param[in] mem_size unsigned int32. Memory word width @ref dma_st_memwidth.
+*/
+
+void dma_set_memory_size(u32 dma, u8 stream, u32 mem_size)
+{
+
+ DMA_SCR(dma, stream) &= ~(DMA_SCR_MSIZE_MASK);
+ DMA_SCR(dma, stream) |= mem_size;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief DMA Stream Set Peripheral Word Width
+
+Set the peripheral word width 8 bits, 16 bits, or 32 bits. Refer to datasheet for
+alignment information if the source and destination widths do not match, or
+if the peripheral does not support byte or half-word writes.
+
+Ensure that the stream is disabled otherwise the setting will not be changed.
+
+@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
+@param[in] stream unsigned int8. Stream number: @ref dma_st_number
+@param[in] peripheral_size unsigned int32. Peripheral word width @ref dma_st_perwidth.
+*/
+
+void dma_set_peripheral_size(u32 dma, u8 stream, u32 peripheral_size)
+{
+ DMA_SCR(dma, stream) &= ~(DMA_SCR_PSIZE_MASK);
+ DMA_SCR(dma, stream) |= peripheral_size;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief DMA Stream Enable Memory Increment after Transfer
+
+Following each transfer the current memory address is incremented by
+1, 2 or 4 depending on the data size set in @ref dma_set_memory_size. The
+value held by the base memory address register is unchanged.
+
+Ensure that the stream is disabled otherwise the setting will not be changed.
+
+@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
+@param[in] stream unsigned int8. Stream number: @ref dma_st_number
+*/
+
+void dma_enable_memory_increment_mode(u32 dma, u8 stream)
+{
+ DMA_SCR(dma, stream) |= DMA_SCR_MINC;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief DMA Channel Disable Memory Increment after Transfer
+
+Ensure that the stream is disabled otherwise the setting will not be changed.
+
+@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
+@param[in] stream unsigned int8. Stream number: @ref dma_st_number
+*/
+
+void dma_disable_memory_increment_mode(u32 dma, u8 stream)
+{
+ DMA_SCR(dma, stream) &= ~DMA_SCR_MINC;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief DMA Channel Enable Variable Sized Peripheral Increment after Transfer
+
+Following each transfer the current peripheral address is incremented by
+1, 2 or 4 depending on the data size set in @ref dma_set_peripheral_size. The
+value held by the base peripheral address register is unchanged.
+
+Ensure that the stream is disabled otherwise the setting will not be changed.
+
+@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
+@param[in] stream unsigned int8. Stream number: @ref dma_st_number
+*/
+
+void dma_enable_peripheral_increment_mode(u32 dma, u8 stream)
+{
+ u32 reg32 = (DMA_SCR(dma, stream) | DMA_SCR_PINC);
+ DMA_SCR(dma, stream) = (reg32 & ~DMA_SCR_PINCOS);
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief DMA Channel Disable Peripheral Increment after Transfer
+
+Ensure that the stream is disabled otherwise the setting will not be changed.
+
+@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
+@param[in] stream unsigned int8. Stream number: @ref dma_st_number
+*/
+
+void dma_disable_peripheral_increment_mode(u32 dma, u8 stream)
+{
+ DMA_SCR(dma, stream) &= ~DMA_SCR_PINC;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief DMA Channel Enable Fixed Sized Peripheral Increment after Transfer
+
+Following each transfer the current peripheral address is incremented by
+4 regardless of the data size. The value held by the base peripheral address
+register is unchanged.
+
+Ensure that the stream is disabled otherwise the setting will not be changed.
+
+@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
+@param[in] stream unsigned int8. Stream number: @ref dma_st_number
+*/
+
+void dma_enable_fixed_peripheral_increment_mode(u32 dma, u8 stream)
+{
+ DMA_SCR(dma, stream) |= (DMA_SCR_PINC | DMA_SCR_PINCOS);
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief DMA Stream Enable Memory Circular Mode
+
+After the number of bytes/words to be transferred has been completed, the
+original transfer block size, memory and peripheral base addresses are
+reloaded and the process repeats.
+
+Ensure that the stream is disabled otherwise the setting will not be changed.
+
+@note This cannot be used with memory to memory mode. It is disabled
+automatically if the peripheral is selected as the flow controller.
+It is enabled automatically if double buffered mode is selected.
+
+@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
+@param[in] stream unsigned int8. Stream number: @ref dma_st_number
+*/
+
+void dma_enable_circular_mode(u32 dma, u8 stream)
+{
+ DMA_SCR(dma, stream) |= DMA_SCR_CIRC;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief DMA Stream Channel Select
+
+Associate an input channel to the stream. Not every channel is allocated to a
+hardware DMA request signal. The allocations for each stream are given in the
+STM32F4 Reference Manual.
+
+Ensure that the stream is disabled otherwise the setting will not be changed.
+
+@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
+@param[in] stream unsigned int8. Stream number: @ref dma_st_number
+@param[in] channel unsigned int8. Channel selection @ref dma_ch_sel
+*/
+
+void dma_channel_select(u32 dma, u8 stream, u32 channel)
+{
+ DMA_SCR(dma, stream) |= channel;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief DMA Stream Set Memory Burst Configuration
+
+Set the memory burst type to none, 4 8 or 16 word length. This is forced to none
+if direct mode is used.
+
+Ensure that the stream is disabled otherwise the setting will not be changed.
+
+@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
+@param[in] stream unsigned int8. Stream number: @ref dma_st_number
+@param[in] burst unsigned int8. Memory Burst selection @ref dma_mburst
+*/
+
+void dma_set_memory_burst(u32 dma, u8 stream, u32 burst)
+{
+ u32 reg32 = (DMA_SCR(dma, stream) & ~DMA_SCR_MBURST_MASK);
+ DMA_SCR(dma, stream) = (reg32 | burst);
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief DMA Stream Set Peripheral Burst Configuration
+
+Set the memory burst type to none, 4 8 or 16 word length. This is forced to none
+if direct mode is used.
+
+Ensure that the stream is disabled otherwise the setting will not be changed.
+
+@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
+@param[in] stream unsigned int8. Stream number: @ref dma_st_number
+@param[in] burst unsigned int8. Peripheral Burst selection @ref dma_pburst
+*/
+
+void dma_set_peripheral_burst(u32 dma, u8 stream, u32 burst)
+{
+ u32 reg32 = (DMA_SCR(dma, stream) & ~DMA_SCR_PBURST_MASK);
+ DMA_SCR(dma, stream) = (reg32 | burst);
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief DMA Stream Set Initial Target Memory
+
+In double buffered mode, set the target memory (M0 or M1) to be used for the first
+transfer.
+
+Ensure that the stream is disabled otherwise the setting will not be changed.
+
+@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
+@param[in] stream unsigned int8. Stream number: @ref dma_st_number
+@param[in] memory unsigned int8. Initial memory pointer to use: 0 or 1
+*/
+
+void dma_set_initial_target(u32 dma, u8 stream, u8 memory)
+{
+ u32 reg32 = (DMA_SCR(dma, stream) & ~DMA_SCR_CT);
+ if (memory == 1) reg32 |= DMA_SCR_CT;
+ DMA_SCR(dma, stream) = reg32;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief DMA Stream Read Current Memory Target
+
+In double buffer mode, return the current memory target (M0 or M1). It is possible
+to update the memory pointer in the register that is <b> not </b> currently in
+use. An attempt to change the register currently in use will cause the stream
+to be disabled and the transfer error flag to be set.
+
+@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
+@param[in] stream unsigned int8. Stream number: @ref dma_st_number
+@returns unsigned int8. Memory buffer in use: 0 or 1
+*/
+
+u8 dma_get_target(u32 dma, u8 stream)
+{
+ if (DMA_SCR(dma, stream) & DMA_SCR_CT) return 1;
+ return 0;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief DMA Stream Enable Double Buffer Mode
+
+Double buffer mode is used for memory to/from peripheral transfers only, and in
+circular mode which is automatically enabled. Two memory buffers must be
+established with pointers stored in the memory pointer registers.
+
+Ensure that the stream is disabled otherwise the setting will not be changed.
+
+@note This cannot be used with memory to memory mode.
+
+@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
+@param[in] stream unsigned int8. Stream number: @ref dma_st_number
+*/
+
+void dma_enable_double_buffer_mode(u32 dma, u8 stream)
+{
+ DMA_SCR(dma, stream) |= DMA_SCR_DBM;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief DMA Stream Set Peripheral Flow Control
+
+Set the peripheral to control DMA flow. Useful when the number of transfers is
+unknown. This is forced off when memory to memory mode is selected.
+
+Ensure that the stream is disabled otherwise the setting will not be changed.
+
+@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
+@param[in] stream unsigned int8. Stream number: @ref dma_st_number
+*/
+
+void dma_set_peripheral_flow_control(u32 dma, u8 stream)
+{
+ DMA_SCR(dma, stream) |= DMA_SCR_PFCTRL;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief DMA Stream Set DMA Flow Control
+
+Set the DMA controller to control DMA flow. This is the default.
+
+Ensure that the stream is disabled otherwise the setting will not be changed.
+
+@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
+@param[in] stream unsigned int8. Stream number: @ref dma_st_number
+*/
+
+void dma_set_dma_flow_control(u32 dma, u8 stream)
+{
+ DMA_SCR(dma, stream) &= ~DMA_SCR_PFCTRL;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief DMA Stream Enable Interrupt on Transfer Error
+
+@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
+@param[in] stream unsigned int8. Stream number: @ref dma_st_number
+*/
+
+void dma_enable_transfer_error_interrupt(u32 dma, u8 stream)
+{
+ dma_clear_interrupt_flags(dma, stream, DMA_ISR_TEIF);
+ DMA_SCR(dma, stream) |= DMA_SCR_TEIE;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief DMA Stream Disable Interrupt on Transfer Error
+
+@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
+@param[in] stream unsigned int8. Stream number: @ref dma_st_number
+*/
+
+void dma_disable_transfer_error_interrupt(u32 dma, u8 stream)
+{
+ DMA_SCR(dma, stream) &= ~DMA_SCR_TEIE;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief DMA Stream Enable Interrupt on Transfer Half Complete
+
+@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
+@param[in] stream unsigned int8. Stream number: @ref dma_st_number
+*/
+
+void dma_enable_half_transfer_interrupt(u32 dma, u8 stream)
+{
+ dma_clear_interrupt_flags(dma, stream, DMA_ISR_HTIF);
+ DMA_SCR(dma, stream) |= DMA_SCR_HTIE;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief DMA Stream Disable Interrupt on Transfer Half Complete
+
+@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
+@param[in] stream unsigned int8. Stream number: @ref dma_st_number
+*/
+
+void dma_disable_half_transfer_interrupt(u32 dma, u8 stream)
+{
+ DMA_SCR(dma, stream) &= ~DMA_SCR_HTIE;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief DMA Stream Enable Interrupt on Transfer Complete
+
+@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
+@param[in] stream unsigned int8. Stream number: @ref dma_st_number
+*/
+
+void dma_enable_transfer_complete_interrupt(u32 dma, u8 stream)
+{
+ dma_clear_interrupt_flags(dma, stream, DMA_ISR_TCIF);
+ DMA_SCR(dma, stream) |= DMA_SCR_TCIE;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief DMA Stream Disable Interrupt on Transfer Complete
+
+@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
+@param[in] stream unsigned int8. Stream number: @ref dma_st_number
+*/
+
+void dma_disable_transfer_complete_interrupt(u32 dma, u8 stream)
+{
+ DMA_SCR(dma, stream) &= ~DMA_SCR_TCIE;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief DMA Stream Enable Interrupt on Direct Mode Error
+
+@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
+@param[in] stream unsigned int8. Stream number: @ref dma_st_number
+*/
+
+void dma_enable_direct_mode_error_interrupt(u32 dma, u8 stream)
+{
+ dma_clear_interrupt_flags(dma, stream, DMA_ISR_DMEIF);
+ DMA_SCR(dma, stream) |= DMA_SCR_DMEIE;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief DMA Stream Disable Interrupt on Direct Mode Error
+
+@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
+@param[in] stream unsigned int8. Stream number: @ref dma_st_number
+*/
+
+void dma_disable_direct_mode_error_interrupt(u32 dma, u8 stream)
+{
+ DMA_SCR(dma, stream) &= ~DMA_SCR_DMEIE;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief DMA Enable Interrupt on FIFO Error
+
+@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
+@param[in] stream unsigned int8. Stream number: @ref dma_st_number
+*/
+
+void dma_enable_fifo_error_interrupt(u32 dma, u8 stream)
+{
+ dma_clear_interrupt_flags(dma, stream, DMA_ISR_FEIF);
+ DMA_SFCR(dma, stream) |= DMA_FCR_FEIE;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief DMA Disable Interrupt on FIFO Error
+
+@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
+@param[in] stream unsigned int8. Stream number: @ref dma_st_number
+*/
+
+void dma_disable_fifo_error_interrupt(u32 dma, u8 stream)
+{
+ DMA_SFCR(dma, stream) &= ~DMA_FCR_FEIE;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief DMA Get FIFO Status
+
+Status of FIFO (empty. full or partial filled states) is returned. This has no
+meaning if direct mode is enabled (as the FIFO is not used).
+
+@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
+@param[in] stream unsigned int8. Stream number: @ref dma_st_number
+@returns u32 FIFO Status @ref dma_fifo_status
+*/
+
+u32 dma_fifo_status(u32 dma, u8 stream)
+{
+ return (DMA_SFCR(dma, stream) & DMA_FCR_FS_MASK);
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief DMA Enable Direct Mode
+
+Direct mode is the default. Data is transferred as soon as a DMA request is
+received. The FIFO is not used. This must not be set when memory to memory
+mode is selected.
+
+@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
+@param[in] stream unsigned int8. Stream number: @ref dma_st_number
+*/
+
+void dma_enable_direct_mode(u32 dma, u8 stream)
+{
+ DMA_SFCR(dma, stream) &= ~DMA_FCR_DMDIS;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief DMA Enable FIFO Mode
+
+Data is transferred via a FIFO.
+
+@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
+@param[in] stream unsigned int8. Stream number: @ref dma_st_number
+*/
+
+void dma_enable_fifo_mode(u32 dma, u8 stream)
+{
+ DMA_SFCR(dma, stream) |= DMA_FCR_DMDIS;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief DMA Set FIFO Threshold
+
+This is the filled level at which data is transferred out of the FIFO to the
+destination.
+
+@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
+@param[in] stream unsigned int8. Stream number: @ref dma_st_number
+@param[in] threshold unsigned int8. Threshold setting @ref dma_fifo_thresh
+*/
+
+void dma_set_fifo_threshold(u32 dma, u8 stream, u32 threshold)
+{
+ u32 reg32 = (DMA_SFCR(dma, stream) & ~DMA_FCR_FTH_MASK);
+ DMA_SFCR(dma, stream) = (reg32 | threshold);
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief DMA Stream Enable
+
+@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
+@param[in] stream unsigned int8. Stream number: @ref dma_st_number
+*/
+
+void dma_enable_stream(u32 dma, u8 stream)
+{
+ DMA_SCR(dma, stream) |= DMA_SCR_EN;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief DMA Stream Disable
+
+@note The DMA stream registers retain their values when the stream is disabled.
+
+@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
+@param[in] stream unsigned int8. Stream number: @ref dma_st_number
+*/
+
+void dma_disable_stream(u32 dma, u8 stream)
+{
+ DMA_SCR(dma, stream) &= ~DMA_SCR_EN;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief DMA Stream Set the Peripheral Address
+
+Set the address of the peripheral register to or from which data is to be transferred.
+Refer to the documentation for the specific peripheral.
+
+@note The DMA stream must be disabled before setting this address. This function
+has no effect if the stream is enabled.
+
+@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
+@param[in] stream unsigned int8. Stream number: @ref dma_st_number
+@param[in] address unsigned int32. Peripheral Address.
+*/
+
+void dma_set_peripheral_address(u32 dma, u8 stream, u32 address)
+{
+ if (!(DMA_SCR(dma, stream) & DMA_SCR_EN))
+ DMA_SPAR(dma, stream) = (u32) address;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief DMA Stream Set the Base Memory Address 0
+
+Set the address pointer to the memory location for DMA transfers. The DMA stream
+must normally be disabled before setting this address, however it is possible
+to change this in double buffer mode when the current target is memory area 1
+(see @ref dma_get_target).
+
+This is the default base memory address used in direct mode.
+
+@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
+@param[in] stream unsigned int8. Stream number: @ref dma_st_number
+@param[in] address unsigned int32. Memory Initial Address.
+*/
+
+void dma_set_memory_address(u32 dma, u8 stream, u32 address)
+{
+ u32 reg32 = DMA_SCR(dma, stream);
+ if ( !(reg32 & DMA_SCR_EN) || ((reg32 & DMA_SCR_CT) && (reg32 & DMA_SCR_DBM)) )
+ DMA_SM0AR(dma, stream) = (u32) address;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief DMA Stream Set the Base Memory Address 1
+
+Set the address pointer to the memory location for DMA transfers. The DMA stream
+must normally be disabled before setting this address, however it is possible
+to change this in double buffer mode when the current target is memory area 0
+(see @ref dma_get_target).
+
+@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
+@param[in] stream unsigned int8. Stream number: @ref dma_st_number
+@param[in] address unsigned int32. Memory Initial Address.
+*/
+
+void dma_set_memory_address_1(u32 dma, u8 stream, u32 address)
+{
+ u32 reg32 = DMA_SCR(dma, stream);
+ if ( !(reg32 & DMA_SCR_EN) || (!(reg32 & DMA_SCR_CT) && (reg32 & DMA_SCR_DBM)) )
+ DMA_SM1AR(dma, stream) = (u32) address;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief DMA Stream Set the Transfer Block Size
+
+@note The DMA stream must be disabled before setting this count value. The count
+is not changed if the stream is enabled.
+
+@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
+@param[in] stream unsigned int8. Stream number: @ref dma_st_number
+@param[in] number unsigned int16. Number of data words to transfer (65535 maximum).
+*/
+
+void dma_set_number_of_data(u32 dma, u8 stream, u16 number)
+{
+ DMA_SNDTR(dma, stream) = number;
+}
+/**@}*/
+
diff --git a/lib/stm32/f4/exti.c b/lib/stm32/f4/exti.c
deleted file mode 100644
index 155c21f..0000000
--- a/lib/stm32/f4/exti.c
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * This file is part of the libopencm3 project.
- *
- * Copyright (C) 2010 Mark Butler <mbutler@physics.otago.ac.nz>
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <libopencm3/stm32/exti.h>
-#include <libopencm3/stm32/f4/syscfg.h>
-#include <libopencm3/stm32/f4/gpio.h>
-
-void exti_set_trigger(u32 extis, exti_trigger_type trig)
-{
- switch (trig) {
- case EXTI_TRIGGER_RISING:
- EXTI_RTSR |= extis;
- EXTI_FTSR &= ~extis;
- break;
- case EXTI_TRIGGER_FALLING:
- EXTI_RTSR &= ~extis;
- EXTI_FTSR |= extis;
- break;
- case EXTI_TRIGGER_BOTH:
- EXTI_RTSR |= extis;
- EXTI_FTSR |= extis;
- break;
- }
-}
-
-void exti_enable_request(u32 extis)
-{
- /* Enable interrupts. */
- EXTI_IMR |= extis;
-
- /* Enable events. */
- EXTI_EMR |= extis;
-}
-
-void exti_disable_request(u32 extis)
-{
- /* Disable interrupts. */
- EXTI_IMR &= ~extis;
-
- /* Disable events. */
- EXTI_EMR &= ~extis;
-}
-
-/*
- * Reset the interrupt request by writing a 1 to the corresponding
- * pending bit register.
- */
-void exti_reset_request(u32 extis)
-{
- EXTI_PR = extis;
-}
-
-/*
- * Remap an external interrupt line to the corresponding pin on the
- * specified GPIO port.
- *
- * TODO: This could be rewritten in fewer lines of code.
- */
-void exti_select_source(u32 exti, u32 gpioport)
-{
- u8 shift, bits;
-
- shift = bits = 0;
-
- switch (exti) {
- case EXTI0:
- case EXTI4:
- case EXTI8:
- case EXTI12:
- shift = 0;
- break;
- case EXTI1:
- case EXTI5:
- case EXTI9:
- case EXTI13:
- shift = 4;
- break;
- case EXTI2:
- case EXTI6:
- case EXTI10:
- case EXTI14:
- shift = 8;
- break;
- case EXTI3:
- case EXTI7:
- case EXTI11:
- case EXTI15:
- shift = 12;
- break;
- }
-
- switch (gpioport) {
- case GPIOA:
- bits = 0xf;
- break;
- case GPIOB:
- bits = 0xe;
- break;
- case GPIOC:
- bits = 0xd;
- break;
- case GPIOD:
- bits = 0xc;
- break;
- case GPIOE:
- bits = 0xb;
- break;
- case GPIOF:
- bits = 0xa;
- break;
- case GPIOG:
- bits = 0x9;
- break;
- }
-
- /* Ensure that only valid EXTI lines are used. */
- if (exti < EXTI4) {
- SYSCFG_EXTICR1 &= ~(0x000F << shift);
- SYSCFG_EXTICR1 |= (~bits << shift);
- } else if (exti < EXTI8) {
- SYSCFG_EXTICR2 &= ~(0x000F << shift);
- SYSCFG_EXTICR2 |= (~bits << shift);
- } else if (exti < EXTI12) {
- SYSCFG_EXTICR3 &= ~(0x000F << shift);
- SYSCFG_EXTICR3 |= (~bits << shift);
- } else if (exti < EXTI16) {
- SYSCFG_EXTICR4 &= ~(0x000F << shift);
- SYSCFG_EXTICR4 |= (~bits << shift);
- }
-}
diff --git a/lib/stm32/f4/gpio.c b/lib/stm32/f4/gpio.c
deleted file mode 100644
index 1d7739d..0000000
--- a/lib/stm32/f4/gpio.c
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * This file is part of the libopencm3 project.
- *
- * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <libopencm3/stm32/f4/gpio.h>
-
-void gpio_mode_setup(u32 gpioport, u8 mode, u8 pull_up_down, u16 gpios)
-{
- u16 i;
- u32 moder, pupd;
-
- /*
- * We want to set the config only for the pins mentioned in gpios,
- * but keeping the others, so read out the actual config first.
- */
- moder = GPIO_MODER(gpioport);
- pupd = GPIO_PUPDR(gpioport);
-
- for (i = 0; i < 16; i++) {
- if (!((1 << i) & gpios))
- continue;
-
- moder &= ~GPIO_MODE_MASK(i);
- moder |= GPIO_MODE(i, mode);
- pupd &= ~GPIO_PUPD_MASK(i);
- pupd |= GPIO_PUPD(i, pull_up_down);
- }
-
- /* Set mode and pull up/down control registers. */
- GPIO_MODER(gpioport) = moder;
- GPIO_PUPDR(gpioport) = pupd;
-}
-
-void gpio_set_output_options(u32 gpioport, u8 otype, u8 speed, u16 gpios)
-{
- u16 i;
- u32 ospeedr;
-
- if (otype == 0x1)
- GPIO_OTYPER(gpioport) |= gpios;
- else
- GPIO_OTYPER(gpioport) &= ~gpios;
-
- ospeedr = GPIO_OSPEEDR(gpioport);
-
- for (i = 0; i < 16; i++) {
- if (!((1 << i) & gpios))
- continue;
- ospeedr &= ~GPIO_OSPEED_MASK(i);
- ospeedr |= GPIO_OSPEED(i, speed);
- }
-
- GPIO_OSPEEDR(gpioport) = ospeedr;
-}
-
-void gpio_set_af(u32 gpioport, u8 alt_func_num, u16 gpios)
-{
- u16 i;
- u32 afrl, afrh;
-
- afrl = GPIO_AFRL(gpioport);
- afrh = GPIO_AFRH(gpioport);
-
- for (i = 0; i < 8; i++) {
- if (!((1 << i) & gpios))
- continue;
- afrl &= ~GPIO_AFR_MASK(i);
- afrl |= GPIO_AFR(i, alt_func_num);
- }
-
- for (i = 8; i < 16; i++) {
- if (!((1 << i) & gpios))
- continue;
- afrl &= ~GPIO_AFR_MASK(i - 8);
- afrh |= GPIO_AFR(i - 8, alt_func_num);
- }
-
- GPIO_AFRL(gpioport) = afrl;
- GPIO_AFRH(gpioport) = afrh;
-}
-
-void gpio_set(u32 gpioport, u16 gpios)
-{
- GPIO_BSRR(gpioport) = gpios;
-}
-
-void gpio_clear(u32 gpioport, u16 gpios)
-{
- GPIO_BSRR(gpioport) = gpios << 16;
-}
-
-u16 gpio_get(u32 gpioport, u16 gpios)
-{
- return gpio_port_read(gpioport) & gpios;
-}
-
-void gpio_toggle(u32 gpioport, u16 gpios)
-{
- GPIO_ODR(gpioport) ^= gpios;
-}
-
-u16 gpio_port_read(u32 gpioport)
-{
- return (u16)GPIO_IDR(gpioport);
-}
-
-void gpio_port_write(u32 gpioport, u16 data)
-{
- GPIO_ODR(gpioport) = data;
-}
-
-void gpio_port_config_lock(u32 gpioport, u16 gpios)
-{
- u32 reg32;
-
- /* Special "Lock Key Writing Sequence", see datasheet. */
- GPIO_LCKR(gpioport) = GPIO_LCKK | gpios; /* Set LCKK. */
- GPIO_LCKR(gpioport) = ~GPIO_LCKK & gpios; /* Clear LCKK. */
- GPIO_LCKR(gpioport) = GPIO_LCKK | gpios; /* Set LCKK. */
- reg32 = GPIO_LCKR(gpioport); /* Read LCKK. */
- reg32 = GPIO_LCKR(gpioport); /* Read LCKK again. */
-
- /* Tell the compiler the variable is actually used. It will get optimized out anyways. */
- reg32 = reg32;
-
- /* If (reg32 & GPIO_LCKK) is true, the lock is now active. */
-}
diff --git a/lib/stm32/f4/timer.c b/lib/stm32/f4/timer.c
deleted file mode 100644
index 6d5ab9d..0000000
--- a/lib/stm32/f4/timer.c
+++ /dev/null
@@ -1,928 +0,0 @@
-/*
- * This file is part of the libopencm3 project.
- *
- * Copyright (C) 2010 Edward Cheeseman <evbuilder@users.sourceforge.org>
- * Copyright (C) 2011 Stephen Caudle <scaudle@doceme.com>
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library. If not, see <http://www.gnu.org/licenses/>.
- */
-
-/*
- * Basic TIMER handling API.
- *
- * Examples:
- * timer_set_mode(TIM1, TIM_CR1_CKD_CK_INT_MUL_2,
- * TIM_CR1_CMS_CENTRE_3, TIM_CR1_DIR_UP);
- */
-
-#include <libopencm3/stm32/f4/timer.h>
-#include <libopencm3/stm32/f4/rcc.h>
-
-void timer_reset(u32 timer_peripheral)
-{
- switch (timer_peripheral) {
- case TIM1:
- rcc_peripheral_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM1RST);
- rcc_peripheral_clear_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM1RST);
- break;
- case TIM2:
- rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM2RST);
- rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM2RST);
- break;
- case TIM3:
- rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM3RST);
- rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM3RST);
- break;
- case TIM4:
- rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM4RST);
- rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM4RST);
- break;
- case TIM5:
- rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM5RST);
- rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM5RST);
- break;
- case TIM6:
- rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM6RST);
- rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM6RST);
- break;
- case TIM7:
- rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM7RST);
- rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM7RST);
- break;
- case TIM8:
- rcc_peripheral_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM8RST);
- rcc_peripheral_clear_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM8RST);
- break;
-/* These timers are not supported in libopencm3 yet */
-/*
- case TIM9:
- rcc_peripheral_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM9RST);
- rcc_peripheral_clear_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM9RST);
- break;
- case TIM10:
- rcc_peripheral_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM10RST);
- rcc_peripheral_clear_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM10RST);
- break;
- case TIM11:
- rcc_peripheral_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM11RST);
- rcc_peripheral_clear_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM11RST);
- break;
- case TIM12:
- rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM12RST);
- rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM12RST);
- break;
- case TIM13:
- rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM13RST);
- rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM13RST);
- break;
- case TIM14:
- rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM14RST);
- rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM14RST);
- break;
-*/
- }
-}
-
-void timer_enable_irq(u32 timer_peripheral, u32 irq)
-{
- TIM_DIER(timer_peripheral) |= irq;
-}
-
-void timer_disable_irq(u32 timer_peripheral, u32 irq)
-{
- TIM_DIER(timer_peripheral) &= ~irq;
-}
-
-bool timer_get_flag(u32 timer_peripheral, u32 flag)
-{
- if (((TIM_SR(timer_peripheral) & flag) != 0) &&
- ((TIM_DIER(timer_peripheral) & flag) != 0)) {
- return true;
- }
-
- return false;
-}
-
-void timer_clear_flag(u32 timer_peripheral, u32 flag)
-{
- TIM_SR(timer_peripheral) &= ~flag;
-}
-
-void timer_set_mode(u32 timer_peripheral, u32 clock_div,
- u32 alignment, u32 direction)
-{
- u32 cr1;
-
- cr1 = TIM_CR1(timer_peripheral);
-
- cr1 &= ~(TIM_CR1_CKD_CK_INT_MASK | TIM_CR1_CMS_MASK | TIM_CR1_DIR_DOWN);
-
- cr1 |= clock_div | alignment | direction;
-
- TIM_CR1(timer_peripheral) = cr1;
-}
-
-void timer_set_clock_division(u32 timer_peripheral, u32 clock_div)
-{
- clock_div &= TIM_CR1_CKD_CK_INT_MASK;
- TIM_CR1(timer_peripheral) &= ~TIM_CR1_CKD_CK_INT_MASK;
- TIM_CR1(timer_peripheral) |= clock_div;
-}
-
-void timer_enable_preload(u32 timer_peripheral)
-{
- TIM_CR1(timer_peripheral) |= TIM_CR1_ARPE;
-}
-
-void timer_disable_preload(u32 timer_peripheral)
-{
- TIM_CR1(timer_peripheral) &= ~TIM_CR1_ARPE;
-}
-
-void timer_set_alignment(u32 timer_peripheral, u32 alignment)
-{
- alignment &= TIM_CR1_CMS_MASK;
- TIM_CR1(timer_peripheral) &= ~TIM_CR1_CMS_MASK;
- TIM_CR1(timer_peripheral) |= alignment;
-}
-
-void timer_direction_up(u32 timer_peripheral)
-{
- TIM_CR1(timer_peripheral) &= ~TIM_CR1_DIR_DOWN;
-}
-
-void timer_direction_down(u32 timer_peripheral)
-{
- TIM_CR1(timer_peripheral) |= TIM_CR1_DIR_DOWN;
-}
-
-void timer_one_shot_mode(u32 timer_peripheral)
-{
- TIM_CR1(timer_peripheral) |= TIM_CR1_OPM;
-}
-
-void timer_continuous_mode(u32 timer_peripheral)
-{
- TIM_CR1(timer_peripheral) &= ~TIM_CR1_OPM;
-}
-
-void timer_update_on_any(u32 timer_peripheral)
-{
- TIM_CR1(timer_peripheral) &= ~TIM_CR1_URS;
-}
-
-void timer_update_on_overflow(u32 timer_peripheral)
-{
- TIM_CR1(timer_peripheral) |= TIM_CR1_URS;
-}
-
-void timer_enable_update_event(u32 timer_peripheral)
-{
- TIM_CR1(timer_peripheral) &= ~TIM_CR1_UDIS;
-}
-
-void timer_disable_update_event(u32 timer_peripheral)
-{
- TIM_CR1(timer_peripheral) |= TIM_CR1_UDIS;
-}
-
-void timer_enable_counter(u32 timer_peripheral)
-{
- TIM_CR1(timer_peripheral) |= TIM_CR1_CEN;
-}
-
-void timer_disable_counter(u32 timer_peripheral)
-{
- TIM_CR1(timer_peripheral) &= ~TIM_CR1_CEN;
-}
-
-void timer_set_output_idle_state(u32 timer_peripheral, u32 outputs)
-{
- TIM_CR2(timer_peripheral) |= outputs & TIM_CR2_OIS_MASK;
-}
-
-void timer_reset_output_idle_state(u32 timer_peripheral, u32 outputs)
-{
- TIM_CR2(timer_peripheral) &= ~(outputs & TIM_CR2_OIS_MASK);
-}
-
-void timer_set_ti1_ch123_xor(u32 timer_peripheral)
-{
- TIM_CR2(timer_peripheral) |= TIM_CR2_TI1S;
-}
-
-void timer_set_ti1_ch1(u32 timer_peripheral)
-{
- TIM_CR2(timer_peripheral) &= ~TIM_CR2_TI1S;
-}
-
-void timer_set_master_mode(u32 timer_peripheral, u32 mode)
-{
- TIM_CR2(timer_peripheral) &= ~TIM_CR2_MMS_MASK;
- TIM_CR2(timer_peripheral) |= mode;
-}
-
-void timer_set_dma_on_compare_event(u32 timer_peripheral)
-{
- TIM_CR2(timer_peripheral) &= ~TIM_CR2_CCDS;
-}
-
-void timer_set_dma_on_update_event(u32 timer_peripheral)
-{
- TIM_CR2(timer_peripheral) |= TIM_CR2_CCDS;
-}
-
-void timer_enable_compare_control_update_on_trigger(u32 timer_peripheral)
-{
- TIM_CR2(timer_peripheral) |= TIM_CR2_CCUS;
-}
-
-void timer_disable_compare_control_update_on_trigger(u32 timer_peripheral)
-{
- TIM_CR2(timer_peripheral) &= ~TIM_CR2_CCUS;
-}
-
-void timer_enable_preload_complementry_enable_bits(u32 timer_peripheral)
-{
- TIM_CR2(timer_peripheral) |= TIM_CR2_CCPC;
-}
-
-void timer_disable_preload_complementry_enable_bits(u32 timer_peripheral)
-{
- TIM_CR2(timer_peripheral) &= ~TIM_CR2_CCPC;
-}
-
-void timer_set_prescaler(u32 timer_peripheral, u32 value)
-{
- TIM_PSC(timer_peripheral) = value;
-}
-
-void timer_set_repetition_counter(u32 timer_peripheral, u32 value)
-{
- if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
- TIM_RCR(timer_peripheral) = value;
-}
-
-void timer_set_period(u32 timer_peripheral, u32 period)
-{
- TIM_ARR(timer_peripheral) = period;
-}
-
-void timer_enable_oc_clear(u32 timer_peripheral, enum tim_oc_id oc_id)
-{
- switch (oc_id) {
- case TIM_OC1:
- TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1CE;
- break;
- case TIM_OC2:
- TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2CE;
- break;
- case TIM_OC3:
- TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3CE;
- break;
- case TIM_OC4:
- TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4CE;
- break;
- case TIM_OC1N:
- case TIM_OC2N:
- case TIM_OC3N:
- /* Ignoring as fast enable only applies to the whole channel. */
- break;
- }
-}
-
-void timer_disable_oc_clear(u32 timer_peripheral, enum tim_oc_id oc_id)
-{
- switch (oc_id) {
- case TIM_OC1:
- TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC1CE;
- break;
- case TIM_OC2:
- TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC2CE;
- break;
- case TIM_OC3:
- TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC3CE;
- break;
- case TIM_OC4:
- TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC4CE;
- break;
- case TIM_OC1N:
- case TIM_OC2N:
- case TIM_OC3N:
- /* Ignoring as fast enable only applies to the whole channel. */
- break;
- }
-}
-
-void timer_set_oc_fast_mode(u32 timer_peripheral, enum tim_oc_id oc_id)
-{
- switch (oc_id) {
- case TIM_OC1:
- TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1FE;
- break;
- case TIM_OC2:
- TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2FE;
- break;
- case TIM_OC3:
- TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3FE;
- break;
- case TIM_OC4:
- TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4FE;
- break;
- case TIM_OC1N:
- case TIM_OC2N:
- case TIM_OC3N:
- /* Ignoring as fast enable only applies to the whole channel. */
- break;
- }
-}
-
-void timer_set_oc_slow_mode(u32 timer_peripheral, enum tim_oc_id oc_id)
-{
- switch (oc_id) {
- case TIM_OC1:
- TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC1FE;
- break;
- case TIM_OC2:
- TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC2FE;
- break;
- case TIM_OC3:
- TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC3FE;
- break;
- case TIM_OC4:
- TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC4FE;
- break;
- case TIM_OC1N:
- case TIM_OC2N:
- case TIM_OC3N:
- /* Ignoring as this option applies to the whole channel. */
- break;
- }
-}
-
-void timer_set_oc_mode(u32 timer_peripheral, enum tim_oc_id oc_id,
- enum tim_oc_mode oc_mode)
-{
- switch (oc_id) {
- case TIM_OC1:
- TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_CC1S_MASK;
- TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_CC1S_OUT;
- TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC1M_MASK;
- switch (oc_mode) {
- case TIM_OCM_FROZEN:
- TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_FROZEN;
- break;
- case TIM_OCM_ACTIVE:
- TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_ACTIVE;
- break;
- case TIM_OCM_INACTIVE:
- TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_INACTIVE;
- break;
- case TIM_OCM_TOGGLE:
- TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_TOGGLE;
- break;
- case TIM_OCM_FORCE_LOW:
- TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_FORCE_LOW;
- break;
- case TIM_OCM_FORCE_HIGH:
- TIM_CCMR1(timer_peripheral) |=
- TIM_CCMR1_OC1M_FORCE_HIGH;
- break;
- case TIM_OCM_PWM1:
- TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_PWM1;
- break;
- case TIM_OCM_PWM2:
- TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_PWM2;
- break;
- }
- break;
- case TIM_OC2:
- TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_CC2S_MASK;
- TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_CC2S_OUT;
- TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC2M_MASK;
- switch (oc_mode) {
- case TIM_OCM_FROZEN:
- TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_FROZEN;
- break;
- case TIM_OCM_ACTIVE:
- TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_ACTIVE;
- break;
- case TIM_OCM_INACTIVE:
- TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_INACTIVE;
- break;
- case TIM_OCM_TOGGLE:
- TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_TOGGLE;
- break;
- case TIM_OCM_FORCE_LOW:
- TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_FORCE_LOW;
- break;
- case TIM_OCM_FORCE_HIGH:
- TIM_CCMR1(timer_peripheral) |=
- TIM_CCMR1_OC2M_FORCE_HIGH;
- break;
- case TIM_OCM_PWM1:
- TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_PWM1;
- break;
- case TIM_OCM_PWM2:
- TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_PWM2;
- break;
- }
- break;
- case TIM_OC3:
- TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR2_CC3S_MASK;
- TIM_CCMR1(timer_peripheral) |= TIM_CCMR2_CC3S_OUT;
- TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC3M_MASK;
- switch (oc_mode) {
- case TIM_OCM_FROZEN:
- TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_FROZEN;
- break;
- case TIM_OCM_ACTIVE:
- TIM_CCMR1(timer_peripheral) |= TIM_CCMR2_OC3M_ACTIVE;
- break;
- case TIM_OCM_INACTIVE:
- TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_INACTIVE;
- break;
- case TIM_OCM_TOGGLE:
- TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_TOGGLE;
- break;
- case TIM_OCM_FORCE_LOW:
- TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_FORCE_LOW;
- break;
- case TIM_OCM_FORCE_HIGH:
- TIM_CCMR2(timer_peripheral) |=
- TIM_CCMR2_OC3M_FORCE_HIGH;
- break;
- case TIM_OCM_PWM1:
- TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_PWM1;
- break;
- case TIM_OCM_PWM2:
- TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_PWM2;
- break;
- }
- break;
- case TIM_OC4:
- TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR2_CC4S_MASK;
- TIM_CCMR1(timer_peripheral) |= TIM_CCMR2_CC4S_OUT;
- TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC4M_MASK;
- switch (oc_mode) {
- case TIM_OCM_FROZEN:
- TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_FROZEN;
- break;
- case TIM_OCM_ACTIVE:
- TIM_CCMR1(timer_peripheral) |= TIM_CCMR2_OC4M_ACTIVE;
- break;
- case TIM_OCM_INACTIVE:
- TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_INACTIVE;
- break;
- case TIM_OCM_TOGGLE:
- TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_TOGGLE;
- break;
- case TIM_OCM_FORCE_LOW:
- TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_FORCE_LOW;
- break;
- case TIM_OCM_FORCE_HIGH:
- TIM_CCMR2(timer_peripheral) |=
- TIM_CCMR2_OC4M_FORCE_HIGH;
- break;
- case TIM_OCM_PWM1:
- TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_PWM1;
- break;
- case TIM_OCM_PWM2:
- TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_PWM2;
- break;
- }
- break;
- case TIM_OC1N:
- case TIM_OC2N:
- case TIM_OC3N:
- /* Ignoring as this option applies to the whole channel. */
- break;
- }
-}
-
-void timer_enable_oc_preload(u32 timer_peripheral, enum tim_oc_id oc_id)
-{
- switch (oc_id) {
- case TIM_OC1:
- TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1PE;
- break;
- case TIM_OC2:
- TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2PE;
- break;
- case TIM_OC3:
- TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3PE;
- break;
- case TIM_OC4:
- TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4PE;
- break;
- case TIM_OC1N:
- case TIM_OC2N:
- case TIM_OC3N:
- /* Ignoring as this option applies to the whole channel. */
- break;
- }
-}
-
-void timer_disable_oc_preload(u32 timer_peripheral, enum tim_oc_id oc_id)
-{
- switch (oc_id) {
- case TIM_OC1:
- TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC1PE;
- break;
- case TIM_OC2:
- TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC2PE;
- break;
- case TIM_OC3:
- TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC3PE;
- break;
- case TIM_OC4:
- TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC4PE;
- break;
- case TIM_OC1N:
- case TIM_OC2N:
- case TIM_OC3N:
- /* Ignoring as this option applies to the whole channel. */
- break;
- }
-}
-
-void timer_set_oc_polarity_high(u32 timer_peripheral, enum tim_oc_id oc_id)
-{
- switch (oc_id) {
- case TIM_OC1:
- TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC1P;
- break;
- case TIM_OC2:
- TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC2P;
- break;
- case TIM_OC3:
- TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC3P;
- break;
- case TIM_OC4:
- TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC4P;
- break;
- case TIM_OC1N:
- case TIM_OC2N:
- case TIM_OC3N:
- /* Ignoring as this option applies to TIM1 and TIM8 only. */
- break;
- }
-
- /* Acting for TIM1 and TIM8 only from here onwards. */
- if ((timer_peripheral != TIM1) && (timer_peripheral != TIM8))
- return;
-
- switch (oc_id) {
- case TIM_OC1N:
- TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC1NP;
- break;
- case TIM_OC2N:
- TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC2NP;
- break;
- case TIM_OC3N:
- TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC3NP;
- break;
- case TIM_OC1:
- case TIM_OC2:
- case TIM_OC3:
- case TIM_OC4:
- /* Ignoring as this option was already set above. */
- break;
- }
-}
-
-void timer_set_oc_polarity_low(u32 timer_peripheral, enum tim_oc_id oc_id)
-{
- switch (oc_id) {
- case TIM_OC1:
- TIM_CCER(timer_peripheral) |= TIM_CCER_CC1P;
- break;
- case TIM_OC2:
- TIM_CCER(timer_peripheral) |= TIM_CCER_CC2P;
- break;
- case TIM_OC3:
- TIM_CCER(timer_peripheral) |= TIM_CCER_CC3P;
- break;
- case TIM_OC4:
- TIM_CCER(timer_peripheral) |= TIM_CCER_CC4P;
- break;
- case TIM_OC1N:
- case TIM_OC2N:
- case TIM_OC3N:
- /* Ignoring as this option applies to TIM1 and TIM8 only. */
- break;
- }
-
- /* Acting for TIM1 and TIM8 only from here onwards. */
- if ((timer_peripheral != TIM1) && (timer_peripheral != TIM8))
- return;
-
- switch (oc_id) {
- case TIM_OC1N:
- TIM_CCER(timer_peripheral) |= TIM_CCER_CC1NP;
- break;
- case TIM_OC2N:
- TIM_CCER(timer_peripheral) |= TIM_CCER_CC2NP;
- break;
- case TIM_OC3N:
- TIM_CCER(timer_peripheral) |= TIM_CCER_CC3NP;
- break;
- case TIM_OC1:
- case TIM_OC2:
- case TIM_OC3:
- case TIM_OC4:
- /* Ignoring as this option was already set above. */
- break;
- }
-}
-
-void timer_enable_oc_output(u32 timer_peripheral, enum tim_oc_id oc_id)
-{
- switch (oc_id) {
- case TIM_OC1:
- TIM_CCER(timer_peripheral) |= TIM_CCER_CC1E;
- break;
- case TIM_OC2:
- TIM_CCER(timer_peripheral) |= TIM_CCER_CC2E;
- break;
- case TIM_OC3:
- TIM_CCER(timer_peripheral) |= TIM_CCER_CC3E;
- break;
- case TIM_OC4:
- TIM_CCER(timer_peripheral) |= TIM_CCER_CC4E;
- break;
- case TIM_OC1N:
- case TIM_OC2N:
- case TIM_OC3N:
- /* Ignoring as this option applies to TIM1 and TIM8 only. */
- break;
- }
-
- /* Acting for TIM1 and TIM8 only from here onwards. */
- if ((timer_peripheral != TIM1) && (timer_peripheral != TIM8))
- return;
-
- switch (oc_id) {
- case TIM_OC1N:
- TIM_CCER(timer_peripheral) |= TIM_CCER_CC1NE;
- break;
- case TIM_OC2N:
- TIM_CCER(timer_peripheral) |= TIM_CCER_CC2NE;
- break;
- case TIM_OC3N:
- TIM_CCER(timer_peripheral) |= TIM_CCER_CC3NE;
- break;
- case TIM_OC1:
- case TIM_OC2:
- case TIM_OC3:
- case TIM_OC4:
- /* Ignoring as this option was already set above. */
- break;
- }
-}
-
-void timer_disable_oc_output(u32 timer_peripheral, enum tim_oc_id oc_id)
-{
- switch (oc_id) {
- case TIM_OC1:
- TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC1E;
- break;
- case TIM_OC2:
- TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC2E;
- break;
- case TIM_OC3:
- TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC3E;
- break;
- case TIM_OC4:
- TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC4E;
- break;
- case TIM_OC1N:
- case TIM_OC2N:
- case TIM_OC3N:
- /* Ignoring as this option applies to TIM1 and TIM8 only. */
- break;
- }
-
- /* Acting for TIM1 and TIM8 only from here onwards. */
- if ((timer_peripheral != TIM1) && (timer_peripheral != TIM8))
- return;
-
- switch (oc_id) {
- case TIM_OC1N:
- TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC1NE;
- break;
- case TIM_OC2N:
- TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC2NE;
- break;
- case TIM_OC3N:
- TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC3NE;
- break;
- case TIM_OC1:
- case TIM_OC2:
- case TIM_OC3:
- case TIM_OC4:
- /* Ignoring as this option was already set above. */
- break;
- }
-}
-
-void timer_set_oc_idle_state_set(u32 timer_peripheral, enum tim_oc_id oc_id)
-{
- /* Acting for TIM1 and TIM8 only. */
- if ((timer_peripheral != TIM1) && (timer_peripheral != TIM8))
- return;
-
- switch (oc_id) {
- case TIM_OC1:
- TIM_CR2(timer_peripheral) |= TIM_CR2_OIS1;
- break;
- case TIM_OC1N:
- TIM_CR2(timer_peripheral) |= TIM_CR2_OIS1N;
- break;
- case TIM_OC2:
- TIM_CR2(timer_peripheral) |= TIM_CR2_OIS2;
- break;
- case TIM_OC2N:
- TIM_CR2(timer_peripheral) |= TIM_CR2_OIS2N;
- break;
- case TIM_OC3:
- TIM_CR2(timer_peripheral) |= TIM_CR2_OIS3;
- break;
- case TIM_OC3N:
- TIM_CR2(timer_peripheral) |= TIM_CR2_OIS3N;
- break;
- case TIM_OC4:
- TIM_CR2(timer_peripheral) |= TIM_CR2_OIS4;
- break;
- }
-}
-
-void timer_set_oc_idle_state_unset(u32 timer_peripheral, enum tim_oc_id oc_id)
-{
- /* Acting for TIM1 and TIM8 only. */
- if ((timer_peripheral != TIM1) && (timer_peripheral != TIM8))
- return;
-
- switch (oc_id) {
- case TIM_OC1:
- TIM_CR2(timer_peripheral) &= ~TIM_CR2_OIS1;
- break;
- case TIM_OC1N:
- TIM_CR2(timer_peripheral) &= ~TIM_CR2_OIS1N;
- break;
- case TIM_OC2:
- TIM_CR2(timer_peripheral) &= ~TIM_CR2_OIS2;
- break;
- case TIM_OC2N:
- TIM_CR2(timer_peripheral) &= ~TIM_CR2_OIS2N;
- break;
- case TIM_OC3:
- TIM_CR2(timer_peripheral) &= ~TIM_CR2_OIS3;
- break;
- case TIM_OC3N:
- TIM_CR2(timer_peripheral) &= ~TIM_CR2_OIS3N;
- break;
- case TIM_OC4:
- TIM_CR2(timer_peripheral) &= ~TIM_CR2_OIS4;
- break;
- }
-}
-
-void timer_set_oc_value(u32 timer_peripheral, enum tim_oc_id oc_id, u32 value)
-{
- switch (oc_id) {
- case TIM_OC1:
- TIM_CCR1(timer_peripheral) = value;
- break;
- case TIM_OC2:
- TIM_CCR2(timer_peripheral) = value;
- break;
- case TIM_OC3:
- TIM_CCR3(timer_peripheral) = value;
- break;
- case TIM_OC4:
- TIM_CCR4(timer_peripheral) = value;
- break;
- case TIM_OC1N:
- case TIM_OC2N:
- case TIM_OC3N:
- /* Ignoring as this option applies to the whole channel. */
- break;
- }
-}
-
-void timer_enable_break_main_output(u32 timer_peripheral)
-{
- if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
- TIM_BDTR(timer_peripheral) |= TIM_BDTR_MOE;
-}
-
-void timer_disable_break_main_output(u32 timer_peripheral)
-{
- if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
- TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_MOE;
-}
-
-void timer_enable_break_automatic_output(u32 timer_peripheral)
-{
- if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
- TIM_BDTR(timer_peripheral) |= TIM_BDTR_AOE;
-}
-
-void timer_disable_break_automatic_output(u32 timer_peripheral)
-{
- if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
- TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_AOE;
-}
-
-void timer_set_break_polarity_high(u32 timer_peripheral)
-{
- if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
- TIM_BDTR(timer_peripheral) |= TIM_BDTR_BKP;
-}
-
-void timer_set_break_polarity_low(u32 timer_peripheral)
-{
- if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
- TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_BKP;
-}
-
-void timer_enable_break(u32 timer_peripheral)
-{
- if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
- TIM_BDTR(timer_peripheral) |= TIM_BDTR_BKE;
-}
-
-void timer_disable_break(u32 timer_peripheral)
-{
- if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
- TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_BKE;
-}
-
-void timer_set_enabled_off_state_in_run_mode(u32 timer_peripheral)
-{
- if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
- TIM_BDTR(timer_peripheral) |= TIM_BDTR_OSSR;
-}
-
-void timer_set_disabled_off_state_in_run_mode(u32 timer_peripheral)
-{
- if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
- TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_OSSR;
-}
-
-void timer_set_enabled_off_state_in_idle_mode(u32 timer_peripheral)
-{
- if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
- TIM_BDTR(timer_peripheral) |= TIM_BDTR_OSSI;
-}
-
-void timer_set_disabled_off_state_in_idle_mode(u32 timer_peripheral)
-{
- if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
- TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_OSSI;
-}
-
-void timer_set_break_lock(u32 timer_peripheral, u32 lock)
-{
- if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
- TIM_BDTR(timer_peripheral) |= lock;
-}
-
-void timer_set_deadtime(u32 timer_peripheral, u32 deadtime)
-{
- if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
- TIM_BDTR(timer_peripheral) |= deadtime;
-}
-
-void timer_generate_event(u32 timer_peripheral, u32 event)
-{
- TIM_EGR(timer_peripheral) |= event;
-}
-
-u32 timer_get_counter(u32 timer_peripheral)
-{
- return TIM_CNT(timer_peripheral);
-}
-
-void timer_set_option(u32 timer_peripheral, u32 option)
-{
- if (timer_peripheral == TIM2) {
- TIM_OR(timer_peripheral) &= ~TIM2_OR_ITR1_RMP_MASK;
- TIM_OR(timer_peripheral) |= option;
- } else if (timer_peripheral == TIM5) {
- TIM_OR(timer_peripheral) &= ~TIM5_OR_TI4_RMP_MASK;
- TIM_OR(timer_peripheral) |= option;
- }
-}
diff --git a/lib/stm32/f4/vector.c b/lib/stm32/f4/vector.c
deleted file mode 100644
index 01b5e64..0000000
--- a/lib/stm32/f4/vector.c
+++ /dev/null
@@ -1,341 +0,0 @@
-/*
- * This file is part of the libopencm3 project.
- *
- * Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
- * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <libopencm3/stm32/f4/scb.h>
-
-#define WEAK __attribute__ ((weak))
-
-/* Symbols exported by the linker script(s): */
-extern unsigned _data_loadaddr, _data, _edata, _ebss, _stack;
-
-void main(void);
-void reset_handler(void);
-void blocking_handler(void);
-void null_handler(void);
-
-void WEAK reset_handler(void);
-void WEAK nmi_handler(void);
-void WEAK hard_fault_handler(void);
-void WEAK mem_manage_handler(void);
-void WEAK bus_fault_handler(void);
-void WEAK usage_fault_handler(void);
-void WEAK sv_call_handler(void);
-void WEAK debug_monitor_handler(void);
-void WEAK pend_sv_handler(void);
-void WEAK sys_tick_handler(void);
-void WEAK wwdg_isr(void);
-void WEAK pvd_isr(void);
-void WEAK tamp_stamp_isr(void);
-void WEAK rtc_wkup_isr(void);
-void WEAK flash_isr(void);
-void WEAK rcc_isr(void);
-void WEAK exti0_isr(void);
-void WEAK exti1_isr(void);
-void WEAK exti2_isr(void);
-void WEAK exti3_isr(void);
-void WEAK exti4_isr(void);
-void WEAK dma1_stream0_isr(void);
-void WEAK dma1_stream1_isr(void);
-void WEAK dma1_stream2_isr(void);
-void WEAK dma1_stream3_isr(void);
-void WEAK dma1_stream4_isr(void);
-void WEAK dma1_stream5_isr(void);
-void WEAK dma1_stream6_isr(void);
-void WEAK adc_isr(void);
-void WEAK can1_tx_isr(void);
-void WEAK can1_rx0_isr(void);
-void WEAK can1_rx1_isr(void);
-void WEAK can1_sce_isr(void);
-void WEAK exti9_5_isr(void);
-void WEAK tim1_brk_tim9_isr(void);
-void WEAK tim1_up_tim10_isr(void);
-void WEAK tim1_trg_com_tim11_isr(void);
-void WEAK tim1_cc_isr(void);
-void WEAK tim2_isr(void);
-void WEAK tim3_isr(void);
-void WEAK tim4_isr(void);
-void WEAK i2c1_ev_isr(void);
-void WEAK i2c1_er_isr(void);
-void WEAK i2c2_ev_isr(void);
-void WEAK i2c2_er_isr(void);
-void WEAK spi1_isr(void);
-void WEAK spi2_isr(void);
-void WEAK usart1_isr(void);
-void WEAK usart2_isr(void);
-void WEAK usart3_isr(void);
-void WEAK exti15_10_isr(void);
-void WEAK rtc_alarm_isr(void);
-void WEAK usb_fs_wkup_isr(void);
-void WEAK tim8_brk_tim12_isr(void);
-void WEAK tim8_up_tim13_isr(void);
-void WEAK tim8_trg_com_tim14_isr(void);
-void WEAK tim8_cc_isr(void);
-void WEAK dma1_stream7_isr(void);
-void WEAK fsmc_isr(void);
-void WEAK sdio_isr(void);
-void WEAK tim5_isr(void);
-void WEAK spi3_isr(void);
-void WEAK uart4_isr(void);
-void WEAK uart5_isr(void);
-void WEAK tim6_dac_isr(void);
-void WEAK tim7_isr(void);
-void WEAK dma2_stream0_isr(void);
-void WEAK dma2_stream1_isr(void);
-void WEAK dma2_stream2_isr(void);
-void WEAK dma2_stream3_isr(void);
-void WEAK dma2_stream4_isr(void);
-void WEAK eth_isr(void);
-void WEAK eth_wkup_isr(void);
-void WEAK can2_tx_isr(void);
-void WEAK can2_rx0_isr(void);
-void WEAK can2_rx1_isr(void);
-void WEAK can2_sce_isr(void);
-void WEAK otg_fs_isr(void);
-void WEAK dma2_stream5_isr(void);
-void WEAK dma2_stream6_isr(void);
-void WEAK dma2_stream7_isr(void);
-void WEAK usart6_isr(void);
-void WEAK i2c3_ev_isr(void);
-void WEAK i2c3_er_isr(void);
-void WEAK otg_hs_ep1_out_isr(void);
-void WEAK otg_hs_ep1_in_isr(void);
-void WEAK otg_hs_wkup_isr(void);
-void WEAK otg_hs_isr(void);
-void WEAK dcmi_isr(void);
-void WEAK cryp_isr(void);
-void WEAK hash_rng_isr(void);
-
-__attribute__ ((section(".vectors")))
-void (*const vector_table[]) (void) = {
- (void *)&_stack,
- reset_handler,
- nmi_handler,
- hard_fault_handler,
- mem_manage_handler,
- bus_fault_handler,
- usage_fault_handler,
- 0, 0, 0, 0, /* Reserved */
- sv_call_handler,
- debug_monitor_handler,
- 0, /* Reserved */
- pend_sv_handler,
- sys_tick_handler,
- wwdg_isr,
- pvd_isr,
- tamp_stamp_isr,
- rtc_wkup_isr,
- flash_isr,
- rcc_isr,
- exti0_isr,
- exti1_isr,
- exti2_isr,
- exti3_isr,
- exti4_isr,
- dma1_stream0_isr,
- dma1_stream1_isr,
- dma1_stream2_isr,
- dma1_stream3_isr,
- dma1_stream4_isr,
- dma1_stream5_isr,
- dma1_stream6_isr,
- adc_isr,
- can1_tx_isr,
- can1_rx0_isr,
- can1_rx1_isr,
- can1_sce_isr,
- exti9_5_isr,
- tim1_brk_tim9_isr,
- tim1_up_tim10_isr,
- tim1_trg_com_tim11_isr,
- tim1_cc_isr,
- tim2_isr,
- tim3_isr,
- tim4_isr,
- i2c1_ev_isr,
- i2c1_er_isr,
- i2c2_ev_isr,
- i2c2_er_isr,
- spi1_isr,
- spi2_isr,
- usart1_isr,
- usart2_isr,
- usart3_isr,
- exti15_10_isr,
- rtc_alarm_isr,
- usb_fs_wkup_isr,
- tim8_brk_tim12_isr,
- tim8_up_tim13_isr,
- tim8_trg_com_tim14_isr,
- tim8_cc_isr,
- dma1_stream7_isr,
- fsmc_isr,
- sdio_isr,
- tim5_isr,
- spi3_isr,
- uart4_isr,
- uart5_isr,
- tim6_dac_isr,
- tim7_isr,
- dma2_stream0_isr,
- dma2_stream1_isr,
- dma2_stream2_isr,
- dma2_stream3_isr,
- dma2_stream4_isr,
- eth_isr,
- eth_wkup_isr,
- can2_tx_isr,
- can2_rx0_isr,
- can2_rx1_isr,
- can2_sce_isr,
- otg_fs_isr,
- dma2_stream5_isr,
- dma2_stream6_isr,
- dma2_stream7_isr,
- usart6_isr,
- i2c3_ev_isr,
- i2c3_er_isr,
- otg_hs_ep1_out_isr,
- otg_hs_ep1_in_isr,
- otg_hs_wkup_isr,
- otg_hs_isr,
- dcmi_isr,
- cryp_isr,
- hash_rng_isr,
-};
-
-void reset_handler(void)
-{
- volatile unsigned *src, *dest;
-
- __asm__("MSR msp, %0" : : "r"(&_stack));
-
- /* Enable access to Floating-Point coprocessor. */
- SCB_CPACR |= SCB_CPACR_FULL * (SCB_CPACR_CP10 | SCB_CPACR_CP11);
-
- for (src = &_data_loadaddr, dest = &_data; dest < &_edata; src++, dest++)
- *dest = *src;
-
- while (dest < &_ebss)
- *dest++ = 0;
-
- /* Call the application's entry point. */
- main();
-}
-
-void blocking_handler(void)
-{
- while (1) ;
-}
-
-void null_handler(void)
-{
- /* Do nothing. */
-}
-
-#pragma weak nmi_handler = null_handler
-#pragma weak hard_fault_handler = blocking_handler
-#pragma weak mem_manage_handler = blocking_handler
-#pragma weak bus_fault_handler = blocking_handler
-#pragma weak usage_fault_handler = blocking_handler
-#pragma weak sv_call_handler = null_handler
-#pragma weak debug_monitor_handler = null_handler
-#pragma weak pend_sv_handler = null_handler
-#pragma weak sys_tick_handler = null_handler
-#pragma weak wwdg_isr = null_handler
-#pragma weak pvd_isr = null_handler
-#pragma weak tamp_stamp_isr = null_handler
-#pragma weak rtc_wkup_isr = null_handler
-#pragma weak flash_isr = null_handler
-#pragma weak rcc_isr = null_handler
-#pragma weak exti0_isr = null_handler
-#pragma weak exti1_isr = null_handler
-#pragma weak exti2_isr = null_handler
-#pragma weak exti3_isr = null_handler
-#pragma weak exti4_isr = null_handler
-#pragma weak dma1_stream0_isr = null_handler
-#pragma weak dma1_stream1_isr = null_handler
-#pragma weak dma1_stream2_isr = null_handler
-#pragma weak dma1_stream3_isr = null_handler
-#pragma weak dma1_stream4_isr = null_handler
-#pragma weak dma1_stream5_isr = null_handler
-#pragma weak dma1_stream6_isr = null_handler
-#pragma weak adc_isr = null_handler
-#pragma weak can1_tx_isr = null_handler
-#pragma weak can1_rx0_isr = null_handler
-#pragma weak can1_rx1_isr = null_handler
-#pragma weak can1_sce_isr = null_handler
-#pragma weak exti9_5_isr = null_handler
-#pragma weak tim1_brk_tim9_isr = null_handler
-#pragma weak tim1_up_tim10_isr = null_handler
-#pragma weak tim1_trg_com_tim11_isr = null_handler
-#pragma weak tim1_cc_isr = null_handler
-#pragma weak tim2_isr = null_handler
-#pragma weak tim3_isr = null_handler
-#pragma weak tim4_isr = null_handler
-#pragma weak i2c1_ev_isr = null_handler
-#pragma weak i2c1_er_isr = null_handler
-#pragma weak i2c2_ev_isr = null_handler
-#pragma weak i2c2_er_isr = null_handler
-#pragma weak spi1_isr = null_handler
-#pragma weak spi2_isr = null_handler
-#pragma weak usart1_isr = null_handler
-#pragma weak usart2_isr = null_handler
-#pragma weak usart3_isr = null_handler
-#pragma weak exti15_10_isr = null_handler
-#pragma weak rtc_alarm_isr = null_handler
-#pragma weak usb_fs_wkup_isr = null_handler
-#pragma weak tim8_brk_tim12_isr = null_handler
-#pragma weak tim8_up_tim13_isr = null_handler
-#pragma weak tim8_trg_com_tim14_isr = null_handler
-#pragma weak tim8_cc_isr = null_handler
-#pragma weak dma1_stream7_isr = null_handler
-#pragma weak fsmc_isr = null_handler
-#pragma weak sdio_isr = null_handler
-#pragma weak tim5_isr = null_handler
-#pragma weak spi3_isr = null_handler
-#pragma weak uart4_isr = null_handler
-#pragma weak uart5_isr = null_handler
-#pragma weak tim6_dac_isr = null_handler
-#pragma weak tim7_isr = null_handler
-#pragma weak dma2_stream0_isr = null_handler
-#pragma weak dma2_stream1_isr = null_handler
-#pragma weak dma2_stream2_isr = null_handler
-#pragma weak dma2_stream3_isr = null_handler
-#pragma weak dma2_stream4_isr = null_handler
-#pragma weak eth_isr = null_handler
-#pragma weak eth_wkup_isr = null_handler
-#pragma weak can2_tx_isr = null_handler
-#pragma weak can2_rx0_isr = null_handler
-#pragma weak can2_rx1_isr = null_handler
-#pragma weak can2_sce_isr = null_handler
-#pragma weak otg_fs_isr = null_handler
-#pragma weak dma2_stream5_isr = null_handler
-#pragma weak dma2_stream6_isr = null_handler
-#pragma weak dma2_stream7_isr = null_handler
-#pragma weak usart6_isr = null_handler
-#pragma weak i2c3_ev_isr = null_handler
-#pragma weak i2c3_er_isr = null_handler
-#pragma weak otg_hs_ep1_out_isr = null_handler
-#pragma weak otg_hs_ep1_in_isr = null_handler
-#pragma weak otg_hs_wkup_isr = null_handler
-#pragma weak otg_hs_isr = null_handler
-#pragma weak dcmi_isr = null_handler
-#pragma weak cryp_isr = null_handler
-#pragma weak hash_rng_isr = null_handler
diff --git a/lib/stm32/f4/scb.c b/lib/stm32/f4/vector_chipset.c
index cbf4d53..145be05 100644
--- a/lib/stm32/f4/scb.c
+++ b/lib/stm32/f4/vector_chipset.c
@@ -1,7 +1,8 @@
/*
* This file is part of the libopencm3 project.
*
- * Copyright (C) 2010 Gareth McMullin <gareth@blacksphere.co.nz>
+ * Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
+ * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
@@ -17,19 +18,10 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
-#include <libopencm3/stm32/f4/scb.h>
+#include <libopencm3/cm3/scb.h>
-void scb_reset_core(void)
+static void pre_main(void)
{
- SCB_AIRCR = SCB_AIRCR_VECTKEY | SCB_AIRCR_VECTRESET;
-}
-
-void scb_reset_system(void)
-{
- SCB_AIRCR = SCB_AIRCR_VECTKEY | SCB_AIRCR_SYSRESETREQ;
-}
-
-void scb_set_priority_grouping(u32 prigroup)
-{
- SCB_AIRCR = SCB_AIRCR_VECTKEY | prigroup;
+ /* Enable access to Floating-Point coprocessor. */
+ SCB_CPACR |= SCB_CPACR_FULL * (SCB_CPACR_CP10 | SCB_CPACR_CP11);
}