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-rw-r--r--lib/stm32/f1/Makefile13
-rw-r--r--lib/stm32/f1/adc.c114
-rw-r--r--lib/stm32/f1/can.c303
-rw-r--r--lib/stm32/f1/crc.c (renamed from lib/stm32/f1/scb.c)26
-rw-r--r--lib/stm32/f1/dac.c (renamed from lib/stm32/f1/desig.c)29
-rw-r--r--lib/stm32/f1/dma.c349
-rw-r--r--lib/stm32/f1/flash.c63
-rw-r--r--lib/stm32/f1/gpio.c142
-rw-r--r--lib/stm32/f1/i2c.c28
-rw-r--r--lib/stm32/f1/iwdg.c28
-rw-r--r--lib/stm32/f1/rcc.c181
-rw-r--r--lib/stm32/f1/rtc.c2
-rw-r--r--lib/stm32/f1/spi.c28
-rw-r--r--lib/stm32/f1/timer.c1948
-rw-r--r--lib/stm32/f1/usart.c28
-rw-r--r--lib/stm32/f1/vector.c296
16 files changed, 417 insertions, 3161 deletions
diff --git a/lib/stm32/f1/Makefile b/lib/stm32/f1/Makefile
index a2f7bf2..ba0d4b8 100644
--- a/lib/stm32/f1/Makefile
+++ b/lib/stm32/f1/Makefile
@@ -24,16 +24,19 @@ PREFIX ?= arm-none-eabi
CC = $(PREFIX)-gcc
AR = $(PREFIX)-ar
CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \
- -mcpu=cortex-m3 -mthumb -Wstrict-prototypes \
+ -mcpu=cortex-m3 -msoft-float -mthumb -Wstrict-prototypes \
-ffunction-sections -fdata-sections -MD -DSTM32F1
# ARFLAGS = rcsv
ARFLAGS = rcs
-OBJS = vector.o rcc.o gpio.o usart.o adc.o spi.o flash.o nvic.o \
- rtc.o i2c.o dma.o systick.o exti.o scb.o ethernet.o \
+OBJS = rcc.o gpio.o adc.o flash.o rtc.o dma.o exti.o ethernet.o \
usb_f103.o usb.o usb_control.o usb_standard.o can.o \
- timer.o usb_f107.o desig.o crc.o assert.o dac.o iwdg.o pwr.o
+ timer.o usb_f107.o desig.o pwr_common_all.o \
+ usb_fx07_common.o \
+ gpio_common_all.o dma_common_f13.o spi_common_all.o \
+ dac_common_all.o usart_common_all.o iwdg_common_all.o \
+ i2c_common_all.o crc_common_all.o
-VPATH += ../../usb:../:../../cm3
+VPATH += ../../usb:../:../../cm3:../common
include ../../Makefile.include
diff --git a/lib/stm32/f1/adc.c b/lib/stm32/f1/adc.c
index 0a05aac..71eb926 100644
--- a/lib/stm32/f1/adc.c
+++ b/lib/stm32/f1/adc.c
@@ -187,7 +187,7 @@ void adc_set_dual_mode(u32 mode)
This flag is set after all channels of a regular or injected group have been
converted.
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base.
@returns bool. End of conversion flag.
*/
@@ -201,7 +201,7 @@ bool adc_eoc(u32 adc)
This flag is set after all channels of an injected group have been converted.
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base.
@returns bool. End of conversion flag.
*/
@@ -217,7 +217,7 @@ The result read back is 12 bits, right or left aligned within the first 16 bits.
For ADC1 only, the higher 16 bits will hold the result from ADC2 if
an appropriate dual mode has been set @see adc_set_dual_mode.
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base.
@returns Unsigned int32 conversion result.
*/
@@ -233,7 +233,7 @@ The result read back from the selected injected result register (one of four) is
12 bits, right or left aligned within the first 16 bits. The result can have a
negative value if the injected channel offset has been set @see adc_set_injected_offset.
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base.
@param[in] reg Unsigned int8. Register number (1 ... 4).
@returns Unsigned int32 conversion result.
*/
@@ -260,7 +260,7 @@ This value is subtracted from the injected channel results after conversion
is complete, and can result in negative results. A separate value can be specified
for each injected data register.
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base.
@param[in] reg Unsigned int8. Register number (1 ... 4).
@param[in] offset Unsigned int32.
*/
@@ -290,7 +290,7 @@ The analog watchdog allows the monitoring of an analog signal between two thresh
levels. The thresholds must be preset. Comparison is done before data alignment
takes place, so the thresholds are left-aligned.
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base.
*/
void adc_enable_analog_watchdog_regular(u32 adc)
@@ -301,7 +301,7 @@ void adc_enable_analog_watchdog_regular(u32 adc)
/*-----------------------------------------------------------------------------*/
/** @brief ADC Disable Analog Watchdog for Regular Conversions
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base.
*/
void adc_disable_analog_watchdog_regular(u32 adc)
@@ -316,7 +316,7 @@ The analog watchdog allows the monitoring of an analog signal between two thresh
levels. The thresholds must be preset. Comparison is done before data alignment
takes place, so the thresholds are left-aligned.
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base.
*/
void adc_enable_analog_watchdog_injected(u32 adc)
@@ -327,7 +327,7 @@ void adc_enable_analog_watchdog_injected(u32 adc)
/*-----------------------------------------------------------------------------*/
/** @brief ADC Disable Analog Watchdog for Injected Conversions
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base.
*/
void adc_disable_analog_watchdog_injected(u32 adc)
@@ -346,8 +346,8 @@ of the same length or until the whole group has all been converted. When the
the whole group has been converted, the next trigger will restart conversion
of the subgroup at the beginning of the whole group.
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
-@param[in] length Unsigned int8. Number of channels in the group @ref adc_cr1_discnum
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base.
+@param[in] length Unsigned int8. Number of channels in the group @ref adc_cr1_discnum.
*/
void adc_enable_discontinuous_mode_regular(u32 adc, u8 length)
@@ -360,7 +360,7 @@ void adc_enable_discontinuous_mode_regular(u32 adc, u8 length)
/*-----------------------------------------------------------------------------*/
/** @brief ADC Disable Discontinuous Mode for Regular Conversions
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base.
*/
void adc_disable_discontinuous_mode_regular(u32 adc)
@@ -375,7 +375,7 @@ In this mode the ADC converts sequentially one channel of the defined group of
injected channels, cycling back to the first channel in the group once the
entire group has been converted.
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base.
*/
void adc_enable_discontinuous_mode_injected(u32 adc)
@@ -386,7 +386,7 @@ void adc_enable_discontinuous_mode_injected(u32 adc)
/*-----------------------------------------------------------------------------*/
/** @brief ADC Disable Discontinuous Mode for Injected Conversions
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base.
*/
void adc_disable_discontinuous_mode_injected(u32 adc)
@@ -413,7 +413,7 @@ void adc_enable_automatic_injected_group_conversion(u32 adc)
/*-----------------------------------------------------------------------------*/
/** @brief ADC Disable Automatic Injected Conversions
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base.
*/
void adc_disable_automatic_injected_group_conversion(u32 adc)
@@ -433,7 +433,7 @@ injected channels. If neither are enabled, the analog watchdog feature will be
disabled.
@ref adc_enable_analog_watchdog_injected, @ref adc_enable_analog_watchdog_regular.
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base.
*/
void adc_enable_analog_watchdog_on_all_channels(u32 adc)
@@ -453,8 +453,8 @@ injected channels. If neither are enabled, the analog watchdog feature will be
disabled. If both are enabled, the same channel number is monitored.
@ref adc_enable_analog_watchdog_injected, @ref adc_enable_analog_watchdog_regular.
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
-@param[in] channel Unsigned int8. ADC channel number @ref adc_watchdog_channel
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base.
+@param[in] channel Unsigned int8. ADC channel number @ref adc_watchdog_channel.
*/
void adc_enable_analog_watchdog_on_selected_channel(u32 adc, u8 channel)
@@ -475,7 +475,7 @@ In this mode a conversion consists of a scan of the predefined set of channels,
regular and injected, each channel conversion immediately following the
previous one. It can use single, continuous or discontinuous mode.
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base.
*/
void adc_enable_scan_mode(u32 adc)
@@ -497,7 +497,7 @@ void adc_disable_scan_mode(u32 adc)
/*-----------------------------------------------------------------------------*/
/** @brief ADC Enable Injected End-Of-Conversion Interrupt
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base.
*/
void adc_enable_eoc_interrupt_injected(u32 adc)
@@ -508,7 +508,7 @@ void adc_enable_eoc_interrupt_injected(u32 adc)
/*-----------------------------------------------------------------------------*/
/** @brief ADC Disable Injected End-Of-Conversion Interrupt
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base.
*/
void adc_disable_eoc_interrupt_injected(u32 adc)
@@ -519,7 +519,7 @@ void adc_disable_eoc_interrupt_injected(u32 adc)
/*-----------------------------------------------------------------------------*/
/** @brief ADC Enable Analog Watchdog Interrupt
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base.
*/
void adc_enable_awd_interrupt(u32 adc)
@@ -530,7 +530,7 @@ void adc_enable_awd_interrupt(u32 adc)
/*-----------------------------------------------------------------------------*/
/** @brief ADC Disable Analog Watchdog Interrupt
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base.
*/
void adc_disable_awd_interrupt(u32 adc)
@@ -541,7 +541,7 @@ void adc_disable_awd_interrupt(u32 adc)
/*-----------------------------------------------------------------------------*/
/** @brief ADC Enable Regular End-Of-Conversion Interrupt
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base.
*/
void adc_enable_eoc_interrupt(u32 adc)
@@ -552,7 +552,7 @@ void adc_enable_eoc_interrupt(u32 adc)
/*-----------------------------------------------------------------------------*/
/** @brief ADC Disable Regular End-Of-Conversion Interrupt
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base.
*/
void adc_disable_eoc_interrupt(u32 adc)
@@ -566,7 +566,7 @@ void adc_disable_eoc_interrupt(u32 adc)
This enables both the sensor and the reference voltage measurements on channels
16 and 17.
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base.
*/
void adc_enable_temperature_sensor(u32 adc)
@@ -580,7 +580,7 @@ void adc_enable_temperature_sensor(u32 adc)
Disabling this will reduce power consumption from the sensor and the reference
voltage measurements.
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base.
*/
void adc_disable_temperature_sensor(u32 adc)
@@ -599,7 +599,7 @@ Note this is a software trigger and requires triggering to be enabled and the
trigger source to be set appropriately otherwise conversion will not start.
This is not the same as the ADC start conversion operation.
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base.
*/
void adc_start_conversion_regular(u32 adc)
@@ -622,7 +622,7 @@ Note this is a software trigger and requires triggering to be enabled and the
trigger source to be set appropriately otherwise conversion will not start.
This is not the same as the ADC start conversion operation.
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base.
*/
void adc_start_conversion_injected(u32 adc)
@@ -659,9 +659,9 @@ For ADC3
@li Timer 5 CC3 event
@li Software Start
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base.
@param[in] trigger Unsigned int8. Trigger identifier @ref adc_trigger_regular_12
-for ADC1 and ADC2, or @ref adc_trigger_regular_3 for ADC3
+for ADC1 and ADC2, or @ref adc_trigger_regular_3 for ADC3.
*/
void adc_enable_external_trigger_regular(u32 adc, u32 trigger)
@@ -677,7 +677,7 @@ void adc_enable_external_trigger_regular(u32 adc, u32 trigger)
/*-----------------------------------------------------------------------------*/
/** @brief ADC Disable an External Trigger for Regular Channels
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base.
*/
void adc_disable_external_trigger_regular(u32 adc)
@@ -710,9 +710,9 @@ For ADC3
@li Timer 5 CC4 event
@li Software Start
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base.
@param[in] trigger Unsigned int8. Trigger identifier @ref adc_trigger_injected_12
-for ADC1 and ADC2, or @ref adc_trigger_injected_3 for ADC3
+for ADC1 and ADC2, or @ref adc_trigger_injected_3 for ADC3.
*/
void adc_enable_external_trigger_injected(u32 adc, u32 trigger)
{
@@ -727,7 +727,7 @@ void adc_enable_external_trigger_injected(u32 adc, u32 trigger)
/*-----------------------------------------------------------------------------*/
/** @brief ADC Disable an External Trigger for Injected Channels
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base.
*/
void adc_disable_external_trigger_injected(u32 adc)
@@ -738,7 +738,7 @@ void adc_disable_external_trigger_injected(u32 adc)
/*-----------------------------------------------------------------------------*/
/** @brief ADC Set the Data as Left Aligned
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base.
*/
void adc_set_left_aligned(u32 adc)
@@ -749,7 +749,7 @@ void adc_set_left_aligned(u32 adc)
/*-----------------------------------------------------------------------------*/
/** @brief ADC Set the Data as Right Aligned
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base.
*/
void adc_set_right_aligned(u32 adc)
@@ -764,7 +764,7 @@ Only available for ADC1 through DMA1 channel1, and ADC3 through DMA2 channel5.
ADC2 will use DMA if it is set as slave in dual mode with ADC1 in DMA transfer
mode.
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base.
*/
void adc_enable_dma(u32 adc)
@@ -776,7 +776,7 @@ void adc_enable_dma(u32 adc)
/*-----------------------------------------------------------------------------*/
/** @brief ADC Disable DMA Transfers
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base.
*/
void adc_disable_dma(u32 adc)
@@ -791,7 +791,7 @@ void adc_disable_dma(u32 adc)
This resets the calibration registers. It is not clear if this is required to be
done before every calibration operation.
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base.
*/
void adc_reset_calibration(u32 adc)
@@ -810,7 +810,7 @@ until this happens and the ADC is ready for use.
The ADC must have been powered down for at least 2 ADC clock cycles, then powered on.
before calibration starts
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base.
*/
void adc_calibration(u32 adc)
@@ -825,7 +825,7 @@ void adc_calibration(u32 adc)
In this mode the ADC starts a new conversion of a single channel or a channel
group immediately following completion of the previous channel group conversion.
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base.
*/
void adc_set_continuous_conversion_mode(u32 adc)
@@ -839,7 +839,7 @@ void adc_set_continuous_conversion_mode(u32 adc)
In this mode the ADC performs a conversion of one channel or a channel group
and stops.
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base.
*/
void adc_set_single_conversion_mode(u32 adc)
@@ -856,7 +856,7 @@ If the ADC is already on this function call will initiate a conversion.
@deprecated to be removed in a later release
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base.
*/
void adc_on(u32 adc)
@@ -869,7 +869,7 @@ void adc_on(u32 adc)
Turn off the ADC to reduce power consumption to a few microamps.
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base.
*/
void adc_off(u32 adc)
@@ -882,9 +882,9 @@ void adc_off(u32 adc)
The sampling time can be selected in ADC clock cycles from 1.5 to 239.5.
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
-@param[in] channel Unsigned int8. ADC Channel integer 0..18 or from @ref adc_channel
-@param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base.
+@param[in] channel Unsigned int8. ADC Channel integer 0..18 or from @ref adc_channel.
+@param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg.
*/
void adc_set_sample_time(u32 adc, u8 channel, u8 time)
@@ -910,8 +910,8 @@ void adc_set_sample_time(u32 adc, u8 channel, u8 time)
The sampling time can be selected in ADC clock cycles from 1.5 to 239.5, same for
all channels.
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
-@param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base.
+@param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg.
*/
void adc_set_sample_time_on_all_channels(u32 adc, u8 time)
@@ -931,8 +931,8 @@ void adc_set_sample_time_on_all_channels(u32 adc, u8 time)
/*-----------------------------------------------------------------------------*/
/** @brief ADC Set Analog Watchdog Upper Threshold
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
-@param[in] threshold Unsigned int8. Upper threshold value
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base.
+@param[in] threshold Unsigned int8. Upper threshold value.
*/
void adc_set_watchdog_high_threshold(u32 adc, u16 threshold)
@@ -947,8 +947,8 @@ void adc_set_watchdog_high_threshold(u32 adc, u16 threshold)
/*-----------------------------------------------------------------------------*/
/** @brief ADC Set Analog Watchdog Lower Threshold
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
-@param[in] threshold Unsigned int8. Lower threshold value
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base.
+@param[in] threshold Unsigned int8. Lower threshold value.
*/
void adc_set_watchdog_low_threshold(u32 adc, u16 threshold)
@@ -967,7 +967,7 @@ Define a sequence of channels to be converted as a regular group with a length
from 1 to 16 channels. If this is called during conversion, the current conversion
is reset and conversion begins again with the newly defined group.
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base.
@param[in] length Unsigned int8. Number of channels in the group.
@param[in] channel Unsigned int8[]. Set of channels in sequence, integers 0..18.
*/
@@ -1003,9 +1003,9 @@ Defines a sequence of channels to be converted as an injected group with a lengt
from 1 to 4 channels. If this is called during conversion, the current conversion
is reset and conversion begins again with the newly defined group.
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base.
@param[in] length Unsigned int8. Number of channels in the group.
-@param[in] channel Unsigned int8[]. Set of channels in sequence, integers 0..18
+@param[in] channel Unsigned int8[]. Set of channels in sequence, integers 0..18.
*/
void adc_set_injected_sequence(u32 adc, u8 length, u8 channel[])
diff --git a/lib/stm32/f1/can.c b/lib/stm32/f1/can.c
deleted file mode 100644
index fc7e0e7..0000000
--- a/lib/stm32/f1/can.c
+++ /dev/null
@@ -1,303 +0,0 @@
-/*
- * This file is part of the libopencm3 project.
- *
- * Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <libopencm3/stm32/can.h>
-#include <libopencm3/stm32/f1/rcc.h>
-
-void can_reset(u32 canport)
-{
- if (canport == CAN1) {
- rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_CAN1RST);
- rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_CAN1RST);
- } else {
- rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_CAN2RST);
- rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_CAN2RST);
- }
-}
-
-int can_init(u32 canport, bool ttcm, bool abom, bool awum, bool nart,
- bool rflm, bool txfp, u32 sjw, u32 ts1, u32 ts2, u32 brp)
-{
- u32 wait_ack = 0x00000000;
- u32 can_msr_inak_timeout = 0x0000FFFF;
- int ret = 0;
-
- /* Exit from sleep mode. */
- CAN_MCR(canport) &= ~CAN_MCR_SLEEP;
-
- /* Request initialization "enter". */
- CAN_MCR(canport) |= CAN_MCR_INRQ;
-
- /* Wait for acknowledge. */
- while ((wait_ack != can_msr_inak_timeout) &&
- ((CAN_MSR(canport) & CAN_MSR_INAK) != CAN_MSR_INAK)) {
- wait_ack++;
- }
-
- /* Check the acknowledge. */
- if ((CAN_MSR(canport) & CAN_MSR_INAK) != CAN_MSR_INAK)
- return 1;
-
- /* Set the automatic bus-off management. */
- if (ttcm)
- CAN_MCR(canport) |= CAN_MCR_TTCM;
- else
- CAN_MCR(canport) &= ~CAN_MCR_TTCM;
-
- if (abom)
- CAN_MCR(canport) |= CAN_MCR_ABOM;
- else
- CAN_MCR(canport) &= ~CAN_MCR_ABOM;
-
- if (awum)
- CAN_MCR(canport) |= CAN_MCR_AWUM;
- else
- CAN_MCR(canport) &= ~CAN_MCR_AWUM;
-
- if (nart)
- CAN_MCR(canport) |= CAN_MCR_NART;
- else
- CAN_MCR(canport) &= ~CAN_MCR_NART;
-
- if (rflm)
- CAN_MCR(canport) |= CAN_MCR_RFLM;
- else
- CAN_MCR(canport) &= ~CAN_MCR_RFLM;
-
- if (txfp)
- CAN_MCR(canport) |= CAN_MCR_TXFP;
- else
- CAN_MCR(canport) &= ~CAN_MCR_TXFP;
-
- /* Set bit timings. */
- CAN_BTR(canport) = sjw | ts2 | ts1 |
- (u32)(CAN_BTR_BRP_MASK & (brp - 1));
-
- /* Request initialization "leave". */
- CAN_MCR(canport) &= ~CAN_MCR_INRQ;
-
- /* Wait for acknowledge. */
- wait_ack = 0x00000000;
- while ((wait_ack != can_msr_inak_timeout) &&
- ((CAN_MSR(canport) & CAN_MSR_INAK) == CAN_MSR_INAK)) {
- wait_ack++;
- }
-
- if ((CAN_MSR(canport) & CAN_MSR_INAK) == CAN_MSR_INAK)
- ret = 1;
-
- return ret;
-}
-
-void can_filter_init(u32 canport, u32 nr, bool scale_32bit, bool id_list_mode,
- u32 fr1, u32 fr2, u32 fifo, bool enable)
-{
- u32 filter_select_bit = 0x00000001 << nr;
-
- /* Request initialization "enter". */
- CAN_FMR(canport) |= CAN_FMR_FINIT;
-
- /* Deactivate the filter. */
- CAN_FA1R(canport) &= ~filter_select_bit;
-
- if (scale_32bit) {
- /* Set 32-bit scale for the filter. */
- CAN_FS1R(canport) |= filter_select_bit;
- } else {
- /* Set 16-bit scale for the filter. */
- CAN_FS1R(canport) &= ~filter_select_bit;
- }
-
- if (id_list_mode) {
- /* Set filter mode to ID list mode. */
- CAN_FM1R(canport) |= filter_select_bit;
- } else {
- /* Set filter mode to id/mask mode. */
- CAN_FM1R(canport) &= ~filter_select_bit;
- }
-
- /* Set the first filter register. */
- CAN_FiR1(canport, nr) = fr1;
-
- /* Set the second filter register. */
- CAN_FiR2(canport, nr) = fr2;
-
- /* Select FIFO0 or FIFO1 as filter assignement. */
- if (fifo)
- CAN_FFA1R(canport) |= filter_select_bit; /* FIFO1 */
- else
- CAN_FFA1R(canport) &= ~filter_select_bit; /* FIFO0 */
-
- if (enable)
- CAN_FA1R(canport) |= filter_select_bit; /* Activate filter. */
-
- /* Request initialization "leave". */
- CAN_FMR(canport) &= ~CAN_FMR_FINIT;
-}
-
-void can_filter_id_mask_16bit_init(u32 canport, u32 nr, u16 id1, u16 mask1,
- u16 id2, u16 mask2, u32 fifo, bool enable)
-{
- can_filter_init(canport, nr, false, false,
- ((u32)id1 << 16) | (u32)mask1,
- ((u32)id2 << 16) | (u32)mask2, fifo, enable);
-}
-
-void can_filter_id_mask_32bit_init(u32 canport, u32 nr, u32 id, u32 mask,
- u32 fifo, bool enable)
-{
- can_filter_init(canport, nr, true, false, id, mask, fifo, enable);
-}
-
-void can_filter_id_list_16bit_init(u32 canport, u32 nr, u16 id1, u16 id2,
- u16 id3, u16 id4, u32 fifo, bool enable)
-{
- can_filter_init(canport, nr, false, true,
- ((u32)id1 << 16) | (u32)id2,
- ((u32)id3 << 16) | (u32)id4, fifo, enable);
-}
-
-void can_filter_id_list_32bit_init(u32 canport, u32 nr, u32 id1, u32 id2,
- u32 fifo, bool enable)
-{
- can_filter_init(canport, nr, true, true, id1, id2, fifo, enable);
-}
-
-void can_enable_irq(u32 canport, u32 irq)
-{
- CAN_IER(canport) |= irq;
-}
-
-void can_disable_irq(u32 canport, u32 irq)
-{
- CAN_IER(canport) &= ~irq;
-}
-
-int can_transmit(u32 canport, u32 id, bool ext, bool rtr, u8 length, u8 *data)
-{
- int ret = 0, i;
- u32 mailbox = 0;
-
- if ((CAN_TSR(canport) & CAN_TSR_TME0) == CAN_TSR_TME0) {
- ret = 0;
- mailbox = CAN_MBOX0;
- } else if ((CAN_TSR(canport) & CAN_TSR_TME1) == CAN_TSR_TME1) {
- ret = 1;
- mailbox = CAN_MBOX1;
- } else if ((CAN_TSR(canport) & CAN_TSR_TME2) == CAN_TSR_TME2) {
- ret = 2;
- mailbox = CAN_MBOX2;
- } else {
- ret = -1;
- }
-
- /* Check if we have an empty mailbox. */
- if (ret == -1)
- return ret;
-
- /* Clear stale register bits */
- CAN_TIxR(canport, mailbox) = 0;
- if (ext) {
- /* Set extended ID. */
- CAN_TIxR(canport, mailbox) |= id << CAN_TIxR_EXID_SHIFT;
- /* Set extended ID indicator bit. */
- CAN_TIxR(canport, mailbox) |= CAN_TIxR_IDE;
- } else {
- /* Set standard ID. */
- CAN_TIxR(canport, mailbox) |= id << CAN_TIxR_STID_SHIFT;
- }
-
- /* Set/clear remote transmission request bit. */
- if (rtr)
- CAN_TIxR(canport, mailbox) |= CAN_TIxR_RTR; /* Set */
-
- /* Set the DLC. */
- CAN_TDTxR(canport, mailbox) &= 0xFFFFFFF0;
- CAN_TDTxR(canport, mailbox) |= length & CAN_TDTxR_DLC_MASK;
-
- /* Set the data. */
- CAN_TDLxR(canport, mailbox) = 0;
- CAN_TDHxR(canport, mailbox) = 0;
- for (i = 0; (i < 4) && (i < length); i++)
- CAN_TDLxR(canport, mailbox) |= (u32)data[i] << (8 * i);
- for (i = 4; (i < 8) && (i < length); i++)
- CAN_TDHxR(canport, mailbox) |= (u32)data[i] << (8 * (i - 4));
-
- /* Request transmission. */
- CAN_TIxR(canport, mailbox) |= CAN_TIxR_TXRQ;
-
- return ret;
-}
-
-void can_fifo_release(u32 canport, u8 fifo)
-{
- if (fifo == 0)
- CAN_RF0R(canport) |= CAN_RF1R_RFOM1;
- else
- CAN_RF1R(canport) |= CAN_RF1R_RFOM1;
-}
-
-void can_receive(u32 canport, u8 fifo, bool release, u32 *id, bool *ext,
- bool *rtr, u32 *fmi, u8 *length, u8 *data)
-{
- u32 fifo_id = 0;
- int i;
-
- if (fifo == 0)
- fifo_id = CAN_FIFO0;
- else
- fifo_id = CAN_FIFO1;
-
- /* Get type of CAN ID and CAN ID. */
- if (CAN_RIxR(canport, fifo_id) & CAN_RIxR_IDE) {
- *ext = true;
- /* Get extended CAN ID. */
- *id = ((CAN_RIxR(canport, fifo_id) & CAN_RIxR_EXID_MASK) >>
- CAN_RIxR_EXID_SHIFT);
- } else {
- *ext = false;
- /* Get standard CAN ID. */
- *id = ((CAN_RIxR(canport, fifo_id) & CAN_RIxR_STID_MASK) >>
- CAN_RIxR_STID_SHIFT);
- }
-
- /* Get request transmit flag. */
- if (CAN_RIxR(canport, fifo_id) & CAN_RIxR_RTR)
- *rtr = true;
- else
- *rtr = false;
-
- /* Get filter match ID. */
- *fmi = ((CAN_RDTxR(canport, fifo_id) & CAN_RDTxR_FMI_MASK) >
- CAN_RDTxR_FMI_SHIFT);
-
- /* Get data length. */
- *length = CAN_RDTxR(canport, fifo_id) & CAN_RDTxR_DLC_MASK;
-
- /* Get data. */
- for (i = 0; (i < 4) && (i < *length); i++)
- data[i] = (CAN_RDLxR(canport, fifo_id) >> (8 * i)) & 0xFF;
-
- for (i = 4; (i < 8) && (i < *length); i++)
- data[i] = (CAN_RDHxR(canport, fifo_id) >> (8 * (i - 4))) & 0xFF;
-
- /* Release the FIFO. */
- if (release)
- can_fifo_release(CAN1, 0);
-}
diff --git a/lib/stm32/f1/scb.c b/lib/stm32/f1/crc.c
index e59134e..505fb79 100644
--- a/lib/stm32/f1/scb.c
+++ b/lib/stm32/f1/crc.c
@@ -1,8 +1,14 @@
+/** @defgroup crc_file CRC
+
+@ingroup STM32F1xx
+
+@brief <b>libopencm3 STM32F1xx CRC</b>
+
+*/
+
/*
* This file is part of the libopencm3 project.
*
- * Copyright (C) 2010 Gareth McMullin <gareth@blacksphere.co.nz>
- *
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
@@ -17,19 +23,7 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
-#include <libopencm3/stm32/f1/scb.h>
-
-void scb_reset_core(void)
-{
- SCB_AIRCR = SCB_AIRCR_VECTKEY | SCB_AIRCR_VECTRESET;
-}
+#include <libopencm3/stm32/crc.h>
+#include <libopencm3/stm32/common/crc_common_all.h>
-void scb_reset_system(void)
-{
- SCB_AIRCR = SCB_AIRCR_VECTKEY | SCB_AIRCR_SYSRESETREQ;
-}
-void scb_set_priority_grouping(u32 prigroup)
-{
- SCB_AIRCR = SCB_AIRCR_VECTKEY | prigroup;
-}
diff --git a/lib/stm32/f1/desig.c b/lib/stm32/f1/dac.c
index 7ae968e..90dc029 100644
--- a/lib/stm32/f1/desig.c
+++ b/lib/stm32/f1/dac.c
@@ -1,8 +1,14 @@
+/** @defgroup dac_file DAC
+
+@ingroup STM32F1xx
+
+@brief <b>libopencm3 STM32F1xx DAC</b>
+
+*/
+
/*
* This file is part of the libopencm3 project.
*
- * Copyright (C) 2012 Karl Palsson <karlp@ŧweak.net.au>
- *
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
@@ -17,21 +23,6 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
-#include <libopencm3/stm32/f1/desig.h>
-
-u16 desig_get_flash_size(void)
-{
- return DESIG_FLASH_SIZE;
-}
+#include <libopencm3/stm32/dac.h>
+#include <libopencm3/stm32/common/dac_common_all.h>
-void desig_get_unique_id(u32 result[])
-{
- // Could also just return a pointer to the start? read it as they wish?
- u16 bits15_0 = DESIG_UID_15_0;
- u32 bits31_16 = DESIG_UID_31_16;
- u32 bits63_32 = DESIG_UID_63_32;
- u32 bits95_64 = DESIG_UID_95_64;
- result[0] = bits95_64;
- result[1] = bits63_32;
- result[2] = bits31_16 << 16 | bits15_0;
-}
diff --git a/lib/stm32/f1/dma.c b/lib/stm32/f1/dma.c
index 04cb8a1..f22baef 100644
--- a/lib/stm32/f1/dma.c
+++ b/lib/stm32/f1/dma.c
@@ -1,29 +1,14 @@
-/** @defgroup STM32F1xx-dma-file DMA
+/** @defgroup dma_file DMA
@ingroup STM32F1xx
-@brief <b>libopencm3 STM32F1xx DMA Controller</b>
+@brief <b>libopencm3 STM32F1xx DMA</b>
-@version 1.0.0
-
-@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
-
-@date 18 August 2012
-
-This library supports the DMA
-Control System in the STM32F1xx series of ARM Cortex Microcontrollers
-by ST Microelectronics. It can provide for two DMA controllers,
-one with 7 channels and one with 5. Channels are hardware dedicated
-and each is shared with a number of different sources (only one can be
-used at a time, under the responsibility of the programmer).
+*/
-LGPL License Terms @ref lgpl_license
- */
/*
* This file is part of the libopencm3 project.
*
- * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
- *
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
@@ -38,330 +23,6 @@ LGPL License Terms @ref lgpl_license
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
-/**@{*/
-
-#include <libopencm3/stm32/f1/dma.h>
-
-/*-----------------------------------------------------------------------------*/
-/** @brief DMA Channel Reset
-
-The channel is disabled and configuration registers are cleared.
-
-@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
-@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
-*/
-
-void dma_channel_reset(u32 dma, u8 channel)
-{
- /* Disable channel. */
- DMA_CCR(dma, channel) &= ~DMA_CCR_EN;
- /* Reset config bits. */
- DMA_CCR(dma, channel) = 0;
- /* Reset data transfer number. */
- DMA_CNDTR(dma, channel) = 0;
- /* Reset peripheral address. */
- DMA_CPAR(dma, channel) = 0;
- /* Reset memory address. */
- DMA_CMAR(dma, channel) = 0;
- /* Reset interrupt flags. */
- DMA_IFCR(dma) |= DMA_IFCR_CIF(channel);
-}
-
-/*-----------------------------------------------------------------------------*/
-/** @brief DMA Channel Enable Memory to Memory Transfers
-
-Memory to memory transfers do not require a trigger to activate each transfer.
-Transfers begin immediately the channel has been enabled, and proceed without
-intervention.
-
-@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
-@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
-*/
-
-void dma_enable_mem2mem_mode(u32 dma, u8 channel)
-{
- DMA_CCR(dma, channel) |= DMA_CCR_MEM2MEM;
- DMA_CCR(dma, channel) &= ~DMA_CCR_CIRC;
-}
-
-/*-----------------------------------------------------------------------------*/
-/** @brief DMA Channel Set Priority
-
-Channel Priority has four levels: low to very high. This has precedence over the
-hardware priority.
-
-@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
-@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
-@param[in] prio unsigned int32. Priority level @ref dma_ch_pri.
-*/
-
-void dma_set_priority(u32 dma, u8 channel, u32 prio)
-{
- DMA_CCR(dma, channel) &= ~(DMA_CCR_PL_MASK);
- DMA_CCR(dma, channel) |= prio;
-}
-
-/*-----------------------------------------------------------------------------*/
-/** @brief DMA Channel Set Memory Word Width
-
-Set the memory word width 8 bits, 16 bits, or 32 bits. Refer to datasheet for
-alignment information if the source and destination widths do not match.
-
-@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
-@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
-@param[in] mem_size unsigned int32. Memory word width @ref dma_ch_memwidth.
-*/
-
-void dma_set_memory_size(u32 dma, u8 channel, u32 mem_size)
-{
-
- DMA_CCR(dma, channel) &= ~(DMA_CCR_MSIZE_MASK);
- DMA_CCR(dma, channel) |= mem_size;
-}
-
-/*-----------------------------------------------------------------------------*/
-/** @brief DMA Channel Set Peripheral Word Width
-
-Set the peripheral word width 8 bits, 16 bits, or 32 bits. Refer to datasheet for
-alignment information if the source and destination widths do not match, or
-if the peripheral does not support byte or half-word writes.
-
-@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
-@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
-@param[in] peripheral_size unsigned int32. Peripheral word width @ref dma_ch_perwidth.
-*/
-
-void dma_set_peripheral_size(u32 dma, u8 channel, u32 peripheral_size)
-{
- DMA_CCR(dma, channel) &= ~(DMA_CCR_PSIZE_MASK);
- DMA_CCR(dma, channel) |= peripheral_size;
-}
-
-/*-----------------------------------------------------------------------------*/
-/** @brief DMA Channel Enable Memory Increment after Transfer
-
-Following each transfer the current memory address is incremented by
-1, 2 or 4 depending on the data size set in @ref dma_set_memory_size. The
-value held by the base memory address register is unchanged.
-
-@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
-@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
-*/
-
-void dma_enable_memory_increment_mode(u32 dma, u8 channel)
-{
- DMA_CCR(dma, channel) |= DMA_CCR_MINC;
-}
-
-/*-----------------------------------------------------------------------------*/
-/** @brief DMA Channel Disable Memory Increment after Transfer
-
-@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
-@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
-*/
-
-void dma_enable_peripheral_increment_mode(u32 dma, u8 channel)
-{
- DMA_CCR(dma, channel) |= DMA_CCR_PINC;
-}
-
-/*-----------------------------------------------------------------------------*/
-/** @brief DMA Channel Enable Memory Circular Mode
-
-After the number of bytes/words to be transferred has been completed, the
-original transfer block size, memory and peripheral base addresses are
-reloaded and the process repeats.
-
-@note This cannot be used with memory to memory mode, which is explictly
-disabled here.
-
-@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
-@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
-*/
-
-void dma_enable_circular_mode(u32 dma, u8 channel)
-{
- DMA_CCR(dma, channel) |= DMA_CCR_CIRC;
- DMA_CCR(dma, channel) &= ~DMA_CCR_MEM2MEM;
-}
-
-/*-----------------------------------------------------------------------------*/
-/** @brief DMA Channel Enable Transfers from a Peripheral
-
-The data direction is set to read from a peripheral.
-
-@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
-@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
-*/
-
-void dma_set_read_from_peripheral(u32 dma, u8 channel)
-{
- DMA_CCR(dma, channel) &= ~DMA_CCR_DIR;
-}
-
-/*-----------------------------------------------------------------------------*/
-/** @brief DMA Channel Enable Transfers from Memory
-
-The data direction is set to read from memory.
-
-@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
-@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
-*/
-
-void dma_set_read_from_memory(u32 dma, u8 channel)
-{
- DMA_CCR(dma, channel) |= DMA_CCR_DIR;
-}
-
-/*-----------------------------------------------------------------------------*/
-/** @brief DMA Channel Enable Interrupt on Transfer Error
-
-@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
-@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
-*/
-
-void dma_enable_transfer_error_interrupt(u32 dma, u8 channel)
-{
- DMA_CCR(dma, channel) |= DMA_CCR_TEIE;
-}
-
-/*-----------------------------------------------------------------------------*/
-/** @brief DMA Channel Disable Interrupt on Transfer Error
-
-@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
-@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
-*/
-
-void dma_disable_transfer_error_interrupt(u32 dma, u8 channel)
-{
- DMA_CCR(dma, channel) &= ~DMA_CCR_TEIE;
-}
-
-/*-----------------------------------------------------------------------------*/
-/** @brief DMA Channel Enable Interrupt on Transfer Half Complete
-
-@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
-@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
-*/
-
-void dma_enable_half_transfer_interrupt(u32 dma, u8 channel)
-{
- DMA_CCR(dma, channel) |= DMA_CCR_HTIE;
-}
-
-/*-----------------------------------------------------------------------------*/
-/** @brief DMA Channel Disable Interrupt on Transfer Half Complete
-
-@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
-@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
-*/
-
-void dma_disable_half_transfer_interrupt(u32 dma, u8 channel)
-{
- DMA_CCR(dma, channel) &= ~DMA_CCR_HTIE;
-}
-
-/*-----------------------------------------------------------------------------*/
-/** @brief DMA Channel Enable Interrupt on Transfer Complete
-
-@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
-@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
-*/
-
-void dma_enable_transfer_complete_interrupt(u32 dma, u8 channel)
-{
- DMA_CCR(dma, channel) |= DMA_CCR_TCIE;
-}
-
-/*-----------------------------------------------------------------------------*/
-/** @brief DMA Channel Disable Interrupt on Transfer Complete
-
-@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
-@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
-*/
-
-void dma_disable_transfer_complete_interrupt(u32 dma, u8 channel)
-{
- DMA_CCR(dma, channel) &= ~DMA_CCR_TCIE;
-}
-
-/*-----------------------------------------------------------------------------*/
-/** @brief DMA Channel Enable
-
-@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
-@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
-*/
-
-void dma_enable_channel(u32 dma, u8 channel)
-{
- DMA_CCR(dma, channel) |= DMA_CCR_EN;
-}
-
-/*-----------------------------------------------------------------------------*/
-/** @brief DMA Channel Disable
-
-@note The DMA channel registers retain their values when the channel is disabled.
-
-@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
-@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
-*/
-
-void dma_disable_channel(u32 dma, u8 channel)
-{
- DMA_CCR(dma, channel) &= ~DMA_CCR_EN;
-}
-
-/*-----------------------------------------------------------------------------*/
-/** @brief DMA Channel Set the Peripheral Address
-
-Set the address of the peripheral register to or from which data is to be transferred.
-Refer to the documentation for the specific peripheral.
-
-@note The DMA channel must be disabled before setting this address. This function
-has no effect if the channel is enabled.
-
-@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
-@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
-@param[in] address unsigned int32. Peripheral Address.
-*/
-
-void dma_set_peripheral_address(u32 dma, u8 channel, u32 address)
-{
- if (!(DMA_CCR(dma, channel) & DMA_CCR_EN))
- DMA_CPAR(dma, channel) = (u32) address;
-}
-
-/*-----------------------------------------------------------------------------*/
-/** @brief DMA Channel Set the Base Memory Address
-
-@note The DMA channel must be disabled before setting this address. This function
-has no effect if the channel is enabled.
-
-@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
-@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
-@param[in] address unsigned int32. Memory Initial Address.
-*/
-
-void dma_set_memory_address(u32 dma, u8 channel, u32 address)
-{
- if (!(DMA_CCR(dma, channel) & DMA_CCR_EN))
- DMA_CMAR(dma, channel) = (u32) address;
-}
-
-/*-----------------------------------------------------------------------------*/
-/** @brief DMA Channel Set the Transfer Block Size
-
-@note The DMA channel must be disabled before setting this count value. The count
-is not changed if the channel is enabled.
-
-@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
-@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
-@param[in] number unsigned int16. Number of data words to transfer (65535 maximum).
-*/
-
-void dma_set_number_of_data(u32 dma, u8 channel, u16 number)
-{
- DMA_CNDTR(dma, channel) = number;
-}
-/**@}*/
+#include <libopencm3/stm32/dma.h>
+#include <libopencm3/stm32/common/dma_common_f13.h>
diff --git a/lib/stm32/f1/flash.c b/lib/stm32/f1/flash.c
index 232086c..49f182c 100644
--- a/lib/stm32/f1/flash.c
+++ b/lib/stm32/f1/flash.c
@@ -22,22 +22,22 @@
void flash_prefetch_buffer_enable(void)
{
- FLASH_ACR |= FLASH_PRFTBE;
+ FLASH_ACR |= FLASH_ACR_PRFTBE;
}
void flash_prefetch_buffer_disable(void)
{
- FLASH_ACR &= ~FLASH_PRFTBE;
+ FLASH_ACR &= ~FLASH_ACR_PRFTBE;
}
void flash_halfcycle_enable(void)
{
- FLASH_ACR |= FLASH_HLFCYA;
+ FLASH_ACR |= FLASH_ACR_HLFCYA;
}
void flash_halfcycle_disable(void)
{
- FLASH_ACR &= ~FLASH_HLFCYA;
+ FLASH_ACR &= ~FLASH_ACR_HLFCYA;
}
void flash_set_ws(u32 ws)
@@ -53,33 +53,33 @@ void flash_set_ws(u32 ws)
void flash_unlock(void)
{
/* Authorize the FPEC access. */
- FLASH_KEYR = FLASH_KEY1;
- FLASH_KEYR = FLASH_KEY2;
+ FLASH_KEYR = FLASH_KEYR_KEY1;
+ FLASH_KEYR = FLASH_KEYR_KEY2;
}
void flash_lock(void)
{
- FLASH_CR |= FLASH_LOCK;
+ FLASH_CR |= FLASH_CR_LOCK;
}
void flash_clear_pgerr_flag(void)
{
- FLASH_SR |= FLASH_PGERR;
+ FLASH_SR |= FLASH_SR_PGERR;
}
void flash_clear_eop_flag(void)
{
- FLASH_SR |= FLASH_EOP;
+ FLASH_SR |= FLASH_SR_EOP;
}
void flash_clear_wrprterr_flag(void)
{
- FLASH_SR |= FLASH_WRPRTERR;
+ FLASH_SR |= FLASH_SR_WRPRTERR;
}
void flash_clear_bsy_flag(void)
{
- FLASH_SR &= ~FLASH_BSY;
+ FLASH_SR &= ~FLASH_SR_BSY;
}
void flash_clear_status_flags(void)
@@ -92,13 +92,14 @@ void flash_clear_status_flags(void)
void flash_unlock_option_bytes(void)
{
- FLASH_OPTKEYR = FLASH_KEY1;
- FLASH_OPTKEYR = FLASH_KEY2;
+ /* F1 uses same keys for flash and option */
+ FLASH_OPTKEYR = FLASH_KEYR_KEY1;
+ FLASH_OPTKEYR = FLASH_KEYR_KEY2;
}
void flash_wait_for_last_operation(void)
{
- while ((FLASH_SR & FLASH_BSY) == FLASH_BSY)
+ while ((FLASH_SR & FLASH_SR_BSY) == FLASH_SR_BSY)
;
}
@@ -108,7 +109,7 @@ void flash_program_word(u32 address, u32 data)
flash_wait_for_last_operation();
/* Enable writes to flash. */
- FLASH_CR |= FLASH_PG;
+ FLASH_CR |= FLASH_CR_PG;
/* Program the first half of the word. */
(*(volatile u16 *)address) = (u16)data;
@@ -123,67 +124,67 @@ void flash_program_word(u32 address, u32 data)
flash_wait_for_last_operation();
/* Disable writes to flash. */
- FLASH_CR &= ~FLASH_PG;
+ FLASH_CR &= ~FLASH_CR_PG;
}
void flash_program_half_word(u32 address, u16 data)
{
flash_wait_for_last_operation();
- FLASH_CR |= FLASH_PG;
+ FLASH_CR |= FLASH_CR_PG;
(*(volatile u16 *)address) = data;
flash_wait_for_last_operation();
- FLASH_CR &= ~FLASH_PG; /* Disable the PG bit. */
+ FLASH_CR &= ~FLASH_CR_PG; /* Disable the PG bit. */
}
void flash_erase_page(u32 page_address)
{
flash_wait_for_last_operation();
- FLASH_CR |= FLASH_PER;
+ FLASH_CR |= FLASH_CR_PER;
FLASH_AR = page_address;
- FLASH_CR |= FLASH_STRT;
+ FLASH_CR |= FLASH_CR_STRT;
flash_wait_for_last_operation();
- FLASH_CR &= ~FLASH_PER;
+ FLASH_CR &= ~FLASH_CR_PER;
}
void flash_erase_all_pages(void)
{
flash_wait_for_last_operation();
- FLASH_CR |= FLASH_MER; /* Enable mass erase. */
- FLASH_CR |= FLASH_STRT; /* Trigger the erase. */
+ FLASH_CR |= FLASH_CR_MER; /* Enable mass erase. */
+ FLASH_CR |= FLASH_CR_STRT; /* Trigger the erase. */
flash_wait_for_last_operation();
- FLASH_CR &= ~FLASH_MER; /* Disable mass erase. */
+ FLASH_CR &= ~FLASH_CR_MER; /* Disable mass erase. */
}
void flash_erase_option_bytes(void)
{
flash_wait_for_last_operation();
- if ((FLASH_CR & FLASH_OPTWRE) == 0)
+ if ((FLASH_CR & FLASH_CR_OPTWRE) == 0)
flash_unlock_option_bytes();
- FLASH_CR |= FLASH_OPTER; /* Enable option byte erase. */
- FLASH_CR |= FLASH_STRT;
+ FLASH_CR |= FLASH_CR_OPTER; /* Enable option byte erase. */
+ FLASH_CR |= FLASH_CR_STRT;
flash_wait_for_last_operation();
- FLASH_CR &= ~FLASH_OPTER; /* Disable option byte erase. */
+ FLASH_CR &= ~FLASH_CR_OPTER; /* Disable option byte erase. */
}
void flash_program_option_bytes(u32 address, u16 data)
{
flash_wait_for_last_operation();
- if ((FLASH_CR & FLASH_OPTWRE) == 0)
+ if ((FLASH_CR & FLASH_CR_OPTWRE) == 0)
flash_unlock_option_bytes();
- FLASH_CR |= FLASH_OPTPG; /* Enable option byte programming. */
+ FLASH_CR |= FLASH_CR_OPTPG; /* Enable option byte programming. */
(*(volatile u16 *)address) = data;
flash_wait_for_last_operation();
- FLASH_CR &= ~FLASH_OPTPG; /* Disable option byte programming. */
+ FLASH_CR &= ~FLASH_CR_OPTPG; /* Disable option byte programming. */
}
diff --git a/lib/stm32/f1/gpio.c b/lib/stm32/f1/gpio.c
index 0602012..2b33cad 100644
--- a/lib/stm32/f1/gpio.c
+++ b/lib/stm32/f1/gpio.c
@@ -1,4 +1,4 @@
-/** @defgroup STM32F1xx_gpio_file GPIO
+/** @defgroup gpio_file GPIO
@ingroup STM32F1xx
@@ -11,9 +11,6 @@
@date 18 August 2012
-This library supports the General Purpose I/O System in the STM32F1xx series
-of ARM Cortex Microcontrollers by ST Microelectronics.
-
Each I/O port has 16 individually configurable bits. Many I/O pins share GPIO
functionality with a number of alternate functions and must be configured to the
alternate function mode if these are to be accessed. A feature is available to
@@ -55,7 +52,7 @@ Example 1: Digital input on port C12
@endcode
LGPL License Terms @ref lgpl_license
- */
+*/
/*
* This file is part of the libopencm3 project.
*
@@ -75,25 +72,10 @@ LGPL License Terms @ref lgpl_license
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
-/*
- * Basic GPIO handling API.
- *
- * Examples:
- * gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_2_MHZ,
- * GPIO_CNF_OUTPUT_PUSHPULL, GPIO12);
- * gpio_set(GPIOB, GPIO4);
- * gpio_clear(GPIOG, GPIO2 | GPIO9);
- * gpio_get(GPIOC, GPIO1);
- * gpio_toggle(GPIOA, GPIO7 | GPIO8);
- * reg16 = gpio_port_read(GPIOD);
- * gpio_port_write(GPIOF, 0xc8fe);
- *
- * TODO:
- * - GPIO remapping support
- */
-/**@{*/
+#include <libopencm3/stm32/gpio.h>
+#include <libopencm3/stm32/common/gpio_common_all.h>
-#include <libopencm3/stm32/f1/gpio.h>
+/**@{*/
/*-----------------------------------------------------------------------------*/
/** @brief Set GPIO Pin Mode
@@ -146,116 +128,6 @@ void gpio_set_mode(u32 gpioport, u8 mode, u8 cnf, u16 gpios)
}
/*-----------------------------------------------------------------------------*/
-/** @brief Set a Group of Pins Atomic
-
-Set one or more pins of the given GPIO port to 1 in an atomic operation.
-
-@param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id
-@param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id
- If multiple pins are to be changed, use logical OR '|' to separate them.
-*/
-void gpio_set(u32 gpioport, u16 gpios)
-{
- GPIO_BSRR(gpioport) = gpios;
-}
-
-/*-----------------------------------------------------------------------------*/
-/** @brief Clear a Group of Pins Atomic
-
-Clear one or more pins of the given GPIO port to 0 in an atomic operation.
-
-@param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id
-@param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id
- If multiple pins are to be changed, use logical OR '|' to separate them.
-*/
-void gpio_clear(u32 gpioport, u16 gpios)
-{
- GPIO_BRR(gpioport) = gpios;
-}
-
-/*-----------------------------------------------------------------------------*/
-/** @brief Read a Group of Pins.
-
-@param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id
-@param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id
- If multiple pins are to be read, use logical OR '|' to separate them.
-@return Unsigned int16 value of the pin values. The bit position of the pin value
- returned corresponds to the pin number.
-*/
-u16 gpio_get(u32 gpioport, u16 gpios)
-{
- return gpio_port_read(gpioport) & gpios;
-}
-
-/*-----------------------------------------------------------------------------*/
-/** @brief Toggle a Group of Pins
-
-Toggle one or more pins of the given GPIO port. This is not an atomic operation.
-
-@param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id
-@param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id
- If multiple pins are to be changed, use logical OR '|' to separate them.
-*/
-void gpio_toggle(u32 gpioport, u16 gpios)
-{
- GPIO_ODR(gpioport) ^= gpios;
-}
-
-/*-----------------------------------------------------------------------------*/
-/** @brief Read from a Port
-
-Read the current value of the given GPIO port. Only the lower 16 bits contain
-valid pin data.
-
-@param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id
-@return Unsigned int16. The value held in the specified GPIO port.
-*/
-u16 gpio_port_read(u32 gpioport)
-{
- return (u16)GPIO_IDR(gpioport);
-}
-
-/*-----------------------------------------------------------------------------*/
-/** @brief Write to a Port
-
-Write a value to the given GPIO port.
-
-@param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id
-@param[in] data Unsigned int16. The value to be written to the GPIO port.
-*/
-void gpio_port_write(u32 gpioport, u16 data)
-{
- GPIO_ODR(gpioport) = data;
-}
-
-/*-----------------------------------------------------------------------------*/
-/** @brief Lock the Configuration of a Group of Pins
-
-The configuration of one or more pins of the given GPIO port is locked. There is
-no mechanism to unlock these via software. Unlocking occurs at the next reset.
-
-@param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id
-@param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id
- If multiple pins are to be locked, use logical OR '|' to separate them.
-*/
-void gpio_port_config_lock(u32 gpioport, u16 gpios)
-{
- u32 reg32;
-
- /* Special "Lock Key Writing Sequence", see datasheet. */
- GPIO_LCKR(gpioport) = GPIO_LCKK | gpios; /* Set LCKK. */
- GPIO_LCKR(gpioport) = ~GPIO_LCKK & gpios; /* Clear LCKK. */
- GPIO_LCKR(gpioport) = GPIO_LCKK | gpios; /* Set LCKK. */
- reg32 = GPIO_LCKR(gpioport); /* Read LCKK. */
- reg32 = GPIO_LCKR(gpioport); /* Read LCKK again. */
-
- /* Tell the compiler the variable is actually used. It will get optimized out anyways. */
- reg32 = reg32;
-
- /* If (reg32 & GPIO_LCKK) is true, the lock is now active. */
-}
-
-/*-----------------------------------------------------------------------------*/
/** @brief Map the EVENTOUT signal
Enable the EVENTOUT signal and select the port and pin to be used.
@@ -292,7 +164,7 @@ value cannot be ascertained from the hardware.
*/
void gpio_primary_remap(u8 swjdisable, u32 maps)
{
- AFIO_MAPR = swjdisable | (maps & 0x1FFFFF);
+ AFIO_MAPR |= swjdisable | (maps & 0x1FFFFF);
}
/*-----------------------------------------------------------------------------*/
@@ -310,7 +182,7 @@ The AFIO remapping feature is used only with the STM32F10x series.
*/
void gpio_secondary_remap(u32 maps)
{
- AFIO_MAPR2 = maps;
+ AFIO_MAPR2 |= maps;
}
/**@}*/
diff --git a/lib/stm32/f1/i2c.c b/lib/stm32/f1/i2c.c
new file mode 100644
index 0000000..2d86bf3
--- /dev/null
+++ b/lib/stm32/f1/i2c.c
@@ -0,0 +1,28 @@
+/** @defgroup i2c_file I2C
+
+@ingroup STM32F1xx
+
+@brief <b>libopencm3 STM32F1xx I2C</b>
+
+*/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopencm3/stm32/i2c.h>
+#include <libopencm3/stm32/common/i2c_common_all.h>
+
diff --git a/lib/stm32/f1/iwdg.c b/lib/stm32/f1/iwdg.c
new file mode 100644
index 0000000..85cf18c
--- /dev/null
+++ b/lib/stm32/f1/iwdg.c
@@ -0,0 +1,28 @@
+/** @defgroup iwdg_file IWDG
+
+@ingroup STM32F1xx
+
+@brief <b>libopencm3 STM32F1xx Independent Watchdog Timer</b>
+
+*/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopencm3/stm32/iwdg.h>
+#include <libopencm3/stm32/common/iwdg_common_all.h>
+
diff --git a/lib/stm32/f1/rcc.c b/lib/stm32/f1/rcc.c
index ab3350b..707c931 100644
--- a/lib/stm32/f1/rcc.c
+++ b/lib/stm32/f1/rcc.c
@@ -71,6 +71,12 @@ void rcc_osc_ready_int_clear(osc_t osc)
case PLL:
RCC_CIR |= RCC_CIR_PLLRDYC;
break;
+ case PLL2:
+ RCC_CIR |= RCC_CIR_PLL2RDYC;
+ break;
+ case PLL3:
+ RCC_CIR |= RCC_CIR_PLL3RDYC;
+ break;
case HSE:
RCC_CIR |= RCC_CIR_HSERDYC;
break;
@@ -98,6 +104,12 @@ void rcc_osc_ready_int_enable(osc_t osc)
case PLL:
RCC_CIR |= RCC_CIR_PLLRDYIE;
break;
+ case PLL2:
+ RCC_CIR |= RCC_CIR_PLL2RDYIE;
+ break;
+ case PLL3:
+ RCC_CIR |= RCC_CIR_PLL3RDYIE;
+ break;
case HSE:
RCC_CIR |= RCC_CIR_HSERDYIE;
break;
@@ -125,6 +137,12 @@ void rcc_osc_ready_int_disable(osc_t osc)
case PLL:
RCC_CIR &= ~RCC_CIR_PLLRDYIE;
break;
+ case PLL2:
+ RCC_CIR &= ~RCC_CIR_PLL2RDYIE;
+ break;
+ case PLL3:
+ RCC_CIR &= ~RCC_CIR_PLL3RDYIE;
+ break;
case HSE:
RCC_CIR &= ~RCC_CIR_HSERDYIE;
break;
@@ -153,6 +171,12 @@ int rcc_osc_ready_int_flag(osc_t osc)
case PLL:
return ((RCC_CIR & RCC_CIR_PLLRDYF) != 0);
break;
+ case PLL2:
+ return ((RCC_CIR & RCC_CIR_PLL2RDYF) != 0);
+ break;
+ case PLL3:
+ return ((RCC_CIR & RCC_CIR_PLL3RDYF) != 0);
+ break;
case HSE:
return ((RCC_CIR & RCC_CIR_HSERDYF) != 0);
break;
@@ -203,6 +227,12 @@ void rcc_wait_for_osc_ready(osc_t osc)
case PLL:
while ((RCC_CR & RCC_CR_PLLRDY) == 0);
break;
+ case PLL2:
+ while ((RCC_CR & RCC_CR_PLL2RDY) == 0);
+ break;
+ case PLL3:
+ while ((RCC_CR & RCC_CR_PLL3RDY) == 0);
+ break;
case HSE:
while ((RCC_CR & RCC_CR_HSERDY) == 0);
break;
@@ -238,6 +268,12 @@ void rcc_osc_on(osc_t osc)
case PLL:
RCC_CR |= RCC_CR_PLLON;
break;
+ case PLL2:
+ RCC_CR |= RCC_CR_PLL2ON;
+ break;
+ case PLL3:
+ RCC_CR |= RCC_CR_PLL3ON;
+ break;
case HSE:
RCC_CR |= RCC_CR_HSEON;
break;
@@ -273,6 +309,12 @@ void rcc_osc_off(osc_t osc)
case PLL:
RCC_CR &= ~RCC_CR_PLLON;
break;
+ case PLL2:
+ RCC_CR &= ~RCC_CR_PLL2ON;
+ break;
+ case PLL3:
+ RCC_CR &= ~RCC_CR_PLL3ON;
+ break;
case HSE:
RCC_CR &= ~RCC_CR_HSEON;
break;
@@ -331,6 +373,8 @@ void rcc_osc_bypass_enable(osc_t osc)
RCC_BDCR |= RCC_BDCR_LSEBYP;
break;
case PLL:
+ case PLL2:
+ case PLL3:
case HSI:
case LSI:
/* Do nothing, only HSE/LSE allowed here. */
@@ -361,6 +405,8 @@ void rcc_osc_bypass_disable(osc_t osc)
RCC_BDCR &= ~RCC_BDCR_LSEBYP;
break;
case PLL:
+ case PLL2:
+ case PLL3:
case HSI:
case LSI:
/* Do nothing, only HSE/LSE allowed here. */
@@ -485,6 +531,40 @@ void rcc_set_pll_multiplication_factor(u32 mul)
}
/*-----------------------------------------------------------------------------*/
+/** @brief RCC Set the PLL2 Multiplication Factor.
+
+@note This only has effect when the PLL is disabled.
+
+@param[in] mul Unsigned int32. PLL multiplication factor @ref rcc_cfgr_pmf
+*/
+
+void rcc_set_pll2_multiplication_factor(u32 mul)
+{
+ u32 reg32;
+
+ reg32 = RCC_CFGR2;
+ reg32 &= ~((1 << 11) | (1 << 10) | (1 << 9) | (1 << 8));
+ RCC_CFGR2 = (reg32 | (mul << 8));
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief RCC Set the PLL3 Multiplication Factor.
+
+@note This only has effect when the PLL is disabled.
+
+@param[in] mul Unsigned int32. PLL multiplication factor @ref rcc_cfgr_pmf
+*/
+
+void rcc_set_pll3_multiplication_factor(u32 mul)
+{
+ u32 reg32;
+
+ reg32 = RCC_CFGR2;
+ reg32 &= ~((1 << 15) | (1 << 14) | (1 << 13) | (1 << 12));
+ RCC_CFGR2 = (reg32 | (mul << 12));
+}
+
+/*-----------------------------------------------------------------------------*/
/** @brief RCC Set the PLL Clock Source.
@note This only has effect when the PLL is disabled.
@@ -602,6 +682,36 @@ void rcc_set_usbpre(u32 usbpre)
RCC_CFGR = (reg32 | (usbpre << 22));
}
+void rcc_set_prediv1(u32 prediv)
+{
+ u32 reg32;
+ reg32 = RCC_CFGR2;
+ reg32 &= ~(1 << 3) | (1 << 2) | (1 << 1) | (1 << 0);
+ RCC_CFGR2 |= (reg32 | prediv);
+}
+
+void rcc_set_prediv2(u32 prediv)
+{
+ u32 reg32;
+ reg32 = RCC_CFGR2;
+ reg32 &= ~(1 << 7) | (1 << 6) | (1 << 5) | (1 << 4);
+ RCC_CFGR2 |= (reg32 | (prediv << 4));
+}
+
+void rcc_set_prediv1_source(u32 rccsrc)
+{
+ RCC_CFGR2 &= ~(1 << 16);
+ RCC_CFGR2 |= (rccsrc << 16);
+}
+
+void rcc_set_mco(u32 mcosrc)
+{
+ u32 reg32;
+ reg32 = RCC_CFGR;
+ reg32 &= ~((1 << 27) | (1 << 26) | (1 << 25) | (1 << 24));
+ RCC_CFGR |= (reg32 | (mcosrc << 24));
+}
+
/*-----------------------------------------------------------------------------*/
/** @brief RCC Get the System Clock Source.
@@ -651,7 +761,7 @@ void rcc_clock_setup_in_hsi_out_64mhz(void)
* 1WS from 24-48MHz
* 2WS from 48-72MHz
*/
- flash_set_ws(FLASH_LATENCY_2WS);
+ flash_set_ws(FLASH_ACR_LATENCY_2WS);
/*
* Set the PLL multiplication factor to 16.
@@ -704,7 +814,7 @@ void rcc_clock_setup_in_hsi_out_48mhz(void)
* 1WS from 24-48MHz
* 2WS from 48-72MHz
*/
- flash_set_ws(FLASH_LATENCY_1WS);
+ flash_set_ws(FLASH_ACR_LATENCY_1WS);
/*
* Set the PLL multiplication factor to 12.
@@ -755,7 +865,7 @@ void rcc_clock_setup_in_hsi_out_24mhz(void) {
* 1WS from 24-48MHz
* 2WS from 48-72MHz
*/
- flash_set_ws(FLASH_LATENCY_0WS);
+ flash_set_ws(FLASH_ACR_LATENCY_0WS);
/*
* Set the PLL multiplication factor to 6.
@@ -812,7 +922,7 @@ void rcc_clock_setup_in_hse_8mhz_out_24mhz(void)
* 1WS from 24-48MHz
* 2WS from 48-72MHz
*/
- flash_set_ws(FLASH_LATENCY_0WS);
+ flash_set_ws(FLASH_ACR_LATENCY_0WS);
/*
* Set the PLL multiplication factor to 3.
@@ -875,7 +985,7 @@ void rcc_clock_setup_in_hse_8mhz_out_72mhz(void)
* 1WS from 24-48MHz
* 2WS from 48-72MHz
*/
- flash_set_ws(FLASH_LATENCY_2WS);
+ flash_set_ws(FLASH_ACR_LATENCY_2WS);
/*
* Set the PLL multiplication factor to 9.
@@ -938,7 +1048,7 @@ void rcc_clock_setup_in_hse_12mhz_out_72mhz(void)
* 1WS from 24-48MHz
* 2WS from 48-72MHz
*/
- flash_set_ws(FLASH_LATENCY_2WS);
+ flash_set_ws(FLASH_ACR_LATENCY_2WS);
/*
* Set the PLL multiplication factor to 9.
@@ -1001,7 +1111,7 @@ void rcc_clock_setup_in_hse_16mhz_out_72mhz(void)
* 1WS from 24-48MHz
* 2WS from 48-72MHz
*/
- flash_set_ws(FLASH_LATENCY_2WS);
+ flash_set_ws(FLASH_ACR_LATENCY_2WS);
/*
* Set the PLL multiplication factor to 9.
@@ -1031,6 +1141,63 @@ void rcc_clock_setup_in_hse_16mhz_out_72mhz(void)
}
/*-----------------------------------------------------------------------------*/
+/** @brief RCC Set System Clock PLL at 72MHz from HSE at 25MHz
+
+*/
+
+void rcc_clock_setup_in_hse_25mhz_out_72mhz(void)
+{
+ /* Enable external high-speed oscillator 25MHz. */
+ rcc_osc_on(HSE);
+ rcc_wait_for_osc_ready(HSE);
+ rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSECLK);
+
+ /*
+ * Sysclk runs with 72MHz -> 2 waitstates.
+ * 0WS from 0-24MHz
+ * 1WS from 24-48MHz
+ * 2WS from 48-72MHz
+ */
+ flash_set_ws(FLASH_ACR_LATENCY_2WS);
+
+ /*
+ * Set prescalers for AHB, ADC, ABP1, ABP2.
+ * Do this before touching the PLL (TODO: why?).
+ */
+ rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 72MHz Max. 72MHz */
+ rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV6); /* Set. 12MHz Max. 14MHz */
+ rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 36MHz Max. 36MHz */
+ rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 72MHz Max. 72MHz */
+
+ /* Set pll2 prediv and multiplier */
+ rcc_set_prediv2(RCC_CFGR2_PREDIV2_DIV5);
+ rcc_set_pll2_multiplication_factor(RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL8);
+
+ /* Enable PLL2 oscillator and wait for it to stabilize */
+ rcc_osc_on(PLL2);
+ rcc_wait_for_osc_ready(PLL2);
+
+ /* Set pll1 prediv/multiplier, prediv1 src, and usb predivider */
+ rcc_set_pllxtpre(RCC_CFGR_PLLXTPRE_HSE_CLK);
+ rcc_set_prediv1_source(RCC_CFGR2_PREDIV1SRC_PLL2_CLK);
+ rcc_set_prediv1(RCC_CFGR2_PREDIV_DIV5);
+ rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_PLL_CLK_MUL9);
+ rcc_set_pll_source(RCC_CFGR_PLLSRC_PREDIV1_CLK);
+ rcc_set_usbpre(RCC_CFGR_USBPRE_PLL_VCO_CLK_DIV3);
+
+ /* enable PLL1 and wait for it to stabilize */
+ rcc_osc_on(PLL);
+ rcc_wait_for_osc_ready(PLL);
+
+ /* Select PLL as SYSCLK source. */
+ rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK);
+
+ /* Set the peripheral clock frequencies used */
+ rcc_ppre1_frequency = 36000000;
+ rcc_ppre2_frequency = 72000000;
+}
+
+/*-----------------------------------------------------------------------------*/
/** @brief RCC Reset the backup domain
The backup domain register is reset to disable all controls.
diff --git a/lib/stm32/f1/rtc.c b/lib/stm32/f1/rtc.c
index 08a4953..cfc5f5b 100644
--- a/lib/stm32/f1/rtc.c
+++ b/lib/stm32/f1/rtc.c
@@ -67,6 +67,8 @@ void rtc_awake_from_off(osc_t clock_source)
RCC_BDCR |= (1 << 9) | (1 << 8);
break;
case PLL:
+ case PLL2:
+ case PLL3:
case HSI:
/* Unusable clock source, here to prevent warnings. */
/* Turn off clock sources to RTC. */
diff --git a/lib/stm32/f1/spi.c b/lib/stm32/f1/spi.c
new file mode 100644
index 0000000..3be5c23
--- /dev/null
+++ b/lib/stm32/f1/spi.c
@@ -0,0 +1,28 @@
+/** @defgroup spi_file SPI
+
+@ingroup STM32F1xx
+
+@brief <b>libopencm3 STM32F1xx SPI</b>
+
+*/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopencm3/stm32/spi.h>
+#include <libopencm3/stm32/common/spi_common_all.h>
+
diff --git a/lib/stm32/f1/timer.c b/lib/stm32/f1/timer.c
deleted file mode 100644
index 384eaaf..0000000
--- a/lib/stm32/f1/timer.c
+++ /dev/null
@@ -1,1948 +0,0 @@
-/** @defgroup STM32F1xx-timer-file Timers
-
-@ingroup STM32F1xx
-
-@brief <b>libopencm3 STM32F1xx Timers</b>
-
-@version 1.0.0
-
-@author @htmlonly &copy; @endhtmlonly 2010 Edward Cheeseman <evbuilder@users.sourceforge.org>
-
-@date 18 August 2012
-
-This library supports the General Purpose and Advanced Control Timers for
-the STM32F1xx series of ARM Cortex Microcontrollers by ST Microelectronics.
-
-The STM32F1xx series have four general purpose timers (2-5), while some have
-an additional two advanced timers (1,8), and some have two basic timers (6,7).
-Some of the larger devices have additional general purpose timers (9-14).
-
-@todo Add timer DMA burst settings
-
-@section tim_api_ex Basic TIMER handling API.
-
-Enable the timer clock first. The timer mode sets the clock division ratio,
-the count alignment (edge or centred) and count direction. Finally enable the timer.
-
-The timer output compare block produces a signal that can be configured for
-output to a pin or passed to other peripherals for use as a trigger. In all cases
-the output compare mode must be set to define how the output responds to a compare
-match, and the output must be enabled. If output to a pin is required, enable the
-appropriate GPIO clock and set the pin to alternate output mode.
-
-Example: Timer 2 with 2x clock divide, edge aligned and up counting.
-@code
- rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_TIM2EN);
- timer_reset(TIM2);
- timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT_MUL_2,
- TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
- ...
- timer_set_period(TIM2, 1000);
- timer_enable_counter(TIM2);
-@endcode
-Example: Timer 1 with PWM output, no clock divide and centre alignment. Set the
-Output Compare mode to PWM and enable the output of channel 1. Note that for the
-advanced timers the break functionality must be enabled before the signal will
-appear at the output, even though break is not being used. This is in addition to
-the normal output enable. Enable the alternate function clock (APB2 only) and port A
-clock. Set ports A8 and A9 (timer 1 channel 1 compare outputs) to alternate function
-push-pull outputs where the PWM output will appear.
-
-@code
- rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN | RCC_APB2ENR_AFIOEN);
- gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ,
- GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO8 | GPIO9);
- rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_TIM1EN);
- timer_reset(TIM1);
- timer_set_mode(TIM1, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_CENTER_1, TIM_CR1_DIR_UP);
- timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_PWM2);
- timer_enable_oc_output(TIM1, TIM_OC1);
- timer_enable_break_main_output(TIM1);
- timer_set_oc_value(TIM1, TIM_OC1, 200);
- timer_set_period(TIM1, 1000);
- timer_enable_counter(TIM1);
-@endcode
-
-@todo input capture example
-
-*/
-/*
- * This file is part of the libopencm3 project.
- *
- * Copyright (C) 2010 Edward Cheeseman <evbuilder@users.sourceforge.org>
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library. If not, see <http://www.gnu.org/licenses/>.
- */
-
-/*
- * Basic TIMER handling API.
- *
- * Examples:
- * timer_set_mode(TIM1, TIM_CR1_CKD_CK_INT_MUL_2,
- * TIM_CR1_CMS_CENTRE_3, TIM_CR1_DIR_UP);
- */
-
-/**@{*/
-
-#include <libopencm3/stm32/timer.h>
-#include <libopencm3/stm32/f1/rcc.h>
-
-/*---------------------------------------------------------------------------*/
-/** @brief Reset a Timer.
-
-The counter and all its associated configuration registers
-are placed in the reset condition. The reset is effected via the RCC peripheral reset
-system.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base
- (TIM9 .. TIM14 not yet supported here).
-*/
-
-void timer_reset(u32 timer_peripheral)
-{
- switch (timer_peripheral) {
- case TIM1:
- rcc_peripheral_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM1RST);
- rcc_peripheral_clear_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM1RST);
- break;
- case TIM2:
- rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM2RST);
- rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM2RST);
- break;
- case TIM3:
- rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM3RST);
- rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM3RST);
- break;
- case TIM4:
- rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM4RST);
- rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM4RST);
- break;
- case TIM5:
- rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM5RST);
- rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM5RST);
- break;
- case TIM6:
- rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM6RST);
- rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM6RST);
- break;
- case TIM7:
- rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM7RST);
- rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM7RST);
- break;
- case TIM8:
- rcc_peripheral_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM8RST);
- rcc_peripheral_clear_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM8RST);
- break;
-/* These timers are not supported in libopencm3 yet */
-/*
- case TIM9:
- rcc_peripheral_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM9RST);
- rcc_peripheral_clear_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM9RST);
- break;
- case TIM10:
- rcc_peripheral_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM10RST);
- rcc_peripheral_clear_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM10RST);
- break;
- case TIM11:
- rcc_peripheral_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM11RST);
- rcc_peripheral_clear_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM11RST);
- break;
- case TIM12:
- rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM12RST);
- rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM12RST);
- break;
- case TIM13:
- rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM13RST);
- rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM13RST);
- break;
- case TIM14:
- rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM14RST);
- rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM14RST);
- break;
-*/
- }
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Enable Interrupts for a Timer
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base
-@param[in] irq Unsigned int32. @ref tim_irq_enable. Logical OR of all interrupt enable bits to be set
-*/
-
-void timer_enable_irq(u32 timer_peripheral, u32 irq)
-{
- TIM_DIER(timer_peripheral) |= irq;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Disable Interrupts for a Timer.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base
-@param[in] irq Unsigned int32. @ref tim_irq_enable. Logical OR of all interrupt enable bits to be cleared
-*/
-
-void timer_disable_irq(u32 timer_peripheral, u32 irq)
-{
- TIM_DIER(timer_peripheral) &= ~irq;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Return Interrupt Source.
-
-Returns true if the specified interrupt flag (UIF, TIF or CCxIF, with BIF or COMIF
-for advanced timers) was set and the interrupt was enabled. If the specified flag
-is not an interrupt flag, the function returns false.
-
-@todo Timers 6-7, 9-14 have fewer interrupts, but invalid flags are not caught here.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base
-@param[in] flag Unsigned int32. Status register flag @ref tim_sr_values.
-@returns boolean: flag set.
-*/
-
-bool timer_interrupt_source(u32 timer_peripheral, u32 flag)
-{
-/* flag not set or interrupt disabled or not an interrupt source */
- if (((TIM_SR(timer_peripheral) & TIM_DIER(timer_peripheral) & flag) == 0) ||
- (flag > TIM_SR_BIF)) return false;
-/* Only an interrupt source for advanced timers */
- if ((flag == TIM_SR_BIF) || (flag == TIM_SR_COMIF))
- return ((timer_peripheral == TIM1) || (timer_peripheral == TIM8));
- return true;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Read a Status Flag.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base
-@param[in] flag Unsigned int32. Status register flag @ref tim_sr_values.
-@returns boolean: flag set.
-*/
-
-bool timer_get_flag(u32 timer_peripheral, u32 flag)
-{
- if ((TIM_SR(timer_peripheral) & flag) != 0) {
- return true;
- }
-
- return false;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Clear a Status Flag.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base
-@param[in] flag Unsigned int32. @ref tim_sr_values. Status register flag.
-*/
-
-void timer_clear_flag(u32 timer_peripheral, u32 flag)
-{
- TIM_SR(timer_peripheral) &= ~flag;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Set the Timer Mode.
-
-The modes are:
-
-@li Clock divider ratio (to form the sampling clock for the input filters,
-and the dead-time clock in the advanced timers 1 and 8)
-@li Edge/centre alignment
-@li Count direction
-
-The alignment and count direction are effective only for timers 1 to 5 and 8
-while the clock divider ratio is effective for all timers except 6,7
-The remaining timers are limited hardware timers which do not support these mode
-settings.
-
-@note: When center alignment mode is selected, count direction is controlled by
-hardware and cannot be written. The count direction setting has no effect
-in this case.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base (TIM1, TIM2 ... TIM5, TIM8)
-@param[in] clock_div Unsigned int32. Clock Divider Ratio in bits 8,9: @ref tim_x_cr1_cdr
-@param[in] alignment Unsigned int32. Alignment bits in 5,6: @ref tim_x_cr1_cms
-@param[in] direction Unsigned int32. Count direction in bit 4,: @ref tim_x_cr1_dir
-*/
-
-void timer_set_mode(u32 timer_peripheral, u32 clock_div,
- u32 alignment, u32 direction)
-{
- u32 cr1;
-
- cr1 = TIM_CR1(timer_peripheral);
-
- cr1 &= ~(TIM_CR1_CKD_CK_INT_MASK | TIM_CR1_CMS_MASK | TIM_CR1_DIR_DOWN);
-
- cr1 |= clock_div | alignment | direction;
-
- TIM_CR1(timer_peripheral) = cr1;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Set Input Filter and Dead-time Clock Divider Ratio.
-
-This forms the sampling clock for the input filters and the dead-time clock
-in the advanced timers 1 and 8, by division from the timer clock.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base
-@param[in] clock_div Unsigned int32. Clock Divider Ratio in bits 8,9: @ref tim_x_cr1_cdr
-*/
-
-void timer_set_clock_division(u32 timer_peripheral, u32 clock_div)
-{
- clock_div &= TIM_CR1_CKD_CK_INT_MASK;
- TIM_CR1(timer_peripheral) &= ~TIM_CR1_CKD_CK_INT_MASK;
- TIM_CR1(timer_peripheral) |= clock_div;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Enable Auto-Reload Buffering.
-
-During counter operation this causes the counter to be loaded from its
-auto-reload register only at the next update event.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base
-*/
-
-void timer_enable_preload(u32 timer_peripheral)
-{
- TIM_CR1(timer_peripheral) |= TIM_CR1_ARPE;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Disable Auto-Reload Buffering.
-
-This causes the counter to be loaded immediately with a new count value when the
-auto-reload register is written, so that the new value becomes effective for the
-current count cycle rather than for the cycle following an update event.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base
-*/
-
-void timer_disable_preload(u32 timer_peripheral)
-{
- TIM_CR1(timer_peripheral) &= ~TIM_CR1_ARPE;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Specify the counter alignment mode.
-
-The mode can be edge aligned or centered.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base
-@param[in] alignment Unsigned int32. Alignment bits in 5,6: @ref tim_x_cr1_cms
-*/
-
-void timer_set_alignment(u32 timer_peripheral, u32 alignment)
-{
- alignment &= TIM_CR1_CMS_MASK;
- TIM_CR1(timer_peripheral) &= ~TIM_CR1_CMS_MASK;
- TIM_CR1(timer_peripheral) |= alignment;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Set the Timer to Count Up.
-
-This has no effect if the timer is set to center aligned.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base
-*/
-
-void timer_direction_up(u32 timer_peripheral)
-{
- TIM_CR1(timer_peripheral) &= ~TIM_CR1_DIR_DOWN;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Set the Timer to Count Down.
-
-This has no effect if the timer is set to center aligned.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base
-*/
-
-void timer_direction_down(u32 timer_peripheral)
-{
- TIM_CR1(timer_peripheral) |= TIM_CR1_DIR_DOWN;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Enable the Timer for One Cycle and Stop.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base
-*/
-
-void timer_one_shot_mode(u32 timer_peripheral)
-{
- TIM_CR1(timer_peripheral) |= TIM_CR1_OPM;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Enable the Timer to Run Continuously.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base
-*/
-
-void timer_continuous_mode(u32 timer_peripheral)
-{
- TIM_CR1(timer_peripheral) &= ~TIM_CR1_OPM;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Set the Timer to Generate Update IRQ or DMA on any Event.
-
-The events which will generate an interrupt or DMA request can be
-@li a counter underflow/overflow,
-@li a forced update,
-@li an event from the slave mode controller.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base
-*/
-
-void timer_update_on_any(u32 timer_peripheral)
-{
- TIM_CR1(timer_peripheral) &= ~TIM_CR1_URS;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Set the Timer to Generate Update IRQ or DMA only from Under/Overflow Events.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base
-*/
-
-void timer_update_on_overflow(u32 timer_peripheral)
-{
- TIM_CR1(timer_peripheral) |= TIM_CR1_URS;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Enable Timer Update Events.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base
-*/
-
-void timer_enable_update_event(u32 timer_peripheral)
-{
- TIM_CR1(timer_peripheral) &= ~TIM_CR1_UDIS;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Disable Timer Update Events.
-
-Update events are not generated and the shadow registers keep their values.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base
-*/
-
-void timer_disable_update_event(u32 timer_peripheral)
-{
- TIM_CR1(timer_peripheral) |= TIM_CR1_UDIS;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Enable the timer to start counting.
-
-This should be called after the timer initial configuration has been completed.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base
-*/
-
-void timer_enable_counter(u32 timer_peripheral)
-{
- TIM_CR1(timer_peripheral) |= TIM_CR1_CEN;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Stop the timer from counting.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base
-*/
-
-void timer_disable_counter(u32 timer_peripheral)
-{
- TIM_CR1(timer_peripheral) &= ~TIM_CR1_CEN;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Set Timer Output Idle States High.
-
-This determines the value of the timer output compare when it enters idle state.
-
-@sa @ref timer_set_oc_idle_state_set
-
-@note This setting is only valid for the advanced timers.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base
-@param[in] outputs Unsigned int32. Timer Output Idle State Controls @ref tim_x_cr2_ois.
-If several settings are to be made, use the logical OR of the output control values.
-*/
-
-void timer_set_output_idle_state(u32 timer_peripheral, u32 outputs)
-{
- if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
- TIM_CR2(timer_peripheral) |= outputs & TIM_CR2_OIS_MASK;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Set Timer Output Idle States Low.
-
-This determines the value of the timer output compare when it enters idle state.
-
-@sa @ref timer_set_oc_idle_state_unset
-
-@note This setting is only valid for the advanced timers.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base
-@param[in] outputs Unsigned int32. Timer Output Idle State Controls @ref tim_x_cr2_ois
-*/
-
-void timer_reset_output_idle_state(u32 timer_peripheral, u32 outputs)
-{
- if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
- TIM_CR2(timer_peripheral) &= ~(outputs & TIM_CR2_OIS_MASK);
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Set Timer 1 Input to XOR of Three Channels.
-
-The first timer capture input is formed from the XOR of the first three timer input
-channels 1, 2, 3.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base
-*/
-
-void timer_set_ti1_ch123_xor(u32 timer_peripheral)
-{
- TIM_CR2(timer_peripheral) |= TIM_CR2_TI1S;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Set Timer 1 Input to Channel 1.
-
-The first timer capture input is taken from the timer input channel 1 only.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base
-*/
-
-void timer_set_ti1_ch1(u32 timer_peripheral)
-{
- TIM_CR2(timer_peripheral) &= ~TIM_CR2_TI1S;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Set the Master Mode
-
-This sets the Trigger Output TRGO for synchronizing with slave timers or passing as
-an internal trigger to the ADC or DAC.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base
-@param[in] mode Unsigned int32. Master Mode @ref tim_mastermode
-*/
-
-void timer_set_master_mode(u32 timer_peripheral, u32 mode)
-{
- TIM_CR2(timer_peripheral) &= ~TIM_CR2_MMS_MASK;
- TIM_CR2(timer_peripheral) |= mode;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Set Timer DMA Requests on Capture/Compare Events.
-
-Capture/compare events will cause DMA requests to be generated.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base
-*/
-
-void timer_set_dma_on_compare_event(u32 timer_peripheral)
-{
- TIM_CR2(timer_peripheral) &= ~TIM_CR2_CCDS;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Set Timer DMA Requests on Update Events.
-
-Update events will cause DMA requests to be generated.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base
-*/
-
-void timer_set_dma_on_update_event(u32 timer_peripheral)
-{
- TIM_CR2(timer_peripheral) |= TIM_CR2_CCDS;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Enable Timer Capture/Compare Control Update with Trigger.
-
-If the capture/compare control bits CCxE, CCxNE and OCxM are set to be
-preloaded, they are updated by software generating the COMG event (@ref
-timer_generate_event) or when a rising edge occurs on the trigger input TRGI.
-
-@note This setting is only valid for the advanced timer channels with complementary
-outputs.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base
-*/
-
-void timer_enable_compare_control_update_on_trigger(u32 timer_peripheral)
-{
- if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
- TIM_CR2(timer_peripheral) |= TIM_CR2_CCUS;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Disable Timer Capture/Compare Control Update with Trigger.
-
-If the capture/compare control bits CCxE, CCxNE and OCxM are set to be
-preloaded, they are updated by software generating the COMG event (@ref
-timer_generate_event).
-
-@note This setting is only valid for the advanced timer channels with complementary
-outputs.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base
-*/
-
-void timer_disable_compare_control_update_on_trigger(u32 timer_peripheral)
-{
- if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
- TIM_CR2(timer_peripheral) &= ~TIM_CR2_CCUS;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Enable Timer Capture/Compare Control Preload.
-
-The capture/compare control bits CCxE, CCxNE and OCxM are set to be preloaded
-when a COM event occurs.
-
-@note This setting is only valid for the advanced timer channels with complementary
-outputs.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base
-*/
-
-void timer_enable_preload_complementry_enable_bits(u32 timer_peripheral)
-{
- if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
- TIM_CR2(timer_peripheral) |= TIM_CR2_CCPC;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Disable Timer Capture/Compare Control Preload.
-
-The capture/compare control bits CCxE, CCxNE and OCxM preload is disabled.
-
-@note This setting is only valid for the advanced timer channels with complementary
-outputs.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base
-*/
-
-void timer_disable_preload_complementry_enable_bits(u32 timer_peripheral)
-{
- if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
- TIM_CR2(timer_peripheral) &= ~TIM_CR2_CCPC;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Set the Value for the Timer Prescaler.
-
-The timer clock is prescaled by the 16 bit scale value plus 1.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base
-@param[in] value Unsigned int32. Prescaler values 0...0xFFFF.
-*/
-
-void timer_set_prescaler(u32 timer_peripheral, u32 value)
-{
- TIM_PSC(timer_peripheral) = value;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Set the Value for the Timer Repetition Counter.
-
-A timer update event is generated only after the specified number of repeat
-count cycles have been completed.
-
-@note This setting is only valid for the advanced timers.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base
-@param[in] value Unsigned int32. Repetition values 0...0xFF.
-*/
-
-void timer_set_repetition_counter(u32 timer_peripheral, u32 value)
-{
- if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
- TIM_RCR(timer_peripheral) = value;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Timer Set Period
-
-Specify the timer period in the auto-reload register.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base
-@param[in] period Unsigned int32. Period in counter clock ticks.
-*/
-
-void timer_set_period(u32 timer_peripheral, u32 period)
-{
- TIM_ARR(timer_peripheral) = period;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Timer Enable the Output Compare Clear Function
-
-When this is enabled, the output compare signal is cleared when a high is detected
-on the external trigger input. This works in the output compare and PWM modes only
-(not forced mode).
-The output compare signal remains off until the next update event.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base
-@param[in] oc_id enum ::tim_oc_id OC channel designators
- TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (no action taken)
-*/
-
-void timer_enable_oc_clear(u32 timer_peripheral, enum tim_oc_id oc_id)
-{
- switch (oc_id) {
- case TIM_OC1:
- TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1CE;
- break;
- case TIM_OC2:
- TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2CE;
- break;
- case TIM_OC3:
- TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3CE;
- break;
- case TIM_OC4:
- TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4CE;
- break;
- case TIM_OC1N:
- case TIM_OC2N:
- case TIM_OC3N:
- /* Ignoring as oc clear enable only applies to the whole channel. */
- break;
- }
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Timer Disable the Output Compare Clear Function
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base
-@param[in] oc_id enum ::tim_oc_id OC channel designators
- TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (no action taken)
-*/
-
-void timer_disable_oc_clear(u32 timer_peripheral, enum tim_oc_id oc_id)
-{
- switch (oc_id) {
- case TIM_OC1:
- TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC1CE;
- break;
- case TIM_OC2:
- TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC2CE;
- break;
- case TIM_OC3:
- TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC3CE;
- break;
- case TIM_OC4:
- TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC4CE;
- break;
- case TIM_OC1N:
- case TIM_OC2N:
- case TIM_OC3N:
- /* Ignoring as oc clear enable only applies to the whole channel. */
- break;
- }
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Timer Enable the Output Compare Fast Mode
-
-When this is enabled, the output compare signal is forced to the compare state
-by a trigger input, independently of the compare match. This speeds up the
-setting of the output compare to 3 clock cycles as opposed to at least 5 in the
-slow mode. This works in the PWM1 and PWM2 modes only.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base
-@param[in] oc_id enum ::tim_oc_id OC channel designators
- TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (no action taken)
-*/
-
-void timer_set_oc_fast_mode(u32 timer_peripheral, enum tim_oc_id oc_id)
-{
- switch (oc_id) {
- case TIM_OC1:
- TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1FE;
- break;
- case TIM_OC2:
- TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2FE;
- break;
- case TIM_OC3:
- TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3FE;
- break;
- case TIM_OC4:
- TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4FE;
- break;
- case TIM_OC1N:
- case TIM_OC2N:
- case TIM_OC3N:
- /* Ignoring as fast enable only applies to the whole channel. */
- break;
- }
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Timer Enable the Output Compare Slow Mode
-
-This disables the fast compare mode and the output compare depends on the
-counter and compare register values.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base
-@param[in] oc_id enum ::tim_oc_id OC channel designators
- TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (no action taken)
-*/
-
-void timer_set_oc_slow_mode(u32 timer_peripheral, enum tim_oc_id oc_id)
-{
- switch (oc_id) {
- case TIM_OC1:
- TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC1FE;
- break;
- case TIM_OC2:
- TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC2FE;
- break;
- case TIM_OC3:
- TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC3FE;
- break;
- case TIM_OC4:
- TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC4FE;
- break;
- case TIM_OC1N:
- case TIM_OC2N:
- case TIM_OC3N:
- /* Ignoring as this option applies to the whole channel. */
- break;
- }
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Timer Set Output Compare Mode
-
-Specifies how the comparator output will respond to a compare match. The mode can be:
-@li Frozen - the output does not respond to a match.
-@li Active - the output assumes the active state on the first match.
-@li Inactive - the output assumes the inactive state on the first match.
-@li Toggle - The output switches between active and inactive states on each match.
-@li Force inactive. The output is forced low regardless of the compare state.
-@li Force active. The output is forced high regardless of the compare state.
-@li PWM1 - The output is active when the counter is less than the compare register contents
-and inactive otherwise.
-@li PWM2 - The output is inactive when the counter is less than the compare register contents
-and active otherwise.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base
-@param[in] oc_id enum ::tim_oc_id OC channel designators
- TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (no action taken)
-@param[in] oc_mode enum ::tim_oc_mode. OC mode designators.
- TIM_OCM_FROZEN, TIM_OCM_ACTIVE, TIM_OCM_INACTIVE, TIM_OCM_TOGGLE,
- TIM_OCM_FORCE_LOW, TIM_OCM_FORCE_HIGH, TIM_OCM_PWM1, TIM_OCM_PWM2
-*/
-
-void timer_set_oc_mode(u32 timer_peripheral, enum tim_oc_id oc_id,
- enum tim_oc_mode oc_mode)
-{
- switch (oc_id) {
- case TIM_OC1:
- TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_CC1S_MASK;
- TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_CC1S_OUT;
- TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC1M_MASK;
- switch (oc_mode) {
- case TIM_OCM_FROZEN:
- TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_FROZEN;
- break;
- case TIM_OCM_ACTIVE:
- TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_ACTIVE;
- break;
- case TIM_OCM_INACTIVE:
- TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_INACTIVE;
- break;
- case TIM_OCM_TOGGLE:
- TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_TOGGLE;
- break;
- case TIM_OCM_FORCE_LOW:
- TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_FORCE_LOW;
- break;
- case TIM_OCM_FORCE_HIGH:
- TIM_CCMR1(timer_peripheral) |=
- TIM_CCMR1_OC1M_FORCE_HIGH;
- break;
- case TIM_OCM_PWM1:
- TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_PWM1;
- break;
- case TIM_OCM_PWM2:
- TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_PWM2;
- break;
- }
- break;
- case TIM_OC2:
- TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_CC2S_MASK;
- TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_CC2S_OUT;
- TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC2M_MASK;
- switch (oc_mode) {
- case TIM_OCM_FROZEN:
- TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_FROZEN;
- break;
- case TIM_OCM_ACTIVE:
- TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_ACTIVE;
- break;
- case TIM_OCM_INACTIVE:
- TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_INACTIVE;
- break;
- case TIM_OCM_TOGGLE:
- TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_TOGGLE;
- break;
- case TIM_OCM_FORCE_LOW:
- TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_FORCE_LOW;
- break;
- case TIM_OCM_FORCE_HIGH:
- TIM_CCMR1(timer_peripheral) |=
- TIM_CCMR1_OC2M_FORCE_HIGH;
- break;
- case TIM_OCM_PWM1:
- TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_PWM1;
- break;
- case TIM_OCM_PWM2:
- TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_PWM2;
- break;
- }
- break;
- case TIM_OC3:
- TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR2_CC3S_MASK;
- TIM_CCMR1(timer_peripheral) |= TIM_CCMR2_CC3S_OUT;
- TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC3M_MASK;
- switch (oc_mode) {
- case TIM_OCM_FROZEN:
- TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_FROZEN;
- break;
- case TIM_OCM_ACTIVE:
- TIM_CCMR1(timer_peripheral) |= TIM_CCMR2_OC3M_ACTIVE;
- break;
- case TIM_OCM_INACTIVE:
- TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_INACTIVE;
- break;
- case TIM_OCM_TOGGLE:
- TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_TOGGLE;
- break;
- case TIM_OCM_FORCE_LOW:
- TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_FORCE_LOW;
- break;
- case TIM_OCM_FORCE_HIGH:
- TIM_CCMR2(timer_peripheral) |=
- TIM_CCMR2_OC3M_FORCE_HIGH;
- break;
- case TIM_OCM_PWM1:
- TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_PWM1;
- break;
- case TIM_OCM_PWM2:
- TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_PWM2;
- break;
- }
- break;
- case TIM_OC4:
- TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR2_CC4S_MASK;
- TIM_CCMR1(timer_peripheral) |= TIM_CCMR2_CC4S_OUT;
- TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC4M_MASK;
- switch (oc_mode) {
- case TIM_OCM_FROZEN:
- TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_FROZEN;
- break;
- case TIM_OCM_ACTIVE:
- TIM_CCMR1(timer_peripheral) |= TIM_CCMR2_OC4M_ACTIVE;
- break;
- case TIM_OCM_INACTIVE:
- TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_INACTIVE;
- break;
- case TIM_OCM_TOGGLE:
- TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_TOGGLE;
- break;
- case TIM_OCM_FORCE_LOW:
- TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_FORCE_LOW;
- break;
- case TIM_OCM_FORCE_HIGH:
- TIM_CCMR2(timer_peripheral) |=
- TIM_CCMR2_OC4M_FORCE_HIGH;
- break;
- case TIM_OCM_PWM1:
- TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_PWM1;
- break;
- case TIM_OCM_PWM2:
- TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_PWM2;
- break;
- }
- break;
- case TIM_OC1N:
- case TIM_OC2N:
- case TIM_OC3N:
- /* Ignoring as this option applies to the whole channel. */
- break;
- }
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Timer Enable the Output Compare Preload Register
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base
-@param[in] oc_id enum ::tim_oc_id OC channel designators
- TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (no action taken)
-*/
-
-void timer_enable_oc_preload(u32 timer_peripheral, enum tim_oc_id oc_id)
-{
- switch (oc_id) {
- case TIM_OC1:
- TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1PE;
- break;
- case TIM_OC2:
- TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2PE;
- break;
- case TIM_OC3:
- TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3PE;
- break;
- case TIM_OC4:
- TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4PE;
- break;
- case TIM_OC1N:
- case TIM_OC2N:
- case TIM_OC3N:
- /* Ignoring as this option applies to the whole channel. */
- break;
- }
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Timer Disable the Output Compare Preload Register
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base
-@param[in] oc_id enum ::tim_oc_id OC channel designators
- TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (no action)
-*/
-
-void timer_disable_oc_preload(u32 timer_peripheral, enum tim_oc_id oc_id)
-{
- switch (oc_id) {
- case TIM_OC1:
- TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC1PE;
- break;
- case TIM_OC2:
- TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC2PE;
- break;
- case TIM_OC3:
- TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC3PE;
- break;
- case TIM_OC4:
- TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC4PE;
- break;
- case TIM_OC1N:
- case TIM_OC2N:
- case TIM_OC3N:
- /* Ignoring as this option applies to the whole channel. */
- break;
- }
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Timer Set the Output Polarity High
-
-The polarity of the channel output is set active high.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base
-@param[in] oc_id enum ::tim_oc_id OC channel designators
- TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (only for advanced timers 1 and 8)
-*/
-
-void timer_set_oc_polarity_high(u32 timer_peripheral, enum tim_oc_id oc_id)
-{
- switch (oc_id) {
- case TIM_OC1:
- TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC1P;
- break;
- case TIM_OC2:
- TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC2P;
- break;
- case TIM_OC3:
- TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC3P;
- break;
- case TIM_OC4:
- TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC4P;
- break;
- case TIM_OC1N:
- case TIM_OC2N:
- case TIM_OC3N:
- /* Ignoring as this option applies to TIM1 and TIM8 only. */
- break;
- }
-
- /* Acting for TIM1 and TIM8 only from here onwards. */
- if ((timer_peripheral != TIM1) && (timer_peripheral != TIM8))
- return;
-
- switch (oc_id) {
- case TIM_OC1N:
- TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC1NP;
- break;
- case TIM_OC2N:
- TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC2NP;
- break;
- case TIM_OC3N:
- TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC3NP;
- break;
- case TIM_OC1:
- case TIM_OC2:
- case TIM_OC3:
- case TIM_OC4:
- /* Ignoring as this option was already set above. */
- break;
- }
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Timer Set the Output Polarity Low
-
-The polarity of the channel output is set active low.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base
-@param[in] oc_id enum ::tim_oc_id OC channel designators
- TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (only for advanced timers 1 and 8)
-*/
-
-void timer_set_oc_polarity_low(u32 timer_peripheral, enum tim_oc_id oc_id)
-{
- switch (oc_id) {
- case TIM_OC1:
- TIM_CCER(timer_peripheral) |= TIM_CCER_CC1P;
- break;
- case TIM_OC2:
- TIM_CCER(timer_peripheral) |= TIM_CCER_CC2P;
- break;
- case TIM_OC3:
- TIM_CCER(timer_peripheral) |= TIM_CCER_CC3P;
- break;
- case TIM_OC4:
- TIM_CCER(timer_peripheral) |= TIM_CCER_CC4P;
- break;
- case TIM_OC1N:
- case TIM_OC2N:
- case TIM_OC3N:
- /* Ignoring as this option applies to TIM1 and TIM8 only. */
- break;
- }
-
- /* Acting for TIM1 and TIM8 only from here onwards. */
- if ((timer_peripheral != TIM1) && (timer_peripheral != TIM8))
- return;
-
- switch (oc_id) {
- case TIM_OC1N:
- TIM_CCER(timer_peripheral) |= TIM_CCER_CC1NP;
- break;
- case TIM_OC2N:
- TIM_CCER(timer_peripheral) |= TIM_CCER_CC2NP;
- break;
- case TIM_OC3N:
- TIM_CCER(timer_peripheral) |= TIM_CCER_CC3NP;
- break;
- case TIM_OC1:
- case TIM_OC2:
- case TIM_OC3:
- case TIM_OC4:
- /* Ignoring as this option was already set above. */
- break;
- }
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Timer Enable the Output Compare
-
-The channel output compare functionality is enabled.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base
-@param[in] oc_id enum ::tim_oc_id OC channel designators
- TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (only for advanced timers 1 and 8)
-*/
-
-void timer_enable_oc_output(u32 timer_peripheral, enum tim_oc_id oc_id)
-{
- switch (oc_id) {
- case TIM_OC1:
- TIM_CCER(timer_peripheral) |= TIM_CCER_CC1E;
- break;
- case TIM_OC2:
- TIM_CCER(timer_peripheral) |= TIM_CCER_CC2E;
- break;
- case TIM_OC3:
- TIM_CCER(timer_peripheral) |= TIM_CCER_CC3E;
- break;
- case TIM_OC4:
- TIM_CCER(timer_peripheral) |= TIM_CCER_CC4E;
- break;
- case TIM_OC1N:
- case TIM_OC2N:
- case TIM_OC3N:
- /* Ignoring as this option applies to TIM1 and TIM8 only. */
- break;
- }
-
- /* Acting for TIM1 and TIM8 only from here onwards. */
- if ((timer_peripheral != TIM1) && (timer_peripheral != TIM8))
- return;
-
- switch (oc_id) {
- case TIM_OC1N:
- TIM_CCER(timer_peripheral) |= TIM_CCER_CC1NE;
- break;
- case TIM_OC2N:
- TIM_CCER(timer_peripheral) |= TIM_CCER_CC2NE;
- break;
- case TIM_OC3N:
- TIM_CCER(timer_peripheral) |= TIM_CCER_CC3NE;
- break;
- case TIM_OC1:
- case TIM_OC2:
- case TIM_OC3:
- case TIM_OC4:
- /* Ignoring as this option was already set above. */
- break;
- }
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Timer Disable the Output Compare
-
-The channel output compare functionality is disabled.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base
-@param[in] oc_id enum ::tim_oc_id OC channel designators
- TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (only for advanced timers 1 and 8)
-*/
-
-void timer_disable_oc_output(u32 timer_peripheral, enum tim_oc_id oc_id)
-{
- switch (oc_id) {
- case TIM_OC1:
- TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC1E;
- break;
- case TIM_OC2:
- TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC2E;
- break;
- case TIM_OC3:
- TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC3E;
- break;
- case TIM_OC4:
- TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC4E;
- break;
- case TIM_OC1N:
- case TIM_OC2N:
- case TIM_OC3N:
- /* Ignoring as this option applies to TIM1 and TIM8 only. */
- break;
- }
-
- /* Acting for TIM1 and TIM8 only from here onwards. */
- if ((timer_peripheral != TIM1) && (timer_peripheral != TIM8))
- return;
-
- switch (oc_id) {
- case TIM_OC1N:
- TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC1NE;
- break;
- case TIM_OC2N:
- TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC2NE;
- break;
- case TIM_OC3N:
- TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC3NE;
- break;
- case TIM_OC1:
- case TIM_OC2:
- case TIM_OC3:
- case TIM_OC4:
- /* Ignoring as this option was already set above. */
- break;
- }
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Timer set Output Compare Idle State High
-
-@sa Similar function suitable for multiple OC idle state settings
-@ref timer_set_output_idle_state
-
-@note This setting is only valid for the advanced timers.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base
-@param[in] oc_id enum ::tim_oc_id OC channel designators
- TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (only for advanced timers 1 and 8)
-*/
-
-void timer_set_oc_idle_state_set(u32 timer_peripheral, enum tim_oc_id oc_id)
-{
- /* Acting for TIM1 and TIM8 only. */
- if ((timer_peripheral != TIM1) && (timer_peripheral != TIM8))
- return;
-
- switch (oc_id) {
- case TIM_OC1:
- TIM_CR2(timer_peripheral) |= TIM_CR2_OIS1;
- break;
- case TIM_OC1N:
- TIM_CR2(timer_peripheral) |= TIM_CR2_OIS1N;
- break;
- case TIM_OC2:
- TIM_CR2(timer_peripheral) |= TIM_CR2_OIS2;
- break;
- case TIM_OC2N:
- TIM_CR2(timer_peripheral) |= TIM_CR2_OIS2N;
- break;
- case TIM_OC3:
- TIM_CR2(timer_peripheral) |= TIM_CR2_OIS3;
- break;
- case TIM_OC3N:
- TIM_CR2(timer_peripheral) |= TIM_CR2_OIS3N;
- break;
- case TIM_OC4:
- TIM_CR2(timer_peripheral) |= TIM_CR2_OIS4;
- break;
- }
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Timer Set Output Compare Idle State Low
-
-@sa Similar function suitable for multiple OC idle state settings
-@ref timer_reset_output_idle_state
-
-@note This setting is only valid for the advanced timers.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base
-@param[in] oc_id enum ::tim_oc_id OC channel designators
- TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (only for advanced timers 1 and 8)
-*/
-
-void timer_set_oc_idle_state_unset(u32 timer_peripheral, enum tim_oc_id oc_id)
-{
- /* Acting for TIM1 and TIM8 only. */
- if ((timer_peripheral != TIM1) && (timer_peripheral != TIM8))
- return;
-
- switch (oc_id) {
- case TIM_OC1:
- TIM_CR2(timer_peripheral) &= ~TIM_CR2_OIS1;
- break;
- case TIM_OC1N:
- TIM_CR2(timer_peripheral) &= ~TIM_CR2_OIS1N;
- break;
- case TIM_OC2:
- TIM_CR2(timer_peripheral) &= ~TIM_CR2_OIS2;
- break;
- case TIM_OC2N:
- TIM_CR2(timer_peripheral) &= ~TIM_CR2_OIS2N;
- break;
- case TIM_OC3:
- TIM_CR2(timer_peripheral) &= ~TIM_CR2_OIS3;
- break;
- case TIM_OC3N:
- TIM_CR2(timer_peripheral) &= ~TIM_CR2_OIS3N;
- break;
- case TIM_OC4:
- TIM_CR2(timer_peripheral) &= ~TIM_CR2_OIS4;
- break;
- }
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Timer Set Output Compare Value
-
-This is a convenience function to set the OC preload register value for loading
-to the compare register.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base
- (TIM9 .. TIM14 not yet supported here).
-@param[in] oc_id enum ::tim_oc_id OC channel designators
- TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (no action taken)
-@param[in] value Unsigned int32. Compare value.
-*/
-
-void timer_set_oc_value(u32 timer_peripheral, enum tim_oc_id oc_id, u32 value)
-{
- switch (oc_id) {
- case TIM_OC1:
- TIM_CCR1(timer_peripheral) = value;
- break;
- case TIM_OC2:
- TIM_CCR2(timer_peripheral) = value;
- break;
- case TIM_OC3:
- TIM_CCR3(timer_peripheral) = value;
- break;
- case TIM_OC4:
- TIM_CCR4(timer_peripheral) = value;
- break;
- case TIM_OC1N:
- case TIM_OC2N:
- case TIM_OC3N:
- /* Ignoring as this option applies to the whole channel. */
- break;
- }
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Enable Output in Break
-
-Enables the output in the Break feature of an advanced timer. This does not
-enable the break functionality itself but only sets the Master Output Enable in
-the Break and Deadtime Register.
-
-@note This setting is only valid for the advanced timers.
-
-@note It is necessary to call this function to enable the output on an advanced
-timer <b>even if break or deadtime features are not being used</b>.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or TIM8
-*/
-
-void timer_enable_break_main_output(u32 timer_peripheral)
-{
- if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
- TIM_BDTR(timer_peripheral) |= TIM_BDTR_MOE;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Disable Output in Break
-
-Disables the output in the Break feature of an advanced timer. This clears
-the Master Output Enable in the Break and Deadtime Register.
-
-@note This setting is only valid for the advanced timers.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or TIM8
-*/
-
-void timer_disable_break_main_output(u32 timer_peripheral)
-{
- if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
- TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_MOE;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Enable Automatic Output in Break
-
-Enables the automatic output feature of the Break function of an advanced
-timer so that the output is re-enabled at the next update event following a
-break event.
-
-@note This setting is only valid for the advanced timers.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or TIM8
-*/
-
-void timer_enable_break_automatic_output(u32 timer_peripheral)
-{
- if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
- TIM_BDTR(timer_peripheral) |= TIM_BDTR_AOE;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Disable Automatic Output in Break
-
-Disables the automatic output feature of the Break function of an advanced
-timer so that the output is re-enabled at the next update event following a
-break event.
-
-@note This setting is only valid for the advanced timers.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or TIM8
-*/
-
-void timer_disable_break_automatic_output(u32 timer_peripheral)
-{
- if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
- TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_AOE;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Activate Break when Input High
-
-Sets the break function to activate when the break input becomes high.
-
-@note This setting is only valid for the advanced timers.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or TIM8
-*/
-
-void timer_set_break_polarity_high(u32 timer_peripheral)
-{
- if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
- TIM_BDTR(timer_peripheral) |= TIM_BDTR_BKP;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Activate Break when Input Low
-
-Sets the break function to activate when the break input becomes low.
-
-@note This setting is only valid for the advanced timers.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or TIM8
-*/
-
-void timer_set_break_polarity_low(u32 timer_peripheral)
-{
- if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
- TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_BKP;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Enable Break
-
-Enables the break function of an advanced timer.
-
-@note This setting is only valid for the advanced timers.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or TIM8
-*/
-
-void timer_enable_break(u32 timer_peripheral)
-{
- if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
- TIM_BDTR(timer_peripheral) |= TIM_BDTR_BKE;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Disable Break
-
-Disables the break function of an advanced timer.
-
-@note This setting is only valid for the advanced timers.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or TIM8
-*/
-
-void timer_disable_break(u32 timer_peripheral)
-{
- if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
- TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_BKE;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Enable Off-State in Run Mode
-
-Enables the off-state in run mode for the break function of an advanced
-timer in which the complementary outputs have been configured. It has no effect
-if no complementary output is present. When the capture-compare output is
-disabled while the complementary output is enabled, the output is set to its
-inactive level as defined by the output polarity.
-
-@note This setting is only valid for the advanced timers.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or TIM8
-*/
-
-void timer_set_enabled_off_state_in_run_mode(u32 timer_peripheral)
-{
- if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
- TIM_BDTR(timer_peripheral) |= TIM_BDTR_OSSR;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Disable Off-State in Run Mode
-
-Disables the off-state in run mode for the break function of an advanced
-timer in which the complementary outputs have been configured. It has no effect
-if no complementary output is present. When the capture-compare output is
-disabled, the output is also disabled.
-
-@note This setting is only valid for the advanced timers.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or TIM8
-*/
-
-void timer_set_disabled_off_state_in_run_mode(u32 timer_peripheral)
-{
- if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
- TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_OSSR;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Enable Off-State in Idle Mode
-
-Enables the off-state in idle mode for the break function of an advanced
-timer. When the master output is disabled the output is set to its
-inactive level as defined by the output polarity.
-
-@note This setting is only valid for the advanced timers.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or TIM8
-*/
-
-void timer_set_enabled_off_state_in_idle_mode(u32 timer_peripheral)
-{
- if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
- TIM_BDTR(timer_peripheral) |= TIM_BDTR_OSSI;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Disable Off-State in Idle Mode
-
-Disables the off-state in idle mode for the break function of an advanced
-timer. When the master output is disabled the output is also disabled.
-
-@note This setting is only valid for the advanced timers.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or TIM8
-*/
-
-void timer_set_disabled_off_state_in_idle_mode(u32 timer_peripheral)
-{
- if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
- TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_OSSI;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Set Lock Bits
-
-Set the lock bits for an advanced timer. Three levels of lock providing
-protection against software errors. Once written they cannot be changed until a
-timer reset has occurred.
-
-@note This setting is only valid for the advanced timers.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or TIM8
-@param[in] lock Unsigned int32. Lock specification @ref tim_lock
-*/
-
-void timer_set_break_lock(u32 timer_peripheral, u32 lock)
-{
- if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
- TIM_BDTR(timer_peripheral) |= lock;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Set Deadtime
-
-The deadtime and sampling clock (DTSC) is set in the clock division ratio part of the
-timer mode settings. The deadtime count is an 8 bit value defined in terms of the
-number of DTSC cycles:
-
-@li Bit 7 = 0, deadtime = bits(6:0)
-@li Bits 7:6 = 10, deadtime = 2x(64+bits(5:0))
-@li Bits 7:5 = 110, deadtime = 8x(32+bits(5:0))
-@li Bits 7:5 = 111, deadtime = 16x(32+bits(5:0))
-
-@note This setting is only valid for the advanced timers.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or TIM8
-@param[in] deadtime Unsigned int32. Deadtime count specification as defined above.
-*/
-
-void timer_set_deadtime(u32 timer_peripheral, u32 deadtime)
-{
- if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
- TIM_BDTR(timer_peripheral) |= deadtime;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Force generate a timer event.
-
-The event specification consists of 8 possible events that can be forced on the
-timer. The forced events are automatically cleared by hardware. The UG event is
-useful to cause shadow registers to be preloaded before the timer is started to
-avoid uncertainties in the first cycle in case an update event may never be
-generated.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base
-@param[in] event Unsigned int32. Event specification @ref tim_event_gen
-*/
-
-void timer_generate_event(u32 timer_peripheral, u32 event)
-{
- TIM_EGR(timer_peripheral) |= event;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Read Counter
-
-Read back the value of a timer's counter register contents
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base
-@returns Unsigned int32. Counter value.
-*/
-
-u32 timer_get_counter(u32 timer_peripheral)
-{
- return TIM_CNT(timer_peripheral);
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Set Counter
-
-Set the value of a timer's counter register contents.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base
-@param[in] Unsigned int32. Counter value.
-*/
-
-void timer_set_counter(u32 timer_peripheral, u32 count)
-{
- TIM_CNT(timer_peripheral) = count;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Set Input Capture Filter Parameters
-
-Set the input filter parameters for an input channel, specifying:
-@li the frequency of sampling from the Deadtime and Sampling clock
-(@see @ref timer_set_clock_division)
-@li the number of events that must occur before a transition is considered valid.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base
-@param[in] ic ::tim_ic_id. Input Capture channel designator.
-@param[in] flt ::tim_ic_filter. Input Capture Filter identifier.
-*/
-
-void timer_ic_set_filter(u32 timer_peripheral, enum tim_ic_id ic, enum tim_ic_filter flt)
-{
- switch (ic) {
- case TIM_IC1:
- TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_IC1F_MASK;
- TIM_CCMR1(timer_peripheral) |= flt << 4;
- break;
- case TIM_IC2:
- TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_IC2F_MASK;
- TIM_CCMR1(timer_peripheral) |= flt << 12;
- break;
- case TIM_IC3:
- TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_IC3F_MASK;
- TIM_CCMR2(timer_peripheral) |= flt << 4;
- break;
- case TIM_IC4:
- TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_IC4F_MASK;
- TIM_CCMR2(timer_peripheral) |= flt << 12;
- break;
- }
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Set Input Capture Prescaler
-
-Set the number of events between each capture.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base
-@param[in] ic ::tim_ic_id. Input Capture channel designator.
-@param[in] psc ::tim_ic_psc. Input Capture sample clock prescaler.
-*/
-
-void timer_ic_set_prescaler(u32 timer_peripheral, enum tim_ic_id ic, enum tim_ic_psc psc)
-{
- switch (ic) {
- case TIM_IC1:
- TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_IC1PSC_MASK;
- TIM_CCMR1(timer_peripheral) |= psc << 2;
- break;
- case TIM_IC2:
- TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_IC2PSC_MASK;
- TIM_CCMR1(timer_peripheral) |= psc << 10;
- break;
- case TIM_IC3:
- TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_IC3PSC_MASK;
- TIM_CCMR2(timer_peripheral) |= psc << 4;
- break;
- case TIM_IC4:
- TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_IC4PSC_MASK;
- TIM_CCMR2(timer_peripheral) |= psc << 10;
- break;
- }
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Set Capture/Compare Channel Direction/Input
-
-The Capture/Compare channel is defined as output (compare) or input with the input
-mapping specified:
-
-@li channel is configured as output
-@li channel is configured as input and mapped on corresponding input
-@li channel is configured as input and mapped on alternate input
-(TI2 for channel 1, TI1 for channel 2, TI4 for channel 3, TI3 for channel 4)
-@li channel is configured as input and is mapped on TRC (requires an
-internal trigger input selected through TS bit
-
-@note not all combinations of the input and channel are valid, see datasheets.
-@note these parameters are writable only when the channel is off.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base
-@param[in] ic ::tim_ic_id. Input Capture channel designator.
-@param[in] in ::tim_ic_input. Input Capture channel direction and source input.
-*/
-
-void timer_ic_set_input(u32 timer_peripheral, enum tim_ic_id ic, enum tim_ic_input in)
-{
- in &= 3;
-
- if (((ic == TIM_IC2) || (ic == TIM_IC4)) &&
- ((in == TIM_IC_IN_TI1) || (in = TIM_IC_IN_TI2))) {
- /* Input select bits are flipped for these combinations */
- in ^= 3;
- }
-
- switch (ic) {
- case TIM_IC1:
- TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_CC1S_MASK;
- TIM_CCMR1(timer_peripheral) |= in;
- break;
- case TIM_IC2:
- TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_CC2S_MASK;
- TIM_CCMR1(timer_peripheral) |= in << 8;
- break;
- case TIM_IC3:
- TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_CC3S_MASK;
- TIM_CCMR2(timer_peripheral) |= in;
- break;
- case TIM_IC4:
- TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_CC4S_MASK;
- TIM_CCMR2(timer_peripheral) |= in << 8;
- break;
- }
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Set Input Polarity
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base
-@param[in] ic ::tim_ic_id. Input Capture channel designator.
-@param[in] pol ::tim_ic_pol. Input Capture polarity.
-*/
-
-void timer_ic_set_polarity(u32 timer_peripheral, enum tim_ic_id ic, enum tim_ic_pol pol)
-{
- if (pol)
- TIM_CCER(timer_peripheral) |= (0x2 << (ic * 4));
- else
- TIM_CCER(timer_peripheral) &= ~(0x2 << (ic * 4));
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Enable Timer Input Capture
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base
-@param[in] ic ::tim_ic_id. Input Capture channel designator.
-*/
-
-void timer_ic_enable(u32 timer_peripheral, enum tim_ic_id ic)
-{
- TIM_CCER(timer_peripheral) |= (0x1 << (ic * 4));
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Disable Timer Input Capture
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base
-@param[in] ic ::tim_ic_id. Input Capture channel designator.
-*/
-
-void timer_ic_disable(u32 timer_peripheral, enum tim_ic_id ic)
-{
- TIM_CCER(timer_peripheral) &= ~(0x1 << (ic * 4));
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Set External Trigger Filter Parameters for Slave
-
-Set the input filter parameters for the external trigger, specifying:
-@li the frequency of sampling from the Deadtime and Sampling clock
-(@see @ref timer_set_clock_division)
-@li the number of events that must occur before a transition is considered valid.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base
-@param[in] flt ::tim_ic_filter. Input Capture Filter identifier.
-*/
-
-void timer_slave_set_filter(u32 timer_peripheral, enum tim_ic_filter flt)
-{
- TIM_SMCR(timer_peripheral) &= ~TIM_SMCR_ETF_MASK;
- TIM_SMCR(timer_peripheral) |= flt << 8;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Set External Trigger Prescaler for Slave
-
-Set the external trigger frequency division ratio.
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base
-@param[in] psc ::tim_ic_psc. Input Capture sample clock prescaler.
-*/
-
-void timer_slave_set_prescaler(u32 timer_peripheral, enum tim_ic_psc psc)
-{
- TIM_SMCR(timer_peripheral) &= ~TIM_SMCR_ETPS_MASK;
- TIM_SMCR(timer_peripheral) |= psc << 12;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Set External Trigger Polarity for Slave
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base
-@param[in] pol ::tim_ic_pol. Input Capture polarity.
-*/
-
-void timer_slave_set_polarity(u32 timer_peripheral, enum tim_ic_pol pol)
-{
- if (pol)
- TIM_SMCR(timer_peripheral) |= TIM_SMCR_ETP;
- else
- TIM_SMCR(timer_peripheral) &= ~TIM_SMCR_ETP;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Set Slave Mode
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base
-@param[in] mode Unsigned int8. Slave mode @ref tim_sms
-*/
-
-void timer_slave_set_mode(u32 timer_peripheral, u8 mode)
-{
- TIM_SMCR(timer_peripheral) &= ~TIM_SMCR_SMS_MASK;
- TIM_SMCR(timer_peripheral) |= mode;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief Set Slave Trigger Source
-
-@param[in] timer_peripheral Unsigned int32. Timer register address base
-@param[in] trigger Unsigned int8. Slave trigger source @ref tim_ts
-*/
-
-void timer_slave_set_trigger(u32 timer_peripheral, u8 trigger)
-{
- TIM_SMCR(timer_peripheral) &= ~TIM_SMCR_TS_MASK;
- TIM_SMCR(timer_peripheral) |= trigger;
-}
-
-/* TODO Timer DMA burst */
-
-/**@}*/
-
diff --git a/lib/stm32/f1/usart.c b/lib/stm32/f1/usart.c
new file mode 100644
index 0000000..ecf2b06
--- /dev/null
+++ b/lib/stm32/f1/usart.c
@@ -0,0 +1,28 @@
+/** @defgroup usart_file USART
+
+@ingroup STM32F1xx
+
+@brief <b>libopencm3 STM32F1xx USART</b>
+
+*/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopencm3/stm32/usart.h>
+#include <libopencm3/stm32/common/usart_common_all.h>
+
diff --git a/lib/stm32/f1/vector.c b/lib/stm32/f1/vector.c
deleted file mode 100644
index f496ae4..0000000
--- a/lib/stm32/f1/vector.c
+++ /dev/null
@@ -1,296 +0,0 @@
-/*
- * This file is part of the libopencm3 project.
- *
- * Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#define WEAK __attribute__ ((weak))
-
-/* Symbols exported by the linker script(s): */
-extern unsigned _data_loadaddr, _data, _edata, _ebss, _stack;
-
-void main(void);
-void reset_handler(void);
-void blocking_handler(void);
-void null_handler(void);
-
-void WEAK nmi_handler(void);
-void WEAK hard_fault_handler(void);
-void WEAK mem_manage_handler(void);
-void WEAK bus_fault_handler(void);
-void WEAK usage_fault_handler(void);
-void WEAK sv_call_handler(void);
-void WEAK debug_monitor_handler(void);
-void WEAK pend_sv_handler(void);
-void WEAK sys_tick_handler(void);
-void WEAK wwdg_isr(void);
-void WEAK pvd_isr(void);
-void WEAK tamper_isr(void);
-void WEAK rtc_isr(void);
-void WEAK flash_isr(void);
-void WEAK rcc_isr(void);
-void WEAK exti0_isr(void);
-void WEAK exti1_isr(void);
-void WEAK exti2_isr(void);
-void WEAK exti3_isr(void);
-void WEAK exti4_isr(void);
-void WEAK dma1_channel1_isr(void);
-void WEAK dma1_channel2_isr(void);
-void WEAK dma1_channel3_isr(void);
-void WEAK dma1_channel4_isr(void);
-void WEAK dma1_channel5_isr(void);
-void WEAK dma1_channel6_isr(void);
-void WEAK dma1_channel7_isr(void);
-void WEAK adc1_2_isr(void);
-void WEAK usb_hp_can_tx_isr(void);
-void WEAK usb_lp_can_rx0_isr(void);
-void WEAK can_rx1_isr(void);
-void WEAK can_sce_isr(void);
-void WEAK exti9_5_isr(void);
-void WEAK tim1_brk_isr(void);
-void WEAK tim1_up_isr(void);
-void WEAK tim1_trg_com_isr(void);
-void WEAK tim1_cc_isr(void);
-void WEAK tim2_isr(void);
-void WEAK tim3_isr(void);
-void WEAK tim4_isr(void);
-void WEAK i2c1_ev_isr(void);
-void WEAK i2c1_er_isr(void);
-void WEAK i2c2_ev_isr(void);
-void WEAK i2c2_er_isr(void);
-void WEAK spi1_isr(void);
-void WEAK spi2_isr(void);
-void WEAK usart1_isr(void);
-void WEAK usart2_isr(void);
-void WEAK usart3_isr(void);
-void WEAK exti15_10_isr(void);
-void WEAK rtc_alarm_isr(void);
-void WEAK usb_wakeup_isr(void);
-void WEAK tim8_brk_isr(void);
-void WEAK tim8_up_isr(void);
-void WEAK tim8_trg_com_isr(void);
-void WEAK tim8_cc_isr(void);
-void WEAK adc3_isr(void);
-void WEAK fsmc_isr(void);
-void WEAK sdio_isr(void);
-void WEAK tim5_isr(void);
-void WEAK spi3_isr(void);
-void WEAK uart4_isr(void);
-void WEAK uart5_isr(void);
-void WEAK tim6_isr(void);
-void WEAK tim7_isr(void);
-void WEAK dma2_channel1_isr(void);
-void WEAK dma2_channel2_isr(void);
-void WEAK dma2_channel3_isr(void);
-void WEAK dma2_channel4_5_isr(void);
-void WEAK dma2_channel5_isr(void);
-void WEAK eth_isr(void);
-void WEAK eth_wkup_isr(void);
-void WEAK can2_tx_isr(void);
-void WEAK can2_rx0_isr(void);
-void WEAK can2_rx1_isr(void);
-void WEAK can2_sce_isr(void);
-void WEAK otg_fs_isr(void);
-
-
-__attribute__ ((section(".vectors")))
-void (*const vector_table[]) (void) = {
- (void*)&_stack, /* Addr: 0x0000_0000 */
- reset_handler, /* Addr: 0x0000_0004 */
- nmi_handler, /* Addr: 0x0000_0008 */
- hard_fault_handler, /* Addr: 0x0000_000C */
- mem_manage_handler, /* Addr: 0x0000_0010 */
- bus_fault_handler, /* Addr: 0x0000_0014 */
- usage_fault_handler, /* Addr: 0x0000_0018 */
- 0, 0, 0, 0, /* Reserved Addr: 0x0000_001C - 0x0000_002B */
- sv_call_handler, /* Addr: 0x0000_002C */
- debug_monitor_handler, /* Addr: 0x0000_0030*/
- 0, /* Reserved Addr: 0x0000_00034 */
- pend_sv_handler, /* Addr: 0x0000_0038 */
- sys_tick_handler, /* Addr: 0x0000_003C */
- wwdg_isr, /* Addr: 0x0000_0040 */
- pvd_isr, /* Addr: 0x0000_0044 */
- tamper_isr, /* Addr: 0x0000_0048 */
- rtc_isr, /* Addr: 0x0000_004C */
- flash_isr, /* Addr: 0x0000_0050 */
- rcc_isr, /* Addr: 0x0000_0054 */
- exti0_isr, /* Addr: 0x0000_0058 */
- exti1_isr, /* Addr: 0x0000_005C */
- exti2_isr, /* Addr: 0x0000_0060 */
- exti3_isr, /* Addr: 0x0000_0064 */
- exti4_isr, /* Addr: 0x0000_0068 */
- dma1_channel1_isr, /* Addr: 0x0000_006C */
- dma1_channel2_isr, /* Addr: 0x0000_0070 */
- dma1_channel3_isr, /* Addr: 0x0000_0074 */
- dma1_channel4_isr, /* Addr: 0x0000_0078 */
- dma1_channel5_isr, /* Addr: 0x0000_007C */
- dma1_channel6_isr, /* Addr: 0x0000_0080 */
- dma1_channel7_isr, /* Addr: 0x0000_0084 */
- adc1_2_isr, /* Addr: 0x0000_0088 */
- usb_hp_can_tx_isr, /* Addr: 0x0000_008C */
- usb_lp_can_rx0_isr, /* Addr: 0x0000_0090 */
- can_rx1_isr, /* Addr: 0x0000_0094 */
- can_sce_isr, /* Addr: 0x0000_0098 */
- exti9_5_isr, /* Addr: 0x0000_009C */
- tim1_brk_isr, /* Addr: 0x0000_00A0 */
- tim1_up_isr, /* Addr: 0x0000_00A4 */
- tim1_trg_com_isr, /* Addr: 0x0000_00A8 */
- tim1_cc_isr, /* Addr: 0x0000_00AC */
- tim2_isr, /* Addr: 0x0000_00B0 */
- tim3_isr, /* Addr: 0x0000_00B4 */
- tim4_isr, /* Addr: 0x0000_00B8 */
- i2c1_ev_isr, /* Addr: 0x0000_00BC */
- i2c1_er_isr, /* Addr: 0x0000_00C0 */
- i2c2_ev_isr, /* Addr: 0x0000_00C4 */
- i2c2_er_isr, /* Addr: 0x0000_00C8 */
- spi1_isr, /* Addr: 0x0000_00CC */
- spi2_isr, /* Addr: 0x0000_00D0 */
- usart1_isr, /* Addr: 0x0000_00D4 */
- usart2_isr, /* Addr: 0x0000_00D8 */
- usart3_isr, /* Addr: 0x0000_00DC */
- exti15_10_isr, /* Addr: 0x0000_00E0 */
- rtc_alarm_isr, /* Addr: 0x0000_00E4 */
- usb_wakeup_isr, /* Addr: 0x0000_00E8 */
- tim8_brk_isr, /* Addr: 0x0000_00EC */
- tim8_up_isr, /* Addr: 0x0000_00F0 */
- tim8_trg_com_isr, /* Addr: 0x0000_00F4 */
- tim8_cc_isr, /* Addr: 0x0000_00F8 */
- adc3_isr, /* Addr: 0x0000_00FC */
- fsmc_isr, /* Addr: 0x0000_0100 */
- sdio_isr, /* Addr: 0x0000_0104 */
- tim5_isr, /* Addr: 0x0000_0108 */
- spi3_isr, /* Addr: 0x0000_010C */
- uart4_isr, /* Addr: 0x0000_0110 */
- uart5_isr, /* Addr: 0x0000_0114 */
- tim6_isr, /* Addr: 0x0000_0118 */
- tim7_isr, /* Addr: 0x0000_011C */
- dma2_channel1_isr, /* Addr: 0x0000_0120 */
- dma2_channel2_isr, /* Addr: 0x0000_0124 */
- dma2_channel3_isr, /* Addr: 0x0000_0128 */
- dma2_channel4_5_isr, /* Addr: 0x0000_012C */
- dma2_channel5_isr, /* Addr: 0x0000_0130 */
- eth_isr, /* Addr: 0x0000_0134 */
- eth_wkup_isr, /* Addr: 0x0000_0138 */
- can2_tx_isr, /* Addr: 0x0000_013C */
- can2_rx0_isr, /* Addr: 0x0000_0140 */
- can2_rx1_isr, /* Addr: 0x0000_0144 */
- can2_sce_isr, /* Addr: 0x0000_0148 */
- otg_fs_isr, /* Addr: 0x0000_014C */
-};
-
-void reset_handler(void)
-{
- volatile unsigned *src, *dest;
-
- __asm__("MSR msp, %0" : : "r"(&_stack));
-
- for (src = &_data_loadaddr, dest = &_data; dest < &_edata; src++, dest++)
- *dest = *src;
-
- while (dest < &_ebss)
- *dest++ = 0;
-
- /* Call the application's entry point. */
- main();
-}
-
-void blocking_handler(void)
-{
- while (1) ;
-}
-
-void null_handler(void)
-{
- /* Do nothing. */
-}
-
-#pragma weak nmi_handler = null_handler
-#pragma weak hard_fault_handler = blocking_handler
-#pragma weak mem_manage_handler = blocking_handler
-#pragma weak bus_fault_handler = blocking_handler
-#pragma weak usage_fault_handler = blocking_handler
-#pragma weak sv_call_handler = null_handler
-#pragma weak debug_monitor_handler = null_handler
-#pragma weak pend_sv_handler = null_handler
-#pragma weak sys_tick_handler = null_handler
-#pragma weak wwdg_isr = null_handler
-#pragma weak pvd_isr = null_handler
-#pragma weak tamper_isr = null_handler
-#pragma weak rtc_isr = null_handler
-#pragma weak flash_isr = null_handler
-#pragma weak rcc_isr = null_handler
-#pragma weak exti0_isr = null_handler
-#pragma weak exti1_isr = null_handler
-#pragma weak exti2_isr = null_handler
-#pragma weak exti3_isr = null_handler
-#pragma weak exti4_isr = null_handler
-#pragma weak dma1_channel1_isr = null_handler
-#pragma weak dma1_channel2_isr = null_handler
-#pragma weak dma1_channel3_isr = null_handler
-#pragma weak dma1_channel4_isr = null_handler
-#pragma weak dma1_channel5_isr = null_handler
-#pragma weak dma1_channel6_isr = null_handler
-#pragma weak dma1_channel7_isr = null_handler
-#pragma weak adc1_2_isr = null_handler
-#pragma weak usb_hp_can_tx_isr = null_handler
-#pragma weak usb_lp_can_rx0_isr = null_handler
-#pragma weak can_rx1_isr = null_handler
-#pragma weak can_sce_isr = null_handler
-#pragma weak exti9_5_isr = null_handler
-#pragma weak tim1_brk_isr = null_handler
-#pragma weak tim1_up_isr = null_handler
-#pragma weak tim1_trg_com_isr = null_handler
-#pragma weak tim1_cc_isr = null_handler
-#pragma weak tim2_isr = null_handler
-#pragma weak tim3_isr = null_handler
-#pragma weak tim4_isr = null_handler
-#pragma weak i2c1_ev_isr = null_handler
-#pragma weak i2c1_er_isr = null_handler
-#pragma weak i2c2_ev_isr = null_handler
-#pragma weak i2c2_er_isr = null_handler
-#pragma weak spi1_isr = null_handler
-#pragma weak spi2_isr = null_handler
-#pragma weak usart1_isr = null_handler
-#pragma weak usart2_isr = null_handler
-#pragma weak usart3_isr = null_handler
-#pragma weak exti15_10_isr = null_handler
-#pragma weak rtc_alarm_isr = null_handler
-#pragma weak usb_wakeup_isr = null_handler
-#pragma weak tim8_brk_isr = null_handler
-#pragma weak tim8_up_isr = null_handler
-#pragma weak tim8_trg_com_isr = null_handler
-#pragma weak tim8_cc_isr = null_handler
-#pragma weak adc3_isr = null_handler
-#pragma weak fsmc_isr = null_handler
-#pragma weak sdio_isr = null_handler
-#pragma weak tim5_isr = null_handler
-#pragma weak spi3_isr = null_handler
-#pragma weak uart4_isr = null_handler
-#pragma weak uart5_isr = null_handler
-#pragma weak tim6_isr = null_handler
-#pragma weak tim7_isr = null_handler
-#pragma weak dma2_channel1_isr = null_handler
-#pragma weak dma2_channel2_isr = null_handler
-#pragma weak dma2_channel3_isr = null_handler
-#pragma weak dma2_channel4_5_isr = null_handler
-#pragma weak dma2_channel5_isr
-#pragma weak eth_isr = null_handler
-#pragma weak eth_wkup_isr = null_handler
-#pragma weak can2_tx_isr = null_handler
-#pragma weak can2_rx0_isr = null_handler
-#pragma weak can2_rx1_isr = null_handler
-#pragma weak can2_sce_isr = null_handler
-#pragma weak otg_fs_isr = null_handler