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-rw-r--r--include/libopencm3/lm4f/rcc.h126
-rw-r--r--include/libopencm3/lm4f/systemcontrol.h272
-rw-r--r--include/libopencm3/stm32/common/pwr_common_all.h119
-rw-r--r--include/libopencm3/stm32/common/rtc_common_bcd.h302
-rw-r--r--include/libopencm3/stm32/f1/flash.h56
-rw-r--r--include/libopencm3/stm32/f1/pwr.h40
-rw-r--r--include/libopencm3/stm32/f1/rtc.h5
-rw-r--r--include/libopencm3/stm32/f2/flash.h112
-rw-r--r--include/libopencm3/stm32/f2/rcc.h2
-rw-r--r--include/libopencm3/stm32/f2/rtc.h39
-rw-r--r--include/libopencm3/stm32/f4/flash.h112
-rw-r--r--include/libopencm3/stm32/f4/pwr.h19
-rw-r--r--include/libopencm3/stm32/f4/rcc.h2
-rw-r--r--include/libopencm3/stm32/f4/rtc.h39
-rw-r--r--include/libopencm3/stm32/l1/flash.h106
-rw-r--r--include/libopencm3/stm32/l1/irq.yaml19
-rw-r--r--include/libopencm3/stm32/l1/memorymap.h7
-rw-r--r--include/libopencm3/stm32/l1/pwr.h25
-rw-r--r--include/libopencm3/stm32/l1/rcc.h47
-rw-r--r--include/libopencm3/stm32/l1/rtc.h39
-rw-r--r--include/libopencm3/stm32/pwr.h122
-rw-r--r--include/libopencm3/stm32/rtc.h31
22 files changed, 1316 insertions, 325 deletions
diff --git a/include/libopencm3/lm4f/rcc.h b/include/libopencm3/lm4f/rcc.h
new file mode 100644
index 0000000..1c15f4b
--- /dev/null
+++ b/include/libopencm3/lm4f/rcc.h
@@ -0,0 +1,126 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/**
+ * @defgroup rcc_defines RCC Defines
+ *
+ * @ingroup LM4F_defines
+ *
+ * \brief <b>Defined Constants and Types for the LM4F Clock control API</b>
+ * @{
+ */
+
+#ifndef LM4F_RCC_H
+#define LM4F_RCC_H
+
+#include <libopencm3/lm4f/systemcontrol.h>
+
+/**
+ * \brief Oscillator source values
+ *
+ * Possible values of the oscillator source.
+ */
+typedef enum {
+ OSCSRC_MOSC = SYSCTL_RCC2_OSCSRC2_MOSC,
+ OSCSRC_PIOSC = SYSCTL_RCC2_OSCSRC2_PIOSC,
+ OSCSRC_PIOSC_D4 = SYSCTL_RCC2_OSCSRC2_PIOSC_D4,
+ OSCSRC_30K_INT = SYSCTL_RCC2_OSCSRC2_30K,
+ OSCSRC_32K_EXT = SYSCTL_RCC2_OSCSRC2_32K768,
+} osc_src_t;
+
+/**
+ * \brief PWM clock divisor values
+ *
+ * Possible values of the binary divisor used to predivide the system clock down
+ * for use as the timing reference for the PWM module.
+ */
+typedef enum {
+ PWMDIV_2 = SYSCTL_RCC_PWMDIV_2,
+ PWMDIV_4 = SYSCTL_RCC_PWMDIV_4,
+ PWMDIV_8 = SYSCTL_RCC_PWMDIV_8,
+ PWMDIV_16 = SYSCTL_RCC_PWMDIV_16,
+ PWMDIV_32 = SYSCTL_RCC_PWMDIV_32,
+ PWMDIV_64 = SYSCTL_RCC_PWMDIV_64,
+} pwm_clkdiv_t;
+
+/**
+ * \brief Predefined crystal values
+ *
+ * Predefined crystal values for the XTAL field in SYSCTL_RCC.
+ * Using these predefined values in the XTAL field, the SYSCTL_PLLFREQ0 and
+ * SYSCTL_PLLFREQ1 are automatically adjusted in hardware to provide a PLL clock
+ * of 400MHz.
+ */
+typedef enum {
+ XTAL_4M = SYSCTL_RCC_XTAL_4M,
+ XTAL_4M_096 = SYSCTL_RCC_XTAL_4M_096,
+ XTAL_4M_9152 = SYSCTL_RCC_XTAL_4M_9152,
+ XTAL_5M = SYSCTL_RCC_XTAL_5M,
+ XTAL_5M_12 = SYSCTL_RCC_XTAL_5M_12,
+ XTAL_6M = SYSCTL_RCC_XTAL_6M,
+ XTAL_6M_144 = SYSCTL_RCC_XTAL_6M_144,
+ XTAL_7M_3728 = SYSCTL_RCC_XTAL_7M_3728,
+ XTAL_8M = SYSCTL_RCC_XTAL_8M,
+ XTAL_8M_192 = SYSCTL_RCC_XTAL_8M_192,
+ XTAL_10M = SYSCTL_RCC_XTAL_10M,
+ XTAL_12M = SYSCTL_RCC_XTAL_12M,
+ XTAL_12M_288 = SYSCTL_RCC_XTAL_12M_288,
+ XTAL_13M_56 = SYSCTL_RCC_XTAL_13M_56,
+ XTAL_14M_31818 = SYSCTL_RCC_XTAL_14M_31818,
+ XTAL_16M = SYSCTL_RCC_XTAL_16M,
+ XTAL_16M_384 = SYSCTL_RCC_XTAL_16M_384,
+ XTAL_18M = SYSCTL_RCC_XTAL_18M,
+ XTAL_20M = SYSCTL_RCC_XTAL_20M,
+ XTAL_24M = SYSCTL_RCC_XTAL_24M,
+ XTAL_25M = SYSCTL_RCC_XTAL_25M,
+} xtal_t;
+
+/**
+ * @}
+ */
+/* =============================================================================
+ * Function prototypes
+ * ---------------------------------------------------------------------------*/
+BEGIN_DECLS
+/* Low-level clock API */
+void rcc_configure_xtal(xtal_t xtal);
+void rcc_disable_main_osc(void);
+void rcc_disable_interal_osc(void);
+void rcc_enable_main_osc(void);
+void rcc_enable_interal_osc(void);
+void rcc_enable_rcc2(void);
+void rcc_pll_off(void);
+void rcc_pll_on(void);
+void rcc_set_osc_source(osc_src_t src);
+void rcc_pll_bypass_disable(void);
+void rcc_pll_bypass_enable(void);
+void rcc_set_pll_divisor(u8 div400);
+void rcc_set_pwm_divisor(pwm_clkdiv_t div);
+void rcc_usb_pll_off(void);
+void rcc_usb_pll_on(void);
+void rcc_wait_for_pll_ready(void);
+/* High-level clock API */
+void rcc_change_pll_divisor(u8 plldiv400);
+u32 rcc_get_system_clock_frequency(void);
+void rcc_sysclk_config(osc_src_t src, xtal_t xtal, u8 pll_div400);
+
+END_DECLS
+
+
+#endif /* LM4F_RCC_H */
diff --git a/include/libopencm3/lm4f/systemcontrol.h b/include/libopencm3/lm4f/systemcontrol.h
index af4b71f..30fa1c9 100644
--- a/include/libopencm3/lm4f/systemcontrol.h
+++ b/include/libopencm3/lm4f/systemcontrol.h
@@ -21,6 +21,7 @@
#define LM4F_SYSTEMCONTROL_H
#include <libopencm3/cm3/common.h>
+#include <libopencm3/lm4f/memorymap.h>
#define SYSCTL_DID0 MMIO32(SYSCTL_BASE + 0x000)
#define SYSCTL_DID1 MMIO32(SYSCTL_BASE + 0x004)
@@ -369,9 +370,11 @@
/** Auto Clock Gating */
#define SYSCTL_RCC2_ACG (1 << 27)
/** System Clock Divisor 2 */
-#define SYSCTL_RCC2_SYSDIV2_MASK (0xF << 23)
+#define SYSCTL_RCC2_SYSDIV2_MASK (0x3F << 23)
/** Additional LSB for SYSDIV2 */
#define SYSCTL_RCC2_SYSDIV2LSB (1 << 22)
+/** System clock divisor mask when RCC2_DIV400 is set */
+#define SYSCTL_RCC2_SYSDIV400_MASK (0x7F << 22)
/** Power-Down USB PLL */
#define SYSCTL_RCC2_USBPWRDN (1 << 14)
/** PLL Power Down 2 */
@@ -450,6 +453,273 @@
/** PLL lock */
#define SYSCTL_PLLSTAT_LOCK (1 << 0)
+/* =============================================================================
+ * Convenience definitions for a readable API
+ * ---------------------------------------------------------------------------*/
+/**
+ * \brief Clock enable definitions
+ *
+ * The definitions are specified in the form
+ * 31:5 register offset from SYSCTL_BASE for the clock register
+ * 4:0 bit offset for the given peripheral
+ *
+ * The names have the form [clock_type]_[periph_type]_[periph_number]
+ * Where clock_type is
+ * RCC for run clock
+ * SCC for sleep clock
+ * DCC for deep-sleep clock
+ */
+typedef enum {
+ /*
+ * Run clock control
+ */
+ RCC_WD0 = ((u32)&SYSCTL_RCGCWD - SYSCTL_BASE) << 5,
+ RCC_WD1,
+
+ RCC_TIMER0 = ((u32)&SYSCTL_RCGCTIMER - SYSCTL_BASE) << 5,
+ RCC_TIMER1,
+ RCC_TIMER2,
+ RCC_TIMER3,
+ RCC_TIMER4,
+ RCC_TIMER5,
+
+ RCC_GPIOA = ((u32)&SYSCTL_RCGCGPIO - SYSCTL_BASE) << 5,
+ RCC_GPIOB,
+ RCC_GPIOC,
+ RCC_GPIOD,
+ RCC_GPIOE,
+ RCC_GPIOF,
+ RCC_GPIOG,
+ RCC_GPIOH,
+ RCC_GPIOJ,
+ RCC_GPIOK,
+ RCC_GPIOL,
+ RCC_GPIOM,
+ RCC_GPION,
+ RCC_GPIOP,
+ RCC_GPIOQ,
+
+ RCC_DMA = ((u32)&SYSCTL_RCGCDMA - SYSCTL_BASE) << 5,
+
+ RCC_HIB = ((u32)&SYSCTL_RCGCGPIO - SYSCTL_BASE) << 5,
+
+ RCC_UART0 = ((u32)&SYSCTL_RCGCUART - SYSCTL_BASE) << 5,
+ RCC_UART1,
+ RCC_UART2,
+ RCC_UART3,
+ RCC_UART4,
+ RCC_UART5,
+ RCC_UART6,
+ RCC_UART7,
+
+ RCC_SSI0 = ((u32)&SYSCTL_RCGCSSI - SYSCTL_BASE) << 5,
+ RCC_SSI1,
+ RCC_SSI2,
+ RCC_SSI3,
+
+ RCC_I2C0 = ((u32)&SYSCTL_RCGCI2C - SYSCTL_BASE) << 5,
+ RCC_I2C1,
+ RCC_I2C2,
+ RCC_I2C3,
+ RCC_I2C4,
+ RCC_I2C5,
+
+ RCC_USB0 = ((u32)&SYSCTL_RCGCUSB - SYSCTL_BASE) << 5,
+
+ RCC_CAN0 = ((u32)&SYSCTL_RCGCCAN - SYSCTL_BASE) << 5,
+ RCC_CAN1,
+
+ RCC_ADC0 = ((u32)&SYSCTL_RCGCADC - SYSCTL_BASE) << 5,
+ RCC_ADC1,
+
+ RCC_ACMP0 = ((u32)&SYSCTL_RCGCACMP - SYSCTL_BASE) << 5,
+
+ RCC_PWM0 = ((u32)&SYSCTL_RCGCPWM - SYSCTL_BASE) << 5,
+ RCC_PWM1,
+
+ RCC_QEI0 = ((u32)&SYSCTL_RCGCQEI - SYSCTL_BASE) << 5,
+ RCC_QEI1,
+
+ RCC_EEPROM0 = ((u32)&SYSCTL_RCGCEEPROM - SYSCTL_BASE) << 5,
+
+ RCC_WTIMER0 = ((u32)&SYSCTL_RCGCWTIMER - SYSCTL_BASE) << 5,
+ RCC_WTIMER1,
+ RCC_WTIMER2,
+ RCC_WTIMER3,
+ RCC_WTIMER4,
+ RCC_WTIMER5,
+
+
+ /*
+ * Sleep clock control
+ */
+ SCC_WD0 = ((u32)&SYSCTL_SCGCWD - SYSCTL_BASE) << 5,
+ SCC_WD1,
+
+ SCC_TIMER0 = ((u32)&SYSCTL_SCGCTIMER - SYSCTL_BASE) << 5,
+ SCC_TIMER1,
+ SCC_TIMER2,
+ SCC_TIMER3,
+ SCC_TIMER4,
+ SCC_TIMER5,
+
+ SCC_GPIOA = ((u32)&SYSCTL_SCGCGPIO - SYSCTL_BASE) << 5,
+ SCC_GPIOB,
+ SCC_GPIOC,
+ SCC_GPIOD,
+ SCC_GPIOE,
+ SCC_GPIOF,
+ SCC_GPIOG,
+ SCC_GPIOH,
+ SCC_GPIOJ,
+ SCC_GPIOK,
+ SCC_GPIOL,
+ SCC_GPIOM,
+ SCC_GPION,
+ SCC_GPIOP,
+ SCC_GPIOQ,
+
+ SCC_DMA = ((u32)&SYSCTL_SCGCDMA - SYSCTL_BASE) << 5,
+
+ SCC_HIB = ((u32)&SYSCTL_SCGCGPIO - SYSCTL_BASE) << 5,
+
+ SCC_UART0 = ((u32)&SYSCTL_SCGCUART - SYSCTL_BASE) << 5,
+ SCC_UART1,
+ SCC_UART2,
+ SCC_UART3,
+ SCC_UART4,
+ SCC_UART5,
+ SCC_UART6,
+ SCC_UART7,
+
+ SCC_SSI0 = ((u32)&SYSCTL_SCGCSSI - SYSCTL_BASE) << 5,
+ SCC_SSI1,
+ SCC_SSI2,
+ SCC_SSI3,
+
+ SCC_I2C0 = ((u32)&SYSCTL_SCGCI2C - SYSCTL_BASE) << 5,
+ SCC_I2C1,
+ SCC_I2C2,
+ SCC_I2C3,
+ SCC_I2C4,
+ SCC_I2C5,
+
+ SCC_USB0 = ((u32)&SYSCTL_SCGCUSB - SYSCTL_BASE) << 5,
+
+ SCC_CAN0 = ((u32)&SYSCTL_SCGCCAN - SYSCTL_BASE) << 5,
+ SCC_CAN1,
+
+ SCC_ADC0 = ((u32)&SYSCTL_SCGCADC - SYSCTL_BASE) << 5,
+ SCC_ADC1,
+
+ SCC_ACMP0 = ((u32)&SYSCTL_SCGCACMP - SYSCTL_BASE) << 5,
+
+ SCC_PWM0 = ((u32)&SYSCTL_SCGCPWM - SYSCTL_BASE) << 5,
+ SCC_PWM1,
+
+ SCC_QEI0 = ((u32)&SYSCTL_SCGCQEI - SYSCTL_BASE) << 5,
+ SCC_QEI1,
+
+ SCC_EEPROM0 = ((u32)&SYSCTL_SCGCEEPROM - SYSCTL_BASE) << 5,
+
+ SCC_WTIMER0 = ((u32)&SYSCTL_SCGCWTIMER - SYSCTL_BASE) << 5,
+ SCC_WTIMER1,
+ SCC_WTIMER2,
+ SCC_WTIMER3,
+ SCC_WTIMER4,
+ SCC_WTIMER5,
+
+ /*
+ * Deep-sleep clock control
+ */
+ DCC_WD0 = ((u32)&SYSCTL_DCGCWD - SYSCTL_BASE) << 5,
+ DCC_WD1,
+
+ DCC_TIMER0 = ((u32)&SYSCTL_DCGCTIMER - SYSCTL_BASE) << 5,
+ DCC_TIMER1,
+ DCC_TIMER2,
+ DCC_TIMER3,
+ DCC_TIMER4,
+ DCC_TIMER5,
+
+ DCC_GPIOA = ((u32)&SYSCTL_DCGCGPIO - SYSCTL_BASE) << 5,
+ DCC_GPIOB,
+ DCC_GPIOC,
+ DCC_GPIOD,
+ DCC_GPIOE,
+ DCC_GPIOF,
+ DCC_GPIOG,
+ DCC_GPIOH,
+ DCC_GPIOJ,
+ DCC_GPIOK,
+ DCC_GPIOL,
+ DCC_GPIOM,
+ DCC_GPION,
+ DCC_GPIOP,
+ DCC_GPIOQ,
+
+ DCC_DMA = ((u32)&SYSCTL_DCGCDMA - SYSCTL_BASE) << 5,
+
+ DCC_HIB = ((u32)&SYSCTL_DCGCGPIO - SYSCTL_BASE) << 5,
+
+ DCC_UART0 = ((u32)&SYSCTL_DCGCUART - SYSCTL_BASE) << 5,
+ DCC_UART1,
+ DCC_UART2,
+ DCC_UART3,
+ DCC_UART4,
+ DCC_UART5,
+ DCC_UART6,
+ DCC_UART7,
+
+ DCC_SSI0 = ((u32)&SYSCTL_DCGCSSI - SYSCTL_BASE) << 5,
+ DCC_SSI1,
+ DCC_SSI2,
+ DCC_SSI3,
+
+ DCC_I2C0 = ((u32)&SYSCTL_DCGCI2C - SYSCTL_BASE) << 5,
+ DCC_I2C1,
+ DCC_I2C2,
+ DCC_I2C3,
+ DCC_I2C4,
+ DCC_I2C5,
+
+ DCC_USB0 = ((u32)&SYSCTL_DCGCUSB - SYSCTL_BASE) << 5,
+
+ DCC_CAN0 = ((u32)&SYSCTL_DCGCCAN - SYSCTL_BASE) << 5,
+ DCC_CAN1,
+
+ DCC_ADC0 = ((u32)&SYSCTL_DCGCADC - SYSCTL_BASE) << 5,
+ DCC_ADC1,
+
+ DCC_ACMP0 = ((u32)&SYSCTL_DCGCACMP - SYSCTL_BASE) << 5,
+
+ DCC_PWM0 = ((u32)&SYSCTL_DCGCPWM - SYSCTL_BASE) << 5,
+ DCC_PWM1,
+
+ DCC_QEI0 = ((u32)&SYSCTL_DCGCQEI - SYSCTL_BASE) << 5,
+ DCC_QEI1,
+
+ DCC_EEPROM0 = ((u32)&SYSCTL_DCGCEEPROM - SYSCTL_BASE) << 5,
+
+ DCC_WTIMER0 = ((u32)&SYSCTL_DCGCWTIMER - SYSCTL_BASE) << 5,
+ DCC_WTIMER1,
+ DCC_WTIMER2,
+ DCC_WTIMER3,
+ DCC_WTIMER4,
+ DCC_WTIMER5,
+
+} clken_t;
+
+/* =============================================================================
+ * Function prototypes
+ * ---------------------------------------------------------------------------*/
+BEGIN_DECLS
+
+void periph_clock_enable(clken_t periph);
+void periph_clock_disable(clken_t periph);
+
+END_DECLS
+
#endif /* LM4F_SYSTEMCONTROL_H */
diff --git a/include/libopencm3/stm32/common/pwr_common_all.h b/include/libopencm3/stm32/common/pwr_common_all.h
new file mode 100644
index 0000000..cc9fd22
--- /dev/null
+++ b/include/libopencm3/stm32/common/pwr_common_all.h
@@ -0,0 +1,119 @@
+/** @addtogroup pwr_defines */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA PWR.H */
+
+#ifndef LIBOPENCM3_PWR_COMMON_ALL_H
+#define LIBOPENCM3_PWR_COMMON_ALL_H
+
+/**@{*/
+
+#include <libopencm3/cm3/common.h>
+
+/* --- PWR registers ------------------------------------------------------- */
+
+/* Power control register (PWR_CR) */
+#define PWR_CR MMIO32(POWER_CONTROL_BASE + 0x00)
+
+/* Power control/status register (PWR_CSR) */
+#define PWR_CSR MMIO32(POWER_CONTROL_BASE + 0x04)
+
+/* --- PWR_CR values ------------------------------------------------------- */
+
+/* Bits [31:9]: Reserved, must be kept at reset value. */
+
+/* DBP: Disable backup domain write protection */
+#define PWR_CR_DBP (1 << 8)
+
+/* PLS[7:5]: PVD level selection */
+#define PWR_CR_PLS_LSB 5
+/** @defgroup pwr_pls PVD level selection
+@ingroup STM32F_pwr_defines
+
+@{*/
+#define PWR_CR_PLS_2V2 (0x0 << PWR_CR_PLS_LSB)
+#define PWR_CR_PLS_2V3 (0x1 << PWR_CR_PLS_LSB)
+#define PWR_CR_PLS_2V4 (0x2 << PWR_CR_PLS_LSB)
+#define PWR_CR_PLS_2V5 (0x3 << PWR_CR_PLS_LSB)
+#define PWR_CR_PLS_2V6 (0x4 << PWR_CR_PLS_LSB)
+#define PWR_CR_PLS_2V7 (0x5 << PWR_CR_PLS_LSB)
+#define PWR_CR_PLS_2V8 (0x6 << PWR_CR_PLS_LSB)
+#define PWR_CR_PLS_2V9 (0x7 << PWR_CR_PLS_LSB)
+/**@}*/
+#define PWR_CR_PLS_MASK (0x7 << PWR_CR_PLS_LSB)
+
+/* PVDE: Power voltage detector enable */
+#define PWR_CR_PVDE (1 << 4)
+
+/* CSBF: Clear standby flag */
+#define PWR_CR_CSBF (1 << 3)
+
+/* CWUF: Clear wakeup flag */
+#define PWR_CR_CWUF (1 << 2)
+
+/* PDDS: Power down deepsleep */
+#define PWR_CR_PDDS (1 << 1)
+
+/* LPDS: Low-power deepsleep */
+#define PWR_CR_LPDS (1 << 0)
+
+/* --- PWR_CSR values ------------------------------------------------------ */
+
+/* Bits [31:9]: Reserved, must be kept at reset value. */
+
+/* EWUP: Enable WKUP pin */
+#define PWR_CSR_EWUP (1 << 8)
+
+/* Bits [7:3]: Reserved, must be kept at reset value. */
+
+/* PVDO: PVD output */
+#define PWR_CSR_PVDO (1 << 2)
+
+/* SBF: Standby flag */
+#define PWR_CSR_SBF (1 << 1)
+
+/* WUF: Wakeup flag */
+#define PWR_CSR_WUF (1 << 0)
+
+/* --- PWR function prototypes ------------------------------------------- */
+
+BEGIN_DECLS
+
+void pwr_disable_backup_domain_write_protect(void);
+void pwr_enable_backup_domain_write_protect(void);
+void pwr_enable_power_voltage_detect(u32 pvd_level);
+void pwr_disable_power_voltage_detect(void);
+void pwr_clear_standby_flag(void);
+void pwr_clear_wakeup_flag(void);
+void pwr_set_standby_mode(void);
+void pwr_set_stop_mode(void);
+void pwr_voltage_regulator_on_in_stop(void);
+void pwr_voltage_regulator_low_power_in_stop(void);
+void pwr_enable_wakeup_pin(void);
+void pwr_disable_wakeup_pin(void);
+bool pwr_voltage_high(void);
+bool pwr_get_standby_flag(void);
+bool pwr_get_wakeup_flag(void);
+
+END_DECLS
+
+/**@}*/
+#endif
diff --git a/include/libopencm3/stm32/common/rtc_common_bcd.h b/include/libopencm3/stm32/common/rtc_common_bcd.h
new file mode 100644
index 0000000..130020e
--- /dev/null
+++ b/include/libopencm3/stm32/common/rtc_common_bcd.h
@@ -0,0 +1,302 @@
+/** @addtogroup rtc_defines */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA RTC.H */
+
+/*
+ * This covers the "version 2" RTC peripheral. This is completely different
+ * to the v1 RTC periph on the F1 series devices. It has BCD counters, with
+ * automatic leapyear corrections and daylight savings support.
+ * This peripheral is used on the F0, F2, F3, F4 and L1 devices, though some
+ * only support a subset.
+ */
+
+#ifndef LIBOPENCM3_RTC2_H
+#define LIBOPENCM3_RTC2_H
+
+/**@{*/
+
+#include <libopencm3/cm3/common.h>
+#include <libopencm3/stm32/memorymap.h>
+
+/* RTC time register (RTC_TR) */
+#define RTC_TR MMIO32(RTC_BASE + 0x00)
+
+/* RTC date register (RTC_DR) */
+#define RTC_DR MMIO32(RTC_BASE + 0x04)
+
+/* RTC control register (RTC_CR) */
+#define RTC_CR MMIO32(RTC_BASE + 0x08)
+
+/* RTC initialization and status register (RTC_ISR) */
+#define RTC_ISR MMIO32(RTC_BASE + 0x0c)
+
+/* RTC prescaler register (RTC_PRER) */
+#define RTC_PRER MMIO32(RTC_BASE + 0x10)
+
+/* RTC wakeup timer register (RTC_WUTR) */
+#define RTC_WUTR MMIO32(RTC_BASE + 0x14)
+
+/* RTC calibration register (RTC_CALIBR) NB: see also RTC_CALR */
+#define RTC_CALIBR MMIO32(RTC_BASE + 0x18)
+
+/* RTC alarm X register (RTC_ALRMxR) */
+#define RTC_ALRMAR MMIO32(RTC_BASE + 0x1c)
+#define RTC_ALRMBR MMIO32(RTC_BASE + 0x20)
+
+/* RTC write protection register (RTC_WPR)*/
+#define RTC_WPR MMIO32(RTC_BASE + 0x24)
+
+/* RTC sub second register (RTC_SSR) (high and med+ only) */
+#define RTC_SSR MMIO32(RTC_BASE + 0x28)
+
+/* RTC shift control register (RTC_SHIFTR) (high and med+ only) */
+#define RTC_SHIFTR MMIO32(RTC_BASE + 0x2c)
+
+/* RTC time stamp time register (RTC_TSTR) */
+#define RTC_TSTR MMIO32(RTC_BASE + 0x30)
+/* RTC time stamp date register (RTC_TSDR) */
+#define RTC_TSDR MMIO32(RTC_BASE + 0x34)
+/* RTC timestamp sub second register (RTC_TSSSR) (high and med+ only) */
+#define RTC_TSSSR MMIO32(RTC_BASE + 0x38)
+
+/* RTC calibration register (RTC_CALR) (high and med+ only) */
+#define RTC_CALR MMIO32(RTC_BASE + 0x3c)
+
+/* RTC tamper and alternate function configuration register (RTC_TAFCR) */
+#define RTC_TAFCR MMIO32(RTC_BASE + 0x40)
+
+/* RTC alarm X sub second register (RTC_ALRMxSSR) (high and med+ only) */
+#define RTC_ALRMASSR MMIO32(RTC_BASE + 0x44)
+#define RTC_ALRMBSSR MMIO32(RTC_BASE + 0x48)
+
+/* RTC backup registers (RTC_BKPxR) */
+#define RTC_BKP_BASE (RTC_BASE + 0x50)
+#define RTC_BKPXR(reg) MMIO32(RTC_BKP_BASE + (4*reg))
+
+
+/* RTC time register (RTC_TR) bits */
+#define RTC_TR_TR_PM (1 << 22)
+#define RTC_TR_HT_SHIFT (20)
+#define RTC_TR_HT_MASK (0x3)
+#define RTC_TR_HU_SHIFT (16)
+#define RTC_TR_HU_MASK (0xf)
+#define RTC_TR_MNT_SHIFT (12)
+#define RTC_TR_MNT_MASK (0x7)
+#define RTC_TR_MNU_SHIFT (8)
+#define RTC_TR_MNU_MASK (0xf)
+#define RTC_TR_ST_SHIFT (4)
+#define RTC_TR_ST_MASK (0x3)
+#define RTC_TR_SU_SHIFT (0)
+#define RTC_TR_SU_MASK (0xf)
+
+/* RTC date register (RTC_DR) bits */
+#define RTC_DR_YT_SHIFT (20)
+#define RTC_DR_YT_MASK (0xf)
+#define RTC_DR_YU_SHIFT (16)
+#define RTC_DR_YU_MASK (0xf)
+#define RTC_DR_WDU_SHIFT (13)
+#define RTC_DR_WDU_MASK (0x7)
+#define RTC_DR_MT (1<<12)
+#define RTC_DR_MU_SHIFT (8)
+#define RTC_DR_MU_MASK (0xf)
+#define RTC_DR_DT_SHIFT (4)
+#define RTC_DR_DT_MASK (0x3)
+#define RTC_DR_DU_SHIFT (0)
+#define RTC_DR_DU_MASK (0xf)
+
+/* RTC control register (RTC_CR) bits */
+#define RTC_CR_COE (1<<23)
+
+/* These bits are used to select the flag to be routed to AFO_ALARM RTC output */
+#define RTC_CR_OSEL_SHIFT 21
+#define RTC_CR_OSEL_MASK (0x3)
+#define RTC_CR_OSEL_DISABLED (0x0)
+#define RTC_CR_OSEL_ALARMA (0x1)
+#define RTC_CR_OSEL_ALARMB (0x2)
+#define RTC_CR_OSEL_WAKEUP (0x3)
+
+#define RTC_CR_POL (1<<20)
+#define RTC_CR_COSEL (1<<19)
+#define RTC_CR_BKP (1<<18)
+#define RTC_CR_SUB1H (1<<17)
+#define RTC_CR_ADD1H (1<<16)
+#define RTC_CR_TSIE (1<<15)
+#define RTC_CR_WUTIE (1<<14)
+#define RTC_CR_ALRBIE (1<<13)
+#define RTC_CR_ALRAIE (1<<12)
+#define RTC_CR_TSE (1<<11)
+#define RTC_CR_WUTE (1<<10)
+#define RTC_CR_ALRBE (1<<9)
+#define RTC_CR_ALRAE (1<<8)
+#define RTC_CR_DCE (1<<7)
+#define RTC_CR_FMT (1<<6)
+#define RTC_CR_BYPSHAD (1<<5)
+#define RTC_CR_REFCKON (1<<4)
+#define RTC_CR_TSEDGE (1<<3)
+#define RTC_CR_TSEDGE (1<<3)
+#define RTC_CR_WUCLKSEL_SHIFT (0)
+#define RTC_CR_WUCLKSEL_MASK (0x7)
+#define RTC_CR_WUCLKSEL_RTC_DIV16 (0x0)
+#define RTC_CR_WUCLKSEL_RTC_DIV8 (0x1)
+#define RTC_CR_WUCLKSEL_RTC_DIV4 (0x2)
+#define RTC_CR_WUCLKSEL_RTC_DIV2 (0x3)
+#define RTC_CR_WUCLKSEL_SPRE (0x4)
+#define RTC_CR_WUCLKSEL_SPRE_216 (0x6)
+
+/* RTC initialization and status register (RTC_ISR) bits */
+#define RTC_ISR_RECALPF (1<<16)
+#define RTC_ISR_TAMP3F (1<<15)
+#define RTC_ISR_TAMP2F (1<<14)
+#define RTC_ISR_TAMP1F (1<<13)
+#define RTC_ISR_TSOVF (1<<12)
+#define RTC_ISR_TSF (1<<11)
+#define RTC_ISR_WUTF (1<<10)
+#define RTC_ISR_ALRBF (1<<9)
+#define RTC_ISR_ALRAF (1<<8)
+#define RTC_ISR_INIT (1<<7)
+#define RTC_ISR_INITF (1<<6)
+#define RTC_ISR_RSF (1<<5)
+#define RTC_ISR_INITS (1<<4)
+#define RTC_ISR_SHPF (1<<3)
+#define RTC_ISR_WUTWF (1<<2)
+#define RTC_ISR_ALRBWF (1<<1)
+#define RTC_ISR_ALRAWF (1<<0)
+
+/* RTC prescaler register (RTC_PRER) bits */
+#define RTC_PRER_PREDIV_A_SHIFT (16)
+#define RTC_PRER_PREDIV_A_MASK (0x7f)
+#define RTC_PRER_PREDIV_S_SHIFT (0)
+#define RTC_PRER_PREDIV_S_MASK (0x7fff)
+
+/* RTC calibration register (RTC_CALIBR) bits */
+// FIXME - TODO
+
+/* RTC Alarm register bits Applies to RTC_ALRMAR and RTC_ALRMBR */
+#define RTC_ALRMXR_MSK4 (1<<31)
+#define RTC_ALRMXR_WDSEL (1<<30)
+#define RTC_ALRMXR_DT_SHIFT (28)
+#define RTC_ALRMXR_DT_MASK (0x3)
+#define RTC_ALRMXR_DU_SHIFT (24)
+#define RTC_ALRMXR_DU_MASK (0xf)
+#define RTC_ALRMXR_MSK3 (1<<23)
+#define RTC_ALRMXR_PM (1<<22)
+#define RTC_ALRMXR_HT_SHIFT (20)
+#define RTC_ALRMXR_HT_MASK (0x3)
+#define RTC_ALRMXR_HU_SHIFT (16)
+#define RTC_ALRMXR_HU_MASK (0xf)
+#define RTC_ALRMXR_MSK2 (1<<15)
+#define RTC_ALRMXR_MNT_SHIFT (12)
+#define RTC_ALRMXR_MNT_MASK (0x7)
+#define RTC_ALRMXR_MNU_SHIFT (8)
+#define RTC_ALRMXR_MNU_MASK (0xf)
+#define RTC_ALRMXR_MSK1 (1<<7)
+#define RTC_ALRMXR_ST_SHIFT (4)
+#define RTC_ALRMXR_ST_MASK (0x7)
+#define RTC_ALRMXR_SU_SHIFT (0)
+#define RTC_ALRMXR_SU_MASK (0xf)
+
+/* RTC shift control register (RTC_SHIFTR) */
+// FIXME - TODO
+
+/* RTC time stamp time register (RTC_TSTR) bits */
+#define RTC_TSTR_PM (1<<22)
+#define RTC_TSTR_HT_SHIFT (20)
+#define RTC_TSTR_HT_MASK (0x3)
+#define RTC_TSTR_HU_SHIFT (16)
+#define RTC_TSTR_HU_MASK (0xf)
+#define RTC_TSTR_MNT_SHIFT (12)
+#define RTC_TSTR_MNT_MASK (0x7)
+#define RTC_TSTR_MNU_SHIFT (8)
+#define RTC_TSTR_MNU_MASK (0xf)
+#define RTC_TSTR_ST_SHIFT (4)
+#define RTC_TSTR_ST_MASK (0x7)
+#define RTC_TSTR_SU_SHIFT (0)
+#define RTC_TSTR_SU_MASK (0xf)
+
+/* RTC time stamp date register (RTC_TSDR) bits */
+#define RTC_TSDR_WDU_SHIFT (13)
+#define RTC_TSDR_WDU_MASK (0x7)
+#define RTC_TSDR_MT (1<<12)
+#define RTC_TSDR_MU_SHIFT (8)
+#define RTC_TSDR_MU_MASK (0xf)
+#define RTC_TSDR_DT_SHIFT (4)
+#define RTC_TSDR_DT_MASK (0x3)
+#define RTC_TSDR_DU_SHIFT (0)
+#define RTC_TSDR_DU_MASK (0xf)
+
+/* RTC calibration register (RTC_CALR) bits */
+// FIXME - TODO
+
+/* RTC tamper and alternate function configuration register (RTC_TAFCR) bits */
+#define RTC_TAFCR_ALARMOUTTYPE (1<<18)
+#define RTC_TAFCR_TAMPPUDIS (1<<15)
+
+#define RTC_TAFCR_TAMPPRCH_SHIFT (13)
+#define RTC_TAFCR_TAMPPRCH_MASK (0x3)
+#define RTC_TAFCR_TAMPPRCH_1RTC (0x0)
+#define RTC_TAFCR_TAMPPRCH_2RTC (0x1)
+#define RTC_TAFCR_TAMPPRCH_4RTC (0x2)
+#define RTC_TAFCR_TAMPPRCH_8RTC (0x3)
+
+#define RTC_TAFCR_TAMPFLT_SHIFT (11)
+#define RTC_TAFCR_TAMPFLT_MASK (0x3)
+#define RTC_TAFCR_TAMPFLT_EDGE1 (0x0)
+#define RTC_TAFCR_TAMPFLT_EDGE2 (0x1)
+#define RTC_TAFCR_TAMPFLT_EDGE4 (0x2)
+#define RTC_TAFCR_TAMPFLT_EDGE8 (0x3)
+
+#define RTC_TAFCR_TAMPFREQ_SHIFT (8)
+#define RTC_TAFCR_TAMPFREQ_MASK (0x7)
+#define RTC_TAFCR_TAMPFREQ_RTCDIV32K (0x0)
+#define RTC_TAFCR_TAMPFREQ_RTCDIV16K (0x1)
+#define RTC_TAFCR_TAMPFREQ_RTCDIV8K (0x2)
+#define RTC_TAFCR_TAMPFREQ_RTCDIV4K (0x3)
+#define RTC_TAFCR_TAMPFREQ_RTCDIV2K (0x4)
+#define RTC_TAFCR_TAMPFREQ_RTCDIV1K (0x5)
+#define RTC_TAFCR_TAMPFREQ_RTCDIV512 (0x6)
+#define RTC_TAFCR_TAMPFREQ_RTCDIV256 (0x7)
+
+#define RTC_TAFCR_TAMPTS (1<<7)
+#define RTC_TAFCR_TAMP3TRG (1<<6)
+#define RTC_TAFCR_TAMP3E (1<<5)
+#define RTC_TAFCR_TAMP2TRG (1<<4)
+#define RTC_TAFCR_TAMP2E (1<<3)
+#define RTC_TAFCR_TAMPIE (1<<2)
+#define RTC_TAFCR_TAMP1TRG (1<<1)
+#define RTC_TAFCR_TAMP1E (1<<0)
+
+/* RTC alarm X sub second register */
+// FIXME - TODO
+
+
+
+BEGIN_DECLS
+
+void rtc_set_prescaler(u32 sync, u32 async);
+void rtc_wait_for_synchro(void);
+void rtc_lock(void);
+void rtc_unlock(void);
+
+END_DECLS
+/**@}*/
+
+#endif /* RTC2_H */
+
diff --git a/include/libopencm3/stm32/f1/flash.h b/include/libopencm3/stm32/f1/flash.h
index 919b4d4..fef1257 100644
--- a/include/libopencm3/stm32/f1/flash.h
+++ b/include/libopencm3/stm32/f1/flash.h
@@ -44,48 +44,48 @@
/* --- FLASH_ACR values ---------------------------------------------------- */
-#define FLASH_PRFTBS (1 << 5)
-#define FLASH_PRFTBE (1 << 4)
-#define FLASH_HLFCYA (1 << 3)
-#define FLASH_LATENCY_0WS 0x00
-#define FLASH_LATENCY_1WS 0x01
-#define FLASH_LATENCY_2WS 0x02
+#define FLASH_ACR_PRFTBS (1 << 5)
+#define FLASH_ACR_PRFTBE (1 << 4)
+#define FLASH_ACR_HLFCYA (1 << 3)
+#define FLASH_ACR_LATENCY_0WS 0x00
+#define FLASH_ACR_LATENCY_1WS 0x01
+#define FLASH_ACR_LATENCY_2WS 0x02
/* --- FLASH_SR values ----------------------------------------------------- */
-#define FLASH_EOP (1 << 5)
-#define FLASH_WRPRTERR (1 << 4)
-#define FLASH_PGERR (1 << 2)
-#define FLASH_BSY (1 << 0)
+#define FLASH_SR_EOP (1 << 5)
+#define FLASH_SR_WRPRTERR (1 << 4)
+#define FLASH_SR_PGERR (1 << 2)
+#define FLASH_SR_BSY (1 << 0)
/* --- FLASH_CR values ----------------------------------------------------- */
-#define FLASH_EOPIE (1 << 12)
-#define FLASH_ERRIE (1 << 10)
-#define FLASH_OPTWRE (1 << 9)
-#define FLASH_LOCK (1 << 7)
-#define FLASH_STRT (1 << 6)
-#define FLASH_OPTER (1 << 5)
-#define FLASH_OPTPG (1 << 4)
-#define FLASH_MER (1 << 2)
-#define FLASH_PER (1 << 1)
-#define FLASH_PG (1 << 0)
+#define FLASH_CR_EOPIE (1 << 12)
+#define FLASH_CR_ERRIE (1 << 10)
+#define FLASH_CR_OPTWRE (1 << 9)
+#define FLASH_CR_LOCK (1 << 7)
+#define FLASH_CR_STRT (1 << 6)
+#define FLASH_CR_OPTER (1 << 5)
+#define FLASH_CR_OPTPG (1 << 4)
+#define FLASH_CR_MER (1 << 2)
+#define FLASH_CR_PER (1 << 1)
+#define FLASH_CR_PG (1 << 0)
/* --- FLASH_OBR values ---------------------------------------------------- */
/* FLASH_OBR[25:18]: Data1 */
/* FLASH_OBR[17:10]: Data0 */
-#define FLASH_NRST_STDBY (1 << 4)
-#define FLASH_NRST_STOP (1 << 3)
-#define FLASH_WDG_SW (1 << 2)
-#define FLASH_RDPRT (1 << 1)
-#define FLASH_OPTERR (1 << 0)
+#define FLASH_OBR_NRST_STDBY (1 << 4)
+#define FLASH_OBR_NRST_STOP (1 << 3)
+#define FLASH_OBR_WDG_SW (1 << 2)
+#define FLASH_OBR_RDPRT (1 << 1)
+#define FLASH_OBR_OPTERR (1 << 0)
/* --- FLASH Keys -----------------------------------------------------------*/
-#define RDP_KEY ((u16)0x00a5)
-#define FLASH_KEY1 ((u32)0x45670123)
-#define FLASH_KEY2 ((u32)0xcdef89ab)
+#define FLASH_RDP_KEY ((u16)0x00a5)
+#define FLASH_KEYR_KEY1 ((u32)0x45670123)
+#define FLASH_KEYR_KEY2 ((u32)0xcdef89ab)
/* --- Function prototypes ------------------------------------------------- */
diff --git a/include/libopencm3/stm32/f1/pwr.h b/include/libopencm3/stm32/f1/pwr.h
new file mode 100644
index 0000000..2875492
--- /dev/null
+++ b/include/libopencm3/stm32/f1/pwr.h
@@ -0,0 +1,40 @@
+/** @defgroup pwr_defines PWR Defines
+
+@brief <b>Defined Constants and Types for the STM32F1xx PWR Control</b>
+
+@ingroup STM32F1xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 5 December 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_PWR_H
+#define LIBOPENCM3_PWR_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/pwr_common_all.h>
+
+#endif
+
diff --git a/include/libopencm3/stm32/f1/rtc.h b/include/libopencm3/stm32/f1/rtc.h
index 04aea01..a8a8966 100644
--- a/include/libopencm3/stm32/f1/rtc.h
+++ b/include/libopencm3/stm32/f1/rtc.h
@@ -17,6 +17,11 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
+/*
+ * The F1 RTC is a straight timestamp, a completely different peripheral to
+ * that found in the F2, F3, F4, L1 and F0.
+ */
+
#ifndef LIBOPENCM3_RTC_H
#define LIBOPENCM3_RTC_H
diff --git a/include/libopencm3/stm32/f2/flash.h b/include/libopencm3/stm32/f2/flash.h
index 2c78757..3e6816f 100644
--- a/include/libopencm3/stm32/f2/flash.h
+++ b/include/libopencm3/stm32/f2/flash.h
@@ -43,76 +43,76 @@
/* --- FLASH_ACR values ---------------------------------------------------- */
-#define FLASH_DCRST (1 << 12)
-#define FLASH_ICRST (1 << 11)
-#define FLASH_DCE (1 << 10)
-#define FLASH_ICE (1 << 9)
-#define FLASH_PRFTEN (1 << 8)
-#define FLASH_LATENCY_0WS 0x00
-#define FLASH_LATENCY_1WS 0x01
-#define FLASH_LATENCY_2WS 0x02
-#define FLASH_LATENCY_3WS 0x03
-#define FLASH_LATENCY_4WS 0x04
-#define FLASH_LATENCY_5WS 0x05
-#define FLASH_LATENCY_6WS 0x06
-#define FLASH_LATENCY_7WS 0x07
+#define FLASH_ACR_DCRST (1 << 12)
+#define FLASH_ACR_ICRST (1 << 11)
+#define FLASH_ACR_DCE (1 << 10)
+#define FLASH_ACR_ICE (1 << 9)
+#define FLASH_ACR_PRFTEN (1 << 8)
+#define FLASH_ACR_LATENCY_0WS 0x00
+#define FLASH_ACR_LATENCY_1WS 0x01
+#define FLASH_ACR_LATENCY_2WS 0x02
+#define FLASH_ACR_LATENCY_3WS 0x03
+#define FLASH_ACR_LATENCY_4WS 0x04
+#define FLASH_ACR_LATENCY_5WS 0x05
+#define FLASH_ACR_LATENCY_6WS 0x06
+#define FLASH_ACR_LATENCY_7WS 0x07
/* --- FLASH_SR values ----------------------------------------------------- */
-#define FLASH_BSY (1 << 16)
-#define FLASH_PGSERR (1 << 7)
-#define FLASH_PGPERR (1 << 6)
-#define FLASH_PGAERR (1 << 5)
-#define FLASH_WRPERR (1 << 4)
-#define FLASH_OPERR (1 << 1)
-#define FLASH_EOP (1 << 0)
+#define FLASH_SR_BSY (1 << 16)
+#define FLASH_SR_PGSERR (1 << 7)
+#define FLASH_SR_PGPERR (1 << 6)
+#define FLASH_SR_PGAERR (1 << 5)
+#define FLASH_SR_WRPERR (1 << 4)
+#define FLASH_SR_OPERR (1 << 1)
+#define FLASH_SR_EOP (1 << 0)
/* --- FLASH_CR values ----------------------------------------------------- */
-#define FLASH_LOCK (1 << 31)
-#define FLASH_ERRIE (1 << 25)
-#define FLASH_EOPIE (1 << 24)
-#define FLASH_STRT (1 << 16)
-#define FLASH_MER (1 << 2)
-#define FLASH_SER (1 << 1)
-#define FLASH_PG (1 << 0)
-#define FLASH_SECTOR_0 (0x00 << 3)
-#define FLASH_SECTOR_1 (0x01 << 3)
-#define FLASH_SECTOR_2 (0x02 << 3)
-#define FLASH_SECTOR_3 (0x03 << 3)
-#define FLASH_SECTOR_4 (0x04 << 3)
-#define FLASH_SECTOR_5 (0x05 << 3)
-#define FLASH_SECTOR_6 (0x06 << 3)
-#define FLASH_SECTOR_7 (0x07 << 3)
-#define FLASH_SECTOR_8 (0x08 << 3)
-#define FLASH_SECTOR_9 (0x09 << 3)
-#define FLASH_SECTOR_10 (0x0a << 3)
-#define FLASH_SECTOR_11 (0x0b << 3)
-#define FLASH_PROGRAM_X8 (0x00 << 8)
-#define FLASH_PROGRAM_X16 (0x01 << 8)
-#define FLASH_PROGRAM_X32 (0x02 << 8)
-#define FLASH_PROGRAM_X64 (0x03 << 8)
+#define FLASH_CR_LOCK (1 << 31)
+#define FLASH_CR_ERRIE (1 << 25)
+#define FLASH_CR_EOPIE (1 << 24)
+#define FLASH_CR_STRT (1 << 16)
+#define FLASH_CR_MER (1 << 2)
+#define FLASH_CR_SER (1 << 1)
+#define FLASH_CR_PG (1 << 0)
+#define FLASH_CR_SECTOR_0 (0x00 << 3)
+#define FLASH_CR_SECTOR_1 (0x01 << 3)
+#define FLASH_CR_SECTOR_2 (0x02 << 3)
+#define FLASH_CR_SECTOR_3 (0x03 << 3)
+#define FLASH_CR_SECTOR_4 (0x04 << 3)
+#define FLASH_CR_SECTOR_5 (0x05 << 3)
+#define FLASH_CR_SECTOR_6 (0x06 << 3)
+#define FLASH_CR_SECTOR_7 (0x07 << 3)
+#define FLASH_CR_SECTOR_8 (0x08 << 3)
+#define FLASH_CR_SECTOR_9 (0x09 << 3)
+#define FLASH_CR_SECTOR_10 (0x0a << 3)
+#define FLASH_CR_SECTOR_11 (0x0b << 3)
+#define FLASH_CR_PROGRAM_X8 (0x00 << 8)
+#define FLASH_CR_PROGRAM_X16 (0x01 << 8)
+#define FLASH_CR_PROGRAM_X32 (0x02 << 8)
+#define FLASH_CR_PROGRAM_X64 (0x03 << 8)
/* --- FLASH_OPTCR values -------------------------------------------------- */
/* FLASH_OPTCR[27:16]: nWRP */
/* FLASH_OBR[15:8]: RDP */
-#define FLASH_NRST_STDBY (1 << 7)
-#define FLASH_NRST_STOP (1 << 6)
-#define FLASH_WDG_SW (1 << 5)
-#define FLASH_OPTSTRT (1 << 1)
-#define FLASH_OPTLOCK (1 << 0)
-#define FLASH_BOR_LEVEL_3 (0x00 << 2)
-#define FLASH_BOR_LEVEL_2 (0x01 << 2)
-#define FLASH_BOR_LEVEL_1 (0x02 << 2)
-#define FLASH_BOR_OFF (0x03 << 2)
+#define FLASH_OPTCR_NRST_STDBY (1 << 7)
+#define FLASH_OPTCR_NRST_STOP (1 << 6)
+#define FLASH_OPTCR_WDG_SW (1 << 5)
+#define FLASH_OPTCR_OPTSTRT (1 << 1)
+#define FLASH_OPTCR_OPTLOCK (1 << 0)
+#define FLASH_OPTCR_BOR_LEVEL_3 (0x00 << 2)
+#define FLASH_OPTCR_BOR_LEVEL_2 (0x01 << 2)
+#define FLASH_OPTCR_BOR_LEVEL_1 (0x02 << 2)
+#define FLASH_OPTCR_BOR_OFF (0x03 << 2)
/* --- FLASH Keys -----------------------------------------------------------*/
-#define FLASH_KEY1 ((u32)0x45670123)
-#define FLASH_KEY2 ((u32)0xcdef89ab)
-#define FLASH_OPTKEY1 ((u32)0x08192a3b)
-#define FLASH_OPTKEY2 ((u32)0x4c5d6e7f)
+#define FLASH_KEYR_KEY1 ((u32)0x45670123)
+#define FLASH_KEYR_KEY2 ((u32)0xcdef89ab)
+#define FLASH_OPTKEYR_KEY1 ((u32)0x08192a3b)
+#define FLASH_OPTKEYR_KEY2 ((u32)0x4c5d6e7f)
/* --- Function prototypes ------------------------------------------------- */
diff --git a/include/libopencm3/stm32/f2/rcc.h b/include/libopencm3/stm32/f2/rcc.h
index 4ffa242..1af6ccf 100644
--- a/include/libopencm3/stm32/f2/rcc.h
+++ b/include/libopencm3/stm32/f2/rcc.h
@@ -426,7 +426,7 @@
#define RCC_CSR_SFTRSTF (1 << 28)
#define RCC_CSR_PORRSTF (1 << 27)
#define RCC_CSR_PINRSTF (1 << 26)
-#define RCC_CSR_BORRSTF (1 << 26)
+#define RCC_CSR_BORRSTF (1 << 25)
#define RCC_CSR_RMVF (1 << 24)
#define RCC_CSR_LSIRDY (1 << 1)
#define RCC_CSR_LSION (1 << 0)
diff --git a/include/libopencm3/stm32/f2/rtc.h b/include/libopencm3/stm32/f2/rtc.h
new file mode 100644
index 0000000..ebc0936
--- /dev/null
+++ b/include/libopencm3/stm32/f2/rtc.h
@@ -0,0 +1,39 @@
+/** @defgroup rtc_defines RTC Defines
+
+@brief <b>Defined Constants and Types for the STM32F2xx RTC</b>
+
+@ingroup STM32F2xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 5 December 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_RTC_H
+#define LIBOPENCM3_RTC_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/rtc_common_bcd.h>
+
+#endif \ No newline at end of file
diff --git a/include/libopencm3/stm32/f4/flash.h b/include/libopencm3/stm32/f4/flash.h
index 2221333..8e7ed30 100644
--- a/include/libopencm3/stm32/f4/flash.h
+++ b/include/libopencm3/stm32/f4/flash.h
@@ -42,76 +42,76 @@
/* --- FLASH_ACR values ---------------------------------------------------- */
-#define FLASH_DCRST (1 << 12)
-#define FLASH_ICRST (1 << 11)
-#define FLASH_DCE (1 << 10)
-#define FLASH_ICE (1 << 9)
-#define FLASH_PRFTEN (1 << 8)
-#define FLASH_LATENCY_0WS 0x00
-#define FLASH_LATENCY_1WS 0x01
-#define FLASH_LATENCY_2WS 0x02
-#define FLASH_LATENCY_3WS 0x03
-#define FLASH_LATENCY_4WS 0x04
-#define FLASH_LATENCY_5WS 0x05
-#define FLASH_LATENCY_6WS 0x06
-#define FLASH_LATENCY_7WS 0x07
+#define FLASH_ACR_DCRST (1 << 12)
+#define FLASH_ACR_ICRST (1 << 11)
+#define FLASH_ACR_DCE (1 << 10)
+#define FLASH_ACR_ICE (1 << 9)
+#define FLASH_ACR_PRFTEN (1 << 8)
+#define FLASH_ACR_LATENCY_0WS 0x00
+#define FLASH_ACR_LATENCY_1WS 0x01
+#define FLASH_ACR_LATENCY_2WS 0x02
+#define FLASH_ACR_LATENCY_3WS 0x03
+#define FLASH_ACR_LATENCY_4WS 0x04
+#define FLASH_ACR_LATENCY_5WS 0x05
+#define FLASH_ACR_LATENCY_6WS 0x06
+#define FLASH_ACR_LATENCY_7WS 0x07
/* --- FLASH_SR values ----------------------------------------------------- */
-#define FLASH_BSY (1 << 16)
-#define FLASH_PGSERR (1 << 7)
-#define FLASH_PGPERR (1 << 6)
-#define FLASH_PGAERR (1 << 5)
-#define FLASH_WRPERR (1 << 4)
-#define FLASH_OPERR (1 << 1)
-#define FLASH_EOP (1 << 0)
+#define FLASH_SR_BSY (1 << 16)
+#define FLASH_SR_PGSERR (1 << 7)
+#define FLASH_SR_PGPERR (1 << 6)
+#define FLASH_SR_PGAERR (1 << 5)
+#define FLASH_SR_WRPERR (1 << 4)
+#define FLASH_SR_OPERR (1 << 1)
+#define FLASH_SR_EOP (1 << 0)
/* --- FLASH_CR values ----------------------------------------------------- */
-#define FLASH_LOCK (1 << 31)
-#define FLASH_ERRIE (1 << 25)
-#define FLASH_EOPIE (1 << 24)
-#define FLASH_STRT (1 << 16)
-#define FLASH_MER (1 << 2)
-#define FLASH_SER (1 << 1)
-#define FLASH_PG (1 << 0)
-#define FLASH_SECTOR_0 (0x00 << 3)
-#define FLASH_SECTOR_1 (0x01 << 3)
-#define FLASH_SECTOR_2 (0x02 << 3)
-#define FLASH_SECTOR_3 (0x03 << 3)
-#define FLASH_SECTOR_4 (0x04 << 3)
-#define FLASH_SECTOR_5 (0x05 << 3)
-#define FLASH_SECTOR_6 (0x06 << 3)
-#define FLASH_SECTOR_7 (0x07 << 3)
-#define FLASH_SECTOR_8 (0x08 << 3)
-#define FLASH_SECTOR_9 (0x09 << 3)
-#define FLASH_SECTOR_10 (0x0a << 3)
-#define FLASH_SECTOR_11 (0x0b << 3)
-#define FLASH_PROGRAM_X8 (0x00 << 8)
-#define FLASH_PROGRAM_X16 (0x01 << 8)
-#define FLASH_PROGRAM_X32 (0x02 << 8)
-#define FLASH_PROGRAM_X64 (0x03 << 8)
+#define FLASH_CR_LOCK (1 << 31)
+#define FLASH_CR_ERRIE (1 << 25)
+#define FLASH_CR_EOPIE (1 << 24)
+#define FLASH_CR_STRT (1 << 16)
+#define FLASH_CR_MER (1 << 2)
+#define FLASH_CR_SER (1 << 1)
+#define FLASH_CR_PG (1 << 0)
+#define FLASH_CR_SECTOR_0 (0x00 << 3)
+#define FLASH_CR_SECTOR_1 (0x01 << 3)
+#define FLASH_CR_SECTOR_2 (0x02 << 3)
+#define FLASH_CR_SECTOR_3 (0x03 << 3)
+#define FLASH_CR_SECTOR_4 (0x04 << 3)
+#define FLASH_CR_SECTOR_5 (0x05 << 3)
+#define FLASH_CR_SECTOR_6 (0x06 << 3)
+#define FLASH_CR_SECTOR_7 (0x07 << 3)
+#define FLASH_CR_SECTOR_8 (0x08 << 3)
+#define FLASH_CR_SECTOR_9 (0x09 << 3)
+#define FLASH_CR_SECTOR_10 (0x0a << 3)
+#define FLASH_CR_SECTOR_11 (0x0b << 3)
+#define FLASH_CR_PROGRAM_X8 (0x00 << 8)
+#define FLASH_CR_PROGRAM_X16 (0x01 << 8)
+#define FLASH_CR_PROGRAM_X32 (0x02 << 8)
+#define FLASH_CR_PROGRAM_X64 (0x03 << 8)
/* --- FLASH_OPTCR values -------------------------------------------------- */
/* FLASH_OPTCR[27:16]: nWRP */
/* FLASH_OBR[15:8]: RDP */
-#define FLASH_NRST_STDBY (1 << 7)
-#define FLASH_NRST_STOP (1 << 6)
-#define FLASH_WDG_SW (1 << 5)
-#define FLASH_OPTSTRT (1 << 1)
-#define FLASH_OPTLOCK (1 << 0)
-#define FLASH_BOR_LEVEL_3 (0x00 << 2)
-#define FLASH_BOR_LEVEL_2 (0x01 << 2)
-#define FLASH_BOR_LEVEL_1 (0x02 << 2)
-#define FLASH_BOR_OFF (0x03 << 2)
+#define FLASH_OPTCR_NRST_STDBY (1 << 7)
+#define FLASH_OPTCR_NRST_STOP (1 << 6)
+#define FLASH_OPTCR_WDG_SW (1 << 5)
+#define FLASH_OPTCR_OPTSTRT (1 << 1)
+#define FLASH_OPTCR_OPTLOCK (1 << 0)
+#define FLASH_OPTCR_BOR_LEVEL_3 (0x00 << 2)
+#define FLASH_OPTCR_BOR_LEVEL_2 (0x01 << 2)
+#define FLASH_OPTCR_BOR_LEVEL_1 (0x02 << 2)
+#define FLASH_OPTCR_BOR_OFF (0x03 << 2)
/* --- FLASH Keys -----------------------------------------------------------*/
-#define FLASH_KEY1 ((u32)0x45670123)
-#define FLASH_KEY2 ((u32)0xcdef89ab)
-#define FLASH_OPTKEY1 ((u32)0x08192a3b)
-#define FLASH_OPTKEY2 ((u32)0x4c5d6e7f)
+#define FLASH_KEYR_KEY1 ((u32)0x45670123)
+#define FLASH_KEYR_KEY2 ((u32)0xcdef89ab)
+#define FLASH_OPTKEYR_KEY1 ((u32)0x08192a3b)
+#define FLASH_OPTKEYR_KEY2 ((u32)0x4c5d6e7f)
/* --- Function prototypes ------------------------------------------------- */
diff --git a/include/libopencm3/stm32/f4/pwr.h b/include/libopencm3/stm32/f4/pwr.h
index 25fb163..c9b27fd 100644
--- a/include/libopencm3/stm32/f4/pwr.h
+++ b/include/libopencm3/stm32/f4/pwr.h
@@ -1,3 +1,15 @@
+/** @defgroup pwr_defines PWR Defines
+
+@brief <b>Defined Constants and Types for the STM32F4xx Power Control</b>
+
+@ingroup STM32F4xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2011 Stephen Caudle <scaudle@doceme.com>
+
+LGPL License Terms @ref lgpl_license
+ */
/*
* This file is part of the libopencm3 project.
*
@@ -17,10 +29,11 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
-#ifndef LIBOPENCM3_PWR_F4_H
-#define LIBOPENCM3_PWR_F4_H
+#ifndef LIBOPENCM3_PWR_H
+#define LIBOPENCM3_PWR_H
-#include <libopencm3/stm32/pwr.h>
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/pwr_common_all.h>
/*
* This file extends the common STM32 version with definitions only
diff --git a/include/libopencm3/stm32/f4/rcc.h b/include/libopencm3/stm32/f4/rcc.h
index 1688584..a718903 100644
--- a/include/libopencm3/stm32/f4/rcc.h
+++ b/include/libopencm3/stm32/f4/rcc.h
@@ -427,7 +427,7 @@
#define RCC_CSR_SFTRSTF (1 << 28)
#define RCC_CSR_PORRSTF (1 << 27)
#define RCC_CSR_PINRSTF (1 << 26)
-#define RCC_CSR_BORRSTF (1 << 26)
+#define RCC_CSR_BORRSTF (1 << 25)
#define RCC_CSR_RMVF (1 << 24)
#define RCC_CSR_LSIRDY (1 << 1)
#define RCC_CSR_LSION (1 << 0)
diff --git a/include/libopencm3/stm32/f4/rtc.h b/include/libopencm3/stm32/f4/rtc.h
new file mode 100644
index 0000000..ab8d3ee
--- /dev/null
+++ b/include/libopencm3/stm32/f4/rtc.h
@@ -0,0 +1,39 @@
+/** @defgroup rtc_defines RTC Defines
+
+@brief <b>Defined Constants and Types for the STM32F4xx RTC</b>
+
+@ingroup STM32F4xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 5 December 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_RTC_H
+#define LIBOPENCM3_RTC_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/rtc_common_bcd.h>
+
+#endif \ No newline at end of file
diff --git a/include/libopencm3/stm32/l1/flash.h b/include/libopencm3/stm32/l1/flash.h
index ed0a696..724fec9 100644
--- a/include/libopencm3/stm32/l1/flash.h
+++ b/include/libopencm3/stm32/l1/flash.h
@@ -33,10 +33,10 @@
#define FLASH_ACR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x00)
#define FLASH_PECR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x04)
-#define FLASH_PDKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x08)
-#define FLASH_PEKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x0C)
-#define FLASH_PRGKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x10)
-#define FLASH_OPTKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14)
+#define FLASH_PDKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x08)
+#define FLASH_PEKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x0C)
+#define FLASH_PRGKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x10)
+#define FLASH_OPTKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14)
#define FLASH_SR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x18)
#define FLASH_OBR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x1c)
#define FLASH_WRPR1 MMIO32(FLASH_MEM_INTERFACE_BASE + 0x20)
@@ -45,70 +45,70 @@
/* --- FLASH_ACR values ---------------------------------------------------- */
-#define FLASH_RUNPD (1 << 4)
-#define FLASH_SLEEPPD (1 << 3)
-#define FLASH_ACC64 (1 << 2)
-#define FLASH_PRFTEN (1 << 1)
-#define FLASH_LATENCY_0WS 0x00
-#define FLASH_LATENCY_1WS 0x01
+#define FLASH_ACR_RUNPD (1 << 4)
+#define FLASH_ACR_SLEEPPD (1 << 3)
+#define FLASH_ACR_ACC64 (1 << 2)
+#define FLASH_ACR_PRFTEN (1 << 1)
+#define FLASH_ACR_LATENCY_0WS 0x00
+#define FLASH_ACR_LATENCY_1WS 0x01
/* --- FLASH_PECR values. Program/erase control register */
-#define FLASH_OBL_LAUNCH (1 << 18)
-#define FLASH_ERRIE (1 << 17)
-#define FLASH_EOPIE (1 << 16)
-#define FLASH_PARALLBANK (1 << 15)
-#define FLASH_FPRG (1 << 10)
-#define FLASH_ERASE (1 << 9)
-#define FLASH_FTDW (1 << 8)
-#define FLASH_FTDW (1 << 8)
-#define FLASH_DATA (1 << 4)
-#define FLASH_PROG (1 << 3)
-#define FLASH_OPTLOCK (1 << 2)
-#define FLASH_PRGLOCK (1 << 1)
-#define FLASH_PELOCK (1 << 0)
+#define FLASH_PECR_OBL_LAUNCH (1 << 18)
+#define FLASH_PECR_ERRIE (1 << 17)
+#define FLASH_PECR_EOPIE (1 << 16)
+#define FLASH_PECR_PARALLBANK (1 << 15)
+#define FLASH_PECR_FPRG (1 << 10)
+#define FLASH_PECR_ERASE (1 << 9)
+#define FLASH_PECR_FTDW (1 << 8)
+#define FLASH_PECR_FTDW (1 << 8)
+#define FLASH_PECR_DATA (1 << 4)
+#define FLASH_PECR_PROG (1 << 3)
+#define FLASH_PECR_OPTLOCK (1 << 2)
+#define FLASH_PECR_PRGLOCK (1 << 1)
+#define FLASH_PECR_PELOCK (1 << 0)
/* Power down key register (FLASH_PDKEYR) */
-#define FLASH_PDKEY1 ((u32)0x04152637)
-#define FLASH_PDKEY2 ((u32)0xFAFBFCFD)
+#define FLASH_PDKEYR_PDKEY1 ((u32)0x04152637)
+#define FLASH_PDKEYR_PDKEY2 ((u32)0xFAFBFCFD)
/* Program/erase key register (FLASH_PEKEYR) */
-#define FLASH_PEKEY1 ((u32)0x89ABCDEF)
-#define FLASH_PEKEY2 ((u32)0x02030405)
+#define FLASH_PEKEYR_PEKEY1 ((u32)0x89ABCDEF)
+#define FLASH_PEKEYR_PEKEY2 ((u32)0x02030405)
/* Program memory key register (FLASH_PRGKEYR) */
-#define FLASH_PRGKEY1 ((u32)0x8C9DAEBF)
-#define FLASH_PRGKEY2 ((u32)0x13141516)
+#define FLASH_PRGKEYR_PRGKEY1 ((u32)0x8C9DAEBF)
+#define FLASH_PRGKEYR_PRGKEY2 ((u32)0x13141516)
/* Option byte key register (FLASH_OPTKEYR) */
-#define FLASH_OPTKEY1 ((u32)0xFBEAD9C8)
-#define FLASH_OPTKEY2 ((u32)0x24252627)
+#define FLASH_OPTKEYR_OPTKEY1 ((u32)0xFBEAD9C8)
+#define FLASH_OPTKEYR_OPTKEY2 ((u32)0x24252627)
/* --- FLASH_SR values ----------------------------------------------------- */
-#define FLASH_OPTVERRUSR (1 << 12)
-#define FLASH_OPTVERR (1 << 11)
-#define FLASH_SIZEERR (1 << 10)
-#define FLASH_PGAERR (1 << 9)
-#define FLASH_WRPERR (1 << 8)
-#define FLASH_READY (1 << 3)
-#define FLASH_ENDHV (1 << 2)
-#define FLASH_EOP (1 << 1)
-#define FLASH_BSY (1 << 0)
+#define FLASH_SR_OPTVERRUSR (1 << 12)
+#define FLASH_SR_OPTVERR (1 << 11)
+#define FLASH_SR_SIZEERR (1 << 10)
+#define FLASH_SR_PGAERR (1 << 9)
+#define FLASH_SR_WRPERR (1 << 8)
+#define FLASH_SR_READY (1 << 3)
+#define FLASH_SR_ENDHV (1 << 2)
+#define FLASH_SR_EOP (1 << 1)
+#define FLASH_SR_BSY (1 << 0)
/* --- FLASH_OBR values ----------------------------------------------------- */
-#define FLASH_BFB2 (1 << 23)
-#define FLASH_NRST_STDBY (1 << 22)
-#define FLASH_NRST_STOP (1 << 21)
-#define FLASH_IWDG_SW (1 << 20)
-#define FLASH_BOR_OFF (0x0 << 16)
-#define FLASH_BOR_LEVEL_1 (0x8 << 16)
-#define FLASH_BOR_LEVEL_2 (0x9 << 16)
-#define FLASH_BOR_LEVEL_3 (0xa << 16)
-#define FLASH_BOR_LEVEL_4 (0xb << 16)
-#define FLASH_BOR_LEVEL_5 (0xc << 16)
-#define FLASH_RDPRT_LEVEL_0 (0xaa)
-#define FLASH_RDPRT_LEVEL_1 (0x00)
-#define FLASH_RDPRT_LEVEL_2 (0xcc)
+#define FLASH_OBR_BFB2 (1 << 23)
+#define FLASH_OBR_NRST_STDBY (1 << 22)
+#define FLASH_OBR_NRST_STOP (1 << 21)
+#define FLASH_OBR_IWDG_SW (1 << 20)
+#define FLASH_OBR_BOR_OFF (0x0 << 16)
+#define FLASH_OBR_BOR_LEVEL_1 (0x8 << 16)
+#define FLASH_OBR_BOR_LEVEL_2 (0x9 << 16)
+#define FLASH_OBR_BOR_LEVEL_3 (0xa << 16)
+#define FLASH_OBR_BOR_LEVEL_4 (0xb << 16)
+#define FLASH_OBR_BOR_LEVEL_5 (0xc << 16)
+#define FLASH_OBR_RDPRT_LEVEL_0 (0xaa)
+#define FLASH_OBR_RDPRT_LEVEL_1 (0x00)
+#define FLASH_OBR_RDPRT_LEVEL_2 (0xcc)
/* --- Function prototypes ------------------------------------------------- */
diff --git a/include/libopencm3/stm32/l1/irq.yaml b/include/libopencm3/stm32/l1/irq.yaml
index c2f118f..a10e96c 100644
--- a/include/libopencm3/stm32/l1/irq.yaml
+++ b/include/libopencm3/stm32/l1/irq.yaml
@@ -4,8 +4,8 @@ partname_doxygen: STM32L1
irqs:
- wwdg
- pvd
- - tamper
- - rtc
+ - tamper_stamp
+ - rtc_wkup
- flash
- rcc
- exti0
@@ -44,6 +44,19 @@ irqs:
- usart3
- exti15_10
- rtc_alarm
- - usb_wakeup
+ - usb_fs_wakeup
- tim6
- tim7
+ # below here is medium+/high density
+ - sdio
+ - tim5
+ - spi3
+ - uart4
+ - uart5
+ - dma2_ch1
+ - dma2_ch2
+ - dma2_ch3
+ - dma2_ch4
+ - dma2_ch5
+ - aes
+ - comp_acq \ No newline at end of file
diff --git a/include/libopencm3/stm32/l1/memorymap.h b/include/libopencm3/stm32/l1/memorymap.h
index d89dbd6..60f1c57 100644
--- a/include/libopencm3/stm32/l1/memorymap.h
+++ b/include/libopencm3/stm32/l1/memorymap.h
@@ -47,7 +47,6 @@
#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000)
/* PERIPH_BASE_APB1 + 0x3400 (0x4000 3400 - 0x4000 37FF): Reserved */
#define SPI2_BASE (PERIPH_BASE_APB1 + 0x3800)
-// datasheet has an error? here
#define SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00)
/* PERIPH_BASE_APB1 + 0x4000 (0x4000 4000 - 0x4000 3FFF): Reserved */
#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400)
@@ -61,6 +60,7 @@
/* gap */
#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)
#define DAC_BASE (PERIPH_BASE_APB1 + 0x7400)
+#define OPAMP_BASE (PERIPH_BASE_APB1 + 0x7c5c)
#define COMP_BASE (PERIPH_BASE_APB1 + 0x7c00)
#define ROUTING_BASE (PERIPH_BASE_APB1 + 0x7c04)
@@ -85,13 +85,16 @@
#define GPIO_PORT_D_BASE (PERIPH_BASE_AHB + 0x00c00)
#define GPIO_PORT_E_BASE (PERIPH_BASE_AHB + 0x01000)
#define GPIO_PORT_H_BASE (PERIPH_BASE_AHB + 0x01400)
+#define GPIO_PORT_F_BASE (PERIPH_BASE_AHB + 0x01800)
+#define GPIO_PORT_G_BASE (PERIPH_BASE_AHB + 0x01c00)
/* gap */
#define CRC_BASE (PERIPH_BASE_AHB + 0x03000)
/* gap */
#define RCC_BASE (PERIPH_BASE_AHB + 0x03800)
#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB + 0x03c00)
/* gap */
-#define DMA_BASE (PERIPH_BASE_AHB + 0x06000)
+#define DMA1_BASE (PERIPH_BASE_AHB + 0x06000)
+#define DMA2_BASE (PERIPH_BASE_AHB + 0x04000)
/* PPIB */
#define DBGMCU_BASE (PPBI_BASE + 0x00042000)
diff --git a/include/libopencm3/stm32/l1/pwr.h b/include/libopencm3/stm32/l1/pwr.h
index 309b464..e976d46 100644
--- a/include/libopencm3/stm32/l1/pwr.h
+++ b/include/libopencm3/stm32/l1/pwr.h
@@ -1,3 +1,18 @@
+/** @defgroup pwr_defines PWR Defines
+
+@brief <b>Defined Constants and Types for the STM32L1xx Power Control</b>
+
+@ingroup STM32L1xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2011 Stephen Caudle <scaudle@doceme.com>
+@author @htmlonly &copy; @endhtmlonly 2012 Karl Palsson <karlp@tweak.net.au>
+
+@date 1 July 2012
+
+LGPL License Terms @ref lgpl_license
+ */
/*
* This file is part of the libopencm3 project.
*
@@ -18,10 +33,11 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
-#ifndef LIBOPENCM3_PWR_L1_H
-#define LIBOPENCM3_PWR_L1_H
+#ifndef LIBOPENCM3_PWR_H
+#define LIBOPENCM3_PWR_H
-#include <libopencm3/stm32/pwr.h>
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/pwr_common_all.h>
/*
* This file extends the common STM32 version with definitions only
@@ -53,6 +69,9 @@
/* ULP: Ultralow power mode */
#define PWR_CR_ULP (1 << 9)
+/* LPSDSR: Low-power deepsleep/sleep/low power run */
+#define PWR_CR_LPSDSR (1 << 0) /* masks common PWR_CR_LPDS */
+
/* --- PWR_CSR values ------------------------------------------------------- */
/* Bits [31:11]: Reserved */
diff --git a/include/libopencm3/stm32/l1/rcc.h b/include/libopencm3/stm32/l1/rcc.h
index 21b073b..4dc5102 100644
--- a/include/libopencm3/stm32/l1/rcc.h
+++ b/include/libopencm3/stm32/l1/rcc.h
@@ -46,7 +46,7 @@ LGPL License Terms @ref lgpl_license
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/cm3/common.h>
-#include <libopencm3/stm32/l1/pwr.h>
+#include <libopencm3/stm32/pwr.h>
/* --- RCC registers ------------------------------------------------------- */
@@ -82,11 +82,31 @@ LGPL License Terms @ref lgpl_license
#define RCC_CR_RTCPRE_DIV2 0
#define RCC_CR_RTCPRE_DIV4 1
#define RCC_CR_RTCPRE_DIV8 2
-#define RCC_CR_RTCPRE_DIV18 3
+#define RCC_CR_RTCPRE_DIV16 3
+#define RCC_CR_RTCPRE_SHIFT 29
+#define RCC_CR_RTCPRE_MASK 0x3
/* --- RCC_ICSCR values ---------------------------------------------------- */
-// TODO
+#define RCC_ICSCR_MSITRIM_SHIFT 24
+#define RCC_ICSCR_MSITRIM_MASK 0xff
+#define RCC_ICSCR_MSICAL_SHIFT 16
+#define RCC_ICSCR_MSICAL_MASK 0xff
+
+#define RCC_ICSCR_MSIRANGE_SHIFT 13
+#define RCC_ICSCR_MSIRANGE_MASK 0x7
+#define RCC_ICSCR_MSIRANGE_65KHZ 0x0
+#define RCC_ICSCR_MSIRANGE_131KHZ 0x1
+#define RCC_ICSCR_MSIRANGE_262KHZ 0x2
+#define RCC_ICSCR_MSIRANGE_524KHZ 0x3
+#define RCC_ICSCR_MSIRANGE_1MHZ 0x4
+#define RCC_ICSCR_MSIRANGE_2MHZ 0x5
+#define RCC_ICSCR_MSIRANGE_4MHZ 0x6
+
+#define RCC_ICSCR_HSITRIM_SHIFT 8
+#define RCC_ICSCR_HSITRIM_MASK 0x1f
+#define RCC_ICSCR_HSICAL_SHIFT 0
+#define RCC_ICSCR_HSICAL_MASK 0xff
/* --- RCC_CFGR values ----------------------------------------------------- */
@@ -347,7 +367,14 @@ LGPL License Terms @ref lgpl_license
#define RCC_CSR_RMVF (1 << 24)
#define RCC_CSR_RTCRST (1 << 23)
#define RCC_CSR_RTCEN (1 << 22)
-/* RTCSEL[1:0] */
+#define RCC_CSR_RTCSEL_SHIFT (16)
+#define RCC_CSR_RTCSEL_MASK (0x3)
+#define RCC_CSR_RTCSEL_NONE (0x0)
+#define RCC_CSR_RTCSEL_LSE (0x1)
+#define RCC_CSR_RTCSEL_LSI (0x2)
+#define RCC_CSR_RTCSEL_HSI (0x3)
+#define RCC_CSR_LSECSSD (1 << 12)
+#define RCC_CSR_LSECSSON (1 << 11)
#define RCC_CSR_LSEBYP (1 << 10)
#define RCC_CSR_LSERDY (1 << 9)
#define RCC_CSR_LSEON (1 << 8)
@@ -365,16 +392,20 @@ typedef struct {
vos_scale_t voltage_scale;
uint32_t apb1_frequency;
uint32_t apb2_frequency;
+ uint8_t msi_range;
} clock_scale_t;
typedef enum {
CLOCK_VRANGE1_HSI_PLL_24MHZ,
CLOCK_VRANGE1_HSI_PLL_32MHZ,
CLOCK_VRANGE1_HSI_RAW_16MHZ,
- CLOCK_VRANGE1_END
-} clock_volt_range1_t;
+ CLOCK_VRANGE1_HSI_RAW_4MHZ,
+ CLOCK_VRANGE1_MSI_RAW_4MHZ,
+ CLOCK_VRANGE1_MSI_RAW_2MHZ,
+ CLOCK_CONFIG_END
+} clock_config_entry_t;
-extern const clock_scale_t clock_vrange1_config[CLOCK_VRANGE1_END];
+extern const clock_scale_t clock_config[CLOCK_CONFIG_END];
/* --- Variable definitions ------------------------------------------------ */
@@ -413,6 +444,8 @@ void rcc_set_ppre1(u32 ppre1);
void rcc_set_hpre(u32 hpre);
void rcc_set_usbpre(u32 usbpre);
u32 rcc_get_system_clock_source(int i);
+void rcc_rtc_select_clock(u32 clock);
+void rcc_clock_setup_msi(const clock_scale_t *clock);
void rcc_clock_setup_hsi(const clock_scale_t *clock);
void rcc_clock_setup_pll(const clock_scale_t *clock);
void rcc_backupdomain_reset(void);
diff --git a/include/libopencm3/stm32/l1/rtc.h b/include/libopencm3/stm32/l1/rtc.h
new file mode 100644
index 0000000..d364fb5
--- /dev/null
+++ b/include/libopencm3/stm32/l1/rtc.h
@@ -0,0 +1,39 @@
+/** @defgroup rtc_defines RTC Defines
+
+@brief <b>Defined Constants and Types for the STM32L1xx RTC</b>
+
+@ingroup STM32L1xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 5 December 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_RTC_H
+#define LIBOPENCM3_RTC_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/rtc_common_bcd.h>
+
+#endif \ No newline at end of file
diff --git a/include/libopencm3/stm32/pwr.h b/include/libopencm3/stm32/pwr.h
index 34b2407..1d907a9 100644
--- a/include/libopencm3/stm32/pwr.h
+++ b/include/libopencm3/stm32/pwr.h
@@ -1,22 +1,8 @@
-/** @defgroup STM32F_pwr_defines PWR Defines
+/* This provides unification of code over STM32F subfamilies */
-@ingroup STM32F_defines
-
-@brief <b>libopencm3 STM32F Power Control</b>
-
-@version 1.0.0
-
-@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
-
-@date 17 August 2012
-
-LGPL License Terms @ref lgpl_license
- */
/*
* This file is part of the libopencm3 project.
*
- * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
- *
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
@@ -31,101 +17,15 @@ LGPL License Terms @ref lgpl_license
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
-/**@{*/
-
-#ifndef LIBOPENCM3_PWR_H
-#define LIBOPENCM3_PWR_H
-
-#include <libopencm3/stm32/memorymap.h>
-#include <libopencm3/cm3/common.h>
-
-/* --- PWR registers ------------------------------------------------------- */
-
-/* Power control register (PWR_CR) */
-#define PWR_CR MMIO32(POWER_CONTROL_BASE + 0x00)
-
-/* Power control/status register (PWR_CSR) */
-#define PWR_CSR MMIO32(POWER_CONTROL_BASE + 0x04)
-
-/* --- PWR_CR values ------------------------------------------------------- */
-
-/* Bits [31:9]: Reserved, must be kept at reset value. */
-
-/* DBP: Disable backup domain write protection */
-#define PWR_CR_DBP (1 << 8)
-
-/* PLS[7:5]: PVD level selection */
-#define PWR_CR_PLS_LSB 5
-/** @defgroup pwr_pls PVD level selection
-@ingroup STM32F_pwr_defines
-
-@{*/
-#define PWR_CR_PLS_2V2 (0x0 << PWR_CR_PLS_LSB)
-#define PWR_CR_PLS_2V3 (0x1 << PWR_CR_PLS_LSB)
-#define PWR_CR_PLS_2V4 (0x2 << PWR_CR_PLS_LSB)
-#define PWR_CR_PLS_2V5 (0x3 << PWR_CR_PLS_LSB)
-#define PWR_CR_PLS_2V6 (0x4 << PWR_CR_PLS_LSB)
-#define PWR_CR_PLS_2V7 (0x5 << PWR_CR_PLS_LSB)
-#define PWR_CR_PLS_2V8 (0x6 << PWR_CR_PLS_LSB)
-#define PWR_CR_PLS_2V9 (0x7 << PWR_CR_PLS_LSB)
-/**@}*/
-#define PWR_CR_PLS_MASK (0x7 << PWR_CR_PLS_LSB)
-
-/* PVDE: Power voltage detector enable */
-#define PWR_CR_PVDE (1 << 4)
-
-/* CSBF: Clear standby flag */
-#define PWR_CR_CSBF (1 << 3)
-
-/* CWUF: Clear wakeup flag */
-#define PWR_CR_CWUF (1 << 2)
-
-/* PDDS: Power down deepsleep */
-#define PWR_CR_PDDS (1 << 1)
-
-/* LPDS: Low-power deepsleep */
-#define PWR_CR_LPDS (1 << 0)
-
-/* --- PWR_CSR values ------------------------------------------------------ */
-
-/* Bits [31:9]: Reserved, must be kept at reset value. */
-
-/* EWUP: Enable WKUP pin */
-#define PWR_CSR_EWUP (1 << 8)
-
-/* Bits [7:3]: Reserved, must be kept at reset value. */
-
-/* PVDO: PVD output */
-#define PWR_CSR_PVDO (1 << 2)
-
-/* SBF: Standby flag */
-#define PWR_CSR_SBF (1 << 1)
-
-/* WUF: Wakeup flag */
-#define PWR_CSR_WUF (1 << 0)
-
-/* --- PWR function prototypes ------------------------------------------- */
-
-BEGIN_DECLS
-
-void pwr_disable_backup_domain_write_protect(void);
-void pwr_enable_backup_domain_write_protect(void);
-void pwr_enable_power_voltage_detect(u32 pvd_level);
-void pwr_disable_power_voltage_detect(void);
-void pwr_clear_standby_flag(void);
-void pwr_clear_wakeup_flag(void);
-void pwr_set_standby_mode(void);
-void pwr_set_stop_mode(void);
-void pwr_voltage_regulator_on_in_stop(void);
-void pwr_voltage_regulator_low_power_in_stop(void);
-void pwr_enable_wakeup_pin(void);
-void pwr_disable_wakeup_pin(void);
-bool pwr_voltage_high(void);
-bool pwr_get_standby_flag(void);
-bool pwr_get_wakeup_flag(void);
-
-END_DECLS
-
+#if defined(STM32F1)
+# include <libopencm3/stm32/f1/pwr.h>
+#elif defined(STM32F2)
+# include <libopencm3/stm32/f2/pwr.h>
+#elif defined(STM32F4)
+# include <libopencm3/stm32/f4/pwr.h>
+#elif defined(STM32L1)
+# include <libopencm3/stm32/l1/pwr.h>
+#else
+# error "stm32 family not defined."
#endif
-/**@}*/
diff --git a/include/libopencm3/stm32/rtc.h b/include/libopencm3/stm32/rtc.h
new file mode 100644
index 0000000..a927dd8
--- /dev/null
+++ b/include/libopencm3/stm32/rtc.h
@@ -0,0 +1,31 @@
+/* This provides unification of code over STM32 subfamilies */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#if defined(STM32F1)
+# include <libopencm3/stm32/f1/rtc.h>
+#elif defined(STM32F2)
+# include <libopencm3/stm32/f2/rtc.h>
+#elif defined(STM32F4)
+# include <libopencm3/stm32/f4/rtc.h>
+#elif defined(STM32L1)
+# include <libopencm3/stm32/l1/rtc.h>
+#else
+# error "stm32 family not defined."
+#endif
+