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-rw-r--r--include/libopenstm32/memorymap.h37
1 files changed, 37 insertions, 0 deletions
diff --git a/include/libopenstm32/memorymap.h b/include/libopenstm32/memorymap.h
index f364148..a9c7fef 100644
--- a/include/libopenstm32/memorymap.h
+++ b/include/libopenstm32/memorymap.h
@@ -20,6 +20,43 @@
#ifndef LIBOPENSTM32_MEMORYMAP_H
#define LIBOPENSTM32_MEMORYMAP_H
+/* --- ARM Cortex-M3 specific definitions ---------------------------------- */
+
+/* Private peripheral bus - Internal */
+#define PPBI_BASE 0xE0000000
+#define ITM_BASE (PPBI_BASE + 0x0000)
+#define DWT_BASE (PPBI_BASE + 0x1000)
+#define FPB_BASE (PPBI_BASE + 0x2000)
+/* PPBI_BASE + 0x3000 (0xE000 3000 - 0xE000 DFFF): Reserved */
+#define SCS_BASE (PPBI_BASE + 0xE000)
+/* PPBI_BASE + 0xF000 (0xE000 F000 - 0xE003 FFFF): Reserved */
+
+/* --- ITM: Instrumentation Trace Macrocell --- */
+/* TODO */
+
+/* --- DWT: Data Watchpoint and Trace unit --- */
+/* TODO */
+
+/* --- FPB: Flash Patch and Breakpoint unit --- */
+/* TODO */
+
+/* --- SCS: System Control Space --- */
+
+/* ITR: Interrupt Type Register */
+#define ITR_BASE (SCS_BASE + 0x0000)
+/* SYS_TICK: System Timer */
+#define SYS_TICK_BASE (SCS_BASE + 0x0010)
+/* NVIC: Nested Vector Interrupt Controller */
+#define NVIC_BASE (SCS_BASE + 0x0100)
+/* SCB: System Control Block */
+#define SCB_BASE (SCS_BASE + 0x0D00)
+/* STE: Software Trigger Interrupt Register */
+#define STIR_BASE (SCS_BASE + 0x0F00)
+/* ID: ID space */
+#define ID_BASE (SCS_BASE + 0x0FD0)
+
+/* --- STM32 specific peripheral definitions ------------------------------- */
+
/* Memory map for all busses */
#define PERIPH_BASE 0x40000000
#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)