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-rw-r--r--include/libopencm3/cm3/vector.h65
-rw-r--r--include/libopencm3/efm32/tinygecko/irq.h130
-rw-r--r--include/libopencm3/lm3s/irq.h505
-rw-r--r--include/libopencm3/lpc17xx/irq.h33
-rw-r--r--include/libopencm3/lpc43xx/irq.h234
-rw-r--r--include/libopencm3/stm32/f1/irq.h306
-rw-r--r--include/libopencm3/stm32/f2/irq.h359
-rw-r--r--include/libopencm3/stm32/f4/irq.h359
8 files changed, 1991 insertions, 0 deletions
diff --git a/include/libopencm3/cm3/vector.h b/include/libopencm3/cm3/vector.h
new file mode 100644
index 0000000..198992b
--- /dev/null
+++ b/include/libopencm3/cm3/vector.h
@@ -0,0 +1,65 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 chrysn <chrysn@fsfe.org>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/** @file
+ *
+ * Definitions for handling vector tables.
+ *
+ * This implements d0002_efm32_cortex-m3_reference_manual.pdf's figure 2.2
+ * (from the EFM32 documentation at
+ * http://www.energymicro.com/downloads/datasheets), and was seen analogously
+ * in other ARM implementations' libopencm3 files.
+ *
+ * The structure of the vector table is implemented independently of the system
+ * vector table starting at memory position 0x0, as it can be relocated to
+ * other memory locations too.
+ *
+ * The exact size of a vector interrupt table depends on the number of
+ * interrupts IRQ_COUNT, which is defined per family.
+ */
+
+#ifndef LIBOPENCM3_VECTOR_H
+#define LIBOPENCM3_VECTOR_H
+
+#include <libopencm3/cm3/common.h>
+
+// #include "irq.h" /* we'll nede some definitions */
+
+/** Type of an interrupt function. Only used to avoid hard-to-read function
+ * pointers in the efm32_vector_table_t struct. */
+typedef void (*vector_table_entry_t)(void);
+
+typedef struct {
+ unsigned int *initial_sp_value; /**< The value the stack pointer is set to initially */
+ vector_table_entry_t reset;
+ vector_table_entry_t nmi;
+ vector_table_entry_t hard_fault;
+ vector_table_entry_t memory_manage_fault;
+ vector_table_entry_t bus_fault;
+ vector_table_entry_t usage_fault;
+ vector_table_entry_t reserved_x001c[4];
+ vector_table_entry_t sv_call;
+ vector_table_entry_t debug_monitor;
+ vector_table_entry_t reserved_x0034;
+ vector_table_entry_t pend_sv;
+ vector_table_entry_t systick;
+ vector_table_entry_t irq[IRQ_COUNT];
+} vector_table_t;
+
+#endif
diff --git a/include/libopencm3/efm32/tinygecko/irq.h b/include/libopencm3/efm32/tinygecko/irq.h
new file mode 100644
index 0000000..f5263ae
--- /dev/null
+++ b/include/libopencm3/efm32/tinygecko/irq.h
@@ -0,0 +1,130 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 chrysn <chrysn@fsfe.org>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/** @file
+ *
+ * Definitions of interrupt names on EFM32 Tiny Gecko systems
+ *
+ * The names and numbers are taken from d0034_efm32tg_reference_manual.pdf table 4.1.
+ */
+
+#ifndef LIBOPENCM3_EFM32_TINYGECKO_VECTOR_H
+#define LIBOPENCM3_EFM32_TINYGECKO_VECTOR_H
+
+#define IRQ_DMA 0
+#define IRQ_GPIO_EVEN 1
+#define IRQ_TIMER0 2
+#define IRQ_USART0_RX 3
+#define IRQ_USART0_TX 4
+#define IRQ_ACMP01 5
+#define IRQ_ADC0 6
+#define IRQ_DAC0 7
+#define IRQ_I2C0 8
+#define IRQ_GPIO_ODD 9
+#define IRQ_TIMER1 10
+#define IRQ_USART1_RX 11
+#define IRQ_USART1_TX 12
+#define IRQ_LESENSE 13
+#define IRQ_LEUART0 14
+#define IRQ_LETIMER0 15
+#define IRQ_PCNT0 16
+#define IRQ_RTC 17
+#define IRQ_CMU 18
+#define IRQ_VCMP 19
+#define IRQ_LCD 20
+#define IRQ_MSC 21
+#define IRQ_AES 22
+#define IRQ_COUNT 23 /**< See also d0002_efm32_cortex-m3_reference_manual.pdf's table 1.1's "number of interrupts" line, which shows that there are really no more interrupts and it is sufficient to allocate only 23 slots. */
+
+#define WEAK __attribute__ ((weak))
+
+void WEAK dma_isr(void);
+void WEAK gpio_even_isr(void);
+void WEAK timer0_isr(void);
+void WEAK usart0_rx_isr(void);
+void WEAK usart0_tx_isr(void);
+void WEAK acmp01_isr(void);
+void WEAK adc0_isr(void);
+void WEAK dac0_isr(void);
+void WEAK i2c0_isr(void);
+void WEAK gpio_odd_isr(void);
+void WEAK timer1_isr(void);
+void WEAK usart1_rx_isr(void);
+void WEAK usart1_tx_isr(void);
+void WEAK lesense_isr(void);
+void WEAK leuart0_isr(void);
+void WEAK letimer0_isr(void);
+void WEAK pcnt0_isr(void);
+void WEAK rtc_isr(void);
+void WEAK cmu_isr(void);
+void WEAK vcmp_isr(void);
+void WEAK lcd_isr(void);
+void WEAK msc_isr(void);
+void WEAK aes_isr(void);
+
+#pragma weak dma_isr = blocking_handler
+#pragma weak gpio_even_isr = blocking_handler
+#pragma weak timer0_isr = blocking_handler
+#pragma weak usart0_rx_isr = blocking_handler
+#pragma weak usart0_tx_isr = blocking_handler
+#pragma weak acmp01_isr = blocking_handler
+#pragma weak adc0_isr = blocking_handler
+#pragma weak dac0_isr = blocking_handler
+#pragma weak i2c0_isr = blocking_handler
+#pragma weak gpio_odd_isr = blocking_handler
+#pragma weak timer1_isr = blocking_handler
+#pragma weak usart1_rx_isr = blocking_handler
+#pragma weak usart1_tx_isr = blocking_handler
+#pragma weak lesense_isr = blocking_handler
+#pragma weak leuart0_isr = blocking_handler
+#pragma weak letimer0_isr = blocking_handler
+#pragma weak pcnt0_isr = blocking_handler
+#pragma weak rtc_isr = blocking_handler
+#pragma weak cmu_isr = blocking_handler
+#pragma weak vcmp_isr = blocking_handler
+#pragma weak lcd_isr = blocking_handler
+#pragma weak msc_isr = blocking_handler
+#pragma weak aes_isr = blocking_handler
+
+#define IRQ_HANDLERS \
+ [IRQ_DMA] = dma_isr, \
+ [IRQ_GPIO_EVEN] = gpio_even_isr, \
+ [IRQ_TIMER0] = timer0_isr, \
+ [IRQ_USART0_RX] = usart0_rx_isr, \
+ [IRQ_USART0_TX] = usart0_tx_isr, \
+ [IRQ_ACMP01] = acmp01_isr, \
+ [IRQ_ADC0] = adc0_isr, \
+ [IRQ_DAC0] = dac0_isr, \
+ [IRQ_I2C0] = i2c0_isr, \
+ [IRQ_GPIO_ODD] = gpio_odd_isr, \
+ [IRQ_TIMER1] = timer1_isr, \
+ [IRQ_USART1_RX] = usart1_rx_isr, \
+ [IRQ_USART1_TX] = usart1_tx_isr, \
+ [IRQ_LESENSE] = lesense_isr, \
+ [IRQ_LEUART0] = leuart0_isr, \
+ [IRQ_LETIMER0] = letimer0_isr, \
+ [IRQ_PCNT0] = pcnt0_isr, \
+ [IRQ_RTC] = rtc_isr, \
+ [IRQ_CMU] = cmu_isr, \
+ [IRQ_VCMP] = vcmp_isr, \
+ [IRQ_LCD] = lcd_isr, \
+ [IRQ_MSC] = msc_isr, \
+ [IRQ_AES] = aes_isr,
+
+#endif
diff --git a/include/libopencm3/lm3s/irq.h b/include/libopencm3/lm3s/irq.h
new file mode 100644
index 0000000..331ee51
--- /dev/null
+++ b/include/libopencm3/lm3s/irq.h
@@ -0,0 +1,505 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
+ * Copyright (C) 2012 chrysn <chrysn@fsfe.org>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_LM3S_IRQ_H
+#define LIBOPENCM3_LM3S_IRQ_H
+
+#define IRQ_GPIOA 0
+#define IRQ_GPIOB 1
+#define IRQ_GPIOC 2
+#define IRQ_GPIOD 3
+#define IRQ_GPIOE 4
+#define IRQ_UART0 5
+#define IRQ_UART1 6
+#define IRQ_SSI0 7
+#define IRQ_I2C0 8
+#define IRQ_PWM0_FAULT 9
+#define IRQ_PWM0_0 10
+#define IRQ_PWM0_1 11
+#define IRQ_PWM0_2 12
+#define IRQ_QEI0 13
+#define IRQ_ADC0SS0 14
+#define IRQ_ADC0SS1 15
+#define IRQ_ADC0SS2 16
+#define IRQ_ADC0SS3 17
+#define IRQ_WATCHDOG 18
+#define IRQ_TIMER0A 19
+#define IRQ_TIMER0B 20
+#define IRQ_TIMER1A 21
+#define IRQ_TIMER1B 22
+#define IRQ_TIMER2A 23
+#define IRQ_TIMER2B 24
+#define IRQ_COMP0 25
+#define IRQ_COMP1 26
+#define IRQ_COMP2 27
+#define IRQ_SYSCTL 28
+#define IRQ_FLASH 29
+#define IRQ_GPIOF 30
+#define IRQ_GPIOG 31
+#define IRQ_GPIOH 32
+#define IRQ_UART2 33
+#define IRQ_SSI1 34
+#define IRQ_TIMER3A 35
+#define IRQ_TIMER3B 36
+#define IRQ_I2C1 37
+#define IRQ_QEI1 38
+#define IRQ_CAN0 39
+#define IRQ_CAN1 40
+#define IRQ_CAN2 41
+#define IRQ_ETH 42
+#define IRQ_HIBERNATE 43
+#define IRQ_USB0 44
+#define IRQ_PWM0_3 45
+#define IRQ_UDMA 46
+#define IRQ_UDMAERR 47
+#define IRQ_ADC1SS0 48
+#define IRQ_ADC1SS1 49
+#define IRQ_ADC1SS2 50
+#define IRQ_ADC1SS3 51
+#define IRQ_I2S0 52
+#define IRQ_EPI0 53
+#define IRQ_GPIOJ 54
+#define IRQ_GPIOK 55
+#define IRQ_GPIOL 56
+#define IRQ_SSI2 57
+#define IRQ_SSI3 58
+#define IRQ_UART3 59
+#define IRQ_UART4 60
+#define IRQ_UART5 61
+#define IRQ_UART6 62
+#define IRQ_UART7 63
+/* undefined: slot 64 */
+/* undefined: slot 65 */
+/* undefined: slot 66 */
+/* undefined: slot 67 */
+#define IRQ_I2C2 68
+#define IRQ_I2C3 69
+#define IRQ_TIMER4A 70
+#define IRQ_TIMER4B 71
+/* undefined: slot 72 */
+/* undefined: slot 73 */
+/* undefined: slot 74 */
+/* undefined: slot 75 */
+/* undefined: slot 76 */
+/* undefined: slot 77 */
+/* undefined: slot 78 */
+/* undefined: slot 79 */
+/* undefined: slot 80 */
+/* undefined: slot 81 */
+/* undefined: slot 82 */
+/* undefined: slot 83 */
+/* undefined: slot 84 */
+/* undefined: slot 85 */
+/* undefined: slot 86 */
+/* undefined: slot 87 */
+/* undefined: slot 88 */
+/* undefined: slot 89 */
+/* undefined: slot 90 */
+/* undefined: slot 91 */
+#define IRQ_TIMER5A 92
+#define IRQ_TIMER5B 93
+#define IRQ_WTIMER0A 94
+#define IRQ_WTIMER0B 95
+#define IRQ_WTIMER1A 96
+#define IRQ_WTIMER1B 97
+#define IRQ_WTIMER2A 98
+#define IRQ_WTIMER2B 99
+#define IRQ_WTIMER3A 100
+#define IRQ_WTIMER3B 101
+#define IRQ_WTIMER4A 102
+#define IRQ_WTIMER4B 103
+#define IRQ_WTIMER5A 104
+#define IRQ_WTIMER5B 105
+#define IRQ_SYSEXC 106
+#define IRQ_PECI0 107
+#define IRQ_LPC0 108
+#define IRQ_I2C4 109
+#define IRQ_I2C5 110
+#define IRQ_GPIOM 111
+#define IRQ_GPION 112
+/* undefined: slot 113 */
+#define IRQ_FAN0 114
+/* undefined: slot 115 */
+#define IRQ_GPIOP0 116
+#define IRQ_GPIOP1 117
+#define IRQ_GPIOP2 118
+#define IRQ_GPIOP3 119
+#define IRQ_GPIOP4 120
+#define IRQ_GPIOP5 121
+#define IRQ_GPIOP6 122
+#define IRQ_GPIOP7 123
+#define IRQ_GPIOQ0 124
+#define IRQ_GPIOQ1 125
+#define IRQ_GPIOQ2 126
+#define IRQ_GPIOQ3 127
+#define IRQ_GPIOQ4 128
+#define IRQ_GPIOQ5 129
+#define IRQ_GPIOQ6 130
+#define IRQ_GPIOQ7 131
+/* undefined: slot 132 */
+/* undefined: slot 133 */
+#define IRQ_PWM1_0 134
+#define IRQ_PWM1_1 135
+#define IRQ_PWM1_2 136
+#define IRQ_PWM1_3 137
+#define IRQ_PWM1_FAULT 138
+
+#define IRQ_COUNT 139
+
+#define WEAK __attribute__ ((weak))
+
+void WEAK gpioa_isr(void);
+void WEAK gpiob_isr(void);
+void WEAK gpioc_isr(void);
+void WEAK gpiod_isr(void);
+void WEAK gpioe_isr(void);
+void WEAK uart0_isr(void);
+void WEAK uart1_isr(void);
+void WEAK ssi0_isr(void);
+void WEAK i2c0_isr(void);
+void WEAK pwm0_fault_isr(void);
+void WEAK pwm0_0_isr(void);
+void WEAK pwm0_1_isr(void);
+void WEAK pwm0_2_isr(void);
+void WEAK qei0_isr(void);
+void WEAK adc0ss0_isr(void);
+void WEAK adc0ss1_isr(void);
+void WEAK adc0ss2_isr(void);
+void WEAK adc0ss3_isr(void);
+void WEAK watchdog_isr(void);
+void WEAK timer0a_isr(void);
+void WEAK timer0b_isr(void);
+void WEAK timer1a_isr(void);
+void WEAK timer1b_isr(void);
+void WEAK timer2a_isr(void);
+void WEAK timer2b_isr(void);
+void WEAK comp0_isr(void);
+void WEAK comp1_isr(void);
+void WEAK comp2_isr(void);
+void WEAK sysctl_isr(void);
+void WEAK flash_isr(void);
+void WEAK gpiof_isr(void);
+void WEAK gpiog_isr(void);
+void WEAK gpioh_isr(void);
+void WEAK uart2_isr(void);
+void WEAK ssi1_isr(void);
+void WEAK timer3a_isr(void);
+void WEAK timer3b_isr(void);
+void WEAK i2c1_isr(void);
+void WEAK qei1_isr(void);
+void WEAK can0_isr(void);
+void WEAK can1_isr(void);
+void WEAK can2_isr(void);
+void WEAK eth_isr(void);
+void WEAK hibernate_isr(void);
+void WEAK usb0_isr(void);
+void WEAK pwm0_3_isr(void);
+void WEAK udma_isr(void);
+void WEAK udmaerr_isr(void);
+void WEAK adc1ss0_isr(void);
+void WEAK adc1ss1_isr(void);
+void WEAK adc1ss2_isr(void);
+void WEAK adc1ss3_isr(void);
+void WEAK i2s0_isr(void);
+void WEAK epi0_isr(void);
+void WEAK gpioj_isr(void);
+void WEAK gpiok_isr(void);
+void WEAK gpiol_isr(void);
+void WEAK ssi2_isr(void);
+void WEAK ssi3_isr(void);
+void WEAK uart3_isr(void);
+void WEAK uart4_isr(void);
+void WEAK uart5_isr(void);
+void WEAK uart6_isr(void);
+void WEAK uart7_isr(void);
+void WEAK i2c2_isr(void);
+void WEAK i2c3_isr(void);
+void WEAK timer4a_isr(void);
+void WEAK timer4b_isr(void);
+void WEAK timer5a_isr(void);
+void WEAK timer5b_isr(void);
+void WEAK wtimer0a_isr(void);
+void WEAK wtimer0b_isr(void);
+void WEAK wtimer1a_isr(void);
+void WEAK wtimer1b_isr(void);
+void WEAK wtimer2a_isr(void);
+void WEAK wtimer2b_isr(void);
+void WEAK wtimer3a_isr(void);
+void WEAK wtimer3b_isr(void);
+void WEAK wtimer4a_isr(void);
+void WEAK wtimer4b_isr(void);
+void WEAK wtimer5a_isr(void);
+void WEAK wtimer5b_isr(void);
+void WEAK sysexc_isr(void);
+void WEAK peci0_isr(void);
+void WEAK lpc0_isr(void);
+void WEAK i2c4_isr(void);
+void WEAK i2c5_isr(void);
+void WEAK gpiom_isr(void);
+void WEAK gpion_isr(void);
+void WEAK fan0_isr(void);
+void WEAK gpiop0_isr(void);
+void WEAK gpiop1_isr(void);
+void WEAK gpiop2_isr(void);
+void WEAK gpiop3_isr(void);
+void WEAK gpiop4_isr(void);
+void WEAK gpiop5_isr(void);
+void WEAK gpiop6_isr(void);
+void WEAK gpiop7_isr(void);
+void WEAK gpioq0_isr(void);
+void WEAK gpioq1_isr(void);
+void WEAK gpioq2_isr(void);
+void WEAK gpioq3_isr(void);
+void WEAK gpioq4_isr(void);
+void WEAK gpioq5_isr(void);
+void WEAK gpioq6_isr(void);
+void WEAK gpioq7_isr(void);
+void WEAK pwm1_0_isr(void);
+void WEAK pwm1_1_isr(void);
+void WEAK pwm1_2_isr(void);
+void WEAK pwm1_3_isr(void);
+void WEAK pwm1_fault_isr(void);
+
+#pragma weak gpioa_isr = blocking_handler
+#pragma weak gpiob_isr = blocking_handler
+#pragma weak gpioc_isr = blocking_handler
+#pragma weak gpiod_isr = blocking_handler
+#pragma weak gpioe_isr = blocking_handler
+#pragma weak uart0_isr = blocking_handler
+#pragma weak uart1_isr = blocking_handler
+#pragma weak ssi0_isr = blocking_handler
+#pragma weak i2c0_isr = blocking_handler
+#pragma weak pwm0_fault_isr = blocking_handler
+#pragma weak pwm0_0_isr = blocking_handler
+#pragma weak pwm0_1_isr = blocking_handler
+#pragma weak pwm0_2_isr = blocking_handler
+#pragma weak qei0_isr = blocking_handler
+#pragma weak adc0ss0_isr = blocking_handler
+#pragma weak adc0ss1_isr = blocking_handler
+#pragma weak adc0ss2_isr = blocking_handler
+#pragma weak adc0ss3_isr = blocking_handler
+#pragma weak watchdog_isr = blocking_handler
+#pragma weak timer0a_isr = blocking_handler
+#pragma weak timer0b_isr = blocking_handler
+#pragma weak timer1a_isr = blocking_handler
+#pragma weak timer1b_isr = blocking_handler
+#pragma weak timer2a_isr = blocking_handler
+#pragma weak timer2b_isr = blocking_handler
+#pragma weak comp0_isr = blocking_handler
+#pragma weak comp1_isr = blocking_handler
+#pragma weak comp2_isr = blocking_handler
+#pragma weak sysctl_isr = blocking_handler
+#pragma weak flash_isr = blocking_handler
+#pragma weak gpiof_isr = blocking_handler
+#pragma weak gpiog_isr = blocking_handler
+#pragma weak gpioh_isr = blocking_handler
+#pragma weak uart2_isr = blocking_handler
+#pragma weak ssi1_isr = blocking_handler
+#pragma weak timer3a_isr = blocking_handler
+#pragma weak timer3b_isr = blocking_handler
+#pragma weak i2c1_isr = blocking_handler
+#pragma weak qei1_isr = blocking_handler
+#pragma weak can0_isr = blocking_handler
+#pragma weak can1_isr = blocking_handler
+#pragma weak can2_isr = blocking_handler
+#pragma weak eth_isr = blocking_handler
+#pragma weak hibernate_isr = blocking_handler
+#pragma weak usb0_isr = blocking_handler
+#pragma weak pwm0_3_isr = blocking_handler
+#pragma weak udma_isr = blocking_handler
+#pragma weak udmaerr_isr = blocking_handler
+#pragma weak adc1ss0_isr = blocking_handler
+#pragma weak adc1ss1_isr = blocking_handler
+#pragma weak adc1ss2_isr = blocking_handler
+#pragma weak adc1ss3_isr = blocking_handler
+#pragma weak i2s0_isr = blocking_handler
+#pragma weak epi0_isr = blocking_handler
+#pragma weak gpioj_isr = blocking_handler
+#pragma weak gpiok_isr = blocking_handler
+#pragma weak gpiol_isr = blocking_handler
+#pragma weak ssi2_isr = blocking_handler
+#pragma weak ssi3_isr = blocking_handler
+#pragma weak uart3_isr = blocking_handler
+#pragma weak uart4_isr = blocking_handler
+#pragma weak uart5_isr = blocking_handler
+#pragma weak uart6_isr = blocking_handler
+#pragma weak uart7_isr = blocking_handler
+#pragma weak i2c2_isr = blocking_handler
+#pragma weak i2c3_isr = blocking_handler
+#pragma weak timer4a_isr = blocking_handler
+#pragma weak timer4b_isr = blocking_handler
+#pragma weak timer5a_isr = blocking_handler
+#pragma weak timer5b_isr = blocking_handler
+#pragma weak wtimer0a_isr = blocking_handler
+#pragma weak wtimer0b_isr = blocking_handler
+#pragma weak wtimer1a_isr = blocking_handler
+#pragma weak wtimer1b_isr = blocking_handler
+#pragma weak wtimer2a_isr = blocking_handler
+#pragma weak wtimer2b_isr = blocking_handler
+#pragma weak wtimer3a_isr = blocking_handler
+#pragma weak wtimer3b_isr = blocking_handler
+#pragma weak wtimer4a_isr = blocking_handler
+#pragma weak wtimer4b_isr = blocking_handler
+#pragma weak wtimer5a_isr = blocking_handler
+#pragma weak wtimer5b_isr = blocking_handler
+#pragma weak sysexc_isr = blocking_handler
+#pragma weak peci0_isr = blocking_handler
+#pragma weak lpc0_isr = blocking_handler
+#pragma weak i2c4_isr = blocking_handler
+#pragma weak i2c5_isr = blocking_handler
+#pragma weak gpiom_isr = blocking_handler
+#pragma weak gpion_isr = blocking_handler
+#pragma weak fan0_isr = blocking_handler
+#pragma weak gpiop0_isr = blocking_handler
+#pragma weak gpiop1_isr = blocking_handler
+#pragma weak gpiop2_isr = blocking_handler
+#pragma weak gpiop3_isr = blocking_handler
+#pragma weak gpiop4_isr = blocking_handler
+#pragma weak gpiop5_isr = blocking_handler
+#pragma weak gpiop6_isr = blocking_handler
+#pragma weak gpiop7_isr = blocking_handler
+#pragma weak gpioq0_isr = blocking_handler
+#pragma weak gpioq1_isr = blocking_handler
+#pragma weak gpioq2_isr = blocking_handler
+#pragma weak gpioq3_isr = blocking_handler
+#pragma weak gpioq4_isr = blocking_handler
+#pragma weak gpioq5_isr = blocking_handler
+#pragma weak gpioq6_isr = blocking_handler
+#pragma weak gpioq7_isr = blocking_handler
+#pragma weak pwm1_0_isr = blocking_handler
+#pragma weak pwm1_1_isr = blocking_handler
+#pragma weak pwm1_2_isr = blocking_handler
+#pragma weak pwm1_3_isr = blocking_handler
+#pragma weak pwm1_fault_isr = blocking_handler
+
+#define IRQ_HANDLERS \
+ [IRQ_GPIOA] = gpioa_isr, \
+ [IRQ_GPIOB] = gpiob_isr, \
+ [IRQ_GPIOC] = gpioc_isr, \
+ [IRQ_GPIOD] = gpiod_isr, \
+ [IRQ_GPIOE] = gpioe_isr, \
+ [IRQ_UART0] = uart0_isr, \
+ [IRQ_UART1] = uart1_isr, \
+ [IRQ_SSI0] = ssi0_isr, \
+ [IRQ_I2C0] = i2c0_isr, \
+ [IRQ_PWM0_FAULT] = pwm0_fault_isr, \
+ [IRQ_PWM0_0] = pwm0_0_isr, \
+ [IRQ_PWM0_1] = pwm0_1_isr, \
+ [IRQ_PWM0_2] = pwm0_2_isr, \
+ [IRQ_QEI0] = qei0_isr, \
+ [IRQ_ADC0SS0] = adc0ss0_isr, \
+ [IRQ_ADC0SS1] = adc0ss1_isr, \
+ [IRQ_ADC0SS2] = adc0ss2_isr, \
+ [IRQ_ADC0SS3] = adc0ss3_isr, \
+ [IRQ_WATCHDOG] = watchdog_isr, \
+ [IRQ_TIMER0A] = timer0a_isr, \
+ [IRQ_TIMER0B] = timer0b_isr, \
+ [IRQ_TIMER1A] = timer1a_isr, \
+ [IRQ_TIMER1B] = timer1b_isr, \
+ [IRQ_TIMER2A] = timer2a_isr, \
+ [IRQ_TIMER2B] = timer2b_isr, \
+ [IRQ_COMP0] = comp0_isr, \
+ [IRQ_COMP1] = comp1_isr, \
+ [IRQ_COMP2] = comp2_isr, \
+ [IRQ_SYSCTL] = sysctl_isr, \
+ [IRQ_FLASH] = flash_isr, \
+ [IRQ_GPIOF] = gpiof_isr, \
+ [IRQ_GPIOG] = gpiog_isr, \
+ [IRQ_GPIOH] = gpioh_isr, \
+ [IRQ_UART2] = uart2_isr, \
+ [IRQ_SSI1] = ssi1_isr, \
+ [IRQ_TIMER3A] = timer3a_isr, \
+ [IRQ_TIMER3B] = timer3b_isr, \
+ [IRQ_I2C1] = i2c1_isr, \
+ [IRQ_QEI1] = qei1_isr, \
+ [IRQ_CAN0] = can0_isr, \
+ [IRQ_CAN1] = can1_isr, \
+ [IRQ_CAN2] = can2_isr, \
+ [IRQ_ETH] = eth_isr, \
+ [IRQ_HIBERNATE] = hibernate_isr, \
+ [IRQ_USB0] = usb0_isr, \
+ [IRQ_PWM0_3] = pwm0_3_isr, \
+ [IRQ_UDMA] = udma_isr, \
+ [IRQ_UDMAERR] = udmaerr_isr, \
+ [IRQ_ADC1SS0] = adc1ss0_isr, \
+ [IRQ_ADC1SS1] = adc1ss1_isr, \
+ [IRQ_ADC1SS2] = adc1ss2_isr, \
+ [IRQ_ADC1SS3] = adc1ss3_isr, \
+ [IRQ_I2S0] = i2s0_isr, \
+ [IRQ_EPI0] = epi0_isr, \
+ [IRQ_GPIOJ] = gpioj_isr, \
+ [IRQ_GPIOK] = gpiok_isr, \
+ [IRQ_GPIOL] = gpiol_isr, \
+ [IRQ_SSI2] = ssi2_isr, \
+ [IRQ_SSI3] = ssi3_isr, \
+ [IRQ_UART3] = uart3_isr, \
+ [IRQ_UART4] = uart4_isr, \
+ [IRQ_UART5] = uart5_isr, \
+ [IRQ_UART6] = uart6_isr, \
+ [IRQ_UART7] = uart7_isr, \
+ [IRQ_I2C2] = i2c2_isr, \
+ [IRQ_I2C3] = i2c3_isr, \
+ [IRQ_TIMER4A] = timer4a_isr, \
+ [IRQ_TIMER4B] = timer4b_isr, \
+ [IRQ_TIMER5A] = timer5a_isr, \
+ [IRQ_TIMER5B] = timer5b_isr, \
+ [IRQ_WTIMER0A] = wtimer0a_isr, \
+ [IRQ_WTIMER0B] = wtimer0b_isr, \
+ [IRQ_WTIMER1A] = wtimer1a_isr, \
+ [IRQ_WTIMER1B] = wtimer1b_isr, \
+ [IRQ_WTIMER2A] = wtimer2a_isr, \
+ [IRQ_WTIMER2B] = wtimer2b_isr, \
+ [IRQ_WTIMER3A] = wtimer3a_isr, \
+ [IRQ_WTIMER3B] = wtimer3b_isr, \
+ [IRQ_WTIMER4A] = wtimer4a_isr, \
+ [IRQ_WTIMER4B] = wtimer4b_isr, \
+ [IRQ_WTIMER5A] = wtimer5a_isr, \
+ [IRQ_WTIMER5B] = wtimer5b_isr, \
+ [IRQ_SYSEXC] = sysexc_isr, \
+ [IRQ_PECI0] = peci0_isr, \
+ [IRQ_LPC0] = lpc0_isr, \
+ [IRQ_I2C4] = i2c4_isr, \
+ [IRQ_I2C5] = i2c5_isr, \
+ [IRQ_GPIOM] = gpiom_isr, \
+ [IRQ_GPION] = gpion_isr, \
+ [IRQ_FAN0] = fan0_isr, \
+ [IRQ_GPIOP0] = gpiop0_isr, \
+ [IRQ_GPIOP1] = gpiop1_isr, \
+ [IRQ_GPIOP2] = gpiop2_isr, \
+ [IRQ_GPIOP3] = gpiop3_isr, \
+ [IRQ_GPIOP4] = gpiop4_isr, \
+ [IRQ_GPIOP5] = gpiop5_isr, \
+ [IRQ_GPIOP6] = gpiop6_isr, \
+ [IRQ_GPIOP7] = gpiop7_isr, \
+ [IRQ_GPIOQ0] = gpioq0_isr, \
+ [IRQ_GPIOQ1] = gpioq1_isr, \
+ [IRQ_GPIOQ2] = gpioq2_isr, \
+ [IRQ_GPIOQ3] = gpioq3_isr, \
+ [IRQ_GPIOQ4] = gpioq4_isr, \
+ [IRQ_GPIOQ5] = gpioq5_isr, \
+ [IRQ_GPIOQ6] = gpioq6_isr, \
+ [IRQ_GPIOQ7] = gpioq7_isr, \
+ [IRQ_PWM1_0] = pwm1_0_isr, \
+ [IRQ_PWM1_1] = pwm1_1_isr, \
+ [IRQ_PWM1_2] = pwm1_2_isr, \
+ [IRQ_PWM1_3] = pwm1_3_isr, \
+ [IRQ_PWM1_FAULT] = pwm1_fault_isr,
+
+#endif
diff --git a/include/libopencm3/lpc17xx/irq.h b/include/libopencm3/lpc17xx/irq.h
new file mode 100644
index 0000000..9c31267
--- /dev/null
+++ b/include/libopencm3/lpc17xx/irq.h
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
+ * Copyright (C) 2012 chrysn <chrysn@fsfe.org>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_LPC17xx_IRQ_H
+#define LIBOPENCM3_LPC17xx_IRQ_H
+
+/* TODO: Interrupt definitions */
+#define IRQ_COUNT 0
+
+/* TODO: Interrupt handler prototypes */
+
+/* TODO: Interrupt handler weak aliases */
+
+#define IRQ_HANDLERS
+
+#endif
diff --git a/include/libopencm3/lpc43xx/irq.h b/include/libopencm3/lpc43xx/irq.h
new file mode 100644
index 0000000..a83a8d7
--- /dev/null
+++ b/include/libopencm3/lpc43xx/irq.h
@@ -0,0 +1,234 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
+ * Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
+ * Copyright (C) 2012 chrysn <chrysn@fsfe.org>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_LPC43XX_IRQ_H
+#define LIBOPENCM3_LPC43XX_IRQ_H
+
+#define IRQ_DAC 0
+#define IRQ_M0CORE 1
+#define IRQ_DMA 2
+/* reserved: 3 */
+/* reserved: 4 */
+#define IRQ_ETHERNET 5
+#define IRQ_SDIO 6
+#define IRQ_LCD 7
+#define IRQ_USB0 8
+#define IRQ_USB1 9
+#define IRQ_SCT 10
+#define IRQ_RITIMER 11
+#define IRQ_TIMER0 12
+#define IRQ_TIMER1 13
+#define IRQ_TIMER2 14
+#define IRQ_TIMER3 15
+#define IRQ_MCPWM 16
+#define IRQ_ADC0 17
+#define IRQ_I2C0 18
+#define IRQ_I2C1 19
+#define IRQ_SPI 20
+#define IRQ_ADC1 21
+#define IRQ_SSP0 22
+#define IRQ_SSP1 23
+#define IRQ_USART0 24
+#define IRQ_UART1 25
+#define IRQ_USART2 26
+#define IRQ_USART3 27
+#define IRQ_I2S0 28
+#define IRQ_I2S1 29
+#define IRQ_SPIFI 30
+#define IRQ_SGPIO 31
+#define IRQ_PIN_INT0 32
+#define IRQ_PIN_INT1 33
+#define IRQ_PIN_INT2 34
+#define IRQ_PIN_INT3 35
+#define IRQ_PIN_INT4 36
+#define IRQ_PIN_INT5 37
+#define IRQ_PIN_INT6 38
+#define IRQ_PIN_INT7 39
+#define IRQ_GINT0 40
+#define IRQ_GINT1 41
+#define IRQ_EVENTROUTER 42
+#define IRQ_C_CAN1 43
+/* reserved: 44 */
+/* reserved: 45 */
+#define IRQ_ATIMER 46
+#define IRQ_RTC 47
+/* reserved: 48 */
+#define IRQ_WWDT 49
+/* reserved: 50 */
+#define IRQ_C_CAN0 51
+#define IRQ_QEI 52
+
+#define IRQ_COUNT 53
+
+#define WEAK __attribute__ ((weak))
+
+void WEAK dac_irqhandler(void);
+void WEAK m0core_irqhandler(void);
+void WEAK dma_irqhandler(void);
+void WEAK ethernet_irqhandler(void);
+void WEAK sdio_irqhandler(void);
+void WEAK lcd_irqhandler(void);
+void WEAK usb0_irqhandler(void);
+void WEAK usb1_irqhandler(void);
+void WEAK sct_irqhandler(void);
+void WEAK ritimer_irqhandler(void);
+void WEAK timer0_irqhandler(void);
+void WEAK timer1_irqhandler(void);
+void WEAK timer2_irqhandler(void);
+void WEAK timer3_irqhandler(void);
+void WEAK mcpwm_irqhandler(void);
+void WEAK adc0_irqhandler(void);
+void WEAK i2c0_irqhandler(void);
+void WEAK i2c1_irqhandler(void);
+void WEAK spi_irqhandler(void);
+void WEAK adc1_irqhandler(void);
+void WEAK ssp0_irqhandler(void);
+void WEAK ssp1_irqhandler(void);
+void WEAK usart0_irqhandler(void);
+void WEAK uart1_irqhandler(void);
+void WEAK usart2_irqhandler(void);
+void WEAK usart3_irqhandler(void);
+void WEAK i2s0_irqhandler(void);
+void WEAK i2s1_irqhandler(void);
+void WEAK spifi_irqhandler(void);
+void WEAK sgpio_irqhandler(void);
+void WEAK pin_int0_irqhandler(void);
+void WEAK pin_int1_irqhandler(void);
+void WEAK pin_int2_irqhandler(void);
+void WEAK pin_int3_irqhandler(void);
+void WEAK pin_int4_irqhandler(void);
+void WEAK pin_int5_irqhandler(void);
+void WEAK pin_int6_irqhandler(void);
+void WEAK pin_int7_irqhandler(void);
+void WEAK gint0_irqhandler(void);
+void WEAK gint1_irqhandler(void);
+void WEAK eventrouter_irqhandler(void);
+void WEAK c_can1_irqhandler(void);
+void WEAK atimer_irqhandler(void);
+void WEAK rtc_irqhandler(void);
+void WEAK wwdt_irqhandler(void);
+void WEAK c_can0_irqhandler(void);
+void WEAK qei_irqhandler(void);
+
+#pragma weak dac_irqhandler = null_handler
+#pragma weak m0core_irqhandler = null_handler
+#pragma weak dma_irqhandler = null_handler
+#pragma weak ethernet_irqhandler = null_handler
+#pragma weak sdio_irqhandler = null_handler
+#pragma weak lcd_irqhandler = null_handler
+#pragma weak usb0_irqhandler = null_handler
+#pragma weak usb1_irqhandler = null_handler
+#pragma weak sct_irqhandler = null_handler
+#pragma weak ritimer_irqhandler = null_handler
+#pragma weak timer0_irqhandler = null_handler
+#pragma weak timer1_irqhandler = null_handler
+#pragma weak timer2_irqhandler = null_handler
+#pragma weak timer3_irqhandler = null_handler
+#pragma weak mcpwm_irqhandler = null_handler
+#pragma weak adc0_irqhandler = null_handler
+#pragma weak i2c0_irqhandler = null_handler
+#pragma weak i2c1_irqhandler = null_handler
+#pragma weak spi_irqhandler = null_handler
+#pragma weak adc1_irqhandler = null_handler
+#pragma weak ssp0_irqhandler = null_handler
+#pragma weak ssp1_irqhandler = null_handler
+#pragma weak usart0_irqhandler = null_handler
+#pragma weak uart1_irqhandler = null_handler
+#pragma weak usart2_irqhandler = null_handler
+#pragma weak usart3_irqhandler = null_handler
+#pragma weak i2s0_irqhandler = null_handler
+#pragma weak i2s1_irqhandler = null_handler
+#pragma weak spifi_irqhandler = null_handler
+#pragma weak sgpio_irqhandler = null_handler
+#pragma weak pin_int0_irqhandler = null_handler
+#pragma weak pin_int1_irqhandler = null_handler
+#pragma weak pin_int2_irqhandler = null_handler
+#pragma weak pin_int3_irqhandler = null_handler
+#pragma weak pin_int4_irqhandler = null_handler
+#pragma weak pin_int5_irqhandler = null_handler
+#pragma weak pin_int6_irqhandler = null_handler
+#pragma weak pin_int7_irqhandler = null_handler
+#pragma weak gint0_irqhandler = null_handler
+#pragma weak gint1_irqhandler = null_handler
+#pragma weak eventrouter_irqhandler = null_handler
+#pragma weak c_can1_irqhandler = null_handler
+#pragma weak atimer_irqhandler = null_handler
+#pragma weak rtc_irqhandler = null_handler
+#pragma weak wwdt_irqhandler = null_handler
+#pragma weak c_can0_irqhandler = null_handler
+#pragma weak qei_irqhandler = null_handler
+
+#define IRQ_HANDLERS \
+ dac_irqhandler, \
+ m0core_irqhandler, \
+ dma_irqhandler, \
+ 0, /* reserved */ \
+ 0, /* reserved */ \
+ ethernet_irqhandler, \
+ sdio_irqhandler, \
+ lcd_irqhandler, \
+ usb0_irqhandler, \
+ usb1_irqhandler, \
+ sct_irqhandler, \
+ ritimer_irqhandler, \
+ timer0_irqhandler, \
+ timer1_irqhandler, \
+ timer2_irqhandler, \
+ timer3_irqhandler, \
+ mcpwm_irqhandler, \
+ adc0_irqhandler, \
+ i2c0_irqhandler, \
+ i2c1_irqhandler, \
+ spi_irqhandler, \
+ adc1_irqhandler, \
+ ssp0_irqhandler, \
+ ssp1_irqhandler, \
+ usart0_irqhandler, \
+ uart1_irqhandler, \
+ usart2_irqhandler, \
+ usart3_irqhandler, \
+ i2s0_irqhandler, \
+ i2s1_irqhandler, \
+ spifi_irqhandler, \
+ sgpio_irqhandler, \
+ pin_int0_irqhandler, \
+ pin_int1_irqhandler, \
+ pin_int2_irqhandler, \
+ pin_int3_irqhandler, \
+ pin_int4_irqhandler, \
+ pin_int5_irqhandler, \
+ pin_int6_irqhandler, \
+ pin_int7_irqhandler, \
+ gint0_irqhandler, \
+ gint1_irqhandler, \
+ eventrouter_irqhandler, \
+ c_can1_irqhandler, \
+ 0, /* reserved */ \
+ 0, /* reserved */ \
+ atimer_irqhandler, \
+ rtc_irqhandler, \
+ 0, /* reserved */ \
+ wwdt_irqhandler, \
+ 0, /* reserved */ \
+ c_can0_irqhandler, \
+ qei_irqhandler,
+
+#endif
diff --git a/include/libopencm3/stm32/f1/irq.h b/include/libopencm3/stm32/f1/irq.h
new file mode 100644
index 0000000..cfa07f1
--- /dev/null
+++ b/include/libopencm3/stm32/f1/irq.h
@@ -0,0 +1,306 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
+ * Copyright (C) 2012 chrysn <chrysn@fsfe.org>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_STM32_F1_IRQ_H
+#define LIBOPENCM3_STM32_F1_IRQ_H
+
+#define IRQ_WWDG 0
+#define IRQ_PVD 1
+#define IRQ_TAMPER 2
+#define IRQ_RTC 3
+#define IRQ_FLASH 4
+#define IRQ_RCC 5
+#define IRQ_EXTI0 6
+#define IRQ_EXTI1 7
+#define IRQ_EXTI2 8
+#define IRQ_EXTI3 9
+#define IRQ_EXTI4 10
+#define IRQ_DMA1_CHANNEL1 11
+#define IRQ_DMA1_CHANNEL2 12
+#define IRQ_DMA1_CHANNEL3 13
+#define IRQ_DMA1_CHANNEL4 14
+#define IRQ_DMA1_CHANNEL5 15
+#define IRQ_DMA1_CHANNEL6 16
+#define IRQ_DMA1_CHANNEL7 17
+#define IRQ_ADC1_2 18
+#define IRQ_USB_HP_CAN_TX 19
+#define IRQ_USB_LP_CAN_RX0 20
+#define IRQ_CAN_RX1 21
+#define IRQ_CAN_SCE 22
+#define IRQ_EXTI9_5 23
+#define IRQ_TIM1_BRK 24
+#define IRQ_TIM1_UP 25
+#define IRQ_TIM1_TRG_COM 26
+#define IRQ_TIM1_CC 27
+#define IRQ_TIM2 28
+#define IRQ_TIM3 29
+#define IRQ_TIM4 30
+#define IRQ_I2C1_EV 31
+#define IRQ_I2C1_ER 32
+#define IRQ_I2C2_EV 33
+#define IRQ_I2C2_ER 34
+#define IRQ_SPI1 35
+#define IRQ_SPI2 36
+#define IRQ_USART1 37
+#define IRQ_USART2 38
+#define IRQ_USART3 39
+#define IRQ_EXTI15_10 40
+#define IRQ_RTC_ALARM 41
+#define IRQ_USB_WAKEUP 42
+#define IRQ_TIM8_BRK 43
+#define IRQ_TIM8_UP 44
+#define IRQ_TIM8_TRG_COM 45
+#define IRQ_TIM8_CC 46
+#define IRQ_ADC3 47
+#define IRQ_FSMC 48
+#define IRQ_SDIO 49
+#define IRQ_TIM5 50
+#define IRQ_SPI3 51
+#define IRQ_UART4 52
+#define IRQ_UART5 53
+#define IRQ_TIM6 54
+#define IRQ_TIM7 55
+#define IRQ_DMA2_CHANNEL1 56
+#define IRQ_DMA2_CHANNEL2 57
+#define IRQ_DMA2_CHANNEL3 58
+#define IRQ_DMA2_CHANNEL4_5 59
+#define IRQ_DMA2_CHANNEL5 60
+#define IRQ_ETH 61
+#define IRQ_ETH_WKUP 62
+#define IRQ_CAN2_TX 63
+#define IRQ_CAN2_RX0 64
+#define IRQ_CAN2_RX1 65
+#define IRQ_CAN2_SCE 66
+#define IRQ_OTG_FS 67
+
+/* FIXME: number from list in lib/stm32/f1/vector.c, might miss irqs */
+#define IRQ_COUNT 68
+
+#define WEAK __attribute__ ((weak))
+
+void WEAK wwdg_isr(void);
+void WEAK pvd_isr(void);
+void WEAK tamper_isr(void);
+void WEAK rtc_isr(void);
+void WEAK flash_isr(void);
+void WEAK rcc_isr(void);
+void WEAK exti0_isr(void);
+void WEAK exti1_isr(void);
+void WEAK exti2_isr(void);
+void WEAK exti3_isr(void);
+void WEAK exti4_isr(void);
+void WEAK dma1_channel1_isr(void);
+void WEAK dma1_channel2_isr(void);
+void WEAK dma1_channel3_isr(void);
+void WEAK dma1_channel4_isr(void);
+void WEAK dma1_channel5_isr(void);
+void WEAK dma1_channel6_isr(void);
+void WEAK dma1_channel7_isr(void);
+void WEAK adc1_2_isr(void);
+void WEAK usb_hp_can_tx_isr(void);
+void WEAK usb_lp_can_rx0_isr(void);
+void WEAK can_rx1_isr(void);
+void WEAK can_sce_isr(void);
+void WEAK exti9_5_isr(void);
+void WEAK tim1_brk_isr(void);
+void WEAK tim1_up_isr(void);
+void WEAK tim1_trg_com_isr(void);
+void WEAK tim1_cc_isr(void);
+void WEAK tim2_isr(void);
+void WEAK tim3_isr(void);
+void WEAK tim4_isr(void);
+void WEAK i2c1_ev_isr(void);
+void WEAK i2c1_er_isr(void);
+void WEAK i2c2_ev_isr(void);
+void WEAK i2c2_er_isr(void);
+void WEAK spi1_isr(void);
+void WEAK spi2_isr(void);
+void WEAK usart1_isr(void);
+void WEAK usart2_isr(void);
+void WEAK usart3_isr(void);
+void WEAK exti15_10_isr(void);
+void WEAK rtc_alarm_isr(void);
+void WEAK usb_wakeup_isr(void);
+void WEAK tim8_brk_isr(void);
+void WEAK tim8_up_isr(void);
+void WEAK tim8_trg_com_isr(void);
+void WEAK tim8_cc_isr(void);
+void WEAK adc3_isr(void);
+void WEAK fsmc_isr(void);
+void WEAK sdio_isr(void);
+void WEAK tim5_isr(void);
+void WEAK spi3_isr(void);
+void WEAK uart4_isr(void);
+void WEAK uart5_isr(void);
+void WEAK tim6_isr(void);
+void WEAK tim7_isr(void);
+void WEAK dma2_channel1_isr(void);
+void WEAK dma2_channel2_isr(void);
+void WEAK dma2_channel3_isr(void);
+void WEAK dma2_channel4_5_isr(void);
+void WEAK dma2_channel5_isr(void);
+void WEAK eth_isr(void);
+void WEAK eth_wkup_isr(void);
+void WEAK can2_tx_isr(void);
+void WEAK can2_rx0_isr(void);
+void WEAK can2_rx1_isr(void);
+void WEAK can2_sce_isr(void);
+void WEAK otg_fs_isr(void);
+
+#pragma weak wwdg_isr = null_handler
+#pragma weak pvd_isr = null_handler
+#pragma weak tamper_isr = null_handler
+#pragma weak rtc_isr = null_handler
+#pragma weak flash_isr = null_handler
+#pragma weak rcc_isr = null_handler
+#pragma weak exti0_isr = null_handler
+#pragma weak exti1_isr = null_handler
+#pragma weak exti2_isr = null_handler
+#pragma weak exti3_isr = null_handler
+#pragma weak exti4_isr = null_handler
+#pragma weak dma1_channel1_isr = null_handler
+#pragma weak dma1_channel2_isr = null_handler
+#pragma weak dma1_channel3_isr = null_handler
+#pragma weak dma1_channel4_isr = null_handler
+#pragma weak dma1_channel5_isr = null_handler
+#pragma weak dma1_channel6_isr = null_handler
+#pragma weak dma1_channel7_isr = null_handler
+#pragma weak adc1_2_isr = null_handler
+#pragma weak usb_hp_can_tx_isr = null_handler
+#pragma weak usb_lp_can_rx0_isr = null_handler
+#pragma weak can_rx1_isr = null_handler
+#pragma weak can_sce_isr = null_handler
+#pragma weak exti9_5_isr = null_handler
+#pragma weak tim1_brk_isr = null_handler
+#pragma weak tim1_up_isr = null_handler
+#pragma weak tim1_trg_com_isr = null_handler
+#pragma weak tim1_cc_isr = null_handler
+#pragma weak tim2_isr = null_handler
+#pragma weak tim3_isr = null_handler
+#pragma weak tim4_isr = null_handler
+#pragma weak i2c1_ev_isr = null_handler
+#pragma weak i2c1_er_isr = null_handler
+#pragma weak i2c2_ev_isr = null_handler
+#pragma weak i2c2_er_isr = null_handler
+#pragma weak spi1_isr = null_handler
+#pragma weak spi2_isr = null_handler
+#pragma weak usart1_isr = null_handler
+#pragma weak usart2_isr = null_handler
+#pragma weak usart3_isr = null_handler
+#pragma weak exti15_10_isr = null_handler
+#pragma weak rtc_alarm_isr = null_handler
+#pragma weak usb_wakeup_isr = null_handler
+#pragma weak tim8_brk_isr = null_handler
+#pragma weak tim8_up_isr = null_handler
+#pragma weak tim8_trg_com_isr = null_handler
+#pragma weak tim8_cc_isr = null_handler
+#pragma weak adc3_isr = null_handler
+#pragma weak fsmc_isr = null_handler
+#pragma weak sdio_isr = null_handler
+#pragma weak tim5_isr = null_handler
+#pragma weak spi3_isr = null_handler
+#pragma weak uart4_isr = null_handler
+#pragma weak uart5_isr = null_handler
+#pragma weak tim6_isr = null_handler
+#pragma weak tim7_isr = null_handler
+#pragma weak dma2_channel1_isr = null_handler
+#pragma weak dma2_channel2_isr = null_handler
+#pragma weak dma2_channel3_isr = null_handler
+#pragma weak dma2_channel4_5_isr = null_handler
+#pragma weak dma2_channel5_isr
+#pragma weak eth_isr = null_handler
+#pragma weak eth_wkup_isr = null_handler
+#pragma weak can2_tx_isr = null_handler
+#pragma weak can2_rx0_isr = null_handler
+#pragma weak can2_rx1_isr = null_handler
+#pragma weak can2_sce_isr = null_handler
+#pragma weak otg_fs_isr = null_handler
+
+#define IRQ_HANDLERS \
+ wwdg_isr, \
+ pvd_isr, \
+ tamper_isr, \
+ rtc_isr, \
+ flash_isr, \
+ rcc_isr, \
+ exti0_isr, \
+ exti1_isr, \
+ exti2_isr, \
+ exti3_isr, \
+ exti4_isr, \
+ dma1_channel1_isr, \
+ dma1_channel2_isr, \
+ dma1_channel3_isr, \
+ dma1_channel4_isr, \
+ dma1_channel5_isr, \
+ dma1_channel6_isr, \
+ dma1_channel7_isr, \
+ adc1_2_isr, \
+ usb_hp_can_tx_isr, \
+ usb_lp_can_rx0_isr, \
+ can_rx1_isr, \
+ can_sce_isr, \
+ exti9_5_isr, \
+ tim1_brk_isr, \
+ tim1_up_isr, \
+ tim1_trg_com_isr, \
+ tim1_cc_isr, \
+ tim2_isr, \
+ tim3_isr, \
+ tim4_isr, \
+ i2c1_ev_isr, \
+ i2c1_er_isr, \
+ i2c2_ev_isr, \
+ i2c2_er_isr, \
+ spi1_isr, \
+ spi2_isr, \
+ usart1_isr, \
+ usart2_isr, \
+ usart3_isr, \
+ exti15_10_isr, \
+ rtc_alarm_isr, \
+ usb_wakeup_isr, \
+ tim8_brk_isr, \
+ tim8_up_isr, \
+ tim8_trg_com_isr, \
+ tim8_cc_isr, \
+ adc3_isr, \
+ fsmc_isr, \
+ sdio_isr, \
+ tim5_isr, \
+ spi3_isr, \
+ uart4_isr, \
+ uart5_isr, \
+ tim6_isr, \
+ tim7_isr, \
+ dma2_channel1_isr, \
+ dma2_channel2_isr, \
+ dma2_channel3_isr, \
+ dma2_channel4_5_isr, \
+ dma2_channel5_isr, \
+ eth_isr, \
+ eth_wkup_isr, \
+ can2_tx_isr, \
+ can2_rx0_isr, \
+ can2_rx1_isr, \
+ can2_sce_isr, \
+ otg_fs_isr, \
+
+#endif
diff --git a/include/libopencm3/stm32/f2/irq.h b/include/libopencm3/stm32/f2/irq.h
new file mode 100644
index 0000000..7aec142
--- /dev/null
+++ b/include/libopencm3/stm32/f2/irq.h
@@ -0,0 +1,359 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
+ * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
+ * Copyright (C) 2012 chrysn <chrysn@fsfe.org>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_STM32_F2_IRQ_H
+#define LIBOPENCM3_STM32_F2_IRQ_H
+
+#define IRQ_WWDG 0
+#define IRQ_PVD 1
+#define IRQ_TAMP_STAMP 2
+#define IRQ_RTC_WKUP 3
+#define IRQ_FLASH 4
+#define IRQ_RCC 5
+#define IRQ_EXTI0 6
+#define IRQ_EXTI1 7
+#define IRQ_EXTI2 8
+#define IRQ_EXTI3 9
+#define IRQ_EXTI4 10
+#define IRQ_DMA1_STREAM0 11
+#define IRQ_DMA1_STREAM1 12
+#define IRQ_DMA1_STREAM2 13
+#define IRQ_DMA1_STREAM3 14
+#define IRQ_DMA1_STREAM4 15
+#define IRQ_DMA1_STREAM5 16
+#define IRQ_DMA1_STREAM6 17
+#define IRQ_ADC 18
+#define IRQ_CAN1_TX 19
+#define IRQ_CAN1_RX0 20
+#define IRQ_CAN1_RX1 21
+#define IRQ_CAN1_SCE 22
+#define IRQ_EXTI9_5 23
+#define IRQ_TIM1_BRK_TIM9 24
+#define IRQ_TIM1_UP_TIM10 25
+#define IRQ_TIM1_TRG_COM_TIM11 26
+#define IRQ_TIM1_CC 27
+#define IRQ_TIM2 28
+#define IRQ_TIM3 29
+#define IRQ_TIM4 30
+#define IRQ_I2C1_EV 31
+#define IRQ_I2C1_ER 32
+#define IRQ_I2C2_EV 33
+#define IRQ_I2C2_ER 34
+#define IRQ_SPI1 35
+#define IRQ_SPI2 36
+#define IRQ_USART1 37
+#define IRQ_USART2 38
+#define IRQ_USART3 39
+#define IRQ_EXTI15_10 40
+#define IRQ_RTC_ALARM 41
+#define IRQ_USB_FS_WKUP 42
+#define IRQ_TIM8_BRK_TIM12 43
+#define IRQ_TIM8_UP_TIM13 44
+#define IRQ_TIM8_TRG_COM_TIM14 45
+#define IRQ_TIM8_CC 46
+#define IRQ_DMA1_STREAM7 47
+#define IRQ_FSMC 48
+#define IRQ_SDIO 49
+#define IRQ_TIM5 50
+#define IRQ_SPI3 51
+#define IRQ_UART4 52
+#define IRQ_UART5 53
+#define IRQ_TIM6_DAC 54
+#define IRQ_TIM7 55
+#define IRQ_DMA2_STREAM0 56
+#define IRQ_DMA2_STREAM1 57
+#define IRQ_DMA2_STREAM2 58
+#define IRQ_DMA2_STREAM3 59
+#define IRQ_DMA2_STREAM4 60
+#define IRQ_ETH 61
+#define IRQ_ETH_WKUP 62
+#define IRQ_CAN2_TX 63
+#define IRQ_CAN2_RX0 64
+#define IRQ_CAN2_RX1 65
+#define IRQ_CAN2_SCE 66
+#define IRQ_OTG_FS 67
+#define IRQ_DMA2_STREAM5 68
+#define IRQ_DMA2_STREAM6 69
+#define IRQ_DMA2_STREAM7 70
+#define IRQ_USART6 71
+#define IRQ_I2C3_EV 72
+#define IRQ_I2C3_ER 73
+#define IRQ_OTG_HS_EP1_OUT 74
+#define IRQ_OTG_HS_EP1_IN 75
+#define IRQ_OTG_HS_WKUP 76
+#define IRQ_OTG_HS 77
+#define IRQ_DCMI 78
+#define IRQ_CRYP 79
+#define IRQ_HASH_RNG 80
+
+/* FIXME: number from list in lib/stm32/f2/vector.c, might miss irqs */
+#define IRQ_COUNT 81
+
+#define WEAK __attribute__ ((weak))
+
+void WEAK wwdg_isr(void);
+void WEAK pvd_isr(void);
+void WEAK tamp_stamp_isr(void);
+void WEAK rtc_wkup_isr(void);
+void WEAK flash_isr(void);
+void WEAK rcc_isr(void);
+void WEAK exti0_isr(void);
+void WEAK exti1_isr(void);
+void WEAK exti2_isr(void);
+void WEAK exti3_isr(void);
+void WEAK exti4_isr(void);
+void WEAK dma1_stream0_isr(void);
+void WEAK dma1_stream1_isr(void);
+void WEAK dma1_stream2_isr(void);
+void WEAK dma1_stream3_isr(void);
+void WEAK dma1_stream4_isr(void);
+void WEAK dma1_stream5_isr(void);
+void WEAK dma1_stream6_isr(void);
+void WEAK adc_isr(void);
+void WEAK can1_tx_isr(void);
+void WEAK can1_rx0_isr(void);
+void WEAK can1_rx1_isr(void);
+void WEAK can1_sce_isr(void);
+void WEAK exti9_5_isr(void);
+void WEAK tim1_brk_tim9_isr(void);
+void WEAK tim1_up_tim10_isr(void);
+void WEAK tim1_trg_com_tim11_isr(void);
+void WEAK tim1_cc_isr(void);
+void WEAK tim2_isr(void);
+void WEAK tim3_isr(void);
+void WEAK tim4_isr(void);
+void WEAK i2c1_ev_isr(void);
+void WEAK i2c1_er_isr(void);
+void WEAK i2c2_ev_isr(void);
+void WEAK i2c2_er_isr(void);
+void WEAK spi1_isr(void);
+void WEAK spi2_isr(void);
+void WEAK usart1_isr(void);
+void WEAK usart2_isr(void);
+void WEAK usart3_isr(void);
+void WEAK exti15_10_isr(void);
+void WEAK rtc_alarm_isr(void);
+void WEAK usb_fs_wkup_isr(void);
+void WEAK tim8_brk_tim12_isr(void);
+void WEAK tim8_up_tim13_isr(void);
+void WEAK tim8_trg_com_tim14_isr(void);
+void WEAK tim8_cc_isr(void);
+void WEAK dma1_stream7_isr(void);
+void WEAK fsmc_isr(void);
+void WEAK sdio_isr(void);
+void WEAK tim5_isr(void);
+void WEAK spi3_isr(void);
+void WEAK uart4_isr(void);
+void WEAK uart5_isr(void);
+void WEAK tim6_dac_isr(void);
+void WEAK tim7_isr(void);
+void WEAK dma2_stream0_isr(void);
+void WEAK dma2_stream1_isr(void);
+void WEAK dma2_stream2_isr(void);
+void WEAK dma2_stream3_isr(void);
+void WEAK dma2_stream4_isr(void);
+void WEAK eth_isr(void);
+void WEAK eth_wkup_isr(void);
+void WEAK can2_tx_isr(void);
+void WEAK can2_rx0_isr(void);
+void WEAK can2_rx1_isr(void);
+void WEAK can2_sce_isr(void);
+void WEAK otg_fs_isr(void);
+void WEAK dma2_stream5_isr(void);
+void WEAK dma2_stream6_isr(void);
+void WEAK dma2_stream7_isr(void);
+void WEAK usart6_isr(void);
+void WEAK i2c3_ev_isr(void);
+void WEAK i2c3_er_isr(void);
+void WEAK otg_hs_ep1_out_isr(void);
+void WEAK otg_hs_ep1_in_isr(void);
+void WEAK otg_hs_wkup_isr(void);
+void WEAK otg_hs_isr(void);
+void WEAK dcmi_isr(void);
+void WEAK cryp_isr(void);
+void WEAK hash_rng_isr(void);
+
+#pragma weak wwdg_isr = null_handler
+#pragma weak pvd_isr = null_handler
+#pragma weak tamp_stamp_isr = null_handler
+#pragma weak rtc_wkup_isr = null_handler
+#pragma weak flash_isr = null_handler
+#pragma weak rcc_isr = null_handler
+#pragma weak exti0_isr = null_handler
+#pragma weak exti1_isr = null_handler
+#pragma weak exti2_isr = null_handler
+#pragma weak exti3_isr = null_handler
+#pragma weak exti4_isr = null_handler
+#pragma weak dma1_stream0_isr = null_handler
+#pragma weak dma1_stream1_isr = null_handler
+#pragma weak dma1_stream2_isr = null_handler
+#pragma weak dma1_stream3_isr = null_handler
+#pragma weak dma1_stream4_isr = null_handler
+#pragma weak dma1_stream5_isr = null_handler
+#pragma weak dma1_stream6_isr = null_handler
+#pragma weak adc_isr = null_handler
+#pragma weak can1_tx_isr = null_handler
+#pragma weak can1_rx0_isr = null_handler
+#pragma weak can1_rx1_isr = null_handler
+#pragma weak can1_sce_isr = null_handler
+#pragma weak exti9_5_isr = null_handler
+#pragma weak tim1_brk_tim9_isr = null_handler
+#pragma weak tim1_up_tim10_isr = null_handler
+#pragma weak tim1_trg_com_tim11_isr = null_handler
+#pragma weak tim1_cc_isr = null_handler
+#pragma weak tim2_isr = null_handler
+#pragma weak tim3_isr = null_handler
+#pragma weak tim4_isr = null_handler
+#pragma weak i2c1_ev_isr = null_handler
+#pragma weak i2c1_er_isr = null_handler
+#pragma weak i2c2_ev_isr = null_handler
+#pragma weak i2c2_er_isr = null_handler
+#pragma weak spi1_isr = null_handler
+#pragma weak spi2_isr = null_handler
+#pragma weak usart1_isr = null_handler
+#pragma weak usart2_isr = null_handler
+#pragma weak usart3_isr = null_handler
+#pragma weak exti15_10_isr = null_handler
+#pragma weak rtc_alarm_isr = null_handler
+#pragma weak usb_fs_wkup_isr = null_handler
+#pragma weak tim8_brk_tim12_isr = null_handler
+#pragma weak tim8_up_tim13_isr = null_handler
+#pragma weak tim8_trg_com_tim14_isr = null_handler
+#pragma weak tim8_cc_isr = null_handler
+#pragma weak dma1_stream7_isr = null_handler
+#pragma weak fsmc_isr = null_handler
+#pragma weak sdio_isr = null_handler
+#pragma weak tim5_isr = null_handler
+#pragma weak spi3_isr = null_handler
+#pragma weak uart4_isr = null_handler
+#pragma weak uart5_isr = null_handler
+#pragma weak tim6_dac_isr = null_handler
+#pragma weak tim7_isr = null_handler
+#pragma weak dma2_stream0_isr = null_handler
+#pragma weak dma2_stream1_isr = null_handler
+#pragma weak dma2_stream2_isr = null_handler
+#pragma weak dma2_stream3_isr = null_handler
+#pragma weak dma2_stream4_isr = null_handler
+#pragma weak eth_isr = null_handler
+#pragma weak eth_wkup_isr = null_handler
+#pragma weak can2_tx_isr = null_handler
+#pragma weak can2_rx0_isr = null_handler
+#pragma weak can2_rx1_isr = null_handler
+#pragma weak can2_sce_isr = null_handler
+#pragma weak otg_fs_isr = null_handler
+#pragma weak dma2_stream5_isr = null_handler
+#pragma weak dma2_stream6_isr = null_handler
+#pragma weak dma2_stream7_isr = null_handler
+#pragma weak usart6_isr = null_handler
+#pragma weak i2c3_ev_isr = null_handler
+#pragma weak i2c3_er_isr = null_handler
+#pragma weak otg_hs_ep1_out_isr = null_handler
+#pragma weak otg_hs_ep1_in_isr = null_handler
+#pragma weak otg_hs_wkup_isr = null_handler
+#pragma weak otg_hs_isr = null_handler
+#pragma weak dcmi_isr = null_handler
+#pragma weak cryp_isr = null_handler
+#pragma weak hash_rng_isr = null_handler
+
+#define IRQ_HANDLERS \
+ wwdg_isr, \
+ pvd_isr, \
+ tamp_stamp_isr, \
+ rtc_wkup_isr, \
+ flash_isr, \
+ rcc_isr, \
+ exti0_isr, \
+ exti1_isr, \
+ exti2_isr, \
+ exti3_isr, \
+ exti4_isr, \
+ dma1_stream0_isr, \
+ dma1_stream1_isr, \
+ dma1_stream2_isr, \
+ dma1_stream3_isr, \
+ dma1_stream4_isr, \
+ dma1_stream5_isr, \
+ dma1_stream6_isr, \
+ adc_isr, \
+ can1_tx_isr, \
+ can1_rx0_isr, \
+ can1_rx1_isr, \
+ can1_sce_isr, \
+ exti9_5_isr, \
+ tim1_brk_tim9_isr, \
+ tim1_up_tim10_isr, \
+ tim1_trg_com_tim11_isr, \
+ tim1_cc_isr, \
+ tim2_isr, \
+ tim3_isr, \
+ tim4_isr, \
+ i2c1_ev_isr, \
+ i2c1_er_isr, \
+ i2c2_ev_isr, \
+ i2c2_er_isr, \
+ spi1_isr, \
+ spi2_isr, \
+ usart1_isr, \
+ usart2_isr, \
+ usart3_isr, \
+ exti15_10_isr, \
+ rtc_alarm_isr, \
+ usb_fs_wkup_isr, \
+ tim8_brk_tim12_isr, \
+ tim8_up_tim13_isr, \
+ tim8_trg_com_tim14_isr, \
+ tim8_cc_isr, \
+ dma1_stream7_isr, \
+ fsmc_isr, \
+ sdio_isr, \
+ tim5_isr, \
+ spi3_isr, \
+ uart4_isr, \
+ uart5_isr, \
+ tim6_dac_isr, \
+ tim7_isr, \
+ dma2_stream0_isr, \
+ dma2_stream1_isr, \
+ dma2_stream2_isr, \
+ dma2_stream3_isr, \
+ dma2_stream4_isr, \
+ eth_isr, \
+ eth_wkup_isr, \
+ can2_tx_isr, \
+ can2_rx0_isr, \
+ can2_rx1_isr, \
+ can2_sce_isr, \
+ otg_fs_isr, \
+ dma2_stream5_isr, \
+ dma2_stream6_isr, \
+ dma2_stream7_isr, \
+ usart6_isr, \
+ i2c3_ev_isr, \
+ i2c3_er_isr, \
+ otg_hs_ep1_out_isr, \
+ otg_hs_ep1_in_isr, \
+ otg_hs_wkup_isr, \
+ otg_hs_isr, \
+ dcmi_isr, \
+ cryp_isr, \
+ hash_rng_isr,
+
+#endif
diff --git a/include/libopencm3/stm32/f4/irq.h b/include/libopencm3/stm32/f4/irq.h
new file mode 100644
index 0000000..4f4f5e5
--- /dev/null
+++ b/include/libopencm3/stm32/f4/irq.h
@@ -0,0 +1,359 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
+ * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
+ * Copyright (C) 2012 chrysn <chrysn@fsfe.org>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_STM32_F4_IRQ_H
+#define LIBOPENCM3_STM32_F4_IRQ_H
+
+#define IRQ_WWDG 0
+#define IRQ_PVD 1
+#define IRQ_TAMP_STAMP 2
+#define IRQ_RTC_WKUP 3
+#define IRQ_FLASH 4
+#define IRQ_RCC 5
+#define IRQ_EXTI0 6
+#define IRQ_EXTI1 7
+#define IRQ_EXTI2 8
+#define IRQ_EXTI3 9
+#define IRQ_EXTI4 10
+#define IRQ_DMA1_STREAM0 11
+#define IRQ_DMA1_STREAM1 12
+#define IRQ_DMA1_STREAM2 13
+#define IRQ_DMA1_STREAM3 14
+#define IRQ_DMA1_STREAM4 15
+#define IRQ_DMA1_STREAM5 16
+#define IRQ_DMA1_STREAM6 17
+#define IRQ_ADC 18
+#define IRQ_CAN1_TX 19
+#define IRQ_CAN1_RX0 20
+#define IRQ_CAN1_RX1 21
+#define IRQ_CAN1_SCE 22
+#define IRQ_EXTI9_5 23
+#define IRQ_TIM1_BRK_TIM9 24
+#define IRQ_TIM1_UP_TIM10 25
+#define IRQ_TIM1_TRG_COM_TIM11 26
+#define IRQ_TIM1_CC 27
+#define IRQ_TIM2 28
+#define IRQ_TIM3 29
+#define IRQ_TIM4 30
+#define IRQ_I2C1_EV 31
+#define IRQ_I2C1_ER 32
+#define IRQ_I2C2_EV 33
+#define IRQ_I2C2_ER 34
+#define IRQ_SPI1 35
+#define IRQ_SPI2 36
+#define IRQ_USART1 37
+#define IRQ_USART2 38
+#define IRQ_USART3 39
+#define IRQ_EXTI15_10 40
+#define IRQ_RTC_ALARM 41
+#define IRQ_USB_FS_WKUP 42
+#define IRQ_TIM8_BRK_TIM12 43
+#define IRQ_TIM8_UP_TIM13 44
+#define IRQ_TIM8_TRG_COM_TIM14 45
+#define IRQ_TIM8_CC 46
+#define IRQ_DMA1_STREAM7 47
+#define IRQ_FSMC 48
+#define IRQ_SDIO 49
+#define IRQ_TIM5 50
+#define IRQ_SPI3 51
+#define IRQ_UART4 52
+#define IRQ_UART5 53
+#define IRQ_TIM6_DAC 54
+#define IRQ_TIM7 55
+#define IRQ_DMA2_STREAM0 56
+#define IRQ_DMA2_STREAM1 57
+#define IRQ_DMA2_STREAM2 58
+#define IRQ_DMA2_STREAM3 59
+#define IRQ_DMA2_STREAM4 60
+#define IRQ_ETH 61
+#define IRQ_ETH_WKUP 62
+#define IRQ_CAN2_TX 63
+#define IRQ_CAN2_RX0 64
+#define IRQ_CAN2_RX1 65
+#define IRQ_CAN2_SCE 66
+#define IRQ_OTG_FS 67
+#define IRQ_DMA2_STREAM5 68
+#define IRQ_DMA2_STREAM6 69
+#define IRQ_DMA2_STREAM7 70
+#define IRQ_USART6 71
+#define IRQ_I2C3_EV 72
+#define IRQ_I2C3_ER 73
+#define IRQ_OTG_HS_EP1_OUT 74
+#define IRQ_OTG_HS_EP1_IN 75
+#define IRQ_OTG_HS_WKUP 76
+#define IRQ_OTG_HS 77
+#define IRQ_DCMI 78
+#define IRQ_CRYP 79
+#define IRQ_HASH_RNG 80
+
+/* FIXME: number from list in lib/stm32/f4/vector.c, might miss irqs */
+#define IRQ_COUNT 81
+
+#define WEAK __attribute__ ((weak))
+
+void WEAK wwdg_isr(void);
+void WEAK pvd_isr(void);
+void WEAK tamp_stamp_isr(void);
+void WEAK rtc_wkup_isr(void);
+void WEAK flash_isr(void);
+void WEAK rcc_isr(void);
+void WEAK exti0_isr(void);
+void WEAK exti1_isr(void);
+void WEAK exti2_isr(void);
+void WEAK exti3_isr(void);
+void WEAK exti4_isr(void);
+void WEAK dma1_stream0_isr(void);
+void WEAK dma1_stream1_isr(void);
+void WEAK dma1_stream2_isr(void);
+void WEAK dma1_stream3_isr(void);
+void WEAK dma1_stream4_isr(void);
+void WEAK dma1_stream5_isr(void);
+void WEAK dma1_stream6_isr(void);
+void WEAK adc_isr(void);
+void WEAK can1_tx_isr(void);
+void WEAK can1_rx0_isr(void);
+void WEAK can1_rx1_isr(void);
+void WEAK can1_sce_isr(void);
+void WEAK exti9_5_isr(void);
+void WEAK tim1_brk_tim9_isr(void);
+void WEAK tim1_up_tim10_isr(void);
+void WEAK tim1_trg_com_tim11_isr(void);
+void WEAK tim1_cc_isr(void);
+void WEAK tim2_isr(void);
+void WEAK tim3_isr(void);
+void WEAK tim4_isr(void);
+void WEAK i2c1_ev_isr(void);
+void WEAK i2c1_er_isr(void);
+void WEAK i2c2_ev_isr(void);
+void WEAK i2c2_er_isr(void);
+void WEAK spi1_isr(void);
+void WEAK spi2_isr(void);
+void WEAK usart1_isr(void);
+void WEAK usart2_isr(void);
+void WEAK usart3_isr(void);
+void WEAK exti15_10_isr(void);
+void WEAK rtc_alarm_isr(void);
+void WEAK usb_fs_wkup_isr(void);
+void WEAK tim8_brk_tim12_isr(void);
+void WEAK tim8_up_tim13_isr(void);
+void WEAK tim8_trg_com_tim14_isr(void);
+void WEAK tim8_cc_isr(void);
+void WEAK dma1_stream7_isr(void);
+void WEAK fsmc_isr(void);
+void WEAK sdio_isr(void);
+void WEAK tim5_isr(void);
+void WEAK spi3_isr(void);
+void WEAK uart4_isr(void);
+void WEAK uart5_isr(void);
+void WEAK tim6_dac_isr(void);
+void WEAK tim7_isr(void);
+void WEAK dma2_stream0_isr(void);
+void WEAK dma2_stream1_isr(void);
+void WEAK dma2_stream2_isr(void);
+void WEAK dma2_stream3_isr(void);
+void WEAK dma2_stream4_isr(void);
+void WEAK eth_isr(void);
+void WEAK eth_wkup_isr(void);
+void WEAK can2_tx_isr(void);
+void WEAK can2_rx0_isr(void);
+void WEAK can2_rx1_isr(void);
+void WEAK can2_sce_isr(void);
+void WEAK otg_fs_isr(void);
+void WEAK dma2_stream5_isr(void);
+void WEAK dma2_stream6_isr(void);
+void WEAK dma2_stream7_isr(void);
+void WEAK usart6_isr(void);
+void WEAK i2c3_ev_isr(void);
+void WEAK i2c3_er_isr(void);
+void WEAK otg_hs_ep1_out_isr(void);
+void WEAK otg_hs_ep1_in_isr(void);
+void WEAK otg_hs_wkup_isr(void);
+void WEAK otg_hs_isr(void);
+void WEAK dcmi_isr(void);
+void WEAK cryp_isr(void);
+void WEAK hash_rng_isr(void);
+
+#pragma weak wwdg_isr = null_handler
+#pragma weak pvd_isr = null_handler
+#pragma weak tamp_stamp_isr = null_handler
+#pragma weak rtc_wkup_isr = null_handler
+#pragma weak flash_isr = null_handler
+#pragma weak rcc_isr = null_handler
+#pragma weak exti0_isr = null_handler
+#pragma weak exti1_isr = null_handler
+#pragma weak exti2_isr = null_handler
+#pragma weak exti3_isr = null_handler
+#pragma weak exti4_isr = null_handler
+#pragma weak dma1_stream0_isr = null_handler
+#pragma weak dma1_stream1_isr = null_handler
+#pragma weak dma1_stream2_isr = null_handler
+#pragma weak dma1_stream3_isr = null_handler
+#pragma weak dma1_stream4_isr = null_handler
+#pragma weak dma1_stream5_isr = null_handler
+#pragma weak dma1_stream6_isr = null_handler
+#pragma weak adc_isr = null_handler
+#pragma weak can1_tx_isr = null_handler
+#pragma weak can1_rx0_isr = null_handler
+#pragma weak can1_rx1_isr = null_handler
+#pragma weak can1_sce_isr = null_handler
+#pragma weak exti9_5_isr = null_handler
+#pragma weak tim1_brk_tim9_isr = null_handler
+#pragma weak tim1_up_tim10_isr = null_handler
+#pragma weak tim1_trg_com_tim11_isr = null_handler
+#pragma weak tim1_cc_isr = null_handler
+#pragma weak tim2_isr = null_handler
+#pragma weak tim3_isr = null_handler
+#pragma weak tim4_isr = null_handler
+#pragma weak i2c1_ev_isr = null_handler
+#pragma weak i2c1_er_isr = null_handler
+#pragma weak i2c2_ev_isr = null_handler
+#pragma weak i2c2_er_isr = null_handler
+#pragma weak spi1_isr = null_handler
+#pragma weak spi2_isr = null_handler
+#pragma weak usart1_isr = null_handler
+#pragma weak usart2_isr = null_handler
+#pragma weak usart3_isr = null_handler
+#pragma weak exti15_10_isr = null_handler
+#pragma weak rtc_alarm_isr = null_handler
+#pragma weak usb_fs_wkup_isr = null_handler
+#pragma weak tim8_brk_tim12_isr = null_handler
+#pragma weak tim8_up_tim13_isr = null_handler
+#pragma weak tim8_trg_com_tim14_isr = null_handler
+#pragma weak tim8_cc_isr = null_handler
+#pragma weak dma1_stream7_isr = null_handler
+#pragma weak fsmc_isr = null_handler
+#pragma weak sdio_isr = null_handler
+#pragma weak tim5_isr = null_handler
+#pragma weak spi3_isr = null_handler
+#pragma weak uart4_isr = null_handler
+#pragma weak uart5_isr = null_handler
+#pragma weak tim6_dac_isr = null_handler
+#pragma weak tim7_isr = null_handler
+#pragma weak dma2_stream0_isr = null_handler
+#pragma weak dma2_stream1_isr = null_handler
+#pragma weak dma2_stream2_isr = null_handler
+#pragma weak dma2_stream3_isr = null_handler
+#pragma weak dma2_stream4_isr = null_handler
+#pragma weak eth_isr = null_handler
+#pragma weak eth_wkup_isr = null_handler
+#pragma weak can2_tx_isr = null_handler
+#pragma weak can2_rx0_isr = null_handler
+#pragma weak can2_rx1_isr = null_handler
+#pragma weak can2_sce_isr = null_handler
+#pragma weak otg_fs_isr = null_handler
+#pragma weak dma2_stream5_isr = null_handler
+#pragma weak dma2_stream6_isr = null_handler
+#pragma weak dma2_stream7_isr = null_handler
+#pragma weak usart6_isr = null_handler
+#pragma weak i2c3_ev_isr = null_handler
+#pragma weak i2c3_er_isr = null_handler
+#pragma weak otg_hs_ep1_out_isr = null_handler
+#pragma weak otg_hs_ep1_in_isr = null_handler
+#pragma weak otg_hs_wkup_isr = null_handler
+#pragma weak otg_hs_isr = null_handler
+#pragma weak dcmi_isr = null_handler
+#pragma weak cryp_isr = null_handler
+#pragma weak hash_rng_isr = null_handler
+
+#define IRQ_HANDLERS \
+ wwdg_isr, \
+ pvd_isr, \
+ tamp_stamp_isr, \
+ rtc_wkup_isr, \
+ flash_isr, \
+ rcc_isr, \
+ exti0_isr, \
+ exti1_isr, \
+ exti2_isr, \
+ exti3_isr, \
+ exti4_isr, \
+ dma1_stream0_isr, \
+ dma1_stream1_isr, \
+ dma1_stream2_isr, \
+ dma1_stream3_isr, \
+ dma1_stream4_isr, \
+ dma1_stream5_isr, \
+ dma1_stream6_isr, \
+ adc_isr, \
+ can1_tx_isr, \
+ can1_rx0_isr, \
+ can1_rx1_isr, \
+ can1_sce_isr, \
+ exti9_5_isr, \
+ tim1_brk_tim9_isr, \
+ tim1_up_tim10_isr, \
+ tim1_trg_com_tim11_isr, \
+ tim1_cc_isr, \
+ tim2_isr, \
+ tim3_isr, \
+ tim4_isr, \
+ i2c1_ev_isr, \
+ i2c1_er_isr, \
+ i2c2_ev_isr, \
+ i2c2_er_isr, \
+ spi1_isr, \
+ spi2_isr, \
+ usart1_isr, \
+ usart2_isr, \
+ usart3_isr, \
+ exti15_10_isr, \
+ rtc_alarm_isr, \
+ usb_fs_wkup_isr, \
+ tim8_brk_tim12_isr, \
+ tim8_up_tim13_isr, \
+ tim8_trg_com_tim14_isr, \
+ tim8_cc_isr, \
+ dma1_stream7_isr, \
+ fsmc_isr, \
+ sdio_isr, \
+ tim5_isr, \
+ spi3_isr, \
+ uart4_isr, \
+ uart5_isr, \
+ tim6_dac_isr, \
+ tim7_isr, \
+ dma2_stream0_isr, \
+ dma2_stream1_isr, \
+ dma2_stream2_isr, \
+ dma2_stream3_isr, \
+ dma2_stream4_isr, \
+ eth_isr, \
+ eth_wkup_isr, \
+ can2_tx_isr, \
+ can2_rx0_isr, \
+ can2_rx1_isr, \
+ can2_sce_isr, \
+ otg_fs_isr, \
+ dma2_stream5_isr, \
+ dma2_stream6_isr, \
+ dma2_stream7_isr, \
+ usart6_isr, \
+ i2c3_ev_isr, \
+ i2c3_er_isr, \
+ otg_hs_ep1_out_isr, \
+ otg_hs_ep1_in_isr, \
+ otg_hs_wkup_isr, \
+ otg_hs_isr, \
+ dcmi_isr, \
+ cryp_isr, \
+ hash_rng_isr,
+
+#endif