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-rw-r--r--include/libopencm3/stm32/can.h2
-rw-r--r--include/libopencm3/stm32/f1/dma.h59
-rw-r--r--include/libopencm3/stm32/f4/adc.h873
-rw-r--r--include/libopencm3/stm32/f4/dma.h693
-rw-r--r--include/libopencm3/stm32/otg_fs.h105
-rw-r--r--include/libopencm3/stm32/otg_hs.h396
-rw-r--r--include/libopencm3/usb/cdc.h2
-rw-r--r--include/libopencm3/usb/usbd.h60
-rw-r--r--include/libopencm3/usb/usbstd.h3
9 files changed, 2104 insertions, 89 deletions
diff --git a/include/libopencm3/stm32/can.h b/include/libopencm3/stm32/can.h
index d6636d5..cdb5df1 100644
--- a/include/libopencm3/stm32/can.h
+++ b/include/libopencm3/stm32/can.h
@@ -458,7 +458,7 @@
/* --- CAN_TIxR values ------------------------------------------------------ */
/* STID[10:0]: Standard identifier */
-#define CAN_TIxR_STID_MASK (0x3FF << 21)
+#define CAN_TIxR_STID_MASK (0x7FF << 21)
#define CAN_TIxR_STID_SHIFT 21
/* EXID[15:0]: Extended identifier */
diff --git a/include/libopencm3/stm32/f1/dma.h b/include/libopencm3/stm32/f1/dma.h
index b08803f..6e5cc20 100644
--- a/include/libopencm3/stm32/f1/dma.h
+++ b/include/libopencm3/stm32/f1/dma.h
@@ -141,9 +141,30 @@ LGPL License Terms @ref lgpl_license
/* --- DMA_ISR values ------------------------------------------------------ */
+/* --- DMA Interrupt Flag offset values ------------------------------------- */
+/* These are based on every interrupt flag and flag clear being at the same relative location */
+/** @defgroup dma_if_offset DMA Interrupt Flag Offsets within stream flag group.
+@ingroup STM32F1xx_dma_defines
+
+@{*/
+/** Transfer Error Interrupt Flag */
+#define DMA_TEIF (1 << 3)
+/** Half Transfer Interrupt Flag */
+#define DMA_HTIF (1 << 2)
+/** Transfer Complete Interrupt Flag */
+#define DMA_TCIF (1 << 1)
+/** Global Interrupt Flag */
+#define DMA_GIF (1 << 0)
+/**@}*/
+
+/* Offset within interrupt status register to start of stream interrupt flag field */
+#define DMA_FLAG_OFFSET(channel) (4*(channel - 1))
+#define DMA_FLAGS (DMA_TEIF | DMA_TCIF | DMA_HTIF | DMA_GIF)
+#define DMA_ISR_MASK(channel) DMA_FLAGS << DMA_FLAG_OFFSET(channel)
+
/* TEIF: Transfer error interrupt flag */
-#define DMA_ISR_TEIF_BIT (1 << 3)
-#define DMA_ISR_TEIF(channel) (DMA_ISR_TEIF_BIT << (4 * ((channel) -1)))
+#define DMA_ISR_TEIF_BIT DMA_ISR_TEIF
+#define DMA_ISR_TEIF(channel) (DMA_ISR_TEIF_BIT << DMA_FLAG_OFFSET(channel)))
#define DMA_ISR_TEIF1 DMA_ISR_TEIF(DMA_CHANNEL1)
#define DMA_ISR_TEIF2 DMA_ISR_TEIF(DMA_CHANNEL2)
@@ -154,8 +175,8 @@ LGPL License Terms @ref lgpl_license
#define DMA_ISR_TEIF7 DMA_ISR_TEIF(DMA_CHANNEL7)
/* HTIF: Half transfer interrupt flag */
-#define DMA_ISR_HTIF_BIT (1 << 2)
-#define DMA_ISR_HTIF(channel) (DMA_ISR_HTIF_BIT << (4 * ((channel) -1)))
+#define DMA_ISR_HTIF_BIT DMA_HTIF
+#define DMA_ISR_HTIF(channel) (DMA_ISR_HTIF_BIT << DMA_FLAG_OFFSET(channel)))
#define DMA_ISR_HTIF1 DMA_ISR_HTIF(DMA_CHANNEL1)
#define DMA_ISR_HTIF2 DMA_ISR_HTIF(DMA_CHANNEL2)
@@ -166,8 +187,8 @@ LGPL License Terms @ref lgpl_license
#define DMA_ISR_HTIF7 DMA_ISR_HTIF(DMA_CHANNEL7)
/* TCIF: Transfer complete interrupt flag */
-#define DMA_ISR_TCIF_BIT (1 << 1)
-#define DMA_ISR_TCIF(channel) (DMA_ISR_TCIF_BIT << (4 * ((channel) -1)))
+#define DMA_ISR_TCIF_BIT DMA_TCIF
+#define DMA_ISR_TCIF(channel) (DMA_ISR_TCIF_BIT << (DMA_FLAG_OFFSET(channel)))
#define DMA_ISR_TCIF1 DMA_ISR_TCIF(DMA_CHANNEL1)
#define DMA_ISR_TCIF2 DMA_ISR_TCIF(DMA_CHANNEL2)
@@ -178,8 +199,8 @@ LGPL License Terms @ref lgpl_license
#define DMA_ISR_TCIF7 DMA_ISR_TCIF(DMA_CHANNEL7)
/* GIF: Global interrupt flag */
-#define DMA_ISR_GIF_BIT (1 << 0)
-#define DMA_ISR_GIF(channel) (DMA_ISR_GIF_BIT << (4 * ((channel) -1)))
+#define DMA_ISR_GIF_BIT DMA_GIF
+#define DMA_ISR_GIF(channel) (DMA_ISR_GIF_BIT << (DMA_FLAG_OFFSET(channel)))
#define DMA_ISR_GIF1 DMA_ISR_GIF(DMA_CHANNEL1)
#define DMA_ISR_GIF2 DMA_ISR_GIF(DMA_CHANNEL2)
@@ -192,8 +213,8 @@ LGPL License Terms @ref lgpl_license
/* --- DMA_IFCR values ----------------------------------------------------- */
/* CTEIF: Transfer error clear */
-#define DMA_IFCR_CTEIF_BIT (1 << 3)
-#define DMA_IFCR_CTEIF(channel) (DMA_IFCR_CTEIF_BIT << (4 * ((channel) -1)))
+#define DMA_IFCR_CTEIF_BIT DMA_TEIF
+#define DMA_IFCR_CTEIF(channel) (DMA_IFCR_CTEIF_BIT << (DMA_FLAG_OFFSET(channel)))
#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF(DMA_CHANNEL1)
#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF(DMA_CHANNEL2)
@@ -204,8 +225,8 @@ LGPL License Terms @ref lgpl_license
#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF(DMA_CHANNEL7)
/* CHTIF: Half transfer clear */
-#define DMA_IFCR_CHTIF_BIT (1 << 2)
-#define DMA_IFCR_CHTIF(channel) (DMA_IFCR_CHTIF_BIT << (4 * ((channel) -1)))
+#define DMA_IFCR_CHTIF_BIT DMA_HTIF
+#define DMA_IFCR_CHTIF(channel) (DMA_IFCR_CHTIF_BIT << (DMA_FLAG_OFFSET(channel)))
#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF(DMA_CHANNEL1)
#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF(DMA_CHANNEL2)
@@ -216,8 +237,8 @@ LGPL License Terms @ref lgpl_license
#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF(DMA_CHANNEL7)
/* CTCIF: Transfer complete clear */
-#define DMA_IFCR_CTCIF_BIT (1 << 1)
-#define DMA_IFCR_CTCIF(channel) (DMA_IFCR_CTCIF_BIT << (4 * ((channel) -1)))
+#define DMA_IFCR_CTCIF_BIT DMA_TCIF
+#define DMA_IFCR_CTCIF(channel) (DMA_IFCR_CTCIF_BIT << (DMA_FLAG_OFFSET(channel)))
#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF(DMA_CHANNEL1)
#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF(DMA_CHANNEL2)
@@ -228,8 +249,8 @@ LGPL License Terms @ref lgpl_license
#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF(DMA_CHANNEL7)
/* CGIF: Global interrupt clear */
-#define DMA_IFCR_CGIF_BIT (1 << 0)
-#define DMA_IFCR_CGIF(channel) (DMA_IFCR_CGIF_BIT << (4 * ((channel) -1)))
+#define DMA_IFCR_CGIF_BIT DMA_GIF
+#define DMA_IFCR_CGIF(channel) (DMA_IFCR_CGIF_BIT << (DMA_FLAG_OFFSET(channel)))
#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF(DMA_CHANNEL1)
#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF(DMA_CHANNEL2)
@@ -241,7 +262,7 @@ LGPL License Terms @ref lgpl_license
/* Clear interrupts mask */
#define DMA_IFCR_CIF_BIT 0xF
-#define DMA_IFCR_CIF(channel) (DMA_IFCR_CIF_BIT << (4 * ((channel) - 1)))
+#define DMA_IFCR_CIF(channel) (DMA_IFCR_CIF_BIT << (DMA_FLAG_OFFSET(channel)))
#define DMA_IFCR_CIF1 DMA_IFCR_CIF(DMA_CHANNEL1)
#define DMA_IFCR_CIF2 DMA_IFCR_CIF(DMA_CHANNEL2)
@@ -349,12 +370,16 @@ LGPL License Terms @ref lgpl_license
BEGIN_DECLS
void dma_channel_reset(u32 dma, u8 channel);
+void dma_clear_interrupt_flags(u32 dma, u8 channel, u32 interrupts);
+bool dma_get_interrupt_flag(u32 dma, u8 channel, u32 interrupts);
void dma_enable_mem2mem_mode(u32 dma, u8 channel);
void dma_set_priority(u32 dma, u8 channel, u32 prio);
void dma_set_memory_size(u32 dma, u8 channel, u32 mem_size);
void dma_set_peripheral_size(u32 dma, u8 channel, u32 peripheral_size);
void dma_enable_memory_increment_mode(u32 dma, u8 channel);
+void dma_disable_memory_increment_mode(u32 dma, u8 channel);
void dma_enable_peripheral_increment_mode(u32 dma, u8 channel);
+void dma_disable_peripheral_increment_mode(u32 dma, u8 channel);
void dma_enable_circular_mode(u32 dma, u8 channel);
void dma_set_read_from_peripheral(u32 dma, u8 channel);
void dma_set_read_from_memory(u32 dma, u8 channel);
diff --git a/include/libopencm3/stm32/f4/adc.h b/include/libopencm3/stm32/f4/adc.h
new file mode 100644
index 0000000..272c4c2
--- /dev/null
+++ b/include/libopencm3/stm32/f4/adc.h
@@ -0,0 +1,873 @@
+/** @defgroup STM32F4xx_adc_defines ADC Defines
+
+@brief <b>Defined Constants and Types for the STM32F4xx Analog to Digital Converters</b>
+
+@ingroup STM32F4xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2012 Matthew Lai <m@matthewlai.ca>
+@author @htmlonly &copy; @endhtmlonly 2009 Edward Cheeseman <evbuilder@users.sourceforge.net>
+
+@date 31 August 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Matthew Lai <m@matthewlai.ca>
+ * Copyright (C) 2009 Edward Cheeseman <evbuilder@users.sourceforge.net>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_ADC_H
+#define LIBOPENCM3_ADC_H
+
+#include <libopencm3/stm32/f4/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/* --- Convenience macros -------------------------------------------------- */
+
+/* ADC port base addresses (for convenience) */
+/****************************************************************************/
+/** @defgroup adc_reg_base ADC register base addresses
+@ingroup STM32F4xx_adc_defines
+
+@{*/
+#define ADC1 ADC1_BASE
+#define ADC2 ADC2_BASE
+#define ADC3 ADC3_BASE
+/**@}*/
+
+/* --- ADC registers ------------------------------------------------------- */
+
+/* ADC status register (ADC_SR) */
+#define ADC_SR(block) MMIO32(block + 0x00)
+#define ADC1_SR ADC_SR(ADC1)
+#define ADC2_SR ADC_SR(ADC2)
+#define ADC3_SR ADC_SR(ADC3)
+
+/* ADC control register 1 (ADC_CR1) */
+#define ADC_CR1(block) MMIO32(block + 0x04)
+#define ADC1_CR1 ADC_CR1(ADC1)
+#define ADC2_CR1 ADC_CR1(ADC2)
+#define ADC3_CR1 ADC_CR1(ADC3)
+
+/* ADC control register 2 (ADC_CR2) */
+#define ADC_CR2(block) MMIO32(block + 0x08)
+#define ADC1_CR2 ADC_CR2(ADC1)
+#define ADC2_CR2 ADC_CR2(ADC2)
+#define ADC3_CR2 ADC_CR2(ADC3)
+
+/* ADC sample time register 1 (ADC_SMPR1) */
+#define ADC_SMPR1(block) MMIO32(block + 0x0c)
+#define ADC1_SMPR1 ADC_SMPR1(ADC1)
+#define ADC2_SMPR1 ADC_SMPR1(ADC2)
+#define ADC3_SMPR1 ADC_SMPR1(ADC3)
+
+/* ADC sample time register 2 (ADC_SMPR2) */
+#define ADC_SMPR2(block) MMIO32(block + 0x10)
+#define ADC1_SMPR2 ADC_SMPR2(ADC1)
+#define ADC2_SMPR2 ADC_SMPR2(ADC2)
+#define ADC3_SMPR2 ADC_SMPR2(ADC3)
+
+/* ADC injected channel data offset register x (ADC_JOFRx) (x=1..4) */
+#define ADC_JOFR1(block) MMIO32(block + 0x14)
+#define ADC_JOFR2(block) MMIO32(block + 0x18)
+#define ADC_JOFR3(block) MMIO32(block + 0x1c)
+#define ADC_JOFR4(block) MMIO32(block + 0x20)
+#define ADC1_JOFR1 ADC_JOFR1(ADC1)
+#define ADC2_JOFR1 ADC_JOFR1(ADC2)
+#define ADC3_JOFR1 ADC_JOFR1(ADC3)
+#define ADC1_JOFR2 ADC_JOFR2(ADC1)
+#define ADC2_JOFR2 ADC_JOFR2(ADC2)
+#define ADC3_JOFR2 ADC_JOFR2(ADC3)
+#define ADC1_JOFR3 ADC_JOFR3(ADC1)
+#define ADC2_JOFR3 ADC_JOFR3(ADC2)
+#define ADC3_JOFR3 ADC_JOFR3(ADC3)
+#define ADC1_JOFR4 ADC_JOFR4(ADC1)
+#define ADC2_JOFR4 ADC_JOFR4(ADC2)
+#define ADC3_JOFR4 ADC_JOFR4(ADC3)
+
+/* ADC watchdog high threshold register (ADC_HTR) */
+#define ADC_HTR(block) MMIO32(block + 0x24)
+#define ADC1_HTR ADC_HTR(ADC1)
+#define ADC2_HTR ADC_HTR(ADC2)
+#define ADC3_HTR ADC_HTR(ADC3)
+
+/* ADC watchdog low threshold register (ADC_LTR) */
+#define ADC_LTR(block) MMIO32(block + 0x28)
+#define ADC1_LTR ADC_LTR(ADC1_BASE)
+#define ADC2_LTR ADC_LTR(ADC2_BASE)
+#define ADC3_LTR ADC_LTR(ADC3_BASE)
+
+/* ADC regular sequence register 1 (ADC_SQR1) */
+#define ADC_SQR1(block) MMIO32(block + 0x2c)
+#define ADC1_SQR1 ADC_SQR1(ADC1)
+#define ADC2_SQR1 ADC_SQR1(ADC2)
+#define ADC3_SQR1 ADC_SQR1(ADC3)
+
+/* ADC regular sequence register 2 (ADC_SQR2) */
+#define ADC_SQR2(block) MMIO32(block + 0x30)
+#define ADC1_SQR2 ADC_SQR2(ADC1)
+#define ADC2_SQR2 ADC_SQR2(ADC2)
+#define ADC3_SQR2 ADC_SQR2(ADC3)
+
+/* ADC regular sequence register 3 (ADC_SQR3) */
+#define ADC_SQR3(block) MMIO32(block + 0x34)
+#define ADC1_SQR3 ADC_SQR3(ADC1)
+#define ADC2_SQR3 ADC_SQR3(ADC2)
+#define ADC3_SQR3 ADC_SQR3(ADC3)
+
+/* ADC injected sequence register (ADC_JSQR) */
+#define ADC_JSQR(block) MMIO32(block + 0x38)
+#define ADC1_JSQR ADC_JSQR(ADC1_BASE)
+#define ADC2_JSQR ADC_JSQR(ADC2_BASE)
+#define ADC3_JSQR ADC_JSQR(ADC3_BASE)
+
+/* ADC injected data register x (ADC_JDRx) (x=1..4) */
+#define ADC_JDR1(block) MMIO32(block + 0x3c)
+#define ADC_JDR2(block) MMIO32(block + 0x40)
+#define ADC_JDR3(block) MMIO32(block + 0x44)
+#define ADC_JDR4(block) MMIO32(block + 0x48)
+#define ADC1_JDR1 ADC_JDR1(ADC1)
+#define ADC2_JDR1 ADC_JDR1(ADC2)
+#define ADC3_JDR1 ADC_JDR1(ADC3)
+#define ADC1_JDR2 ADC_JDR2(ADC1)
+#define ADC2_JDR2 ADC_JDR2(ADC2)
+#define ADC3_JDR2 ADC_JDR2(ADC3)
+#define ADC1_JDR3 ADC_JDR3(ADC1)
+#define ADC2_JDR3 ADC_JDR3(ADC2)
+#define ADC3_JDR3 ADC_JDR3(ADC3)
+#define ADC1_JDR4 ADC_JDR4(ADC1)
+#define ADC2_JDR4 ADC_JDR4(ADC2)
+#define ADC3_JDR4 ADC_JDR4(ADC3)
+
+/* ADC regular data register (ADC_DR) */
+#define ADC_DR(block) MMIO32(block + 0x4c)
+#define ADC1_DR ADC_DR(ADC1)
+#define ADC2_DR ADC_DR(ADC2)
+#define ADC3_DR ADC_DR(ADC3)
+
+/* ADC common (shared) registers */
+#define ADC_COMMON_REGISTERS_BASE (ADC1_BASE+0x300)
+#define ADC_CSR MMIO32(ADC_COMMON_REGISTERS_BASE + 0x0)
+#define ADC_CCR MMIO32(ADC_COMMON_REGISTERS_BASE + 0x4)
+#define ADC_CDR MMIO32(ADC_COMMON_REGISTERS_BASE + 0x8)
+
+/* --- ADC Channels ------------------------------------------------------- */
+
+/****************************************************************************/
+/** @defgroup adc_channel ADC Channel Numbers
+@ingroup STM32F4xx_adc_defines
+
+@{*/
+#define ADC_CHANNEL0 0x00
+#define ADC_CHANNEL1 0x01
+#define ADC_CHANNEL2 0x02
+#define ADC_CHANNEL3 0x03
+#define ADC_CHANNEL4 0x04
+#define ADC_CHANNEL5 0x05
+#define ADC_CHANNEL6 0x06
+#define ADC_CHANNEL7 0x07
+#define ADC_CHANNEL8 0x08
+#define ADC_CHANNEL9 0x09
+#define ADC_CHANNEL10 0x0A
+#define ADC_CHANNEL11 0x0B
+#define ADC_CHANNEL12 0x0C
+#define ADC_CHANNEL13 0x0D
+#define ADC_CHANNEL14 0x0E
+#define ADC_CHANNEL15 0x0F
+#define ADC_CHANNEL16 0x10
+#define ADC_CHANNEL17 0x11
+#define ADC_CHANNEL18 0x12
+/**@}*/
+#define ADC_MASK 0x1F
+#define ADC_SHIFT 0
+
+/* --- ADC_SR values ------------------------------------------------------- */
+
+#define ADC_SR_OVR (1 << 5)
+#define ADC_SR_STRT (1 << 4)
+#define ADC_SR_JSTRT (1 << 3)
+#define ADC_SR_JEOC (1 << 2)
+#define ADC_SR_EOC (1 << 1)
+#define ADC_SR_AWD (1 << 0)
+
+/* --- ADC_CR1 values specific to STM32F2,4------------------------------------ */
+
+/* OVRIE: Overrun interrupt enable */
+#define ADC_CR1_OVRIE (1 << 26)
+
+/* RES[1:0]: Resolution */
+/****************************************************************************/
+/** @defgroup adc_cr1_res ADC Resolution.
+@ingroup STM32F4xx_adc_defines
+
+@{*/
+#define ADC_CR1_RES_12BIT (0x0 << 24)
+#define ADC_CR1_RES_10BIT (0x1 << 24)
+#define ADC_CR1_RES_8BIT (0x2 << 24)
+#define ADC_CR1_RES_6BIT (0x3 << 24)
+/**@}*/
+#define ADC_CR1_RES_MASK (0x3 << 24)
+#define ADC_CR1_RES_SHIFT 24
+
+/* Note: Bits [21:16] are reserved, and must be kept at reset value. */
+
+/* --- ADC_CR1 values (note some of these are defined elsewhere) ----------- */
+
+/* AWDEN: Analog watchdog enable on regular channels */
+#define ADC_CR1_AWDEN (1 << 23)
+
+/* JAWDEN: Analog watchdog enable on injected channels */
+#define ADC_CR1_JAWDEN (1 << 22)
+
+/* DISCNUM[2:0]: Discontinuous mode channel count. */
+/****************************************************************************/
+/** @defgroup adc_cr1_discnum ADC Number of channels in discontinuous mode.
+@ingroup STM32F4xx_adc_defines
+
+@{*/
+#define ADC_CR1_DISCNUM_1CHANNELS (0x0 << 13)
+#define ADC_CR1_DISCNUM_2CHANNELS (0x1 << 13)
+#define ADC_CR1_DISCNUM_3CHANNELS (0x2 << 13)
+#define ADC_CR1_DISCNUM_4CHANNELS (0x3 << 13)
+#define ADC_CR1_DISCNUM_5CHANNELS (0x4 << 13)
+#define ADC_CR1_DISCNUM_6CHANNELS (0x5 << 13)
+#define ADC_CR1_DISCNUM_7CHANNELS (0x6 << 13)
+#define ADC_CR1_DISCNUM_8CHANNELS (0x7 << 13)
+/**@}*/
+#define ADC_CR1_DISCNUM_MASK (0x7 << 13)
+#define ADC_CR1_DISCNUM_SHIFT 13
+
+/* JDISCEN: */ /** Discontinuous mode on injected channels. */
+#define ADC_CR1_JDISCEN (1 << 12)
+
+/* DISCEN: */ /** Discontinuous mode on regular channels. */
+#define ADC_CR1_DISCEN (1 << 11)
+
+/* JAUTO: */ /** Automatic Injection Group conversion. */
+#define ADC_CR1_JAUTO (1 << 10)
+
+/* AWDSGL: */ /** Enable the watchdog on a single channel in scan mode. */
+#define ADC_CR1_AWDSGL (1 << 9)
+
+/* SCAN: */ /** Scan mode. */
+#define ADC_CR1_SCAN (1 << 8)
+
+/* JEOCIE: */ /** Interrupt enable for injected channels. */
+#define ADC_CR1_JEOCIE (1 << 7)
+
+/* AWDIE: */ /** Analog watchdog interrupt enable. */
+#define ADC_CR1_AWDIE (1 << 6)
+
+/* EOCIE: */ /** Interrupt enable EOC. */
+#define ADC_CR1_EOCIE (1 << 5)
+
+/* AWDCH[4:0]: Analog watchdog channel bits. (Up to 17 other values reserved) */
+/* Notes:
+ * ADC1: Analog channel 16 and 17 are internally connected to the temperature
+ * sensor and V_REFINT, respectively.
+ * ADC2: Analog channel 16 and 17 are internally connected to V_SS.
+ * ADC3: Analog channel 9, 14, 15, 16 and 17 are internally connected to V_SS.
+ */
+/****************************************************************************/
+/* ADC_CR1 AWDCH[4:0] ADC watchdog channel */
+/** @defgroup adc_watchdog_channel ADC watchdog channel
+@ingroup STM32F4xx_adc_defines
+
+@{*/
+#define ADC_CR1_AWDCH_CHANNEL0 (0x00 << 0)
+#define ADC_CR1_AWDCH_CHANNEL1 (0x01 << 0)
+#define ADC_CR1_AWDCH_CHANNEL2 (0x02 << 0)
+#define ADC_CR1_AWDCH_CHANNEL3 (0x03 << 0)
+#define ADC_CR1_AWDCH_CHANNEL4 (0x04 << 0)
+#define ADC_CR1_AWDCH_CHANNEL5 (0x05 << 0)
+#define ADC_CR1_AWDCH_CHANNEL6 (0x06 << 0)
+#define ADC_CR1_AWDCH_CHANNEL7 (0x07 << 0)
+#define ADC_CR1_AWDCH_CHANNEL8 (0x08 << 0)
+#define ADC_CR1_AWDCH_CHANNEL9 (0x09 << 0)
+#define ADC_CR1_AWDCH_CHANNEL10 (0x0A << 0)
+#define ADC_CR1_AWDCH_CHANNEL11 (0x0B << 0)
+#define ADC_CR1_AWDCH_CHANNEL12 (0x0C << 0)
+#define ADC_CR1_AWDCH_CHANNEL13 (0x0D << 0)
+#define ADC_CR1_AWDCH_CHANNEL14 (0x0E << 0)
+#define ADC_CR1_AWDCH_CHANNEL15 (0x0F << 0)
+#define ADC_CR1_AWDCH_CHANNEL16 (0x10 << 0)
+#define ADC_CR1_AWDCH_CHANNEL17 (0x11 << 0)
+/**@}*/
+#define ADC_CR1_AWDCH_MASK (0x1F << 0)
+#define ADC_CR1_AWDCH_SHIFT 0
+
+/* --- ADC_CR2 values ------------------------------------------------------ */
+
+/* SWSTART: Start conversion of regular channels. */
+#define ADC_CR2_SWSTART (1 << 30)
+
+/* EXTEN[1:0]: External trigger enable for regular channels. */
+/****************************************************************************/
+/** @defgroup adc_trigger_polarity_regular ADC Trigger Polarity
+@ingroup STM32F4xx_adc_defines
+
+@{*/
+#define ADC_CR2_EXTEN_DISABLED (0x0 << 28)
+#define ADC_CR2_EXTEN_RISING_EDGE (0x1 << 28)
+#define ADC_CR2_EXTEN_FALLING_EDGE (0x2 << 28)
+#define ADC_CR2_EXTEN_BOTH_EDGES (0x3 << 28)
+/**@}*/
+#define ADC_CR2_EXTEN_MASK (0x3 << 28)
+#define ADC_CR2_EXTEN_SHIFT 28
+
+/* EXTSEL[3:0]: External event selection for regular group. */
+/****************************************************************************/
+/** @defgroup adc_trigger_regular ADC Trigger Identifier for Regular group
+@ingroup STM32F4xx_adc_defines
+
+@{*/
+/** Timer 1 Compare Output 1 */
+#define ADC_CR2_EXTSEL_TIM1_CC1 (0x0 << 24)
+/** Timer 1 Compare Output 2 */
+#define ADC_CR2_EXTSEL_TIM1_CC2 (0x1 << 24)
+/** Timer 1 Compare Output 3 */
+#define ADC_CR2_EXTSEL_TIM1_CC3 (0x2 << 24)
+/** Timer 2 Compare Output 2 */
+#define ADC_CR2_EXTSEL_TIM2_CC2 (0x3 << 24)
+/** Timer 2 Compare Output 3 */
+#define ADC_CR2_EXTSEL_TIM2_CC3 (0x4 << 24)
+/** Timer 2 Compare Output 4 */
+#define ADC_CR2_EXTSEL_TIM2_CC4 (0x5 << 24)
+/** Timer 2 TRGO Event */
+#define ADC_CR2_EXTSEL_TIM2_TRGO (0x6 << 24)
+/** Timer 3 Compare Output 1 */
+#define ADC_CR2_EXTSEL_TIM3_CC1 (0x7 << 24)
+/** Timer 3 TRGO Event */
+#define ADC_CR2_EXTSEL_TIM3_TRGO (0x8 << 24)
+/** Timer 4 Compare Output 4 */
+#define ADC_CR2_EXTSEL_TIM4_CC4 (0x9 << 24)
+/** Timer 5 Compare Output 1 */
+#define ADC_CR2_EXTSEL_TIM5_CC1 (0xA << 24)
+/** Timer 5 Compare Output 2 */
+#define ADC_CR2_EXTSEL_TIM5_CC2 (0xB << 24)
+/** Timer 5 Compare Output 3 */
+#define ADC_CR2_EXTSEL_TIM5_CC3 (0xC << 24)
+/** Timer 8 Compare Output 1 */
+#define ADC_CR2_EXTSEL_TIM8_CC1 (0xD << 24)
+/** Timer 8 TRGO Event */
+#define ADC_CR2_EXTSEL_TIM8_TRGO (0xE << 24)
+/** EXTI Line 11 Event */
+#define ADC_CR2_EXTSEL_EXTI_LINE_11 (0xF << 24)
+/**@}*/
+#define ADC_CR2_EXTSEL_MASK (0xF << 24)
+#define ADC_CR2_EXTSEL_SHIFT 24
+
+/* Bit 23 is reserved */
+
+/* JSWSTART: Start conversion of injected channels. */
+#define ADC_CR2_JSWSTART (1 << 22)
+
+/* JEXTEN[1:0]: External trigger enable for injected channels. */
+/****************************************************************************/
+/** @defgroup adc_trigger_polarity_injected ADC Injected Trigger Polarity
+@ingroup STM32F4xx_adc_defines
+
+@{*/
+#define ADC_CR2_JEXTEN_DISABLED (0x0 << 20)
+#define ADC_CR2_JEXTEN_RISING_EDGE (0x1 << 20)
+#define ADC_CR2_JEXTEN_FALLING_EDGE (0x2 << 20)
+#define ADC_CR2_JEXTEN_BOTH_EDGES (0x3 << 20)
+/**@}*/
+#define ADC_CR2_JEXTEN_MASK (0x3 << 20)
+#define ADC_CR2_JEXTEN_SHIFT 20
+
+/* JEXTSEL[3:0]: External event selection for injected group. */
+/****************************************************************************/
+/** @defgroup adc_trigger_injected ADC Trigger Identifier for Injected group
+@ingroup STM32F4xx_adc_defines
+
+@{*/
+#define ADC_CR2_JEXTSEL_TIM1_CC4 (0x0 << 16)
+#define ADC_CR2_JEXTSEL_TIM1_TRGO (0x1 << 16)
+#define ADC_CR2_JEXTSEL_TIM2_CC1 (0x2 << 16)
+#define ADC_CR2_JEXTSEL_TIM2_TRGO (0x3 << 16)
+#define ADC_CR2_JEXTSEL_TIM3_CC2 (0x4 << 16)
+#define ADC_CR2_JEXTSEL_TIM3_CC4 (0x5 << 16)
+#define ADC_CR2_JEXTSEL_TIM4_CC1 (0x6 << 16)
+#define ADC_CR2_JEXTSEL_TIM4_CC2 (0x7 << 16)
+#define ADC_CR2_JEXTSEL_TIM4_CC3 (0x8 << 16)
+#define ADC_CR2_JEXTSEL_TIM4_TRGO (0x9 << 16)
+#define ADC_CR2_JEXTSEL_TIM5_CC4 (0xA << 16)
+#define ADC_CR2_JEXTSEL_TIM5_TRGO (0xB << 16)
+#define ADC_CR2_JEXTSEL_TIM8_CC2 (0xC << 16)
+#define ADC_CR2_JEXTSEL_TIM8_CC3 (0xD << 16)
+#define ADC_CR2_JEXTSEL_TIM8_CC4 (0xE << 16)
+#define ADC_CR2_JEXTSEL_EXTI_LINE_15 (0xF << 16)
+/**@}*/
+#define ADC_CR2_JEXTSEL_MASK (0xF << 16)
+#define ADC_CR2_JEXTSEL_SHIFT 16
+
+/* ALIGN: Data alignement. */
+#define ADC_CR2_ALIGN_RIGHT (0 << 11)
+#define ADC_CR2_ALIGN_LEFT (1 << 11)
+#define ADC_CR2_ALIGN (1 << 11)
+
+/* EOCS: End of conversion selection. */
+#define ADC_CR2_EOCS (1 << 10)
+
+/* DDS: DMA disable selection */
+#define ADC_CR2_DDS (1 << 9)
+
+/* DMA: Direct memory access mode. (ADC1 and ADC3 only!) */
+#define ADC_CR2_DMA (1 << 8)
+
+/* Note: Bits [7:2] are reserved and must be kept at reset value. */
+
+/* CONT: Continous conversion. */
+#define ADC_CR2_CONT (1 << 1)
+
+/* ADON: A/D converter On/Off. */
+/* Note: If any other bit in this register apart from ADON is changed at the
+ * same time, then conversion is not triggered. This is to prevent triggering
+ * an erroneous conversion.
+ * Conclusion: Must be separately written.
+ */
+#define ADC_CR2_ADON (1 << 0)
+
+/* --- ADC_SMPR1 values ---------------------------------------------------- */
+
+#define ADC_SMPR1_SMP17_LSB 21
+#define ADC_SMPR1_SMP16_LSB 18
+#define ADC_SMPR1_SMP15_LSB 15
+#define ADC_SMPR1_SMP14_LSB 12
+#define ADC_SMPR1_SMP13_LSB 9
+#define ADC_SMPR1_SMP12_LSB 6
+#define ADC_SMPR1_SMP11_LSB 3
+#define ADC_SMPR1_SMP10_LSB 0
+#define ADC_SMPR1_SMP17_MSK (0x7 << ADC_SMP17_LSB)
+#define ADC_SMPR1_SMP16_MSK (0x7 << ADC_SMP16_LSB)
+#define ADC_SMPR1_SMP15_MSK (0x7 << ADC_SMP15_LSB)
+#define ADC_SMPR1_SMP14_MSK (0x7 << ADC_SMP14_LSB)
+#define ADC_SMPR1_SMP13_MSK (0x7 << ADC_SMP13_LSB)
+#define ADC_SMPR1_SMP12_MSK (0x7 << ADC_SMP12_LSB)
+#define ADC_SMPR1_SMP11_MSK (0x7 << ADC_SMP11_LSB)
+#define ADC_SMPR1_SMP10_MSK (0x7 << ADC_SMP10_LSB)
+/****************************************************************************/
+/* ADC_SMPR1 ADC Sample Time Selection for Channels */
+/** @defgroup adc_sample_r1 ADC Sample Time Selection for ADC1
+@ingroup STM32F4xx_adc_defines
+
+@{*/
+#define ADC_SMPR1_SMP_1DOT5CYC 0x0
+#define ADC_SMPR1_SMP_7DOT5CYC 0x1
+#define ADC_SMPR1_SMP_13DOT5CYC 0x2
+#define ADC_SMPR1_SMP_28DOT5CYC 0x3
+#define ADC_SMPR1_SMP_41DOT5CYC 0x4
+#define ADC_SMPR1_SMP_55DOT5CYC 0x5
+#define ADC_SMPR1_SMP_71DOT5CYC 0x6
+#define ADC_SMPR1_SMP_239DOT5CYC 0x7
+/**@}*/
+
+/* --- ADC_SMPR2 values ---------------------------------------------------- */
+
+#define ADC_SMPR2_SMP9_LSB 27
+#define ADC_SMPR2_SMP8_LSB 24
+#define ADC_SMPR2_SMP7_LSB 21
+#define ADC_SMPR2_SMP6_LSB 18
+#define ADC_SMPR2_SMP5_LSB 15
+#define ADC_SMPR2_SMP4_LSB 12
+#define ADC_SMPR2_SMP3_LSB 9
+#define ADC_SMPR2_SMP2_LSB 6
+#define ADC_SMPR2_SMP1_LSB 3
+#define ADC_SMPR2_SMP0_LSB 0
+#define ADC_SMPR2_SMP9_MSK (0x7 << ADC_SMP9_LSB)
+#define ADC_SMPR2_SMP8_MSK (0x7 << ADC_SMP8_LSB)
+#define ADC_SMPR2_SMP7_MSK (0x7 << ADC_SMP7_LSB)
+#define ADC_SMPR2_SMP6_MSK (0x7 << ADC_SMP6_LSB)
+#define ADC_SMPR2_SMP5_MSK (0x7 << ADC_SMP5_LSB)
+#define ADC_SMPR2_SMP4_MSK (0x7 << ADC_SMP4_LSB)
+#define ADC_SMPR2_SMP3_MSK (0x7 << ADC_SMP3_LSB)
+#define ADC_SMPR2_SMP2_MSK (0x7 << ADC_SMP2_LSB)
+#define ADC_SMPR2_SMP1_MSK (0x7 << ADC_SMP1_LSB)
+#define ADC_SMPR2_SMP0_MSK (0x7 << ADC_SMP0_LSB)
+/****************************************************************************/
+/* ADC_SMPR2 ADC Sample Time Selection for Channels */
+/** @defgroup adc_sample_r2 ADC Sample Time Selection for ADC2
+@ingroup STM32F4xx_adc_defines
+
+@{*/
+#define ADC_SMPR2_SMP_1DOT5CYC 0x0
+#define ADC_SMPR2_SMP_7DOT5CYC 0x1
+#define ADC_SMPR2_SMP_13DOT5CYC 0x2
+#define ADC_SMPR2_SMP_28DOT5CYC 0x3
+#define ADC_SMPR2_SMP_41DOT5CYC 0x4
+#define ADC_SMPR2_SMP_55DOT5CYC 0x5
+#define ADC_SMPR2_SMP_71DOT5CYC 0x6
+#define ADC_SMPR2_SMP_239DOT5CYC 0x7
+/**@}*/
+
+/* --- ADC_SMPRx generic values -------------------------------------------- */
+/****************************************************************************/
+/* ADC_SMPRG ADC Sample Time Selection for Channels */
+/** @defgroup adc_sample_rg ADC Sample Time Selection for All Channels
+@ingroup STM32F4xx_adc_defines
+
+@{*/
+#define ADC_SMPR_SMP_1DOT5CYC 0x0
+#define ADC_SMPR_SMP_7DOT5CYC 0x1
+#define ADC_SMPR_SMP_13DOT5CYC 0x2
+#define ADC_SMPR_SMP_28DOT5CYC 0x3
+#define ADC_SMPR_SMP_41DOT5CYC 0x4
+#define ADC_SMPR_SMP_55DOT5CYC 0x5
+#define ADC_SMPR_SMP_71DOT5CYC 0x6
+#define ADC_SMPR_SMP_239DOT5CYC 0x7
+/**@}*/
+
+/* --- ADC_JOFRx, ADC_HTR, ADC_LTR values ---------------------------------- */
+
+#define ADC_JOFFSET_LSB 0
+#define ADC_JOFFSET_MSK (0x7ff << 0)
+#define ADC_HT_LSB 0
+#define ADC_HT_MSK (0x7ff << 0)
+#define ADC_LT_LSB 0
+#define ADC_LT_MSK (0x7ff << 0)
+
+/* --- ADC_SQR1 values ----------------------------------------------------- */
+
+#define ADC_SQR1_L_LSB 20
+#define ADC_SQR1_SQ16_LSB 15
+#define ADC_SQR1_SQ15_LSB 10
+#define ADC_SQR1_SQ14_LSB 5
+#define ADC_SQR1_SQ13_LSB 0
+#define ADC_SQR1_L_MSK (0xf << ADC_SQR1_L_LSB)
+#define ADC_SQR1_SQ16_MSK (0x1f << ADC_SQR1_SQ16_LSB)
+#define ADC_SQR1_SQ15_MSK (0x1f << ADC_SQR1_SQ15_LSB)
+#define ADC_SQR1_SQ14_MSK (0x1f << ADC_SQR1_SQ14_LSB)
+#define ADC_SQR1_SQ13_MSK (0x1f << ADC_SQR1_SQ13_LSB)
+
+/* --- ADC_SQR2 values ----------------------------------------------------- */
+
+#define ADC_SQR2_SQ12_LSB 25
+#define ADC_SQR2_SQ11_LSB 20
+#define ADC_SQR2_SQ10_LSB 15
+#define ADC_SQR2_SQ9_LSB 10
+#define ADC_SQR2_SQ8_LSB 5
+#define ADC_SQR2_SQ7_LSB 0
+#define ADC_SQR2_SQ12_MSK (0x1f << ADC_SQR2_SQ12_LSB)
+#define ADC_SQR2_SQ11_MSK (0x1f << ADC_SQR2_SQ11_LSB)
+#define ADC_SQR2_SQ10_MSK (0x1f << ADC_SQR2_SQ10_LSB)
+#define ADC_SQR2_SQ9_MSK (0x1f << ADC_SQR2_SQ9_LSB)
+#define ADC_SQR2_SQ8_MSK (0x1f << ADC_SQR2_SQ8_LSB)
+#define ADC_SQR2_SQ7_MSK (0x1f << ADC_SQR2_SQ7_LSB)
+
+/* --- ADC_SQR3 values ----------------------------------------------------- */
+
+#define ADC_SQR3_SQ6_LSB 25
+#define ADC_SQR3_SQ5_LSB 20
+#define ADC_SQR3_SQ4_LSB 15
+#define ADC_SQR3_SQ3_LSB 10
+#define ADC_SQR3_SQ2_LSB 5
+#define ADC_SQR3_SQ1_LSB 0
+#define ADC_SQR3_SQ6_MSK (0x1f << ADC_SQR3_SQ6_LSB)
+#define ADC_SQR3_SQ5_MSK (0x1f << ADC_SQR3_SQ5_LSB)
+#define ADC_SQR3_SQ4_MSK (0x1f << ADC_SQR3_SQ4_LSB)
+#define ADC_SQR3_SQ3_MSK (0x1f << ADC_SQR3_SQ3_LSB)
+#define ADC_SQR3_SQ2_MSK (0x1f << ADC_SQR3_SQ2_LSB)
+#define ADC_SQR3_SQ1_MSK (0x1f << ADC_SQR3_SQ1_LSB)
+
+/* --- ADC_JSQR values ----------------------------------------------------- */
+
+#define ADC_JSQR_JL_LSB 20
+#define ADC_JSQR_JSQ4_LSB 15
+#define ADC_JSQR_JSQ3_LSB 10
+#define ADC_JSQR_JSQ2_LSB 5
+#define ADC_JSQR_JSQ1_LSB 0
+
+/* JL[2:0]: Discontinous mode channel count injected channels. */
+/****************************************************************************/
+/** @defgroup adc_jsqr_jl ADC Number of channels in discontinuous mode fro injected channels.
+@ingroup STM32F4xx_adc_defines
+
+@{*/
+#define ADC_JSQR_JL_1CHANNELS (0x0 << ADC_JSQR_JL_LSB)
+#define ADC_JSQR_JL_2CHANNELS (0x1 << ADC_JSQR_JL_LSB)
+#define ADC_JSQR_JL_3CHANNELS (0x2 << ADC_JSQR_JL_LSB)
+#define ADC_JSQR_JL_4CHANNELS (0x3 << ADC_JSQR_JL_LSB)
+/**@}*/
+#define ADC_JSQR_JL_SHIFT 13
+#define ADC_JSQR_JL_MSK (0x2 << ADC_JSQR_JL_LSB)
+#define ADC_JSQR_JSQ4_MSK (0x1f << ADC_JSQR_JSQ4_LSB)
+#define ADC_JSQR_JSQ3_MSK (0x1f << ADC_JSQR_JSQ3_LSB)
+#define ADC_JSQR_JSQ2_MSK (0x1f << ADC_JSQR_JSQ2_LSB)
+#define ADC_JSQR_JSQ1_MSK (0x1f << ADC_JSQR_JSQ1_LSB)
+
+/* --- ADC_JDRx, ADC_DR values --------------------------------------------- */
+
+#define ADC_JDATA_LSB 0
+#define ADC_DATA_LSB 0
+#define ADC_JDATA_MSK (0xffff << ADC_JDATA_LSB)
+#define ADC_DATA_MSK (0xffff << ADC_DA)
+
+/* --- Common Registers ---------------------------------------------------- */
+
+/* --- ADC_CSR values (read only images) ------------------------------------ */
+
+/* OVR3: Overrun ADC3. */
+#define ADC_CSR_OVR3 (1 << 21)
+
+/* STRT3: Regular channel start ADC3. */
+#define ADC_CSR_STRT3 (1 << 20)
+
+/* JSTRT3: Injected channel start ADC3. */
+#define ADC_CSR_JSTRT3 (1 << 19)
+
+/* JEOC3: Injected channel end of conversion ADC3. */
+#define ADC_CSR_JEOC3 (1 << 18)
+
+/* EOC3: Regular channel end of conversion ADC3. */
+#define ADC_CSR_EOC3 (1 << 17)
+
+/* EOC3: Regular channel end of conversion ADC3. */
+#define ADC_CSR_AWD3 (1 << 16)
+
+/* Bits 15:14 Reserved, must be kept at reset value */
+
+/* OVR2: Overrun ADC2. */
+#define ADC_CSR_OVR2 (1 << 13)
+
+/* STRT2: Regular channel start ADC2. */
+#define ADC_CSR_STRT2 (1 << 12)
+
+/* JSTRT2: Injected channel start ADC2. */
+#define ADC_CSR_JSTRT2 (1 << 11)
+
+/* JEOC2: Injected channel end of conversion ADC2. */
+#define ADC_CSR_JEOC2 (1 << 10)
+
+/* EOC2: Regular channel end of conversion ADC2. */
+#define ADC_CSR_EOC2 (1 << 9)
+
+/* EOC2: Regular channel end of conversion ADC2. */
+#define ADC_CSR_AWD2 (1 << 8)
+
+/* Bits 7:6 Reserved, must be kept at reset value */
+
+/* OVR1: Overrun ADC1. */
+#define ADC_CSR_OVR1 (1 << 5)
+
+/* STRT1: Regular channel start ADC1. */
+#define ADC_CSR_STRT1 (1 << 4)
+
+/* JSTRT1: Injected channel start ADC1. */
+#define ADC_CSR_JSTRT1 (1 << 3)
+
+/* JEOC1: Injected channel end of conversion ADC1. */
+#define ADC_CSR_JEOC1 (1 << 2)
+
+/* EOC1: Regular channel end of conversion ADC1. */
+#define ADC_CSR_EOC1 (1 << 1)
+
+/* EOC1: Regular channel end of conversion ADC1. */
+#define ADC_CSR_AWD1 (1 << 0)
+
+/* --- ADC_CCR values ------------------------------------------------------ */
+
+/* TSVREFE: Temperature sensor and Vrefint enable. */
+#define ADC_CCR_TSVREFE (1 << 23)
+
+/* VBATE: VBat enable. */
+#define ADC_CCR_VBATE (1 << 22)
+
+/* Bit 18:21 reserved, must be kept at reset value. */
+
+/* ADCPRE: ADC prescaler. */
+/****************************************************************************/
+/** @defgroup adc_ccr_adcpre ADC Prescale
+@ingroup STM32F4xx_adc_defines
+
+@{*/
+#define ADC_CCR_ADCPRE_BY2 (0x0 << 16)
+#define ADC_CCR_ADCPRE_BY4 (0x1 << 16)
+#define ADC_CCR_ADCPRE_BY6 (0x2 << 16)
+#define ADC_CCR_ADCPRE_BY8 (0x3 << 16)
+/**@}*/
+#define ADC_CCR_ADCPRE_MASK (0x3 << 16)
+#define ADC_CCR_ADCPRE_SHIFT 16
+
+/* DMA: Direct memory access mode for multi ADC mode. */
+/****************************************************************************/
+/** @defgroup adc_dma_mode ADC DMA mode for multi ADC mode
+@ingroup STM32F4xx_adc_defines
+
+@{*/
+#define ADC_CCR_DMA_DISABLE (0x0 << 14)
+#define ADC_CCR_DMA_MODE_1 (0x1 << 14)
+#define ADC_CCR_DMA_MODE_2 (0x2 << 14)
+#define ADC_CCR_DMA_MODE_3 (0x3 << 14)
+/**@}*/
+#define ADC_CCR_DMA_MASK (0x3 << 14)
+#define ADC_CCR_DMA_SHIFT 14
+
+/* DDS: DMA disable selection (for multi-ADC mode). */
+#define ADC_CCR_DDS (1 << 13)
+
+/* Bit 12 reserved, must be kept at reset value */
+
+/* DELAY: Delay between 2 sampling phases. */
+/****************************************************************************/
+/** @defgroup adc_delay ADC Delay between 2 sampling phases
+@ingroup STM32F4xx_adc_defines
+
+@{*/
+#define ADC_CCR_DELAY_5ADCCLK (0x0 << 8)
+#define ADC_CCR_DELAY_6ADCCLK (0x1 << 8)
+#define ADC_CCR_DELAY_7ADCCLK (0x2 << 8)
+#define ADC_CCR_DELAY_8ADCCLK (0x3 << 8)
+#define ADC_CCR_DELAY_9ADCCLK (0x4 << 8)
+#define ADC_CCR_DELAY_10ADCCLK (0x5 << 8)
+#define ADC_CCR_DELAY_11ADCCLK (0x6 << 8)
+#define ADC_CCR_DELAY_12ADCCLK (0x7 << 8)
+#define ADC_CCR_DELAY_13ADCCLK (0x8 << 8)
+#define ADC_CCR_DELAY_14ADCCLK (0x9 << 8)
+#define ADC_CCR_DELAY_15ADCCLK (0xa << 8)
+#define ADC_CCR_DELAY_16ADCCLK (0xb << 8)
+#define ADC_CCR_DELAY_17ADCCLK (0xc << 8)
+#define ADC_CCR_DELAY_18ADCCLK (0xd << 8)
+#define ADC_CCR_DELAY_19ADCCLK (0xe << 8)
+#define ADC_CCR_DELAY_20ADCCLK (0xf << 8)
+/**@}*/
+#define ADC_CCR_DELAY_MASK (0xf << 8)
+#define ADC_CCR_DELAY_SHIFT 8
+
+/* Bit 7:5 reserved, must be kept at reset value */
+
+/* MULTI: Multi ADC mode selection. */
+/****************************************************************************/
+/** @defgroup adc_multi_mode ADC Multi mode selection
+@ingroup STM32F4xx_adc_defines
+
+@{*/
+
+/** All ADCs independent */
+#define ADC_CCR_MULTI_INDEPENDENT (0x00 << 0)
+
+/* dual modes (ADC1 + ADC2) */
+/** Dual modes (ADC1 + ADC2) Combined regular simultaneous + injected simultaneous mode */
+#define ADC_CCR_MULTI_DUAL_REG_SIMUL_AND_INJECTED_SIMUL (0x01 << 0)
+/** Dual modes (ADC1 + ADC2) Combined regular simultaneous + alternate trigger mode. */
+#define ADC_CCR_MULTI_DUAL_REG_SIMUL_AND_ALTERNATE_TRIG (0x02 << 0)
+/** Dual modes (ADC1 + ADC2) Injected simultaneous mode only. */
+#define ADC_CCR_MULTI_DUAL_INJECTED_SIMUL (0x05 << 0)
+/** Dual modes (ADC1 + ADC2) Regular simultaneous mode only. */
+#define ADC_CCR_MULTI_DUAL_REGULAR_SIMUL (0x06 << 0)
+/** Dual modes (ADC1 + ADC2) Interleaved mode only. */
+#define ADC_CCR_MULTI_DUAL_INTERLEAVED (0x07 << 0)
+/** Dual modes (ADC1 + ADC2) Alternate trigger mode only. */
+#define ADC_CCR_MULTI_DUAL_ALTERNATE_TRIG (0x09 << 0)
+
+/* Triple modes (ADC1 + ADC2 + ADC3) */
+/** Triple modes (ADC1 + ADC2 + ADC3) Combined regular simultaneous + injected simultaneous mode */
+#define ADC_CCR_MULTI_TRIPLE_REG_SIMUL_AND_INJECTED_SIMUL (0x11 << 0)
+/** Triple modes (ADC1 + ADC2 + ADC3) Combined regular simultaneous + alternate trigger mode. */
+#define ADC_CCR_MULTI_TRIPLE_REG_SIMUL_AND_ALTERNATE_TRIG (0x12 << 0)
+/** Triple modes (ADC1 + ADC2 + ADC3) Injected simultaneous mode only. */
+#define ADC_CCR_MULTI_TRIPLE_INJECTED_SIMUL (0x15 << 0)
+/** Triple modes (ADC1 + ADC2 + ADC3) Regular simultaneous mode only. */
+#define ADC_CCR_MULTI_TRIPLE_REGULAR_SIMUL (0x16 << 0)
+/** Triple modes (ADC1 + ADC2 + ADC3) Interleaved mode only. */
+#define ADC_CCR_MULTI_TRIPLE_INTERLEAVED (0x17 << 0)
+/** Triple modes (ADC1 + ADC2 + ADC3) Alternate trigger mode only. */
+#define ADC_CCR_MULTI_TRIPLE_ALTERNATE_TRIG (0x19 << 0)
+/**@}*/
+
+#define ADC_CCR_MULTI_MASK (0x1f << 0)
+#define ADC_CCR_MULTI_SHIFT 0
+
+/* --- ADC_CDR values ------------------------------------------------------ */
+
+#define ADC_CDR_DATA2_MASK (0xffff << 16)
+#define ADC_CDR_DATA2_SHIFT 16
+
+#define ADC_CDR_DATA1_MASK (0xffff << 0)
+#define ADC_CDR_DATA1_SHIFT 0
+
+BEGIN_DECLS
+
+void adc_power_on(u32 adc);
+void adc_off(u32 adc);
+void adc_enable_analog_watchdog_regular(u32 adc);
+void adc_disable_analog_watchdog_regular(u32 adc);
+void adc_enable_analog_watchdog_injected(u32 adc);
+void adc_disable_analog_watchdog_injected(u32 adc);
+void adc_enable_discontinuous_mode_regular(u32 adc, u8 length);
+void adc_disable_discontinuous_mode_regular(u32 adc);
+void adc_enable_discontinuous_mode_injected(u32 adc);
+void adc_disable_discontinuous_mode_injected(u32 adc);
+void adc_enable_automatic_injected_group_conversion(u32 adc);
+void adc_disable_automatic_injected_group_conversion(u32 adc);
+void adc_enable_analog_watchdog_on_all_channels(u32 adc);
+void adc_enable_analog_watchdog_on_selected_channel(u32 adc, u8 channel);
+void adc_enable_scan_mode(u32 adc);
+void adc_disable_scan_mode(u32 adc);
+void adc_enable_eoc_interrupt_injected(u32 adc);
+void adc_disable_eoc_interrupt_injected(u32 adc);
+void adc_enable_awd_interrupt(u32 adc);
+void adc_disable_awd_interrupt(u32 adc);
+void adc_enable_eoc_interrupt(u32 adc);
+void adc_disable_eoc_interrupt(u32 adc);
+void adc_start_conversion_regular(u32 adc);
+void adc_start_conversion_injected(u32 adc);
+void adc_disable_external_trigger_regular(u32 adc);
+void adc_disable_external_trigger_injected(u32 adc);
+void adc_set_left_aligned(u32 adc);
+void adc_set_right_aligned(u32 adc);
+void adc_enable_dma(u32 adc);
+void adc_disable_dma(u32 adc);
+void adc_set_continuous_conversion_mode(u32 adc);
+void adc_set_single_conversion_mode(u32 adc);
+void adc_set_sample_time(u32 adc, u8 channel, u8 time);
+void adc_set_sample_time_on_all_channels(u32 adc, u8 time);
+void adc_set_watchdog_high_threshold(u32 adc, u16 threshold);
+void adc_set_watchdog_low_threshold(u32 adc, u16 threshold);
+void adc_set_regular_sequence(u32 adc, u8 length, u8 channel[]);
+void adc_set_injected_sequence(u32 adc, u8 length, u8 channel[]);
+bool adc_eoc(u32 adc);
+bool adc_eoc_injected(u32 adc);
+u32 adc_read_regular(u32 adc);
+u32 adc_read_injected(u32 adc, u8 reg);
+void adc_set_injected_offset(u32 adc, u8 reg, u32 offset);
+
+void adc_set_clk_prescale(u32 prescaler);
+void adc_set_multi_mode(u32 mode);
+void adc_enable_external_trigger_regular(u32 adc, u32 trigger, u32 polarity);
+void adc_enable_external_trigger_injected(u32 adc, u32 trigger, u32 polarity);
+void adc_set_resolution(u32 adc, u16 resolution);
+void adc_enable_overrun_interrupt(u32 adc);
+void adc_disable_overrun_interrupt(u32 adc);
+bool adc_get_overrun_flag(u32 adc);
+void adc_clear_overrun_flag(u32 adc);
+bool adc_awd(u32 adc);
+void adc_eoc_after_each(u32 adc);
+void adc_eoc_after_group(u32 adc);
+void adc_set_dma_continue(u32 adc);
+void adc_set_dma_terminate(u32 adc);
+void adc_enable_temperature_sensor(void);
+void adc_disable_temperature_sensor(void);
+
+END_DECLS
+
+/**@}*/
+
+#endif
diff --git a/include/libopencm3/stm32/f4/dma.h b/include/libopencm3/stm32/f4/dma.h
new file mode 100644
index 0000000..1f034fa
--- /dev/null
+++ b/include/libopencm3/stm32/f4/dma.h
@@ -0,0 +1,693 @@
+/** @defgroup STM32F4xx_dma_defines DMA Defines
+
+@ingroup STM32F4xx_defines
+
+@brief Defined Constants and Types for the STM32F4xx DMA Controller
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 18 October 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Ken Sarkies <ksarkies@internode.on.net>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/**@{*/
+
+#ifndef LIBOPENCM3_DMA_H
+#define LIBOPENCM3_DMA_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/* --- Convenience macros -------------------------------------------------- */
+
+/* DMA register base adresses (for convenience) */
+#define DMA1 DMA1_BASE
+#define DMA2 DMA2_BASE
+
+/* --- DMA registers ------------------------------------------------------- */
+
+/* DMA low interrupt status register (DMAx_ISR) */
+#define DMA_LISR(dma_base) MMIO32(dma_base + 0x00)
+#define DMA1_LISR DMA_ISR(DMA1)
+#define DMA2_LISR DMA_ISR(DMA2)
+
+/* DMA high interrupt status register (DMAx_ISR) */
+#define DMA_HISR(dma_base) MMIO32(dma_base + 0x04)
+#define DMA1_HISR DMA_ISR(DMA1)
+#define DMA2_HISR DMA_ISR(DMA2)
+
+/* DMA low interrupt flag clear register (DMAx_IFCR) */
+#define DMA_LIFCR(dma_base) MMIO32(dma_base + 0x08)
+#define DMA1_LIFCR DMA_IFCR(DMA1)
+#define DMA2_LIFCR DMA_IFCR(DMA2)
+
+/* DMA high interrupt flag clear register (DMAx_IFCR) */
+#define DMA_HIFCR(dma_base) MMIO32(dma_base + 0x0C)
+#define DMA1_HIFCR DMA_IFCR(DMA1)
+#define DMA2_HIFCR DMA_IFCR(DMA2)
+
+/* DMA stream configuration register (DMAx_SyCR) */
+#define DMA_SCR(dma_base, stream) MMIO32(dma_base + 0x10 + \
+ (0x18 * (stream)))
+
+#define DMA1_SCR(stream) DMA_SCR(DMA1, stream)
+#define DMA1_S0CR DMA1_SCR(DMA_STREAM0)
+#define DMA1_S1CR DMA1_SCR(DMA_STREAM1)
+#define DMA1_S2CR DMA1_SCR(DMA_STREAM2)
+#define DMA1_S3CR DMA1_SCR(DMA_STREAM3)
+#define DMA1_S4CR DMA1_SCR(DMA_STREAM4)
+#define DMA1_S5CR DMA1_SCR(DMA_STREAM5)
+#define DMA1_S6CR DMA1_SCR(DMA_STREAM6)
+#define DMA1_S7CR DMA1_SCR(DMA_STREAM7)
+
+#define DMA2_SCR(stream) DMA_SCR(DMA2, stream)
+#define DMA2_S0CR DMA2_SCR(DMA_STREAM0)
+#define DMA2_S1CR DMA2_SCR(DMA_STREAM1)
+#define DMA2_S2CR DMA2_SCR(DMA_STREAM2)
+#define DMA2_S3CR DMA2_SCR(DMA_STREAM3)
+#define DMA2_S4CR DMA2_SCR(DMA_STREAM4)
+#define DMA2_S5CR DMA2_SCR(DMA_STREAM5)
+#define DMA2_S6CR DMA2_SCR(DMA_STREAM6)
+#define DMA2_S7CR DMA2_SCR(DMA_STREAM7)
+
+/* DMA number of data register (DMAx_SyNDTR) */
+#define DMA_SNDTR(dma_base, stream) MMIO32(dma_base + 0x14 + \
+ (0x18 * (stream)))
+
+#define DMA1_SNDTR(stream) DMA_SNDTR(DMA1, stream)
+#define DMA1_S0NDTR DMA1_SNDTR(DMA_STREAM0)
+#define DMA1_S1NDTR DMA1_SNDTR(DMA_STREAM1)
+#define DMA1_S2NDTR DMA1_SNDTR(DMA_STREAM2)
+#define DMA1_S3NDTR DMA1_SNDTR(DMA_STREAM3)
+#define DMA1_S4NDTR DMA1_SNDTR(DMA_STREAM4)
+#define DMA1_S5NDTR DMA1_SNDTR(DMA_STREAM5)
+#define DMA1_S6NDTR DMA1_SNDTR(DMA_STREAM6)
+#define DMA1_S7NDTR DMA1_SNDTR(DMA_STREAM7)
+
+#define DMA2_SNDTR(stream) DMA_CNDTR(DMA2, stream)
+#define DMA2_S0NDTR DMA2_SNDTR(DMA_STREAM0)
+#define DMA2_S1NDTR DMA2_SNDTR(DMA_STREAM1)
+#define DMA2_S2NDTR DMA2_SNDTR(DMA_STREAM2)
+#define DMA2_S3NDTR DMA2_SNDTR(DMA_STREAM3)
+#define DMA2_S4NDTR DMA2_SNDTR(DMA_STREAM4)
+#define DMA2_S5NDTR DMA2_SNDTR(DMA_STREAM5)
+#define DMA2_S6NDTR DMA2_SNDTR(DMA_STREAM6)
+#define DMA2_S7NDTR DMA2_SNDTR(DMA_STREAM7)
+
+/* DMA peripheral address register (DMAx_SyPAR) */
+#define DMA_SPAR(dma_base, stream) MMIO32(dma_base + 0x18 + \
+ (0x18 * (stream)))
+
+#define DMA1_SPAR(stream) DMA_SPAR(DMA1, stream)
+#define DMA1_S0PAR DMA1_SPAR(DMA_STREAM0)
+#define DMA1_S1PAR DMA1_SPAR(DMA_STREAM1)
+#define DMA1_S2PAR DMA1_SPAR(DMA_STREAM2)
+#define DMA1_S3PAR DMA1_SPAR(DMA_STREAM3)
+#define DMA1_S4PAR DMA1_SPAR(DMA_STREAM4)
+#define DMA1_S5PAR DMA1_SPAR(DMA_STREAM5)
+#define DMA1_S6PAR DMA1_SPAR(DMA_STREAM6)
+#define DMA1_S7PAR DMA1_SPAR(DMA_STREAM7)
+
+#define DMA2_SPAR(stream) DMA_SPAR(DMA2, stream)
+#define DMA2_S0PAR DMA2_SPAR(DMA_STREAM0)
+#define DMA2_S1PAR DMA2_SPAR(DMA_STREAM1)
+#define DMA2_S2PAR DMA2_SPAR(DMA_STREAM2)
+#define DMA2_S3PAR DMA2_SPAR(DMA_STREAM3)
+#define DMA2_S4PAR DMA2_SPAR(DMA_STREAM4)
+#define DMA2_S5PAR DMA2_SPAR(DMA_STREAM5)
+#define DMA2_S6PAR DMA2_SPAR(DMA_STREAM6)
+#define DMA2_S7PAR DMA2_SPAR(DMA_STREAM7)
+
+/* DMA memory 0 address register (DMAx_SyM0AR) */
+
+#define DMA_SM0AR(dma_base, stream) MMIO32(dma_base + 0x1C + \
+ (0x18 * (stream)))
+
+#define DMA1_SM0AR(stream) DMA_SM0AR(DMA1, stream)
+#define DMA1_S0M0AR DMA1_SM0AR(DMA_STREAM0)
+#define DMA1_S1M0AR DMA1_SM0AR(DMA_STREAM1)
+#define DMA1_S2M0AR DMA1_SM0AR(DMA_STREAM2)
+#define DMA1_S3M0AR DMA1_SM0AR(DMA_STREAM3)
+#define DMA1_S4M0AR DMA1_SM0AR(DMA_STREAM4)
+#define DMA1_S5M0AR DMA1_SM0AR(DMA_STREAM5)
+#define DMA1_S6M0AR DMA1_SM0AR(DMA_STREAM6)
+#define DMA1_S7M0AR DMA1_SM0AR(DMA_STREAM7)
+
+#define DMA2_SM0AR(stream) DMA_CM0AR(DMA2, stream)
+#define DMA2_S0M0AR DMA2_SM0AR(DMA_STREAM0)
+#define DMA2_S1M0AR DMA2_SM0AR(DMA_STREAM1)
+#define DMA2_S2M0AR DMA2_SM0AR(DMA_STREAM2)
+#define DMA2_S3M0AR DMA2_SM0AR(DMA_STREAM3)
+#define DMA2_S4M0AR DMA2_SM0AR(DMA_STREAM4)
+#define DMA2_S5M0AR DMA2_SM0AR(DMA_STREAM5)
+#define DMA2_S6M0AR DMA2_SM0AR(DMA_STREAM6)
+#define DMA2_S7M0AR DMA2_SM0AR(DMA_STREAM7)
+
+/* DMA memory 1 address register (DMAx_SyM1AR) */
+
+#define DMA_SM1AR(dma_base, stream) MMIO32(dma_base + 0x20 + \
+ (0x18 * (stream)))
+
+#define DMA1_SM1AR(stream) DMA_SM1AR(DMA1, stream)
+#define DMA1_S0M1AR DMA1_SM1AR(DMA_STREAM0)
+#define DMA1_S1M1AR DMA1_SM1AR(DMA_STREAM1)
+#define DMA1_S2M1AR DMA1_SM1AR(DMA_STREAM2)
+#define DMA1_S3M1AR DMA1_SM1AR(DMA_STREAM3)
+#define DMA1_S4M1AR DMA1_SM1AR(DMA_STREAM4)
+#define DMA1_S5M1AR DMA1_SM1AR(DMA_STREAM5)
+#define DMA1_S6M1AR DMA1_SM1AR(DMA_STREAM6)
+#define DMA1_S7M1AR DMA1_SM1AR(DMA_STREAM7)
+
+#define DMA2_SM1AR(stream) DMA_CM1AR(DMA2, stream)
+#define DMA2_S0M1AR DMA2_SM1AR(DMA_STREAM0)
+#define DMA2_S1M1AR DMA2_SM1AR(DMA_STREAM1)
+#define DMA2_S2M1AR DMA2_SM1AR(DMA_STREAM2)
+#define DMA2_S3M1AR DMA2_SM1AR(DMA_STREAM3)
+#define DMA2_S4M1AR DMA2_SM1AR(DMA_STREAM4)
+#define DMA2_S5M1AR DMA2_SM1AR(DMA_STREAM5)
+#define DMA2_S6M1AR DMA2_SM1AR(DMA_STREAM6)
+#define DMA2_S7M1AR DMA2_SM1AR(DMA_STREAM7)
+
+/* DMA FIFO Control Register register (DMAx_SyFCR) */
+
+#define DMA_SFCR(dma_base, stream) MMIO32(dma_base + 0x24 + \
+ (0x18 * (stream)))
+
+#define DMA1_SFCR(stream) DMA_SFCR(DMA1, stream)
+#define DMA1_S0FCR DMA1_SFCR(DMA_STREAM0)
+#define DMA1_S1FCR DMA1_SFCR(DMA_STREAM1)
+#define DMA1_S2FCR DMA1_SFCR(DMA_STREAM2)
+#define DMA1_S3FCR DMA1_SFCR(DMA_STREAM3)
+#define DMA1_S4FCR DMA1_SFCR(DMA_STREAM4)
+#define DMA1_S5FCR DMA1_SFCR(DMA_STREAM5)
+#define DMA1_S6FCR DMA1_SFCR(DMA_STREAM6)
+#define DMA1_S7FCR DMA1_SFCR(DMA_STREAM7)
+
+#define DMA2_SFCR(stream) DMA_CFCR(DMA2, stream)
+#define DMA2_S0FCR DMA2_SFCR(DMA_STREAM0)
+#define DMA2_S1FCR DMA2_SFCR(DMA_STREAM1)
+#define DMA2_S2FCR DMA2_SFCR(DMA_STREAM2)
+#define DMA2_S3FCR DMA2_SFCR(DMA_STREAM3)
+#define DMA2_S4FCR DMA2_SFCR(DMA_STREAM4)
+#define DMA2_S5FCR DMA2_SFCR(DMA_STREAM5)
+#define DMA2_S6FCR DMA2_SFCR(DMA_STREAM6)
+#define DMA2_S7FCR DMA2_SFCR(DMA_STREAM7)
+
+/* --- DMA Interrupt Flag offset values ------------------------------------- */
+/* These are based on every interrupt flag and flag clear being at the same relative location */
+/** @defgroup dma_if_offset DMA Interrupt Flag Offsets within stream flag group.
+@ingroup STM32F4xx_dma_defines
+
+@{*/
+/** Transfer Complete Interrupt Flag */
+#define DMA_ISR_TCIF (1 << 5)
+/** Half Transfer Interrupt Flag */
+#define DMA_ISR_HTIF (1 << 4)
+/** Transfer Error Interrupt Flag */
+#define DMA_ISR_TEIF (1 << 3)
+/** Direct Mode Error Interrupt Flag */
+#define DMA_ISR_DMEIF (1 << 2)
+/** FIFO Error Interrupt Flag */
+#define DMA_ISR_FEIF (1 << 0)
+/**@}*/
+
+/* Offset within interrupt status register to start of stream interrupt flag field */
+#define DMA_ISR_OFFSET(stream) (6*(stream & 0x01)+16*(stream & 0x02))
+#define DMA_ISR_FLAGS (DMA_ISR_TCIF | DMA_ISR_HTIF | DMA_ISR_TEIF | DMA_ISR_DMEIF | DMA_ISR_FEIF)
+#define DMA_ISR_MASK(stream) DMA_ISR_FLAGS << DMA_ISR_OFFSET(stream)
+
+/* --- DMA_LISR values ------------------------------------------------------ */
+
+/* TCIF: Transfer complete interrupt flag, streams 0-3 only */
+#define DMA_LISR_TCIF_BIT DMA_ISR_TCIF
+#define DMA_LISR_TCIF(stream) (DMA_LISR_TCIF_BIT << DMA_ISR_OFFSET(stream))
+
+#define DMA_LISR_TCIF0 DMA_LISR_TCIF(DMA_STREAM0)
+#define DMA_LISR_TCIF1 DMA_LISR_TCIF(DMA_STREAM1)
+#define DMA_LISR_TCIF2 DMA_LISR_TCIF(DMA_STREAM2)
+#define DMA_LISR_TCIF3 DMA_LISR_TCIF(DMA_STREAM3)
+
+/* HTIF: Half transfer interrupt flag, streams 0-3 only */
+#define DMA_LISR_HTIF_BIT DMA_ISR_HTIF
+#define DMA_LISR_HTIF(stream) (DMA_LISR_HTIF_BIT << DMA_ISR_OFFSET(stream))
+
+#define DMA_LISR_HTIF0 DMA_LISR_HTIF(DMA_STREAM0)
+#define DMA_LISR_HTIF1 DMA_LISR_HTIF(DMA_STREAM1)
+#define DMA_LISR_HTIF2 DMA_LISR_HTIF(DMA_STREAM2)
+#define DMA_LISR_HTIF3 DMA_LISR_HTIF(DMA_STREAM3)
+
+/* TEIF: Transfer error interrupt flag, streams 0-3 only */
+#define DMA_LISR_TEIF_BIT DMA_ISR_TEIF
+#define DMA_LISR_TEIF(stream) (DMA_LISR_TEIF_BIT << DMA_ISR_OFFSET(stream))
+
+#define DMA_LISR_TEIF0 DMA_LISR_TEIF(DMA_STREAM0)
+#define DMA_LISR_TEIF1 DMA_LISR_TEIF(DMA_STREAM1)
+#define DMA_LISR_TEIF2 DMA_LISR_TEIF(DMA_STREAM2)
+#define DMA_LISR_TEIF3 DMA_LISR_TEIF(DMA_STREAM3)
+
+/* DMEIF: Direct Mode Error interrupt flag, streams 0-3 only */
+#define DMA_LISR_DMEIF_BIT DMA_ISR_DMEIF
+#define DMA_LISR_DMEIF(stream) (DMA_LISR_DMEIF_BIT << DMA_ISR_OFFSET(stream))
+
+#define DMA_LISR_DMEIF0 DMA_LISR_DMEIF(DMA_STREAM0)
+#define DMA_LISR_DMEIF1 DMA_LISR_DMEIF(DMA_STREAM1)
+#define DMA_LISR_DMEIF2 DMA_LISR_DMEIF(DMA_STREAM2)
+#define DMA_LISR_DMEIF3 DMA_LISR_DMEIF(DMA_STREAM3)
+
+/* Interrupt #1 is reserved */
+
+/* FEIF: FIFO Error interrupt flag, streams 0-3 only */
+#define DMA_LISR_FEIF_BIT DMA_ISR_FEIF
+#define DMA_LISR_FEIF(stream) (DMA_LISR_FEIF_BIT << DMA_ISR_OFFSET(stream))
+
+#define DMA_LISR_FEIF0 DMA_LISR_FEIF(DMA_STREAM0)
+#define DMA_LISR_FEIF1 DMA_LISR_FEIF(DMA_STREAM1)
+#define DMA_LISR_FEIF2 DMA_LISR_FEIF(DMA_STREAM2)
+#define DMA_LISR_FEIF3 DMA_LISR_FEIF(DMA_STREAM3)
+
+/* --- DMA_HISR values ------------------------------------------------------ */
+
+/* TCIF: Transfer complete interrupt flag, streams 4-7 only */
+#define DMA_HISR_TCIF_BIT DMA_ISR_TCIF
+#define DMA_HISR_TCIF(stream) (DMA_HISR_TCIF_BIT << (DMA_ISR_OFFSET(stream - 4))
+
+#define DMA_HISR_TCIF4 DMA_HISR_TCIF(DMA_STREAM4)
+#define DMA_HISR_TCIF5 DMA_HISR_TCIF(DMA_STREAM5)
+#define DMA_HISR_TCIF6 DMA_HISR_TCIF(DMA_STREAM6)
+#define DMA_HISR_TCIF7 DMA_HISR_TCIF(DMA_STREAM7)
+
+/* HTIF: Half transfer interrupt flag, streams 4-7 only */
+#define DMA_HISR_HTIF_BIT DMA_ISR_HTIF
+#define DMA_HISR_HTIF(stream) (DMA_HISR_HTIF_BIT << (DMA_ISR_OFFSET(stream - 4))
+
+#define DMA_HISR_HTIF4 DMA_HISR_HTIF(DMA_STREAM4)
+#define DMA_HISR_HTIF5 DMA_HISR_HTIF(DMA_STREAM5)
+#define DMA_HISR_HTIF6 DMA_HISR_HTIF(DMA_STREAM6)
+#define DMA_HISR_HTIF7 DMA_HISR_HTIF(DMA_STREAM7)
+
+/* TEIF: Transfer error interrupt flag, streams 4-7 only */
+#define DMA_HISR_TEIF_BIT DMA_ISR_TEIF
+#define DMA_HISR_TEIF(stream) (DMA_HISR_TEIF_BIT << (DMA_ISR_OFFSET(stream - 4))
+
+#define DMA_HISR_TEIF4 DMA_HISR_TEIF(DMA_STREAM4)
+#define DMA_HISR_TEIF5 DMA_HISR_TEIF(DMA_STREAM5)
+#define DMA_HISR_TEIF6 DMA_HISR_TEIF(DMA_STREAM6)
+#define DMA_HISR_TEIF7 DMA_HISR_TEIF(DMA_STREAM7)
+
+/* DMEIF: Direct Mode Error interrupt flag, streams 4-7 only */
+#define DMA_HISR_DMEIF_BIT DMA_ISR_DMEIF
+#define DMA_HISR_DMEIF(stream) (DMA_HISR_DMEIF_BIT << (DMA_ISR_OFFSET(stream - 4))
+
+#define DMA_HISR_DMEIF4 DMA_HISR_DMEIF(DMA_STREAM4)
+#define DMA_HISR_DMEIF5 DMA_HISR_DMEIF(DMA_STREAM5)
+#define DMA_HISR_DMEIF6 DMA_HISR_DMEIF(DMA_STREAM6)
+#define DMA_HISR_DMEIF7 DMA_HISR_DMEIF(DMA_STREAM7)
+
+/* Interrupt #1 is reserved */
+
+/* FEIF: FIFO Error interrupt flag, streams 4-7 only */
+#define DMA_HISR_FEIF_BIT DMA_ISR_FEIF
+#define DMA_HISR_FEIF(stream) (DMA_HISR_FEIF_BIT << (DMA_ISR_OFFSET(stream - 4))
+
+#define DMA_HISR_FEIF4 DMA_HISR_FEIF(DMA_STREAM4)
+#define DMA_HISR_FEIF5 DMA_HISR_FEIF(DMA_STREAM5)
+#define DMA_HISR_FEIF6 DMA_HISR_FEIF(DMA_STREAM6)
+#define DMA_HISR_FEIF7 DMA_HISR_FEIF(DMA_STREAM7)
+
+/* --- DMA_LIFCR values ------------------------------------------------------ */
+
+/* TCIF: Transfer complete interrupt flag, streams 0-3 only */
+#define DMA_LIFCR_CTCIF_BIT DMA_ISR_TCIF
+#define DMA_LIFCR_CTCIF(stream) (DMA_LIFCR_CTCIF_BIT << DMA_ISR_OFFSET(stream))
+
+#define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF(DMA_STREAM0)
+#define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF(DMA_STREAM1)
+#define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF(DMA_STREAM2)
+#define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF(DMA_STREAM3)
+
+/* HTIF: Half transfer interrupt flag, streams 0-3 only */
+#define DMA_LIFCR_CHTIF_BIT DMA_ISR_HTIF
+#define DMA_LIFCR_CHTIF(stream) (DMA_LIFCR_CHTIF_BIT << DMA_ISR_OFFSET(stream))
+
+#define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF(DMA_STREAM0)
+#define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF(DMA_STREAM1)
+#define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF(DMA_STREAM2)
+#define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF(DMA_STREAM3)
+
+/* TEIF: Transfer error interrupt flag, streams 0-3 only */
+#define DMA_LIFCR_CTEIF_BIT DMA_ISR_TEIF
+#define DMA_LIFCR_CTEIF(stream) (DMA_LIFCR_CTEIF_BIT << DMA_ISR_OFFSET(stream))
+
+#define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF(DMA_STREAM0)
+#define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF(DMA_STREAM1)
+#define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF(DMA_STREAM2)
+#define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF(DMA_STREAM3)
+
+/* DMEIF: Direct Mode Error interrupt flag, streams 0-3 only */
+#define DMA_LIFCR_CDMEIF_BIT DMA_ISR_DMEIF
+#define DMA_LIFCR_CDMEIF(stream) (DMA_LIFCR_CDMEIF_BIT << DMA_ISR_OFFSET(stream))
+
+#define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF(DMA_STREAM0)
+#define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF(DMA_STREAM1)
+#define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF(DMA_STREAM2)
+#define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF(DMA_STREAM3)
+
+/* Interrupt #1 is reserved */
+
+/* FEIF: FIFO Error interrupt flag, streams 0-3 only */
+#define DMA_LIFCR_CFEIF_BIT DMA_ISR_FEIF
+#define DMA_LIFCR_CFEIF(stream) (DMA_LIFCR_CFEIF_BIT << DMA_ISR_OFFSET(stream))
+
+#define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF(DMA_STREAM0)
+#define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF(DMA_STREAM1)
+#define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF(DMA_STREAM2)
+#define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF(DMA_STREAM3)
+
+/* --- DMA_HIFCR values ------------------------------------------------------ */
+
+/* TCIF: Transfer complete interrupt flag, streams 4-7 only */
+#define DMA_HIFCR_CTCIF_BIT DMA_ISR_TCIF
+#define DMA_HIFCR_CTCIF(stream) (DMA_HIFCR_CTCIF_BIT << (DMA_ISR_OFFSET(stream - 4))
+
+#define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF(DMA_STREAM4)
+#define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF(DMA_STREAM5)
+#define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF(DMA_STREAM6)
+#define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF(DMA_STREAM7)
+
+/* HTIF: Half transfer interrupt flag, streams 4-7 only */
+#define DMA_HIFCR_CHTIF_BIT DMA_ISR_HTIF
+#define DMA_HIFCR_CHTIF(stream) (DMA_HIFCR_CHTIF_BIT << (DMA_ISR_OFFSET(stream - 4))
+
+#define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF(DMA_STREAM4)
+#define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF(DMA_STREAM5)
+#define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF(DMA_STREAM6)
+#define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF(DMA_STREAM7)
+
+/* TEIF: Transfer error interrupt flag, streams 4-7 only */
+#define DMA_HIFCR_CTEIF_BIT DMA_ISR_TEIF
+#define DMA_HIFCR_CTEIF(stream) (DMA_HIFCR_CTEIF_BIT << (DMA_ISR_OFFSET(stream - 4))
+
+#define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF(DMA_STREAM4)
+#define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF(DMA_STREAM5)
+#define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF(DMA_STREAM6)
+#define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF(DMA_STREAM7)
+
+/* DMEIF: Direct Mode Error interrupt flag, streams 4-7 only */
+#define DMA_HIFCR_CDMEIF_BIT DMA_ISR_DMEIF
+#define DMA_HIFCR_CDMEIF(stream) (DMA_HIFCR_CDMEIF_BIT << (DMA_ISR_OFFSET(stream - 4))
+
+#define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF(DMA_STREAM4)
+#define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF(DMA_STREAM5)
+#define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF(DMA_STREAM6)
+#define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF(DMA_STREAM7)
+
+/* Interrupt #1 is reserved */
+
+/* FEIF: FIFO Error interrupt flag, streams 4-7 only */
+#define DMA_HIFCR_CFEIF_BIT DMA_ISR_FEIF
+#define DMA_HIFCR_CFEIF(stream) (DMA_HIFCR_CFEIF_BIT << (DMA_ISR_OFFSET(stream - 4))
+
+#define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF(DMA_STREAM4)
+#define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF(DMA_STREAM5)
+#define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF(DMA_STREAM6)
+#define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF(DMA_STREAM7)
+
+/* --- DMA_SxCR generic values --------------------------------------------- */
+
+/* Reserved [31:28] */
+
+/* CHSEL[13:12]: Channel Select */
+/** @defgroup dma_ch_sel DMA Channel Select
+@ingroup STM32F4xx_dma_defines
+
+@{*/
+#define DMA_SCR_CHSEL_0 (0x0 << 25)
+#define DMA_SCR_CHSEL_1 (0x1 << 25)
+#define DMA_SCR_CHSEL_2 (0x2 << 25)
+#define DMA_SCR_CHSEL_3 (0x3 << 25)
+#define DMA_SCR_CHSEL_4 (0x4 << 25)
+#define DMA_SCR_CHSEL_5 (0x5 << 25)
+#define DMA_SCR_CHSEL_6 (0x6 << 25)
+#define DMA_SCR_CHSEL_7 (0x7 << 25)
+/**@}*/
+#define DMA_SCR_CHSEL_MASK (0x7 << 25)
+#define DMA_SCR_CHSEL_SHIFT 25
+
+/* MBURST[13:12]: Memory Burst Configuration */
+/** @defgroup dma_mburst DMA Memory Burst Length
+@ingroup STM32F4xx_dma_defines
+
+@{*/
+#define DMA_SCR_MBURST_INCR0 (0x0 << 23)
+#define DMA_SCR_MBURST_INCR4 (0x1 << 23)
+#define DMA_SCR_MBURST_INCR8 (0x2 << 23)
+#define DMA_SCR_MBURST_INCR16 (0x3 << 23)
+/**@}*/
+#define DMA_SCR_MBURST_MASK (0x3 << 23)
+#define DMA_SCR_MBURST_SHIFT 23
+
+/* PBURST[13:12]: Peripheral Burst Configuration */
+/** @defgroup dma_pburst DMA Peripheral Burst Length
+@ingroup STM32F4xx_dma_defines
+
+@{*/
+#define DMA_SCR_PBURST_INCR0 (0x0 << 21)
+#define DMA_SCR_PBURST_INCR4 (0x1 << 21)
+#define DMA_SCR_PBURST_INCR8 (0x2 << 21)
+#define DMA_SCR_PBURST_INCR16 (0x3 << 21)
+/**@}*/
+#define DMA_SCR_PBURST_MASK (0x3 << 21)
+#define DMA_SCR_PBURST_SHIFT 21
+
+/* Bit 20 reserved */
+
+/* CT: Current target (in double buffered mode) */
+#define DMA_SCR_CT (1 << 19)
+
+/* DBM: Double buffered mode */
+#define DMA_SCR_DBM (1 << 18)
+
+/* PL[17:16]: Stream priority level */
+/** @defgroup dma_st_pri DMA Stream Priority Levels
+@ingroup STM32F4xx_dma_defines
+
+@{*/
+#define DMA_SCR_PL_LOW (0x0 << 16)
+#define DMA_SCR_PL_MEDIUM (0x1 << 16)
+#define DMA_SCR_PL_HIGH (0x2 << 16)
+#define DMA_SCR_PL_VERY_HIGH (0x3 << 16)
+/**@}*/
+#define DMA_SCR_PL_MASK (0x3 << 16)
+#define DMA_SCR_PL_SHIFT 16
+
+/* PINCOS: Peripheral increment offset size */
+#define DMA_SCR_PINCOS (1 << 15)
+
+/* MSIZE[14:13]: Memory size */
+/** @defgroup dma_st_memwidth DMA Stream Memory Word Width
+@ingroup STM32F4xx_dma_defines
+
+@{*/
+#define DMA_SCR_MSIZE_8BIT (0x0 << 13)
+#define DMA_SCR_MSIZE_16BIT (0x1 << 13)
+#define DMA_SCR_MSIZE_32BIT (0x2 << 13)
+/**@}*/
+#define DMA_SCR_MSIZE_MASK (0x3 << 13)
+#define DMA_SCR_MSIZE_SHIFT 13
+
+/* PSIZE[12:11]: Peripheral size */
+/** @defgroup dma_st_perwidth DMA Stream Peripheral Word Width
+@ingroup STM32F4xx_dma_defines
+
+@{*/
+#define DMA_SCR_PSIZE_8BIT (0x0 << 11)
+#define DMA_SCR_PSIZE_16BIT (0x1 << 11)
+#define DMA_SCR_PSIZE_32BIT (0x2 << 11)
+/**@}*/
+#define DMA_SCR_PSIZE_MASK (0x3 << 11)
+#define DMA_SCR_PSIZE_SHIFT 11
+
+/* MINC: Memory increment mode */
+#define DMA_SCR_MINC (1 << 10)
+
+/* PINC: Peripheral increment mode */
+#define DMA_SCR_PINC (1 << 9)
+
+/* CIRC: Circular mode */
+#define DMA_SCR_CIRC (1 << 8)
+
+/* DIR[7:6]: Data transfer direction */
+/** @defgroup dma_st_dir DMA Stream Data transfer direction
+@ingroup STM32F4xx_dma_defines
+
+@{*/
+#define DMA_SCR_DIR_PER2MEM (0x0 << 6)
+#define DMA_SCR_DIR_MEM2PER (0x1 << 6)
+#define DMA_SCR_DIR_MEM2MEM (0x2 << 6)
+/**@}*/
+#define DMA_SCR_DIR_MASK (0x3 << 6)
+#define DMA_SCR_DIR_SHIFT 6
+
+/* PFCTRL: Peripheral Flow Controller */
+#define DMA_SCR_PFCTRL (1 << 5)
+
+/* TCIE: Transfer complete interrupt enable */
+#define DMA_SCR_TCIE (1 << 4)
+
+/* HTIE: Half transfer interrupt enable */
+#define DMA_SCR_HTIE (1 << 3)
+
+/* TEIE: Transfer error interrupt enable */
+#define DMA_SCR_TEIE (1 << 2)
+
+/* DMEIE: Direct Mode error interrupt enable */
+#define DMA_SCR_DMEIE (1 << 1)
+
+/* EN: Stream enable */
+#define DMA_SCR_EN (1 << 0)
+
+/* --- DMA_SxNDTR values --------------------------------------------------- */
+
+/* NDT[15:0]: Number of data to transfer */
+
+/* --- DMA_SxPAR values ---------------------------------------------------- */
+
+/* PA[31:0]: Peripheral address */
+
+/* --- DMA_SxM0AR values ---------------------------------------------------- */
+
+/* M0A[31:0]: Memory address */
+
+/* --- DMA_SxM1AR values ---------------------------------------------------- */
+
+/* M1A[31:0]: Memory address */
+
+/* --- DMA_SxFCR generic values --------------------------------------------- */
+
+/* Reserved [31:8] */
+
+/* FEIE: FIFO error interrupt enable */
+#define DMA_FCR_FEIE (1 << 7)
+
+/* Bit 6 reserved */
+
+/* FS[5:3]: FIFO Status */
+/** @defgroup dma_fifo_status FIFO Status
+@ingroup STM32F4xx_dma_defines
+
+@{*/
+#define DMA_FCR_FS_LOW (0x0 << 3)
+#define DMA_FCR_FS_UNDER_HALF (0x1 << 3)
+#define DMA_FCR_FS_MEDIUM (0x2 << 3)
+#define DMA_FCR_FS_HIGH (0x3 << 3)
+#define DMA_FCR_FS_EMPTY (0x4 << 3)
+#define DMA_FCR_FS_FULL (0x5 << 3)
+/**@}*/
+#define DMA_FCR_FS_MASK (0x7 << 3)
+#define DMA_FCR_FS_SHIFT 3
+
+/* DMDIS: Direct Mode disable */
+#define DMA_FCR_DMDIS (1 << 2)
+
+/* FTH[1:0]: FIFO Threshold selection */
+/** @defgroup dma_fifo_thresh FIFO Threshold selection
+@ingroup STM32F4xx_dma_defines
+
+@{*/
+#define DMA_FCR_FTH_LOW (0x0 << 0)
+#define DMA_FCR_FTH_HALF (0x1 << 0)
+#define DMA_FCR_FTH_MEDIUM (0x2 << 0)
+#define DMA_FCR_FTH_FULL (0x3 << 0)
+/**@}*/
+#define DMA_FCR_FTH_MASK (0x3 << 0)
+#define DMA_FCR_FTH_SHIFT 3
+
+/* --- Generic values ------------------------------------------------------ */
+
+/** @defgroup dma_st_number DMA Stream Number
+@ingroup STM32F4xx_dma_defines
+
+@{*/
+#define DMA_STREAM0 0
+#define DMA_STREAM1 1
+#define DMA_STREAM2 2
+#define DMA_STREAM3 3
+#define DMA_STREAM4 4
+#define DMA_STREAM5 5
+#define DMA_STREAM6 6
+#define DMA_STREAM7 7
+/**@}*/
+
+/* --- function prototypes ------------------------------------------------- */
+
+BEGIN_DECLS
+
+void dma_stream_reset(u32 dma, u8 stream);
+void dma_clear_interrupt_flags(u32 dma, u8 stream, u32 interrupts);
+bool dma_get_interrupt_flag(u32 dma, u8 stream, u32 interrupt);
+void dma_set_transfer_mode(u32 dma, u8 stream, u32 direction);
+void dma_set_priority(u32 dma, u8 stream, u32 prio);
+void dma_set_memory_size(u32 dma, u8 stream, u32 mem_size);
+void dma_set_peripheral_size(u32 dma, u8 stream, u32 peripheral_size);
+void dma_enable_memory_increment_mode(u32 dma, u8 stream);
+void dma_disable_memory_increment_mode(u32 dma, u8 channel);
+void dma_enable_peripheral_increment_mode(u32 dma, u8 stream);
+void dma_disable_peripheral_increment_mode(u32 dma, u8 channel);
+void dma_enable_fixed_peripheral_increment_mode(u32 dma, u8 stream);
+void dma_enable_circular_mode(u32 dma, u8 stream);
+void dma_channel_select(u32 dma, u8 stream, u32 channel);
+void dma_channel_select(u32 dma, u8 stream, u32 channel);
+void dma_set_memory_burst(u32 dma, u8 stream, u32 burst);
+void dma_set_peripheral_burst(u32 dma, u8 stream, u32 burst);
+void dma_set_initial_target(u32 dma, u8 stream, u8 memory);
+u8 dma_get_target(u32 dma, u8 stream);
+void dma_enable_double_buffer_mode(u32 dma, u8 stream);
+void dma_set_peripheral_flow_control(u32 dma, u8 stream);
+void dma_set_dma_flow_control(u32 dma, u8 stream);
+void dma_enable_transfer_error_interrupt(u32 dma, u8 stream);
+void dma_disable_transfer_error_interrupt(u32 dma, u8 stream);
+void dma_enable_half_transfer_interrupt(u32 dma, u8 stream);
+void dma_disable_half_transfer_interrupt(u32 dma, u8 stream);
+void dma_enable_transfer_complete_interrupt(u32 dma, u8 stream);
+void dma_disable_transfer_complete_interrupt(u32 dma, u8 stream);
+u32 dma_fifo_status(u32 dma, u8 stream);
+void dma_enable_direct_mode_error_interrupt(u32 dma, u8 stream);
+void dma_disable_direct_mode_error_interrupt(u32 dma, u8 stream);
+void dma_enable_fifo_error_interrupt(u32 dma, u8 stream);
+void dma_disable_fifo_error_interrupt(u32 dma, u8 stream);
+void dma_enable_direct_mode(u32 dma, u8 stream);
+void dma_enable_fifo_mode(u32 dma, u8 stream);
+void dma_set_fifo_threshold(u32 dma, u8 stream, u32 threshold);
+void dma_enable_stream(u32 dma, u8 stream);
+void dma_disable_stream(u32 dma, u8 stream);
+void dma_set_peripheral_address(u32 dma, u8 stream, u32 address);
+void dma_set_memory_address(u32 dma, u8 stream, u32 address);
+void dma_set_memory_address_1(u32 dma, u8 stream, u32 address);
+void dma_set_number_of_data(u32 dma, u8 stream, u16 number);
+
+END_DECLS
+
+#endif
+/**@}*/
+
diff --git a/include/libopencm3/stm32/otg_fs.h b/include/libopencm3/stm32/otg_fs.h
index 5680e43..d8ee393 100644
--- a/include/libopencm3/stm32/otg_fs.h
+++ b/include/libopencm3/stm32/otg_fs.h
@@ -24,7 +24,7 @@
#include <libopencm3/cm3/common.h>
/* Core Global Control and Status Registers */
-#define OTG_FS_OTGCTL MMIO32(USB_OTG_FS_BASE + 0x000)
+#define OTG_FS_GOTGCTL MMIO32(USB_OTG_FS_BASE + 0x000)
#define OTG_FS_GOTGINT MMIO32(USB_OTG_FS_BASE + 0x004)
#define OTG_FS_GAHBCFG MMIO32(USB_OTG_FS_BASE + 0x008)
#define OTG_FS_GUSBCFG MMIO32(USB_OTG_FS_BASE + 0x00C)
@@ -42,40 +42,40 @@
#define OTG_FS_DIEPTXF(x) MMIO32(USB_OTG_FS_BASE + 0x104 + 4*(x-1))
/* Host-mode Control and Status Registers */
-#define OTG_FS_HCFG MMIO32(USB_OTG_FS_BASE + 0x400)
-#define OTG_FS_HFIR MMIO32(USB_OTG_FS_BASE + 0x404)
-#define OTG_FS_HFNUM MMIO32(USB_OTG_FS_BASE + 0x408)
-#define OTG_FS_HPTXSTS MMIO32(USB_OTG_FS_BASE + 0x410)
-#define OTG_FS_HAINT MMIO32(USB_OTG_FS_BASE + 0x414)
-#define OTG_FS_HAINTMSK MMIO32(USB_OTG_FS_BASE + 0x418)
-#define OTG_FS_HPRT MMIO32(USB_OTG_FS_BASE + 0x440)
-#define OTG_FS_HCCHARx MMIO32(USB_OTG_FS_BASE + 0x500)
-#define OTG_FS_HCINTx MMIO32(USB_OTG_FS_BASE + 0x508)
-#define OTG_FS_HCINTMSKx MMIO32(USB_OTG_FS_BASE + 0x50C)
-#define OTG_FS_HCTSIZx MMIO32(USB_OTG_FS_BASE + 0x510)
+#define OTG_FS_HCFG MMIO32(USB_OTG_FS_BASE + 0x400)
+#define OTG_FS_HFIR MMIO32(USB_OTG_FS_BASE + 0x404)
+#define OTG_FS_HFNUM MMIO32(USB_OTG_FS_BASE + 0x408)
+#define OTG_FS_HPTXSTS MMIO32(USB_OTG_FS_BASE + 0x410)
+#define OTG_FS_HAINT MMIO32(USB_OTG_FS_BASE + 0x414)
+#define OTG_FS_HAINTMSK MMIO32(USB_OTG_FS_BASE + 0x418)
+#define OTG_FS_HPRT MMIO32(USB_OTG_FS_BASE + 0x440)
+#define OTG_FS_HCCHARx MMIO32(USB_OTG_FS_BASE + 0x500)
+#define OTG_FS_HCINTx MMIO32(USB_OTG_FS_BASE + 0x508)
+#define OTG_FS_HCINTMSKx MMIO32(USB_OTG_FS_BASE + 0x50C)
+#define OTG_FS_HCTSIZx MMIO32(USB_OTG_FS_BASE + 0x510)
/* Device-mode Control and Status Registers */
-#define OTG_FS_DCFG MMIO32(USB_OTG_FS_BASE + 0x800)
-#define OTG_FS_DCTL MMIO32(USB_OTG_FS_BASE + 0x804)
-#define OTG_FS_DSTS MMIO32(USB_OTG_FS_BASE + 0x808)
-#define OTG_FS_DIEPMSK MMIO32(USB_OTG_FS_BASE + 0x810)
-#define OTG_FS_DOEPMSK MMIO32(USB_OTG_FS_BASE + 0x814)
-#define OTG_FS_DAINT MMIO32(USB_OTG_FS_BASE + 0x818)
-#define OTG_FS_DAINTMSK MMIO32(USB_OTG_FS_BASE + 0x81C)
-#define OTG_FS_DVBUSDIS MMIO32(USB_OTG_FS_BASE + 0x828)
-#define OTG_FS_DVBUSPULSE MMIO32(USB_OTG_FS_BASE + 0x82C)
-#define OTG_FS_DIEPEMPMSK MMIO32(USB_OTG_FS_BASE + 0x834)
-#define OTG_FS_DIEPCTL0 MMIO32(USB_OTG_FS_BASE + 0x900)
-#define OTG_FS_DIEPCTL(x) MMIO32(USB_OTG_FS_BASE + 0x900 + 0x20*(x))
-#define OTG_FS_DOEPCTL0 MMIO32(USB_OTG_FS_BASE + 0xB00)
-#define OTG_FS_DOEPCTL(x) MMIO32(USB_OTG_FS_BASE + 0xB00 + 0x20*(x))
-#define OTG_FS_DIEPINT(x) MMIO32(USB_OTG_FS_BASE + 0x908 + 0x20*(x))
-#define OTG_FS_DOEPINT(x) MMIO32(USB_OTG_FS_BASE + 0xB08 + 0x20*(x))
-#define OTG_FS_DIEPTSIZ0 MMIO32(USB_OTG_FS_BASE + 0x910)
-#define OTG_FS_DOEPTSIZ0 MMIO32(USB_OTG_FS_BASE + 0xB10)
-#define OTG_FS_DIEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + 0x910 + 0x20*(x))
-#define OTG_FS_DTXFSTS(x) MMIO32(USB_OTG_FS_BASE + 0x918 + 0x20*(x))
-#define OTG_FS_DOEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + 0xB10 + 0x20*(x))
+#define OTG_FS_DCFG MMIO32(USB_OTG_FS_BASE + 0x800)
+#define OTG_FS_DCTL MMIO32(USB_OTG_FS_BASE + 0x804)
+#define OTG_FS_DSTS MMIO32(USB_OTG_FS_BASE + 0x808)
+#define OTG_FS_DIEPMSK MMIO32(USB_OTG_FS_BASE + 0x810)
+#define OTG_FS_DOEPMSK MMIO32(USB_OTG_FS_BASE + 0x814)
+#define OTG_FS_DAINT MMIO32(USB_OTG_FS_BASE + 0x818)
+#define OTG_FS_DAINTMSK MMIO32(USB_OTG_FS_BASE + 0x81C)
+#define OTG_FS_DVBUSDIS MMIO32(USB_OTG_FS_BASE + 0x828)
+#define OTG_FS_DVBUSPULSE MMIO32(USB_OTG_FS_BASE + 0x82C)
+#define OTG_FS_DIEPEMPMSK MMIO32(USB_OTG_FS_BASE + 0x834)
+#define OTG_FS_DIEPCTL0 MMIO32(USB_OTG_FS_BASE + 0x900)
+#define OTG_FS_DIEPCTL(x) MMIO32(USB_OTG_FS_BASE + 0x900 + 0x20*(x))
+#define OTG_FS_DOEPCTL0 MMIO32(USB_OTG_FS_BASE + 0xB00)
+#define OTG_FS_DOEPCTL(x) MMIO32(USB_OTG_FS_BASE + 0xB00 + 0x20*(x))
+#define OTG_FS_DIEPINT(x) MMIO32(USB_OTG_FS_BASE + 0x908 + 0x20*(x))
+#define OTG_FS_DOEPINT(x) MMIO32(USB_OTG_FS_BASE + 0xB08 + 0x20*(x))
+#define OTG_FS_DIEPTSIZ0 MMIO32(USB_OTG_FS_BASE + 0x910)
+#define OTG_FS_DOEPTSIZ0 MMIO32(USB_OTG_FS_BASE + 0xB10)
+#define OTG_FS_DIEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + 0x910 + 0x20*(x))
+#define OTG_FS_DTXFSTS(x) MMIO32(USB_OTG_FS_BASE + 0x918 + 0x20*(x))
+#define OTG_FS_DOEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + 0xB10 + 0x20*(x))
/* Power and clock gating control and status register */
#define OTG_FS_PCGCCTL MMIO32(USB_OTG_FS_BASE + 0xE00)
@@ -84,6 +84,18 @@
#define OTG_FS_FIFO(x) ((volatile u32*)(USB_OTG_FS_BASE + (((x) + 1) << 12)))
/* Global CSRs */
+/* OTG_FS USB control registers (OTG_HS_GOTGCTL) */
+#define OTG_FS_GOTGCTL_BSVLD (1 << 19)
+#define OTG_FS_GOTGCTL_ASVLD (1 << 18)
+#define OTG_FS_GOTGCTL_DBCT (1 << 17)
+#define OTG_FS_GOTGCTL_CIDSTS (1 << 16)
+#define OTG_FS_GOTGCTL_DHNPEN (1 << 11)
+#define OTG_FS_GOTGCTL_HSHNPEN (1 << 10)
+#define OTG_FS_GOTGCTL_HNPRQ (1 << 9)
+#define OTG_FS_GOTGCTL_HNGSCS (1 << 8)
+#define OTG_FS_GOTGCTL_SRQ (1 << 1)
+#define OTG_FS_GOTGCTL_SRQSCS (1 << 0)
+
/* OTG_FS AHB configuration register (OTG_FS_GAHBCFG) */
#define OTG_FS_GAHBCFG_GINT 0x0001
#define OTG_FS_GAHBCFG_TXFELVL 0x0080
@@ -175,20 +187,20 @@
/* OTG_FS Receive Status Pop Register (OTG_FS_GRXSTSP) */
/* Bits 31:25 - Reserved */
-#define OTG_FS_GRXSTSP_FRMNUM_MASK (0xf << 21)
-#define OTG_FS_GRXSTSP_PKTSTS_MASK (0xf << 17)
-#define OTG_FS_GRXSTSP_PKTSTS_GOUTNAK (0x1 << 17)
-#define OTG_FS_GRXSTSP_PKTSTS_OUT (0x2 << 17)
-#define OTG_FS_GRXSTSP_PKTSTS_OUT_COMP (0x3 << 17)
+#define OTG_FS_GRXSTSP_FRMNUM_MASK (0xf << 21)
+#define OTG_FS_GRXSTSP_PKTSTS_MASK (0xf << 17)
+#define OTG_FS_GRXSTSP_PKTSTS_GOUTNAK (0x1 << 17)
+#define OTG_FS_GRXSTSP_PKTSTS_OUT (0x2 << 17)
+#define OTG_FS_GRXSTSP_PKTSTS_OUT_COMP (0x3 << 17)
#define OTG_FS_GRXSTSP_PKTSTS_SETUP_COMP (0x4 << 17)
-#define OTG_FS_GRXSTSP_PKTSTS_SETUP (0x6 << 17)
-#define OTG_FS_GRXSTSP_DPID_MASK (0x3 << 15)
-#define OTG_FS_GRXSTSP_DPID_DATA0 (0x0 << 15)
-#define OTG_FS_GRXSTSP_DPID_DATA1 (0x2 << 15)
-#define OTG_FS_GRXSTSP_DPID_DATA2 (0x1 << 15)
-#define OTG_FS_GRXSTSP_DPID_MDATA (0x3 << 15)
-#define OTG_FS_GRXSTSP_BCNT_MASK (0x7ff << 4)
-#define OTG_FS_GRXSTSP_EPNUM_MASK (0xf << 0)
+#define OTG_FS_GRXSTSP_PKTSTS_SETUP (0x6 << 17)
+#define OTG_FS_GRXSTSP_DPID_MASK (0x3 << 15)
+#define OTG_FS_GRXSTSP_DPID_DATA0 (0x0 << 15)
+#define OTG_FS_GRXSTSP_DPID_DATA1 (0x2 << 15)
+#define OTG_FS_GRXSTSP_DPID_DATA2 (0x1 << 15)
+#define OTG_FS_GRXSTSP_DPID_MDATA (0x3 << 15)
+#define OTG_FS_GRXSTSP_BCNT_MASK (0x7ff << 4)
+#define OTG_FS_GRXSTSP_EPNUM_MASK (0xf << 0)
/* OTG_FS general core configuration register (OTG_FS_GCCFG) */
/* Bits 31:21 - Reserved */
@@ -320,4 +332,3 @@
#define OTG_FS_DIEPSIZ0_XFRSIZ_MASK (0x7f << 0)
#endif
-
diff --git a/include/libopencm3/stm32/otg_hs.h b/include/libopencm3/stm32/otg_hs.h
new file mode 100644
index 0000000..2f59ddd
--- /dev/null
+++ b/include/libopencm3/stm32/otg_hs.h
@@ -0,0 +1,396 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Gareth McMullin <gareth@blacksphere.co.nz>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_OTG_HS_H
+#define LIBOPENCM3_OTG_HS_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/* Core Global Control and Status Registers */
+#define OTG_GOTGCTL 0x000
+#define OTG_GOTGIN 0x004
+#define OTG_GAHBCFG 0x008
+#define OTG_GUSBCFG 0x00C
+#define OTG_GRSTCTL 0x010
+#define OTG_GINTSTS 0x014
+#define OTG_GINTMSK 0x018
+#define OTG_GRXSTSR 0x01C
+#define OTG_GRXSTSP 0x020
+#define OTG_GRXFSIZ 0x024
+#define OTG_GNPTXFSIZ 0x028
+#define OTG_GNPTXSTS 0x02C
+#define OTG_GCCFG 0x038
+#define OTG_CID 0x03C
+#define OTG_HPTXFSIZ 0x100
+#define OTG_DIEPTXF(x) (0x104 + 4*(x-1))
+
+/* Host-mode Control and Status Registers */
+#define OTG_HCFG 0x400
+#define OTG_HFIR 0x404
+#define OTG_HFNUM 0x408
+#define OTG_HPTXSTS 0x410
+#define OTG_HAINT 0x414
+#define OTG_HAINTMSK 0x418
+#define OTG_HPRT 0x440
+#define OTG_HCCHARx 0x500
+#define OTG_HCINTx 0x508
+#define OTG_HCINTMSKx 0x50C
+#define OTG_HCTSIZx 0x510
+
+/* Device-mode Control and Status Registers */
+#define OTG_DCFG 0x800
+#define OTG_DCTL 0x804
+#define OTG_DSTS 0x808
+#define OTG_DIEPMSK 0x810
+#define OTG_DOEPMSK 0x814
+#define OTG_DAINT 0x818
+#define OTG_DAINTMSK 0x81C
+#define OTG_DVBUSDIS 0x828
+#define OTG_DVBUSPULSE 0x82C
+#define OTG_DIEPEMPMSK 0x834
+#define OTG_DIEPCTL0 0x900
+#define OTG_DIEPCTL(x) (0x900 + 0x20*(x))
+#define OTG_DOEPCTL0 0xB00
+#define OTG_DOEPCTL(x) (0xB00 + 0x20*(x))
+#define OTG_DIEPINT(x) (0x908 + 0x20*(x))
+#define OTG_DOEPINT(x) (0xB08 + 0x20*(x))
+#define OTG_DIEPTSIZ0 0x910
+#define OTG_DOEPTSIZ0 0xB10
+#define OTG_DIEPTSIZ(x) (0x910 + 0x20*(x))
+#define OTG_DTXFSTS(x) (0x918 + 0x20*(x))
+#define OTG_DOEPTSIZ(x) (0xB10 + 0x20*(x))
+
+/* Power and clock gating control and status register */
+#define OTG_PCGCCTL 0xE00
+
+/* Data FIFO */
+#define OTG_FIFO(x) (((x) + 1) << 12)
+
+/***********************************************************************/
+
+/* Core Global Control and Status Registers */
+#define OTG_HS_GOTGCTL MMIO32(USB_OTG_HS_BASE + OTG_GOTGCTL)
+#define OTG_HS_GOTGINT MMIO32(USB_OTG_HS_BASE + OTG_GOTGINT)
+#define OTG_HS_GAHBCFG MMIO32(USB_OTG_HS_BASE + OTG_GAHBCFG)
+#define OTG_HS_GUSBCFG MMIO32(USB_OTG_HS_BASE + OTG_GUSBCFG)
+#define OTG_HS_GRSTCTL MMIO32(USB_OTG_HS_BASE + OTG_GRSTCTL)
+#define OTG_HS_GINTSTS MMIO32(USB_OTG_HS_BASE + OTG_GINTSTS)
+#define OTG_HS_GINTMSK MMIO32(USB_OTG_HS_BASE + OTG_GINTMSK)
+#define OTG_HS_GRXSTSR MMIO32(USB_OTG_HS_BASE + OTG_GRXSTSR)
+#define OTG_HS_GRXSTSP MMIO32(USB_OTG_HS_BASE + OTG_GRXSTSP)
+#define OTG_HS_GRXFSIZ MMIO32(USB_OTG_HS_BASE + OTG_GRXFSIZ)
+#define OTG_HS_GNPTXFSIZ MMIO32(USB_OTG_HS_BASE + OTG_GNPTXFSIZ)
+#define OTG_HS_GNPTXSTS MMIO32(USB_OTG_HS_BASE + OTG_GNPTXSTS)
+#define OTG_HS_GCCFG MMIO32(USB_OTG_HS_BASE + OTG_GCCFG)
+#define OTG_HS_CID MMIO32(USB_OTG_HS_BASE + OTG_CID)
+#define OTG_HS_HPTXFSIZ MMIO32(USB_OTG_HS_BASE + OTG_HPTXFSIZ)
+#define OTG_HS_DIEPTXF(x) MMIO32(USB_OTG_HS_BASE + OTG_DIEPTXF(x))
+
+/* Host-mode Control and Status Registers */
+#define OTG_HS_HCFG MMIO32(USB_OTG_HS_BASE + OTG_HCFG)
+#define OTG_HS_HFIR MMIO32(USB_OTG_HS_BASE + OTG_HFIR)
+#define OTG_HS_HFNUM MMIO32(USB_OTG_HS_BASE + OTG_HFNUM)
+#define OTG_HS_HPTXSTS MMIO32(USB_OTG_HS_BASE + OTG_HPTXSTS)
+#define OTG_HS_HAINT MMIO32(USB_OTG_HS_BASE + OTG_HAINT)
+#define OTG_HS_HAINTMSK MMIO32(USB_OTG_HS_BASE + OTG_HAINTMSK)
+#define OTG_HS_HPRT MMIO32(USB_OTG_HS_BASE + OTG_HPRT)
+#define OTG_HS_HCCHARx MMIO32(USB_OTG_HS_BASE + OTG_HCCHARx)
+#define OTG_HS_HCINTx MMIO32(USB_OTG_HS_BASE + OTG_HCINTx)
+#define OTG_HS_HCINTMSKx MMIO32(USB_OTG_HS_BASE + OTG_HCINTMSKx)
+#define OTG_HS_HCTSIZx MMIO32(USB_OTG_HS_BASE + OTG_HCTSIZx)
+
+/* Device-mode Control and Status Registers */
+#define OTG_HS_DCFG MMIO32(USB_OTG_HS_BASE + OTG_DCFG)
+#define OTG_HS_DCTL MMIO32(USB_OTG_HS_BASE + OTG_DCTL)
+#define OTG_HS_DSTS MMIO32(USB_OTG_HS_BASE + OTG_DSTS)
+#define OTG_HS_DIEPMSK MMIO32(USB_OTG_HS_BASE + OTG_DIEPMSK)
+#define OTG_HS_DOEPMSK MMIO32(USB_OTG_HS_BASE + OTG_DOEPMSK)
+#define OTG_HS_DAINT MMIO32(USB_OTG_HS_BASE + OTG_DAINT)
+#define OTG_HS_DAINTMSK MMIO32(USB_OTG_HS_BASE + OTG_DAINTMSK)
+#define OTG_HS_DVBUSDIS MMIO32(USB_OTG_HS_BASE + OTG_DVBUSDIS)
+#define OTG_HS_DVBUSPULSE MMIO32(USB_OTG_HS_BASE + OTG_DVBUSPULSE)
+#define OTG_HS_DIEPEMPMSK MMIO32(USB_OTG_HS_BASE + OTG_DIEPEMPMSK)
+#define OTG_HS_DIEPCTL0 MMIO32(USB_OTG_HS_BASE + OTG_DIEPCTL0)
+#define OTG_HS_DIEPCTL(x) MMIO32(USB_OTG_HS_BASE + OTG_DIEPCTL(x))
+#define OTG_HS_DOEPCTL0 MMIO32(USB_OTG_HS_BASE + OTG_DOEPCTL0)
+#define OTG_HS_DOEPCTL(x) MMIO32(USB_OTG_HS_BASE + OTG_DOEPCTL(x))
+#define OTG_HS_DIEPINT(x) MMIO32(USB_OTG_HS_BASE + OTG_DIEPINT(x))
+#define OTG_HS_DOEPINT(x) MMIO32(USB_OTG_HS_BASE + OTG_DOEPINT(x))
+#define OTG_HS_DIEPTSIZ0 MMIO32(USB_OTG_HS_BASE + OTG_DIEPTSIZ0)
+#define OTG_HS_DOEPTSIZ0 MMIO32(USB_OTG_HS_BASE + OTG_DOEPTSIZ0)
+#define OTG_HS_DIEPTSIZ(x) MMIO32(USB_OTG_HS_BASE + OTG_DIEPTSIZ(x)))
+#define OTG_HS_DTXFSTS(x) MMIO32(USB_OTG_HS_BASE + OTG_DTXFSTS(x))
+#define OTG_HS_DOEPTSIZ(x) MMIO32(USB_OTG_HS_BASE + OTG_DOEPTSIZ(x))
+
+/* Power and clock gating control and status register */
+#define OTG_HS_PCGCCTL MMIO32(USB_OTG_HS_BASE + OTG_PCGCCTL)
+
+/* Data FIFO */
+#define OTG_HS_FIFO(x) ((volatile u32*)(USB_OTG_HS_BASE + OTG_FIFO(x)))
+
+/* Global CSRs */
+/* OTG_HS USB control registers (OTG_FS_GOTGCTL) */
+#define OTG_HS_GOTGCTL_BSVLD (1 << 19)
+#define OTG_HS_GOTGCTL_ASVLD (1 << 18)
+#define OTG_HS_GOTGCTL_DBCT (1 << 17)
+#define OTG_HS_GOTGCTL_CIDSTS (1 << 16)
+#define OTG_HS_GOTGCTL_DHNPEN (1 << 11)
+#define OTG_HS_GOTGCTL_HSHNPEN (1 << 10)
+#define OTG_HS_GOTGCTL_HNPRQ (1 << 9)
+#define OTG_HS_GOTGCTL_HNGSCS (1 << 8)
+#define OTG_HS_GOTGCTL_SRQ (1 << 1)
+#define OTG_HS_GOTGCTL_SRQSCS (1 << 0)
+
+/* OTG_FS AHB configuration register (OTG_HS_GAHBCFG) */
+#define OTG_HS_GAHBCFG_GINT 0x0001
+#define OTG_HS_GAHBCFG_TXFELVL 0x0080
+#define OTG_HS_GAHBCFG_PTXFELVL 0x0100
+
+/* OTG_FS USB configuration register (OTG_HS_GUSBCFG) */
+#define OTG_HS_GUSBCFG_TOCAL 0x00000003
+#define OTG_HS_GUSBCFG_SRPCAP 0x00000100
+#define OTG_HS_GUSBCFG_HNPCAP 0x00000200
+#define OTG_HS_GUSBCFG_TRDT_MASK (0xf << 10)
+#define OTG_HS_GUSBCFG_TRDT_16BIT (0x5 << 10)
+#define OTG_HS_GUSBCFG_TRDT_8BIT (0x9 << 10)
+#define OTG_HS_GUSBCFG_NPTXRWEN 0x00004000
+#define OTG_HS_GUSBCFG_FHMOD 0x20000000
+#define OTG_HS_GUSBCFG_FDMOD 0x40000000
+#define OTG_HS_GUSBCFG_CTXPKT 0x80000000
+#define OTG_HS_GUSBCFG_PHYSEL (1 << 6)
+
+/* OTG_FS reset register (OTG_HS_GRSTCTL) */
+#define OTG_HS_GRSTCTL_AHBIDL (1 << 31)
+/* Bits 30:11 - Reserved */
+#define OTG_HS_GRSTCTL_TXFNUM_MASK (0x1f << 6)
+#define OTG_HS_GRSTCTL_TXFFLSH (1 << 5)
+#define OTG_HS_GRSTCTL_RXFFLSH (1 << 4)
+/* Bit 3 - Reserved */
+#define OTG_HS_GRSTCTL_FCRST (1 << 2)
+#define OTG_HS_GRSTCTL_HSRST (1 << 1)
+#define OTG_HS_GRSTCTL_CSRST (1 << 0)
+
+/* OTG_FS interrupt status register (OTG_HS_GINTSTS) */
+#define OTG_HS_GINTSTS_WKUPINT (1 << 31)
+#define OTG_HS_GINTSTS_SRQINT (1 << 30)
+#define OTG_HS_GINTSTS_DISCINT (1 << 29)
+#define OTG_HS_GINTSTS_CIDSCHG (1 << 28)
+/* Bit 27 - Reserved */
+#define OTG_HS_GINTSTS_PTXFE (1 << 26)
+#define OTG_HS_GINTSTS_HCINT (1 << 25)
+#define OTG_HS_GINTSTS_HPRTINT (1 << 24)
+/* Bits 23:22 - Reserved */
+#define OTG_HS_GINTSTS_IPXFR (1 << 21)
+#define OTG_HS_GINTSTS_INCOMPISOOUT (1 << 21)
+#define OTG_HS_GINTSTS_IISOIXFR (1 << 20)
+#define OTG_HS_GINTSTS_OEPINT (1 << 19)
+#define OTG_HS_GINTSTS_IEPINT (1 << 18)
+/* Bits 17:16 - Reserved */
+#define OTG_HS_GINTSTS_EOPF (1 << 15)
+#define OTG_HS_GINTSTS_ISOODRP (1 << 14)
+#define OTG_HS_GINTSTS_ENUMDNE (1 << 13)
+#define OTG_HS_GINTSTS_USBRST (1 << 12)
+#define OTG_HS_GINTSTS_USBSUSP (1 << 11)
+#define OTG_HS_GINTSTS_ESUSP (1 << 10)
+/* Bits 9:8 - Reserved */
+#define OTG_HS_GINTSTS_GONAKEFF (1 << 7)
+#define OTG_HS_GINTSTS_GINAKEFF (1 << 6)
+#define OTG_HS_GINTSTS_NPTXFE (1 << 5)
+#define OTG_HS_GINTSTS_RXFLVL (1 << 4)
+#define OTG_HS_GINTSTS_SOF (1 << 3)
+#define OTG_HS_GINTSTS_OTGINT (1 << 2)
+#define OTG_HS_GINTSTS_MMIS (1 << 1)
+#define OTG_HS_GINTSTS_CMOD (1 << 0)
+
+/* OTG_FS interrupt mask register (OTG_HS_GINTMSK) */
+#define OTG_HS_GINTMSK_MMISM 0x00000002
+#define OTG_HS_GINTMSK_OTGINT 0x00000004
+#define OTG_HS_GINTMSK_SOFM 0x00000008
+#define OTG_HS_GINTMSK_RXFLVLM 0x00000010
+#define OTG_HS_GINTMSK_NPTXFEM 0x00000020
+#define OTG_HS_GINTMSK_GINAKEFFM 0x00000040
+#define OTG_HS_GINTMSK_GONAKEFFM 0x00000080
+#define OTG_HS_GINTMSK_ESUSPM 0x00000400
+#define OTG_HS_GINTMSK_USBSUSPM 0x00000800
+#define OTG_HS_GINTMSK_USBRST 0x00001000
+#define OTG_HS_GINTMSK_ENUMDNEM 0x00002000
+#define OTG_HS_GINTMSK_ISOODRPM 0x00004000
+#define OTG_HS_GINTMSK_EOPFM 0x00008000
+#define OTG_HS_GINTMSK_EPMISM 0x00020000
+#define OTG_HS_GINTMSK_IEPINT 0x00040000
+#define OTG_HS_GINTMSK_OEPINT 0x00080000
+#define OTG_HS_GINTMSK_IISOIXFRM 0x00100000
+#define OTG_HS_GINTMSK_IISOOXFRM 0x00200000
+#define OTG_HS_GINTMSK_IPXFRM 0x00200000
+#define OTG_HS_GINTMSK_PRTIM 0x01000000
+#define OTG_HS_GINTMSK_HCIM 0x02000000
+#define OTG_HS_GINTMSK_PTXFEM 0x04000000
+#define OTG_HS_GINTMSK_CIDSCHGM 0x10000000
+#define OTG_HS_GINTMSK_DISCINT 0x20000000
+#define OTG_HS_GINTMSK_SRQIM 0x40000000
+#define OTG_HS_GINTMSK_WUIM 0x80000000
+
+/* OTG_FS Receive Status Pop Register (OTG_HS_GRXSTSP) */
+/* Bits 31:25 - Reserved */
+#define OTG_HS_GRXSTSP_FRMNUM_MASK (0xf << 21)
+#define OTG_HS_GRXSTSP_PKTSTS_MASK (0xf << 17)
+#define OTG_HS_GRXSTSP_PKTSTS_GOUTNAK (0x1 << 17)
+#define OTG_HS_GRXSTSP_PKTSTS_OUT (0x2 << 17)
+#define OTG_HS_GRXSTSP_PKTSTS_OUT_COMP (0x3 << 17)
+#define OTG_HS_GRXSTSP_PKTSTS_SETUP_COMP (0x4 << 17)
+#define OTG_HS_GRXSTSP_PKTSTS_SETUP (0x6 << 17)
+#define OTG_HS_GRXSTSP_DPID_MASK (0x3 << 15)
+#define OTG_HS_GRXSTSP_DPID_DATA0 (0x0 << 15)
+#define OTG_HS_GRXSTSP_DPID_DATA1 (0x2 << 15)
+#define OTG_HS_GRXSTSP_DPID_DATA2 (0x1 << 15)
+#define OTG_HS_GRXSTSP_DPID_MDATA (0x3 << 15)
+#define OTG_HS_GRXSTSP_BCNT_MASK (0x7ff << 4)
+#define OTG_HS_GRXSTSP_EPNUM_MASK (0xf << 0)
+
+/* OTG_FS general core configuration register (OTG_HS_GCCFG) */
+/* Bits 31:21 - Reserved */
+#define OTG_HS_GCCFG_SOFOUTEN (1 << 20)
+#define OTG_HS_GCCFG_VBUSBSEN (1 << 19)
+#define OTG_HS_GCCFG_VBUSASEN (1 << 18)
+/* Bit 17 - Reserved */
+#define OTG_HS_GCCFG_PWRDWN (1 << 16)
+/* Bits 15:0 - Reserved */
+
+
+/* Device-mode CSRs */
+/* OTG_FS device control register (OTG_HS_DCTL) */
+/* Bits 31:12 - Reserved */
+#define OTG_HS_DCTL_POPRGDNE (1 << 11)
+#define OTG_HS_DCTL_CGONAK (1 << 10)
+#define OTG_HS_DCTL_SGONAK (1 << 9)
+#define OTG_HS_DCTL_SGINAK (1 << 8)
+#define OTG_HS_DCTL_TCTL_MASK (7 << 4)
+#define OTG_HS_DCTL_GONSTS (1 << 3)
+#define OTG_HS_DCTL_GINSTS (1 << 2)
+#define OTG_HS_DCTL_SDIS (1 << 1)
+#define OTG_HS_DCTL_RWUSIG (1 << 0)
+
+/* OTG_FS device configuration register (OTG_HS_DCFG) */
+#define OTG_HS_DCFG_DSPD 0x0003
+#define OTG_HS_DCFG_NZLSOHSK 0x0004
+#define OTG_HS_DCFG_DAD 0x07F0
+#define OTG_HS_DCFG_PFIVL 0x1800
+
+/* OTG_FS Device IN Endpoint Common Interrupt Mask Register (OTG_HS_DIEPMSK) */
+/* Bits 31:10 - Reserved */
+#define OTG_HS_DIEPMSK_BIM (1 << 9)
+#define OTG_HS_DIEPMSK_TXFURM (1 << 8)
+/* Bit 7 - Reserved */
+#define OTG_HS_DIEPMSK_INEPNEM (1 << 6)
+#define OTG_HS_DIEPMSK_INEPNMM (1 << 5)
+#define OTG_HS_DIEPMSK_ITTXFEMSK (1 << 4)
+#define OTG_HS_DIEPMSK_TOM (1 << 3)
+/* Bit 2 - Reserved */
+#define OTG_HS_DIEPMSK_EPDM (1 << 1)
+#define OTG_HS_DIEPMSK_XFRCM (1 << 0)
+
+/* OTG_FS Device OUT Endpoint Common Interrupt Mask Register (OTG_HS_DOEPMSK) */
+/* Bits 31:10 - Reserved */
+#define OTG_HS_DOEPMSK_BOIM (1 << 9)
+#define OTG_HS_DOEPMSK_OPEM (1 << 8)
+/* Bit 7 - Reserved */
+#define OTG_HS_DOEPMSK_B2BSTUP (1 << 6)
+/* Bit 5 - Reserved */
+#define OTG_HS_DOEPMSK_OTEPDM (1 << 4)
+#define OTG_HS_DOEPMSK_STUPM (1 << 3)
+/* Bit 2 - Reserved */
+#define OTG_HS_DOEPMSK_EPDM (1 << 1)
+#define OTG_HS_DOEPMSK_XFRCM (1 << 0)
+
+/* OTG_FS Device Control IN Endpoint 0 Control Register (OTG_HS_DIEPCTL0) */
+#define OTG_HS_DIEPCTL0_EPENA (1 << 31)
+#define OTG_HS_DIEPCTL0_EPDIS (1 << 30)
+/* Bits 29:28 - Reserved */
+#define OTG_HS_DIEPCTLX_SD0PID (1 << 28)
+#define OTG_HS_DIEPCTL0_SNAK (1 << 27)
+#define OTG_HS_DIEPCTL0_CNAK (1 << 26)
+#define OTG_HS_DIEPCTL0_TXFNUM_MASK (0xf << 22)
+#define OTG_HS_DIEPCTL0_STALL (1 << 21)
+/* Bit 20 - Reserved */
+#define OTG_HS_DIEPCTL0_EPTYP_MASK (0x3 << 18)
+#define OTG_HS_DIEPCTL0_NAKSTS (1 << 17)
+/* Bit 16 - Reserved */
+#define OTG_HS_DIEPCTL0_USBAEP (1 << 15)
+/* Bits 14:2 - Reserved */
+#define OTG_HS_DIEPCTL0_MPSIZ_MASK (0x3 << 0)
+#define OTG_HS_DIEPCTL0_MPSIZ_64 (0x0 << 0)
+#define OTG_HS_DIEPCTL0_MPSIZ_32 (0x1 << 0)
+#define OTG_HS_DIEPCTL0_MPSIZ_16 (0x2 << 0)
+#define OTG_HS_DIEPCTL0_MPSIZ_8 (0x3 << 0)
+
+/* OTG_FS Device Control OUT Endpoint 0 Control Register (OTG_HS_DOEPCTL0) */
+#define OTG_HS_DOEPCTL0_EPENA (1 << 31)
+#define OTG_HS_DOEPCTL0_EPDIS (1 << 30)
+/* Bits 29:28 - Reserved */
+#define OTG_HS_DOEPCTLX_SD0PID (1 << 28)
+#define OTG_HS_DOEPCTL0_SNAK (1 << 27)
+#define OTG_HS_DOEPCTL0_CNAK (1 << 26)
+/* Bits 25:22 - Reserved */
+#define OTG_HS_DOEPCTL0_STALL (1 << 21)
+#define OTG_HS_DOEPCTL0_SNPM (1 << 20)
+#define OTG_HS_DOEPCTL0_EPTYP_MASK (0x3 << 18)
+#define OTG_HS_DOEPCTL0_NAKSTS (1 << 17)
+/* Bit 16 - Reserved */
+#define OTG_HS_DOEPCTL0_USBAEP (1 << 15)
+/* Bits 14:2 - Reserved */
+#define OTG_HS_DOEPCTL0_MPSIZ_MASK (0x3 << 0)
+#define OTG_HS_DOEPCTL0_MPSIZ_64 (0x0 << 0)
+#define OTG_HS_DOEPCTL0_MPSIZ_32 (0x1 << 0)
+#define OTG_HS_DOEPCTL0_MPSIZ_16 (0x2 << 0)
+#define OTG_HS_DOEPCTL0_MPSIZ_8 (0x3 << 0)
+
+/* OTG_FS Device IN Endpoint Interrupt Register (OTG_HS_DIEPINTx) */
+/* Bits 31:8 - Reserved */
+#define OTG_HS_DIEPINTX_TXFE (1 << 7)
+#define OTG_HS_DIEPINTX_INEPNE (1 << 6)
+/* Bit 5 - Reserved */
+#define OTG_HS_DIEPINTX_ITTXFE (1 << 4)
+#define OTG_HS_DIEPINTX_TOC (1 << 3)
+/* Bit 2 - Reserved */
+#define OTG_HS_DIEPINTX_EPDISD (1 << 1)
+#define OTG_HS_DIEPINTX_XFRC (1 << 0)
+
+/* OTG_FS Device IN Endpoint Interrupt Register (OTG_HS_DOEPINTx) */
+/* Bits 31:7 - Reserved */
+#define OTG_HS_DOEPINTX_B2BSTUP (1 << 6)
+/* Bit 5 - Reserved */
+#define OTG_HS_DOEPINTX_OTEPDIS (1 << 4)
+#define OTG_HS_DOEPINTX_STUP (1 << 3)
+/* Bit 2 - Reserved */
+#define OTG_HS_DOEPINTX_EPDISD (1 << 1)
+#define OTG_HS_DOEPINTX_XFRC (1 << 0)
+
+/* OTG_FS Device OUT Endpoint 0 Transfer Size Regsiter (OTG_HS_DOEPTSIZ0) */
+/* Bit 31 - Reserved */
+#define OTG_HS_DIEPSIZ0_STUPCNT_1 (0x1 << 29)
+#define OTG_HS_DIEPSIZ0_STUPCNT_2 (0x2 << 29)
+#define OTG_HS_DIEPSIZ0_STUPCNT_3 (0x3 << 29)
+#define OTG_HS_DIEPSIZ0_STUPCNT_MASK (0x3 << 29)
+/* Bits 28:20 - Reserved */
+#define OTG_HS_DIEPSIZ0_PKTCNT (1 << 19)
+/* Bits 18:7 - Reserved */
+#define OTG_HS_DIEPSIZ0_XFRSIZ_MASK (0x7f << 0)
+
+#endif
diff --git a/include/libopencm3/usb/cdc.h b/include/libopencm3/usb/cdc.h
index 4b54961..5036411 100644
--- a/include/libopencm3/usb/cdc.h
+++ b/include/libopencm3/usb/cdc.h
@@ -112,7 +112,7 @@ struct usb_cdc_line_coding {
/* Table 30: Class-Specific Notification Codes for PSTN subclasses */
/* ... */
-#define USB_CDC_NOTIFY_SERIAL_STATE 0x20
+#define USB_CDC_NOTIFY_SERIAL_STATE 0x20
/* ... */
/* Notification Structure */
diff --git a/include/libopencm3/usb/usbd.h b/include/libopencm3/usb/usbd.h
index e4b3578..98bf6eb 100644
--- a/include/libopencm3/usb/usbd.h
+++ b/include/libopencm3/usb/usbd.h
@@ -25,9 +25,13 @@
BEGIN_DECLS
typedef struct _usbd_driver usbd_driver;
+typedef struct _usbd_device usbd_device;
+
extern const usbd_driver stm32f103_usb_driver;
extern const usbd_driver stm32f107_usb_driver;
+extern const usbd_driver stm32f207_usb_driver;
#define otgfs_usb_driver stm32f107_usb_driver
+#define otghs_usb_driver stm32f207_usb_driver
/* Static buffer for control transactions:
* This is defined as weak in the library, applicaiton
@@ -35,45 +39,55 @@ extern const usbd_driver stm32f107_usb_driver;
extern u8 usbd_control_buffer[];
/* <usb.c> */
-extern int usbd_init(const usbd_driver *driver,
+extern usbd_device *usbd_init(const usbd_driver *driver,
const struct usb_device_descriptor *dev,
const struct usb_config_descriptor *conf,
const char **strings);
-extern void usbd_set_control_buffer_size(u16 size);
-
-extern void usbd_register_reset_callback(void (*callback)(void));
-extern void usbd_register_suspend_callback(void (*callback)(void));
-extern void usbd_register_resume_callback(void (*callback)(void));
-extern void usbd_register_sof_callback(void (*callback)(void));
-
-typedef int (*usbd_control_callback)(struct usb_setup_data *req, u8 **buf,
- u16 *len, void (**complete)(struct usb_setup_data *req));
+extern void usbd_set_control_buffer_size(usbd_device *usbd_dev, u16 size);
+
+extern void usbd_register_reset_callback(usbd_device *usbd_dev,
+ void (*callback)(void));
+extern void usbd_register_suspend_callback(usbd_device *usbd_dev,
+ void (*callback)(void));
+extern void usbd_register_resume_callback(usbd_device *usbd_dev,
+ void (*callback)(void));
+extern void usbd_register_sof_callback(usbd_device *usbd_dev,
+ void (*callback)(void));
+
+typedef int (*usbd_control_callback)(usbd_device *usbd_dev,
+ struct usb_setup_data *req, u8 **buf, u16 *len,
+ void (**complete)(usbd_device *usbd_dev,
+ struct usb_setup_data *req));
/* <usb_control.c> */
-extern int usbd_register_control_callback(u8 type, u8 type_mask,
- usbd_control_callback callback);
+extern int usbd_register_control_callback(usbd_device *usbd_dev, u8 type,
+ u8 type_mask,
+ usbd_control_callback callback);
/* <usb_standard.c> */
-extern void usbd_register_set_config_callback(void (*callback)(u16 wValue));
+extern void usbd_register_set_config_callback(usbd_device *usbd_dev,
+ void (*callback)(usbd_device *usbd_dev, u16 wValue));
/* Functions to be provided by the hardware abstraction layer */
-extern void usbd_poll(void);
-extern void usbd_disconnect(bool disconnected);
+extern void usbd_poll(usbd_device *usbd_dev);
+extern void usbd_disconnect(usbd_device *usbd_dev, bool disconnected);
-extern void usbd_ep_setup(u8 addr, u8 type, u16 max_size,
- void (*callback)(u8 ep));
+extern void usbd_ep_setup(usbd_device *usbd_dev, u8 addr, u8 type, u16 max_size,
+ void (*callback)(usbd_device *usbd_dev, u8 ep));
-extern u16 usbd_ep_write_packet(u8 addr, const void *buf, u16 len);
+extern u16 usbd_ep_write_packet(usbd_device *usbd_dev, u8 addr,
+ const void *buf, u16 len);
-extern u16 usbd_ep_read_packet(u8 addr, void *buf, u16 len);
+extern u16 usbd_ep_read_packet(usbd_device *usbd_dev, u8 addr,
+ void *buf, u16 len);
-extern void usbd_ep_stall_set(u8 addr, u8 stall);
-extern u8 usbd_ep_stall_get(u8 addr);
+extern void usbd_ep_stall_set(usbd_device *usbd_dev, u8 addr, u8 stall);
+extern u8 usbd_ep_stall_get(usbd_device *usbd_dev, u8 addr);
-extern void usbd_ep_nak_set(u8 addr, u8 nak);
+extern void usbd_ep_nak_set(usbd_device *usbd_dev, u8 addr, u8 nak);
/* Optional */
-extern void usbd_cable_connect(u8 on);
+extern void usbd_cable_connect(usbd_device *usbd_dev, u8 on);
END_DECLS
diff --git a/include/libopencm3/usb/usbstd.h b/include/libopencm3/usb/usbstd.h
index 8610fdb..5b1cea4 100644
--- a/include/libopencm3/usb/usbstd.h
+++ b/include/libopencm3/usb/usbstd.h
@@ -38,6 +38,9 @@ struct usb_setup_data {
u16 wLength;
} __attribute__((packed));
+/* Class Definition */
+#define USB_CLASS_VENDOR 0xFF
+
/* bmRequestType bit definitions */
#define USB_REQ_TYPE_IN 0x80
#define USB_REQ_TYPE_STANDARD 0x00