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-rw-r--r--include/libopencm3/stm32_common/can.h642
-rw-r--r--include/libopencm3/stm32_common/crc.h52
-rw-r--r--include/libopencm3/stm32_common/dbgmcu.h60
-rw-r--r--include/libopencm3/stm32_common/exti.h70
-rw-r--r--include/libopencm3/stm32_common/fsmc.h284
-rw-r--r--include/libopencm3/stm32_common/iwdg.h75
-rw-r--r--include/libopencm3/stm32_common/wwdg.h74
7 files changed, 1257 insertions, 0 deletions
diff --git a/include/libopencm3/stm32_common/can.h b/include/libopencm3/stm32_common/can.h
new file mode 100644
index 0000000..1aa95a1
--- /dev/null
+++ b/include/libopencm3/stm32_common/can.h
@@ -0,0 +1,642 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_CAN_H
+#define LIBOPENCM3_CAN_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/* --- Convenience macros -------------------------------------------------- */
+
+/* CAN register base adresses (for convenience) */
+#define CAN1 BX_CAN1_BASE
+#define CAN2 BX_CAN2_BASE
+
+/* --- CAN registers ------------------------------------------------------- */
+
+/* CAN master control register (CAN_MCR) */
+#define CAN_MCR(can_base) MMIO32(can_base + 0x000)
+/* CAN master status register (CAN_MSR) */
+#define CAN_MSR(can_base) MMIO32(can_base + 0x004)
+/* CAN transmit status register (CAN_TSR) */
+#define CAN_TSR(can_base) MMIO32(can_base + 0x008)
+
+/* CAN receive FIFO 0 register (CAN_RF0R) */
+#define CAN_RF0R(can_base) MMIO32(can_base + 0x00C)
+/* CAN receive FIFO 1 register (CAN_RF1R) */
+#define CAN_RF1R(can_base) MMIO32(can_base + 0x010)
+
+/* CAN interrupt enable register (CAN_IER) */
+#define CAN_IER(can_base) MMIO32(can_base + 0x014)
+/* CAN error status register (CAN_ESR) */
+#define CAN_ESR(can_base) MMIO32(can_base + 0x018)
+/* CAN bit timing register (CAN_BTR) */
+#define CAN_BTR(can_base) MMIO32(can_base + 0x01C)
+
+/* Registers in the offset range 0x020 to 0x17F are reserved. */
+
+/* --- CAN mailbox registers ----------------------------------------------- */
+
+/* CAN mailbox / FIFO register offsets */
+#define CAN_MBOX0 0x180
+#define CAN_MBOX1 0x190
+#define CAN_MBOX2 0x1A0
+#define CAN_FIFO0 0x1B0
+#define CAN_FIFO1 0x1C0
+
+/* CAN TX mailbox identifier register (CAN_TIxR) */
+#define CAN_TIxR(can_base, mbox) MMIO32(can_base + mbox + 0x0)
+#define CAN_TI0R(can_base) CAN_TIxR(can_base, CAN_MBOX0)
+#define CAN_TI1R(can_base) CAN_TIxR(can_base, CAN_MBOX1)
+#define CAN_TI2R(can_base) CAN_TIxR(can_base, CAN_MBOX2)
+
+/* CAN mailbox data length control and time stamp register (CAN_TDTxR) */
+#define CAN_TDTxR(can_base, mbox) MMIO32(can_base + mbox + 0x4)
+#define CAN_TDT0R(can_base) CAN_TDTxR(can_base, CAN_MBOX0)
+#define CAN_TDT1R(can_base) CAN_TDTxR(can_base, CAN_MBOX1)
+#define CAN_TDT2R(can_base) CAN_TDTxR(can_base, CAN_MBOX2)
+
+/* CAN mailbox data low register (CAN_TDLxR) */
+#define CAN_TDLxR(can_base, mbox) MMIO32(can_base + mbox + 0x8)
+#define CAN_TDL0R(can_base) CAN_TDLxR(can_base, CAN_MBOX0)
+#define CAN_TDL1R(can_base) CAN_TDLxR(can_base, CAN_MBOX1)
+#define CAN_TDL2R(can_base) CAN_TDLxR(can_base, CAN_MBOX2)
+
+/* CAN mailbox data high register (CAN_TDHxR) */
+#define CAN_TDHxR(can_base, mbox) MMIO32(can_base + mbox + 0xC)
+#define CAN_TDH0R(can_base) CAN_TDHxR(can_base, CAN_MBOX0)
+#define CAN_TDH1R(can_base) CAN_TDHxR(can_base, CAN_MBOX1)
+#define CAN_TDH2R(can_base) CAN_TDHxR(can_base, CAN_MBOX2)
+
+/* CAN RX FIFO identifier register (CAN_RIxR) */
+#define CAN_RIxR(can_base, fifo) MMIO32(can_base + fifo + 0x0)
+#define CAN_RI0R(can_base) CAN_RIxR(can_base, CAN_FIFO0)
+#define CAN_RI1R(can_base) CAN_RIxR(can_base, CAN_FIFO1)
+
+/* CAN RX FIFO mailbox data length control & time stamp register (CAN_RDTxR) */
+#define CAN_RDTxR(can_base, fifo) MMIO32(can_base + fifo + 0x4)
+#define CAN_RDT0R(can_base) CAN_RDTxR(can_base, CAN_FIFO0)
+#define CAN_RDT1R(can_base) CAN_RDTxR(can_base, CAN_FIFO1)
+
+/* CAN RX FIFO mailbox data low register (CAN_RDLxR) */
+#define CAN_RDLxR(can_base, fifo) MMIO32(can_base + fifo + 0x8)
+#define CAN_RDL0R(can_base) CAN_RDLxR(can_base, CAN_FIFO0)
+#define CAN_RDL1R(can_base) CAN_RDLxR(can_base, CAN_FIFO1)
+
+/* CAN RX FIFO mailbox data high register (CAN_RDHxR) */
+#define CAN_RDHxR(can_base, fifo) MMIO32(can_base + fifo + 0xC)
+#define CAN_RDH0R(can_base) CAN_RDHxR(can_base, CAN_FIFO0)
+#define CAN_RDH1R(can_base) CAN_RDHxR(can_base, CAN_FIFO1)
+
+/* --- CAN filter registers ------------------------------------------------ */
+
+/* CAN filter master register (CAN_FMR) */
+#define CAN_FMR(can_base) MMIO32(can_base + 0x200)
+
+/* CAN filter mode register (CAN_FM1R) */
+#define CAN_FM1R(can_base) MMIO32(can_base + 0x204)
+
+/* Register offset 0x208 is reserved. */
+
+/* CAN filter scale register (CAN_FS1R) */
+#define CAN_FS1R(can_base) MMIO32(can_base + 0x20C)
+
+/* Register offset 0x210 is reserved. */
+
+/* CAN filter FIFO assignement register (CAN_FFA1R) */
+#define CAN_FFA1R(can_base) MMIO32(can_base + 0x214)
+
+/* Register offset 0x218 is reserved. */
+
+/* CAN filter activation register (CAN_FA1R) */
+#define CAN_FA1R(can_base) MMIO32(can_base + 0x21C)
+
+/* Register offset 0x220 is reserved. */
+
+/* Registers with offset 0x224 to 0x23F are reserved. */
+
+/* CAN filter bank registers (CAN_FiRx) */
+/*
+ * Connectivity line devices have 28 banks so the bank ID spans 0..27
+ * all other devices have 14 banks so the bank ID spans 0..13.
+ */
+#define CAN_FiR1(can_base, bank) MMIO32(can_base + 0x240 + (bank * 0x8) + 0x0)
+#define CAN_FiR2(can_base, bank) MMIO32(can_base + 0x240 + (bank * 0x8) + 0x4)
+
+/* --- CAN_MCR values ------------------------------------------------------ */
+
+/* 31:17 Reserved, forced by hardware to 0 */
+
+/* DBF: Debug freeze */
+#define CAN_MCR_DBF (1 << 16)
+
+/* RESET: bxCAN software master reset */
+#define CAN_MCR_RESET (1 << 15)
+
+/* 14:8 Reserved, forced by hardware to 0 */
+
+/* TTCM: Time triggered communication mode */
+#define CAN_MCR_TTCM (1 << 7)
+
+/* ABOM: Automatic bus-off management */
+#define CAN_MCR_ABOM (1 << 6)
+
+/* AWUM: Automatic wakeup mode */
+#define CAN_MCR_AWUM (1 << 5)
+
+/* NART: No automatic retransmission */
+#define CAN_MCR_NART (1 << 4)
+
+/* RFLM: Receive FIFO locked mode */
+#define CAN_MCR_RFLM (1 << 3)
+
+/* TXFP: Transmit FIFO priority */
+#define CAN_MCR_TXFP (1 << 2)
+
+/* SLEEP: Sleep mode request */
+#define CAN_MCR_SLEEP (1 << 1)
+
+/* INRQ: Initialization request */
+#define CAN_MCR_INRQ (1 << 0)
+
+/* --- CAN_MSR values ------------------------------------------------------ */
+
+/* 31:12 Reserved, forced by hardware to 0 */
+
+/* RX: CAN Rx signal */
+#define CAN_MSR_RX (1 << 11)
+
+/* SAMP: Last sample point */
+#define CAN_MSR_SAMP (1 << 10)
+
+/* RXM: Receive mode */
+#define CAN_MSR_RXM (1 << 9)
+
+/* TXM: Transmit mode */
+#define CAN_MSR_TXM (1 << 8)
+
+/* 7:5 Reserved, forced by hardware to 0 */
+
+/* SLAKI: Sleep acknowledge interrupt */
+#define CAN_MSR_SLAKI (1 << 4)
+
+/* WKUI: Wakeup interrupt */
+#define CAN_MSR_WKUI (1 << 3)
+
+/* ERRI: Error interrupt */
+#define CAN_MSR_ERRI (1 << 2)
+
+/* SLAK: Sleep acknowledge */
+#define CAN_MSR_SLAK (1 << 1)
+
+/* INAK: Initialization acknowledge */
+#define CAN_MSR_INAK (1 << 0)
+
+/* --- CAN_TSR values ------------------------------------------------------ */
+
+/* LOW2: Lowest priority flag for mailbox 2 */
+#define CAN_TSR_LOW2 (1 << 31)
+
+/* LOW1: Lowest priority flag for mailbox 1 */
+#define CAN_TSR_LOW1 (1 << 30)
+
+/* LOW0: Lowest priority flag for mailbox 0 */
+#define CAN_TSR_LOW0 (1 << 29)
+
+/* TME2: Transmit mailbox 2 empty */
+#define CAN_TSR_TME2 (1 << 28)
+
+/* TME1: Transmit mailbox 1 empty */
+#define CAN_TSR_TME1 (1 << 27)
+
+/* TME0: Transmit mailbox 0 empty */
+#define CAN_TSR_TME0 (1 << 26)
+
+/* CODE[1:0]: Mailbox code */
+#define CAN_TSR_CODE_MASK (0x3 << 24)
+
+/* ABRQ2: Abort request for mailbox 2 */
+#define CAN_TSR_TABRQ2 (1 << 23)
+
+/* 22:20 Reserved, forced by hardware to 0 */
+
+/* TERR2: Transmission error for mailbox 2 */
+#define CAN_TSR_TERR2 (1 << 19)
+
+/* ALST2: Arbitration lost for mailbox 2 */
+#define CAN_TSR_ALST2 (1 << 18)
+
+/* TXOK2: Transmission OK for mailbox 2 */
+#define CAN_TSR_TXOK2 (1 << 17)
+
+/* RQCP2: Request completed mailbox 2 */
+#define CAN_TSR_RQCP2 (1 << 16)
+
+/* ABRQ1: Abort request for mailbox 1 */
+#define CAN_TSR_ABRQ1 (1 << 15)
+
+/* 14:12 Reserved, forced by hardware to 0 */
+
+/* TERR1: Transmission error for mailbox 1 */
+#define CAN_TSR_TERR1 (1 << 11)
+
+/* ALST1: Arbitration lost for mailbox 1 */
+#define CAN_TSR_ALST1 (1 << 10)
+
+/* TXOK1: Transmission OK for mailbox 1 */
+#define CAN_TSR_TXOK1 (1 << 9)
+
+/* RQCP1: Request completed mailbox 1 */
+#define CAN_TSR_RQCP1 (1 << 8)
+
+/* ABRQ0: Abort request for mailbox 0 */
+#define CAN_TSR_ABRQ0 (1 << 7)
+
+/* 6:4 Reserved, forced by hardware to 0 */
+
+/* TERR0: Transmission error for mailbox 0 */
+#define CAN_TSR_TERR0 (1 << 3)
+
+/* ALST0: Arbitration lost for mailbox 0 */
+#define CAN_TSR_ALST0 (1 << 2)
+
+/* TXOK0: Transmission OK for mailbox 0 */
+#define CAN_TSR_TXOK0 (1 << 1)
+
+/* RQCP0: Request completed mailbox 0 */
+#define CAN_TSR_RQCP0 (1 << 0)
+
+/* --- CAN_RF0R values ----------------------------------------------------- */
+
+/* 31:6 Reserved, forced by hardware to 0 */
+
+/* RFOM0: Release FIFO 0 output mailbox */
+#define CAN_RF0R_RFOM0 (1 << 5)
+
+/* FOVR0: FIFO 0 overrun */
+#define CAN_RF0R_FAVR0 (1 << 4)
+
+/* FULL0: FIFO 0 full */
+#define CAN_RF0R_FULL0 (1 << 3)
+
+/* 2 Reserved, forced by hardware to 0 */
+
+/* FMP0[1:0]: FIFO 0 message pending */
+#define CAN_RF0R_FMP0_MASK (0x3 << 0)
+
+/* --- CAN_RF1R values ----------------------------------------------------- */
+
+/* 31:6 Reserved, forced by hardware to 0 */
+
+/* RFOM1: Release FIFO 1 output mailbox */
+#define CAN_RF1R_RFOM1 (1 << 5)
+
+/* FOVR1: FIFO 1 overrun */
+#define CAN_RF1R_FAVR1 (1 << 4)
+
+/* FULL1: FIFO 1 full */
+#define CAN_RF1R_FULL1 (1 << 3)
+
+/* 2 Reserved, forced by hardware to 0 */
+
+/* FMP1[1:0]: FIFO 1 message pending */
+#define CAN_RF1R_FMP1_MASK (0x3 << 0)
+
+/* --- CAN_IER values ------------------------------------------------------ */
+
+/* 32:18 Reserved, forced by hardware to 0 */
+
+/* SLKIE: Sleep interrupt enable */
+#define CAN_IER_SLKIE (1 << 17)
+
+/* WKUIE: Wakeup interrupt enable */
+#define CAN_IER_WKUIE (1 << 16)
+
+/* ERRIE: Error interrupt enable */
+#define CAN_IER_ERRIE (1 << 15)
+
+/* 14:12 Reserved, forced by hardware to 0 */
+
+/* LECIE: Last error code interrupt enable */
+#define CAN_IER_LECIE (1 << 11)
+
+/* BOFIE: Bus-off interrupt enable */
+#define CAN_IER_BOFIE (1 << 10)
+
+/* EPVIE: Error passive interrupt enable */
+#define CAN_IER_EPVIE (1 << 9)
+
+/* EWGIE: Error warning interrupt enable */
+#define CAN_IER_EWGIE (1 << 8)
+
+/* 7 Reserved, forced by hardware to 0 */
+
+/* FOVIE1: FIFO overrun interrupt enable */
+#define CAN_IER_FOVIE1 (1 << 6)
+
+/* FFIE1: FIFO full interrupt enable */
+#define CAN_IER_FFIE1 (1 << 5)
+
+/* FMPIE1: FIFO message pending interrupt enable */
+#define CAN_IER_FMPIE1 (1 << 4)
+
+/* FOVIE0: FIFO overrun interrupt enable */
+#define CAN_IER_FOVIE0 (1 << 3)
+
+/* FFIE0: FIFO full interrupt enable */
+#define CAN_IER_FFIE0 (1 << 2)
+
+/* FMPIE0: FIFO message pending interrupt enable */
+#define CAN_IER_FMPIE0 (1 << 1)
+
+/* TMEIE: Transmit mailbox empty interrupt enable */
+#define CAN_IER_TMEIE (1 << 0)
+
+/* --- CAN_ESR values ------------------------------------------------------ */
+
+/* REC[7:0]: Receive error counter */
+#define CAN_ESR_REC_MASK (0xF << 24)
+
+/* TEC[7:0]: Least significant byte of the 9-bit transmit error counter */
+#define CAN_ESR_TEC_MASK (0xF << 16)
+
+/* 15:7 Reserved, forced by hardware to 0 */
+
+/* LEC[2:0]: Last error code */
+#define CAN_ESR_LEC_NO_ERROR (0x0 << 4)
+#define CAN_ESR_LEC_STUFF_ERROR (0x1 << 4)
+#define CAN_ESR_LEC_FORM_ERROR (0x2 << 4)
+#define CAN_ESR_LEC_ACK_ERROR (0x3 << 4)
+#define CAN_ESR_LEC_REC_ERROR (0x4 << 4)
+#define CAN_ESR_LEC_DOM_ERROR (0x5 << 4)
+#define CAN_ESR_LEC_CRC_ERROR (0x6 << 4)
+#define CAN_ESR_LEC_SOFT_ERROR (0x7 << 4)
+#define CAN_ESR_LEC_MASK (0x7 << 4)
+
+/* 3 Reserved, forced by hardware to 0 */
+
+/* BOFF: Bus-off flag */
+#define CAN_ESR_BOFF (1 << 2)
+
+/* EPVF: Error passive flag */
+#define CAN_ESR_EPVF (1 << 1)
+
+/* EWGF: Error warning flag */
+#define CAN_ESR_EWGF (1 << 0)
+
+/* --- CAN_BTR values ------------------------------------------------------ */
+
+/* SILM: Silent mode (debug) */
+#define CAN_BTR_SILM (1 << 31)
+
+/* LBKM: Loop back mode (debug) */
+#define CAN_BTR_LBKM (1 << 30)
+
+/* 29:26 Reserved, forced by hardware to 0 */
+
+/* SJW[1:0]: Resynchronization jump width */
+#define CAN_BTR_SJW_1TQ (0x0 << 24)
+#define CAN_BTR_SJW_2TQ (0x1 << 24)
+#define CAN_BTR_SJW_3TQ (0x2 << 24)
+#define CAN_BTR_SJW_4TQ (0x3 << 24)
+#define CAN_BTR_SJW_MASK (0x3 << 24)
+
+/* 23 Reserved, forced by hardware to 0 */
+
+/* TS2[2:0]: Time segment 2 */
+#define CAN_BTR_TS2_1TQ (0x0 << 20)
+#define CAN_BTR_TS2_2TQ (0x1 << 20)
+#define CAN_BTR_TS2_3TQ (0x2 << 20)
+#define CAN_BTR_TS2_4TQ (0x3 << 20)
+#define CAN_BTR_TS2_5TQ (0x4 << 20)
+#define CAN_BTR_TS2_6TQ (0x5 << 20)
+#define CAN_BTR_TS2_7TQ (0x6 << 20)
+#define CAN_BTR_TS2_8TQ (0x7 << 20)
+#define CAN_BTR_TS2_MASK (0x7 << 20)
+
+/* TS1[3:0]: Time segment 1 */
+#define CAN_BTR_TS1_1TQ (0x0 << 16)
+#define CAN_BTR_TS1_2TQ (0x1 << 16)
+#define CAN_BTR_TS1_3TQ (0x2 << 16)
+#define CAN_BTR_TS1_4TQ (0x3 << 16)
+#define CAN_BTR_TS1_5TQ (0x4 << 16)
+#define CAN_BTR_TS1_6TQ (0x5 << 16)
+#define CAN_BTR_TS1_7TQ (0x6 << 16)
+#define CAN_BTR_TS1_8TQ (0x7 << 16)
+#define CAN_BTR_TS1_9TQ (0x8 << 16)
+#define CAN_BTR_TS1_10TQ (0x9 << 16)
+#define CAN_BTR_TS1_11TQ (0xA << 16)
+#define CAN_BTR_TS1_12TQ (0xB << 16)
+#define CAN_BTR_TS1_13TQ (0xC << 16)
+#define CAN_BTR_TS1_14TQ (0xD << 16)
+#define CAN_BTR_TS1_15TQ (0xE << 16)
+#define CAN_BTR_TS1_16TQ (0xF << 16)
+#define CAN_BTR_TS1_MASK (0xF << 16)
+
+/* 15:10 Reserved, forced by hardware to 0 */
+
+/* BRP[9:0]: Baud rate prescaler */
+#define CAN_BTR_BRP_MASK (0x1FF << 0)
+
+/* --- CAN_TIxR values ------------------------------------------------------ */
+
+/* STID[10:0]: Standard identifier */
+#define CAN_TIxR_STID_MASK (0x3FF << 21)
+#define CAN_TIxR_STID_SHIFT 21
+
+/* EXID[15:0]: Extended identifier */
+#define CAN_TIxR_EXID_MASK (0x1FFFFFF << 3)
+#define CAN_TIxR_EXID_SHIFT 3
+
+/* IDE: Identifier extension */
+#define CAN_TIxR_IDE (1 << 2)
+
+/* RTR: Remote transmission request */
+#define CAN_TIxR_RTR (1 << 1)
+
+/* TXRQ: Transmit mailbox request */
+#define CAN_TIxR_TXRQ (1 << 0)
+
+/* --- CAN_TDTxR values ----------------------------------------------------- */
+
+/* TIME[15:0]: Message time stamp */
+#define CAN_TDTxR_TIME_MASK (0xFFFF << 15)
+#define CAN_TDTxR_TIME_SHIFT 15
+
+/* 15:6 Reserved, forced by hardware to 0 */
+
+/* TGT: Transmit global time */
+#define CAN_TDTxR_TGT (1 << 5)
+
+/* 7:4 Reserved, forced by hardware to 0 */
+
+/* DLC[3:0]: Data length code */
+#define CAN_TDTxR_DLC_MASK (0xF << 0)
+#define CAN_TDTxR_DLC_SHIFT 0
+
+/* --- CAN_TDLxR values ----------------------------------------------------- */
+
+/* DATA3[7:0]: Data byte 3 */
+/* DATA2[7:0]: Data byte 2 */
+/* DATA1[7:0]: Data byte 1 */
+/* DATA0[7:0]: Data byte 0 */
+
+/* --- CAN_TDHxR values ----------------------------------------------------- */
+
+/* DATA7[7:0]: Data byte 7 */
+/* DATA6[7:0]: Data byte 6 */
+/* DATA5[7:0]: Data byte 5 */
+/* DATA4[7:0]: Data byte 4 */
+
+/* --- CAN_RIxR values ------------------------------------------------------ */
+
+/* STID[10:0]: Standard identifier */
+#define CAN_RIxR_STID_MASK (0x3FF << 21)
+#define CAN_RIxR_STID_SHIFT 21
+
+/* EXID[15:0]: Extended identifier */
+#define CAN_RIxR_EXID_MASK (0x1FFFFFF << 3)
+#define CAN_RIxR_EXID_SHIFT 3
+
+/* IDE: Identifier extension */
+#define CAN_RIxR_IDE (1 << 2)
+
+/* RTR: Remote transmission request */
+#define CAN_RIxR_RTR (1 << 1)
+
+/* 0 Reserved */
+
+/* --- CAN_RDTxR values ----------------------------------------------------- */
+
+/* TIME[15:0]: Message time stamp */
+#define CAN_RDTxR_TIME_MASK (0xFFFF << 15)
+#define CAN_RDTxR_TIME_SHIFT 15
+
+/* FMI[7:0]: Filter match index */
+#define CAN_RDTxR_FMI_MASK (0xFF << 8)
+#define CAN_RDTxR_FMI_SHIFT 8
+
+/* 7:4 Reserved, forced by hardware to 0 */
+
+/* DLC[3:0]: Data length code */
+#define CAN_RDTxR_DLC_MASK (0xF << 0)
+#define CAN_RDTxR_DLC_SHIFT 0
+
+/* --- CAN_RDLxR values ----------------------------------------------------- */
+
+/* DATA3[7:0]: Data byte 3 */
+/* DATA2[7:0]: Data byte 2 */
+/* DATA1[7:0]: Data byte 1 */
+/* DATA0[7:0]: Data byte 0 */
+
+/* --- CAN_RDHxR values ----------------------------------------------------- */
+
+/* DATA7[7:0]: Data byte 7 */
+/* DATA6[7:0]: Data byte 6 */
+/* DATA5[7:0]: Data byte 5 */
+/* DATA4[7:0]: Data byte 4 */
+
+/* --- CAN_FMR values ------------------------------------------------------- */
+
+/* 31:14 Reserved, forced to reset value */
+
+/*
+ * CAN2SB[5:0]: CAN2 start bank
+ * (only on connectivity line devices otherwise reserved)
+ */
+#define CAN_FMR_CAN2SB_MASK (0x3F << 8)
+#define CAN_FMR_CAN2SB_SHIFT 15
+
+/* 7:1 Reserved, forced to reset value */
+
+/* FINIT: Filter init mode */
+#define CAN_FMR_FINIT (1 << 0)
+
+/* --- CAN_FM1R values ------------------------------------------------------ */
+
+/* 31:28 Reserved, forced by hardware to 0 */
+
+/*
+ * FBMx: Filter mode
+ * x is 0..27 should be calculated by a helper function making so many macros
+ * seems like an overkill?
+ */
+
+/* --- CAN_FS1R values ------------------------------------------------------ */
+
+/* 31:28 Reserved, forced by hardware to 0 */
+
+/*
+ * FSCx: Filter scale configuration
+ * x is 0..27 should be calculated by a helper function making so many macros
+ * seems like an overkill?
+ */
+
+/* --- CAN_FFA1R values ----------------------------------------------------- */
+
+/* 31:28 Reserved, forced by hardware to 0 */
+
+/*
+ * FFAx: Filter scale configuration
+ * x is 0..27 should be calculated by a helper function making so many macros
+ * seems like an overkill?
+ */
+
+/* --- CAN_FA1R values ------------------------------------------------------ */
+
+/* 31:28 Reserved, forced by hardware to 0 */
+
+/*
+ * FACTx: Filter active
+ * x is 0..27 should be calculated by a helper function making so many macros
+ * seems like an overkill?
+ */
+
+/* --- CAN_FiRx values ------------------------------------------------------ */
+
+/* FB[31:0]: Filter bits */
+
+/* --- CAN functions -------------------------------------------------------- */
+
+void can_reset(u32 canport);
+int can_init(u32 canport, bool ttcm, bool abom, bool awum, bool nart,
+ bool rflm, bool txfp, u32 sjw, u32 ts1, u32 ts2, u32 brp);
+
+void can_filter_init(u32 canport, u32 nr, bool scale_32bit, bool id_list_mode,
+ u32 fr1, u32 fr2, u32 fifo, bool enable);
+void can_filter_id_mask_16bit_init(u32 canport, u32 nr, u16 id1, u16 mask1,
+ u16 id2, u16 mask2, u32 fifo, bool enable);
+void can_filter_id_mask_32bit_init(u32 canport, u32 nr, u32 id, u32 mask,
+ u32 fifo, bool enable);
+void can_filter_id_list_16bit_init(u32 canport, u32 nr, u16 id1, u16 id2,
+ u16 id3, u16 id4, u32 fifo, bool enable);
+void can_filter_id_list_32bit_init(u32 canport, u32 nr, u32 id1, u32 id2,
+ u32 fifo, bool enable);
+
+void can_enable_irq(u32 canport, u32 irq);
+void can_disable_irq(u32 canport, u32 irq);
+
+int can_transmit(u32 canport, u32 id, bool ext, bool rtr, u8 length, u8 *data);
+void can_receive(u32 canport, u8 fifo, bool release, u32 *id, bool *ext,
+ bool *rtr, u32 *fmi, u8 *length, u8 *data);
+
+void can_fifo_release(u32 canport, u8 fifo);
+
+#endif
diff --git a/include/libopencm3/stm32_common/crc.h b/include/libopencm3/stm32_common/crc.h
new file mode 100644
index 0000000..5ad866e
--- /dev/null
+++ b/include/libopencm3/stm32_common/crc.h
@@ -0,0 +1,52 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_CRC_H
+#define LIBOPENCM3_CRC_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/* --- CRC registers ------------------------------------------------------- */
+
+/* Data register (CRC_DR) */
+#define CRC_DR MMIO32(CRC_BASE + 0x00)
+
+/* Independent data register (CRC_IDR) */
+#define CRC_IDR MMIO32(CRC_BASE + 0x04)
+
+/* Control register (CRC_CR) */
+#define CRC_CR MMIO32(CRC_BASE + 0x08)
+
+/* --- CRC_DR values ------------------------------------------------------- */
+
+/* Bits[31:0] Data register */
+
+/* --- CRC_IDR values ------------------------------------------------------ */
+
+/* Bits[7:0] General-purpose 8-bit data register bits */
+
+/* --- CRC_CR values ------------------------------------------------------- */
+
+/* RESET bit */
+#define CRC_CR_RESET (1 << 0)
+
+/* --- CRC function prototypes --------------------------------------------- */
+
+#endif
diff --git a/include/libopencm3/stm32_common/dbgmcu.h b/include/libopencm3/stm32_common/dbgmcu.h
new file mode 100644
index 0000000..e753f5e
--- /dev/null
+++ b/include/libopencm3/stm32_common/dbgmcu.h
@@ -0,0 +1,60 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_STM32_DBGMCU_H
+#define LIBOPENCM3_STM32_DBGMCU_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/* --- DBGMCU registers ---------------------------------------------------- */
+
+#define DBGMCU_IDCODE MMIO32(DBGMCU_BASE + 0x00)
+#define DBGMCU_CR MMIO32(DBGMCU_BASE + 0x04)
+
+/* DBGMCU_CR bits */
+#define DBGMCU_CR_SLEEP 0x00000001
+#define DBGMCU_CR_STOP 0x00000002
+#define DBGMCU_CR_STANDBY 0x00000004
+#define DBGMCU_CR_TRACE_IOEN 0x00000020
+#define DBGMCU_CR_TRACE_MODE_MASK 0x000000C0
+#define DBGMCU_CR_TRACE_MODE_ASYNC 0x00000000
+#define DBGMCU_CR_TRACE_MODE_SYNC_1 0x00000040
+#define DBGMCU_CR_TRACE_MODE_SYNC_2 0x00000080
+#define DBGMCU_CR_TRACE_MODE_SYNC_4 0x000000C0
+#define DBGMCU_CR_IWDG_STOP 0x00000100
+#define DBGMCU_CR_WWDG_STOP 0x00000200
+#define DBGMCU_CR_TIM1_STOP 0x00000400
+#define DBGMCU_CR_TIM2_STOP 0x00000800
+#define DBGMCU_CR_TIM3_STOP 0x00001000
+#define DBGMCU_CR_TIM4_STOP 0x00002000
+#define DBGMCU_CR_CAN1_STOP 0x00004000
+#define DBGMCU_CR_I2C1_SMBUS_TIMEOUT 0x00008000
+#define DBGMCU_CR_I2C2_SMBUS_TIMEOUT 0x00010000
+#define DBGMCU_CR_TIM8_STOP 0x00020000
+#define DBGMCU_CR_TIM5_STOP 0x00040000
+#define DBGMCU_CR_TIM6_STOP 0x00080000
+#define DBGMCU_CR_TIM7_STOP 0x00100000
+#define DBGMCU_CR_CAN2_STOP 0x00200000
+
+/* DBGMCU_IDCODE bits */
+#define DBGMCU_IDCODE_DEV_ID_MASK 0x00000fff
+#define DBGMCU_IDCODE_REV_ID_MASK 0xffff0000
+
+#endif
diff --git a/include/libopencm3/stm32_common/exti.h b/include/libopencm3/stm32_common/exti.h
new file mode 100644
index 0000000..19ab547
--- /dev/null
+++ b/include/libopencm3/stm32_common/exti.h
@@ -0,0 +1,70 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Mark Butler <mbutler@physics.otago.ac.nz>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_EXTI_H
+#define LIBOPENCM3_EXTI_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/* --- EXTI registers ------------------------------------------------------ */
+
+#define EXTI_IMR MMIO32(EXTI_BASE + 0x00)
+#define EXTI_EMR MMIO32(EXTI_BASE + 0x04)
+#define EXTI_RTSR MMIO32(EXTI_BASE + 0x08)
+#define EXTI_FTSR MMIO32(EXTI_BASE + 0x0c)
+#define EXTI_SWIER MMIO32(EXTI_BASE + 0x10)
+#define EXTI_PR MMIO32(EXTI_BASE + 0x14)
+
+/* EXTI number definitions */
+#define EXTI0 (1 << 0)
+#define EXTI1 (1 << 1)
+#define EXTI2 (1 << 2)
+#define EXTI3 (1 << 3)
+#define EXTI4 (1 << 4)
+#define EXTI5 (1 << 5)
+#define EXTI6 (1 << 6)
+#define EXTI7 (1 << 7)
+#define EXTI8 (1 << 8)
+#define EXTI9 (1 << 9)
+#define EXTI10 (1 << 10)
+#define EXTI11 (1 << 11)
+#define EXTI12 (1 << 12)
+#define EXTI13 (1 << 13)
+#define EXTI14 (1 << 14)
+#define EXTI15 (1 << 15)
+#define EXTI16 (1 << 16)
+#define EXTI17 (1 << 17)
+#define EXTI18 (1 << 18)
+#define EXTI19 (1 << 19)
+
+/* Trigger types */
+typedef enum trigger_e {
+ EXTI_TRIGGER_RISING,
+ EXTI_TRIGGER_FALLING,
+ EXTI_TRIGGER_BOTH,
+} exti_trigger_type;
+
+void exti_set_trigger(u32 extis, exti_trigger_type trig);
+void exti_enable_request(u32 extis);
+void exti_disable_request(u32 extis);
+void exti_reset_request(u32 extis);
+void exti_select_source(u32 exti, u32 gpioport);
+
+#endif
diff --git a/include/libopencm3/stm32_common/fsmc.h b/include/libopencm3/stm32_common/fsmc.h
new file mode 100644
index 0000000..1d318e3
--- /dev/null
+++ b/include/libopencm3/stm32_common/fsmc.h
@@ -0,0 +1,284 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_FSMC_H
+#define LIBOPENCM3_FSMC_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/* --- Convenience macros -------------------------------------------------- */
+
+/* TODO: Move to memorymap.h? */
+#define FSMC_BASE 0xa0000000
+
+#define FSMC_BANK1_BASE 0x60000000 /* NOR / PSRAM */
+#define FSMC_BANK2_BASE 0x70000000 /* NAND flash */
+#define FSMC_BANK3_BASE 0x80000000 /* NAND flash */
+#define FSMC_BANK4_BASE 0x90000000 /* PC card */
+
+/* --- FSMC registers ------------------------------------------------------ */
+
+/* SRAM/NOR-Flash chip-select control registers 1..4 (FSMC_BCRx) */
+#define FSMC_BCR(x) MMIO32(FSMC_BASE + 0x00 + 8 * x)
+#define FSMC_BCR1 FSMC_BCR(0)
+#define FSMC_BCR2 FSMC_BCR(1)
+#define FSMC_BCR3 FSMC_BCR(2)
+#define FSMC_BCR4 FSMC_BCR(3)
+
+/* SRAM/NOR-Flash chip-select timing registers 1..4 (FSMC_BTRx) */
+#define FSMC_BTR(x) MMIO32(FSMC_BASE + 0x04 + 8 * x)
+#define FSMC_BTR1 FSMC_BTR(0)
+#define FSMC_BTR2 FSMC_BTR(1)
+#define FSMC_BTR3 FSMC_BTR(2)
+#define FSMC_BTR4 FSMC_BTR(3)
+
+/* SRAM/NOR-Flash write timing registers 1..4 (FSMC_BWTRx) */
+#define FSMC_BWTR(x) MMIO32(FSMC_BASE + 0x104 + 8 * x)
+#define FSMC_BWTR1 FSMC_BWTR(0)
+#define FSMC_BWTR2 FSMC_BWTR(1)
+#define FSMC_BWTR3 FSMC_BWTR(2)
+#define FSMC_BWTR4 FSMC_BWTR(3)
+
+/* PC Card/NAND Flash control registers 2..4 (FSMC_PCRx) */
+#define FSMC_PCR(x) MMIO32(FSMC_BASE + 0x40 + 0x20 * x)
+#define FSMC_PCR2 FSMC_PCR(1)
+#define FSMC_PCR3 FSMC_PCR(2)
+#define FSMC_PCR4 FSMC_PCR(3)
+
+/* FIFO status and interrupt registers 2..4 (FSMC_SRx) */
+#define FSMC_SR(x) MMIO32(FSMC_BASE + 0x44 + 0x20 * x)
+#define FSMC_SR2 FSMC_SR(1)
+#define FSMC_SR3 FSMC_SR(2)
+#define FSMC_SR4 FSMC_SR(3)
+
+/* Common memory space timing registers 2..4 (FSMC_PMEMx) */
+#define FSMC_PMEM(x) MMIO32(FSMC_BASE + 0x48 + 0x20 * x)
+#define FSMC_PMEM2 FSMC_PMEM(1)
+#define FSMC_PMEM3 FSMC_PMEM(2)
+#define FSMC_PMEM4 FSMC_PMEM(3)
+
+/* Attribute memory space timing registers 2..4 (FSMC_PATTx) */
+#define FSMC_PATT(x) MMIO32(FSMC_BASE + 0x4c + 0x20 * x)
+#define FSMC_PATT2 FSMC_PATT(1)
+#define FSMC_PATT3 FSMC_PATT(2)
+#define FSMC_PATT4 FSMC_PATT(3)
+
+/* I/O space timing register 4 (FSMC_PIO4) */
+#define FSMC_PIO4 MMIO32(FSMC_BASE + 0xb0)
+
+/* ECC result registers 2/3 (FSMC_ECCRx) */
+#define FSMC_ECCR(x) MMIO32(FSMC_BASE + 0x54 + 0x20 * x)
+#define FSMC_ECCR2 FSMC_ECCR(1)
+#define FSMC_ECCR3 FSMC_ECCR(2)
+
+/* --- FSMC_BCRx values ---------------------------------------------------- */
+
+/* CBURSTRW: Write burst enable */
+#define FSMC_BCR_CBURSTRW (1 << 19)
+
+/* Bits 18..16: Reserved. */
+
+/* ASYNCWAIT: Wait signal during asynchronous transfers */
+#define FSMC_BCR_ASYNCWAIT (1 << 15)
+
+/* EXTMOD: Extended mode enable */
+#define FSMC_BCR_EXTMOD (1 << 14)
+
+/* WAITEN: Wait enable bit */
+#define FSMC_BCR_WAITEN (1 << 13)
+
+/* WREN: Write enable bit */
+#define FSMC_BCR_WREN (1 << 12)
+
+/* WAITCFG: Wait timing configuration */
+#define FSMC_BCR_WAITCFG (1 << 11)
+
+/* WRAPMOD: Wrapped burst mode support */
+#define FSMC_BCR_WRAPMOD (1 << 10)
+
+/* WAITPOL: Wait signal polarity bit */
+#define FSMC_BCR_WAITPOL (1 << 9)
+
+/* BURSTEN: Burst enable bit */
+#define FSMC_BCR_BURSTEN (1 << 8)
+
+/* Bit 7: Reserved. */
+
+/* FACCEN: Flash access enable */
+#define FSMC_BCR_FACCEN (1 << 6)
+
+/* MWID[5:4]: Memory databus width */
+#define FSMC_BCR_MWID (1 << 4)
+
+/* MTYP[3:2]: Memory type */
+#define FSMC_BCR_MTYP (1 << 2)
+
+/* MUXEN: Address/data multiplexing enable bit */
+#define FSMC_BCR_MUXEN (1 << 1)
+
+/* MBKEN: Memory bank enable bit */
+#define FSMC_BCR_MBKEN (1 << 0)
+
+/* --- FSMC_BTRx values ---------------------------------------------------- */
+
+/* ACCMOD[29:28]: Access mode */
+#define FSMC_BTR_ACCMOD (1 << 28)
+
+/* DATLAT[27:24]: Data latency (for synchronous burst NOR flash) */
+#define FSMC_BTR_DATLAT (1 << 24)
+
+/* CLKDIV[23:20]: Clock divide ratio (for CLK signal) */
+#define FSMC_BTR_CLKDIV (1 << 20)
+
+/* BUSTURN[19:16]: Bus turnaround phase duration */
+#define FSMC_BTR_BUSTURN (1 << 16)
+
+/* DATAST[15:8]: Data-phase duration */
+#define FSMC_BTR_DATAST (1 << 8)
+
+/* ADDHLD[7:4]: Address-hold phase duration */
+#define FSMC_BTR_ADDHLD (1 << 4)
+
+/* ADDSET[3:0]: Address setup phase duration */
+#define FSMC_BTR_ADDSET (1 << 0)
+
+/* --- FSMC_BWTRx values --------------------------------------------------- */
+
+/* ACCMOD[29:28]: Access mode */
+#define FSMC_BWTR_ACCMOD (1 << 28)
+
+/* DATLAT[27:24]: Data latency (for synchronous burst NOR Flash) */
+#define FSMC_BWTR_DATLAT (1 << 24)
+
+/* CLKDIV[23:20]: Clock divide ratio (for CLK signal) */
+#define FSMC_BWTR_CLKDIV (1 << 20)
+
+/* Bits 19..16: Reserved. */
+
+/* DATAST[15:8]: Data-phase duration */
+#define FSMC_BWTR_DATAST (1 << 8)
+
+/* ADDHLD[7:4]: Address-hold phase duration */
+#define FSMC_BWTR_ADDHLD (1 << 4)
+
+/* ADDSET[3:0]: Address setup phase duration */
+#define FSMC_BWTR_ADDSET (1 << 0)
+
+/* --- FSMC_PCRx values ---------------------------------------------------- */
+
+/* ECCPS[19:17]: ECC page size */
+#define FSMC_PCR_ECCPS (1 << 17)
+
+/* TAR[16:13]: ALE to RE delay */
+#define FSMC_PCR_TAR (1 << 13)
+
+/* TCLR[12:9]: CLE to RE delay */
+#define FSMC_PCR_TCLR (1 << 9)
+
+/* Bits 8..7: Reserved. */
+
+/* ECCEN: ECC computation logic enable bit */
+#define FSMC_PCR_ECCEN (1 << 6)
+
+/* PWID[5:4]: Databus width */
+#define FSMC_PCR_PWID (1 << 4)
+
+/* PTYP: Memory type */
+#define FSMC_PCR_PTYP (1 << 3)
+
+/* PBKEN: PC Card/NAND Flash memory bank enable bit */
+#define FSMC_PCR_PBKEN (1 << 2)
+
+/* PWAITEN: Wait feature enable bit */
+#define FSMC_PCR_PWAITEN (1 << 1)
+
+/* Bit 0: Reserved. */
+
+/* --- FSMC_SRx values ----------------------------------------------------- */
+
+/* FEMPT: FIFO empty */
+#define FSMC_SR_FEMPT (1 << 6)
+
+/* IFEN: Interrupt falling edge detection enable bit */
+#define FSMC_SR_IFEN (1 << 5)
+
+/* ILEN: Interrupt high-level detection enable bit */
+#define FSMC_SR_ILEN (1 << 4)
+
+/* IREN: Interrupt rising edge detection enable bit */
+#define FSMC_SR_IREN (1 << 3)
+
+/* IFS: Interrupt falling edge status */
+#define FSMC_SR_IFS (1 << 2)
+
+/* ILS: Interrupt high-level status */
+#define FSMC_SR_ILS (1 << 1)
+
+/* IRS: Interrupt rising edge status */
+#define FSMC_SR_IRS (1 << 0)
+
+/* --- FSMC_PMEMx values --------------------------------------------------- */
+
+/* MEMHIZx[31:24]: Common memory x databus HiZ time */
+#define FSMC_PMEM_MEMHIZX (1 << 24)
+
+/* MEMHOLDx[23:16]: Common memory x hold time */
+#define FSMC_PMEM_MEMHOLDX (1 << 16)
+
+/* MEMWAITx[15:8]: Common memory x wait time */
+#define FSMC_PMEM_MEMHOLDX (1 << 8)
+
+/* MEMSETx[7:0]: Common memory x setup time */
+#define FSMC_PMEM_MEMSETX (1 << 0)
+
+/* --- FSMC_PATTx values --------------------------------------------------- */
+
+/* ATTHIZx[31:24]: Attribute memory x databus HiZ time */
+#define FSMC_PATT_ATTHIZX (1 << 24)
+
+/* ATTHOLDx[23:16]: Attribute memory x hold time */
+#define FSMC_PATT_ATTHOLDX (1 << 16)
+
+/* ATTWAITx[15:8]: Attribute memory x wait time */
+#define FSMC_PATT_ATTWAITX (1 << 8)
+
+/* ATTSETx[7:0]: Attribute memory x setup time */
+#define FSMC_PATT_ATTSETX (1 << 0)
+
+/* --- FSMC_PIO4 values ---------------------------------------------------- */
+
+/* IOHIZx[31:24]: I/O x databus HiZ time */
+#define FSMC_PIO4_IOHIZX (1 << 24)
+
+/* IOHOLDx[23:16]: I/O x hold time */
+#define FSMC_PIO4_IOHOLDX (1 << 16)
+
+/* IOWAITx[15:8]: I/O x wait time */
+#define FSMC_PIO4_IOWAITX (1 << 8)
+
+/* IOSETx[7:0]: I/O x setup time */
+#define FSMC_PIO4_IOSETX (1 << 0)
+
+/* --- FSMC_ECCRx values --------------------------------------------------- */
+
+/* ECCx[31:0]: ECC result */
+#define FSMC_ECCR_ECCX (1 << 0)
+
+#endif
diff --git a/include/libopencm3/stm32_common/iwdg.h b/include/libopencm3/stm32_common/iwdg.h
new file mode 100644
index 0000000..bf2784a
--- /dev/null
+++ b/include/libopencm3/stm32_common/iwdg.h
@@ -0,0 +1,75 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_IWDG_H
+#define LIBOPENCM3_IWDG_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/* --- IWDG registers ------------------------------------------------------ */
+
+/* Key Register (IWDG_KR) */
+#define IWDG_KR MMIO32(IWDG_BASE + 0x00)
+
+/* Prescaler register (IWDG_PR) */
+#define IWDG_PR MMIO32(IWDG_BASE + 0x04)
+
+/* Reload register (IWDG_RLR) */
+#define IWDG_RLR MMIO32(IWDG_BASE + 0x08)
+
+/* Status register (IWDG_SR) */
+#define IWDG_SR MMIO32(IWDG_BASE + 0x0C)
+
+/* --- IWDG_KR values ------------------------------------------------------ */
+
+/* KEY[15:0]: Key value */
+#define IWDG_KR_RESET 0xAAAA
+#define IWDG_KR_UNLOCK 0x5555
+#define IWDG_KR_START 0xCCCC
+
+/* --- IWDG_PR values ------------------------------------------------------ */
+
+/* PR[2:0]: Prescaler divider */
+#define IWDG_PR_LSB 0
+#define IWDG_PR_DIV4 0x0
+#define IWDG_PR_DIV8 0x1
+#define IWDG_PR_DIV16 0x2
+#define IWDG_PR_DIV32 0x3
+#define IWDG_PR_DIV64 0x4
+#define IWDG_PR_DIV128 0x5
+#define IWDG_PR_DIV256 0x6
+/* Double definition: 0x06 and 0x07 both mean DIV256 as per datasheet. */
+/* #define IWDG_PR_DIV256 0x7 */
+
+/* --- IWDG_RLR values ----------------------------------------------------- */
+
+/* RL[11:0]: Watchdog counter reload value */
+
+/* --- IWDG_SR values ------------------------------------------------------ */
+
+/* RVU: Watchdog counter reload value update */
+#define IWDG_SR_RVU (1 << 1)
+
+/* PVU: Watchdog prescaler value update */
+#define IWDG_SR_PVU (1 << 0)
+
+/* --- IWDG funtion prototypes---------------------------------------------- */
+
+#endif
diff --git a/include/libopencm3/stm32_common/wwdg.h b/include/libopencm3/stm32_common/wwdg.h
new file mode 100644
index 0000000..552d02e
--- /dev/null
+++ b/include/libopencm3/stm32_common/wwdg.h
@@ -0,0 +1,74 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_WWDG_H
+#define LIBOPENCM3_WWDG_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/* --- WWDG registers ------------------------------------------------------ */
+
+/* Control register (WWDG_CR) */
+#define WWDG_CR MMIO32(WWDG_BASE + 0x00)
+
+/* Configuration register (WWDG_CFR) */
+#define WWDG_CFR MMIO32(WWDG_BASE + 0x04)
+
+/* Status register (WWDG_SR) */
+#define WWDG_SR MMIO32(WWDG_BASE + 0x08)
+
+/* --- WWDG_CR values ------------------------------------------------------ */
+
+/* WDGA: Activation bit */
+#define WWDG_CR_WDGA (1 << 7)
+
+/* T[6:0]: 7-bit counter (MSB to LSB) */
+#define WWDG_CR_T_LSB 0
+#define WWDG_CR_T0 (1 << 0)
+#define WWDG_CR_T1 (1 << 1)
+#define WWDG_CR_T2 (1 << 2)
+#define WWDG_CR_T3 (1 << 3)
+#define WWDG_CR_T4 (1 << 4)
+#define WWDG_CR_T5 (1 << 5)
+#define WWDG_CR_T6 (1 << 6)
+
+/* --- WWDG_CFR values ----------------------------------------------------- */
+
+/* EWI: Early wakeup interrupt */
+#define WWDG_CFR_EWI (1 << 9)
+
+/* WDGTB[8:7]: Timer base */
+#define WWDG_CFR_WDGTB_LSB 7
+#define WWDG_CFR_WDGTB_CK_DIV1 0x0
+#define WWDG_CFR_WDGTB_CK_DIV2 0x1
+#define WWDG_CFR_WDGTB_CK_DIV4 0x2
+#define WWDG_CFR_WDGTB_CK_DIV8 0x3
+
+/* W[6:0]: 7-bit window value */
+#define WWDG_CFG_W_LSB 0
+
+/* --- WWDG_SR values ------------------------------------------------------ */
+
+/* EWIF: Early wakeup interrupt flag */
+#define WWDG_SR_EWIF (1 << 0)
+
+/* --- WWDG funtion prototypes---------------------------------------------- */
+
+#endif