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-rw-r--r--include/libopencm3/stm32/crc.h14
-rw-r--r--include/libopencm3/stm32/f1/adc.h89
-rw-r--r--include/libopencm3/stm32/f4/rng.h61
-rw-r--r--include/libopencm3/stm32/f4/scb.h69
-rw-r--r--include/libopencm3/stm32/i2c.h38
-rw-r--r--include/libopencm3/stm32/spi.h62
-rw-r--r--include/libopencm3/stm32/timer.h28
-rw-r--r--include/libopencm3/stm32/usart.h83
8 files changed, 377 insertions, 67 deletions
diff --git a/include/libopencm3/stm32/crc.h b/include/libopencm3/stm32/crc.h
index 3848191..aa30182 100644
--- a/include/libopencm3/stm32/crc.h
+++ b/include/libopencm3/stm32/crc.h
@@ -1,3 +1,17 @@
+/** @defgroup crc_defines CRC Defines
+
+@brief <b>libopencm3 Defined Constants and Types for the STM32F CRC Generator </b>
+
+@ingroup STM32F_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
+
+@date 18 August 2012
+
+LGPL License Terms @ref lgpl_license
+ */
/*
* This file is part of the libopencm3 project.
*
diff --git a/include/libopencm3/stm32/f1/adc.h b/include/libopencm3/stm32/f1/adc.h
index 116aeaa..aa54bdf 100644
--- a/include/libopencm3/stm32/f1/adc.h
+++ b/include/libopencm3/stm32/f1/adc.h
@@ -252,7 +252,7 @@ LGPL License Terms @ref lgpl_license
#define ADC_CR1_DUALMOD_MASK (0xF << 16)
#define ADC_CR1_DUALMOD_SHIFT 16
-/* DISCNUM[2:0]: Discontinous mode channel count. */
+/* DISCNUM[2:0]: Discontinuous mode channel count. */
/****************************************************************************/
/** @defgroup adc_cr1_discnum ADC Number of channels in discontinuous mode.
@ingroup STM32F1xx_adc_defines
@@ -270,10 +270,10 @@ LGPL License Terms @ref lgpl_license
#define ADC_CR1_DISCNUM_MASK (0x7 << 13)
#define ADC_CR1_DISCNUM_SHIFT 13
-/* JDISCEN: */ /** Discontinous mode on injected channels. */
+/* JDISCEN: */ /** Discontinuous mode on injected channels. */
#define ADC_CR1_JDISCEN (1 << 12)
-/* DISCEN: */ /** Discontinous mode on regular channels. */
+/* DISCEN: */ /** Discontinuous mode on regular channels. */
#define ADC_CR1_DISCEN (1 << 11)
/* JAUTO: */ /** Automatic Injection Group conversion. */
@@ -557,7 +557,7 @@ LGPL License Terms @ref lgpl_license
/* --- ADC_SMPRx generic values -------------------------------------------- */
/****************************************************************************/
/* ADC_SMPRG ADC Sample Time Selection for Channels */
-/** @defgroup adc_sample_rg ADC Sample Time Selection Generic
+/** @defgroup adc_sample_rg ADC Sample Time Selection for All Channels
@ingroup STM32F1xx_adc_defines
@{*/
@@ -587,18 +587,11 @@ LGPL License Terms @ref lgpl_license
#define ADC_SQR1_SQ15_LSB 10
#define ADC_SQR1_SQ14_LSB 5
#define ADC_SQR1_SQ13_LSB 0
-#define ADC_SQR1_L_MSK (0xf << ADC_L_LSB)
-#define ADC_SQR1_SQ16_MSK (0x1f << ADC_SQ16_LSB)
-#define ADC_SQR1_SQ15_MSK (0x1f << ADC_SQ15_LSB)
-#define ADC_SQR1_SQ14_MSK (0x1f << ADC_SQ14_LSB)
-#define ADC_SQR1_SQ13_MSK (0x1f << ADC_SQ13_LSB)
-/* TODO Fix error
#define ADC_SQR1_L_MSK (0xf << ADC_SQR1_L_LSB)
#define ADC_SQR1_SQ16_MSK (0x1f << ADC_SQR1_SQ16_LSB)
#define ADC_SQR1_SQ15_MSK (0x1f << ADC_SQR1_SQ15_LSB)
#define ADC_SQR1_SQ14_MSK (0x1f << ADC_SQR1_SQ14_LSB)
#define ADC_SQR1_SQ13_MSK (0x1f << ADC_SQR1_SQ13_LSB)
-*/
/* --- ADC_SQR2 values ----------------------------------------------------- */
@@ -608,20 +601,12 @@ LGPL License Terms @ref lgpl_license
#define ADC_SQR2_SQ9_LSB 10
#define ADC_SQR2_SQ8_LSB 5
#define ADC_SQR2_SQ7_LSB 0
-#define ADC_SQR2_SQ12_MSK (0x1f << ADC_SQ12_LSB)
-#define ADC_SQR2_SQ11_MSK (0x1f << ADC_SQ11_LSB)
-#define ADC_SQR2_SQ10_MSK (0x1f << ADC_SQ10_LSB)
-#define ADC_SQR2_SQ9_MSK (0x1f << ADC_SQ9_LSB)
-#define ADC_SQR2_SQ8_MSK (0x1f << ADC_SQ8_LSB)
-#define ADC_SQR2_SQ7_MSK (0x1f << ADC_SQ7_LSB)
-/* TODO Fix error
#define ADC_SQR2_SQ12_MSK (0x1f << ADC_SQR2_SQ12_LSB)
#define ADC_SQR2_SQ11_MSK (0x1f << ADC_SQR2_SQ11_LSB)
#define ADC_SQR2_SQ10_MSK (0x1f << ADC_SQR2_SQ10_LSB)
#define ADC_SQR2_SQ9_MSK (0x1f << ADC_SQR2_SQ9_LSB)
#define ADC_SQR2_SQ8_MSK (0x1f << ADC_SQR2_SQ8_LSB)
#define ADC_SQR2_SQ7_MSK (0x1f << ADC_SQR2_SQ7_LSB)
-*/
/* --- ADC_SQR3 values ----------------------------------------------------- */
@@ -631,20 +616,12 @@ LGPL License Terms @ref lgpl_license
#define ADC_SQR3_SQ3_LSB 10
#define ADC_SQR3_SQ2_LSB 5
#define ADC_SQR3_SQ1_LSB 0
-#define ADC_SQR3_SQ6_MSK (0x1f << ADC_SQ6_LSB)
-#define ADC_SQR3_SQ5_MSK (0x1f << ADC_SQ5_LSB)
-#define ADC_SQR3_SQ4_MSK (0x1f << ADC_SQ4_LSB)
-#define ADC_SQR3_SQ3_MSK (0x1f << ADC_SQ3_LSB)
-#define ADC_SQR3_SQ2_MSK (0x1f << ADC_SQ2_LSB)
-#define ADC_SQR3_SQ1_MSK (0x1f << ADC_SQ1_LSB)
-/* TODO Fix error
#define ADC_SQR3_SQ6_MSK (0x1f << ADC_SQR3_SQ6_LSB)
#define ADC_SQR3_SQ5_MSK (0x1f << ADC_SQR3_SQ5_LSB)
#define ADC_SQR3_SQ4_MSK (0x1f << ADC_SQR3_SQ4_LSB)
#define ADC_SQR3_SQ3_MSK (0x1f << ADC_SQR3_SQ3_LSB)
#define ADC_SQR3_SQ2_MSK (0x1f << ADC_SQR3_SQ2_LSB)
#define ADC_SQR3_SQ1_MSK (0x1f << ADC_SQR3_SQ1_LSB)
-*/
/* --- ADC_JSQR values ----------------------------------------------------- */
#define ADC_JSQR_JL_LSB 20
@@ -652,18 +629,24 @@ LGPL License Terms @ref lgpl_license
#define ADC_JSQR_JSQ3_LSB 10
#define ADC_JSQR_JSQ2_LSB 5
#define ADC_JSQR_JSQ1_LSB 0
-#define ADC_JSQR_JL_MSK (0x2 << ADC_JL_LSB)
-#define ADC_JSQR_JSQ4_MSK (0x1f << ADC_JSQ4_LSB)
-#define ADC_JSQR_JSQ3_MSK (0x1f << ADC_JSQ3_LSB)
-#define ADC_JSQR_JSQ2_MSK (0x1f << ADC_JSQ2_LSB)
-#define ADC_JSQR_JSQ1_MSK (0x1f << ADC_JSQ1_LSB)
-/* TODO Fix error
+
+/* JL[2:0]: Discontinous mode channel count injected channels. */
+/****************************************************************************/
+/** @defgroup adc_jsqr_jl ADC Number of channels in discontinuous mode fro injected channels.
+@ingroup STM32F1xx_adc_defines
+
+@{*/
+#define ADC_JSQR_JL_1CHANNELS (0x0 << ADC_JSQR_JL_LSB)
+#define ADC_JSQR_JL_2CHANNELS (0x1 << ADC_JSQR_JL_LSB)
+#define ADC_JSQR_JL_3CHANNELS (0x2 << ADC_JSQR_JL_LSB)
+#define ADC_JSQR_JL_4CHANNELS (0x3 << ADC_JSQR_JL_LSB)
+/**@}*/
+#define ADC_JSQR_JL_SHIFT 13
#define ADC_JSQR_JL_MSK (0x2 << ADC_JSQR_JL_LSB)
#define ADC_JSQR_JSQ4_MSK (0x1f << ADC_JSQR_JSQ4_LSB)
#define ADC_JSQR_JSQ3_MSK (0x1f << ADC_JSQR_JSQ3_LSB)
#define ADC_JSQR_JSQ2_MSK (0x1f << ADC_JSQR_JSQ2_LSB)
#define ADC_JSQR_JSQ1_MSK (0x1f << ADC_JSQR_JSQ1_LSB)
-*/
/* --- ADC_JDRx, ADC_DR values --------------------------------------------- */
@@ -679,22 +662,31 @@ LGPL License Terms @ref lgpl_license
BEGIN_DECLS
+void adc_power_on(u32 adc);
+void adc_start_conversion_direct(u32 adc);
+void adc_set_single_channel(u32 adc, u8 channel);
+void adc_set_dual_mode(u32 mode);
+bool adc_eoc(u32 adc);
+bool adc_eoc_injected(u32 adc);
+u32 adc_read_regular(u32 adc);
+u32 adc_read_injected(u32 adc, u8 reg);
+void adc_set_injected_offset(u32 adc, u8 reg, u32 offset);
void adc_enable_analog_watchdog_regular(u32 adc);
void adc_disable_analog_watchdog_regular(u32 adc);
void adc_enable_analog_watchdog_injected(u32 adc);
void adc_disable_analog_watchdog_injected(u32 adc);
-void adc_enable_discontinous_mode_regular(u32 adc);
-void adc_disable_discontinous_mode_regular(u32 adc);
-void adc_enable_discontinous_mode_injected(u32 adc);
-void adc_disable_discontinous_mode_injected(u32 adc);
+void adc_enable_discontinuous_mode_regular(u32 adc, u8 length);
+void adc_disable_discontinuous_mode_regular(u32 adc);
+void adc_enable_discontinuous_mode_injected(u32 adc);
+void adc_disable_discontinuous_mode_injected(u32 adc);
void adc_enable_automatic_injected_group_conversion(u32 adc);
void adc_disable_automatic_injected_group_conversion(u32 adc);
void adc_enable_analog_watchdog_on_all_channels(u32 adc);
void adc_enable_analog_watchdog_on_selected_channel(u32 adc, u8 channel);
void adc_enable_scan_mode(u32 adc);
void adc_disable_scan_mode(u32 adc);
-void adc_enable_jeoc_interrupt(u32 adc);
-void adc_disable_jeoc_interrupt(u32 adc);
+void adc_enable_eoc_interrupt_injected(u32 adc);
+void adc_disable_eoc_interrupt_injected(u32 adc);
void adc_enable_awd_interrupt(u32 adc);
void adc_disable_awd_interrupt(u32 adc);
void adc_enable_eoc_interrupt(u32 adc);
@@ -713,17 +705,28 @@ void adc_enable_dma(u32 adc);
void adc_disable_dma(u32 adc);
void adc_reset_calibration(u32 adc);
void adc_calibration(u32 adc);
-void adc_set_continous_conversion_mode(u32 adc);
+void adc_set_continuous_conversion_mode(u32 adc);
void adc_set_single_conversion_mode(u32 adc);
+#ifdef __GNUC__
+void adc_on(u32 adc) __attribute__ ((deprecated ("will be removed in the first release")));
+#else
void adc_on(u32 adc);
+#endif
void adc_off(u32 adc);
-void adc_set_conversion_time(u32 adc, u8 channel, u8 time);
-void adc_set_conversion_time_on_all_channels(u32 adc, u8 time);
+void adc_set_sample_time(u32 adc, u8 channel, u8 time);
+void adc_set_sample_time_on_all_channels(u32 adc, u8 time);
void adc_set_watchdog_high_threshold(u32 adc, u16 threshold);
void adc_set_watchdog_low_threshold(u32 adc, u16 threshold);
void adc_set_regular_sequence(u32 adc, u8 length, u8 channel[]);
void adc_set_injected_sequence(u32 adc, u8 length, u8 channel[]);
+#ifdef __GNUC__
+void adc_set_continous_conversion_mode(u32 adc) __attribute__ ((deprecated ("change to adc_set_continuous_conversion_mode")));
+void adc_set_conversion_time(u32 adc, u8 channel, u8 time) __attribute__ ((deprecated ("change to adc_set_sample_time")));
+void adc_set_conversion_time_on_all_channels(u32 adc, u8 time) __attribute__ ((deprecated ("change to adc_set_sample_time_on_all_channels")));
+void adc_enable_jeoc_interrupt(u32 adc) __attribute__ ((deprecated ("change to adc_enable_eoc_interrupt_injected")));
+void adc_disable_jeoc_interrupt(u32 adc) __attribute__ ((deprecated ("change to adc_disable_eoc_interrupt_injected")));
+#endif
END_DECLS
#endif
diff --git a/include/libopencm3/stm32/f4/rng.h b/include/libopencm3/stm32/f4/rng.h
new file mode 100644
index 0000000..5f517c8
--- /dev/null
+++ b/include/libopencm3/stm32/f4/rng.h
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_RNG_H
+#define LIBOPENCM3_RNG_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/* --- Random number generator registers ----------------------------------- */
+
+/* Control register */
+#define RNG_CR MMIO32(RNG_BASE + 0x00)
+
+/* Status register */
+#define RNG_SR MMIO32(RNG_BASE + 0x04)
+
+/* Data register */
+#define RNG_DR MMIO32(RNG_BASE + 0x08)
+
+/* --- RNG_CR values ------------------------------------------------------- */
+
+/* RNG ENABLE */
+#define RNG_CR_EN (1 << 2)
+
+/* RNG interupt enable */
+#define RNG_CR_IE (1 << 3)
+
+/* --- RNG_SR values ------------------------------------------------------- */
+
+/* Data ready */
+#define RNG_SR_DRDY (1 << 0)
+
+/* Clock error current status */
+#define RNG_SR_CECS (1 << 1)
+
+/* Seed error current status */
+#define RNG_SR_SECS (1 << 2)
+
+/* Clock error interup status */
+#define RNG_SR_CEIS (1 << 5)
+
+/* Seed error interup status */
+#define RNG_SR_SEIS (1 << 6)
+
+#endif
diff --git a/include/libopencm3/stm32/f4/scb.h b/include/libopencm3/stm32/f4/scb.h
index 181aa7a..7187ca9 100644
--- a/include/libopencm3/stm32/f4/scb.h
+++ b/include/libopencm3/stm32/f4/scb.h
@@ -72,6 +72,63 @@
/* AFSR: Auxiliary Fault Status Register */
#define SCB_AFSR MMIO32(SCB_BASE + 0x3C)
+/* ID_PFR0: Processor Feature Register 0 */
+#define SCB_ID_PFR0 MMIO32(SCB_BASE + 0x40)
+
+/* ID_PFR1: Processor Feature Register 1 */
+#define SCB_ID_PFR1 MMIO32(SCB_BASE + 0x44)
+
+/* ID_DFR0: Debug Features Register 0 */
+#define SCB_ID_DFR0 MMIO32(SCB_BASE + 0x48)
+
+/* ID_AFR0: Auxiliary Features Register 0 */
+#define SCB_ID_AFR0 MMIO32(SCB_BASE + 0x4C)
+
+/* ID_MMFR0: Memory Model Feature Register 0 */
+#define SCB_ID_MMFR0 MMIO32(SCB_BASE + 0x50)
+
+/* ID_MMFR1: Memory Model Feature Register 1 */
+#define SCB_ID_MMFR1 MMIO32(SCB_BASE + 0x54)
+
+/* ID_MMFR2: Memory Model Feature Register 2 */
+#define SCB_ID_MMFR2 MMIO32(SCB_BASE + 0x58)
+
+/* ID_MMFR3: Memory Model Feature Register 3 */
+#define SCB_ID_MMFR3 MMIO32(SCB_BASE + 0x5C)
+
+/* ID_ISAR0: Instruction Set Attributes Register 0 */
+#define SCB_ID_ISAR0 MMIO32(SCB_BASE + 0x60)
+
+/* ID_ISAR1: Instruction Set Attributes Register 1 */
+#define SCB_ID_ISAR1 MMIO32(SCB_BASE + 0x64)
+
+/* ID_ISAR2: Instruction Set Attributes Register 2 */
+#define SCB_ID_ISAR2 MMIO32(SCB_BASE + 0x68)
+
+/* ID_ISAR3: Instruction Set Attributes Register 3 */
+#define SCB_ID_ISAR3 MMIO32(SCB_BASE + 0x6C)
+
+/* ID_ISAR4: Instruction Set Attributes Register 4 */
+#define SCB_ID_ISAR4 MMIO32(SCB_BASE + 0x70)
+
+/* CPACR: Coprocessor Access Control Register */
+#define SCB_CPACR MMIO32(SCB_BASE + 0x88)
+
+/* FPCCR: Floating-Point Context Control Register */
+#define SCB_FPCCR MMIO32(SCB_BASE + 0x234)
+
+/* FPCAR: Floating-Point Context Address Register */
+#define SCB_FPCAR MMIO32(SCB_BASE + 0x238)
+
+/* FPDSCR: Floating-Point Default Status Control Register */
+#define SCB_FPDSCR MMIO32(SCB_BASE + 0x23C)
+
+/* MVFR0: Media and Floating-Point Feature Register 0 */
+#define SCB_MVFR0 MMIO32(SCB_BASE + 0x240)
+
+/* MVFR1: Media and Floating-Point Feature Register 1 */
+#define SCB_MVFR1 MMIO32(SCB_BASE + 0x244)
+
/* --- SCB values ---------------------------------------------------------- */
/* --- SCB_CPUID values ---------------------------------------------------- */
@@ -292,6 +349,18 @@
/* BFAR [31:0]: Bus fault address */
+/* --- SCB_CPACR values ---------------------------------------------------- */
+
+/* CPACR CPn: Access privileges values */
+#define SCB_CPACR_NONE 0 /* Access denied */
+#define SCB_CPACR_PRIV 1 /* Privileged access only */
+#define SCB_CPACR_FULL 3 /* Full access */
+
+/* CPACR [20:21]: Access privileges for coprocessor 10 */
+#define SCB_CPACR_CP10 (1 << 20)
+/* CPACR [22:23]: Access privileges for coprocessor 11 */
+#define SCB_CPACR_CP11 (1 << 22)
+
/* --- SCB functions ------------------------------------------------------- */
BEGIN_DECLS
diff --git a/include/libopencm3/stm32/i2c.h b/include/libopencm3/stm32/i2c.h
index 13257eb..a59c420 100644
--- a/include/libopencm3/stm32/i2c.h
+++ b/include/libopencm3/stm32/i2c.h
@@ -1,3 +1,19 @@
+/** @defgroup i2c_defines I2C Defines
+
+@ingroup STM32F_defines
+
+@brief <b>libopencm3 Defined Constants and Types for the STM32 I2C </b>
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 12 October 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
/*
* This file is part of the libopencm3 project.
*
@@ -23,11 +39,19 @@
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/cm3/common.h>
+/**@{*/
+
/* --- Convenience macros -------------------------------------------------- */
/* I2C register base adresses (for convenience) */
+/****************************************************************************/
+/** @defgroup i2c_reg_base I2C register base address
+@ingroup i2c_defines
+
+@{*/
#define I2C1 I2C1_BASE
#define I2C2 I2C2_BASE
+/**@}*/
/* --- I2C registers ------------------------------------------------------- */
@@ -146,6 +170,11 @@
/* Note: Bits [7:6] are reserved, and forced to 0 by hardware. */
/* FREQ[5:0]: Peripheral clock frequency (valid values: 2-36 MHz) */
+/****************************************************************************/
+/** @defgroup i2c_clock I2C clock frequency settings
+@ingroup i2c_defines
+
+@{*/
#define I2C_CR2_FREQ_2MHZ 0x02
#define I2C_CR2_FREQ_3MHZ 0x03
#define I2C_CR2_FREQ_4MHZ 0x04
@@ -181,6 +210,7 @@
#define I2C_CR2_FREQ_34MHZ 0x22
#define I2C_CR2_FREQ_35MHZ 0x23
#define I2C_CR2_FREQ_36MHZ 0x24
+/**@}*/
/* --- I2Cx_OAR1 values ---------------------------------------------------- */
@@ -311,8 +341,14 @@
/* --- I2C const definitions ----------------------------------------------- */
+/****************************************************************************/
+/** @defgroup i2c_rw I2C Read/Write bit
+@ingroup i2c_defines
+
+@{*/
#define I2C_WRITE 0
#define I2C_READ 1
+/**@}*/
/* --- I2C funtion prototypes----------------------------------------------- */
@@ -336,3 +372,5 @@ void i2c_send_data(u32 i2c, u8 data);
END_DECLS
#endif
+/**@}*/
+
diff --git a/include/libopencm3/stm32/spi.h b/include/libopencm3/stm32/spi.h
index 11ba820..f23df3a 100644
--- a/include/libopencm3/stm32/spi.h
+++ b/include/libopencm3/stm32/spi.h
@@ -1,3 +1,19 @@
+/** @defgroup spi_defines SPI Defines
+
+@ingroup STM32F_defines
+
+@brief <b>libopencm3 Defined Constants and Types for the STM32 SPI </b>
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 12 October 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
/*
* This file is part of the libopencm3 project.
*
@@ -23,13 +39,21 @@
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/cm3/common.h>
+/**@{*/
+
/* Registers can be accessed as 16bit or 32bit values. */
/* --- Convenience macros -------------------------------------------------- */
+/****************************************************************************/
+/** @defgroup spi_reg_base SPI Register base address
+@ingroup spi_defines
+
+@{*/
#define SPI1 SPI1_BASE
#define SPI2 SPI2_I2S_BASE
#define SPI3 SPI3_I2S_BASE
+/**@}*/
/* --- SPI registers ------------------------------------------------------- */
@@ -110,8 +134,14 @@
#define SPI_CR1_CRCNEXT (1 << 12)
/* DFF: Data frame format */
+/****************************************************************************/
+/** @defgroup spi_dff SPI data frame format
+@ingroup spi_defines
+
+@{*/
#define SPI_CR1_DFF_8BIT (0 << 11)
#define SPI_CR1_DFF_16BIT (1 << 11)
+/**@}*/
#define SPI_CR1_DFF (1 << 11)
/* RXONLY: Receive only */
@@ -124,13 +154,24 @@
#define SPI_CR1_SSI (1 << 8)
/* LSBFIRST: Frame format */
+/****************************************************************************/
+/** @defgroup spi_lsbfirst SPI lsb/msb first
+@ingroup spi_defines
+
+@{*/
#define SPI_CR1_MSBFIRST (0 << 7)
#define SPI_CR1_LSBFIRST (1 << 7)
+/**@}*/
/* SPE: SPI enable */
#define SPI_CR1_SPE (1 << 6)
/* BR[2:0]: Baud rate control */
+/****************************************************************************/
+/** @defgroup spi_baudrate SPI peripheral baud rates
+@ingroup spi_defines
+
+@{*/
#define SPI_CR1_BAUDRATE_FPCLK_DIV_2 (0x00 << 3)
#define SPI_CR1_BAUDRATE_FPCLK_DIV_4 (0x01 << 3)
#define SPI_CR1_BAUDRATE_FPCLK_DIV_8 (0x02 << 3)
@@ -139,6 +180,12 @@
#define SPI_CR1_BAUDRATE_FPCLK_DIV_64 (0x05 << 3)
#define SPI_CR1_BAUDRATE_FPCLK_DIV_128 (0x06 << 3)
#define SPI_CR1_BAUDRATE_FPCLK_DIV_256 (0x07 << 3)
+/**@}*/
+/****************************************************************************/
+/** @defgroup spi_br_pre SPI peripheral baud rate prescale values
+@ingroup spi_defines
+
+@{*/
#define SPI_CR1_BR_FPCLK_DIV_2 0x0
#define SPI_CR1_BR_FPCLK_DIV_4 0x1
#define SPI_CR1_BR_FPCLK_DIV_8 0x2
@@ -147,18 +194,31 @@
#define SPI_CR1_BR_FPCLK_DIV_64 0x5
#define SPI_CR1_BR_FPCLK_DIV_128 0x6
#define SPI_CR1_BR_FPCLK_DIV_256 0x7
+/**@}*/
/* MSTR: Master selection */
#define SPI_CR1_MSTR (1 << 2)
/* CPOL: Clock polarity */
+/****************************************************************************/
+/** @defgroup spi_cpol SPI clock polarity
+@ingroup spi_defines
+
+@{*/
#define SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE (0 << 1)
#define SPI_CR1_CPOL_CLK_TO_1_WHEN_IDLE (1 << 1)
+/**@}*/
#define SPI_CR1_CPOL (1 << 1)
/* CPHA: Clock phase */
+/****************************************************************************/
+/** @defgroup spi_cpha SPI clock phase
+@ingroup spi_defines
+
+@{*/
#define SPI_CR1_CPHA_CLK_TRANSITION_1 (0 << 0)
#define SPI_CR1_CPHA_CLK_TRANSITION_2 (1 << 0)
+/**@}*/
#define SPI_CR1_CPHA (1 << 0)
/* --- SPI_CR2 values ------------------------------------------------------ */
@@ -347,4 +407,6 @@ void spi_disable_rx_dma(u32 spi);
END_DECLS
+/**@}*/
+
#endif
diff --git a/include/libopencm3/stm32/timer.h b/include/libopencm3/stm32/timer.h
index b6f8949..4977674 100644
--- a/include/libopencm3/stm32/timer.h
+++ b/include/libopencm3/stm32/timer.h
@@ -1,6 +1,6 @@
/** @defgroup STM32F_tim_defines Timers Defines
-@brief <b>libopencm3 Defined Constants and Types for the STM32F1xx Timers</b>
+@brief <b>libopencm3 Defined Constants and Types for the STM32 Timers</b>
@ingroup STM32F_defines
@@ -44,7 +44,7 @@ LGPL License Terms @ref lgpl_license
/* Timer register base adresses (for convenience) */
/****************************************************************************/
/** @defgroup tim_reg_base Timer register base addresses
-@ingroup STM32F1xx_tim_defines
+@ingroup STM32F_tim_defines
@{*/
#define TIM1 TIM1_BASE
@@ -251,7 +251,7 @@ LGPL License Terms @ref lgpl_license
/****************************************************************************/
/** @defgroup tim_x_cr1_cdr TIMx_CR1 CKD[1:0] Clock Division Ratio
-@ingroup STM32F1xx_tim_defines
+@ingroup STM32F_tim_defines
@{*/
/* CKD[1:0]: Clock division */
@@ -267,7 +267,7 @@ LGPL License Terms @ref lgpl_license
/* CMS[1:0]: Center-aligned mode selection */
/****************************************************************************/
/** @defgroup tim_x_cr1_cms TIMx_CR1 CMS[1:0]: Center-aligned Mode Selection
-@ingroup STM32F1xx_tim_defines
+@ingroup STM32F_tim_defines
@{*/
#define TIM_CR1_CMS_EDGE (0x0 << 5)
@@ -280,7 +280,7 @@ LGPL License Terms @ref lgpl_license
/* DIR: Direction */
/****************************************************************************/
/** @defgroup tim_x_cr1_dir TIMx_CR1 DIR: Direction
-@ingroup STM32F1xx_tim_defines
+@ingroup STM32F_tim_defines
@{*/
#define TIM_CR1_DIR_UP (0 << 4)
@@ -303,7 +303,7 @@ LGPL License Terms @ref lgpl_license
/****************************************************************************/
/** @defgroup tim_x_cr2_ois TIMx_CR2_OIS: Force Output Idle State Control Values
-@ingroup STM32F1xx_tim_defines
+@ingroup STM32F_tim_defines
@{*/
/* OIS4:*//** Output idle state 4 (OC4 output) */
@@ -335,7 +335,7 @@ LGPL License Terms @ref lgpl_license
/* MMS[2:0]: Master mode selection */
/****************************************************************************/
/** @defgroup tim_mastermode TIMx_CR2 MMS[6:4]: Master Mode Selection
-@ingroup STM32F1xx_tim_defines
+@ingroup STM32F_tim_defines
@{*/
#define TIM_CR2_MMS_RESET (0x0 << 4)
@@ -397,7 +397,7 @@ LGPL License Terms @ref lgpl_license
/* TS[2:0]: Trigger selection */
/** @defgroup tim_ts TS Trigger selection
-@ingroup STM32F1xx_tim_defines
+@ingroup STM32F_tim_defines
@{*/
/** Internal Trigger 0 (ITR0) */
@@ -421,7 +421,7 @@ LGPL License Terms @ref lgpl_license
/* SMS[2:0]: Slave mode selection */
/** @defgroup tim_sms SMS Slave mode selection
-@ingroup STM32F1xx_tim_defines
+@ingroup STM32F_tim_defines
@{*/
/** Slave mode disabled */
@@ -451,7 +451,7 @@ and generates an update of the registers. */
/****************************************************************************/
/** @defgroup tim_irq_enable TIMx_DIER Timer DMA and Interrupt Enable Values
-@ingroup STM32F1xx_tim_defines
+@ingroup STM32F_tim_defines
@{*/
/* TDE:*//** Trigger DMA request enable */
@@ -503,7 +503,7 @@ and generates an update of the registers. */
/* --- TIMx_SR values ------------------------------------------------------ */
/****************************************************************************/
/** @defgroup tim_sr_values TIMx_SR Timer Status Register Flags
-@ingroup STM32F1xx_tim_defines
+@ingroup STM32F_tim_defines
@{*/
@@ -548,7 +548,7 @@ and generates an update of the registers. */
/****************************************************************************/
/** @defgroup tim_event_gen TIMx_EGR Timer Event Generator Values
-@ingroup STM32F1xx_tim_defines
+@ingroup STM32F_tim_defines
@{*/
@@ -908,7 +908,7 @@ and generates an update of the registers. */
/* LOCK[1:0]: Lock configuration */
/****************************************************************************/
/** @defgroup tim_lock TIM_BDTR_LOCK Timer Lock Values
-@ingroup STM32F1xx_tim_defines
+@ingroup STM32F_tim_defines
@{*/
#define TIM_BDTR_LOCK_OFF (0x0 << 8)
@@ -1028,6 +1028,7 @@ BEGIN_DECLS
void timer_reset(u32 timer_peripheral);
void timer_enable_irq(u32 timer_peripheral, u32 irq);
void timer_disable_irq(u32 timer_peripheral, u32 irq);
+bool timer_return_interrupt_source(u32 timer_peripheral, u32 flag);
bool timer_get_flag(u32 timer_peripheral, u32 flag);
void timer_clear_flag(u32 timer_peripheral, u32 flag);
void timer_set_mode(u32 timer_peripheral, u32 clock_div,
@@ -1090,6 +1091,7 @@ void timer_set_break_lock(u32 timer_peripheral, u32 lock);
void timer_set_deadtime(u32 timer_peripheral, u32 deadtime);
void timer_generate_event(u32 timer_peripheral, u32 event);
u32 timer_get_counter(u32 timer_peripheral);
+void timer_set_counter(u32 timer_peripheral, u32 count);
void timer_ic_set_filter(u32 timer, enum tim_ic_id ic, enum tim_ic_filter flt);
void timer_ic_set_prescaler(u32 timer, enum tim_ic_id ic, enum tim_ic_psc psc);
diff --git a/include/libopencm3/stm32/usart.h b/include/libopencm3/stm32/usart.h
index 9ec6c3d..088e67b 100644
--- a/include/libopencm3/stm32/usart.h
+++ b/include/libopencm3/stm32/usart.h
@@ -1,3 +1,18 @@
+/** @defgroup STM32F_usart_defines USART Defines
+
+@brief <b>libopencm3 Defined Constants and Types for the STM32F Digital to Analog Converter </b>
+
+@ingroup STM32F_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
+
+@date 1 September 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
/*
* This file is part of the libopencm3 project.
*
@@ -17,6 +32,8 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
+/**@{*/
+
#ifndef LIBOPENCM3_USART_H
#define LIBOPENCM3_USART_H
@@ -25,9 +42,15 @@
/* --- Convenience macros -------------------------------------------------- */
+/****************************************************************************/
+/** @defgroup usart_reg_base USART register base addresses
+@ingroup STM32F_usart_defines
+
+@{*/
#define USART1 USART1_BASE
#define USART2 USART2_BASE
#define USART3 USART3_BASE
+/**@}*/
#define UART4 UART4_BASE
#define UART5 UART5_BASE
@@ -90,37 +113,43 @@
#define UART5_GTPR USART_GTPR(UART5_BASE)
/* --- USART_SR values ----------------------------------------------------- */
+/****************************************************************************/
+/** @defgroup usart_sr_flags USART Status register Flags
+@ingroup STM32F_usart_defines
-/* CTS: CTS flag */
-/* Note: N/A on UART4/5 */
+@{*/
+
+/** CTS: CTS flag */
+/** @note: undefined on UART4 and UART5 */
#define USART_SR_CTS (1 << 9)
-/* LBD: LIN break detection flag */
+/** LBD: LIN break detection flag */
#define USART_SR_LBD (1 << 8)
-/* TXE: Transmit data buffer empty */
+/** TXE: Transmit data buffer empty */
#define USART_SR_TXE (1 << 7)
-/* TC: Transmission complete */
+/** TC: Transmission complete */
#define USART_SR_TC (1 << 6)
-/* RXNE: Read data register not empty */
+/** RXNE: Read data register not empty */
#define USART_SR_RXNE (1 << 5)
-/* IDLE: Idle line detected */
+/** IDLE: Idle line detected */
#define USART_SR_IDLE (1 << 4)
-/* ORE: Overrun error */
+/** ORE: Overrun error */
#define USART_SR_ORE (1 << 3)
-/* NE: Noise error flag */
+/** NE: Noise error flag */
#define USART_SR_NE (1 << 2)
-/* FE: Framing error */
+/** FE: Framing error */
#define USART_SR_FE (1 << 1)
-/* PE: Parity error */
+/** PE: Parity error */
#define USART_SR_PE (1 << 0)
+/**@}*/
/* --- USART_DR values ----------------------------------------------------- */
@@ -269,27 +298,51 @@
/* --- Convenience defines ------------------------------------------------- */
/* CR1_PCE / CR1_PS combined values */
+/****************************************************************************/
+/** @defgroup usart_cr1_parity USART Parity Selection
+@ingroup STM32F_usart_defines
+
+@{*/
#define USART_PARITY_NONE 0x00
#define USART_PARITY_EVEN USART_CR1_PCE
#define USART_PARITY_ODD (USART_CR1_PS | USART_CR1_PCE)
+/**@}*/
#define USART_PARITY_MASK (USART_CR1_PS | USART_CR1_PCE)
/* CR1_TE/CR1_RE combined values */
+/****************************************************************************/
+/** @defgroup usart_cr1_mode USART Tx/Rx Mode Selection
+@ingroup STM32F_usart_defines
+
+@{*/
#define USART_MODE_RX USART_CR1_RE
#define USART_MODE_TX USART_CR1_TE
#define USART_MODE_TX_RX (USART_CR1_RE | USART_CR1_TE)
+/**@}*/
#define USART_MODE_MASK (USART_CR1_RE | USART_CR1_TE)
+/****************************************************************************/
+/** @defgroup usart_cr2_stopbits USART Stop Bit Selection
+@ingroup STM32F_usart_defines
+
+@{*/
#define USART_STOPBITS_1 USART_CR2_STOPBITS_1 /* 1 stop bit */
#define USART_STOPBITS_0_5 USART_CR2_STOPBITS_0_5 /* 0.5 stop bits */
#define USART_STOPBITS_2 USART_CR2_STOPBITS_2 /* 2 stop bits */
#define USART_STOPBITS_1_5 USART_CR2_STOPBITS_1_5 /* 1.5 stop bits */
+/**@}*/
/* CR3_CTSE/CR3_RTSE combined values */
+/****************************************************************************/
+/** @defgroup usart_cr3_flowcontrol USART Hardware Flow Control Selection
+@ingroup STM32F_usart_defines
+
+@{*/
#define USART_FLOWCONTROL_NONE 0x00
#define USART_FLOWCONTROL_RTS USART_CR3_RTSE
#define USART_FLOWCONTROL_CTS USART_CR3_CTSE
#define USART_FLOWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)
+/**@}*/
#define USART_FLOWCONTROL_MASK (USART_CR3_RTSE | USART_CR3_CTSE)
/* --- Function prototypes ------------------------------------------------- */
@@ -314,7 +367,15 @@ void usart_enable_rx_dma(u32 usart);
void usart_disable_rx_dma(u32 usart);
void usart_enable_tx_dma(u32 usart);
void usart_disable_tx_dma(u32 usart);
+void usart_enable_rx_interrupt(u32 usart);
+void usart_disable_rx_interrupt(u32 usart);
+void usart_enable_tx_interrupt(u32 usart);
+void usart_disable_tx_interrupt(u32 usart);
+bool usart_get_flag(u32 usart, u32 flag);
+bool usart_get_interrupt_source(u32 usart, u32 flag);
END_DECLS
#endif
+/**@}*/
+