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-rw-r--r--include/libopencm3/stm32/can.h32
-rw-r--r--include/libopencm3/stm32/common/crc_common_all.h85
-rw-r--r--include/libopencm3/stm32/common/dac_common_all.h403
-rw-r--r--include/libopencm3/stm32/common/dma_common_f13.h388
-rw-r--r--include/libopencm3/stm32/common/dma_common_f24.h604
-rw-r--r--include/libopencm3/stm32/common/gpio_common_all.h73
-rw-r--r--include/libopencm3/stm32/common/gpio_common_f24.h285
-rw-r--r--include/libopencm3/stm32/common/i2c_common_all.h383
-rw-r--r--include/libopencm3/stm32/common/i2c_common_f24.h35
-rw-r--r--include/libopencm3/stm32/common/iwdg_common_all.h109
-rw-r--r--include/libopencm3/stm32/common/pwr_common_all.h119
-rw-r--r--include/libopencm3/stm32/common/rng_common_f24.h61
-rw-r--r--include/libopencm3/stm32/common/rtc_common_bcd.h302
-rw-r--r--include/libopencm3/stm32/common/spi_common_all.h399
-rw-r--r--include/libopencm3/stm32/common/spi_common_f24.h (renamed from include/libopencm3/stm32/f4/syscfg.h)36
-rw-r--r--include/libopencm3/stm32/common/usart_common_all.h369
-rw-r--r--include/libopencm3/stm32/common/usart_common_f24.h66
-rw-r--r--include/libopencm3/stm32/crc.h89
-rw-r--r--include/libopencm3/stm32/dac.h409
-rw-r--r--include/libopencm3/stm32/desig.h (renamed from include/libopencm3/stm32/f1/desig.h)9
-rw-r--r--include/libopencm3/stm32/dma.h31
-rw-r--r--include/libopencm3/stm32/exti.h3
-rw-r--r--include/libopencm3/stm32/f1/crc.h40
-rw-r--r--include/libopencm3/stm32/f1/dac.h40
-rw-r--r--include/libopencm3/stm32/f1/dma.h344
-rw-r--r--include/libopencm3/stm32/f1/flash.h56
-rw-r--r--include/libopencm3/stm32/f1/gpio.h86
-rw-r--r--include/libopencm3/stm32/f1/i2c.h41
-rw-r--r--include/libopencm3/stm32/f1/irq.yaml72
-rw-r--r--include/libopencm3/stm32/f1/iwdg.h41
-rw-r--r--include/libopencm3/stm32/f1/nvic_f1.h114
-rw-r--r--include/libopencm3/stm32/f1/pwr.h40
-rw-r--r--include/libopencm3/stm32/f1/rcc.h25
-rw-r--r--include/libopencm3/stm32/f1/rtc.h5
-rw-r--r--include/libopencm3/stm32/f1/scb.h307
-rw-r--r--include/libopencm3/stm32/f1/spi.h40
-rw-r--r--include/libopencm3/stm32/f1/usart.h40
-rw-r--r--include/libopencm3/stm32/f2/crc.h40
-rw-r--r--include/libopencm3/stm32/f2/dac.h40
-rw-r--r--include/libopencm3/stm32/f2/dma.h406
-rw-r--r--include/libopencm3/stm32/f2/flash.h112
-rw-r--r--include/libopencm3/stm32/f2/gpio.h278
-rw-r--r--include/libopencm3/stm32/f2/i2c.h41
-rw-r--r--include/libopencm3/stm32/f2/irq.yaml85
-rw-r--r--include/libopencm3/stm32/f2/iwdg.h41
-rw-r--r--include/libopencm3/stm32/f2/nvic_f2.h112
-rw-r--r--include/libopencm3/stm32/f2/rcc.h2
-rw-r--r--include/libopencm3/stm32/f2/rng.h24
-rw-r--r--include/libopencm3/stm32/f2/rtc.h39
-rw-r--r--include/libopencm3/stm32/f2/scb.h307
-rw-r--r--include/libopencm3/stm32/f2/spi.h43
-rw-r--r--include/libopencm3/stm32/f2/usart.h63
-rw-r--r--include/libopencm3/stm32/f4/adc.h873
-rw-r--r--include/libopencm3/stm32/f4/crc.h40
-rw-r--r--include/libopencm3/stm32/f4/dac.h40
-rw-r--r--include/libopencm3/stm32/f4/dma.h41
-rw-r--r--include/libopencm3/stm32/f4/flash.h112
-rw-r--r--include/libopencm3/stm32/f4/gpio.h278
-rw-r--r--include/libopencm3/stm32/f4/i2c.h41
-rw-r--r--include/libopencm3/stm32/f4/irq.yaml85
-rw-r--r--include/libopencm3/stm32/f4/iwdg.h41
-rw-r--r--include/libopencm3/stm32/f4/memorymap.h5
-rw-r--r--include/libopencm3/stm32/f4/nvic_f4.h112
-rw-r--r--include/libopencm3/stm32/f4/pwr.h19
-rw-r--r--include/libopencm3/stm32/f4/rcc.h2
-rw-r--r--include/libopencm3/stm32/f4/rng.h43
-rw-r--r--include/libopencm3/stm32/f4/rtc.h39
-rw-r--r--include/libopencm3/stm32/f4/scb.h376
-rw-r--r--include/libopencm3/stm32/f4/spi.h43
-rw-r--r--include/libopencm3/stm32/f4/usart.h63
-rw-r--r--include/libopencm3/stm32/gpio.h31
-rw-r--r--include/libopencm3/stm32/i2c.h367
-rw-r--r--include/libopencm3/stm32/iwdg.h112
-rw-r--r--include/libopencm3/stm32/l1/crc.h40
-rw-r--r--include/libopencm3/stm32/l1/dac.h40
-rw-r--r--include/libopencm3/stm32/l1/doc-stm32l1.h32
-rw-r--r--include/libopencm3/stm32/l1/flash.h125
-rw-r--r--include/libopencm3/stm32/l1/gpio.h266
-rw-r--r--include/libopencm3/stm32/l1/i2c.h41
-rw-r--r--include/libopencm3/stm32/l1/irq.yaml62
-rw-r--r--include/libopencm3/stm32/l1/iwdg.h41
-rw-r--r--include/libopencm3/stm32/l1/memorymap.h116
-rw-r--r--include/libopencm3/stm32/l1/pwr.h112
-rw-r--r--include/libopencm3/stm32/l1/rcc.h455
-rw-r--r--include/libopencm3/stm32/l1/rtc.h39
-rw-r--r--include/libopencm3/stm32/l1/spi.h40
-rw-r--r--include/libopencm3/stm32/l1/usart.h40
-rw-r--r--include/libopencm3/stm32/memorymap.h2
-rw-r--r--include/libopencm3/stm32/nvic.h135
-rw-r--r--include/libopencm3/stm32/otg_fs.h105
-rw-r--r--include/libopencm3/stm32/otg_hs.h396
-rw-r--r--include/libopencm3/stm32/pwr.h122
-rw-r--r--include/libopencm3/stm32/rcc.h31
-rw-r--r--include/libopencm3/stm32/rtc.h31
-rw-r--r--include/libopencm3/stm32/spi.h405
-rw-r--r--include/libopencm3/stm32/syscfg.h (renamed from include/libopencm3/stm32/f2/syscfg.h)0
-rw-r--r--include/libopencm3/stm32/systick.h111
-rw-r--r--include/libopencm3/stm32/usart.h372
98 files changed, 8073 insertions, 5063 deletions
diff --git a/include/libopencm3/stm32/can.h b/include/libopencm3/stm32/can.h
index d6636d5..65aca5c 100644
--- a/include/libopencm3/stm32/can.h
+++ b/include/libopencm3/stm32/can.h
@@ -1,3 +1,17 @@
+/** @defgroup can_defines CAN defines
+
+@ingroup STM32F_defines
+
+@brief <b>libopencm3 Defined Constants and Types for STM32 CAN </b>
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2010 Piotr Esden-Tempski <piotr@esden.net>
+
+@date 12 November 2012
+
+LGPL License Terms @ref lgpl_license
+*/
/*
* This file is part of the libopencm3 project.
*
@@ -23,11 +37,19 @@
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/cm3/common.h>
+/**@{*/
+
/* --- Convenience macros -------------------------------------------------- */
/* CAN register base adresses (for convenience) */
+/*****************************************************************************/
+/** @defgroup can_reg_base CAN register base address
+@ingroup can_defines
+
+@{*/
#define CAN1 BX_CAN1_BASE
#define CAN2 BX_CAN2_BASE
+/**@}*/
/* --- CAN registers ------------------------------------------------------- */
@@ -417,6 +439,7 @@
#define CAN_BTR_SJW_3TQ (0x2 << 24)
#define CAN_BTR_SJW_4TQ (0x3 << 24)
#define CAN_BTR_SJW_MASK (0x3 << 24)
+#define CAN_BTR_SJW_SHIFT 24
/* 23 Reserved, forced by hardware to 0 */
@@ -430,6 +453,7 @@
#define CAN_BTR_TS2_7TQ (0x6 << 20)
#define CAN_BTR_TS2_8TQ (0x7 << 20)
#define CAN_BTR_TS2_MASK (0x7 << 20)
+#define CAN_BTR_TS2_SHIFT 20
/* TS1[3:0]: Time segment 1 */
#define CAN_BTR_TS1_1TQ (0x0 << 16)
@@ -449,6 +473,7 @@
#define CAN_BTR_TS1_15TQ (0xE << 16)
#define CAN_BTR_TS1_16TQ (0xF << 16)
#define CAN_BTR_TS1_MASK (0xF << 16)
+#define CAN_BTR_TS1_SHIFT 16
/* 15:10 Reserved, forced by hardware to 0 */
@@ -458,7 +483,7 @@
/* --- CAN_TIxR values ------------------------------------------------------ */
/* STID[10:0]: Standard identifier */
-#define CAN_TIxR_STID_MASK (0x3FF << 21)
+#define CAN_TIxR_STID_MASK (0x7FF << 21)
#define CAN_TIxR_STID_SHIFT 21
/* EXID[15:0]: Extended identifier */
@@ -619,7 +644,8 @@ BEGIN_DECLS
void can_reset(u32 canport);
int can_init(u32 canport, bool ttcm, bool abom, bool awum, bool nart,
- bool rflm, bool txfp, u32 sjw, u32 ts1, u32 ts2, u32 brp);
+ bool rflm, bool txfp, u32 sjw, u32 ts1, u32 ts2, u32 brp,
+ bool loopback, bool silent);
void can_filter_init(u32 canport, u32 nr, bool scale_32bit, bool id_list_mode,
u32 fr1, u32 fr2, u32 fifo, bool enable);
@@ -640,7 +666,7 @@ void can_receive(u32 canport, u8 fifo, bool release, u32 *id, bool *ext,
bool *rtr, u32 *fmi, u8 *length, u8 *data);
void can_fifo_release(u32 canport, u8 fifo);
-
+bool can_available_mailbox(u32 canport);
END_DECLS
#endif
diff --git a/include/libopencm3/stm32/common/crc_common_all.h b/include/libopencm3/stm32/common/crc_common_all.h
new file mode 100644
index 0000000..892f41b
--- /dev/null
+++ b/include/libopencm3/stm32/common/crc_common_all.h
@@ -0,0 +1,85 @@
+/** @addtogroup crc_defines */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA SPI.H */
+
+#ifndef LIBOPENCM3_CRC_COMMON_ALL_H
+#define LIBOPENCM3_CRC_COMMON_ALL_H
+
+#include <libopencm3/cm3/common.h>
+
+/* --- CRC registers ------------------------------------------------------- */
+
+/* Data register (CRC_DR) */
+#define CRC_DR MMIO32(CRC_BASE + 0x00)
+
+/* Independent data register (CRC_IDR) */
+#define CRC_IDR MMIO32(CRC_BASE + 0x04)
+
+/* Control register (CRC_CR) */
+#define CRC_CR MMIO32(CRC_BASE + 0x08)
+
+/* --- CRC_DR values ------------------------------------------------------- */
+
+/* Bits [31:0]: Data register */
+
+/* --- CRC_IDR values ------------------------------------------------------ */
+
+/* Bits [31:8]: Reserved */
+
+/* Bits [7:0]: General-purpose 8-bit data register bits */
+
+/* --- CRC_CR values ------------------------------------------------------- */
+
+/* Bits [31:1]: Reserved */
+
+/* RESET bit */
+#define CRC_CR_RESET (1 << 0)
+
+/* --- CRC function prototypes --------------------------------------------- */
+
+BEGIN_DECLS
+
+/* TODO */
+
+/**
+ * Reset the CRC calculator to initial values.
+ */
+void crc_reset(void);
+
+/**
+ * Add a word to the crc calculator and return the result.
+ * @param data new word to add to the crc calculator
+ * @return final crc calculator value
+ */
+u32 crc_calculate(u32 data);
+
+/**
+ * Add a block of data to the CRC calculator and return the final result
+ * @param datap pointer to the start of a block of 32bit data words
+ * @param size length of data, in 32bit increments
+ * @return final CRC calculator value
+ */
+u32 crc_calculate_block(u32 *datap, int size);
+
+END_DECLS
+
+#endif
diff --git a/include/libopencm3/stm32/common/dac_common_all.h b/include/libopencm3/stm32/common/dac_common_all.h
new file mode 100644
index 0000000..c843c55
--- /dev/null
+++ b/include/libopencm3/stm32/common/dac_common_all.h
@@ -0,0 +1,403 @@
+/** @addtogroup dac_defines */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Felix Held <felix-libopencm3@felixheld.de>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/**@{*/
+
+#ifndef LIBOPENCM3_DAC_COMMON_ALL_H
+#define LIBOPENCM3_DAC_COMMON_ALL_H
+
+#include <libopencm3/cm3/common.h>
+
+
+/* --- DAC registers ------------------------------------------------------- */
+
+/* DAC control register (DAC_CR) */
+#define DAC_CR MMIO32(DAC_BASE + 0x00)
+
+/* DAC software trigger register (DAC_SWTRIGR) */
+#define DAC_SWTRIGR MMIO32(DAC_BASE + 0x04)
+
+/* DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) */
+#define DAC_DHR12R1 MMIO32(DAC_BASE + 0x08)
+
+/* DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) */
+#define DAC_DHR12L1 MMIO32(DAC_BASE + 0x0C)
+
+/* DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) */
+#define DAC_DHR8R1 MMIO32(DAC_BASE + 0x10)
+
+/* DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) */
+#define DAC_DHR12R2 MMIO32(DAC_BASE + 0x14)
+
+/* DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) */
+#define DAC_DHR12L2 MMIO32(DAC_BASE + 0x18)
+
+/* DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) */
+#define DAC_DHR8R2 MMIO32(DAC_BASE + 0x1C)
+
+/* Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) */
+#define DAC_DHR12RD MMIO32(DAC_BASE + 0x20)
+
+/* DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD) */
+#define DAC_DHR12LD MMIO32(DAC_BASE + 0x24)
+
+/* DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD) */
+#define DAC_DHR8RD MMIO32(DAC_BASE + 0x28)
+
+/* DAC channel1 data output register (DAC_DOR1) */
+#define DAC_DOR1 MMIO32(DAC_BASE + 0x2C)
+
+/* DAC channel2 data output register (DAC_DOR2) */
+#define DAC_DOR2 MMIO32(DAC_BASE + 0x30)
+
+
+/* --- DAC_CR values ------------------------------------------------------- */
+
+/* DMAUDRIE2: DAC channel2 DMA underrun interrupt enable */
+/* doesn't exist in most members of the STM32F1 family */
+#define DAC_CR_DMAUDRIE2 (1 << 29)
+
+/* DMAEN2: DAC channel2 DMA enable */
+#define DAC_CR_DMAEN2 (1 << 28)
+
+/* MAMP2[3:0]: DAC channel2 mask/amplitude selector */
+/* DAC_CR_MAMP2_n:
+ * Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**n)-1
+ */
+#define DAC_CR_MAMP2_SHIFT 24
+/** @defgroup dac_mamp2 DAC Channel 2 LFSR Mask and Triangle Wave Amplitude values
+@ingroup STM32F_dac_defines
+
+Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n)-1
+@{*/
+#define DAC_CR_MAMP2_1 (0x0 << DAC_CR_MAMP2_SHIFT)
+#define DAC_CR_MAMP2_2 (0x1 << DAC_CR_MAMP2_SHIFT)
+#define DAC_CR_MAMP2_3 (0x2 << DAC_CR_MAMP2_SHIFT)
+#define DAC_CR_MAMP2_4 (0x3 << DAC_CR_MAMP2_SHIFT)
+#define DAC_CR_MAMP2_5 (0x4 << DAC_CR_MAMP2_SHIFT)
+#define DAC_CR_MAMP2_6 (0x5 << DAC_CR_MAMP2_SHIFT)
+#define DAC_CR_MAMP2_7 (0x6 << DAC_CR_MAMP2_SHIFT)
+#define DAC_CR_MAMP2_8 (0x7 << DAC_CR_MAMP2_SHIFT)
+#define DAC_CR_MAMP2_9 (0x8 << DAC_CR_MAMP2_SHIFT)
+#define DAC_CR_MAMP2_10 (0x9 << DAC_CR_MAMP2_SHIFT)
+#define DAC_CR_MAMP2_11 (0xA << DAC_CR_MAMP2_SHIFT)
+#define DAC_CR_MAMP2_12 (0xB << DAC_CR_MAMP2_SHIFT)
+/**@}*/
+
+/* WAVE2[1:0]: DAC channel2 noise/triangle wave generation enable */
+/* Legend:
+ * DIS: wave generation disabled
+ * NOISE: Noise wave generation enabled
+ * TRI: Triangle wave generation enabled
+ *
+ * Note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled)
+ */
+#define DAC_CR_WAVE2_SHIFT 22
+#define DAC_CR_WAVE2_DIS (0x3 << DAC_CR_WAVE2_SHIFT)
+/** @defgroup dac_wave2_en DAC Channel 2 Waveform Generation Enable
+@ingroup STM32F_dac_defines
+
+@li NOISE: Noise wave generation enabled
+@li TRI: Triangle wave generation enabled
+
+@note: only used if bit TEN2 is set (DAC channel2 trigger enabled)
+@{*/
+#define DAC_CR_WAVE2_NOISE (0x1 << DAC_CR_WAVE2_SHIFT)
+#define DAC_CR_WAVE2_TRI (0x2 << DAC_CR_WAVE2_SHIFT)
+/**@}*/
+
+/* TSEL2[2:0]: DAC channel2 trigger selection */
+/* Legend:
+ *
+ * T6: Timer 6 TRGO event
+ * T3: Timer 3 TRGO event
+ * T8: Timer 8 TRGO event
+ * T7: Timer 7 TRGO event
+ * T5: Timer 5 TRGO event
+ * T15: Timer 15 TRGO event
+ * T2: Timer 2 TRGO event
+ * T4: Timer 4 TRGO event
+ * E9: External line9
+ * SW: Software trigger
+ *
+ * Note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled)
+ * Note: T3 == T8; T5 == T15; not both present on one device
+ * Note: this is *not* valid for the STM32L1 family
+ */
+#define DAC_CR_TSEL2_SHIFT 19
+/** @defgroup dac_trig2_sel DAC Channel 2 Trigger Source Selection
+@ingroup STM32F_dac_defines
+
+@li T6: Timer 6 TRGO event
+@li T3: Timer 3 TRGO event
+@li T8: Timer 8 TRGO event
+@li T7: Timer 7 TRGO event
+@li T5: Timer 5 TRGO event
+@li T15: Timer 15 TRGO event
+@li T2: Timer 2 TRGO event
+@li T4: Timer 4 TRGO event
+@li E9: External line9
+@li SW: Software trigger
+
+@note: Refer to the timer documentation for details of the TRGO event.
+@note: T3 replaced by T8 and T5 replaced by T15 in some devices.
+@note: this is <b>not</b> valid for the STM32L1 family.
+@note: only used if bit TEN2 is set (DAC channel 2 trigger enabled)
+@{*/
+#define DAC_CR_TSEL2_T6 (0x0 << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_T3 (0x1 << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_T8 (0x1 << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_T7 (0x2 << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_T5 (0x3 << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_T15 (0x3 << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_T2 (0x4 << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_T4 (0x5 << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_E9 (0x6 << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_SW (0x7 << DAC_CR_TSEL2_SHIFT)
+/**@}*/
+
+/* TEN2: DAC channel2 trigger enable */
+#define DAC_CR_TEN2 (1 << 18)
+
+/* BOFF2: DAC channel2 output buffer disable */
+#define DAC_CR_BOFF2 (1 << 17)
+
+/* EN2: DAC channel2 enable */
+#define DAC_CR_EN2 (1 << 16)
+
+/* DMAUDRIE1: DAC channel1 DMA underrun interrupt enable */
+/* doesn't exist in most members of the STM32F1 family */
+#define DAC_CR_DMAUDRIE1 (1 << 13)
+
+/* DMAEN1: DAC channel1 DMA enable */
+#define DAC_CR_DMAEN1 (1 << 12)
+
+/* MAMP1[3:0]: DAC channel1 mask/amplitude selector */
+/* DAC_CR_MAMP1_n:
+ * Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**n)-1
+ */
+#define DAC_CR_MAMP1_SHIFT 8
+/** @defgroup dac_mamp1 DAC Channel 1 LFSR Mask and Triangle Wave Amplitude values
+@ingroup STM32F_dac_defines
+
+Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n+1)-1
+@{*/
+#define DAC_CR_MAMP1_1 (0x0 << DAC_CR_MAMP1_SHIFT)
+#define DAC_CR_MAMP1_2 (0x1 << DAC_CR_MAMP1_SHIFT)
+#define DAC_CR_MAMP1_3 (0x2 << DAC_CR_MAMP1_SHIFT)
+#define DAC_CR_MAMP1_4 (0x3 << DAC_CR_MAMP1_SHIFT)
+#define DAC_CR_MAMP1_5 (0x4 << DAC_CR_MAMP1_SHIFT)
+#define DAC_CR_MAMP1_6 (0x5 << DAC_CR_MAMP1_SHIFT)
+#define DAC_CR_MAMP1_7 (0x6 << DAC_CR_MAMP1_SHIFT)
+#define DAC_CR_MAMP1_8 (0x7 << DAC_CR_MAMP1_SHIFT)
+#define DAC_CR_MAMP1_9 (0x8 << DAC_CR_MAMP1_SHIFT)
+#define DAC_CR_MAMP1_10 (0x9 << DAC_CR_MAMP1_SHIFT)
+#define DAC_CR_MAMP1_11 (0xA << DAC_CR_MAMP1_SHIFT)
+#define DAC_CR_MAMP1_12 (0xB << DAC_CR_MAMP1_SHIFT)
+/**@}*/
+
+/* WAVE1[1:0]: DAC channel1 noise/triangle wave generation enable */
+/* Legend:
+ * DIS: wave generation disabled
+ * NOISE: Noise wave generation enabled
+ * TRI: Triangle wave generation enabled
+ *
+ * Note: only used if bit TEN1 = 1 (DAC channel1 trigger enabled)
+ */
+#define DAC_CR_WAVE1_SHIFT 6
+#define DAC_CR_WAVE1_DIS (0x3 << DAC_CR_WAVE1_SHIFT)
+/** @defgroup dac_wave1_en DAC Channel 1 Waveform Generation Enable
+@ingroup STM32F_dac_defines
+
+@li DIS: wave generation disabled
+@li NOISE: Noise wave generation enabled
+@li TRI: Triangle wave generation enabled
+
+@note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled)
+@{*/
+#define DAC_CR_WAVE1_NOISE (0x1 << DAC_CR_WAVE1_SHIFT)
+#define DAC_CR_WAVE1_TRI (0x2 << DAC_CR_WAVE1_SHIFT)
+/**@}*/
+
+/* TSEL1[2:0]: DAC channel1 trigger selection */
+/* Legend:
+ *
+ * T6: Timer 6 TRGO event
+ * T3: Timer 3 TRGO event in connectivity line devices
+ * T8: Timer 8 TRGO event in high-density and XL-density devices
+ * T7: Timer 7 TRGO event
+ * T5: Timer 5 TRGO event
+ * T15: Timer 15 TRGO event
+ * T2: Timer 2 TRGO event
+ * T4: Timer 4 TRGO event
+ * E9: External line9
+ * SW: Software trigger
+ *
+ * Note: only used if bit TEN1 = 1 (DAC channel1 trigger enabled)
+ * Note: T3 == T8; T5 == T15; not both present on one device
+ * Note: this is *not* valid for the STM32L1 family
+ */
+#define DAC_CR_TSEL1_SHIFT 3
+/** @defgroup dac_trig1_sel DAC Channel 1 Trigger Source Selection
+@ingroup STM32F_dac_defines
+
+@li T6: Timer 6 TRGO event
+@li T3: Timer 3 TRGO event
+@li T8: Timer 8 TRGO event
+@li T7: Timer 7 TRGO event
+@li T5: Timer 5 TRGO event
+@li T15: Timer 15 TRGO event
+@li T2: Timer 2 TRGO event
+@li T4: Timer 4 TRGO event
+@li E9: External line 9
+@li SW: Software trigger
+
+@note: Refer to the timer documentation for details of the TRGO event.
+@note: T3 replaced by T8 and T5 replaced by T15 in some devices.
+@note: this is <b>not</b> valid for the STM32L1 family.
+@note: only used if bit TEN2 is set (DAC channel 1 trigger enabled).
+@{*/
+#define DAC_CR_TSEL1_T6 (0x0 << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_T3 (0x1 << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_T8 (0x1 << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_T7 (0x2 << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_T5 (0x3 << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_T15 (0x3 << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_T2 (0x4 << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_T4 (0x5 << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_E9 (0x6 << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_SW (0x7 << DAC_CR_TSEL1_SHIFT)
+/**@}*/
+
+/* TEN1: DAC channel1 trigger enable */
+#define DAC_CR_TEN1 (1 << 2)
+
+/* BOFF1: DAC channel1 output buffer disable */
+#define DAC_CR_BOFF1 (1 << 1)
+
+/* EN1: DAC channel1 enable */
+#define DAC_CR_EN1 (1 << 0)
+
+
+/* --- DAC_SWTRIGR values -------------------------------------------------- */
+
+/* SWTRIG2: DAC channel2 software trigger */
+#define DAC_SWTRIGR_SWTRIG2 (1 << 1)
+
+/* SWTRIG1: DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG1 (1 << 0)
+
+
+/* --- DAC_DHR12R1 values -------------------------------------------------- */
+#define DAC_DHR12R1_DACC1DHR_LSB (1 << 0)
+#define DAC_DHR12R1_DACC1DHR_MSK (0x0FFF << 0)
+
+
+/* --- DAC_DHR12L1 values -------------------------------------------------- */
+#define DAC_DHR12L1_DACC1DHR_LSB (1 << 4)
+#define DAC_DHR12L1_DACC1DHR_MSK (0x0FFF << 4)
+
+
+/* --- DAC_DHR8R1 values --------------------------------------------------- */
+#define DAC_DHR8R1_DACC1DHR_LSB (1 << 0)
+#define DAC_DHR8R1_DACC1DHR_MSK (0x00FF << 0)
+
+
+/* --- DAC_DHR12R2 values -------------------------------------------------- */
+#define DAC_DHR12R2_DACC2DHR_LSB (1 << 0)
+#define DAC_DHR12R2_DACC2DHR_MSK (0x00FFF << 0)
+
+
+/* --- DAC_DHR12L2 values -------------------------------------------------- */
+#define DAC_DHR12L2_DACC2DHR_LSB (1 << 4)
+#define DAC_DHR12L2_DACC2DHR_MSK (0x0FFF << 4)
+
+
+/* --- DAC_DHR8R2 values --------------------------------------------------- */
+#define DAC_DHR8R2_DACC2DHR_LSB (1 << 0)
+#define DAC_DHR8R2_DACC2DHR_MSK (0x00FF << 0)
+
+
+/* --- DAC_DHR12RD values -------------------------------------------------- */
+#define DAC_DHR12RD_DACC2DHR_LSB (1 << 16)
+#define DAC_DHR12RD_DACC2DHR_MSK (0x0FFF << 16)
+#define DAC_DHR12RD_DACC1DHR_LSB (1 << 0)
+#define DAC_DHR12RD_DACC1DHR_MSK (0x0FFF << 0)
+
+
+/* --- DAC_DHR12LD values -------------------------------------------------- */
+#define DAC_DHR12LD_DACC2DHR_LSB (1 << 16)
+#define DAC_DHR12LD_DACC2DHR_MSK (0x0FFF << 20)
+#define DAC_DHR12LD_DACC1DHR_LSB (1 << 0)
+#define DAC_DHR12LD_DACC1DHR_MSK (0x0FFF << 4)
+
+
+/* --- DAC_DHR8RD values --------------------------------------------------- */
+#define DAC_DHR8RD_DACC2DHR_LSB (1 << 8)
+#define DAC_DHR8RD_DACC2DHR_MSK (0x00FF << 8)
+#define DAC_DHR8RD_DACC1DHR_LSB (1 << 0)
+#define DAC_DHR8RD_DACC1DHR_MSK (0x00FF << 0)
+
+
+/* --- DAC_DOR1 values ----------------------------------------------------- */
+#define DAC_DOR1_DACC1DOR_LSB (1 << 0)
+#define DAC_DOR1_DACC1DOR_MSK (0x0FFF << 0)
+
+
+/* --- DAC_DOR2 values ----------------------------------------------------- */
+#define DAC_DOR2_DACC2DOR_LSB (1 << 0)
+#define DAC_DOR2_DACC2DOR_MSK (0x0FFF << 0)
+
+/** DAC channel identifier */
+typedef enum {
+ CHANNEL_1, CHANNEL_2, CHANNEL_D
+} data_channel;
+
+/** DAC data size (8/12 bits), alignment (right/left) */
+typedef enum {
+ RIGHT8, RIGHT12, LEFT12
+} data_align;
+
+/* --- Function prototypes ------------------------------------------------- */
+
+BEGIN_DECLS
+
+void dac_enable(data_channel dac_channel);
+void dac_disable(data_channel dac_channel);
+void dac_buffer_enable(data_channel dac_channel);
+void dac_buffer_disable(data_channel dac_channel);
+void dac_dma_enable(data_channel dac_channel);
+void dac_dma_disable(data_channel dac_channel);
+void dac_trigger_enable(data_channel dac_channel);
+void dac_trigger_disable(data_channel dac_channel);
+void dac_set_trigger_source(u32 dac_trig_src);
+void dac_set_waveform_generation(u32 dac_wave_ens);
+void dac_disable_waveform_generation(data_channel dac_channel);
+void dac_set_waveform_characteristics(u32 dac_mamp);
+void dac_load_data_buffer_single(u32 dac_data, data_align dac_data_format, data_channel dac_channel);
+void dac_load_data_buffer_dual(u32 dac_data1, u32 dac_data2, data_align dac_data_format);
+void dac_software_trigger(data_channel dac_channel);
+
+END_DECLS
+
+#endif
+/**@}*/
+
diff --git a/include/libopencm3/stm32/common/dma_common_f13.h b/include/libopencm3/stm32/common/dma_common_f13.h
new file mode 100644
index 0000000..964bdf1
--- /dev/null
+++ b/include/libopencm3/stm32/common/dma_common_f13.h
@@ -0,0 +1,388 @@
+/** @addtogroup dma_defines */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
+ * Copyright (C) 2012 Piotr Esden-Tempski <piotr@esden.net>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/**@{*/
+
+#ifndef LIBOPENCM3_DMA_COMMON_F13_H
+#define LIBOPENCM3_DMA_COMMON_F13_H
+
+#include <libopencm3/cm3/common.h>
+
+/* --- Convenience macros -------------------------------------------------- */
+
+/* DMA register base adresses (for convenience) */
+#define DMA1 DMA1_BASE
+#define DMA2 DMA2_BASE
+
+/* --- DMA registers ------------------------------------------------------- */
+
+/* DMA interrupt status register (DMAx_ISR) */
+#define DMA_ISR(dma_base) MMIO32(dma_base + 0x00)
+#define DMA1_ISR DMA_ISR(DMA1)
+#define DMA2_ISR DMA_ISR(DMA2)
+
+/* DMA interrupt flag clear register (DMAx_IFCR) */
+#define DMA_IFCR(dma_base) MMIO32(dma_base + 0x04)
+#define DMA1_IFCR DMA_IFCR(DMA1)
+#define DMA2_IFCR DMA_IFCR(DMA2)
+
+/* DMA channel configuration register (DMAx_CCRy) */
+#define DMA_CCR(dma_base, channel) MMIO32(dma_base + 0x08 + \
+ (0x14 * ((channel) - 1)))
+
+#define DMA1_CCR(channel) DMA_CCR(DMA1, channel)
+#define DMA1_CCR1 DMA1_CCR(DMA_CHANNEL1)
+#define DMA1_CCR2 DMA1_CCR(DMA_CHANNEL2)
+#define DMA1_CCR3 DMA1_CCR(DMA_CHANNEL3)
+#define DMA1_CCR4 DMA1_CCR(DMA_CHANNEL4)
+#define DMA1_CCR5 DMA1_CCR(DMA_CHANNEL5)
+#define DMA1_CCR6 DMA1_CCR(DMA_CHANNEL6)
+#define DMA1_CCR7 DMA1_CCR(DMA_CHANNEL7)
+
+#define DMA2_CCR(channel) DMA_CCR(DMA2, channel)
+#define DMA2_CCR1 DMA2_CCR(DMA_CHANNEL1)
+#define DMA2_CCR2 DMA2_CCR(DMA_CHANNEL2)
+#define DMA2_CCR3 DMA2_CCR(DMA_CHANNEL3)
+#define DMA2_CCR4 DMA2_CCR(DMA_CHANNEL4)
+#define DMA2_CCR5 DMA2_CCR(DMA_CHANNEL5)
+
+/* DMA number of data register (DMAx_CNDTRy) */
+#define DMA_CNDTR(dma_base, channel) MMIO32(dma_base + 0x0C + \
+ (0x14 * ((channel) - 1)))
+
+#define DMA1_CNDTR(channel) DMA_CNDTR(DMA1, channel)
+#define DMA1_CNDTR1 DMA1_CNDTR(DMA_CHANNEL1)
+#define DMA1_CNDTR2 DMA1_CNDTR(DMA_CHANNEL2)
+#define DMA1_CNDTR3 DMA1_CNDTR(DMA_CHANNEL3)
+#define DMA1_CNDTR4 DMA1_CNDTR(DMA_CHANNEL4)
+#define DMA1_CNDTR5 DMA1_CNDTR(DMA_CHANNEL5)
+#define DMA1_CNDTR6 DMA1_CNDTR(DMA_CHANNEL6)
+#define DMA1_CNDTR7 DMA1_CNDTR(DMA_CHANNEL7)
+
+#define DMA2_CNDTR(channel) DMA_CNDTR(DMA2, channel)
+#define DMA2_CNDTR1 DMA2_CNDTR(DMA_CHANNEL1)
+#define DMA2_CNDTR2 DMA2_CNDTR(DMA_CHANNEL2)
+#define DMA2_CNDTR3 DMA2_CNDTR(DMA_CHANNEL3)
+#define DMA2_CNDTR4 DMA2_CNDTR(DMA_CHANNEL4)
+#define DMA2_CNDTR5 DMA2_CNDTR(DMA_CHANNEL5)
+
+/* DMA peripheral address register (DMAx_CPARy) */
+#define DMA_CPAR(dma_base, channel) MMIO32(dma_base + 0x10 + \
+ (0x14 * ((channel) - 1)))
+
+#define DMA1_CPAR(channel) DMA_CPAR(DMA1, channel)
+#define DMA1_CPAR1 DMA1_CPAR(DMA_CHANNEL1)
+#define DMA1_CPAR2 DMA1_CPAR(DMA_CHANNEL2)
+#define DMA1_CPAR3 DMA1_CPAR(DMA_CHANNEL3)
+#define DMA1_CPAR4 DMA1_CPAR(DMA_CHANNEL4)
+#define DMA1_CPAR5 DMA1_CPAR(DMA_CHANNEL5)
+#define DMA1_CPAR6 DMA1_CPAR(DMA_CHANNEL6)
+#define DMA1_CPAR7 DMA1_CPAR(DMA_CHANNEL7)
+
+#define DMA2_CPAR(channel) DMA_CPAR(DMA2, channel)
+#define DMA2_CPAR1 DMA2_CPAR(DMA_CHANNEL1)
+#define DMA2_CPAR2 DMA2_CPAR(DMA_CHANNEL2)
+#define DMA2_CPAR3 DMA2_CPAR(DMA_CHANNEL3)
+#define DMA2_CPAR4 DMA2_CPAR(DMA_CHANNEL4)
+#define DMA2_CPAR5 DMA2_CPAR(DMA_CHANNEL5)
+
+/* DMA memory address register (DMAx_CMARy) */
+
+#define DMA_CMAR(dma_base, channel) MMIO32(dma_base + 0x14 + \
+ (0x14 * ((channel) - 1)))
+
+#define DMA1_CMAR(channel) DMA_CMAR(DMA1, channel)
+#define DMA1_CMAR1 DMA1_CMAR(DMA_CHANNEL1)
+#define DMA1_CMAR2 DMA1_CMAR(DMA_CHANNEL2)
+#define DMA1_CMAR3 DMA1_CMAR(DMA_CHANNEL3)
+#define DMA1_CMAR4 DMA1_CMAR(DMA_CHANNEL4)
+#define DMA1_CMAR5 DMA1_CMAR(DMA_CHANNEL5)
+#define DMA1_CMAR6 DMA1_CMAR(DMA_CHANNEL6)
+#define DMA1_CMAR7 DMA1_CMAR(DMA_CHANNEL7)
+
+#define DMA2_CMAR(channel) DMA_CMAR(DMA2, channel)
+#define DMA2_CMAR1 DMA2_CMAR(DMA_CHANNEL1)
+#define DMA2_CMAR2 DMA2_CMAR(DMA_CHANNEL2)
+#define DMA2_CMAR3 DMA2_CMAR(DMA_CHANNEL3)
+#define DMA2_CMAR4 DMA2_CMAR(DMA_CHANNEL4)
+#define DMA2_CMAR5 DMA2_CMAR(DMA_CHANNEL5)
+
+/* --- DMA_ISR values ------------------------------------------------------ */
+
+/* --- DMA Interrupt Flag offset values ------------------------------------- */
+/* These are based on every interrupt flag and flag clear being at the same relative location */
+/** @defgroup dma_if_offset DMA Interrupt Flag Offsets within channel flag group.
+@ingroup dma_defines
+
+@{*/
+/** Transfer Error Interrupt Flag */
+#define DMA_TEIF (1 << 3)
+/** Half Transfer Interrupt Flag */
+#define DMA_HTIF (1 << 2)
+/** Transfer Complete Interrupt Flag */
+#define DMA_TCIF (1 << 1)
+/** Global Interrupt Flag */
+#define DMA_GIF (1 << 0)
+/**@}*/
+
+/* Offset within interrupt status register to start of channel interrupt flag field */
+#define DMA_FLAG_OFFSET(channel) (4*(channel - 1))
+#define DMA_FLAGS (DMA_TEIF | DMA_TCIF | DMA_HTIF | DMA_GIF)
+#define DMA_ISR_MASK(channel) DMA_FLAGS << DMA_FLAG_OFFSET(channel)
+
+/* TEIF: Transfer error interrupt flag */
+#define DMA_ISR_TEIF_BIT DMA_ISR_TEIF
+#define DMA_ISR_TEIF(channel) (DMA_ISR_TEIF_BIT << DMA_FLAG_OFFSET(channel)))
+
+#define DMA_ISR_TEIF1 DMA_ISR_TEIF(DMA_CHANNEL1)
+#define DMA_ISR_TEIF2 DMA_ISR_TEIF(DMA_CHANNEL2)
+#define DMA_ISR_TEIF3 DMA_ISR_TEIF(DMA_CHANNEL3)
+#define DMA_ISR_TEIF4 DMA_ISR_TEIF(DMA_CHANNEL4)
+#define DMA_ISR_TEIF5 DMA_ISR_TEIF(DMA_CHANNEL5)
+#define DMA_ISR_TEIF6 DMA_ISR_TEIF(DMA_CHANNEL6)
+#define DMA_ISR_TEIF7 DMA_ISR_TEIF(DMA_CHANNEL7)
+
+/* HTIF: Half transfer interrupt flag */
+#define DMA_ISR_HTIF_BIT DMA_HTIF
+#define DMA_ISR_HTIF(channel) (DMA_ISR_HTIF_BIT << DMA_FLAG_OFFSET(channel)))
+
+#define DMA_ISR_HTIF1 DMA_ISR_HTIF(DMA_CHANNEL1)
+#define DMA_ISR_HTIF2 DMA_ISR_HTIF(DMA_CHANNEL2)
+#define DMA_ISR_HTIF3 DMA_ISR_HTIF(DMA_CHANNEL3)
+#define DMA_ISR_HTIF4 DMA_ISR_HTIF(DMA_CHANNEL4)
+#define DMA_ISR_HTIF5 DMA_ISR_HTIF(DMA_CHANNEL5)
+#define DMA_ISR_HTIF6 DMA_ISR_HTIF(DMA_CHANNEL6)
+#define DMA_ISR_HTIF7 DMA_ISR_HTIF(DMA_CHANNEL7)
+
+/* TCIF: Transfer complete interrupt flag */
+#define DMA_ISR_TCIF_BIT DMA_TCIF
+#define DMA_ISR_TCIF(channel) (DMA_ISR_TCIF_BIT << (DMA_FLAG_OFFSET(channel)))
+
+#define DMA_ISR_TCIF1 DMA_ISR_TCIF(DMA_CHANNEL1)
+#define DMA_ISR_TCIF2 DMA_ISR_TCIF(DMA_CHANNEL2)
+#define DMA_ISR_TCIF3 DMA_ISR_TCIF(DMA_CHANNEL3)
+#define DMA_ISR_TCIF4 DMA_ISR_TCIF(DMA_CHANNEL4)
+#define DMA_ISR_TCIF5 DMA_ISR_TCIF(DMA_CHANNEL5)
+#define DMA_ISR_TCIF6 DMA_ISR_TCIF(DMA_CHANNEL6)
+#define DMA_ISR_TCIF7 DMA_ISR_TCIF(DMA_CHANNEL7)
+
+/* GIF: Global interrupt flag */
+#define DMA_ISR_GIF_BIT DMA_GIF
+#define DMA_ISR_GIF(channel) (DMA_ISR_GIF_BIT << (DMA_FLAG_OFFSET(channel)))
+
+#define DMA_ISR_GIF1 DMA_ISR_GIF(DMA_CHANNEL1)
+#define DMA_ISR_GIF2 DMA_ISR_GIF(DMA_CHANNEL2)
+#define DMA_ISR_GIF3 DMA_ISR_GIF(DMA_CHANNEL3)
+#define DMA_ISR_GIF4 DMA_ISR_GIF(DMA_CHANNEL4)
+#define DMA_ISR_GIF5 DMA_ISR_GIF(DMA_CHANNEL5)
+#define DMA_ISR_GIF6 DMA_ISR_GIF(DMA_CHANNEL6)
+#define DMA_ISR_GIF7 DMA_ISR_GIF(DMA_CHANNEL7)
+
+/* --- DMA_IFCR values ----------------------------------------------------- */
+
+/* CTEIF: Transfer error clear */
+#define DMA_IFCR_CTEIF_BIT DMA_TEIF
+#define DMA_IFCR_CTEIF(channel) (DMA_IFCR_CTEIF_BIT << (DMA_FLAG_OFFSET(channel)))
+
+#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF(DMA_CHANNEL1)
+#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF(DMA_CHANNEL2)
+#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF(DMA_CHANNEL3)
+#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF(DMA_CHANNEL4)
+#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF(DMA_CHANNEL5)
+#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF(DMA_CHANNEL6)
+#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF(DMA_CHANNEL7)
+
+/* CHTIF: Half transfer clear */
+#define DMA_IFCR_CHTIF_BIT DMA_HTIF
+#define DMA_IFCR_CHTIF(channel) (DMA_IFCR_CHTIF_BIT << (DMA_FLAG_OFFSET(channel)))
+
+#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF(DMA_CHANNEL1)
+#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF(DMA_CHANNEL2)
+#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF(DMA_CHANNEL3)
+#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF(DMA_CHANNEL4)
+#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF(DMA_CHANNEL5)
+#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF(DMA_CHANNEL6)
+#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF(DMA_CHANNEL7)
+
+/* CTCIF: Transfer complete clear */
+#define DMA_IFCR_CTCIF_BIT DMA_TCIF
+#define DMA_IFCR_CTCIF(channel) (DMA_IFCR_CTCIF_BIT << (DMA_FLAG_OFFSET(channel)))
+
+#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF(DMA_CHANNEL1)
+#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF(DMA_CHANNEL2)
+#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF(DMA_CHANNEL3)
+#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF(DMA_CHANNEL4)
+#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF(DMA_CHANNEL5)
+#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF(DMA_CHANNEL6)
+#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF(DMA_CHANNEL7)
+
+/* CGIF: Global interrupt clear */
+#define DMA_IFCR_CGIF_BIT DMA_GIF
+#define DMA_IFCR_CGIF(channel) (DMA_IFCR_CGIF_BIT << (DMA_FLAG_OFFSET(channel)))
+
+#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF(DMA_CHANNEL1)
+#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF(DMA_CHANNEL2)
+#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF(DMA_CHANNEL3)
+#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF(DMA_CHANNEL4)
+#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF(DMA_CHANNEL5)
+#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF(DMA_CHANNEL6)
+#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF(DMA_CHANNEL7)
+
+/* Clear interrupts mask */
+#define DMA_IFCR_CIF_BIT 0xF
+#define DMA_IFCR_CIF(channel) (DMA_IFCR_CIF_BIT << (DMA_FLAG_OFFSET(channel)))
+
+#define DMA_IFCR_CIF1 DMA_IFCR_CIF(DMA_CHANNEL1)
+#define DMA_IFCR_CIF2 DMA_IFCR_CIF(DMA_CHANNEL2)
+#define DMA_IFCR_CIF3 DMA_IFCR_CIF(DMA_CHANNEL3)
+#define DMA_IFCR_CIF4 DMA_IFCR_CIF(DMA_CHANNEL4)
+#define DMA_IFCR_CIF5 DMA_IFCR_CIF(DMA_CHANNEL5)
+#define DMA_IFCR_CIF6 DMA_IFCR_CIF(DMA_CHANNEL6)
+#define DMA_IFCR_CIF7 DMA_IFCR_CIF(DMA_CHANNEL7)
+
+/* --- DMA_CCRx generic values --------------------------------------------- */
+
+/* MEM2MEM: Memory to memory mode */
+#define DMA_CCR_MEM2MEM (1 << 14)
+
+/* PL[13:12]: Channel priority level */
+/** @defgroup dma_ch_pri DMA Channel Priority Levels
+@ingroup dma_defines
+
+@{*/
+#define DMA_CCR_PL_LOW (0x0 << 12)
+#define DMA_CCR_PL_MEDIUM (0x1 << 12)
+#define DMA_CCR_PL_HIGH (0x2 << 12)
+#define DMA_CCR_PL_VERY_HIGH (0x3 << 12)
+/**@}*/
+#define DMA_CCR_PL_MASK (0x3 << 12)
+#define DMA_CCR_PL_SHIFT 12
+
+/* MSIZE[11:10]: Memory size */
+/** @defgroup dma_ch_memwidth DMA Channel Memory Word Width
+@ingroup dma_defines
+
+@{*/
+#define DMA_CCR_MSIZE_8BIT (0x0 << 10)
+#define DMA_CCR_MSIZE_16BIT (0x1 << 10)
+#define DMA_CCR_MSIZE_32BIT (0x2 << 10)
+/**@}*/
+#define DMA_CCR_MSIZE_MASK (0x3 << 10)
+#define DMA_CCR_MSIZE_SHIFT 10
+
+/* PSIZE[9:8]: Peripheral size */
+/** @defgroup dma_ch_perwidth DMA Channel Peripheral Word Width
+@ingroup dma_defines
+
+@{*/
+#define DMA_CCR_PSIZE_8BIT (0x0 << 8)
+#define DMA_CCR_PSIZE_16BIT (0x1 << 8)
+#define DMA_CCR_PSIZE_32BIT (0x2 << 8)
+/**@}*/
+#define DMA_CCR_PSIZE_MASK (0x3 << 8)
+#define DMA_CCR_PSIZE_SHIFT 8
+
+/* MINC: Memory increment mode */
+#define DMA_CCR_MINC (1 << 7)
+
+/* PINC: Peripheral increment mode */
+#define DMA_CCR_PINC (1 << 6)
+
+/* CIRC: Circular mode */
+#define DMA_CCR_CIRC (1 << 5)
+
+/* DIR: Data transfer direction */
+#define DMA_CCR_DIR (1 << 4)
+
+/* TEIE: Transfer error interrupt enable */
+#define DMA_CCR_TEIE (1 << 3)
+
+/* HTIE: Half transfer interrupt enable */
+#define DMA_CCR_HTIE (1 << 2)
+
+/* TCIE: Transfer complete interrupt enable */
+#define DMA_CCR_TCIE (1 << 1)
+
+/* EN: Channel enable */
+#define DMA_CCR_EN (1 << 0)
+
+/* --- DMA_CNDTRx values --------------------------------------------------- */
+
+/* NDT[15:0]: Number of data to transfer */
+
+/* --- DMA_CPARx values ---------------------------------------------------- */
+
+/* PA[31:0]: Peripheral address */
+
+/* --- DMA_CMARx values ---------------------------------------------------- */
+
+/* MA[31:0]: Memory address */
+
+/* --- Generic values ------------------------------------------------------ */
+
+/** @defgroup dma_ch DMA Channel Number
+@ingroup dma_defines
+
+@{*/
+#define DMA_CHANNEL1 1
+#define DMA_CHANNEL2 2
+#define DMA_CHANNEL3 3
+#define DMA_CHANNEL4 4
+#define DMA_CHANNEL5 5
+#define DMA_CHANNEL6 6
+#define DMA_CHANNEL7 7
+/**@}*/
+
+/* --- function prototypes ------------------------------------------------- */
+
+BEGIN_DECLS
+
+void dma_channel_reset(u32 dma, u8 channel);
+void dma_clear_interrupt_flags(u32 dma, u8 channel, u32 interrupts);
+bool dma_get_interrupt_flag(u32 dma, u8 channel, u32 interrupts);
+void dma_enable_mem2mem_mode(u32 dma, u8 channel);
+void dma_set_priority(u32 dma, u8 channel, u32 prio);
+void dma_set_memory_size(u32 dma, u8 channel, u32 mem_size);
+void dma_set_peripheral_size(u32 dma, u8 channel, u32 peripheral_size);
+void dma_enable_memory_increment_mode(u32 dma, u8 channel);
+void dma_disable_memory_increment_mode(u32 dma, u8 channel);
+void dma_enable_peripheral_increment_mode(u32 dma, u8 channel);
+void dma_disable_peripheral_increment_mode(u32 dma, u8 channel);
+void dma_enable_circular_mode(u32 dma, u8 channel);
+void dma_set_read_from_peripheral(u32 dma, u8 channel);
+void dma_set_read_from_memory(u32 dma, u8 channel);
+void dma_enable_transfer_error_interrupt(u32 dma, u8 channel);
+void dma_disable_transfer_error_interrupt(u32 dma, u8 channel);
+void dma_enable_half_transfer_interrupt(u32 dma, u8 channel);
+void dma_disable_half_transfer_interrupt(u32 dma, u8 channel);
+void dma_enable_transfer_complete_interrupt(u32 dma, u8 channel);
+void dma_disable_transfer_complete_interrupt(u32 dma, u8 channel);
+void dma_enable_channel(u32 dma, u8 channel);
+void dma_disable_channel(u32 dma, u8 channel);
+void dma_set_peripheral_address(u32 dma, u8 channel, u32 address);
+void dma_set_memory_address(u32 dma, u8 channel, u32 address);
+void dma_set_number_of_data(u32 dma, u8 channel, u16 number);
+
+END_DECLS
+
+#endif
+/**@}*/
+
diff --git a/include/libopencm3/stm32/common/dma_common_f24.h b/include/libopencm3/stm32/common/dma_common_f24.h
new file mode 100644
index 0000000..3db3d26
--- /dev/null
+++ b/include/libopencm3/stm32/common/dma_common_f24.h
@@ -0,0 +1,604 @@
+/** @addtogroup dma_defines */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
+ * Copyright (C) 2012 Ken Sarkies <ksarkies@internode.on.net>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA DMA.H */
+
+#ifndef LIBOPENCM3_DMA_COMMON_F24_H
+#define LIBOPENCM3_DMA_COMMON_F24_H
+
+/**@{*/
+
+#include <libopencm3/cm3/common.h>
+
+/* --- Convenience macros -------------------------------------------------- */
+
+/* DMA controller base addresses (for convenience) */
+#define DMA1 DMA1_BASE
+#define DMA2 DMA2_BASE
+
+/* DMA stream base addresses (for API parameters) */
+/** @defgroup dma_st_number DMA Stream Number
+@ingroup STM32F4xx_dma_defines
+
+@{*/
+#define DMA_STREAM0 0
+#define DMA_STREAM1 1
+#define DMA_STREAM2 2
+#define DMA_STREAM3 3
+#define DMA_STREAM4 4
+#define DMA_STREAM5 5
+#define DMA_STREAM6 6
+#define DMA_STREAM7 7
+/**@}*/
+
+#define DMA_STREAM(port, n) ((port) + 0x10 + (24 * (n)))
+#define DMA1_STREAM(n) DMA_STREAM(DMA1, n)
+#define DMA2_STREAM(n) DMA_STREAM(DMA2, n)
+
+#define DMA1_STREAM0 DMA1_STREAM(0)
+#define DMA1_STREAM1 DMA1_STREAM(1)
+#define DMA1_STREAM2 DMA1_STREAM(2)
+#define DMA1_STREAM3 DMA1_STREAM(3)
+#define DMA1_STREAM4 DMA1_STREAM(4)
+#define DMA1_STREAM5 DMA1_STREAM(5)
+#define DMA1_STREAM6 DMA1_STREAM(6)
+#define DMA1_STREAM7 DMA1_STREAM(7)
+
+#define DMA2_STREAM0 DMA2_STREAM(0)
+#define DMA2_STREAM1 DMA2_STREAM(1)
+#define DMA2_STREAM2 DMA2_STREAM(2)
+#define DMA2_STREAM3 DMA2_STREAM(3)
+#define DMA2_STREAM4 DMA2_STREAM(4)
+#define DMA2_STREAM5 DMA2_STREAM(5)
+#define DMA2_STREAM6 DMA2_STREAM(6)
+#define DMA2_STREAM7 DMA2_STREAM(7)
+
+/* --- DMA controller registers -------------------------------------------- */
+
+/* DMA low interrupt status register (DMAx_LISR) */
+#define DMA_LISR(port) MMIO32(port + 0x00)
+#define DMA1_LISR DMA_LISR(DMA1)
+#define DMA2_LISR DMA_LISR(DMA2)
+
+/* DMA high interrupt status register (DMAx_HISR) */
+#define DMA_HISR(port) MMIO32(port + 0x04)
+#define DMA1_HISR DMA_HISR(DMA1)
+#define DMA2_HISR DMA_HISR(DMA2)
+
+/* DMA low interrupt flag clear register (DMAx_LIFCR) */
+#define DMA_LIFCR(port) MMIO32(port + 0x08)
+#define DMA1_LIFCR DMA_LIFCR(DMA1)
+#define DMA2_LIFCR DMA_LIFCR(DMA2)
+
+/* DMA high interrupt flag clear register (DMAx_HIFCR) */
+#define DMA_HIFCR(port) MMIO32(port + 0x0C)
+#define DMA1_HIFCR DMA_HIFCR(DMA1)
+#define DMA2_HIFCR DMA_HIFCR(DMA2)
+
+/* --- DMA stream registers ------------------------------------------------ */
+
+/* DMA Stream x configuration register (DMA_SxCR) */
+#define DMA_SCR(port, n) MMIO32(DMA_STREAM(port, n) + 0x00)
+#define DMA1_SCR(n) DMA_SCR(DMA1, n)
+#define DMA2_SCR(n) DMA_SCR(DMA2, n)
+
+#define DMA1_S0CR DMA1_SCR(0)
+#define DMA1_S1CR DMA1_SCR(1)
+#define DMA1_S2CR DMA1_SCR(2)
+#define DMA1_S3CR DMA1_SCR(3)
+#define DMA1_S4CR DMA1_SCR(4)
+#define DMA1_S5CR DMA1_SCR(5)
+#define DMA1_S6CR DMA1_SCR(6)
+#define DMA1_S7CR DMA1_SCR(7)
+
+#define DMA2_S0CR DMA2_SCR(0)
+#define DMA2_S1CR DMA2_SCR(1)
+#define DMA2_S2CR DMA2_SCR(2)
+#define DMA2_S3CR DMA2_SCR(3)
+#define DMA2_S4CR DMA2_SCR(4)
+#define DMA2_S5CR DMA2_SCR(5)
+#define DMA2_S6CR DMA2_SCR(6)
+#define DMA2_S7CR DMA2_SCR(7)
+
+/* DMA Stream x number of data register (DMA_SxNDTR) */
+#define DMA_SNDTR(port, n) MMIO32(DMA_STREAM(port, n) + 0x04)
+#define DMA1_SNDTR(n) DMA_SNDTR(DMA1, n)
+#define DMA2_SNDTR(n) DMA_SNDTR(DMA2, n)
+
+#define DMA1_S0NDTR DMA1_SNDTR(0)
+#define DMA1_S1NDTR DMA1_SNDTR(1)
+#define DMA1_S2NDTR DMA1_SNDTR(2)
+#define DMA1_S3NDTR DMA1_SNDTR(3)
+#define DMA1_S4NDTR DMA1_SNDTR(4)
+#define DMA1_S5NDTR DMA1_SNDTR(5)
+#define DMA1_S6NDTR DMA1_SNDTR(6)
+#define DMA1_S7NDTR DMA1_SNDTR(7)
+
+#define DMA2_S0NDTR DMA2_SNDTR(0)
+#define DMA2_S1NDTR DMA2_SNDTR(1)
+#define DMA2_S2NDTR DMA2_SNDTR(2)
+#define DMA2_S3NDTR DMA2_SNDTR(3)
+#define DMA2_S4NDTR DMA2_SNDTR(4)
+#define DMA2_S5NDTR DMA2_SNDTR(5)
+#define DMA2_S6NDTR DMA2_SNDTR(6)
+#define DMA2_S7NDTR DMA2_SNDTR(7)
+
+/* DMA Stream x peripheral address register (DMA_SxPAR) */
+#define DMA_SPAR(port, n) *(volatile void **)(DMA_STREAM(port, n) + 0x08)
+#define DMA1_SPAR(n) DMA_SPAR(DMA1, n)
+#define DMA2_SPAR(n) DMA_SPAR(DMA2, n)
+
+#define DMA1_S0PAR DMA1_SPAR(0)
+#define DMA1_S1PAR DMA1_SPAR(1)
+#define DMA1_S2PAR DMA1_SPAR(2)
+#define DMA1_S3PAR DMA1_SPAR(3)
+#define DMA1_S4PAR DMA1_SPAR(4)
+#define DMA1_S5PAR DMA1_SPAR(5)
+#define DMA1_S6PAR DMA1_SPAR(6)
+#define DMA1_S7PAR DMA1_SPAR(7)
+
+#define DMA2_S0PAR DMA2_SPAR(0)
+#define DMA2_S1PAR DMA2_SPAR(1)
+#define DMA2_S2PAR DMA2_SPAR(2)
+#define DMA2_S3PAR DMA2_SPAR(3)
+#define DMA2_S4PAR DMA2_SPAR(4)
+#define DMA2_S5PAR DMA2_SPAR(5)
+#define DMA2_S6PAR DMA2_SPAR(6)
+#define DMA2_S7PAR DMA2_SPAR(7)
+
+/* DMA Stream x memory address 0 register (DMA_SxM0AR) */
+#define DMA_SM0AR(port, n) *(volatile void **)(DMA_STREAM(port, n) + 0x0c)
+#define DMA1_SM0AR(n) DMA_SM0AR(DMA1, n)
+#define DMA2_SM0AR(n) DMA_SM0AR(DMA2, n)
+
+#define DMA1_S0M0AR DMA1_SM0AR(0)
+#define DMA1_S1M0AR DMA1_SM0AR(1)
+#define DMA1_S2M0AR DMA1_SM0AR(2)
+#define DMA1_S3M0AR DMA1_SM0AR(3)
+#define DMA1_S4M0AR DMA1_SM0AR(4)
+#define DMA1_S5M0AR DMA1_SM0AR(5)
+#define DMA1_S6M0AR DMA1_SM0AR(6)
+#define DMA1_S7M0AR DMA1_SM0AR(7)
+
+#define DMA2_S0M0AR DMA2_SM0AR(0)
+#define DMA2_S1M0AR DMA2_SM0AR(1)
+#define DMA2_S2M0AR DMA2_SM0AR(2)
+#define DMA2_S3M0AR DMA2_SM0AR(3)
+#define DMA2_S4M0AR DMA2_SM0AR(4)
+#define DMA2_S5M0AR DMA2_SM0AR(5)
+#define DMA2_S6M0AR DMA2_SM0AR(6)
+#define DMA2_S7M0AR DMA2_SM0AR(7)
+
+/* DMA Stream x memory address 1 register (DMA_SxM1AR) */
+#define DMA_SM1AR(port, n) *(volatile void **)(DMA_STREAM(port, n) + 0x10)
+#define DMA1_SM1AR(n) DMA_SM1AR(DMA1, n)
+#define DMA2_SM1AR(n) DMA_SM1AR(DMA2, n)
+
+#define DMA1_S0M1AR DMA1_SM1AR(0)
+#define DMA1_S1M1AR DMA1_SM1AR(1)
+#define DMA1_S2M1AR DMA1_SM1AR(2)
+#define DMA1_S3M1AR DMA1_SM1AR(3)
+#define DMA1_S4M1AR DMA1_SM1AR(4)
+#define DMA1_S5M1AR DMA1_SM1AR(5)
+#define DMA1_S6M1AR DMA1_SM1AR(6)
+#define DMA1_S7M1AR DMA1_SM1AR(7)
+
+#define DMA2_S0M1AR DMA2_SM1AR(0)
+#define DMA2_S1M1AR DMA2_SM1AR(1)
+#define DMA2_S2M1AR DMA2_SM1AR(2)
+#define DMA2_S3M1AR DMA2_SM1AR(3)
+#define DMA2_S4M1AR DMA2_SM1AR(4)
+#define DMA2_S5M1AR DMA2_SM1AR(5)
+#define DMA2_S6M1AR DMA2_SM1AR(6)
+#define DMA2_S7M1AR DMA2_SM1AR(7)
+
+/* DMA Stream x FIFO control register (DMA_SxFCR) */
+#define DMA_SFCR(port, n) MMIO32(DMA_STREAM(port, n) + 0x14)
+#define DMA1_SFCR(n) DMA_SFCR(DMA1, n)
+#define DMA2_SFCR(n) DMA_SFCR(DMA2, n)
+
+#define DMA1_S0FCR DMA1_SFCR(0)
+#define DMA1_S1FCR DMA1_SFCR(1)
+#define DMA1_S2FCR DMA1_SFCR(2)
+#define DMA1_S3FCR DMA1_SFCR(3)
+#define DMA1_S4FCR DMA1_SFCR(4)
+#define DMA1_S5FCR DMA1_SFCR(5)
+#define DMA1_S6FCR DMA1_SFCR(6)
+#define DMA1_S7FCR DMA1_SFCR(7)
+
+#define DMA2_S0FCR DMA2_SFCR(0)
+#define DMA2_S1FCR DMA2_SFCR(1)
+#define DMA2_S2FCR DMA2_SFCR(2)
+#define DMA2_S3FCR DMA2_SFCR(3)
+#define DMA2_S4FCR DMA2_SFCR(4)
+#define DMA2_S5FCR DMA2_SFCR(5)
+#define DMA2_S6FCR DMA2_SFCR(6)
+#define DMA2_S7FCR DMA2_SFCR(7)
+
+/* --- DMA Interrupt Flag offset values ------------------------------------- */
+
+/* For API parameters. These are based on every interrupt flag and flag clear
+being at the same relative location */
+/** @defgroup dma_if_offset DMA Interrupt Flag Offsets within stream flag group.
+@ingroup dma_defines
+
+@{*/
+/** Transfer Complete Interrupt Flag */
+#define DMA_ISR_TCIF (1 << 5)
+/** Half Transfer Interrupt Flag */
+#define DMA_ISR_HTIF (1 << 4)
+/** Transfer Error Interrupt Flag */
+#define DMA_ISR_TEIF (1 << 3)
+/** Direct Mode Error Interrupt Flag */
+#define DMA_ISR_DMEIF (1 << 2)
+/** FIFO Error Interrupt Flag */
+#define DMA_ISR_FEIF (1 << 0)
+/**@}*/
+
+/* Offset within interrupt status register to start of stream interrupt flag field */
+#define DMA_ISR_OFFSET(stream) (6*(stream & 0x01)+16*((stream & 0x02) >> 1))
+#define DMA_ISR_FLAGS (DMA_ISR_TCIF | DMA_ISR_HTIF | DMA_ISR_TEIF | DMA_ISR_DMEIF | DMA_ISR_FEIF)
+#define DMA_ISR_MASK(stream) DMA_ISR_FLAGS << DMA_ISR_OFFSET(stream)
+
+/* --- DMA_LISR values ----------------------------------------------------- */
+
+#define DMA_LISR_FEIF0 (1 << 0)
+#define DMA_LISR_DMEIF0 (1 << 2)
+#define DMA_LISR_TEIF0 (1 << 3)
+#define DMA_LISR_HTIF0 (1 << 4)
+#define DMA_LISR_TCIF0 (1 << 5)
+
+#define DMA_LISR_FEIF1 (1 << 6)
+#define DMA_LISR_DMEIF1 (1 << 8)
+#define DMA_LISR_TEIF1 (1 << 9)
+#define DMA_LISR_HTIF1 (1 << 10)
+#define DMA_LISR_TCIF1 (1 << 11)
+
+#define DMA_LISR_FEIF2 (1 << 16)
+#define DMA_LISR_DMEIF2 (1 << 18)
+#define DMA_LISR_TEIF2 (1 << 19)
+#define DMA_LISR_HTIF2 (1 << 20)
+#define DMA_LISR_TCIF2 (1 << 21)
+
+#define DMA_LISR_FEIF3 (1 << 22)
+#define DMA_LISR_DMEIF3 (1 << 24)
+#define DMA_LISR_TEIF3 (1 << 25)
+#define DMA_LISR_HTIF3 (1 << 26)
+#define DMA_LISR_TCIF3 (1 << 27)
+
+/* --- DMA_HISR values ----------------------------------------------------- */
+
+#define DMA_HISR_FEIF4 (1 << 0)
+#define DMA_HISR_DMEIF4 (1 << 2)
+#define DMA_HISR_TEIF4 (1 << 3)
+#define DMA_HISR_HTIF4 (1 << 4)
+#define DMA_HISR_TCIF4 (1 << 5)
+
+#define DMA_HISR_FEIF5 (1 << 6)
+#define DMA_HISR_DMEIF5 (1 << 8)
+#define DMA_HISR_TEIF5 (1 << 9)
+#define DMA_HISR_HTIF5 (1 << 10)
+#define DMA_HISR_TCIF5 (1 << 11)
+
+#define DMA_HISR_FEIF6 (1 << 16)
+#define DMA_HISR_DMEIF6 (1 << 18)
+#define DMA_HISR_TEIF6 (1 << 19)
+#define DMA_HISR_HTIF6 (1 << 20)
+#define DMA_HISR_TCIF6 (1 << 21)
+
+#define DMA_HISR_FEIF7 (1 << 22)
+#define DMA_HISR_DMEIF7 (1 << 24)
+#define DMA_HISR_TEIF7 (1 << 25)
+#define DMA_HISR_HTIF7 (1 << 26)
+#define DMA_HISR_TCIF7 (1 << 27)
+
+/* --- DMA_LIFCR values ----------------------------------------------------- */
+
+#define DMA_LIFCR_CFEIF0 (1 << 0)
+#define DMA_LIFCR_CDMEIF0 (1 << 2)
+#define DMA_LIFCR_CTEIF0 (1 << 3)
+#define DMA_LIFCR_CHTIF0 (1 << 4)
+#define DMA_LIFCR_CTCIF0 (1 << 5)
+
+#define DMA_LIFCR_CFEIF1 (1 << 6)
+#define DMA_LIFCR_CDMEIF1 (1 << 8)
+#define DMA_LIFCR_CTEIF1 (1 << 9)
+#define DMA_LIFCR_CHTIF1 (1 << 10)
+#define DMA_LIFCR_CTCIF1 (1 << 11)
+
+#define DMA_LIFCR_CFEIF2 (1 << 16)
+#define DMA_LIFCR_CDMEIF2 (1 << 18)
+#define DMA_LIFCR_CTEIF2 (1 << 19)
+#define DMA_LIFCR_CHTIF2 (1 << 20)
+#define DMA_LIFCR_CTCIF2 (1 << 21)
+
+#define DMA_LIFCR_CFEIF3 (1 << 22)
+#define DMA_LIFCR_CDMEIF3 (1 << 24)
+#define DMA_LIFCR_CTEIF3 (1 << 25)
+#define DMA_LIFCR_CHTIF3 (1 << 26)
+#define DMA_LIFCR_CTCIF3 (1 << 27)
+
+/* --- DMA_HIFCR values ----------------------------------------------------- */
+
+#define DMA_HIFCR_CFEIF4 (1 << 0)
+#define DMA_HIFCR_CDMEIF4 (1 << 2)
+#define DMA_HIFCR_CTEIF4 (1 << 3)
+#define DMA_HIFCR_CHTIF4 (1 << 4)
+#define DMA_HIFCR_CTCIF4 (1 << 5)
+
+#define DMA_HIFCR_CFEIF5 (1 << 6)
+#define DMA_HIFCR_CDMEIF5 (1 << 8)
+#define DMA_HIFCR_CTEIF5 (1 << 9)
+#define DMA_HIFCR_CHTIF5 (1 << 10)
+#define DMA_HIFCR_CTCIF5 (1 << 11)
+
+#define DMA_HIFCR_CFEIF6 (1 << 16)
+#define DMA_HIFCR_CDMEIF6 (1 << 18)
+#define DMA_HIFCR_CTEIF6 (1 << 19)
+#define DMA_HIFCR_CHTIF6 (1 << 20)
+#define DMA_HIFCR_CTCIF6 (1 << 21)
+
+#define DMA_HIFCR_CFEIF7 (1 << 22)
+#define DMA_HIFCR_CDMEIF7 (1 << 24)
+#define DMA_HIFCR_CTEIF7 (1 << 25)
+#define DMA_HIFCR_CHTIF7 (1 << 26)
+#define DMA_HIFCR_CTCIF7 (1 << 27)
+
+/* --- DMA_SxCR values ----------------------------------------------------- */
+
+/* EN: Stream enable */
+#define DMA_SxCR_EN (1 << 0)
+/* DMEIE: Direct Mode error interrupt enable */
+#define DMA_SxCR_DMEIE (1 << 1)
+/* TEIE: Transfer error interrupt enable */
+#define DMA_SxCR_TEIE (1 << 2)
+/* HTIE: Half transfer interrupt enable */
+#define DMA_SxCR_HTIE (1 << 3)
+/* TCIE: Transfer complete interrupt enable */
+#define DMA_SxCR_TCIE (1 << 4)
+/* PFCTRL: Peripheral Flow Controller */
+#define DMA_SxCR_PFCTRL (1 << 5)
+
+/* DIR[7:6]: Data transfer direction */
+/** @defgroup dma_st_dir DMA Stream Data transfer direction
+@ingroup dma_defines
+
+@{*/
+#define DMA_SxCR_DIR_PERIPHERAL_TO_MEM (0 << 6)
+#define DMA_SxCR_DIR_MEM_TO_PERIPHERAL (1 << 6)
+#define DMA_SxCR_DIR_MEM_TO_MEM (2 << 6)
+/**@}*/
+#define DMA_SxCR_DIR_SHIFT 6
+#define DMA_SxCR_DIR_MASK (3 << 6)
+
+/* CIRC: Circular mode */
+#define DMA_SxCR_CIRC (1 << 8)
+/* PINC: Peripheral increment mode */
+#define DMA_SxCR_PINC (1 << 9)
+/* MINC: Memory increment mode */
+#define DMA_SxCR_MINC (1 << 10)
+
+/* PSIZE[12:11]: Peripheral size */
+/** @defgroup dma_st_perwidth DMA Stream Peripheral Word Width
+@ingroup STM32F4xx_dma_defines
+
+@{*/
+#define DMA_SxCR_PSIZE_8BIT (0 << 11)
+#define DMA_SxCR_PSIZE_16BIT (1 << 11)
+#define DMA_SxCR_PSIZE_32BIT (2 << 11)
+/**@}*/
+#define DMA_SxCR_PSIZE_SHIFT 11
+#define DMA_SxCR_PSIZE_MASK (3 << 11)
+
+/* MSIZE[14:13]: Memory size */
+/** @defgroup dma_st_memwidth DMA Stream Memory Word Width
+@ingroup STM32F4xx_dma_defines
+
+@{*/
+#define DMA_SxCR_MSIZE_8BIT (0 << 13)
+#define DMA_SxCR_MSIZE_16BIT (1 << 13)
+#define DMA_SxCR_MSIZE_32BIT (2 << 13)
+/**@}*/
+#define DMA_SxCR_MSIZE_SHIFT 13
+#define DMA_SxCR_MSIZE_MASK (3 << 13)
+
+/* PINCOS: Peripheral increment offset size */
+#define DMA_SxCR_PINCOS (1 << 15)
+
+/* PL[17:16]: Stream priority level */
+/** @defgroup dma_st_pri DMA Stream Priority Levels
+@ingroup dma_defines
+
+@{*/
+#define DMA_SxCR_PL_LOW (0 << 16)
+#define DMA_SxCR_PL_MEDIUM (1 << 16)
+#define DMA_SxCR_PL_HIGH (2 << 16)
+#define DMA_SxCR_PL_VERY_HIGH (3 << 16)
+/**@}*/
+#define DMA_SxCR_PL_SHIFT 16
+#define DMA_SxCR_PL_MASK (3 << 16)
+
+/* DBM: Double buffered mode */
+#define DMA_SxCR_DBM (1 << 18)
+/* CT: Current target (in double buffered mode) */
+#define DMA_SxCR_CT (1 << 19)
+
+/* Bit 20 reserved */
+
+/* PBURST[13:12]: Peripheral Burst Configuration */
+/** @defgroup dma_pburst DMA Peripheral Burst Length
+@ingroup dma_defines
+
+@{*/
+#define DMA_SxCR_PBURST_SINGLE (0 << 21)
+#define DMA_SxCR_PBURST_INCR4 (1 << 21)
+#define DMA_SxCR_PBURST_INCR8 (2 << 21)
+#define DMA_SxCR_PBURST_INCR16 (3 << 21)
+/**@}*/
+#define DMA_SxCR_PBURST_SHIFT 21
+#define DMA_SxCR_PBURST_MASK (3 << 21)
+
+/* MBURST[13:12]: Memory Burst Configuration */
+/** @defgroup dma_mburst DMA Memory Burst Length
+@ingroup STM32F4xx_dma_defines
+
+@{*/
+#define DMA_SxCR_MBURST_SINGLE (0 << 23)
+#define DMA_SxCR_MBURST_INCR4 (1 << 23)
+#define DMA_SxCR_MBURST_INCR8 (2 << 23)
+#define DMA_SxCR_MBURST_INCR16 (3 << 23)
+/**@}*/
+#define DMA_SxCR_MBURST_SHIFT 23
+#define DMA_SxCR_MBURST_MASK (3 << 23)
+
+/* CHSEL[25:27]: Channel Select */
+/** @defgroup dma_ch_sel DMA Channel Select
+@ingroup dma_defines
+
+@{*/
+#define DMA_SxCR_CHSEL_0 (0 << DMA_SxCR_CHSEL_SHIFT)
+#define DMA_SxCR_CHSEL_1 (1 << DMA_SxCR_CHSEL_SHIFT)
+#define DMA_SxCR_CHSEL_2 (2 << DMA_SxCR_CHSEL_SHIFT)
+#define DMA_SxCR_CHSEL_3 (3 << DMA_SxCR_CHSEL_SHIFT)
+#define DMA_SxCR_CHSEL_4 (4 << DMA_SxCR_CHSEL_SHIFT)
+#define DMA_SxCR_CHSEL_5 (5 << DMA_SxCR_CHSEL_SHIFT)
+#define DMA_SxCR_CHSEL_6 (6 << DMA_SxCR_CHSEL_SHIFT)
+#define DMA_SxCR_CHSEL_7 (7 << DMA_SxCR_CHSEL_SHIFT)
+/**@}*/
+#define DMA_SxCR_CHSEL_SHIFT 25
+#define DMA_SxCR_CHSEL_MASK (7 << 25)
+#define DMA_SxCR_CHSEL(n) (n << DMA_SxCR_CHSEL_SHIFT)
+
+/* Reserved [31:28] */
+
+/* --- DMA_SxNDTR values --------------------------------------------------- */
+
+/* DMA_SxNDTR[15:0]: Number of data register. */
+
+/* --- DMA_SxPAR values ---------------------------------------------------- */
+
+/* DMA_SxPAR[31:0]: Peripheral address register. */
+
+/* --- DMA_SxM0AR values --------------------------------------------------- */
+
+/* DMA_SxM0AR[31:0]: Memory 0 address register. */
+
+/* --- DMA_SxM1AR values --------------------------------------------------- */
+
+/* DMA_SxM1AR[31:0]: Memory 1 address register. */
+
+/* --- DMA_SxFCR values ---------------------------------------------------- */
+
+/* FTH[1:0]: FIFO Threshold selection */
+/** @defgroup dma_fifo_thresh FIFO Threshold selection
+@ingroup STM32F4xx_dma_defines
+
+@{*/
+#define DMA_SxFCR_FTH_1_4_FULL (0 << 0)
+#define DMA_SxFCR_FTH_2_4_FULL (1 << 0)
+#define DMA_SxFCR_FTH_3_4_FULL (2 << 0)
+#define DMA_SxFCR_FTH_4_4_FULL (3 << 0)
+/**@}*/
+#define DMA_SxFCR_FTH_SHIFT 0
+#define DMA_SxFCR_FTH_MASK (3 << 0)
+
+/* DMDIS: Direct Mode disable */
+#define DMA_SxFCR_DMDIS (1 << 2)
+
+/* FS[5:3]: FIFO Status */
+/** @defgroup dma_fifo_status FIFO Status
+@ingroup STM32F4xx_dma_defines
+
+@{*/
+#define DMA_SxFCR_FS_LT_1_4_FULL (0 << 0)
+#define DMA_SxFCR_FS_LT_2_4_FULL (1 << 0)
+#define DMA_SxFCR_FS_LT_3_4_FULL (2 << 0)
+#define DMA_SxFCR_FS_LT_4_4_FULL (3 << 0)
+#define DMA_SxFCR_FS_FULL (4 << 3)
+#define DMA_SxFCR_FS_EMPTY (5 << 3)
+/**@}*/
+#define DMA_SxFCR_FS_SHIFT 3
+#define DMA_SxFCR_FS_MASK (7 << 3)
+
+/* [6]: reserved */
+
+/* FEIE[7]: FIFO error interrupt enable */
+#define DMA_SxFCR_FEIE (1 << 7)
+
+/* [31:8]: Reserved */
+
+/* --- Function prototypes ------------------------------------------------- */
+
+BEGIN_DECLS
+
+/*
+ * Note: The F2 and F4 series have a completely new DMA peripheral with different
+ * configuration options.
+ */
+
+void dma_stream_reset(u32 dma, u8 stream);
+void dma_clear_interrupt_flags(u32 dma, u8 stream, u32 interrupts);
+bool dma_get_interrupt_flag(u32 dma, u8 stream, u32 interrupt);
+void dma_set_transfer_mode(u32 dma, u8 stream, u32 direction);
+void dma_set_priority(u32 dma, u8 stream, u32 prio);
+void dma_set_memory_size(u32 dma, u8 stream, u32 mem_size);
+void dma_set_peripheral_size(u32 dma, u8 stream, u32 peripheral_size);
+void dma_enable_memory_increment_mode(u32 dma, u8 stream);
+void dma_disable_memory_increment_mode(u32 dma, u8 channel);
+void dma_enable_peripheral_increment_mode(u32 dma, u8 stream);
+void dma_disable_peripheral_increment_mode(u32 dma, u8 channel);
+void dma_enable_fixed_peripheral_increment_mode(u32 dma, u8 stream);
+void dma_enable_circular_mode(u32 dma, u8 stream);
+void dma_channel_select(u32 dma, u8 stream, u32 channel);
+void dma_channel_select(u32 dma, u8 stream, u32 channel);
+void dma_set_memory_burst(u32 dma, u8 stream, u32 burst);
+void dma_set_peripheral_burst(u32 dma, u8 stream, u32 burst);
+void dma_set_initial_target(u32 dma, u8 stream, u8 memory);
+u8 dma_get_target(u32 dma, u8 stream);
+void dma_enable_double_buffer_mode(u32 dma, u8 stream);
+void dma_disable_double_buffer_mode(u32 dma, u8 stream);
+void dma_set_peripheral_flow_control(u32 dma, u8 stream);
+void dma_set_dma_flow_control(u32 dma, u8 stream);
+void dma_enable_transfer_error_interrupt(u32 dma, u8 stream);
+void dma_disable_transfer_error_interrupt(u32 dma, u8 stream);
+void dma_enable_half_transfer_interrupt(u32 dma, u8 stream);
+void dma_disable_half_transfer_interrupt(u32 dma, u8 stream);
+void dma_enable_transfer_complete_interrupt(u32 dma, u8 stream);
+void dma_disable_transfer_complete_interrupt(u32 dma, u8 stream);
+u32 dma_fifo_status(u32 dma, u8 stream);
+void dma_enable_direct_mode_error_interrupt(u32 dma, u8 stream);
+void dma_disable_direct_mode_error_interrupt(u32 dma, u8 stream);
+void dma_enable_fifo_error_interrupt(u32 dma, u8 stream);
+void dma_disable_fifo_error_interrupt(u32 dma, u8 stream);
+void dma_enable_direct_mode(u32 dma, u8 stream);
+void dma_enable_fifo_mode(u32 dma, u8 stream);
+void dma_set_fifo_threshold(u32 dma, u8 stream, u32 threshold);
+void dma_enable_stream(u32 dma, u8 stream);
+void dma_disable_stream(u32 dma, u8 stream);
+void dma_set_peripheral_address(u32 dma, u8 stream, u32 address);
+void dma_set_memory_address(u32 dma, u8 stream, u32 address);
+void dma_set_memory_address_1(u32 dma, u8 stream, u32 address);
+void dma_set_number_of_data(u32 dma, u8 stream, u16 number);
+
+END_DECLS
+/**@}*/
+#endif
+
diff --git a/include/libopencm3/stm32/common/gpio_common_all.h b/include/libopencm3/stm32/common/gpio_common_all.h
new file mode 100644
index 0000000..b2327e5
--- /dev/null
+++ b/include/libopencm3/stm32/common/gpio_common_all.h
@@ -0,0 +1,73 @@
+/** @addtogroup gpio_defines */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
+ * Copyright (C) 2012 Ken Sarkies <ksarkies@internode.on.net>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA GPIO.H */
+
+#ifndef LIBOPENCM3_GPIO_COMMON_ALL_H
+#define LIBOPENCM3_GPIO_COMMON_ALL_H
+
+/**@{*/
+
+#include <libopencm3/cm3/common.h>
+
+/* --- Convenience macros -------------------------------------------------- */
+
+/* --- GPIO_LCKR values ---------------------------------------------------- */
+
+#define GPIO_LCKK (1 << 16)
+/* GPIO_LCKR[15:0]: LCKy: Port x lock bit y (y = 0..15) */
+
+/* GPIO number definitions (for convenience) */
+/** @defgroup gpio_pin_id GPIO Pin Identifiers
+@ingroup gpio_defines
+
+@{*/
+#define GPIO0 (1 << 0)
+#define GPIO1 (1 << 1)
+#define GPIO2 (1 << 2)
+#define GPIO3 (1 << 3)
+#define GPIO4 (1 << 4)
+#define GPIO5 (1 << 5)
+#define GPIO6 (1 << 6)
+#define GPIO7 (1 << 7)
+#define GPIO8 (1 << 8)
+#define GPIO9 (1 << 9)
+#define GPIO10 (1 << 10)
+#define GPIO11 (1 << 11)
+#define GPIO12 (1 << 12)
+#define GPIO13 (1 << 13)
+#define GPIO14 (1 << 14)
+#define GPIO15 (1 << 15)
+#define GPIO_ALL 0xffff
+/**@}*/
+
+void gpio_set(u32 gpioport, u16 gpios);
+void gpio_clear(u32 gpioport, u16 gpios);
+u16 gpio_get(u32 gpioport, u16 gpios);
+void gpio_toggle(u32 gpioport, u16 gpios);
+u16 gpio_port_read(u32 gpioport);
+void gpio_port_write(u32 gpioport, u16 data);
+void gpio_port_config_lock(u32 gpioport, u16 gpios);
+
+/**@}*/
+#endif
+
diff --git a/include/libopencm3/stm32/common/gpio_common_f24.h b/include/libopencm3/stm32/common/gpio_common_f24.h
new file mode 100644
index 0000000..f8bd4fb
--- /dev/null
+++ b/include/libopencm3/stm32/common/gpio_common_f24.h
@@ -0,0 +1,285 @@
+/** @addtogroup gpio_defines */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
+ * Copyright (C) 2012 Ken Sarkies <ksarkies@internode.on.net>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA GPIO.H */
+
+#ifndef LIBOPENCM3_GPIO_COMMON_F24_H
+#define LIBOPENCM3_GPIO_COMMON_F24_H
+
+/**@{*/
+
+#include <libopencm3/stm32/common/gpio_common_all.h>
+
+/* GPIO port base addresses (for convenience) */
+/** @defgroup gpio_port_id GPIO Port IDs
+@ingroup gpio_defines
+
+@{*/
+#define GPIOA GPIO_PORT_A_BASE
+#define GPIOB GPIO_PORT_B_BASE
+#define GPIOC GPIO_PORT_C_BASE
+#define GPIOD GPIO_PORT_D_BASE
+#define GPIOE GPIO_PORT_E_BASE
+#define GPIOF GPIO_PORT_F_BASE
+#define GPIOG GPIO_PORT_G_BASE
+#define GPIOH GPIO_PORT_H_BASE
+#define GPIOI GPIO_PORT_I_BASE
+/**@}*/
+
+/* --- GPIO registers for STM32F2 and STM32F4 --------------------------- */
+
+/* Port mode register (GPIOx_MODER) */
+#define GPIO_MODER(port) MMIO32(port + 0x00)
+#define GPIOA_MODER GPIO_MODER(GPIOA)
+#define GPIOB_MODER GPIO_MODER(GPIOB)
+#define GPIOC_MODER GPIO_MODER(GPIOC)
+#define GPIOD_MODER GPIO_MODER(GPIOD)
+#define GPIOE_MODER GPIO_MODER(GPIOE)
+#define GPIOF_MODER GPIO_MODER(GPIOF)
+#define GPIOG_MODER GPIO_MODER(GPIOG)
+#define GPIOH_MODER GPIO_MODER(GPIOH)
+#define GPIOI_MODER GPIO_MODER(GPIOI)
+
+/* Port output type register (GPIOx_OTYPER) */
+#define GPIO_OTYPER(port) MMIO32(port + 0x04)
+#define GPIOA_OTYPER GPIO_OTYPER(GPIOA)
+#define GPIOB_OTYPER GPIO_OTYPER(GPIOB)
+#define GPIOC_OTYPER GPIO_OTYPER(GPIOC)
+#define GPIOD_OTYPER GPIO_OTYPER(GPIOD)
+#define GPIOE_OTYPER GPIO_OTYPER(GPIOE)
+#define GPIOF_OTYPER GPIO_OTYPER(GPIOF)
+#define GPIOG_OTYPER GPIO_OTYPER(GPIOG)
+#define GPIOH_OTYPER GPIO_OTYPER(GPIOH)
+#define GPIOI_OTYPER GPIO_OTYPER(GPIOI)
+
+/* Port output speed register (GPIOx_OSPEEDR) */
+#define GPIO_OSPEEDR(port) MMIO32(port + 0x08)
+#define GPIOA_OSPEEDR GPIO_OSPEEDR(GPIOA)
+#define GPIOB_OSPEEDR GPIO_OSPEEDR(GPIOB)
+#define GPIOC_OSPEEDR GPIO_OSPEEDR(GPIOC)
+#define GPIOD_OSPEEDR GPIO_OSPEEDR(GPIOD)
+#define GPIOE_OSPEEDR GPIO_OSPEEDR(GPIOE)
+#define GPIOF_OSPEEDR GPIO_OSPEEDR(GPIOF)
+#define GPIOG_OSPEEDR GPIO_OSPEEDR(GPIOG)
+#define GPIOH_OSPEEDR GPIO_OSPEEDR(GPIOH)
+#define GPIOI_OSPEEDR GPIO_OSPEEDR(GPIOI)
+
+/* Port pull-up/pull-down register (GPIOx_PUPDR) */
+#define GPIO_PUPDR(port) MMIO32(port + 0x0c)
+#define GPIOA_PUPDR GPIO_PUPDR(GPIOA)
+#define GPIOB_PUPDR GPIO_PUPDR(GPIOB)
+#define GPIOC_PUPDR GPIO_PUPDR(GPIOC)
+#define GPIOD_PUPDR GPIO_PUPDR(GPIOD)
+#define GPIOE_PUPDR GPIO_PUPDR(GPIOE)
+#define GPIOF_PUPDR GPIO_PUPDR(GPIOF)
+#define GPIOG_PUPDR GPIO_PUPDR(GPIOG)
+#define GPIOH_PUPDR GPIO_PUPDR(GPIOH)
+#define GPIOI_PUPDR GPIO_PUPDR(GPIOI)
+
+/* Port input data register (GPIOx_IDR) */
+#define GPIO_IDR(port) MMIO32(port + 0x10)
+#define GPIOA_IDR GPIO_IDR(GPIOA)
+#define GPIOB_IDR GPIO_IDR(GPIOB)
+#define GPIOC_IDR GPIO_IDR(GPIOC)
+#define GPIOD_IDR GPIO_IDR(GPIOD)
+#define GPIOE_IDR GPIO_IDR(GPIOE)
+#define GPIOF_IDR GPIO_IDR(GPIOF)
+#define GPIOG_IDR GPIO_IDR(GPIOG)
+#define GPIOH_IDR GPIO_IDR(GPIOH)
+#define GPIOI_IDR GPIO_IDR(GPIOI)
+
+/* Port output data register (GPIOx_ODR) */
+#define GPIO_ODR(port) MMIO32(port + 0x14)
+#define GPIOA_ODR GPIO_ODR(GPIOA)
+#define GPIOB_ODR GPIO_ODR(GPIOB)
+#define GPIOC_ODR GPIO_ODR(GPIOC)
+#define GPIOD_ODR GPIO_ODR(GPIOD)
+#define GPIOE_ODR GPIO_ODR(GPIOE)
+#define GPIOF_ODR GPIO_ODR(GPIOF)
+#define GPIOG_ODR GPIO_ODR(GPIOG)
+#define GPIOH_ODR GPIO_ODR(GPIOH)
+#define GPIOI_ODR GPIO_ODR(GPIOI)
+
+/* Port bit set/reset register (GPIOx_BSRR) */
+#define GPIO_BSRR(port) MMIO32(port + 0x18)
+#define GPIOA_BSRR GPIO_BSRR(GPIOA)
+#define GPIOB_BSRR GPIO_BSRR(GPIOB)
+#define GPIOC_BSRR GPIO_BSRR(GPIOC)
+#define GPIOD_BSRR GPIO_BSRR(GPIOD)
+#define GPIOE_BSRR GPIO_BSRR(GPIOE)
+#define GPIOF_BSRR GPIO_BSRR(GPIOF)
+#define GPIOG_BSRR GPIO_BSRR(GPIOG)
+#define GPIOH_BSRR GPIO_BSRR(GPIOH)
+#define GPIOI_BSRR GPIO_BSRR(GPIOI)
+
+/* Port configuration lock register (GPIOx_LCKR) */
+#define GPIO_LCKR(port) MMIO32(port + 0x1c)
+#define GPIOA_LCKR GPIO_LCKR(GPIOA)
+#define GPIOB_LCKR GPIO_LCKR(GPIOB)
+#define GPIOC_LCKR GPIO_LCKR(GPIOC)
+#define GPIOD_LCKR GPIO_LCKR(GPIOD)
+#define GPIOE_LCKR GPIO_LCKR(GPIOE)
+#define GPIOF_LCKR GPIO_LCKR(GPIOF)
+#define GPIOG_LCKR GPIO_LCKR(GPIOG)
+#define GPIOH_LCKR GPIO_LCKR(GPIOH)
+#define GPIOI_LCKR GPIO_LCKR(GPIOI)
+
+/* Alternate function low register (GPIOx_AFRL) */
+#define GPIO_AFRL(port) MMIO32(port + 0x20)
+#define GPIOA_AFRL GPIO_AFRL(GPIOA)
+#define GPIOB_AFRL GPIO_AFRL(GPIOB)
+#define GPIOC_AFRL GPIO_AFRL(GPIOC)
+#define GPIOD_AFRL GPIO_AFRL(GPIOD)
+#define GPIOE_AFRL GPIO_AFRL(GPIOE)
+#define GPIOF_AFRL GPIO_AFRL(GPIOF)
+#define GPIOG_AFRL GPIO_AFRL(GPIOG)
+#define GPIOH_AFRL GPIO_AFRL(GPIOH)
+#define GPIOI_AFRL GPIO_AFRL(GPIOI)
+
+/* Alternate function high register (GPIOx_AFRH) */
+#define GPIO_AFRH(port) MMIO32(port + 0x24)
+#define GPIOA_AFRH GPIO_AFRH(GPIOA)
+#define GPIOB_AFRH GPIO_AFRH(GPIOB)
+#define GPIOC_AFRH GPIO_AFRH(GPIOC)
+#define GPIOD_AFRH GPIO_AFRH(GPIOD)
+#define GPIOE_AFRH GPIO_AFRH(GPIOE)
+#define GPIOF_AFRH GPIO_AFRH(GPIOF)
+#define GPIOG_AFRH GPIO_AFRH(GPIOG)
+#define GPIOH_AFRH GPIO_AFRH(GPIOH)
+#define GPIOI_AFRH GPIO_AFRH(GPIOI)
+
+/* --- GPIOx_MODER values -------------------------------------------------- */
+
+#define GPIO_MODE(n, mode) (mode << (2 * (n)))
+#define GPIO_MODE_MASK(n) (0x3 << (2 * (n)))
+/** @defgroup gpio_mode GPIO Pin Direction and Analog/Digital Mode
+@ingroup gpio_defines
+@{*/
+#define GPIO_MODE_INPUT 0x0
+#define GPIO_MODE_OUTPUT 0x1
+#define GPIO_MODE_AF 0x2
+#define GPIO_MODE_ANALOG 0x3
+/**@}*/
+
+/* --- GPIOx_OTYPER values ------------------------------------------------- */
+
+/** @defgroup gpio_output_type GPIO Output Pin Driver Type
+@ingroup gpio_defines
+@list Push Pull
+@list Open Drain
+@{*/
+#define GPIO_OTYPE_PP 0x0
+#define GPIO_OTYPE_OD 0x1
+/**@}*/
+
+/* --- GPIOx_OSPEEDR values ------------------------------------------------ */
+
+#define GPIO_OSPEED(n, speed) (speed << (2 * (n)))
+#define GPIO_OSPEED_MASK(n) (0x3 << (2 * (n)))
+/** @defgroup gpio_speed GPIO Output Pin Speed
+@ingroup gpio_defines
+@{*/
+#define GPIO_OSPEED_2MHZ 0x0
+#define GPIO_OSPEED_25MHZ 0x1
+#define GPIO_OSPEED_50MHZ 0x2
+#define GPIO_OSPEED_100MHZ 0x3
+/**@}*/
+
+/* --- GPIOx_PUPDR values -------------------------------------------------- */
+
+#define GPIO_PUPD(n, pupd) (pupd << (2 * (n)))
+#define GPIO_PUPD_MASK(n) (0x3 << (2 * (n)))
+/** @defgroup gpio_pup GPIO Output Pin Pullup
+@ingroup gpio_defines
+@{*/
+#define GPIO_PUPD_NONE 0x0
+#define GPIO_PUPD_PULLUP 0x1
+#define GPIO_PUPD_PULLDOWN 0x2
+/**@}*/
+
+/* --- GPIOx_IDR values ---------------------------------------------------- */
+
+/* GPIOx_IDR[15:0]: IDRy[15:0]: Port input data (y = 0..15) */
+
+/* --- GPIOx_ODR values ---------------------------------------------------- */
+
+/* GPIOx_ODR[15:0]: ODRy[15:0]: Port output data (y = 0..15) */
+
+/* --- GPIOx_BSRR values --------------------------------------------------- */
+
+/* GPIOx_BSRR[31:16]: BRy: Port x reset bit y (y = 0..15) */
+/* GPIOx_BSRR[15:0]: BSy: Port x set bit y (y = 0..15) */
+
+/* --- GPIOx_LCKR values --------------------------------------------------- */
+
+#define GPIO_LCKK (1 << 16)
+/* GPIOx_LCKR[15:0]: LCKy: Port x lock bit y (y = 0..15) */
+
+/* --- GPIOx_AFRL/H values ------------------------------------------------- */
+
+/* Note: AFRL is used for bits 0..7, AFRH is used for 8..15 */
+/* See Datasheet Table 6 (pg. 48) for alternate function mappings. */
+
+#define GPIO_AFR(n, af) (af << ((n) * 4))
+#define GPIO_AFR_MASK(n) (0xf << ((n) * 4))
+/** @defgroup gpio_af_num Alternate Function Pin Selection
+@ingroup gpio_defines
+@{*/
+#define GPIO_AF0 0x0
+#define GPIO_AF1 0x1
+#define GPIO_AF2 0x2
+#define GPIO_AF3 0x3
+#define GPIO_AF4 0x4
+#define GPIO_AF5 0x5
+#define GPIO_AF6 0x6
+#define GPIO_AF7 0x7
+#define GPIO_AF8 0x8
+#define GPIO_AF9 0x9
+#define GPIO_AF10 0xa
+#define GPIO_AF11 0xb
+#define GPIO_AF12 0xc
+#define GPIO_AF13 0xd
+#define GPIO_AF14 0xe
+#define GPIO_AF15 0xf
+/**@}*/
+
+/* Note: EXTI source selection is now in the SYSCFG peripheral. */
+
+/* --- Function prototypes ------------------------------------------------- */
+
+BEGIN_DECLS
+
+/*
+ * Note: The F2 and F4 series have a completely new GPIO peripheral with different
+ * configuration options. Here we implement a different API partly to more
+ * closely match the peripheral capabilities and also to deliberately break
+ * compatibility with old F1 code so there is no confusion with similar
+ * sounding functions that have very different functionality.
+ */
+
+void gpio_mode_setup(u32 gpioport, u8 mode, u8 pull_up_down, u16 gpios);
+void gpio_set_output_options(u32 gpioport, u8 otype, u8 speed, u16 gpios);
+void gpio_set_af(u32 gpioport, u8 alt_func_num, u16 gpios);
+
+END_DECLS
+/**@}*/
+#endif
+
diff --git a/include/libopencm3/stm32/common/i2c_common_all.h b/include/libopencm3/stm32/common/i2c_common_all.h
new file mode 100644
index 0000000..d5cc490
--- /dev/null
+++ b/include/libopencm3/stm32/common/i2c_common_all.h
@@ -0,0 +1,383 @@
+/** @addtogroup i2c_defines */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA I2C.H */
+
+#ifndef LIBOPENCM3_I2C_COMMON_ALL_H
+#define LIBOPENCM3_I2C_COMMON_ALL_H
+
+#include <libopencm3/cm3/common.h>
+
+/**@{*/
+
+/* --- Convenience macros -------------------------------------------------- */
+
+/* I2C register base adresses (for convenience) */
+/****************************************************************************/
+/** @defgroup i2c_reg_base I2C register base address
+@ingroup i2c_defines
+
+@{*/
+#define I2C1 I2C1_BASE
+#define I2C2 I2C2_BASE
+/**@}*/
+
+/* --- I2C registers ------------------------------------------------------- */
+
+/* Control register 1 (I2Cx_CR1) */
+#define I2C_CR1(i2c_base) MMIO32(i2c_base + 0x00)
+#define I2C1_CR1 I2C_CR1(I2C1)
+#define I2C2_CR1 I2C_CR1(I2C2)
+
+/* Control register 2 (I2Cx_CR2) */
+#define I2C_CR2(i2c_base) MMIO32(i2c_base + 0x04)
+#define I2C1_CR2 I2C_CR2(I2C1)
+#define I2C2_CR2 I2C_CR2(I2C2)
+
+/* Own address register 1 (I2Cx_OAR1) */
+#define I2C_OAR1(i2c_base) MMIO32(i2c_base + 0x08)
+#define I2C1_OAR1 I2C_OAR1(I2C1)
+#define I2C2_OAR1 I2C_OAR1(I2C2)
+
+/* Own address register 2 (I2Cx_OAR2) */
+#define I2C_OAR2(i2c_base) MMIO32(i2c_base + 0x0c)
+#define I2C1_OAR2 I2C_OAR2(I2C1)
+#define I2C2_OAR2 I2C_OAR2(I2C2)
+
+/* Data register (I2Cx_DR) */
+#define I2C_DR(i2c_base) MMIO32(i2c_base + 0x10)
+#define I2C1_DR I2C_DR(I2C1)
+#define I2C2_DR I2C_DR(I2C2)
+
+/* Status register 1 (I2Cx_SR1) */
+#define I2C_SR1(i2c_base) MMIO32(i2c_base + 0x14)
+#define I2C1_SR1 I2C_SR1(I2C1)
+#define I2C2_SR1 I2C_SR1(I2C2)
+
+/* Status register 2 (I2Cx_SR2) */
+#define I2C_SR2(i2c_base) MMIO32(i2c_base + 0x18)
+#define I2C1_SR2 I2C_SR2(I2C1)
+#define I2C2_SR2 I2C_SR2(I2C2)
+
+/* Clock control register (I2Cx_CCR) */
+#define I2C_CCR(i2c_base) MMIO32(i2c_base + 0x1c)
+#define I2C1_CCR I2C_CCR(I2C1)
+#define I2C2_CCR I2C_CCR(I2C2)
+
+/* TRISE register (I2Cx_CCR) */
+#define I2C_TRISE(i2c_base) MMIO32(i2c_base + 0x20)
+#define I2C1_TRISE I2C_TRISE(I2C1)
+#define I2C2_TRISE I2C_TRISE(I2C2)
+
+/* --- I2Cx_CR1 values ----------------------------------------------------- */
+
+/* SWRST: Software reset */
+#define I2C_CR1_SWRST (1 << 15)
+
+/* Note: Bit 14 is reserved, and forced to 0 by hardware. */
+
+/* ALERT: SMBus alert */
+#define I2C_CR1_ALERT (1 << 13)
+
+/* PEC: Packet error checking */
+#define I2C_CR1_PEC (1 << 12)
+
+/* POS: Acknowledge / PEC postition */
+#define I2C_CR1_POS (1 << 11)
+
+/* ACK: Acknowledge enable */
+#define I2C_CR1_ACK (1 << 10)
+
+/* STOP: STOP generation */
+#define I2C_CR1_STOP (1 << 9)
+
+/* START: START generation */
+#define I2C_CR1_START (1 << 8)
+
+/* NOSTRETCH: Clock stretching disable (slave mode) */
+#define I2C_CR1_NOSTRETCH (1 << 7)
+
+/* ENGC: General call enable */
+#define I2C_CR1_ENGC (1 << 6)
+
+/* ENPEC: Enable PEC */
+#define I2C_CR1_ENPEC (1 << 5)
+
+/* ENARP: ARP enable */
+#define I2C_CR1_ENARP (1 << 4)
+
+/* SMBTYPE: SMBus type */
+#define I2C_CR1_SMBTYPE (1 << 3)
+
+/* Note: Bit 2 is reserved, and forced to 0 by hardware. */
+
+/* SMBUS: SMBus mode */
+#define I2C_CR1_SMBUS (1 << 1)
+
+/* PE: Peripheral enable */
+#define I2C_CR1_PE (1 << 0)
+
+/* --- I2Cx_CR2 values ----------------------------------------------------- */
+
+/* Note: Bits [15:13] are reserved, and forced to 0 by hardware. */
+
+/* LAST: DMA last transfer */
+#define I2C_CR2_LAST (1 << 12)
+
+/* DMAEN: DMA requests enable */
+#define I2C_CR2_DMAEN (1 << 11)
+
+/* ITBUFEN: Buffer interrupt enable */
+#define I2C_CR2_ITBUFEN (1 << 10)
+
+/* ITEVTEN: Event interrupt enable */
+#define I2C_CR2_ITEVTEN (1 << 9)
+
+/* ITERREN: Error interrupt enable */
+#define I2C_CR2_ITERREN (1 << 8)
+
+/* Note: Bits [7:6] are reserved, and forced to 0 by hardware. */
+
+/* FREQ[5:0]: Peripheral clock frequency (valid values: 2-36 MHz) */
+/****************************************************************************/
+/** @defgroup i2c_clock I2C clock frequency settings
+@ingroup i2c_defines
+
+@{*/
+#define I2C_CR2_FREQ_2MHZ 0x02
+#define I2C_CR2_FREQ_3MHZ 0x03
+#define I2C_CR2_FREQ_4MHZ 0x04
+#define I2C_CR2_FREQ_5MHZ 0x05
+#define I2C_CR2_FREQ_6MHZ 0x06
+#define I2C_CR2_FREQ_7MHZ 0x07
+#define I2C_CR2_FREQ_8MHZ 0x08
+#define I2C_CR2_FREQ_9MHZ 0x09
+#define I2C_CR2_FREQ_10MHZ 0x0a
+#define I2C_CR2_FREQ_11MHZ 0x0b
+#define I2C_CR2_FREQ_12MHZ 0x0c
+#define I2C_CR2_FREQ_13MHZ 0x0d
+#define I2C_CR2_FREQ_14MHZ 0x0e
+#define I2C_CR2_FREQ_15MHZ 0x0f
+#define I2C_CR2_FREQ_16MHZ 0x10
+#define I2C_CR2_FREQ_17MHZ 0x11
+#define I2C_CR2_FREQ_18MHZ 0x12
+#define I2C_CR2_FREQ_19MHZ 0x13
+#define I2C_CR2_FREQ_20MHZ 0x14
+#define I2C_CR2_FREQ_21MHZ 0x15
+#define I2C_CR2_FREQ_22MHZ 0x16
+#define I2C_CR2_FREQ_23MHZ 0x17
+#define I2C_CR2_FREQ_24MHZ 0x18
+#define I2C_CR2_FREQ_25MHZ 0x19
+#define I2C_CR2_FREQ_26MHZ 0x1a
+#define I2C_CR2_FREQ_27MHZ 0x1b
+#define I2C_CR2_FREQ_28MHZ 0x1c
+#define I2C_CR2_FREQ_29MHZ 0x1d
+#define I2C_CR2_FREQ_30MHZ 0x1e
+#define I2C_CR2_FREQ_31MHZ 0x1f
+#define I2C_CR2_FREQ_32MHZ 0x20
+#define I2C_CR2_FREQ_33MHZ 0x21
+#define I2C_CR2_FREQ_34MHZ 0x22
+#define I2C_CR2_FREQ_35MHZ 0x23
+#define I2C_CR2_FREQ_36MHZ 0x24
+/**@}*/
+
+/* --- I2Cx_OAR1 values ---------------------------------------------------- */
+
+/* ADDMODE: Addressing mode (slave mode) */
+#define I2C_OAR1_ADDMODE (1 << 15)
+#define I2C_OAR1_ADDMODE_7BIT 0
+#define I2C_OAR1_ADDMODE_10BIT 1
+
+/* Note: Bit 14 should always be kept at 1 by software! */
+
+/* Note: Bits [13:10] are reserved, and forced to 0 by hardware. */
+
+/* ADD: Address bits: [7:1] in 7-bit mode, bits [9:0] in 10-bit mode */
+
+/* --- I2Cx_OAR2 values ---------------------------------------------------- */
+
+/* Note: Bits [15:8] are reserved, and forced to 0 by hardware. */
+
+/* ADD2[7:1]: Interface address (bits [7:1] in dual addressing mode) */
+
+/* ENDUAL: Dual addressing mode enable */
+#define I2C_OAR2_ENDUAL (1 << 0)
+
+/* --- I2Cx_DR values ------------------------------------------------------ */
+
+/* Note: Bits [15:8] are reserved, and forced to 0 by hardware. */
+
+/* DR[7:0] 8-bit data register */
+
+/* --- I2Cx_SR1 values ----------------------------------------------------- */
+
+/* SMBALERT: SMBus alert */
+#define I2C_SR1_SMBALERT (1 << 15)
+
+/* TIMEOUT: Timeout or Tlow Error */
+#define I2C_SR1_TIMEOUT (1 << 14)
+
+/* Note: Bit 13 is reserved, and forced to 0 by hardware. */
+
+/* PECERR: PEC Error in reception */
+#define I2C_SR1_PECERR (1 << 12)
+
+/* OVR: Overrun/Underrun */
+#define I2C_SR1_OVR (1 << 11)
+
+/* AF: Acknowledge failure */
+#define I2C_SR1_AF (1 << 10)
+
+/* ARLO: Arbitration lost (master mode) */
+#define I2C_SR1_ARLO (1 << 9)
+
+/* BERR: Bus error */
+#define I2C_SR1_BERR (1 << 8)
+
+/* TxE: Data register empty (transmitters) */
+#define I2C_SR1_TxE (1 << 7)
+
+/* RxNE: Data register not empty (receivers) */
+#define I2C_SR1_RxNE (1 << 6)
+
+/* Note: Bit 5 is reserved, and forced to 0 by hardware. */
+
+/* STOPF: STOP detection (slave mode) */
+#define I2C_SR1_STOPF (1 << 4)
+
+/* ADD10: 10-bit header sent (master mode) */
+#define I2C_SR1_ADD10 (1 << 3)
+
+/* BTF: Byte transfer finished */
+#define I2C_SR1_BTF (1 << 2)
+
+/* ADDR: Address sent (master mode) / address matched (slave mode) */
+#define I2C_SR1_ADDR (1 << 1)
+
+/* SB: Start bit (master mode) */
+#define I2C_SR1_SB (1 << 0)
+
+/* --- I2Cx_SR2 values ----------------------------------------------------- */
+
+/* Bits [15:8]: PEC[7:0]: Packet error checking register */
+
+/* DUALF: Dual flag (slave mode) */
+#define I2C_SR2_DUALF (1 << 7)
+
+/* SMBHOST: SMBus host header (slave mode) */
+#define I2C_SR2_SMBHOST (1 << 6)
+
+/* SMBDEFAULT: SMBus device default address (slave mode) */
+#define I2C_SR2_SMBDEFAULT (1 << 5)
+
+/* GENCALL: General call address (slave mode) */
+#define I2C_SR2_GENCALL (1 << 4)
+
+/* Note: Bit 3 is reserved, and forced to 0 by hardware. */
+
+/* TRA: Transmitter / receiver */
+#define I2C_SR2_TRA (1 << 2)
+
+/* BUSY: Bus busy */
+#define I2C_SR2_BUSY (1 << 1)
+
+/* MSL: Master / slave */
+#define I2C_SR2_MSL (1 << 0)
+
+/* --- I2Cx_CCR values ----------------------------------------------------- */
+
+/* F/S: I2C Master mode selection (fast / standard) */
+#define I2C_CCR_FS (1 << 15)
+
+/* DUTY: Fast Mode Duty Cycle */
+/** @defgroup i2c_duty_cycle I2C peripheral clock duty cycles
+@ingroup i2c_defines
+
+@{*/
+#define I2C_CCR_DUTY (1 << 14)
+#define I2C_CCR_DUTY_DIV2 0
+#define I2C_CCR_DUTY_16_DIV_9 1
+/**@}*/
+
+/* Note: Bits [13:12] are reserved, and forced to 0 by hardware. */
+
+/*
+ * Bits [11:0]:
+ * CCR[11:0]: Clock control register in Fast/Standard mode (master mode)
+ */
+
+/* --- I2Cx_TRISE values --------------------------------------------------- */
+
+/* Note: Bits [15:6] are reserved, and forced to 0 by hardware. */
+
+/*
+ * Bits [5:0]:
+ * TRISE[5:0]: Maximum rise time in Fast/Standard mode (master mode)
+ */
+
+/* --- I2C const definitions ----------------------------------------------- */
+
+/****************************************************************************/
+/** @defgroup i2c_rw I2C Read/Write bit
+@ingroup i2c_defines
+
+@{*/
+#define I2C_WRITE 0
+#define I2C_READ 1
+/**@}*/
+
+/* --- I2C funtion prototypes----------------------------------------------- */
+
+BEGIN_DECLS
+
+void i2c_reset(u32 i2c);
+void i2c_peripheral_enable(u32 i2c);
+void i2c_peripheral_disable(u32 i2c);
+void i2c_send_start(u32 i2c);
+void i2c_send_stop(u32 i2c);
+void i2c_clear_stop(u32 i2c);
+void i2c_set_own_7bit_slave_address(u32 i2c, u8 slave);
+void i2c_set_own_10bit_slave_address(u32 i2c, u16 slave);
+void i2c_set_fast_mode(u32 i2c);
+void i2c_set_standard_mode(u32 i2c);
+void i2c_set_clock_frequency(u32 i2c, u8 freq);
+void i2c_set_ccr(u32 i2c, u16 freq);
+void i2c_set_trise(u32 i2c, u16 trise);
+void i2c_send_7bit_address(u32 i2c, u8 slave, u8 readwrite);
+void i2c_send_data(u32 i2c, u8 data);
+uint8_t i2c_get_data(u32 i2c);
+void i2c_enable_interrupt(u32 i2c, u32 interrupt);
+void i2c_disable_interrupt(u32 i2c, u32 interrupt);
+void i2c_enable_ack(u32 i2c);
+void i2c_disable_ack(u32 i2c);
+void i2c_nack_next(u32 i2c);
+void i2c_nack_current(u32 i2c);
+void i2c_set_dutycycle(u32 i2c, u32 dutycycle);
+void i2c_enable_dma(u32 i2c);
+void i2c_disable_dma(u32 i2c);
+void i2c_set_dma_last_transfer(u32 i2c);
+void i2c_clear_dma_last_transfer(u32 i2c);
+
+END_DECLS
+
+#endif
+/**@}*/
+
diff --git a/include/libopencm3/stm32/common/i2c_common_f24.h b/include/libopencm3/stm32/common/i2c_common_f24.h
new file mode 100644
index 0000000..22a5733
--- /dev/null
+++ b/include/libopencm3/stm32/common/i2c_common_f24.h
@@ -0,0 +1,35 @@
+/** @addtogroup i2c_defines */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Ken Sarkies <ksarkies@internode.on.net>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA I2C.H */
+
+#ifndef LIBOPENCM3_I2C_COMMON_F24_H
+#define LIBOPENCM3_I2C_COMMON_F24_H
+
+#include <libopencm3/stm32/common/i2c_common_all.h>
+
+/**@{*/
+
+#define I2C3 I2C3_BASE
+
+/**@}*/
+
+#endif
diff --git a/include/libopencm3/stm32/common/iwdg_common_all.h b/include/libopencm3/stm32/common/iwdg_common_all.h
new file mode 100644
index 0000000..ea2ad16
--- /dev/null
+++ b/include/libopencm3/stm32/common/iwdg_common_all.h
@@ -0,0 +1,109 @@
+/** @addtogroup iwdg_defines */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA IWDG.H */
+
+#ifndef LIBOPENCM3_IWDG_COMMON_ALL_H
+#define LIBOPENCM3_IWDG_COMMON_ALL_H
+
+#include <libopencm3/cm3/common.h>
+
+/**@{*/
+
+/* --- IWDG registers ------------------------------------------------------ */
+
+/* Key Register (IWDG_KR) */
+#define IWDG_KR MMIO32(IWDG_BASE + 0x00)
+
+/* Prescaler register (IWDG_PR) */
+#define IWDG_PR MMIO32(IWDG_BASE + 0x04)
+
+/* Reload register (IWDG_RLR) */
+#define IWDG_RLR MMIO32(IWDG_BASE + 0x08)
+
+/* Status register (IWDG_SR) */
+#define IWDG_SR MMIO32(IWDG_BASE + 0x0c)
+
+/* --- IWDG_KR values ------------------------------------------------------ */
+
+/* Bits [31:16]: Reserved. */
+
+/* KEY[15:0]: Key value (write-only, reads as 0x0000) */
+/** @defgroup iwdg_key IWDG Key Values
+@ingroup STM32F_iwdg_defines
+
+@{*/
+#define IWDG_KR_RESET 0xaaaa
+#define IWDG_KR_UNLOCK 0x5555
+#define IWDG_KR_START 0xcccc
+/**@}*/
+
+/* --- IWDG_PR values ------------------------------------------------------ */
+
+/* Bits [31:3]: Reserved. */
+
+/* PR[2:0]: Prescaler divider */
+#define IWDG_PR_LSB 0
+/** @defgroup iwdg_prediv IWDG Prescaler divider
+@ingroup STM32F_iwdg_defines
+
+@{*/
+#define IWDG_PR_DIV4 0x0
+#define IWDG_PR_DIV8 0x1
+#define IWDG_PR_DIV16 0x2
+#define IWDG_PR_DIV32 0x3
+#define IWDG_PR_DIV64 0x4
+#define IWDG_PR_DIV128 0x5
+#define IWDG_PR_DIV256 0x6
+/**@}*/
+/* Double definition: 0x06 and 0x07 both mean DIV256 as per datasheet. */
+/* #define IWDG_PR_DIV256 0x7 */
+
+/* --- IWDG_RLR values ----------------------------------------------------- */
+
+/* Bits [31:12]: Reserved. */
+
+/* RL[11:0]: Watchdog counter reload value */
+
+/* --- IWDG_SR values ------------------------------------------------------ */
+
+/* Bits [31:2]: Reserved. */
+
+/* RVU: Watchdog counter reload value update */
+#define IWDG_SR_RVU (1 << 1)
+
+/* PVU: Watchdog prescaler value update */
+#define IWDG_SR_PVU (1 << 0)
+
+/* --- IWDG function prototypes---------------------------------------------- */
+
+BEGIN_DECLS
+
+void iwdg_start(void);
+void iwdg_set_period_ms(u32 period);
+bool iwdg_reload_busy(void);
+bool iwdg_prescaler_busy(void);
+void iwdg_reset(void);
+
+END_DECLS
+
+#endif
+/**@}*/
+
diff --git a/include/libopencm3/stm32/common/pwr_common_all.h b/include/libopencm3/stm32/common/pwr_common_all.h
new file mode 100644
index 0000000..cc9fd22
--- /dev/null
+++ b/include/libopencm3/stm32/common/pwr_common_all.h
@@ -0,0 +1,119 @@
+/** @addtogroup pwr_defines */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA PWR.H */
+
+#ifndef LIBOPENCM3_PWR_COMMON_ALL_H
+#define LIBOPENCM3_PWR_COMMON_ALL_H
+
+/**@{*/
+
+#include <libopencm3/cm3/common.h>
+
+/* --- PWR registers ------------------------------------------------------- */
+
+/* Power control register (PWR_CR) */
+#define PWR_CR MMIO32(POWER_CONTROL_BASE + 0x00)
+
+/* Power control/status register (PWR_CSR) */
+#define PWR_CSR MMIO32(POWER_CONTROL_BASE + 0x04)
+
+/* --- PWR_CR values ------------------------------------------------------- */
+
+/* Bits [31:9]: Reserved, must be kept at reset value. */
+
+/* DBP: Disable backup domain write protection */
+#define PWR_CR_DBP (1 << 8)
+
+/* PLS[7:5]: PVD level selection */
+#define PWR_CR_PLS_LSB 5
+/** @defgroup pwr_pls PVD level selection
+@ingroup STM32F_pwr_defines
+
+@{*/
+#define PWR_CR_PLS_2V2 (0x0 << PWR_CR_PLS_LSB)
+#define PWR_CR_PLS_2V3 (0x1 << PWR_CR_PLS_LSB)
+#define PWR_CR_PLS_2V4 (0x2 << PWR_CR_PLS_LSB)
+#define PWR_CR_PLS_2V5 (0x3 << PWR_CR_PLS_LSB)
+#define PWR_CR_PLS_2V6 (0x4 << PWR_CR_PLS_LSB)
+#define PWR_CR_PLS_2V7 (0x5 << PWR_CR_PLS_LSB)
+#define PWR_CR_PLS_2V8 (0x6 << PWR_CR_PLS_LSB)
+#define PWR_CR_PLS_2V9 (0x7 << PWR_CR_PLS_LSB)
+/**@}*/
+#define PWR_CR_PLS_MASK (0x7 << PWR_CR_PLS_LSB)
+
+/* PVDE: Power voltage detector enable */
+#define PWR_CR_PVDE (1 << 4)
+
+/* CSBF: Clear standby flag */
+#define PWR_CR_CSBF (1 << 3)
+
+/* CWUF: Clear wakeup flag */
+#define PWR_CR_CWUF (1 << 2)
+
+/* PDDS: Power down deepsleep */
+#define PWR_CR_PDDS (1 << 1)
+
+/* LPDS: Low-power deepsleep */
+#define PWR_CR_LPDS (1 << 0)
+
+/* --- PWR_CSR values ------------------------------------------------------ */
+
+/* Bits [31:9]: Reserved, must be kept at reset value. */
+
+/* EWUP: Enable WKUP pin */
+#define PWR_CSR_EWUP (1 << 8)
+
+/* Bits [7:3]: Reserved, must be kept at reset value. */
+
+/* PVDO: PVD output */
+#define PWR_CSR_PVDO (1 << 2)
+
+/* SBF: Standby flag */
+#define PWR_CSR_SBF (1 << 1)
+
+/* WUF: Wakeup flag */
+#define PWR_CSR_WUF (1 << 0)
+
+/* --- PWR function prototypes ------------------------------------------- */
+
+BEGIN_DECLS
+
+void pwr_disable_backup_domain_write_protect(void);
+void pwr_enable_backup_domain_write_protect(void);
+void pwr_enable_power_voltage_detect(u32 pvd_level);
+void pwr_disable_power_voltage_detect(void);
+void pwr_clear_standby_flag(void);
+void pwr_clear_wakeup_flag(void);
+void pwr_set_standby_mode(void);
+void pwr_set_stop_mode(void);
+void pwr_voltage_regulator_on_in_stop(void);
+void pwr_voltage_regulator_low_power_in_stop(void);
+void pwr_enable_wakeup_pin(void);
+void pwr_disable_wakeup_pin(void);
+bool pwr_voltage_high(void);
+bool pwr_get_standby_flag(void);
+bool pwr_get_wakeup_flag(void);
+
+END_DECLS
+
+/**@}*/
+#endif
diff --git a/include/libopencm3/stm32/common/rng_common_f24.h b/include/libopencm3/stm32/common/rng_common_f24.h
new file mode 100644
index 0000000..7d98bfa
--- /dev/null
+++ b/include/libopencm3/stm32/common/rng_common_f24.h
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_RNG_COMMON_F24_H
+#define LIBOPENCM3_RNG_COMMON_F24_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/* --- Random number generator registers ----------------------------------- */
+
+/* Control register */
+#define RNG_CR MMIO32(RNG_BASE + 0x00)
+
+/* Status register */
+#define RNG_SR MMIO32(RNG_BASE + 0x04)
+
+/* Data register */
+#define RNG_DR MMIO32(RNG_BASE + 0x08)
+
+/* --- RNG_CR values ------------------------------------------------------- */
+
+/* RNG ENABLE */
+#define RNG_CR_RNGEN (1 << 2)
+
+/* RNG interupt enable */
+#define RNG_CR_IE (1 << 3)
+
+/* --- RNG_SR values ------------------------------------------------------- */
+
+/* Data ready */
+#define RNG_SR_DRDY (1 << 0)
+
+/* Clock error current status */
+#define RNG_SR_CECS (1 << 1)
+
+/* Seed error current status */
+#define RNG_SR_SECS (1 << 2)
+
+/* Clock error interup status */
+#define RNG_SR_CEIS (1 << 5)
+
+/* Seed error interup status */
+#define RNG_SR_SEIS (1 << 6)
+
+#endif
diff --git a/include/libopencm3/stm32/common/rtc_common_bcd.h b/include/libopencm3/stm32/common/rtc_common_bcd.h
new file mode 100644
index 0000000..130020e
--- /dev/null
+++ b/include/libopencm3/stm32/common/rtc_common_bcd.h
@@ -0,0 +1,302 @@
+/** @addtogroup rtc_defines */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA RTC.H */
+
+/*
+ * This covers the "version 2" RTC peripheral. This is completely different
+ * to the v1 RTC periph on the F1 series devices. It has BCD counters, with
+ * automatic leapyear corrections and daylight savings support.
+ * This peripheral is used on the F0, F2, F3, F4 and L1 devices, though some
+ * only support a subset.
+ */
+
+#ifndef LIBOPENCM3_RTC2_H
+#define LIBOPENCM3_RTC2_H
+
+/**@{*/
+
+#include <libopencm3/cm3/common.h>
+#include <libopencm3/stm32/memorymap.h>
+
+/* RTC time register (RTC_TR) */
+#define RTC_TR MMIO32(RTC_BASE + 0x00)
+
+/* RTC date register (RTC_DR) */
+#define RTC_DR MMIO32(RTC_BASE + 0x04)
+
+/* RTC control register (RTC_CR) */
+#define RTC_CR MMIO32(RTC_BASE + 0x08)
+
+/* RTC initialization and status register (RTC_ISR) */
+#define RTC_ISR MMIO32(RTC_BASE + 0x0c)
+
+/* RTC prescaler register (RTC_PRER) */
+#define RTC_PRER MMIO32(RTC_BASE + 0x10)
+
+/* RTC wakeup timer register (RTC_WUTR) */
+#define RTC_WUTR MMIO32(RTC_BASE + 0x14)
+
+/* RTC calibration register (RTC_CALIBR) NB: see also RTC_CALR */
+#define RTC_CALIBR MMIO32(RTC_BASE + 0x18)
+
+/* RTC alarm X register (RTC_ALRMxR) */
+#define RTC_ALRMAR MMIO32(RTC_BASE + 0x1c)
+#define RTC_ALRMBR MMIO32(RTC_BASE + 0x20)
+
+/* RTC write protection register (RTC_WPR)*/
+#define RTC_WPR MMIO32(RTC_BASE + 0x24)
+
+/* RTC sub second register (RTC_SSR) (high and med+ only) */
+#define RTC_SSR MMIO32(RTC_BASE + 0x28)
+
+/* RTC shift control register (RTC_SHIFTR) (high and med+ only) */
+#define RTC_SHIFTR MMIO32(RTC_BASE + 0x2c)
+
+/* RTC time stamp time register (RTC_TSTR) */
+#define RTC_TSTR MMIO32(RTC_BASE + 0x30)
+/* RTC time stamp date register (RTC_TSDR) */
+#define RTC_TSDR MMIO32(RTC_BASE + 0x34)
+/* RTC timestamp sub second register (RTC_TSSSR) (high and med+ only) */
+#define RTC_TSSSR MMIO32(RTC_BASE + 0x38)
+
+/* RTC calibration register (RTC_CALR) (high and med+ only) */
+#define RTC_CALR MMIO32(RTC_BASE + 0x3c)
+
+/* RTC tamper and alternate function configuration register (RTC_TAFCR) */
+#define RTC_TAFCR MMIO32(RTC_BASE + 0x40)
+
+/* RTC alarm X sub second register (RTC_ALRMxSSR) (high and med+ only) */
+#define RTC_ALRMASSR MMIO32(RTC_BASE + 0x44)
+#define RTC_ALRMBSSR MMIO32(RTC_BASE + 0x48)
+
+/* RTC backup registers (RTC_BKPxR) */
+#define RTC_BKP_BASE (RTC_BASE + 0x50)
+#define RTC_BKPXR(reg) MMIO32(RTC_BKP_BASE + (4*reg))
+
+
+/* RTC time register (RTC_TR) bits */
+#define RTC_TR_TR_PM (1 << 22)
+#define RTC_TR_HT_SHIFT (20)
+#define RTC_TR_HT_MASK (0x3)
+#define RTC_TR_HU_SHIFT (16)
+#define RTC_TR_HU_MASK (0xf)
+#define RTC_TR_MNT_SHIFT (12)
+#define RTC_TR_MNT_MASK (0x7)
+#define RTC_TR_MNU_SHIFT (8)
+#define RTC_TR_MNU_MASK (0xf)
+#define RTC_TR_ST_SHIFT (4)
+#define RTC_TR_ST_MASK (0x3)
+#define RTC_TR_SU_SHIFT (0)
+#define RTC_TR_SU_MASK (0xf)
+
+/* RTC date register (RTC_DR) bits */
+#define RTC_DR_YT_SHIFT (20)
+#define RTC_DR_YT_MASK (0xf)
+#define RTC_DR_YU_SHIFT (16)
+#define RTC_DR_YU_MASK (0xf)
+#define RTC_DR_WDU_SHIFT (13)
+#define RTC_DR_WDU_MASK (0x7)
+#define RTC_DR_MT (1<<12)
+#define RTC_DR_MU_SHIFT (8)
+#define RTC_DR_MU_MASK (0xf)
+#define RTC_DR_DT_SHIFT (4)
+#define RTC_DR_DT_MASK (0x3)
+#define RTC_DR_DU_SHIFT (0)
+#define RTC_DR_DU_MASK (0xf)
+
+/* RTC control register (RTC_CR) bits */
+#define RTC_CR_COE (1<<23)
+
+/* These bits are used to select the flag to be routed to AFO_ALARM RTC output */
+#define RTC_CR_OSEL_SHIFT 21
+#define RTC_CR_OSEL_MASK (0x3)
+#define RTC_CR_OSEL_DISABLED (0x0)
+#define RTC_CR_OSEL_ALARMA (0x1)
+#define RTC_CR_OSEL_ALARMB (0x2)
+#define RTC_CR_OSEL_WAKEUP (0x3)
+
+#define RTC_CR_POL (1<<20)
+#define RTC_CR_COSEL (1<<19)
+#define RTC_CR_BKP (1<<18)
+#define RTC_CR_SUB1H (1<<17)
+#define RTC_CR_ADD1H (1<<16)
+#define RTC_CR_TSIE (1<<15)
+#define RTC_CR_WUTIE (1<<14)
+#define RTC_CR_ALRBIE (1<<13)
+#define RTC_CR_ALRAIE (1<<12)
+#define RTC_CR_TSE (1<<11)
+#define RTC_CR_WUTE (1<<10)
+#define RTC_CR_ALRBE (1<<9)
+#define RTC_CR_ALRAE (1<<8)
+#define RTC_CR_DCE (1<<7)
+#define RTC_CR_FMT (1<<6)
+#define RTC_CR_BYPSHAD (1<<5)
+#define RTC_CR_REFCKON (1<<4)
+#define RTC_CR_TSEDGE (1<<3)
+#define RTC_CR_TSEDGE (1<<3)
+#define RTC_CR_WUCLKSEL_SHIFT (0)
+#define RTC_CR_WUCLKSEL_MASK (0x7)
+#define RTC_CR_WUCLKSEL_RTC_DIV16 (0x0)
+#define RTC_CR_WUCLKSEL_RTC_DIV8 (0x1)
+#define RTC_CR_WUCLKSEL_RTC_DIV4 (0x2)
+#define RTC_CR_WUCLKSEL_RTC_DIV2 (0x3)
+#define RTC_CR_WUCLKSEL_SPRE (0x4)
+#define RTC_CR_WUCLKSEL_SPRE_216 (0x6)
+
+/* RTC initialization and status register (RTC_ISR) bits */
+#define RTC_ISR_RECALPF (1<<16)
+#define RTC_ISR_TAMP3F (1<<15)
+#define RTC_ISR_TAMP2F (1<<14)
+#define RTC_ISR_TAMP1F (1<<13)
+#define RTC_ISR_TSOVF (1<<12)
+#define RTC_ISR_TSF (1<<11)
+#define RTC_ISR_WUTF (1<<10)
+#define RTC_ISR_ALRBF (1<<9)
+#define RTC_ISR_ALRAF (1<<8)
+#define RTC_ISR_INIT (1<<7)
+#define RTC_ISR_INITF (1<<6)
+#define RTC_ISR_RSF (1<<5)
+#define RTC_ISR_INITS (1<<4)
+#define RTC_ISR_SHPF (1<<3)
+#define RTC_ISR_WUTWF (1<<2)
+#define RTC_ISR_ALRBWF (1<<1)
+#define RTC_ISR_ALRAWF (1<<0)
+
+/* RTC prescaler register (RTC_PRER) bits */
+#define RTC_PRER_PREDIV_A_SHIFT (16)
+#define RTC_PRER_PREDIV_A_MASK (0x7f)
+#define RTC_PRER_PREDIV_S_SHIFT (0)
+#define RTC_PRER_PREDIV_S_MASK (0x7fff)
+
+/* RTC calibration register (RTC_CALIBR) bits */
+// FIXME - TODO
+
+/* RTC Alarm register bits Applies to RTC_ALRMAR and RTC_ALRMBR */
+#define RTC_ALRMXR_MSK4 (1<<31)
+#define RTC_ALRMXR_WDSEL (1<<30)
+#define RTC_ALRMXR_DT_SHIFT (28)
+#define RTC_ALRMXR_DT_MASK (0x3)
+#define RTC_ALRMXR_DU_SHIFT (24)
+#define RTC_ALRMXR_DU_MASK (0xf)
+#define RTC_ALRMXR_MSK3 (1<<23)
+#define RTC_ALRMXR_PM (1<<22)
+#define RTC_ALRMXR_HT_SHIFT (20)
+#define RTC_ALRMXR_HT_MASK (0x3)
+#define RTC_ALRMXR_HU_SHIFT (16)
+#define RTC_ALRMXR_HU_MASK (0xf)
+#define RTC_ALRMXR_MSK2 (1<<15)
+#define RTC_ALRMXR_MNT_SHIFT (12)
+#define RTC_ALRMXR_MNT_MASK (0x7)
+#define RTC_ALRMXR_MNU_SHIFT (8)
+#define RTC_ALRMXR_MNU_MASK (0xf)
+#define RTC_ALRMXR_MSK1 (1<<7)
+#define RTC_ALRMXR_ST_SHIFT (4)
+#define RTC_ALRMXR_ST_MASK (0x7)
+#define RTC_ALRMXR_SU_SHIFT (0)
+#define RTC_ALRMXR_SU_MASK (0xf)
+
+/* RTC shift control register (RTC_SHIFTR) */
+// FIXME - TODO
+
+/* RTC time stamp time register (RTC_TSTR) bits */
+#define RTC_TSTR_PM (1<<22)
+#define RTC_TSTR_HT_SHIFT (20)
+#define RTC_TSTR_HT_MASK (0x3)
+#define RTC_TSTR_HU_SHIFT (16)
+#define RTC_TSTR_HU_MASK (0xf)
+#define RTC_TSTR_MNT_SHIFT (12)
+#define RTC_TSTR_MNT_MASK (0x7)
+#define RTC_TSTR_MNU_SHIFT (8)
+#define RTC_TSTR_MNU_MASK (0xf)
+#define RTC_TSTR_ST_SHIFT (4)
+#define RTC_TSTR_ST_MASK (0x7)
+#define RTC_TSTR_SU_SHIFT (0)
+#define RTC_TSTR_SU_MASK (0xf)
+
+/* RTC time stamp date register (RTC_TSDR) bits */
+#define RTC_TSDR_WDU_SHIFT (13)
+#define RTC_TSDR_WDU_MASK (0x7)
+#define RTC_TSDR_MT (1<<12)
+#define RTC_TSDR_MU_SHIFT (8)
+#define RTC_TSDR_MU_MASK (0xf)
+#define RTC_TSDR_DT_SHIFT (4)
+#define RTC_TSDR_DT_MASK (0x3)
+#define RTC_TSDR_DU_SHIFT (0)
+#define RTC_TSDR_DU_MASK (0xf)
+
+/* RTC calibration register (RTC_CALR) bits */
+// FIXME - TODO
+
+/* RTC tamper and alternate function configuration register (RTC_TAFCR) bits */
+#define RTC_TAFCR_ALARMOUTTYPE (1<<18)
+#define RTC_TAFCR_TAMPPUDIS (1<<15)
+
+#define RTC_TAFCR_TAMPPRCH_SHIFT (13)
+#define RTC_TAFCR_TAMPPRCH_MASK (0x3)
+#define RTC_TAFCR_TAMPPRCH_1RTC (0x0)
+#define RTC_TAFCR_TAMPPRCH_2RTC (0x1)
+#define RTC_TAFCR_TAMPPRCH_4RTC (0x2)
+#define RTC_TAFCR_TAMPPRCH_8RTC (0x3)
+
+#define RTC_TAFCR_TAMPFLT_SHIFT (11)
+#define RTC_TAFCR_TAMPFLT_MASK (0x3)
+#define RTC_TAFCR_TAMPFLT_EDGE1 (0x0)
+#define RTC_TAFCR_TAMPFLT_EDGE2 (0x1)
+#define RTC_TAFCR_TAMPFLT_EDGE4 (0x2)
+#define RTC_TAFCR_TAMPFLT_EDGE8 (0x3)
+
+#define RTC_TAFCR_TAMPFREQ_SHIFT (8)
+#define RTC_TAFCR_TAMPFREQ_MASK (0x7)
+#define RTC_TAFCR_TAMPFREQ_RTCDIV32K (0x0)
+#define RTC_TAFCR_TAMPFREQ_RTCDIV16K (0x1)
+#define RTC_TAFCR_TAMPFREQ_RTCDIV8K (0x2)
+#define RTC_TAFCR_TAMPFREQ_RTCDIV4K (0x3)
+#define RTC_TAFCR_TAMPFREQ_RTCDIV2K (0x4)
+#define RTC_TAFCR_TAMPFREQ_RTCDIV1K (0x5)
+#define RTC_TAFCR_TAMPFREQ_RTCDIV512 (0x6)
+#define RTC_TAFCR_TAMPFREQ_RTCDIV256 (0x7)
+
+#define RTC_TAFCR_TAMPTS (1<<7)
+#define RTC_TAFCR_TAMP3TRG (1<<6)
+#define RTC_TAFCR_TAMP3E (1<<5)
+#define RTC_TAFCR_TAMP2TRG (1<<4)
+#define RTC_TAFCR_TAMP2E (1<<3)
+#define RTC_TAFCR_TAMPIE (1<<2)
+#define RTC_TAFCR_TAMP1TRG (1<<1)
+#define RTC_TAFCR_TAMP1E (1<<0)
+
+/* RTC alarm X sub second register */
+// FIXME - TODO
+
+
+
+BEGIN_DECLS
+
+void rtc_set_prescaler(u32 sync, u32 async);
+void rtc_wait_for_synchro(void);
+void rtc_lock(void);
+void rtc_unlock(void);
+
+END_DECLS
+/**@}*/
+
+#endif /* RTC2_H */
+
diff --git a/include/libopencm3/stm32/common/spi_common_all.h b/include/libopencm3/stm32/common/spi_common_all.h
new file mode 100644
index 0000000..57b1465
--- /dev/null
+++ b/include/libopencm3/stm32/common/spi_common_all.h
@@ -0,0 +1,399 @@
+/** @addtogroup spi_defines */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA SPI.H */
+
+#ifndef LIBOPENCM3_SPI_COMMON_ALL_H
+#define LIBOPENCM3_SPI_COMMON_ALL_H
+
+#include <libopencm3/cm3/common.h>
+
+/**@{*/
+
+/* Registers can be accessed as 16bit or 32bit values. */
+
+/* --- Convenience macros -------------------------------------------------- */
+
+/****************************************************************************/
+/** @defgroup spi_reg_base SPI Register base address
+@ingroup spi_defines
+
+@{*/
+#define SPI1 SPI1_BASE
+#define SPI2 SPI2_I2S_BASE
+#define SPI3 SPI3_I2S_BASE
+/**@}*/
+
+/* --- SPI registers ------------------------------------------------------- */
+
+/* Control register 1 (SPIx_CR1) */
+/* Note: Not used in I2S mode. */
+#define SPI_CR1(spi_base) MMIO32(spi_base + 0x00)
+#define SPI1_CR1 SPI_CR1(SPI1_BASE)
+#define SPI2_CR1 SPI_CR1(SPI2_I2S_BASE)
+#define SPI3_CR1 SPI_CR1(SPI3_I2S_BASE)
+
+/* Control register 2 (SPIx_CR2) */
+#define SPI_CR2(spi_base) MMIO32(spi_base + 0x04)
+#define SPI1_CR2 SPI_CR2(SPI1_BASE)
+#define SPI2_CR2 SPI_CR2(SPI2_I2S_BASE)
+#define SPI3_CR2 SPI_CR2(SPI3_I2S_BASE)
+
+/* Status register (SPIx_SR) */
+#define SPI_SR(spi_base) MMIO32(spi_base + 0x08)
+#define SPI1_SR SPI_SR(SPI1_BASE)
+#define SPI2_SR SPI_SR(SPI2_I2S_BASE)
+#define SPI3_SR SPI_SR(SPI3_I2S_BASE)
+
+/* Data register (SPIx_DR) */
+#define SPI_DR(spi_base) MMIO32(spi_base + 0x0c)
+#define SPI1_DR SPI_DR(SPI1_BASE)
+#define SPI2_DR SPI_DR(SPI2_I2S_BASE)
+#define SPI3_DR SPI_DR(SPI3_I2S_BASE)
+
+/* CRC polynomial register (SPIx_CRCPR) */
+/* Note: Not used in I2S mode. */
+#define SPI_CRCPR(spi_base) MMIO32(spi_base + 0x10)
+#define SPI1_CRCPR SPI_CRCPR(SPI1_BASE)
+#define SPI2_CRCPR SPI_CRCPR(SPI2_I2S_BASE)
+#define SPI3_CRCPR SPI_CRCPR(SPI3_I2S_BASE)
+
+/* RX CRC register (SPIx_RXCRCR) */
+/* Note: Not used in I2S mode. */
+#define SPI_RXCRCR(spi_base) MMIO32(spi_base + 0x14)
+#define SPI1_RXCRCR SPI_RXCRCR(SPI1_BASE)
+#define SPI2_RXCRCR SPI_RXCRCR(SPI2_I2S_BASE)
+#define SPI3_RXCRCR SPI_RXCRCR(SPI3_I2S_BASE)
+
+/* TX CRC register (SPIx_RXCRCR) */
+/* Note: Not used in I2S mode. */
+#define SPI_TXCRCR(spi_base) MMIO32(spi_base + 0x18)
+#define SPI1_TXCRCR SPI_TXCRCR(SPI1_BASE)
+#define SPI2_TXCRCR SPI_TXCRCR(SPI2_I2S_BASE)
+#define SPI3_TXCRCR SPI_TXCRCR(SPI3_I2S_BASE)
+
+/* I2S configuration register (SPIx_I2SCFGR) */
+#define SPI_I2SCFGR(spi_base) MMIO32(spi_base + 0x1c)
+#define SPI1_I2SCFGR SPI_I2SCFGR(SPI1_BASE)
+#define SPI2_I2SCFGR SPI_I2SCFGR(SPI2_I2S_BASE)
+#define SPI3_I2SCFGR SPI_I2SCFGR(SPI3_I2S_BASE)
+
+/* I2S prescaler register (SPIx_I2SPR) */
+#define SPI_I2SPR(spi_base) MMIO32(spi_base + 0x20)
+#define SPI1_I2SPR SPI_I2SPR(SPI1_BASE)
+#define SPI2_I2SPR SPI_I2SPR(SPI2_I2S_BASE)
+#define SPI3_I2SPR SPI_I2SPR(SPI3_I2S_BASE)
+
+/* --- SPI_CR1 values ------------------------------------------------------ */
+
+/* Note: None of the CR1 bits are used in I2S mode. */
+
+/* BIDIMODE: Bidirectional data mode enable */
+#define SPI_CR1_BIDIMODE_2LINE_UNIDIR (0 << 15)
+#define SPI_CR1_BIDIMODE_1LINE_BIDIR (1 << 15)
+#define SPI_CR1_BIDIMODE (1 << 15)
+
+/* BIDIOE: Output enable in bidirectional mode */
+#define SPI_CR1_BIDIOE (1 << 14)
+
+/* CRCEN: Hardware CRC calculation enable */
+#define SPI_CR1_CRCEN (1 << 13)
+
+/* CRCNEXT: Transmit CRC next */
+#define SPI_CR1_CRCNEXT (1 << 12)
+
+/* DFF: Data frame format */
+/****************************************************************************/
+/** @defgroup spi_dff SPI data frame format
+@ingroup spi_defines
+
+@{*/
+#define SPI_CR1_DFF_8BIT (0 << 11)
+#define SPI_CR1_DFF_16BIT (1 << 11)
+/**@}*/
+#define SPI_CR1_DFF (1 << 11)
+
+/* RXONLY: Receive only */
+#define SPI_CR1_RXONLY (1 << 10)
+
+/* SSM: Software slave management */
+#define SPI_CR1_SSM (1 << 9)
+
+/* SSI: Internal slave select */
+#define SPI_CR1_SSI (1 << 8)
+
+/* LSBFIRST: Frame format */
+/****************************************************************************/
+/** @defgroup spi_lsbfirst SPI lsb/msb first
+@ingroup spi_defines
+
+@{*/
+#define SPI_CR1_MSBFIRST (0 << 7)
+#define SPI_CR1_LSBFIRST (1 << 7)
+/**@}*/
+
+/* SPE: SPI enable */
+#define SPI_CR1_SPE (1 << 6)
+
+/* BR[2:0]: Baud rate control */
+/****************************************************************************/
+/** @defgroup spi_baudrate SPI peripheral baud rates
+@ingroup spi_defines
+
+@{*/
+#define SPI_CR1_BAUDRATE_FPCLK_DIV_2 (0x00 << 3)
+#define SPI_CR1_BAUDRATE_FPCLK_DIV_4 (0x01 << 3)
+#define SPI_CR1_BAUDRATE_FPCLK_DIV_8 (0x02 << 3)
+#define SPI_CR1_BAUDRATE_FPCLK_DIV_16 (0x03 << 3)
+#define SPI_CR1_BAUDRATE_FPCLK_DIV_32 (0x04 << 3)
+#define SPI_CR1_BAUDRATE_FPCLK_DIV_64 (0x05 << 3)
+#define SPI_CR1_BAUDRATE_FPCLK_DIV_128 (0x06 << 3)
+#define SPI_CR1_BAUDRATE_FPCLK_DIV_256 (0x07 << 3)
+/**@}*/
+/****************************************************************************/
+/** @defgroup spi_br_pre SPI peripheral baud rate prescale values
+@ingroup spi_defines
+
+@{*/
+#define SPI_CR1_BR_FPCLK_DIV_2 0x0
+#define SPI_CR1_BR_FPCLK_DIV_4 0x1
+#define SPI_CR1_BR_FPCLK_DIV_8 0x2
+#define SPI_CR1_BR_FPCLK_DIV_16 0x3
+#define SPI_CR1_BR_FPCLK_DIV_32 0x4
+#define SPI_CR1_BR_FPCLK_DIV_64 0x5
+#define SPI_CR1_BR_FPCLK_DIV_128 0x6
+#define SPI_CR1_BR_FPCLK_DIV_256 0x7
+/**@}*/
+
+/* MSTR: Master selection */
+#define SPI_CR1_MSTR (1 << 2)
+
+/* CPOL: Clock polarity */
+/****************************************************************************/
+/** @defgroup spi_cpol SPI clock polarity
+@ingroup spi_defines
+
+@{*/
+#define SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE (0 << 1)
+#define SPI_CR1_CPOL_CLK_TO_1_WHEN_IDLE (1 << 1)
+/**@}*/
+#define SPI_CR1_CPOL (1 << 1)
+
+/* CPHA: Clock phase */
+/****************************************************************************/
+/** @defgroup spi_cpha SPI clock phase
+@ingroup spi_defines
+
+@{*/
+#define SPI_CR1_CPHA_CLK_TRANSITION_1 (0 << 0)
+#define SPI_CR1_CPHA_CLK_TRANSITION_2 (1 << 0)
+/**@}*/
+#define SPI_CR1_CPHA (1 << 0)
+
+/* --- SPI_CR2 values ------------------------------------------------------ */
+
+/* Bits [15:8]: Reserved. Forced to 0 by hardware. */
+
+/* TXEIE: Tx buffer empty interrupt enable */
+#define SPI_CR2_TXEIE (1 << 7)
+
+/* RXNEIE: Rx buffer not empty interrupt enable */
+#define SPI_CR2_RXNEIE (1 << 6)
+
+/* ERRIE: Error interrupt enable */
+#define SPI_CR2_ERRIE (1 << 5)
+
+/* Bits [4:3]: Reserved. Forced to 0 by hardware. */
+
+/* SSOE: SS output enable */
+/* Note: Not used in I2S mode. */
+#define SPI_CR2_SSOE (1 << 2)
+
+/* TXDMAEN: Tx buffer DMA enable */
+#define SPI_CR2_TXDMAEN (1 << 1)
+
+/* RXDMAEN: Rx buffer DMA enable */
+#define SPI_CR2_RXDMAEN (1 << 0)
+
+/* --- SPI_SR values ------------------------------------------------------- */
+
+/* Bits [15:8]: Reserved. Forced to 0 by hardware. */
+
+/* BSY: Busy flag */
+#define SPI_SR_BSY (1 << 7)
+
+/* OVR: Overrun flag */
+#define SPI_SR_OVR (1 << 6)
+
+/* MODF: Mode fault */
+/* Note: Not used in I2S mode. */
+#define SPI_SR_MODF (1 << 5)
+
+/* CRCERR: CRC error flag */
+/* Note: Not used in I2S mode. */
+#define SPI_SR_CRCERR (1 << 4)
+
+/* UDR: Underrun flag */
+/* Note: Not used in SPI mode. */
+#define SPI_SR_UDR (1 << 3)
+
+/* CHSIDE: Channel side */
+/* Note: Not used in SPI mode. No meaning in PCM mode. */
+#define SPI_SR_CHSIDE (1 << 2)
+
+/* TXE: Transmit buffer empty */
+#define SPI_SR_TXE (1 << 1)
+
+/* RXNE: Receive buffer not empty */
+#define SPI_SR_RXNE (1 << 0)
+
+/* --- SPI_DR values ------------------------------------------------------- */
+
+/* SPI_DR[15:0]: Data Register. */
+
+/* --- SPI_CRCPR values ---------------------------------------------------- */
+
+/* Note: Not used in I2S mode. */
+/* SPI_CRCPR [15:0]: CRC Polynomial Register. */
+
+/* --- SPI_RXCRCR values --------------------------------------------------- */
+
+/* Note: Not used in I2S mode. */
+/* SPI_RXCRCR [15:0]: RX CRC Register. */
+
+/* --- SPI_TXCRCR values --------------------------------------------------- */
+
+/* Note: Not used in I2S mode. */
+/* SPI_TXCRCR [15:0]: TX CRC Register. */
+
+/* --- SPI_I2SCFGR values -------------------------------------------------- */
+
+/* Note: None of these bits are used in SPI mode. */
+
+/* Bits [15:12]: Reserved. Forced to 0 by hardware. */
+
+/* I2SMOD: I2S mode selection */
+#define SPI_I2SCFGR_I2SMOD (1 << 11)
+
+/* I2SE: I2S enable */
+#define SPI_I2SCFGR_I2SE (1 << 10)
+
+/* I2SCFG[9:8]: I2S configuration mode */
+#define SPI_I2SCFGR_I2SCFG_LSB 8
+#define SPI_I2SCFGR_I2SCFG_SLAVE_TRANSMIT 0x0
+#define SPI_I2SCFGR_I2SCFG_SLAVE_RECEIVE 0x1
+#define SPI_I2SCFGR_I2SCFG_MASTER_TRANSMIT 0x2
+#define SPI_I2SCFGR_I2SCFG_MASTER_RECEIVE 0x3
+
+/* PCMSYNC: PCM frame synchronization */
+#define SPI_I2SCFGR_PCMSYNC (1 << 7)
+
+/* Bit 6: Reserved. Forced to 0 by hardware. */
+
+/* I2SSTD[5:4]: I2S standard selection */
+#define SPI_I2SCFGR_I2SSTD_LSB 4
+#define SPI_I2SCFGR_I2SSTD_I2S_PHILLIPS 0x0
+#define SPI_I2SCFGR_I2SSTD_MSB_JUSTIFIED 0x1
+#define SPI_I2SCFGR_I2SSTD_LSB_JUSTIFIED 0x2
+#define SPI_I2SCFGR_I2SSTD_PCM 0x3
+
+/* CKPOL: Steady state clock polarity */
+#define SPI_I2SCFGR_CKPOL (1 << 3)
+
+/* DATLEN[2:1]: Data length to be transferred */
+#define SPI_I2SCFGR_DATLEN_LSB 1
+#define SPI_I2SCFGR_DATLEN_16BIT 0x0
+#define SPI_I2SCFGR_DATLEN_24BIT 0x1
+#define SPI_I2SCFGR_DATLEN_32BIT 0x2
+
+/* CHLEN: Channel length */
+#define SPI_I2SCFGR_CHLEN (1 << 0)
+
+/* --- SPI_I2SPR values ---------------------------------------------------- */
+
+/* Note: None of these bits are used in SPI mode. */
+
+/* Bits [15:10]: Reserved. Forced to 0 by hardware. */
+
+/* MCKOE: Master clock output enable */
+#define SPI_I2SPR_MCKOE (1 << 9)
+
+/* ODD: Odd factor for the prescaler */
+#define SPI_I2SPR_ODD (1 << 8)
+
+/* I2SDIV[7:0]: I2S linear prescaler */
+/* 0 and 1 are forbidden values */
+
+/* --- Function prototypes ------------------------------------------------- */
+
+BEGIN_DECLS
+
+void spi_reset(u32 spi_peripheral);
+int spi_init_master(u32 spi, u32 br, u32 cpol, u32 cpha, u32 dff, u32 lsbfirst);
+void spi_enable(u32 spi);
+void spi_disable(u32 spi);
+void spi_write(u32 spi, u16 data);
+void spi_send(u32 spi, u16 data);
+u16 spi_read(u32 spi);
+u16 spi_xfer(u32 spi, u16 data);
+void spi_set_bidirectional_mode(u32 spi);
+void spi_set_unidirectional_mode(u32 spi);
+void spi_set_bidirectional_receive_only_mode(u32 spi);
+void spi_set_bidirectional_transmit_only_mode(u32 spi);
+void spi_enable_crc(u32 spi);
+void spi_disable_crc(u32 spi);
+void spi_set_next_tx_from_buffer(u32 spi);
+void spi_set_next_tx_from_crc(u32 spi);
+void spi_set_dff_8bit(u32 spi);
+void spi_set_dff_16bit(u32 spi);
+void spi_set_full_duplex_mode(u32 spi);
+void spi_set_receive_only_mode(u32 spi);
+void spi_disable_software_slave_management(u32 spi);
+void spi_enable_software_slave_management(u32 spi);
+void spi_set_nss_high(u32 spi);
+void spi_set_nss_low(u32 spi);
+void spi_send_lsb_first(u32 spi);
+void spi_send_msb_first(u32 spi);
+void spi_set_baudrate_prescaler(u32 spi, u8 baudrate);
+void spi_set_master_mode(u32 spi);
+void spi_set_slave_mode(u32 spi);
+void spi_set_clock_polarity_1(u32 spi);
+void spi_set_clock_polarity_0(u32 spi);
+void spi_set_clock_phase_1(u32 spi);
+void spi_set_clock_phase_0(u32 spi);
+void spi_enable_tx_buffer_empty_interrupt(u32 spi);
+void spi_disable_tx_buffer_empty_interrupt(u32 spi);
+void spi_enable_rx_buffer_not_empty_interrupt(u32 spi);
+void spi_disable_rx_buffer_not_empty_interrupt(u32 spi);
+void spi_enable_error_interrupt(u32 spi);
+void spi_disable_error_interrupt(u32 spi);
+void spi_enable_ss_output(u32 spi);
+void spi_disable_ss_output(u32 spi);
+void spi_enable_tx_dma(u32 spi);
+void spi_disable_tx_dma(u32 spi);
+void spi_enable_rx_dma(u32 spi);
+void spi_disable_rx_dma(u32 spi);
+
+END_DECLS
+
+/**@}*/
+
+#endif
diff --git a/include/libopencm3/stm32/f4/syscfg.h b/include/libopencm3/stm32/common/spi_common_f24.h
index 7426f16..6b3764e 100644
--- a/include/libopencm3/stm32/f4/syscfg.h
+++ b/include/libopencm3/stm32/common/spi_common_f24.h
@@ -1,3 +1,4 @@
+/** @addtogroup spi_defines */
/*
* This file is part of the libopencm3 project.
*
@@ -17,30 +18,33 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
-#ifndef LIBOPENCM3_SYSCFG_H
-#define LIBOPENCM3_SYSCFG_H
+/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA SPI.H */
-#include <libopencm3/stm32/memorymap.h>
+#ifndef LIBOPENCM3_SPI_COMMON_F24_H
+#define LIBOPENCM3_SPI_COMMON_F24_H
-/* --- SYSCFG registers ------------------------------------------------------ */
+/**@{*/
-#define SYSCFG_MEMRM MMIO32(SYSCFG_BASE + 0x00)
+#include <libopencm3/stm32/common/spi_common_all.h>
-#define SYSCFG_PMC MMIO32(SYSCFG_BASE + 0x04)
-
-/* External interrupt configuration register 1 (SYSCFG_EXTICR1) */
-#define SYSCFG_EXTICR1 MMIO32(SYSCFG_BASE + 0x08)
+/*
+ * This file extends the common STM32 version with definitions only
+ * applicable to the STM32F2/4 series of devices.
+ */
-/* External interrupt configuration register 2 (SYSCFG_EXTICR2) */
-#define SYSCFG_EXTICR2 MMIO32(SYSCFG_BASE + 0x0c)
+/* --- SPI_CR2 values ------------------------------------------------------ */
-/* External interrupt configuration register 3 (SYSCFG_EXTICR3) */
-#define SYSCFG_EXTICR3 MMIO32(SYSCFG_BASE + 0x10)
+/* FRF: Frame format */
+/* Note: Not used in I2S mode. */
+#define SPI_CR2_FRF (1 << 4)
+#define SPI_CR2_FRF_MOTOROLA_MODE (0 << 4)
+#define SPI_CR2_FRF_TI_MODE (1 << 4)
-/* External interrupt configuration register 4 (SYSCFG_EXTICR4) */
-#define SYSCFG_EXTICR4 MMIO32(SYSCFG_BASE + 0x14)
+/* --- SPI_SR values ------------------------------------------------------- */
-#define SYSCFG_CMPCR MMIO32(SYSCFG_BASE + 0x20)
+/* TIFRFE: TI frame format error */
+#define SPI_SR_TIFRFE (1 << 8)
#endif
+/**@}*/
diff --git a/include/libopencm3/stm32/common/usart_common_all.h b/include/libopencm3/stm32/common/usart_common_all.h
new file mode 100644
index 0000000..1334420
--- /dev/null
+++ b/include/libopencm3/stm32/common/usart_common_all.h
@@ -0,0 +1,369 @@
+/** @addtogroup usart_defines */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/**@{*/
+
+/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA SPI.H */
+
+#ifndef LIBOPENCM3_USART_COMMON_ALL_H
+#define LIBOPENCM3_USART_COMMON_ALL_H
+
+#include <libopencm3/cm3/common.h>
+
+/* --- Convenience macros -------------------------------------------------- */
+
+/****************************************************************************/
+/** @defgroup usart_reg_base USART register base addresses
+@ingroup STM32F_usart_defines
+
+@{*/
+#define USART1 USART1_BASE
+#define USART2 USART2_BASE
+#define USART3 USART3_BASE
+/**@}*/
+#define UART4 UART4_BASE
+#define UART5 UART5_BASE
+
+/* --- USART registers ----------------------------------------------------- */
+
+/* Status register (USARTx_SR) */
+#define USART_SR(usart_base) MMIO32(usart_base + 0x00)
+#define USART1_SR USART_SR(USART1_BASE)
+#define USART2_SR USART_SR(USART2_BASE)
+#define USART3_SR USART_SR(USART3_BASE)
+#define UART4_SR USART_SR(UART4_BASE)
+#define UART5_SR USART_SR(UART5_BASE)
+
+/* Data register (USARTx_DR) */
+#define USART_DR(usart_base) MMIO32(usart_base + 0x04)
+#define USART1_DR USART_DR(USART1_BASE)
+#define USART2_DR USART_DR(USART2_BASE)
+#define USART3_DR USART_DR(USART3_BASE)
+#define UART4_DR USART_DR(UART4_BASE)
+#define UART5_DR USART_DR(UART5_BASE)
+
+/* Baud rate register (USARTx_BRR) */
+#define USART_BRR(usart_base) MMIO32(usart_base + 0x08)
+#define USART1_BRR USART_BRR(USART1_BASE)
+#define USART2_BRR USART_BRR(USART2_BASE)
+#define USART3_BRR USART_BRR(USART3_BASE)
+#define UART4_BRR USART_BRR(UART4_BASE)
+#define UART5_BRR USART_BRR(UART5_BASE)
+
+/* Control register 1 (USARTx_CR1) */
+#define USART_CR1(usart_base) MMIO32(usart_base + 0x0c)
+#define USART1_CR1 USART_CR1(USART1_BASE)
+#define USART2_CR1 USART_CR1(USART2_BASE)
+#define USART3_CR1 USART_CR1(USART3_BASE)
+#define UART4_CR1 USART_CR1(UART4_BASE)
+#define UART5_CR1 USART_CR1(UART5_BASE)
+
+/* Control register 2 (USARTx_CR2) */
+#define USART_CR2(usart_base) MMIO32(usart_base + 0x10)
+#define USART1_CR2 USART_CR2(USART1_BASE)
+#define USART2_CR2 USART_CR2(USART2_BASE)
+#define USART3_CR2 USART_CR2(USART3_BASE)
+#define UART4_CR2 USART_CR2(UART4_BASE)
+#define UART5_CR2 USART_CR2(UART5_BASE)
+
+/* Control register 3 (USARTx_CR3) */
+#define USART_CR3(usart_base) MMIO32(usart_base + 0x14)
+#define USART1_CR3 USART_CR3(USART1_BASE)
+#define USART2_CR3 USART_CR3(USART2_BASE)
+#define USART3_CR3 USART_CR3(USART3_BASE)
+#define UART4_CR3 USART_CR3(UART4_BASE)
+#define UART5_CR3 USART_CR3(UART5_BASE)
+
+/* Guard time and prescaler register (USARTx_GTPR) */
+#define USART_GTPR(usart_base) MMIO32(usart_base + 0x18)
+#define USART1_GTPR USART_GTPR(USART1_BASE)
+#define USART2_GTPR USART_GTPR(USART2_BASE)
+#define USART3_GTPR USART_GTPR(USART3_BASE)
+#define UART4_GTPR USART_GTPR(UART4_BASE)
+#define UART5_GTPR USART_GTPR(UART5_BASE)
+
+/* --- USART_SR values ----------------------------------------------------- */
+/****************************************************************************/
+/** @defgroup usart_sr_flags USART Status register Flags
+@ingroup STM32F_usart_defines
+
+@{*/
+
+/** CTS: CTS flag */
+/** @note: undefined on UART4 and UART5 */
+#define USART_SR_CTS (1 << 9)
+
+/** LBD: LIN break detection flag */
+#define USART_SR_LBD (1 << 8)
+
+/** TXE: Transmit data buffer empty */
+#define USART_SR_TXE (1 << 7)
+
+/** TC: Transmission complete */
+#define USART_SR_TC (1 << 6)
+
+/** RXNE: Read data register not empty */
+#define USART_SR_RXNE (1 << 5)
+
+/** IDLE: Idle line detected */
+#define USART_SR_IDLE (1 << 4)
+
+/** ORE: Overrun error */
+#define USART_SR_ORE (1 << 3)
+
+/** NE: Noise error flag */
+#define USART_SR_NE (1 << 2)
+
+/** FE: Framing error */
+#define USART_SR_FE (1 << 1)
+
+/** PE: Parity error */
+#define USART_SR_PE (1 << 0)
+/**@}*/
+
+/* --- USART_DR values ----------------------------------------------------- */
+
+/* USART_DR[8:0]: DR[8:0]: Data value */
+#define USART_DR_MASK 0x1FF
+
+/* --- USART_BRR values ---------------------------------------------------- */
+
+/* DIV_Mantissa[11:0]: mantissa of USARTDIV */
+#define USART_BRR_DIV_MANTISSA_MASK (0xFFF << 4)
+/* DIV_Fraction[3:0]: fraction of USARTDIV */
+#define USART_BRR_DIV_FRACTION_MASK 0xF
+
+/* --- USART_CR1 values ---------------------------------------------------- */
+
+/* UE: USART enable */
+#define USART_CR1_UE (1 << 13)
+
+/* M: Word length */
+#define USART_CR1_M (1 << 12)
+
+/* WAKE: Wakeup method */
+#define USART_CR1_WAKE (1 << 11)
+
+/* PCE: Parity control enable */
+#define USART_CR1_PCE (1 << 10)
+
+/* PS: Parity selection */
+#define USART_CR1_PS (1 << 9)
+
+/* PEIE: PE interrupt enable */
+#define USART_CR1_PEIE (1 << 8)
+
+/* TXEIE: TXE interrupt enable */
+#define USART_CR1_TXEIE (1 << 7)
+
+/* TCIE: Transmission complete interrupt enable */
+#define USART_CR1_TCIE (1 << 6)
+
+/* RXNEIE: RXNE interrupt enable */
+#define USART_CR1_RXNEIE (1 << 5)
+
+/* IDLEIE: IDLE interrupt enable */
+#define USART_CR1_IDLEIE (1 << 4)
+
+/* TE: Transmitter enable */
+#define USART_CR1_TE (1 << 3)
+
+/* RE: Receiver enable */
+#define USART_CR1_RE (1 << 2)
+
+/* RWU: Receiver wakeup */
+#define USART_CR1_RWU (1 << 1)
+
+/* SBK: Send break */
+#define USART_CR1_SBK (1 << 0)
+
+/* --- USART_CR2 values ---------------------------------------------------- */
+
+/* LINEN: LIN mode enable */
+#define USART_CR2_LINEN (1 << 14)
+
+/* STOP[13:12]: STOP bits */
+#define USART_CR2_STOPBITS_1 (0x00 << 12) /* 1 stop bit */
+#define USART_CR2_STOPBITS_0_5 (0x01 << 12) /* 0.5 stop bits */
+#define USART_CR2_STOPBITS_2 (0x02 << 12) /* 2 stop bits */
+#define USART_CR2_STOPBITS_1_5 (0x03 << 12) /* 1.5 stop bits */
+#define USART_CR2_STOPBITS_MASK (0x03 << 12)
+#define USART_CR2_STOPBITS_SHIFT 12
+
+/* CLKEN: Clock enable */
+#define USART_CR2_CLKEN (1 << 11)
+
+/* CPOL: Clock polarity */
+#define USART_CR2_CPOL (1 << 10)
+
+/* CPHA: Clock phase */
+#define USART_CR2_CPHA (1 << 9)
+
+/* LBCL: Last bit clock pulse */
+#define USART_CR2_LBCL (1 << 8)
+
+/* LBDIE: LIN break detection interrupt enable */
+#define USART_CR2_LBDIE (1 << 6)
+
+/* LBDL: LIN break detection length */
+#define USART_CR2_LBDL (1 << 5)
+
+/* ADD[3:0]: Addres of the usart node */
+#define USART_CR2_ADD_MASK 0xF
+
+/* --- USART_CR3 values ---------------------------------------------------- */
+
+/* CTSIE: CTS interrupt enable */
+/* Note: N/A on UART4 & UART5 */
+#define USART_CR3_CTSIE (1 << 10)
+
+/* CTSE: CTS enable */
+/* Note: N/A on UART4 & UART5 */
+#define USART_CR3_CTSE (1 << 9)
+
+/* RTSE: RTS enable */
+/* Note: N/A on UART4 & UART5 */
+#define USART_CR3_RTSE (1 << 8)
+
+/* DMAT: DMA enable transmitter */
+/* Note: N/A on UART5 */
+#define USART_CR3_DMAT (1 << 7)
+
+/* DMAR: DMA enable receiver */
+/* Note: N/A on UART5 */
+#define USART_CR3_DMAR (1 << 6)
+
+/* SCEN: Smartcard mode enable */
+/* Note: N/A on UART4 & UART5 */
+#define USART_CR3_SCEN (1 << 5)
+
+/* NACK: Smartcard NACK enable */
+/* Note: N/A on UART4 & UART5 */
+#define USART_CR3_NACK (1 << 4)
+
+/* HDSEL: Half-duplex selection */
+#define USART_CR3_HDSEL (1 << 3)
+
+/* IRLP: IrDA low-power */
+#define USART_CR3_IRLP (1 << 2)
+
+/* IREN: IrDA mode enable */
+#define USART_CR3_IREN (1 << 1)
+
+/* EIE: Error interrupt enable */
+#define USART_CR3_EIE (1 << 0)
+
+/* --- USART_GTPR values --------------------------------------------------- */
+
+/* GT[7:0]: Guard time value */
+/* Note: N/A on UART4 & UART5 */
+#define USART_GTPR_GT_MASK (0xFF << 8)
+
+/* PSC[7:0]: Prescaler value */
+/* Note: N/A on UART4/5 */
+#define USART_GTPR_PSC_MASK 0xFF
+
+/* TODO */ /* Note to Uwe: what needs to be done here? */
+
+/* --- Convenience defines ------------------------------------------------- */
+
+/* CR1_PCE / CR1_PS combined values */
+/****************************************************************************/
+/** @defgroup usart_cr1_parity USART Parity Selection
+@ingroup STM32F_usart_defines
+
+@{*/
+#define USART_PARITY_NONE 0x00
+#define USART_PARITY_EVEN USART_CR1_PCE
+#define USART_PARITY_ODD (USART_CR1_PS | USART_CR1_PCE)
+/**@}*/
+#define USART_PARITY_MASK (USART_CR1_PS | USART_CR1_PCE)
+
+/* CR1_TE/CR1_RE combined values */
+/****************************************************************************/
+/** @defgroup usart_cr1_mode USART Tx/Rx Mode Selection
+@ingroup STM32F_usart_defines
+
+@{*/
+#define USART_MODE_RX USART_CR1_RE
+#define USART_MODE_TX USART_CR1_TE
+#define USART_MODE_TX_RX (USART_CR1_RE | USART_CR1_TE)
+/**@}*/
+#define USART_MODE_MASK (USART_CR1_RE | USART_CR1_TE)
+
+/****************************************************************************/
+/** @defgroup usart_cr2_stopbits USART Stop Bit Selection
+@ingroup STM32F_usart_defines
+
+@{*/
+#define USART_STOPBITS_1 USART_CR2_STOPBITS_1 /* 1 stop bit */
+#define USART_STOPBITS_0_5 USART_CR2_STOPBITS_0_5 /* 0.5 stop bits */
+#define USART_STOPBITS_2 USART_CR2_STOPBITS_2 /* 2 stop bits */
+#define USART_STOPBITS_1_5 USART_CR2_STOPBITS_1_5 /* 1.5 stop bits */
+/**@}*/
+
+/* CR3_CTSE/CR3_RTSE combined values */
+/****************************************************************************/
+/** @defgroup usart_cr3_flowcontrol USART Hardware Flow Control Selection
+@ingroup STM32F_usart_defines
+
+@{*/
+#define USART_FLOWCONTROL_NONE 0x00
+#define USART_FLOWCONTROL_RTS USART_CR3_RTSE
+#define USART_FLOWCONTROL_CTS USART_CR3_CTSE
+#define USART_FLOWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)
+/**@}*/
+#define USART_FLOWCONTROL_MASK (USART_CR3_RTSE | USART_CR3_CTSE)
+
+/* --- Function prototypes ------------------------------------------------- */
+
+BEGIN_DECLS
+
+void usart_set_baudrate(u32 usart, u32 baud);
+void usart_set_databits(u32 usart, u32 bits);
+void usart_set_stopbits(u32 usart, u32 stopbits);
+void usart_set_parity(u32 usart, u32 parity);
+void usart_set_mode(u32 usart, u32 mode);
+void usart_set_flow_control(u32 usart, u32 flowcontrol);
+void usart_enable(u32 usart);
+void usart_disable(u32 usart);
+void usart_send(u32 usart, u16 data);
+u16 usart_recv(u32 usart);
+void usart_wait_send_ready(u32 usart);
+void usart_wait_recv_ready(u32 usart);
+void usart_send_blocking(u32 usart, u16 data);
+u16 usart_recv_blocking(u32 usart);
+void usart_enable_rx_dma(u32 usart);
+void usart_disable_rx_dma(u32 usart);
+void usart_enable_tx_dma(u32 usart);
+void usart_disable_tx_dma(u32 usart);
+void usart_enable_rx_interrupt(u32 usart);
+void usart_disable_rx_interrupt(u32 usart);
+void usart_enable_tx_interrupt(u32 usart);
+void usart_disable_tx_interrupt(u32 usart);
+bool usart_get_flag(u32 usart, u32 flag);
+bool usart_get_interrupt_source(u32 usart, u32 flag);
+
+END_DECLS
+
+#endif
+/**@}*/
+
diff --git a/include/libopencm3/stm32/common/usart_common_f24.h b/include/libopencm3/stm32/common/usart_common_f24.h
new file mode 100644
index 0000000..089a0c2
--- /dev/null
+++ b/include/libopencm3/stm32/common/usart_common_f24.h
@@ -0,0 +1,66 @@
+/** @addtogroup usart_defines */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
+ * Copyright (C) 2011 Stephen Caudle <scaudle@doceme.com>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA SPI.H */
+
+#ifndef LIBOPENCM3_USART_COMMON_F24_H
+#define LIBOPENCM3_USART_COMMON_F24_H
+
+#include <libopencm3/stm32/common/usart_common_all.h>
+
+/* --- Convenience macros -------------------------------------------------- */
+
+#define USART6 USART6_BASE
+
+/* --- USART registers ----------------------------------------------------- */
+
+/* Status register (USARTx_SR) */
+#define USART6_SR USART_SR(USART6_BASE)
+
+/* Data register (USARTx_DR) */
+#define USART6_DR USART_DR(USART6_BASE)
+
+/* Baud rate register (USARTx_BRR) */
+#define USART6_BRR USART_BRR(USART6_BASE)
+
+/* Control register 1 (USARTx_CR1) */
+#define USART6_CR1 USART_CR1(USART6_BASE)
+
+/* Control register 2 (USARTx_CR2) */
+#define USART6_CR2 USART_CR2(USART6_BASE)
+
+/* Control register 3 (USARTx_CR3) */
+#define USART6_CR3 USART_CR3(USART6_BASE)
+
+/* Guard time and prescaler register (USARTx_GTPR) */
+#define USART6_GTPR USART_GTPR(USART6_BASE)
+
+/* --- USART_CR1 values ---------------------------------------------------- */
+
+/* OVER8: Oversampling mode */
+#define USART_CR1_OVER8 (1 << 15)
+
+/* --- USART_CR3 values ---------------------------------------------------- */
+
+/* ONEBIT: One sample bit method enable */
+#define USART_CR3_ONEBIT (1 << 11)
+
+#endif
diff --git a/include/libopencm3/stm32/crc.h b/include/libopencm3/stm32/crc.h
index aa30182..3d43061 100644
--- a/include/libopencm3/stm32/crc.h
+++ b/include/libopencm3/stm32/crc.h
@@ -1,22 +1,8 @@
-/** @defgroup crc_defines CRC Defines
+/* This provides unification of code over STM32F subfamilies */
-@brief <b>libopencm3 Defined Constants and Types for the STM32F CRC Generator </b>
-
-@ingroup STM32F_defines
-
-@version 1.0.0
-
-@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
-
-@date 18 August 2012
-
-LGPL License Terms @ref lgpl_license
- */
/*
* This file is part of the libopencm3 project.
*
- * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
- *
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
@@ -31,66 +17,15 @@ LGPL License Terms @ref lgpl_license
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
-#ifndef LIBOPENCM3_CRC_H
-#define LIBOPENCM3_CRC_H
-
-#include <libopencm3/stm32/memorymap.h>
-#include <libopencm3/cm3/common.h>
-
-/* --- CRC registers ------------------------------------------------------- */
-
-/* Data register (CRC_DR) */
-#define CRC_DR MMIO32(CRC_BASE + 0x00)
-
-/* Independent data register (CRC_IDR) */
-#define CRC_IDR MMIO32(CRC_BASE + 0x04)
-
-/* Control register (CRC_CR) */
-#define CRC_CR MMIO32(CRC_BASE + 0x08)
-
-/* --- CRC_DR values ------------------------------------------------------- */
-
-/* Bits [31:0]: Data register */
-
-/* --- CRC_IDR values ------------------------------------------------------ */
-
-/* Bits [31:8]: Reserved */
-
-/* Bits [7:0]: General-purpose 8-bit data register bits */
-
-/* --- CRC_CR values ------------------------------------------------------- */
-
-/* Bits [31:1]: Reserved */
-
-/* RESET bit */
-#define CRC_CR_RESET (1 << 0)
-
-/* --- CRC function prototypes --------------------------------------------- */
-
-BEGIN_DECLS
-
-/* TODO */
-
-/**
- * Reset the CRC calculator to initial values.
- */
-void crc_reset(void);
-
-/**
- * Add a word to the crc calculator and return the result.
- * @param data new word to add to the crc calculator
- * @return final crc calculator value
- */
-u32 crc_calculate(u32 data);
-
-/**
- * Add a block of data to the CRC calculator and return the final result
- * @param datap pointer to the start of a block of 32bit data words
- * @param size length of data, in 32bit increments
- * @return final CRC calculator value
- */
-u32 crc_calculate_block(u32 *datap, int size);
-
-END_DECLS
-
+#if defined(STM32F1)
+# include <libopencm3/stm32/f1/crc.h>
+#elif defined(STM32F2)
+# include <libopencm3/stm32/f2/crc.h>
+#elif defined(STM32F4)
+# include <libopencm3/stm32/f4/crc.h>
+#elif defined(STM32L1)
+# include <libopencm3/stm32/l1/crc.h>
+#else
+# error "stm32 family not defined."
#endif
+
diff --git a/include/libopencm3/stm32/dac.h b/include/libopencm3/stm32/dac.h
index 75d4edb..242ef89 100644
--- a/include/libopencm3/stm32/dac.h
+++ b/include/libopencm3/stm32/dac.h
@@ -1,24 +1,8 @@
-/** @defgroup STM32F_dac_defines DAC Defines
-
-@brief <b>libopencm3 Defined Constants and Types for the STM32F Digital to Analog Converter </b>
-
-@ingroup STM32F_defines
-
-@version 1.0.0
-
-@author @htmlonly &copy; @endhtmlonly 2012 Felix Held <felix-libopencm3@felixheld.de>
-@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies
-
-@date 18 August 2012
-
-LGPL License Terms @ref lgpl_license
- */
+/* This provides unification of code over STM32F subfamilies */
/*
* This file is part of the libopencm3 project.
*
- * Copyright (C) 2012 Felix Held <felix-libopencm3@felixheld.de>
- *
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
@@ -33,386 +17,15 @@ LGPL License Terms @ref lgpl_license
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
-/**@{*/
-
-#ifndef LIBOPENCM3_DAC_H
-#define LIBOPENCM3_DAC_H
-
-#include <libopencm3/stm32/memorymap.h>
-#include <libopencm3/cm3/common.h>
-
-
-/* --- DAC registers ------------------------------------------------------- */
-
-/* DAC control register (DAC_CR) */
-#define DAC_CR MMIO32(DAC_BASE + 0x00)
-
-/* DAC software trigger register (DAC_SWTRIGR) */
-#define DAC_SWTRIGR MMIO32(DAC_BASE + 0x04)
-
-/* DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) */
-#define DAC_DHR12R1 MMIO32(DAC_BASE + 0x08)
-
-/* DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) */
-#define DAC_DHR12L1 MMIO32(DAC_BASE + 0x0C)
-
-/* DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) */
-#define DAC_DHR8R1 MMIO32(DAC_BASE + 0x10)
-
-/* DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) */
-#define DAC_DHR12R2 MMIO32(DAC_BASE + 0x14)
-
-/* DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) */
-#define DAC_DHR12L2 MMIO32(DAC_BASE + 0x18)
-
-/* DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) */
-#define DAC_DHR8R2 MMIO32(DAC_BASE + 0x1C)
-
-/* Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) */
-#define DAC_DHR12RD MMIO32(DAC_BASE + 0x20)
-
-/* DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD) */
-#define DAC_DHR12LD MMIO32(DAC_BASE + 0x24)
-
-/* DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD) */
-#define DAC_DHR8RD MMIO32(DAC_BASE + 0x28)
-
-/* DAC channel1 data output register (DAC_DOR1) */
-#define DAC_DOR1 MMIO32(DAC_BASE + 0x2C)
-
-/* DAC channel2 data output register (DAC_DOR2) */
-#define DAC_DOR2 MMIO32(DAC_BASE + 0x30)
-
-
-/* --- DAC_CR values ------------------------------------------------------- */
-
-/* DMAUDRIE2: DAC channel2 DMA underrun interrupt enable */
-/* doesn't exist in most members of the STM32F1 family */
-#define DAC_CR_DMAUDRIE2 (1 << 29)
-
-/* DMAEN2: DAC channel2 DMA enable */
-#define DAC_CR_DMAEN2 (1 << 28)
-
-/* MAMP2[3:0]: DAC channel2 mask/amplitude selector */
-/* DAC_CR_MAMP2_n:
- * Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**n)-1
- */
-#define DAC_CR_MAMP2_SHIFT 24
-/** @defgroup dac_mamp2 DAC Channel 2 LFSR Mask and Triangle Wave Amplitude values
-@ingroup STM32F_dac_defines
-
-Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n)-1
-@{*/
-#define DAC_CR_MAMP2_1 (0x0 << DAC_CR_MAMP2_SHIFT)
-#define DAC_CR_MAMP2_2 (0x1 << DAC_CR_MAMP2_SHIFT)
-#define DAC_CR_MAMP2_3 (0x2 << DAC_CR_MAMP2_SHIFT)
-#define DAC_CR_MAMP2_4 (0x3 << DAC_CR_MAMP2_SHIFT)
-#define DAC_CR_MAMP2_5 (0x4 << DAC_CR_MAMP2_SHIFT)
-#define DAC_CR_MAMP2_6 (0x5 << DAC_CR_MAMP2_SHIFT)
-#define DAC_CR_MAMP2_7 (0x6 << DAC_CR_MAMP2_SHIFT)
-#define DAC_CR_MAMP2_8 (0x7 << DAC_CR_MAMP2_SHIFT)
-#define DAC_CR_MAMP2_9 (0x8 << DAC_CR_MAMP2_SHIFT)
-#define DAC_CR_MAMP2_10 (0x9 << DAC_CR_MAMP2_SHIFT)
-#define DAC_CR_MAMP2_11 (0xA << DAC_CR_MAMP2_SHIFT)
-#define DAC_CR_MAMP2_12 (0xB << DAC_CR_MAMP2_SHIFT)
-/**@}*/
-
-/* WAVE2[1:0]: DAC channel2 noise/triangle wave generation enable */
-/* Legend:
- * DIS: wave generation disabled
- * NOISE: Noise wave generation enabled
- * TRI: Triangle wave generation enabled
- *
- * Note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled)
- */
-#define DAC_CR_WAVE2_SHIFT 22
-#define DAC_CR_WAVE2_DIS (0x3 << DAC_CR_WAVE2_SHIFT)
-/** @defgroup dac_wave2_en DAC Channel 2 Waveform Generation Enable
-@ingroup STM32F_dac_defines
-
-@li NOISE: Noise wave generation enabled
-@li TRI: Triangle wave generation enabled
-
-@note: only used if bit TEN2 is set (DAC channel2 trigger enabled)
-@{*/
-#define DAC_CR_WAVE2_NOISE (0x1 << DAC_CR_WAVE2_SHIFT)
-#define DAC_CR_WAVE2_TRI (0x2 << DAC_CR_WAVE2_SHIFT)
-/**@}*/
-
-/* TSEL2[2:0]: DAC channel2 trigger selection */
-/* Legend:
- *
- * T6: Timer 6 TRGO event
- * T3: Timer 3 TRGO event
- * T8: Timer 8 TRGO event
- * T7: Timer 7 TRGO event
- * T5: Timer 5 TRGO event
- * T15: Timer 15 TRGO event
- * T2: Timer 2 TRGO event
- * T4: Timer 4 TRGO event
- * E9: External line9
- * SW: Software trigger
- *
- * Note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled)
- * Note: T3 == T8; T5 == T15; not both present on one device
- * Note: this is *not* valid for the STM32L1 family
- */
-#define DAC_CR_TSEL2_SHIFT 19
-/** @defgroup dac_trig2_sel DAC Channel 2 Trigger Source Selection
-@ingroup STM32F_dac_defines
-
-@li T6: Timer 6 TRGO event
-@li T3: Timer 3 TRGO event
-@li T8: Timer 8 TRGO event
-@li T7: Timer 7 TRGO event
-@li T5: Timer 5 TRGO event
-@li T15: Timer 15 TRGO event
-@li T2: Timer 2 TRGO event
-@li T4: Timer 4 TRGO event
-@li E9: External line9
-@li SW: Software trigger
-
-@note: Refer to the timer documentation for details of the TRGO event.
-@note: T3 replaced by T8 and T5 replaced by T15 in some devices.
-@note: this is <b>not</b> valid for the STM32L1 family.
-@note: only used if bit TEN2 is set (DAC channel 2 trigger enabled)
-@{*/
-#define DAC_CR_TSEL2_T6 (0x0 << DAC_CR_TSEL2_SHIFT)
-#define DAC_CR_TSEL2_T3 (0x1 << DAC_CR_TSEL2_SHIFT)
-#define DAC_CR_TSEL2_T8 (0x1 << DAC_CR_TSEL2_SHIFT)
-#define DAC_CR_TSEL2_T7 (0x2 << DAC_CR_TSEL2_SHIFT)
-#define DAC_CR_TSEL2_T5 (0x3 << DAC_CR_TSEL2_SHIFT)
-#define DAC_CR_TSEL2_T15 (0x3 << DAC_CR_TSEL2_SHIFT)
-#define DAC_CR_TSEL2_T2 (0x4 << DAC_CR_TSEL2_SHIFT)
-#define DAC_CR_TSEL2_T4 (0x5 << DAC_CR_TSEL2_SHIFT)
-#define DAC_CR_TSEL2_E9 (0x6 << DAC_CR_TSEL2_SHIFT)
-#define DAC_CR_TSEL2_SW (0x7 << DAC_CR_TSEL2_SHIFT)
-/**@}*/
-
-/* TEN2: DAC channel2 trigger enable */
-#define DAC_CR_TEN2 (1 << 18)
-
-/* BOFF2: DAC channel2 output buffer disable */
-#define DAC_CR_BOFF2 (1 << 17)
-
-/* EN2: DAC channel2 enable */
-#define DAC_CR_EN2 (1 << 16)
-
-/* DMAUDRIE1: DAC channel1 DMA underrun interrupt enable */
-/* doesn't exist in most members of the STM32F1 family */
-#define DAC_CR_DMAUDRIE1 (1 << 13)
-
-/* DMAEN1: DAC channel1 DMA enable */
-#define DAC_CR_DMAEN1 (1 << 12)
-
-/* MAMP1[3:0]: DAC channel1 mask/amplitude selector */
-/* DAC_CR_MAMP1_n:
- * Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**n)-1
- */
-#define DAC_CR_MAMP1_SHIFT 8
-/** @defgroup dac_mamp1 DAC Channel 1 LFSR Mask and Triangle Wave Amplitude values
-@ingroup STM32F_dac_defines
-
-Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n+1)-1
-@{*/
-#define DAC_CR_MAMP1_1 (0x0 << DAC_CR_MAMP1_SHIFT)
-#define DAC_CR_MAMP1_2 (0x1 << DAC_CR_MAMP1_SHIFT)
-#define DAC_CR_MAMP1_3 (0x2 << DAC_CR_MAMP1_SHIFT)
-#define DAC_CR_MAMP1_4 (0x3 << DAC_CR_MAMP1_SHIFT)
-#define DAC_CR_MAMP1_5 (0x4 << DAC_CR_MAMP1_SHIFT)
-#define DAC_CR_MAMP1_6 (0x5 << DAC_CR_MAMP1_SHIFT)
-#define DAC_CR_MAMP1_7 (0x6 << DAC_CR_MAMP1_SHIFT)
-#define DAC_CR_MAMP1_8 (0x7 << DAC_CR_MAMP1_SHIFT)
-#define DAC_CR_MAMP1_9 (0x8 << DAC_CR_MAMP1_SHIFT)
-#define DAC_CR_MAMP1_10 (0x9 << DAC_CR_MAMP1_SHIFT)
-#define DAC_CR_MAMP1_11 (0xA << DAC_CR_MAMP1_SHIFT)
-#define DAC_CR_MAMP1_12 (0xB << DAC_CR_MAMP1_SHIFT)
-/**@}*/
-
-/* WAVE1[1:0]: DAC channel1 noise/triangle wave generation enable */
-/* Legend:
- * DIS: wave generation disabled
- * NOISE: Noise wave generation enabled
- * TRI: Triangle wave generation enabled
- *
- * Note: only used if bit TEN1 = 1 (DAC channel1 trigger enabled)
- */
-#define DAC_CR_WAVE1_SHIFT 6
-#define DAC_CR_WAVE1_DIS (0x3 << DAC_CR_WAVE1_SHIFT)
-/** @defgroup dac_wave1_en DAC Channel 1 Waveform Generation Enable
-@ingroup STM32F_dac_defines
-
-@li DIS: wave generation disabled
-@li NOISE: Noise wave generation enabled
-@li TRI: Triangle wave generation enabled
-
-@note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled)
-@{*/
-#define DAC_CR_WAVE1_NOISE (0x1 << DAC_CR_WAVE1_SHIFT)
-#define DAC_CR_WAVE1_TRI (0x2 << DAC_CR_WAVE1_SHIFT)
-/**@}*/
-
-/* TSEL1[2:0]: DAC channel1 trigger selection */
-/* Legend:
- *
- * T6: Timer 6 TRGO event
- * T3: Timer 3 TRGO event in connectivity line devices
- * T8: Timer 8 TRGO event in high-density and XL-density devices
- * T7: Timer 7 TRGO event
- * T5: Timer 5 TRGO event
- * T15: Timer 15 TRGO event
- * T2: Timer 2 TRGO event
- * T4: Timer 4 TRGO event
- * E9: External line9
- * SW: Software trigger
- *
- * Note: only used if bit TEN1 = 1 (DAC channel1 trigger enabled)
- * Note: T3 == T8; T5 == T15; not both present on one device
- * Note: this is *not* valid for the STM32L1 family
- */
-#define DAC_CR_TSEL1_SHIFT 3
-/** @defgroup dac_trig1_sel DAC Channel 1 Trigger Source Selection
-@ingroup STM32F_dac_defines
-
-@li T6: Timer 6 TRGO event
-@li T3: Timer 3 TRGO event
-@li T8: Timer 8 TRGO event
-@li T7: Timer 7 TRGO event
-@li T5: Timer 5 TRGO event
-@li T15: Timer 15 TRGO event
-@li T2: Timer 2 TRGO event
-@li T4: Timer 4 TRGO event
-@li E9: External line 9
-@li SW: Software trigger
-
-@note: Refer to the timer documentation for details of the TRGO event.
-@note: T3 replaced by T8 and T5 replaced by T15 in some devices.
-@note: this is <b>not</b> valid for the STM32L1 family.
-@note: only used if bit TEN2 is set (DAC channel 1 trigger enabled).
-@{*/
-#define DAC_CR_TSEL1_T6 (0x0 << DAC_CR_TSEL1_SHIFT)
-#define DAC_CR_TSEL1_T3 (0x1 << DAC_CR_TSEL1_SHIFT)
-#define DAC_CR_TSEL1_T8 (0x1 << DAC_CR_TSEL1_SHIFT)
-#define DAC_CR_TSEL1_T7 (0x2 << DAC_CR_TSEL1_SHIFT)
-#define DAC_CR_TSEL1_T5 (0x3 << DAC_CR_TSEL1_SHIFT)
-#define DAC_CR_TSEL1_T15 (0x3 << DAC_CR_TSEL1_SHIFT)
-#define DAC_CR_TSEL1_T2 (0x4 << DAC_CR_TSEL1_SHIFT)
-#define DAC_CR_TSEL1_T4 (0x5 << DAC_CR_TSEL1_SHIFT)
-#define DAC_CR_TSEL1_E9 (0x6 << DAC_CR_TSEL1_SHIFT)
-#define DAC_CR_TSEL1_SW (0x7 << DAC_CR_TSEL1_SHIFT)
-/**@}*/
-
-/* TEN1: DAC channel1 trigger enable */
-#define DAC_CR_TEN1 (1 << 2)
-
-/* BOFF1: DAC channel1 output buffer disable */
-#define DAC_CR_BOFF1 (1 << 1)
-
-/* EN1: DAC channel1 enable */
-#define DAC_CR_EN1 (1 << 0)
-
-
-/* --- DAC_SWTRIGR values -------------------------------------------------- */
-
-/* SWTRIG2: DAC channel2 software trigger */
-#define DAC_SWTRIGR_SWTRIG2 (1 << 1)
-
-/* SWTRIG1: DAC channel1 software trigger */
-#define DAC_SWTRIGR_SWTRIG1 (1 << 0)
-
-
-/* --- DAC_DHR12R1 values -------------------------------------------------- */
-#define DAC_DHR12R1_DACC1DHR_LSB (1 << 0)
-#define DAC_DHR12R1_DACC1DHR_MSK (0x0FFF << 0)
-
-
-/* --- DAC_DHR12L1 values -------------------------------------------------- */
-#define DAC_DHR12L1_DACC1DHR_LSB (1 << 4)
-#define DAC_DHR12L1_DACC1DHR_MSK (0x0FFF << 4)
-
-
-/* --- DAC_DHR8R1 values --------------------------------------------------- */
-#define DAC_DHR8R1_DACC1DHR_LSB (1 << 0)
-#define DAC_DHR8R1_DACC1DHR_MSK (0x00FF << 0)
-
-
-/* --- DAC_DHR12R2 values -------------------------------------------------- */
-#define DAC_DHR12R2_DACC2DHR_LSB (1 << 0)
-#define DAC_DHR12R2_DACC2DHR_MSK (0x00FFF << 0)
-
-
-/* --- DAC_DHR12L2 values -------------------------------------------------- */
-#define DAC_DHR12L2_DACC2DHR_LSB (1 << 4)
-#define DAC_DHR12L2_DACC2DHR_MSK (0x0FFF << 4)
-
-
-/* --- DAC_DHR8R2 values --------------------------------------------------- */
-#define DAC_DHR8R2_DACC2DHR_LSB (1 << 0)
-#define DAC_DHR8R2_DACC2DHR_MSK (0x00FF << 0)
-
-
-/* --- DAC_DHR12RD values -------------------------------------------------- */
-#define DAC_DHR12RD_DACC2DHR_LSB (1 << 16)
-#define DAC_DHR12RD_DACC2DHR_MSK (0x0FFF << 16)
-#define DAC_DHR12RD_DACC1DHR_LSB (1 << 0)
-#define DAC_DHR12RD_DACC1DHR_MSK (0x0FFF << 0)
-
-
-/* --- DAC_DHR12LD values -------------------------------------------------- */
-#define DAC_DHR12LD_DACC2DHR_LSB (1 << 16)
-#define DAC_DHR12LD_DACC2DHR_MSK (0x0FFF << 20)
-#define DAC_DHR12LD_DACC1DHR_LSB (1 << 0)
-#define DAC_DHR12LD_DACC1DHR_MSK (0x0FFF << 4)
-
-
-/* --- DAC_DHR8RD values --------------------------------------------------- */
-#define DAC_DHR8RD_DACC2DHR_LSB (1 << 8)
-#define DAC_DHR8RD_DACC2DHR_MSK (0x00FF << 8)
-#define DAC_DHR8RD_DACC1DHR_LSB (1 << 0)
-#define DAC_DHR8RD_DACC1DHR_MSK (0x00FF << 0)
-
-
-/* --- DAC_DOR1 values ----------------------------------------------------- */
-#define DAC_DOR1_DACC1DOR_LSB (1 << 0)
-#define DAC_DOR1_DACC1DOR_MSK (0x0FFF << 0)
-
-
-/* --- DAC_DOR2 values ----------------------------------------------------- */
-#define DAC_DOR2_DACC2DOR_LSB (1 << 0)
-#define DAC_DOR2_DACC2DOR_MSK (0x0FFF << 0)
-
-/** DAC channel identifier */
-typedef enum {
- CHANNEL_1, CHANNEL_2, CHANNEL_D
-} data_channel;
-
-/** DAC data size (8/12 bits), alignment (right/left) */
-typedef enum {
- RIGHT8, RIGHT12, LEFT12
-} data_align;
-
-/* --- Function prototypes ------------------------------------------------- */
-
-BEGIN_DECLS
-
-void dac_enable(data_channel dac_channel);
-void dac_disable(data_channel dac_channel);
-void dac_buffer_enable(data_channel dac_channel);
-void dac_buffer_disable(data_channel dac_channel);
-void dac_dma_enable(data_channel dac_channel);
-void dac_dma_disable(data_channel dac_channel);
-void dac_trigger_enable(data_channel dac_channel);
-void dac_trigger_disable(data_channel dac_channel);
-void dac_set_trigger_source(u32 dac_trig_src);
-void dac_set_waveform_generation(u32 dac_wave_ens);
-void dac_disable_waveform_generation(data_channel dac_channel);
-void dac_set_waveform_characteristics(u32 dac_mamp);
-void dac_load_data_buffer_single(u32 dac_data, data_align dac_data_format, data_channel dac_channel);
-void dac_load_data_buffer_dual(u32 dac_data1, u32 dac_data2, data_align dac_data_format);
-void dac_software_trigger(data_channel dac_channel);
-
-END_DECLS
-
+#if defined(STM32F1)
+# include <libopencm3/stm32/f1/dac.h>
+#elif defined(STM32F2)
+# include <libopencm3/stm32/f2/dac.h>
+#elif defined(STM32F4)
+# include <libopencm3/stm32/f4/dac.h>
+#elif defined(STM32L1)
+# include <libopencm3/stm32/l1/dac.h>
+#else
+# error "stm32 family not defined."
#endif
-/**@}*/
diff --git a/include/libopencm3/stm32/f1/desig.h b/include/libopencm3/stm32/desig.h
index 74cfb35..6ceb665 100644
--- a/include/libopencm3/stm32/f1/desig.h
+++ b/include/libopencm3/stm32/desig.h
@@ -51,6 +51,15 @@ u16 desig_get_flash_size(void);
*/
void desig_get_unique_id(u32 result[]);
+/**
+ * Read the full 96 bit unique identifier and return it as a
+ * zero-terminated string
+ * @param string memory region to write the result to
+ 8 @param string_len the size of string in bytes
+ */
+void desig_get_unique_id_as_string(char *string,
+ unsigned int string_len);
+
END_DECLS
#endif
diff --git a/include/libopencm3/stm32/dma.h b/include/libopencm3/stm32/dma.h
new file mode 100644
index 0000000..3d553e5
--- /dev/null
+++ b/include/libopencm3/stm32/dma.h
@@ -0,0 +1,31 @@
+/* This provides unification of code over STM32F subfamilies */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#if defined(STM32F1)
+# include <libopencm3/stm32/f1/dma.h>
+#elif defined(STM32F2)
+# include <libopencm3/stm32/f2/dma.h>
+#elif defined(STM32F4)
+# include <libopencm3/stm32/f4/dma.h>
+/*#elif defined(STM32L1)
+# include <libopencm3/stm32/l1/dma.h>*/
+#else
+# error "stm32 family not defined."
+#endif
+
diff --git a/include/libopencm3/stm32/exti.h b/include/libopencm3/stm32/exti.h
index 7645825..48065b9 100644
--- a/include/libopencm3/stm32/exti.h
+++ b/include/libopencm3/stm32/exti.h
@@ -53,6 +53,9 @@
#define EXTI17 (1 << 17)
#define EXTI18 (1 << 18)
#define EXTI19 (1 << 19)
+#define EXTI20 (1 << 20)
+#define EXTI21 (1 << 21)
+#define EXTI22 (1 << 22)
/* Trigger types */
typedef enum trigger_e {
diff --git a/include/libopencm3/stm32/f1/crc.h b/include/libopencm3/stm32/f1/crc.h
new file mode 100644
index 0000000..c3b9939
--- /dev/null
+++ b/include/libopencm3/stm32/f1/crc.h
@@ -0,0 +1,40 @@
+/** @defgroup crc_defines CRC Defines
+
+@brief <b>libopencm3 Defined Constants and Types for the STM32F1xx CRC Generator </b>
+
+@ingroup STM32F1xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
+
+@date 18 August 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_CRC_H
+#define LIBOPENCM3_CRC_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/crc_common_all.h>
+
+#endif
diff --git a/include/libopencm3/stm32/f1/dac.h b/include/libopencm3/stm32/f1/dac.h
new file mode 100644
index 0000000..1e6ecfa
--- /dev/null
+++ b/include/libopencm3/stm32/f1/dac.h
@@ -0,0 +1,40 @@
+/** @defgroup dac_defines DAC Defines
+
+@brief <b>Defined Constants and Types for the STM32F1xx DAC</b>
+
+@ingroup STM32F1xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 5 December 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_DAC_H
+#define LIBOPENCM3_DAC_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/dac_common_all.h>
+
+#endif
+
diff --git a/include/libopencm3/stm32/f1/dma.h b/include/libopencm3/stm32/f1/dma.h
index b08803f..e0c55a6 100644
--- a/include/libopencm3/stm32/f1/dma.h
+++ b/include/libopencm3/stm32/f1/dma.h
@@ -7,17 +7,16 @@
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
-@date 18 August 2012
+@date 30 November 2012
LGPL License Terms @ref lgpl_license
*/
+
/*
* This file is part of the libopencm3 project.
*
- * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
- * Copyright (C) 2012 Piotr Esden-Tempski <piotr@esden.net>
- *
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
@@ -32,346 +31,11 @@ LGPL License Terms @ref lgpl_license
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
-/**@{*/
-
#ifndef LIBOPENCM3_DMA_H
#define LIBOPENCM3_DMA_H
#include <libopencm3/stm32/memorymap.h>
-#include <libopencm3/cm3/common.h>
-
-/* --- Convenience macros -------------------------------------------------- */
-
-/* DMA register base adresses (for convenience) */
-#define DMA1 DMA1_BASE
-#define DMA2 DMA2_BASE
-
-/* --- DMA registers ------------------------------------------------------- */
-
-/* DMA interrupt status register (DMAx_ISR) */
-#define DMA_ISR(dma_base) MMIO32(dma_base + 0x00)
-#define DMA1_ISR DMA_ISR(DMA1)
-#define DMA2_ISR DMA_ISR(DMA2)
-
-/* DMA interrupt flag clear register (DMAx_IFCR) */
-#define DMA_IFCR(dma_base) MMIO32(dma_base + 0x04)
-#define DMA1_IFCR DMA_IFCR(DMA1)
-#define DMA2_IFCR DMA_IFCR(DMA2)
-
-/* DMA channel configuration register (DMAx_CCRy) */
-#define DMA_CCR(dma_base, channel) MMIO32(dma_base + 0x08 + \
- (0x14 * ((channel) - 1)))
-
-#define DMA1_CCR(channel) DMA_CCR(DMA1, channel)
-#define DMA1_CCR1 DMA1_CCR(DMA_CHANNEL1)
-#define DMA1_CCR2 DMA1_CCR(DMA_CHANNEL2)
-#define DMA1_CCR3 DMA1_CCR(DMA_CHANNEL3)
-#define DMA1_CCR4 DMA1_CCR(DMA_CHANNEL4)
-#define DMA1_CCR5 DMA1_CCR(DMA_CHANNEL5)
-#define DMA1_CCR6 DMA1_CCR(DMA_CHANNEL6)
-#define DMA1_CCR7 DMA1_CCR(DMA_CHANNEL7)
-
-#define DMA2_CCR(channel) DMA_CCR(DMA2, channel)
-#define DMA2_CCR1 DMA2_CCR(DMA_CHANNEL1)
-#define DMA2_CCR2 DMA2_CCR(DMA_CHANNEL2)
-#define DMA2_CCR3 DMA2_CCR(DMA_CHANNEL3)
-#define DMA2_CCR4 DMA2_CCR(DMA_CHANNEL4)
-#define DMA2_CCR5 DMA2_CCR(DMA_CHANNEL5)
-
-/* DMA number of data register (DMAx_CNDTRy) */
-#define DMA_CNDTR(dma_base, channel) MMIO32(dma_base + 0x0C + \
- (0x14 * ((channel) - 1)))
-
-#define DMA1_CNDTR(channel) DMA_CNDTR(DMA1, channel)
-#define DMA1_CNDTR1 DMA1_CNDTR(DMA_CHANNEL1)
-#define DMA1_CNDTR2 DMA1_CNDTR(DMA_CHANNEL2)
-#define DMA1_CNDTR3 DMA1_CNDTR(DMA_CHANNEL3)
-#define DMA1_CNDTR4 DMA1_CNDTR(DMA_CHANNEL4)
-#define DMA1_CNDTR5 DMA1_CNDTR(DMA_CHANNEL5)
-#define DMA1_CNDTR6 DMA1_CNDTR(DMA_CHANNEL6)
-#define DMA1_CNDTR7 DMA1_CNDTR(DMA_CHANNEL7)
-
-#define DMA2_CNDTR(channel) DMA_CNDTR(DMA2, channel)
-#define DMA2_CNDTR1 DMA2_CNDTR(DMA_CHANNEL1)
-#define DMA2_CNDTR2 DMA2_CNDTR(DMA_CHANNEL2)
-#define DMA2_CNDTR3 DMA2_CNDTR(DMA_CHANNEL3)
-#define DMA2_CNDTR4 DMA2_CNDTR(DMA_CHANNEL4)
-#define DMA2_CNDTR5 DMA2_CNDTR(DMA_CHANNEL5)
-
-/* DMA peripheral address register (DMAx_CPARy) */
-#define DMA_CPAR(dma_base, channel) MMIO32(dma_base + 0x10 + \
- (0x14 * ((channel) - 1)))
-
-#define DMA1_CPAR(channel) DMA_CPAR(DMA1, channel)
-#define DMA1_CPAR1 DMA1_CPAR(DMA_CHANNEL1)
-#define DMA1_CPAR2 DMA1_CPAR(DMA_CHANNEL2)
-#define DMA1_CPAR3 DMA1_CPAR(DMA_CHANNEL3)
-#define DMA1_CPAR4 DMA1_CPAR(DMA_CHANNEL4)
-#define DMA1_CPAR5 DMA1_CPAR(DMA_CHANNEL5)
-#define DMA1_CPAR6 DMA1_CPAR(DMA_CHANNEL6)
-#define DMA1_CPAR7 DMA1_CPAR(DMA_CHANNEL7)
-
-#define DMA2_CPAR(channel) DMA_CPAR(DMA2, channel)
-#define DMA2_CPAR1 DMA2_CPAR(DMA_CHANNEL1)
-#define DMA2_CPAR2 DMA2_CPAR(DMA_CHANNEL2)
-#define DMA2_CPAR3 DMA2_CPAR(DMA_CHANNEL3)
-#define DMA2_CPAR4 DMA2_CPAR(DMA_CHANNEL4)
-#define DMA2_CPAR5 DMA2_CPAR(DMA_CHANNEL5)
-
-/* DMA memory address register (DMAx_CMARy) */
-
-#define DMA_CMAR(dma_base, channel) MMIO32(dma_base + 0x14 + \
- (0x14 * ((channel) - 1)))
-
-#define DMA1_CMAR(channel) DMA_CMAR(DMA1, channel)
-#define DMA1_CMAR1 DMA1_CMAR(DMA_CHANNEL1)
-#define DMA1_CMAR2 DMA1_CMAR(DMA_CHANNEL2)
-#define DMA1_CMAR3 DMA1_CMAR(DMA_CHANNEL3)
-#define DMA1_CMAR4 DMA1_CMAR(DMA_CHANNEL4)
-#define DMA1_CMAR5 DMA1_CMAR(DMA_CHANNEL5)
-#define DMA1_CMAR6 DMA1_CMAR(DMA_CHANNEL6)
-#define DMA1_CMAR7 DMA1_CMAR(DMA_CHANNEL7)
-
-#define DMA2_CMAR(channel) DMA_CMAR(DMA2, channel)
-#define DMA2_CMAR1 DMA2_CMAR(DMA_CHANNEL1)
-#define DMA2_CMAR2 DMA2_CMAR(DMA_CHANNEL2)
-#define DMA2_CMAR3 DMA2_CMAR(DMA_CHANNEL3)
-#define DMA2_CMAR4 DMA2_CMAR(DMA_CHANNEL4)
-#define DMA2_CMAR5 DMA2_CMAR(DMA_CHANNEL5)
-
-/* --- DMA_ISR values ------------------------------------------------------ */
-
-/* TEIF: Transfer error interrupt flag */
-#define DMA_ISR_TEIF_BIT (1 << 3)
-#define DMA_ISR_TEIF(channel) (DMA_ISR_TEIF_BIT << (4 * ((channel) -1)))
-
-#define DMA_ISR_TEIF1 DMA_ISR_TEIF(DMA_CHANNEL1)
-#define DMA_ISR_TEIF2 DMA_ISR_TEIF(DMA_CHANNEL2)
-#define DMA_ISR_TEIF3 DMA_ISR_TEIF(DMA_CHANNEL3)
-#define DMA_ISR_TEIF4 DMA_ISR_TEIF(DMA_CHANNEL4)
-#define DMA_ISR_TEIF5 DMA_ISR_TEIF(DMA_CHANNEL5)
-#define DMA_ISR_TEIF6 DMA_ISR_TEIF(DMA_CHANNEL6)
-#define DMA_ISR_TEIF7 DMA_ISR_TEIF(DMA_CHANNEL7)
-
-/* HTIF: Half transfer interrupt flag */
-#define DMA_ISR_HTIF_BIT (1 << 2)
-#define DMA_ISR_HTIF(channel) (DMA_ISR_HTIF_BIT << (4 * ((channel) -1)))
-
-#define DMA_ISR_HTIF1 DMA_ISR_HTIF(DMA_CHANNEL1)
-#define DMA_ISR_HTIF2 DMA_ISR_HTIF(DMA_CHANNEL2)
-#define DMA_ISR_HTIF3 DMA_ISR_HTIF(DMA_CHANNEL3)
-#define DMA_ISR_HTIF4 DMA_ISR_HTIF(DMA_CHANNEL4)
-#define DMA_ISR_HTIF5 DMA_ISR_HTIF(DMA_CHANNEL5)
-#define DMA_ISR_HTIF6 DMA_ISR_HTIF(DMA_CHANNEL6)
-#define DMA_ISR_HTIF7 DMA_ISR_HTIF(DMA_CHANNEL7)
-
-/* TCIF: Transfer complete interrupt flag */
-#define DMA_ISR_TCIF_BIT (1 << 1)
-#define DMA_ISR_TCIF(channel) (DMA_ISR_TCIF_BIT << (4 * ((channel) -1)))
-
-#define DMA_ISR_TCIF1 DMA_ISR_TCIF(DMA_CHANNEL1)
-#define DMA_ISR_TCIF2 DMA_ISR_TCIF(DMA_CHANNEL2)
-#define DMA_ISR_TCIF3 DMA_ISR_TCIF(DMA_CHANNEL3)
-#define DMA_ISR_TCIF4 DMA_ISR_TCIF(DMA_CHANNEL4)
-#define DMA_ISR_TCIF5 DMA_ISR_TCIF(DMA_CHANNEL5)
-#define DMA_ISR_TCIF6 DMA_ISR_TCIF(DMA_CHANNEL6)
-#define DMA_ISR_TCIF7 DMA_ISR_TCIF(DMA_CHANNEL7)
-
-/* GIF: Global interrupt flag */
-#define DMA_ISR_GIF_BIT (1 << 0)
-#define DMA_ISR_GIF(channel) (DMA_ISR_GIF_BIT << (4 * ((channel) -1)))
-
-#define DMA_ISR_GIF1 DMA_ISR_GIF(DMA_CHANNEL1)
-#define DMA_ISR_GIF2 DMA_ISR_GIF(DMA_CHANNEL2)
-#define DMA_ISR_GIF3 DMA_ISR_GIF(DMA_CHANNEL3)
-#define DMA_ISR_GIF4 DMA_ISR_GIF(DMA_CHANNEL4)
-#define DMA_ISR_GIF5 DMA_ISR_GIF(DMA_CHANNEL5)
-#define DMA_ISR_GIF6 DMA_ISR_GIF(DMA_CHANNEL6)
-#define DMA_ISR_GIF7 DMA_ISR_GIF(DMA_CHANNEL7)
-
-/* --- DMA_IFCR values ----------------------------------------------------- */
-
-/* CTEIF: Transfer error clear */
-#define DMA_IFCR_CTEIF_BIT (1 << 3)
-#define DMA_IFCR_CTEIF(channel) (DMA_IFCR_CTEIF_BIT << (4 * ((channel) -1)))
-
-#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF(DMA_CHANNEL1)
-#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF(DMA_CHANNEL2)
-#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF(DMA_CHANNEL3)
-#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF(DMA_CHANNEL4)
-#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF(DMA_CHANNEL5)
-#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF(DMA_CHANNEL6)
-#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF(DMA_CHANNEL7)
-
-/* CHTIF: Half transfer clear */
-#define DMA_IFCR_CHTIF_BIT (1 << 2)
-#define DMA_IFCR_CHTIF(channel) (DMA_IFCR_CHTIF_BIT << (4 * ((channel) -1)))
-
-#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF(DMA_CHANNEL1)
-#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF(DMA_CHANNEL2)
-#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF(DMA_CHANNEL3)
-#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF(DMA_CHANNEL4)
-#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF(DMA_CHANNEL5)
-#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF(DMA_CHANNEL6)
-#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF(DMA_CHANNEL7)
-
-/* CTCIF: Transfer complete clear */
-#define DMA_IFCR_CTCIF_BIT (1 << 1)
-#define DMA_IFCR_CTCIF(channel) (DMA_IFCR_CTCIF_BIT << (4 * ((channel) -1)))
-
-#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF(DMA_CHANNEL1)
-#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF(DMA_CHANNEL2)
-#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF(DMA_CHANNEL3)
-#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF(DMA_CHANNEL4)
-#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF(DMA_CHANNEL5)
-#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF(DMA_CHANNEL6)
-#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF(DMA_CHANNEL7)
-
-/* CGIF: Global interrupt clear */
-#define DMA_IFCR_CGIF_BIT (1 << 0)
-#define DMA_IFCR_CGIF(channel) (DMA_IFCR_CGIF_BIT << (4 * ((channel) -1)))
-
-#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF(DMA_CHANNEL1)
-#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF(DMA_CHANNEL2)
-#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF(DMA_CHANNEL3)
-#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF(DMA_CHANNEL4)
-#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF(DMA_CHANNEL5)
-#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF(DMA_CHANNEL6)
-#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF(DMA_CHANNEL7)
-
-/* Clear interrupts mask */
-#define DMA_IFCR_CIF_BIT 0xF
-#define DMA_IFCR_CIF(channel) (DMA_IFCR_CIF_BIT << (4 * ((channel) - 1)))
-
-#define DMA_IFCR_CIF1 DMA_IFCR_CIF(DMA_CHANNEL1)
-#define DMA_IFCR_CIF2 DMA_IFCR_CIF(DMA_CHANNEL2)
-#define DMA_IFCR_CIF3 DMA_IFCR_CIF(DMA_CHANNEL3)
-#define DMA_IFCR_CIF4 DMA_IFCR_CIF(DMA_CHANNEL4)
-#define DMA_IFCR_CIF5 DMA_IFCR_CIF(DMA_CHANNEL5)
-#define DMA_IFCR_CIF6 DMA_IFCR_CIF(DMA_CHANNEL6)
-#define DMA_IFCR_CIF7 DMA_IFCR_CIF(DMA_CHANNEL7)
-
-/* --- DMA_CCRx generic values --------------------------------------------- */
-
-/* MEM2MEM: Memory to memory mode */
-#define DMA_CCR_MEM2MEM (1 << 14)
-
-/* PL[13:12]: Channel priority level */
-/** @defgroup dma_ch_pri DMA Channel Priority Levels
-@ingroup STM32F1xx_dma_defines
-
-@{*/
-#define DMA_CCR_PL_LOW (0x0 << 12)
-#define DMA_CCR_PL_MEDIUM (0x1 << 12)
-#define DMA_CCR_PL_HIGH (0x2 << 12)
-#define DMA_CCR_PL_VERY_HIGH (0x3 << 12)
-/**@}*/
-#define DMA_CCR_PL_MASK (0x3 << 12)
-#define DMA_CCR_PL_SHIFT 12
-
-/* MSIZE[11:10]: Memory size */
-/** @defgroup dma_ch_memwidth DMA Channel Memory Word Width
-@ingroup STM32F1xx_dma_defines
-
-@{*/
-#define DMA_CCR_MSIZE_8BIT (0x0 << 10)
-#define DMA_CCR_MSIZE_16BIT (0x1 << 10)
-#define DMA_CCR_MSIZE_32BIT (0x2 << 10)
-/**@}*/
-#define DMA_CCR_MSIZE_MASK (0x3 << 10)
-#define DMA_CCR_MSIZE_SHIFT 10
-
-/* PSIZE[9:8]: Peripheral size */
-/** @defgroup dma_ch_perwidth DMA Channel Peripheral Word Width
-@ingroup STM32F1xx_dma_defines
-
-@{*/
-#define DMA_CCR_PSIZE_8BIT (0x0 << 8)
-#define DMA_CCR_PSIZE_16BIT (0x1 << 8)
-#define DMA_CCR_PSIZE_32BIT (0x2 << 8)
-/**@}*/
-#define DMA_CCR_PSIZE_MASK (0x3 << 8)
-#define DMA_CCR_PSIZE_SHIFT 8
-
-/* MINC: Memory increment mode */
-#define DMA_CCR_MINC (1 << 7)
-
-/* PINC: Peripheral increment mode */
-#define DMA_CCR_PINC (1 << 6)
-
-/* CIRC: Circular mode */
-#define DMA_CCR_CIRC (1 << 5)
-
-/* DIR: Data transfer direction */
-#define DMA_CCR_DIR (1 << 4)
-
-/* TEIE: Transfer error interrupt enable */
-#define DMA_CCR_TEIE (1 << 3)
-
-/* HTIE: Half transfer interrupt enable */
-#define DMA_CCR_HTIE (1 << 2)
-
-/* TCIE: Transfer complete interrupt enable */
-#define DMA_CCR_TCIE (1 << 1)
-
-/* EN: Channel enable */
-#define DMA_CCR_EN (1 << 0)
-
-/* --- DMA_CNDTRx values --------------------------------------------------- */
-
-/* NDT[15:0]: Number of data to transfer */
-
-/* --- DMA_CPARx values ---------------------------------------------------- */
-
-/* PA[31:0]: Peripheral address */
-
-/* --- DMA_CMARx values ---------------------------------------------------- */
-
-/* MA[31:0]: Memory address */
-
-/* --- Generic values ------------------------------------------------------ */
-
-/** @defgroup dma_ch DMA Channel Number
-@ingroup STM32F1xx_dma_defines
-
-@{*/
-#define DMA_CHANNEL1 1
-#define DMA_CHANNEL2 2
-#define DMA_CHANNEL3 3
-#define DMA_CHANNEL4 4
-#define DMA_CHANNEL5 5
-#define DMA_CHANNEL6 6
-#define DMA_CHANNEL7 7
-/**@}*/
-
-/* --- function prototypes ------------------------------------------------- */
-
-BEGIN_DECLS
-
-void dma_channel_reset(u32 dma, u8 channel);
-void dma_enable_mem2mem_mode(u32 dma, u8 channel);
-void dma_set_priority(u32 dma, u8 channel, u32 prio);
-void dma_set_memory_size(u32 dma, u8 channel, u32 mem_size);
-void dma_set_peripheral_size(u32 dma, u8 channel, u32 peripheral_size);
-void dma_enable_memory_increment_mode(u32 dma, u8 channel);
-void dma_enable_peripheral_increment_mode(u32 dma, u8 channel);
-void dma_enable_circular_mode(u32 dma, u8 channel);
-void dma_set_read_from_peripheral(u32 dma, u8 channel);
-void dma_set_read_from_memory(u32 dma, u8 channel);
-void dma_enable_transfer_error_interrupt(u32 dma, u8 channel);
-void dma_disable_transfer_error_interrupt(u32 dma, u8 channel);
-void dma_enable_half_transfer_interrupt(u32 dma, u8 channel);
-void dma_disable_half_transfer_interrupt(u32 dma, u8 channel);
-void dma_enable_transfer_complete_interrupt(u32 dma, u8 channel);
-void dma_disable_transfer_complete_interrupt(u32 dma, u8 channel);
-void dma_enable_channel(u32 dma, u8 channel);
-void dma_disable_channel(u32 dma, u8 channel);
-void dma_set_peripheral_address(u32 dma, u8 channel, u32 address);
-void dma_set_memory_address(u32 dma, u8 channel, u32 address);
-void dma_set_number_of_data(u32 dma, u8 channel, u16 number);
-
-END_DECLS
+#include <libopencm3/stm32/common/dma_common_f13.h>
#endif
-/**@}*/
diff --git a/include/libopencm3/stm32/f1/flash.h b/include/libopencm3/stm32/f1/flash.h
index 919b4d4..fef1257 100644
--- a/include/libopencm3/stm32/f1/flash.h
+++ b/include/libopencm3/stm32/f1/flash.h
@@ -44,48 +44,48 @@
/* --- FLASH_ACR values ---------------------------------------------------- */
-#define FLASH_PRFTBS (1 << 5)
-#define FLASH_PRFTBE (1 << 4)
-#define FLASH_HLFCYA (1 << 3)
-#define FLASH_LATENCY_0WS 0x00
-#define FLASH_LATENCY_1WS 0x01
-#define FLASH_LATENCY_2WS 0x02
+#define FLASH_ACR_PRFTBS (1 << 5)
+#define FLASH_ACR_PRFTBE (1 << 4)
+#define FLASH_ACR_HLFCYA (1 << 3)
+#define FLASH_ACR_LATENCY_0WS 0x00
+#define FLASH_ACR_LATENCY_1WS 0x01
+#define FLASH_ACR_LATENCY_2WS 0x02
/* --- FLASH_SR values ----------------------------------------------------- */
-#define FLASH_EOP (1 << 5)
-#define FLASH_WRPRTERR (1 << 4)
-#define FLASH_PGERR (1 << 2)
-#define FLASH_BSY (1 << 0)
+#define FLASH_SR_EOP (1 << 5)
+#define FLASH_SR_WRPRTERR (1 << 4)
+#define FLASH_SR_PGERR (1 << 2)
+#define FLASH_SR_BSY (1 << 0)
/* --- FLASH_CR values ----------------------------------------------------- */
-#define FLASH_EOPIE (1 << 12)
-#define FLASH_ERRIE (1 << 10)
-#define FLASH_OPTWRE (1 << 9)
-#define FLASH_LOCK (1 << 7)
-#define FLASH_STRT (1 << 6)
-#define FLASH_OPTER (1 << 5)
-#define FLASH_OPTPG (1 << 4)
-#define FLASH_MER (1 << 2)
-#define FLASH_PER (1 << 1)
-#define FLASH_PG (1 << 0)
+#define FLASH_CR_EOPIE (1 << 12)
+#define FLASH_CR_ERRIE (1 << 10)
+#define FLASH_CR_OPTWRE (1 << 9)
+#define FLASH_CR_LOCK (1 << 7)
+#define FLASH_CR_STRT (1 << 6)
+#define FLASH_CR_OPTER (1 << 5)
+#define FLASH_CR_OPTPG (1 << 4)
+#define FLASH_CR_MER (1 << 2)
+#define FLASH_CR_PER (1 << 1)
+#define FLASH_CR_PG (1 << 0)
/* --- FLASH_OBR values ---------------------------------------------------- */
/* FLASH_OBR[25:18]: Data1 */
/* FLASH_OBR[17:10]: Data0 */
-#define FLASH_NRST_STDBY (1 << 4)
-#define FLASH_NRST_STOP (1 << 3)
-#define FLASH_WDG_SW (1 << 2)
-#define FLASH_RDPRT (1 << 1)
-#define FLASH_OPTERR (1 << 0)
+#define FLASH_OBR_NRST_STDBY (1 << 4)
+#define FLASH_OBR_NRST_STOP (1 << 3)
+#define FLASH_OBR_WDG_SW (1 << 2)
+#define FLASH_OBR_RDPRT (1 << 1)
+#define FLASH_OBR_OPTERR (1 << 0)
/* --- FLASH Keys -----------------------------------------------------------*/
-#define RDP_KEY ((u16)0x00a5)
-#define FLASH_KEY1 ((u32)0x45670123)
-#define FLASH_KEY2 ((u32)0xcdef89ab)
+#define FLASH_RDP_KEY ((u16)0x00a5)
+#define FLASH_KEYR_KEY1 ((u32)0x45670123)
+#define FLASH_KEYR_KEY2 ((u32)0xcdef89ab)
/* --- Function prototypes ------------------------------------------------- */
diff --git a/include/libopencm3/stm32/f1/gpio.h b/include/libopencm3/stm32/f1/gpio.h
index a1e74cc..580c501 100644
--- a/include/libopencm3/stm32/f1/gpio.h
+++ b/include/libopencm3/stm32/f1/gpio.h
@@ -1,4 +1,4 @@
-/** @defgroup STM32F1xx_gpio_defines GPIO Defines
+/** @defgroup gpio_defines GPIO Defines
@brief <b>Defined Constants and Types for the STM32F1xx General Purpose I/O</b>
@@ -8,6 +8,7 @@
@author @htmlonly &copy; @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
@author @htmlonly &copy; @endhtmlonly 2012 Piotr Esden-Tempski <piotr@esden.net>
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
@date 1 July 2012
@@ -18,6 +19,7 @@ LGPL License Terms @ref lgpl_license
*
* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
* Copyright (C) 2012 Piotr Esden-Tempski <piotr@esden.net>
+ * Copyright (C) 2012 Ken Sarkies <ksarkies@internode.on.net>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
@@ -32,21 +34,23 @@ LGPL License Terms @ref lgpl_license
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
+
/**@{*/
#ifndef LIBOPENCM3_GPIO_H
#define LIBOPENCM3_GPIO_H
#include <libopencm3/stm32/memorymap.h>
-#include <libopencm3/cm3/common.h>
+#include <libopencm3/stm32/common/gpio_common_all.h>
/* --- Convenience macros -------------------------------------------------- */
/* GPIO port base addresses (for convenience) */
/** @defgroup gpio_port_id GPIO Port IDs
-@ingroup STM32F1xx_gpio_defines
+@ingroup gpio_defines
@{*/
+/* GPIO port base addresses (for convenience) */
#define GPIOA GPIO_PORT_A_BASE
#define GPIOB GPIO_PORT_B_BASE
#define GPIOC GPIO_PORT_C_BASE
@@ -56,30 +60,6 @@ LGPL License Terms @ref lgpl_license
#define GPIOG GPIO_PORT_G_BASE
/**@}*/
-/* GPIO number definitions (for convenience) */
-/** @defgroup gpio_pin_id GPIO Pin Identifiers
-@ingroup STM32F1xx_gpio_defines
-
-@{*/
-#define GPIO0 (1 << 0)
-#define GPIO1 (1 << 1)
-#define GPIO2 (1 << 2)
-#define GPIO3 (1 << 3)
-#define GPIO4 (1 << 4)
-#define GPIO5 (1 << 5)
-#define GPIO6 (1 << 6)
-#define GPIO7 (1 << 7)
-#define GPIO8 (1 << 8)
-#define GPIO9 (1 << 9)
-#define GPIO10 (1 << 10)
-#define GPIO11 (1 << 11)
-#define GPIO12 (1 << 12)
-#define GPIO13 (1 << 13)
-#define GPIO14 (1 << 14)
-#define GPIO15 (1 << 15)
-#define GPIO_ALL 0xffff
-/**@}*/
-
/* --- Alternate function GPIOs -------------------------------------------- */
/* Default alternate functions of some pins (with and without remapping) */
@@ -103,18 +83,18 @@ LGPL License Terms @ref lgpl_license
/* CAN1 / CAN BANK */
#define GPIO_BANK_CAN1_RX GPIOA /* PA11 */
#define GPIO_BANK_CAN1_TX GPIOA /* PA12 */
-#define GPIO_BANK_CAN_RX GPIO_CAN1_RX /* Alias */
-#define GPIO_BANK_CAN_TX GPIO_CAN1_TX /* Alias */
+#define GPIO_BANK_CAN_RX GPIO_BANK_CAN1_RX /* Alias */
+#define GPIO_BANK_CAN_TX GPIO_BANK_CAN1_TX /* Alias */
#define GPIO_BANK_CAN_PB_RX GPIOB /* PB8 */
#define GPIO_BANK_CAN_PB_TX GPIOB /* PB9 */
-#define GPIO_BANK_CAN1_PB_RX GPIO_CAN_PB_RX /* Alias */
-#define GPIO_BANK_CAN1_PB_TX GPIO_CAN_PB_TX /* Alias */
+#define GPIO_BANK_CAN1_PB_RX GPIO_BANK_CAN_PB_RX /* Alias */
+#define GPIO_BANK_CAN1_PB_TX GPIO_BANK_CAN_PB_TX /* Alias */
#define GPIO_BANK_CAN_PD_RX GPIOD /* PD0 */
#define GPIO_BANK_CAN_PD_TX GPIOD /* PD1 */
-#define GPIO_BANK_CAN1_PD_RX GPIO_CAN_PD_RX /* Alias */
-#define GPIO_BANK_CAN1_PD_TX GPIO_CAN_PD_TX /* Alias */
+#define GPIO_BANK_CAN1_PD_RX GPIO_BANK_CAN_PD_RX /* Alias */
+#define GPIO_BANK_CAN1_PD_TX GPIO_BANK_CAN_PD_TX /* Alias */
/* CAN2 GPIO */
#define GPIO_CAN2_RX GPIO12 /* PB12 */
@@ -620,7 +600,7 @@ LGPL License Terms @ref lgpl_license
/* --- GPIO_CRL/GPIO_CRH values -------------------------------------------- */
/** @defgroup gpio_cnf GPIO Pin Configuration
-@ingroup STM32F1xx_gpio_defines
+@ingroup gpio_defines
If mode specifies input, configuration can be
@li Analog input
@li Floating input
@@ -652,7 +632,7 @@ If mode specifies output, configuration can be
/* Pin mode (MODE[1:0]) values */
/** @defgroup gpio_mode GPIO Pin Mode
-@ingroup STM32F1xx_gpio_defines
+@ingroup gpio_defines
@li Input (default after reset)
@li Output mode at 10 MHz maximum speed
@li Output mode at 2 MHz maximum speed
@@ -681,11 +661,6 @@ If mode specifies output, configuration can be
/* GPIO_BRR[15:0]: BRy: Port x reset bit y (y = 0..15) */
-/* --- GPIO_LCKR values ---------------------------------------------------- */
-
-#define GPIO_LCKK (1 << 16)
-/* GPIO_LCKR[15:0]: LCKy: Port x lock bit y (y = 0..15) */
-
/* --- AFIO registers ------------------------------------------------------ */
/* Event control register (AFIO_EVCR) */
@@ -716,7 +691,7 @@ If mode specifies output, configuration can be
/* PORT[2:0]: Port selection */
/** @defgroup afio_evcr_port EVENTOUT Port selection
-@ingroup STM32F1xx_gpio_defines
+@ingroup gpio_defines
@{*/
#define AFIO_EVCR_PORT_PA (0x0 << 4)
@@ -728,7 +703,7 @@ If mode specifies output, configuration can be
/* PIN[3:0]: Pin selection */
/** @defgroup afio_evcr_pin EVENTOUT Pin selection
-@ingroup STM32F1xx_gpio_defines
+@ingroup gpio_defines
@{*/
#define AFIO_EVCR_PIN_Px0 (0x0 << 0)
@@ -755,7 +730,7 @@ If mode specifies output, configuration can be
/** @defgroup afio_remap_cld Alternate Function Remap Controls for Connectivity
Line Devices only
-@ingroup STM32F1xx_gpio_defines
+@ingroup gpio_defines
@{*/
/* PTP_PPS_REMAP: *//** Ethernet PTP PPS remapping
@@ -788,7 +763,7 @@ Line Devices only
/* SWJ_CFG[2:0]: Serial wire JTAG configuration */
/** @defgroup afio_swj_disable Serial Wire JTAG disables
-@ingroup STM32F1xx_gpio_defines
+@ingroup gpio_defines
@{*/
#define AFIO_MAPR_SWJ_MASK (0x7 << 24)
@@ -803,7 +778,7 @@ Line Devices only
/**@}*/
/** @defgroup afio_remap Alternate Function Remap Controls
-@ingroup STM32F1xx_gpio_defines
+@ingroup gpio_defines
@{*/
/* ADC2_ETRGREG_REMAP: */ /** ADC2 external trigger regulator conversion remapping
@@ -846,7 +821,7 @@ Line Devices only
/* CAN_REMAP[1:0]: CAN1 alternate function remapping */
/** @defgroup afio_remap_can1 Alternate Function Remap Controls for CAN 1
-@ingroup STM32F1xx_gpio_defines
+@ingroup gpio_defines
@{*/
#define AFIO_MAPR_CAN1_REMAP_PORTA (0x0 << 13)
@@ -856,7 +831,7 @@ Line Devices only
/* TIM3_REMAP[1:0]: TIM3 remapping */
/** @defgroup afio_remap_tim3 Alternate Function Remap Controls for Timer 3
-@ingroup STM32F1xx_gpio_defines
+@ingroup gpio_defines
@{*/
#define AFIO_MAPR_TIM3_REMAP_NO_REMAP (0x0 << 10)
@@ -866,7 +841,7 @@ Line Devices only
/* TIM2_REMAP[1:0]: TIM2 remapping */
/** @defgroup afio_remap_tim2 Alternate Function Remap Controls for Timer 2
-@ingroup STM32F1xx_gpio_defines
+@ingroup gpio_defines
@{*/
#define AFIO_MAPR_TIM2_REMAP_NO_REMAP (0x0 << 8)
@@ -877,7 +852,7 @@ Line Devices only
/* TIM1_REMAP[1:0]: TIM1 remapping */
/** @defgroup afio_remap_tim1 Alternate Function Remap Controls for Timer 1
-@ingroup STM32F1xx_gpio_defines
+@ingroup gpio_defines
@{*/
#define AFIO_MAPR_TIM1_REMAP_NO_REMAP (0x0 << 6)
@@ -887,7 +862,7 @@ Line Devices only
/* USART3_REMAP[1:0]: USART3 remapping */
/** @defgroup afio_remap_usart3 Alternate Function Remap Controls for USART 3
-@ingroup STM32F1xx_gpio_defines
+@ingroup gpio_defines
@{*/
#define AFIO_MAPR_USART3_REMAP_NO_REMAP (0x0 << 4)
@@ -896,7 +871,7 @@ Line Devices only
/**@}*/
/** @defgroup afio_remap2 Alternate Function Remap Controls Secondary Set
-@ingroup STM32F1xx_gpio_defines
+@ingroup gpio_defines
@{*/
/* FSMC_NADV_DISCONNECT: */ /** The NADV is disconnected from its allocated pin */
@@ -925,7 +900,7 @@ Line Devices only
/* --- AFIO_EXTICR4 values ------------------------------------------------- */
/** @defgroup afio_exti Alternate Function EXTI pin number
-@ingroup STM32F1xx_gpio_defines
+@ingroup gpio_defines
@{*/
@@ -953,13 +928,6 @@ Line Devices only
BEGIN_DECLS
void gpio_set_mode(u32 gpioport, u8 mode, u8 cnf, u16 gpios);
-void gpio_set(u32 gpioport, u16 gpios);
-void gpio_clear(u32 gpioport, u16 gpios);
-u16 gpio_get(u32 gpioport, u16 gpios);
-void gpio_toggle(u32 gpioport, u16 gpios);
-u16 gpio_port_read(u32 gpioport);
-void gpio_port_write(u32 gpioport, u16 data);
-void gpio_port_config_lock(u32 gpioport, u16 gpios);
void gpio_set_eventout(u8 evoutport, u8 evoutpin);
void gpio_primary_remap(u8 swjenable, u32 maps);
void gpio_secondary_remap(u32 maps);
diff --git a/include/libopencm3/stm32/f1/i2c.h b/include/libopencm3/stm32/f1/i2c.h
new file mode 100644
index 0000000..44d906a
--- /dev/null
+++ b/include/libopencm3/stm32/f1/i2c.h
@@ -0,0 +1,41 @@
+/** @defgroup i2c_defines I2C Defines
+
+@brief <b>Defined Constants and Types for the STM32F1xx I2C </b>
+
+@ingroup STM32F1xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 12 October 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_I2C_H
+#define LIBOPENCM3_I2C_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/i2c_common_all.h>
+
+#endif
+
diff --git a/include/libopencm3/stm32/f1/irq.yaml b/include/libopencm3/stm32/f1/irq.yaml
new file mode 100644
index 0000000..14cbcc0
--- /dev/null
+++ b/include/libopencm3/stm32/f1/irq.yaml
@@ -0,0 +1,72 @@
+includeguard: LIBOPENCM3_STM32_F1_NVIC_H
+partname_humanreadable: STM32 F1 series
+partname_doxygen: STM32F1
+irqs:
+ - wwdg
+ - pvd
+ - tamper
+ - rtc
+ - flash
+ - rcc
+ - exti0
+ - exti1
+ - exti2
+ - exti3
+ - exti4
+ - dma1_channel1
+ - dma1_channel2
+ - dma1_channel3
+ - dma1_channel4
+ - dma1_channel5
+ - dma1_channel6
+ - dma1_channel7
+ - adc1_2
+ - usb_hp_can_tx
+ - usb_lp_can_rx0
+ - can_rx1
+ - can_sce
+ - exti9_5
+ - tim1_brk
+ - tim1_up
+ - tim1_trg_com
+ - tim1_cc
+ - tim2
+ - tim3
+ - tim4
+ - i2c1_ev
+ - i2c1_er
+ - i2c2_ev
+ - i2c2_er
+ - spi1
+ - spi2
+ - usart1
+ - usart2
+ - usart3
+ - exti15_10
+ - rtc_alarm
+ - usb_wakeup
+ - tim8_brk
+ - tim8_up
+ - tim8_trg_com
+ - tim8_cc
+ - adc3
+ - fsmc
+ - sdio
+ - tim5
+ - spi3
+ - uart4
+ - uart5
+ - tim6
+ - tim7
+ - dma2_channel1
+ - dma2_channel2
+ - dma2_channel3
+ - dma2_channel4_5
+ - dma2_channel5
+ - eth
+ - eth_wkup
+ - can2_tx
+ - can2_rx0
+ - can2_rx1
+ - can2_sce
+ - otg_fs
diff --git a/include/libopencm3/stm32/f1/iwdg.h b/include/libopencm3/stm32/f1/iwdg.h
new file mode 100644
index 0000000..c8a1e85
--- /dev/null
+++ b/include/libopencm3/stm32/f1/iwdg.h
@@ -0,0 +1,41 @@
+/** @defgroup iwdg_defines IWDG Defines
+
+@brief <b>Defined Constants and Types for the STM32F1xx Independent Watchdog Timer</b>
+
+@ingroup STM32F1xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
+
+@date 18 August 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_IWDG_H
+#define LIBOPENCM3_IWDG_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/iwdg_common_all.h>
+
+#endif
+
diff --git a/include/libopencm3/stm32/f1/nvic_f1.h b/include/libopencm3/stm32/f1/nvic_f1.h
deleted file mode 100644
index 5223bb6..0000000
--- a/include/libopencm3/stm32/f1/nvic_f1.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/** @brief <b>Defined Constants and Types for the STM32F1xx Nested Vectored Interrupt Controller</b>
-
-@version 1.0.0
-
-@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
-
-@date 18 August 2012
-
-LGPL License Terms @ref lgpl_license
- */
-/*
- * This file is part of the libopencm3 project.
- *
- * Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef LIBOPENCM3_NVIC_F1_H
-#define LIBOPENCM3_NVIC_F1_H
-
-/* --- IRQ channel numbers-------------------------------------------------- */
-
-/* Note: These F1 specific user interrupt definitions supplement the
- * general NVIC definitions in ../nvic.h
- */
-
-/* User Interrupts */
-/** @defgroup nvic_stm32f1_userint STM32F1xx User Interrupts
-@ingroup STM32F_nvic_defines
-
-@{*/
-#define NVIC_WWDG_IRQ 0
-#define NVIC_PVD_IRQ 1
-#define NVIC_TAMPER_IRQ 2
-#define NVIC_RTC_IRQ 3
-#define NVIC_FLASH_IRQ 4
-#define NVIC_RCC_IRQ 5
-#define NVIC_EXTI0_IRQ 6
-#define NVIC_EXTI1_IRQ 7
-#define NVIC_EXTI2_IRQ 8
-#define NVIC_EXTI3_IRQ 9
-#define NVIC_EXTI4_IRQ 10
-#define NVIC_DMA1_CHANNEL1_IRQ 11
-#define NVIC_DMA1_CHANNEL2_IRQ 12
-#define NVIC_DMA1_CHANNEL3_IRQ 13
-#define NVIC_DMA1_CHANNEL4_IRQ 14
-#define NVIC_DMA1_CHANNEL5_IRQ 15
-#define NVIC_DMA1_CHANNEL6_IRQ 16
-#define NVIC_DMA1_CHANNEL7_IRQ 17
-#define NVIC_ADC1_2_IRQ 18
-#define NVIC_USB_HP_CAN_TX_IRQ 19
-#define NVIC_USB_LP_CAN_RX0_IRQ 20
-#define NVIC_CAN_RX1_IRQ 21
-#define NVIC_CAN_SCE_IRQ 22
-#define NVIC_EXTI9_5_IRQ 23
-#define NVIC_TIM1_BRK_IRQ 24
-#define NVIC_TIM1_UP_IRQ 25
-#define NVIC_TIM1_TRG_COM_IRQ 26
-#define NVIC_TIM1_CC_IRQ 27
-#define NVIC_TIM2_IRQ 28
-#define NVIC_TIM3_IRQ 29
-#define NVIC_TIM4_IRQ 30
-#define NVIC_I2C1_EV_IRQ 31
-#define NVIC_I2C1_ER_IRQ 32
-#define NVIC_I2C2_EV_IRQ 33
-#define NVIC_I2C2_ER_IRQ 34
-#define NVIC_SPI1_IRQ 35
-#define NVIC_SPI2_IRQ 36
-#define NVIC_USART1_IRQ 37
-#define NVIC_USART2_IRQ 38
-#define NVIC_USART3_IRQ 39
-#define NVIC_EXTI15_10_IRQ 40
-#define NVIC_RTC_ALARM_IRQ 41
-#define NVIC_USB_WAKEUP_IRQ 42
-#define NVIC_TIM8_BRK_IRQ 43
-#define NVIC_TIM8_UP_IRQ 44
-#define NVIC_TIM8_TRG_COM_IRQ 45
-#define NVIC_TIM8_CC_IRQ 46
-#define NVIC_ADC3_IRQ 47
-#define NVIC_FSMC_IRQ 48
-#define NVIC_SDIO_IRQ 49
-#define NVIC_TIM5_IRQ 50
-#define NVIC_SPI3_IRQ 51
-#define NVIC_UART4_IRQ 52
-#define NVIC_UART5_IRQ 53
-#define NVIC_TIM6_IRQ 54
-#define NVIC_TIM7_IRQ 55
-#define NVIC_DMA2_CHANNEL1_IRQ 56
-#define NVIC_DMA2_CHANNEL2_IRQ 57
-#define NVIC_DMA2_CHANNEL3_IRQ 58
-#define NVIC_DMA2_CHANNEL4_5_IRQ 59
-#define NVIC_DMA2_CHANNEL5_IRQ 60
-#define NVIC_ETH_IRQ 61
-#define NVIC_ETH_WKUP_IRQ 62
-#define NVIC_CAN2_TX_IRQ 63
-#define NVIC_CAN2_RX0_IRQ 64
-#define NVIC_CAN2_RX1_IRQ 65
-#define NVIC_CAN2_SCE_IRQ 66
-#define NVIC_OTG_FS_IRQ 67
-/**@}*/
-
-#endif
diff --git a/include/libopencm3/stm32/f1/pwr.h b/include/libopencm3/stm32/f1/pwr.h
new file mode 100644
index 0000000..2875492
--- /dev/null
+++ b/include/libopencm3/stm32/f1/pwr.h
@@ -0,0 +1,40 @@
+/** @defgroup pwr_defines PWR Defines
+
+@brief <b>Defined Constants and Types for the STM32F1xx PWR Control</b>
+
+@ingroup STM32F1xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 5 December 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_PWR_H
+#define LIBOPENCM3_PWR_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/pwr_common_all.h>
+
+#endif
+
diff --git a/include/libopencm3/stm32/f1/rcc.h b/include/libopencm3/stm32/f1/rcc.h
index 855e43b..868ad9c 100644
--- a/include/libopencm3/stm32/f1/rcc.h
+++ b/include/libopencm3/stm32/f1/rcc.h
@@ -86,7 +86,7 @@ LGPL License Terms @ref lgpl_license
#define RCC_CFGR_MCO_SYSCLK 0x4
#define RCC_CFGR_MCO_HSICLK 0x5
#define RCC_CFGR_MCO_HSECLK 0x6
-#define RCC_CFGR_RMCO_PLLCLK_DIV2 0x7
+#define RCC_CFGR_MCO_PLLCLK_DIV2 0x7
#define RCC_CFGR_MCO_PLL2CLK 0x8 /* (**) */
#define RCC_CFGR_MCO_PLL3CLK_DIV2 0x9 /* (**) */
#define RCC_CFGR_MCO_XT1 0xa /* (**) */
@@ -448,6 +448,24 @@ LGPL License Terms @ref lgpl_license
#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL16 0xe
#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL20 0xf
+/* PREDIV: PREDIV division factor */
+#define RCC_CFGR2_PREDIV_NODIV 0x0
+#define RCC_CFGR2_PREDIV_DIV2 0x1
+#define RCC_CFGR2_PREDIV_DIV3 0x2
+#define RCC_CFGR2_PREDIV_DIV4 0x3
+#define RCC_CFGR2_PREDIV_DIV5 0x4
+#define RCC_CFGR2_PREDIV_DIV6 0x5
+#define RCC_CFGR2_PREDIV_DIV7 0x6
+#define RCC_CFGR2_PREDIV_DIV8 0x7
+#define RCC_CFGR2_PREDIV_DIV9 0x8
+#define RCC_CFGR2_PREDIV_DIV10 0x9
+#define RCC_CFGR2_PREDIV_DIV11 0xa
+#define RCC_CFGR2_PREDIV_DIV12 0xb
+#define RCC_CFGR2_PREDIV_DIV13 0xc
+#define RCC_CFGR2_PREDIV_DIV14 0xd
+#define RCC_CFGR2_PREDIV_DIV15 0xe
+#define RCC_CFGR2_PREDIV_DIV16 0xf
+
/* PREDIV2: PREDIV2 division factor */
#define RCC_CFGR2_PREDIV2_NODIV 0x0
#define RCC_CFGR2_PREDIV2_DIV2 0x1
@@ -473,7 +491,7 @@ extern u32 rcc_ppre2_frequency;
/* --- Function prototypes ------------------------------------------------- */
typedef enum {
- PLL, HSE, HSI, LSE, LSI
+ PLL, PLL2, PLL3, HSE, HSI, LSE, LSI
} osc_t;
BEGIN_DECLS
@@ -489,6 +507,7 @@ void rcc_osc_on(osc_t osc);
void rcc_osc_off(osc_t osc);
void rcc_css_enable(void);
void rcc_css_disable(void);
+void rcc_set_mco(u32 mcosrc);
void rcc_osc_bypass_enable(osc_t osc);
void rcc_osc_bypass_disable(osc_t osc);
void rcc_peripheral_enable_clock(volatile u32 *reg, u32 en);
@@ -497,6 +516,7 @@ void rcc_peripheral_reset(volatile u32 *reg, u32 reset);
void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset);
void rcc_set_sysclk_source(u32 clk);
void rcc_set_pll_multiplication_factor(u32 mul);
+void rcc_set_pll2_multiplication_factor(u32 mul);
void rcc_set_pll_source(u32 pllsrc);
void rcc_set_pllxtpre(u32 pllxtpre);
void rcc_set_adcpre(u32 adcpre);
@@ -512,6 +532,7 @@ void rcc_clock_setup_in_hse_8mhz_out_24mhz(void);
void rcc_clock_setup_in_hse_8mhz_out_72mhz(void);
void rcc_clock_setup_in_hse_12mhz_out_72mhz(void);
void rcc_clock_setup_in_hse_16mhz_out_72mhz(void);
+void rcc_clock_setup_in_hse_25mhz_out_72mhz(void);
void rcc_backupdomain_reset(void);
END_DECLS
diff --git a/include/libopencm3/stm32/f1/rtc.h b/include/libopencm3/stm32/f1/rtc.h
index 04aea01..a8a8966 100644
--- a/include/libopencm3/stm32/f1/rtc.h
+++ b/include/libopencm3/stm32/f1/rtc.h
@@ -17,6 +17,11 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
+/*
+ * The F1 RTC is a straight timestamp, a completely different peripheral to
+ * that found in the F2, F3, F4, L1 and F0.
+ */
+
#ifndef LIBOPENCM3_RTC_H
#define LIBOPENCM3_RTC_H
diff --git a/include/libopencm3/stm32/f1/scb.h b/include/libopencm3/stm32/f1/scb.h
deleted file mode 100644
index 181aa7a..0000000
--- a/include/libopencm3/stm32/f1/scb.h
+++ /dev/null
@@ -1,307 +0,0 @@
-/*
- * This file is part of the libopencm3 project.
- *
- * Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
- * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef LIBOPENCM3_SCB_H
-#define LIBOPENCM3_SCB_H
-
-#include <libopencm3/stm32/memorymap.h>
-#include <libopencm3/cm3/common.h>
-
-/* --- SCB: Registers ------------------------------------------------------ */
-
-/* CPUID: CPUID base register */
-#define SCB_CPUID MMIO32(SCB_BASE + 0x00)
-
-/* ICSR: Interrupt Control State Register */
-#define SCB_ICSR MMIO32(SCB_BASE + 0x04)
-
-/* VTOR: Vector Table Offset Register */
-#define SCB_VTOR MMIO32(SCB_BASE + 0x08)
-
-/* AIRCR: Application Interrupt and Reset Control Register */
-#define SCB_AIRCR MMIO32(SCB_BASE + 0x0C)
-
-/* SCR: System Control Register */
-#define SCB_SCR MMIO32(SCB_BASE + 0x10)
-
-/* CCR: Configuration Control Register */
-#define SCB_CCR MMIO32(SCB_BASE + 0x14)
-
-/* SHP: System Handler Priority Registers */
-/* Note: 12 8bit registers */
-#define SCB_SHPR(shpr_id) MMIO8(SCB_BASE + 0x18 + shpr_id)
-#define SCB_SHPR1 MMIO8(SCB_BASE + 0x18 + 1)
-#define SCB_SHPR2 MMIO8(SCB_BASE + 0x18 + 2)
-#define SCB_SHPR3 MMIO8(SCB_BASE + 0x18 + 3)
-
-/* SHCSR: System Handler Control and State Register */
-#define SCB_SHCSR MMIO32(SCB_BASE + 0x24)
-
-/* CFSR: Configurable Fault Status Registers */
-#define SCB_CFSR MMIO32(SCB_BASE + 0x28)
-
-/* HFSR: Hard Fault Status Register */
-#define SCB_HFSR MMIO32(SCB_BASE + 0x2C)
-
-/* DFSR: Debug Fault Status Register */
-#define SCB_DFSR MMIO32(SCB_BASE + 0x30)
-
-/* MMFAR: Memory Manage Fault Address Register */
-#define SCB_MMFAR MMIO32(SCB_BASE + 0x34)
-
-/* BFAR: Bus Fault Address Register */
-#define SCB_BFAR MMIO32(SCB_BASE + 0x38)
-
-/* AFSR: Auxiliary Fault Status Register */
-#define SCB_AFSR MMIO32(SCB_BASE + 0x3C)
-
-/* --- SCB values ---------------------------------------------------------- */
-
-/* --- SCB_CPUID values ---------------------------------------------------- */
-
-/* Implementer[31:24]: Implementer code */
-#define SCP_CPUID_IMPLEMENTER_LSB 24
-/* Variant[23:20]: Variant number */
-#define SCP_CPUID_VARIANT_LSB 20
-/* Constant[19:16]: Reads as 0xF */
-#define SCP_CPUID_CONSTANT_LSB 16
-/* PartNo[15:4]: Part number of the processor */
-#define SCP_CPUID_PARTNO_LSB 4
-/* Revision[3:0]: Revision number */
-#define SCP_CPUID_REVISION_LSB 0
-
-/* --- SCB_ICSR values ----------------------------------------------------- */
-
-/* NMIPENDSET: NMI set-pending bit */
-#define SCB_ICSR_NMIPENDSET (1 << 31)
-/* Bits [30:29]: reserved - must be kept cleared */
-/* PENDSVSET: PendSV set-pending bit */
-#define SCB_ICSR_PENDSVSET (1 << 28)
-/* PENDSVCLR: PendSV clear-pending bit */
-#define SCB_ICSR_PENDSVCLR (1 << 27)
-/* PENDSTSET: SysTick exception set-pending bit */
-#define SCB_ICSR_PENDSTSET (1 << 26)
-/* PENDSTCLR: SysTick exception clear-pending bit */
-#define SCB_ICSR_PENDSTCLR (1 << 25)
-/* Bit 24: reserved - must be kept cleared */
-/* Bit 23: reserved for debug - reads as 0 when not in debug mode */
-/* ISRPENDING: Interrupt pending flag, excluding NMI and Faults */
-#define SCB_ICSR_ISRPENDING (1 << 22)
-/* VECTPENDING[21:12] Pending vector */
-#define SCB_ICSR_VECTPENDING_LSB 12
-/* RETOBASE: Return to base level */
-#define SCB_ICSR_RETOBASE (1 << 11)
-/* Bits [10:9]: reserved - must be kept cleared */
-/* VECTACTIVE[8:0] Active vector */
-#define SCB_ICSR_VECTACTIVE_LSB 0
-
-/* --- SCB_VTOR values ----------------------------------------------------- */
-
-/* Bits [31:30]: reserved - must be kept cleared */
-/* TBLOFF[29:9]: Vector table base offset field */
-#define SCB_VTOR_TBLOFF_LSB 9 /* inconsistent datasheet - LSB could be 11 */
-
-/* --- SCB_AIRCR values ---------------------------------------------------- */
-
-/* VECTKEYSTAT[31:16]/ VECTKEY[31:16] Register key */
-#define SCB_AIRCR_VECTKEYSTAT_LSB 16
-#define SCB_AIRCR_VECTKEY 0x05FA0000
-/* ENDIANESS Data endianness bit */
-#define SCB_AIRCR_ENDIANESS (1 << 15)
-/* Bits [14:11]: reserved - must be kept cleared */
-/* PRIGROUP[10:8]: Interrupt priority grouping field */
-#define SCB_AIRCR_PRIGROUP_GROUP16_NOSUB (0x3 << 8)
-#define SCB_AIRCR_PRIGROUP_GROUP8_SUB2 (0x4 << 8)
-#define SCB_AIRCR_PRIGROUP_GROUP4_SUB4 (0x5 << 8)
-#define SCB_AIRCR_PRIGROUP_GROUP2_SUB8 (0x6 << 8)
-#define SCB_AIRCR_PRIGROUP_NOGROUP_SUB16 (0x7 << 8)
-#define SCB_AIRCR_PRIGROUP_MASK (0x7 << 8)
-#define SCB_AIRCR_PRIGROUP_SHIFT 8
-/* Bits [7:3]: reserved - must be kept cleared */
-/* SYSRESETREQ System reset request */
-#define SCB_AIRCR_SYSRESETREQ (1 << 2)
-/* VECTCLRACTIVE */
-#define SCB_AIRCR_VECTCLRACTIVE (1 << 1)
-/* VECTRESET */
-#define SCB_AIRCR_VECTRESET (1 << 0)
-
-/* --- SCB_SCR values ------------------------------------------------------ */
-
-/* Bits [31:5]: reserved - must be kept cleared */
-/* SEVEONPEND Send Event on Pending bit */
-#define SCB_SCR_SEVEONPEND (1 << 4)
-/* Bit 3: reserved - must be kept cleared */
-/* SLEEPDEEP */
-#define SCB_SCR_SLEEPDEEP (1 << 2)
-/* SLEEPONEXIT */
-#define SCB_SCR_SLEEPONEXIT (1 << 1)
-/* Bit 0: reserved - must be kept cleared */
-
-/* --- SCB_CCR values ------------------------------------------------------ */
-
-/* Bits [31:10]: reserved - must be kept cleared */
-/* STKALIGN */
-#define SCB_CCR_STKALIGN (1 << 9)
-/* BFHFNMIGN */
-#define SCB_CCR_BFHFNMIGN (1 << 8)
-/* Bits [7:5]: reserved - must be kept cleared */
-/* DIV_0_TRP */
-#define SCB_CCR_DIV_0_TRP (1 << 4)
-/* UNALIGN_TRP */
-#define SCB_CCR_UNALIGN_TRP (1 << 3)
-/* Bit 2: reserved - must be kept cleared */
-/* USERSETMPEND */
-#define SCB_CCR_USERSETMPEND (1 << 1)
-/* NONBASETHRDENA */
-#define SCB_CCR_NONBASETHRDENA (1 << 0)
-
-/* --- SCB_SHPR1 values ---------------------------------------------------- */
-
-/* Bits [31:24]: reserved - must be kept cleared */
-/* PRI_6[23:16]: Priority of system handler 6, usage fault */
-#define SCB_SHPR1_PRI_6_LSB 16
-/* PRI_5[15:8]: Priority of system handler 5, bus fault */
-#define SCB_SHPR1_PRI_5_LSB 8
-/* PRI_4[7:0]: Priority of system handler 4, memory management fault */
-#define SCB_SHPR1_PRI_4_LSB 0
-
-/* --- SCB_SHPR2 values ---------------------------------------------------- */
-
-/* PRI_11[31:24]: Priority of system handler 11, SVCall */
-#define SCB_SHPR2_PRI_11_LSB 24
-/* Bits [23:0]: reserved - must be kept cleared */
-
-/* --- SCB_SHPR3 values ---------------------------------------------------- */
-
-/* PRI_15[31:24]: Priority of system handler 15, SysTick exception */
-#define SCB_SHPR3_PRI_15_LSB 24
-/* PRI_14[23:16]: Priority of system handler 14, PendSV */
-#define SCB_SHPR3_PRI_14_LSB 16
-/* Bits [15:0]: reserved - must be kept cleared */
-
-/* --- SCB_SHCSR values ---------------------------------------------------- */
-
-/* Bits [31:19]: reserved - must be kept cleared */
-/* USGFAULTENA: Usage fault enable */
-#define SCB_SHCSR_USGFAULTENA (1 << 18)
-/* BUSFAULTENA: Bus fault enable */
-#define SCB_SHCSR_BUSFAULTENA (1 << 17)
-/* MEMFAULTENA: Memory management fault enable */
-#define SCB_SHCSR_MEMFAULTENA (1 << 16)
-/* SVCALLPENDED: SVC call pending */
-#define SCB_SHCSR_SVCALLPENDED (1 << 15)
-/* BUSFAULTPENDED: Bus fault exception pending */
-#define SCB_SHCSR_BUSFAULTPENDED (1 << 14)
-/* MEMFAULTPENDED: Memory management fault exception pending */
-#define SCB_SHCSR_MEMFAULTPENDED (1 << 13)
-/* USGFAULTPENDED: Usage fault exception pending */
-#define SCB_SHCSR_USGFAULTPENDED (1 << 12)
-/* SYSTICKACT: SysTick exception active */
-#define SCB_SHCSR_SYSTICKACT (1 << 11)
-/* PENDSVACT: PendSV exception active */
-#define SCB_SHCSR_PENDSVACT (1 << 10)
-/* Bit 9: reserved - must be kept cleared */
-/* MONITORACT: Debug monitor active */
-#define SCB_SHCSR_MONITORACT (1 << 8)
-/* SVCALLACT: SVC call active */
-#define SCB_SHCSR_SVCALLACT (1 << 7)
-/* Bits [6:4]: reserved - must be kept cleared */
-/* USGFAULTACT: Usage fault exception active */
-#define SCB_SHCSR_USGFAULTACT (1 << 3)
-/* Bit 2: reserved - must be kept cleared */
-/* BUSFAULTACT: Bus fault exception active */
-#define SCB_SHCSR_BUSFAULTACT (1 << 1)
-/* MEMFAULTACT: Memory management fault exception active */
-#define SCB_SHCSR_MEMFAULTACT (1 << 0)
-
-/* --- SCB_CFSR values ----------------------------------------------------- */
-
-/* Bits [31:26]: reserved - must be kept cleared */
-/* DIVBYZERO: Divide by zero usage fault */
-#define SCB_CFSR_DIVBYZERO (1 << 25)
-/* UNALIGNED: Unaligned access usage fault */
-#define SCB_CFSR_UNALIGNED (1 << 24)
-/* Bits [23:20]: reserved - must be kept cleared */
-/* NOCP: No coprocessor usage fault */
-#define SCB_CFSR_NOCP (1 << 19)
-/* INVPC: Invalid PC load usage fault */
-#define SCB_CFSR_INVPC (1 << 18)
-/* INVSTATE: Invalid state usage fault */
-#define SCB_CFSR_INVSTATE (1 << 17)
-/* UNDEFINSTR: Undefined instruction usage fault */
-#define SCB_CFSR_UNDEFINSTR (1 << 16)
-/* BFARVALID: Bus Fault Address Register (BFAR) valid flag */
-#define SCB_CFSR_BFARVALID (1 << 15)
-/* Bits [14:13]: reserved - must be kept cleared */
-/* STKERR: Bus fault on stacking for exception entry */
-#define SCB_CFSR_STKERR (1 << 12)
-/* UNSTKERR: Bus fault on unstacking for a return from exception */
-#define SCB_CFSR_UNSTKERR (1 << 11)
-/* IMPRECISERR: Imprecise data bus error */
-#define SCB_CFSR_IMPRECISERR (1 << 10)
-/* PRECISERR: Precise data bus error */
-#define SCB_CFSR_PRECISERR (1 << 9)
-/* IBUSERR: Instruction bus error */
-#define SCB_CFSR_IBUSERR (1 << 8)
-/* MMARVALID: Memory Management Fault Address Register (MMAR) valid flag */
-#define SCB_CFSR_MMARVALID (1 << 7)
-/* Bits [6:5]: reserved - must be kept cleared */
-/* MSTKERR: Memory manager fault on stacking for exception entry */
-#define SCB_CFSR_MSTKERR (1 << 4)
-/* MUNSTKERR: Memory manager fault on unstacking for a return from exception */
-#define SCB_CFSR_MUNSTKERR (1 << 3)
-/* Bit 2: reserved - must be kept cleared */
-/* DACCVIOL: Data access violation flag */
-#define SCB_CFSR_DACCVIOL (1 << 1)
-/* IACCVIOL: Instruction access violation flag */
-#define SCB_CFSR_IACCVIOL (1 << 0)
-
-/* --- SCB_HFSR values ----------------------------------------------------- */
-
-/* DEBUG_VT: reserved for debug use */
-#define SCB_HFSR_DEBUG_VT (1 << 31)
-/* FORCED: Forced hard fault */
-#define SCB_HFSR_FORCED (1 << 30)
-/* Bits [29:2]: reserved - must be kept cleared */
-/* VECTTBL: Vector table hard fault */
-#define SCB_HFSR_VECTTBL (1 << 1)
-/* Bit 0: reserved - must be kept cleared */
-
-/* --- SCB_MMFAR values ---------------------------------------------------- */
-
-/* MMFAR [31:0]: Memory management fault address */
-
-/* --- SCB_BFAR values ----------------------------------------------------- */
-
-/* BFAR [31:0]: Bus fault address */
-
-/* --- SCB functions ------------------------------------------------------- */
-
-BEGIN_DECLS
-
-void scb_reset_core(void);
-void scb_reset_system(void);
-void scb_set_priority_grouping(u32 prigroup);
-
-/* TODO: */
-
-END_DECLS
-
-#endif
diff --git a/include/libopencm3/stm32/f1/spi.h b/include/libopencm3/stm32/f1/spi.h
new file mode 100644
index 0000000..eb434a1
--- /dev/null
+++ b/include/libopencm3/stm32/f1/spi.h
@@ -0,0 +1,40 @@
+/** @defgroup spi_defines SPI Defines
+
+@brief <b>Defined Constants and Types for the STM32F1xx SPI</b>
+
+@ingroup STM32F1xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 5 December 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_SPI_H
+#define LIBOPENCM3_SPI_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/spi_common_all.h>
+
+#endif
+
diff --git a/include/libopencm3/stm32/f1/usart.h b/include/libopencm3/stm32/f1/usart.h
new file mode 100644
index 0000000..24a8137
--- /dev/null
+++ b/include/libopencm3/stm32/f1/usart.h
@@ -0,0 +1,40 @@
+/** @defgroup usart_defines USART Defines
+
+@brief <b>Defined Constants and Types for the STM32F1xx USART</b>
+
+@ingroup STM32F1xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 5 December 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_USART_H
+#define LIBOPENCM3_USART_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/usart_common_all.h>
+
+#endif
+
diff --git a/include/libopencm3/stm32/f2/crc.h b/include/libopencm3/stm32/f2/crc.h
new file mode 100644
index 0000000..bf2d9fe
--- /dev/null
+++ b/include/libopencm3/stm32/f2/crc.h
@@ -0,0 +1,40 @@
+/** @defgroup crc_defines CRC Defines
+
+@brief <b>libopencm3 Defined Constants and Types for the STM32F2xx CRC Generator </b>
+
+@ingroup STM32F2xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
+
+@date 18 August 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_CRC_H
+#define LIBOPENCM3_CRC_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/crc_common_all.h>
+
+#endif
diff --git a/include/libopencm3/stm32/f2/dac.h b/include/libopencm3/stm32/f2/dac.h
new file mode 100644
index 0000000..f6e16e7
--- /dev/null
+++ b/include/libopencm3/stm32/f2/dac.h
@@ -0,0 +1,40 @@
+/** @defgroup dac_defines DAC Defines
+
+@brief <b>Defined Constants and Types for the STM32F2xx DAC</b>
+
+@ingroup STM32F2xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 5 December 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_DAC_H
+#define LIBOPENCM3_DAC_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/dac_common_all.h>
+
+#endif
+
diff --git a/include/libopencm3/stm32/f2/dma.h b/include/libopencm3/stm32/f2/dma.h
index 545df6f..0eb952c 100644
--- a/include/libopencm3/stm32/f2/dma.h
+++ b/include/libopencm3/stm32/f2/dma.h
@@ -1,8 +1,22 @@
+/** @defgroup STM32F2xx_dma_defines DMA Defines
+
+@ingroup STM32F2xx_defines
+
+@brief Defined Constants and Types for the STM32F2xx DMA Controller
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2011 Fergus Noble <fergusnoble@gmail.com>
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 18 October 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
/*
* This file is part of the libopencm3 project.
*
- * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
- *
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
@@ -21,391 +35,7 @@
#define LIBOPENCM3_DMA_H
#include <libopencm3/stm32/memorymap.h>
-#include <libopencm3/cm3/common.h>
-
-/* --- Convenience macros -------------------------------------------------- */
-
-/* DMA controller base addresses (for convenience) */
-#define DMA1 DMA1_BASE
-#define DMA2 DMA2_BASE
-
-/* DMA stream base addresses (for convenience) */
-#define DMA_STREAM(port, n) ((port) + 0x10 + (24 * (n)))
-#define DMA1_STREAM(n) DMA_STREAM(DMA1, n)
-#define DMA2_STREAM(n) DMA_STREAM(DMA2, n)
-
-#define DMA1_STREAM0 DMA1_STREAM(0)
-#define DMA1_STREAM1 DMA1_STREAM(1)
-#define DMA1_STREAM2 DMA1_STREAM(2)
-#define DMA1_STREAM3 DMA1_STREAM(3)
-#define DMA1_STREAM4 DMA1_STREAM(4)
-#define DMA1_STREAM5 DMA1_STREAM(5)
-#define DMA1_STREAM6 DMA1_STREAM(6)
-#define DMA1_STREAM7 DMA1_STREAM(7)
-
-#define DMA2_STREAM0 DMA2_STREAM(0)
-#define DMA2_STREAM1 DMA2_STREAM(1)
-#define DMA2_STREAM2 DMA2_STREAM(2)
-#define DMA2_STREAM3 DMA2_STREAM(3)
-#define DMA2_STREAM4 DMA2_STREAM(4)
-#define DMA2_STREAM5 DMA2_STREAM(5)
-#define DMA2_STREAM6 DMA2_STREAM(6)
-#define DMA2_STREAM7 DMA2_STREAM(7)
-
-/* --- DMA controller registers -------------------------------------------- */
-
-/* DMA low interrupt status register (DMAx_LISR) */
-#define DMA_LISR(port) MMIO32(port + 0x00)
-#define DMA1_LISR DMA_LISR(DMA1)
-#define DMA2_LISR DMA_LISR(DMA2)
-
-/* DMA high interrupt status register (DMAx_HISR) */
-#define DMA_HISR(port) MMIO32(port + 0x04)
-#define DMA1_HISR DMA_HISR(DMA1)
-#define DMA2_HISR DMA_HISR(DMA2)
-
-/* DMA low interrupt flag clear register (DMAx_LIFCR) */
-#define DMA_LIFCR(port) MMIO32(port + 0x08)
-#define DMA1_LIFCR DMA_LIFCR(DMA1)
-#define DMA2_LIFCR DMA_LIFCR(DMA2)
-
-/* DMA high interrupt flag clear register (DMAx_HIFCR) */
-#define DMA_HIFCR(port) MMIO32(port + 0x0C)
-#define DMA1_HIFCR DMA_HIFCR(DMA1)
-#define DMA2_HIFCR DMA_HIFCR(DMA2)
-
-/* --- DMA stream registers ------------------------------------------------ */
-
-/* DMA Stream x configuration register (DMA_SxCR) */
-#define DMA_SCR(port, n) MMIO32(DMA_STREAM(port, n) + 0x00)
-#define DMA1_SCR(n) DMA_SCR(DMA1, n)
-#define DMA2_SCR(n) DMA_SCR(DMA2, n)
-
-#define DMA1_S0CR DMA1_SCR(0)
-#define DMA1_S1CR DMA1_SCR(1)
-#define DMA1_S2CR DMA1_SCR(2)
-#define DMA1_S3CR DMA1_SCR(3)
-#define DMA1_S4CR DMA1_SCR(4)
-#define DMA1_S5CR DMA1_SCR(5)
-#define DMA1_S6CR DMA1_SCR(6)
-#define DMA1_S7CR DMA1_SCR(7)
-
-#define DMA2_S0CR DMA2_SCR(0)
-#define DMA2_S1CR DMA2_SCR(1)
-#define DMA2_S2CR DMA2_SCR(2)
-#define DMA2_S3CR DMA2_SCR(3)
-#define DMA2_S4CR DMA2_SCR(4)
-#define DMA2_S5CR DMA2_SCR(5)
-#define DMA2_S6CR DMA2_SCR(6)
-#define DMA2_S7CR DMA2_SCR(7)
-
-/* DMA Stream x number of data register (DMA_SxNDTR) */
-#define DMA_SNDTR(port, n) MMIO32(DMA_STREAM(port, n) + 0x04)
-#define DMA1_SNDTR(n) DMA_SNDTR(DMA1, n)
-#define DMA2_SNDTR(n) DMA_SNDTR(DMA2, n)
-
-#define DMA1_S0NDTR DMA1_SNDTR(0)
-#define DMA1_S1NDTR DMA1_SNDTR(1)
-#define DMA1_S2NDTR DMA1_SNDTR(2)
-#define DMA1_S3NDTR DMA1_SNDTR(3)
-#define DMA1_S4NDTR DMA1_SNDTR(4)
-#define DMA1_S5NDTR DMA1_SNDTR(5)
-#define DMA1_S6NDTR DMA1_SNDTR(6)
-#define DMA1_S7NDTR DMA1_SNDTR(7)
-
-#define DMA2_S0NDTR DMA2_SNDTR(0)
-#define DMA2_S1NDTR DMA2_SNDTR(1)
-#define DMA2_S2NDTR DMA2_SNDTR(2)
-#define DMA2_S3NDTR DMA2_SNDTR(3)
-#define DMA2_S4NDTR DMA2_SNDTR(4)
-#define DMA2_S5NDTR DMA2_SNDTR(5)
-#define DMA2_S6NDTR DMA2_SNDTR(6)
-#define DMA2_S7NDTR DMA2_SNDTR(7)
-
-/* DMA Stream x peripheral address register (DMA_SxPAR) */
-#define DMA_SPAR(port, n) *(volatile void **)(DMA_STREAM(port, n) + 0x08)
-#define DMA1_SPAR(n) DMA_SPAR(DMA1, n)
-#define DMA2_SPAR(n) DMA_SPAR(DMA2, n)
-
-#define DMA1_S0PAR DMA1_SPAR(0)
-#define DMA1_S1PAR DMA1_SPAR(1)
-#define DMA1_S2PAR DMA1_SPAR(2)
-#define DMA1_S3PAR DMA1_SPAR(3)
-#define DMA1_S4PAR DMA1_SPAR(4)
-#define DMA1_S5PAR DMA1_SPAR(5)
-#define DMA1_S6PAR DMA1_SPAR(6)
-#define DMA1_S7PAR DMA1_SPAR(7)
-
-#define DMA2_S0PAR DMA2_SPAR(0)
-#define DMA2_S1PAR DMA2_SPAR(1)
-#define DMA2_S2PAR DMA2_SPAR(2)
-#define DMA2_S3PAR DMA2_SPAR(3)
-#define DMA2_S4PAR DMA2_SPAR(4)
-#define DMA2_S5PAR DMA2_SPAR(5)
-#define DMA2_S6PAR DMA2_SPAR(6)
-#define DMA2_S7PAR DMA2_SPAR(7)
-
-/* DMA Stream x memory address 0 register (DMA_SxM0AR) */
-#define DMA_SM0AR(port, n) *(volatile void **)(DMA_STREAM(port, n) + 0x0c)
-#define DMA1_SM0AR(n) DMA_SM0AR(DMA1, n)
-#define DMA2_SM0AR(n) DMA_SM0AR(DMA2, n)
-
-#define DMA1_S0M0AR DMA1_SM0AR(0)
-#define DMA1_S1M0AR DMA1_SM0AR(1)
-#define DMA1_S2M0AR DMA1_SM0AR(2)
-#define DMA1_S3M0AR DMA1_SM0AR(3)
-#define DMA1_S4M0AR DMA1_SM0AR(4)
-#define DMA1_S5M0AR DMA1_SM0AR(5)
-#define DMA1_S6M0AR DMA1_SM0AR(6)
-#define DMA1_S7M0AR DMA1_SM0AR(7)
-
-#define DMA2_S0M0AR DMA2_SM0AR(0)
-#define DMA2_S1M0AR DMA2_SM0AR(1)
-#define DMA2_S2M0AR DMA2_SM0AR(2)
-#define DMA2_S3M0AR DMA2_SM0AR(3)
-#define DMA2_S4M0AR DMA2_SM0AR(4)
-#define DMA2_S5M0AR DMA2_SM0AR(5)
-#define DMA2_S6M0AR DMA2_SM0AR(6)
-#define DMA2_S7M0AR DMA2_SM0AR(7)
-
-/* DMA Stream x memory address 1 register (DMA_SxM1AR) */
-#define DMA_SM1AR(port, n) *(volatile void **)(DMA_STREAM(port, n) + 0x10)
-#define DMA1_SM1AR(n) DMA_SM1AR(DMA1, n)
-#define DMA2_SM1AR(n) DMA_SM1AR(DMA2, n)
-
-#define DMA1_S0M1AR DMA1_SM1AR(0)
-#define DMA1_S1M1AR DMA1_SM1AR(1)
-#define DMA1_S2M1AR DMA1_SM1AR(2)
-#define DMA1_S3M1AR DMA1_SM1AR(3)
-#define DMA1_S4M1AR DMA1_SM1AR(4)
-#define DMA1_S5M1AR DMA1_SM1AR(5)
-#define DMA1_S6M1AR DMA1_SM1AR(6)
-#define DMA1_S7M1AR DMA1_SM1AR(7)
-
-#define DMA2_S0M1AR DMA2_SM1AR(0)
-#define DMA2_S1M1AR DMA2_SM1AR(1)
-#define DMA2_S2M1AR DMA2_SM1AR(2)
-#define DMA2_S3M1AR DMA2_SM1AR(3)
-#define DMA2_S4M1AR DMA2_SM1AR(4)
-#define DMA2_S5M1AR DMA2_SM1AR(5)
-#define DMA2_S6M1AR DMA2_SM1AR(6)
-#define DMA2_S7M1AR DMA2_SM1AR(7)
-
-/* DMA Stream x FIFO control register (DMA_SxFCR) */
-#define DMA_SFCR(port, n) MMIO32(DMA_STREAM(port, n) + 0x10)
-#define DMA1_SFCR(n) DMA_SFCR(DMA1, n)
-#define DMA2_SFCR(n) DMA_SFCR(DMA2, n)
-
-#define DMA1_S0FCR DMA1_SFCR(0)
-#define DMA1_S1FCR DMA1_SFCR(1)
-#define DMA1_S2FCR DMA1_SFCR(2)
-#define DMA1_S3FCR DMA1_SFCR(3)
-#define DMA1_S4FCR DMA1_SFCR(4)
-#define DMA1_S5FCR DMA1_SFCR(5)
-#define DMA1_S6FCR DMA1_SFCR(6)
-#define DMA1_S7FCR DMA1_SFCR(7)
-
-#define DMA2_S0FCR DMA2_SFCR(0)
-#define DMA2_S1FCR DMA2_SFCR(1)
-#define DMA2_S2FCR DMA2_SFCR(2)
-#define DMA2_S3FCR DMA2_SFCR(3)
-#define DMA2_S4FCR DMA2_SFCR(4)
-#define DMA2_S5FCR DMA2_SFCR(5)
-#define DMA2_S6FCR DMA2_SFCR(6)
-#define DMA2_S7FCR DMA2_SFCR(7)
-
-/* --- DMA_LISR values ----------------------------------------------------- */
-
-#define DMA_LISR_FEIF0 (1 << 0)
-#define DMA_LISR_DMEIF0 (1 << 2)
-#define DMA_LISR_TEIF0 (1 << 3)
-#define DMA_LISR_HTIF0 (1 << 4)
-#define DMA_LISR_TCIF0 (1 << 5)
-
-#define DMA_LISR_FEIF1 (1 << 6)
-#define DMA_LISR_DMEIF1 (1 << 8)
-#define DMA_LISR_TEIF1 (1 << 9)
-#define DMA_LISR_HTIF1 (1 << 10)
-#define DMA_LISR_TCIF1 (1 << 11)
-
-#define DMA_LISR_FEIF2 (1 << 16)
-#define DMA_LISR_DMEIF2 (1 << 18)
-#define DMA_LISR_TEIF2 (1 << 19)
-#define DMA_LISR_HTIF2 (1 << 20)
-#define DMA_LISR_TCIF2 (1 << 21)
-
-#define DMA_LISR_FEIF3 (1 << 22)
-#define DMA_LISR_DMEIF3 (1 << 24)
-#define DMA_LISR_TEIF3 (1 << 25)
-#define DMA_LISR_HTIF3 (1 << 26)
-#define DMA_LISR_TCIF3 (1 << 27)
-
-/* --- DMA_HISR values ----------------------------------------------------- */
-
-#define DMA_HISR_FEIF4 (1 << 0)
-#define DMA_HISR_DMEIF4 (1 << 2)
-#define DMA_HISR_TEIF4 (1 << 3)
-#define DMA_HISR_HTIF4 (1 << 4)
-#define DMA_HISR_TCIF4 (1 << 5)
-
-#define DMA_HISR_FEIF5 (1 << 6)
-#define DMA_HISR_DMEIF5 (1 << 8)
-#define DMA_HISR_TEIF5 (1 << 9)
-#define DMA_HISR_HTIF5 (1 << 10)
-#define DMA_HISR_TCIF5 (1 << 11)
-
-#define DMA_HISR_FEIF6 (1 << 16)
-#define DMA_HISR_DMEIF6 (1 << 18)
-#define DMA_HISR_TEIF6 (1 << 19)
-#define DMA_HISR_HTIF6 (1 << 20)
-#define DMA_HISR_TCIF6 (1 << 21)
-
-#define DMA_HISR_FEIF7 (1 << 22)
-#define DMA_HISR_DMEIF7 (1 << 24)
-#define DMA_HISR_TEIF7 (1 << 25)
-#define DMA_HISR_HTIF7 (1 << 26)
-#define DMA_HISR_TCIF7 (1 << 27)
-
-/* --- DMA_LIFCR values ----------------------------------------------------- */
-
-#define DMA_LIFCR_CFEIF0 (1 << 0)
-#define DMA_LIFCR_CDMEIF0 (1 << 2)
-#define DMA_LIFCR_CTEIF0 (1 << 3)
-#define DMA_LIFCR_CHTIF0 (1 << 4)
-#define DMA_LIFCR_CTCIF0 (1 << 5)
-
-#define DMA_LIFCR_CFEIF1 (1 << 6)
-#define DMA_LIFCR_CDMEIF1 (1 << 8)
-#define DMA_LIFCR_CTEIF1 (1 << 9)
-#define DMA_LIFCR_CHTIF1 (1 << 10)
-#define DMA_LIFCR_CTCIF1 (1 << 11)
-
-#define DMA_LIFCR_CFEIF2 (1 << 16)
-#define DMA_LIFCR_CDMEIF2 (1 << 18)
-#define DMA_LIFCR_CTEIF2 (1 << 19)
-#define DMA_LIFCR_CHTIF2 (1 << 20)
-#define DMA_LIFCR_CTCIF2 (1 << 21)
-
-#define DMA_LIFCR_CFEIF3 (1 << 22)
-#define DMA_LIFCR_CDMEIF3 (1 << 24)
-#define DMA_LIFCR_CTEIF3 (1 << 25)
-#define DMA_LIFCR_CHTIF3 (1 << 26)
-#define DMA_LIFCR_CTCIF3 (1 << 27)
-
-/* --- DMA_HIFCR values ----------------------------------------------------- */
-
-#define DMA_HIFCR_CFEIF4 (1 << 0)
-#define DMA_HIFCR_CDMEIF4 (1 << 2)
-#define DMA_HIFCR_CTEIF4 (1 << 3)
-#define DMA_HIFCR_CHTIF4 (1 << 4)
-#define DMA_HIFCR_CTCIF4 (1 << 5)
-
-#define DMA_HIFCR_CFEIF5 (1 << 6)
-#define DMA_HIFCR_CDMEIF5 (1 << 8)
-#define DMA_HIFCR_CTEIF5 (1 << 9)
-#define DMA_HIFCR_CHTIF5 (1 << 10)
-#define DMA_HIFCR_CTCIF5 (1 << 11)
-
-#define DMA_HIFCR_CFEIF6 (1 << 16)
-#define DMA_HIFCR_CDMEIF6 (1 << 18)
-#define DMA_HIFCR_CTEIF6 (1 << 19)
-#define DMA_HIFCR_CHTIF6 (1 << 20)
-#define DMA_HIFCR_CTCIF6 (1 << 21)
-
-#define DMA_HIFCR_CFEIF7 (1 << 22)
-#define DMA_HIFCR_CDMEIF7 (1 << 24)
-#define DMA_HIFCR_CTEIF7 (1 << 25)
-#define DMA_HIFCR_CHTIF7 (1 << 26)
-#define DMA_HIFCR_CTCIF7 (1 << 27)
-
-/* --- DMA_SxCR values ----------------------------------------------------- */
-
-#define DMA_SxCR_EN (1 << 0)
-#define DMA_SxCR_DMEIE (1 << 1)
-#define DMA_SxCR_TEIE (1 << 2)
-#define DMA_SxCR_HTIE (1 << 3)
-#define DMA_SxCR_TCIE (1 << 4)
-#define DMA_SxCR_PFCTRL (1 << 5)
-
-#define DMA_SxCR_DIR_SHIFT 6
-#define DMA_SxCR_DIR_PERIPHERAL_TO_MEM (0 << 6)
-#define DMA_SxCR_DIR_MEM_TO_PERIPHERAL (1 << 6)
-#define DMA_SxCR_DIR_MEM_TO_MEM (2 << 6)
-
-#define DMA_SxCR_CIRC (1 << 8)
-#define DMA_SxCR_PINC (1 << 9)
-#define DMA_SxCR_MINC (1 << 10)
-
-#define DMA_SxCR_PSIZE_SHIFT 11
-#define DMA_SxCR_PSIZE_8BIT (0 << 11)
-#define DMA_SxCR_PSIZE_16BIT (1 << 11)
-#define DMA_SxCR_PSIZE_32BIT (2 << 11)
-
-#define DMA_SxCR_MSIZE_SHIFT 13
-#define DMA_SxCR_MSIZE_8BIT (0 << 13)
-#define DMA_SxCR_MSIZE_16BIT (1 << 13)
-#define DMA_SxCR_MSIZE_32BIT (2 << 13)
-
-#define DMA_SxCR_PINCOS (1 << 15)
-
-#define DMA_SxCR_PL_SHIFT 16
-#define DMA_SxCR_PL_LOW (0 << 16)
-#define DMA_SxCR_PL_MEDIUM (1 << 16)
-#define DMA_SxCR_PL_HIGH (2 << 16)
-#define DMA_SxCR_PL_VERY_HIGH (3 << 16)
-
-#define DMA_SxCR_DBM (1 << 18)
-#define DMA_SxCR_CT (1 << 18)
-
-#define DMA_SxCR_PBURST_SHIFT 21
-#define DMA_SxCR_PBURST_SINGLE (0 << 21)
-#define DMA_SxCR_PBURST_INCR4 (1 << 21)
-#define DMA_SxCR_PBURST_INCR8 (2 << 21)
-#define DMA_SxCR_PBURST_INCR16 (3 << 21)
-
-#define DMA_SxCR_MBURST_SHIFT 23
-#define DMA_SxCR_MBURST_SINGLE (0 << 23)
-#define DMA_SxCR_MBURST_INCR4 (1 << 23)
-#define DMA_SxCR_MBURST_INCR8 (2 << 23)
-#define DMA_SxCR_MBURST_INCR16 (3 << 23)
-
-#define DMA_SxCR_CHSEL_SHIFT 25
-#define DMA_SxCR_CHSEL(n) (n << 25)
-
-/* --- DMA_SxNDTR values --------------------------------------------------- */
-
-/* DMA_SxNDTR[15:0]: Number of data register. */
-
-/* --- DMA_SxPAR values ---------------------------------------------------- */
-
-/* DMA_SxPAR[31:0]: Peripheral address register. */
-
-/* --- DMA_SxM0AR values --------------------------------------------------- */
-
-/* DMA_SxM0AR[31:0]: Memory 0 address register. */
-
-/* --- DMA_SxM1AR values --------------------------------------------------- */
-
-/* DMA_SxM1AR[31:0]: Memory 1 address register. */
-
-/* --- DMA_SxFCR values ---------------------------------------------------- */
-
-#define DMA_SxFCR_FTH_SHIFT 0
-#define DMA_SxFCR_FTH_1_4_FULL (0 << 0)
-#define DMA_SxFCR_FTH_2_4_FULL (1 << 0)
-#define DMA_SxFCR_FTH_3_4_FULL (2 << 0)
-#define DMA_SxFCR_FTH_4_4_FULL (3 << 0)
-
-#define DMA_SxFCR_DMDIS (1 << 2)
-
-#define DMA_SxFCR_FS_SHIFT 3
-#define DMA_SxFCR_FS_LT_1_4_FULL (0 << 0)
-#define DMA_SxFCR_FS_LT_2_4_FULL (1 << 0)
-#define DMA_SxFCR_FS_LT_3_4_FULL (2 << 0)
-#define DMA_SxFCR_FS_LT_4_4_FULL (3 << 0)
-#define DMA_SxFCR_FS_FULL (4 << 3)
-#define DMA_SxFCR_FS_EMPTY (5 << 3)
-
-#define DMA_SxFCR_FEIE (1 << 7)
+#include <libopencm3/stm32/common/dma_common_f24.h>
#endif
+
diff --git a/include/libopencm3/stm32/f2/flash.h b/include/libopencm3/stm32/f2/flash.h
index 2c78757..3e6816f 100644
--- a/include/libopencm3/stm32/f2/flash.h
+++ b/include/libopencm3/stm32/f2/flash.h
@@ -43,76 +43,76 @@
/* --- FLASH_ACR values ---------------------------------------------------- */
-#define FLASH_DCRST (1 << 12)
-#define FLASH_ICRST (1 << 11)
-#define FLASH_DCE (1 << 10)
-#define FLASH_ICE (1 << 9)
-#define FLASH_PRFTEN (1 << 8)
-#define FLASH_LATENCY_0WS 0x00
-#define FLASH_LATENCY_1WS 0x01
-#define FLASH_LATENCY_2WS 0x02
-#define FLASH_LATENCY_3WS 0x03
-#define FLASH_LATENCY_4WS 0x04
-#define FLASH_LATENCY_5WS 0x05
-#define FLASH_LATENCY_6WS 0x06
-#define FLASH_LATENCY_7WS 0x07
+#define FLASH_ACR_DCRST (1 << 12)
+#define FLASH_ACR_ICRST (1 << 11)
+#define FLASH_ACR_DCE (1 << 10)
+#define FLASH_ACR_ICE (1 << 9)
+#define FLASH_ACR_PRFTEN (1 << 8)
+#define FLASH_ACR_LATENCY_0WS 0x00
+#define FLASH_ACR_LATENCY_1WS 0x01
+#define FLASH_ACR_LATENCY_2WS 0x02
+#define FLASH_ACR_LATENCY_3WS 0x03
+#define FLASH_ACR_LATENCY_4WS 0x04
+#define FLASH_ACR_LATENCY_5WS 0x05
+#define FLASH_ACR_LATENCY_6WS 0x06
+#define FLASH_ACR_LATENCY_7WS 0x07
/* --- FLASH_SR values ----------------------------------------------------- */
-#define FLASH_BSY (1 << 16)
-#define FLASH_PGSERR (1 << 7)
-#define FLASH_PGPERR (1 << 6)
-#define FLASH_PGAERR (1 << 5)
-#define FLASH_WRPERR (1 << 4)
-#define FLASH_OPERR (1 << 1)
-#define FLASH_EOP (1 << 0)
+#define FLASH_SR_BSY (1 << 16)
+#define FLASH_SR_PGSERR (1 << 7)
+#define FLASH_SR_PGPERR (1 << 6)
+#define FLASH_SR_PGAERR (1 << 5)
+#define FLASH_SR_WRPERR (1 << 4)
+#define FLASH_SR_OPERR (1 << 1)
+#define FLASH_SR_EOP (1 << 0)
/* --- FLASH_CR values ----------------------------------------------------- */
-#define FLASH_LOCK (1 << 31)
-#define FLASH_ERRIE (1 << 25)
-#define FLASH_EOPIE (1 << 24)
-#define FLASH_STRT (1 << 16)
-#define FLASH_MER (1 << 2)
-#define FLASH_SER (1 << 1)
-#define FLASH_PG (1 << 0)
-#define FLASH_SECTOR_0 (0x00 << 3)
-#define FLASH_SECTOR_1 (0x01 << 3)
-#define FLASH_SECTOR_2 (0x02 << 3)
-#define FLASH_SECTOR_3 (0x03 << 3)
-#define FLASH_SECTOR_4 (0x04 << 3)
-#define FLASH_SECTOR_5 (0x05 << 3)
-#define FLASH_SECTOR_6 (0x06 << 3)
-#define FLASH_SECTOR_7 (0x07 << 3)
-#define FLASH_SECTOR_8 (0x08 << 3)
-#define FLASH_SECTOR_9 (0x09 << 3)
-#define FLASH_SECTOR_10 (0x0a << 3)
-#define FLASH_SECTOR_11 (0x0b << 3)
-#define FLASH_PROGRAM_X8 (0x00 << 8)
-#define FLASH_PROGRAM_X16 (0x01 << 8)
-#define FLASH_PROGRAM_X32 (0x02 << 8)
-#define FLASH_PROGRAM_X64 (0x03 << 8)
+#define FLASH_CR_LOCK (1 << 31)
+#define FLASH_CR_ERRIE (1 << 25)
+#define FLASH_CR_EOPIE (1 << 24)
+#define FLASH_CR_STRT (1 << 16)
+#define FLASH_CR_MER (1 << 2)
+#define FLASH_CR_SER (1 << 1)
+#define FLASH_CR_PG (1 << 0)
+#define FLASH_CR_SECTOR_0 (0x00 << 3)
+#define FLASH_CR_SECTOR_1 (0x01 << 3)
+#define FLASH_CR_SECTOR_2 (0x02 << 3)
+#define FLASH_CR_SECTOR_3 (0x03 << 3)
+#define FLASH_CR_SECTOR_4 (0x04 << 3)
+#define FLASH_CR_SECTOR_5 (0x05 << 3)
+#define FLASH_CR_SECTOR_6 (0x06 << 3)
+#define FLASH_CR_SECTOR_7 (0x07 << 3)
+#define FLASH_CR_SECTOR_8 (0x08 << 3)
+#define FLASH_CR_SECTOR_9 (0x09 << 3)
+#define FLASH_CR_SECTOR_10 (0x0a << 3)
+#define FLASH_CR_SECTOR_11 (0x0b << 3)
+#define FLASH_CR_PROGRAM_X8 (0x00 << 8)
+#define FLASH_CR_PROGRAM_X16 (0x01 << 8)
+#define FLASH_CR_PROGRAM_X32 (0x02 << 8)
+#define FLASH_CR_PROGRAM_X64 (0x03 << 8)
/* --- FLASH_OPTCR values -------------------------------------------------- */
/* FLASH_OPTCR[27:16]: nWRP */
/* FLASH_OBR[15:8]: RDP */
-#define FLASH_NRST_STDBY (1 << 7)
-#define FLASH_NRST_STOP (1 << 6)
-#define FLASH_WDG_SW (1 << 5)
-#define FLASH_OPTSTRT (1 << 1)
-#define FLASH_OPTLOCK (1 << 0)
-#define FLASH_BOR_LEVEL_3 (0x00 << 2)
-#define FLASH_BOR_LEVEL_2 (0x01 << 2)
-#define FLASH_BOR_LEVEL_1 (0x02 << 2)
-#define FLASH_BOR_OFF (0x03 << 2)
+#define FLASH_OPTCR_NRST_STDBY (1 << 7)
+#define FLASH_OPTCR_NRST_STOP (1 << 6)
+#define FLASH_OPTCR_WDG_SW (1 << 5)
+#define FLASH_OPTCR_OPTSTRT (1 << 1)
+#define FLASH_OPTCR_OPTLOCK (1 << 0)
+#define FLASH_OPTCR_BOR_LEVEL_3 (0x00 << 2)
+#define FLASH_OPTCR_BOR_LEVEL_2 (0x01 << 2)
+#define FLASH_OPTCR_BOR_LEVEL_1 (0x02 << 2)
+#define FLASH_OPTCR_BOR_OFF (0x03 << 2)
/* --- FLASH Keys -----------------------------------------------------------*/
-#define FLASH_KEY1 ((u32)0x45670123)
-#define FLASH_KEY2 ((u32)0xcdef89ab)
-#define FLASH_OPTKEY1 ((u32)0x08192a3b)
-#define FLASH_OPTKEY2 ((u32)0x4c5d6e7f)
+#define FLASH_KEYR_KEY1 ((u32)0x45670123)
+#define FLASH_KEYR_KEY2 ((u32)0xcdef89ab)
+#define FLASH_OPTKEYR_KEY1 ((u32)0x08192a3b)
+#define FLASH_OPTKEYR_KEY2 ((u32)0x4c5d6e7f)
/* --- Function prototypes ------------------------------------------------- */
diff --git a/include/libopencm3/stm32/f2/gpio.h b/include/libopencm3/stm32/f2/gpio.h
index 6616769..099fb38 100644
--- a/include/libopencm3/stm32/f2/gpio.h
+++ b/include/libopencm3/stm32/f2/gpio.h
@@ -1,8 +1,23 @@
+/** @defgroup gpio_defines GPIO Defines
+
+@brief <b>Defined Constants and Types for the STM32F2xx General Purpose I/O</b>
+
+@ingroup STM32F2xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
+@author @htmlonly &copy; @endhtmlonly 2012 Piotr Esden-Tempski <piotr@esden.net>
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 1 July 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
/*
* This file is part of the libopencm3 project.
*
- * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
- *
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
@@ -21,262 +36,7 @@
#define LIBOPENCM3_GPIO_H
#include <libopencm3/stm32/memorymap.h>
-#include <libopencm3/cm3/common.h>
-
-/* --- Convenience macros -------------------------------------------------- */
-
-/* GPIO port base addresses (for convenience) */
-#define GPIOA GPIO_PORT_A_BASE
-#define GPIOB GPIO_PORT_B_BASE
-#define GPIOC GPIO_PORT_C_BASE
-#define GPIOD GPIO_PORT_D_BASE
-#define GPIOE GPIO_PORT_E_BASE
-#define GPIOF GPIO_PORT_F_BASE
-#define GPIOG GPIO_PORT_G_BASE
-#define GPIOH GPIO_PORT_H_BASE
-#define GPIOI GPIO_PORT_I_BASE
-
-/* GPIO number definitions (for convenience) */
-#define GPIO0 (1 << 0)
-#define GPIO1 (1 << 1)
-#define GPIO2 (1 << 2)
-#define GPIO3 (1 << 3)
-#define GPIO4 (1 << 4)
-#define GPIO5 (1 << 5)
-#define GPIO6 (1 << 6)
-#define GPIO7 (1 << 7)
-#define GPIO8 (1 << 8)
-#define GPIO9 (1 << 9)
-#define GPIO10 (1 << 10)
-#define GPIO11 (1 << 11)
-#define GPIO12 (1 << 12)
-#define GPIO13 (1 << 13)
-#define GPIO14 (1 << 14)
-#define GPIO15 (1 << 15)
-#define GPIO_ALL 0xffff
-
-/* --- GPIO registers ------------------------------------------------------ */
-
-/* Port mode register (GPIOx_MODER) */
-#define GPIO_MODER(port) MMIO32(port + 0x00)
-#define GPIOA_MODER GPIO_MODER(GPIOA)
-#define GPIOB_MODER GPIO_MODER(GPIOB)
-#define GPIOC_MODER GPIO_MODER(GPIOC)
-#define GPIOD_MODER GPIO_MODER(GPIOD)
-#define GPIOE_MODER GPIO_MODER(GPIOE)
-#define GPIOF_MODER GPIO_MODER(GPIOF)
-#define GPIOG_MODER GPIO_MODER(GPIOG)
-#define GPIOH_MODER GPIO_MODER(GPIOH)
-#define GPIOI_MODER GPIO_MODER(GPIOI)
-
-/* Port output type register (GPIOx_OTYPER) */
-#define GPIO_OTYPER(port) MMIO32(port + 0x04)
-#define GPIOA_OTYPER GPIO_OTYPER(GPIOA)
-#define GPIOB_OTYPER GPIO_OTYPER(GPIOB)
-#define GPIOC_OTYPER GPIO_OTYPER(GPIOC)
-#define GPIOD_OTYPER GPIO_OTYPER(GPIOD)
-#define GPIOE_OTYPER GPIO_OTYPER(GPIOE)
-#define GPIOF_OTYPER GPIO_OTYPER(GPIOF)
-#define GPIOG_OTYPER GPIO_OTYPER(GPIOG)
-#define GPIOH_OTYPER GPIO_OTYPER(GPIOH)
-#define GPIOI_OTYPER GPIO_OTYPER(GPIOI)
-
-/* Port output speed register (GPIOx_OSPEEDR) */
-#define GPIO_OSPEEDR(port) MMIO32(port + 0x08)
-#define GPIOA_OSPEEDR GPIO_OSPEEDR(GPIOA)
-#define GPIOB_OSPEEDR GPIO_OSPEEDR(GPIOB)
-#define GPIOC_OSPEEDR GPIO_OSPEEDR(GPIOC)
-#define GPIOD_OSPEEDR GPIO_OSPEEDR(GPIOD)
-#define GPIOE_OSPEEDR GPIO_OSPEEDR(GPIOE)
-#define GPIOF_OSPEEDR GPIO_OSPEEDR(GPIOF)
-#define GPIOG_OSPEEDR GPIO_OSPEEDR(GPIOG)
-#define GPIOH_OSPEEDR GPIO_OSPEEDR(GPIOH)
-#define GPIOI_OSPEEDR GPIO_OSPEEDR(GPIOI)
-
-/* Port pull-up/pull-down register (GPIOx_PUPDR) */
-#define GPIO_PUPDR(port) MMIO32(port + 0x0c)
-#define GPIOA_PUPDR GPIO_PUPDR(GPIOA)
-#define GPIOB_PUPDR GPIO_PUPDR(GPIOB)
-#define GPIOC_PUPDR GPIO_PUPDR(GPIOC)
-#define GPIOD_PUPDR GPIO_PUPDR(GPIOD)
-#define GPIOE_PUPDR GPIO_PUPDR(GPIOE)
-#define GPIOF_PUPDR GPIO_PUPDR(GPIOF)
-#define GPIOG_PUPDR GPIO_PUPDR(GPIOG)
-#define GPIOH_PUPDR GPIO_PUPDR(GPIOH)
-#define GPIOI_PUPDR GPIO_PUPDR(GPIOI)
-
-/* Port input data register (GPIOx_IDR) */
-#define GPIO_IDR(port) MMIO32(port + 0x10)
-#define GPIOA_IDR GPIO_IDR(GPIOA)
-#define GPIOB_IDR GPIO_IDR(GPIOB)
-#define GPIOC_IDR GPIO_IDR(GPIOC)
-#define GPIOD_IDR GPIO_IDR(GPIOD)
-#define GPIOE_IDR GPIO_IDR(GPIOE)
-#define GPIOF_IDR GPIO_IDR(GPIOF)
-#define GPIOG_IDR GPIO_IDR(GPIOG)
-#define GPIOH_IDR GPIO_IDR(GPIOH)
-#define GPIOI_IDR GPIO_IDR(GPIOI)
-
-/* Port output data register (GPIOx_ODR) */
-#define GPIO_ODR(port) MMIO32(port + 0x14)
-#define GPIOA_ODR GPIO_ODR(GPIOA)
-#define GPIOB_ODR GPIO_ODR(GPIOB)
-#define GPIOC_ODR GPIO_ODR(GPIOC)
-#define GPIOD_ODR GPIO_ODR(GPIOD)
-#define GPIOE_ODR GPIO_ODR(GPIOE)
-#define GPIOF_ODR GPIO_ODR(GPIOF)
-#define GPIOG_ODR GPIO_ODR(GPIOG)
-#define GPIOH_ODR GPIO_ODR(GPIOH)
-#define GPIOI_ODR GPIO_ODR(GPIOI)
-
-/* Port bit set/reset register (GPIOx_BSRR) */
-#define GPIO_BSRR(port) MMIO32(port + 0x18)
-#define GPIOA_BSRR GPIO_BSRR(GPIOA)
-#define GPIOB_BSRR GPIO_BSRR(GPIOB)
-#define GPIOC_BSRR GPIO_BSRR(GPIOC)
-#define GPIOD_BSRR GPIO_BSRR(GPIOD)
-#define GPIOE_BSRR GPIO_BSRR(GPIOE)
-#define GPIOF_BSRR GPIO_BSRR(GPIOF)
-#define GPIOG_BSRR GPIO_BSRR(GPIOG)
-#define GPIOH_BSRR GPIO_BSRR(GPIOH)
-#define GPIOI_BSRR GPIO_BSRR(GPIOI)
-
-/* Port configuration lock register (GPIOx_LCKR) */
-#define GPIO_LCKR(port) MMIO32(port + 0x1c)
-#define GPIOA_LCKR GPIO_LCKR(GPIOA)
-#define GPIOB_LCKR GPIO_LCKR(GPIOB)
-#define GPIOC_LCKR GPIO_LCKR(GPIOC)
-#define GPIOD_LCKR GPIO_LCKR(GPIOD)
-#define GPIOE_LCKR GPIO_LCKR(GPIOE)
-#define GPIOF_LCKR GPIO_LCKR(GPIOF)
-#define GPIOG_LCKR GPIO_LCKR(GPIOG)
-#define GPIOH_LCKR GPIO_LCKR(GPIOH)
-#define GPIOI_LCKR GPIO_LCKR(GPIOI)
-
-/* Alternate function low register (GPIOx_AFRL) */
-#define GPIO_AFRL(port) MMIO32(port + 0x20)
-#define GPIOA_AFRL GPIO_AFRL(GPIOA)
-#define GPIOB_AFRL GPIO_AFRL(GPIOB)
-#define GPIOC_AFRL GPIO_AFRL(GPIOC)
-#define GPIOD_AFRL GPIO_AFRL(GPIOD)
-#define GPIOE_AFRL GPIO_AFRL(GPIOE)
-#define GPIOF_AFRL GPIO_AFRL(GPIOF)
-#define GPIOG_AFRL GPIO_AFRL(GPIOG)
-#define GPIOH_AFRL GPIO_AFRL(GPIOH)
-#define GPIOI_AFRL GPIO_AFRL(GPIOI)
-
-/* Alternate function high register (GPIOx_AFRH) */
-#define GPIO_AFRH(port) MMIO32(port + 0x24)
-#define GPIOA_AFRH GPIO_AFRH(GPIOA)
-#define GPIOB_AFRH GPIO_AFRH(GPIOB)
-#define GPIOC_AFRH GPIO_AFRH(GPIOC)
-#define GPIOD_AFRH GPIO_AFRH(GPIOD)
-#define GPIOE_AFRH GPIO_AFRH(GPIOE)
-#define GPIOF_AFRH GPIO_AFRH(GPIOF)
-#define GPIOG_AFRH GPIO_AFRH(GPIOG)
-#define GPIOH_AFRH GPIO_AFRH(GPIOH)
-#define GPIOI_AFRH GPIO_AFRH(GPIOI)
-
-/* --- GPIOx_MODER values -------------------------------------------------- */
-
-#define GPIO_MODE(n, mode) (mode << (2 * (n)))
-#define GPIO_MODE_MASK(n) (0x3 << (2 * (n)))
-#define GPIO_MODE_INPUT 0x0
-#define GPIO_MODE_OUTPUT 0x1
-#define GPIO_MODE_AF 0x2
-#define GPIO_MODE_ANALOG 0x3
-
-/* --- GPIOx_OTYPER values ------------------------------------------------- */
-
-#define GPIO_OTYPE_PP 0x0
-#define GPIO_OTYPE_OD 0x1
-
-/* --- GPIOx_OSPEEDR values ------------------------------------------------ */
-
-#define GPIO_OSPEED(n, speed) (speed << (2 * (n)))
-#define GPIO_OSPEED_MASK(n) (0x3 << (2 * (n)))
-#define GPIO_OSPEED_2MHZ 0x0
-#define GPIO_OSPEED_25MHZ 0x1
-#define GPIO_OSPEED_50MHZ 0x2
-#define GPIO_OSPEED_100MHZ 0x3
-
-/* --- GPIOx_PUPDR values -------------------------------------------------- */
-
-#define GPIO_PUPD(n, pupd) (pupd << (2 * (n)))
-#define GPIO_PUPD_MASK(n) (0x3 << (2 * (n)))
-#define GPIO_PUPD_NONE 0x0
-#define GPIO_PUPD_PULLUP 0x1
-#define GPIO_PUPD_PULLDOWN 0x2
-
-/* --- GPIOx_IDR values ---------------------------------------------------- */
-
-/* GPIOx_IDR[15:0]: IDRy[15:0]: Port input data (y = 0..15) */
-
-/* --- GPIOx_ODR values ---------------------------------------------------- */
-
-/* GPIOx_ODR[15:0]: ODRy[15:0]: Port output data (y = 0..15) */
-
-/* --- GPIOx_BSRR values --------------------------------------------------- */
-
-/* GPIOx_BSRR[31:16]: BRy: Port x reset bit y (y = 0..15) */
-/* GPIOx_BSRR[15:0]: BSy: Port x set bit y (y = 0..15) */
-
-/* --- GPIOx_LCKR values --------------------------------------------------- */
-
-#define GPIO_LCKK (1 << 16)
-/* GPIOx_LCKR[15:0]: LCKy: Port x lock bit y (y = 0..15) */
-
-/* --- GPIOx_AFRL/H values ------------------------------------------------- */
-
-/* Note: AFRL is used for bits 0..7, AFRH is used for 8..15 */
-/* See Datasheet Table 6 (pg. 48) for alternate function mappings. */
-
-#define GPIO_AFR(n, af) (af << ((n) * 4))
-#define GPIO_AFR_MASK(n) (0xf << ((n) * 4))
-#define GPIO_AF0 0x0
-#define GPIO_AF1 0x1
-#define GPIO_AF2 0x2
-#define GPIO_AF3 0x3
-#define GPIO_AF4 0x4
-#define GPIO_AF5 0x5
-#define GPIO_AF6 0x6
-#define GPIO_AF7 0x7
-#define GPIO_AF8 0x8
-#define GPIO_AF9 0x9
-#define GPIO_AF10 0xa
-#define GPIO_AF11 0xb
-#define GPIO_AF12 0xc
-#define GPIO_AF13 0xd
-#define GPIO_AF14 0xe
-#define GPIO_AF15 0xf
-
-/* Note: EXTI source selection is now in the SYSCFG peripheral. */
-
-/* --- Function prototypes ------------------------------------------------- */
-
-BEGIN_DECLS
-
-/*
- * Note: The F2 series has a completely new GPIO peripheral with different
- * configuration options. Here we implement a different API partly to more
- * closely match the peripheral capabilities and also to deliberately break
- * compatibility with old F1 code so there is no confusion with similar
- * sounding functions that have very different functionality.
- */
-
-void gpio_mode_setup(u32 gpioport, u8 mode, u8 pull_up_down, u16 gpios);
-void gpio_set_output_options(u32 gpioport, u8 otype, u8 speed, u16 gpios);
-void gpio_set_af(u32 gpioport, u8 alt_func_num, u16 gpios);
-
-/* This part of the API is compatible with the F1 series ------------------- */
-void gpio_set(u32 gpioport, u16 gpios);
-void gpio_clear(u32 gpioport, u16 gpios);
-u16 gpio_get(u32 gpioport, u16 gpios);
-void gpio_toggle(u32 gpioport, u16 gpios);
-u16 gpio_port_read(u32 gpioport);
-void gpio_port_write(u32 gpioport, u16 data);
-void gpio_port_config_lock(u32 gpioport, u16 gpios);
-
-END_DECLS
+#include <libopencm3/stm32/common/gpio_common_f24.h>
#endif
+
diff --git a/include/libopencm3/stm32/f2/i2c.h b/include/libopencm3/stm32/f2/i2c.h
new file mode 100644
index 0000000..3dc1652
--- /dev/null
+++ b/include/libopencm3/stm32/f2/i2c.h
@@ -0,0 +1,41 @@
+/** @defgroup i2c_defines I2C Defines
+
+@brief <b>Defined Constants and Types for the STM32F2xx I2C </b>
+
+@ingroup STM32F2xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 12 October 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_I2C_H
+#define LIBOPENCM3_I2C_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/i2c_common_f24.h>
+
+#endif
+
diff --git a/include/libopencm3/stm32/f2/irq.yaml b/include/libopencm3/stm32/f2/irq.yaml
new file mode 100644
index 0000000..c3600b3
--- /dev/null
+++ b/include/libopencm3/stm32/f2/irq.yaml
@@ -0,0 +1,85 @@
+includeguard: LIBOPENCM3_STM32_F2_NVIC_H
+partname_humanreadable: STM32 F2 series
+partname_doxygen: STM32F2
+irqs:
+ - nvic_wwdg
+ - pvd
+ - tamp_stamp
+ - rtc_wkup
+ - flash
+ - rcc
+ - exti0
+ - exti1
+ - exti2
+ - exti3
+ - exti4
+ - dma1_stream0
+ - dma1_stream1
+ - dma1_stream2
+ - dma1_stream3
+ - dma1_stream4
+ - dma1_stream5
+ - dma1_stream6
+ - adc
+ - can1_tx
+ - can1_rx0
+ - can1_rx1
+ - can1_sce
+ - exti9_5
+ - tim1_brk_tim9
+ - tim1_up_tim10
+ - tim1_trg_com_tim11
+ - tim1_cc
+ - tim2
+ - tim3
+ - tim4
+ - i2c1_ev
+ - i2c1_er
+ - i2c2_ev
+ - i2c2_er
+ - spi1
+ - spi2
+ - usart1
+ - usart2
+ - usart3
+ - exti15_10
+ - rtc_alarm
+ - usb_fs_wkup
+ - tim8_brk_tim12
+ - tim8_up_tim13
+ - tim8_trg_com_tim14
+ - tim8_cc
+ - dma1_stream7
+ - fsmc
+ - sdio
+ - tim5
+ - spi3
+ - uart4
+ - uart5
+ - tim6_dac
+ - tim7
+ - dma2_stream0
+ - dma2_stream1
+ - dma2_stream2
+ - dma2_stream3
+ - dma2_stream4
+ - eth
+ - eth_wkup
+ - can2_tx
+ - can2_rx0
+ - can2_rx1
+ - can2_sce
+ - otg_fs
+ - dma2_stream5
+ - dma2_stream6
+ - dma2_stream7
+ - usart6
+ - i2c3_ev
+ - i2c3_er
+ - otg_hs_ep1_out
+ - otg_hs_ep1_in
+ - otg_hs_wkup
+ - otg_hs
+ - dcmi
+ - cryp
+ - hash_rng
diff --git a/include/libopencm3/stm32/f2/iwdg.h b/include/libopencm3/stm32/f2/iwdg.h
new file mode 100644
index 0000000..d15f9a9
--- /dev/null
+++ b/include/libopencm3/stm32/f2/iwdg.h
@@ -0,0 +1,41 @@
+/** @defgroup iwdg_defines IWDG Defines
+
+@brief <b>Defined Constants and Types for the STM32F2xx Independent Watchdog Timer</b>
+
+@ingroup STM32F2xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
+
+@date 18 August 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_IWDG_H
+#define LIBOPENCM3_IWDG_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/iwdg_common_all.h>
+
+#endif
+
diff --git a/include/libopencm3/stm32/f2/nvic_f2.h b/include/libopencm3/stm32/f2/nvic_f2.h
deleted file mode 100644
index 2bf2997..0000000
--- a/include/libopencm3/stm32/f2/nvic_f2.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * This file is part of the libopencm3 project.
- *
- * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef LIBOPENCM3_NVIC_F2_H
-#define LIBOPENCM3_NVIC_F2_H
-
-/* --- IRQ channel numbers-------------------------------------------------- */
-
-/* Note: These F2 specific user interrupt definitions supplement the
- * general NVIC definitions in ../nvic.h
- */
-
-/* User Interrupts */
-#define NVIC_NVIC_WWDG_IRQ 0
-#define NVIC_PVD_IRQ 1
-#define NVIC_TAMP_STAMP_IRQ 2
-#define NVIC_RTC_WKUP_IRQ 3
-#define NVIC_FLASH_IRQ 4
-#define NVIC_RCC_IRQ 5
-#define NVIC_EXTI0_IRQ 6
-#define NVIC_EXTI1_IRQ 7
-#define NVIC_EXTI2_IRQ 8
-#define NVIC_EXTI3_IRQ 9
-#define NVIC_EXTI4_IRQ 10
-#define NVIC_DMA1_STREAM0_IRQ 11
-#define NVIC_DMA1_STREAM1_IRQ 12
-#define NVIC_DMA1_STREAM2_IRQ 13
-#define NVIC_DMA1_STREAM3_IRQ 14
-#define NVIC_DMA1_STREAM4_IRQ 15
-#define NVIC_DMA1_STREAM5_IRQ 16
-#define NVIC_DMA1_STREAM6_IRQ 17
-#define NVIC_ADC_IRQ 18
-#define NVIC_CAN1_TX_IRQ 19
-#define NVIC_CAN1_RX0_IRQ 20
-#define NVIC_CAN1_RX1_IRQ 21
-#define NVIC_CAN1_SCE_IRQ 22
-#define NVIC_EXTI9_5_IRQ 23
-#define NVIC_TIM1_BRK_TIM9_IRQ 24
-#define NVIC_TIM1_UP_TIM10_IRQ 25
-#define NVIC_TIM1_TRG_COM_TIM11_IRQ 26
-#define NVIC_TIM1_CC_IRQ 27
-#define NVIC_TIM2_IRQ 28
-#define NVIC_TIM3_IRQ 29
-#define NVIC_TIM4_IRQ 30
-#define NVIC_I2C1_EV_IRQ 31
-#define NVIC_I2C1_ER_IRQ 32
-#define NVIC_I2C2_EV_IRQ 33
-#define NVIC_I2C2_ER_IRQ 34
-#define NVIC_SPI1_IRQ 35
-#define NVIC_SPI2_IRQ 36
-#define NVIC_USART1_IRQ 37
-#define NVIC_USART2_IRQ 38
-#define NVIC_USART3_IRQ 39
-#define NVIC_EXTI15_10_IRQ 40
-#define NVIC_RTC_ALARM_IRQ 41
-#define NVIC_USB_FS_WKUP_IRQ 42
-#define NVIC_TIM8_BRK_TIM12_IRQ 43
-#define NVIC_TIM8_UP_TIM13_IRQ 44
-#define NVIC_TIM8_TRG_COM_TIM14_IRQ 45
-#define NVIC_TIM8_CC_IRQ 46
-#define NVIC_DMA1_STREAM7_IRQ 47
-#define NVIC_FSMC_IRQ 48
-#define NVIC_SDIO_IRQ 49
-#define NVIC_TIM5_IRQ 50
-#define NVIC_SPI3_IRQ 51
-#define NVIC_UART4_IRQ 52
-#define NVIC_UART5_IRQ 53
-#define NVIC_TIM6_DAC_IRQ 54
-#define NVIC_TIM7_IRQ 55
-#define NVIC_DMA2_STREAM0_IRQ 56
-#define NVIC_DMA2_STREAM1_IRQ 57
-#define NVIC_DMA2_STREAM2_IRQ 58
-#define NVIC_DMA2_STREAM3_IRQ 59
-#define NVIC_DMA2_STREAM4_IRQ 60
-#define NVIC_ETH_IRQ 61
-#define NVIC_ETH_WKUP_IRQ 62
-#define NVIC_CAN2_TX_IRQ 63
-#define NVIC_CAN2_RX0_IRQ 64
-#define NVIC_CAN2_RX1_IRQ 65
-#define NVIC_CAN2_SCE_IRQ 66
-#define NVIC_OTG_FS_IRQ 67
-#define NVIC_DMA2_STREAM5_IRQ 68
-#define NVIC_DMA2_STREAM6_IRQ 69
-#define NVIC_DMA2_STREAM7_IRQ 70
-#define NVIC_USART6_IRQ 71
-#define NVIC_I2C3_EV_IRQ 72
-#define NVIC_I2C3_ER_IRQ 73
-#define NVIC_OTG_HS_EP1_OUT_IRQ 74
-#define NVIC_OTG_HS_EP1_IN_IRQ 75
-#define NVIC_OTG_HS_WKUP_IRQ 76
-#define NVIC_OTG_HS_IRQ 77
-#define NVIC_DCMI_IRQ 78
-#define NVIC_CRYP_IRQ 79
-#define NVIC_HASH_RNG_IRQ 80
-
-#endif
diff --git a/include/libopencm3/stm32/f2/rcc.h b/include/libopencm3/stm32/f2/rcc.h
index 4ffa242..1af6ccf 100644
--- a/include/libopencm3/stm32/f2/rcc.h
+++ b/include/libopencm3/stm32/f2/rcc.h
@@ -426,7 +426,7 @@
#define RCC_CSR_SFTRSTF (1 << 28)
#define RCC_CSR_PORRSTF (1 << 27)
#define RCC_CSR_PINRSTF (1 << 26)
-#define RCC_CSR_BORRSTF (1 << 26)
+#define RCC_CSR_BORRSTF (1 << 25)
#define RCC_CSR_RMVF (1 << 24)
#define RCC_CSR_LSIRDY (1 << 1)
#define RCC_CSR_LSION (1 << 0)
diff --git a/include/libopencm3/stm32/f2/rng.h b/include/libopencm3/stm32/f2/rng.h
new file mode 100644
index 0000000..403c7c7
--- /dev/null
+++ b/include/libopencm3/stm32/f2/rng.h
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_RNG_F2_H
+#define LIBOPENCM3_RNG_F2_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/rng_common_f24.h>
+
+#endif
diff --git a/include/libopencm3/stm32/f2/rtc.h b/include/libopencm3/stm32/f2/rtc.h
new file mode 100644
index 0000000..ebc0936
--- /dev/null
+++ b/include/libopencm3/stm32/f2/rtc.h
@@ -0,0 +1,39 @@
+/** @defgroup rtc_defines RTC Defines
+
+@brief <b>Defined Constants and Types for the STM32F2xx RTC</b>
+
+@ingroup STM32F2xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 5 December 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_RTC_H
+#define LIBOPENCM3_RTC_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/rtc_common_bcd.h>
+
+#endif \ No newline at end of file
diff --git a/include/libopencm3/stm32/f2/scb.h b/include/libopencm3/stm32/f2/scb.h
deleted file mode 100644
index 181aa7a..0000000
--- a/include/libopencm3/stm32/f2/scb.h
+++ /dev/null
@@ -1,307 +0,0 @@
-/*
- * This file is part of the libopencm3 project.
- *
- * Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
- * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef LIBOPENCM3_SCB_H
-#define LIBOPENCM3_SCB_H
-
-#include <libopencm3/stm32/memorymap.h>
-#include <libopencm3/cm3/common.h>
-
-/* --- SCB: Registers ------------------------------------------------------ */
-
-/* CPUID: CPUID base register */
-#define SCB_CPUID MMIO32(SCB_BASE + 0x00)
-
-/* ICSR: Interrupt Control State Register */
-#define SCB_ICSR MMIO32(SCB_BASE + 0x04)
-
-/* VTOR: Vector Table Offset Register */
-#define SCB_VTOR MMIO32(SCB_BASE + 0x08)
-
-/* AIRCR: Application Interrupt and Reset Control Register */
-#define SCB_AIRCR MMIO32(SCB_BASE + 0x0C)
-
-/* SCR: System Control Register */
-#define SCB_SCR MMIO32(SCB_BASE + 0x10)
-
-/* CCR: Configuration Control Register */
-#define SCB_CCR MMIO32(SCB_BASE + 0x14)
-
-/* SHP: System Handler Priority Registers */
-/* Note: 12 8bit registers */
-#define SCB_SHPR(shpr_id) MMIO8(SCB_BASE + 0x18 + shpr_id)
-#define SCB_SHPR1 MMIO8(SCB_BASE + 0x18 + 1)
-#define SCB_SHPR2 MMIO8(SCB_BASE + 0x18 + 2)
-#define SCB_SHPR3 MMIO8(SCB_BASE + 0x18 + 3)
-
-/* SHCSR: System Handler Control and State Register */
-#define SCB_SHCSR MMIO32(SCB_BASE + 0x24)
-
-/* CFSR: Configurable Fault Status Registers */
-#define SCB_CFSR MMIO32(SCB_BASE + 0x28)
-
-/* HFSR: Hard Fault Status Register */
-#define SCB_HFSR MMIO32(SCB_BASE + 0x2C)
-
-/* DFSR: Debug Fault Status Register */
-#define SCB_DFSR MMIO32(SCB_BASE + 0x30)
-
-/* MMFAR: Memory Manage Fault Address Register */
-#define SCB_MMFAR MMIO32(SCB_BASE + 0x34)
-
-/* BFAR: Bus Fault Address Register */
-#define SCB_BFAR MMIO32(SCB_BASE + 0x38)
-
-/* AFSR: Auxiliary Fault Status Register */
-#define SCB_AFSR MMIO32(SCB_BASE + 0x3C)
-
-/* --- SCB values ---------------------------------------------------------- */
-
-/* --- SCB_CPUID values ---------------------------------------------------- */
-
-/* Implementer[31:24]: Implementer code */
-#define SCP_CPUID_IMPLEMENTER_LSB 24
-/* Variant[23:20]: Variant number */
-#define SCP_CPUID_VARIANT_LSB 20
-/* Constant[19:16]: Reads as 0xF */
-#define SCP_CPUID_CONSTANT_LSB 16
-/* PartNo[15:4]: Part number of the processor */
-#define SCP_CPUID_PARTNO_LSB 4
-/* Revision[3:0]: Revision number */
-#define SCP_CPUID_REVISION_LSB 0
-
-/* --- SCB_ICSR values ----------------------------------------------------- */
-
-/* NMIPENDSET: NMI set-pending bit */
-#define SCB_ICSR_NMIPENDSET (1 << 31)
-/* Bits [30:29]: reserved - must be kept cleared */
-/* PENDSVSET: PendSV set-pending bit */
-#define SCB_ICSR_PENDSVSET (1 << 28)
-/* PENDSVCLR: PendSV clear-pending bit */
-#define SCB_ICSR_PENDSVCLR (1 << 27)
-/* PENDSTSET: SysTick exception set-pending bit */
-#define SCB_ICSR_PENDSTSET (1 << 26)
-/* PENDSTCLR: SysTick exception clear-pending bit */
-#define SCB_ICSR_PENDSTCLR (1 << 25)
-/* Bit 24: reserved - must be kept cleared */
-/* Bit 23: reserved for debug - reads as 0 when not in debug mode */
-/* ISRPENDING: Interrupt pending flag, excluding NMI and Faults */
-#define SCB_ICSR_ISRPENDING (1 << 22)
-/* VECTPENDING[21:12] Pending vector */
-#define SCB_ICSR_VECTPENDING_LSB 12
-/* RETOBASE: Return to base level */
-#define SCB_ICSR_RETOBASE (1 << 11)
-/* Bits [10:9]: reserved - must be kept cleared */
-/* VECTACTIVE[8:0] Active vector */
-#define SCB_ICSR_VECTACTIVE_LSB 0
-
-/* --- SCB_VTOR values ----------------------------------------------------- */
-
-/* Bits [31:30]: reserved - must be kept cleared */
-/* TBLOFF[29:9]: Vector table base offset field */
-#define SCB_VTOR_TBLOFF_LSB 9 /* inconsistent datasheet - LSB could be 11 */
-
-/* --- SCB_AIRCR values ---------------------------------------------------- */
-
-/* VECTKEYSTAT[31:16]/ VECTKEY[31:16] Register key */
-#define SCB_AIRCR_VECTKEYSTAT_LSB 16
-#define SCB_AIRCR_VECTKEY 0x05FA0000
-/* ENDIANESS Data endianness bit */
-#define SCB_AIRCR_ENDIANESS (1 << 15)
-/* Bits [14:11]: reserved - must be kept cleared */
-/* PRIGROUP[10:8]: Interrupt priority grouping field */
-#define SCB_AIRCR_PRIGROUP_GROUP16_NOSUB (0x3 << 8)
-#define SCB_AIRCR_PRIGROUP_GROUP8_SUB2 (0x4 << 8)
-#define SCB_AIRCR_PRIGROUP_GROUP4_SUB4 (0x5 << 8)
-#define SCB_AIRCR_PRIGROUP_GROUP2_SUB8 (0x6 << 8)
-#define SCB_AIRCR_PRIGROUP_NOGROUP_SUB16 (0x7 << 8)
-#define SCB_AIRCR_PRIGROUP_MASK (0x7 << 8)
-#define SCB_AIRCR_PRIGROUP_SHIFT 8
-/* Bits [7:3]: reserved - must be kept cleared */
-/* SYSRESETREQ System reset request */
-#define SCB_AIRCR_SYSRESETREQ (1 << 2)
-/* VECTCLRACTIVE */
-#define SCB_AIRCR_VECTCLRACTIVE (1 << 1)
-/* VECTRESET */
-#define SCB_AIRCR_VECTRESET (1 << 0)
-
-/* --- SCB_SCR values ------------------------------------------------------ */
-
-/* Bits [31:5]: reserved - must be kept cleared */
-/* SEVEONPEND Send Event on Pending bit */
-#define SCB_SCR_SEVEONPEND (1 << 4)
-/* Bit 3: reserved - must be kept cleared */
-/* SLEEPDEEP */
-#define SCB_SCR_SLEEPDEEP (1 << 2)
-/* SLEEPONEXIT */
-#define SCB_SCR_SLEEPONEXIT (1 << 1)
-/* Bit 0: reserved - must be kept cleared */
-
-/* --- SCB_CCR values ------------------------------------------------------ */
-
-/* Bits [31:10]: reserved - must be kept cleared */
-/* STKALIGN */
-#define SCB_CCR_STKALIGN (1 << 9)
-/* BFHFNMIGN */
-#define SCB_CCR_BFHFNMIGN (1 << 8)
-/* Bits [7:5]: reserved - must be kept cleared */
-/* DIV_0_TRP */
-#define SCB_CCR_DIV_0_TRP (1 << 4)
-/* UNALIGN_TRP */
-#define SCB_CCR_UNALIGN_TRP (1 << 3)
-/* Bit 2: reserved - must be kept cleared */
-/* USERSETMPEND */
-#define SCB_CCR_USERSETMPEND (1 << 1)
-/* NONBASETHRDENA */
-#define SCB_CCR_NONBASETHRDENA (1 << 0)
-
-/* --- SCB_SHPR1 values ---------------------------------------------------- */
-
-/* Bits [31:24]: reserved - must be kept cleared */
-/* PRI_6[23:16]: Priority of system handler 6, usage fault */
-#define SCB_SHPR1_PRI_6_LSB 16
-/* PRI_5[15:8]: Priority of system handler 5, bus fault */
-#define SCB_SHPR1_PRI_5_LSB 8
-/* PRI_4[7:0]: Priority of system handler 4, memory management fault */
-#define SCB_SHPR1_PRI_4_LSB 0
-
-/* --- SCB_SHPR2 values ---------------------------------------------------- */
-
-/* PRI_11[31:24]: Priority of system handler 11, SVCall */
-#define SCB_SHPR2_PRI_11_LSB 24
-/* Bits [23:0]: reserved - must be kept cleared */
-
-/* --- SCB_SHPR3 values ---------------------------------------------------- */
-
-/* PRI_15[31:24]: Priority of system handler 15, SysTick exception */
-#define SCB_SHPR3_PRI_15_LSB 24
-/* PRI_14[23:16]: Priority of system handler 14, PendSV */
-#define SCB_SHPR3_PRI_14_LSB 16
-/* Bits [15:0]: reserved - must be kept cleared */
-
-/* --- SCB_SHCSR values ---------------------------------------------------- */
-
-/* Bits [31:19]: reserved - must be kept cleared */
-/* USGFAULTENA: Usage fault enable */
-#define SCB_SHCSR_USGFAULTENA (1 << 18)
-/* BUSFAULTENA: Bus fault enable */
-#define SCB_SHCSR_BUSFAULTENA (1 << 17)
-/* MEMFAULTENA: Memory management fault enable */
-#define SCB_SHCSR_MEMFAULTENA (1 << 16)
-/* SVCALLPENDED: SVC call pending */
-#define SCB_SHCSR_SVCALLPENDED (1 << 15)
-/* BUSFAULTPENDED: Bus fault exception pending */
-#define SCB_SHCSR_BUSFAULTPENDED (1 << 14)
-/* MEMFAULTPENDED: Memory management fault exception pending */
-#define SCB_SHCSR_MEMFAULTPENDED (1 << 13)
-/* USGFAULTPENDED: Usage fault exception pending */
-#define SCB_SHCSR_USGFAULTPENDED (1 << 12)
-/* SYSTICKACT: SysTick exception active */
-#define SCB_SHCSR_SYSTICKACT (1 << 11)
-/* PENDSVACT: PendSV exception active */
-#define SCB_SHCSR_PENDSVACT (1 << 10)
-/* Bit 9: reserved - must be kept cleared */
-/* MONITORACT: Debug monitor active */
-#define SCB_SHCSR_MONITORACT (1 << 8)
-/* SVCALLACT: SVC call active */
-#define SCB_SHCSR_SVCALLACT (1 << 7)
-/* Bits [6:4]: reserved - must be kept cleared */
-/* USGFAULTACT: Usage fault exception active */
-#define SCB_SHCSR_USGFAULTACT (1 << 3)
-/* Bit 2: reserved - must be kept cleared */
-/* BUSFAULTACT: Bus fault exception active */
-#define SCB_SHCSR_BUSFAULTACT (1 << 1)
-/* MEMFAULTACT: Memory management fault exception active */
-#define SCB_SHCSR_MEMFAULTACT (1 << 0)
-
-/* --- SCB_CFSR values ----------------------------------------------------- */
-
-/* Bits [31:26]: reserved - must be kept cleared */
-/* DIVBYZERO: Divide by zero usage fault */
-#define SCB_CFSR_DIVBYZERO (1 << 25)
-/* UNALIGNED: Unaligned access usage fault */
-#define SCB_CFSR_UNALIGNED (1 << 24)
-/* Bits [23:20]: reserved - must be kept cleared */
-/* NOCP: No coprocessor usage fault */
-#define SCB_CFSR_NOCP (1 << 19)
-/* INVPC: Invalid PC load usage fault */
-#define SCB_CFSR_INVPC (1 << 18)
-/* INVSTATE: Invalid state usage fault */
-#define SCB_CFSR_INVSTATE (1 << 17)
-/* UNDEFINSTR: Undefined instruction usage fault */
-#define SCB_CFSR_UNDEFINSTR (1 << 16)
-/* BFARVALID: Bus Fault Address Register (BFAR) valid flag */
-#define SCB_CFSR_BFARVALID (1 << 15)
-/* Bits [14:13]: reserved - must be kept cleared */
-/* STKERR: Bus fault on stacking for exception entry */
-#define SCB_CFSR_STKERR (1 << 12)
-/* UNSTKERR: Bus fault on unstacking for a return from exception */
-#define SCB_CFSR_UNSTKERR (1 << 11)
-/* IMPRECISERR: Imprecise data bus error */
-#define SCB_CFSR_IMPRECISERR (1 << 10)
-/* PRECISERR: Precise data bus error */
-#define SCB_CFSR_PRECISERR (1 << 9)
-/* IBUSERR: Instruction bus error */
-#define SCB_CFSR_IBUSERR (1 << 8)
-/* MMARVALID: Memory Management Fault Address Register (MMAR) valid flag */
-#define SCB_CFSR_MMARVALID (1 << 7)
-/* Bits [6:5]: reserved - must be kept cleared */
-/* MSTKERR: Memory manager fault on stacking for exception entry */
-#define SCB_CFSR_MSTKERR (1 << 4)
-/* MUNSTKERR: Memory manager fault on unstacking for a return from exception */
-#define SCB_CFSR_MUNSTKERR (1 << 3)
-/* Bit 2: reserved - must be kept cleared */
-/* DACCVIOL: Data access violation flag */
-#define SCB_CFSR_DACCVIOL (1 << 1)
-/* IACCVIOL: Instruction access violation flag */
-#define SCB_CFSR_IACCVIOL (1 << 0)
-
-/* --- SCB_HFSR values ----------------------------------------------------- */
-
-/* DEBUG_VT: reserved for debug use */
-#define SCB_HFSR_DEBUG_VT (1 << 31)
-/* FORCED: Forced hard fault */
-#define SCB_HFSR_FORCED (1 << 30)
-/* Bits [29:2]: reserved - must be kept cleared */
-/* VECTTBL: Vector table hard fault */
-#define SCB_HFSR_VECTTBL (1 << 1)
-/* Bit 0: reserved - must be kept cleared */
-
-/* --- SCB_MMFAR values ---------------------------------------------------- */
-
-/* MMFAR [31:0]: Memory management fault address */
-
-/* --- SCB_BFAR values ----------------------------------------------------- */
-
-/* BFAR [31:0]: Bus fault address */
-
-/* --- SCB functions ------------------------------------------------------- */
-
-BEGIN_DECLS
-
-void scb_reset_core(void);
-void scb_reset_system(void);
-void scb_set_priority_grouping(u32 prigroup);
-
-/* TODO: */
-
-END_DECLS
-
-#endif
diff --git a/include/libopencm3/stm32/f2/spi.h b/include/libopencm3/stm32/f2/spi.h
index df5021c..c1a5f45 100644
--- a/include/libopencm3/stm32/f2/spi.h
+++ b/include/libopencm3/stm32/f2/spi.h
@@ -1,8 +1,21 @@
+/** @defgroup spi_defines SPI Defines
+
+@brief <b>Defined Constants and Types for the STM32F2xx SPI</b>
+
+@ingroup STM32F2xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 5 December 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
/*
* This file is part of the libopencm3 project.
*
- * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
- *
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
@@ -17,27 +30,11 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
-#ifndef LIBOPENCM3_SPI_F2_H
-#define LIBOPENCM3_SPI_F2_H
+#ifndef LIBOPENCM3_SPI_H
+#define LIBOPENCM3_SPI_H
-#include <libopencm3/stm32/spi.h>
-
-/*
- * This file extends the common STM32 version with definitions only
- * applicable to the STM32F2 series of devices.
- */
-
-/* --- SPI_CR2 values ------------------------------------------------------ */
-
-/* FRF: Frame format */
-/* Note: Not used in I2S mode. */
-#define SPI_CR2_FRF (1 << 4)
-#define SPI_CR2_FRF_MOTOROLA_MODE (0 << 4)
-#define SPI_CR2_FRF_TI_MODE (1 << 4)
-
-/* --- SPI_SR values ------------------------------------------------------- */
-
-/* TIFRFE: TI frame format error */
-#define SPI_SR_TIFRFE (1 << 8)
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/spi_common_f24.h>
#endif
+
diff --git a/include/libopencm3/stm32/f2/usart.h b/include/libopencm3/stm32/f2/usart.h
index 1c007ab..31314bc 100644
--- a/include/libopencm3/stm32/f2/usart.h
+++ b/include/libopencm3/stm32/f2/usart.h
@@ -1,9 +1,21 @@
+/** @defgroup usart_defines USART Defines
+
+@brief <b>Defined Constants and Types for the STM32F2xx USART</b>
+
+@ingroup STM32F2xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 5 December 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
/*
* This file is part of the libopencm3 project.
*
- * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
- * Copyright (C) 2011 Stephen Caudle <scaudle@doceme.com>
- *
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
@@ -18,46 +30,11 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
-#ifndef LIBOPENCM3_USART_F2_H
-#define LIBOPENCM3_USART_F2_H
-
-#include <libopencm3/stm32/usart.h>
-
-/* --- Convenience macros -------------------------------------------------- */
-
-#define USART6 USART6_BASE
+#ifndef LIBOPENCM3_USART_H
+#define LIBOPENCM3_USART_H
-/* --- USART registers ----------------------------------------------------- */
-
-/* Status register (USARTx_SR) */
-#define USART6_SR USART_SR(USART6_BASE)
-
-/* Data register (USARTx_DR) */
-#define USART6_DR USART_DR(USART6_BASE)
-
-/* Baud rate register (USARTx_BRR) */
-#define USART6_BRR USART_BRR(USART6_BASE)
-
-/* Control register 1 (USARTx_CR1) */
-#define USART6_CR1 USART_CR1(USART6_BASE)
-
-/* Control register 2 (USARTx_CR2) */
-#define USART6_CR2 USART_CR2(USART6_BASE)
-
-/* Control register 3 (USARTx_CR3) */
-#define USART6_CR3 USART_CR3(USART6_BASE)
-
-/* Guard time and prescaler register (USARTx_GTPR) */
-#define USART6_GTPR USART_GTPR(USART6_BASE)
-
-/* --- USART_CR1 values ---------------------------------------------------- */
-
-/* OVER8: Oversampling mode */
-#define USART_CR1_OVER8 (1 << 15)
-
-/* --- USART_CR3 values ---------------------------------------------------- */
-
-/* ONEBIT: One sample bit method enable */
-#define USART_CR3_ONEBIT (1 << 11)
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/usart_common_f24.h>
#endif
+
diff --git a/include/libopencm3/stm32/f4/adc.h b/include/libopencm3/stm32/f4/adc.h
new file mode 100644
index 0000000..e400591
--- /dev/null
+++ b/include/libopencm3/stm32/f4/adc.h
@@ -0,0 +1,873 @@
+/** @defgroup STM32F4xx_adc_defines ADC Defines
+
+@brief <b>Defined Constants and Types for the STM32F4xx Analog to Digital Converters</b>
+
+@ingroup STM32F4xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2012 Matthew Lai <m@matthewlai.ca>
+@author @htmlonly &copy; @endhtmlonly 2009 Edward Cheeseman <evbuilder@users.sourceforge.net>
+
+@date 31 August 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Matthew Lai <m@matthewlai.ca>
+ * Copyright (C) 2009 Edward Cheeseman <evbuilder@users.sourceforge.net>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_ADC_H
+#define LIBOPENCM3_ADC_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/* --- Convenience macros -------------------------------------------------- */
+
+/* ADC port base addresses (for convenience) */
+/****************************************************************************/
+/** @defgroup adc_reg_base ADC register base addresses
+@ingroup STM32F4xx_adc_defines
+
+@{*/
+#define ADC1 ADC1_BASE
+#define ADC2 ADC2_BASE
+#define ADC3 ADC3_BASE
+/**@}*/
+
+/* --- ADC registers ------------------------------------------------------- */
+
+/* ADC status register (ADC_SR) */
+#define ADC_SR(block) MMIO32(block + 0x00)
+#define ADC1_SR ADC_SR(ADC1)
+#define ADC2_SR ADC_SR(ADC2)
+#define ADC3_SR ADC_SR(ADC3)
+
+/* ADC control register 1 (ADC_CR1) */
+#define ADC_CR1(block) MMIO32(block + 0x04)
+#define ADC1_CR1 ADC_CR1(ADC1)
+#define ADC2_CR1 ADC_CR1(ADC2)
+#define ADC3_CR1 ADC_CR1(ADC3)
+
+/* ADC control register 2 (ADC_CR2) */
+#define ADC_CR2(block) MMIO32(block + 0x08)
+#define ADC1_CR2 ADC_CR2(ADC1)
+#define ADC2_CR2 ADC_CR2(ADC2)
+#define ADC3_CR2 ADC_CR2(ADC3)
+
+/* ADC sample time register 1 (ADC_SMPR1) */
+#define ADC_SMPR1(block) MMIO32(block + 0x0c)
+#define ADC1_SMPR1 ADC_SMPR1(ADC1)
+#define ADC2_SMPR1 ADC_SMPR1(ADC2)
+#define ADC3_SMPR1 ADC_SMPR1(ADC3)
+
+/* ADC sample time register 2 (ADC_SMPR2) */
+#define ADC_SMPR2(block) MMIO32(block + 0x10)
+#define ADC1_SMPR2 ADC_SMPR2(ADC1)
+#define ADC2_SMPR2 ADC_SMPR2(ADC2)
+#define ADC3_SMPR2 ADC_SMPR2(ADC3)
+
+/* ADC injected channel data offset register x (ADC_JOFRx) (x=1..4) */
+#define ADC_JOFR1(block) MMIO32(block + 0x14)
+#define ADC_JOFR2(block) MMIO32(block + 0x18)
+#define ADC_JOFR3(block) MMIO32(block + 0x1c)
+#define ADC_JOFR4(block) MMIO32(block + 0x20)
+#define ADC1_JOFR1 ADC_JOFR1(ADC1)
+#define ADC2_JOFR1 ADC_JOFR1(ADC2)
+#define ADC3_JOFR1 ADC_JOFR1(ADC3)
+#define ADC1_JOFR2 ADC_JOFR2(ADC1)
+#define ADC2_JOFR2 ADC_JOFR2(ADC2)
+#define ADC3_JOFR2 ADC_JOFR2(ADC3)
+#define ADC1_JOFR3 ADC_JOFR3(ADC1)
+#define ADC2_JOFR3 ADC_JOFR3(ADC2)
+#define ADC3_JOFR3 ADC_JOFR3(ADC3)
+#define ADC1_JOFR4 ADC_JOFR4(ADC1)
+#define ADC2_JOFR4 ADC_JOFR4(ADC2)
+#define ADC3_JOFR4 ADC_JOFR4(ADC3)
+
+/* ADC watchdog high threshold register (ADC_HTR) */
+#define ADC_HTR(block) MMIO32(block + 0x24)
+#define ADC1_HTR ADC_HTR(ADC1)
+#define ADC2_HTR ADC_HTR(ADC2)
+#define ADC3_HTR ADC_HTR(ADC3)
+
+/* ADC watchdog low threshold register (ADC_LTR) */
+#define ADC_LTR(block) MMIO32(block + 0x28)
+#define ADC1_LTR ADC_LTR(ADC1_BASE)
+#define ADC2_LTR ADC_LTR(ADC2_BASE)
+#define ADC3_LTR ADC_LTR(ADC3_BASE)
+
+/* ADC regular sequence register 1 (ADC_SQR1) */
+#define ADC_SQR1(block) MMIO32(block + 0x2c)
+#define ADC1_SQR1 ADC_SQR1(ADC1)
+#define ADC2_SQR1 ADC_SQR1(ADC2)
+#define ADC3_SQR1 ADC_SQR1(ADC3)
+
+/* ADC regular sequence register 2 (ADC_SQR2) */
+#define ADC_SQR2(block) MMIO32(block + 0x30)
+#define ADC1_SQR2 ADC_SQR2(ADC1)
+#define ADC2_SQR2 ADC_SQR2(ADC2)
+#define ADC3_SQR2 ADC_SQR2(ADC3)
+
+/* ADC regular sequence register 3 (ADC_SQR3) */
+#define ADC_SQR3(block) MMIO32(block + 0x34)
+#define ADC1_SQR3 ADC_SQR3(ADC1)
+#define ADC2_SQR3 ADC_SQR3(ADC2)
+#define ADC3_SQR3 ADC_SQR3(ADC3)
+
+/* ADC injected sequence register (ADC_JSQR) */
+#define ADC_JSQR(block) MMIO32(block + 0x38)
+#define ADC1_JSQR ADC_JSQR(ADC1_BASE)
+#define ADC2_JSQR ADC_JSQR(ADC2_BASE)
+#define ADC3_JSQR ADC_JSQR(ADC3_BASE)
+
+/* ADC injected data register x (ADC_JDRx) (x=1..4) */
+#define ADC_JDR1(block) MMIO32(block + 0x3c)
+#define ADC_JDR2(block) MMIO32(block + 0x40)
+#define ADC_JDR3(block) MMIO32(block + 0x44)
+#define ADC_JDR4(block) MMIO32(block + 0x48)
+#define ADC1_JDR1 ADC_JDR1(ADC1)
+#define ADC2_JDR1 ADC_JDR1(ADC2)
+#define ADC3_JDR1 ADC_JDR1(ADC3)
+#define ADC1_JDR2 ADC_JDR2(ADC1)
+#define ADC2_JDR2 ADC_JDR2(ADC2)
+#define ADC3_JDR2 ADC_JDR2(ADC3)
+#define ADC1_JDR3 ADC_JDR3(ADC1)
+#define ADC2_JDR3 ADC_JDR3(ADC2)
+#define ADC3_JDR3 ADC_JDR3(ADC3)
+#define ADC1_JDR4 ADC_JDR4(ADC1)
+#define ADC2_JDR4 ADC_JDR4(ADC2)
+#define ADC3_JDR4 ADC_JDR4(ADC3)
+
+/* ADC regular data register (ADC_DR) */
+#define ADC_DR(block) MMIO32(block + 0x4c)
+#define ADC1_DR ADC_DR(ADC1)
+#define ADC2_DR ADC_DR(ADC2)
+#define ADC3_DR ADC_DR(ADC3)
+
+/* ADC common (shared) registers */
+#define ADC_COMMON_REGISTERS_BASE (ADC1_BASE+0x300)
+#define ADC_CSR MMIO32(ADC_COMMON_REGISTERS_BASE + 0x0)
+#define ADC_CCR MMIO32(ADC_COMMON_REGISTERS_BASE + 0x4)
+#define ADC_CDR MMIO32(ADC_COMMON_REGISTERS_BASE + 0x8)
+
+/* --- ADC Channels ------------------------------------------------------- */
+
+/****************************************************************************/
+/** @defgroup adc_channel ADC Channel Numbers
+@ingroup STM32F4xx_adc_defines
+
+@{*/
+#define ADC_CHANNEL0 0x00
+#define ADC_CHANNEL1 0x01
+#define ADC_CHANNEL2 0x02
+#define ADC_CHANNEL3 0x03
+#define ADC_CHANNEL4 0x04
+#define ADC_CHANNEL5 0x05
+#define ADC_CHANNEL6 0x06
+#define ADC_CHANNEL7 0x07
+#define ADC_CHANNEL8 0x08
+#define ADC_CHANNEL9 0x09
+#define ADC_CHANNEL10 0x0A
+#define ADC_CHANNEL11 0x0B
+#define ADC_CHANNEL12 0x0C
+#define ADC_CHANNEL13 0x0D
+#define ADC_CHANNEL14 0x0E
+#define ADC_CHANNEL15 0x0F
+#define ADC_CHANNEL16 0x10
+#define ADC_CHANNEL17 0x11
+#define ADC_CHANNEL18 0x12
+/**@}*/
+#define ADC_MASK 0x1F
+#define ADC_SHIFT 0
+
+/* --- ADC_SR values ------------------------------------------------------- */
+
+#define ADC_SR_OVR (1 << 5)
+#define ADC_SR_STRT (1 << 4)
+#define ADC_SR_JSTRT (1 << 3)
+#define ADC_SR_JEOC (1 << 2)
+#define ADC_SR_EOC (1 << 1)
+#define ADC_SR_AWD (1 << 0)
+
+/* --- ADC_CR1 values specific to STM32F2,4------------------------------------ */
+
+/* OVRIE: Overrun interrupt enable */
+#define ADC_CR1_OVRIE (1 << 26)
+
+/* RES[1:0]: Resolution */
+/****************************************************************************/
+/** @defgroup adc_cr1_res ADC Resolution.
+@ingroup STM32F4xx_adc_defines
+
+@{*/
+#define ADC_CR1_RES_12BIT (0x0 << 24)
+#define ADC_CR1_RES_10BIT (0x1 << 24)
+#define ADC_CR1_RES_8BIT (0x2 << 24)
+#define ADC_CR1_RES_6BIT (0x3 << 24)
+/**@}*/
+#define ADC_CR1_RES_MASK (0x3 << 24)
+#define ADC_CR1_RES_SHIFT 24
+
+/* Note: Bits [21:16] are reserved, and must be kept at reset value. */
+
+/* --- ADC_CR1 values (note some of these are defined elsewhere) ----------- */
+
+/* AWDEN: Analog watchdog enable on regular channels */
+#define ADC_CR1_AWDEN (1 << 23)
+
+/* JAWDEN: Analog watchdog enable on injected channels */
+#define ADC_CR1_JAWDEN (1 << 22)
+
+/* DISCNUM[2:0]: Discontinuous mode channel count. */
+/****************************************************************************/
+/** @defgroup adc_cr1_discnum ADC Number of channels in discontinuous mode.
+@ingroup STM32F4xx_adc_defines
+
+@{*/
+#define ADC_CR1_DISCNUM_1CHANNELS (0x0 << 13)
+#define ADC_CR1_DISCNUM_2CHANNELS (0x1 << 13)
+#define ADC_CR1_DISCNUM_3CHANNELS (0x2 << 13)
+#define ADC_CR1_DISCNUM_4CHANNELS (0x3 << 13)
+#define ADC_CR1_DISCNUM_5CHANNELS (0x4 << 13)
+#define ADC_CR1_DISCNUM_6CHANNELS (0x5 << 13)
+#define ADC_CR1_DISCNUM_7CHANNELS (0x6 << 13)
+#define ADC_CR1_DISCNUM_8CHANNELS (0x7 << 13)
+/**@}*/
+#define ADC_CR1_DISCNUM_MASK (0x7 << 13)
+#define ADC_CR1_DISCNUM_SHIFT 13
+
+/* JDISCEN: */ /** Discontinuous mode on injected channels. */
+#define ADC_CR1_JDISCEN (1 << 12)
+
+/* DISCEN: */ /** Discontinuous mode on regular channels. */
+#define ADC_CR1_DISCEN (1 << 11)
+
+/* JAUTO: */ /** Automatic Injection Group conversion. */
+#define ADC_CR1_JAUTO (1 << 10)
+
+/* AWDSGL: */ /** Enable the watchdog on a single channel in scan mode. */
+#define ADC_CR1_AWDSGL (1 << 9)
+
+/* SCAN: */ /** Scan mode. */
+#define ADC_CR1_SCAN (1 << 8)
+
+/* JEOCIE: */ /** Interrupt enable for injected channels. */
+#define ADC_CR1_JEOCIE (1 << 7)
+
+/* AWDIE: */ /** Analog watchdog interrupt enable. */
+#define ADC_CR1_AWDIE (1 << 6)
+
+/* EOCIE: */ /** Interrupt enable EOC. */
+#define ADC_CR1_EOCIE (1 << 5)
+
+/* AWDCH[4:0]: Analog watchdog channel bits. (Up to 17 other values reserved) */
+/* Notes:
+ * ADC1: Analog channel 16 and 17 are internally connected to the temperature
+ * sensor and V_REFINT, respectively.
+ * ADC2: Analog channel 16 and 17 are internally connected to V_SS.
+ * ADC3: Analog channel 9, 14, 15, 16 and 17 are internally connected to V_SS.
+ */
+/****************************************************************************/
+/* ADC_CR1 AWDCH[4:0] ADC watchdog channel */
+/** @defgroup adc_watchdog_channel ADC watchdog channel
+@ingroup STM32F4xx_adc_defines
+
+@{*/
+#define ADC_CR1_AWDCH_CHANNEL0 (0x00 << 0)
+#define ADC_CR1_AWDCH_CHANNEL1 (0x01 << 0)
+#define ADC_CR1_AWDCH_CHANNEL2 (0x02 << 0)
+#define ADC_CR1_AWDCH_CHANNEL3 (0x03 << 0)
+#define ADC_CR1_AWDCH_CHANNEL4 (0x04 << 0)
+#define ADC_CR1_AWDCH_CHANNEL5 (0x05 << 0)
+#define ADC_CR1_AWDCH_CHANNEL6 (0x06 << 0)
+#define ADC_CR1_AWDCH_CHANNEL7 (0x07 << 0)
+#define ADC_CR1_AWDCH_CHANNEL8 (0x08 << 0)
+#define ADC_CR1_AWDCH_CHANNEL9 (0x09 << 0)
+#define ADC_CR1_AWDCH_CHANNEL10 (0x0A << 0)
+#define ADC_CR1_AWDCH_CHANNEL11 (0x0B << 0)
+#define ADC_CR1_AWDCH_CHANNEL12 (0x0C << 0)
+#define ADC_CR1_AWDCH_CHANNEL13 (0x0D << 0)
+#define ADC_CR1_AWDCH_CHANNEL14 (0x0E << 0)
+#define ADC_CR1_AWDCH_CHANNEL15 (0x0F << 0)
+#define ADC_CR1_AWDCH_CHANNEL16 (0x10 << 0)
+#define ADC_CR1_AWDCH_CHANNEL17 (0x11 << 0)
+/**@}*/
+#define ADC_CR1_AWDCH_MASK (0x1F << 0)
+#define ADC_CR1_AWDCH_SHIFT 0
+
+/* --- ADC_CR2 values ------------------------------------------------------ */
+
+/* SWSTART: Start conversion of regular channels. */
+#define ADC_CR2_SWSTART (1 << 30)
+
+/* EXTEN[1:0]: External trigger enable for regular channels. */
+/****************************************************************************/
+/** @defgroup adc_trigger_polarity_regular ADC Trigger Polarity
+@ingroup STM32F4xx_adc_defines
+
+@{*/
+#define ADC_CR2_EXTEN_DISABLED (0x0 << 28)
+#define ADC_CR2_EXTEN_RISING_EDGE (0x1 << 28)
+#define ADC_CR2_EXTEN_FALLING_EDGE (0x2 << 28)
+#define ADC_CR2_EXTEN_BOTH_EDGES (0x3 << 28)
+/**@}*/
+#define ADC_CR2_EXTEN_MASK (0x3 << 28)
+#define ADC_CR2_EXTEN_SHIFT 28
+
+/* EXTSEL[3:0]: External event selection for regular group. */
+/****************************************************************************/
+/** @defgroup adc_trigger_regular ADC Trigger Identifier for Regular group
+@ingroup STM32F4xx_adc_defines
+
+@{*/
+/** Timer 1 Compare Output 1 */
+#define ADC_CR2_EXTSEL_TIM1_CC1 (0x0 << 24)
+/** Timer 1 Compare Output 2 */
+#define ADC_CR2_EXTSEL_TIM1_CC2 (0x1 << 24)
+/** Timer 1 Compare Output 3 */
+#define ADC_CR2_EXTSEL_TIM1_CC3 (0x2 << 24)
+/** Timer 2 Compare Output 2 */
+#define ADC_CR2_EXTSEL_TIM2_CC2 (0x3 << 24)
+/** Timer 2 Compare Output 3 */
+#define ADC_CR2_EXTSEL_TIM2_CC3 (0x4 << 24)
+/** Timer 2 Compare Output 4 */
+#define ADC_CR2_EXTSEL_TIM2_CC4 (0x5 << 24)
+/** Timer 2 TRGO Event */
+#define ADC_CR2_EXTSEL_TIM2_TRGO (0x6 << 24)
+/** Timer 3 Compare Output 1 */
+#define ADC_CR2_EXTSEL_TIM3_CC1 (0x7 << 24)
+/** Timer 3 TRGO Event */
+#define ADC_CR2_EXTSEL_TIM3_TRGO (0x8 << 24)
+/** Timer 4 Compare Output 4 */
+#define ADC_CR2_EXTSEL_TIM4_CC4 (0x9 << 24)
+/** Timer 5 Compare Output 1 */
+#define ADC_CR2_EXTSEL_TIM5_CC1 (0xA << 24)
+/** Timer 5 Compare Output 2 */
+#define ADC_CR2_EXTSEL_TIM5_CC2 (0xB << 24)
+/** Timer 5 Compare Output 3 */
+#define ADC_CR2_EXTSEL_TIM5_CC3 (0xC << 24)
+/** Timer 8 Compare Output 1 */
+#define ADC_CR2_EXTSEL_TIM8_CC1 (0xD << 24)
+/** Timer 8 TRGO Event */
+#define ADC_CR2_EXTSEL_TIM8_TRGO (0xE << 24)
+/** EXTI Line 11 Event */
+#define ADC_CR2_EXTSEL_EXTI_LINE_11 (0xF << 24)
+/**@}*/
+#define ADC_CR2_EXTSEL_MASK (0xF << 24)
+#define ADC_CR2_EXTSEL_SHIFT 24
+
+/* Bit 23 is reserved */
+
+/* JSWSTART: Start conversion of injected channels. */
+#define ADC_CR2_JSWSTART (1 << 22)
+
+/* JEXTEN[1:0]: External trigger enable for injected channels. */
+/****************************************************************************/
+/** @defgroup adc_trigger_polarity_injected ADC Injected Trigger Polarity
+@ingroup STM32F4xx_adc_defines
+
+@{*/
+#define ADC_CR2_JEXTEN_DISABLED (0x0 << 20)
+#define ADC_CR2_JEXTEN_RISING_EDGE (0x1 << 20)
+#define ADC_CR2_JEXTEN_FALLING_EDGE (0x2 << 20)
+#define ADC_CR2_JEXTEN_BOTH_EDGES (0x3 << 20)
+/**@}*/
+#define ADC_CR2_JEXTEN_MASK (0x3 << 20)
+#define ADC_CR2_JEXTEN_SHIFT 20
+
+/* JEXTSEL[3:0]: External event selection for injected group. */
+/****************************************************************************/
+/** @defgroup adc_trigger_injected ADC Trigger Identifier for Injected group
+@ingroup STM32F4xx_adc_defines
+
+@{*/
+#define ADC_CR2_JEXTSEL_TIM1_CC4 (0x0 << 16)
+#define ADC_CR2_JEXTSEL_TIM1_TRGO (0x1 << 16)
+#define ADC_CR2_JEXTSEL_TIM2_CC1 (0x2 << 16)
+#define ADC_CR2_JEXTSEL_TIM2_TRGO (0x3 << 16)
+#define ADC_CR2_JEXTSEL_TIM3_CC2 (0x4 << 16)
+#define ADC_CR2_JEXTSEL_TIM3_CC4 (0x5 << 16)
+#define ADC_CR2_JEXTSEL_TIM4_CC1 (0x6 << 16)
+#define ADC_CR2_JEXTSEL_TIM4_CC2 (0x7 << 16)
+#define ADC_CR2_JEXTSEL_TIM4_CC3 (0x8 << 16)
+#define ADC_CR2_JEXTSEL_TIM4_TRGO (0x9 << 16)
+#define ADC_CR2_JEXTSEL_TIM5_CC4 (0xA << 16)
+#define ADC_CR2_JEXTSEL_TIM5_TRGO (0xB << 16)
+#define ADC_CR2_JEXTSEL_TIM8_CC2 (0xC << 16)
+#define ADC_CR2_JEXTSEL_TIM8_CC3 (0xD << 16)
+#define ADC_CR2_JEXTSEL_TIM8_CC4 (0xE << 16)
+#define ADC_CR2_JEXTSEL_EXTI_LINE_15 (0xF << 16)
+/**@}*/
+#define ADC_CR2_JEXTSEL_MASK (0xF << 16)
+#define ADC_CR2_JEXTSEL_SHIFT 16
+
+/* ALIGN: Data alignement. */
+#define ADC_CR2_ALIGN_RIGHT (0 << 11)
+#define ADC_CR2_ALIGN_LEFT (1 << 11)
+#define ADC_CR2_ALIGN (1 << 11)
+
+/* EOCS: End of conversion selection. */
+#define ADC_CR2_EOCS (1 << 10)
+
+/* DDS: DMA disable selection */
+#define ADC_CR2_DDS (1 << 9)
+
+/* DMA: Direct memory access mode. (ADC1 and ADC3 only!) */
+#define ADC_CR2_DMA (1 << 8)
+
+/* Note: Bits [7:2] are reserved and must be kept at reset value. */
+
+/* CONT: Continous conversion. */
+#define ADC_CR2_CONT (1 << 1)
+
+/* ADON: A/D converter On/Off. */
+/* Note: If any other bit in this register apart from ADON is changed at the
+ * same time, then conversion is not triggered. This is to prevent triggering
+ * an erroneous conversion.
+ * Conclusion: Must be separately written.
+ */
+#define ADC_CR2_ADON (1 << 0)
+
+/* --- ADC_SMPR1 values ---------------------------------------------------- */
+
+#define ADC_SMPR1_SMP17_LSB 21
+#define ADC_SMPR1_SMP16_LSB 18
+#define ADC_SMPR1_SMP15_LSB 15
+#define ADC_SMPR1_SMP14_LSB 12
+#define ADC_SMPR1_SMP13_LSB 9
+#define ADC_SMPR1_SMP12_LSB 6
+#define ADC_SMPR1_SMP11_LSB 3
+#define ADC_SMPR1_SMP10_LSB 0
+#define ADC_SMPR1_SMP17_MSK (0x7 << ADC_SMP17_LSB)
+#define ADC_SMPR1_SMP16_MSK (0x7 << ADC_SMP16_LSB)
+#define ADC_SMPR1_SMP15_MSK (0x7 << ADC_SMP15_LSB)
+#define ADC_SMPR1_SMP14_MSK (0x7 << ADC_SMP14_LSB)
+#define ADC_SMPR1_SMP13_MSK (0x7 << ADC_SMP13_LSB)
+#define ADC_SMPR1_SMP12_MSK (0x7 << ADC_SMP12_LSB)
+#define ADC_SMPR1_SMP11_MSK (0x7 << ADC_SMP11_LSB)
+#define ADC_SMPR1_SMP10_MSK (0x7 << ADC_SMP10_LSB)
+/****************************************************************************/
+/* ADC_SMPR1 ADC Sample Time Selection for Channels */
+/** @defgroup adc_sample_r1 ADC Sample Time Selection for ADC1
+@ingroup STM32F4xx_adc_defines
+
+@{*/
+#define ADC_SMPR1_SMP_1DOT5CYC 0x0
+#define ADC_SMPR1_SMP_7DOT5CYC 0x1
+#define ADC_SMPR1_SMP_13DOT5CYC 0x2
+#define ADC_SMPR1_SMP_28DOT5CYC 0x3
+#define ADC_SMPR1_SMP_41DOT5CYC 0x4
+#define ADC_SMPR1_SMP_55DOT5CYC 0x5
+#define ADC_SMPR1_SMP_71DOT5CYC 0x6
+#define ADC_SMPR1_SMP_239DOT5CYC 0x7
+/**@}*/
+
+/* --- ADC_SMPR2 values ---------------------------------------------------- */
+
+#define ADC_SMPR2_SMP9_LSB 27
+#define ADC_SMPR2_SMP8_LSB 24
+#define ADC_SMPR2_SMP7_LSB 21
+#define ADC_SMPR2_SMP6_LSB 18
+#define ADC_SMPR2_SMP5_LSB 15
+#define ADC_SMPR2_SMP4_LSB 12
+#define ADC_SMPR2_SMP3_LSB 9
+#define ADC_SMPR2_SMP2_LSB 6
+#define ADC_SMPR2_SMP1_LSB 3
+#define ADC_SMPR2_SMP0_LSB 0
+#define ADC_SMPR2_SMP9_MSK (0x7 << ADC_SMP9_LSB)
+#define ADC_SMPR2_SMP8_MSK (0x7 << ADC_SMP8_LSB)
+#define ADC_SMPR2_SMP7_MSK (0x7 << ADC_SMP7_LSB)
+#define ADC_SMPR2_SMP6_MSK (0x7 << ADC_SMP6_LSB)
+#define ADC_SMPR2_SMP5_MSK (0x7 << ADC_SMP5_LSB)
+#define ADC_SMPR2_SMP4_MSK (0x7 << ADC_SMP4_LSB)
+#define ADC_SMPR2_SMP3_MSK (0x7 << ADC_SMP3_LSB)
+#define ADC_SMPR2_SMP2_MSK (0x7 << ADC_SMP2_LSB)
+#define ADC_SMPR2_SMP1_MSK (0x7 << ADC_SMP1_LSB)
+#define ADC_SMPR2_SMP0_MSK (0x7 << ADC_SMP0_LSB)
+/****************************************************************************/
+/* ADC_SMPR2 ADC Sample Time Selection for Channels */
+/** @defgroup adc_sample_r2 ADC Sample Time Selection for ADC2
+@ingroup STM32F4xx_adc_defines
+
+@{*/
+#define ADC_SMPR2_SMP_1DOT5CYC 0x0
+#define ADC_SMPR2_SMP_7DOT5CYC 0x1
+#define ADC_SMPR2_SMP_13DOT5CYC 0x2
+#define ADC_SMPR2_SMP_28DOT5CYC 0x3
+#define ADC_SMPR2_SMP_41DOT5CYC 0x4
+#define ADC_SMPR2_SMP_55DOT5CYC 0x5
+#define ADC_SMPR2_SMP_71DOT5CYC 0x6
+#define ADC_SMPR2_SMP_239DOT5CYC 0x7
+/**@}*/
+
+/* --- ADC_SMPRx generic values -------------------------------------------- */
+/****************************************************************************/
+/* ADC_SMPRG ADC Sample Time Selection for Channels */
+/** @defgroup adc_sample_rg ADC Sample Time Selection for All Channels
+@ingroup STM32F4xx_adc_defines
+
+@{*/
+#define ADC_SMPR_SMP_1DOT5CYC 0x0
+#define ADC_SMPR_SMP_7DOT5CYC 0x1
+#define ADC_SMPR_SMP_13DOT5CYC 0x2
+#define ADC_SMPR_SMP_28DOT5CYC 0x3
+#define ADC_SMPR_SMP_41DOT5CYC 0x4
+#define ADC_SMPR_SMP_55DOT5CYC 0x5
+#define ADC_SMPR_SMP_71DOT5CYC 0x6
+#define ADC_SMPR_SMP_239DOT5CYC 0x7
+/**@}*/
+
+/* --- ADC_JOFRx, ADC_HTR, ADC_LTR values ---------------------------------- */
+
+#define ADC_JOFFSET_LSB 0
+#define ADC_JOFFSET_MSK (0x7ff << 0)
+#define ADC_HT_LSB 0
+#define ADC_HT_MSK (0x7ff << 0)
+#define ADC_LT_LSB 0
+#define ADC_LT_MSK (0x7ff << 0)
+
+/* --- ADC_SQR1 values ----------------------------------------------------- */
+
+#define ADC_SQR1_L_LSB 20
+#define ADC_SQR1_SQ16_LSB 15
+#define ADC_SQR1_SQ15_LSB 10
+#define ADC_SQR1_SQ14_LSB 5
+#define ADC_SQR1_SQ13_LSB 0
+#define ADC_SQR1_L_MSK (0xf << ADC_SQR1_L_LSB)
+#define ADC_SQR1_SQ16_MSK (0x1f << ADC_SQR1_SQ16_LSB)
+#define ADC_SQR1_SQ15_MSK (0x1f << ADC_SQR1_SQ15_LSB)
+#define ADC_SQR1_SQ14_MSK (0x1f << ADC_SQR1_SQ14_LSB)
+#define ADC_SQR1_SQ13_MSK (0x1f << ADC_SQR1_SQ13_LSB)
+
+/* --- ADC_SQR2 values ----------------------------------------------------- */
+
+#define ADC_SQR2_SQ12_LSB 25
+#define ADC_SQR2_SQ11_LSB 20
+#define ADC_SQR2_SQ10_LSB 15
+#define ADC_SQR2_SQ9_LSB 10
+#define ADC_SQR2_SQ8_LSB 5
+#define ADC_SQR2_SQ7_LSB 0
+#define ADC_SQR2_SQ12_MSK (0x1f << ADC_SQR2_SQ12_LSB)
+#define ADC_SQR2_SQ11_MSK (0x1f << ADC_SQR2_SQ11_LSB)
+#define ADC_SQR2_SQ10_MSK (0x1f << ADC_SQR2_SQ10_LSB)
+#define ADC_SQR2_SQ9_MSK (0x1f << ADC_SQR2_SQ9_LSB)
+#define ADC_SQR2_SQ8_MSK (0x1f << ADC_SQR2_SQ8_LSB)
+#define ADC_SQR2_SQ7_MSK (0x1f << ADC_SQR2_SQ7_LSB)
+
+/* --- ADC_SQR3 values ----------------------------------------------------- */
+
+#define ADC_SQR3_SQ6_LSB 25
+#define ADC_SQR3_SQ5_LSB 20
+#define ADC_SQR3_SQ4_LSB 15
+#define ADC_SQR3_SQ3_LSB 10
+#define ADC_SQR3_SQ2_LSB 5
+#define ADC_SQR3_SQ1_LSB 0
+#define ADC_SQR3_SQ6_MSK (0x1f << ADC_SQR3_SQ6_LSB)
+#define ADC_SQR3_SQ5_MSK (0x1f << ADC_SQR3_SQ5_LSB)
+#define ADC_SQR3_SQ4_MSK (0x1f << ADC_SQR3_SQ4_LSB)
+#define ADC_SQR3_SQ3_MSK (0x1f << ADC_SQR3_SQ3_LSB)
+#define ADC_SQR3_SQ2_MSK (0x1f << ADC_SQR3_SQ2_LSB)
+#define ADC_SQR3_SQ1_MSK (0x1f << ADC_SQR3_SQ1_LSB)
+
+/* --- ADC_JSQR values ----------------------------------------------------- */
+
+#define ADC_JSQR_JL_LSB 20
+#define ADC_JSQR_JSQ4_LSB 15
+#define ADC_JSQR_JSQ3_LSB 10
+#define ADC_JSQR_JSQ2_LSB 5
+#define ADC_JSQR_JSQ1_LSB 0
+
+/* JL[2:0]: Discontinous mode channel count injected channels. */
+/****************************************************************************/
+/** @defgroup adc_jsqr_jl ADC Number of channels in discontinuous mode fro injected channels.
+@ingroup STM32F4xx_adc_defines
+
+@{*/
+#define ADC_JSQR_JL_1CHANNELS (0x0 << ADC_JSQR_JL_LSB)
+#define ADC_JSQR_JL_2CHANNELS (0x1 << ADC_JSQR_JL_LSB)
+#define ADC_JSQR_JL_3CHANNELS (0x2 << ADC_JSQR_JL_LSB)
+#define ADC_JSQR_JL_4CHANNELS (0x3 << ADC_JSQR_JL_LSB)
+/**@}*/
+#define ADC_JSQR_JL_SHIFT 13
+#define ADC_JSQR_JL_MSK (0x2 << ADC_JSQR_JL_LSB)
+#define ADC_JSQR_JSQ4_MSK (0x1f << ADC_JSQR_JSQ4_LSB)
+#define ADC_JSQR_JSQ3_MSK (0x1f << ADC_JSQR_JSQ3_LSB)
+#define ADC_JSQR_JSQ2_MSK (0x1f << ADC_JSQR_JSQ2_LSB)
+#define ADC_JSQR_JSQ1_MSK (0x1f << ADC_JSQR_JSQ1_LSB)
+
+/* --- ADC_JDRx, ADC_DR values --------------------------------------------- */
+
+#define ADC_JDATA_LSB 0
+#define ADC_DATA_LSB 0
+#define ADC_JDATA_MSK (0xffff << ADC_JDATA_LSB)
+#define ADC_DATA_MSK (0xffff << ADC_DA)
+
+/* --- Common Registers ---------------------------------------------------- */
+
+/* --- ADC_CSR values (read only images) ------------------------------------ */
+
+/* OVR3: Overrun ADC3. */
+#define ADC_CSR_OVR3 (1 << 21)
+
+/* STRT3: Regular channel start ADC3. */
+#define ADC_CSR_STRT3 (1 << 20)
+
+/* JSTRT3: Injected channel start ADC3. */
+#define ADC_CSR_JSTRT3 (1 << 19)
+
+/* JEOC3: Injected channel end of conversion ADC3. */
+#define ADC_CSR_JEOC3 (1 << 18)
+
+/* EOC3: Regular channel end of conversion ADC3. */
+#define ADC_CSR_EOC3 (1 << 17)
+
+/* EOC3: Regular channel end of conversion ADC3. */
+#define ADC_CSR_AWD3 (1 << 16)
+
+/* Bits 15:14 Reserved, must be kept at reset value */
+
+/* OVR2: Overrun ADC2. */
+#define ADC_CSR_OVR2 (1 << 13)
+
+/* STRT2: Regular channel start ADC2. */
+#define ADC_CSR_STRT2 (1 << 12)
+
+/* JSTRT2: Injected channel start ADC2. */
+#define ADC_CSR_JSTRT2 (1 << 11)
+
+/* JEOC2: Injected channel end of conversion ADC2. */
+#define ADC_CSR_JEOC2 (1 << 10)
+
+/* EOC2: Regular channel end of conversion ADC2. */
+#define ADC_CSR_EOC2 (1 << 9)
+
+/* EOC2: Regular channel end of conversion ADC2. */
+#define ADC_CSR_AWD2 (1 << 8)
+
+/* Bits 7:6 Reserved, must be kept at reset value */
+
+/* OVR1: Overrun ADC1. */
+#define ADC_CSR_OVR1 (1 << 5)
+
+/* STRT1: Regular channel start ADC1. */
+#define ADC_CSR_STRT1 (1 << 4)
+
+/* JSTRT1: Injected channel start ADC1. */
+#define ADC_CSR_JSTRT1 (1 << 3)
+
+/* JEOC1: Injected channel end of conversion ADC1. */
+#define ADC_CSR_JEOC1 (1 << 2)
+
+/* EOC1: Regular channel end of conversion ADC1. */
+#define ADC_CSR_EOC1 (1 << 1)
+
+/* EOC1: Regular channel end of conversion ADC1. */
+#define ADC_CSR_AWD1 (1 << 0)
+
+/* --- ADC_CCR values ------------------------------------------------------ */
+
+/* TSVREFE: Temperature sensor and Vrefint enable. */
+#define ADC_CCR_TSVREFE (1 << 23)
+
+/* VBATE: VBat enable. */
+#define ADC_CCR_VBATE (1 << 22)
+
+/* Bit 18:21 reserved, must be kept at reset value. */
+
+/* ADCPRE: ADC prescaler. */
+/****************************************************************************/
+/** @defgroup adc_ccr_adcpre ADC Prescale
+@ingroup STM32F4xx_adc_defines
+
+@{*/
+#define ADC_CCR_ADCPRE_BY2 (0x0 << 16)
+#define ADC_CCR_ADCPRE_BY4 (0x1 << 16)
+#define ADC_CCR_ADCPRE_BY6 (0x2 << 16)
+#define ADC_CCR_ADCPRE_BY8 (0x3 << 16)
+/**@}*/
+#define ADC_CCR_ADCPRE_MASK (0x3 << 16)
+#define ADC_CCR_ADCPRE_SHIFT 16
+
+/* DMA: Direct memory access mode for multi ADC mode. */
+/****************************************************************************/
+/** @defgroup adc_dma_mode ADC DMA mode for multi ADC mode
+@ingroup STM32F4xx_adc_defines
+
+@{*/
+#define ADC_CCR_DMA_DISABLE (0x0 << 14)
+#define ADC_CCR_DMA_MODE_1 (0x1 << 14)
+#define ADC_CCR_DMA_MODE_2 (0x2 << 14)
+#define ADC_CCR_DMA_MODE_3 (0x3 << 14)
+/**@}*/
+#define ADC_CCR_DMA_MASK (0x3 << 14)
+#define ADC_CCR_DMA_SHIFT 14
+
+/* DDS: DMA disable selection (for multi-ADC mode). */
+#define ADC_CCR_DDS (1 << 13)
+
+/* Bit 12 reserved, must be kept at reset value */
+
+/* DELAY: Delay between 2 sampling phases. */
+/****************************************************************************/
+/** @defgroup adc_delay ADC Delay between 2 sampling phases
+@ingroup STM32F4xx_adc_defines
+
+@{*/
+#define ADC_CCR_DELAY_5ADCCLK (0x0 << 8)
+#define ADC_CCR_DELAY_6ADCCLK (0x1 << 8)
+#define ADC_CCR_DELAY_7ADCCLK (0x2 << 8)
+#define ADC_CCR_DELAY_8ADCCLK (0x3 << 8)
+#define ADC_CCR_DELAY_9ADCCLK (0x4 << 8)
+#define ADC_CCR_DELAY_10ADCCLK (0x5 << 8)
+#define ADC_CCR_DELAY_11ADCCLK (0x6 << 8)
+#define ADC_CCR_DELAY_12ADCCLK (0x7 << 8)
+#define ADC_CCR_DELAY_13ADCCLK (0x8 << 8)
+#define ADC_CCR_DELAY_14ADCCLK (0x9 << 8)
+#define ADC_CCR_DELAY_15ADCCLK (0xa << 8)
+#define ADC_CCR_DELAY_16ADCCLK (0xb << 8)
+#define ADC_CCR_DELAY_17ADCCLK (0xc << 8)
+#define ADC_CCR_DELAY_18ADCCLK (0xd << 8)
+#define ADC_CCR_DELAY_19ADCCLK (0xe << 8)
+#define ADC_CCR_DELAY_20ADCCLK (0xf << 8)
+/**@}*/
+#define ADC_CCR_DELAY_MASK (0xf << 8)
+#define ADC_CCR_DELAY_SHIFT 8
+
+/* Bit 7:5 reserved, must be kept at reset value */
+
+/* MULTI: Multi ADC mode selection. */
+/****************************************************************************/
+/** @defgroup adc_multi_mode ADC Multi mode selection
+@ingroup STM32F4xx_adc_defines
+
+@{*/
+
+/** All ADCs independent */
+#define ADC_CCR_MULTI_INDEPENDENT (0x00 << 0)
+
+/* dual modes (ADC1 + ADC2) */
+/** Dual modes (ADC1 + ADC2) Combined regular simultaneous + injected simultaneous mode */
+#define ADC_CCR_MULTI_DUAL_REG_SIMUL_AND_INJECTED_SIMUL (0x01 << 0)
+/** Dual modes (ADC1 + ADC2) Combined regular simultaneous + alternate trigger mode. */
+#define ADC_CCR_MULTI_DUAL_REG_SIMUL_AND_ALTERNATE_TRIG (0x02 << 0)
+/** Dual modes (ADC1 + ADC2) Injected simultaneous mode only. */
+#define ADC_CCR_MULTI_DUAL_INJECTED_SIMUL (0x05 << 0)
+/** Dual modes (ADC1 + ADC2) Regular simultaneous mode only. */
+#define ADC_CCR_MULTI_DUAL_REGULAR_SIMUL (0x06 << 0)
+/** Dual modes (ADC1 + ADC2) Interleaved mode only. */
+#define ADC_CCR_MULTI_DUAL_INTERLEAVED (0x07 << 0)
+/** Dual modes (ADC1 + ADC2) Alternate trigger mode only. */
+#define ADC_CCR_MULTI_DUAL_ALTERNATE_TRIG (0x09 << 0)
+
+/* Triple modes (ADC1 + ADC2 + ADC3) */
+/** Triple modes (ADC1 + ADC2 + ADC3) Combined regular simultaneous + injected simultaneous mode */
+#define ADC_CCR_MULTI_TRIPLE_REG_SIMUL_AND_INJECTED_SIMUL (0x11 << 0)
+/** Triple modes (ADC1 + ADC2 + ADC3) Combined regular simultaneous + alternate trigger mode. */
+#define ADC_CCR_MULTI_TRIPLE_REG_SIMUL_AND_ALTERNATE_TRIG (0x12 << 0)
+/** Triple modes (ADC1 + ADC2 + ADC3) Injected simultaneous mode only. */
+#define ADC_CCR_MULTI_TRIPLE_INJECTED_SIMUL (0x15 << 0)
+/** Triple modes (ADC1 + ADC2 + ADC3) Regular simultaneous mode only. */
+#define ADC_CCR_MULTI_TRIPLE_REGULAR_SIMUL (0x16 << 0)
+/** Triple modes (ADC1 + ADC2 + ADC3) Interleaved mode only. */
+#define ADC_CCR_MULTI_TRIPLE_INTERLEAVED (0x17 << 0)
+/** Triple modes (ADC1 + ADC2 + ADC3) Alternate trigger mode only. */
+#define ADC_CCR_MULTI_TRIPLE_ALTERNATE_TRIG (0x19 << 0)
+/**@}*/
+
+#define ADC_CCR_MULTI_MASK (0x1f << 0)
+#define ADC_CCR_MULTI_SHIFT 0
+
+/* --- ADC_CDR values ------------------------------------------------------ */
+
+#define ADC_CDR_DATA2_MASK (0xffff << 16)
+#define ADC_CDR_DATA2_SHIFT 16
+
+#define ADC_CDR_DATA1_MASK (0xffff << 0)
+#define ADC_CDR_DATA1_SHIFT 0
+
+BEGIN_DECLS
+
+void adc_power_on(u32 adc);
+void adc_off(u32 adc);
+void adc_enable_analog_watchdog_regular(u32 adc);
+void adc_disable_analog_watchdog_regular(u32 adc);
+void adc_enable_analog_watchdog_injected(u32 adc);
+void adc_disable_analog_watchdog_injected(u32 adc);
+void adc_enable_discontinuous_mode_regular(u32 adc, u8 length);
+void adc_disable_discontinuous_mode_regular(u32 adc);
+void adc_enable_discontinuous_mode_injected(u32 adc);
+void adc_disable_discontinuous_mode_injected(u32 adc);
+void adc_enable_automatic_injected_group_conversion(u32 adc);
+void adc_disable_automatic_injected_group_conversion(u32 adc);
+void adc_enable_analog_watchdog_on_all_channels(u32 adc);
+void adc_enable_analog_watchdog_on_selected_channel(u32 adc, u8 channel);
+void adc_enable_scan_mode(u32 adc);
+void adc_disable_scan_mode(u32 adc);
+void adc_enable_eoc_interrupt_injected(u32 adc);
+void adc_disable_eoc_interrupt_injected(u32 adc);
+void adc_enable_awd_interrupt(u32 adc);
+void adc_disable_awd_interrupt(u32 adc);
+void adc_enable_eoc_interrupt(u32 adc);
+void adc_disable_eoc_interrupt(u32 adc);
+void adc_start_conversion_regular(u32 adc);
+void adc_start_conversion_injected(u32 adc);
+void adc_disable_external_trigger_regular(u32 adc);
+void adc_disable_external_trigger_injected(u32 adc);
+void adc_set_left_aligned(u32 adc);
+void adc_set_right_aligned(u32 adc);
+void adc_enable_dma(u32 adc);
+void adc_disable_dma(u32 adc);
+void adc_set_continuous_conversion_mode(u32 adc);
+void adc_set_single_conversion_mode(u32 adc);
+void adc_set_sample_time(u32 adc, u8 channel, u8 time);
+void adc_set_sample_time_on_all_channels(u32 adc, u8 time);
+void adc_set_watchdog_high_threshold(u32 adc, u16 threshold);
+void adc_set_watchdog_low_threshold(u32 adc, u16 threshold);
+void adc_set_regular_sequence(u32 adc, u8 length, u8 channel[]);
+void adc_set_injected_sequence(u32 adc, u8 length, u8 channel[]);
+bool adc_eoc(u32 adc);
+bool adc_eoc_injected(u32 adc);
+u32 adc_read_regular(u32 adc);
+u32 adc_read_injected(u32 adc, u8 reg);
+void adc_set_injected_offset(u32 adc, u8 reg, u32 offset);
+
+void adc_set_clk_prescale(u32 prescaler);
+void adc_set_multi_mode(u32 mode);
+void adc_enable_external_trigger_regular(u32 adc, u32 trigger, u32 polarity);
+void adc_enable_external_trigger_injected(u32 adc, u32 trigger, u32 polarity);
+void adc_set_resolution(u32 adc, u16 resolution);
+void adc_enable_overrun_interrupt(u32 adc);
+void adc_disable_overrun_interrupt(u32 adc);
+bool adc_get_overrun_flag(u32 adc);
+void adc_clear_overrun_flag(u32 adc);
+bool adc_awd(u32 adc);
+void adc_eoc_after_each(u32 adc);
+void adc_eoc_after_group(u32 adc);
+void adc_set_dma_continue(u32 adc);
+void adc_set_dma_terminate(u32 adc);
+void adc_enable_temperature_sensor(void);
+void adc_disable_temperature_sensor(void);
+
+END_DECLS
+
+/**@}*/
+
+#endif
diff --git a/include/libopencm3/stm32/f4/crc.h b/include/libopencm3/stm32/f4/crc.h
new file mode 100644
index 0000000..1c375fa
--- /dev/null
+++ b/include/libopencm3/stm32/f4/crc.h
@@ -0,0 +1,40 @@
+/** @defgroup crc_defines CRC Defines
+
+@brief <b>libopencm3 Defined Constants and Types for the STM32F4xx CRC Generator </b>
+
+@ingroup STM32F4xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
+
+@date 18 August 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_CRC_H
+#define LIBOPENCM3_CRC_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/crc_common_all.h>
+
+#endif
diff --git a/include/libopencm3/stm32/f4/dac.h b/include/libopencm3/stm32/f4/dac.h
new file mode 100644
index 0000000..0961c30
--- /dev/null
+++ b/include/libopencm3/stm32/f4/dac.h
@@ -0,0 +1,40 @@
+/** @defgroup dac_defines DAC Defines
+
+@brief <b>Defined Constants and Types for the STM32F4xx DAC</b>
+
+@ingroup STM32F4xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 5 December 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_DAC_H
+#define LIBOPENCM3_DAC_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/dac_common_all.h>
+
+#endif
+
diff --git a/include/libopencm3/stm32/f4/dma.h b/include/libopencm3/stm32/f4/dma.h
new file mode 100644
index 0000000..a3e9db1
--- /dev/null
+++ b/include/libopencm3/stm32/f4/dma.h
@@ -0,0 +1,41 @@
+/** @defgroup STM32F4xx_dma_defines DMA Defines
+
+@ingroup STM32F4xx_defines
+
+@brief Defined Constants and Types for the STM32F4xx DMA Controller
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2011 Fergus Noble <fergusnoble@gmail.com>
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 30 November 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_DMA_H
+#define LIBOPENCM3_DMA_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/dma_common_f24.h>
+
+#endif
+
diff --git a/include/libopencm3/stm32/f4/flash.h b/include/libopencm3/stm32/f4/flash.h
index 2221333..8e7ed30 100644
--- a/include/libopencm3/stm32/f4/flash.h
+++ b/include/libopencm3/stm32/f4/flash.h
@@ -42,76 +42,76 @@
/* --- FLASH_ACR values ---------------------------------------------------- */
-#define FLASH_DCRST (1 << 12)
-#define FLASH_ICRST (1 << 11)
-#define FLASH_DCE (1 << 10)
-#define FLASH_ICE (1 << 9)
-#define FLASH_PRFTEN (1 << 8)
-#define FLASH_LATENCY_0WS 0x00
-#define FLASH_LATENCY_1WS 0x01
-#define FLASH_LATENCY_2WS 0x02
-#define FLASH_LATENCY_3WS 0x03
-#define FLASH_LATENCY_4WS 0x04
-#define FLASH_LATENCY_5WS 0x05
-#define FLASH_LATENCY_6WS 0x06
-#define FLASH_LATENCY_7WS 0x07
+#define FLASH_ACR_DCRST (1 << 12)
+#define FLASH_ACR_ICRST (1 << 11)
+#define FLASH_ACR_DCE (1 << 10)
+#define FLASH_ACR_ICE (1 << 9)
+#define FLASH_ACR_PRFTEN (1 << 8)
+#define FLASH_ACR_LATENCY_0WS 0x00
+#define FLASH_ACR_LATENCY_1WS 0x01
+#define FLASH_ACR_LATENCY_2WS 0x02
+#define FLASH_ACR_LATENCY_3WS 0x03
+#define FLASH_ACR_LATENCY_4WS 0x04
+#define FLASH_ACR_LATENCY_5WS 0x05
+#define FLASH_ACR_LATENCY_6WS 0x06
+#define FLASH_ACR_LATENCY_7WS 0x07
/* --- FLASH_SR values ----------------------------------------------------- */
-#define FLASH_BSY (1 << 16)
-#define FLASH_PGSERR (1 << 7)
-#define FLASH_PGPERR (1 << 6)
-#define FLASH_PGAERR (1 << 5)
-#define FLASH_WRPERR (1 << 4)
-#define FLASH_OPERR (1 << 1)
-#define FLASH_EOP (1 << 0)
+#define FLASH_SR_BSY (1 << 16)
+#define FLASH_SR_PGSERR (1 << 7)
+#define FLASH_SR_PGPERR (1 << 6)
+#define FLASH_SR_PGAERR (1 << 5)
+#define FLASH_SR_WRPERR (1 << 4)
+#define FLASH_SR_OPERR (1 << 1)
+#define FLASH_SR_EOP (1 << 0)
/* --- FLASH_CR values ----------------------------------------------------- */
-#define FLASH_LOCK (1 << 31)
-#define FLASH_ERRIE (1 << 25)
-#define FLASH_EOPIE (1 << 24)
-#define FLASH_STRT (1 << 16)
-#define FLASH_MER (1 << 2)
-#define FLASH_SER (1 << 1)
-#define FLASH_PG (1 << 0)
-#define FLASH_SECTOR_0 (0x00 << 3)
-#define FLASH_SECTOR_1 (0x01 << 3)
-#define FLASH_SECTOR_2 (0x02 << 3)
-#define FLASH_SECTOR_3 (0x03 << 3)
-#define FLASH_SECTOR_4 (0x04 << 3)
-#define FLASH_SECTOR_5 (0x05 << 3)
-#define FLASH_SECTOR_6 (0x06 << 3)
-#define FLASH_SECTOR_7 (0x07 << 3)
-#define FLASH_SECTOR_8 (0x08 << 3)
-#define FLASH_SECTOR_9 (0x09 << 3)
-#define FLASH_SECTOR_10 (0x0a << 3)
-#define FLASH_SECTOR_11 (0x0b << 3)
-#define FLASH_PROGRAM_X8 (0x00 << 8)
-#define FLASH_PROGRAM_X16 (0x01 << 8)
-#define FLASH_PROGRAM_X32 (0x02 << 8)
-#define FLASH_PROGRAM_X64 (0x03 << 8)
+#define FLASH_CR_LOCK (1 << 31)
+#define FLASH_CR_ERRIE (1 << 25)
+#define FLASH_CR_EOPIE (1 << 24)
+#define FLASH_CR_STRT (1 << 16)
+#define FLASH_CR_MER (1 << 2)
+#define FLASH_CR_SER (1 << 1)
+#define FLASH_CR_PG (1 << 0)
+#define FLASH_CR_SECTOR_0 (0x00 << 3)
+#define FLASH_CR_SECTOR_1 (0x01 << 3)
+#define FLASH_CR_SECTOR_2 (0x02 << 3)
+#define FLASH_CR_SECTOR_3 (0x03 << 3)
+#define FLASH_CR_SECTOR_4 (0x04 << 3)
+#define FLASH_CR_SECTOR_5 (0x05 << 3)
+#define FLASH_CR_SECTOR_6 (0x06 << 3)
+#define FLASH_CR_SECTOR_7 (0x07 << 3)
+#define FLASH_CR_SECTOR_8 (0x08 << 3)
+#define FLASH_CR_SECTOR_9 (0x09 << 3)
+#define FLASH_CR_SECTOR_10 (0x0a << 3)
+#define FLASH_CR_SECTOR_11 (0x0b << 3)
+#define FLASH_CR_PROGRAM_X8 (0x00 << 8)
+#define FLASH_CR_PROGRAM_X16 (0x01 << 8)
+#define FLASH_CR_PROGRAM_X32 (0x02 << 8)
+#define FLASH_CR_PROGRAM_X64 (0x03 << 8)
/* --- FLASH_OPTCR values -------------------------------------------------- */
/* FLASH_OPTCR[27:16]: nWRP */
/* FLASH_OBR[15:8]: RDP */
-#define FLASH_NRST_STDBY (1 << 7)
-#define FLASH_NRST_STOP (1 << 6)
-#define FLASH_WDG_SW (1 << 5)
-#define FLASH_OPTSTRT (1 << 1)
-#define FLASH_OPTLOCK (1 << 0)
-#define FLASH_BOR_LEVEL_3 (0x00 << 2)
-#define FLASH_BOR_LEVEL_2 (0x01 << 2)
-#define FLASH_BOR_LEVEL_1 (0x02 << 2)
-#define FLASH_BOR_OFF (0x03 << 2)
+#define FLASH_OPTCR_NRST_STDBY (1 << 7)
+#define FLASH_OPTCR_NRST_STOP (1 << 6)
+#define FLASH_OPTCR_WDG_SW (1 << 5)
+#define FLASH_OPTCR_OPTSTRT (1 << 1)
+#define FLASH_OPTCR_OPTLOCK (1 << 0)
+#define FLASH_OPTCR_BOR_LEVEL_3 (0x00 << 2)
+#define FLASH_OPTCR_BOR_LEVEL_2 (0x01 << 2)
+#define FLASH_OPTCR_BOR_LEVEL_1 (0x02 << 2)
+#define FLASH_OPTCR_BOR_OFF (0x03 << 2)
/* --- FLASH Keys -----------------------------------------------------------*/
-#define FLASH_KEY1 ((u32)0x45670123)
-#define FLASH_KEY2 ((u32)0xcdef89ab)
-#define FLASH_OPTKEY1 ((u32)0x08192a3b)
-#define FLASH_OPTKEY2 ((u32)0x4c5d6e7f)
+#define FLASH_KEYR_KEY1 ((u32)0x45670123)
+#define FLASH_KEYR_KEY2 ((u32)0xcdef89ab)
+#define FLASH_OPTKEYR_KEY1 ((u32)0x08192a3b)
+#define FLASH_OPTKEYR_KEY2 ((u32)0x4c5d6e7f)
/* --- Function prototypes ------------------------------------------------- */
diff --git a/include/libopencm3/stm32/f4/gpio.h b/include/libopencm3/stm32/f4/gpio.h
index b7da9c6..4eedc6e 100644
--- a/include/libopencm3/stm32/f4/gpio.h
+++ b/include/libopencm3/stm32/f4/gpio.h
@@ -1,8 +1,23 @@
+/** @defgroup gpio_defines GPIO Defines
+
+@brief <b>Defined Constants and Types for the STM32F4xx General Purpose I/O</b>
+
+@ingroup STM32F4xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
+@author @htmlonly &copy; @endhtmlonly 2012 Piotr Esden-Tempski <piotr@esden.net>
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 1 July 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
/*
* This file is part of the libopencm3 project.
*
- * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
- *
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
@@ -21,262 +36,7 @@
#define LIBOPENCM3_GPIO_H
#include <libopencm3/stm32/memorymap.h>
-#include <libopencm3/cm3/common.h>
-
-/* --- Convenience macros -------------------------------------------------- */
-
-/* GPIO port base addresses (for convenience) */
-#define GPIOA GPIO_PORT_A_BASE
-#define GPIOB GPIO_PORT_B_BASE
-#define GPIOC GPIO_PORT_C_BASE
-#define GPIOD GPIO_PORT_D_BASE
-#define GPIOE GPIO_PORT_E_BASE
-#define GPIOF GPIO_PORT_F_BASE
-#define GPIOG GPIO_PORT_G_BASE
-#define GPIOH GPIO_PORT_H_BASE
-#define GPIOI GPIO_PORT_I_BASE
-
-/* GPIO number definitions (for convenience) */
-#define GPIO0 (1 << 0)
-#define GPIO1 (1 << 1)
-#define GPIO2 (1 << 2)
-#define GPIO3 (1 << 3)
-#define GPIO4 (1 << 4)
-#define GPIO5 (1 << 5)
-#define GPIO6 (1 << 6)
-#define GPIO7 (1 << 7)
-#define GPIO8 (1 << 8)
-#define GPIO9 (1 << 9)
-#define GPIO10 (1 << 10)
-#define GPIO11 (1 << 11)
-#define GPIO12 (1 << 12)
-#define GPIO13 (1 << 13)
-#define GPIO14 (1 << 14)
-#define GPIO15 (1 << 15)
-#define GPIO_ALL 0xffff
-
-/* --- GPIO registers ------------------------------------------------------ */
-
-/* Port mode register (GPIOx_MODER) */
-#define GPIO_MODER(port) MMIO32(port + 0x00)
-#define GPIOA_MODER GPIO_MODER(GPIOA)
-#define GPIOB_MODER GPIO_MODER(GPIOB)
-#define GPIOC_MODER GPIO_MODER(GPIOC)
-#define GPIOD_MODER GPIO_MODER(GPIOD)
-#define GPIOE_MODER GPIO_MODER(GPIOE)
-#define GPIOF_MODER GPIO_MODER(GPIOF)
-#define GPIOG_MODER GPIO_MODER(GPIOG)
-#define GPIOH_MODER GPIO_MODER(GPIOH)
-#define GPIOI_MODER GPIO_MODER(GPIOI)
-
-/* Port output type register (GPIOx_OTYPER) */
-#define GPIO_OTYPER(port) MMIO32(port + 0x04)
-#define GPIOA_OTYPER GPIO_OTYPER(GPIOA)
-#define GPIOB_OTYPER GPIO_OTYPER(GPIOB)
-#define GPIOC_OTYPER GPIO_OTYPER(GPIOC)
-#define GPIOD_OTYPER GPIO_OTYPER(GPIOD)
-#define GPIOE_OTYPER GPIO_OTYPER(GPIOE)
-#define GPIOF_OTYPER GPIO_OTYPER(GPIOF)
-#define GPIOG_OTYPER GPIO_OTYPER(GPIOG)
-#define GPIOH_OTYPER GPIO_OTYPER(GPIOH)
-#define GPIOI_OTYPER GPIO_OTYPER(GPIOI)
-
-/* Port output speed register (GPIOx_OSPEEDR) */
-#define GPIO_OSPEEDR(port) MMIO32(port + 0x08)
-#define GPIOA_OSPEEDR GPIO_OSPEEDR(GPIOA)
-#define GPIOB_OSPEEDR GPIO_OSPEEDR(GPIOB)
-#define GPIOC_OSPEEDR GPIO_OSPEEDR(GPIOC)
-#define GPIOD_OSPEEDR GPIO_OSPEEDR(GPIOD)
-#define GPIOE_OSPEEDR GPIO_OSPEEDR(GPIOE)
-#define GPIOF_OSPEEDR GPIO_OSPEEDR(GPIOF)
-#define GPIOG_OSPEEDR GPIO_OSPEEDR(GPIOG)
-#define GPIOH_OSPEEDR GPIO_OSPEEDR(GPIOH)
-#define GPIOI_OSPEEDR GPIO_OSPEEDR(GPIOI)
-
-/* Port pull-up/pull-down register (GPIOx_PUPDR) */
-#define GPIO_PUPDR(port) MMIO32(port + 0x0c)
-#define GPIOA_PUPDR GPIO_PUPDR(GPIOA)
-#define GPIOB_PUPDR GPIO_PUPDR(GPIOB)
-#define GPIOC_PUPDR GPIO_PUPDR(GPIOC)
-#define GPIOD_PUPDR GPIO_PUPDR(GPIOD)
-#define GPIOE_PUPDR GPIO_PUPDR(GPIOE)
-#define GPIOF_PUPDR GPIO_PUPDR(GPIOF)
-#define GPIOG_PUPDR GPIO_PUPDR(GPIOG)
-#define GPIOH_PUPDR GPIO_PUPDR(GPIOH)
-#define GPIOI_PUPDR GPIO_PUPDR(GPIOI)
-
-/* Port input data register (GPIOx_IDR) */
-#define GPIO_IDR(port) MMIO32(port + 0x10)
-#define GPIOA_IDR GPIO_IDR(GPIOA)
-#define GPIOB_IDR GPIO_IDR(GPIOB)
-#define GPIOC_IDR GPIO_IDR(GPIOC)
-#define GPIOD_IDR GPIO_IDR(GPIOD)
-#define GPIOE_IDR GPIO_IDR(GPIOE)
-#define GPIOF_IDR GPIO_IDR(GPIOF)
-#define GPIOG_IDR GPIO_IDR(GPIOG)
-#define GPIOH_IDR GPIO_IDR(GPIOH)
-#define GPIOI_IDR GPIO_IDR(GPIOI)
-
-/* Port output data register (GPIOx_ODR) */
-#define GPIO_ODR(port) MMIO32(port + 0x14)
-#define GPIOA_ODR GPIO_ODR(GPIOA)
-#define GPIOB_ODR GPIO_ODR(GPIOB)
-#define GPIOC_ODR GPIO_ODR(GPIOC)
-#define GPIOD_ODR GPIO_ODR(GPIOD)
-#define GPIOE_ODR GPIO_ODR(GPIOE)
-#define GPIOF_ODR GPIO_ODR(GPIOF)
-#define GPIOG_ODR GPIO_ODR(GPIOG)
-#define GPIOH_ODR GPIO_ODR(GPIOH)
-#define GPIOI_ODR GPIO_ODR(GPIOI)
-
-/* Port bit set/reset register (GPIOx_BSRR) */
-#define GPIO_BSRR(port) MMIO32(port + 0x18)
-#define GPIOA_BSRR GPIO_BSRR(GPIOA)
-#define GPIOB_BSRR GPIO_BSRR(GPIOB)
-#define GPIOC_BSRR GPIO_BSRR(GPIOC)
-#define GPIOD_BSRR GPIO_BSRR(GPIOD)
-#define GPIOE_BSRR GPIO_BSRR(GPIOE)
-#define GPIOF_BSRR GPIO_BSRR(GPIOF)
-#define GPIOG_BSRR GPIO_BSRR(GPIOG)
-#define GPIOH_BSRR GPIO_BSRR(GPIOH)
-#define GPIOI_BSRR GPIO_BSRR(GPIOI)
-
-/* Port configuration lock register (GPIOx_LCKR) */
-#define GPIO_LCKR(port) MMIO32(port + 0x1c)
-#define GPIOA_LCKR GPIO_LCKR(GPIOA)
-#define GPIOB_LCKR GPIO_LCKR(GPIOB)
-#define GPIOC_LCKR GPIO_LCKR(GPIOC)
-#define GPIOD_LCKR GPIO_LCKR(GPIOD)
-#define GPIOE_LCKR GPIO_LCKR(GPIOE)
-#define GPIOF_LCKR GPIO_LCKR(GPIOF)
-#define GPIOG_LCKR GPIO_LCKR(GPIOG)
-#define GPIOH_LCKR GPIO_LCKR(GPIOH)
-#define GPIOI_LCKR GPIO_LCKR(GPIOI)
-
-/* Alternate function low register (GPIOx_AFRL) */
-#define GPIO_AFRL(port) MMIO32(port + 0x20)
-#define GPIOA_AFRL GPIO_AFRL(GPIOA)
-#define GPIOB_AFRL GPIO_AFRL(GPIOB)
-#define GPIOC_AFRL GPIO_AFRL(GPIOC)
-#define GPIOD_AFRL GPIO_AFRL(GPIOD)
-#define GPIOE_AFRL GPIO_AFRL(GPIOE)
-#define GPIOF_AFRL GPIO_AFRL(GPIOF)
-#define GPIOG_AFRL GPIO_AFRL(GPIOG)
-#define GPIOH_AFRL GPIO_AFRL(GPIOH)
-#define GPIOI_AFRL GPIO_AFRL(GPIOI)
-
-/* Alternate function high register (GPIOx_AFRH) */
-#define GPIO_AFRH(port) MMIO32(port + 0x24)
-#define GPIOA_AFRH GPIO_AFRH(GPIOA)
-#define GPIOB_AFRH GPIO_AFRH(GPIOB)
-#define GPIOC_AFRH GPIO_AFRH(GPIOC)
-#define GPIOD_AFRH GPIO_AFRH(GPIOD)
-#define GPIOE_AFRH GPIO_AFRH(GPIOE)
-#define GPIOF_AFRH GPIO_AFRH(GPIOF)
-#define GPIOG_AFRH GPIO_AFRH(GPIOG)
-#define GPIOH_AFRH GPIO_AFRH(GPIOH)
-#define GPIOI_AFRH GPIO_AFRH(GPIOI)
-
-/* --- GPIOx_MODER values -------------------------------------------------- */
-
-#define GPIO_MODE(n, mode) (mode << (2 * (n)))
-#define GPIO_MODE_MASK(n) (0x3 << (2 * (n)))
-#define GPIO_MODE_INPUT 0x0
-#define GPIO_MODE_OUTPUT 0x1
-#define GPIO_MODE_AF 0x2
-#define GPIO_MODE_ANALOG 0x3
-
-/* --- GPIOx_OTYPER values ------------------------------------------------- */
-
-#define GPIO_OTYPE_PP 0x0
-#define GPIO_OTYPE_OD 0x1
-
-/* --- GPIOx_OSPEEDR values ------------------------------------------------ */
-
-#define GPIO_OSPEED(n, speed) (speed << (2 * (n)))
-#define GPIO_OSPEED_MASK(n) (0x3 << (2 * (n)))
-#define GPIO_OSPEED_2MHZ 0x0
-#define GPIO_OSPEED_25MHZ 0x1
-#define GPIO_OSPEED_50MHZ 0x2
-#define GPIO_OSPEED_100MHZ 0x3
-
-/* --- GPIOx_PUPDR values -------------------------------------------------- */
-
-#define GPIO_PUPD(n, pupd) (pupd << (2 * (n)))
-#define GPIO_PUPD_MASK(n) (0x3 << (2 * (n)))
-#define GPIO_PUPD_NONE 0x0
-#define GPIO_PUPD_PULLUP 0x1
-#define GPIO_PUPD_PULLDOWN 0x2
-
-/* --- GPIOx_IDR values ---------------------------------------------------- */
-
-/* GPIOx_IDR[15:0]: IDRy[15:0]: Port input data (y = 0..15) */
-
-/* --- GPIOx_ODR values ---------------------------------------------------- */
-
-/* GPIOx_ODR[15:0]: ODRy[15:0]: Port output data (y = 0..15) */
-
-/* --- GPIOx_BSRR values --------------------------------------------------- */
-
-/* GPIOx_BSRR[31:16]: BRy: Port x reset bit y (y = 0..15) */
-/* GPIOx_BSRR[15:0]: BSy: Port x set bit y (y = 0..15) */
-
-/* --- GPIOx_LCKR values --------------------------------------------------- */
-
-#define GPIO_LCKK (1 << 16)
-/* GPIOx_LCKR[15:0]: LCKy: Port x lock bit y (y = 0..15) */
-
-/* --- GPIOx_AFRL/H values ------------------------------------------------- */
-
-/* Note: AFRL is used for bits 0..7, AFRH is used for 8..15 */
-/* See Datasheet Table 6 (pg. 48) for alternate function mappings. */
-
-#define GPIO_AFR(n, af) (af << ((n) * 4))
-#define GPIO_AFR_MASK(n) (0xf << ((n) * 4))
-#define GPIO_AF0 0x0
-#define GPIO_AF1 0x1
-#define GPIO_AF2 0x2
-#define GPIO_AF3 0x3
-#define GPIO_AF4 0x4
-#define GPIO_AF5 0x5
-#define GPIO_AF6 0x6
-#define GPIO_AF7 0x7
-#define GPIO_AF8 0x8
-#define GPIO_AF9 0x9
-#define GPIO_AF10 0xa
-#define GPIO_AF11 0xb
-#define GPIO_AF12 0xc
-#define GPIO_AF13 0xd
-#define GPIO_AF14 0xe
-#define GPIO_AF15 0xf
-
-/* Note: EXTI source selection is now in the SYSCFG peripheral. */
-
-/* --- Function prototypes ------------------------------------------------- */
-
-BEGIN_DECLS
-
-/*
- * Note: The F4 series has a completely new GPIO peripheral with different
- * configuration options. Here we implement a different API partly to more
- * closely match the peripheral capabilities and also to deliberately break
- * compatibility with old F1 code so there is no confusion with similar
- * sounding functions that have very different functionality.
- */
-
-void gpio_mode_setup(u32 gpioport, u8 mode, u8 pull_up_down, u16 gpios);
-void gpio_set_output_options(u32 gpioport, u8 otype, u8 speed, u16 gpios);
-void gpio_set_af(u32 gpioport, u8 alt_func_num, u16 gpios);
-
-/* This part of the API is compatible with the F1 series ------------------- */
-void gpio_set(u32 gpioport, u16 gpios);
-void gpio_clear(u32 gpioport, u16 gpios);
-u16 gpio_get(u32 gpioport, u16 gpios);
-void gpio_toggle(u32 gpioport, u16 gpios);
-u16 gpio_port_read(u32 gpioport);
-void gpio_port_write(u32 gpioport, u16 data);
-void gpio_port_config_lock(u32 gpioport, u16 gpios);
-
-END_DECLS
+#include <libopencm3/stm32/common/gpio_common_f24.h>
#endif
+
diff --git a/include/libopencm3/stm32/f4/i2c.h b/include/libopencm3/stm32/f4/i2c.h
new file mode 100644
index 0000000..e1a41cf
--- /dev/null
+++ b/include/libopencm3/stm32/f4/i2c.h
@@ -0,0 +1,41 @@
+/** @defgroup i2c_defines I2C Defines
+
+@brief <b>Defined Constants and Types for the STM32F4xx I2C </b>
+
+@ingroup STM32F4xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 12 October 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_I2C_H
+#define LIBOPENCM3_I2C_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/i2c_common_f24.h>
+
+#endif
+
diff --git a/include/libopencm3/stm32/f4/irq.yaml b/include/libopencm3/stm32/f4/irq.yaml
new file mode 100644
index 0000000..2d4bae9
--- /dev/null
+++ b/include/libopencm3/stm32/f4/irq.yaml
@@ -0,0 +1,85 @@
+includeguard: LIBOPENCM3_STM32_F4_NVIC_H
+partname_humanreadable: STM32 F4 series
+partname_doxygen: STM32F4
+irqs:
+ - nvic_wwdg
+ - pvd
+ - tamp_stamp
+ - rtc_wkup
+ - flash
+ - rcc
+ - exti0
+ - exti1
+ - exti2
+ - exti3
+ - exti4
+ - dma1_stream0
+ - dma1_stream1
+ - dma1_stream2
+ - dma1_stream3
+ - dma1_stream4
+ - dma1_stream5
+ - dma1_stream6
+ - adc
+ - can1_tx
+ - can1_rx0
+ - can1_rx1
+ - can1_sce
+ - exti9_5
+ - tim1_brk_tim9
+ - tim1_up_tim10
+ - tim1_trg_com_tim11
+ - tim1_cc
+ - tim2
+ - tim3
+ - tim4
+ - i2c1_ev
+ - i2c1_er
+ - i2c2_ev
+ - i2c2_er
+ - spi1
+ - spi2
+ - usart1
+ - usart2
+ - usart3
+ - exti15_10
+ - rtc_alarm
+ - usb_fs_wkup
+ - tim8_brk_tim12
+ - tim8_up_tim13
+ - tim8_trg_com_tim14
+ - tim8_cc
+ - dma1_stream7
+ - fsmc
+ - sdio
+ - tim5
+ - spi3
+ - uart4
+ - uart5
+ - tim6_dac
+ - tim7
+ - dma2_stream0
+ - dma2_stream1
+ - dma2_stream2
+ - dma2_stream3
+ - dma2_stream4
+ - eth
+ - eth_wkup
+ - can2_tx
+ - can2_rx0
+ - can2_rx1
+ - can2_sce
+ - otg_fs
+ - dma2_stream5
+ - dma2_stream6
+ - dma2_stream7
+ - usart6
+ - i2c3_ev
+ - i2c3_er
+ - otg_hs_ep1_out
+ - otg_hs_ep1_in
+ - otg_hs_wkup
+ - otg_hs
+ - dcmi
+ - cryp
+ - hash_rng
diff --git a/include/libopencm3/stm32/f4/iwdg.h b/include/libopencm3/stm32/f4/iwdg.h
new file mode 100644
index 0000000..d5baef4
--- /dev/null
+++ b/include/libopencm3/stm32/f4/iwdg.h
@@ -0,0 +1,41 @@
+/** @defgroup iwdg_defines IWDG Defines
+
+@brief <b>Defined Constants and Types for the STM32F4xx Independent Watchdog Timer</b>
+
+@ingroup STM32F4xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
+
+@date 18 August 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_IWDG_H
+#define LIBOPENCM3_IWDG_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/iwdg_common_all.h>
+
+#endif
+
diff --git a/include/libopencm3/stm32/f4/memorymap.h b/include/libopencm3/stm32/f4/memorymap.h
index 0a22ad4..7625838 100644
--- a/include/libopencm3/stm32/f4/memorymap.h
+++ b/include/libopencm3/stm32/f4/memorymap.h
@@ -75,8 +75,9 @@
#define USART6_BASE (PERIPH_BASE_APB2 + 0x1400)
/* PERIPH_BASE_APB2 + 0x1800 (0x4001 1800 - 0x4001 1FFF): Reserved */
#define ADC1_BASE (PERIPH_BASE_APB2 + 0x2000)
-#define ADC2_BASE (PERIPH_BASE_APB2 + 0x2000)
-#define ADC3_BASE (PERIPH_BASE_APB2 + 0x2000)
+#define ADC2_BASE (PERIPH_BASE_APB2 + 0x2100)
+#define ADC3_BASE (PERIPH_BASE_APB2 + 0x2200)
+#define ADC_COMMON_BASE (PERIPH_BASE_APB2 + 0x2300)
/* PERIPH_BASE_APB2 + 0x2400 (0x4001 2400 - 0x4001 27FF): Reserved */
#define SDIO_BASE (PERIPH_BASE_APB2 + 0x2800)
/* PERIPH_BASE_APB2 + 0x2C00 (0x4001 2C00 - 0x4001 2FFF): Reserved */
diff --git a/include/libopencm3/stm32/f4/nvic_f4.h b/include/libopencm3/stm32/f4/nvic_f4.h
deleted file mode 100644
index 91b6c25..0000000
--- a/include/libopencm3/stm32/f4/nvic_f4.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * This file is part of the libopencm3 project.
- *
- * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef LIBOPENCM3_NVIC_F4_H
-#define LIBOPENCM3_NVIC_F4_H
-
-/* --- IRQ channel numbers-------------------------------------------------- */
-
-/* Note: These F4 specific user interrupt definitions supplement the
- * general NVIC definitions in ../nvic.h
- */
-
-/* User Interrupts */
-#define NVIC_NVIC_WWDG_IRQ 0
-#define NVIC_PVD_IRQ 1
-#define NVIC_TAMP_STAMP_IRQ 2
-#define NVIC_RTC_WKUP_IRQ 3
-#define NVIC_FLASH_IRQ 4
-#define NVIC_RCC_IRQ 5
-#define NVIC_EXTI0_IRQ 6
-#define NVIC_EXTI1_IRQ 7
-#define NVIC_EXTI2_IRQ 8
-#define NVIC_EXTI3_IRQ 9
-#define NVIC_EXTI4_IRQ 10
-#define NVIC_DMA1_STREAM0_IRQ 11
-#define NVIC_DMA1_STREAM1_IRQ 12
-#define NVIC_DMA1_STREAM2_IRQ 13
-#define NVIC_DMA1_STREAM3_IRQ 14
-#define NVIC_DMA1_STREAM4_IRQ 15
-#define NVIC_DMA1_STREAM5_IRQ 16
-#define NVIC_DMA1_STREAM6_IRQ 17
-#define NVIC_ADC_IRQ 18
-#define NVIC_CAN1_TX_IRQ 19
-#define NVIC_CAN1_RX0_IRQ 20
-#define NVIC_CAN1_RX1_IRQ 21
-#define NVIC_CAN1_SCE_IRQ 22
-#define NVIC_EXTI9_5_IRQ 23
-#define NVIC_TIM1_BRK_TIM9_IRQ 24
-#define NVIC_TIM1_UP_TIM10_IRQ 25
-#define NVIC_TIM1_TRG_COM_TIM11_IRQ 26
-#define NVIC_TIM1_CC_IRQ 27
-#define NVIC_TIM2_IRQ 28
-#define NVIC_TIM3_IRQ 29
-#define NVIC_TIM4_IRQ 30
-#define NVIC_I2C1_EV_IRQ 31
-#define NVIC_I2C1_ER_IRQ 32
-#define NVIC_I2C2_EV_IRQ 33
-#define NVIC_I2C2_ER_IRQ 34
-#define NVIC_SPI1_IRQ 35
-#define NVIC_SPI2_IRQ 36
-#define NVIC_USART1_IRQ 37
-#define NVIC_USART2_IRQ 38
-#define NVIC_USART3_IRQ 39
-#define NVIC_EXTI15_10_IRQ 40
-#define NVIC_RTC_ALARM_IRQ 41
-#define NVIC_USB_FS_WKUP_IRQ 42
-#define NVIC_TIM8_BRK_TIM12_IRQ 43
-#define NVIC_TIM8_UP_TIM13_IRQ 44
-#define NVIC_TIM8_TRG_COM_TIM14_IRQ 45
-#define NVIC_TIM8_CC_IRQ 46
-#define NVIC_DMA1_STREAM7_IRQ 47
-#define NVIC_FSMC_IRQ 48
-#define NVIC_SDIO_IRQ 49
-#define NVIC_TIM5_IRQ 50
-#define NVIC_SPI3_IRQ 51
-#define NVIC_UART4_IRQ 52
-#define NVIC_UART5_IRQ 53
-#define NVIC_TIM6_DAC_IRQ 54
-#define NVIC_TIM7_IRQ 55
-#define NVIC_DMA2_STREAM0_IRQ 56
-#define NVIC_DMA2_STREAM1_IRQ 57
-#define NVIC_DMA2_STREAM2_IRQ 58
-#define NVIC_DMA2_STREAM3_IRQ 59
-#define NVIC_DMA2_STREAM4_IRQ 60
-#define NVIC_ETH_IRQ 61
-#define NVIC_ETH_WKUP_IRQ 62
-#define NVIC_CAN2_TX_IRQ 63
-#define NVIC_CAN2_RX0_IRQ 64
-#define NVIC_CAN2_RX1_IRQ 65
-#define NVIC_CAN2_SCE_IRQ 66
-#define NVIC_OTG_FS_IRQ 67
-#define NVIC_DMA2_STREAM5_IRQ 68
-#define NVIC_DMA2_STREAM6_IRQ 69
-#define NVIC_DMA2_STREAM7_IRQ 70
-#define NVIC_USART6_IRQ 71
-#define NVIC_I2C3_EV_IRQ 72
-#define NVIC_I2C3_ER_IRQ 73
-#define NVIC_OTG_HS_EP1_OUT_IRQ 74
-#define NVIC_OTG_HS_EP1_IN_IRQ 75
-#define NVIC_OTG_HS_WKUP_IRQ 76
-#define NVIC_OTG_HS_IRQ 77
-#define NVIC_DCMI_IRQ 78
-#define NVIC_CRYP_IRQ 79
-#define NVIC_HASH_RNG_IRQ 80
-
-#endif
diff --git a/include/libopencm3/stm32/f4/pwr.h b/include/libopencm3/stm32/f4/pwr.h
index 25fb163..c9b27fd 100644
--- a/include/libopencm3/stm32/f4/pwr.h
+++ b/include/libopencm3/stm32/f4/pwr.h
@@ -1,3 +1,15 @@
+/** @defgroup pwr_defines PWR Defines
+
+@brief <b>Defined Constants and Types for the STM32F4xx Power Control</b>
+
+@ingroup STM32F4xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2011 Stephen Caudle <scaudle@doceme.com>
+
+LGPL License Terms @ref lgpl_license
+ */
/*
* This file is part of the libopencm3 project.
*
@@ -17,10 +29,11 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
-#ifndef LIBOPENCM3_PWR_F4_H
-#define LIBOPENCM3_PWR_F4_H
+#ifndef LIBOPENCM3_PWR_H
+#define LIBOPENCM3_PWR_H
-#include <libopencm3/stm32/pwr.h>
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/pwr_common_all.h>
/*
* This file extends the common STM32 version with definitions only
diff --git a/include/libopencm3/stm32/f4/rcc.h b/include/libopencm3/stm32/f4/rcc.h
index 1688584..a718903 100644
--- a/include/libopencm3/stm32/f4/rcc.h
+++ b/include/libopencm3/stm32/f4/rcc.h
@@ -427,7 +427,7 @@
#define RCC_CSR_SFTRSTF (1 << 28)
#define RCC_CSR_PORRSTF (1 << 27)
#define RCC_CSR_PINRSTF (1 << 26)
-#define RCC_CSR_BORRSTF (1 << 26)
+#define RCC_CSR_BORRSTF (1 << 25)
#define RCC_CSR_RMVF (1 << 24)
#define RCC_CSR_LSIRDY (1 << 1)
#define RCC_CSR_LSION (1 << 0)
diff --git a/include/libopencm3/stm32/f4/rng.h b/include/libopencm3/stm32/f4/rng.h
index 5f517c8..e8e6cc4 100644
--- a/include/libopencm3/stm32/f4/rng.h
+++ b/include/libopencm3/stm32/f4/rng.h
@@ -1,7 +1,6 @@
/*
* This file is part of the libopencm3 project.
*
- *
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
@@ -16,46 +15,10 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
-#ifndef LIBOPENCM3_RNG_H
-#define LIBOPENCM3_RNG_H
+#ifndef LIBOPENCM3_RNG_F4_H
+#define LIBOPENCM3_RNG_F4_H
#include <libopencm3/stm32/memorymap.h>
-#include <libopencm3/cm3/common.h>
-
-/* --- Random number generator registers ----------------------------------- */
-
-/* Control register */
-#define RNG_CR MMIO32(RNG_BASE + 0x00)
-
-/* Status register */
-#define RNG_SR MMIO32(RNG_BASE + 0x04)
-
-/* Data register */
-#define RNG_DR MMIO32(RNG_BASE + 0x08)
-
-/* --- RNG_CR values ------------------------------------------------------- */
-
-/* RNG ENABLE */
-#define RNG_CR_EN (1 << 2)
-
-/* RNG interupt enable */
-#define RNG_CR_IE (1 << 3)
-
-/* --- RNG_SR values ------------------------------------------------------- */
-
-/* Data ready */
-#define RNG_SR_DRDY (1 << 0)
-
-/* Clock error current status */
-#define RNG_SR_CECS (1 << 1)
-
-/* Seed error current status */
-#define RNG_SR_SECS (1 << 2)
-
-/* Clock error interup status */
-#define RNG_SR_CEIS (1 << 5)
-
-/* Seed error interup status */
-#define RNG_SR_SEIS (1 << 6)
+#include <libopencm3/stm32/common/rng_common_f24.h>
#endif
diff --git a/include/libopencm3/stm32/f4/rtc.h b/include/libopencm3/stm32/f4/rtc.h
new file mode 100644
index 0000000..ab8d3ee
--- /dev/null
+++ b/include/libopencm3/stm32/f4/rtc.h
@@ -0,0 +1,39 @@
+/** @defgroup rtc_defines RTC Defines
+
+@brief <b>Defined Constants and Types for the STM32F4xx RTC</b>
+
+@ingroup STM32F4xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 5 December 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_RTC_H
+#define LIBOPENCM3_RTC_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/rtc_common_bcd.h>
+
+#endif \ No newline at end of file
diff --git a/include/libopencm3/stm32/f4/scb.h b/include/libopencm3/stm32/f4/scb.h
deleted file mode 100644
index 7187ca9..0000000
--- a/include/libopencm3/stm32/f4/scb.h
+++ /dev/null
@@ -1,376 +0,0 @@
-/*
- * This file is part of the libopencm3 project.
- *
- * Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
- * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef LIBOPENCM3_SCB_H
-#define LIBOPENCM3_SCB_H
-
-#include <libopencm3/stm32/memorymap.h>
-#include <libopencm3/cm3/common.h>
-
-/* --- SCB: Registers ------------------------------------------------------ */
-
-/* CPUID: CPUID base register */
-#define SCB_CPUID MMIO32(SCB_BASE + 0x00)
-
-/* ICSR: Interrupt Control State Register */
-#define SCB_ICSR MMIO32(SCB_BASE + 0x04)
-
-/* VTOR: Vector Table Offset Register */
-#define SCB_VTOR MMIO32(SCB_BASE + 0x08)
-
-/* AIRCR: Application Interrupt and Reset Control Register */
-#define SCB_AIRCR MMIO32(SCB_BASE + 0x0C)
-
-/* SCR: System Control Register */
-#define SCB_SCR MMIO32(SCB_BASE + 0x10)
-
-/* CCR: Configuration Control Register */
-#define SCB_CCR MMIO32(SCB_BASE + 0x14)
-
-/* SHP: System Handler Priority Registers */
-/* Note: 12 8bit registers */
-#define SCB_SHPR(shpr_id) MMIO8(SCB_BASE + 0x18 + shpr_id)
-#define SCB_SHPR1 MMIO8(SCB_BASE + 0x18 + 1)
-#define SCB_SHPR2 MMIO8(SCB_BASE + 0x18 + 2)
-#define SCB_SHPR3 MMIO8(SCB_BASE + 0x18 + 3)
-
-/* SHCSR: System Handler Control and State Register */
-#define SCB_SHCSR MMIO32(SCB_BASE + 0x24)
-
-/* CFSR: Configurable Fault Status Registers */
-#define SCB_CFSR MMIO32(SCB_BASE + 0x28)
-
-/* HFSR: Hard Fault Status Register */
-#define SCB_HFSR MMIO32(SCB_BASE + 0x2C)
-
-/* DFSR: Debug Fault Status Register */
-#define SCB_DFSR MMIO32(SCB_BASE + 0x30)
-
-/* MMFAR: Memory Manage Fault Address Register */
-#define SCB_MMFAR MMIO32(SCB_BASE + 0x34)
-
-/* BFAR: Bus Fault Address Register */
-#define SCB_BFAR MMIO32(SCB_BASE + 0x38)
-
-/* AFSR: Auxiliary Fault Status Register */
-#define SCB_AFSR MMIO32(SCB_BASE + 0x3C)
-
-/* ID_PFR0: Processor Feature Register 0 */
-#define SCB_ID_PFR0 MMIO32(SCB_BASE + 0x40)
-
-/* ID_PFR1: Processor Feature Register 1 */
-#define SCB_ID_PFR1 MMIO32(SCB_BASE + 0x44)
-
-/* ID_DFR0: Debug Features Register 0 */
-#define SCB_ID_DFR0 MMIO32(SCB_BASE + 0x48)
-
-/* ID_AFR0: Auxiliary Features Register 0 */
-#define SCB_ID_AFR0 MMIO32(SCB_BASE + 0x4C)
-
-/* ID_MMFR0: Memory Model Feature Register 0 */
-#define SCB_ID_MMFR0 MMIO32(SCB_BASE + 0x50)
-
-/* ID_MMFR1: Memory Model Feature Register 1 */
-#define SCB_ID_MMFR1 MMIO32(SCB_BASE + 0x54)
-
-/* ID_MMFR2: Memory Model Feature Register 2 */
-#define SCB_ID_MMFR2 MMIO32(SCB_BASE + 0x58)
-
-/* ID_MMFR3: Memory Model Feature Register 3 */
-#define SCB_ID_MMFR3 MMIO32(SCB_BASE + 0x5C)
-
-/* ID_ISAR0: Instruction Set Attributes Register 0 */
-#define SCB_ID_ISAR0 MMIO32(SCB_BASE + 0x60)
-
-/* ID_ISAR1: Instruction Set Attributes Register 1 */
-#define SCB_ID_ISAR1 MMIO32(SCB_BASE + 0x64)
-
-/* ID_ISAR2: Instruction Set Attributes Register 2 */
-#define SCB_ID_ISAR2 MMIO32(SCB_BASE + 0x68)
-
-/* ID_ISAR3: Instruction Set Attributes Register 3 */
-#define SCB_ID_ISAR3 MMIO32(SCB_BASE + 0x6C)
-
-/* ID_ISAR4: Instruction Set Attributes Register 4 */
-#define SCB_ID_ISAR4 MMIO32(SCB_BASE + 0x70)
-
-/* CPACR: Coprocessor Access Control Register */
-#define SCB_CPACR MMIO32(SCB_BASE + 0x88)
-
-/* FPCCR: Floating-Point Context Control Register */
-#define SCB_FPCCR MMIO32(SCB_BASE + 0x234)
-
-/* FPCAR: Floating-Point Context Address Register */
-#define SCB_FPCAR MMIO32(SCB_BASE + 0x238)
-
-/* FPDSCR: Floating-Point Default Status Control Register */
-#define SCB_FPDSCR MMIO32(SCB_BASE + 0x23C)
-
-/* MVFR0: Media and Floating-Point Feature Register 0 */
-#define SCB_MVFR0 MMIO32(SCB_BASE + 0x240)
-
-/* MVFR1: Media and Floating-Point Feature Register 1 */
-#define SCB_MVFR1 MMIO32(SCB_BASE + 0x244)
-
-/* --- SCB values ---------------------------------------------------------- */
-
-/* --- SCB_CPUID values ---------------------------------------------------- */
-
-/* Implementer[31:24]: Implementer code */
-#define SCP_CPUID_IMPLEMENTER_LSB 24
-/* Variant[23:20]: Variant number */
-#define SCP_CPUID_VARIANT_LSB 20
-/* Constant[19:16]: Reads as 0xF */
-#define SCP_CPUID_CONSTANT_LSB 16
-/* PartNo[15:4]: Part number of the processor */
-#define SCP_CPUID_PARTNO_LSB 4
-/* Revision[3:0]: Revision number */
-#define SCP_CPUID_REVISION_LSB 0
-
-/* --- SCB_ICSR values ----------------------------------------------------- */
-
-/* NMIPENDSET: NMI set-pending bit */
-#define SCB_ICSR_NMIPENDSET (1 << 31)
-/* Bits [30:29]: reserved - must be kept cleared */
-/* PENDSVSET: PendSV set-pending bit */
-#define SCB_ICSR_PENDSVSET (1 << 28)
-/* PENDSVCLR: PendSV clear-pending bit */
-#define SCB_ICSR_PENDSVCLR (1 << 27)
-/* PENDSTSET: SysTick exception set-pending bit */
-#define SCB_ICSR_PENDSTSET (1 << 26)
-/* PENDSTCLR: SysTick exception clear-pending bit */
-#define SCB_ICSR_PENDSTCLR (1 << 25)
-/* Bit 24: reserved - must be kept cleared */
-/* Bit 23: reserved for debug - reads as 0 when not in debug mode */
-/* ISRPENDING: Interrupt pending flag, excluding NMI and Faults */
-#define SCB_ICSR_ISRPENDING (1 << 22)
-/* VECTPENDING[21:12] Pending vector */
-#define SCB_ICSR_VECTPENDING_LSB 12
-/* RETOBASE: Return to base level */
-#define SCB_ICSR_RETOBASE (1 << 11)
-/* Bits [10:9]: reserved - must be kept cleared */
-/* VECTACTIVE[8:0] Active vector */
-#define SCB_ICSR_VECTACTIVE_LSB 0
-
-/* --- SCB_VTOR values ----------------------------------------------------- */
-
-/* Bits [31:30]: reserved - must be kept cleared */
-/* TBLOFF[29:9]: Vector table base offset field */
-#define SCB_VTOR_TBLOFF_LSB 9 /* inconsistent datasheet - LSB could be 11 */
-
-/* --- SCB_AIRCR values ---------------------------------------------------- */
-
-/* VECTKEYSTAT[31:16]/ VECTKEY[31:16] Register key */
-#define SCB_AIRCR_VECTKEYSTAT_LSB 16
-#define SCB_AIRCR_VECTKEY 0x05FA0000
-/* ENDIANESS Data endianness bit */
-#define SCB_AIRCR_ENDIANESS (1 << 15)
-/* Bits [14:11]: reserved - must be kept cleared */
-/* PRIGROUP[10:8]: Interrupt priority grouping field */
-#define SCB_AIRCR_PRIGROUP_GROUP16_NOSUB (0x3 << 8)
-#define SCB_AIRCR_PRIGROUP_GROUP8_SUB2 (0x4 << 8)
-#define SCB_AIRCR_PRIGROUP_GROUP4_SUB4 (0x5 << 8)
-#define SCB_AIRCR_PRIGROUP_GROUP2_SUB8 (0x6 << 8)
-#define SCB_AIRCR_PRIGROUP_NOGROUP_SUB16 (0x7 << 8)
-#define SCB_AIRCR_PRIGROUP_MASK (0x7 << 8)
-#define SCB_AIRCR_PRIGROUP_SHIFT 8
-/* Bits [7:3]: reserved - must be kept cleared */
-/* SYSRESETREQ System reset request */
-#define SCB_AIRCR_SYSRESETREQ (1 << 2)
-/* VECTCLRACTIVE */
-#define SCB_AIRCR_VECTCLRACTIVE (1 << 1)
-/* VECTRESET */
-#define SCB_AIRCR_VECTRESET (1 << 0)
-
-/* --- SCB_SCR values ------------------------------------------------------ */
-
-/* Bits [31:5]: reserved - must be kept cleared */
-/* SEVEONPEND Send Event on Pending bit */
-#define SCB_SCR_SEVEONPEND (1 << 4)
-/* Bit 3: reserved - must be kept cleared */
-/* SLEEPDEEP */
-#define SCB_SCR_SLEEPDEEP (1 << 2)
-/* SLEEPONEXIT */
-#define SCB_SCR_SLEEPONEXIT (1 << 1)
-/* Bit 0: reserved - must be kept cleared */
-
-/* --- SCB_CCR values ------------------------------------------------------ */
-
-/* Bits [31:10]: reserved - must be kept cleared */
-/* STKALIGN */
-#define SCB_CCR_STKALIGN (1 << 9)
-/* BFHFNMIGN */
-#define SCB_CCR_BFHFNMIGN (1 << 8)
-/* Bits [7:5]: reserved - must be kept cleared */
-/* DIV_0_TRP */
-#define SCB_CCR_DIV_0_TRP (1 << 4)
-/* UNALIGN_TRP */
-#define SCB_CCR_UNALIGN_TRP (1 << 3)
-/* Bit 2: reserved - must be kept cleared */
-/* USERSETMPEND */
-#define SCB_CCR_USERSETMPEND (1 << 1)
-/* NONBASETHRDENA */
-#define SCB_CCR_NONBASETHRDENA (1 << 0)
-
-/* --- SCB_SHPR1 values ---------------------------------------------------- */
-
-/* Bits [31:24]: reserved - must be kept cleared */
-/* PRI_6[23:16]: Priority of system handler 6, usage fault */
-#define SCB_SHPR1_PRI_6_LSB 16
-/* PRI_5[15:8]: Priority of system handler 5, bus fault */
-#define SCB_SHPR1_PRI_5_LSB 8
-/* PRI_4[7:0]: Priority of system handler 4, memory management fault */
-#define SCB_SHPR1_PRI_4_LSB 0
-
-/* --- SCB_SHPR2 values ---------------------------------------------------- */
-
-/* PRI_11[31:24]: Priority of system handler 11, SVCall */
-#define SCB_SHPR2_PRI_11_LSB 24
-/* Bits [23:0]: reserved - must be kept cleared */
-
-/* --- SCB_SHPR3 values ---------------------------------------------------- */
-
-/* PRI_15[31:24]: Priority of system handler 15, SysTick exception */
-#define SCB_SHPR3_PRI_15_LSB 24
-/* PRI_14[23:16]: Priority of system handler 14, PendSV */
-#define SCB_SHPR3_PRI_14_LSB 16
-/* Bits [15:0]: reserved - must be kept cleared */
-
-/* --- SCB_SHCSR values ---------------------------------------------------- */
-
-/* Bits [31:19]: reserved - must be kept cleared */
-/* USGFAULTENA: Usage fault enable */
-#define SCB_SHCSR_USGFAULTENA (1 << 18)
-/* BUSFAULTENA: Bus fault enable */
-#define SCB_SHCSR_BUSFAULTENA (1 << 17)
-/* MEMFAULTENA: Memory management fault enable */
-#define SCB_SHCSR_MEMFAULTENA (1 << 16)
-/* SVCALLPENDED: SVC call pending */
-#define SCB_SHCSR_SVCALLPENDED (1 << 15)
-/* BUSFAULTPENDED: Bus fault exception pending */
-#define SCB_SHCSR_BUSFAULTPENDED (1 << 14)
-/* MEMFAULTPENDED: Memory management fault exception pending */
-#define SCB_SHCSR_MEMFAULTPENDED (1 << 13)
-/* USGFAULTPENDED: Usage fault exception pending */
-#define SCB_SHCSR_USGFAULTPENDED (1 << 12)
-/* SYSTICKACT: SysTick exception active */
-#define SCB_SHCSR_SYSTICKACT (1 << 11)
-/* PENDSVACT: PendSV exception active */
-#define SCB_SHCSR_PENDSVACT (1 << 10)
-/* Bit 9: reserved - must be kept cleared */
-/* MONITORACT: Debug monitor active */
-#define SCB_SHCSR_MONITORACT (1 << 8)
-/* SVCALLACT: SVC call active */
-#define SCB_SHCSR_SVCALLACT (1 << 7)
-/* Bits [6:4]: reserved - must be kept cleared */
-/* USGFAULTACT: Usage fault exception active */
-#define SCB_SHCSR_USGFAULTACT (1 << 3)
-/* Bit 2: reserved - must be kept cleared */
-/* BUSFAULTACT: Bus fault exception active */
-#define SCB_SHCSR_BUSFAULTACT (1 << 1)
-/* MEMFAULTACT: Memory management fault exception active */
-#define SCB_SHCSR_MEMFAULTACT (1 << 0)
-
-/* --- SCB_CFSR values ----------------------------------------------------- */
-
-/* Bits [31:26]: reserved - must be kept cleared */
-/* DIVBYZERO: Divide by zero usage fault */
-#define SCB_CFSR_DIVBYZERO (1 << 25)
-/* UNALIGNED: Unaligned access usage fault */
-#define SCB_CFSR_UNALIGNED (1 << 24)
-/* Bits [23:20]: reserved - must be kept cleared */
-/* NOCP: No coprocessor usage fault */
-#define SCB_CFSR_NOCP (1 << 19)
-/* INVPC: Invalid PC load usage fault */
-#define SCB_CFSR_INVPC (1 << 18)
-/* INVSTATE: Invalid state usage fault */
-#define SCB_CFSR_INVSTATE (1 << 17)
-/* UNDEFINSTR: Undefined instruction usage fault */
-#define SCB_CFSR_UNDEFINSTR (1 << 16)
-/* BFARVALID: Bus Fault Address Register (BFAR) valid flag */
-#define SCB_CFSR_BFARVALID (1 << 15)
-/* Bits [14:13]: reserved - must be kept cleared */
-/* STKERR: Bus fault on stacking for exception entry */
-#define SCB_CFSR_STKERR (1 << 12)
-/* UNSTKERR: Bus fault on unstacking for a return from exception */
-#define SCB_CFSR_UNSTKERR (1 << 11)
-/* IMPRECISERR: Imprecise data bus error */
-#define SCB_CFSR_IMPRECISERR (1 << 10)
-/* PRECISERR: Precise data bus error */
-#define SCB_CFSR_PRECISERR (1 << 9)
-/* IBUSERR: Instruction bus error */
-#define SCB_CFSR_IBUSERR (1 << 8)
-/* MMARVALID: Memory Management Fault Address Register (MMAR) valid flag */
-#define SCB_CFSR_MMARVALID (1 << 7)
-/* Bits [6:5]: reserved - must be kept cleared */
-/* MSTKERR: Memory manager fault on stacking for exception entry */
-#define SCB_CFSR_MSTKERR (1 << 4)
-/* MUNSTKERR: Memory manager fault on unstacking for a return from exception */
-#define SCB_CFSR_MUNSTKERR (1 << 3)
-/* Bit 2: reserved - must be kept cleared */
-/* DACCVIOL: Data access violation flag */
-#define SCB_CFSR_DACCVIOL (1 << 1)
-/* IACCVIOL: Instruction access violation flag */
-#define SCB_CFSR_IACCVIOL (1 << 0)
-
-/* --- SCB_HFSR values ----------------------------------------------------- */
-
-/* DEBUG_VT: reserved for debug use */
-#define SCB_HFSR_DEBUG_VT (1 << 31)
-/* FORCED: Forced hard fault */
-#define SCB_HFSR_FORCED (1 << 30)
-/* Bits [29:2]: reserved - must be kept cleared */
-/* VECTTBL: Vector table hard fault */
-#define SCB_HFSR_VECTTBL (1 << 1)
-/* Bit 0: reserved - must be kept cleared */
-
-/* --- SCB_MMFAR values ---------------------------------------------------- */
-
-/* MMFAR [31:0]: Memory management fault address */
-
-/* --- SCB_BFAR values ----------------------------------------------------- */
-
-/* BFAR [31:0]: Bus fault address */
-
-/* --- SCB_CPACR values ---------------------------------------------------- */
-
-/* CPACR CPn: Access privileges values */
-#define SCB_CPACR_NONE 0 /* Access denied */
-#define SCB_CPACR_PRIV 1 /* Privileged access only */
-#define SCB_CPACR_FULL 3 /* Full access */
-
-/* CPACR [20:21]: Access privileges for coprocessor 10 */
-#define SCB_CPACR_CP10 (1 << 20)
-/* CPACR [22:23]: Access privileges for coprocessor 11 */
-#define SCB_CPACR_CP11 (1 << 22)
-
-/* --- SCB functions ------------------------------------------------------- */
-
-BEGIN_DECLS
-
-void scb_reset_core(void);
-void scb_reset_system(void);
-void scb_set_priority_grouping(u32 prigroup);
-
-/* TODO: */
-
-END_DECLS
-
-#endif
diff --git a/include/libopencm3/stm32/f4/spi.h b/include/libopencm3/stm32/f4/spi.h
index c852a41..6589290 100644
--- a/include/libopencm3/stm32/f4/spi.h
+++ b/include/libopencm3/stm32/f4/spi.h
@@ -1,8 +1,21 @@
+/** @defgroup spi_defines SPI Defines
+
+@brief <b>Defined Constants and Types for the STM32F4xx SPI</b>
+
+@ingroup STM32F4xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 5 December 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
/*
* This file is part of the libopencm3 project.
*
- * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
- *
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
@@ -17,27 +30,11 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
-#ifndef LIBOPENCM3_SPI_F4_H
-#define LIBOPENCM3_SPI_F4_H
+#ifndef LIBOPENCM3_SPI_H
+#define LIBOPENCM3_SPI_H
-#include <libopencm3/stm32/spi.h>
-
-/*
- * This file extends the common STM32 version with definitions only
- * applicable to the STM32F4 series of devices.
- */
-
-/* --- SPI_CR2 values ------------------------------------------------------ */
-
-/* FRF: Frame format */
-/* Note: Not used in I2S mode. */
-#define SPI_CR2_FRF (1 << 4)
-#define SPI_CR2_FRF_MOTOROLA_MODE (0 << 4)
-#define SPI_CR2_FRF_TI_MODE (1 << 4)
-
-/* --- SPI_SR values ------------------------------------------------------- */
-
-/* TIFRFE: TI frame format error */
-#define SPI_SR_TIFRFE (1 << 8)
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/spi_common_f24.h>
#endif
+
diff --git a/include/libopencm3/stm32/f4/usart.h b/include/libopencm3/stm32/f4/usart.h
index ac113da..740f0a8 100644
--- a/include/libopencm3/stm32/f4/usart.h
+++ b/include/libopencm3/stm32/f4/usart.h
@@ -1,9 +1,21 @@
+/** @defgroup usart_defines USART Defines
+
+@brief <b>Defined Constants and Types for the STM32F4xx USART</b>
+
+@ingroup STM32F4xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 5 December 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
/*
* This file is part of the libopencm3 project.
*
- * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
- * Copyright (C) 2011 Stephen Caudle <scaudle@doceme.com>
- *
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
@@ -18,46 +30,11 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
-#ifndef LIBOPENCM3_USART_F4_H
-#define LIBOPENCM3_USART_F4_H
-
-#include <libopencm3/stm32/usart.h>
-
-/* --- Convenience macros -------------------------------------------------- */
-
-#define USART6 USART6_BASE
+#ifndef LIBOPENCM3_USART_H
+#define LIBOPENCM3_USART_H
-/* --- USART registers ----------------------------------------------------- */
-
-/* Status register (USARTx_SR) */
-#define USART6_SR USART_SR(USART6_BASE)
-
-/* Data register (USARTx_DR) */
-#define USART6_DR USART_DR(USART6_BASE)
-
-/* Baud rate register (USARTx_BRR) */
-#define USART6_BRR USART_BRR(USART6_BASE)
-
-/* Control register 1 (USARTx_CR1) */
-#define USART6_CR1 USART_CR1(USART6_BASE)
-
-/* Control register 2 (USARTx_CR2) */
-#define USART6_CR2 USART_CR2(USART6_BASE)
-
-/* Control register 3 (USARTx_CR3) */
-#define USART6_CR3 USART_CR3(USART6_BASE)
-
-/* Guard time and prescaler register (USARTx_GTPR) */
-#define USART6_GTPR USART_GTPR(USART6_BASE)
-
-/* --- USART_CR1 values ---------------------------------------------------- */
-
-/* OVER8: Oversampling mode */
-#define USART_CR1_OVER8 (1 << 15)
-
-/* --- USART_CR3 values ---------------------------------------------------- */
-
-/* ONEBIT: One sample bit method enable */
-#define USART_CR3_ONEBIT (1 << 11)
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/usart_common_f24.h>
#endif
+
diff --git a/include/libopencm3/stm32/gpio.h b/include/libopencm3/stm32/gpio.h
new file mode 100644
index 0000000..c106a09
--- /dev/null
+++ b/include/libopencm3/stm32/gpio.h
@@ -0,0 +1,31 @@
+/* This provides unification of code over STM32F subfamilies */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#if defined(STM32F1)
+# include <libopencm3/stm32/f1/gpio.h>
+#elif defined(STM32F2)
+# include <libopencm3/stm32/f2/gpio.h>
+#elif defined(STM32F4)
+# include <libopencm3/stm32/f4/gpio.h>
+#elif defined(STM32L1)
+# include <libopencm3/stm32/l1/gpio.h>
+#else
+# error "stm32 family not defined."
+#endif
+
diff --git a/include/libopencm3/stm32/i2c.h b/include/libopencm3/stm32/i2c.h
index a59c420..c1d0793 100644
--- a/include/libopencm3/stm32/i2c.h
+++ b/include/libopencm3/stm32/i2c.h
@@ -1,24 +1,8 @@
-/** @defgroup i2c_defines I2C Defines
-
-@ingroup STM32F_defines
-
-@brief <b>libopencm3 Defined Constants and Types for the STM32 I2C </b>
-
-@version 1.0.0
-
-@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
-@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
-
-@date 12 October 2012
-
-LGPL License Terms @ref lgpl_license
- */
+/* This provides unification of code over STM32F subfamilies */
/*
* This file is part of the libopencm3 project.
*
- * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
- *
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
@@ -33,344 +17,15 @@ LGPL License Terms @ref lgpl_license
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
-#ifndef LIBOPENCM3_I2C_H
-#define LIBOPENCM3_I2C_H
-
-#include <libopencm3/stm32/memorymap.h>
-#include <libopencm3/cm3/common.h>
-
-/**@{*/
-
-/* --- Convenience macros -------------------------------------------------- */
-
-/* I2C register base adresses (for convenience) */
-/****************************************************************************/
-/** @defgroup i2c_reg_base I2C register base address
-@ingroup i2c_defines
-
-@{*/
-#define I2C1 I2C1_BASE
-#define I2C2 I2C2_BASE
-/**@}*/
-
-/* --- I2C registers ------------------------------------------------------- */
-
-/* Control register 1 (I2Cx_CR1) */
-#define I2C_CR1(i2c_base) MMIO32(i2c_base + 0x00)
-#define I2C1_CR1 I2C_CR1(I2C1)
-#define I2C2_CR1 I2C_CR1(I2C2)
-
-/* Control register 2 (I2Cx_CR2) */
-#define I2C_CR2(i2c_base) MMIO32(i2c_base + 0x04)
-#define I2C1_CR2 I2C_CR2(I2C1)
-#define I2C2_CR2 I2C_CR2(I2C2)
-
-/* Own address register 1 (I2Cx_OAR1) */
-#define I2C_OAR1(i2c_base) MMIO32(i2c_base + 0x08)
-#define I2C1_OAR1 I2C_OAR1(I2C1)
-#define I2C2_OAR1 I2C_OAR1(I2C2)
-
-/* Own address register 2 (I2Cx_OAR2) */
-#define I2C_OAR2(i2c_base) MMIO32(i2c_base + 0x0c)
-#define I2C1_OAR2 I2C_OAR2(I2C1)
-#define I2C2_OAR2 I2C_OAR2(I2C2)
-
-/* Data register (I2Cx_DR) */
-#define I2C_DR(i2c_base) MMIO32(i2c_base + 0x10)
-#define I2C1_DR I2C_DR(I2C1)
-#define I2C2_DR I2C_DR(I2C2)
-
-/* Status register 1 (I2Cx_SR1) */
-#define I2C_SR1(i2c_base) MMIO32(i2c_base + 0x14)
-#define I2C1_SR1 I2C_SR1(I2C1)
-#define I2C2_SR1 I2C_SR1(I2C2)
-
-/* Status register 2 (I2Cx_SR2) */
-#define I2C_SR2(i2c_base) MMIO32(i2c_base + 0x18)
-#define I2C1_SR2 I2C_SR2(I2C1)
-#define I2C2_SR2 I2C_SR2(I2C2)
-
-/* Clock control register (I2Cx_CCR) */
-#define I2C_CCR(i2c_base) MMIO32(i2c_base + 0x1c)
-#define I2C1_CCR I2C_CCR(I2C1)
-#define I2C2_CCR I2C_CCR(I2C2)
-
-/* TRISE register (I2Cx_CCR) */
-#define I2C_TRISE(i2c_base) MMIO32(i2c_base + 0x20)
-#define I2C1_TRISE I2C_TRISE(I2C1)
-#define I2C2_TRISE I2C_TRISE(I2C2)
-
-/* --- I2Cx_CR1 values ----------------------------------------------------- */
-
-/* SWRST: Software reset */
-#define I2C_CR1_SWRST (1 << 15)
-
-/* Note: Bit 14 is reserved, and forced to 0 by hardware. */
-
-/* ALERT: SMBus alert */
-#define I2C_CR1_ALERT (1 << 13)
-
-/* PEC: Packet error checking */
-#define I2C_CR1_PEC (1 << 12)
-
-/* POS: Acknowledge / PEC postition */
-#define I2C_CR1_POS (1 << 11)
-
-/* ACK: Acknowledge enable */
-#define I2C_CR1_ACK (1 << 10)
-
-/* STOP: STOP generation */
-#define I2C_CR1_STOP (1 << 9)
-
-/* START: START generation */
-#define I2C_CR1_START (1 << 8)
-
-/* NOSTRETCH: Clock stretching disable (slave mode) */
-#define I2C_CR1_NOSTRETCH (1 << 7)
-
-/* ENGC: General call enable */
-#define I2C_CR1_ENGC (1 << 6)
-
-/* ENPEC: Enable PEC */
-#define I2C_CR1_ENPEC (1 << 5)
-
-/* ENARP: ARP enable */
-#define I2C_CR1_ENARP (1 << 4)
-
-/* SMBTYPE: SMBus type */
-#define I2C_CR1_SMBTYPE (1 << 3)
-
-/* Note: Bit 2 is reserved, and forced to 0 by hardware. */
-
-/* SMBUS: SMBus mode */
-#define I2C_CR1_SMBUS (1 << 1)
-
-/* PE: Peripheral enable */
-#define I2C_CR1_PE (1 << 0)
-
-/* --- I2Cx_CR2 values ----------------------------------------------------- */
-
-/* Note: Bits [15:13] are reserved, and forced to 0 by hardware. */
-
-/* LAST: DMA last transfer */
-#define I2C_CR2_LAST (1 << 12)
-
-/* DMAEN: DMA requests enable */
-#define I2C_CR2_DMAEN (1 << 11)
-
-/* ITBUFEN: Buffer interrupt enable */
-#define I2C_CR2_ITBUFEN (1 << 10)
-
-/* ITEVTEN: Event interrupt enable */
-#define I2C_CR2_ITEVTEN (1 << 9)
-
-/* ITERREN: Error interrupt enable */
-#define I2C_CR2_ITERREN (1 << 8)
-
-/* Note: Bits [7:6] are reserved, and forced to 0 by hardware. */
-
-/* FREQ[5:0]: Peripheral clock frequency (valid values: 2-36 MHz) */
-/****************************************************************************/
-/** @defgroup i2c_clock I2C clock frequency settings
-@ingroup i2c_defines
-
-@{*/
-#define I2C_CR2_FREQ_2MHZ 0x02
-#define I2C_CR2_FREQ_3MHZ 0x03
-#define I2C_CR2_FREQ_4MHZ 0x04
-#define I2C_CR2_FREQ_5MHZ 0x05
-#define I2C_CR2_FREQ_6MHZ 0x06
-#define I2C_CR2_FREQ_7MHZ 0x07
-#define I2C_CR2_FREQ_8MHZ 0x08
-#define I2C_CR2_FREQ_9MHZ 0x09
-#define I2C_CR2_FREQ_10MHZ 0x0a
-#define I2C_CR2_FREQ_11MHZ 0x0b
-#define I2C_CR2_FREQ_12MHZ 0x0c
-#define I2C_CR2_FREQ_13MHZ 0x0d
-#define I2C_CR2_FREQ_14MHZ 0x0e
-#define I2C_CR2_FREQ_15MHZ 0x0f
-#define I2C_CR2_FREQ_16MHZ 0x10
-#define I2C_CR2_FREQ_17MHZ 0x11
-#define I2C_CR2_FREQ_18MHZ 0x12
-#define I2C_CR2_FREQ_19MHZ 0x13
-#define I2C_CR2_FREQ_20MHZ 0x14
-#define I2C_CR2_FREQ_21MHZ 0x15
-#define I2C_CR2_FREQ_22MHZ 0x16
-#define I2C_CR2_FREQ_23MHZ 0x17
-#define I2C_CR2_FREQ_24MHZ 0x18
-#define I2C_CR2_FREQ_25MHZ 0x19
-#define I2C_CR2_FREQ_26MHZ 0x1a
-#define I2C_CR2_FREQ_27MHZ 0x1b
-#define I2C_CR2_FREQ_28MHZ 0x1c
-#define I2C_CR2_FREQ_29MHZ 0x1d
-#define I2C_CR2_FREQ_30MHZ 0x1e
-#define I2C_CR2_FREQ_31MHZ 0x1f
-#define I2C_CR2_FREQ_32MHZ 0x20
-#define I2C_CR2_FREQ_33MHZ 0x21
-#define I2C_CR2_FREQ_34MHZ 0x22
-#define I2C_CR2_FREQ_35MHZ 0x23
-#define I2C_CR2_FREQ_36MHZ 0x24
-/**@}*/
-
-/* --- I2Cx_OAR1 values ---------------------------------------------------- */
-
-/* ADDMODE: Addressing mode (slave mode) */
-#define I2C_OAR1_ADDMODE (1 << 15)
-#define I2C_OAR1_ADDMODE_7BIT 0
-#define I2C_OAR1_ADDMODE_10BIT 1
-
-/* Note: Bit 14 should always be kept at 1 by software! */
-
-/* Note: Bits [13:10] are reserved, and forced to 0 by hardware. */
-
-/* ADD: Address bits: [7:1] in 7-bit mode, bits [9:0] in 10-bit mode */
-
-/* --- I2Cx_OAR2 values ---------------------------------------------------- */
-
-/* Note: Bits [15:8] are reserved, and forced to 0 by hardware. */
-
-/* ADD2[7:1]: Interface address (bits [7:1] in dual addressing mode) */
-
-/* ENDUAL: Dual addressing mode enable */
-#define I2C_OAR2_ENDUAL (1 << 0)
-
-/* --- I2Cx_DR values ------------------------------------------------------ */
-
-/* Note: Bits [15:8] are reserved, and forced to 0 by hardware. */
-
-/* DR[7:0] 8-bit data register */
-
-/* --- I2Cx_SR1 values ----------------------------------------------------- */
-
-/* SMBALERT: SMBus alert */
-#define I2C_SR1_SMBALERT (1 << 15)
-
-/* TIMEOUT: Timeout or Tlow Error */
-#define I2C_SR1_TIMEOUT (1 << 14)
-
-/* Note: Bit 13 is reserved, and forced to 0 by hardware. */
-
-/* PECERR: PEC Error in reception */
-#define I2C_SR1_PECERR (1 << 12)
-
-/* OVR: Overrun/Underrun */
-#define I2C_SR1_OVR (1 << 11)
-
-/* AF: Acknowledge failure */
-#define I2C_SR1_AF (1 << 10)
-
-/* ARLO: Arbitration lost (master mode) */
-#define I2C_SR1_ARLO (1 << 9)
-
-/* BERR: Bus error */
-#define I2C_SR1_BERR (1 << 8)
-
-/* TxE: Data register empty (transmitters) */
-#define I2C_SR1_TxE (1 << 7)
-
-/* RxNE: Data register not empty (receivers) */
-#define I2C_SR1_RxNE (1 << 6)
-
-/* Note: Bit 5 is reserved, and forced to 0 by hardware. */
-
-/* STOPF: STOP detection (slave mode) */
-#define I2C_SR1_STOPF (1 << 4)
-
-/* ADD10: 10-bit header sent (master mode) */
-#define I2C_SR1_ADD10 (1 << 3)
-
-/* BTF: Byte transfer finished */
-#define I2C_SR1_BTF (1 << 2)
-
-/* ADDR: Address sent (master mode) / address matched (slave mode) */
-#define I2C_SR1_ADDR (1 << 1)
-
-/* SB: Start bit (master mode) */
-#define I2C_SR1_SB (1 << 0)
-
-/* --- I2Cx_SR2 values ----------------------------------------------------- */
-
-/* Bits [15:8]: PEC[7:0]: Packet error checking register */
-
-/* DUALF: Dual flag (slave mode) */
-#define I2C_SR2_DUALF (1 << 7)
-
-/* SMBHOST: SMBus host header (slave mode) */
-#define I2C_SR2_SMBHOST (1 << 6)
-
-/* SMBDEFAULT: SMBus device default address (slave mode) */
-#define I2C_SR2_SMBDEFAULT (1 << 5)
-
-/* GENCALL: General call address (slave mode) */
-#define I2C_SR2_GENCALL (1 << 4)
-
-/* Note: Bit 3 is reserved, and forced to 0 by hardware. */
-
-/* TRA: Transmitter / receiver */
-#define I2C_SR2_TRA (1 << 2)
-
-/* BUSY: Bus busy */
-#define I2C_SR2_BUSY (1 << 1)
-
-/* MSL: Master / slave */
-#define I2C_SR2_MSL (1 << 0)
-
-/* --- I2Cx_CCR values ----------------------------------------------------- */
-
-/* F/S: I2C Master mode selection (fast / standard) */
-#define I2C_CCR_FS (1 << 15)
-
-/* DUTY: Fast Mode Duty Cycle */
-#define I2C_CCR_DUTY (1 << 14)
-
-/* Note: Bits [13:12] are reserved, and forced to 0 by hardware. */
-
-/*
- * Bits [11:0]:
- * CCR[11:0]: Clock control register in Fast/Standard mode (master mode)
- */
-
-/* --- I2Cx_TRISE values --------------------------------------------------- */
-
-/* Note: Bits [15:6] are reserved, and forced to 0 by hardware. */
-
-/*
- * Bits [5:0]:
- * TRISE[5:0]: Maximum rise time in Fast/Standard mode (master mode)
- */
-
-/* --- I2C const definitions ----------------------------------------------- */
-
-/****************************************************************************/
-/** @defgroup i2c_rw I2C Read/Write bit
-@ingroup i2c_defines
-
-@{*/
-#define I2C_WRITE 0
-#define I2C_READ 1
-/**@}*/
-
-/* --- I2C funtion prototypes----------------------------------------------- */
-
-BEGIN_DECLS
-
-void i2c_reset(u32 i2c);
-void i2c_peripheral_enable(u32 i2c);
-void i2c_peripheral_disable(u32 i2c);
-void i2c_send_start(u32 i2c);
-void i2c_send_stop(u32 i2c);
-void i2c_set_own_7bit_slave_address(u32 i2c, u8 slave);
-void i2c_set_own_10bit_slave_address(u32 i2c, u16 slave);
-void i2c_set_fast_mode(u32 i2c);
-void i2c_set_standard_mode(u32 i2c);
-void i2c_set_clock_frequency(u32 i2c, u8 freq);
-void i2c_set_ccr(u32 i2c, u16 freq);
-void i2c_set_trise(u32 i2c, u16 trise);
-void i2c_send_7bit_address(u32 i2c, u8 slave, u8 readwrite);
-void i2c_send_data(u32 i2c, u8 data);
-
-END_DECLS
-
+#if defined(STM32F1)
+# include <libopencm3/stm32/f1/i2c.h>
+#elif defined(STM32F2)
+# include <libopencm3/stm32/f2/i2c.h>
+#elif defined(STM32F4)
+# include <libopencm3/stm32/f4/i2c.h>
+#elif defined(STM32L1)
+# include <libopencm3/stm32/l1/i2c.h>
+#else
+# error "stm32 family not defined."
#endif
-/**@}*/
diff --git a/include/libopencm3/stm32/iwdg.h b/include/libopencm3/stm32/iwdg.h
index 4e44907..60bbd9e 100644
--- a/include/libopencm3/stm32/iwdg.h
+++ b/include/libopencm3/stm32/iwdg.h
@@ -1,22 +1,8 @@
-/** @defgroup STM32F_iwdg_defines IWDG Defines
+/* This provides unification of code over STM32F subfamilies */
-@brief <b>libopencm3 Defined Constants and Types for the STM32F Independent Watchdog Timer</b>
-
-@ingroup STM32F_defines
-
-@version 1.0.0
-
-@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
-
-@date 18 August 2012
-
-LGPL License Terms @ref lgpl_license
- */
/*
* This file is part of the libopencm3 project.
*
- * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
- *
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
@@ -31,91 +17,15 @@ LGPL License Terms @ref lgpl_license
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
-/**@{*/
-
-#ifndef LIBOPENCM3_IWDG_H
-#define LIBOPENCM3_IWDG_H
-
-#include <libopencm3/stm32/memorymap.h>
-#include <libopencm3/cm3/common.h>
-
-/* --- IWDG registers ------------------------------------------------------ */
-
-/* Key Register (IWDG_KR) */
-#define IWDG_KR MMIO32(IWDG_BASE + 0x00)
-
-/* Prescaler register (IWDG_PR) */
-#define IWDG_PR MMIO32(IWDG_BASE + 0x04)
-
-/* Reload register (IWDG_RLR) */
-#define IWDG_RLR MMIO32(IWDG_BASE + 0x08)
-
-/* Status register (IWDG_SR) */
-#define IWDG_SR MMIO32(IWDG_BASE + 0x0c)
-
-/* --- IWDG_KR values ------------------------------------------------------ */
-
-/* Bits [31:16]: Reserved. */
-
-/* KEY[15:0]: Key value (write-only, reads as 0x0000) */
-/** @defgroup iwdg_key IWDG Key Values
-@ingroup STM32F_iwdg_defines
-
-@{*/
-#define IWDG_KR_RESET 0xaaaa
-#define IWDG_KR_UNLOCK 0x5555
-#define IWDG_KR_START 0xcccc
-/**@}*/
-
-/* --- IWDG_PR values ------------------------------------------------------ */
-
-/* Bits [31:3]: Reserved. */
-
-/* PR[2:0]: Prescaler divider */
-#define IWDG_PR_LSB 0
-/** @defgroup iwdg_prediv IWDG Prescaler divider
-@ingroup STM32F_iwdg_defines
-
-@{*/
-#define IWDG_PR_DIV4 0x0
-#define IWDG_PR_DIV8 0x1
-#define IWDG_PR_DIV16 0x2
-#define IWDG_PR_DIV32 0x3
-#define IWDG_PR_DIV64 0x4
-#define IWDG_PR_DIV128 0x5
-#define IWDG_PR_DIV256 0x6
-/**@}*/
-/* Double definition: 0x06 and 0x07 both mean DIV256 as per datasheet. */
-/* #define IWDG_PR_DIV256 0x7 */
-
-/* --- IWDG_RLR values ----------------------------------------------------- */
-
-/* Bits [31:12]: Reserved. */
-
-/* RL[11:0]: Watchdog counter reload value */
-
-/* --- IWDG_SR values ------------------------------------------------------ */
-
-/* Bits [31:2]: Reserved. */
-
-/* RVU: Watchdog counter reload value update */
-#define IWDG_SR_RVU (1 << 1)
-
-/* PVU: Watchdog prescaler value update */
-#define IWDG_SR_PVU (1 << 0)
-
-/* --- IWDG function prototypes---------------------------------------------- */
-
-BEGIN_DECLS
-
-void iwdg_start(void);
-void iwdg_set_period_ms(u32 period);
-bool iwdg_reload_busy(void);
-bool iwdg_prescaler_busy(void);
-void iwdg_reset(void);
-
-END_DECLS
-
+#if defined(STM32F1)
+# include <libopencm3/stm32/f1/iwdg.h>
+#elif defined(STM32F2)
+# include <libopencm3/stm32/f2/iwdg.h>
+#elif defined(STM32F4)
+# include <libopencm3/stm32/f4/iwdg.h>
+#elif defined(STM32L1)
+# include <libopencm3/stm32/l1/iwdg.h>
+#else
+# error "stm32 family not defined."
#endif
-/**@}*/
diff --git a/include/libopencm3/stm32/l1/crc.h b/include/libopencm3/stm32/l1/crc.h
new file mode 100644
index 0000000..07370f2
--- /dev/null
+++ b/include/libopencm3/stm32/l1/crc.h
@@ -0,0 +1,40 @@
+/** @defgroup crc_defines CRC Defines
+
+@brief <b>libopencm3 Defined Constants and Types for the STM32L1xx CRC Generator </b>
+
+@ingroup STM32L1xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
+
+@date 18 August 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_CRC_H
+#define LIBOPENCM3_CRC_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/crc_common_all.h>
+
+#endif
diff --git a/include/libopencm3/stm32/l1/dac.h b/include/libopencm3/stm32/l1/dac.h
new file mode 100644
index 0000000..7f7ea52
--- /dev/null
+++ b/include/libopencm3/stm32/l1/dac.h
@@ -0,0 +1,40 @@
+/** @defgroup dac_defines DAC Defines
+
+@brief <b>Defined Constants and Types for the STM32L1xx DAC</b>
+
+@ingroup STM32L1xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 5 December 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_DAC_H
+#define LIBOPENCM3_DAC_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/dac_common_all.h>
+
+#endif
+
diff --git a/include/libopencm3/stm32/l1/doc-stm32l1.h b/include/libopencm3/stm32/l1/doc-stm32l1.h
new file mode 100644
index 0000000..96bea00
--- /dev/null
+++ b/include/libopencm3/stm32/l1/doc-stm32l1.h
@@ -0,0 +1,32 @@
+/** @mainpage libopencm3 STM32L1
+
+@version 1.0.0
+
+@date 12 November 2012
+
+API documentation for ST Microelectronics STM32L1 Cortex M3 series.
+
+LGPL License Terms @ref lgpl_license
+*/
+
+/** @defgroup STM32L1xx STM32L1xx
+Libraries for ST Microelectronics STM32L1xx series.
+
+@version 1.0.0
+
+@date 12 November 2012
+
+LGPL License Terms @ref lgpl_license
+*/
+
+/** @defgroup STM32L1xx_defines STM32L1xx Defines
+
+@brief Defined Constants and Types for the STM32L1xx series
+
+@version 1.0.0
+
+@date 12 November 2012
+
+LGPL License Terms @ref lgpl_license
+*/
+
diff --git a/include/libopencm3/stm32/l1/flash.h b/include/libopencm3/stm32/l1/flash.h
new file mode 100644
index 0000000..724fec9
--- /dev/null
+++ b/include/libopencm3/stm32/l1/flash.h
@@ -0,0 +1,125 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
+ * Copyright (C) 2010 Mark Butler <mbutler@physics.otago.ac.nz>
+ * Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/*
+ * All extracted from PM0062 rev2, L15xx and L16xx Flash/EEPROM programming manual
+ */
+
+#ifndef LIBOPENCM3_FLASH_H
+#define LIBOPENCM3_FLASH_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/* --- FLASH registers ----------------------------------------------------- */
+
+#define FLASH_ACR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x00)
+#define FLASH_PECR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x04)
+#define FLASH_PDKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x08)
+#define FLASH_PEKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x0C)
+#define FLASH_PRGKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x10)
+#define FLASH_OPTKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14)
+#define FLASH_SR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x18)
+#define FLASH_OBR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x1c)
+#define FLASH_WRPR1 MMIO32(FLASH_MEM_INTERFACE_BASE + 0x20)
+#define FLASH_WRPR2 MMIO32(FLASH_MEM_INTERFACE_BASE + 0x80)
+#define FLASH_WRPR3 MMIO32(FLASH_MEM_INTERFACE_BASE + 0x84)
+
+/* --- FLASH_ACR values ---------------------------------------------------- */
+
+#define FLASH_ACR_RUNPD (1 << 4)
+#define FLASH_ACR_SLEEPPD (1 << 3)
+#define FLASH_ACR_ACC64 (1 << 2)
+#define FLASH_ACR_PRFTEN (1 << 1)
+#define FLASH_ACR_LATENCY_0WS 0x00
+#define FLASH_ACR_LATENCY_1WS 0x01
+
+/* --- FLASH_PECR values. Program/erase control register */
+#define FLASH_PECR_OBL_LAUNCH (1 << 18)
+#define FLASH_PECR_ERRIE (1 << 17)
+#define FLASH_PECR_EOPIE (1 << 16)
+#define FLASH_PECR_PARALLBANK (1 << 15)
+#define FLASH_PECR_FPRG (1 << 10)
+#define FLASH_PECR_ERASE (1 << 9)
+#define FLASH_PECR_FTDW (1 << 8)
+#define FLASH_PECR_FTDW (1 << 8)
+#define FLASH_PECR_DATA (1 << 4)
+#define FLASH_PECR_PROG (1 << 3)
+#define FLASH_PECR_OPTLOCK (1 << 2)
+#define FLASH_PECR_PRGLOCK (1 << 1)
+#define FLASH_PECR_PELOCK (1 << 0)
+
+/* Power down key register (FLASH_PDKEYR) */
+#define FLASH_PDKEYR_PDKEY1 ((u32)0x04152637)
+#define FLASH_PDKEYR_PDKEY2 ((u32)0xFAFBFCFD)
+
+/* Program/erase key register (FLASH_PEKEYR) */
+#define FLASH_PEKEYR_PEKEY1 ((u32)0x89ABCDEF)
+#define FLASH_PEKEYR_PEKEY2 ((u32)0x02030405)
+
+/* Program memory key register (FLASH_PRGKEYR) */
+#define FLASH_PRGKEYR_PRGKEY1 ((u32)0x8C9DAEBF)
+#define FLASH_PRGKEYR_PRGKEY2 ((u32)0x13141516)
+
+/* Option byte key register (FLASH_OPTKEYR) */
+#define FLASH_OPTKEYR_OPTKEY1 ((u32)0xFBEAD9C8)
+#define FLASH_OPTKEYR_OPTKEY2 ((u32)0x24252627)
+
+
+/* --- FLASH_SR values ----------------------------------------------------- */
+#define FLASH_SR_OPTVERRUSR (1 << 12)
+#define FLASH_SR_OPTVERR (1 << 11)
+#define FLASH_SR_SIZEERR (1 << 10)
+#define FLASH_SR_PGAERR (1 << 9)
+#define FLASH_SR_WRPERR (1 << 8)
+#define FLASH_SR_READY (1 << 3)
+#define FLASH_SR_ENDHV (1 << 2)
+#define FLASH_SR_EOP (1 << 1)
+#define FLASH_SR_BSY (1 << 0)
+
+/* --- FLASH_OBR values ----------------------------------------------------- */
+#define FLASH_OBR_BFB2 (1 << 23)
+#define FLASH_OBR_NRST_STDBY (1 << 22)
+#define FLASH_OBR_NRST_STOP (1 << 21)
+#define FLASH_OBR_IWDG_SW (1 << 20)
+#define FLASH_OBR_BOR_OFF (0x0 << 16)
+#define FLASH_OBR_BOR_LEVEL_1 (0x8 << 16)
+#define FLASH_OBR_BOR_LEVEL_2 (0x9 << 16)
+#define FLASH_OBR_BOR_LEVEL_3 (0xa << 16)
+#define FLASH_OBR_BOR_LEVEL_4 (0xb << 16)
+#define FLASH_OBR_BOR_LEVEL_5 (0xc << 16)
+#define FLASH_OBR_RDPRT_LEVEL_0 (0xaa)
+#define FLASH_OBR_RDPRT_LEVEL_1 (0x00)
+#define FLASH_OBR_RDPRT_LEVEL_2 (0xcc)
+
+/* --- Function prototypes ------------------------------------------------- */
+
+BEGIN_DECLS
+
+void flash_64bit_enable(void);
+void flash_64bit_disable(void);
+void flash_prefetch_enable(void);
+void flash_prefetch_disable(void);
+void flash_set_ws(u32 ws);
+
+END_DECLS
+
+#endif
diff --git a/include/libopencm3/stm32/l1/gpio.h b/include/libopencm3/stm32/l1/gpio.h
new file mode 100644
index 0000000..93850a2
--- /dev/null
+++ b/include/libopencm3/stm32/l1/gpio.h
@@ -0,0 +1,266 @@
+/** @defgroup gpio_defines GPIO Defines
+
+@brief <b>Defined Constants and Types for the STM32L1xx General Purpose I/O</b>
+
+@ingroup STM32L1xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
+@author @htmlonly &copy; @endhtmlonly 2012 Piotr Esden-Tempski <piotr@esden.net>
+@author @htmlonly &copy; @endhtmlonly 2012 Karl Palsson <karlp@tweak.net.au>
+
+@date 1 July 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+ * Copyright (C) 2012 Piotr Esden-Tempski <piotr@esden.net>
+ * Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/**@{*/
+
+#ifndef LIBOPENCM3_GPIO_H
+#define LIBOPENCM3_GPIO_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/gpio_common_all.h>
+
+/* --- Convenience macros -------------------------------------------------- */
+
+/* GPIO port base addresses (for convenience) */
+/* GPIO port base addresses (for convenience) */
+/** @defgroup gpio_port_id GPIO Port IDs
+@ingroup gpio_defines
+
+@{*/
+#define GPIOA GPIO_PORT_A_BASE
+#define GPIOB GPIO_PORT_B_BASE
+#define GPIOC GPIO_PORT_C_BASE
+#define GPIOD GPIO_PORT_D_BASE
+#define GPIOE GPIO_PORT_E_BASE
+#define GPIOH GPIO_PORT_H_BASE
+/**@}*/
+
+/* --- GPIO registers ------------------------------------------------------ */
+
+/* Port mode register (GPIOx_MODER) */
+#define GPIO_MODER(port) MMIO32(port + 0x00)
+#define GPIOA_MODER GPIO_MODER(GPIOA)
+#define GPIOB_MODER GPIO_MODER(GPIOB)
+#define GPIOC_MODER GPIO_MODER(GPIOC)
+#define GPIOD_MODER GPIO_MODER(GPIOD)
+#define GPIOE_MODER GPIO_MODER(GPIOE)
+#define GPIOH_MODER GPIO_MODER(GPIOH)
+
+/* Port output type register (GPIOx_OTYPER) */
+#define GPIO_OTYPER(port) MMIO32(port + 0x04)
+#define GPIOA_OTYPER GPIO_OTYPER(GPIOA)
+#define GPIOB_OTYPER GPIO_OTYPER(GPIOB)
+#define GPIOC_OTYPER GPIO_OTYPER(GPIOC)
+#define GPIOD_OTYPER GPIO_OTYPER(GPIOD)
+#define GPIOE_OTYPER GPIO_OTYPER(GPIOE)
+#define GPIOH_OTYPER GPIO_OTYPER(GPIOH)
+
+/* Port output speed register (GPIOx_OSPEEDR) */
+#define GPIO_OSPEEDR(port) MMIO32(port + 0x08)
+#define GPIOA_OSPEEDR GPIO_OSPEEDR(GPIOA)
+#define GPIOB_OSPEEDR GPIO_OSPEEDR(GPIOB)
+#define GPIOC_OSPEEDR GPIO_OSPEEDR(GPIOC)
+#define GPIOD_OSPEEDR GPIO_OSPEEDR(GPIOD)
+#define GPIOE_OSPEEDR GPIO_OSPEEDR(GPIOE)
+#define GPIOH_OSPEEDR GPIO_OSPEEDR(GPIOH)
+
+/* Port pull-up/pull-down register (GPIOx_PUPDR) */
+#define GPIO_PUPDR(port) MMIO32(port + 0x0c)
+#define GPIOA_PUPDR GPIO_PUPDR(GPIOA)
+#define GPIOB_PUPDR GPIO_PUPDR(GPIOB)
+#define GPIOC_PUPDR GPIO_PUPDR(GPIOC)
+#define GPIOD_PUPDR GPIO_PUPDR(GPIOD)
+#define GPIOE_PUPDR GPIO_PUPDR(GPIOE)
+#define GPIOH_PUPDR GPIO_PUPDR(GPIOH)
+
+/* Port input data register (GPIOx_IDR) */
+#define GPIO_IDR(port) MMIO32(port + 0x10)
+#define GPIOA_IDR GPIO_IDR(GPIOA)
+#define GPIOB_IDR GPIO_IDR(GPIOB)
+#define GPIOC_IDR GPIO_IDR(GPIOC)
+#define GPIOD_IDR GPIO_IDR(GPIOD)
+#define GPIOE_IDR GPIO_IDR(GPIOE)
+#define GPIOH_IDR GPIO_IDR(GPIOH)
+
+/* Port output data register (GPIOx_ODR) */
+#define GPIO_ODR(port) MMIO32(port + 0x14)
+#define GPIOA_ODR GPIO_ODR(GPIOA)
+#define GPIOB_ODR GPIO_ODR(GPIOB)
+#define GPIOC_ODR GPIO_ODR(GPIOC)
+#define GPIOD_ODR GPIO_ODR(GPIOD)
+#define GPIOE_ODR GPIO_ODR(GPIOE)
+#define GPIOH_ODR GPIO_ODR(GPIOH)
+
+/* Port bit set/reset register (GPIOx_BSRR) */
+#define GPIO_BSRR(port) MMIO32(port + 0x18)
+#define GPIOA_BSRR GPIO_BSRR(GPIOA)
+#define GPIOB_BSRR GPIO_BSRR(GPIOB)
+#define GPIOC_BSRR GPIO_BSRR(GPIOC)
+#define GPIOD_BSRR GPIO_BSRR(GPIOD)
+#define GPIOE_BSRR GPIO_BSRR(GPIOE)
+#define GPIOH_BSRR GPIO_BSRR(GPIOH)
+
+/* Port configuration lock register (GPIOx_LCKR) */
+#define GPIO_LCKR(port) MMIO32(port + 0x1C)
+#define GPIOA_LCKR GPIO_LCKR(GPIOA)
+#define GPIOB_LCKR GPIO_LCKR(GPIOB)
+#define GPIOC_LCKR GPIO_LCKR(GPIOC)
+#define GPIOD_LCKR GPIO_LCKR(GPIOD)
+#define GPIOE_LCKR GPIO_LCKR(GPIOE)
+#define GPIOH_LCKR GPIO_LCKR(GPIOH)
+
+/* Alternate function low register (GPIOx_AFRL) */
+#define GPIO_AFRL(port) MMIO32(port + 0x20)
+#define GPIOA_AFRL GPIO_AFRL(GPIOA)
+#define GPIOB_AFRL GPIO_AFRL(GPIOB)
+#define GPIOC_AFRL GPIO_AFRL(GPIOC)
+#define GPIOD_AFRL GPIO_AFRL(GPIOD)
+#define GPIOE_AFRL GPIO_AFRL(GPIOE)
+#define GPIOH_AFRL GPIO_AFRL(GPIOH)
+
+/* Alternate function high register (GPIOx_AFRH) */
+#define GPIO_AFRH(port) MMIO32(port + 0x24)
+#define GPIOA_AFRH GPIO_AFRH(GPIOA)
+#define GPIOB_AFRH GPIO_AFRH(GPIOB)
+#define GPIOC_AFRH GPIO_AFRH(GPIOC)
+#define GPIOD_AFRH GPIO_AFRH(GPIOD)
+#define GPIOE_AFRH GPIO_AFRH(GPIOE)
+#define GPIOH_AFRH GPIO_AFRH(GPIOH)
+
+/* --- GPIOx_MODER values-------------------------------------------- */
+
+#define GPIO_MODE(n, mode) (mode << (2 * (n)))
+#define GPIO_MODE_MASK(n) (0x3 << (2 * (n)))
+/** @defgroup gpio_mode GPIO Pin Direction and Analog/Digital Mode
+@ingroup gpio_defines
+@{*/
+#define GPIO_MODE_INPUT 0x00 /* Default */
+#define GPIO_MODE_OUTPUT 0x01
+#define GPIO_MODE_AF 0x02
+#define GPIO_MODE_ANALOG 0x03
+/**@}*/
+
+/* --- GPIOx_OTYPER values -------------------------------------------- */
+/* Output type (OTx values) */
+/** @defgroup gpio_output_type GPIO Output Pin Driver Type
+@ingroup gpio_defines
+@list Push Pull
+@list Open Drain
+@{*/
+#define GPIO_OTYPE_PP 0x0
+#define GPIO_OTYPE_OD 0x1
+/**@}*/
+
+/* Output speed values */
+#define GPIO_OSPEED(n, speed) (speed << (2 * (n)))
+#define GPIO_OSPEED_MASK(n) (0x3 << (2 * (n)))
+/** @defgroup gpio_speed GPIO Output Pin Speed
+@ingroup gpio_defines
+@{*/
+#define GPIO_OSPEED_400KHZ 0x0
+#define GPIO_OSPEED_2MHZ 0x1
+#define GPIO_OSPEED_10MHZ 0x2
+#define GPIO_OSPEED_40MHZ 0x3
+/**@}*/
+
+/* --- GPIOx_PUPDR values ------------------------------------------- */
+
+#define GPIO_PUPD(n, pupd) (pupd << (2 * (n)))
+#define GPIO_PUPD_MASK(n) (0x3 << (2 * (n)))
+/** @defgroup gpio_pup GPIO Output Pin Pullup
+@ingroup gpio_defines
+@{*/
+#define GPIO_PUPD_NONE 0x0
+#define GPIO_PUPD_PULLUP 0x1
+#define GPIO_PUPD_PULLDOWN 0x2
+/**@}*/
+
+/* --- GPIO_IDR values ----------------------------------------------------- */
+
+/* GPIO_IDR[15:0]: IDRy[15:0]: Port input data (y = 0..15) */
+
+/* --- GPIO_ODR values ----------------------------------------------------- */
+
+/* GPIO_ODR[15:0]: ODRy[15:0]: Port output data (y = 0..15) */
+
+/* --- GPIO_BSRR values ---------------------------------------------------- */
+
+/* GPIO_BSRR[31:16]: BRy: Port x reset bit y (y = 0..15) */
+/* GPIO_BSRR[15:0]: BSy: Port x set bit y (y = 0..15) */
+
+/* --- GPIO_LCKR values ---------------------------------------------------- */
+
+#define GPIO_LCKK (1 << 16)
+/* GPIO_LCKR[15:0]: LCKy: Port x lock bit y (y = 0..15) */
+
+/* --- GPIOx_AFRL/H values ------------------------------------------------- */
+
+/* Note: AFRL is used for bits 0..7, AFRH is used for 8..15 */
+/* See datasheet table 5, page 35 for the definitions */
+
+#define GPIO_AFR(n, af) (af << ((n) * 4))
+#define GPIO_AFR_MASK(n) (0xf << ((n) * 4))
+/** @defgroup gpio_af_num Alternate Function Pin Selection
+@ingroup gpio_defines
+@{*/
+#define GPIO_AF0 0x0
+#define GPIO_AF1 0x1
+#define GPIO_AF2 0x2
+#define GPIO_AF3 0x3
+#define GPIO_AF4 0x4
+#define GPIO_AF5 0x5
+#define GPIO_AF6 0x6
+#define GPIO_AF7 0x7
+#define GPIO_AF8 0x8
+#define GPIO_AF9 0x9
+#define GPIO_AF10 0xa
+#define GPIO_AF11 0xb
+#define GPIO_AF12 0xc
+#define GPIO_AF13 0xd
+#define GPIO_AF14 0xe
+#define GPIO_AF15 0xf
+/**@}*/
+
+/* --- Function prototypes ------------------------------------------------- */
+
+BEGIN_DECLS
+
+/*
+ * L1, like F2 and F4, has the "new" GPIO peripheral, so use that style
+ * however the number of ports is reduced and H port naming is different.
+ * TODO: this should all really be moved to a "common" gpio header
+ */
+
+void gpio_mode_setup(u32 gpioport, u8 mode, u8 pull_up_down, u16 gpios);
+void gpio_set_output_options(u32 gpioport, u8 otype, u8 speed, u16 gpios);
+void gpio_set_af(u32 gpioport, u8 alt_func_num, u16 gpios);
+
+END_DECLS
+
+#endif
+/**@}*/
+
diff --git a/include/libopencm3/stm32/l1/i2c.h b/include/libopencm3/stm32/l1/i2c.h
new file mode 100644
index 0000000..1fd419d
--- /dev/null
+++ b/include/libopencm3/stm32/l1/i2c.h
@@ -0,0 +1,41 @@
+/** @defgroup i2c_defines I2C Defines
+
+@brief <b>Defined Constants and Types for the STM32L1xx I2C </b>
+
+@ingroup STM32L1xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 12 October 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_I2C_H
+#define LIBOPENCM3_I2C_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/i2c_common_all.h>
+
+#endif
+
diff --git a/include/libopencm3/stm32/l1/irq.yaml b/include/libopencm3/stm32/l1/irq.yaml
new file mode 100644
index 0000000..a10e96c
--- /dev/null
+++ b/include/libopencm3/stm32/l1/irq.yaml
@@ -0,0 +1,62 @@
+includeguard: LIBOPENCM3_STM32_L1_NVIC_H
+partname_humanreadable: STM32 L1 series
+partname_doxygen: STM32L1
+irqs:
+ - wwdg
+ - pvd
+ - tamper_stamp
+ - rtc_wkup
+ - flash
+ - rcc
+ - exti0
+ - exti1
+ - exti2
+ - exti3
+ - exti4
+ - dma1_channel1
+ - dma1_channel2
+ - dma1_channel3
+ - dma1_channel4
+ - dma1_channel5
+ - dma1_channel6
+ - dma1_channel7
+ - adc1
+ - usb_hp
+ - usb_lp
+ - dac
+ - comp
+ - exti9_5
+ - lcd
+ - tim9
+ - tim10
+ - tim11
+ - tim2
+ - tim3
+ - tim4
+ - i2c1_ev
+ - i2c1_er
+ - i2c2_ev
+ - i2c2_er
+ - spi1
+ - spi2
+ - usart1
+ - usart2
+ - usart3
+ - exti15_10
+ - rtc_alarm
+ - usb_fs_wakeup
+ - tim6
+ - tim7
+ # below here is medium+/high density
+ - sdio
+ - tim5
+ - spi3
+ - uart4
+ - uart5
+ - dma2_ch1
+ - dma2_ch2
+ - dma2_ch3
+ - dma2_ch4
+ - dma2_ch5
+ - aes
+ - comp_acq \ No newline at end of file
diff --git a/include/libopencm3/stm32/l1/iwdg.h b/include/libopencm3/stm32/l1/iwdg.h
new file mode 100644
index 0000000..8ba6c44
--- /dev/null
+++ b/include/libopencm3/stm32/l1/iwdg.h
@@ -0,0 +1,41 @@
+/** @defgroup iwdg_defines IWDG Defines
+
+@brief <b>Defined Constants and Types for the STM32L1xx Independent Watchdog Timer</b>
+
+@ingroup STM32L1xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
+
+@date 18 August 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_IWDG_H
+#define LIBOPENCM3_IWDG_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/iwdg_common_all.h>
+
+#endif
+
diff --git a/include/libopencm3/stm32/l1/memorymap.h b/include/libopencm3/stm32/l1/memorymap.h
new file mode 100644
index 0000000..60f1c57
--- /dev/null
+++ b/include/libopencm3/stm32/l1/memorymap.h
@@ -0,0 +1,116 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+ * Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_MEMORYMAP_H
+#define LIBOPENCM3_MEMORYMAP_H
+
+#include <libopencm3/cm3/memorymap.h>
+
+/* --- STM32 specific peripheral definitions ------------------------------- */
+
+/* Memory map for all busses */
+#define PERIPH_BASE ((u32)0x40000000)
+#define INFO_BASE ((u32)0x1ff00000)
+#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)
+#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)
+#define PERIPH_BASE_AHB (PERIPH_BASE + 0x20000)
+
+/* Register boundary addresses */
+
+/* APB1 */
+#define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000)
+#define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400)
+#define TIM4_BASE (PERIPH_BASE_APB1 + 0x0800)
+#define TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00)
+#define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000)
+#define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400)
+#define LCD_BASE (PERIPH_BASE_APB1 + 0x2400)
+#define RTC_BASE (PERIPH_BASE_APB1 + 0x2800)
+#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00)
+#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000)
+/* PERIPH_BASE_APB1 + 0x3400 (0x4000 3400 - 0x4000 37FF): Reserved */
+#define SPI2_BASE (PERIPH_BASE_APB1 + 0x3800)
+#define SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00)
+/* PERIPH_BASE_APB1 + 0x4000 (0x4000 4000 - 0x4000 3FFF): Reserved */
+#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400)
+#define USART3_BASE (PERIPH_BASE_APB1 + 0x4800)
+#define USART4_BASE (PERIPH_BASE_APB1 + 0x4c00)
+#define USART5_BASE (PERIPH_BASE_APB1 + 0x5000)
+#define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400)
+#define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800)
+#define USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x5c00)
+#define USB_SRAM_BASE (PERIPH_BASE_APB1 + 0x6000)
+/* gap */
+#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)
+#define DAC_BASE (PERIPH_BASE_APB1 + 0x7400)
+#define OPAMP_BASE (PERIPH_BASE_APB1 + 0x7c5c)
+#define COMP_BASE (PERIPH_BASE_APB1 + 0x7c00)
+#define ROUTING_BASE (PERIPH_BASE_APB1 + 0x7c04)
+
+/* APB2 */
+#define SYSCFG_BASE (PERIPH_BASE_APB2 + 0x0000)
+#define EXTI_BASE (PERIPH_BASE_APB2 + 0x0400)
+#define TIM9_BASE (PERIPH_BASE_APB2 + 0x0800)
+#define TIM10_BASE (PERIPH_BASE_APB2 + 0x0c00)
+#define TIM11_BASE (PERIPH_BASE_APB2 + 0x1000)
+/* gap */
+#define ADC_BASE (PERIPH_BASE_APB2 + 0x2400)
+/* gap */
+#define SDIO_BASE (PERIPH_BASE_APB2 + 0x2c00)
+#define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000)
+/* gap */
+#define USART1_BASE (PERIPH_BASE_APB2 + 0x3800)
+
+/* AHB */
+#define GPIO_PORT_A_BASE (PERIPH_BASE_AHB + 0x00000)
+#define GPIO_PORT_B_BASE (PERIPH_BASE_AHB + 0x00400)
+#define GPIO_PORT_C_BASE (PERIPH_BASE_AHB + 0x00800)
+#define GPIO_PORT_D_BASE (PERIPH_BASE_AHB + 0x00c00)
+#define GPIO_PORT_E_BASE (PERIPH_BASE_AHB + 0x01000)
+#define GPIO_PORT_H_BASE (PERIPH_BASE_AHB + 0x01400)
+#define GPIO_PORT_F_BASE (PERIPH_BASE_AHB + 0x01800)
+#define GPIO_PORT_G_BASE (PERIPH_BASE_AHB + 0x01c00)
+/* gap */
+#define CRC_BASE (PERIPH_BASE_AHB + 0x03000)
+/* gap */
+#define RCC_BASE (PERIPH_BASE_AHB + 0x03800)
+#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB + 0x03c00)
+/* gap */
+#define DMA1_BASE (PERIPH_BASE_AHB + 0x06000)
+#define DMA2_BASE (PERIPH_BASE_AHB + 0x04000)
+
+/* PPIB */
+#define DBGMCU_BASE (PPBI_BASE + 0x00042000)
+
+/* FSMC */
+#define FSMC_BASE (PERIPH_BASE + 0x60000000)
+/* AES */
+#define AES_BASE (PERIPH_BASE + 0x10000000)
+
+/* Device Electronic Signature */
+#define DESIG_FLASH_SIZE_BASE (INFO_BASE + 0x8004C)
+#define DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x80050)
+
+/* Make the map names match those for other families to allow commonality */
+#define SPI1_I2S_BASE SPI1_BASE
+#define SPI2_I2S_BASE SPI2_BASE
+#define SPI3_I2S_BASE SPI3_BASE
+
+#endif
diff --git a/include/libopencm3/stm32/l1/pwr.h b/include/libopencm3/stm32/l1/pwr.h
new file mode 100644
index 0000000..e976d46
--- /dev/null
+++ b/include/libopencm3/stm32/l1/pwr.h
@@ -0,0 +1,112 @@
+/** @defgroup pwr_defines PWR Defines
+
+@brief <b>Defined Constants and Types for the STM32L1xx Power Control</b>
+
+@ingroup STM32L1xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2011 Stephen Caudle <scaudle@doceme.com>
+@author @htmlonly &copy; @endhtmlonly 2012 Karl Palsson <karlp@tweak.net.au>
+
+@date 1 July 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2011 Stephen Caudle <scaudle@doceme.com>
+ * Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_PWR_H
+#define LIBOPENCM3_PWR_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/pwr_common_all.h>
+
+/*
+ * This file extends the common STM32 version with definitions only
+ * applicable to the STM32L1 series of devices.
+ */
+
+/* --- PWR_CR values ------------------------------------------------------- */
+
+/* Bits [31:15]: Reserved */
+
+/* LPRUN: Low power run mode */
+#define PWR_CR_LPRUN (1 << 14)
+
+/* VOS[12:11]: Regulator voltage scaling output selection */
+#define PWR_CR_VOS_LSB 11
+/** @defgroup pwr_vos Voltage Scaling Output level selection
+@ingroup STM32F_pwr_defines
+
+@{*/
+#define PWR_CR_VOS_RANGE1 (0x1 << PWR_CR_VOS_LSB)
+#define PWR_CR_VOS_RANGE2 (0x2 << PWR_CR_VOS_LSB)
+#define PWR_CR_VOS_RANGE3 (0x3 << PWR_CR_VOS_LSB)
+/**@}*/
+#define PWR_CR_VOS_MASK (0x3 << PWR_CR_VOS_LSB)
+
+/* FWU: Fast wakeup */
+#define PWR_CR_FWU (1 << 10)
+
+/* ULP: Ultralow power mode */
+#define PWR_CR_ULP (1 << 9)
+
+/* LPSDSR: Low-power deepsleep/sleep/low power run */
+#define PWR_CR_LPSDSR (1 << 0) /* masks common PWR_CR_LPDS */
+
+/* --- PWR_CSR values ------------------------------------------------------- */
+
+/* Bits [31:11]: Reserved */
+/* EWUP3: Enable WKUP3 pin */
+#define PWR_CSR_EWUP3 (1 << 10)
+
+/* EWUP2: Enable WKUP2 pin */
+#define PWR_CSR_EWUP2 (1 << 9)
+
+/* EWUP1: Enable WKUP1 pin */
+#define PWR_CSR_EWUP1 PWR_CSR_EWUP
+
+/* REGLPF : Regulator LP flag */
+#define PWR_CSR_REGLPF (1 << 5)
+
+/* VOSF: Voltage Scaling select flag */
+#define PWR_CSR_VOSF (1 << 4)
+
+/* VREFINTRDYF: Internal voltage reference (VREFINT) ready flag */
+#define PWR_CSR_VREFINTRDYF (1 << 3)
+
+
+
+/* --- Function prototypes ------------------------------------------------- */
+
+typedef enum {
+ RANGE1,
+ RANGE2,
+ RANGE3,
+} vos_scale_t;
+
+BEGIN_DECLS
+
+void pwr_set_vos_scale(vos_scale_t scale);
+
+END_DECLS
+
+#endif
diff --git a/include/libopencm3/stm32/l1/rcc.h b/include/libopencm3/stm32/l1/rcc.h
new file mode 100644
index 0000000..4dc5102
--- /dev/null
+++ b/include/libopencm3/stm32/l1/rcc.h
@@ -0,0 +1,455 @@
+/** @defgroup STM32L1xx_rcc_defines RCC Defines
+
+@ingroup STM32L1xx_defines
+
+@brief <b>libopencm3 STM32L1xx Reset and Clock Control</b>
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2009 Federico Ruiz-Ugalde \<memeruiz at gmail dot com\>
+@author @htmlonly &copy; @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
+@author @htmlonly &copy; @endhtmlonly 2012 Karl Palsson <karlp@tweak.net.au>
+
+@date 11 November 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+ * Copyright (C) 2009 Federico Ruiz-Ugalde <memeruiz at gmail dot com>
+ * Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ *
+ * Originally based on the F1 code, as it seemed most similar to the L1
+ * TODO: very incomplete still!
+ */
+
+/**@{*/
+
+#ifndef LIBOPENCM3_RCC_H
+#define LIBOPENCM3_RCC_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+#include <libopencm3/stm32/pwr.h>
+
+/* --- RCC registers ------------------------------------------------------- */
+
+#define RCC_CR MMIO32(RCC_BASE + 0x00)
+#define RCC_ICSCR MMIO32(RCC_BASE + 0x04)
+#define RCC_CFGR MMIO32(RCC_BASE + 0x08)
+#define RCC_CIR MMIO32(RCC_BASE + 0x0c)
+#define RCC_AHBRSTR MMIO32(RCC_BASE + 0x10)
+#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x14)
+#define RCC_APB1RSTR MMIO32(RCC_BASE + 0x18)
+#define RCC_AHBENR MMIO32(RCC_BASE + 0x1c)
+#define RCC_APB2ENR MMIO32(RCC_BASE + 0x20)
+#define RCC_APB1ENR MMIO32(RCC_BASE + 0x24)
+#define RCC_AHBLPENR MMIO32(RCC_BASE + 0x28)
+#define RCC_APB2LPENR MMIO32(RCC_BASE + 0x2c)
+#define RCC_APB1LPENR MMIO32(RCC_BASE + 0x30)
+#define RCC_CSR MMIO32(RCC_BASE + 0x34)
+
+/* --- RCC_CR values ------------------------------------------------------- */
+
+/* RTCPRE[1:0] at 30:29 */
+#define RCC_CR_CSSON (1 << 28)
+#define RCC_CR_PLLRDY (1 << 25)
+#define RCC_CR_PLLON (1 << 24)
+#define RCC_CR_HSEBYP (1 << 18)
+#define RCC_CR_HSERDY (1 << 17)
+#define RCC_CR_HSEON (1 << 16)
+#define RCC_CR_MSIRDY (1 << 9)
+#define RCC_CR_MSION (1 << 8)
+#define RCC_CR_HSIRDY (1 << 1)
+#define RCC_CR_HSION (1 << 0)
+
+#define RCC_CR_RTCPRE_DIV2 0
+#define RCC_CR_RTCPRE_DIV4 1
+#define RCC_CR_RTCPRE_DIV8 2
+#define RCC_CR_RTCPRE_DIV16 3
+#define RCC_CR_RTCPRE_SHIFT 29
+#define RCC_CR_RTCPRE_MASK 0x3
+
+/* --- RCC_ICSCR values ---------------------------------------------------- */
+
+#define RCC_ICSCR_MSITRIM_SHIFT 24
+#define RCC_ICSCR_MSITRIM_MASK 0xff
+#define RCC_ICSCR_MSICAL_SHIFT 16
+#define RCC_ICSCR_MSICAL_MASK 0xff
+
+#define RCC_ICSCR_MSIRANGE_SHIFT 13
+#define RCC_ICSCR_MSIRANGE_MASK 0x7
+#define RCC_ICSCR_MSIRANGE_65KHZ 0x0
+#define RCC_ICSCR_MSIRANGE_131KHZ 0x1
+#define RCC_ICSCR_MSIRANGE_262KHZ 0x2
+#define RCC_ICSCR_MSIRANGE_524KHZ 0x3
+#define RCC_ICSCR_MSIRANGE_1MHZ 0x4
+#define RCC_ICSCR_MSIRANGE_2MHZ 0x5
+#define RCC_ICSCR_MSIRANGE_4MHZ 0x6
+
+#define RCC_ICSCR_HSITRIM_SHIFT 8
+#define RCC_ICSCR_HSITRIM_MASK 0x1f
+#define RCC_ICSCR_HSICAL_SHIFT 0
+#define RCC_ICSCR_HSICAL_MASK 0xff
+
+/* --- RCC_CFGR values ----------------------------------------------------- */
+
+/* MCOPRE */
+#define RCC_CFGR_MCOPRE_DIV1 0
+#define RCC_CFGR_MCOPRE_DIV2 1
+#define RCC_CFGR_MCOPRE_DIV4 2
+#define RCC_CFGR_MCOPRE_DIV8 3
+#define RCC_CFGR_MCOPRE_DIV16 4
+
+/* MCO: Microcontroller clock output */
+#define RCC_CFGR_MCO_NOCLK 0x0
+#define RCC_CFGR_MCO_SYSCLK 0x1
+#define RCC_CFGR_MCO_HSICLK 0x2
+#define RCC_CFGR_MCO_MSICLK 0x3
+#define RCC_CFGR_MCO_HSECLK 0x4
+#define RCC_CFGR_MCO_PLLCLK 0x5
+#define RCC_CFGR_MCO_LSICLK 0x6
+#define RCC_CFGR_MCO_LSECLK 0x7
+
+/* PLL Output division selection */
+#define RCC_CFGR_PLLDIV_DIV2 0x1
+#define RCC_CFGR_PLLDIV_DIV3 0x2
+#define RCC_CFGR_PLLDIV_DIV4 0x3
+#define RCC_CFGR_PLLDIV_SHIFT 22
+#define RCC_CFGR_PLLDIV_MASK 0x3
+
+/* PLLMUL: PLL multiplication factor */
+#define RCC_CFGR_PLLMUL_MUL3 0x0
+#define RCC_CFGR_PLLMUL_MUL4 0x1
+#define RCC_CFGR_PLLMUL_MUL6 0x2
+#define RCC_CFGR_PLLMUL_MUL8 0x3
+#define RCC_CFGR_PLLMUL_MUL12 0x4
+#define RCC_CFGR_PLLMUL_MUL16 0x5
+#define RCC_CFGR_PLLMUL_MUL24 0x6
+#define RCC_CFGR_PLLMUL_MUL32 0x7
+#define RCC_CFGR_PLLMUL_MUL48 0x8
+#define RCC_CFGR_PLLMUL_SHIFT 18
+#define RCC_CFGR_PLLMUL_MASK 0xf
+
+/* PLLSRC: PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSI_CLK 0x0
+#define RCC_CFGR_PLLSRC_HSE_CLK 0x1
+
+/* PPRE2: APB high-speed prescaler (APB2) */
+#define RCC_CFGR_PPRE2_HCLK_NODIV 0x0
+#define RCC_CFGR_PPRE2_HCLK_DIV2 0x4
+#define RCC_CFGR_PPRE2_HCLK_DIV4 0x5
+#define RCC_CFGR_PPRE2_HCLK_DIV8 0x6
+#define RCC_CFGR_PPRE2_HCLK_DIV16 0x7
+
+/* PPRE1: APB low-speed prescaler (APB1) */
+#define RCC_CFGR_PPRE1_HCLK_NODIV 0x0
+#define RCC_CFGR_PPRE1_HCLK_DIV2 0x4
+#define RCC_CFGR_PPRE1_HCLK_DIV4 0x5
+#define RCC_CFGR_PPRE1_HCLK_DIV8 0x6
+#define RCC_CFGR_PPRE1_HCLK_DIV16 0x7
+
+/* HPRE: AHB prescaler */
+#define RCC_CFGR_HPRE_SYSCLK_NODIV 0x0
+#define RCC_CFGR_HPRE_SYSCLK_DIV2 0x8
+#define RCC_CFGR_HPRE_SYSCLK_DIV4 0x9
+#define RCC_CFGR_HPRE_SYSCLK_DIV8 0xa
+#define RCC_CFGR_HPRE_SYSCLK_DIV16 0xb
+#define RCC_CFGR_HPRE_SYSCLK_DIV64 0xc
+#define RCC_CFGR_HPRE_SYSCLK_DIV128 0xd
+#define RCC_CFGR_HPRE_SYSCLK_DIV256 0xe
+#define RCC_CFGR_HPRE_SYSCLK_DIV512 0xf
+
+/* SWS: System clock switch status */
+#define RCC_CFGR_SWS_SYSCLKSEL_MSICLK 0x0
+#define RCC_CFGR_SWS_SYSCLKSEL_HSICLK 0x1
+#define RCC_CFGR_SWS_SYSCLKSEL_HSECLK 0x2
+#define RCC_CFGR_SWS_SYSCLKSEL_PLLCLK 0x3
+
+/* SW: System clock switch */
+#define RCC_CFGR_SW_SYSCLKSEL_MSICLK 0x0
+#define RCC_CFGR_SW_SYSCLKSEL_HSICLK 0x1
+#define RCC_CFGR_SW_SYSCLKSEL_HSECLK 0x2
+#define RCC_CFGR_SW_SYSCLKSEL_PLLCLK 0x3
+
+/* --- RCC_CIR values ------------------------------------------------------ */
+
+/* Clock security system interrupt clear bit */
+#define RCC_CIR_CSSC (1 << 23)
+
+/* OSC ready interrupt clear bits */
+#define RCC_CIR_MSIRDYC (1 << 21)
+#define RCC_CIR_PLLRDYC (1 << 20)
+#define RCC_CIR_HSERDYC (1 << 19)
+#define RCC_CIR_HSIRDYC (1 << 18)
+#define RCC_CIR_LSERDYC (1 << 17)
+#define RCC_CIR_LSIRDYC (1 << 16)
+
+/* OSC ready interrupt enable bits */
+#define RCC_CIR_MSIRDYIE (1 << 13)
+#define RCC_CIR_PLLRDYIE (1 << 12)
+#define RCC_CIR_HSERDYIE (1 << 11)
+#define RCC_CIR_HSIRDYIE (1 << 10)
+#define RCC_CIR_LSERDYIE (1 << 9)
+#define RCC_CIR_LSIRDYIE (1 << 8)
+
+/* Clock security system interrupt flag bit */
+#define RCC_CIR_CSSF (1 << 7)
+
+/* OSC ready interrupt flag bits */
+#define RCC_CIR_MSIRDYF (1 << 5) /* (**) */
+#define RCC_CIR_PLLRDYF (1 << 4)
+#define RCC_CIR_HSERDYF (1 << 3)
+#define RCC_CIR_HSIRDYF (1 << 2)
+#define RCC_CIR_LSERDYF (1 << 1)
+#define RCC_CIR_LSIRDYF (1 << 0)
+
+/* --- RCC_AHBRSTR values ------------------------------------------------- */
+#define RCC_AHBRSTR_DMA1RST (1 << 24)
+#define RCC_AHBRSTR_FLITFRST (1 << 15)
+#define RCC_AHBRSTR_CRCRST (1 << 12)
+#define RCC_AHBRSTR_GPIOHRST (1 << 5)
+#define RCC_AHBRSTR_GPIOERST (1 << 4)
+#define RCC_AHBRSTR_GPIODRST (1 << 3)
+#define RCC_AHBRSTR_GPIOCRST (1 << 2)
+#define RCC_AHBRSTR_GPIOBRST (1 << 1)
+#define RCC_AHBRSTR_GPIOARST (1 << 0)
+
+/* --- RCC_APB2RSTR values ------------------------------------------------- */
+
+#define RCC_APB2RSTR_USART1RST (1 << 14)
+#define RCC_APB2RSTR_SPI1RST (1 << 12)
+#define RCC_APB2RSTR_ADC1RST (1 << 9)
+#define RCC_APB2RSTR_TIM11RST (1 << 4)
+#define RCC_APB2RSTR_TIM10RST (1 << 3)
+#define RCC_APB2RSTR_TIM9RST (1 << 2)
+#define RCC_APB2RSTR_SYSCFGRST (1 << 0)
+
+/* --- RCC_APB1RSTR values ------------------------------------------------- */
+
+#define RCC_APB1RSTR_COMPRST (1 << 31)
+#define RCC_APB1RSTR_DACRST (1 << 29)
+#define RCC_APB1RSTR_PWRRST (1 << 28)
+#define RCC_APB1RSTR_USBRST (1 << 23)
+#define RCC_APB1RSTR_I2C2RST (1 << 22)
+#define RCC_APB1RSTR_I2C1RST (1 << 21)
+#define RCC_APB1RSTR_USART3RST (1 << 18)
+#define RCC_APB1RSTR_USART2RST (1 << 17)
+#define RCC_APB1RSTR_SPI2RST (1 << 14)
+#define RCC_APB1RSTR_WWDGRST (1 << 11)
+#define RCC_APB1RSTR_LCDRST (1 << 9)
+#define RCC_APB1RSTR_TIM7RST (1 << 5)
+#define RCC_APB1RSTR_TIM6RST (1 << 4)
+#define RCC_APB1RSTR_TIM5RST (1 << 3)
+#define RCC_APB1RSTR_TIM4RST (1 << 2)
+#define RCC_APB1RSTR_TIM3RST (1 << 1)
+#define RCC_APB1RSTR_TIM2RST (1 << 0)
+
+/* --- RCC_AHBENR values --------------------------------------------------- */
+
+/** @defgroup rcc_ahbenr_en RCC_AHBENR enable values
+@ingroup STM32L1xx_rcc_defines
+
+@{*/
+#define RCC_AHBENR_DMA1EN (1 << 24)
+#define RCC_AHBENR_FLITFEN (1 << 15)
+#define RCC_AHBENR_CRCEN (1 << 12)
+#define RCC_AHBENR_GPIOHEN (1 << 5)
+#define RCC_AHBENR_GPIOEEN (1 << 4)
+#define RCC_AHBENR_GPIODEN (1 << 3)
+#define RCC_AHBENR_GPIOCEN (1 << 2)
+#define RCC_AHBENR_GPIOBEN (1 << 1)
+#define RCC_AHBENR_GPIOAEN (1 << 0)
+/*@}*/
+
+/* --- RCC_APB2ENR values -------------------------------------------------- */
+
+/** @defgroup rcc_apb2enr_en RCC_APB2ENR enable values
+@ingroup STM32L1xx_rcc_defines
+
+@{*/
+#define RCC_APB2ENR_USART1EN (1 << 14)
+#define RCC_APB2ENR_SPI1EN (1 << 12)
+#define RCC_APB2ENR_ADC1EN (1 << 9)
+#define RCC_APB2ENR_TIM11EN (1 << 4)
+#define RCC_APB2ENR_TIM10EN (1 << 3)
+#define RCC_APB2ENR_TIM9EN (1 << 2)
+#define RCC_APB2ENR_SYSCFGEN (1 << 0)
+/*@}*/
+
+/* --- RCC_APB1ENR values -------------------------------------------------- */
+
+/** @defgroup rcc_apb1enr_en RCC_APB1ENR enable values
+@ingroup STM32L1xx_rcc_defines
+
+@{*/
+#define RCC_APB1ENR_COMPEN (1 << 31)
+#define RCC_APB1ENR_DACEN (1 << 29)
+#define RCC_APB1ENR_PWREN (1 << 28)
+#define RCC_APB1ENR_USBEN (1 << 23)
+#define RCC_APB1ENR_I2C2EN (1 << 22)
+#define RCC_APB1ENR_I2C1EN (1 << 21)
+#define RCC_APB1ENR_USART3EN (1 << 18)
+#define RCC_APB1ENR_USART2EN (1 << 17)
+#define RCC_APB1ENR_SPI2EN (1 << 14)
+#define RCC_APB1ENR_WWDGEN (1 << 11)
+#define RCC_APB1ENR_LCDEN (1 << 9)
+#define RCC_APB1ENR_TIM7EN (1 << 5)
+#define RCC_APB1ENR_TIM6EN (1 << 4)
+#define RCC_APB1ENR_TIM4EN (1 << 2)
+#define RCC_APB1ENR_TIM3EN (1 << 1)
+#define RCC_APB1ENR_TIM2EN (1 << 0)
+/*@}*/
+
+/* --- RCC_AHBLPENR -------------------------------------------------------- */
+#define RCC_AHBLPENR_DMA1LPEN (1 << 24)
+#define RCC_AHBLPENR_SRAMLPEN (1 << 16)
+#define RCC_AHBLPENR_FLITFLPEN (1 << 15)
+#define RCC_AHBLPENR_CRCLPEN (1 << 12)
+#define RCC_AHBLPENR_GPIOHLPEN (1 << 5)
+#define RCC_AHBLPENR_GPIOELPEN (1 << 4)
+#define RCC_AHBLPENR_GPIODLPEN (1 << 3)
+#define RCC_AHBLPENR_GPIOCLPEN (1 << 2)
+#define RCC_AHBLPENR_GPIOBLPEN (1 << 1)
+#define RCC_AHBLPENR_GPIOALPEN (1 << 0)
+
+#define RCC_APB2LPENR_USART1LPEN (1 << 14)
+#define RCC_APB2LPENR_SPI1LPEN (1 << 12)
+#define RCC_APB2LPENR_ADC1LPEN (1 << 9)
+#define RCC_APB2LPENR_TIM11LPEN (1 << 4)
+#define RCC_APB2LPENR_TIM10LPEN (1 << 3)
+#define RCC_APB2LPENR_TIM9LPEN (1 << 2)
+#define RCC_APB2LPENR_SYSCFGLPEN (1 << 0)
+
+#define RCC_APB1LPENR_COMPLPEN (1 << 31)
+#define RCC_APB1LPENR_DACLPEN (1 << 29)
+#define RCC_APB1LPENR_PWRLPEN (1 << 28)
+#define RCC_APB1LPENR_USBLPEN (1 << 23)
+#define RCC_APB1LPENR_I2C2LPEN (1 << 22)
+#define RCC_APB1LPENR_I2C1LPEN (1 << 21)
+#define RCC_APB1LPENR_USART3LPEN (1 << 18)
+#define RCC_APB1LPENR_USART2LPEN (1 << 17)
+#define RCC_APB1LPENR_SPI2LPEN (1 << 14)
+#define RCC_APB1LPENR_WWDGLPEN (1 << 11)
+#define RCC_APB1LPENR_LCDLPEN (1 << 9)
+#define RCC_APB1LPENR_TIM7LPEN (1 << 5)
+#define RCC_APB1LPENR_TIM6LPEN (1 << 4)
+#define RCC_APB1LPENR_TIM4LPEN (1 << 2)
+#define RCC_APB1LPENR_TIM3LPEN (1 << 1)
+#define RCC_APB1LPENR_TIM2LPEN (1 << 0)
+
+
+/* --- RCC_CSR values ------------------------------------------------------ */
+
+#define RCC_CSR_LPWRRSTF (1 << 31)
+#define RCC_CSR_WWDGRSTF (1 << 30)
+#define RCC_CSR_IWDGRSTF (1 << 29)
+#define RCC_CSR_SFTRSTF (1 << 28)
+#define RCC_CSR_PORRSTF (1 << 27)
+#define RCC_CSR_PINRSTF (1 << 26)
+#define RCC_CSR_OBLRSTF (1 << 25)
+#define RCC_CSR_RMVF (1 << 24)
+#define RCC_CSR_RTCRST (1 << 23)
+#define RCC_CSR_RTCEN (1 << 22)
+#define RCC_CSR_RTCSEL_SHIFT (16)
+#define RCC_CSR_RTCSEL_MASK (0x3)
+#define RCC_CSR_RTCSEL_NONE (0x0)
+#define RCC_CSR_RTCSEL_LSE (0x1)
+#define RCC_CSR_RTCSEL_LSI (0x2)
+#define RCC_CSR_RTCSEL_HSI (0x3)
+#define RCC_CSR_LSECSSD (1 << 12)
+#define RCC_CSR_LSECSSON (1 << 11)
+#define RCC_CSR_LSEBYP (1 << 10)
+#define RCC_CSR_LSERDY (1 << 9)
+#define RCC_CSR_LSEON (1 << 8)
+#define RCC_CSR_LSIRDY (1 << 1)
+#define RCC_CSR_LSION (1 << 0)
+
+typedef struct {
+ uint8_t pll_mul;
+ uint16_t pll_div;
+ uint8_t pll_source;
+ uint32_t flash_config;
+ uint8_t hpre;
+ uint8_t ppre1;
+ uint8_t ppre2;
+ vos_scale_t voltage_scale;
+ uint32_t apb1_frequency;
+ uint32_t apb2_frequency;
+ uint8_t msi_range;
+} clock_scale_t;
+
+typedef enum {
+ CLOCK_VRANGE1_HSI_PLL_24MHZ,
+ CLOCK_VRANGE1_HSI_PLL_32MHZ,
+ CLOCK_VRANGE1_HSI_RAW_16MHZ,
+ CLOCK_VRANGE1_HSI_RAW_4MHZ,
+ CLOCK_VRANGE1_MSI_RAW_4MHZ,
+ CLOCK_VRANGE1_MSI_RAW_2MHZ,
+ CLOCK_CONFIG_END
+} clock_config_entry_t;
+
+extern const clock_scale_t clock_config[CLOCK_CONFIG_END];
+
+
+/* --- Variable definitions ------------------------------------------------ */
+extern u32 rcc_ppre1_frequency;
+extern u32 rcc_ppre2_frequency;
+
+/* --- Function prototypes ------------------------------------------------- */
+
+typedef enum {
+ PLL, HSE, HSI, MSI, LSE, LSI
+} osc_t;
+
+void rcc_osc_ready_int_clear(osc_t osc);
+void rcc_osc_ready_int_enable(osc_t osc);
+void rcc_osc_ready_int_disable(osc_t osc);
+int rcc_osc_ready_int_flag(osc_t osc);
+void rcc_css_int_clear(void);
+int rcc_css_int_flag(void);
+void rcc_wait_for_osc_ready(osc_t osc);
+void rcc_osc_on(osc_t osc);
+void rcc_osc_off(osc_t osc);
+void rcc_css_enable(void);
+void rcc_css_disable(void);
+void rcc_osc_bypass_enable(osc_t osc);
+void rcc_osc_bypass_disable(osc_t osc);
+void rcc_peripheral_enable_clock(volatile u32 *reg, u32 en);
+void rcc_peripheral_disable_clock(volatile u32 *reg, u32 en);
+void rcc_peripheral_reset(volatile u32 *reg, u32 reset);
+void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset);
+void rcc_set_sysclk_source(u32 clk);
+void rcc_set_pll_configuration(u32 source, u32 multiplier, u32 divisor);
+void rcc_set_pll_source(u32 pllsrc);
+void rcc_set_adcpre(u32 adcpre);
+void rcc_set_ppre2(u32 ppre2);
+void rcc_set_ppre1(u32 ppre1);
+void rcc_set_hpre(u32 hpre);
+void rcc_set_usbpre(u32 usbpre);
+u32 rcc_get_system_clock_source(int i);
+void rcc_rtc_select_clock(u32 clock);
+void rcc_clock_setup_msi(const clock_scale_t *clock);
+void rcc_clock_setup_hsi(const clock_scale_t *clock);
+void rcc_clock_setup_pll(const clock_scale_t *clock);
+void rcc_backupdomain_reset(void);
+
+/**@}*/
+
+#endif
diff --git a/include/libopencm3/stm32/l1/rtc.h b/include/libopencm3/stm32/l1/rtc.h
new file mode 100644
index 0000000..d364fb5
--- /dev/null
+++ b/include/libopencm3/stm32/l1/rtc.h
@@ -0,0 +1,39 @@
+/** @defgroup rtc_defines RTC Defines
+
+@brief <b>Defined Constants and Types for the STM32L1xx RTC</b>
+
+@ingroup STM32L1xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 5 December 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_RTC_H
+#define LIBOPENCM3_RTC_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/rtc_common_bcd.h>
+
+#endif \ No newline at end of file
diff --git a/include/libopencm3/stm32/l1/spi.h b/include/libopencm3/stm32/l1/spi.h
new file mode 100644
index 0000000..0484956
--- /dev/null
+++ b/include/libopencm3/stm32/l1/spi.h
@@ -0,0 +1,40 @@
+/** @defgroup spi_defines SPI Defines
+
+@brief <b>Defined Constants and Types for the STM32L1xx SPI</b>
+
+@ingroup STM32L1xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 5 December 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_SPI_H
+#define LIBOPENCM3_SPI_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/spi_common_all.h>
+
+#endif
+
diff --git a/include/libopencm3/stm32/l1/usart.h b/include/libopencm3/stm32/l1/usart.h
new file mode 100644
index 0000000..5b67a5a
--- /dev/null
+++ b/include/libopencm3/stm32/l1/usart.h
@@ -0,0 +1,40 @@
+/** @defgroup usart_defines USART Defines
+
+@brief <b>Defined Constants and Types for the STM32L1xx USART</b>
+
+@ingroup STM32L1xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 5 December 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_USART_H
+#define LIBOPENCM3_USART_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/usart_common_all.h>
+
+#endif
+
diff --git a/include/libopencm3/stm32/memorymap.h b/include/libopencm3/stm32/memorymap.h
index 6f213da..9b757ce 100644
--- a/include/libopencm3/stm32/memorymap.h
+++ b/include/libopencm3/stm32/memorymap.h
@@ -26,6 +26,8 @@
# include <libopencm3/stm32/f2/memorymap.h>
#elif defined(STM32F4)
# include <libopencm3/stm32/f4/memorymap.h>
+#elif defined(STM32L1)
+# include <libopencm3/stm32/l1/memorymap.h>
#else
# error "stm32 family not defined."
#endif
diff --git a/include/libopencm3/stm32/nvic.h b/include/libopencm3/stm32/nvic.h
deleted file mode 100644
index 694fab8..0000000
--- a/include/libopencm3/stm32/nvic.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/** @defgroup STM32F_nvic_defines NVIC Defines
-
-@brief <b>libopencm3 STM32F Nested Vectored Interrupt Controller</b>
-
-@ingroup STM32F_defines
-
-@version 1.0.0
-
-@author @htmlonly &copy; @endhtmlonly 2010 Piotr Esden-Tempski <piotr@esden.net>
-
-@date 18 August 2012
-
-LGPL License Terms @ref lgpl_license
- */
-/*
- * This file is part of the libopencm3 project.
- *
- * Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library. If not, see <http://www.gnu.org/licenses/>.
- */
-/**@{*/
-
-#ifndef LIBOPENCM3_NVIC_H
-#define LIBOPENCM3_NVIC_H
-
-#include <libopencm3/stm32/memorymap.h>
-#include <libopencm3/cm3/common.h>
-
-/* --- NVIC Registers ------------------------------------------------------ */
-
-/* ISER: Interrupt Set Enable Registers */
-/* Note: 8 32bit Registers */
-#define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + (iser_id * 4))
-
-/* NVIC_BASE + 0x020 (0xE000 E120 - 0xE000 E17F): Reserved */
-
-/* ICER: Interrupt Clear Enable Registers */
-/* Note: 8 32bit Registers */
-#define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + (icer_id * 4))
-
-/* NVIC_BASE + 0x0A0 (0xE000 E1A0 - 0xE000 E1FF): Reserved */
-
-/* ISPR: Interrupt Set Pending Registers */
-/* Note: 8 32bit Registers */
-#define NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + (ispr_id * 4))
-
-/* NVIC_BASE + 0x120 (0xE000 E220 - 0xE000 E27F): Reserved */
-
-/* ICPR: Interrupt Clear Pending Registers */
-/* Note: 8 32bit Registers */
-#define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + (icpr_id * 4))
-
-/* NVIC_BASE + 0x1A0 (0xE000 E2A0 - 0xE00 E2FF): Reserved */
-
-/* IABR: Interrupt Active Bit Register */
-/* Note: 8 32bit Registers */
-#define NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + (iabr_id * 4))
-
-/* NVIC_BASE + 0x220 (0xE000 E320 - 0xE000 E3FF): Reserved */
-
-/* IPR: Interrupt Priority Registers */
-/* Note: 240 8bit Registers */
-#define NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + ipr_id)
-
-/* STIR: Software Trigger Interrupt Register */
-#define NVIC_STIR MMIO32(STIR_BASE)
-
-/* --- IRQ channel numbers-------------------------------------------------- */
-
-/* Cortex M3 System Interrupts */
-/** @defgroup nvic_sysint Cortex M3 System Interrupts
-@ingroup STM32F_nvic_defines
-
-IRQ numbers -3 and -6 to -9 are reserved
-@{*/
-#define NVIC_NMI_IRQ -14
-#define NVIC_HARD_FAULT_IRQ -13
-#define NVIC_MEM_MANAGE_IRQ -12
-#define NVIC_BUS_FAULT_IRQ -11
-#define NVIC_USAGE_FAULT_IRQ -10
-/* irq numbers -6 to -9 are reserved */
-#define NVIC_SV_CALL_IRQ -5
-#define DEBUG_MONITOR_IRQ -4
-/* irq number -3 reserved */
-#define NVIC_PENDSV_IRQ -2
-#define NVIC_SYSTICK_IRQ -1
-/**@}*/
-
-
-/* Note: User interrupts are family specific and are defined in a family
- * specific header file in the corresponding subfolder.
- */
-
-#if defined(STM32F1)
-# include <libopencm3/stm32/f1/nvic_f1.h>
-#elif defined(STM32F2)
-# include <libopencm3/stm32/f2/nvic_f2.h>
-#elif defined(STM32F4)
-# include <libopencm3/stm32/f4/nvic_f4.h>
-#else
-# error "stm32 family not defined."
-#endif
-
-
-/* --- NVIC functions ------------------------------------------------------ */
-
-BEGIN_DECLS
-
-void nvic_enable_irq(u8 irqn);
-void nvic_disable_irq(u8 irqn);
-u8 nvic_get_pending_irq(u8 irqn);
-void nvic_set_pending_irq(u8 irqn);
-void nvic_clear_pending_irq(u8 irqn);
-u8 nvic_get_active_irq(u8 irqn);
-u8 nvic_get_irq_enabled(u8 irqn);
-void nvic_set_priority(u8 irqn, u8 priority);
-void nvic_generate_software_interrupt(u16 irqn);
-
-END_DECLS
-
-#endif
-/**@}*/
-
diff --git a/include/libopencm3/stm32/otg_fs.h b/include/libopencm3/stm32/otg_fs.h
index 5680e43..d8ee393 100644
--- a/include/libopencm3/stm32/otg_fs.h
+++ b/include/libopencm3/stm32/otg_fs.h
@@ -24,7 +24,7 @@
#include <libopencm3/cm3/common.h>
/* Core Global Control and Status Registers */
-#define OTG_FS_OTGCTL MMIO32(USB_OTG_FS_BASE + 0x000)
+#define OTG_FS_GOTGCTL MMIO32(USB_OTG_FS_BASE + 0x000)
#define OTG_FS_GOTGINT MMIO32(USB_OTG_FS_BASE + 0x004)
#define OTG_FS_GAHBCFG MMIO32(USB_OTG_FS_BASE + 0x008)
#define OTG_FS_GUSBCFG MMIO32(USB_OTG_FS_BASE + 0x00C)
@@ -42,40 +42,40 @@
#define OTG_FS_DIEPTXF(x) MMIO32(USB_OTG_FS_BASE + 0x104 + 4*(x-1))
/* Host-mode Control and Status Registers */
-#define OTG_FS_HCFG MMIO32(USB_OTG_FS_BASE + 0x400)
-#define OTG_FS_HFIR MMIO32(USB_OTG_FS_BASE + 0x404)
-#define OTG_FS_HFNUM MMIO32(USB_OTG_FS_BASE + 0x408)
-#define OTG_FS_HPTXSTS MMIO32(USB_OTG_FS_BASE + 0x410)
-#define OTG_FS_HAINT MMIO32(USB_OTG_FS_BASE + 0x414)
-#define OTG_FS_HAINTMSK MMIO32(USB_OTG_FS_BASE + 0x418)
-#define OTG_FS_HPRT MMIO32(USB_OTG_FS_BASE + 0x440)
-#define OTG_FS_HCCHARx MMIO32(USB_OTG_FS_BASE + 0x500)
-#define OTG_FS_HCINTx MMIO32(USB_OTG_FS_BASE + 0x508)
-#define OTG_FS_HCINTMSKx MMIO32(USB_OTG_FS_BASE + 0x50C)
-#define OTG_FS_HCTSIZx MMIO32(USB_OTG_FS_BASE + 0x510)
+#define OTG_FS_HCFG MMIO32(USB_OTG_FS_BASE + 0x400)
+#define OTG_FS_HFIR MMIO32(USB_OTG_FS_BASE + 0x404)
+#define OTG_FS_HFNUM MMIO32(USB_OTG_FS_BASE + 0x408)
+#define OTG_FS_HPTXSTS MMIO32(USB_OTG_FS_BASE + 0x410)
+#define OTG_FS_HAINT MMIO32(USB_OTG_FS_BASE + 0x414)
+#define OTG_FS_HAINTMSK MMIO32(USB_OTG_FS_BASE + 0x418)
+#define OTG_FS_HPRT MMIO32(USB_OTG_FS_BASE + 0x440)
+#define OTG_FS_HCCHARx MMIO32(USB_OTG_FS_BASE + 0x500)
+#define OTG_FS_HCINTx MMIO32(USB_OTG_FS_BASE + 0x508)
+#define OTG_FS_HCINTMSKx MMIO32(USB_OTG_FS_BASE + 0x50C)
+#define OTG_FS_HCTSIZx MMIO32(USB_OTG_FS_BASE + 0x510)
/* Device-mode Control and Status Registers */
-#define OTG_FS_DCFG MMIO32(USB_OTG_FS_BASE + 0x800)
-#define OTG_FS_DCTL MMIO32(USB_OTG_FS_BASE + 0x804)
-#define OTG_FS_DSTS MMIO32(USB_OTG_FS_BASE + 0x808)
-#define OTG_FS_DIEPMSK MMIO32(USB_OTG_FS_BASE + 0x810)
-#define OTG_FS_DOEPMSK MMIO32(USB_OTG_FS_BASE + 0x814)
-#define OTG_FS_DAINT MMIO32(USB_OTG_FS_BASE + 0x818)
-#define OTG_FS_DAINTMSK MMIO32(USB_OTG_FS_BASE + 0x81C)
-#define OTG_FS_DVBUSDIS MMIO32(USB_OTG_FS_BASE + 0x828)
-#define OTG_FS_DVBUSPULSE MMIO32(USB_OTG_FS_BASE + 0x82C)
-#define OTG_FS_DIEPEMPMSK MMIO32(USB_OTG_FS_BASE + 0x834)
-#define OTG_FS_DIEPCTL0 MMIO32(USB_OTG_FS_BASE + 0x900)
-#define OTG_FS_DIEPCTL(x) MMIO32(USB_OTG_FS_BASE + 0x900 + 0x20*(x))
-#define OTG_FS_DOEPCTL0 MMIO32(USB_OTG_FS_BASE + 0xB00)
-#define OTG_FS_DOEPCTL(x) MMIO32(USB_OTG_FS_BASE + 0xB00 + 0x20*(x))
-#define OTG_FS_DIEPINT(x) MMIO32(USB_OTG_FS_BASE + 0x908 + 0x20*(x))
-#define OTG_FS_DOEPINT(x) MMIO32(USB_OTG_FS_BASE + 0xB08 + 0x20*(x))
-#define OTG_FS_DIEPTSIZ0 MMIO32(USB_OTG_FS_BASE + 0x910)
-#define OTG_FS_DOEPTSIZ0 MMIO32(USB_OTG_FS_BASE + 0xB10)
-#define OTG_FS_DIEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + 0x910 + 0x20*(x))
-#define OTG_FS_DTXFSTS(x) MMIO32(USB_OTG_FS_BASE + 0x918 + 0x20*(x))
-#define OTG_FS_DOEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + 0xB10 + 0x20*(x))
+#define OTG_FS_DCFG MMIO32(USB_OTG_FS_BASE + 0x800)
+#define OTG_FS_DCTL MMIO32(USB_OTG_FS_BASE + 0x804)
+#define OTG_FS_DSTS MMIO32(USB_OTG_FS_BASE + 0x808)
+#define OTG_FS_DIEPMSK MMIO32(USB_OTG_FS_BASE + 0x810)
+#define OTG_FS_DOEPMSK MMIO32(USB_OTG_FS_BASE + 0x814)
+#define OTG_FS_DAINT MMIO32(USB_OTG_FS_BASE + 0x818)
+#define OTG_FS_DAINTMSK MMIO32(USB_OTG_FS_BASE + 0x81C)
+#define OTG_FS_DVBUSDIS MMIO32(USB_OTG_FS_BASE + 0x828)
+#define OTG_FS_DVBUSPULSE MMIO32(USB_OTG_FS_BASE + 0x82C)
+#define OTG_FS_DIEPEMPMSK MMIO32(USB_OTG_FS_BASE + 0x834)
+#define OTG_FS_DIEPCTL0 MMIO32(USB_OTG_FS_BASE + 0x900)
+#define OTG_FS_DIEPCTL(x) MMIO32(USB_OTG_FS_BASE + 0x900 + 0x20*(x))
+#define OTG_FS_DOEPCTL0 MMIO32(USB_OTG_FS_BASE + 0xB00)
+#define OTG_FS_DOEPCTL(x) MMIO32(USB_OTG_FS_BASE + 0xB00 + 0x20*(x))
+#define OTG_FS_DIEPINT(x) MMIO32(USB_OTG_FS_BASE + 0x908 + 0x20*(x))
+#define OTG_FS_DOEPINT(x) MMIO32(USB_OTG_FS_BASE + 0xB08 + 0x20*(x))
+#define OTG_FS_DIEPTSIZ0 MMIO32(USB_OTG_FS_BASE + 0x910)
+#define OTG_FS_DOEPTSIZ0 MMIO32(USB_OTG_FS_BASE + 0xB10)
+#define OTG_FS_DIEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + 0x910 + 0x20*(x))
+#define OTG_FS_DTXFSTS(x) MMIO32(USB_OTG_FS_BASE + 0x918 + 0x20*(x))
+#define OTG_FS_DOEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + 0xB10 + 0x20*(x))
/* Power and clock gating control and status register */
#define OTG_FS_PCGCCTL MMIO32(USB_OTG_FS_BASE + 0xE00)
@@ -84,6 +84,18 @@
#define OTG_FS_FIFO(x) ((volatile u32*)(USB_OTG_FS_BASE + (((x) + 1) << 12)))
/* Global CSRs */
+/* OTG_FS USB control registers (OTG_HS_GOTGCTL) */
+#define OTG_FS_GOTGCTL_BSVLD (1 << 19)
+#define OTG_FS_GOTGCTL_ASVLD (1 << 18)
+#define OTG_FS_GOTGCTL_DBCT (1 << 17)
+#define OTG_FS_GOTGCTL_CIDSTS (1 << 16)
+#define OTG_FS_GOTGCTL_DHNPEN (1 << 11)
+#define OTG_FS_GOTGCTL_HSHNPEN (1 << 10)
+#define OTG_FS_GOTGCTL_HNPRQ (1 << 9)
+#define OTG_FS_GOTGCTL_HNGSCS (1 << 8)
+#define OTG_FS_GOTGCTL_SRQ (1 << 1)
+#define OTG_FS_GOTGCTL_SRQSCS (1 << 0)
+
/* OTG_FS AHB configuration register (OTG_FS_GAHBCFG) */
#define OTG_FS_GAHBCFG_GINT 0x0001
#define OTG_FS_GAHBCFG_TXFELVL 0x0080
@@ -175,20 +187,20 @@
/* OTG_FS Receive Status Pop Register (OTG_FS_GRXSTSP) */
/* Bits 31:25 - Reserved */
-#define OTG_FS_GRXSTSP_FRMNUM_MASK (0xf << 21)
-#define OTG_FS_GRXSTSP_PKTSTS_MASK (0xf << 17)
-#define OTG_FS_GRXSTSP_PKTSTS_GOUTNAK (0x1 << 17)
-#define OTG_FS_GRXSTSP_PKTSTS_OUT (0x2 << 17)
-#define OTG_FS_GRXSTSP_PKTSTS_OUT_COMP (0x3 << 17)
+#define OTG_FS_GRXSTSP_FRMNUM_MASK (0xf << 21)
+#define OTG_FS_GRXSTSP_PKTSTS_MASK (0xf << 17)
+#define OTG_FS_GRXSTSP_PKTSTS_GOUTNAK (0x1 << 17)
+#define OTG_FS_GRXSTSP_PKTSTS_OUT (0x2 << 17)
+#define OTG_FS_GRXSTSP_PKTSTS_OUT_COMP (0x3 << 17)
#define OTG_FS_GRXSTSP_PKTSTS_SETUP_COMP (0x4 << 17)
-#define OTG_FS_GRXSTSP_PKTSTS_SETUP (0x6 << 17)
-#define OTG_FS_GRXSTSP_DPID_MASK (0x3 << 15)
-#define OTG_FS_GRXSTSP_DPID_DATA0 (0x0 << 15)
-#define OTG_FS_GRXSTSP_DPID_DATA1 (0x2 << 15)
-#define OTG_FS_GRXSTSP_DPID_DATA2 (0x1 << 15)
-#define OTG_FS_GRXSTSP_DPID_MDATA (0x3 << 15)
-#define OTG_FS_GRXSTSP_BCNT_MASK (0x7ff << 4)
-#define OTG_FS_GRXSTSP_EPNUM_MASK (0xf << 0)
+#define OTG_FS_GRXSTSP_PKTSTS_SETUP (0x6 << 17)
+#define OTG_FS_GRXSTSP_DPID_MASK (0x3 << 15)
+#define OTG_FS_GRXSTSP_DPID_DATA0 (0x0 << 15)
+#define OTG_FS_GRXSTSP_DPID_DATA1 (0x2 << 15)
+#define OTG_FS_GRXSTSP_DPID_DATA2 (0x1 << 15)
+#define OTG_FS_GRXSTSP_DPID_MDATA (0x3 << 15)
+#define OTG_FS_GRXSTSP_BCNT_MASK (0x7ff << 4)
+#define OTG_FS_GRXSTSP_EPNUM_MASK (0xf << 0)
/* OTG_FS general core configuration register (OTG_FS_GCCFG) */
/* Bits 31:21 - Reserved */
@@ -320,4 +332,3 @@
#define OTG_FS_DIEPSIZ0_XFRSIZ_MASK (0x7f << 0)
#endif
-
diff --git a/include/libopencm3/stm32/otg_hs.h b/include/libopencm3/stm32/otg_hs.h
new file mode 100644
index 0000000..2f59ddd
--- /dev/null
+++ b/include/libopencm3/stm32/otg_hs.h
@@ -0,0 +1,396 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Gareth McMullin <gareth@blacksphere.co.nz>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_OTG_HS_H
+#define LIBOPENCM3_OTG_HS_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/* Core Global Control and Status Registers */
+#define OTG_GOTGCTL 0x000
+#define OTG_GOTGIN 0x004
+#define OTG_GAHBCFG 0x008
+#define OTG_GUSBCFG 0x00C
+#define OTG_GRSTCTL 0x010
+#define OTG_GINTSTS 0x014
+#define OTG_GINTMSK 0x018
+#define OTG_GRXSTSR 0x01C
+#define OTG_GRXSTSP 0x020
+#define OTG_GRXFSIZ 0x024
+#define OTG_GNPTXFSIZ 0x028
+#define OTG_GNPTXSTS 0x02C
+#define OTG_GCCFG 0x038
+#define OTG_CID 0x03C
+#define OTG_HPTXFSIZ 0x100
+#define OTG_DIEPTXF(x) (0x104 + 4*(x-1))
+
+/* Host-mode Control and Status Registers */
+#define OTG_HCFG 0x400
+#define OTG_HFIR 0x404
+#define OTG_HFNUM 0x408
+#define OTG_HPTXSTS 0x410
+#define OTG_HAINT 0x414
+#define OTG_HAINTMSK 0x418
+#define OTG_HPRT 0x440
+#define OTG_HCCHARx 0x500
+#define OTG_HCINTx 0x508
+#define OTG_HCINTMSKx 0x50C
+#define OTG_HCTSIZx 0x510
+
+/* Device-mode Control and Status Registers */
+#define OTG_DCFG 0x800
+#define OTG_DCTL 0x804
+#define OTG_DSTS 0x808
+#define OTG_DIEPMSK 0x810
+#define OTG_DOEPMSK 0x814
+#define OTG_DAINT 0x818
+#define OTG_DAINTMSK 0x81C
+#define OTG_DVBUSDIS 0x828
+#define OTG_DVBUSPULSE 0x82C
+#define OTG_DIEPEMPMSK 0x834
+#define OTG_DIEPCTL0 0x900
+#define OTG_DIEPCTL(x) (0x900 + 0x20*(x))
+#define OTG_DOEPCTL0 0xB00
+#define OTG_DOEPCTL(x) (0xB00 + 0x20*(x))
+#define OTG_DIEPINT(x) (0x908 + 0x20*(x))
+#define OTG_DOEPINT(x) (0xB08 + 0x20*(x))
+#define OTG_DIEPTSIZ0 0x910
+#define OTG_DOEPTSIZ0 0xB10
+#define OTG_DIEPTSIZ(x) (0x910 + 0x20*(x))
+#define OTG_DTXFSTS(x) (0x918 + 0x20*(x))
+#define OTG_DOEPTSIZ(x) (0xB10 + 0x20*(x))
+
+/* Power and clock gating control and status register */
+#define OTG_PCGCCTL 0xE00
+
+/* Data FIFO */
+#define OTG_FIFO(x) (((x) + 1) << 12)
+
+/***********************************************************************/
+
+/* Core Global Control and Status Registers */
+#define OTG_HS_GOTGCTL MMIO32(USB_OTG_HS_BASE + OTG_GOTGCTL)
+#define OTG_HS_GOTGINT MMIO32(USB_OTG_HS_BASE + OTG_GOTGINT)
+#define OTG_HS_GAHBCFG MMIO32(USB_OTG_HS_BASE + OTG_GAHBCFG)
+#define OTG_HS_GUSBCFG MMIO32(USB_OTG_HS_BASE + OTG_GUSBCFG)
+#define OTG_HS_GRSTCTL MMIO32(USB_OTG_HS_BASE + OTG_GRSTCTL)
+#define OTG_HS_GINTSTS MMIO32(USB_OTG_HS_BASE + OTG_GINTSTS)
+#define OTG_HS_GINTMSK MMIO32(USB_OTG_HS_BASE + OTG_GINTMSK)
+#define OTG_HS_GRXSTSR MMIO32(USB_OTG_HS_BASE + OTG_GRXSTSR)
+#define OTG_HS_GRXSTSP MMIO32(USB_OTG_HS_BASE + OTG_GRXSTSP)
+#define OTG_HS_GRXFSIZ MMIO32(USB_OTG_HS_BASE + OTG_GRXFSIZ)
+#define OTG_HS_GNPTXFSIZ MMIO32(USB_OTG_HS_BASE + OTG_GNPTXFSIZ)
+#define OTG_HS_GNPTXSTS MMIO32(USB_OTG_HS_BASE + OTG_GNPTXSTS)
+#define OTG_HS_GCCFG MMIO32(USB_OTG_HS_BASE + OTG_GCCFG)
+#define OTG_HS_CID MMIO32(USB_OTG_HS_BASE + OTG_CID)
+#define OTG_HS_HPTXFSIZ MMIO32(USB_OTG_HS_BASE + OTG_HPTXFSIZ)
+#define OTG_HS_DIEPTXF(x) MMIO32(USB_OTG_HS_BASE + OTG_DIEPTXF(x))
+
+/* Host-mode Control and Status Registers */
+#define OTG_HS_HCFG MMIO32(USB_OTG_HS_BASE + OTG_HCFG)
+#define OTG_HS_HFIR MMIO32(USB_OTG_HS_BASE + OTG_HFIR)
+#define OTG_HS_HFNUM MMIO32(USB_OTG_HS_BASE + OTG_HFNUM)
+#define OTG_HS_HPTXSTS MMIO32(USB_OTG_HS_BASE + OTG_HPTXSTS)
+#define OTG_HS_HAINT MMIO32(USB_OTG_HS_BASE + OTG_HAINT)
+#define OTG_HS_HAINTMSK MMIO32(USB_OTG_HS_BASE + OTG_HAINTMSK)
+#define OTG_HS_HPRT MMIO32(USB_OTG_HS_BASE + OTG_HPRT)
+#define OTG_HS_HCCHARx MMIO32(USB_OTG_HS_BASE + OTG_HCCHARx)
+#define OTG_HS_HCINTx MMIO32(USB_OTG_HS_BASE + OTG_HCINTx)
+#define OTG_HS_HCINTMSKx MMIO32(USB_OTG_HS_BASE + OTG_HCINTMSKx)
+#define OTG_HS_HCTSIZx MMIO32(USB_OTG_HS_BASE + OTG_HCTSIZx)
+
+/* Device-mode Control and Status Registers */
+#define OTG_HS_DCFG MMIO32(USB_OTG_HS_BASE + OTG_DCFG)
+#define OTG_HS_DCTL MMIO32(USB_OTG_HS_BASE + OTG_DCTL)
+#define OTG_HS_DSTS MMIO32(USB_OTG_HS_BASE + OTG_DSTS)
+#define OTG_HS_DIEPMSK MMIO32(USB_OTG_HS_BASE + OTG_DIEPMSK)
+#define OTG_HS_DOEPMSK MMIO32(USB_OTG_HS_BASE + OTG_DOEPMSK)
+#define OTG_HS_DAINT MMIO32(USB_OTG_HS_BASE + OTG_DAINT)
+#define OTG_HS_DAINTMSK MMIO32(USB_OTG_HS_BASE + OTG_DAINTMSK)
+#define OTG_HS_DVBUSDIS MMIO32(USB_OTG_HS_BASE + OTG_DVBUSDIS)
+#define OTG_HS_DVBUSPULSE MMIO32(USB_OTG_HS_BASE + OTG_DVBUSPULSE)
+#define OTG_HS_DIEPEMPMSK MMIO32(USB_OTG_HS_BASE + OTG_DIEPEMPMSK)
+#define OTG_HS_DIEPCTL0 MMIO32(USB_OTG_HS_BASE + OTG_DIEPCTL0)
+#define OTG_HS_DIEPCTL(x) MMIO32(USB_OTG_HS_BASE + OTG_DIEPCTL(x))
+#define OTG_HS_DOEPCTL0 MMIO32(USB_OTG_HS_BASE + OTG_DOEPCTL0)
+#define OTG_HS_DOEPCTL(x) MMIO32(USB_OTG_HS_BASE + OTG_DOEPCTL(x))
+#define OTG_HS_DIEPINT(x) MMIO32(USB_OTG_HS_BASE + OTG_DIEPINT(x))
+#define OTG_HS_DOEPINT(x) MMIO32(USB_OTG_HS_BASE + OTG_DOEPINT(x))
+#define OTG_HS_DIEPTSIZ0 MMIO32(USB_OTG_HS_BASE + OTG_DIEPTSIZ0)
+#define OTG_HS_DOEPTSIZ0 MMIO32(USB_OTG_HS_BASE + OTG_DOEPTSIZ0)
+#define OTG_HS_DIEPTSIZ(x) MMIO32(USB_OTG_HS_BASE + OTG_DIEPTSIZ(x)))
+#define OTG_HS_DTXFSTS(x) MMIO32(USB_OTG_HS_BASE + OTG_DTXFSTS(x))
+#define OTG_HS_DOEPTSIZ(x) MMIO32(USB_OTG_HS_BASE + OTG_DOEPTSIZ(x))
+
+/* Power and clock gating control and status register */
+#define OTG_HS_PCGCCTL MMIO32(USB_OTG_HS_BASE + OTG_PCGCCTL)
+
+/* Data FIFO */
+#define OTG_HS_FIFO(x) ((volatile u32*)(USB_OTG_HS_BASE + OTG_FIFO(x)))
+
+/* Global CSRs */
+/* OTG_HS USB control registers (OTG_FS_GOTGCTL) */
+#define OTG_HS_GOTGCTL_BSVLD (1 << 19)
+#define OTG_HS_GOTGCTL_ASVLD (1 << 18)
+#define OTG_HS_GOTGCTL_DBCT (1 << 17)
+#define OTG_HS_GOTGCTL_CIDSTS (1 << 16)
+#define OTG_HS_GOTGCTL_DHNPEN (1 << 11)
+#define OTG_HS_GOTGCTL_HSHNPEN (1 << 10)
+#define OTG_HS_GOTGCTL_HNPRQ (1 << 9)
+#define OTG_HS_GOTGCTL_HNGSCS (1 << 8)
+#define OTG_HS_GOTGCTL_SRQ (1 << 1)
+#define OTG_HS_GOTGCTL_SRQSCS (1 << 0)
+
+/* OTG_FS AHB configuration register (OTG_HS_GAHBCFG) */
+#define OTG_HS_GAHBCFG_GINT 0x0001
+#define OTG_HS_GAHBCFG_TXFELVL 0x0080
+#define OTG_HS_GAHBCFG_PTXFELVL 0x0100
+
+/* OTG_FS USB configuration register (OTG_HS_GUSBCFG) */
+#define OTG_HS_GUSBCFG_TOCAL 0x00000003
+#define OTG_HS_GUSBCFG_SRPCAP 0x00000100
+#define OTG_HS_GUSBCFG_HNPCAP 0x00000200
+#define OTG_HS_GUSBCFG_TRDT_MASK (0xf << 10)
+#define OTG_HS_GUSBCFG_TRDT_16BIT (0x5 << 10)
+#define OTG_HS_GUSBCFG_TRDT_8BIT (0x9 << 10)
+#define OTG_HS_GUSBCFG_NPTXRWEN 0x00004000
+#define OTG_HS_GUSBCFG_FHMOD 0x20000000
+#define OTG_HS_GUSBCFG_FDMOD 0x40000000
+#define OTG_HS_GUSBCFG_CTXPKT 0x80000000
+#define OTG_HS_GUSBCFG_PHYSEL (1 << 6)
+
+/* OTG_FS reset register (OTG_HS_GRSTCTL) */
+#define OTG_HS_GRSTCTL_AHBIDL (1 << 31)
+/* Bits 30:11 - Reserved */
+#define OTG_HS_GRSTCTL_TXFNUM_MASK (0x1f << 6)
+#define OTG_HS_GRSTCTL_TXFFLSH (1 << 5)
+#define OTG_HS_GRSTCTL_RXFFLSH (1 << 4)
+/* Bit 3 - Reserved */
+#define OTG_HS_GRSTCTL_FCRST (1 << 2)
+#define OTG_HS_GRSTCTL_HSRST (1 << 1)
+#define OTG_HS_GRSTCTL_CSRST (1 << 0)
+
+/* OTG_FS interrupt status register (OTG_HS_GINTSTS) */
+#define OTG_HS_GINTSTS_WKUPINT (1 << 31)
+#define OTG_HS_GINTSTS_SRQINT (1 << 30)
+#define OTG_HS_GINTSTS_DISCINT (1 << 29)
+#define OTG_HS_GINTSTS_CIDSCHG (1 << 28)
+/* Bit 27 - Reserved */
+#define OTG_HS_GINTSTS_PTXFE (1 << 26)
+#define OTG_HS_GINTSTS_HCINT (1 << 25)
+#define OTG_HS_GINTSTS_HPRTINT (1 << 24)
+/* Bits 23:22 - Reserved */
+#define OTG_HS_GINTSTS_IPXFR (1 << 21)
+#define OTG_HS_GINTSTS_INCOMPISOOUT (1 << 21)
+#define OTG_HS_GINTSTS_IISOIXFR (1 << 20)
+#define OTG_HS_GINTSTS_OEPINT (1 << 19)
+#define OTG_HS_GINTSTS_IEPINT (1 << 18)
+/* Bits 17:16 - Reserved */
+#define OTG_HS_GINTSTS_EOPF (1 << 15)
+#define OTG_HS_GINTSTS_ISOODRP (1 << 14)
+#define OTG_HS_GINTSTS_ENUMDNE (1 << 13)
+#define OTG_HS_GINTSTS_USBRST (1 << 12)
+#define OTG_HS_GINTSTS_USBSUSP (1 << 11)
+#define OTG_HS_GINTSTS_ESUSP (1 << 10)
+/* Bits 9:8 - Reserved */
+#define OTG_HS_GINTSTS_GONAKEFF (1 << 7)
+#define OTG_HS_GINTSTS_GINAKEFF (1 << 6)
+#define OTG_HS_GINTSTS_NPTXFE (1 << 5)
+#define OTG_HS_GINTSTS_RXFLVL (1 << 4)
+#define OTG_HS_GINTSTS_SOF (1 << 3)
+#define OTG_HS_GINTSTS_OTGINT (1 << 2)
+#define OTG_HS_GINTSTS_MMIS (1 << 1)
+#define OTG_HS_GINTSTS_CMOD (1 << 0)
+
+/* OTG_FS interrupt mask register (OTG_HS_GINTMSK) */
+#define OTG_HS_GINTMSK_MMISM 0x00000002
+#define OTG_HS_GINTMSK_OTGINT 0x00000004
+#define OTG_HS_GINTMSK_SOFM 0x00000008
+#define OTG_HS_GINTMSK_RXFLVLM 0x00000010
+#define OTG_HS_GINTMSK_NPTXFEM 0x00000020
+#define OTG_HS_GINTMSK_GINAKEFFM 0x00000040
+#define OTG_HS_GINTMSK_GONAKEFFM 0x00000080
+#define OTG_HS_GINTMSK_ESUSPM 0x00000400
+#define OTG_HS_GINTMSK_USBSUSPM 0x00000800
+#define OTG_HS_GINTMSK_USBRST 0x00001000
+#define OTG_HS_GINTMSK_ENUMDNEM 0x00002000
+#define OTG_HS_GINTMSK_ISOODRPM 0x00004000
+#define OTG_HS_GINTMSK_EOPFM 0x00008000
+#define OTG_HS_GINTMSK_EPMISM 0x00020000
+#define OTG_HS_GINTMSK_IEPINT 0x00040000
+#define OTG_HS_GINTMSK_OEPINT 0x00080000
+#define OTG_HS_GINTMSK_IISOIXFRM 0x00100000
+#define OTG_HS_GINTMSK_IISOOXFRM 0x00200000
+#define OTG_HS_GINTMSK_IPXFRM 0x00200000
+#define OTG_HS_GINTMSK_PRTIM 0x01000000
+#define OTG_HS_GINTMSK_HCIM 0x02000000
+#define OTG_HS_GINTMSK_PTXFEM 0x04000000
+#define OTG_HS_GINTMSK_CIDSCHGM 0x10000000
+#define OTG_HS_GINTMSK_DISCINT 0x20000000
+#define OTG_HS_GINTMSK_SRQIM 0x40000000
+#define OTG_HS_GINTMSK_WUIM 0x80000000
+
+/* OTG_FS Receive Status Pop Register (OTG_HS_GRXSTSP) */
+/* Bits 31:25 - Reserved */
+#define OTG_HS_GRXSTSP_FRMNUM_MASK (0xf << 21)
+#define OTG_HS_GRXSTSP_PKTSTS_MASK (0xf << 17)
+#define OTG_HS_GRXSTSP_PKTSTS_GOUTNAK (0x1 << 17)
+#define OTG_HS_GRXSTSP_PKTSTS_OUT (0x2 << 17)
+#define OTG_HS_GRXSTSP_PKTSTS_OUT_COMP (0x3 << 17)
+#define OTG_HS_GRXSTSP_PKTSTS_SETUP_COMP (0x4 << 17)
+#define OTG_HS_GRXSTSP_PKTSTS_SETUP (0x6 << 17)
+#define OTG_HS_GRXSTSP_DPID_MASK (0x3 << 15)
+#define OTG_HS_GRXSTSP_DPID_DATA0 (0x0 << 15)
+#define OTG_HS_GRXSTSP_DPID_DATA1 (0x2 << 15)
+#define OTG_HS_GRXSTSP_DPID_DATA2 (0x1 << 15)
+#define OTG_HS_GRXSTSP_DPID_MDATA (0x3 << 15)
+#define OTG_HS_GRXSTSP_BCNT_MASK (0x7ff << 4)
+#define OTG_HS_GRXSTSP_EPNUM_MASK (0xf << 0)
+
+/* OTG_FS general core configuration register (OTG_HS_GCCFG) */
+/* Bits 31:21 - Reserved */
+#define OTG_HS_GCCFG_SOFOUTEN (1 << 20)
+#define OTG_HS_GCCFG_VBUSBSEN (1 << 19)
+#define OTG_HS_GCCFG_VBUSASEN (1 << 18)
+/* Bit 17 - Reserved */
+#define OTG_HS_GCCFG_PWRDWN (1 << 16)
+/* Bits 15:0 - Reserved */
+
+
+/* Device-mode CSRs */
+/* OTG_FS device control register (OTG_HS_DCTL) */
+/* Bits 31:12 - Reserved */
+#define OTG_HS_DCTL_POPRGDNE (1 << 11)
+#define OTG_HS_DCTL_CGONAK (1 << 10)
+#define OTG_HS_DCTL_SGONAK (1 << 9)
+#define OTG_HS_DCTL_SGINAK (1 << 8)
+#define OTG_HS_DCTL_TCTL_MASK (7 << 4)
+#define OTG_HS_DCTL_GONSTS (1 << 3)
+#define OTG_HS_DCTL_GINSTS (1 << 2)
+#define OTG_HS_DCTL_SDIS (1 << 1)
+#define OTG_HS_DCTL_RWUSIG (1 << 0)
+
+/* OTG_FS device configuration register (OTG_HS_DCFG) */
+#define OTG_HS_DCFG_DSPD 0x0003
+#define OTG_HS_DCFG_NZLSOHSK 0x0004
+#define OTG_HS_DCFG_DAD 0x07F0
+#define OTG_HS_DCFG_PFIVL 0x1800
+
+/* OTG_FS Device IN Endpoint Common Interrupt Mask Register (OTG_HS_DIEPMSK) */
+/* Bits 31:10 - Reserved */
+#define OTG_HS_DIEPMSK_BIM (1 << 9)
+#define OTG_HS_DIEPMSK_TXFURM (1 << 8)
+/* Bit 7 - Reserved */
+#define OTG_HS_DIEPMSK_INEPNEM (1 << 6)
+#define OTG_HS_DIEPMSK_INEPNMM (1 << 5)
+#define OTG_HS_DIEPMSK_ITTXFEMSK (1 << 4)
+#define OTG_HS_DIEPMSK_TOM (1 << 3)
+/* Bit 2 - Reserved */
+#define OTG_HS_DIEPMSK_EPDM (1 << 1)
+#define OTG_HS_DIEPMSK_XFRCM (1 << 0)
+
+/* OTG_FS Device OUT Endpoint Common Interrupt Mask Register (OTG_HS_DOEPMSK) */
+/* Bits 31:10 - Reserved */
+#define OTG_HS_DOEPMSK_BOIM (1 << 9)
+#define OTG_HS_DOEPMSK_OPEM (1 << 8)
+/* Bit 7 - Reserved */
+#define OTG_HS_DOEPMSK_B2BSTUP (1 << 6)
+/* Bit 5 - Reserved */
+#define OTG_HS_DOEPMSK_OTEPDM (1 << 4)
+#define OTG_HS_DOEPMSK_STUPM (1 << 3)
+/* Bit 2 - Reserved */
+#define OTG_HS_DOEPMSK_EPDM (1 << 1)
+#define OTG_HS_DOEPMSK_XFRCM (1 << 0)
+
+/* OTG_FS Device Control IN Endpoint 0 Control Register (OTG_HS_DIEPCTL0) */
+#define OTG_HS_DIEPCTL0_EPENA (1 << 31)
+#define OTG_HS_DIEPCTL0_EPDIS (1 << 30)
+/* Bits 29:28 - Reserved */
+#define OTG_HS_DIEPCTLX_SD0PID (1 << 28)
+#define OTG_HS_DIEPCTL0_SNAK (1 << 27)
+#define OTG_HS_DIEPCTL0_CNAK (1 << 26)
+#define OTG_HS_DIEPCTL0_TXFNUM_MASK (0xf << 22)
+#define OTG_HS_DIEPCTL0_STALL (1 << 21)
+/* Bit 20 - Reserved */
+#define OTG_HS_DIEPCTL0_EPTYP_MASK (0x3 << 18)
+#define OTG_HS_DIEPCTL0_NAKSTS (1 << 17)
+/* Bit 16 - Reserved */
+#define OTG_HS_DIEPCTL0_USBAEP (1 << 15)
+/* Bits 14:2 - Reserved */
+#define OTG_HS_DIEPCTL0_MPSIZ_MASK (0x3 << 0)
+#define OTG_HS_DIEPCTL0_MPSIZ_64 (0x0 << 0)
+#define OTG_HS_DIEPCTL0_MPSIZ_32 (0x1 << 0)
+#define OTG_HS_DIEPCTL0_MPSIZ_16 (0x2 << 0)
+#define OTG_HS_DIEPCTL0_MPSIZ_8 (0x3 << 0)
+
+/* OTG_FS Device Control OUT Endpoint 0 Control Register (OTG_HS_DOEPCTL0) */
+#define OTG_HS_DOEPCTL0_EPENA (1 << 31)
+#define OTG_HS_DOEPCTL0_EPDIS (1 << 30)
+/* Bits 29:28 - Reserved */
+#define OTG_HS_DOEPCTLX_SD0PID (1 << 28)
+#define OTG_HS_DOEPCTL0_SNAK (1 << 27)
+#define OTG_HS_DOEPCTL0_CNAK (1 << 26)
+/* Bits 25:22 - Reserved */
+#define OTG_HS_DOEPCTL0_STALL (1 << 21)
+#define OTG_HS_DOEPCTL0_SNPM (1 << 20)
+#define OTG_HS_DOEPCTL0_EPTYP_MASK (0x3 << 18)
+#define OTG_HS_DOEPCTL0_NAKSTS (1 << 17)
+/* Bit 16 - Reserved */
+#define OTG_HS_DOEPCTL0_USBAEP (1 << 15)
+/* Bits 14:2 - Reserved */
+#define OTG_HS_DOEPCTL0_MPSIZ_MASK (0x3 << 0)
+#define OTG_HS_DOEPCTL0_MPSIZ_64 (0x0 << 0)
+#define OTG_HS_DOEPCTL0_MPSIZ_32 (0x1 << 0)
+#define OTG_HS_DOEPCTL0_MPSIZ_16 (0x2 << 0)
+#define OTG_HS_DOEPCTL0_MPSIZ_8 (0x3 << 0)
+
+/* OTG_FS Device IN Endpoint Interrupt Register (OTG_HS_DIEPINTx) */
+/* Bits 31:8 - Reserved */
+#define OTG_HS_DIEPINTX_TXFE (1 << 7)
+#define OTG_HS_DIEPINTX_INEPNE (1 << 6)
+/* Bit 5 - Reserved */
+#define OTG_HS_DIEPINTX_ITTXFE (1 << 4)
+#define OTG_HS_DIEPINTX_TOC (1 << 3)
+/* Bit 2 - Reserved */
+#define OTG_HS_DIEPINTX_EPDISD (1 << 1)
+#define OTG_HS_DIEPINTX_XFRC (1 << 0)
+
+/* OTG_FS Device IN Endpoint Interrupt Register (OTG_HS_DOEPINTx) */
+/* Bits 31:7 - Reserved */
+#define OTG_HS_DOEPINTX_B2BSTUP (1 << 6)
+/* Bit 5 - Reserved */
+#define OTG_HS_DOEPINTX_OTEPDIS (1 << 4)
+#define OTG_HS_DOEPINTX_STUP (1 << 3)
+/* Bit 2 - Reserved */
+#define OTG_HS_DOEPINTX_EPDISD (1 << 1)
+#define OTG_HS_DOEPINTX_XFRC (1 << 0)
+
+/* OTG_FS Device OUT Endpoint 0 Transfer Size Regsiter (OTG_HS_DOEPTSIZ0) */
+/* Bit 31 - Reserved */
+#define OTG_HS_DIEPSIZ0_STUPCNT_1 (0x1 << 29)
+#define OTG_HS_DIEPSIZ0_STUPCNT_2 (0x2 << 29)
+#define OTG_HS_DIEPSIZ0_STUPCNT_3 (0x3 << 29)
+#define OTG_HS_DIEPSIZ0_STUPCNT_MASK (0x3 << 29)
+/* Bits 28:20 - Reserved */
+#define OTG_HS_DIEPSIZ0_PKTCNT (1 << 19)
+/* Bits 18:7 - Reserved */
+#define OTG_HS_DIEPSIZ0_XFRSIZ_MASK (0x7f << 0)
+
+#endif
diff --git a/include/libopencm3/stm32/pwr.h b/include/libopencm3/stm32/pwr.h
index e709f3d..1d907a9 100644
--- a/include/libopencm3/stm32/pwr.h
+++ b/include/libopencm3/stm32/pwr.h
@@ -1,22 +1,8 @@
-/** @defgroup STM32F1xx_pwr_defines PWR Defines
+/* This provides unification of code over STM32F subfamilies */
-@ingroup STM32F_defines
-
-@brief <b>libopencm3 STM32F Power Control</b>
-
-@version 1.0.0
-
-@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
-
-@date 17 August 2012
-
-LGPL License Terms @ref lgpl_license
- */
/*
* This file is part of the libopencm3 project.
*
- * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
- *
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
@@ -31,101 +17,15 @@ LGPL License Terms @ref lgpl_license
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
-/**@{*/
-
-#ifndef LIBOPENCM3_PWR_H
-#define LIBOPENCM3_PWR_H
-
-#include <libopencm3/stm32/memorymap.h>
-#include <libopencm3/cm3/common.h>
-
-/* --- PWR registers ------------------------------------------------------- */
-
-/* Power control register (PWR_CR) */
-#define PWR_CR MMIO32(POWER_CONTROL_BASE + 0x00)
-
-/* Power control/status register (PWR_CSR) */
-#define PWR_CSR MMIO32(POWER_CONTROL_BASE + 0x04)
-
-/* --- PWR_CR values ------------------------------------------------------- */
-
-/* Bits [31:9]: Reserved, must be kept at reset value. */
-
-/* DBP: Disable backup domain write protection */
-#define PWR_CR_DBP (1 << 8)
-
-/* PLS[7:5]: PVD level selection */
-#define PWR_CR_PLS_LSB 5
-/** @defgroup pwr_pls PVD level selection
-@ingroup STM32F_pwr_defines
-
-@{*/
-#define PWR_CR_PLS_2V2 (0x0 << PWR_CR_PLS_LSB)
-#define PWR_CR_PLS_2V3 (0x1 << PWR_CR_PLS_LSB)
-#define PWR_CR_PLS_2V4 (0x2 << PWR_CR_PLS_LSB)
-#define PWR_CR_PLS_2V5 (0x3 << PWR_CR_PLS_LSB)
-#define PWR_CR_PLS_2V6 (0x4 << PWR_CR_PLS_LSB)
-#define PWR_CR_PLS_2V7 (0x5 << PWR_CR_PLS_LSB)
-#define PWR_CR_PLS_2V8 (0x6 << PWR_CR_PLS_LSB)
-#define PWR_CR_PLS_2V9 (0x7 << PWR_CR_PLS_LSB)
-/**@}*/
-#define PWR_CR_PLS_MASK (0x7 << PWR_CR_PLS_LSB)
-
-/* PVDE: Power voltage detector enable */
-#define PWR_CR_PVDE (1 << 4)
-
-/* CSBF: Clear standby flag */
-#define PWR_CR_CSBF (1 << 3)
-
-/* CWUF: Clear wakeup flag */
-#define PWR_CR_CWUF (1 << 2)
-
-/* PDDS: Power down deepsleep */
-#define PWR_CR_PDDS (1 << 1)
-
-/* LPDS: Low-power deepsleep */
-#define PWR_CR_LPDS (1 << 0)
-
-/* --- PWR_CSR values ------------------------------------------------------ */
-
-/* Bits [31:9]: Reserved, must be kept at reset value. */
-
-/* EWUP: Enable WKUP pin */
-#define PWR_CSR_EWUP (1 << 8)
-
-/* Bits [7:3]: Reserved, must be kept at reset value. */
-
-/* PVDO: PVD output */
-#define PWR_CSR_PVDO (1 << 2)
-
-/* SBF: Standby flag */
-#define PWR_CSR_SBF (1 << 1)
-
-/* WUF: Wakeup flag */
-#define PWR_CSR_WUF (1 << 0)
-
-/* --- PWR function prototypes ------------------------------------------- */
-
-BEGIN_DECLS
-
-void pwr_disable_backup_domain_write_protect(void);
-void pwr_enable_backup_domain_write_protect(void);
-void pwr_enable_power_voltage_detect(u32 pvd_level);
-void pwr_disable_power_voltage_detect(void);
-void pwr_clear_standby_flag(void);
-void pwr_clear_wakeup_flag(void);
-void pwr_set_standby_mode(void);
-void pwr_set_stop_mode(void);
-void pwr_voltage_regulator_on_in_stop(void);
-void pwr_voltage_regulator_low_power_in_stop(void);
-void pwr_enable_wakeup_pin(void);
-void pwr_disable_wakeup_pin(void);
-bool pwr_voltage_high(void);
-bool pwr_get_standby_flag(void);
-bool pwr_get_wakeup_flag(void);
-
-END_DECLS
-
+#if defined(STM32F1)
+# include <libopencm3/stm32/f1/pwr.h>
+#elif defined(STM32F2)
+# include <libopencm3/stm32/f2/pwr.h>
+#elif defined(STM32F4)
+# include <libopencm3/stm32/f4/pwr.h>
+#elif defined(STM32L1)
+# include <libopencm3/stm32/l1/pwr.h>
+#else
+# error "stm32 family not defined."
#endif
-/**@}*/
diff --git a/include/libopencm3/stm32/rcc.h b/include/libopencm3/stm32/rcc.h
new file mode 100644
index 0000000..2f2c9f3
--- /dev/null
+++ b/include/libopencm3/stm32/rcc.h
@@ -0,0 +1,31 @@
+/* This provides unification of code over STM32F subfamilies */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#if defined(STM32F1)
+# include <libopencm3/stm32/f1/rcc.h>
+#elif defined(STM32F2)
+# include <libopencm3/stm32/f2/rcc.h>
+#elif defined(STM32F4)
+# include <libopencm3/stm32/f4/rcc.h>
+#elif defined(STM32L1)
+# include <libopencm3/stm32/l1/rcc.h>
+#else
+# error "stm32 family not defined."
+#endif
+
diff --git a/include/libopencm3/stm32/rtc.h b/include/libopencm3/stm32/rtc.h
new file mode 100644
index 0000000..a927dd8
--- /dev/null
+++ b/include/libopencm3/stm32/rtc.h
@@ -0,0 +1,31 @@
+/* This provides unification of code over STM32 subfamilies */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#if defined(STM32F1)
+# include <libopencm3/stm32/f1/rtc.h>
+#elif defined(STM32F2)
+# include <libopencm3/stm32/f2/rtc.h>
+#elif defined(STM32F4)
+# include <libopencm3/stm32/f4/rtc.h>
+#elif defined(STM32L1)
+# include <libopencm3/stm32/l1/rtc.h>
+#else
+# error "stm32 family not defined."
+#endif
+
diff --git a/include/libopencm3/stm32/spi.h b/include/libopencm3/stm32/spi.h
index f23df3a..28aadd1 100644
--- a/include/libopencm3/stm32/spi.h
+++ b/include/libopencm3/stm32/spi.h
@@ -1,24 +1,8 @@
-/** @defgroup spi_defines SPI Defines
-
-@ingroup STM32F_defines
-
-@brief <b>libopencm3 Defined Constants and Types for the STM32 SPI </b>
-
-@version 1.0.0
-
-@author @htmlonly &copy; @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
-@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
-
-@date 12 October 2012
-
-LGPL License Terms @ref lgpl_license
- */
+/* This provides unification of code over STM32F subfamilies */
/*
* This file is part of the libopencm3 project.
*
- * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
- *
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
@@ -33,380 +17,15 @@ LGPL License Terms @ref lgpl_license
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
-#ifndef LIBOPENCM3_SPI_H
-#define LIBOPENCM3_SPI_H
-
-#include <libopencm3/stm32/memorymap.h>
-#include <libopencm3/cm3/common.h>
-
-/**@{*/
-
-/* Registers can be accessed as 16bit or 32bit values. */
-
-/* --- Convenience macros -------------------------------------------------- */
-
-/****************************************************************************/
-/** @defgroup spi_reg_base SPI Register base address
-@ingroup spi_defines
-
-@{*/
-#define SPI1 SPI1_BASE
-#define SPI2 SPI2_I2S_BASE
-#define SPI3 SPI3_I2S_BASE
-/**@}*/
-
-/* --- SPI registers ------------------------------------------------------- */
-
-/* Control register 1 (SPIx_CR1) */
-/* Note: Not used in I2S mode. */
-#define SPI_CR1(spi_base) MMIO32(spi_base + 0x00)
-#define SPI1_CR1 SPI_CR1(SPI1_BASE)
-#define SPI2_CR1 SPI_CR1(SPI2_I2S_BASE)
-#define SPI3_CR1 SPI_CR1(SPI3_I2S_BASE)
-
-/* Control register 2 (SPIx_CR2) */
-#define SPI_CR2(spi_base) MMIO32(spi_base + 0x04)
-#define SPI1_CR2 SPI_CR2(SPI1_BASE)
-#define SPI2_CR2 SPI_CR2(SPI2_I2S_BASE)
-#define SPI3_CR2 SPI_CR2(SPI3_I2S_BASE)
-
-/* Status register (SPIx_SR) */
-#define SPI_SR(spi_base) MMIO32(spi_base + 0x08)
-#define SPI1_SR SPI_SR(SPI1_BASE)
-#define SPI2_SR SPI_SR(SPI2_I2S_BASE)
-#define SPI3_SR SPI_SR(SPI3_I2S_BASE)
-
-/* Data register (SPIx_DR) */
-#define SPI_DR(spi_base) MMIO32(spi_base + 0x0c)
-#define SPI1_DR SPI_DR(SPI1_BASE)
-#define SPI2_DR SPI_DR(SPI2_I2S_BASE)
-#define SPI3_DR SPI_DR(SPI3_I2S_BASE)
-
-/* CRC polynomial register (SPIx_CRCPR) */
-/* Note: Not used in I2S mode. */
-#define SPI_CRCPR(spi_base) MMIO32(spi_base + 0x10)
-#define SPI1_CRCPR SPI_CRCPR(SPI1_BASE)
-#define SPI2_CRCPR SPI_CRCPR(SPI2_I2S_BASE)
-#define SPI3_CRCPR SPI_CRCPR(SPI3_I2S_BASE)
-
-/* RX CRC register (SPIx_RXCRCR) */
-/* Note: Not used in I2S mode. */
-#define SPI_RXCRCR(spi_base) MMIO32(spi_base + 0x14)
-#define SPI1_RXCRCR SPI_RXCRCR(SPI1_BASE)
-#define SPI2_RXCRCR SPI_RXCRCR(SPI2_I2S_BASE)
-#define SPI3_RXCRCR SPI_RXCRCR(SPI3_I2S_BASE)
-
-/* TX CRC register (SPIx_RXCRCR) */
-/* Note: Not used in I2S mode. */
-#define SPI_TXCRCR(spi_base) MMIO32(spi_base + 0x18)
-#define SPI1_TXCRCR SPI_TXCRCR(SPI1_BASE)
-#define SPI2_TXCRCR SPI_TXCRCR(SPI2_I2S_BASE)
-#define SPI3_TXCRCR SPI_TXCRCR(SPI3_I2S_BASE)
-
-/* I2S configuration register (SPIx_I2SCFGR) */
-#define SPI_I2SCFGR(spi_base) MMIO32(spi_base + 0x1c)
-#define SPI1_I2SCFGR SPI_I2SCFGR(SPI1_BASE)
-#define SPI2_I2SCFGR SPI_I2SCFGR(SPI2_I2S_BASE)
-#define SPI3_I2SCFGR SPI_I2SCFGR(SPI3_I2S_BASE)
-
-/* I2S prescaler register (SPIx_I2SPR) */
-#define SPI_I2SPR(spi_base) MMIO32(spi_base + 0x20)
-#define SPI1_I2SPR SPI_I2SPR(SPI1_BASE)
-#define SPI2_I2SPR SPI_I2SPR(SPI2_I2S_BASE)
-#define SPI3_I2SPR SPI_I2SPR(SPI3_I2S_BASE)
-
-/* --- SPI_CR1 values ------------------------------------------------------ */
-
-/* Note: None of the CR1 bits are used in I2S mode. */
-
-/* BIDIMODE: Bidirectional data mode enable */
-#define SPI_CR1_BIDIMODE_2LINE_UNIDIR (0 << 15)
-#define SPI_CR1_BIDIMODE_1LINE_BIDIR (1 << 15)
-#define SPI_CR1_BIDIMODE (1 << 15)
-
-/* BIDIOE: Output enable in bidirectional mode */
-#define SPI_CR1_BIDIOE (1 << 14)
-
-/* CRCEN: Hardware CRC calculation enable */
-#define SPI_CR1_CRCEN (1 << 13)
-
-/* CRCNEXT: Transmit CRC next */
-#define SPI_CR1_CRCNEXT (1 << 12)
-
-/* DFF: Data frame format */
-/****************************************************************************/
-/** @defgroup spi_dff SPI data frame format
-@ingroup spi_defines
-
-@{*/
-#define SPI_CR1_DFF_8BIT (0 << 11)
-#define SPI_CR1_DFF_16BIT (1 << 11)
-/**@}*/
-#define SPI_CR1_DFF (1 << 11)
-
-/* RXONLY: Receive only */
-#define SPI_CR1_RXONLY (1 << 10)
-
-/* SSM: Software slave management */
-#define SPI_CR1_SSM (1 << 9)
-
-/* SSI: Internal slave select */
-#define SPI_CR1_SSI (1 << 8)
-
-/* LSBFIRST: Frame format */
-/****************************************************************************/
-/** @defgroup spi_lsbfirst SPI lsb/msb first
-@ingroup spi_defines
-
-@{*/
-#define SPI_CR1_MSBFIRST (0 << 7)
-#define SPI_CR1_LSBFIRST (1 << 7)
-/**@}*/
-
-/* SPE: SPI enable */
-#define SPI_CR1_SPE (1 << 6)
-
-/* BR[2:0]: Baud rate control */
-/****************************************************************************/
-/** @defgroup spi_baudrate SPI peripheral baud rates
-@ingroup spi_defines
-
-@{*/
-#define SPI_CR1_BAUDRATE_FPCLK_DIV_2 (0x00 << 3)
-#define SPI_CR1_BAUDRATE_FPCLK_DIV_4 (0x01 << 3)
-#define SPI_CR1_BAUDRATE_FPCLK_DIV_8 (0x02 << 3)
-#define SPI_CR1_BAUDRATE_FPCLK_DIV_16 (0x03 << 3)
-#define SPI_CR1_BAUDRATE_FPCLK_DIV_32 (0x04 << 3)
-#define SPI_CR1_BAUDRATE_FPCLK_DIV_64 (0x05 << 3)
-#define SPI_CR1_BAUDRATE_FPCLK_DIV_128 (0x06 << 3)
-#define SPI_CR1_BAUDRATE_FPCLK_DIV_256 (0x07 << 3)
-/**@}*/
-/****************************************************************************/
-/** @defgroup spi_br_pre SPI peripheral baud rate prescale values
-@ingroup spi_defines
-
-@{*/
-#define SPI_CR1_BR_FPCLK_DIV_2 0x0
-#define SPI_CR1_BR_FPCLK_DIV_4 0x1
-#define SPI_CR1_BR_FPCLK_DIV_8 0x2
-#define SPI_CR1_BR_FPCLK_DIV_16 0x3
-#define SPI_CR1_BR_FPCLK_DIV_32 0x4
-#define SPI_CR1_BR_FPCLK_DIV_64 0x5
-#define SPI_CR1_BR_FPCLK_DIV_128 0x6
-#define SPI_CR1_BR_FPCLK_DIV_256 0x7
-/**@}*/
-
-/* MSTR: Master selection */
-#define SPI_CR1_MSTR (1 << 2)
-
-/* CPOL: Clock polarity */
-/****************************************************************************/
-/** @defgroup spi_cpol SPI clock polarity
-@ingroup spi_defines
-
-@{*/
-#define SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE (0 << 1)
-#define SPI_CR1_CPOL_CLK_TO_1_WHEN_IDLE (1 << 1)
-/**@}*/
-#define SPI_CR1_CPOL (1 << 1)
-
-/* CPHA: Clock phase */
-/****************************************************************************/
-/** @defgroup spi_cpha SPI clock phase
-@ingroup spi_defines
-
-@{*/
-#define SPI_CR1_CPHA_CLK_TRANSITION_1 (0 << 0)
-#define SPI_CR1_CPHA_CLK_TRANSITION_2 (1 << 0)
-/**@}*/
-#define SPI_CR1_CPHA (1 << 0)
-
-/* --- SPI_CR2 values ------------------------------------------------------ */
-
-/* Bits [15:8]: Reserved. Forced to 0 by hardware. */
-
-/* TXEIE: Tx buffer empty interrupt enable */
-#define SPI_CR2_TXEIE (1 << 7)
-
-/* RXNEIE: Rx buffer not empty interrupt enable */
-#define SPI_CR2_RXNEIE (1 << 6)
-
-/* ERRIE: Error interrupt enable */
-#define SPI_CR2_ERRIE (1 << 5)
-
-/* Bits [4:3]: Reserved. Forced to 0 by hardware. */
-
-/* SSOE: SS output enable */
-/* Note: Not used in I2S mode. */
-#define SPI_CR2_SSOE (1 << 2)
-
-/* TXDMAEN: Tx buffer DMA enable */
-#define SPI_CR2_TXDMAEN (1 << 1)
-
-/* RXDMAEN: Rx buffer DMA enable */
-#define SPI_CR2_RXDMAEN (1 << 0)
-
-/* --- SPI_SR values ------------------------------------------------------- */
-
-/* Bits [15:8]: Reserved. Forced to 0 by hardware. */
-
-/* BSY: Busy flag */
-#define SPI_SR_BSY (1 << 7)
-
-/* OVR: Overrun flag */
-#define SPI_SR_OVR (1 << 6)
-
-/* MODF: Mode fault */
-/* Note: Not used in I2S mode. */
-#define SPI_SR_MODF (1 << 5)
-
-/* CRCERR: CRC error flag */
-/* Note: Not used in I2S mode. */
-#define SPI_SR_CRCERR (1 << 4)
-
-/* UDR: Underrun flag */
-/* Note: Not used in SPI mode. */
-#define SPI_SR_UDR (1 << 3)
-
-/* CHSIDE: Channel side */
-/* Note: Not used in SPI mode. No meaning in PCM mode. */
-#define SPI_SR_CHSIDE (1 << 2)
-
-/* TXE: Transmit buffer empty */
-#define SPI_SR_TXE (1 << 1)
-
-/* RXNE: Receive buffer not empty */
-#define SPI_SR_RXNE (1 << 0)
-
-/* --- SPI_DR values ------------------------------------------------------- */
-
-/* SPI_DR[15:0]: Data Register. */
-
-/* --- SPI_CRCPR values ---------------------------------------------------- */
-
-/* Note: Not used in I2S mode. */
-/* SPI_CRCPR [15:0]: CRC Polynomial Register. */
-
-/* --- SPI_RXCRCR values --------------------------------------------------- */
-
-/* Note: Not used in I2S mode. */
-/* SPI_RXCRCR [15:0]: RX CRC Register. */
-
-/* --- SPI_TXCRCR values --------------------------------------------------- */
-
-/* Note: Not used in I2S mode. */
-/* SPI_TXCRCR [15:0]: TX CRC Register. */
-
-/* --- SPI_I2SCFGR values -------------------------------------------------- */
-
-/* Note: None of these bits are used in SPI mode. */
-
-/* Bits [15:12]: Reserved. Forced to 0 by hardware. */
-
-/* I2SMOD: I2S mode selection */
-#define SPI_I2SCFGR_I2SMOD (1 << 11)
-
-/* I2SE: I2S enable */
-#define SPI_I2SCFGR_I2SE (1 << 10)
-
-/* I2SCFG[9:8]: I2S configuration mode */
-#define SPI_I2SCFGR_I2SCFG_LSB 8
-#define SPI_I2SCFGR_I2SCFG_SLAVE_TRANSMIT 0x0
-#define SPI_I2SCFGR_I2SCFG_SLAVE_RECEIVE 0x1
-#define SPI_I2SCFGR_I2SCFG_MASTER_TRANSMIT 0x2
-#define SPI_I2SCFGR_I2SCFG_MASTER_RECEIVE 0x3
-
-/* PCMSYNC: PCM frame synchronization */
-#define SPI_I2SCFGR_PCMSYNC (1 << 7)
-
-/* Bit 6: Reserved. Forced to 0 by hardware. */
-
-/* I2SSTD[5:4]: I2S standard selection */
-#define SPI_I2SCFGR_I2SSTD_LSB 4
-#define SPI_I2SCFGR_I2SSTD_I2S_PHILLIPS 0x0
-#define SPI_I2SCFGR_I2SSTD_MSB_JUSTIFIED 0x1
-#define SPI_I2SCFGR_I2SSTD_LSB_JUSTIFIED 0x2
-#define SPI_I2SCFGR_I2SSTD_PCM 0x3
-
-/* CKPOL: Steady state clock polarity */
-#define SPI_I2SCFGR_CKPOL (1 << 3)
-
-/* DATLEN[2:1]: Data length to be transferred */
-#define SPI_I2SCFGR_DATLEN_LSB 1
-#define SPI_I2SCFGR_DATLEN_16BIT 0x0
-#define SPI_I2SCFGR_DATLEN_24BIT 0x1
-#define SPI_I2SCFGR_DATLEN_32BIT 0x2
-
-/* CHLEN: Channel length */
-#define SPI_I2SCFGR_CHLEN (1 << 0)
-
-/* --- SPI_I2SPR values ---------------------------------------------------- */
-
-/* Note: None of these bits are used in SPI mode. */
-
-/* Bits [15:10]: Reserved. Forced to 0 by hardware. */
-
-/* MCKOE: Master clock output enable */
-#define SPI_I2SPR_MCKOE (1 << 9)
-
-/* ODD: Odd factor for the prescaler */
-#define SPI_I2SPR_ODD (1 << 8)
-
-/* I2SDIV[7:0]: I2S linear prescaler */
-/* 0 and 1 are forbidden values */
-
-/* --- Function prototypes ------------------------------------------------- */
-
-BEGIN_DECLS
-
-void spi_reset(u32 spi_peripheral);
-int spi_init_master(u32 spi, u32 br, u32 cpol, u32 cpha, u32 dff, u32 lsbfirst);
-void spi_enable(u32 spi);
-void spi_disable(u32 spi);
-void spi_write(u32 spi, u16 data);
-void spi_send(u32 spi, u16 data);
-u16 spi_read(u32 spi);
-u16 spi_xfer(u32 spi, u16 data);
-void spi_set_bidirectional_mode(u32 spi);
-void spi_set_unidirectional_mode(u32 spi);
-void spi_set_bidirectional_receive_only_mode(u32 spi);
-void spi_set_bidirectional_transmit_only_mode(u32 spi);
-void spi_enable_crc(u32 spi);
-void spi_disable_crc(u32 spi);
-void spi_set_next_tx_from_buffer(u32 spi);
-void spi_set_next_tx_from_crc(u32 spi);
-void spi_set_dff_8bit(u32 spi);
-void spi_set_dff_16bit(u32 spi);
-void spi_set_full_duplex_mode(u32 spi);
-void spi_set_receive_only_mode(u32 spi);
-void spi_disable_software_slave_management(u32 spi);
-void spi_enable_software_slave_management(u32 spi);
-void spi_set_nss_high(u32 spi);
-void spi_set_nss_low(u32 spi);
-void spi_send_lsb_first(u32 spi);
-void spi_send_msb_first(u32 spi);
-void spi_set_baudrate_prescaler(u32 spi, u8 baudrate);
-void spi_set_master_mode(u32 spi);
-void spi_set_slave_mode(u32 spi);
-void spi_set_clock_polarity_1(u32 spi);
-void spi_set_clock_polarity_0(u32 spi);
-void spi_set_clock_phase_1(u32 spi);
-void spi_set_clock_phase_0(u32 spi);
-void spi_enable_tx_buffer_empty_interrupt(u32 spi);
-void spi_disable_tx_buffer_empty_interrupt(u32 spi);
-void spi_enable_rx_buffer_not_empty_interrupt(u32 spi);
-void spi_disable_rx_buffer_not_empty_interrupt(u32 spi);
-void spi_enable_error_interrupt(u32 spi);
-void spi_disable_error_interrupt(u32 spi);
-void spi_enable_ss_output(u32 spi);
-void spi_disable_ss_output(u32 spi);
-void spi_enable_tx_dma(u32 spi);
-void spi_disable_tx_dma(u32 spi);
-void spi_enable_rx_dma(u32 spi);
-void spi_disable_rx_dma(u32 spi);
-
-END_DECLS
-
-/**@}*/
-
+#if defined(STM32F1)
+# include <libopencm3/stm32/f1/spi.h>
+#elif defined(STM32F2)
+# include <libopencm3/stm32/f2/spi.h>
+#elif defined(STM32F4)
+# include <libopencm3/stm32/f4/spi.h>
+#elif defined(STM32L1)
+# include <libopencm3/stm32/l1/spi.h>
+#else
+# error "stm32 family not defined."
#endif
+
diff --git a/include/libopencm3/stm32/f2/syscfg.h b/include/libopencm3/stm32/syscfg.h
index 7426f16..7426f16 100644
--- a/include/libopencm3/stm32/f2/syscfg.h
+++ b/include/libopencm3/stm32/syscfg.h
diff --git a/include/libopencm3/stm32/systick.h b/include/libopencm3/stm32/systick.h
deleted file mode 100644
index e42c4e6..0000000
--- a/include/libopencm3/stm32/systick.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/** @defgroup STM32F_systick_defines SysTick Defines
-
-@brief <b>libopencm3 Defined Constants and Types for the STM32F SysTick </b>
-
-@ingroup STM32F_defines
-
-@version 1.0.0
-
-@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
-
-@date 19 August 2012
-
-LGPL License Terms @ref lgpl_license
- */
-
-/*
- * This file is part of the libopencm3 project.
- *
- * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library. If not, see <http://www.gnu.org/licenses/>.
- */
-
-/**@{*/
-
-#ifndef LIBOPENCM3_SYSTICK_H
-#define LIBOPENCM3_SYSTICK_H
-
-#include <libopencm3/stm32/memorymap.h>
-#include <libopencm3/cm3/common.h>
-
-/* --- SYSTICK registers --------------------------------------------------- */
-
-/* Control and status register (STK_CTRL) */
-#define STK_CTRL MMIO32(SYS_TICK_BASE + 0x00)
-
-/* reload value register (STK_LOAD) */
-#define STK_LOAD MMIO32(SYS_TICK_BASE + 0x04)
-
-/* current value register (STK_VAL) */
-#define STK_VAL MMIO32(SYS_TICK_BASE + 0x08)
-
-/* calibration value register (STK_CALIB) */
-#define STK_CALIB MMIO32(SYS_TICK_BASE + 0x0C)
-
-/* --- STK_CTRL values ----------------------------------------------------- */
-/* Bits [31:17] Reserved, must be kept cleared. */
-/* COUNTFLAG: */
-#define STK_CTRL_COUNTFLAG (1 << 16)
-/* Bits [15:3] Reserved, must be kept cleared. */
-/* CLKSOURCE: Clock source selection */
-#define STK_CTRL_CLKSOURCE (1 << 2)
-#define STK_CTRL_CLKSOURCE_LSB 2
-/** @defgroup systick_clksource Clock source selection
-@ingroup STM32F_systick_defines
-
-@{*/
-#define STK_CTRL_CLKSOURCE_AHB_DIV8 0
-#define STK_CTRL_CLKSOURCE_AHB 1
-/**@}*/
-
-/* TICKINT: SysTick exception request enable */
-#define STK_CTRL_TICKINT (1 << 1)
-/* ENABLE: Counter enable */
-#define STK_CTRL_ENABLE (1 << 0)
-
-/* --- STK_LOAD values ----------------------------------------------------- */
-/* Bits [31:24] Reserved, must be kept cleared. */
-/* RELOAD[23:0]: RELOAD value */
-
-/* --- STK_VAL values ------------------------------------------------------ */
-/* Bits [31:24] Reserved, must be kept cleared. */
-/* CURRENT[23:0]: Current counter value */
-
-/* --- STK_CALIB values ---------------------------------------------------- */
-/* NOREF: NOREF flag */
-#define STK_CALIB_NOREF (1 << 31)
-/* SKEW: SKEW flag */
-#define STK_CALIB_SKEW (1 << 30)
-/* Bits [29:24] Reserved, must be kept cleared. */
-/* TENMS[23:0]: Calibration value */
-
-/* --- Function Prototypes ------------------------------------------------- */
-
-BEGIN_DECLS
-
-void systick_set_reload(u32 value);
-u32 systick_get_value(void);
-void systick_set_clocksource(u8 clocksource);
-void systick_interrupt_enable(void);
-void systick_interrupt_disable(void);
-void systick_counter_enable(void);
-void systick_counter_disable(void);
-u8 systick_get_countflag(void);
-
-END_DECLS
-
-#endif
-/**@}*/
-
diff --git a/include/libopencm3/stm32/usart.h b/include/libopencm3/stm32/usart.h
index 088e67b..fc6cbcb 100644
--- a/include/libopencm3/stm32/usart.h
+++ b/include/libopencm3/stm32/usart.h
@@ -1,23 +1,8 @@
-/** @defgroup STM32F_usart_defines USART Defines
-
-@brief <b>libopencm3 Defined Constants and Types for the STM32F Digital to Analog Converter </b>
-
-@ingroup STM32F_defines
-
-@version 1.0.0
-
-@author @htmlonly &copy; @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
-
-@date 1 September 2012
-
-LGPL License Terms @ref lgpl_license
- */
+/* This provides unification of code over STM32F subfamilies */
/*
* This file is part of the libopencm3 project.
*
- * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
- *
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
@@ -32,350 +17,15 @@ LGPL License Terms @ref lgpl_license
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
-/**@{*/
-
-#ifndef LIBOPENCM3_USART_H
-#define LIBOPENCM3_USART_H
-
-#include <libopencm3/stm32/memorymap.h>
-#include <libopencm3/cm3/common.h>
-
-/* --- Convenience macros -------------------------------------------------- */
-
-/****************************************************************************/
-/** @defgroup usart_reg_base USART register base addresses
-@ingroup STM32F_usart_defines
-
-@{*/
-#define USART1 USART1_BASE
-#define USART2 USART2_BASE
-#define USART3 USART3_BASE
-/**@}*/
-#define UART4 UART4_BASE
-#define UART5 UART5_BASE
-
-/* --- USART registers ----------------------------------------------------- */
-
-/* Status register (USARTx_SR) */
-#define USART_SR(usart_base) MMIO32(usart_base + 0x00)
-#define USART1_SR USART_SR(USART1_BASE)
-#define USART2_SR USART_SR(USART2_BASE)
-#define USART3_SR USART_SR(USART3_BASE)
-#define UART4_SR USART_SR(UART4_BASE)
-#define UART5_SR USART_SR(UART5_BASE)
-
-/* Data register (USARTx_DR) */
-#define USART_DR(usart_base) MMIO32(usart_base + 0x04)
-#define USART1_DR USART_DR(USART1_BASE)
-#define USART2_DR USART_DR(USART2_BASE)
-#define USART3_DR USART_DR(USART3_BASE)
-#define UART4_DR USART_DR(UART4_BASE)
-#define UART5_DR USART_DR(UART5_BASE)
-
-/* Baud rate register (USARTx_BRR) */
-#define USART_BRR(usart_base) MMIO32(usart_base + 0x08)
-#define USART1_BRR USART_BRR(USART1_BASE)
-#define USART2_BRR USART_BRR(USART2_BASE)
-#define USART3_BRR USART_BRR(USART3_BASE)
-#define UART4_BRR USART_BRR(UART4_BASE)
-#define UART5_BRR USART_BRR(UART5_BASE)
-
-/* Control register 1 (USARTx_CR1) */
-#define USART_CR1(usart_base) MMIO32(usart_base + 0x0c)
-#define USART1_CR1 USART_CR1(USART1_BASE)
-#define USART2_CR1 USART_CR1(USART2_BASE)
-#define USART3_CR1 USART_CR1(USART3_BASE)
-#define UART4_CR1 USART_CR1(UART4_BASE)
-#define UART5_CR1 USART_CR1(UART5_BASE)
-
-/* Control register 2 (USARTx_CR2) */
-#define USART_CR2(usart_base) MMIO32(usart_base + 0x10)
-#define USART1_CR2 USART_CR2(USART1_BASE)
-#define USART2_CR2 USART_CR2(USART2_BASE)
-#define USART3_CR2 USART_CR2(USART3_BASE)
-#define UART4_CR2 USART_CR2(UART4_BASE)
-#define UART5_CR2 USART_CR2(UART5_BASE)
-
-/* Control register 3 (USARTx_CR3) */
-#define USART_CR3(usart_base) MMIO32(usart_base + 0x14)
-#define USART1_CR3 USART_CR3(USART1_BASE)
-#define USART2_CR3 USART_CR3(USART2_BASE)
-#define USART3_CR3 USART_CR3(USART3_BASE)
-#define UART4_CR3 USART_CR3(UART4_BASE)
-#define UART5_CR3 USART_CR3(UART5_BASE)
-
-/* Guard time and prescaler register (USARTx_GTPR) */
-#define USART_GTPR(usart_base) MMIO32(usart_base + 0x18)
-#define USART1_GTPR USART_GTPR(USART1_BASE)
-#define USART2_GTPR USART_GTPR(USART2_BASE)
-#define USART3_GTPR USART_GTPR(USART3_BASE)
-#define UART4_GTPR USART_GTPR(UART4_BASE)
-#define UART5_GTPR USART_GTPR(UART5_BASE)
-
-/* --- USART_SR values ----------------------------------------------------- */
-/****************************************************************************/
-/** @defgroup usart_sr_flags USART Status register Flags
-@ingroup STM32F_usart_defines
-
-@{*/
-
-/** CTS: CTS flag */
-/** @note: undefined on UART4 and UART5 */
-#define USART_SR_CTS (1 << 9)
-
-/** LBD: LIN break detection flag */
-#define USART_SR_LBD (1 << 8)
-
-/** TXE: Transmit data buffer empty */
-#define USART_SR_TXE (1 << 7)
-
-/** TC: Transmission complete */
-#define USART_SR_TC (1 << 6)
-
-/** RXNE: Read data register not empty */
-#define USART_SR_RXNE (1 << 5)
-
-/** IDLE: Idle line detected */
-#define USART_SR_IDLE (1 << 4)
-
-/** ORE: Overrun error */
-#define USART_SR_ORE (1 << 3)
-
-/** NE: Noise error flag */
-#define USART_SR_NE (1 << 2)
-
-/** FE: Framing error */
-#define USART_SR_FE (1 << 1)
-
-/** PE: Parity error */
-#define USART_SR_PE (1 << 0)
-/**@}*/
-
-/* --- USART_DR values ----------------------------------------------------- */
-
-/* USART_DR[8:0]: DR[8:0]: Data value */
-#define USART_DR_MASK 0x1FF
-
-/* --- USART_BRR values ---------------------------------------------------- */
-
-/* DIV_Mantissa[11:0]: mantissa of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_MASK (0xFFF << 4)
-/* DIV_Fraction[3:0]: fraction of USARTDIV */
-#define USART_BRR_DIV_FRACTION_MASK 0xF
-
-/* --- USART_CR1 values ---------------------------------------------------- */
-
-/* UE: USART enable */
-#define USART_CR1_UE (1 << 13)
-
-/* M: Word length */
-#define USART_CR1_M (1 << 12)
-
-/* WAKE: Wakeup method */
-#define USART_CR1_WAKE (1 << 11)
-
-/* PCE: Parity control enable */
-#define USART_CR1_PCE (1 << 10)
-
-/* PS: Parity selection */
-#define USART_CR1_PS (1 << 9)
-
-/* PEIE: PE interrupt enable */
-#define USART_CR1_PEIE (1 << 8)
-
-/* TXEIE: TXE interrupt enable */
-#define USART_CR1_TXEIE (1 << 7)
-
-/* TCIE: Transmission complete interrupt enable */
-#define USART_CR1_TCIE (1 << 6)
-
-/* RXNEIE: RXNE interrupt enable */
-#define USART_CR1_RXNEIE (1 << 5)
-
-/* IDLEIE: IDLE interrupt enable */
-#define USART_CR1_IDLEIE (1 << 4)
-
-/* TE: Transmitter enable */
-#define USART_CR1_TE (1 << 3)
-
-/* RE: Receiver enable */
-#define USART_CR1_RE (1 << 2)
-
-/* RWU: Receiver wakeup */
-#define USART_CR1_RWU (1 << 1)
-
-/* SBK: Send break */
-#define USART_CR1_SBK (1 << 0)
-
-/* --- USART_CR2 values ---------------------------------------------------- */
-
-/* LINEN: LIN mode enable */
-#define USART_CR2_LINEN (1 << 14)
-
-/* STOP[13:12]: STOP bits */
-#define USART_CR2_STOPBITS_1 (0x00 << 12) /* 1 stop bit */
-#define USART_CR2_STOPBITS_0_5 (0x01 << 12) /* 0.5 stop bits */
-#define USART_CR2_STOPBITS_2 (0x02 << 12) /* 2 stop bits */
-#define USART_CR2_STOPBITS_1_5 (0x03 << 12) /* 1.5 stop bits */
-#define USART_CR2_STOPBITS_MASK (0x03 << 12)
-#define USART_CR2_STOPBITS_SHIFT 12
-
-/* CLKEN: Clock enable */
-#define USART_CR2_CLKEN (1 << 11)
-
-/* CPOL: Clock polarity */
-#define USART_CR2_CPOL (1 << 10)
-
-/* CPHA: Clock phase */
-#define USART_CR2_CPHA (1 << 9)
-
-/* LBCL: Last bit clock pulse */
-#define USART_CR2_LBCL (1 << 8)
-
-/* LBDIE: LIN break detection interrupt enable */
-#define USART_CR2_LBDIE (1 << 6)
-
-/* LBDL: LIN break detection length */
-#define USART_CR2_LBDL (1 << 5)
-
-/* ADD[3:0]: Addres of the usart node */
-#define USART_CR2_ADD_MASK 0xF
-
-/* --- USART_CR3 values ---------------------------------------------------- */
-
-/* CTSIE: CTS interrupt enable */
-/* Note: N/A on UART4 & UART5 */
-#define USART_CR3_CTSIE (1 << 10)
-
-/* CTSE: CTS enable */
-/* Note: N/A on UART4 & UART5 */
-#define USART_CR3_CTSE (1 << 9)
-
-/* RTSE: RTS enable */
-/* Note: N/A on UART4 & UART5 */
-#define USART_CR3_RTSE (1 << 8)
-
-/* DMAT: DMA enable transmitter */
-/* Note: N/A on UART5 */
-#define USART_CR3_DMAT (1 << 7)
-
-/* DMAR: DMA enable receiver */
-/* Note: N/A on UART5 */
-#define USART_CR3_DMAR (1 << 6)
-
-/* SCEN: Smartcard mode enable */
-/* Note: N/A on UART4 & UART5 */
-#define USART_CR3_SCEN (1 << 5)
-
-/* NACK: Smartcard NACK enable */
-/* Note: N/A on UART4 & UART5 */
-#define USART_CR3_NACK (1 << 4)
-
-/* HDSEL: Half-duplex selection */
-#define USART_CR3_HDSEL (1 << 3)
-
-/* IRLP: IrDA low-power */
-#define USART_CR3_IRLP (1 << 2)
-
-/* IREN: IrDA mode enable */
-#define USART_CR3_IREN (1 << 1)
-
-/* EIE: Error interrupt enable */
-#define USART_CR3_EIE (1 << 0)
-
-/* --- USART_GTPR values --------------------------------------------------- */
-
-/* GT[7:0]: Guard time value */
-/* Note: N/A on UART4 & UART5 */
-#define USART_GTPR_GT_MASK (0xFF << 8)
-
-/* PSC[7:0]: Prescaler value */
-/* Note: N/A on UART4/5 */
-#define USART_GTPR_PSC_MASK 0xFF
-
-/* TODO */ /* Note to Uwe: what needs to be done here? */
-
-/* --- Convenience defines ------------------------------------------------- */
-
-/* CR1_PCE / CR1_PS combined values */
-/****************************************************************************/
-/** @defgroup usart_cr1_parity USART Parity Selection
-@ingroup STM32F_usart_defines
-
-@{*/
-#define USART_PARITY_NONE 0x00
-#define USART_PARITY_EVEN USART_CR1_PCE
-#define USART_PARITY_ODD (USART_CR1_PS | USART_CR1_PCE)
-/**@}*/
-#define USART_PARITY_MASK (USART_CR1_PS | USART_CR1_PCE)
-
-/* CR1_TE/CR1_RE combined values */
-/****************************************************************************/
-/** @defgroup usart_cr1_mode USART Tx/Rx Mode Selection
-@ingroup STM32F_usart_defines
-
-@{*/
-#define USART_MODE_RX USART_CR1_RE
-#define USART_MODE_TX USART_CR1_TE
-#define USART_MODE_TX_RX (USART_CR1_RE | USART_CR1_TE)
-/**@}*/
-#define USART_MODE_MASK (USART_CR1_RE | USART_CR1_TE)
-
-/****************************************************************************/
-/** @defgroup usart_cr2_stopbits USART Stop Bit Selection
-@ingroup STM32F_usart_defines
-
-@{*/
-#define USART_STOPBITS_1 USART_CR2_STOPBITS_1 /* 1 stop bit */
-#define USART_STOPBITS_0_5 USART_CR2_STOPBITS_0_5 /* 0.5 stop bits */
-#define USART_STOPBITS_2 USART_CR2_STOPBITS_2 /* 2 stop bits */
-#define USART_STOPBITS_1_5 USART_CR2_STOPBITS_1_5 /* 1.5 stop bits */
-/**@}*/
-
-/* CR3_CTSE/CR3_RTSE combined values */
-/****************************************************************************/
-/** @defgroup usart_cr3_flowcontrol USART Hardware Flow Control Selection
-@ingroup STM32F_usart_defines
-
-@{*/
-#define USART_FLOWCONTROL_NONE 0x00
-#define USART_FLOWCONTROL_RTS USART_CR3_RTSE
-#define USART_FLOWCONTROL_CTS USART_CR3_CTSE
-#define USART_FLOWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)
-/**@}*/
-#define USART_FLOWCONTROL_MASK (USART_CR3_RTSE | USART_CR3_CTSE)
-
-/* --- Function prototypes ------------------------------------------------- */
-
-BEGIN_DECLS
-
-void usart_set_baudrate(u32 usart, u32 baud);
-void usart_set_databits(u32 usart, u32 bits);
-void usart_set_stopbits(u32 usart, u32 stopbits);
-void usart_set_parity(u32 usart, u32 parity);
-void usart_set_mode(u32 usart, u32 mode);
-void usart_set_flow_control(u32 usart, u32 flowcontrol);
-void usart_enable(u32 usart);
-void usart_disable(u32 usart);
-void usart_send(u32 usart, u16 data);
-u16 usart_recv(u32 usart);
-void usart_wait_send_ready(u32 usart);
-void usart_wait_recv_ready(u32 usart);
-void usart_send_blocking(u32 usart, u16 data);
-u16 usart_recv_blocking(u32 usart);
-void usart_enable_rx_dma(u32 usart);
-void usart_disable_rx_dma(u32 usart);
-void usart_enable_tx_dma(u32 usart);
-void usart_disable_tx_dma(u32 usart);
-void usart_enable_rx_interrupt(u32 usart);
-void usart_disable_rx_interrupt(u32 usart);
-void usart_enable_tx_interrupt(u32 usart);
-void usart_disable_tx_interrupt(u32 usart);
-bool usart_get_flag(u32 usart, u32 flag);
-bool usart_get_interrupt_source(u32 usart, u32 flag);
-
-END_DECLS
-
+#if defined(STM32F1)
+# include <libopencm3/stm32/f1/usart.h>
+#elif defined(STM32F2)
+# include <libopencm3/stm32/f2/usart.h>
+#elif defined(STM32F4)
+# include <libopencm3/stm32/f4/usart.h>
+#elif defined(STM32L1)
+# include <libopencm3/stm32/l1/usart.h>
+#else
+# error "stm32 family not defined."
#endif
-/**@}*/