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-rw-r--r--include/libopencm3/stm32/can.h4
-rw-r--r--include/libopencm3/stm32/crc.h24
-rw-r--r--include/libopencm3/stm32/dac.h130
-rw-r--r--include/libopencm3/stm32/doc-stm32f.h24
-rw-r--r--include/libopencm3/stm32/exti.h4
-rw-r--r--include/libopencm3/stm32/f1/adc.h227
-rw-r--r--include/libopencm3/stm32/f1/desig.h56
-rw-r--r--include/libopencm3/stm32/f1/dma.h42
-rw-r--r--include/libopencm3/stm32/f1/doc-stm32f1.h15
-rw-r--r--include/libopencm3/stm32/f1/flash.h4
-rw-r--r--include/libopencm3/stm32/f1/gpio.h250
-rw-r--r--include/libopencm3/stm32/f1/memorymap.h5
-rw-r--r--include/libopencm3/stm32/f1/nvic_f1.h15
-rw-r--r--include/libopencm3/stm32/f1/rcc.h104
-rw-r--r--include/libopencm3/stm32/f1/rtc.h4
-rw-r--r--include/libopencm3/stm32/f1/scb.h5
-rw-r--r--include/libopencm3/stm32/f2/flash.h4
-rw-r--r--include/libopencm3/stm32/f2/gpio.h4
-rw-r--r--include/libopencm3/stm32/f2/rcc.h4
-rw-r--r--include/libopencm3/stm32/f2/scb.h5
-rw-r--r--include/libopencm3/stm32/f2/timer.h4
-rw-r--r--include/libopencm3/stm32/f4/flash.h4
-rw-r--r--include/libopencm3/stm32/f4/gpio.h4
-rw-r--r--include/libopencm3/stm32/f4/pwr.h4
-rw-r--r--include/libopencm3/stm32/f4/rcc.h4
-rw-r--r--include/libopencm3/stm32/f4/scb.h5
-rw-r--r--include/libopencm3/stm32/f4/timer.h4
-rw-r--r--include/libopencm3/stm32/i2c.h4
-rw-r--r--include/libopencm3/stm32/iwdg.h40
-rw-r--r--include/libopencm3/stm32/nvic.h31
-rw-r--r--include/libopencm3/stm32/pwr.h60
-rw-r--r--include/libopencm3/stm32/sdio.h426
-rw-r--r--include/libopencm3/stm32/spi.h4
-rw-r--r--include/libopencm3/stm32/systick.h29
-rw-r--r--include/libopencm3/stm32/timer.h225
-rw-r--r--include/libopencm3/stm32/usart.h8
36 files changed, 1656 insertions, 130 deletions
diff --git a/include/libopencm3/stm32/can.h b/include/libopencm3/stm32/can.h
index 0a05798..d6636d5 100644
--- a/include/libopencm3/stm32/can.h
+++ b/include/libopencm3/stm32/can.h
@@ -615,6 +615,8 @@
/* --- CAN functions -------------------------------------------------------- */
+BEGIN_DECLS
+
void can_reset(u32 canport);
int can_init(u32 canport, bool ttcm, bool abom, bool awum, bool nart,
bool rflm, bool txfp, u32 sjw, u32 ts1, u32 ts2, u32 brp);
@@ -639,4 +641,6 @@ void can_receive(u32 canport, u8 fifo, bool release, u32 *id, bool *ext,
void can_fifo_release(u32 canport, u8 fifo);
+END_DECLS
+
#endif
diff --git a/include/libopencm3/stm32/crc.h b/include/libopencm3/stm32/crc.h
index 6ae4085..3848191 100644
--- a/include/libopencm3/stm32/crc.h
+++ b/include/libopencm3/stm32/crc.h
@@ -53,6 +53,30 @@
/* --- CRC function prototypes --------------------------------------------- */
+BEGIN_DECLS
+
/* TODO */
+/**
+ * Reset the CRC calculator to initial values.
+ */
+void crc_reset(void);
+
+/**
+ * Add a word to the crc calculator and return the result.
+ * @param data new word to add to the crc calculator
+ * @return final crc calculator value
+ */
+u32 crc_calculate(u32 data);
+
+/**
+ * Add a block of data to the CRC calculator and return the final result
+ * @param datap pointer to the start of a block of 32bit data words
+ * @param size length of data, in 32bit increments
+ * @return final CRC calculator value
+ */
+u32 crc_calculate_block(u32 *datap, int size);
+
+END_DECLS
+
#endif
diff --git a/include/libopencm3/stm32/dac.h b/include/libopencm3/stm32/dac.h
index 0402eb0..75d4edb 100644
--- a/include/libopencm3/stm32/dac.h
+++ b/include/libopencm3/stm32/dac.h
@@ -1,3 +1,19 @@
+/** @defgroup STM32F_dac_defines DAC Defines
+
+@brief <b>libopencm3 Defined Constants and Types for the STM32F Digital to Analog Converter </b>
+
+@ingroup STM32F_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2012 Felix Held <felix-libopencm3@felixheld.de>
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies
+
+@date 18 August 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
/*
* This file is part of the libopencm3 project.
*
@@ -17,6 +33,8 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
+/**@{*/
+
#ifndef LIBOPENCM3_DAC_H
#define LIBOPENCM3_DAC_H
@@ -69,7 +87,7 @@
/* --- DAC_CR values ------------------------------------------------------- */
/* DMAUDRIE2: DAC channel2 DMA underrun interrupt enable */
-/* doesn't exist in most members of the stm32f1 family */
+/* doesn't exist in most members of the STM32F1 family */
#define DAC_CR_DMAUDRIE2 (1 << 29)
/* DMAEN2: DAC channel2 DMA enable */
@@ -80,6 +98,11 @@
* Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**n)-1
*/
#define DAC_CR_MAMP2_SHIFT 24
+/** @defgroup dac_mamp2 DAC Channel 2 LFSR Mask and Triangle Wave Amplitude values
+@ingroup STM32F_dac_defines
+
+Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n)-1
+@{*/
#define DAC_CR_MAMP2_1 (0x0 << DAC_CR_MAMP2_SHIFT)
#define DAC_CR_MAMP2_2 (0x1 << DAC_CR_MAMP2_SHIFT)
#define DAC_CR_MAMP2_3 (0x2 << DAC_CR_MAMP2_SHIFT)
@@ -92,6 +115,7 @@
#define DAC_CR_MAMP2_10 (0x9 << DAC_CR_MAMP2_SHIFT)
#define DAC_CR_MAMP2_11 (0xA << DAC_CR_MAMP2_SHIFT)
#define DAC_CR_MAMP2_12 (0xB << DAC_CR_MAMP2_SHIFT)
+/**@}*/
/* WAVE2[1:0]: DAC channel2 noise/triangle wave generation enable */
/* Legend:
@@ -102,9 +126,18 @@
* Note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled)
*/
#define DAC_CR_WAVE2_SHIFT 22
-#define DAC_CR_WAVE2_DIS (0x0 << DAC_CR_WAVE2_SHIFT)
+#define DAC_CR_WAVE2_DIS (0x3 << DAC_CR_WAVE2_SHIFT)
+/** @defgroup dac_wave2_en DAC Channel 2 Waveform Generation Enable
+@ingroup STM32F_dac_defines
+
+@li NOISE: Noise wave generation enabled
+@li TRI: Triangle wave generation enabled
+
+@note: only used if bit TEN2 is set (DAC channel2 trigger enabled)
+@{*/
#define DAC_CR_WAVE2_NOISE (0x1 << DAC_CR_WAVE2_SHIFT)
#define DAC_CR_WAVE2_TRI (0x2 << DAC_CR_WAVE2_SHIFT)
+/**@}*/
/* TSEL2[2:0]: DAC channel2 trigger selection */
/* Legend:
@@ -125,6 +158,25 @@
* Note: this is *not* valid for the STM32L1 family
*/
#define DAC_CR_TSEL2_SHIFT 19
+/** @defgroup dac_trig2_sel DAC Channel 2 Trigger Source Selection
+@ingroup STM32F_dac_defines
+
+@li T6: Timer 6 TRGO event
+@li T3: Timer 3 TRGO event
+@li T8: Timer 8 TRGO event
+@li T7: Timer 7 TRGO event
+@li T5: Timer 5 TRGO event
+@li T15: Timer 15 TRGO event
+@li T2: Timer 2 TRGO event
+@li T4: Timer 4 TRGO event
+@li E9: External line9
+@li SW: Software trigger
+
+@note: Refer to the timer documentation for details of the TRGO event.
+@note: T3 replaced by T8 and T5 replaced by T15 in some devices.
+@note: this is <b>not</b> valid for the STM32L1 family.
+@note: only used if bit TEN2 is set (DAC channel 2 trigger enabled)
+@{*/
#define DAC_CR_TSEL2_T6 (0x0 << DAC_CR_TSEL2_SHIFT)
#define DAC_CR_TSEL2_T3 (0x1 << DAC_CR_TSEL2_SHIFT)
#define DAC_CR_TSEL2_T8 (0x1 << DAC_CR_TSEL2_SHIFT)
@@ -135,6 +187,7 @@
#define DAC_CR_TSEL2_T4 (0x5 << DAC_CR_TSEL2_SHIFT)
#define DAC_CR_TSEL2_E9 (0x6 << DAC_CR_TSEL2_SHIFT)
#define DAC_CR_TSEL2_SW (0x7 << DAC_CR_TSEL2_SHIFT)
+/**@}*/
/* TEN2: DAC channel2 trigger enable */
#define DAC_CR_TEN2 (1 << 18)
@@ -146,7 +199,7 @@
#define DAC_CR_EN2 (1 << 16)
/* DMAUDRIE1: DAC channel1 DMA underrun interrupt enable */
-/* doesn't exist in most members of the stm32f1 family */
+/* doesn't exist in most members of the STM32F1 family */
#define DAC_CR_DMAUDRIE1 (1 << 13)
/* DMAEN1: DAC channel1 DMA enable */
@@ -157,6 +210,11 @@
* Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**n)-1
*/
#define DAC_CR_MAMP1_SHIFT 8
+/** @defgroup dac_mamp1 DAC Channel 1 LFSR Mask and Triangle Wave Amplitude values
+@ingroup STM32F_dac_defines
+
+Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n+1)-1
+@{*/
#define DAC_CR_MAMP1_1 (0x0 << DAC_CR_MAMP1_SHIFT)
#define DAC_CR_MAMP1_2 (0x1 << DAC_CR_MAMP1_SHIFT)
#define DAC_CR_MAMP1_3 (0x2 << DAC_CR_MAMP1_SHIFT)
@@ -169,6 +227,7 @@
#define DAC_CR_MAMP1_10 (0x9 << DAC_CR_MAMP1_SHIFT)
#define DAC_CR_MAMP1_11 (0xA << DAC_CR_MAMP1_SHIFT)
#define DAC_CR_MAMP1_12 (0xB << DAC_CR_MAMP1_SHIFT)
+/**@}*/
/* WAVE1[1:0]: DAC channel1 noise/triangle wave generation enable */
/* Legend:
@@ -179,9 +238,19 @@
* Note: only used if bit TEN1 = 1 (DAC channel1 trigger enabled)
*/
#define DAC_CR_WAVE1_SHIFT 6
-#define DAC_CR_WAVE1_DIS (0x0 << DAC_CR_WAVE1_SHIFT)
+#define DAC_CR_WAVE1_DIS (0x3 << DAC_CR_WAVE1_SHIFT)
+/** @defgroup dac_wave1_en DAC Channel 1 Waveform Generation Enable
+@ingroup STM32F_dac_defines
+
+@li DIS: wave generation disabled
+@li NOISE: Noise wave generation enabled
+@li TRI: Triangle wave generation enabled
+
+@note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled)
+@{*/
#define DAC_CR_WAVE1_NOISE (0x1 << DAC_CR_WAVE1_SHIFT)
#define DAC_CR_WAVE1_TRI (0x2 << DAC_CR_WAVE1_SHIFT)
+/**@}*/
/* TSEL1[2:0]: DAC channel1 trigger selection */
/* Legend:
@@ -202,6 +271,25 @@
* Note: this is *not* valid for the STM32L1 family
*/
#define DAC_CR_TSEL1_SHIFT 3
+/** @defgroup dac_trig1_sel DAC Channel 1 Trigger Source Selection
+@ingroup STM32F_dac_defines
+
+@li T6: Timer 6 TRGO event
+@li T3: Timer 3 TRGO event
+@li T8: Timer 8 TRGO event
+@li T7: Timer 7 TRGO event
+@li T5: Timer 5 TRGO event
+@li T15: Timer 15 TRGO event
+@li T2: Timer 2 TRGO event
+@li T4: Timer 4 TRGO event
+@li E9: External line 9
+@li SW: Software trigger
+
+@note: Refer to the timer documentation for details of the TRGO event.
+@note: T3 replaced by T8 and T5 replaced by T15 in some devices.
+@note: this is <b>not</b> valid for the STM32L1 family.
+@note: only used if bit TEN2 is set (DAC channel 1 trigger enabled).
+@{*/
#define DAC_CR_TSEL1_T6 (0x0 << DAC_CR_TSEL1_SHIFT)
#define DAC_CR_TSEL1_T3 (0x1 << DAC_CR_TSEL1_SHIFT)
#define DAC_CR_TSEL1_T8 (0x1 << DAC_CR_TSEL1_SHIFT)
@@ -212,6 +300,7 @@
#define DAC_CR_TSEL1_T4 (0x5 << DAC_CR_TSEL1_SHIFT)
#define DAC_CR_TSEL1_E9 (0x6 << DAC_CR_TSEL1_SHIFT)
#define DAC_CR_TSEL1_SW (0x7 << DAC_CR_TSEL1_SHIFT)
+/**@}*/
/* TEN1: DAC channel1 trigger enable */
#define DAC_CR_TEN1 (1 << 2)
@@ -292,11 +381,38 @@
#define DAC_DOR2_DACC2DOR_LSB (1 << 0)
#define DAC_DOR2_DACC2DOR_MSK (0x0FFF << 0)
+/** DAC channel identifier */
+typedef enum {
+ CHANNEL_1, CHANNEL_2, CHANNEL_D
+} data_channel;
-/* --- Function prototypes ------------------------------------------------- */
-
+/** DAC data size (8/12 bits), alignment (right/left) */
+typedef enum {
+ RIGHT8, RIGHT12, LEFT12
+} data_align;
-/* TODO */
+/* --- Function prototypes ------------------------------------------------- */
+BEGIN_DECLS
+
+void dac_enable(data_channel dac_channel);
+void dac_disable(data_channel dac_channel);
+void dac_buffer_enable(data_channel dac_channel);
+void dac_buffer_disable(data_channel dac_channel);
+void dac_dma_enable(data_channel dac_channel);
+void dac_dma_disable(data_channel dac_channel);
+void dac_trigger_enable(data_channel dac_channel);
+void dac_trigger_disable(data_channel dac_channel);
+void dac_set_trigger_source(u32 dac_trig_src);
+void dac_set_waveform_generation(u32 dac_wave_ens);
+void dac_disable_waveform_generation(data_channel dac_channel);
+void dac_set_waveform_characteristics(u32 dac_mamp);
+void dac_load_data_buffer_single(u32 dac_data, data_align dac_data_format, data_channel dac_channel);
+void dac_load_data_buffer_dual(u32 dac_data1, u32 dac_data2, data_align dac_data_format);
+void dac_software_trigger(data_channel dac_channel);
+
+END_DECLS
#endif
+/**@}*/
+
diff --git a/include/libopencm3/stm32/doc-stm32f.h b/include/libopencm3/stm32/doc-stm32f.h
new file mode 100644
index 0000000..b0532de
--- /dev/null
+++ b/include/libopencm3/stm32/doc-stm32f.h
@@ -0,0 +1,24 @@
+/** @defgroup STM32F_defines STM32F Top Level Defines
+
+@brief Defined Constants and Types for the STM32F series
+
+@ingroup STM32F
+
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies ksarkies@internode.on.net
+
+@version 1.0.0
+
+@date 18 August 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
+/** @defgroup STM32F_files STM32F Top Level Files
+
+@brief Common Files for ST Microelectronics STM32F series.
+
+@ingroup STM32F
+
+*/
+
+
diff --git a/include/libopencm3/stm32/exti.h b/include/libopencm3/stm32/exti.h
index d1935ad..7645825 100644
--- a/include/libopencm3/stm32/exti.h
+++ b/include/libopencm3/stm32/exti.h
@@ -61,10 +61,14 @@ typedef enum trigger_e {
EXTI_TRIGGER_BOTH,
} exti_trigger_type;
+BEGIN_DECLS
+
void exti_set_trigger(u32 extis, exti_trigger_type trig);
void exti_enable_request(u32 extis);
void exti_disable_request(u32 extis);
void exti_reset_request(u32 extis);
void exti_select_source(u32 exti, u32 gpioport);
+END_DECLS
+
#endif
diff --git a/include/libopencm3/stm32/f1/adc.h b/include/libopencm3/stm32/f1/adc.h
index 563e75d..b1396a5 100644
--- a/include/libopencm3/stm32/f1/adc.h
+++ b/include/libopencm3/stm32/f1/adc.h
@@ -1,3 +1,17 @@
+/** @defgroup STM32F1xx_adc_defines ADC Defines
+
+@brief <b>Defined Constants and Types for the STM32F1xx Analog to Digital Converters</b>
+
+@ingroup STM32F1xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2009 Edward Cheeseman <evbuilder@users.sourceforge.net>
+
+@date 18 August 2012
+
+LGPL License Terms @ref lgpl_license
+ */
/*
* This file is part of the libopencm3 project.
*
@@ -17,6 +31,8 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
+/**@{*/
+
#ifndef LIBOPENCM3_ADC_H
#define LIBOPENCM3_ADC_H
@@ -26,9 +42,15 @@
/* --- Convenience macros -------------------------------------------------- */
/* ADC port base addresses (for convenience) */
+/****************************************************************************/
+/** @defgroup adc_reg_base ADC register base addresses
+@ingroup STM32F1xx_adc_defines
+
+@{*/
#define ADC1 ADC1_BASE
#define ADC2 ADC2_BASE
#define ADC3 ADC3_BASE
+/**@}*/
/* --- ADC registers ------------------------------------------------------- */
@@ -140,6 +162,35 @@
#define ADC2_DR ADC_DR(ADC2)
#define ADC3_DR ADC_DR(ADC3)
+/* --- ADC Channels ------------------------------------------------------- */
+
+/****************************************************************************/
+/** @defgroup adc_channel ADC Channel Numbers
+@ingroup STM32F1xx_adc_defines
+
+@{*/
+#define ADC_CHANNEL0 0x00
+#define ADC_CHANNEL1 0x01
+#define ADC_CHANNEL2 0x02
+#define ADC_CHANNEL3 0x03
+#define ADC_CHANNEL4 0x04
+#define ADC_CHANNEL5 0x05
+#define ADC_CHANNEL6 0x06
+#define ADC_CHANNEL7 0x07
+#define ADC_CHANNEL8 0x08
+#define ADC_CHANNEL9 0x09
+#define ADC_CHANNEL10 0x0A
+#define ADC_CHANNEL11 0x0B
+#define ADC_CHANNEL12 0x0C
+#define ADC_CHANNEL13 0x0D
+#define ADC_CHANNEL14 0x0E
+#define ADC_CHANNEL15 0x0F
+#define ADC_CHANNEL16 0x10
+#define ADC_CHANNEL17 0x11
+/**@}*/
+#define ADC_MASK 0x1F
+#define ADC_SHIFT 0
+
/* --- ADC_SR values ------------------------------------------------------- */
#define ADC_SR_STRT (1 << 4)
@@ -171,20 +222,42 @@
* SIM: Slow interleaved mode only.
* ATM: Alternate trigger mode only.
*/
+/****************************************************************************/
+/* ADC_CR1 DUALMOD[3:0] ADC Mode Selection */
+/** @defgroup adc_cr1_dualmod ADC Mode Selection
+@ingroup STM32F1xx_adc_defines
+
+@{*/
+/** Independent (non-dual) mode */
#define ADC_CR1_DUALMOD_IND (0x0 << 16)
+/** Combined regular simultaneous + injected simultaneous mode. */
#define ADC_CR1_DUALMOD_CRSISM (0x1 << 16)
+/** Combined regular simultaneous + alternate trigger mode. */
#define ADC_CR1_DUALMOD_CRSATM (0x2 << 16)
+/** Combined injected simultaneous + fast interleaved mode. */
#define ADC_CR1_DUALMOD_CISFIM (0x3 << 16)
+/** Combined injected simultaneous + slow interleaved mode. */
#define ADC_CR1_DUALMOD_CISSIM (0x4 << 16)
+/** Injected simultaneous mode only. */
#define ADC_CR1_DUALMOD_ISM (0x5 << 16)
+/** Regular simultaneous mode only. */
#define ADC_CR1_DUALMOD_RSM (0x6 << 16)
+/** Fast interleaved mode only. */
#define ADC_CR1_DUALMOD_FIM (0x7 << 16)
+/** Slow interleaved mode only. */
#define ADC_CR1_DUALMOD_SIM (0x8 << 16)
+/** Alternate trigger mode only. */
#define ADC_CR1_DUALMOD_ATM (0x9 << 16)
+/**@}*/
#define ADC_CR1_DUALMOD_MASK (0xF << 16)
#define ADC_CR1_DUALMOD_SHIFT 16
/* DISCNUM[2:0]: Discontinous mode channel count. */
+/****************************************************************************/
+/** @defgroup adc_cr1_discnum ADC Number of channels in discontinuous mode.
+@ingroup STM32F1xx_adc_defines
+
+@{*/
#define ADC_CR1_DISCNUM_1CHANNELS (0x0 << 13)
#define ADC_CR1_DISCNUM_2CHANNELS (0x1 << 13)
#define ADC_CR1_DISCNUM_3CHANNELS (0x2 << 13)
@@ -193,31 +266,32 @@
#define ADC_CR1_DISCNUM_6CHANNELS (0x5 << 13)
#define ADC_CR1_DISCNUM_7CHANNELS (0x6 << 13)
#define ADC_CR1_DISCNUM_8CHANNELS (0x7 << 13)
+/**@}*/
#define ADC_CR1_DISCNUM_MASK (0x7 << 13)
#define ADC_CR1_DISCNUM_SHIFT 13
-/* JDISCEN: Discontinous mode on injected channels. */
+/* JDISCEN: */ /** Discontinous mode on injected channels. */
#define ADC_CR1_JDISCEN (1 << 12)
-/* DISCEN: Discontinous mode on regular channels. */
+/* DISCEN: */ /** Discontinous mode on regular channels. */
#define ADC_CR1_DISCEN (1 << 11)
-/* JAUTO: Automatic Injection Group conversion. */
+/* JAUTO: */ /** Automatic Injection Group conversion. */
#define ADC_CR1_JAUTO (1 << 10)
-/* AWDSGL: Enable the watchdog on a single channel in scan mode. */
+/* AWDSGL: */ /** Enable the watchdog on a single channel in scan mode. */
#define ADC_CR1_AWDSGL (1 << 9)
-/* SCAN: Scan mode. */
+/* SCAN: */ /** Scan mode. */
#define ADC_CR1_SCAN (1 << 8)
-/* JEOCIE: Interrupt enable for injected channels. */
+/* JEOCIE: */ /** Interrupt enable for injected channels. */
#define ADC_CR1_JEOCIE (1 << 7)
-/* AWDIE: Analog watchdog interrupt enable. */
+/* AWDIE: */ /** Analog watchdog interrupt enable. */
#define ADC_CR1_AWDIE (1 << 6)
-/* EOCIE: Interrupt enable EOC. */
+/* EOCIE: */ /** Interrupt enable EOC. */
#define ADC_CR1_EOCIE (1 << 5)
/* AWDCH[4:0]: Analog watchdog channel bits. (Up to 17 other values reserved) */
@@ -227,6 +301,12 @@
* ADC2: Analog channel 16 and 17 are internally connected to V_SS.
* ADC3: Analog channel 9, 14, 15, 16 and 17 are internally connected to V_SS.
*/
+/****************************************************************************/
+/* ADC_CR1 AWDCH[4:0] ADC watchdog channel */
+/** @defgroup adc_watchdog_channel ADC watchdog channel
+@ingroup STM32F1xx_adc_defines
+
+@{*/
#define ADC_CR1_AWDCH_CHANNEL0 (0x00 << 0)
#define ADC_CR1_AWDCH_CHANNEL1 (0x01 << 0)
#define ADC_CR1_AWDCH_CHANNEL2 (0x02 << 0)
@@ -245,41 +325,72 @@
#define ADC_CR1_AWDCH_CHANNEL15 (0x0F << 0)
#define ADC_CR1_AWDCH_CHANNEL16 (0x10 << 0)
#define ADC_CR1_AWDCH_CHANNEL17 (0x11 << 0)
+/**@}*/
#define ADC_CR1_AWDCH_MASK (0x1F << 0)
#define ADC_CR1_AWDCH_SHIFT 0
/* --- ADC_CR2 values ------------------------------------------------------ */
-/* TSVREFE: Temperature sensor and V_REFINT enable. (ADC1 only!) */
+/* TSVREFE: */ /** Temperature sensor and V_REFINT enable. (ADC1 only!) */
#define ADC_CR2_TSVREFE (1 << 23)
-/* SWSTART: Start conversion of regular channels. */
+/* SWSTART: */ /** Start conversion of regular channels. */
#define ADC_CR2_SWSTART (1 << 22)
-/* JSWSTART: Start conversion of injected channels. */
+/* JSWSTART: */ /** Start conversion of injected channels. */
#define ADC_CR2_JSWSTART (1 << 21)
-/* EXTTRIG: External trigger conversion mode for regular channels. */
+/* EXTTRIG: */ /** External trigger conversion mode for regular channels. */
#define ADC_CR2_EXTTRIG (1 << 20)
/* EXTSEL[2:0]: External event select for regular group. */
/* The following are only valid for ADC1 and ADC2. */
+/****************************************************************************/
+/* ADC_CR2 EXTSEL[2:0] ADC Trigger Identifier for ADC1 and ADC2 */
+/** @defgroup adc_trigger_regular_12 ADC Trigger Identifier for ADC1 and ADC2
+@ingroup STM32F1xx_adc_defines
+
+@{*/
+/** Timer 1 Compare Output 1 */
#define ADC_CR2_EXTSEL_TIM1_CC1 (0x0 << 17)
+/** Timer 1 Compare Output 2 */
#define ADC_CR2_EXTSEL_TIM1_CC2 (0x1 << 17)
+/** Timer 1 Compare Output 3 */
#define ADC_CR2_EXTSEL_TIM1_CC3 (0x2 << 17)
+/** Timer 2 Compare Output 2 */
#define ADC_CR2_EXTSEL_TIM2_CC2 (0x3 << 17)
+/** Timer 3 Trigger Output */
#define ADC_CR2_EXTSEL_TIM3_TRGO (0x4 << 17)
+/** Timer 4 Compare Output 4 */
#define ADC_CR2_EXTSEL_TIM4_CC4 (0x5 << 17)
+/** External Interrupt 11 */
#define ADC_CR2_EXTSEL_EXTI11 (0x6 << 17)
+/** Software Trigger */
#define ADC_CR2_EXTSEL_SWSTART (0x7 << 17)
+/**@}*/
/* The following are only valid for ADC3 */
+/****************************************************************************/
+/* ADC_CR2 EXTSEL[2:0] ADC Trigger Identifier for ADC3 */
+/** @defgroup adc_trigger_regular_3 ADC Trigger Identifier for ADC3
+@ingroup STM32F1xx_adc_defines
+
+@{*/
+/** Timer 2 Compare Output 1 */
#define ADC_CR2_EXTSEL_TIM3_CC1 (0x0 << 17)
+/** Timer 2 Compare Output 3 */
#define ADC_CR2_EXTSEL_TIM2_CC3 (0x1 << 17)
+/** Timer 1 Compare Output 3 */
+#define ADC_CR2_EXTSEL_TIM1_CC3 (0x2 << 17)
+/** Timer 8 Compare Output 1 */
#define ADC_CR2_EXTSEL_TIM8_CC1 (0x3 << 17)
+/** Timer 8 Trigger Output */
#define ADC_CR2_EXTSEL_TIM8_TRGO (0x4 << 17)
+/** Timer 5 Compare Output 1 */
#define ADC_CR2_EXTSEL_TIM5_CC1 (0x5 << 17)
+/** Timer 5 Compare Output 3 */
#define ADC_CR2_EXTSEL_TIM5_CC3 (0x6 << 17)
+/**@}*/
#define ADC_CR2_EXTSEL_MASK (0x7 << 17)
#define ADC_CR2_EXTSEL_SHIFT 17
@@ -291,21 +402,54 @@
/* JEXTSEL[2:0]: External event selection for injected group. */
/* The following are only valid for ADC1 and ADC2. */
+/****************************************************************************/
+/* ADC_CR2 JEXTSEL[2:0] ADC Injected Trigger Identifier for ADC1 and ADC2 */
+/** @defgroup adc_trigger_injected_12 ADC Injected Trigger Identifier for ADC1 and ADC2
+@ingroup STM32F1xx_adc_defines
+
+@{*/
+/** Timer 1 Trigger Output */
#define ADC_CR2_JEXTSEL_TIM1_TRGO (0x0 << 12)
+/** Timer 1 Compare Output 4 */
#define ADC_CR2_JEXTSEL_TIM1_CC4 (0x1 << 12)
+/** Timer 2 Trigger Output */
#define ADC_CR2_JEXTSEL_TIM2_TRGO (0x2 << 12)
+/** Timer 2 Compare Output 1 */
#define ADC_CR2_JEXTSEL_TIM2_CC1 (0x3 << 12)
+/** Timer 3 Compare Output 4 */
#define ADC_CR2_JEXTSEL_TIM3_CC4 (0x4 << 12)
+/** Timer 4 Trigger Output */
#define ADC_CR2_JEXTSEL_TIM4_TRGO (0x5 << 12)
+/** External Interrupt 15 */
#define ADC_CR2_JEXTSEL_EXTI15 (0x6 << 12)
+/** Injected Software Trigger */
#define ADC_CR2_JEXTSEL_JSWSTART (0x7 << 12) /* Software start. */
+/**@}*/
/* The following are the different meanings for ADC3 only. */
+/****************************************************************************/
+/* ADC_CR2 JEXTSEL[2:0] ADC Injected Trigger Identifier for ADC3 */
+/** @defgroup adc_trigger_injected_3 ADC Injected Trigger Identifier for ADC3
+@ingroup STM32F1xx_adc_defines
+
+@{*/
+/** Timer 1 Trigger Output */
+#define ADC_CR2_JEXTSEL_TIM1_TRGO (0x0 << 12)
+/** Timer 1 Compare Output 4 */
+#define ADC_CR2_JEXTSEL_TIM1_CC4 (0x1 << 12)
+/** Timer 4 Compare Output 3 */
#define ADC_CR2_JEXTSEL_TIM4_CC3 (0x2 << 12)
+/** Timer 8 Compare Output 2 */
#define ADC_CR2_JEXTSEL_TIM8_CC2 (0x3 << 12)
+/** Timer 8 Compare Output 4 */
#define ADC_CR2_JEXTSEL_TIM8_CC4 (0x4 << 12)
+/** Timer 5 Trigger Output */
#define ADC_CR2_JEXTSEL_TIM5_TRGO (0x5 << 12)
+/** Timer53 Compare Output 4 */
#define ADC_CR2_JEXTSEL_TIM5_CC4 (0x6 << 12)
+/** Injected Software Trigger */
+#define ADC_CR2_JEXTSEL_JSWSTART (0x7 << 12) /* Software start. */
+/**@}*/
#define ADC_CR2_JEXTSEL_MASK (0x7 << 12)
#define ADC_CR2_JEXTSEL_SHIFT 12
@@ -340,7 +484,6 @@
#define ADC_CR2_ADON (1 << 0)
/* --- ADC_SMPR1 values ---------------------------------------------------- */
-
#define ADC_SMPR1_SMP17_LSB 21
#define ADC_SMPR1_SMP16_LSB 18
#define ADC_SMPR1_SMP15_LSB 15
@@ -357,6 +500,12 @@
#define ADC_SMPR1_SMP12_MSK (0x7 << ADC_SMP12_LSB)
#define ADC_SMPR1_SMP11_MSK (0x7 << ADC_SMP11_LSB)
#define ADC_SMPR1_SMP10_MSK (0x7 << ADC_SMP10_LSB)
+/****************************************************************************/
+/* ADC_SMPR1 ADC Sample Time Selection for Channels */
+/** @defgroup adc_sample_r1 ADC Sample Time Selection for ADC1
+@ingroup STM32F1xx_adc_defines
+
+@{*/
#define ADC_SMPR1_SMP_1DOT5CYC 0x0
#define ADC_SMPR1_SMP_7DOT5CYC 0x1
#define ADC_SMPR1_SMP_13DOT5CYC 0x2
@@ -365,6 +514,7 @@
#define ADC_SMPR1_SMP_55DOT5CYC 0x5
#define ADC_SMPR1_SMP_71DOT5CYC 0x6
#define ADC_SMPR1_SMP_239DOT5CYC 0x7
+/**@}*/
/* --- ADC_SMPR2 values ---------------------------------------------------- */
@@ -388,6 +538,12 @@
#define ADC_SMPR2_SMP2_MSK (0x7 << ADC_SMP2_LSB)
#define ADC_SMPR2_SMP1_MSK (0x7 << ADC_SMP1_LSB)
#define ADC_SMPR2_SMP0_MSK (0x7 << ADC_SMP0_LSB)
+/****************************************************************************/
+/* ADC_SMPR2 ADC Sample Time Selection for Channels */
+/** @defgroup adc_sample_r2 ADC Sample Time Selection for ADC2
+@ingroup STM32F1xx_adc_defines
+
+@{*/
#define ADC_SMPR2_SMP_1DOT5CYC 0x0
#define ADC_SMPR2_SMP_7DOT5CYC 0x1
#define ADC_SMPR2_SMP_13DOT5CYC 0x2
@@ -396,9 +552,15 @@
#define ADC_SMPR2_SMP_55DOT5CYC 0x5
#define ADC_SMPR2_SMP_71DOT5CYC 0x6
#define ADC_SMPR2_SMP_239DOT5CYC 0x7
+/**@}*/
/* --- ADC_SMPRx generic values -------------------------------------------- */
+/****************************************************************************/
+/* ADC_SMPRG ADC Sample Time Selection for Channels */
+/** @defgroup adc_sample_rg ADC Sample Time Selection Generic
+@ingroup STM32F1xx_adc_defines
+@{*/
#define ADC_SMPR_SMP_1DOT5CYC 0x0
#define ADC_SMPR_SMP_7DOT5CYC 0x1
#define ADC_SMPR_SMP_13DOT5CYC 0x2
@@ -407,6 +569,7 @@
#define ADC_SMPR_SMP_55DOT5CYC 0x5
#define ADC_SMPR_SMP_71DOT5CYC 0x6
#define ADC_SMPR_SMP_239DOT5CYC 0x7
+/**@}*/
/* --- ADC_JOFRx, ADC_HTR, ADC_LTR values ---------------------------------- */
@@ -429,6 +592,13 @@
#define ADC_SQR1_SQ15_MSK (0x1f << ADC_SQ15_LSB)
#define ADC_SQR1_SQ14_MSK (0x1f << ADC_SQ14_LSB)
#define ADC_SQR1_SQ13_MSK (0x1f << ADC_SQ13_LSB)
+/* TODO Fix error
+#define ADC_SQR1_L_MSK (0xf << ADC_SQR1_L_LSB)
+#define ADC_SQR1_SQ16_MSK (0x1f << ADC_SQR1_SQ16_LSB)
+#define ADC_SQR1_SQ15_MSK (0x1f << ADC_SQR1_SQ15_LSB)
+#define ADC_SQR1_SQ14_MSK (0x1f << ADC_SQR1_SQ14_LSB)
+#define ADC_SQR1_SQ13_MSK (0x1f << ADC_SQR1_SQ13_LSB)
+*/
/* --- ADC_SQR2 values ----------------------------------------------------- */
@@ -444,6 +614,14 @@
#define ADC_SQR2_SQ9_MSK (0x1f << ADC_SQ9_LSB)
#define ADC_SQR2_SQ8_MSK (0x1f << ADC_SQ8_LSB)
#define ADC_SQR2_SQ7_MSK (0x1f << ADC_SQ7_LSB)
+/* TODO Fix error
+#define ADC_SQR2_SQ12_MSK (0x1f << ADC_SQR2_SQ12_LSB)
+#define ADC_SQR2_SQ11_MSK (0x1f << ADC_SQR2_SQ11_LSB)
+#define ADC_SQR2_SQ10_MSK (0x1f << ADC_SQR2_SQ10_LSB)
+#define ADC_SQR2_SQ9_MSK (0x1f << ADC_SQR2_SQ9_LSB)
+#define ADC_SQR2_SQ8_MSK (0x1f << ADC_SQR2_SQ8_LSB)
+#define ADC_SQR2_SQ7_MSK (0x1f << ADC_SQR2_SQ7_LSB)
+*/
/* --- ADC_SQR3 values ----------------------------------------------------- */
@@ -459,7 +637,14 @@
#define ADC_SQR3_SQ3_MSK (0x1f << ADC_SQ3_LSB)
#define ADC_SQR3_SQ2_MSK (0x1f << ADC_SQ2_LSB)
#define ADC_SQR3_SQ1_MSK (0x1f << ADC_SQ1_LSB)
-
+/* TODO Fix error
+#define ADC_SQR3_SQ6_MSK (0x1f << ADC_SQR3_SQ6_LSB)
+#define ADC_SQR3_SQ5_MSK (0x1f << ADC_SQR3_SQ5_LSB)
+#define ADC_SQR3_SQ4_MSK (0x1f << ADC_SQR3_SQ4_LSB)
+#define ADC_SQR3_SQ3_MSK (0x1f << ADC_SQR3_SQ3_LSB)
+#define ADC_SQR3_SQ2_MSK (0x1f << ADC_SQR3_SQ2_LSB)
+#define ADC_SQR3_SQ1_MSK (0x1f << ADC_SQR3_SQ1_LSB)
+*/
/* --- ADC_JSQR values ----------------------------------------------------- */
#define ADC_JSQR_JL_LSB 20
@@ -472,6 +657,13 @@
#define ADC_JSQR_JSQ3_MSK (0x1f << ADC_JSQ3_LSB)
#define ADC_JSQR_JSQ2_MSK (0x1f << ADC_JSQ2_LSB)
#define ADC_JSQR_JSQ1_MSK (0x1f << ADC_JSQ1_LSB)
+/* TODO Fix error
+#define ADC_JSQR_JL_MSK (0x2 << ADC_JSQR_JL_LSB)
+#define ADC_JSQR_JSQ4_MSK (0x1f << ADC_JSQR_JSQ4_LSB)
+#define ADC_JSQR_JSQ3_MSK (0x1f << ADC_JSQR_JSQ3_LSB)
+#define ADC_JSQR_JSQ2_MSK (0x1f << ADC_JSQR_JSQ2_LSB)
+#define ADC_JSQR_JSQ1_MSK (0x1f << ADC_JSQR_JSQ1_LSB)
+*/
/* --- ADC_JDRx, ADC_DR values --------------------------------------------- */
@@ -481,10 +673,11 @@
#define ADC_JDATA_MSK (0xffff << ADC_JDATA_LSB)
#define ADC_DATA_MSK (0xffff << ADC_DA)
#define ADC_ADC2DATA_MSK (0xffff << ADC_ADC2DATA_LSB)
- /* ADC1 only (dual mode) */
+ /* ADC1 only (dual mode) */
/* --- Function prototypes ------------------------------------------------- */
+BEGIN_DECLS
/* TODO */
void adc_enable_analog_watchdog_regular(u32 adc);
@@ -532,4 +725,8 @@ void adc_set_watchdog_low_threshold(u32 adc, u16 threshold);
void adc_set_regular_sequence(u32 adc, u8 length, u8 channel[]);
void adc_set_injected_sequence(u32 adc, u8 length, u8 channel[]);
+END_DECLS
+
#endif
+/**@}*/
+
diff --git a/include/libopencm3/stm32/f1/desig.h b/include/libopencm3/stm32/f1/desig.h
new file mode 100644
index 0000000..74cfb35
--- /dev/null
+++ b/include/libopencm3/stm32/f1/desig.h
@@ -0,0 +1,56 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_DESIG_H
+#define LIBOPENCM3_DESIG_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/* --- Device Electronic Signature -------------------------------- */
+
+/* Flash size register */
+#define DESIG_FLASH_SIZE MMIO16(DESIG_FLASH_SIZE_BASE + 0x00)
+
+/* Unique ID register (96 bits) */
+/* Note: ST says these may be accessed in any width if you choose */
+#define DESIG_UID_15_0 MMIO16(DESIG_UNIQUE_ID_BASE + 0x00)
+/* Listed as "This field value is also reserved for a future feature" WTH?! */
+#define DESIG_UID_31_16 MMIO16(DESIG_UNIQUE_ID_BASE + 0x02)
+#define DESIG_UID_63_32 MMIO32(DESIG_UNIQUE_ID_BASE + 0x04)
+#define DESIG_UID_95_64 MMIO32(DESIG_UNIQUE_ID_BASE + 0x08)
+
+BEGIN_DECLS
+
+/**
+ * Read the onboard flash size
+ * @return flash size in KB
+ */
+u16 desig_get_flash_size(void);
+
+/**
+ * Read the full 96 bit unique identifier
+ * Note: ST specifies that bits 31..16 are _also_ reserved for future use
+ * @param result pointer to at least 3xu32s (96 bits)
+ */
+void desig_get_unique_id(u32 result[]);
+
+END_DECLS
+
+#endif
diff --git a/include/libopencm3/stm32/f1/dma.h b/include/libopencm3/stm32/f1/dma.h
index 5aa0183..b08803f 100644
--- a/include/libopencm3/stm32/f1/dma.h
+++ b/include/libopencm3/stm32/f1/dma.h
@@ -1,3 +1,17 @@
+/** @defgroup STM32F1xx_dma_defines DMA Defines
+
+@ingroup STM32F1xx_defines
+
+@brief Defined Constants and Types for the STM32F1xx DMA Controller
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
+
+@date 18 August 2012
+
+LGPL License Terms @ref lgpl_license
+ */
/*
* This file is part of the libopencm3 project.
*
@@ -18,6 +32,8 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
+/**@{*/
+
#ifndef LIBOPENCM3_DMA_H
#define LIBOPENCM3_DMA_H
@@ -241,24 +257,39 @@
#define DMA_CCR_MEM2MEM (1 << 14)
/* PL[13:12]: Channel priority level */
+/** @defgroup dma_ch_pri DMA Channel Priority Levels
+@ingroup STM32F1xx_dma_defines
+
+@{*/
#define DMA_CCR_PL_LOW (0x0 << 12)
#define DMA_CCR_PL_MEDIUM (0x1 << 12)
#define DMA_CCR_PL_HIGH (0x2 << 12)
#define DMA_CCR_PL_VERY_HIGH (0x3 << 12)
+/**@}*/
#define DMA_CCR_PL_MASK (0x3 << 12)
#define DMA_CCR_PL_SHIFT 12
/* MSIZE[11:10]: Memory size */
+/** @defgroup dma_ch_memwidth DMA Channel Memory Word Width
+@ingroup STM32F1xx_dma_defines
+
+@{*/
#define DMA_CCR_MSIZE_8BIT (0x0 << 10)
#define DMA_CCR_MSIZE_16BIT (0x1 << 10)
#define DMA_CCR_MSIZE_32BIT (0x2 << 10)
+/**@}*/
#define DMA_CCR_MSIZE_MASK (0x3 << 10)
#define DMA_CCR_MSIZE_SHIFT 10
/* PSIZE[9:8]: Peripheral size */
+/** @defgroup dma_ch_perwidth DMA Channel Peripheral Word Width
+@ingroup STM32F1xx_dma_defines
+
+@{*/
#define DMA_CCR_PSIZE_8BIT (0x0 << 8)
#define DMA_CCR_PSIZE_16BIT (0x1 << 8)
#define DMA_CCR_PSIZE_32BIT (0x2 << 8)
+/**@}*/
#define DMA_CCR_PSIZE_MASK (0x3 << 8)
#define DMA_CCR_PSIZE_SHIFT 8
@@ -300,6 +331,10 @@
/* --- Generic values ------------------------------------------------------ */
+/** @defgroup dma_ch DMA Channel Number
+@ingroup STM32F1xx_dma_defines
+
+@{*/
#define DMA_CHANNEL1 1
#define DMA_CHANNEL2 2
#define DMA_CHANNEL3 3
@@ -307,9 +342,12 @@
#define DMA_CHANNEL5 5
#define DMA_CHANNEL6 6
#define DMA_CHANNEL7 7
+/**@}*/
/* --- function prototypes ------------------------------------------------- */
+BEGIN_DECLS
+
void dma_channel_reset(u32 dma, u8 channel);
void dma_enable_mem2mem_mode(u32 dma, u8 channel);
void dma_set_priority(u32 dma, u8 channel, u32 prio);
@@ -332,4 +370,8 @@ void dma_set_peripheral_address(u32 dma, u8 channel, u32 address);
void dma_set_memory_address(u32 dma, u8 channel, u32 address);
void dma_set_number_of_data(u32 dma, u8 channel, u16 number);
+END_DECLS
+
#endif
+/**@}*/
+
diff --git a/include/libopencm3/stm32/f1/doc-stm32f1.h b/include/libopencm3/stm32/f1/doc-stm32f1.h
new file mode 100644
index 0000000..04293a6
--- /dev/null
+++ b/include/libopencm3/stm32/f1/doc-stm32f1.h
@@ -0,0 +1,15 @@
+/** @defgroup STM32F1xx_defines STM32F1xx Defines
+
+@brief Defined Constants and Types for the STM32F1xx series
+
+@ingroup STM32F1xx
+
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies ksarkies@internode.on.net
+
+@version 1.0.0
+
+@date 18 August 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
diff --git a/include/libopencm3/stm32/f1/flash.h b/include/libopencm3/stm32/f1/flash.h
index 2c026d6..919b4d4 100644
--- a/include/libopencm3/stm32/f1/flash.h
+++ b/include/libopencm3/stm32/f1/flash.h
@@ -89,6 +89,8 @@
/* --- Function prototypes ------------------------------------------------- */
+BEGIN_DECLS
+
void flash_prefetch_buffer_enable(void);
void flash_prefetch_buffer_disable(void);
void flash_halfcycle_enable(void);
@@ -110,4 +112,6 @@ void flash_wait_for_last_operation(void);
void flash_erase_option_bytes(void);
void flash_program_option_bytes(u32 address, u16 data);
+END_DECLS
+
#endif
diff --git a/include/libopencm3/stm32/f1/gpio.h b/include/libopencm3/stm32/f1/gpio.h
index e4e11be..a1e74cc 100644
--- a/include/libopencm3/stm32/f1/gpio.h
+++ b/include/libopencm3/stm32/f1/gpio.h
@@ -1,3 +1,18 @@
+/** @defgroup STM32F1xx_gpio_defines GPIO Defines
+
+@brief <b>Defined Constants and Types for the STM32F1xx General Purpose I/O</b>
+
+@ingroup STM32F1xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
+@author @htmlonly &copy; @endhtmlonly 2012 Piotr Esden-Tempski <piotr@esden.net>
+
+@date 1 July 2012
+
+LGPL License Terms @ref lgpl_license
+ */
/*
* This file is part of the libopencm3 project.
*
@@ -17,6 +32,7 @@
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
+/**@{*/
#ifndef LIBOPENCM3_GPIO_H
#define LIBOPENCM3_GPIO_H
@@ -27,6 +43,10 @@
/* --- Convenience macros -------------------------------------------------- */
/* GPIO port base addresses (for convenience) */
+/** @defgroup gpio_port_id GPIO Port IDs
+@ingroup STM32F1xx_gpio_defines
+
+@{*/
#define GPIOA GPIO_PORT_A_BASE
#define GPIOB GPIO_PORT_B_BASE
#define GPIOC GPIO_PORT_C_BASE
@@ -34,8 +54,13 @@
#define GPIOE GPIO_PORT_E_BASE
#define GPIOF GPIO_PORT_F_BASE
#define GPIOG GPIO_PORT_G_BASE
+/**@}*/
/* GPIO number definitions (for convenience) */
+/** @defgroup gpio_pin_id GPIO Pin Identifiers
+@ingroup STM32F1xx_gpio_defines
+
+@{*/
#define GPIO0 (1 << 0)
#define GPIO1 (1 << 1)
#define GPIO2 (1 << 2)
@@ -53,6 +78,7 @@
#define GPIO14 (1 << 14)
#define GPIO15 (1 << 15)
#define GPIO_ALL 0xffff
+/**@}*/
/* --- Alternate function GPIOs -------------------------------------------- */
@@ -593,22 +619,50 @@
/* --- GPIO_CRL/GPIO_CRH values -------------------------------------------- */
+/** @defgroup gpio_cnf GPIO Pin Configuration
+@ingroup STM32F1xx_gpio_defines
+If mode specifies input, configuration can be
+@li Analog input
+@li Floating input
+@li Pull up/down input
+
+If mode specifies output, configuration can be
+@li Digital push-pull
+@li Digital open drain
+@li Alternate function push-pull or analog output
+@li Alternate function open drain or analog output
+@{*/
/* CNF[1:0] values when MODE[1:0] is 00 (input mode) */
+/** Analog Input */
#define GPIO_CNF_INPUT_ANALOG 0x00
+/** Digital Input Floating */
#define GPIO_CNF_INPUT_FLOAT 0x01 /* Default */
+/** Digital Input Pull Up and Down */
#define GPIO_CNF_INPUT_PULL_UPDOWN 0x02
-
-/* Output mode (MODE[1:0]) values */
-#define GPIO_MODE_INPUT 0x00 /* Default */
-#define GPIO_MODE_OUTPUT_10_MHZ 0x01
-#define GPIO_MODE_OUTPUT_2_MHZ 0x02
-#define GPIO_MODE_OUTPUT_50_MHZ 0x03
-
/* CNF[1:0] values when MODE[1:0] is != 00 (one of the output modes) */
+/** Digital Output Pushpull */
#define GPIO_CNF_OUTPUT_PUSHPULL 0x00
+/** Digital Output Open Drain */
#define GPIO_CNF_OUTPUT_OPENDRAIN 0x01
+/** Alternate Function Output Pushpull */
#define GPIO_CNF_OUTPUT_ALTFN_PUSHPULL 0x02
+/** Alternate Function Output Open Drain */
#define GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN 0x03
+/**@}*/
+
+/* Pin mode (MODE[1:0]) values */
+/** @defgroup gpio_mode GPIO Pin Mode
+@ingroup STM32F1xx_gpio_defines
+@li Input (default after reset)
+@li Output mode at 10 MHz maximum speed
+@li Output mode at 2 MHz maximum speed
+@li Output mode at 50 MHz maximum speed
+@{*/
+#define GPIO_MODE_INPUT 0x00 /* Default */
+#define GPIO_MODE_OUTPUT_10_MHZ 0x01
+#define GPIO_MODE_OUTPUT_2_MHZ 0x02
+#define GPIO_MODE_OUTPUT_50_MHZ 0x03
+/**@}*/
/* --- GPIO_IDR values ----------------------------------------------------- */
@@ -652,19 +706,31 @@
/* External interrupt configuration register 4 (AFIO_EXTICR4) */
#define AFIO_EXTICR4 MMIO32(AFIO_BASE + 0x14)
+/* AF remap and debug I/O configuration register (AFIO_MAPR) */
+#define AFIO_MAPR2 MMIO32(AFIO_BASE + 0x1C)
+
/* --- AFIO_EVCR values ---------------------------------------------------- */
/* EVOE: Event output enable */
#define AFIO_EVCR_EVOE (1 << 7)
/* PORT[2:0]: Port selection */
+/** @defgroup afio_evcr_port EVENTOUT Port selection
+@ingroup STM32F1xx_gpio_defines
+
+@{*/
#define AFIO_EVCR_PORT_PA (0x0 << 4)
#define AFIO_EVCR_PORT_PB (0x1 << 4)
#define AFIO_EVCR_PORT_PC (0x2 << 4)
#define AFIO_EVCR_PORT_PD (0x3 << 4)
#define AFIO_EVCR_PORT_PE (0x4 << 4)
+/**@}*/
/* PIN[3:0]: Pin selection */
+/** @defgroup afio_evcr_pin EVENTOUT Pin selection
+@ingroup STM32F1xx_gpio_defines
+
+@{*/
#define AFIO_EVCR_PIN_Px0 (0x0 << 0)
#define AFIO_EVCR_PIN_Px1 (0x1 << 0)
#define AFIO_EVCR_PIN_Px2 (0x2 << 0)
@@ -681,120 +747,211 @@
#define AFIO_EVCR_PIN_Px13 (0xD << 0)
#define AFIO_EVCR_PIN_Px14 (0xE << 0)
#define AFIO_EVCR_PIN_Px15 (0xF << 0)
+/**@}*/
/* --- AFIO_MAPR values ---------------------------------------------------- */
/* 31 reserved */
-/* PTP_PPS_REMAP: Ethernet PTP PPS remapping
+/** @defgroup afio_remap_cld Alternate Function Remap Controls for Connectivity
+Line Devices only
+@ingroup STM32F1xx_gpio_defines
+
+@{*/
+/* PTP_PPS_REMAP: *//** Ethernet PTP PPS remapping
* (only connectivity line devices) */
#define AFIO_MAPR_PTP_PPS_REMAP (1 << 30)
-/* TIM2ITR1_IREMAP: TIM2 internal trigger 1 remapping
+/* TIM2ITR1_IREMAP: *//** TIM2 internal trigger 1 remapping
* (only connectivity line devices) */
#define AFIO_MAPR_TIM2ITR1_IREMAP (1 << 29)
-/* SPI3_REMAP: SPI3/I2S3 remapping
+/* SPI3_REMAP: *//** SPI3/I2S3 remapping
* (only connectivity line devices) */
#define AFIO_MAPR_SPI3_REMAP (1 << 28)
+/* MII_REMAP: */ /** MII or RMII selection
+ * (only connectivity line devices) */
+#define AFIO_MAPR_MII_RMII_SEL (1 << 23)
+
+/* CAN2_REMAP: */ /** CAN2 I/O remapping
+ * (only connectivity line devices) */
+#define AFIO_MAPR_CAN2_REMAP (1 << 22)
+
+/* ETH_REMAP: */ /** Ethernet MAC I/O remapping
+ * (only connectivity line devices) */
+#define AFIO_MAPR_ETH_REMAP (1 << 21)
+
+/**@}*/
+
/* 27 reserved */
/* SWJ_CFG[2:0]: Serial wire JTAG configuration */
+/** @defgroup afio_swj_disable Serial Wire JTAG disables
+@ingroup STM32F1xx_gpio_defines
+
+@{*/
#define AFIO_MAPR_SWJ_MASK (0x7 << 24)
+/** Full Serial Wire JTAG capability */
#define AFIO_MAPR_SWJ_CFG_FULL_SWJ (0x0 << 24)
+/** Full Serial Wire JTAG capability without JNTRST */
#define AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_JNTRST (0x1 << 24)
+/** JTAG-DP disabled with SW-DP enabled */
#define AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_ON (0x2 << 24)
+/** JTAG-DP disabled and SW-DP disabled */
#define AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_OFF (0x4 << 24)
+/**@}*/
-/* MII_REMAP: MII or RMII selection
- * (only connectivity line devices) */
-#define AFIO_MAPR_MII_RMII_SEL (1 << 23)
+/** @defgroup afio_remap Alternate Function Remap Controls
+@ingroup STM32F1xx_gpio_defines
-/* CAN2_REMAP: CAN2 I/O remapping
- * (only connectivity line devices) */
-#define AFIO_MAPR_CAN2_REMAP (1 << 22)
-
-/* ETH_REMAP: Ethernet MAC I/O remapping
- * (only connectivity line devices) */
-#define AFIO_MAPR_ETH_REMAP (1 << 21)
-
-/* ADC2_ETRGREG_REMAP: ADC2 external trigger regulator conversion remapping
+@{*/
+/* ADC2_ETRGREG_REMAP: */ /** ADC2 external trigger regulator conversion remapping
* (only low-, medium-, high- and XL-densitiy devices) */
#define AFIO_MAPR_ADC2_ETRGREG_REMAP (1 << 20)
-/* ADC2_ETRGINJ_REMAP: ADC2 external trigger injected conversion remapping
+/* ADC2_ETRGINJ_REMAP: */ /** ADC2 external trigger injected conversion remapping
* (only low-, medium-, high- and XL-densitiy devices) */
#define AFIO_MAPR_ADC2_ETRGINJ_REMAP (1 << 19)
-/* ADC1_ETRGREG_REMAP: ADC1 external trigger regulator conversion remapping
+/* ADC1_ETRGREG_REMAP: */ /** ADC1 external trigger regulator conversion remapping
* (only low-, medium-, high- and XL-densitiy devices) */
#define AFIO_MAPR_ADC1_ETRGREG_REMAP (1 << 18)
-/* ADC1_ETRGINJ_REMAP: ADC1 external trigger injected conversion remapping
+/* ADC1_ETRGINJ_REMAP: */ /** ADC1 external trigger injected conversion remapping
* (only low-, medium-, high- and XL-densitiy devices) */
#define AFIO_MAPR_ADC1_ETRGINJ_REMAP (1 << 17)
-/* TIM5CH4_IREMAP: TIM5 channel4 internal remap */
+/* TIM5CH4_IREMAP: */ /** TIM5 channel4 internal remap */
#define AFIO_MAPR_TIM5CH4_IREMAP (1 << 16)
-/* PD01_REMAP: Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
+/* PD01_REMAP: */ /** Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
#define AFIO_MAPR_PD01_REMAP (1 << 15)
+/* TIM4_REMAP: */ /** TIM4 remapping */
+#define AFIO_MAPR_TIM4_REMAP (1 << 12)
+
+/* USART2_REMAP[1:0]: */ /** USART2 remapping */
+#define AFIO_MAPR_USART2_REMAP (1 << 3)
+
+/* USART1_REMAP[1:0]: */ /** USART1 remapping */
+#define AFIO_MAPR_USART1_REMAP (1 << 2)
+
+/* I2C1_REMAP[1:0]: */ /** I2C1 remapping */
+#define AFIO_MAPR_I2C1_REMAP (1 << 1)
+
+/* SPI1_REMAP[1:0]: */ /** SPI1 remapping */
+#define AFIO_MAPR_SPI1_REMAP (1 << 0)
+/**@}*/
+
/* CAN_REMAP[1:0]: CAN1 alternate function remapping */
+/** @defgroup afio_remap_can1 Alternate Function Remap Controls for CAN 1
+@ingroup STM32F1xx_gpio_defines
+
+@{*/
#define AFIO_MAPR_CAN1_REMAP_PORTA (0x0 << 13)
#define AFIO_MAPR_CAN1_REMAP_PORTB (0x2 << 13) /* Not on 36pin pkg */
#define AFIO_MAPR_CAN1_REMAP_PORTD (0x3 << 13)
-
-/* TIM4_REMAP: TIM4 remapping */
-#define AFIO_MAPR_TIM4_REMAP (1 << 12)
+/**@}*/
/* TIM3_REMAP[1:0]: TIM3 remapping */
+/** @defgroup afio_remap_tim3 Alternate Function Remap Controls for Timer 3
+@ingroup STM32F1xx_gpio_defines
+
+@{*/
#define AFIO_MAPR_TIM3_REMAP_NO_REMAP (0x0 << 10)
#define AFIO_MAPR_TIM3_REMAP_PARTIAL_REMAP (0x2 << 10)
#define AFIO_MAPR_TIM3_REMAP_FULL_REMAP (0x3 << 10)
+/**@}*/
/* TIM2_REMAP[1:0]: TIM2 remapping */
+/** @defgroup afio_remap_tim2 Alternate Function Remap Controls for Timer 2
+@ingroup STM32F1xx_gpio_defines
+
+@{*/
#define AFIO_MAPR_TIM2_REMAP_NO_REMAP (0x0 << 8)
#define AFIO_MAPR_TIM2_REMAP_PARTIAL_REMAP1 (0x1 << 8)
#define AFIO_MAPR_TIM2_REMAP_PARTIAL_REMAP2 (0x2 << 8)
#define AFIO_MAPR_TIM2_REMAP_FULL_REMAP (0x3 << 8)
+/**@}*/
/* TIM1_REMAP[1:0]: TIM1 remapping */
+/** @defgroup afio_remap_tim1 Alternate Function Remap Controls for Timer 1
+@ingroup STM32F1xx_gpio_defines
+
+@{*/
#define AFIO_MAPR_TIM1_REMAP_NO_REMAP (0x0 << 6)
#define AFIO_MAPR_TIM1_REMAP_PARTIAL_REMAP (0x1 << 6)
#define AFIO_MAPR_TIM1_REMAP_FULL_REMAP (0x3 << 6)
+/**@}*/
/* USART3_REMAP[1:0]: USART3 remapping */
+/** @defgroup afio_remap_usart3 Alternate Function Remap Controls for USART 3
+@ingroup STM32F1xx_gpio_defines
+
+@{*/
#define AFIO_MAPR_USART3_REMAP_NO_REMAP (0x0 << 4)
#define AFIO_MAPR_USART3_REMAP_PARTIAL_REMAP (0x1 << 4)
#define AFIO_MAPR_USART3_REMAP_FULL_REMAP (0x3 << 4)
+/**@}*/
-/* USART2_REMAP[1:0]: USART2 remapping */
-#define AFIO_MAPR_USART2_REMAP (1 << 3)
+/** @defgroup afio_remap2 Alternate Function Remap Controls Secondary Set
+@ingroup STM32F1xx_gpio_defines
-/* USART1_REMAP[1:0]: USART1 remapping */
-#define AFIO_MAPR_USART1_REMAP (1 << 2)
+@{*/
+/* FSMC_NADV_DISCONNECT: */ /** The NADV is disconnected from its allocated pin */
+#define AFIO_MAPR2_FSMC_NADV_DISCONNECT (1 << 10)
-/* I2C1_REMAP[1:0]: I2C1 remapping */
-#define AFIO_MAPR_I2C1_REMAP (1 << 1)
+/* TIM14_REMAP: */ /** TIM14 remapping */
+#define AFIO_MAPR2_TIM14_REMAP (1 << 9)
-/* SPI1_REMAP[1:0]: SPI1 remapping */
-#define AFIO_MAPR_SPI1_REMAP (1 << 0)
+/* TIM13_REMAP: */ /** TIM13 remapping */
+#define AFIO_MAPR2_TIM13_REMAP (1 << 8)
+
+/* TIM11_REMAP: */ /** TIM11 remapping */
+#define AFIO_MAPR2_TIM11_REMAP (1 << 7)
+
+/* TIM10_REMAP: */ /** TIM10 remapping */
+#define AFIO_MAPR2_TIM10_REMAP (1 << 6)
+
+/* TIM9_REMAP: */ /** TIM9 remapping */
+#define AFIO_MAPR2_TIM9_REMAP (1 << 5)
+
+/**@}*/
/* --- AFIO_EXTICR1 values ------------------------------------------------- */
/* --- AFIO_EXTICR2 values ------------------------------------------------- */
/* --- AFIO_EXTICR3 values ------------------------------------------------- */
/* --- AFIO_EXTICR4 values ------------------------------------------------- */
-/* EXTI0 - EXTI15 interrupt source selection registers */
-
-/* Note: For using them we should define a function that calculates the right
- * registers, using definitions is probably not a good idea.
- */
+/** @defgroup afio_exti Alternate Function EXTI pin number
+@ingroup STM32F1xx_gpio_defines
+
+@{*/
+
+#define AFIO_EXTI0 0
+#define AFIO_EXTI1 1
+#define AFIO_EXTI2 2
+#define AFIO_EXTI3 3
+#define AFIO_EXTI4 4
+#define AFIO_EXTI5 5
+#define AFIO_EXTI6 6
+#define AFIO_EXTI7 7
+#define AFIO_EXTI8 8
+#define AFIO_EXTI9 9
+#define AFIO_EXTI10 10
+#define AFIO_EXTI11 11
+#define AFIO_EXTI12 12
+#define AFIO_EXTI13 13
+#define AFIO_EXTI14 14
+#define AFIO_EXTI15 15
+
+/**@}*/
/* --- Function prototypes ------------------------------------------------- */
+BEGIN_DECLS
+
void gpio_set_mode(u32 gpioport, u8 mode, u8 cnf, u16 gpios);
void gpio_set(u32 gpioport, u16 gpios);
void gpio_clear(u32 gpioport, u16 gpios);
@@ -803,5 +960,12 @@ void gpio_toggle(u32 gpioport, u16 gpios);
u16 gpio_port_read(u32 gpioport);
void gpio_port_write(u32 gpioport, u16 data);
void gpio_port_config_lock(u32 gpioport, u16 gpios);
+void gpio_set_eventout(u8 evoutport, u8 evoutpin);
+void gpio_primary_remap(u8 swjenable, u32 maps);
+void gpio_secondary_remap(u32 maps);
+
+END_DECLS
#endif
+/**@}*/
+
diff --git a/include/libopencm3/stm32/f1/memorymap.h b/include/libopencm3/stm32/f1/memorymap.h
index f8528d4..5cc432e 100644
--- a/include/libopencm3/stm32/f1/memorymap.h
+++ b/include/libopencm3/stm32/f1/memorymap.h
@@ -26,6 +26,7 @@
/* Memory map for all busses */
#define PERIPH_BASE ((u32)0x40000000)
+#define INFO_BASE ((u32)0x1ffff000)
#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)
#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)
#define PERIPH_BASE_AHB (PERIPH_BASE + 0x18000)
@@ -110,4 +111,8 @@
/* FSMC */
#define FSMC_BASE (PERIPH_BASE + 0x60000000)
+/* Device Electronic Signature */
+#define DESIG_FLASH_SIZE_BASE (INFO_BASE + 0x7e0)
+#define DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x7e8)
+
#endif
diff --git a/include/libopencm3/stm32/f1/nvic_f1.h b/include/libopencm3/stm32/f1/nvic_f1.h
index 884f728..5223bb6 100644
--- a/include/libopencm3/stm32/f1/nvic_f1.h
+++ b/include/libopencm3/stm32/f1/nvic_f1.h
@@ -1,3 +1,13 @@
+/** @brief <b>Defined Constants and Types for the STM32F1xx Nested Vectored Interrupt Controller</b>
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
+
+@date 18 August 2012
+
+LGPL License Terms @ref lgpl_license
+ */
/*
* This file is part of the libopencm3 project.
*
@@ -27,6 +37,10 @@
*/
/* User Interrupts */
+/** @defgroup nvic_stm32f1_userint STM32F1xx User Interrupts
+@ingroup STM32F_nvic_defines
+
+@{*/
#define NVIC_WWDG_IRQ 0
#define NVIC_PVD_IRQ 1
#define NVIC_TAMPER_IRQ 2
@@ -95,5 +109,6 @@
#define NVIC_CAN2_RX1_IRQ 65
#define NVIC_CAN2_SCE_IRQ 66
#define NVIC_OTG_FS_IRQ 67
+/**@}*/
#endif
diff --git a/include/libopencm3/stm32/f1/rcc.h b/include/libopencm3/stm32/f1/rcc.h
index 9cbe1e7..855e43b 100644
--- a/include/libopencm3/stm32/f1/rcc.h
+++ b/include/libopencm3/stm32/f1/rcc.h
@@ -1,3 +1,18 @@
+/** @defgroup STM32F1xx_rcc_defines RCC Defines
+
+@brief <b>libopencm3 STM32F1xx Reset and Clock Control</b>
+
+@ingroup STM32F1xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2009 Federico Ruiz-Ugalde \<memeruiz at gmail dot com\>
+@author @htmlonly &copy; @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
+
+@date 18 August 2012
+
+LGPL License Terms @ref lgpl_license
+ */
/*
* This file is part of the libopencm3 project.
*
@@ -17,6 +32,7 @@
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
+/**@{*/
#ifndef LIBOPENCM3_RCC_H
#define LIBOPENCM3_RCC_H
@@ -62,6 +78,10 @@
/* --- RCC_CFGR values ----------------------------------------------------- */
/* MCO: Microcontroller clock output */
+/** @defgroup rcc_cfgr_co RCC_CFGR Microcontroller Clock Output Source
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
#define RCC_CFGR_MCO_NOCLK 0x0
#define RCC_CFGR_MCO_SYSCLK 0x4
#define RCC_CFGR_MCO_HSICLK 0x5
@@ -71,16 +91,26 @@
#define RCC_CFGR_MCO_PLL3CLK_DIV2 0x9 /* (**) */
#define RCC_CFGR_MCO_XT1 0xa /* (**) */
#define RCC_CFGR_MCO_PLL3 0xb /* (**) */
+/**@}*/
/* USBPRE: USB prescaler (RCC_CFGR[22]) */
+/** @defgroup rcc_cfgr_usbpre RCC_CFGR USB prescale Factors
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
#define RCC_CFGR_USBPRE_PLL_CLK_DIV1_5 0x0
#define RCC_CFGR_USBPRE_PLL_CLK_NODIV 0x1
+/**@}*/
/* OTGFSPRE: USB OTG FS prescaler (RCC_CFGR[22]; only in conn. line STM32s) */
#define RCC_CFGR_USBPRE_PLL_VCO_CLK_DIV3 0x0
#define RCC_CFGR_USBPRE_PLL_VCO_CLK_DIV2 0x1
/* PLLMUL: PLL multiplication factor */
+/** @defgroup rcc_cfgr_pmf RCC_CFGR PLL Multiplication Factor
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL2 0x0 /* (XX) */
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL3 0x1 /* (XX) */
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL4 0x2
@@ -98,38 +128,69 @@
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL6_5 0xd /* 0xd: PLL x 6.5 for conn. line */
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL16 0xe /* (XX) */
// #define PLLMUL_PLL_CLK_MUL16 0xf /* (XX) */ /* Errata? 17? */
+/**@}*/
/* TODO: conn. line differs. */
/* PLLXTPRE: HSE divider for PLL entry */
+/** @defgroup rcc_cfgr_hsepre RCC_CFGR HSE Divider for PLL
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
#define RCC_CFGR_PLLXTPRE_HSE_CLK 0x0
#define RCC_CFGR_PLLXTPRE_HSE_CLK_DIV2 0x1
+/**@}*/
/* PLLSRC: PLL entry clock source */
+/** @defgroup rcc_cfgr_pcs RCC_CFGR PLL Clock Source
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
#define RCC_CFGR_PLLSRC_HSI_CLK_DIV2 0x0
#define RCC_CFGR_PLLSRC_HSE_CLK 0x1
#define RCC_CFGR_PLLSRC_PREDIV1_CLK 0x1 /* On conn. line */
+/**@}*/
/* ADCPRE: ADC prescaler */
+/****************************************************************************/
+/** @defgroup rcc_cfgr_adcpre RCC ADC Clock Prescaler enable values
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
#define RCC_CFGR_ADCPRE_PCLK2_DIV2 0x0
#define RCC_CFGR_ADCPRE_PCLK2_DIV4 0x1
#define RCC_CFGR_ADCPRE_PCLK2_DIV6 0x2
#define RCC_CFGR_ADCPRE_PCLK2_DIV8 0x3
+/**@}*/
/* PPRE2: APB high-speed prescaler (APB2) */
+/** @defgroup rcc_cfgr_apb2pre RCC_CFGR APB2 Prescale Factors
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
#define RCC_CFGR_PPRE2_HCLK_NODIV 0x0
#define RCC_CFGR_PPRE2_HCLK_DIV2 0x4
#define RCC_CFGR_PPRE2_HCLK_DIV4 0x5
#define RCC_CFGR_PPRE2_HCLK_DIV8 0x6
#define RCC_CFGR_PPRE2_HCLK_DIV16 0x7
+/**@}*/
/* PPRE1: APB low-speed prescaler (APB1) */
+/** @defgroup rcc_cfgr_apb1pre RCC_CFGR APB1 Prescale Factors
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
#define RCC_CFGR_PPRE1_HCLK_NODIV 0x0
#define RCC_CFGR_PPRE1_HCLK_DIV2 0x4
#define RCC_CFGR_PPRE1_HCLK_DIV4 0x5
#define RCC_CFGR_PPRE1_HCLK_DIV8 0x6
#define RCC_CFGR_PPRE1_HCLK_DIV16 0x7
+/**@}*/
/* HPRE: AHB prescaler */
+/** @defgroup rcc_cfgr_ahbpre RCC_CFGR AHB Prescale Factors
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
#define RCC_CFGR_HPRE_SYSCLK_NODIV 0x0
#define RCC_CFGR_HPRE_SYSCLK_DIV2 0x8
#define RCC_CFGR_HPRE_SYSCLK_DIV4 0x9
@@ -139,6 +200,7 @@
#define RCC_CFGR_HPRE_SYSCLK_DIV128 0xd
#define RCC_CFGR_HPRE_SYSCLK_DIV256 0xe
#define RCC_CFGR_HPRE_SYSCLK_DIV512 0xf
+/**@}*/
/* SWS: System clock switch status */
#define RCC_CFGR_SWS_SYSCLKSEL_HSICLK 0x0
@@ -146,9 +208,14 @@
#define RCC_CFGR_SWS_SYSCLKSEL_PLLCLK 0x2
/* SW: System clock switch */
+/** @defgroup rcc_cfgr_scs RCC_CFGR System Clock Selection
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
#define RCC_CFGR_SW_SYSCLKSEL_HSICLK 0x0
#define RCC_CFGR_SW_SYSCLKSEL_HSECLK 0x1
#define RCC_CFGR_SW_SYSCLKSEL_PLLCLK 0x2
+/**@}*/
/* --- RCC_CIR values ------------------------------------------------------ */
@@ -187,6 +254,10 @@
/* --- RCC_APB2RSTR values ------------------------------------------------- */
+/** @defgroup rcc_apb2rstr_rst RCC_APB2RSTR reset values
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
#define RCC_APB2RSTR_ADC3RST (1 << 15) /* (XX) */
#define RCC_APB2RSTR_USART1RST (1 << 14)
#define RCC_APB2RSTR_TIM8RST (1 << 13) /* (XX) */
@@ -202,9 +273,14 @@
#define RCC_APB2RSTR_IOPBRST (1 << 3)
#define RCC_APB2RSTR_IOPARST (1 << 2)
#define RCC_APB2RSTR_AFIORST (1 << 0)
+/**@}*/
/* --- RCC_APB1RSTR values ------------------------------------------------- */
+/** @defgroup rcc_apb1rstr_rst RCC_APB1RSTR reset values
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
#define RCC_APB1RSTR_DACRST (1 << 29)
#define RCC_APB1RSTR_PWRRST (1 << 28)
#define RCC_APB1RSTR_BKPRST (1 << 27)
@@ -227,9 +303,14 @@
#define RCC_APB1RSTR_TIM4RST (1 << 2)
#define RCC_APB1RSTR_TIM3RST (1 << 1)
#define RCC_APB1RSTR_TIM2RST (1 << 0)
+/**@}*/
/* --- RCC_AHBENR values --------------------------------------------------- */
+/** @defgroup rcc_ahbenr_en RCC_AHBENR enable values
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
#define RCC_AHBENR_ETHMACENRX (1 << 16)
#define RCC_AHBENR_ETHMACENTX (1 << 15)
#define RCC_AHBENR_ETHMACEN (1 << 14)
@@ -241,9 +322,14 @@
#define RCC_AHBENR_SRAMEN (1 << 2)
#define RCC_AHBENR_DMA2EN (1 << 1)
#define RCC_AHBENR_DMA1EN (1 << 0)
+/**@}*/
/* --- RCC_APB2ENR values -------------------------------------------------- */
+/** @defgroup rcc_apb2enr_en RCC_APB2ENR enable values
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
#define RCC_APB2ENR_ADC3EN (1 << 15) /* (XX) */
#define RCC_APB2ENR_USART1EN (1 << 14)
#define RCC_APB2ENR_TIM8EN (1 << 13) /* (XX) */
@@ -259,9 +345,14 @@
#define RCC_APB2ENR_IOPBEN (1 << 3)
#define RCC_APB2ENR_IOPAEN (1 << 2)
#define RCC_APB2ENR_AFIOEN (1 << 0)
+/**@}*/
/* --- RCC_APB1ENR values -------------------------------------------------- */
+/** @defgroup rcc_apb1enr_en RCC_APB1ENR enable values
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
#define RCC_APB1ENR_DACEN (1 << 29)
#define RCC_APB1ENR_PWREN (1 << 28)
#define RCC_APB1ENR_BKPEN (1 << 27)
@@ -284,6 +375,7 @@
#define RCC_APB1ENR_TIM4EN (1 << 2)
#define RCC_APB1ENR_TIM3EN (1 << 1)
#define RCC_APB1ENR_TIM2EN (1 << 0)
+/**@}*/
/* --- RCC_BDCR values ----------------------------------------------------- */
@@ -308,8 +400,13 @@
/* --- RCC_AHBRSTR values -------------------------------------------------- */
+/** @defgroup rcc_ahbrstr_rst RCC_AHBRSTR reset values
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
#define RCC_AHBRSTR_ETHMACRST (1 << 14)
#define RCC_AHBRSTR_OTGFSRST (1 << 12)
+/**@}*/
/* --- RCC_CFGR2 values ---------------------------------------------------- */
@@ -379,6 +476,8 @@ typedef enum {
PLL, HSE, HSI, LSE, LSI
} osc_t;
+BEGIN_DECLS
+
void rcc_osc_ready_int_clear(osc_t osc);
void rcc_osc_ready_int_enable(osc_t osc);
void rcc_osc_ready_int_disable(osc_t osc);
@@ -408,10 +507,15 @@ void rcc_set_usbpre(u32 usbpre);
u32 rcc_get_system_clock_source(int i);
void rcc_clock_setup_in_hsi_out_64mhz(void);
void rcc_clock_setup_in_hsi_out_48mhz(void);
+void rcc_clock_setup_in_hsi_out_24mhz(void);
void rcc_clock_setup_in_hse_8mhz_out_24mhz(void);
void rcc_clock_setup_in_hse_8mhz_out_72mhz(void);
void rcc_clock_setup_in_hse_12mhz_out_72mhz(void);
void rcc_clock_setup_in_hse_16mhz_out_72mhz(void);
void rcc_backupdomain_reset(void);
+END_DECLS
+
#endif
+/**@}*/
+
diff --git a/include/libopencm3/stm32/f1/rtc.h b/include/libopencm3/stm32/f1/rtc.h
index 5e203ab..04aea01 100644
--- a/include/libopencm3/stm32/f1/rtc.h
+++ b/include/libopencm3/stm32/f1/rtc.h
@@ -126,6 +126,8 @@ typedef enum {
RTC_SEC, RTC_ALR, RTC_OW,
} rtcflag_t;
+BEGIN_DECLS
+
void rtc_awake_from_off(osc_t clock_source);
void rtc_enter_config_mode(void);
void rtc_exit_config_mode(void);
@@ -144,4 +146,6 @@ u32 rtc_check_flag(rtcflag_t flag_val);
void rtc_awake_from_standby(void);
void rtc_auto_awake(osc_t clock_source, u32 prescale_val);
+END_DECLS
+
#endif
diff --git a/include/libopencm3/stm32/f1/scb.h b/include/libopencm3/stm32/f1/scb.h
index 12a74a2..181aa7a 100644
--- a/include/libopencm3/stm32/f1/scb.h
+++ b/include/libopencm3/stm32/f1/scb.h
@@ -293,10 +293,15 @@
/* BFAR [31:0]: Bus fault address */
/* --- SCB functions ------------------------------------------------------- */
+
+BEGIN_DECLS
+
void scb_reset_core(void);
void scb_reset_system(void);
void scb_set_priority_grouping(u32 prigroup);
/* TODO: */
+END_DECLS
+
#endif
diff --git a/include/libopencm3/stm32/f2/flash.h b/include/libopencm3/stm32/f2/flash.h
index 5b4483f..2c78757 100644
--- a/include/libopencm3/stm32/f2/flash.h
+++ b/include/libopencm3/stm32/f2/flash.h
@@ -116,6 +116,8 @@
/* --- Function prototypes ------------------------------------------------- */
+BEGIN_DECLS
+
void flash_dcache_enable(void);
void flash_dcache_disable(void);
void flash_icache_enable(void);
@@ -145,4 +147,6 @@ void flash_program_byte(u32 address, u8 data, u32 program_size);
void flash_wait_for_last_operation(void);
void flash_program_option_bytes(u32 data);
+END_DECLS
+
#endif
diff --git a/include/libopencm3/stm32/f2/gpio.h b/include/libopencm3/stm32/f2/gpio.h
index 1a9fd0f..6616769 100644
--- a/include/libopencm3/stm32/f2/gpio.h
+++ b/include/libopencm3/stm32/f2/gpio.h
@@ -254,6 +254,8 @@
/* --- Function prototypes ------------------------------------------------- */
+BEGIN_DECLS
+
/*
* Note: The F2 series has a completely new GPIO peripheral with different
* configuration options. Here we implement a different API partly to more
@@ -275,4 +277,6 @@ u16 gpio_port_read(u32 gpioport);
void gpio_port_write(u32 gpioport, u16 data);
void gpio_port_config_lock(u32 gpioport, u16 gpios);
+END_DECLS
+
#endif
diff --git a/include/libopencm3/stm32/f2/rcc.h b/include/libopencm3/stm32/f2/rcc.h
index dfce266..4ffa242 100644
--- a/include/libopencm3/stm32/f2/rcc.h
+++ b/include/libopencm3/stm32/f2/rcc.h
@@ -479,6 +479,8 @@ typedef enum {
PLL, HSE, HSI, LSE, LSI
} osc_t;
+BEGIN_DECLS
+
void rcc_osc_ready_int_clear(osc_t osc);
void rcc_osc_ready_int_enable(osc_t osc);
void rcc_osc_ready_int_disable(osc_t osc);
@@ -509,4 +511,6 @@ u32 rcc_get_system_clock_source(int i);
void rcc_clock_setup_hse_3v3(const clock_scale_t *clock);
void rcc_backupdomain_reset(void);
+END_DECLS
+
#endif
diff --git a/include/libopencm3/stm32/f2/scb.h b/include/libopencm3/stm32/f2/scb.h
index 12a74a2..181aa7a 100644
--- a/include/libopencm3/stm32/f2/scb.h
+++ b/include/libopencm3/stm32/f2/scb.h
@@ -293,10 +293,15 @@
/* BFAR [31:0]: Bus fault address */
/* --- SCB functions ------------------------------------------------------- */
+
+BEGIN_DECLS
+
void scb_reset_core(void);
void scb_reset_system(void);
void scb_set_priority_grouping(u32 prigroup);
/* TODO: */
+END_DECLS
+
#endif
diff --git a/include/libopencm3/stm32/f2/timer.h b/include/libopencm3/stm32/f2/timer.h
index 3436bba..737d6f0 100644
--- a/include/libopencm3/stm32/f2/timer.h
+++ b/include/libopencm3/stm32/f2/timer.h
@@ -52,6 +52,10 @@
/* --- Function prototypes ------------------------------------------------- */
+BEGIN_DECLS
+
void timer_set_option(u32 timer_peripheral, u32 option);
+END_DECLS
+
#endif
diff --git a/include/libopencm3/stm32/f4/flash.h b/include/libopencm3/stm32/f4/flash.h
index f85d56f..2221333 100644
--- a/include/libopencm3/stm32/f4/flash.h
+++ b/include/libopencm3/stm32/f4/flash.h
@@ -115,6 +115,8 @@
/* --- Function prototypes ------------------------------------------------- */
+BEGIN_DECLS
+
void flash_dcache_enable(void);
void flash_dcache_disable(void);
void flash_icache_enable(void);
@@ -144,4 +146,6 @@ void flash_program_byte(u32 address, u8 data, u32 program_size);
void flash_wait_for_last_operation(void);
void flash_program_option_bytes(u32 data);
+END_DECLS
+
#endif
diff --git a/include/libopencm3/stm32/f4/gpio.h b/include/libopencm3/stm32/f4/gpio.h
index a5b4361..b7da9c6 100644
--- a/include/libopencm3/stm32/f4/gpio.h
+++ b/include/libopencm3/stm32/f4/gpio.h
@@ -254,6 +254,8 @@
/* --- Function prototypes ------------------------------------------------- */
+BEGIN_DECLS
+
/*
* Note: The F4 series has a completely new GPIO peripheral with different
* configuration options. Here we implement a different API partly to more
@@ -275,4 +277,6 @@ u16 gpio_port_read(u32 gpioport);
void gpio_port_write(u32 gpioport, u16 data);
void gpio_port_config_lock(u32 gpioport, u16 gpios);
+END_DECLS
+
#endif
diff --git a/include/libopencm3/stm32/f4/pwr.h b/include/libopencm3/stm32/f4/pwr.h
index ede1ae7..25fb163 100644
--- a/include/libopencm3/stm32/f4/pwr.h
+++ b/include/libopencm3/stm32/f4/pwr.h
@@ -63,6 +63,10 @@ typedef enum {
SCALE2,
} vos_scale_t;
+BEGIN_DECLS
+
void pwr_set_vos_scale(vos_scale_t scale);
+END_DECLS
+
#endif
diff --git a/include/libopencm3/stm32/f4/rcc.h b/include/libopencm3/stm32/f4/rcc.h
index 648ccb0..1688584 100644
--- a/include/libopencm3/stm32/f4/rcc.h
+++ b/include/libopencm3/stm32/f4/rcc.h
@@ -482,6 +482,8 @@ typedef enum {
PLL, HSE, HSI, LSE, LSI
} osc_t;
+BEGIN_DECLS
+
void rcc_osc_ready_int_clear(osc_t osc);
void rcc_osc_ready_int_enable(osc_t osc);
void rcc_osc_ready_int_disable(osc_t osc);
@@ -512,4 +514,6 @@ u32 rcc_get_system_clock_source(int i);
void rcc_clock_setup_hse_3v3(const clock_scale_t *clock);
void rcc_backupdomain_reset(void);
+END_DECLS
+
#endif
diff --git a/include/libopencm3/stm32/f4/scb.h b/include/libopencm3/stm32/f4/scb.h
index 12a74a2..181aa7a 100644
--- a/include/libopencm3/stm32/f4/scb.h
+++ b/include/libopencm3/stm32/f4/scb.h
@@ -293,10 +293,15 @@
/* BFAR [31:0]: Bus fault address */
/* --- SCB functions ------------------------------------------------------- */
+
+BEGIN_DECLS
+
void scb_reset_core(void);
void scb_reset_system(void);
void scb_set_priority_grouping(u32 prigroup);
/* TODO: */
+END_DECLS
+
#endif
diff --git a/include/libopencm3/stm32/f4/timer.h b/include/libopencm3/stm32/f4/timer.h
index 6d19990..988d02c 100644
--- a/include/libopencm3/stm32/f4/timer.h
+++ b/include/libopencm3/stm32/f4/timer.h
@@ -52,6 +52,10 @@
/* --- Function prototypes ------------------------------------------------- */
+BEGIN_DECLS
+
void timer_set_option(u32 timer_peripheral, u32 option);
+END_DECLS
+
#endif
diff --git a/include/libopencm3/stm32/i2c.h b/include/libopencm3/stm32/i2c.h
index 1606b64..13257eb 100644
--- a/include/libopencm3/stm32/i2c.h
+++ b/include/libopencm3/stm32/i2c.h
@@ -316,6 +316,8 @@
/* --- I2C funtion prototypes----------------------------------------------- */
+BEGIN_DECLS
+
void i2c_reset(u32 i2c);
void i2c_peripheral_enable(u32 i2c);
void i2c_peripheral_disable(u32 i2c);
@@ -331,4 +333,6 @@ void i2c_set_trise(u32 i2c, u16 trise);
void i2c_send_7bit_address(u32 i2c, u8 slave, u8 readwrite);
void i2c_send_data(u32 i2c, u8 data);
+END_DECLS
+
#endif
diff --git a/include/libopencm3/stm32/iwdg.h b/include/libopencm3/stm32/iwdg.h
index 2d24482..4e44907 100644
--- a/include/libopencm3/stm32/iwdg.h
+++ b/include/libopencm3/stm32/iwdg.h
@@ -1,3 +1,17 @@
+/** @defgroup STM32F_iwdg_defines IWDG Defines
+
+@brief <b>libopencm3 Defined Constants and Types for the STM32F Independent Watchdog Timer</b>
+
+@ingroup STM32F_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
+
+@date 18 August 2012
+
+LGPL License Terms @ref lgpl_license
+ */
/*
* This file is part of the libopencm3 project.
*
@@ -17,6 +31,8 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
+/**@{*/
+
#ifndef LIBOPENCM3_IWDG_H
#define LIBOPENCM3_IWDG_H
@@ -42,9 +58,14 @@
/* Bits [31:16]: Reserved. */
/* KEY[15:0]: Key value (write-only, reads as 0x0000) */
+/** @defgroup iwdg_key IWDG Key Values
+@ingroup STM32F_iwdg_defines
+
+@{*/
#define IWDG_KR_RESET 0xaaaa
#define IWDG_KR_UNLOCK 0x5555
#define IWDG_KR_START 0xcccc
+/**@}*/
/* --- IWDG_PR values ------------------------------------------------------ */
@@ -52,6 +73,10 @@
/* PR[2:0]: Prescaler divider */
#define IWDG_PR_LSB 0
+/** @defgroup iwdg_prediv IWDG Prescaler divider
+@ingroup STM32F_iwdg_defines
+
+@{*/
#define IWDG_PR_DIV4 0x0
#define IWDG_PR_DIV8 0x1
#define IWDG_PR_DIV16 0x2
@@ -59,6 +84,7 @@
#define IWDG_PR_DIV64 0x4
#define IWDG_PR_DIV128 0x5
#define IWDG_PR_DIV256 0x6
+/**@}*/
/* Double definition: 0x06 and 0x07 both mean DIV256 as per datasheet. */
/* #define IWDG_PR_DIV256 0x7 */
@@ -78,8 +104,18 @@
/* PVU: Watchdog prescaler value update */
#define IWDG_SR_PVU (1 << 0)
-/* --- IWDG funtion prototypes---------------------------------------------- */
+/* --- IWDG function prototypes---------------------------------------------- */
-/* TODO */
+BEGIN_DECLS
+
+void iwdg_start(void);
+void iwdg_set_period_ms(u32 period);
+bool iwdg_reload_busy(void);
+bool iwdg_prescaler_busy(void);
+void iwdg_reset(void);
+
+END_DECLS
#endif
+/**@}*/
+
diff --git a/include/libopencm3/stm32/nvic.h b/include/libopencm3/stm32/nvic.h
index 36a8fe5..694fab8 100644
--- a/include/libopencm3/stm32/nvic.h
+++ b/include/libopencm3/stm32/nvic.h
@@ -1,3 +1,17 @@
+/** @defgroup STM32F_nvic_defines NVIC Defines
+
+@brief <b>libopencm3 STM32F Nested Vectored Interrupt Controller</b>
+
+@ingroup STM32F_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2010 Piotr Esden-Tempski <piotr@esden.net>
+
+@date 18 August 2012
+
+LGPL License Terms @ref lgpl_license
+ */
/*
* This file is part of the libopencm3 project.
*
@@ -16,6 +30,7 @@
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
+/**@{*/
#ifndef LIBOPENCM3_NVIC_H
#define LIBOPENCM3_NVIC_H
@@ -65,6 +80,11 @@
/* --- IRQ channel numbers-------------------------------------------------- */
/* Cortex M3 System Interrupts */
+/** @defgroup nvic_sysint Cortex M3 System Interrupts
+@ingroup STM32F_nvic_defines
+
+IRQ numbers -3 and -6 to -9 are reserved
+@{*/
#define NVIC_NMI_IRQ -14
#define NVIC_HARD_FAULT_IRQ -13
#define NVIC_MEM_MANAGE_IRQ -12
@@ -76,9 +96,10 @@
/* irq number -3 reserved */
#define NVIC_PENDSV_IRQ -2
#define NVIC_SYSTICK_IRQ -1
+/**@}*/
-/* Note: User interrupts are family specific and are defined in a familiy
+/* Note: User interrupts are family specific and are defined in a family
* specific header file in the corresponding subfolder.
*/
@@ -95,6 +116,8 @@
/* --- NVIC functions ------------------------------------------------------ */
+BEGIN_DECLS
+
void nvic_enable_irq(u8 irqn);
void nvic_disable_irq(u8 irqn);
u8 nvic_get_pending_irq(u8 irqn);
@@ -103,6 +126,10 @@ void nvic_clear_pending_irq(u8 irqn);
u8 nvic_get_active_irq(u8 irqn);
u8 nvic_get_irq_enabled(u8 irqn);
void nvic_set_priority(u8 irqn, u8 priority);
-void nvic_generate_software_interrupt(u8 irqn);
+void nvic_generate_software_interrupt(u16 irqn);
+
+END_DECLS
#endif
+/**@}*/
+
diff --git a/include/libopencm3/stm32/pwr.h b/include/libopencm3/stm32/pwr.h
index 423ab1a..e709f3d 100644
--- a/include/libopencm3/stm32/pwr.h
+++ b/include/libopencm3/stm32/pwr.h
@@ -1,3 +1,17 @@
+/** @defgroup STM32F1xx_pwr_defines PWR Defines
+
+@ingroup STM32F_defines
+
+@brief <b>libopencm3 STM32F Power Control</b>
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
+
+@date 17 August 2012
+
+LGPL License Terms @ref lgpl_license
+ */
/*
* This file is part of the libopencm3 project.
*
@@ -17,6 +31,8 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
+/**@{*/
+
#ifndef LIBOPENCM3_PWR_H
#define LIBOPENCM3_PWR_H
@@ -40,14 +56,20 @@
/* PLS[7:5]: PVD level selection */
#define PWR_CR_PLS_LSB 5
-#define PWR_CR_PLS_2V2 0x0
-#define PWR_CR_PLS_2V3 0x1
-#define PWR_CR_PLS_2V4 0x2
-#define PWR_CR_PLS_2V5 0x3
-#define PWR_CR_PLS_2V6 0x4
-#define PWR_CR_PLS_2V7 0x5
-#define PWR_CR_PLS_2V8 0x6
-#define PWR_CR_PLS_2V9 0x7
+/** @defgroup pwr_pls PVD level selection
+@ingroup STM32F_pwr_defines
+
+@{*/
+#define PWR_CR_PLS_2V2 (0x0 << PWR_CR_PLS_LSB)
+#define PWR_CR_PLS_2V3 (0x1 << PWR_CR_PLS_LSB)
+#define PWR_CR_PLS_2V4 (0x2 << PWR_CR_PLS_LSB)
+#define PWR_CR_PLS_2V5 (0x3 << PWR_CR_PLS_LSB)
+#define PWR_CR_PLS_2V6 (0x4 << PWR_CR_PLS_LSB)
+#define PWR_CR_PLS_2V7 (0x5 << PWR_CR_PLS_LSB)
+#define PWR_CR_PLS_2V8 (0x6 << PWR_CR_PLS_LSB)
+#define PWR_CR_PLS_2V9 (0x7 << PWR_CR_PLS_LSB)
+/**@}*/
+#define PWR_CR_PLS_MASK (0x7 << PWR_CR_PLS_LSB)
/* PVDE: Power voltage detector enable */
#define PWR_CR_PVDE (1 << 4)
@@ -84,6 +106,26 @@
/* --- PWR function prototypes ------------------------------------------- */
-/* TODO */
+BEGIN_DECLS
+
+void pwr_disable_backup_domain_write_protect(void);
+void pwr_enable_backup_domain_write_protect(void);
+void pwr_enable_power_voltage_detect(u32 pvd_level);
+void pwr_disable_power_voltage_detect(void);
+void pwr_clear_standby_flag(void);
+void pwr_clear_wakeup_flag(void);
+void pwr_set_standby_mode(void);
+void pwr_set_stop_mode(void);
+void pwr_voltage_regulator_on_in_stop(void);
+void pwr_voltage_regulator_low_power_in_stop(void);
+void pwr_enable_wakeup_pin(void);
+void pwr_disable_wakeup_pin(void);
+bool pwr_voltage_high(void);
+bool pwr_get_standby_flag(void);
+bool pwr_get_wakeup_flag(void);
+
+END_DECLS
#endif
+/**@}*/
+
diff --git a/include/libopencm3/stm32/sdio.h b/include/libopencm3/stm32/sdio.h
new file mode 100644
index 0000000..16244ed
--- /dev/null
+++ b/include/libopencm3/stm32/sdio.h
@@ -0,0 +1,426 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Felix Held <felix-libopencm3@felixheld.de>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_SDIO_H
+#define LIBOPENCM3_SDIO_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+
+/* --- SDIO registers ------------------------------------------------------ */
+
+/* SDIO power control register (SDIO_POWER) */
+#define SDIO_POWER MMIO32(SDIO_BASE + 0x00)
+
+/* SDI clock control register (SDIO_CLKCR) */
+#define SDIO_CLKCR MMIO32(SDIO_BASE + 0x04)
+
+/* SDIO argument register (SDIO_ARG) */
+#define SDIO_ARG MMIO32(SDIO_BASE + 0x08)
+
+/* SDIO command register (SDIO_CMD) */
+#define SDIO_CMD MMIO32(SDIO_BASE + 0x0C)
+
+/* SDIO command response register (SDIO_RESPCMD) */
+#define SDIO_RESPCMD MMIO32(SDIO_BASE + 0x10)
+
+/* SDIO response 1..4 register (SDIO_RESPx) */
+#define SDIO_RESP1 MMIO32(SDIO_BASE + 0x14)
+#define SDIO_RESP2 MMIO32(SDIO_BASE + 0x18)
+#define SDIO_RESP3 MMIO32(SDIO_BASE + 0x1C)
+#define SDIO_RESP4 MMIO32(SDIO_BASE + 0x20)
+
+/* SDIO data timer register (SDIO_DTIMER) */
+#define SDIO_DTIMER MMIO32(SDIO_BASE + 0x24)
+
+/* SDIO data length register (SDIO_DLEN) */
+#define SDIO_DLEN MMIO32(SDIO_BASE + 0x28)
+
+/* SDIO data control register (SDIO_DCTRL) */
+#define SDIO_DCTRL MMIO32(SDIO_BASE + 0x2C)
+
+/* SDIO data counter register (SDIO_DCOUNT) */
+/* read only, write has no effect */
+#define SDIO_DCOUNT MMIO32(SDIO_BASE + 0x30)
+
+/* SDIO status register (SDIO_STA) */
+#define SDIO_STA MMIO32(SDIO_BASE + 0x34)
+
+/* SDIO interrupt clear register (SDIO_ICR) */
+#define SDIO_ICR MMIO32(SDIO_BASE + 0x38)
+
+/* SDIO mask register (SDIO_MASK) */
+#define SDIO_MASK MMIO32(SDIO_BASE + 0x3C)
+
+/* SDIO FIFO counter register (SDIO_FIFOCNT) */
+#define SDIO_FIFOCNT MMIO32(SDIO_BASE + 0x48)
+
+/* SDIO data FIFO register (SDIO_FIFO) */
+/* the SDIO data FIFO is 32 32bit words long, beginning at this address */
+#define SDIO_FIFO MMIO32(SDIO_BASE + 0x80)
+
+
+/* --- SDIO_POWER values --------------------------------------------------- */
+
+#define SDIO_POWER_PWRCTRL_SHIFT 0
+#define SDIO_POWER_PWRCTRL_PWROFF (0x0 << SDIO_POWER_PWRCTRL_SHIFT)
+/* what does "10: Reserved power-up" mean? */
+#define SDIO_POWER_PWRCTRL_RSVPWRUP (0x2 << SDIO_POWER_PWRCTRL_SHIFT)
+#define SDIO_POWER_PWRCTRL_PWRON (0x3 << SDIO_POWER_PWRCTRL_SHIFT)
+
+
+/* --- SDIO_POWER values --------------------------------------------------- */
+
+/* HWFC_EN: HW Flow Control enable */
+#define SDIO_CLKCR_HWFC_EN (1 << 14)
+
+/* NEGEDGE: SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_NEGEDGE (1 << 13)
+
+/* WIDBUS: Wide bus mode enable bit */
+/* set the width of the data bus */
+#define SDIO_CLKCR_WIDBUS_SHIFT 11
+#define SDIO_CLKCR_WIDBUS_1 (0x0 << SDIO_CLKCR_WIDBUS_SHIFT)
+#define SDIO_CLKCR_WIDBUS_4 (0x1 << SDIO_CLKCR_WIDBUS_SHIFT)
+#define SDIO_CLKCR_WIDBUS_8 (0x2 << SDIO_CLKCR_WIDBUS_SHIFT)
+
+/* BYPASS: Clock divider bypass enable bit */
+#define SDIO_CLKCR_BYPASS (1 << 10)
+
+/* PWRSAV: Power saving configuration bit */
+#define SDIO_CLKCR_PWRSAV (1 << 9)
+
+/* CLKEN: Clock enable bit */
+#define SDIO_CLKCR_CLKEN (1 << 8)
+
+/* CLKDIV: Clock divide factor */
+#define SDIO_CLKCR_CLKDIV_SHIFT 0
+#define SDIO_CLKCR_CLKDIV_MSK (0xFF << SDIO_CLKCR_CLKDIV_SHIFT)
+
+
+/* --- SDIO_CMD values ---------------------------------------------------- */
+
+/* ATACMD: CE-ATA command */
+#define SDIO_CMD_ATACMD (1 << 14)
+
+/* nIEN: not Interrupt Enable */
+#define SDIO_CMD_NIEN (1 << 13)
+
+/* ENCMDcompl: Enable CMD completion */
+#define SDIO_CMD_ENCMDCOMPL (1 << 12)
+
+/* SDIOSuspend: SD I/O suspend command */
+#define SDIO_CMD_SDIOSUSPEND (1 << 11)
+
+/* CPSMEN: Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_CPSMEN (1 << 10)
+
+/* WAITPEND: CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_WAITPEND (1 << 9)
+
+/* WAITINT: CPSM waits for interrupt request */
+#define SDIO_CMD_WAITINT (1 << 8)
+
+/* WAITRESP: Wait for response bits */
+#define SDIO_CMD_WAITRESP_SHIFT 6
+/* 00: No response, expect CMDSENT flag */
+#define SDIO_CMD_WAITRESP_NO_0 (0x0 << SDIO_CMD_WAITRESP_SHIFT)
+/* 01: Short response, expect CMDREND or CCRCFAIL flag */
+#define SDIO_CMD_WAITRESP_SHORT (0x1 << SDIO_CMD_WAITRESP_SHIFT)
+/* 10: No response, expect CMDSENT flag */
+#define SDIO_CMD_WAITRESP_NO_2 (0x2 << SDIO_CMD_WAITRESP_SHIFT)
+/* 11: Long response, expect CMDREND or CCRCFAIL flag */
+#define SDIO_CMD_WAITRESP_LONG (0x3 << SDIO_CMD_WAITRESP_SHIFT)
+
+/* CMDINDEX: Command index */
+#define SDIO_CMD_CMDINDEX_SHIFT 0
+#define SDIO_CMD_CMDINDEX_MSK (0x3F << SDIO_CMD_CMDINDEX_SHIFT)
+
+
+/* --- SDIO_RESPCMD values ------------------------------------------------ */
+
+#define SDIO_RESPCMD_SHIFT 0
+#define SDIO_RESPCMD_MSK (0x3F << SDIO_RESPCMD_SHIFT)
+
+
+/* --- SDIO_DCTRL values -------------------------------------------------- */
+
+/* SDIOEN: SD I/O enable functions */
+#define SDIO_DCTRL_SDIOEN (1 << 11)
+
+/* RWMOD: Read wait mode */
+/* 0: Read Wait control stopping SDIO_D2
+ * 1: Read Wait control using SDIO_CK
+ */
+#define SDIO_DCTRL_RWMOD (1 << 10)
+
+/* RWSTOP: Read wait stop */
+/* 0: Read wait in progress if RWSTART bit is set
+ * 1: Enable for read wait stop if RWSTART bit is set
+ */
+#define SDIO_DCTRL_RWSTOP (1 << 9)
+
+/* RWSTART: Read wait start */
+#define SDIO_DCTRL_RWSTART (1 << 8)
+
+/* DBLOCKSIZE: Data block size */
+/* SDIO_DCTRL_DBLOCKSIZE_n
+ * blocksize is 2**n bytes with 0<=n<=14
+ */
+#define SDIO_DCTRL_DBLOCKSIZE_SHIFT 4
+#define SDIO_DCTRL_DBLOCKSIZE_0 (0x0 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
+#define SDIO_DCTRL_DBLOCKSIZE_1 (0x1 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
+#define SDIO_DCTRL_DBLOCKSIZE_2 (0x2 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
+#define SDIO_DCTRL_DBLOCKSIZE_3 (0x3 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
+#define SDIO_DCTRL_DBLOCKSIZE_4 (0x4 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
+#define SDIO_DCTRL_DBLOCKSIZE_5 (0x5 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
+#define SDIO_DCTRL_DBLOCKSIZE_6 (0x6 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
+#define SDIO_DCTRL_DBLOCKSIZE_7 (0x7 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
+#define SDIO_DCTRL_DBLOCKSIZE_8 (0x8 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
+#define SDIO_DCTRL_DBLOCKSIZE_9 (0x9 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
+#define SDIO_DCTRL_DBLOCKSIZE_10 (0xA << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
+#define SDIO_DCTRL_DBLOCKSIZE_11 (0xB << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
+#define SDIO_DCTRL_DBLOCKSIZE_12 (0xC << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
+#define SDIO_DCTRL_DBLOCKSIZE_13 (0xD << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
+#define SDIO_DCTRL_DBLOCKSIZE_14 (0xE << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
+
+/* DMAEN: DMA enable bit */
+#define SDIO_DCTRL_DMAEN (1 << 3)
+
+/* DTMODE: Data transfer mode selection 1: Stream or SDIO multibyte transfer */
+#define SDIO_DCTRL_DTMODE (1 << 2)
+
+/* DTDIR: Data transfer direction selection */
+/* 0: From controller to card.
+ * 1: From card to controller.
+ */
+#define SDIO_DCTRL_DTDIR (1 << 1)
+
+/* DTEN: Data transfer enabled bit */
+#define SDIO_DCTRL_DTEN (1 << 0)
+
+
+/* --- SDIO_STA values ---------------------------------------------------- */
+
+/* CEATAEND: CE-ATA command completion signal received for CMD61 */
+#define SDIO_STA_CEATAEND (1 << 23)
+
+/* SDIOIT: SDIO interrupt received */
+#define SDIO_STA_SDIOIT (1 << 22)
+
+/* RXDAVL: Data available in receive FIFO */
+#define SDIO_STA_RXDAVL (1 << 21)
+
+/* TXDAVL: Data available in transmit FIFO */
+#define SDIO_STA_TXDAVL (1 << 20)
+
+/* RXFIFOE: Receive FIFO empty */
+#define SDIO_STA_RXFIFOE (1 << 19)
+
+/* TXFIFOE: Transmit FIFO empty */
+/* HW Flow Control enabled -> TXFIFOE signals becomes activated when the FIFO
+ * contains 2 words.
+ */
+#define SDIO_STA_TXFIFOE (1 << 18)
+
+/* RXFIFOF: Receive FIFO full */
+/* HW Flow Control enabled => RXFIFOF signals becomes activated 2 words before
+ * the FIFO is full.
+ */
+#define SDIO_STA_RXFIFOF (1 << 17)
+
+/* TXFIFOF: Transmit FIFO full */
+#define SDIO_STA_TXFIFOF (1 << 16)
+
+/* RXFIFOHF: Receive FIFO half full: there are at least 8 words in the FIFO */
+#define SDIO_STA_RXFIFOHF (1 << 15)
+
+/* TXFIFOHE: Transmit FIFO half empty: at least 8 words can be written into
+ * the FIFO
+ */
+#define SDIO_STA_TXFIFOHE (1 << 14)
+
+/* RXACT: Data receive in progress */
+#define SDIO_STA_RXACT (1 << 13)
+
+/* TXACT: Data transmit in progress */
+#define SDIO_STA_TXACT (1 << 12)
+
+/* CMDACT: Command transfer in progress */
+#define SDIO_STA_CMDACT (1 << 11)
+
+/* DBCKEND: Data block sent/received (CRC check passed) */
+#define SDIO_STA_DBCKEND (1 << 10)
+
+/* STBITERR: Start bit not detected on all data signals in wide bus mode */
+#define SDIO_STA_STBITERR (1 << 9)
+
+/* DATAEND: Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_DATAEND (1 << 8)
+
+/* CMDSENT: Command sent (no response required) */
+#define SDIO_STA_CMDSENT (1 << 7)
+
+/* CMDREND: Command response received (CRC check passed) */
+#define SDIO_STA_CMDREND (1 << 6)
+
+/* RXOVERR: Received FIFO overrun error */
+#define SDIO_STA_RXOVERR (1 << 5)
+
+/* TXUNDERR: Transmit FIFO underrun error */
+#define SDIO_STA_TXUNDERR (1 << 4)
+
+/* DTIMEOUT: Data timeout */
+#define SDIO_STA_DTIMEOUT (1 << 3)
+
+/* CTIMEOUT: Command response timeout */
+#define SDIO_STA_CTIMEOUT (1 << 2)
+
+/* DCRCFAIL: Data block sent/received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL (1 << 1)
+
+/* CCRCFAIL: Command response received (CRC check failed) */
+#define SDIO_STA_CCRCFAIL (1 << 0)
+
+
+/* --- SDIO_ICR values ---------------------------------------------------- */
+
+/* CEATAENDC: CEATAEND flag clear bit */
+#define SDIO_ICR_CEATAENDC (1 << 23)
+
+/* SDIOITC: SDIOIT flag clear bit */
+#define SDIO_ICR_SDIOITC (1 << 22)
+
+/* DBCKENDC: DBCKEND flag clear bit */
+#define SDIO_ICR_DBCKENDC (1 << 10)
+
+/* STBITERRC: STBITERR flag clear bit */
+#define SDIO_ICR_STBITERRC (1 << 9)
+
+/* DATAENDC: DATAEND flag clear bit */
+#define SDIO_ICR_DATAENDC (1 << 8)
+
+/* CMDSENTC: CMDSENT flag clear bit */
+#define SDIO_ICR_CMDSENTC (1 << 7)
+
+/* CMDRENDC: CMDREND flag clear bit */
+#define SDIO_ICR_CMDRENDC (1 << 6)
+
+/* RXOVERRC: RXOVERR flag clear bit */
+#define SDIO_ICR_RXOVERRC (1 << 5)
+
+/* TXUNDERRC: TXUNDERR flag clear bit */
+#define SDIO_ICR_TXUNDERRC (1 << 4)
+
+/* DTIMEOUTC: DTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC (1 << 3)
+
+/* CTIMEOUTC: CTIMEOUT flag clear bit */
+#define SDIO_ICR_CTIMEOUTC (1 << 2)
+
+/* DCRCFAILC: DCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC (1 << 1)
+
+/* CCRCFAILC: CCRCFAIL flag clear bit */
+#define SDIO_ICR_CCRCFAILC (1 << 0)
+
+
+/* --- SDIO_MASK values --------------------------------------------------- */
+
+/* CEATAENDIE: CE-ATA command completion signal received interrupt enable */
+#define SDIO_MASK_CEATAENDIE (1 << 23)
+
+/* SDIOITIE: SDIO mode interrupt received interrupt enable */
+#define SDIO_MASK_SDIOITIE (1 << 22)
+
+/* RXDAVLIE: Data available in Rx FIFO interrupt enable */
+#define SDIO_MASK_RXDAVLIE (1 << 21)
+
+/* TXDAVLIE: Data available in Tx FIFO interrupt enable */
+#define SDIO_MASK_TXDAVLIE (1 << 20)
+
+/* RXFIFOEIE: Rx FIFO empty interrupt enable */
+#define SDIO_MASK_RXFIFOEIE (1 << 19)
+
+/* TXFIFOEIE: Tx FIFO empty interrupt enable */
+#define SDIO_MASK_TXFIFOEIE (1 << 18)
+
+/* RXFIFOFIE: Rx FIFO full interrupt enable */
+#define SDIO_MASK_RXFIFOFIE (1 << 17)
+
+/* TXFIFOFIE: Tx FIFO full interrupt enable */
+#define SDIO_MASK_TXFIFOFIE (1 << 16)
+
+/* RXFIFOHFIE: Rx FIFO half full interrupt enable */
+#define SDIO_MASK_RXFIFOHFIE (1 << 15)
+
+/* TXFIFOHEIE: Tx FIFO half empty interrupt enable */
+#define SDIO_MASK_TXFIFOHEIE (1 << 14)
+
+/* RXACTIE: Data receive acting interrupt enable */
+#define SDIO_MASK_RXACTIE (1 << 13)
+
+/* TXACTIE: Data transmit acting interrupt enable */
+#define SDIO_MASK_TXACTIE (1 << 12)
+
+/* CMDACTIE: Command acting interrupt enable */
+#define SDIO_MASK_CMDACTIE (1 << 11)
+
+/* DBCKENDIE: Data block end interrupt enable */
+#define SDIO_MASK_DBCKENDIE (1 << 10)
+
+/* STBITERRIE: Start bit error interrupt enable */
+#define SDIO_MASK_STBITERRIE (1 << 9)
+
+/* DATAENDIE: Data end interrupt enable */
+#define SDIO_MASK_DATAENDIE (1 << 8)
+
+/* CMDSENTIE: Command sent interrupt enable */
+#define SDIO_MASK_CMDSENTIE (1 << 7)
+
+/* CMDRENDIE: Command response received interrupt enable */
+#define SDIO_MASK_CMDRENDIE (1 << 6)
+
+/* RXOVERRIE: Rx FIFO overrun error interrupt enable */
+#define SDIO_MASK_RXOVERRIE (1 << 5)
+
+/* TXUNDERRIE: Tx FIFO underrun error interrupt enable */
+#define SDIO_MASK_TXUNDERRIE (1 << 4)
+
+/* DTIMEOUTIE: Data timeout interrupt enable */
+#define SDIO_MASK_DTIMEOUTIE (1 << 3)
+
+/* CTIMEOUTIE: Command timeout interrupt enable */
+#define SDIO_MASK_CTIMEOUTIE (1 << 2)
+
+/* DCRCFAILIE: Data CRC fail interrupt enable */
+#define SDIO_MASK_DCRCFAILIE (1 << 1)
+
+/* CCRCFAILIE: Command CRC fail interrupt enable */
+#define SDIO_MASK_CCRCFAILIE (1 << 0)
+
+
+/* --- Function prototypes ------------------------------------------------- */
+
+
+/* TODO */
+
+
+#endif
diff --git a/include/libopencm3/stm32/spi.h b/include/libopencm3/stm32/spi.h
index e64dd0f..11ba820 100644
--- a/include/libopencm3/stm32/spi.h
+++ b/include/libopencm3/stm32/spi.h
@@ -297,6 +297,8 @@
/* --- Function prototypes ------------------------------------------------- */
+BEGIN_DECLS
+
void spi_reset(u32 spi_peripheral);
int spi_init_master(u32 spi, u32 br, u32 cpol, u32 cpha, u32 dff, u32 lsbfirst);
void spi_enable(u32 spi);
@@ -343,4 +345,6 @@ void spi_disable_tx_dma(u32 spi);
void spi_enable_rx_dma(u32 spi);
void spi_disable_rx_dma(u32 spi);
+END_DECLS
+
#endif
diff --git a/include/libopencm3/stm32/systick.h b/include/libopencm3/stm32/systick.h
index 376bea0..e42c4e6 100644
--- a/include/libopencm3/stm32/systick.h
+++ b/include/libopencm3/stm32/systick.h
@@ -1,3 +1,18 @@
+/** @defgroup STM32F_systick_defines SysTick Defines
+
+@brief <b>libopencm3 Defined Constants and Types for the STM32F SysTick </b>
+
+@ingroup STM32F_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
+
+@date 19 August 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
/*
* This file is part of the libopencm3 project.
*
@@ -17,6 +32,8 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
+/**@{*/
+
#ifndef LIBOPENCM3_SYSTICK_H
#define LIBOPENCM3_SYSTICK_H
@@ -45,8 +62,14 @@
/* CLKSOURCE: Clock source selection */
#define STK_CTRL_CLKSOURCE (1 << 2)
#define STK_CTRL_CLKSOURCE_LSB 2
+/** @defgroup systick_clksource Clock source selection
+@ingroup STM32F_systick_defines
+
+@{*/
#define STK_CTRL_CLKSOURCE_AHB_DIV8 0
#define STK_CTRL_CLKSOURCE_AHB 1
+/**@}*/
+
/* TICKINT: SysTick exception request enable */
#define STK_CTRL_TICKINT (1 << 1)
/* ENABLE: Counter enable */
@@ -70,6 +93,8 @@
/* --- Function Prototypes ------------------------------------------------- */
+BEGIN_DECLS
+
void systick_set_reload(u32 value);
u32 systick_get_value(void);
void systick_set_clocksource(u8 clocksource);
@@ -79,4 +104,8 @@ void systick_counter_enable(void);
void systick_counter_disable(void);
u8 systick_get_countflag(void);
+END_DECLS
+
#endif
+/**@}*/
+
diff --git a/include/libopencm3/stm32/timer.h b/include/libopencm3/stm32/timer.h
index 3c8c8c2..b6f8949 100644
--- a/include/libopencm3/stm32/timer.h
+++ b/include/libopencm3/stm32/timer.h
@@ -1,3 +1,17 @@
+/** @defgroup STM32F_tim_defines Timers Defines
+
+@brief <b>libopencm3 Defined Constants and Types for the STM32F1xx Timers</b>
+
+@ingroup STM32F_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2009 Piotr Esden-Tempski <piotr@esden.net>
+
+@date 18 May 2012
+
+LGPL License Terms @ref lgpl_license
+ */
/*
* This file is part of the libopencm3 project.
*
@@ -17,6 +31,8 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
+/**@{*/
+
#ifndef LIBOPENCM3_TIMER_H
#define LIBOPENCM3_TIMER_H
@@ -26,6 +42,11 @@
/* --- Convenience macros -------------------------------------------------- */
/* Timer register base adresses (for convenience) */
+/****************************************************************************/
+/** @defgroup tim_reg_base Timer register base addresses
+@ingroup STM32F1xx_tim_defines
+
+@{*/
#define TIM1 TIM1_BASE
#define TIM2 TIM2_BASE
#define TIM3 TIM3_BASE
@@ -34,6 +55,7 @@
#define TIM6 TIM6_BASE
#define TIM7 TIM7_BASE
#define TIM8 TIM8_BASE
+/**@}*/
/* --- Timer registers ----------------------------------------------------- */
@@ -227,25 +249,43 @@
/* --- TIMx_CR1 values ----------------------------------------------------- */
+/****************************************************************************/
+/** @defgroup tim_x_cr1_cdr TIMx_CR1 CKD[1:0] Clock Division Ratio
+@ingroup STM32F1xx_tim_defines
+
+@{*/
/* CKD[1:0]: Clock division */
#define TIM_CR1_CKD_CK_INT (0x0 << 8)
#define TIM_CR1_CKD_CK_INT_MUL_2 (0x1 << 8)
#define TIM_CR1_CKD_CK_INT_MUL_4 (0x2 << 8)
#define TIM_CR1_CKD_CK_INT_MASK (0x3 << 8)
+/**@}*/
/* ARPE: Auto-reload preload enable */
#define TIM_CR1_ARPE (1 << 7)
/* CMS[1:0]: Center-aligned mode selection */
+/****************************************************************************/
+/** @defgroup tim_x_cr1_cms TIMx_CR1 CMS[1:0]: Center-aligned Mode Selection
+@ingroup STM32F1xx_tim_defines
+
+@{*/
#define TIM_CR1_CMS_EDGE (0x0 << 5)
#define TIM_CR1_CMS_CENTER_1 (0x1 << 5)
#define TIM_CR1_CMS_CENTER_2 (0x2 << 5)
#define TIM_CR1_CMS_CENTER_3 (0x3 << 5)
#define TIM_CR1_CMS_MASK (0x3 << 5)
+/**@}*/
/* DIR: Direction */
+/****************************************************************************/
+/** @defgroup tim_x_cr1_dir TIMx_CR1 DIR: Direction
+@ingroup STM32F1xx_tim_defines
+
+@{*/
#define TIM_CR1_DIR_UP (0 << 4)
#define TIM_CR1_DIR_DOWN (1 << 4)
+/**@}*/
/* OPM: One pulse mode */
#define TIM_CR1_OPM (1 << 3)
@@ -261,32 +301,43 @@
/* --- TIMx_CR2 values ----------------------------------------------------- */
-/* OIS4: Output idle state 4 (OC4 output) */
+/****************************************************************************/
+/** @defgroup tim_x_cr2_ois TIMx_CR2_OIS: Force Output Idle State Control Values
+@ingroup STM32F1xx_tim_defines
+
+@{*/
+/* OIS4:*//** Output idle state 4 (OC4 output) */
#define TIM_CR2_OIS4 (1 << 14)
-/* OIS3N: Output idle state 3 (OC3N output) */
+/* OIS3N:*//** Output idle state 3 (OC3N output) */
#define TIM_CR2_OIS3N (1 << 13)
-/* OIS3: Output idle state 3 (OC3 output) */
+/* OIS3:*//** Output idle state 3 (OC3 output) */
#define TIM_CR2_OIS3 (1 << 12)
-/* OIS2N: Output idle state 2 (OC2N output) */
+/* OIS2N:*//** Output idle state 2 (OC2N output) */
#define TIM_CR2_OIS2N (1 << 11)
-/* OIS2: Output idle state 2 (OC2 output) */
+/* OIS2:*//** Output idle state 2 (OC2 output) */
#define TIM_CR2_OIS2 (1 << 10)
-/* OIS1N: Output idle state 1 (OC1N output) */
+/* OIS1N:*//** Output idle state 1 (OC1N output) */
#define TIM_CR2_OIS1N (1 << 9)
-/* OIS1: Output idle state 1 (OC1 output) */
+/* OIS1:*//** Output idle state 1 (OC1 output) */
#define TIM_CR2_OIS1 (1 << 8)
#define TIM_CR2_OIS_MASK (0x7f << 8)
+/**@}*/
/* TI1S: TI1 selection */
#define TIM_CR2_TI1S (1 << 7)
/* MMS[2:0]: Master mode selection */
+/****************************************************************************/
+/** @defgroup tim_mastermode TIMx_CR2 MMS[6:4]: Master Mode Selection
+@ingroup STM32F1xx_tim_defines
+
+@{*/
#define TIM_CR2_MMS_RESET (0x0 << 4)
#define TIM_CR2_MMS_ENABLE (0x1 << 4)
#define TIM_CR2_MMS_UPDATE (0x2 << 4)
@@ -296,6 +347,7 @@
#define TIM_CR2_MMS_COMPARE_OC3REF (0x6 << 4)
#define TIM_CR2_MMS_COMPARE_OC4REF (0x7 << 4)
#define TIM_CR2_MMS_MASK (0x7 << 4)
+/**@}*/
/* CCDS: Capture/compare DMA selection */
#define TIM_CR2_CCDS (1 << 3)
@@ -344,137 +396,186 @@
#define TIM_SMCR_MSM (1 << 7)
/* TS[2:0]: Trigger selection */
+/** @defgroup tim_ts TS Trigger selection
+@ingroup STM32F1xx_tim_defines
+
+@{*/
+/** Internal Trigger 0 (ITR0) */
#define TIM_SMCR_TS_ITR0 (0x0 << 4)
+/** Internal Trigger 1 (ITR1) */
#define TIM_SMCR_TS_ITR1 (0x1 << 4)
+/** Internal Trigger 2 (ITR2) */
#define TIM_SMCR_TS_ITR2 (0x2 << 4)
+/** Internal Trigger 3 (ITR3) */
#define TIM_SMCR_TS_ITR3 (0x3 << 4)
+/** TI1 Edge Detector (TI1F_ED) */
#define TIM_SMCR_TS_IT1F_ED (0x4 << 4)
+/** Filtered Timer Input 1 (TI1FP1) */
#define TIM_SMCR_TS_IT1FP1 (0x5 << 4)
+/** Filtered Timer Input 2 (TI1FP2) */
#define TIM_SMCR_TS_IT1FP2 (0x6 << 4)
+/** External Trigger input (ETRF) */
#define TIM_SMCR_TS_ETRF (0x7 << 4)
#define TIM_SMCR_TS_MASK (0x7 << 4)
+/**@}*/
/* SMS[2:0]: Slave mode selection */
+/** @defgroup tim_sms SMS Slave mode selection
+@ingroup STM32F1xx_tim_defines
+
+@{*/
+/** Slave mode disabled */
#define TIM_SMCR_SMS_OFF (0x0 << 0)
+/** Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1
+level. */
#define TIM_SMCR_SMS_EM1 (0x1 << 0)
+/** Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2
+level. */
#define TIM_SMCR_SMS_EM2 (0x2 << 0)
+/** Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges
+depending on the level of the complementary input. */
#define TIM_SMCR_SMS_EM3 (0x3 << 0)
+/** Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter
+and generates an update of the registers. */
#define TIM_SMCR_SMS_RM (0x4 << 0)
+/** Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. */
#define TIM_SMCR_SMS_GM (0x5 << 0)
+/** Trigger Mode - The counter starts at a rising edge of the trigger TRGI. */
#define TIM_SMCR_SMS_TM (0x6 << 0)
+/** External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. */
#define TIM_SMCR_SMS_ECM1 (0x7 << 0)
#define TIM_SMCR_SMS_MASK (0x7 << 0)
+/**@}*/
/* --- TIMx_DIER values ---------------------------------------------------- */
-/* TDE: Trigger DMA request enable */
+/****************************************************************************/
+/** @defgroup tim_irq_enable TIMx_DIER Timer DMA and Interrupt Enable Values
+@ingroup STM32F1xx_tim_defines
+
+@{*/
+/* TDE:*//** Trigger DMA request enable */
#define TIM_DIER_TDE (1 << 14)
-/* COMDE: COM DMA request enable */
+/* COMDE:*//** COM DMA request enable */
#define TIM_DIER_COMDE (1 << 13)
-/* CC4DE: Capture/Compare 4 DMA request enable */
+/* CC4DE:*//** Capture/Compare 4 DMA request enable */
#define TIM_DIER_CC4DE (1 << 12)
-/* CC3DE: Capture/Compare 3 DMA request enable */
+/* CC3DE:*//** Capture/Compare 3 DMA request enable */
#define TIM_DIER_CC3DE (1 << 11)
-/* CC2DE: Capture/Compare 2 DMA request enable */
+/* CC2DE:*//** Capture/Compare 2 DMA request enable */
#define TIM_DIER_CC2DE (1 << 10)
-/* CC1DE: Capture/Compare 1 DMA request enable */
+/* CC1DE:*//** Capture/Compare 1 DMA request enable */
#define TIM_DIER_CC1DE (1 << 9)
-/* UDE: Update DMA request enable */
+/* UDE*//**: Update DMA request enable */
#define TIM_DIER_UDE (1 << 8)
-/* BIE: Break interrupt enable */
+/* BIE:*//** Break interrupt enable */
#define TIM_DIER_BIE (1 << 7)
-/* TIE: Trigger interrupt enable */
+/* TIE:*//** Trigger interrupt enable */
#define TIM_DIER_TIE (1 << 6)
-/* COMIE: COM interrupt enable */
+/* COMIE:*//** COM interrupt enable */
#define TIM_DIER_COMIE (1 << 5)
-/* CC4IE: Capture/compare 4 interrupt enable */
+/* CC4IE:*//** Capture/compare 4 interrupt enable */
#define TIM_DIER_CC4IE (1 << 4)
-/* CC3IE: Capture/compare 3 interrupt enable */
+/* CC3IE:*//** Capture/compare 3 interrupt enable */
#define TIM_DIER_CC3IE (1 << 3)
-/* CC2IE: Capture/compare 2 interrupt enable */
+/* CC2IE:*//** Capture/compare 2 interrupt enable */
#define TIM_DIER_CC2IE (1 << 2)
-/* CC1IE: Capture/compare 1 interrupt enable */
+/* CC1IE:*//** Capture/compare 1 interrupt enable */
#define TIM_DIER_CC1IE (1 << 1)
-/* UIE: Update interrupt enable */
+/* UIE:*//** Update interrupt enable */
#define TIM_DIER_UIE (1 << 0)
+/**@}*/
/* --- TIMx_SR values ------------------------------------------------------ */
+/****************************************************************************/
+/** @defgroup tim_sr_values TIMx_SR Timer Status Register Flags
+@ingroup STM32F1xx_tim_defines
-/* CC4OF: Capture/compare 4 overcapture flag */
+@{*/
+
+/* CC4OF:*//** Capture/compare 4 overcapture flag */
#define TIM_SR_CC4OF (1 << 12)
-/* CC3OF: Capture/compare 3 overcapture flag */
+/* CC3OF:*//** Capture/compare 3 overcapture flag */
#define TIM_SR_CC3OF (1 << 11)
-/* CC2OF: Capture/compare 2 overcapture flag */
+/* CC2OF:*//** Capture/compare 2 overcapture flag */
#define TIM_SR_CC2OF (1 << 10)
-/* CC1OF: Capture/compare 1 overcapture flag */
+/* CC1OF:*//** Capture/compare 1 overcapture flag */
#define TIM_SR_CC1OF (1 << 9)
-/* BIF: Break interrupt flag */
+/* BIF:*//** Break interrupt flag */
#define TIM_SR_BIF (1 << 7)
-/* TIF: Trigger interrupt flag */
+/* TIF:*//** Trigger interrupt flag */
#define TIM_SR_TIF (1 << 6)
-/* COMIF: COM interrupt flag */
+/* COMIF:*//** COM interrupt flag */
#define TIM_SR_COMIF (1 << 5)
-/* CC4IF: Capture/compare 4 interrupt flag */
+/* CC4IF:*//** Capture/compare 4 interrupt flag */
#define TIM_SR_CC4IF (1 << 4)
-/* CC3IF: Capture/compare 3 interrupt flag */
+/* CC3IF:*//** Capture/compare 3 interrupt flag */
#define TIM_SR_CC3IF (1 << 3)
-/* CC2IF: Capture/compare 2 interrupt flag */
+/* CC2IF:*//** Capture/compare 2 interrupt flag */
#define TIM_SR_CC2IF (1 << 2)
-/* CC1IF: Capture/compare 1 interrupt flag */
+/* CC1IF:*//** Capture/compare 1 interrupt flag */
#define TIM_SR_CC1IF (1 << 1)
-/* UIF: Update interrupt flag */
+/* UIF:*//** Update interrupt flag */
#define TIM_SR_UIF (1 << 0)
+/**@}*/
/* --- TIMx_EGR values ----------------------------------------------------- */
-/* BG: Break generation */
+/****************************************************************************/
+/** @defgroup tim_event_gen TIMx_EGR Timer Event Generator Values
+@ingroup STM32F1xx_tim_defines
+
+@{*/
+
+/* BG:*//** Break generation */
#define TIM_EGR_BG (1 << 7)
-/* TG: Trigger generation */
+/* TG:*//** Trigger generation */
#define TIM_EGR_TG (1 << 6)
-/* COMG: Capture/compare control update generation */
+/* COMG:*//** Capture/compare control update generation */
#define TIM_EGR_COMG (1 << 5)
-/* CC4G: Capture/compare 4 generation */
+/* CC4G:*//** Capture/compare 4 generation */
#define TIM_EGR_CC4G (1 << 4)
-/* CC3G: Capture/compare 3 generation */
+/* CC3G:*//** Capture/compare 3 generation */
#define TIM_EGR_CC3G (1 << 3)
-/* CC2G: Capture/compare 2 generation */
+/* CC2G:*//** Capture/compare 2 generation */
#define TIM_EGR_CC2G (1 << 2)
-/* CC1G: Capture/compare 1 generation */
+/* CC1G:*//** Capture/compare 1 generation */
#define TIM_EGR_CC1G (1 << 1)
-/* UG: Update generation */
+/* UG:*//** Update generation */
#define TIM_EGR_UG (1 << 0)
+/**@}*/
/* --- TIMx_CCMR1 values --------------------------------------------------- */
@@ -805,11 +906,17 @@
#define TIM_BDTR_OSSI (1 << 10)
/* LOCK[1:0]: Lock configuration */
+/****************************************************************************/
+/** @defgroup tim_lock TIM_BDTR_LOCK Timer Lock Values
+@ingroup STM32F1xx_tim_defines
+
+@{*/
#define TIM_BDTR_LOCK_OFF (0x0 << 8)
#define TIM_BDTR_LOCK_LEVEL_1 (0x1 << 8)
#define TIM_BDTR_LOCK_LEVEL_2 (0x2 << 8)
#define TIM_BDTR_LOCK_LEVEL_3 (0x3 << 8)
#define TIM_BDTR_LOCK_MASK (0x3 << 8)
+/**@}*/
/* DTG[7:0]: Dead-time generator set-up */
#define TIM_BDTR_DTG_MASK 0x00FF
@@ -828,7 +935,7 @@
/* --- TIMx convenience defines -------------------------------------------- */
-/* Output Compare channel designators */
+/** Output Compare channel designators */
enum tim_oc_id {
TIM_OC1=0,
TIM_OC1N,
@@ -839,7 +946,7 @@ enum tim_oc_id {
TIM_OC4,
};
-/* Output Compare mode designators */
+/** Output Compare mode designators */
enum tim_oc_mode {
TIM_OCM_FROZEN,
TIM_OCM_ACTIVE,
@@ -851,7 +958,7 @@ enum tim_oc_mode {
TIM_OCM_PWM2,
};
-/* Input Capture channel designators */
+/** Input Capture channel designators */
enum tim_ic_id {
TIM_IC1,
TIM_IC2,
@@ -859,7 +966,13 @@ enum tim_ic_id {
TIM_IC4,
};
-/* Input Capture input filter */
+/** Input Capture input filter. The frequency used to sample the
+input and the number of events needed to validate an output transition.
+
+TIM_IC_CK_INT_N_x No division from the Deadtime and Sampling Clock frequency (DTF),
+filter length x
+TIM_IC_DTF_DIV_y_N_x Division by y from the DTF, filter length x
+ */
enum tim_ic_filter {
TIM_IC_OFF,
TIM_IC_CK_INT_N_2,
@@ -879,7 +992,9 @@ enum tim_ic_filter {
TIM_IC_DTF_DIV_32_N_8,
};
-/* Input Capture input prescaler */
+/** Input Capture input prescaler.
+
+TIM_IC_PSC_x Input capture is done every x events*/
enum tim_ic_psc {
TIM_IC_PSC_OFF,
TIM_IC_PSC_2,
@@ -887,7 +1002,10 @@ enum tim_ic_psc {
TIM_IC_PSC_8,
};
-/* Input Capture input prescaler */
+/** Input Capture input source.
+
+The direction of the channel (input/output) as well as the input used.
+ */
enum tim_ic_input {
TIM_IC_OUT = 0,
TIM_IC_IN_TI1 = 1,
@@ -897,13 +1015,16 @@ enum tim_ic_input {
TIM_IC_IN_TI4 = 6,
};
-/* Input Capture input prescaler */
+/** Input Capture input polarity */
enum tim_ic_pol {
TIM_IC_RISING,
TIM_IC_FALLING,
};
-/* --- TIM functions ------------------------------------------------------- */
+/* --- TIM function prototypes ------------------------------------------------------- */
+
+BEGIN_DECLS
+
void timer_reset(u32 timer_peripheral);
void timer_enable_irq(u32 timer_peripheral, u32 irq);
void timer_disable_irq(u32 timer_peripheral, u32 irq);
@@ -983,4 +1104,8 @@ void timer_slave_set_polarity(u32 timer, enum tim_ic_pol pol);
void timer_slave_set_mode(u32 timer, u8 mode);
void timer_slave_set_trigger(u32 timer, u8 trigger);
+END_DECLS
+
#endif
+/**@}*/
+
diff --git a/include/libopencm3/stm32/usart.h b/include/libopencm3/stm32/usart.h
index d9f2c8d..9ec6c3d 100644
--- a/include/libopencm3/stm32/usart.h
+++ b/include/libopencm3/stm32/usart.h
@@ -270,8 +270,8 @@
/* CR1_PCE / CR1_PS combined values */
#define USART_PARITY_NONE 0x00
-#define USART_PARITY_ODD USART_CR1_PS
-#define USART_PARITY_EVEN (USART_CR1_PS | USART_CR1_PCE)
+#define USART_PARITY_EVEN USART_CR1_PCE
+#define USART_PARITY_ODD (USART_CR1_PS | USART_CR1_PCE)
#define USART_PARITY_MASK (USART_CR1_PS | USART_CR1_PCE)
/* CR1_TE/CR1_RE combined values */
@@ -294,6 +294,8 @@
/* --- Function prototypes ------------------------------------------------- */
+BEGIN_DECLS
+
void usart_set_baudrate(u32 usart, u32 baud);
void usart_set_databits(u32 usart, u32 bits);
void usart_set_stopbits(u32 usart, u32 stopbits);
@@ -313,4 +315,6 @@ void usart_disable_rx_dma(u32 usart);
void usart_enable_tx_dma(u32 usart);
void usart_disable_tx_dma(u32 usart);
+END_DECLS
+
#endif