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-rw-r--r--include/libopencm3/stm32/f1/adc.h227
-rw-r--r--include/libopencm3/stm32/f1/desig.h56
-rw-r--r--include/libopencm3/stm32/f1/dma.h42
-rw-r--r--include/libopencm3/stm32/f1/doc-stm32f1.h15
-rw-r--r--include/libopencm3/stm32/f1/flash.h4
-rw-r--r--include/libopencm3/stm32/f1/gpio.h250
-rw-r--r--include/libopencm3/stm32/f1/memorymap.h5
-rw-r--r--include/libopencm3/stm32/f1/nvic_f1.h15
-rw-r--r--include/libopencm3/stm32/f1/rcc.h104
-rw-r--r--include/libopencm3/stm32/f1/rtc.h4
-rw-r--r--include/libopencm3/stm32/f1/scb.h5
11 files changed, 669 insertions, 58 deletions
diff --git a/include/libopencm3/stm32/f1/adc.h b/include/libopencm3/stm32/f1/adc.h
index 563e75d..b1396a5 100644
--- a/include/libopencm3/stm32/f1/adc.h
+++ b/include/libopencm3/stm32/f1/adc.h
@@ -1,3 +1,17 @@
+/** @defgroup STM32F1xx_adc_defines ADC Defines
+
+@brief <b>Defined Constants and Types for the STM32F1xx Analog to Digital Converters</b>
+
+@ingroup STM32F1xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2009 Edward Cheeseman <evbuilder@users.sourceforge.net>
+
+@date 18 August 2012
+
+LGPL License Terms @ref lgpl_license
+ */
/*
* This file is part of the libopencm3 project.
*
@@ -17,6 +31,8 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
+/**@{*/
+
#ifndef LIBOPENCM3_ADC_H
#define LIBOPENCM3_ADC_H
@@ -26,9 +42,15 @@
/* --- Convenience macros -------------------------------------------------- */
/* ADC port base addresses (for convenience) */
+/****************************************************************************/
+/** @defgroup adc_reg_base ADC register base addresses
+@ingroup STM32F1xx_adc_defines
+
+@{*/
#define ADC1 ADC1_BASE
#define ADC2 ADC2_BASE
#define ADC3 ADC3_BASE
+/**@}*/
/* --- ADC registers ------------------------------------------------------- */
@@ -140,6 +162,35 @@
#define ADC2_DR ADC_DR(ADC2)
#define ADC3_DR ADC_DR(ADC3)
+/* --- ADC Channels ------------------------------------------------------- */
+
+/****************************************************************************/
+/** @defgroup adc_channel ADC Channel Numbers
+@ingroup STM32F1xx_adc_defines
+
+@{*/
+#define ADC_CHANNEL0 0x00
+#define ADC_CHANNEL1 0x01
+#define ADC_CHANNEL2 0x02
+#define ADC_CHANNEL3 0x03
+#define ADC_CHANNEL4 0x04
+#define ADC_CHANNEL5 0x05
+#define ADC_CHANNEL6 0x06
+#define ADC_CHANNEL7 0x07
+#define ADC_CHANNEL8 0x08
+#define ADC_CHANNEL9 0x09
+#define ADC_CHANNEL10 0x0A
+#define ADC_CHANNEL11 0x0B
+#define ADC_CHANNEL12 0x0C
+#define ADC_CHANNEL13 0x0D
+#define ADC_CHANNEL14 0x0E
+#define ADC_CHANNEL15 0x0F
+#define ADC_CHANNEL16 0x10
+#define ADC_CHANNEL17 0x11
+/**@}*/
+#define ADC_MASK 0x1F
+#define ADC_SHIFT 0
+
/* --- ADC_SR values ------------------------------------------------------- */
#define ADC_SR_STRT (1 << 4)
@@ -171,20 +222,42 @@
* SIM: Slow interleaved mode only.
* ATM: Alternate trigger mode only.
*/
+/****************************************************************************/
+/* ADC_CR1 DUALMOD[3:0] ADC Mode Selection */
+/** @defgroup adc_cr1_dualmod ADC Mode Selection
+@ingroup STM32F1xx_adc_defines
+
+@{*/
+/** Independent (non-dual) mode */
#define ADC_CR1_DUALMOD_IND (0x0 << 16)
+/** Combined regular simultaneous + injected simultaneous mode. */
#define ADC_CR1_DUALMOD_CRSISM (0x1 << 16)
+/** Combined regular simultaneous + alternate trigger mode. */
#define ADC_CR1_DUALMOD_CRSATM (0x2 << 16)
+/** Combined injected simultaneous + fast interleaved mode. */
#define ADC_CR1_DUALMOD_CISFIM (0x3 << 16)
+/** Combined injected simultaneous + slow interleaved mode. */
#define ADC_CR1_DUALMOD_CISSIM (0x4 << 16)
+/** Injected simultaneous mode only. */
#define ADC_CR1_DUALMOD_ISM (0x5 << 16)
+/** Regular simultaneous mode only. */
#define ADC_CR1_DUALMOD_RSM (0x6 << 16)
+/** Fast interleaved mode only. */
#define ADC_CR1_DUALMOD_FIM (0x7 << 16)
+/** Slow interleaved mode only. */
#define ADC_CR1_DUALMOD_SIM (0x8 << 16)
+/** Alternate trigger mode only. */
#define ADC_CR1_DUALMOD_ATM (0x9 << 16)
+/**@}*/
#define ADC_CR1_DUALMOD_MASK (0xF << 16)
#define ADC_CR1_DUALMOD_SHIFT 16
/* DISCNUM[2:0]: Discontinous mode channel count. */
+/****************************************************************************/
+/** @defgroup adc_cr1_discnum ADC Number of channels in discontinuous mode.
+@ingroup STM32F1xx_adc_defines
+
+@{*/
#define ADC_CR1_DISCNUM_1CHANNELS (0x0 << 13)
#define ADC_CR1_DISCNUM_2CHANNELS (0x1 << 13)
#define ADC_CR1_DISCNUM_3CHANNELS (0x2 << 13)
@@ -193,31 +266,32 @@
#define ADC_CR1_DISCNUM_6CHANNELS (0x5 << 13)
#define ADC_CR1_DISCNUM_7CHANNELS (0x6 << 13)
#define ADC_CR1_DISCNUM_8CHANNELS (0x7 << 13)
+/**@}*/
#define ADC_CR1_DISCNUM_MASK (0x7 << 13)
#define ADC_CR1_DISCNUM_SHIFT 13
-/* JDISCEN: Discontinous mode on injected channels. */
+/* JDISCEN: */ /** Discontinous mode on injected channels. */
#define ADC_CR1_JDISCEN (1 << 12)
-/* DISCEN: Discontinous mode on regular channels. */
+/* DISCEN: */ /** Discontinous mode on regular channels. */
#define ADC_CR1_DISCEN (1 << 11)
-/* JAUTO: Automatic Injection Group conversion. */
+/* JAUTO: */ /** Automatic Injection Group conversion. */
#define ADC_CR1_JAUTO (1 << 10)
-/* AWDSGL: Enable the watchdog on a single channel in scan mode. */
+/* AWDSGL: */ /** Enable the watchdog on a single channel in scan mode. */
#define ADC_CR1_AWDSGL (1 << 9)
-/* SCAN: Scan mode. */
+/* SCAN: */ /** Scan mode. */
#define ADC_CR1_SCAN (1 << 8)
-/* JEOCIE: Interrupt enable for injected channels. */
+/* JEOCIE: */ /** Interrupt enable for injected channels. */
#define ADC_CR1_JEOCIE (1 << 7)
-/* AWDIE: Analog watchdog interrupt enable. */
+/* AWDIE: */ /** Analog watchdog interrupt enable. */
#define ADC_CR1_AWDIE (1 << 6)
-/* EOCIE: Interrupt enable EOC. */
+/* EOCIE: */ /** Interrupt enable EOC. */
#define ADC_CR1_EOCIE (1 << 5)
/* AWDCH[4:0]: Analog watchdog channel bits. (Up to 17 other values reserved) */
@@ -227,6 +301,12 @@
* ADC2: Analog channel 16 and 17 are internally connected to V_SS.
* ADC3: Analog channel 9, 14, 15, 16 and 17 are internally connected to V_SS.
*/
+/****************************************************************************/
+/* ADC_CR1 AWDCH[4:0] ADC watchdog channel */
+/** @defgroup adc_watchdog_channel ADC watchdog channel
+@ingroup STM32F1xx_adc_defines
+
+@{*/
#define ADC_CR1_AWDCH_CHANNEL0 (0x00 << 0)
#define ADC_CR1_AWDCH_CHANNEL1 (0x01 << 0)
#define ADC_CR1_AWDCH_CHANNEL2 (0x02 << 0)
@@ -245,41 +325,72 @@
#define ADC_CR1_AWDCH_CHANNEL15 (0x0F << 0)
#define ADC_CR1_AWDCH_CHANNEL16 (0x10 << 0)
#define ADC_CR1_AWDCH_CHANNEL17 (0x11 << 0)
+/**@}*/
#define ADC_CR1_AWDCH_MASK (0x1F << 0)
#define ADC_CR1_AWDCH_SHIFT 0
/* --- ADC_CR2 values ------------------------------------------------------ */
-/* TSVREFE: Temperature sensor and V_REFINT enable. (ADC1 only!) */
+/* TSVREFE: */ /** Temperature sensor and V_REFINT enable. (ADC1 only!) */
#define ADC_CR2_TSVREFE (1 << 23)
-/* SWSTART: Start conversion of regular channels. */
+/* SWSTART: */ /** Start conversion of regular channels. */
#define ADC_CR2_SWSTART (1 << 22)
-/* JSWSTART: Start conversion of injected channels. */
+/* JSWSTART: */ /** Start conversion of injected channels. */
#define ADC_CR2_JSWSTART (1 << 21)
-/* EXTTRIG: External trigger conversion mode for regular channels. */
+/* EXTTRIG: */ /** External trigger conversion mode for regular channels. */
#define ADC_CR2_EXTTRIG (1 << 20)
/* EXTSEL[2:0]: External event select for regular group. */
/* The following are only valid for ADC1 and ADC2. */
+/****************************************************************************/
+/* ADC_CR2 EXTSEL[2:0] ADC Trigger Identifier for ADC1 and ADC2 */
+/** @defgroup adc_trigger_regular_12 ADC Trigger Identifier for ADC1 and ADC2
+@ingroup STM32F1xx_adc_defines
+
+@{*/
+/** Timer 1 Compare Output 1 */
#define ADC_CR2_EXTSEL_TIM1_CC1 (0x0 << 17)
+/** Timer 1 Compare Output 2 */
#define ADC_CR2_EXTSEL_TIM1_CC2 (0x1 << 17)
+/** Timer 1 Compare Output 3 */
#define ADC_CR2_EXTSEL_TIM1_CC3 (0x2 << 17)
+/** Timer 2 Compare Output 2 */
#define ADC_CR2_EXTSEL_TIM2_CC2 (0x3 << 17)
+/** Timer 3 Trigger Output */
#define ADC_CR2_EXTSEL_TIM3_TRGO (0x4 << 17)
+/** Timer 4 Compare Output 4 */
#define ADC_CR2_EXTSEL_TIM4_CC4 (0x5 << 17)
+/** External Interrupt 11 */
#define ADC_CR2_EXTSEL_EXTI11 (0x6 << 17)
+/** Software Trigger */
#define ADC_CR2_EXTSEL_SWSTART (0x7 << 17)
+/**@}*/
/* The following are only valid for ADC3 */
+/****************************************************************************/
+/* ADC_CR2 EXTSEL[2:0] ADC Trigger Identifier for ADC3 */
+/** @defgroup adc_trigger_regular_3 ADC Trigger Identifier for ADC3
+@ingroup STM32F1xx_adc_defines
+
+@{*/
+/** Timer 2 Compare Output 1 */
#define ADC_CR2_EXTSEL_TIM3_CC1 (0x0 << 17)
+/** Timer 2 Compare Output 3 */
#define ADC_CR2_EXTSEL_TIM2_CC3 (0x1 << 17)
+/** Timer 1 Compare Output 3 */
+#define ADC_CR2_EXTSEL_TIM1_CC3 (0x2 << 17)
+/** Timer 8 Compare Output 1 */
#define ADC_CR2_EXTSEL_TIM8_CC1 (0x3 << 17)
+/** Timer 8 Trigger Output */
#define ADC_CR2_EXTSEL_TIM8_TRGO (0x4 << 17)
+/** Timer 5 Compare Output 1 */
#define ADC_CR2_EXTSEL_TIM5_CC1 (0x5 << 17)
+/** Timer 5 Compare Output 3 */
#define ADC_CR2_EXTSEL_TIM5_CC3 (0x6 << 17)
+/**@}*/
#define ADC_CR2_EXTSEL_MASK (0x7 << 17)
#define ADC_CR2_EXTSEL_SHIFT 17
@@ -291,21 +402,54 @@
/* JEXTSEL[2:0]: External event selection for injected group. */
/* The following are only valid for ADC1 and ADC2. */
+/****************************************************************************/
+/* ADC_CR2 JEXTSEL[2:0] ADC Injected Trigger Identifier for ADC1 and ADC2 */
+/** @defgroup adc_trigger_injected_12 ADC Injected Trigger Identifier for ADC1 and ADC2
+@ingroup STM32F1xx_adc_defines
+
+@{*/
+/** Timer 1 Trigger Output */
#define ADC_CR2_JEXTSEL_TIM1_TRGO (0x0 << 12)
+/** Timer 1 Compare Output 4 */
#define ADC_CR2_JEXTSEL_TIM1_CC4 (0x1 << 12)
+/** Timer 2 Trigger Output */
#define ADC_CR2_JEXTSEL_TIM2_TRGO (0x2 << 12)
+/** Timer 2 Compare Output 1 */
#define ADC_CR2_JEXTSEL_TIM2_CC1 (0x3 << 12)
+/** Timer 3 Compare Output 4 */
#define ADC_CR2_JEXTSEL_TIM3_CC4 (0x4 << 12)
+/** Timer 4 Trigger Output */
#define ADC_CR2_JEXTSEL_TIM4_TRGO (0x5 << 12)
+/** External Interrupt 15 */
#define ADC_CR2_JEXTSEL_EXTI15 (0x6 << 12)
+/** Injected Software Trigger */
#define ADC_CR2_JEXTSEL_JSWSTART (0x7 << 12) /* Software start. */
+/**@}*/
/* The following are the different meanings for ADC3 only. */
+/****************************************************************************/
+/* ADC_CR2 JEXTSEL[2:0] ADC Injected Trigger Identifier for ADC3 */
+/** @defgroup adc_trigger_injected_3 ADC Injected Trigger Identifier for ADC3
+@ingroup STM32F1xx_adc_defines
+
+@{*/
+/** Timer 1 Trigger Output */
+#define ADC_CR2_JEXTSEL_TIM1_TRGO (0x0 << 12)
+/** Timer 1 Compare Output 4 */
+#define ADC_CR2_JEXTSEL_TIM1_CC4 (0x1 << 12)
+/** Timer 4 Compare Output 3 */
#define ADC_CR2_JEXTSEL_TIM4_CC3 (0x2 << 12)
+/** Timer 8 Compare Output 2 */
#define ADC_CR2_JEXTSEL_TIM8_CC2 (0x3 << 12)
+/** Timer 8 Compare Output 4 */
#define ADC_CR2_JEXTSEL_TIM8_CC4 (0x4 << 12)
+/** Timer 5 Trigger Output */
#define ADC_CR2_JEXTSEL_TIM5_TRGO (0x5 << 12)
+/** Timer53 Compare Output 4 */
#define ADC_CR2_JEXTSEL_TIM5_CC4 (0x6 << 12)
+/** Injected Software Trigger */
+#define ADC_CR2_JEXTSEL_JSWSTART (0x7 << 12) /* Software start. */
+/**@}*/
#define ADC_CR2_JEXTSEL_MASK (0x7 << 12)
#define ADC_CR2_JEXTSEL_SHIFT 12
@@ -340,7 +484,6 @@
#define ADC_CR2_ADON (1 << 0)
/* --- ADC_SMPR1 values ---------------------------------------------------- */
-
#define ADC_SMPR1_SMP17_LSB 21
#define ADC_SMPR1_SMP16_LSB 18
#define ADC_SMPR1_SMP15_LSB 15
@@ -357,6 +500,12 @@
#define ADC_SMPR1_SMP12_MSK (0x7 << ADC_SMP12_LSB)
#define ADC_SMPR1_SMP11_MSK (0x7 << ADC_SMP11_LSB)
#define ADC_SMPR1_SMP10_MSK (0x7 << ADC_SMP10_LSB)
+/****************************************************************************/
+/* ADC_SMPR1 ADC Sample Time Selection for Channels */
+/** @defgroup adc_sample_r1 ADC Sample Time Selection for ADC1
+@ingroup STM32F1xx_adc_defines
+
+@{*/
#define ADC_SMPR1_SMP_1DOT5CYC 0x0
#define ADC_SMPR1_SMP_7DOT5CYC 0x1
#define ADC_SMPR1_SMP_13DOT5CYC 0x2
@@ -365,6 +514,7 @@
#define ADC_SMPR1_SMP_55DOT5CYC 0x5
#define ADC_SMPR1_SMP_71DOT5CYC 0x6
#define ADC_SMPR1_SMP_239DOT5CYC 0x7
+/**@}*/
/* --- ADC_SMPR2 values ---------------------------------------------------- */
@@ -388,6 +538,12 @@
#define ADC_SMPR2_SMP2_MSK (0x7 << ADC_SMP2_LSB)
#define ADC_SMPR2_SMP1_MSK (0x7 << ADC_SMP1_LSB)
#define ADC_SMPR2_SMP0_MSK (0x7 << ADC_SMP0_LSB)
+/****************************************************************************/
+/* ADC_SMPR2 ADC Sample Time Selection for Channels */
+/** @defgroup adc_sample_r2 ADC Sample Time Selection for ADC2
+@ingroup STM32F1xx_adc_defines
+
+@{*/
#define ADC_SMPR2_SMP_1DOT5CYC 0x0
#define ADC_SMPR2_SMP_7DOT5CYC 0x1
#define ADC_SMPR2_SMP_13DOT5CYC 0x2
@@ -396,9 +552,15 @@
#define ADC_SMPR2_SMP_55DOT5CYC 0x5
#define ADC_SMPR2_SMP_71DOT5CYC 0x6
#define ADC_SMPR2_SMP_239DOT5CYC 0x7
+/**@}*/
/* --- ADC_SMPRx generic values -------------------------------------------- */
+/****************************************************************************/
+/* ADC_SMPRG ADC Sample Time Selection for Channels */
+/** @defgroup adc_sample_rg ADC Sample Time Selection Generic
+@ingroup STM32F1xx_adc_defines
+@{*/
#define ADC_SMPR_SMP_1DOT5CYC 0x0
#define ADC_SMPR_SMP_7DOT5CYC 0x1
#define ADC_SMPR_SMP_13DOT5CYC 0x2
@@ -407,6 +569,7 @@
#define ADC_SMPR_SMP_55DOT5CYC 0x5
#define ADC_SMPR_SMP_71DOT5CYC 0x6
#define ADC_SMPR_SMP_239DOT5CYC 0x7
+/**@}*/
/* --- ADC_JOFRx, ADC_HTR, ADC_LTR values ---------------------------------- */
@@ -429,6 +592,13 @@
#define ADC_SQR1_SQ15_MSK (0x1f << ADC_SQ15_LSB)
#define ADC_SQR1_SQ14_MSK (0x1f << ADC_SQ14_LSB)
#define ADC_SQR1_SQ13_MSK (0x1f << ADC_SQ13_LSB)
+/* TODO Fix error
+#define ADC_SQR1_L_MSK (0xf << ADC_SQR1_L_LSB)
+#define ADC_SQR1_SQ16_MSK (0x1f << ADC_SQR1_SQ16_LSB)
+#define ADC_SQR1_SQ15_MSK (0x1f << ADC_SQR1_SQ15_LSB)
+#define ADC_SQR1_SQ14_MSK (0x1f << ADC_SQR1_SQ14_LSB)
+#define ADC_SQR1_SQ13_MSK (0x1f << ADC_SQR1_SQ13_LSB)
+*/
/* --- ADC_SQR2 values ----------------------------------------------------- */
@@ -444,6 +614,14 @@
#define ADC_SQR2_SQ9_MSK (0x1f << ADC_SQ9_LSB)
#define ADC_SQR2_SQ8_MSK (0x1f << ADC_SQ8_LSB)
#define ADC_SQR2_SQ7_MSK (0x1f << ADC_SQ7_LSB)
+/* TODO Fix error
+#define ADC_SQR2_SQ12_MSK (0x1f << ADC_SQR2_SQ12_LSB)
+#define ADC_SQR2_SQ11_MSK (0x1f << ADC_SQR2_SQ11_LSB)
+#define ADC_SQR2_SQ10_MSK (0x1f << ADC_SQR2_SQ10_LSB)
+#define ADC_SQR2_SQ9_MSK (0x1f << ADC_SQR2_SQ9_LSB)
+#define ADC_SQR2_SQ8_MSK (0x1f << ADC_SQR2_SQ8_LSB)
+#define ADC_SQR2_SQ7_MSK (0x1f << ADC_SQR2_SQ7_LSB)
+*/
/* --- ADC_SQR3 values ----------------------------------------------------- */
@@ -459,7 +637,14 @@
#define ADC_SQR3_SQ3_MSK (0x1f << ADC_SQ3_LSB)
#define ADC_SQR3_SQ2_MSK (0x1f << ADC_SQ2_LSB)
#define ADC_SQR3_SQ1_MSK (0x1f << ADC_SQ1_LSB)
-
+/* TODO Fix error
+#define ADC_SQR3_SQ6_MSK (0x1f << ADC_SQR3_SQ6_LSB)
+#define ADC_SQR3_SQ5_MSK (0x1f << ADC_SQR3_SQ5_LSB)
+#define ADC_SQR3_SQ4_MSK (0x1f << ADC_SQR3_SQ4_LSB)
+#define ADC_SQR3_SQ3_MSK (0x1f << ADC_SQR3_SQ3_LSB)
+#define ADC_SQR3_SQ2_MSK (0x1f << ADC_SQR3_SQ2_LSB)
+#define ADC_SQR3_SQ1_MSK (0x1f << ADC_SQR3_SQ1_LSB)
+*/
/* --- ADC_JSQR values ----------------------------------------------------- */
#define ADC_JSQR_JL_LSB 20
@@ -472,6 +657,13 @@
#define ADC_JSQR_JSQ3_MSK (0x1f << ADC_JSQ3_LSB)
#define ADC_JSQR_JSQ2_MSK (0x1f << ADC_JSQ2_LSB)
#define ADC_JSQR_JSQ1_MSK (0x1f << ADC_JSQ1_LSB)
+/* TODO Fix error
+#define ADC_JSQR_JL_MSK (0x2 << ADC_JSQR_JL_LSB)
+#define ADC_JSQR_JSQ4_MSK (0x1f << ADC_JSQR_JSQ4_LSB)
+#define ADC_JSQR_JSQ3_MSK (0x1f << ADC_JSQR_JSQ3_LSB)
+#define ADC_JSQR_JSQ2_MSK (0x1f << ADC_JSQR_JSQ2_LSB)
+#define ADC_JSQR_JSQ1_MSK (0x1f << ADC_JSQR_JSQ1_LSB)
+*/
/* --- ADC_JDRx, ADC_DR values --------------------------------------------- */
@@ -481,10 +673,11 @@
#define ADC_JDATA_MSK (0xffff << ADC_JDATA_LSB)
#define ADC_DATA_MSK (0xffff << ADC_DA)
#define ADC_ADC2DATA_MSK (0xffff << ADC_ADC2DATA_LSB)
- /* ADC1 only (dual mode) */
+ /* ADC1 only (dual mode) */
/* --- Function prototypes ------------------------------------------------- */
+BEGIN_DECLS
/* TODO */
void adc_enable_analog_watchdog_regular(u32 adc);
@@ -532,4 +725,8 @@ void adc_set_watchdog_low_threshold(u32 adc, u16 threshold);
void adc_set_regular_sequence(u32 adc, u8 length, u8 channel[]);
void adc_set_injected_sequence(u32 adc, u8 length, u8 channel[]);
+END_DECLS
+
#endif
+/**@}*/
+
diff --git a/include/libopencm3/stm32/f1/desig.h b/include/libopencm3/stm32/f1/desig.h
new file mode 100644
index 0000000..74cfb35
--- /dev/null
+++ b/include/libopencm3/stm32/f1/desig.h
@@ -0,0 +1,56 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_DESIG_H
+#define LIBOPENCM3_DESIG_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/* --- Device Electronic Signature -------------------------------- */
+
+/* Flash size register */
+#define DESIG_FLASH_SIZE MMIO16(DESIG_FLASH_SIZE_BASE + 0x00)
+
+/* Unique ID register (96 bits) */
+/* Note: ST says these may be accessed in any width if you choose */
+#define DESIG_UID_15_0 MMIO16(DESIG_UNIQUE_ID_BASE + 0x00)
+/* Listed as "This field value is also reserved for a future feature" WTH?! */
+#define DESIG_UID_31_16 MMIO16(DESIG_UNIQUE_ID_BASE + 0x02)
+#define DESIG_UID_63_32 MMIO32(DESIG_UNIQUE_ID_BASE + 0x04)
+#define DESIG_UID_95_64 MMIO32(DESIG_UNIQUE_ID_BASE + 0x08)
+
+BEGIN_DECLS
+
+/**
+ * Read the onboard flash size
+ * @return flash size in KB
+ */
+u16 desig_get_flash_size(void);
+
+/**
+ * Read the full 96 bit unique identifier
+ * Note: ST specifies that bits 31..16 are _also_ reserved for future use
+ * @param result pointer to at least 3xu32s (96 bits)
+ */
+void desig_get_unique_id(u32 result[]);
+
+END_DECLS
+
+#endif
diff --git a/include/libopencm3/stm32/f1/dma.h b/include/libopencm3/stm32/f1/dma.h
index 5aa0183..b08803f 100644
--- a/include/libopencm3/stm32/f1/dma.h
+++ b/include/libopencm3/stm32/f1/dma.h
@@ -1,3 +1,17 @@
+/** @defgroup STM32F1xx_dma_defines DMA Defines
+
+@ingroup STM32F1xx_defines
+
+@brief Defined Constants and Types for the STM32F1xx DMA Controller
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
+
+@date 18 August 2012
+
+LGPL License Terms @ref lgpl_license
+ */
/*
* This file is part of the libopencm3 project.
*
@@ -18,6 +32,8 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
+/**@{*/
+
#ifndef LIBOPENCM3_DMA_H
#define LIBOPENCM3_DMA_H
@@ -241,24 +257,39 @@
#define DMA_CCR_MEM2MEM (1 << 14)
/* PL[13:12]: Channel priority level */
+/** @defgroup dma_ch_pri DMA Channel Priority Levels
+@ingroup STM32F1xx_dma_defines
+
+@{*/
#define DMA_CCR_PL_LOW (0x0 << 12)
#define DMA_CCR_PL_MEDIUM (0x1 << 12)
#define DMA_CCR_PL_HIGH (0x2 << 12)
#define DMA_CCR_PL_VERY_HIGH (0x3 << 12)
+/**@}*/
#define DMA_CCR_PL_MASK (0x3 << 12)
#define DMA_CCR_PL_SHIFT 12
/* MSIZE[11:10]: Memory size */
+/** @defgroup dma_ch_memwidth DMA Channel Memory Word Width
+@ingroup STM32F1xx_dma_defines
+
+@{*/
#define DMA_CCR_MSIZE_8BIT (0x0 << 10)
#define DMA_CCR_MSIZE_16BIT (0x1 << 10)
#define DMA_CCR_MSIZE_32BIT (0x2 << 10)
+/**@}*/
#define DMA_CCR_MSIZE_MASK (0x3 << 10)
#define DMA_CCR_MSIZE_SHIFT 10
/* PSIZE[9:8]: Peripheral size */
+/** @defgroup dma_ch_perwidth DMA Channel Peripheral Word Width
+@ingroup STM32F1xx_dma_defines
+
+@{*/
#define DMA_CCR_PSIZE_8BIT (0x0 << 8)
#define DMA_CCR_PSIZE_16BIT (0x1 << 8)
#define DMA_CCR_PSIZE_32BIT (0x2 << 8)
+/**@}*/
#define DMA_CCR_PSIZE_MASK (0x3 << 8)
#define DMA_CCR_PSIZE_SHIFT 8
@@ -300,6 +331,10 @@
/* --- Generic values ------------------------------------------------------ */
+/** @defgroup dma_ch DMA Channel Number
+@ingroup STM32F1xx_dma_defines
+
+@{*/
#define DMA_CHANNEL1 1
#define DMA_CHANNEL2 2
#define DMA_CHANNEL3 3
@@ -307,9 +342,12 @@
#define DMA_CHANNEL5 5
#define DMA_CHANNEL6 6
#define DMA_CHANNEL7 7
+/**@}*/
/* --- function prototypes ------------------------------------------------- */
+BEGIN_DECLS
+
void dma_channel_reset(u32 dma, u8 channel);
void dma_enable_mem2mem_mode(u32 dma, u8 channel);
void dma_set_priority(u32 dma, u8 channel, u32 prio);
@@ -332,4 +370,8 @@ void dma_set_peripheral_address(u32 dma, u8 channel, u32 address);
void dma_set_memory_address(u32 dma, u8 channel, u32 address);
void dma_set_number_of_data(u32 dma, u8 channel, u16 number);
+END_DECLS
+
#endif
+/**@}*/
+
diff --git a/include/libopencm3/stm32/f1/doc-stm32f1.h b/include/libopencm3/stm32/f1/doc-stm32f1.h
new file mode 100644
index 0000000..04293a6
--- /dev/null
+++ b/include/libopencm3/stm32/f1/doc-stm32f1.h
@@ -0,0 +1,15 @@
+/** @defgroup STM32F1xx_defines STM32F1xx Defines
+
+@brief Defined Constants and Types for the STM32F1xx series
+
+@ingroup STM32F1xx
+
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies ksarkies@internode.on.net
+
+@version 1.0.0
+
+@date 18 August 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
diff --git a/include/libopencm3/stm32/f1/flash.h b/include/libopencm3/stm32/f1/flash.h
index 2c026d6..919b4d4 100644
--- a/include/libopencm3/stm32/f1/flash.h
+++ b/include/libopencm3/stm32/f1/flash.h
@@ -89,6 +89,8 @@
/* --- Function prototypes ------------------------------------------------- */
+BEGIN_DECLS
+
void flash_prefetch_buffer_enable(void);
void flash_prefetch_buffer_disable(void);
void flash_halfcycle_enable(void);
@@ -110,4 +112,6 @@ void flash_wait_for_last_operation(void);
void flash_erase_option_bytes(void);
void flash_program_option_bytes(u32 address, u16 data);
+END_DECLS
+
#endif
diff --git a/include/libopencm3/stm32/f1/gpio.h b/include/libopencm3/stm32/f1/gpio.h
index e4e11be..a1e74cc 100644
--- a/include/libopencm3/stm32/f1/gpio.h
+++ b/include/libopencm3/stm32/f1/gpio.h
@@ -1,3 +1,18 @@
+/** @defgroup STM32F1xx_gpio_defines GPIO Defines
+
+@brief <b>Defined Constants and Types for the STM32F1xx General Purpose I/O</b>
+
+@ingroup STM32F1xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
+@author @htmlonly &copy; @endhtmlonly 2012 Piotr Esden-Tempski <piotr@esden.net>
+
+@date 1 July 2012
+
+LGPL License Terms @ref lgpl_license
+ */
/*
* This file is part of the libopencm3 project.
*
@@ -17,6 +32,7 @@
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
+/**@{*/
#ifndef LIBOPENCM3_GPIO_H
#define LIBOPENCM3_GPIO_H
@@ -27,6 +43,10 @@
/* --- Convenience macros -------------------------------------------------- */
/* GPIO port base addresses (for convenience) */
+/** @defgroup gpio_port_id GPIO Port IDs
+@ingroup STM32F1xx_gpio_defines
+
+@{*/
#define GPIOA GPIO_PORT_A_BASE
#define GPIOB GPIO_PORT_B_BASE
#define GPIOC GPIO_PORT_C_BASE
@@ -34,8 +54,13 @@
#define GPIOE GPIO_PORT_E_BASE
#define GPIOF GPIO_PORT_F_BASE
#define GPIOG GPIO_PORT_G_BASE
+/**@}*/
/* GPIO number definitions (for convenience) */
+/** @defgroup gpio_pin_id GPIO Pin Identifiers
+@ingroup STM32F1xx_gpio_defines
+
+@{*/
#define GPIO0 (1 << 0)
#define GPIO1 (1 << 1)
#define GPIO2 (1 << 2)
@@ -53,6 +78,7 @@
#define GPIO14 (1 << 14)
#define GPIO15 (1 << 15)
#define GPIO_ALL 0xffff
+/**@}*/
/* --- Alternate function GPIOs -------------------------------------------- */
@@ -593,22 +619,50 @@
/* --- GPIO_CRL/GPIO_CRH values -------------------------------------------- */
+/** @defgroup gpio_cnf GPIO Pin Configuration
+@ingroup STM32F1xx_gpio_defines
+If mode specifies input, configuration can be
+@li Analog input
+@li Floating input
+@li Pull up/down input
+
+If mode specifies output, configuration can be
+@li Digital push-pull
+@li Digital open drain
+@li Alternate function push-pull or analog output
+@li Alternate function open drain or analog output
+@{*/
/* CNF[1:0] values when MODE[1:0] is 00 (input mode) */
+/** Analog Input */
#define GPIO_CNF_INPUT_ANALOG 0x00
+/** Digital Input Floating */
#define GPIO_CNF_INPUT_FLOAT 0x01 /* Default */
+/** Digital Input Pull Up and Down */
#define GPIO_CNF_INPUT_PULL_UPDOWN 0x02
-
-/* Output mode (MODE[1:0]) values */
-#define GPIO_MODE_INPUT 0x00 /* Default */
-#define GPIO_MODE_OUTPUT_10_MHZ 0x01
-#define GPIO_MODE_OUTPUT_2_MHZ 0x02
-#define GPIO_MODE_OUTPUT_50_MHZ 0x03
-
/* CNF[1:0] values when MODE[1:0] is != 00 (one of the output modes) */
+/** Digital Output Pushpull */
#define GPIO_CNF_OUTPUT_PUSHPULL 0x00
+/** Digital Output Open Drain */
#define GPIO_CNF_OUTPUT_OPENDRAIN 0x01
+/** Alternate Function Output Pushpull */
#define GPIO_CNF_OUTPUT_ALTFN_PUSHPULL 0x02
+/** Alternate Function Output Open Drain */
#define GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN 0x03
+/**@}*/
+
+/* Pin mode (MODE[1:0]) values */
+/** @defgroup gpio_mode GPIO Pin Mode
+@ingroup STM32F1xx_gpio_defines
+@li Input (default after reset)
+@li Output mode at 10 MHz maximum speed
+@li Output mode at 2 MHz maximum speed
+@li Output mode at 50 MHz maximum speed
+@{*/
+#define GPIO_MODE_INPUT 0x00 /* Default */
+#define GPIO_MODE_OUTPUT_10_MHZ 0x01
+#define GPIO_MODE_OUTPUT_2_MHZ 0x02
+#define GPIO_MODE_OUTPUT_50_MHZ 0x03
+/**@}*/
/* --- GPIO_IDR values ----------------------------------------------------- */
@@ -652,19 +706,31 @@
/* External interrupt configuration register 4 (AFIO_EXTICR4) */
#define AFIO_EXTICR4 MMIO32(AFIO_BASE + 0x14)
+/* AF remap and debug I/O configuration register (AFIO_MAPR) */
+#define AFIO_MAPR2 MMIO32(AFIO_BASE + 0x1C)
+
/* --- AFIO_EVCR values ---------------------------------------------------- */
/* EVOE: Event output enable */
#define AFIO_EVCR_EVOE (1 << 7)
/* PORT[2:0]: Port selection */
+/** @defgroup afio_evcr_port EVENTOUT Port selection
+@ingroup STM32F1xx_gpio_defines
+
+@{*/
#define AFIO_EVCR_PORT_PA (0x0 << 4)
#define AFIO_EVCR_PORT_PB (0x1 << 4)
#define AFIO_EVCR_PORT_PC (0x2 << 4)
#define AFIO_EVCR_PORT_PD (0x3 << 4)
#define AFIO_EVCR_PORT_PE (0x4 << 4)
+/**@}*/
/* PIN[3:0]: Pin selection */
+/** @defgroup afio_evcr_pin EVENTOUT Pin selection
+@ingroup STM32F1xx_gpio_defines
+
+@{*/
#define AFIO_EVCR_PIN_Px0 (0x0 << 0)
#define AFIO_EVCR_PIN_Px1 (0x1 << 0)
#define AFIO_EVCR_PIN_Px2 (0x2 << 0)
@@ -681,120 +747,211 @@
#define AFIO_EVCR_PIN_Px13 (0xD << 0)
#define AFIO_EVCR_PIN_Px14 (0xE << 0)
#define AFIO_EVCR_PIN_Px15 (0xF << 0)
+/**@}*/
/* --- AFIO_MAPR values ---------------------------------------------------- */
/* 31 reserved */
-/* PTP_PPS_REMAP: Ethernet PTP PPS remapping
+/** @defgroup afio_remap_cld Alternate Function Remap Controls for Connectivity
+Line Devices only
+@ingroup STM32F1xx_gpio_defines
+
+@{*/
+/* PTP_PPS_REMAP: *//** Ethernet PTP PPS remapping
* (only connectivity line devices) */
#define AFIO_MAPR_PTP_PPS_REMAP (1 << 30)
-/* TIM2ITR1_IREMAP: TIM2 internal trigger 1 remapping
+/* TIM2ITR1_IREMAP: *//** TIM2 internal trigger 1 remapping
* (only connectivity line devices) */
#define AFIO_MAPR_TIM2ITR1_IREMAP (1 << 29)
-/* SPI3_REMAP: SPI3/I2S3 remapping
+/* SPI3_REMAP: *//** SPI3/I2S3 remapping
* (only connectivity line devices) */
#define AFIO_MAPR_SPI3_REMAP (1 << 28)
+/* MII_REMAP: */ /** MII or RMII selection
+ * (only connectivity line devices) */
+#define AFIO_MAPR_MII_RMII_SEL (1 << 23)
+
+/* CAN2_REMAP: */ /** CAN2 I/O remapping
+ * (only connectivity line devices) */
+#define AFIO_MAPR_CAN2_REMAP (1 << 22)
+
+/* ETH_REMAP: */ /** Ethernet MAC I/O remapping
+ * (only connectivity line devices) */
+#define AFIO_MAPR_ETH_REMAP (1 << 21)
+
+/**@}*/
+
/* 27 reserved */
/* SWJ_CFG[2:0]: Serial wire JTAG configuration */
+/** @defgroup afio_swj_disable Serial Wire JTAG disables
+@ingroup STM32F1xx_gpio_defines
+
+@{*/
#define AFIO_MAPR_SWJ_MASK (0x7 << 24)
+/** Full Serial Wire JTAG capability */
#define AFIO_MAPR_SWJ_CFG_FULL_SWJ (0x0 << 24)
+/** Full Serial Wire JTAG capability without JNTRST */
#define AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_JNTRST (0x1 << 24)
+/** JTAG-DP disabled with SW-DP enabled */
#define AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_ON (0x2 << 24)
+/** JTAG-DP disabled and SW-DP disabled */
#define AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_OFF (0x4 << 24)
+/**@}*/
-/* MII_REMAP: MII or RMII selection
- * (only connectivity line devices) */
-#define AFIO_MAPR_MII_RMII_SEL (1 << 23)
+/** @defgroup afio_remap Alternate Function Remap Controls
+@ingroup STM32F1xx_gpio_defines
-/* CAN2_REMAP: CAN2 I/O remapping
- * (only connectivity line devices) */
-#define AFIO_MAPR_CAN2_REMAP (1 << 22)
-
-/* ETH_REMAP: Ethernet MAC I/O remapping
- * (only connectivity line devices) */
-#define AFIO_MAPR_ETH_REMAP (1 << 21)
-
-/* ADC2_ETRGREG_REMAP: ADC2 external trigger regulator conversion remapping
+@{*/
+/* ADC2_ETRGREG_REMAP: */ /** ADC2 external trigger regulator conversion remapping
* (only low-, medium-, high- and XL-densitiy devices) */
#define AFIO_MAPR_ADC2_ETRGREG_REMAP (1 << 20)
-/* ADC2_ETRGINJ_REMAP: ADC2 external trigger injected conversion remapping
+/* ADC2_ETRGINJ_REMAP: */ /** ADC2 external trigger injected conversion remapping
* (only low-, medium-, high- and XL-densitiy devices) */
#define AFIO_MAPR_ADC2_ETRGINJ_REMAP (1 << 19)
-/* ADC1_ETRGREG_REMAP: ADC1 external trigger regulator conversion remapping
+/* ADC1_ETRGREG_REMAP: */ /** ADC1 external trigger regulator conversion remapping
* (only low-, medium-, high- and XL-densitiy devices) */
#define AFIO_MAPR_ADC1_ETRGREG_REMAP (1 << 18)
-/* ADC1_ETRGINJ_REMAP: ADC1 external trigger injected conversion remapping
+/* ADC1_ETRGINJ_REMAP: */ /** ADC1 external trigger injected conversion remapping
* (only low-, medium-, high- and XL-densitiy devices) */
#define AFIO_MAPR_ADC1_ETRGINJ_REMAP (1 << 17)
-/* TIM5CH4_IREMAP: TIM5 channel4 internal remap */
+/* TIM5CH4_IREMAP: */ /** TIM5 channel4 internal remap */
#define AFIO_MAPR_TIM5CH4_IREMAP (1 << 16)
-/* PD01_REMAP: Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
+/* PD01_REMAP: */ /** Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
#define AFIO_MAPR_PD01_REMAP (1 << 15)
+/* TIM4_REMAP: */ /** TIM4 remapping */
+#define AFIO_MAPR_TIM4_REMAP (1 << 12)
+
+/* USART2_REMAP[1:0]: */ /** USART2 remapping */
+#define AFIO_MAPR_USART2_REMAP (1 << 3)
+
+/* USART1_REMAP[1:0]: */ /** USART1 remapping */
+#define AFIO_MAPR_USART1_REMAP (1 << 2)
+
+/* I2C1_REMAP[1:0]: */ /** I2C1 remapping */
+#define AFIO_MAPR_I2C1_REMAP (1 << 1)
+
+/* SPI1_REMAP[1:0]: */ /** SPI1 remapping */
+#define AFIO_MAPR_SPI1_REMAP (1 << 0)
+/**@}*/
+
/* CAN_REMAP[1:0]: CAN1 alternate function remapping */
+/** @defgroup afio_remap_can1 Alternate Function Remap Controls for CAN 1
+@ingroup STM32F1xx_gpio_defines
+
+@{*/
#define AFIO_MAPR_CAN1_REMAP_PORTA (0x0 << 13)
#define AFIO_MAPR_CAN1_REMAP_PORTB (0x2 << 13) /* Not on 36pin pkg */
#define AFIO_MAPR_CAN1_REMAP_PORTD (0x3 << 13)
-
-/* TIM4_REMAP: TIM4 remapping */
-#define AFIO_MAPR_TIM4_REMAP (1 << 12)
+/**@}*/
/* TIM3_REMAP[1:0]: TIM3 remapping */
+/** @defgroup afio_remap_tim3 Alternate Function Remap Controls for Timer 3
+@ingroup STM32F1xx_gpio_defines
+
+@{*/
#define AFIO_MAPR_TIM3_REMAP_NO_REMAP (0x0 << 10)
#define AFIO_MAPR_TIM3_REMAP_PARTIAL_REMAP (0x2 << 10)
#define AFIO_MAPR_TIM3_REMAP_FULL_REMAP (0x3 << 10)
+/**@}*/
/* TIM2_REMAP[1:0]: TIM2 remapping */
+/** @defgroup afio_remap_tim2 Alternate Function Remap Controls for Timer 2
+@ingroup STM32F1xx_gpio_defines
+
+@{*/
#define AFIO_MAPR_TIM2_REMAP_NO_REMAP (0x0 << 8)
#define AFIO_MAPR_TIM2_REMAP_PARTIAL_REMAP1 (0x1 << 8)
#define AFIO_MAPR_TIM2_REMAP_PARTIAL_REMAP2 (0x2 << 8)
#define AFIO_MAPR_TIM2_REMAP_FULL_REMAP (0x3 << 8)
+/**@}*/
/* TIM1_REMAP[1:0]: TIM1 remapping */
+/** @defgroup afio_remap_tim1 Alternate Function Remap Controls for Timer 1
+@ingroup STM32F1xx_gpio_defines
+
+@{*/
#define AFIO_MAPR_TIM1_REMAP_NO_REMAP (0x0 << 6)
#define AFIO_MAPR_TIM1_REMAP_PARTIAL_REMAP (0x1 << 6)
#define AFIO_MAPR_TIM1_REMAP_FULL_REMAP (0x3 << 6)
+/**@}*/
/* USART3_REMAP[1:0]: USART3 remapping */
+/** @defgroup afio_remap_usart3 Alternate Function Remap Controls for USART 3
+@ingroup STM32F1xx_gpio_defines
+
+@{*/
#define AFIO_MAPR_USART3_REMAP_NO_REMAP (0x0 << 4)
#define AFIO_MAPR_USART3_REMAP_PARTIAL_REMAP (0x1 << 4)
#define AFIO_MAPR_USART3_REMAP_FULL_REMAP (0x3 << 4)
+/**@}*/
-/* USART2_REMAP[1:0]: USART2 remapping */
-#define AFIO_MAPR_USART2_REMAP (1 << 3)
+/** @defgroup afio_remap2 Alternate Function Remap Controls Secondary Set
+@ingroup STM32F1xx_gpio_defines
-/* USART1_REMAP[1:0]: USART1 remapping */
-#define AFIO_MAPR_USART1_REMAP (1 << 2)
+@{*/
+/* FSMC_NADV_DISCONNECT: */ /** The NADV is disconnected from its allocated pin */
+#define AFIO_MAPR2_FSMC_NADV_DISCONNECT (1 << 10)
-/* I2C1_REMAP[1:0]: I2C1 remapping */
-#define AFIO_MAPR_I2C1_REMAP (1 << 1)
+/* TIM14_REMAP: */ /** TIM14 remapping */
+#define AFIO_MAPR2_TIM14_REMAP (1 << 9)
-/* SPI1_REMAP[1:0]: SPI1 remapping */
-#define AFIO_MAPR_SPI1_REMAP (1 << 0)
+/* TIM13_REMAP: */ /** TIM13 remapping */
+#define AFIO_MAPR2_TIM13_REMAP (1 << 8)
+
+/* TIM11_REMAP: */ /** TIM11 remapping */
+#define AFIO_MAPR2_TIM11_REMAP (1 << 7)
+
+/* TIM10_REMAP: */ /** TIM10 remapping */
+#define AFIO_MAPR2_TIM10_REMAP (1 << 6)
+
+/* TIM9_REMAP: */ /** TIM9 remapping */
+#define AFIO_MAPR2_TIM9_REMAP (1 << 5)
+
+/**@}*/
/* --- AFIO_EXTICR1 values ------------------------------------------------- */
/* --- AFIO_EXTICR2 values ------------------------------------------------- */
/* --- AFIO_EXTICR3 values ------------------------------------------------- */
/* --- AFIO_EXTICR4 values ------------------------------------------------- */
-/* EXTI0 - EXTI15 interrupt source selection registers */
-
-/* Note: For using them we should define a function that calculates the right
- * registers, using definitions is probably not a good idea.
- */
+/** @defgroup afio_exti Alternate Function EXTI pin number
+@ingroup STM32F1xx_gpio_defines
+
+@{*/
+
+#define AFIO_EXTI0 0
+#define AFIO_EXTI1 1
+#define AFIO_EXTI2 2
+#define AFIO_EXTI3 3
+#define AFIO_EXTI4 4
+#define AFIO_EXTI5 5
+#define AFIO_EXTI6 6
+#define AFIO_EXTI7 7
+#define AFIO_EXTI8 8
+#define AFIO_EXTI9 9
+#define AFIO_EXTI10 10
+#define AFIO_EXTI11 11
+#define AFIO_EXTI12 12
+#define AFIO_EXTI13 13
+#define AFIO_EXTI14 14
+#define AFIO_EXTI15 15
+
+/**@}*/
/* --- Function prototypes ------------------------------------------------- */
+BEGIN_DECLS
+
void gpio_set_mode(u32 gpioport, u8 mode, u8 cnf, u16 gpios);
void gpio_set(u32 gpioport, u16 gpios);
void gpio_clear(u32 gpioport, u16 gpios);
@@ -803,5 +960,12 @@ void gpio_toggle(u32 gpioport, u16 gpios);
u16 gpio_port_read(u32 gpioport);
void gpio_port_write(u32 gpioport, u16 data);
void gpio_port_config_lock(u32 gpioport, u16 gpios);
+void gpio_set_eventout(u8 evoutport, u8 evoutpin);
+void gpio_primary_remap(u8 swjenable, u32 maps);
+void gpio_secondary_remap(u32 maps);
+
+END_DECLS
#endif
+/**@}*/
+
diff --git a/include/libopencm3/stm32/f1/memorymap.h b/include/libopencm3/stm32/f1/memorymap.h
index f8528d4..5cc432e 100644
--- a/include/libopencm3/stm32/f1/memorymap.h
+++ b/include/libopencm3/stm32/f1/memorymap.h
@@ -26,6 +26,7 @@
/* Memory map for all busses */
#define PERIPH_BASE ((u32)0x40000000)
+#define INFO_BASE ((u32)0x1ffff000)
#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)
#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)
#define PERIPH_BASE_AHB (PERIPH_BASE + 0x18000)
@@ -110,4 +111,8 @@
/* FSMC */
#define FSMC_BASE (PERIPH_BASE + 0x60000000)
+/* Device Electronic Signature */
+#define DESIG_FLASH_SIZE_BASE (INFO_BASE + 0x7e0)
+#define DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x7e8)
+
#endif
diff --git a/include/libopencm3/stm32/f1/nvic_f1.h b/include/libopencm3/stm32/f1/nvic_f1.h
index 884f728..5223bb6 100644
--- a/include/libopencm3/stm32/f1/nvic_f1.h
+++ b/include/libopencm3/stm32/f1/nvic_f1.h
@@ -1,3 +1,13 @@
+/** @brief <b>Defined Constants and Types for the STM32F1xx Nested Vectored Interrupt Controller</b>
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
+
+@date 18 August 2012
+
+LGPL License Terms @ref lgpl_license
+ */
/*
* This file is part of the libopencm3 project.
*
@@ -27,6 +37,10 @@
*/
/* User Interrupts */
+/** @defgroup nvic_stm32f1_userint STM32F1xx User Interrupts
+@ingroup STM32F_nvic_defines
+
+@{*/
#define NVIC_WWDG_IRQ 0
#define NVIC_PVD_IRQ 1
#define NVIC_TAMPER_IRQ 2
@@ -95,5 +109,6 @@
#define NVIC_CAN2_RX1_IRQ 65
#define NVIC_CAN2_SCE_IRQ 66
#define NVIC_OTG_FS_IRQ 67
+/**@}*/
#endif
diff --git a/include/libopencm3/stm32/f1/rcc.h b/include/libopencm3/stm32/f1/rcc.h
index 9cbe1e7..855e43b 100644
--- a/include/libopencm3/stm32/f1/rcc.h
+++ b/include/libopencm3/stm32/f1/rcc.h
@@ -1,3 +1,18 @@
+/** @defgroup STM32F1xx_rcc_defines RCC Defines
+
+@brief <b>libopencm3 STM32F1xx Reset and Clock Control</b>
+
+@ingroup STM32F1xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2009 Federico Ruiz-Ugalde \<memeruiz at gmail dot com\>
+@author @htmlonly &copy; @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
+
+@date 18 August 2012
+
+LGPL License Terms @ref lgpl_license
+ */
/*
* This file is part of the libopencm3 project.
*
@@ -17,6 +32,7 @@
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
+/**@{*/
#ifndef LIBOPENCM3_RCC_H
#define LIBOPENCM3_RCC_H
@@ -62,6 +78,10 @@
/* --- RCC_CFGR values ----------------------------------------------------- */
/* MCO: Microcontroller clock output */
+/** @defgroup rcc_cfgr_co RCC_CFGR Microcontroller Clock Output Source
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
#define RCC_CFGR_MCO_NOCLK 0x0
#define RCC_CFGR_MCO_SYSCLK 0x4
#define RCC_CFGR_MCO_HSICLK 0x5
@@ -71,16 +91,26 @@
#define RCC_CFGR_MCO_PLL3CLK_DIV2 0x9 /* (**) */
#define RCC_CFGR_MCO_XT1 0xa /* (**) */
#define RCC_CFGR_MCO_PLL3 0xb /* (**) */
+/**@}*/
/* USBPRE: USB prescaler (RCC_CFGR[22]) */
+/** @defgroup rcc_cfgr_usbpre RCC_CFGR USB prescale Factors
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
#define RCC_CFGR_USBPRE_PLL_CLK_DIV1_5 0x0
#define RCC_CFGR_USBPRE_PLL_CLK_NODIV 0x1
+/**@}*/
/* OTGFSPRE: USB OTG FS prescaler (RCC_CFGR[22]; only in conn. line STM32s) */
#define RCC_CFGR_USBPRE_PLL_VCO_CLK_DIV3 0x0
#define RCC_CFGR_USBPRE_PLL_VCO_CLK_DIV2 0x1
/* PLLMUL: PLL multiplication factor */
+/** @defgroup rcc_cfgr_pmf RCC_CFGR PLL Multiplication Factor
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL2 0x0 /* (XX) */
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL3 0x1 /* (XX) */
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL4 0x2
@@ -98,38 +128,69 @@
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL6_5 0xd /* 0xd: PLL x 6.5 for conn. line */
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL16 0xe /* (XX) */
// #define PLLMUL_PLL_CLK_MUL16 0xf /* (XX) */ /* Errata? 17? */
+/**@}*/
/* TODO: conn. line differs. */
/* PLLXTPRE: HSE divider for PLL entry */
+/** @defgroup rcc_cfgr_hsepre RCC_CFGR HSE Divider for PLL
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
#define RCC_CFGR_PLLXTPRE_HSE_CLK 0x0
#define RCC_CFGR_PLLXTPRE_HSE_CLK_DIV2 0x1
+/**@}*/
/* PLLSRC: PLL entry clock source */
+/** @defgroup rcc_cfgr_pcs RCC_CFGR PLL Clock Source
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
#define RCC_CFGR_PLLSRC_HSI_CLK_DIV2 0x0
#define RCC_CFGR_PLLSRC_HSE_CLK 0x1
#define RCC_CFGR_PLLSRC_PREDIV1_CLK 0x1 /* On conn. line */
+/**@}*/
/* ADCPRE: ADC prescaler */
+/****************************************************************************/
+/** @defgroup rcc_cfgr_adcpre RCC ADC Clock Prescaler enable values
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
#define RCC_CFGR_ADCPRE_PCLK2_DIV2 0x0
#define RCC_CFGR_ADCPRE_PCLK2_DIV4 0x1
#define RCC_CFGR_ADCPRE_PCLK2_DIV6 0x2
#define RCC_CFGR_ADCPRE_PCLK2_DIV8 0x3
+/**@}*/
/* PPRE2: APB high-speed prescaler (APB2) */
+/** @defgroup rcc_cfgr_apb2pre RCC_CFGR APB2 Prescale Factors
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
#define RCC_CFGR_PPRE2_HCLK_NODIV 0x0
#define RCC_CFGR_PPRE2_HCLK_DIV2 0x4
#define RCC_CFGR_PPRE2_HCLK_DIV4 0x5
#define RCC_CFGR_PPRE2_HCLK_DIV8 0x6
#define RCC_CFGR_PPRE2_HCLK_DIV16 0x7
+/**@}*/
/* PPRE1: APB low-speed prescaler (APB1) */
+/** @defgroup rcc_cfgr_apb1pre RCC_CFGR APB1 Prescale Factors
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
#define RCC_CFGR_PPRE1_HCLK_NODIV 0x0
#define RCC_CFGR_PPRE1_HCLK_DIV2 0x4
#define RCC_CFGR_PPRE1_HCLK_DIV4 0x5
#define RCC_CFGR_PPRE1_HCLK_DIV8 0x6
#define RCC_CFGR_PPRE1_HCLK_DIV16 0x7
+/**@}*/
/* HPRE: AHB prescaler */
+/** @defgroup rcc_cfgr_ahbpre RCC_CFGR AHB Prescale Factors
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
#define RCC_CFGR_HPRE_SYSCLK_NODIV 0x0
#define RCC_CFGR_HPRE_SYSCLK_DIV2 0x8
#define RCC_CFGR_HPRE_SYSCLK_DIV4 0x9
@@ -139,6 +200,7 @@
#define RCC_CFGR_HPRE_SYSCLK_DIV128 0xd
#define RCC_CFGR_HPRE_SYSCLK_DIV256 0xe
#define RCC_CFGR_HPRE_SYSCLK_DIV512 0xf
+/**@}*/
/* SWS: System clock switch status */
#define RCC_CFGR_SWS_SYSCLKSEL_HSICLK 0x0
@@ -146,9 +208,14 @@
#define RCC_CFGR_SWS_SYSCLKSEL_PLLCLK 0x2
/* SW: System clock switch */
+/** @defgroup rcc_cfgr_scs RCC_CFGR System Clock Selection
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
#define RCC_CFGR_SW_SYSCLKSEL_HSICLK 0x0
#define RCC_CFGR_SW_SYSCLKSEL_HSECLK 0x1
#define RCC_CFGR_SW_SYSCLKSEL_PLLCLK 0x2
+/**@}*/
/* --- RCC_CIR values ------------------------------------------------------ */
@@ -187,6 +254,10 @@
/* --- RCC_APB2RSTR values ------------------------------------------------- */
+/** @defgroup rcc_apb2rstr_rst RCC_APB2RSTR reset values
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
#define RCC_APB2RSTR_ADC3RST (1 << 15) /* (XX) */
#define RCC_APB2RSTR_USART1RST (1 << 14)
#define RCC_APB2RSTR_TIM8RST (1 << 13) /* (XX) */
@@ -202,9 +273,14 @@
#define RCC_APB2RSTR_IOPBRST (1 << 3)
#define RCC_APB2RSTR_IOPARST (1 << 2)
#define RCC_APB2RSTR_AFIORST (1 << 0)
+/**@}*/
/* --- RCC_APB1RSTR values ------------------------------------------------- */
+/** @defgroup rcc_apb1rstr_rst RCC_APB1RSTR reset values
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
#define RCC_APB1RSTR_DACRST (1 << 29)
#define RCC_APB1RSTR_PWRRST (1 << 28)
#define RCC_APB1RSTR_BKPRST (1 << 27)
@@ -227,9 +303,14 @@
#define RCC_APB1RSTR_TIM4RST (1 << 2)
#define RCC_APB1RSTR_TIM3RST (1 << 1)
#define RCC_APB1RSTR_TIM2RST (1 << 0)
+/**@}*/
/* --- RCC_AHBENR values --------------------------------------------------- */
+/** @defgroup rcc_ahbenr_en RCC_AHBENR enable values
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
#define RCC_AHBENR_ETHMACENRX (1 << 16)
#define RCC_AHBENR_ETHMACENTX (1 << 15)
#define RCC_AHBENR_ETHMACEN (1 << 14)
@@ -241,9 +322,14 @@
#define RCC_AHBENR_SRAMEN (1 << 2)
#define RCC_AHBENR_DMA2EN (1 << 1)
#define RCC_AHBENR_DMA1EN (1 << 0)
+/**@}*/
/* --- RCC_APB2ENR values -------------------------------------------------- */
+/** @defgroup rcc_apb2enr_en RCC_APB2ENR enable values
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
#define RCC_APB2ENR_ADC3EN (1 << 15) /* (XX) */
#define RCC_APB2ENR_USART1EN (1 << 14)
#define RCC_APB2ENR_TIM8EN (1 << 13) /* (XX) */
@@ -259,9 +345,14 @@
#define RCC_APB2ENR_IOPBEN (1 << 3)
#define RCC_APB2ENR_IOPAEN (1 << 2)
#define RCC_APB2ENR_AFIOEN (1 << 0)
+/**@}*/
/* --- RCC_APB1ENR values -------------------------------------------------- */
+/** @defgroup rcc_apb1enr_en RCC_APB1ENR enable values
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
#define RCC_APB1ENR_DACEN (1 << 29)
#define RCC_APB1ENR_PWREN (1 << 28)
#define RCC_APB1ENR_BKPEN (1 << 27)
@@ -284,6 +375,7 @@
#define RCC_APB1ENR_TIM4EN (1 << 2)
#define RCC_APB1ENR_TIM3EN (1 << 1)
#define RCC_APB1ENR_TIM2EN (1 << 0)
+/**@}*/
/* --- RCC_BDCR values ----------------------------------------------------- */
@@ -308,8 +400,13 @@
/* --- RCC_AHBRSTR values -------------------------------------------------- */
+/** @defgroup rcc_ahbrstr_rst RCC_AHBRSTR reset values
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
#define RCC_AHBRSTR_ETHMACRST (1 << 14)
#define RCC_AHBRSTR_OTGFSRST (1 << 12)
+/**@}*/
/* --- RCC_CFGR2 values ---------------------------------------------------- */
@@ -379,6 +476,8 @@ typedef enum {
PLL, HSE, HSI, LSE, LSI
} osc_t;
+BEGIN_DECLS
+
void rcc_osc_ready_int_clear(osc_t osc);
void rcc_osc_ready_int_enable(osc_t osc);
void rcc_osc_ready_int_disable(osc_t osc);
@@ -408,10 +507,15 @@ void rcc_set_usbpre(u32 usbpre);
u32 rcc_get_system_clock_source(int i);
void rcc_clock_setup_in_hsi_out_64mhz(void);
void rcc_clock_setup_in_hsi_out_48mhz(void);
+void rcc_clock_setup_in_hsi_out_24mhz(void);
void rcc_clock_setup_in_hse_8mhz_out_24mhz(void);
void rcc_clock_setup_in_hse_8mhz_out_72mhz(void);
void rcc_clock_setup_in_hse_12mhz_out_72mhz(void);
void rcc_clock_setup_in_hse_16mhz_out_72mhz(void);
void rcc_backupdomain_reset(void);
+END_DECLS
+
#endif
+/**@}*/
+
diff --git a/include/libopencm3/stm32/f1/rtc.h b/include/libopencm3/stm32/f1/rtc.h
index 5e203ab..04aea01 100644
--- a/include/libopencm3/stm32/f1/rtc.h
+++ b/include/libopencm3/stm32/f1/rtc.h
@@ -126,6 +126,8 @@ typedef enum {
RTC_SEC, RTC_ALR, RTC_OW,
} rtcflag_t;
+BEGIN_DECLS
+
void rtc_awake_from_off(osc_t clock_source);
void rtc_enter_config_mode(void);
void rtc_exit_config_mode(void);
@@ -144,4 +146,6 @@ u32 rtc_check_flag(rtcflag_t flag_val);
void rtc_awake_from_standby(void);
void rtc_auto_awake(osc_t clock_source, u32 prescale_val);
+END_DECLS
+
#endif
diff --git a/include/libopencm3/stm32/f1/scb.h b/include/libopencm3/stm32/f1/scb.h
index 12a74a2..181aa7a 100644
--- a/include/libopencm3/stm32/f1/scb.h
+++ b/include/libopencm3/stm32/f1/scb.h
@@ -293,10 +293,15 @@
/* BFAR [31:0]: Bus fault address */
/* --- SCB functions ------------------------------------------------------- */
+
+BEGIN_DECLS
+
void scb_reset_core(void);
void scb_reset_system(void);
void scb_set_priority_grouping(u32 prigroup);
/* TODO: */
+END_DECLS
+
#endif