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Diffstat (limited to 'examples/stm32-h103/fancyblink')
-rw-r--r--examples/stm32-h103/fancyblink/fancyblink.c21
1 files changed, 3 insertions, 18 deletions
diff --git a/examples/stm32-h103/fancyblink/fancyblink.c b/examples/stm32-h103/fancyblink/fancyblink.c
index 1118e4d..39652ec 100644
--- a/examples/stm32-h103/fancyblink/fancyblink.c
+++ b/examples/stm32-h103/fancyblink/fancyblink.c
@@ -23,30 +23,15 @@
/* Set STM32 to 72 MHz. */
void clock_setup(void)
{
- /* Select HSI as SYSCLK source. */
- rcc_set_sysclk_source(SW_SYSCLKSEL_HSICLK);
+ rcc_clock_setup_in_hse_8mhz_out_72mhz();
- /* Set the PLL multiplication factor to 9. */
- rcc_set_pll_multiplication_factor(PLLMUL_PLL_CLK_MUL9);
-
- /* Select HSI/2 as PLL source. */
- rcc_set_pll_source(PLLSRC_HSI_CLK_DIV2);
-
- rcc_set_pllxtpre(PLLXTPRE_HSE_CLK_DIV2);
-
- /* Enable PLL oscillator and wait for it to stabilize. */
- rcc_osc_on(PLL);
- rcc_wait_for_osc_ready(PLL);
+ /* Enable GPIOC clock. */
+ rcc_peripheral_enable_clock(&RCC_APB2ENR, IOPCEN);
- /* Select PLL as SYSCLK source. */
- rcc_set_sysclk_source(SW_SYSCLKSEL_PLLCLK);
}
void gpio_setup(void)
{
- /* Enable GPIOC clock. */
- rcc_peripheral_enable_clock(&RCC_APB2ENR, IOPCEN);
-
/* Set GPIO12 (in GPIO port C) to 'output push-pull'. */
gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_PUSHPULL, GPIO12);