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-rw-r--r--examples/mb525/fancyblink/fancyblink.c22
-rw-r--r--examples/mb525/pwmleds/pwmleds.c19
2 files changed, 4 insertions, 37 deletions
diff --git a/examples/mb525/fancyblink/fancyblink.c b/examples/mb525/fancyblink/fancyblink.c
index f3e7c9b..c10715e 100644
--- a/examples/mb525/fancyblink/fancyblink.c
+++ b/examples/mb525/fancyblink/fancyblink.c
@@ -21,33 +21,17 @@
#include <libopenstm32/rcc.h>
#include <libopenstm32/gpio.h>
-/* Set STM32 to 72 MHz. */
void clock_setup(void)
{
- /* Select HSI as SYSCLK source. */
- rcc_set_sysclk_source(SW_SYSCLKSEL_HSICLK);
+ rcc_clock_setup_in_hse_8mhz_out_72mhz();
- /* Set the PLL multiplication factor to 9. */
- rcc_set_pll_multiplication_factor(PLLMUL_PLL_CLK_MUL9);
-
- /* Select HSI/2 as PLL source. */
- rcc_set_pll_source(PLLSRC_HSI_CLK_DIV2);
-
- rcc_set_pllxtpre(PLLXTPRE_HSE_CLK_DIV2);
-
- /* Enable PLL oscillator and wait for it to stabilize. */
- rcc_osc_on(PLL);
- rcc_wait_for_osc_ready(PLL);
+ /* Enable GPIOC clock. */
+ rcc_peripheral_enable_clock(&RCC_APB2ENR, IOPCEN);
- /* Select PLL as SYSCLK source. */
- rcc_set_sysclk_source(SW_SYSCLKSEL_PLLCLK);
}
void gpio_setup(void)
{
- /* Enable GPIOC clock. */
- rcc_peripheral_enable_clock(&RCC_APB2ENR, IOPCEN);
-
/* Set GPIO6 (in GPIO port C) to 'output push-pull'. */
gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_PUSHPULL, GPIO6 | GPIO7 | GPIO8 | GPIO9);
diff --git a/examples/mb525/pwmleds/pwmleds.c b/examples/mb525/pwmleds/pwmleds.c
index 2bff5a4..4502d11 100644
--- a/examples/mb525/pwmleds/pwmleds.c
+++ b/examples/mb525/pwmleds/pwmleds.c
@@ -236,26 +236,9 @@ static const u16 gamma_table_3_0[] = {
};
#endif
-/* Set STM32 to 72 MHz. */
void clock_setup(void)
{
- /* Select HSI as SYSCLK source. */
- rcc_set_sysclk_source(SW_SYSCLKSEL_HSICLK);
-
- /* Set the PLL multiplication factor to 9. */
- rcc_set_pll_multiplication_factor(PLLMUL_PLL_CLK_MUL9);
-
- /* Select HSI/2 as PLL source. */
- rcc_set_pll_source(PLLSRC_HSI_CLK_DIV2);
-
- rcc_set_pllxtpre(PLLXTPRE_HSE_CLK_DIV2);
-
- /* Enable PLL oscillator and wait for it to stabilize. */
- rcc_osc_on(PLL);
- rcc_wait_for_osc_ready(PLL);
-
- /* Select PLL as SYSCLK source. */
- rcc_set_sysclk_source(SW_SYSCLKSEL_PLLCLK);
+ rcc_clock_setup_in_hse_8mhz_out_72mhz();
/* Enable TIM3 clock. */
rcc_peripheral_enable_clock(&RCC_APB1ENR, TIM3EN);