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-rw-r--r--examples/stm32/lisa-m/fancyblink/fancyblink.c2
-rw-r--r--examples/stm32/stm32-h103/exti_both/exti_both.c2
-rw-r--r--examples/stm32/stm32-h103/led_stripe/Makefile23
-rw-r--r--examples/stm32/stm32-h103/led_stripe/led_stripe.c234
-rw-r--r--examples/stm32/stm32-h103/led_stripe/led_stripe.ld31
-rw-r--r--examples/stm32/stm32-h103/usart/usart.c42
-rw-r--r--include/libopencm3/stm32/rcc.h7
-rw-r--r--lib/stm32/rcc.c124
-rw-r--r--lib/stm32/usart.c19
9 files changed, 453 insertions, 31 deletions
diff --git a/examples/stm32/lisa-m/fancyblink/fancyblink.c b/examples/stm32/lisa-m/fancyblink/fancyblink.c
index efada62..5987bdf 100644
--- a/examples/stm32/lisa-m/fancyblink/fancyblink.c
+++ b/examples/stm32/lisa-m/fancyblink/fancyblink.c
@@ -24,7 +24,7 @@
/* Set STM32 to 72 MHz. */
void clock_setup(void)
{
- rcc_clock_setup_in_hse_16mhz_out_72mhz();
+ rcc_clock_setup_in_hse_12mhz_out_72mhz();
/* Enable GPIOC clock. */
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPBEN);
diff --git a/examples/stm32/stm32-h103/exti_both/exti_both.c b/examples/stm32/stm32-h103/exti_both/exti_both.c
index da4c5b6..edfc676 100644
--- a/examples/stm32/stm32-h103/exti_both/exti_both.c
+++ b/examples/stm32/stm32-h103/exti_both/exti_both.c
@@ -53,7 +53,7 @@ void exti_setup(void)
/* Enable EXTI0 interrupt */
nvic_enable_irq(NVIC_EXTI0_IRQ);
- /* Set GPIO0 (in GPIO port A) to 'input open-drain'. */
+ /* Set GPIO0 (in GPIO port A) to 'input float'. */
gpio_set_mode(GPIOA, GPIO_MODE_INPUT,
GPIO_CNF_INPUT_FLOAT, GPIO0);
diff --git a/examples/stm32/stm32-h103/led_stripe/Makefile b/examples/stm32/stm32-h103/led_stripe/Makefile
new file mode 100644
index 0000000..60fd1ef
--- /dev/null
+++ b/examples/stm32/stm32-h103/led_stripe/Makefile
@@ -0,0 +1,23 @@
+##
+## This file is part of the libopencm3 project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+##
+## This program is free software: you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation, either version 3 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program. If not, see <http://www.gnu.org/licenses/>.
+##
+
+BINARY = led_stripe
+
+include ../../Makefile.include
+
diff --git a/examples/stm32/stm32-h103/led_stripe/led_stripe.c b/examples/stm32/stm32-h103/led_stripe/led_stripe.c
new file mode 100644
index 0000000..9cf9d4f
--- /dev/null
+++ b/examples/stm32/stm32-h103/led_stripe/led_stripe.c
@@ -0,0 +1,234 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2011 Piotr Esden-Tempski <piotr@esden.net>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/*
+ * This example is implementing the protocol of ZJ168 addressable led
+ * strips. These strips use the LPD6803 controller. You may be able to
+ * find the datasheet here:
+ * http://www.adafruit.com/datasheets/LPD6803.pdf
+ */
+
+#include <stdlib.h>
+
+#include <libopencm3/stm32/rcc.h>
+#include <libopencm3/stm32/gpio.h>
+
+#define SPI_BANK GPIOB
+#define SCLK_PIN GPIO13
+#define MOSI_PIN GPIO15
+
+#define SMALL_DELAY_VALUE 0
+
+#define COLOR_COUNT 50
+
+#define SCLK(VAL) \
+ if (VAL) { \
+ gpio_set(SPI_BANK, SCLK_PIN); \
+ } else { \
+ gpio_clear(SPI_BANK, SCLK_PIN); \
+ }
+
+#define MOSI(VAL) \
+ if (VAL) { \
+ gpio_set(SPI_BANK, MOSI_PIN); \
+ } else { \
+ gpio_clear(SPI_BANK, MOSI_PIN); \
+ }
+
+#define SMALL_DELAY() { \
+ int j; \
+ for (j = 0; j < SMALL_DELAY_VALUE; j++) \
+ __asm__("nop"); \
+ }
+
+struct color {
+ u8 r;
+ u8 g;
+ u8 b;
+};
+
+/* Set STM32 to 72 MHz. */
+void clock_setup(void)
+{
+ rcc_clock_setup_in_hse_8mhz_out_72mhz();
+
+ /* Enable GPIOC clock. */
+ rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN);
+ rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPBEN);
+
+}
+
+void gpio_setup(void)
+{
+ /* Set GPIO12 (in GPIO port C) to 'output push-pull'. */
+ gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ,
+ GPIO_CNF_OUTPUT_PUSHPULL, GPIO12);
+ gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ,
+ GPIO_CNF_OUTPUT_PUSHPULL, GPIO13);
+ gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ,
+ GPIO_CNF_OUTPUT_PUSHPULL, GPIO15);
+}
+
+void send_colors(struct color *colors, int count) {
+ int i, k;
+
+ /* initialize spi pins */
+ SCLK(0);
+ MOSI(0);
+
+ /* start frame */
+ for (i=0; i<32; i++) {
+ SCLK(1);
+ SMALL_DELAY();
+ SCLK(0);
+ SMALL_DELAY();
+ }
+
+ /* color cell output */
+ for (k = 0; k < count; k++) {
+ /* Start bit */
+ MOSI(1);
+ SCLK(1);
+ SMALL_DELAY();
+ SCLK(0);
+ SMALL_DELAY();
+
+ /* Blue */
+ for (i=0; i<5; i++) {
+ MOSI(((colors[k].b & ((1 << 4) >> i)) != 0));
+ SCLK(1);
+ SMALL_DELAY();
+ SCLK(0);
+ SMALL_DELAY();
+ }
+ /* Red */
+ for (i=0; i<5; i++) {
+ MOSI(((colors[k].r & ((1 << 4) >> i)) != 0));
+ SCLK(1);
+ SMALL_DELAY();
+ SCLK(0);
+ SMALL_DELAY();
+ }
+ /* Green */
+ for (i=0; i<5; i++) {
+ MOSI(((colors[k].g & ((1 << 4) >> i)) != 0));
+ SCLK(1);
+ SMALL_DELAY();
+ SCLK(0);
+ SMALL_DELAY();
+ }
+ }
+
+ /* End frame */
+ MOSI(0);
+ for (k=0; k < count; k++) {
+ SCLK(1);
+ SMALL_DELAY();
+ SCLK(0);
+ SMALL_DELAY();
+ }
+}
+
+void reset_colors(struct color *colors, int count) {
+ int i;
+
+ for (i=0; i<count; i++) {
+ colors[i].r = 0;
+ colors[i].g = 0;
+ colors[i].b = 0;
+ }
+}
+
+void init_colors(struct color *colors, int count) {
+
+ colors[0].r = 0x1F;
+ colors[0].g = 0;
+ colors[0].b = 0;
+ colors[1].r = 0;
+ colors[1].g = 0x1F;
+ colors[1].b = 0;
+ colors[2].r = 0;
+ colors[2].g = 0;
+ colors[2].b = 0x1F;
+
+ count = count;
+}
+
+void step_colors(struct color *colors, int count) {
+ int i;
+ struct color tmp_color1;
+ struct color tmp_color2;
+
+/* random blinking */
+/*
+ for (i=0; i<count; i++) {
+ colors[i].r = rand()&0x01;
+ colors[i].g = rand()&0x01;
+ colors[i].b = rand()&0x01;
+ }
+*/
+ /* generate next colors */
+
+ tmp_color1.r = colors[0].r;
+ tmp_color1.g = colors[0].g;
+ tmp_color1.b = colors[0].b;
+ colors[0].r = colors[count-1].r;
+ colors[0].g = colors[count-1].g;
+ colors[0].b = colors[count-1].b;
+ for(i=1; i<count; i++) {
+ tmp_color2.r = colors[i].r;
+ tmp_color2.g = colors[i].g;
+ tmp_color2.b = colors[i].b;
+ colors[i].r = tmp_color1.r;
+ colors[i].g = tmp_color1.g;
+ colors[i].b = tmp_color1.b;
+ tmp_color1.r = tmp_color2.r;
+ tmp_color1.g = tmp_color2.g;
+ tmp_color1.b = tmp_color2.b;
+ }
+
+}
+
+int main(void)
+{
+ int i;
+
+ struct color colors[COLOR_COUNT];
+
+ clock_setup();
+ gpio_setup();
+
+ reset_colors(colors, COLOR_COUNT);
+ init_colors(colors, COLOR_COUNT);
+
+ while (1) {
+ gpio_toggle(GPIOC, GPIO12); /* LED on/off */
+
+ send_colors(colors, COLOR_COUNT);
+
+ step_colors(colors, COLOR_COUNT);
+
+ /* Wait a little */
+ for (i = 0; i < 1000000; i++) /* Wait a bit. */
+ __asm__("nop");
+
+ }
+
+ return 0;
+}
diff --git a/examples/stm32/stm32-h103/led_stripe/led_stripe.ld b/examples/stm32/stm32-h103/led_stripe/led_stripe.ld
new file mode 100644
index 0000000..7ea2b92
--- /dev/null
+++ b/examples/stm32/stm32-h103/led_stripe/led_stripe.ld
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Linker script for Olimex STM32-H103 (STM32F103RBT6, 128K flash, 20K RAM). */
+
+/* Define memory regions. */
+MEMORY
+{
+ rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K
+}
+
+/* Include the common ld script. */
+INCLUDE libopencm3_stm32.ld
+
diff --git a/examples/stm32/stm32-h103/usart/usart.c b/examples/stm32/stm32-h103/usart/usart.c
index 487ee84..9692d61 100644
--- a/examples/stm32/stm32-h103/usart/usart.c
+++ b/examples/stm32/stm32-h103/usart/usart.c
@@ -26,15 +26,45 @@ void clock_setup(void)
rcc_clock_setup_in_hse_8mhz_out_72mhz();
/* Enable GPIOC clock. */
- rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN);
+ rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | RCC_APB2ENR_IOPCEN);
/* Enable clocks for GPIO port B (for GPIO_USART3_TX) and USART3. */
- rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPBEN);
- rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_USART3EN);
+ rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_USART1EN);
+ rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_USART2EN | RCC_APB1ENR_USART3EN);
}
void usart_setup(void)
{
+ /* Setup GPIO pin GPIO_USART1_TX. */
+ gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ,
+ GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_USART1_TX);
+
+ /* Setup UART parameters. */
+ usart_set_baudrate(USART1, 38400);
+ usart_set_databits(USART1, 8);
+ usart_set_stopbits(USART1, USART_STOPBITS_1);
+ usart_set_mode(USART1, USART_MODE_TX);
+ usart_set_parity(USART1, USART_PARITY_NONE);
+ usart_set_flow_control(USART1, USART_FLOWCONTROL_NONE);
+
+ /* Finally enable the USART. */
+ usart_enable(USART1);
+
+ /* Setup GPIO pin GPIO_USART2_TX. */
+ gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ,
+ GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_USART2_TX);
+
+ /* Setup UART parameters. */
+ usart_set_baudrate(USART2, 38400);
+ usart_set_databits(USART2, 8);
+ usart_set_stopbits(USART2, USART_STOPBITS_1);
+ usart_set_mode(USART2, USART_MODE_TX);
+ usart_set_parity(USART2, USART_PARITY_NONE);
+ usart_set_flow_control(USART2, USART_FLOWCONTROL_NONE);
+
+ /* Finally enable the USART. */
+ usart_enable(USART2);
+
/* Setup GPIO pin GPIO_USART3_TX/GPIO10 on GPIO port B for transmit. */
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_USART3_TX);
@@ -69,9 +99,15 @@ int main(void)
/* Blink the LED (PC12) on the board with every transmitted byte. */
while (1) {
gpio_toggle(GPIOC, GPIO12); /* LED on/off */
+ usart_send_blocking(USART1, c + '0'); /* USART1: Send byte. */
+ usart_send_blocking(USART2, c + '0'); /* USART2: Send byte. */
usart_send_blocking(USART3, c + '0'); /* USART3: Send byte. */
c = (c == 9) ? 0 : c + 1; /* Increment c. */
if ((j++ % 80) == 0) { /* Newline after line full. */
+ usart_send_blocking(USART1, '\r');
+ usart_send_blocking(USART1, '\n');
+ usart_send_blocking(USART2, '\r');
+ usart_send_blocking(USART2, '\n');
usart_send_blocking(USART3, '\r');
usart_send_blocking(USART3, '\n');
}
diff --git a/include/libopencm3/stm32/rcc.h b/include/libopencm3/stm32/rcc.h
index a618439..1072445 100644
--- a/include/libopencm3/stm32/rcc.h
+++ b/include/libopencm3/stm32/rcc.h
@@ -369,6 +369,10 @@
#define RCC_CFGR2_PREDIV2_DIV15 0xe
#define RCC_CFGR2_PREDIV2_DIV16 0xf
+/* --- Variable definitions ------------------------------------------------ */
+extern u32 rcc_ppre1_frequency;
+extern u32 rcc_ppre2_frequency;
+
/* --- Function prototypes ------------------------------------------------- */
typedef enum {
@@ -404,8 +408,9 @@ void rcc_set_usbpre(u32 usbpre);
u32 rcc_get_system_clock_source(int i);
void rcc_clock_setup_in_hsi_out_64mhz(void);
void rcc_clock_setup_in_hsi_out_48mhz(void);
-void rcc_clock_setup_in_hse_8mhz_out_72mhz(void);
void rcc_clock_setup_in_hse_8mhz_out_24mhz(void);
+void rcc_clock_setup_in_hse_8mhz_out_72mhz(void);
+void rcc_clock_setup_in_hse_12mhz_out_72mhz(void);
void rcc_clock_setup_in_hse_16mhz_out_72mhz(void);
void rcc_backupdomain_reset(void);
diff --git a/lib/stm32/rcc.c b/lib/stm32/rcc.c
index f429ff4..f646168 100644
--- a/lib/stm32/rcc.c
+++ b/lib/stm32/rcc.c
@@ -22,6 +22,10 @@
#include <libopencm3/stm32/rcc.h>
#include <libopencm3/stm32/flash.h>
+/* Set the default ppre1 and ppre2 peripheral clock frequencies after reset */
+u32 rcc_ppre1_frequency = 8000000;
+u32 rcc_ppre2_frequency = 8000000;
+
void rcc_osc_ready_int_clear(osc_t osc)
{
switch (osc) {
@@ -350,10 +354,10 @@ void rcc_clock_setup_in_hsi_out_64mhz(void)
* Set prescalers for AHB, ADC, ABP1, ABP2.
* Do this before touching the PLL (TODO: why?).
*/
- rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Max. 72MHz */
- rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV8); /* Max. 14MHz */
- rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Max. 36MHz */
- rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Max. 72MHz */
+ rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 64MHz Max. 72MHz */
+ rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV8); /* Set. 8MHz Max. 14MHz */
+ rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 32MHz Max. 36MHz */
+ rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 64MHz Max. 72MHz */
/*
* Sysclk is running with 64MHz -> 2 waitstates.
@@ -378,6 +382,10 @@ void rcc_clock_setup_in_hsi_out_64mhz(void)
/* Select PLL as SYSCLK source. */
rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK);
+
+ /* Set the peripheral clock frequencies used */
+ rcc_ppre1_frequency = 32000000;
+ rcc_ppre2_frequency = 64000000;
}
void rcc_clock_setup_in_hsi_out_48mhz(void)
@@ -393,11 +401,11 @@ void rcc_clock_setup_in_hsi_out_48mhz(void)
* Set prescalers for AHB, ADC, ABP1, ABP2.
* Do this before touching the PLL (TODO: why?).
*/
- rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Max. 72MHz */
- rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV8); /* Max. 14MHz */
- rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Max. 36MHz */
- rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Max. 72MHz */
- rcc_set_usbpre(RCC_CFGR_USBPRE_PLL_CLK_NODIV); /* 48 MHz */
+ rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 48MHz Max. 72MHz */
+ rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV8); /* Set. 6MHz Max. 14MHz */
+ rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 24MHz Max. 36MHz */
+ rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 48MHz Max. 72MHz */
+ rcc_set_usbpre(RCC_CFGR_USBPRE_PLL_CLK_NODIV); /* Set. 48MHz Max. 48MHz */
/*
* Sysclk runs with 48MHz -> 1 waitstates.
@@ -422,6 +430,10 @@ void rcc_clock_setup_in_hsi_out_48mhz(void)
/* Select PLL as SYSCLK source. */
rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK);
+
+ /* Set the peripheral clock frequencies used */
+ rcc_ppre1_frequency = 24000000;
+ rcc_ppre2_frequency = 48000000;
}
void rcc_clock_setup_in_hse_8mhz_out_24mhz(void)
@@ -442,10 +454,10 @@ void rcc_clock_setup_in_hse_8mhz_out_24mhz(void)
* Set prescalers for AHB, ADC, ABP1, ABP2.
* Do this before touching the PLL (TODO: why?).
*/
- rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Max. 72MHz */
- rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV2); /* Max. 14MHz */
- rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_NODIV); /* Max. 36MHz */
- rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Max. 72MHz */
+ rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 24MHz Max. 72MHz */
+ rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV2); /* Set. 12MHz Max. 14MHz */
+ rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_NODIV); /* Set. 24MHz Max. 36MHz */
+ rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 24MHz Max. 72MHz */
/*
* Sysclk runs with 24MHz -> 0 waitstates.
@@ -476,6 +488,10 @@ void rcc_clock_setup_in_hse_8mhz_out_24mhz(void)
/* Select PLL as SYSCLK source. */
rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK);
+
+ /* Set the peripheral clock frequencies used */
+ rcc_ppre1_frequency = 24000000;
+ rcc_ppre2_frequency = 24000000;
}
void rcc_clock_setup_in_hse_8mhz_out_72mhz(void)
{
@@ -495,10 +511,10 @@ void rcc_clock_setup_in_hse_8mhz_out_72mhz(void)
* Set prescalers for AHB, ADC, ABP1, ABP2.
* Do this before touching the PLL (TODO: why?).
*/
- rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Max. 72MHz */
- rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV8); /* Max. 14MHz */
- rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Max. 36MHz */
- rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Max. 72MHz */
+ rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 72MHz Max. 72MHz */
+ rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV8); /* Set. 9MHz Max. 14MHz */
+ rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 36MHz Max. 36MHz */
+ rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 72MHz Max. 72MHz */
/*
* Sysclk runs with 72MHz -> 2 waitstates.
@@ -529,6 +545,68 @@ void rcc_clock_setup_in_hse_8mhz_out_72mhz(void)
/* Select PLL as SYSCLK source. */
rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK);
+
+ /* Set the peripheral clock frequencies used */
+ rcc_ppre1_frequency = 36000000;
+ rcc_ppre2_frequency = 72000000;
+}
+
+void rcc_clock_setup_in_hse_12mhz_out_72mhz(void)
+{
+ /* Enable internal high-speed oscillator. */
+ rcc_osc_on(HSI);
+ rcc_wait_for_osc_ready(HSI);
+
+ /* Select HSI as SYSCLK source. */
+ rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK);
+
+ /* Enable external high-speed oscillator 16MHz. */
+ rcc_osc_on(HSE);
+ rcc_wait_for_osc_ready(HSE);
+ rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSECLK);
+
+ /*
+ * Set prescalers for AHB, ADC, ABP1, ABP2.
+ * Do this before touching the PLL (TODO: why?).
+ */
+ rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 72MHz Max. 72MHz */
+ rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV6); /* Set. 12MHz Max. 14MHz */
+ rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 36MHz Max. 36MHz */
+ rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 72MHz Max. 72MHz */
+
+ /*
+ * Sysclk runs with 72MHz -> 2 waitstates.
+ * 0WS from 0-24MHz
+ * 1WS from 24-48MHz
+ * 2WS from 48-72MHz
+ */
+ flash_set_ws(FLASH_LATENCY_2WS);
+
+ /*
+ * Set the PLL multiplication factor to 9.
+ * 12MHz (external) * 6 (multiplier) / 1 (PLLXTPRE_HSE_CLK) = 72MHz
+ */
+ rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_PLL_CLK_MUL6);
+
+ /* Select HSI as PLL source. */
+ rcc_set_pll_source(RCC_CFGR_PLLSRC_HSE_CLK);
+
+ /*
+ * Divide external frequency by 2 before entering PLL
+ * (only valid/needed for HSE).
+ */
+ rcc_set_pllxtpre(RCC_CFGR_PLLXTPRE_HSE_CLK);
+
+ /* Enable PLL oscillator and wait for it to stabilize. */
+ rcc_osc_on(PLL);
+ rcc_wait_for_osc_ready(PLL);
+
+ /* Select PLL as SYSCLK source. */
+ rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK);
+
+ /* Set the peripheral clock frequencies used */
+ rcc_ppre1_frequency = 36000000;
+ rcc_ppre2_frequency = 72000000;
}
void rcc_clock_setup_in_hse_16mhz_out_72mhz(void)
@@ -549,10 +627,10 @@ void rcc_clock_setup_in_hse_16mhz_out_72mhz(void)
* Set prescalers for AHB, ADC, ABP1, ABP2.
* Do this before touching the PLL (TODO: why?).
*/
- rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Max. 72MHz */
- rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV6); /* Max. 14MHz */
- rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Max. 36MHz */
- rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Max. 72MHz */
+ rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 72MHz Max. 72MHz */
+ rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV6); /* Set. 12MHz Max. 14MHz */
+ rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 36MHz Max. 36MHz */
+ rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 72MHz Max. 72MHz */
/*
* Sysclk runs with 72MHz -> 2 waitstates.
@@ -583,6 +661,10 @@ void rcc_clock_setup_in_hse_16mhz_out_72mhz(void)
/* Select PLL as SYSCLK source. */
rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK);
+
+ /* Set the peripheral clock frequencies used */
+ rcc_ppre1_frequency = 36000000;
+ rcc_ppre2_frequency = 72000000;
}
void rcc_backupdomain_reset(void)
diff --git a/lib/stm32/usart.c b/lib/stm32/usart.c
index f644776..ead0ef7 100644
--- a/lib/stm32/usart.c
+++ b/lib/stm32/usart.c
@@ -17,14 +17,25 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
+#include <libopencm3/stm32/rcc.h>
+
#include <libopencm3/stm32/usart.h>
void usart_set_baudrate(u32 usart, u32 baud)
{
- u32 clock = 72000000; /* FIXME: Don't hardcode this clock! */
-
- /* TODO: Document and explain calculation. */
- USART_BRR(usart) = (u16)((clock << 4) / (baud * 16));
+ u32 clock = rcc_ppre1_frequency;
+
+ if (usart == USART1) {
+ clock = rcc_ppre2_frequency;
+ }
+
+ /* yes it is as simple as that. The reference manual is
+ * talking about factional calculation but it seems to be only
+ * marketting bable to sound awesome. It is nothing else but a
+ * simple divider to generate the correct baudrate. >_< If I
+ * am wrong feel free to correct me on that. :) (esden)
+ */
+ USART_BRR(usart) = clock/baud;
}
void usart_set_databits(u32 usart, u32 bits)