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-rw-r--r--doc/stm32f1/Doxyfile10
-rw-r--r--doc/stm32f1/Doxyfile_latex7
-rw-r--r--doc/stm32f1/DoxygenLayout_stm32f1.xml2
-rw-r--r--doc/stm32f2/Doxyfile8
-rw-r--r--doc/stm32f2/Doxyfile_latex7
-rw-r--r--doc/stm32f4/Doxyfile6
-rw-r--r--doc/stm32f4/Doxyfile_latex7
-rw-r--r--doc/stm32l1/Doxyfile25
-rw-r--r--doc/stm32l1/Doxyfile_latex14
-rw-r--r--include/libopencm3/stm32/common/spi_common_all.h399
-rw-r--r--include/libopencm3/stm32/common/spi_common_f24.h50
-rw-r--r--include/libopencm3/stm32/f1/spi.h40
-rw-r--r--include/libopencm3/stm32/f2/spi.h43
-rw-r--r--include/libopencm3/stm32/f4/spi.h43
-rw-r--r--include/libopencm3/stm32/l1/memorymap.h5
-rw-r--r--include/libopencm3/stm32/l1/spi.h40
-rw-r--r--include/libopencm3/stm32/rcc.h31
-rw-r--r--include/libopencm3/stm32/spi.h405
-rw-r--r--lib/stm32/common/spi_common_all.c (renamed from lib/stm32/spi.c)18
-rw-r--r--lib/stm32/f1/Makefile4
-rw-r--r--lib/stm32/f1/spi.c28
-rw-r--r--lib/stm32/f2/Makefile4
-rw-r--r--lib/stm32/f2/spi.c28
-rw-r--r--lib/stm32/f4/Makefile4
-rw-r--r--lib/stm32/f4/spi.c28
-rw-r--r--lib/stm32/l1/Makefile4
-rw-r--r--lib/stm32/l1/spi.c28
27 files changed, 790 insertions, 498 deletions
diff --git a/doc/stm32f1/Doxyfile b/doc/stm32f1/Doxyfile
index ae83259..17a89c2 100644
--- a/doc/stm32f1/Doxyfile
+++ b/doc/stm32f1/Doxyfile
@@ -16,16 +16,16 @@
WARN_LOGFILE = doxygen_stm32f1.log
INPUT = ../../include/libopencm3/license.dox \
- ../../include/libopencm3/stm32/f1 \
- ../../include/libopencm3/stm32/common/gpio_common_all.h
+ ../../include/libopencm3/stm32/f1 \
+ ../../include/libopencm3/stm32/common
INPUT += ../../lib/stm32/f1 \
- ../../lib/stm32/common/gpio_common_all.c
+ ../../lib/stm32/common
EXCLUDE = ../../include/libopencm3/stm32/f1/usb.h \
- ../../include/libopencm3/stm32/f1/usb_desc.h
+ ../../include/libopencm3/stm32/f1/usb_desc.h
-EXCLUDE_PATTERNS = *_common_f24.h *_common_f24.c
+EXCLUDE_PATTERNS = *_common_f24.h *_common_f24.c
LAYOUT_FILE = DoxygenLayout_stm32f1.xml
diff --git a/doc/stm32f1/Doxyfile_latex b/doc/stm32f1/Doxyfile_latex
index 217b6f9..97c32e7 100644
--- a/doc/stm32f1/Doxyfile_latex
+++ b/doc/stm32f1/Doxyfile_latex
@@ -18,9 +18,10 @@ WARN_LOGFILE = doxygen_stm32f1_latex.log
INPUT = ../../include/libopencm3/docmain.dox \
../../include/libopencm3/license.dox \
../../include/libopencm3/stm32/f1 \
- ../../include/libopencm3/stm32/common \
- ../../lib/stm32/f1 \
- ../../lib/stm32/common
+ ../../include/libopencm3/stm32/common
+
+INPUT += ../../lib/stm32/f1 \
+ ../../lib/stm32/common
EXCLUDE = ../../include/libopencm3/stm32/f1/doc-stm32f1.h \
../../include/libopencm3/stm32/f1/usb.h \
diff --git a/doc/stm32f1/DoxygenLayout_stm32f1.xml b/doc/stm32f1/DoxygenLayout_stm32f1.xml
index c3dfdf2..3e435b3 100644
--- a/doc/stm32f1/DoxygenLayout_stm32f1.xml
+++ b/doc/stm32f1/DoxygenLayout_stm32f1.xml
@@ -5,7 +5,7 @@
<tab type="pages" visible="yes" title="General Information" intro=""/>
<tab type="user" visible="yes" url="../../html/index.html" title="Back to Top" intro=""/>
<tab type="user" visible="yes" url="../../cm3/html/modules.html" title="CM3 Core" intro=""/>
- <tab type="modules" visible="yes" title="STMF1" intro=""/>
+ <tab type="modules" visible="yes" title="STM32F1" intro=""/>
<tab type="user" visible="yes" url="../../stm32f2/html/modules.html" title="STM32F2" intro=""/>
<tab type="user" visible="yes" url="../../stm32f4/html/modules.html" title="STM32F4" intro=""/>
<tab type="user" visible="yes" url="../../stm32l1/html/modules.html" title="STM32L1" intro=""/>
diff --git a/doc/stm32f2/Doxyfile b/doc/stm32f2/Doxyfile
index ff5765b..e230316 100644
--- a/doc/stm32f2/Doxyfile
+++ b/doc/stm32f2/Doxyfile
@@ -17,15 +17,15 @@ WARN_LOGFILE = doxygen_stm32f2.log
INPUT = ../../include/libopencm3/license.dox \
../../include/libopencm3/stm32/f2 \
- ../../include/libopencm3/stm32/common/gpio_common_all.h \
- ../../include/libopencm3/stm32/common/gpio_common_f24.h
+ ../../include/libopencm3/stm32/common
INPUT += ../../lib/stm32/f2 \
- ../../lib/stm32/common/gpio_common_all.c \
- ../../lib/stm32/common/gpio_common_f24.c
+ ../../lib/stm32/common
EXCLUDE =
+EXCLUDE_PATTERNS =
+
LAYOUT_FILE = DoxygenLayout_stm32f2.xml
TAGFILES = ../cm3/cm3.tag=../../cm3/html
diff --git a/doc/stm32f2/Doxyfile_latex b/doc/stm32f2/Doxyfile_latex
index 29bdc95..dad6848 100644
--- a/doc/stm32f2/Doxyfile_latex
+++ b/doc/stm32f2/Doxyfile_latex
@@ -18,12 +18,15 @@ WARN_LOGFILE = doxygen_stm32f2_latex.log
INPUT = ../../include/libopencm3/docmain.dox \
../../include/libopencm3/license.dox \
../../include/libopencm3/stm32/f2 \
- ../../include/libopencm3/stm32/common \
- ../../lib/stm32/f2 \
+ ../../include/libopencm3/stm32/common
+
+INPUT += ../../lib/stm32/f2 \
../../lib/stm32/common
EXCLUDE = ../../include/libopencm3/stm32/f2/doc-stm32f2.h
+EXCLUDE_PATTERNS =
+
LAYOUT_FILE = DoxygenLayout_stm32f2.xml
GENERATE_HTML = NO
diff --git a/doc/stm32f4/Doxyfile b/doc/stm32f4/Doxyfile
index 6eff41c..9b3ba9b 100644
--- a/doc/stm32f4/Doxyfile
+++ b/doc/stm32f4/Doxyfile
@@ -17,12 +17,10 @@ WARN_LOGFILE = doxygen_stm32f4.log
INPUT = ../../include/libopencm3/license.dox \
../../include/libopencm3/stm32/f4 \
- ../../include/libopencm3/stm32/common/gpio_common_all.h \
- ../../include/libopencm3/stm32/common/gpio_common_f24.h
+ ../../include/libopencm3/stm32/common
INPUT += ../../lib/stm32/f4 \
- ../../lib/stm32/common/gpio_common_all.c \
- ../../lib/stm32/common/gpio_common_f24.c
+ ../../lib/stm32/common
EXCLUDE =
diff --git a/doc/stm32f4/Doxyfile_latex b/doc/stm32f4/Doxyfile_latex
index 6f62b21..e93248c 100644
--- a/doc/stm32f4/Doxyfile_latex
+++ b/doc/stm32f4/Doxyfile_latex
@@ -18,12 +18,15 @@ WARN_LOGFILE = doxygen_stm32f4_latex.log
INPUT = ../../include/libopencm3/docmain.dox \
../../include/libopencm3/license.dox \
../../include/libopencm3/stm32/f4 \
- ../../include/libopencm3/stm32/common \
- ../../lib/stm32/f4 \
+ ../../include/libopencm3/stm32/common
+
+INPUT += ../../lib/stm32/f4 \
../../lib/stm32/common
EXCLUDE = ../../include/libopencm3/stm32/f4/doc-stm32f4.h
+EXCLUDE_PATTERNS =
+
LAYOUT_FILE = DoxygenLayout_stm32f4.xml
GENERATE_HTML = NO
diff --git a/doc/stm32l1/Doxyfile b/doc/stm32l1/Doxyfile
index deca18b..566bb01 100644
--- a/doc/stm32l1/Doxyfile
+++ b/doc/stm32l1/Doxyfile
@@ -1,13 +1,13 @@
-# HTML Documentation for STM32F1 code level
+# HTML Documentation for STM32L1 code level
-# 14 September 2012
+# 15 December 2012
# (C) Ken Sarkies <ksarkies@internode.on.net>
#---------------------------------------------------------------------------
# Common Include File
#---------------------------------------------------------------------------
-@INCLUDE = ../Doxyfile_common
+@INCLUDE = ../Doxyfile_common
#---------------------------------------------------------------------------
# Local settings
@@ -16,18 +16,21 @@
WARN_LOGFILE = doxygen_stm32l1.log
INPUT = ../../include/libopencm3/license.dox \
- ../../include/libopencm3/stm32/l1 \
- ../../include/libopencm3/stm32/common \
- ../../lib/stm32/l1 \
- ../../lib/stm32/common
+ ../../include/libopencm3/stm32/l1 \
+ ../../include/libopencm3/stm32/common
-EXCLUDE =
+INPUT += ../../lib/stm32/l1 \
+ ../../lib/stm32/common
-EXCLUDE_PATTERNS = *_common_f24.h
+EXCLUDE = ../../include/libopencm3/stm32/common/gpio_common_f24.h
-LAYOUT_FILE = DoxygenLayout_stm32l1.xml
+EXCLUDE += ../../lib/stm32/common/gpio_common_f24.c
-TAGFILES = ../cm3/cm3.tag=../../cm3/html \
+EXCLUDE_PATTERNS =
+
+LAYOUT_FILE = DoxygenLayout_stm32l1.xml
+
+TAGFILES = ../cm3/cm3.tag=../../cm3/html
GENERATE_TAGFILE = stm32l1.tag
diff --git a/doc/stm32l1/Doxyfile_latex b/doc/stm32l1/Doxyfile_latex
index 80b5600..51d217f 100644
--- a/doc/stm32l1/Doxyfile_latex
+++ b/doc/stm32l1/Doxyfile_latex
@@ -18,13 +18,17 @@ WARN_LOGFILE = doxygen_stm32l1_latex.log
INPUT = ../../include/libopencm3/docmain.dox \
../../include/libopencm3/license.dox \
../../include/libopencm3/stm32/l1 \
- ../../include/libopencm3/stm32/common \
- ../../lib/stm32/l1 \
- ../../lib/stm32/common
+ ../../include/libopencm3/stm32/common
-EXCLUDE = ../../include/libopencm3/stm32/l1/doc-stm32l1.h
+INPUT += ../../lib/stm32/l1 \
+ ../../lib/stm32/common
-EXCLUDE_PATTERNS = *_common_f24.h
+EXCLUDE = ../../include/libopencm3/stm32/l1/doc-stm32l1.h \
+ ../../include/libopencm3/stm32/common/gpio_common_f24.h
+
+EXCLUDE += ../../lib/stm32/common/gpio_common_f24.c
+
+EXCLUDE_PATTERNS =
LAYOUT_FILE = DoxygenLayout_stm32l1.xml
diff --git a/include/libopencm3/stm32/common/spi_common_all.h b/include/libopencm3/stm32/common/spi_common_all.h
new file mode 100644
index 0000000..57b1465
--- /dev/null
+++ b/include/libopencm3/stm32/common/spi_common_all.h
@@ -0,0 +1,399 @@
+/** @addtogroup spi_defines */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA SPI.H */
+
+#ifndef LIBOPENCM3_SPI_COMMON_ALL_H
+#define LIBOPENCM3_SPI_COMMON_ALL_H
+
+#include <libopencm3/cm3/common.h>
+
+/**@{*/
+
+/* Registers can be accessed as 16bit or 32bit values. */
+
+/* --- Convenience macros -------------------------------------------------- */
+
+/****************************************************************************/
+/** @defgroup spi_reg_base SPI Register base address
+@ingroup spi_defines
+
+@{*/
+#define SPI1 SPI1_BASE
+#define SPI2 SPI2_I2S_BASE
+#define SPI3 SPI3_I2S_BASE
+/**@}*/
+
+/* --- SPI registers ------------------------------------------------------- */
+
+/* Control register 1 (SPIx_CR1) */
+/* Note: Not used in I2S mode. */
+#define SPI_CR1(spi_base) MMIO32(spi_base + 0x00)
+#define SPI1_CR1 SPI_CR1(SPI1_BASE)
+#define SPI2_CR1 SPI_CR1(SPI2_I2S_BASE)
+#define SPI3_CR1 SPI_CR1(SPI3_I2S_BASE)
+
+/* Control register 2 (SPIx_CR2) */
+#define SPI_CR2(spi_base) MMIO32(spi_base + 0x04)
+#define SPI1_CR2 SPI_CR2(SPI1_BASE)
+#define SPI2_CR2 SPI_CR2(SPI2_I2S_BASE)
+#define SPI3_CR2 SPI_CR2(SPI3_I2S_BASE)
+
+/* Status register (SPIx_SR) */
+#define SPI_SR(spi_base) MMIO32(spi_base + 0x08)
+#define SPI1_SR SPI_SR(SPI1_BASE)
+#define SPI2_SR SPI_SR(SPI2_I2S_BASE)
+#define SPI3_SR SPI_SR(SPI3_I2S_BASE)
+
+/* Data register (SPIx_DR) */
+#define SPI_DR(spi_base) MMIO32(spi_base + 0x0c)
+#define SPI1_DR SPI_DR(SPI1_BASE)
+#define SPI2_DR SPI_DR(SPI2_I2S_BASE)
+#define SPI3_DR SPI_DR(SPI3_I2S_BASE)
+
+/* CRC polynomial register (SPIx_CRCPR) */
+/* Note: Not used in I2S mode. */
+#define SPI_CRCPR(spi_base) MMIO32(spi_base + 0x10)
+#define SPI1_CRCPR SPI_CRCPR(SPI1_BASE)
+#define SPI2_CRCPR SPI_CRCPR(SPI2_I2S_BASE)
+#define SPI3_CRCPR SPI_CRCPR(SPI3_I2S_BASE)
+
+/* RX CRC register (SPIx_RXCRCR) */
+/* Note: Not used in I2S mode. */
+#define SPI_RXCRCR(spi_base) MMIO32(spi_base + 0x14)
+#define SPI1_RXCRCR SPI_RXCRCR(SPI1_BASE)
+#define SPI2_RXCRCR SPI_RXCRCR(SPI2_I2S_BASE)
+#define SPI3_RXCRCR SPI_RXCRCR(SPI3_I2S_BASE)
+
+/* TX CRC register (SPIx_RXCRCR) */
+/* Note: Not used in I2S mode. */
+#define SPI_TXCRCR(spi_base) MMIO32(spi_base + 0x18)
+#define SPI1_TXCRCR SPI_TXCRCR(SPI1_BASE)
+#define SPI2_TXCRCR SPI_TXCRCR(SPI2_I2S_BASE)
+#define SPI3_TXCRCR SPI_TXCRCR(SPI3_I2S_BASE)
+
+/* I2S configuration register (SPIx_I2SCFGR) */
+#define SPI_I2SCFGR(spi_base) MMIO32(spi_base + 0x1c)
+#define SPI1_I2SCFGR SPI_I2SCFGR(SPI1_BASE)
+#define SPI2_I2SCFGR SPI_I2SCFGR(SPI2_I2S_BASE)
+#define SPI3_I2SCFGR SPI_I2SCFGR(SPI3_I2S_BASE)
+
+/* I2S prescaler register (SPIx_I2SPR) */
+#define SPI_I2SPR(spi_base) MMIO32(spi_base + 0x20)
+#define SPI1_I2SPR SPI_I2SPR(SPI1_BASE)
+#define SPI2_I2SPR SPI_I2SPR(SPI2_I2S_BASE)
+#define SPI3_I2SPR SPI_I2SPR(SPI3_I2S_BASE)
+
+/* --- SPI_CR1 values ------------------------------------------------------ */
+
+/* Note: None of the CR1 bits are used in I2S mode. */
+
+/* BIDIMODE: Bidirectional data mode enable */
+#define SPI_CR1_BIDIMODE_2LINE_UNIDIR (0 << 15)
+#define SPI_CR1_BIDIMODE_1LINE_BIDIR (1 << 15)
+#define SPI_CR1_BIDIMODE (1 << 15)
+
+/* BIDIOE: Output enable in bidirectional mode */
+#define SPI_CR1_BIDIOE (1 << 14)
+
+/* CRCEN: Hardware CRC calculation enable */
+#define SPI_CR1_CRCEN (1 << 13)
+
+/* CRCNEXT: Transmit CRC next */
+#define SPI_CR1_CRCNEXT (1 << 12)
+
+/* DFF: Data frame format */
+/****************************************************************************/
+/** @defgroup spi_dff SPI data frame format
+@ingroup spi_defines
+
+@{*/
+#define SPI_CR1_DFF_8BIT (0 << 11)
+#define SPI_CR1_DFF_16BIT (1 << 11)
+/**@}*/
+#define SPI_CR1_DFF (1 << 11)
+
+/* RXONLY: Receive only */
+#define SPI_CR1_RXONLY (1 << 10)
+
+/* SSM: Software slave management */
+#define SPI_CR1_SSM (1 << 9)
+
+/* SSI: Internal slave select */
+#define SPI_CR1_SSI (1 << 8)
+
+/* LSBFIRST: Frame format */
+/****************************************************************************/
+/** @defgroup spi_lsbfirst SPI lsb/msb first
+@ingroup spi_defines
+
+@{*/
+#define SPI_CR1_MSBFIRST (0 << 7)
+#define SPI_CR1_LSBFIRST (1 << 7)
+/**@}*/
+
+/* SPE: SPI enable */
+#define SPI_CR1_SPE (1 << 6)
+
+/* BR[2:0]: Baud rate control */
+/****************************************************************************/
+/** @defgroup spi_baudrate SPI peripheral baud rates
+@ingroup spi_defines
+
+@{*/
+#define SPI_CR1_BAUDRATE_FPCLK_DIV_2 (0x00 << 3)
+#define SPI_CR1_BAUDRATE_FPCLK_DIV_4 (0x01 << 3)
+#define SPI_CR1_BAUDRATE_FPCLK_DIV_8 (0x02 << 3)
+#define SPI_CR1_BAUDRATE_FPCLK_DIV_16 (0x03 << 3)
+#define SPI_CR1_BAUDRATE_FPCLK_DIV_32 (0x04 << 3)
+#define SPI_CR1_BAUDRATE_FPCLK_DIV_64 (0x05 << 3)
+#define SPI_CR1_BAUDRATE_FPCLK_DIV_128 (0x06 << 3)
+#define SPI_CR1_BAUDRATE_FPCLK_DIV_256 (0x07 << 3)
+/**@}*/
+/****************************************************************************/
+/** @defgroup spi_br_pre SPI peripheral baud rate prescale values
+@ingroup spi_defines
+
+@{*/
+#define SPI_CR1_BR_FPCLK_DIV_2 0x0
+#define SPI_CR1_BR_FPCLK_DIV_4 0x1
+#define SPI_CR1_BR_FPCLK_DIV_8 0x2
+#define SPI_CR1_BR_FPCLK_DIV_16 0x3
+#define SPI_CR1_BR_FPCLK_DIV_32 0x4
+#define SPI_CR1_BR_FPCLK_DIV_64 0x5
+#define SPI_CR1_BR_FPCLK_DIV_128 0x6
+#define SPI_CR1_BR_FPCLK_DIV_256 0x7
+/**@}*/
+
+/* MSTR: Master selection */
+#define SPI_CR1_MSTR (1 << 2)
+
+/* CPOL: Clock polarity */
+/****************************************************************************/
+/** @defgroup spi_cpol SPI clock polarity
+@ingroup spi_defines
+
+@{*/
+#define SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE (0 << 1)
+#define SPI_CR1_CPOL_CLK_TO_1_WHEN_IDLE (1 << 1)
+/**@}*/
+#define SPI_CR1_CPOL (1 << 1)
+
+/* CPHA: Clock phase */
+/****************************************************************************/
+/** @defgroup spi_cpha SPI clock phase
+@ingroup spi_defines
+
+@{*/
+#define SPI_CR1_CPHA_CLK_TRANSITION_1 (0 << 0)
+#define SPI_CR1_CPHA_CLK_TRANSITION_2 (1 << 0)
+/**@}*/
+#define SPI_CR1_CPHA (1 << 0)
+
+/* --- SPI_CR2 values ------------------------------------------------------ */
+
+/* Bits [15:8]: Reserved. Forced to 0 by hardware. */
+
+/* TXEIE: Tx buffer empty interrupt enable */
+#define SPI_CR2_TXEIE (1 << 7)
+
+/* RXNEIE: Rx buffer not empty interrupt enable */
+#define SPI_CR2_RXNEIE (1 << 6)
+
+/* ERRIE: Error interrupt enable */
+#define SPI_CR2_ERRIE (1 << 5)
+
+/* Bits [4:3]: Reserved. Forced to 0 by hardware. */
+
+/* SSOE: SS output enable */
+/* Note: Not used in I2S mode. */
+#define SPI_CR2_SSOE (1 << 2)
+
+/* TXDMAEN: Tx buffer DMA enable */
+#define SPI_CR2_TXDMAEN (1 << 1)
+
+/* RXDMAEN: Rx buffer DMA enable */
+#define SPI_CR2_RXDMAEN (1 << 0)
+
+/* --- SPI_SR values ------------------------------------------------------- */
+
+/* Bits [15:8]: Reserved. Forced to 0 by hardware. */
+
+/* BSY: Busy flag */
+#define SPI_SR_BSY (1 << 7)
+
+/* OVR: Overrun flag */
+#define SPI_SR_OVR (1 << 6)
+
+/* MODF: Mode fault */
+/* Note: Not used in I2S mode. */
+#define SPI_SR_MODF (1 << 5)
+
+/* CRCERR: CRC error flag */
+/* Note: Not used in I2S mode. */
+#define SPI_SR_CRCERR (1 << 4)
+
+/* UDR: Underrun flag */
+/* Note: Not used in SPI mode. */
+#define SPI_SR_UDR (1 << 3)
+
+/* CHSIDE: Channel side */
+/* Note: Not used in SPI mode. No meaning in PCM mode. */
+#define SPI_SR_CHSIDE (1 << 2)
+
+/* TXE: Transmit buffer empty */
+#define SPI_SR_TXE (1 << 1)
+
+/* RXNE: Receive buffer not empty */
+#define SPI_SR_RXNE (1 << 0)
+
+/* --- SPI_DR values ------------------------------------------------------- */
+
+/* SPI_DR[15:0]: Data Register. */
+
+/* --- SPI_CRCPR values ---------------------------------------------------- */
+
+/* Note: Not used in I2S mode. */
+/* SPI_CRCPR [15:0]: CRC Polynomial Register. */
+
+/* --- SPI_RXCRCR values --------------------------------------------------- */
+
+/* Note: Not used in I2S mode. */
+/* SPI_RXCRCR [15:0]: RX CRC Register. */
+
+/* --- SPI_TXCRCR values --------------------------------------------------- */
+
+/* Note: Not used in I2S mode. */
+/* SPI_TXCRCR [15:0]: TX CRC Register. */
+
+/* --- SPI_I2SCFGR values -------------------------------------------------- */
+
+/* Note: None of these bits are used in SPI mode. */
+
+/* Bits [15:12]: Reserved. Forced to 0 by hardware. */
+
+/* I2SMOD: I2S mode selection */
+#define SPI_I2SCFGR_I2SMOD (1 << 11)
+
+/* I2SE: I2S enable */
+#define SPI_I2SCFGR_I2SE (1 << 10)
+
+/* I2SCFG[9:8]: I2S configuration mode */
+#define SPI_I2SCFGR_I2SCFG_LSB 8
+#define SPI_I2SCFGR_I2SCFG_SLAVE_TRANSMIT 0x0
+#define SPI_I2SCFGR_I2SCFG_SLAVE_RECEIVE 0x1
+#define SPI_I2SCFGR_I2SCFG_MASTER_TRANSMIT 0x2
+#define SPI_I2SCFGR_I2SCFG_MASTER_RECEIVE 0x3
+
+/* PCMSYNC: PCM frame synchronization */
+#define SPI_I2SCFGR_PCMSYNC (1 << 7)
+
+/* Bit 6: Reserved. Forced to 0 by hardware. */
+
+/* I2SSTD[5:4]: I2S standard selection */
+#define SPI_I2SCFGR_I2SSTD_LSB 4
+#define SPI_I2SCFGR_I2SSTD_I2S_PHILLIPS 0x0
+#define SPI_I2SCFGR_I2SSTD_MSB_JUSTIFIED 0x1
+#define SPI_I2SCFGR_I2SSTD_LSB_JUSTIFIED 0x2
+#define SPI_I2SCFGR_I2SSTD_PCM 0x3
+
+/* CKPOL: Steady state clock polarity */
+#define SPI_I2SCFGR_CKPOL (1 << 3)
+
+/* DATLEN[2:1]: Data length to be transferred */
+#define SPI_I2SCFGR_DATLEN_LSB 1
+#define SPI_I2SCFGR_DATLEN_16BIT 0x0
+#define SPI_I2SCFGR_DATLEN_24BIT 0x1
+#define SPI_I2SCFGR_DATLEN_32BIT 0x2
+
+/* CHLEN: Channel length */
+#define SPI_I2SCFGR_CHLEN (1 << 0)
+
+/* --- SPI_I2SPR values ---------------------------------------------------- */
+
+/* Note: None of these bits are used in SPI mode. */
+
+/* Bits [15:10]: Reserved. Forced to 0 by hardware. */
+
+/* MCKOE: Master clock output enable */
+#define SPI_I2SPR_MCKOE (1 << 9)
+
+/* ODD: Odd factor for the prescaler */
+#define SPI_I2SPR_ODD (1 << 8)
+
+/* I2SDIV[7:0]: I2S linear prescaler */
+/* 0 and 1 are forbidden values */
+
+/* --- Function prototypes ------------------------------------------------- */
+
+BEGIN_DECLS
+
+void spi_reset(u32 spi_peripheral);
+int spi_init_master(u32 spi, u32 br, u32 cpol, u32 cpha, u32 dff, u32 lsbfirst);
+void spi_enable(u32 spi);
+void spi_disable(u32 spi);
+void spi_write(u32 spi, u16 data);
+void spi_send(u32 spi, u16 data);
+u16 spi_read(u32 spi);
+u16 spi_xfer(u32 spi, u16 data);
+void spi_set_bidirectional_mode(u32 spi);
+void spi_set_unidirectional_mode(u32 spi);
+void spi_set_bidirectional_receive_only_mode(u32 spi);
+void spi_set_bidirectional_transmit_only_mode(u32 spi);
+void spi_enable_crc(u32 spi);
+void spi_disable_crc(u32 spi);
+void spi_set_next_tx_from_buffer(u32 spi);
+void spi_set_next_tx_from_crc(u32 spi);
+void spi_set_dff_8bit(u32 spi);
+void spi_set_dff_16bit(u32 spi);
+void spi_set_full_duplex_mode(u32 spi);
+void spi_set_receive_only_mode(u32 spi);
+void spi_disable_software_slave_management(u32 spi);
+void spi_enable_software_slave_management(u32 spi);
+void spi_set_nss_high(u32 spi);
+void spi_set_nss_low(u32 spi);
+void spi_send_lsb_first(u32 spi);
+void spi_send_msb_first(u32 spi);
+void spi_set_baudrate_prescaler(u32 spi, u8 baudrate);
+void spi_set_master_mode(u32 spi);
+void spi_set_slave_mode(u32 spi);
+void spi_set_clock_polarity_1(u32 spi);
+void spi_set_clock_polarity_0(u32 spi);
+void spi_set_clock_phase_1(u32 spi);
+void spi_set_clock_phase_0(u32 spi);
+void spi_enable_tx_buffer_empty_interrupt(u32 spi);
+void spi_disable_tx_buffer_empty_interrupt(u32 spi);
+void spi_enable_rx_buffer_not_empty_interrupt(u32 spi);
+void spi_disable_rx_buffer_not_empty_interrupt(u32 spi);
+void spi_enable_error_interrupt(u32 spi);
+void spi_disable_error_interrupt(u32 spi);
+void spi_enable_ss_output(u32 spi);
+void spi_disable_ss_output(u32 spi);
+void spi_enable_tx_dma(u32 spi);
+void spi_disable_tx_dma(u32 spi);
+void spi_enable_rx_dma(u32 spi);
+void spi_disable_rx_dma(u32 spi);
+
+END_DECLS
+
+/**@}*/
+
+#endif
diff --git a/include/libopencm3/stm32/common/spi_common_f24.h b/include/libopencm3/stm32/common/spi_common_f24.h
new file mode 100644
index 0000000..6b3764e
--- /dev/null
+++ b/include/libopencm3/stm32/common/spi_common_f24.h
@@ -0,0 +1,50 @@
+/** @addtogroup spi_defines */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA SPI.H */
+
+#ifndef LIBOPENCM3_SPI_COMMON_F24_H
+#define LIBOPENCM3_SPI_COMMON_F24_H
+
+/**@{*/
+
+#include <libopencm3/stm32/common/spi_common_all.h>
+
+/*
+ * This file extends the common STM32 version with definitions only
+ * applicable to the STM32F2/4 series of devices.
+ */
+
+/* --- SPI_CR2 values ------------------------------------------------------ */
+
+/* FRF: Frame format */
+/* Note: Not used in I2S mode. */
+#define SPI_CR2_FRF (1 << 4)
+#define SPI_CR2_FRF_MOTOROLA_MODE (0 << 4)
+#define SPI_CR2_FRF_TI_MODE (1 << 4)
+
+/* --- SPI_SR values ------------------------------------------------------- */
+
+/* TIFRFE: TI frame format error */
+#define SPI_SR_TIFRFE (1 << 8)
+
+#endif
+/**@}*/
+
diff --git a/include/libopencm3/stm32/f1/spi.h b/include/libopencm3/stm32/f1/spi.h
new file mode 100644
index 0000000..81cdddd
--- /dev/null
+++ b/include/libopencm3/stm32/f1/spi.h
@@ -0,0 +1,40 @@
+/** @defgroup spi_defines SPI Defines
+
+@brief <b>Defined Constants and Types for the STM32F1xx SPI</b>
+
+@ingroup STM32F1xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 5 December 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_SPI_H
+#define LIBOPENCM3_SPI_H
+
+#include <libopencm3/stm32/f1/memorymap.h>
+#include <libopencm3/stm32/common/spi_common_all.h>
+
+#endif
+
diff --git a/include/libopencm3/stm32/f2/spi.h b/include/libopencm3/stm32/f2/spi.h
index df5021c..b4d99d4 100644
--- a/include/libopencm3/stm32/f2/spi.h
+++ b/include/libopencm3/stm32/f2/spi.h
@@ -1,8 +1,21 @@
+/** @defgroup spi_defines SPI Defines
+
+@brief <b>Defined Constants and Types for the STM32F2xx SPI</b>
+
+@ingroup STM32F2xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 5 December 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
/*
* This file is part of the libopencm3 project.
*
- * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
- *
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
@@ -17,27 +30,11 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
-#ifndef LIBOPENCM3_SPI_F2_H
-#define LIBOPENCM3_SPI_F2_H
+#ifndef LIBOPENCM3_SPI_H
+#define LIBOPENCM3_SPI_H
-#include <libopencm3/stm32/spi.h>
-
-/*
- * This file extends the common STM32 version with definitions only
- * applicable to the STM32F2 series of devices.
- */
-
-/* --- SPI_CR2 values ------------------------------------------------------ */
-
-/* FRF: Frame format */
-/* Note: Not used in I2S mode. */
-#define SPI_CR2_FRF (1 << 4)
-#define SPI_CR2_FRF_MOTOROLA_MODE (0 << 4)
-#define SPI_CR2_FRF_TI_MODE (1 << 4)
-
-/* --- SPI_SR values ------------------------------------------------------- */
-
-/* TIFRFE: TI frame format error */
-#define SPI_SR_TIFRFE (1 << 8)
+#include <libopencm3/stm32/f2/memorymap.h>
+#include <libopencm3/stm32/common/spi_common_f24.h>
#endif
+
diff --git a/include/libopencm3/stm32/f4/spi.h b/include/libopencm3/stm32/f4/spi.h
index c852a41..e4b0cd0 100644
--- a/include/libopencm3/stm32/f4/spi.h
+++ b/include/libopencm3/stm32/f4/spi.h
@@ -1,8 +1,21 @@
+/** @defgroup spi_defines SPI Defines
+
+@brief <b>Defined Constants and Types for the STM32F4xx SPI</b>
+
+@ingroup STM32F4xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 5 December 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
/*
* This file is part of the libopencm3 project.
*
- * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
- *
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
@@ -17,27 +30,11 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
-#ifndef LIBOPENCM3_SPI_F4_H
-#define LIBOPENCM3_SPI_F4_H
+#ifndef LIBOPENCM3_SPI_H
+#define LIBOPENCM3_SPI_H
-#include <libopencm3/stm32/spi.h>
-
-/*
- * This file extends the common STM32 version with definitions only
- * applicable to the STM32F4 series of devices.
- */
-
-/* --- SPI_CR2 values ------------------------------------------------------ */
-
-/* FRF: Frame format */
-/* Note: Not used in I2S mode. */
-#define SPI_CR2_FRF (1 << 4)
-#define SPI_CR2_FRF_MOTOROLA_MODE (0 << 4)
-#define SPI_CR2_FRF_TI_MODE (1 << 4)
-
-/* --- SPI_SR values ------------------------------------------------------- */
-
-/* TIFRFE: TI frame format error */
-#define SPI_SR_TIFRFE (1 << 8)
+#include <libopencm3/stm32/f4/memorymap.h>
+#include <libopencm3/stm32/common/spi_common_f24.h>
#endif
+
diff --git a/include/libopencm3/stm32/l1/memorymap.h b/include/libopencm3/stm32/l1/memorymap.h
index 950dd18..d89dbd6 100644
--- a/include/libopencm3/stm32/l1/memorymap.h
+++ b/include/libopencm3/stm32/l1/memorymap.h
@@ -105,4 +105,9 @@
#define DESIG_FLASH_SIZE_BASE (INFO_BASE + 0x8004C)
#define DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x80050)
+/* Make the map names match those for other families to allow commonality */
+#define SPI1_I2S_BASE SPI1_BASE
+#define SPI2_I2S_BASE SPI2_BASE
+#define SPI3_I2S_BASE SPI3_BASE
+
#endif
diff --git a/include/libopencm3/stm32/l1/spi.h b/include/libopencm3/stm32/l1/spi.h
new file mode 100644
index 0000000..97cfaa7
--- /dev/null
+++ b/include/libopencm3/stm32/l1/spi.h
@@ -0,0 +1,40 @@
+/** @defgroup spi_defines SPI Defines
+
+@brief <b>Defined Constants and Types for the STM32L1xx SPI</b>
+
+@ingroup STM32L1xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 5 December 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_SPI_H
+#define LIBOPENCM3_SPI_H
+
+#include <libopencm3/stm32/l1/memorymap.h>
+#include <libopencm3/stm32/common/spi_common_all.h>
+
+#endif
+
diff --git a/include/libopencm3/stm32/rcc.h b/include/libopencm3/stm32/rcc.h
new file mode 100644
index 0000000..2f2c9f3
--- /dev/null
+++ b/include/libopencm3/stm32/rcc.h
@@ -0,0 +1,31 @@
+/* This provides unification of code over STM32F subfamilies */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#if defined(STM32F1)
+# include <libopencm3/stm32/f1/rcc.h>
+#elif defined(STM32F2)
+# include <libopencm3/stm32/f2/rcc.h>
+#elif defined(STM32F4)
+# include <libopencm3/stm32/f4/rcc.h>
+#elif defined(STM32L1)
+# include <libopencm3/stm32/l1/rcc.h>
+#else
+# error "stm32 family not defined."
+#endif
+
diff --git a/include/libopencm3/stm32/spi.h b/include/libopencm3/stm32/spi.h
index f23df3a..28aadd1 100644
--- a/include/libopencm3/stm32/spi.h
+++ b/include/libopencm3/stm32/spi.h
@@ -1,24 +1,8 @@
-/** @defgroup spi_defines SPI Defines
-
-@ingroup STM32F_defines
-
-@brief <b>libopencm3 Defined Constants and Types for the STM32 SPI </b>
-
-@version 1.0.0
-
-@author @htmlonly &copy; @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
-@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
-
-@date 12 October 2012
-
-LGPL License Terms @ref lgpl_license
- */
+/* This provides unification of code over STM32F subfamilies */
/*
* This file is part of the libopencm3 project.
*
- * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
- *
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
@@ -33,380 +17,15 @@ LGPL License Terms @ref lgpl_license
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
-#ifndef LIBOPENCM3_SPI_H
-#define LIBOPENCM3_SPI_H
-
-#include <libopencm3/stm32/memorymap.h>
-#include <libopencm3/cm3/common.h>
-
-/**@{*/
-
-/* Registers can be accessed as 16bit or 32bit values. */
-
-/* --- Convenience macros -------------------------------------------------- */
-
-/****************************************************************************/
-/** @defgroup spi_reg_base SPI Register base address
-@ingroup spi_defines
-
-@{*/
-#define SPI1 SPI1_BASE
-#define SPI2 SPI2_I2S_BASE
-#define SPI3 SPI3_I2S_BASE
-/**@}*/
-
-/* --- SPI registers ------------------------------------------------------- */
-
-/* Control register 1 (SPIx_CR1) */
-/* Note: Not used in I2S mode. */
-#define SPI_CR1(spi_base) MMIO32(spi_base + 0x00)
-#define SPI1_CR1 SPI_CR1(SPI1_BASE)
-#define SPI2_CR1 SPI_CR1(SPI2_I2S_BASE)
-#define SPI3_CR1 SPI_CR1(SPI3_I2S_BASE)
-
-/* Control register 2 (SPIx_CR2) */
-#define SPI_CR2(spi_base) MMIO32(spi_base + 0x04)
-#define SPI1_CR2 SPI_CR2(SPI1_BASE)
-#define SPI2_CR2 SPI_CR2(SPI2_I2S_BASE)
-#define SPI3_CR2 SPI_CR2(SPI3_I2S_BASE)
-
-/* Status register (SPIx_SR) */
-#define SPI_SR(spi_base) MMIO32(spi_base + 0x08)
-#define SPI1_SR SPI_SR(SPI1_BASE)
-#define SPI2_SR SPI_SR(SPI2_I2S_BASE)
-#define SPI3_SR SPI_SR(SPI3_I2S_BASE)
-
-/* Data register (SPIx_DR) */
-#define SPI_DR(spi_base) MMIO32(spi_base + 0x0c)
-#define SPI1_DR SPI_DR(SPI1_BASE)
-#define SPI2_DR SPI_DR(SPI2_I2S_BASE)
-#define SPI3_DR SPI_DR(SPI3_I2S_BASE)
-
-/* CRC polynomial register (SPIx_CRCPR) */
-/* Note: Not used in I2S mode. */
-#define SPI_CRCPR(spi_base) MMIO32(spi_base + 0x10)
-#define SPI1_CRCPR SPI_CRCPR(SPI1_BASE)
-#define SPI2_CRCPR SPI_CRCPR(SPI2_I2S_BASE)
-#define SPI3_CRCPR SPI_CRCPR(SPI3_I2S_BASE)
-
-/* RX CRC register (SPIx_RXCRCR) */
-/* Note: Not used in I2S mode. */
-#define SPI_RXCRCR(spi_base) MMIO32(spi_base + 0x14)
-#define SPI1_RXCRCR SPI_RXCRCR(SPI1_BASE)
-#define SPI2_RXCRCR SPI_RXCRCR(SPI2_I2S_BASE)
-#define SPI3_RXCRCR SPI_RXCRCR(SPI3_I2S_BASE)
-
-/* TX CRC register (SPIx_RXCRCR) */
-/* Note: Not used in I2S mode. */
-#define SPI_TXCRCR(spi_base) MMIO32(spi_base + 0x18)
-#define SPI1_TXCRCR SPI_TXCRCR(SPI1_BASE)
-#define SPI2_TXCRCR SPI_TXCRCR(SPI2_I2S_BASE)
-#define SPI3_TXCRCR SPI_TXCRCR(SPI3_I2S_BASE)
-
-/* I2S configuration register (SPIx_I2SCFGR) */
-#define SPI_I2SCFGR(spi_base) MMIO32(spi_base + 0x1c)
-#define SPI1_I2SCFGR SPI_I2SCFGR(SPI1_BASE)
-#define SPI2_I2SCFGR SPI_I2SCFGR(SPI2_I2S_BASE)
-#define SPI3_I2SCFGR SPI_I2SCFGR(SPI3_I2S_BASE)
-
-/* I2S prescaler register (SPIx_I2SPR) */
-#define SPI_I2SPR(spi_base) MMIO32(spi_base + 0x20)
-#define SPI1_I2SPR SPI_I2SPR(SPI1_BASE)
-#define SPI2_I2SPR SPI_I2SPR(SPI2_I2S_BASE)
-#define SPI3_I2SPR SPI_I2SPR(SPI3_I2S_BASE)
-
-/* --- SPI_CR1 values ------------------------------------------------------ */
-
-/* Note: None of the CR1 bits are used in I2S mode. */
-
-/* BIDIMODE: Bidirectional data mode enable */
-#define SPI_CR1_BIDIMODE_2LINE_UNIDIR (0 << 15)
-#define SPI_CR1_BIDIMODE_1LINE_BIDIR (1 << 15)
-#define SPI_CR1_BIDIMODE (1 << 15)
-
-/* BIDIOE: Output enable in bidirectional mode */
-#define SPI_CR1_BIDIOE (1 << 14)
-
-/* CRCEN: Hardware CRC calculation enable */
-#define SPI_CR1_CRCEN (1 << 13)
-
-/* CRCNEXT: Transmit CRC next */
-#define SPI_CR1_CRCNEXT (1 << 12)
-
-/* DFF: Data frame format */
-/****************************************************************************/
-/** @defgroup spi_dff SPI data frame format
-@ingroup spi_defines
-
-@{*/
-#define SPI_CR1_DFF_8BIT (0 << 11)
-#define SPI_CR1_DFF_16BIT (1 << 11)
-/**@}*/
-#define SPI_CR1_DFF (1 << 11)
-
-/* RXONLY: Receive only */
-#define SPI_CR1_RXONLY (1 << 10)
-
-/* SSM: Software slave management */
-#define SPI_CR1_SSM (1 << 9)
-
-/* SSI: Internal slave select */
-#define SPI_CR1_SSI (1 << 8)
-
-/* LSBFIRST: Frame format */
-/****************************************************************************/
-/** @defgroup spi_lsbfirst SPI lsb/msb first
-@ingroup spi_defines
-
-@{*/
-#define SPI_CR1_MSBFIRST (0 << 7)
-#define SPI_CR1_LSBFIRST (1 << 7)
-/**@}*/
-
-/* SPE: SPI enable */
-#define SPI_CR1_SPE (1 << 6)
-
-/* BR[2:0]: Baud rate control */
-/****************************************************************************/
-/** @defgroup spi_baudrate SPI peripheral baud rates
-@ingroup spi_defines
-
-@{*/
-#define SPI_CR1_BAUDRATE_FPCLK_DIV_2 (0x00 << 3)
-#define SPI_CR1_BAUDRATE_FPCLK_DIV_4 (0x01 << 3)
-#define SPI_CR1_BAUDRATE_FPCLK_DIV_8 (0x02 << 3)
-#define SPI_CR1_BAUDRATE_FPCLK_DIV_16 (0x03 << 3)
-#define SPI_CR1_BAUDRATE_FPCLK_DIV_32 (0x04 << 3)
-#define SPI_CR1_BAUDRATE_FPCLK_DIV_64 (0x05 << 3)
-#define SPI_CR1_BAUDRATE_FPCLK_DIV_128 (0x06 << 3)
-#define SPI_CR1_BAUDRATE_FPCLK_DIV_256 (0x07 << 3)
-/**@}*/
-/****************************************************************************/
-/** @defgroup spi_br_pre SPI peripheral baud rate prescale values
-@ingroup spi_defines
-
-@{*/
-#define SPI_CR1_BR_FPCLK_DIV_2 0x0
-#define SPI_CR1_BR_FPCLK_DIV_4 0x1
-#define SPI_CR1_BR_FPCLK_DIV_8 0x2
-#define SPI_CR1_BR_FPCLK_DIV_16 0x3
-#define SPI_CR1_BR_FPCLK_DIV_32 0x4
-#define SPI_CR1_BR_FPCLK_DIV_64 0x5
-#define SPI_CR1_BR_FPCLK_DIV_128 0x6
-#define SPI_CR1_BR_FPCLK_DIV_256 0x7
-/**@}*/
-
-/* MSTR: Master selection */
-#define SPI_CR1_MSTR (1 << 2)
-
-/* CPOL: Clock polarity */
-/****************************************************************************/
-/** @defgroup spi_cpol SPI clock polarity
-@ingroup spi_defines
-
-@{*/
-#define SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE (0 << 1)
-#define SPI_CR1_CPOL_CLK_TO_1_WHEN_IDLE (1 << 1)
-/**@}*/
-#define SPI_CR1_CPOL (1 << 1)
-
-/* CPHA: Clock phase */
-/****************************************************************************/
-/** @defgroup spi_cpha SPI clock phase
-@ingroup spi_defines
-
-@{*/
-#define SPI_CR1_CPHA_CLK_TRANSITION_1 (0 << 0)
-#define SPI_CR1_CPHA_CLK_TRANSITION_2 (1 << 0)
-/**@}*/
-#define SPI_CR1_CPHA (1 << 0)
-
-/* --- SPI_CR2 values ------------------------------------------------------ */
-
-/* Bits [15:8]: Reserved. Forced to 0 by hardware. */
-
-/* TXEIE: Tx buffer empty interrupt enable */
-#define SPI_CR2_TXEIE (1 << 7)
-
-/* RXNEIE: Rx buffer not empty interrupt enable */
-#define SPI_CR2_RXNEIE (1 << 6)
-
-/* ERRIE: Error interrupt enable */
-#define SPI_CR2_ERRIE (1 << 5)
-
-/* Bits [4:3]: Reserved. Forced to 0 by hardware. */
-
-/* SSOE: SS output enable */
-/* Note: Not used in I2S mode. */
-#define SPI_CR2_SSOE (1 << 2)
-
-/* TXDMAEN: Tx buffer DMA enable */
-#define SPI_CR2_TXDMAEN (1 << 1)
-
-/* RXDMAEN: Rx buffer DMA enable */
-#define SPI_CR2_RXDMAEN (1 << 0)
-
-/* --- SPI_SR values ------------------------------------------------------- */
-
-/* Bits [15:8]: Reserved. Forced to 0 by hardware. */
-
-/* BSY: Busy flag */
-#define SPI_SR_BSY (1 << 7)
-
-/* OVR: Overrun flag */
-#define SPI_SR_OVR (1 << 6)
-
-/* MODF: Mode fault */
-/* Note: Not used in I2S mode. */
-#define SPI_SR_MODF (1 << 5)
-
-/* CRCERR: CRC error flag */
-/* Note: Not used in I2S mode. */
-#define SPI_SR_CRCERR (1 << 4)
-
-/* UDR: Underrun flag */
-/* Note: Not used in SPI mode. */
-#define SPI_SR_UDR (1 << 3)
-
-/* CHSIDE: Channel side */
-/* Note: Not used in SPI mode. No meaning in PCM mode. */
-#define SPI_SR_CHSIDE (1 << 2)
-
-/* TXE: Transmit buffer empty */
-#define SPI_SR_TXE (1 << 1)
-
-/* RXNE: Receive buffer not empty */
-#define SPI_SR_RXNE (1 << 0)
-
-/* --- SPI_DR values ------------------------------------------------------- */
-
-/* SPI_DR[15:0]: Data Register. */
-
-/* --- SPI_CRCPR values ---------------------------------------------------- */
-
-/* Note: Not used in I2S mode. */
-/* SPI_CRCPR [15:0]: CRC Polynomial Register. */
-
-/* --- SPI_RXCRCR values --------------------------------------------------- */
-
-/* Note: Not used in I2S mode. */
-/* SPI_RXCRCR [15:0]: RX CRC Register. */
-
-/* --- SPI_TXCRCR values --------------------------------------------------- */
-
-/* Note: Not used in I2S mode. */
-/* SPI_TXCRCR [15:0]: TX CRC Register. */
-
-/* --- SPI_I2SCFGR values -------------------------------------------------- */
-
-/* Note: None of these bits are used in SPI mode. */
-
-/* Bits [15:12]: Reserved. Forced to 0 by hardware. */
-
-/* I2SMOD: I2S mode selection */
-#define SPI_I2SCFGR_I2SMOD (1 << 11)
-
-/* I2SE: I2S enable */
-#define SPI_I2SCFGR_I2SE (1 << 10)
-
-/* I2SCFG[9:8]: I2S configuration mode */
-#define SPI_I2SCFGR_I2SCFG_LSB 8
-#define SPI_I2SCFGR_I2SCFG_SLAVE_TRANSMIT 0x0
-#define SPI_I2SCFGR_I2SCFG_SLAVE_RECEIVE 0x1
-#define SPI_I2SCFGR_I2SCFG_MASTER_TRANSMIT 0x2
-#define SPI_I2SCFGR_I2SCFG_MASTER_RECEIVE 0x3
-
-/* PCMSYNC: PCM frame synchronization */
-#define SPI_I2SCFGR_PCMSYNC (1 << 7)
-
-/* Bit 6: Reserved. Forced to 0 by hardware. */
-
-/* I2SSTD[5:4]: I2S standard selection */
-#define SPI_I2SCFGR_I2SSTD_LSB 4
-#define SPI_I2SCFGR_I2SSTD_I2S_PHILLIPS 0x0
-#define SPI_I2SCFGR_I2SSTD_MSB_JUSTIFIED 0x1
-#define SPI_I2SCFGR_I2SSTD_LSB_JUSTIFIED 0x2
-#define SPI_I2SCFGR_I2SSTD_PCM 0x3
-
-/* CKPOL: Steady state clock polarity */
-#define SPI_I2SCFGR_CKPOL (1 << 3)
-
-/* DATLEN[2:1]: Data length to be transferred */
-#define SPI_I2SCFGR_DATLEN_LSB 1
-#define SPI_I2SCFGR_DATLEN_16BIT 0x0
-#define SPI_I2SCFGR_DATLEN_24BIT 0x1
-#define SPI_I2SCFGR_DATLEN_32BIT 0x2
-
-/* CHLEN: Channel length */
-#define SPI_I2SCFGR_CHLEN (1 << 0)
-
-/* --- SPI_I2SPR values ---------------------------------------------------- */
-
-/* Note: None of these bits are used in SPI mode. */
-
-/* Bits [15:10]: Reserved. Forced to 0 by hardware. */
-
-/* MCKOE: Master clock output enable */
-#define SPI_I2SPR_MCKOE (1 << 9)
-
-/* ODD: Odd factor for the prescaler */
-#define SPI_I2SPR_ODD (1 << 8)
-
-/* I2SDIV[7:0]: I2S linear prescaler */
-/* 0 and 1 are forbidden values */
-
-/* --- Function prototypes ------------------------------------------------- */
-
-BEGIN_DECLS
-
-void spi_reset(u32 spi_peripheral);
-int spi_init_master(u32 spi, u32 br, u32 cpol, u32 cpha, u32 dff, u32 lsbfirst);
-void spi_enable(u32 spi);
-void spi_disable(u32 spi);
-void spi_write(u32 spi, u16 data);
-void spi_send(u32 spi, u16 data);
-u16 spi_read(u32 spi);
-u16 spi_xfer(u32 spi, u16 data);
-void spi_set_bidirectional_mode(u32 spi);
-void spi_set_unidirectional_mode(u32 spi);
-void spi_set_bidirectional_receive_only_mode(u32 spi);
-void spi_set_bidirectional_transmit_only_mode(u32 spi);
-void spi_enable_crc(u32 spi);
-void spi_disable_crc(u32 spi);
-void spi_set_next_tx_from_buffer(u32 spi);
-void spi_set_next_tx_from_crc(u32 spi);
-void spi_set_dff_8bit(u32 spi);
-void spi_set_dff_16bit(u32 spi);
-void spi_set_full_duplex_mode(u32 spi);
-void spi_set_receive_only_mode(u32 spi);
-void spi_disable_software_slave_management(u32 spi);
-void spi_enable_software_slave_management(u32 spi);
-void spi_set_nss_high(u32 spi);
-void spi_set_nss_low(u32 spi);
-void spi_send_lsb_first(u32 spi);
-void spi_send_msb_first(u32 spi);
-void spi_set_baudrate_prescaler(u32 spi, u8 baudrate);
-void spi_set_master_mode(u32 spi);
-void spi_set_slave_mode(u32 spi);
-void spi_set_clock_polarity_1(u32 spi);
-void spi_set_clock_polarity_0(u32 spi);
-void spi_set_clock_phase_1(u32 spi);
-void spi_set_clock_phase_0(u32 spi);
-void spi_enable_tx_buffer_empty_interrupt(u32 spi);
-void spi_disable_tx_buffer_empty_interrupt(u32 spi);
-void spi_enable_rx_buffer_not_empty_interrupt(u32 spi);
-void spi_disable_rx_buffer_not_empty_interrupt(u32 spi);
-void spi_enable_error_interrupt(u32 spi);
-void spi_disable_error_interrupt(u32 spi);
-void spi_enable_ss_output(u32 spi);
-void spi_disable_ss_output(u32 spi);
-void spi_enable_tx_dma(u32 spi);
-void spi_disable_tx_dma(u32 spi);
-void spi_enable_rx_dma(u32 spi);
-void spi_disable_rx_dma(u32 spi);
-
-END_DECLS
-
-/**@}*/
-
+#if defined(STM32F1)
+# include <libopencm3/stm32/f1/spi.h>
+#elif defined(STM32F2)
+# include <libopencm3/stm32/f2/spi.h>
+#elif defined(STM32F4)
+# include <libopencm3/stm32/f4/spi.h>
+#elif defined(STM32L1)
+# include <libopencm3/stm32/l1/spi.h>
+#else
+# error "stm32 family not defined."
#endif
+
diff --git a/lib/stm32/spi.c b/lib/stm32/common/spi_common_all.c
index 90675b3..3df3dcd 100644
--- a/lib/stm32/spi.c
+++ b/lib/stm32/common/spi_common_all.c
@@ -1,8 +1,4 @@
-/** @defgroup spi_file SPI
-
-@ingroup STM32F_files
-
-@brief <b>libopencm3 STM32Fxxx SPI</b>
+/** @addtogroup gpio_file
@version 1.0.0
@@ -58,15 +54,7 @@ LGPL License Terms @ref lgpl_license
*/
#include <libopencm3/stm32/spi.h>
-#if defined(STM32F1)
-# include <libopencm3/stm32/f1/rcc.h>
-#elif defined(STM32F2)
-# include <libopencm3/stm32/f2/rcc.h>
-#elif defined(STM32F4)
-# include <libopencm3/stm32/f4/rcc.h>
-#else
-# error "stm32 family not defined."
-#endif
+#include <libopencm3/stm32/rcc.h>
/*
* SPI and I2S code.
@@ -103,10 +91,12 @@ void spi_reset(u32 spi_peripheral)
rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_SPI2RST);
rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_SPI2RST);
break;
+#if defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4)
case SPI3:
rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_SPI3RST);
rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_SPI3RST);
break;
+#endif
}
}
diff --git a/lib/stm32/f1/Makefile b/lib/stm32/f1/Makefile
index 2572554..845ae0c 100644
--- a/lib/stm32/f1/Makefile
+++ b/lib/stm32/f1/Makefile
@@ -28,12 +28,12 @@ CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \
-ffunction-sections -fdata-sections -MD -DSTM32F1
# ARFLAGS = rcsv
ARFLAGS = rcs
-OBJS = rcc.o gpio.o usart.o adc.o spi.o flash.o \
+OBJS = rcc.o gpio.o usart.o adc.o flash.o \
rtc.o i2c.o dma.o exti.o ethernet.o \
usb_f103.o usb.o usb_control.o usb_standard.o can.o \
timer.o usb_f107.o desig.o crc.o dac.o iwdg.o pwr.o \
usb_fx07_common.o \
- gpio_common_all.o
+ gpio_common_all.o spi_common_all.o
VPATH += ../../usb:../:../../cm3:../common
diff --git a/lib/stm32/f1/spi.c b/lib/stm32/f1/spi.c
new file mode 100644
index 0000000..3be5c23
--- /dev/null
+++ b/lib/stm32/f1/spi.c
@@ -0,0 +1,28 @@
+/** @defgroup spi_file SPI
+
+@ingroup STM32F1xx
+
+@brief <b>libopencm3 STM32F1xx SPI</b>
+
+*/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopencm3/stm32/spi.h>
+#include <libopencm3/stm32/common/spi_common_all.h>
+
diff --git a/lib/stm32/f2/Makefile b/lib/stm32/f2/Makefile
index b890fa4..174dbce 100644
--- a/lib/stm32/f2/Makefile
+++ b/lib/stm32/f2/Makefile
@@ -28,9 +28,9 @@ CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \
-ffunction-sections -fdata-sections -MD -DSTM32F2
# ARFLAGS = rcsv
ARFLAGS = rcs
-OBJS = rcc.o gpio.o usart.o spi.o flash.o \
+OBJS = rcc.o gpio.o usart.o flash.o \
i2c.o exti2.o timer.o \
- gpio_common_all.o gpio_common_f24.o
+ gpio_common_all.o gpio_common_f24.o spi_common_all.o
VPATH += ../../usb:../:../../cm3:../common
diff --git a/lib/stm32/f2/spi.c b/lib/stm32/f2/spi.c
new file mode 100644
index 0000000..bc4a4ee
--- /dev/null
+++ b/lib/stm32/f2/spi.c
@@ -0,0 +1,28 @@
+/** @defgroup spi_file SPI
+
+@ingroup STM32F2xx
+
+@brief <b>libopencm3 STM32F2xx SPI</b>
+
+*/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopencm3/stm32/spi.h>
+#include <libopencm3/stm32/common/spi_common_f24.h>
+
diff --git a/lib/stm32/f4/Makefile b/lib/stm32/f4/Makefile
index c9ad847..0bd9a10 100644
--- a/lib/stm32/f4/Makefile
+++ b/lib/stm32/f4/Makefile
@@ -29,11 +29,11 @@ CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \
-ffunction-sections -fdata-sections -MD -DSTM32F4
# ARFLAGS = rcsv
ARFLAGS = rcs
-OBJS = rcc.o gpio.o usart.o spi.o flash.o \
+OBJS = rcc.o gpio.o usart.o flash.o \
i2c.o exti2.o pwr.o timer.o \
usb.o usb_standard.o usb_control.o usb_fx07_common.o usb_f107.o \
usb_f207.o adc.o dma.o \
- gpio_common_all.o gpio_common_f24.o
+ gpio_common_all.o gpio_common_f24.o spi_common_all.o
VPATH += ../../usb:../:../../cm3:../common
diff --git a/lib/stm32/f4/spi.c b/lib/stm32/f4/spi.c
new file mode 100644
index 0000000..40f5501
--- /dev/null
+++ b/lib/stm32/f4/spi.c
@@ -0,0 +1,28 @@
+/** @defgroup spi_file SPI
+
+@ingroup STM32F4xx
+
+@brief <b>libopencm3 STM32F4xx SPI</b>
+
+*/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopencm3/stm32/spi.h>
+#include <libopencm3/stm32/common/spi_common_f24.h>
+
diff --git a/lib/stm32/l1/Makefile b/lib/stm32/l1/Makefile
index a3c8856..b533acf 100644
--- a/lib/stm32/l1/Makefile
+++ b/lib/stm32/l1/Makefile
@@ -28,8 +28,8 @@ CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \
-ffunction-sections -fdata-sections -MD -DSTM32L1
# ARFLAGS = rcsv
ARFLAGS = rcs
-OBJS = rcc.o gpio.o desig.o crc.o usart.o exti2.o
-OBJS += flash.o gpio_common_all.o gpio_common_f24.o
+OBJS = rcc.o desig.o crc.o usart.o exti2.o
+OBJS += flash.o gpio_common_all.o gpio_common_f24.o spi_common_all.o
OBJS += pwr_chipset.o # TODO, get pwr.o to fix f2/f4 first... pwr.o
OBJS += timer.o
diff --git a/lib/stm32/l1/spi.c b/lib/stm32/l1/spi.c
new file mode 100644
index 0000000..30c44dd
--- /dev/null
+++ b/lib/stm32/l1/spi.c
@@ -0,0 +1,28 @@
+/** @defgroup spi_file SPI
+
+@ingroup STM32L1xx
+
+@brief <b>libopencm3 STM32L1xx SPI</b>
+
+*/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopencm3/stm32/spi.h>
+#include <libopencm3/stm32/common/spi_common_all.h>
+