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-rw-r--r--examples/stm32/stm32-h103/pwm_6step/Makefile23
-rw-r--r--examples/stm32/stm32-h103/pwm_6step/pwm_6step.c319
-rw-r--r--examples/stm32/stm32-h103/pwm_6step/pwm_6step.ld31
-rw-r--r--include/libopencm3/stm32/timer.h53
-rw-r--r--lib/stm32/Makefile3
-rw-r--r--lib/stm32/timer.c20
6 files changed, 440 insertions, 9 deletions
diff --git a/examples/stm32/stm32-h103/pwm_6step/Makefile b/examples/stm32/stm32-h103/pwm_6step/Makefile
new file mode 100644
index 0000000..2360082
--- /dev/null
+++ b/examples/stm32/stm32-h103/pwm_6step/Makefile
@@ -0,0 +1,23 @@
+##
+## This file is part of the libopencm3 project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+##
+## This program is free software: you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation, either version 3 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program. If not, see <http://www.gnu.org/licenses/>.
+##
+
+BINARY = pwm_6step
+
+include ../../Makefile.include
+
diff --git a/examples/stm32/stm32-h103/pwm_6step/pwm_6step.c b/examples/stm32/stm32-h103/pwm_6step/pwm_6step.c
new file mode 100644
index 0000000..af26c5a
--- /dev/null
+++ b/examples/stm32/stm32-h103/pwm_6step/pwm_6step.c
@@ -0,0 +1,319 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2011 Piotr Esden-Tempski <piotr@esden.net>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopencm3/stm32/rcc.h>
+#include <libopencm3/stm32/nvic.h>
+#include <libopencm3/stm32/gpio.h>
+#include <libopencm3/stm32/timer.h>
+
+void clock_setup(void)
+{
+ rcc_clock_setup_in_hse_8mhz_out_72mhz();
+
+ /* Enable TIM1 clock. */
+ rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_TIM1EN);
+
+ /* Enable GPIOA, GPIOB and Alternate Function clocks. */
+ rcc_peripheral_enable_clock(&RCC_APB2ENR,
+ RCC_APB2ENR_IOPAEN |
+ RCC_APB2ENR_IOPBEN |
+ RCC_APB2ENR_AFIOEN);
+}
+
+void gpio_setup(void)
+{
+ /*
+ * Set GPIO12 (PORTC) (led) to
+ * 'output alternate function push-pull'.
+ */
+ gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ,
+ GPIO_CNF_OUTPUT_PUSHPULL, GPIO12);
+
+ /*
+ * Set TIM1 chanel output pins to
+ * 'output alternate function push-pull'.
+ */
+ gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ,
+ GPIO_CNF_OUTPUT_ALTFN_PUSHPULL,
+ GPIO_TIM1_CH1 |
+ GPIO_TIM1_CH2 |
+ GPIO_TIM1_CH3);
+
+ /*
+ * Set TIM1 complementary chanel output pins to
+ * 'output alternate function push-pull'.
+ */
+ gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ,
+ GPIO_CNF_OUTPUT_ALTFN_PUSHPULL,
+ GPIO_TIM1_CH1N |
+ GPIO_TIM1_CH2N |
+ GPIO_TIM1_CH3N);
+
+}
+
+void tim_setup(void)
+{
+
+ /* Enable TIM1 commutation interrupt. */
+ nvic_enable_irq(NVIC_TIM1_TRG_COM_IRQ);
+
+ /* Clock division. */
+ timer_set_clock_division(TIM1, TIM_CR1_CKD_CK_INT);
+
+ /* Timer global mode:
+ * - No divider
+ * - alignment edge
+ * - direction up
+ */
+ timer_set_mode(TIM1, TIM_CR1_CKD_CK_INT,
+ TIM_CR1_CMS_EDGE,
+ TIM_CR1_DIR_UP);
+
+ /* Enable preload. */
+ timer_enable_preload(TIM1);
+ //timer_disable_preload(TIM1);
+
+ /* Continous mode. */
+ timer_continuous_mode(TIM1);
+
+ /* Period (32kHz) */
+ TIM1_ARR = 72000000 / 32000;
+
+ /* -- OC1 and OC1N configuration -- */
+ {
+ u16 tmp_ccmr1 = 0, tmp_ccer = 0, tmp_cr2 = 0;
+
+ /** Disable OC1. **/
+ TIM1_CCER &= ~TIM_CCER_CC1E;
+
+ /** Disable OC1N. **/
+ TIM1_CCER &= ~TIM_CCER_CC1NE;
+
+ /** Get registers. **/
+ tmp_ccmr1 = TIM1_CCMR1;
+ tmp_ccer = TIM1_CCER;
+ tmp_cr2 = TIM1_CR2;
+
+ /** Configure global mode of line 1 **/
+
+ /* Disable OC1 clear. (esden: What is that?) */
+ tmp_ccmr1 &= ~TIM_CCMR1_OC1CE;
+
+ /* Set CC1 to output mode. */
+ tmp_ccmr1 &= ~TIM_CCMR1_CC1S_MASK;
+ tmp_ccmr1 |= TIM_CCMR1_CC1S_OUT;
+
+ /* Enable OC1 preload enable. */
+ //tmp_ccmr1 |= TIM_CCMR1_OC1PE;
+ tmp_ccmr1 &= ~TIM_CCMR1_OC1PE;
+
+ /* Disable OC1 fast mode. */
+ tmp_ccmr1 &= ~TIM_CCMR1_OC1FE;
+
+ /* Set OC1 mode to PWM1. */
+ tmp_ccmr1 &= ~TIM_CCMR1_OC1M_MASK;
+ tmp_ccmr1 |= TIM_CCMR1_OC1M_PWM1;
+
+ /** Configure OC1. **/
+
+ /* Set output polarity level, high. */
+ tmp_ccer &= ~TIM_CCER_CC1P;
+
+ /* Enable OC1 output */
+ tmp_ccer |= TIM_CCER_CC1E;
+
+ /* Set OC1 idle state to "set". (TIM1 and TIM8 only) */
+ tmp_cr2 |= TIM_CR2_OIS1;
+
+ /** Configure OC1N. **/
+
+ /* Set output polarity level, high. (TIM1 and TIM8 only) */
+ tmp_ccer &= ~TIM_CCER_CC1NP;
+
+ /* Enable OC1N output. (TIM1 and TIM8 only) */
+ tmp_ccer |= TIM_CCER_CC1NE;
+
+ /* Set OC1N idle state to "set". (TIM1 and TIM8 only) */
+ tmp_cr2 |= TIM_CR2_OIS1N;
+
+ /** Set the capture compare value for OC1 **/
+ TIM1_CCR1 = 100;
+
+ /** Write register values **/
+ TIM1_CR2 = tmp_cr2;
+ TIM1_CCMR1 = tmp_ccmr1;
+ TIM1_CCER = tmp_ccer;
+
+ }
+
+ /* -- OC2 and OC2N configuration -- */
+ {
+ u16 tmp_ccmr1 = 0, tmp_ccer = 0, tmp_cr2 = 0;
+
+ /** Disable OC2. **/
+ TIM1_CCER &= ~TIM_CCER_CC2E;
+
+ /** Disable OC2N. **/
+ TIM1_CCER &= ~TIM_CCER_CC2NE;
+
+ /** Get registers. **/
+ tmp_ccmr1 = TIM1_CCMR1;
+ tmp_ccer = TIM1_CCER;
+ tmp_cr2 = TIM1_CR2;
+
+ /** Configure global mode of line 1 **/
+
+ /* Disable OC2 clear. (esden: What is that?) */
+ tmp_ccmr1 &= ~TIM_CCMR1_OC2CE;
+
+ /* Set CC2 to output mode. */
+ tmp_ccmr1 &= ~TIM_CCMR1_CC2S_MASK;
+ tmp_ccmr1 |= TIM_CCMR1_CC2S_OUT;
+
+ /* Enable OC2 preload enable. */
+ tmp_ccmr1 |= TIM_CCMR1_OC2PE;
+
+ /* Disable OC2 fast mode. */
+ tmp_ccmr1 &= ~TIM_CCMR1_OC2FE;
+
+ /* Set OC2 mode to PWM1. */
+ tmp_ccmr1 &= ~TIM_CCMR1_OC2M_MASK;
+ tmp_ccmr1 |= TIM_CCMR1_OC2M_PWM1;
+
+ /** Configure OC2. **/
+
+ /* Set output polarity level, high. */
+ tmp_ccer &= ~TIM_CCER_CC2P;
+
+ /* Enable OC2 output */
+ tmp_ccer |= TIM_CCER_CC2E;
+
+ /* Set OC2 idle state to "set". (TIM1 and TIM8 only) */
+ tmp_cr2 |= TIM_CR2_OIS2;
+
+ /** Configure OC2N. **/
+
+ /* Set output polarity level, high. (TIM1 and TIM8 only) */
+ tmp_ccer &= ~TIM_CCER_CC2NP;
+
+ /* Enable OC2N output. (TIM1 and TIM8 only) */
+ tmp_ccer |= TIM_CCER_CC2NE;
+
+ /* Set OC2N idle state to "set". (TIM1 and TIM8 only) */
+ tmp_cr2 |= TIM_CR2_OIS2N;
+
+ /** Set the capture compare value for OC2 **/
+ TIM1_CCR2 = 200;
+
+ /** Write register values **/
+ TIM1_CR2 = tmp_cr2;
+ TIM1_CCMR1 = tmp_ccmr1;
+ TIM1_CCER = tmp_ccer;
+
+ }
+
+ /* -- OC3 and OC3N configuration -- */
+ {
+ u16 tmp_ccmr2 = 0, tmp_ccer = 0, tmp_cr2 = 0;
+
+ /** Disable OC3. **/
+ TIM1_CCER &= ~TIM_CCER_CC3E;
+
+ /** Disable OC3N. **/
+ TIM1_CCER &= ~TIM_CCER_CC3NE;
+
+ /** Get registers. **/
+ tmp_ccmr2 = TIM1_CCMR2;
+ tmp_ccer = TIM1_CCER;
+ tmp_cr2 = TIM1_CR2;
+
+ /** Configure global mode of line 1 **/
+
+ /* Disable OC3 clear. (esden: What is that?) */
+ tmp_ccmr2 &= ~TIM_CCMR2_OC3CE;
+
+ /* Set CC3 to output mode. */
+ tmp_ccmr2 &= ~TIM_CCMR2_CC3S_MASK;
+ tmp_ccmr2 |= TIM_CCMR2_CC3S_OUT;
+
+ /* Enable OC3 preload enable. */
+ tmp_ccmr2 |= TIM_CCMR2_OC3PE;
+
+ /* Disable OC3 fast mode. */
+ tmp_ccmr2 &= ~TIM_CCMR2_OC3FE;
+
+ /* Set OC3 mode to PWM1. */
+ tmp_ccmr2 &= ~TIM_CCMR2_OC3M_MASK;
+ tmp_ccmr2 |= TIM_CCMR2_OC3M_PWM1;
+
+ /** Configure OC3. **/
+
+ /* Set output polarity level, high. */
+ tmp_ccer &= ~TIM_CCER_CC3P;
+
+ /* Enable OC3 output */
+ tmp_ccer |= TIM_CCER_CC3E;
+
+ /* Set OC3 idle state to "set". (TIM1 and TIM8 only) */
+ tmp_cr2 |= TIM_CR2_OIS3;
+
+ /** Configure OC3N. **/
+
+ /* Set output polarity level, high. (TIM1 and TIM8 only) */
+ tmp_ccer &= ~TIM_CCER_CC3NP;
+
+ /* Enable OC3N output. (TIM1 and TIM8 only) */
+ tmp_ccer |= TIM_CCER_CC3NE;
+
+ /* Set OC3N idle state to "set". (TIM1 and TIM8 only) */
+ tmp_cr2 |= TIM_CR2_OIS3N;
+
+ /** Set the capture compare value for OC3 **/
+ TIM1_CCR3 = 300;
+
+ /** Write register values **/
+ TIM1_CR2 = tmp_cr2;
+ TIM1_CCMR2 = tmp_ccmr2;
+ TIM1_CCER = tmp_ccer;
+
+ }
+
+ /* ---- */
+ /* ARR reload enable */
+ TIM1_CR1 |= TIM_CR1_ARPE;
+
+ /* Enable outputs in the break subsystem */
+ TIM1_BDTR |= TIM_BDTR_MOE;
+
+ /* Counter enable */
+ TIM1_CR1 |= TIM_CR1_CEN;
+}
+
+int main(void)
+{
+ clock_setup();
+ gpio_setup();
+ tim_setup();
+
+ while (1) {
+ __asm("nop");
+ }
+
+ return 0;
+}
diff --git a/examples/stm32/stm32-h103/pwm_6step/pwm_6step.ld b/examples/stm32/stm32-h103/pwm_6step/pwm_6step.ld
new file mode 100644
index 0000000..7ea2b92
--- /dev/null
+++ b/examples/stm32/stm32-h103/pwm_6step/pwm_6step.ld
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Linker script for Olimex STM32-H103 (STM32F103RBT6, 128K flash, 20K RAM). */
+
+/* Define memory regions. */
+MEMORY
+{
+ rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K
+}
+
+/* Include the common ld script. */
+INCLUDE libopencm3_stm32.ld
+
diff --git a/include/libopencm3/stm32/timer.h b/include/libopencm3/stm32/timer.h
index dabf732..738765b 100644
--- a/include/libopencm3/stm32/timer.h
+++ b/include/libopencm3/stm32/timer.h
@@ -241,6 +241,7 @@
#define TIM_CR1_CMS_CENTER_1 (0x1 << 5)
#define TIM_CR1_CMS_CENTER_2 (0x2 << 5)
#define TIM_CR1_CMS_CENTER_3 (0x3 << 5)
+#define TIM_CR1_CMS_MASK (0x3 << 5)
/* DIR: Direction */
#define TIM_CR1_DIR_UP (0 << 4)
@@ -318,6 +319,7 @@
#define TIM_SMCR_ETPS_ETRP_DIV_2 (0x1 << 12)
#define TIM_SMCR_ETPS_ETRP_DIV_4 (0x2 << 12)
#define TIM_SMCR_ETPS_ETRP_DIV_8 (0x3 << 12)
+#define TIM_SMCR_ETPS_MASK (0X3 << 12)
/* ETF[3:0]: External trigger filter */
#define TIM_SMCR_ETF_OFF (0x0 << 8)
@@ -336,6 +338,7 @@
#define TIM_SMCR_ETF_DTS_DIV_32_N_5 (0xD << 8)
#define TIM_SMCR_ETF_DTS_DIV_32_N_6 (0xE << 8)
#define TIM_SMCR_ETF_DTS_DIV_32_N_8 (0xF << 8)
+#define TIM_SMCR_ETF_MASK (0xF << 8)
/* MSM: Master/slave mode */
#define TIM_SMCR_MSM (1 << 7)
@@ -349,6 +352,7 @@
#define TIM_SMCR_TS_IT1FP1 (0x5 << 4)
#define TIM_SMCR_TS_IT1FP2 (0x6 << 4)
#define TIM_SMCR_TS_ETRF (0x7 << 4)
+#define TIM_SMCR_TS_MASK (0x7 << 4)
/* SMS[2:0]: Slave mode selection */
#define TIM_SMCR_SMS_OFF (0x0 << 0)
@@ -359,6 +363,7 @@
#define TIM_SMCR_SMS_GM (0x5 << 0)
#define TIM_SMCR_SMS_TM (0x6 << 0)
#define TIM_SMCR_SMS_ECM1 (0x7 << 0)
+#define TIM_SMCR_SMS_MASK (0x7 << 0)
/* --- TIMx_DIER values ---------------------------------------------------- */
@@ -487,6 +492,7 @@
#define TIM_CCMR1_OC2M_FORCE_HIGH (0x5 << 12)
#define TIM_CCMR1_OC2M_PWM1 (0x6 << 12)
#define TIM_CCMR1_OC2M_PWM2 (0x7 << 12)
+#define TIM_CCMR1_OC2M_MASK (0x7 << 12)
/* OC2PE: Output compare 2 preload enable */
#define TIM_CCMR1_OC2PE (1 << 11)
@@ -501,6 +507,7 @@
#define TIM_CCMR1_CC2S_IN_TI2 (0x1 << 8)
#define TIM_CCMR1_CC2S_IN_TI1 (0x2 << 8)
#define TIM_CCMR1_CC2S_IN_TRC (0x3 << 8)
+#define TIM_CCMR1_CC2S_MASK (0x3 << 8)
/* OC1CE: Output compare 1 clear enable */
#define TIM_CCMR1_OC1CE (1 << 7)
@@ -514,6 +521,7 @@
#define TIM_CCMR1_OC1M_FORCE_HIGH (0x5 << 4)
#define TIM_CCMR1_OC1M_PWM1 (0x6 << 4)
#define TIM_CCMR1_OC1M_PWM2 (0x7 << 4)
+#define TIM_CCMR1_OC1M_MASK (0x7 << 4)
/* OC1PE: Output compare 1 preload enable */
#define TIM_CCMR1_OC1PE (1 << 3)
@@ -528,6 +536,7 @@
#define TIM_CCMR1_CC1S_IN_TI2 (0x1 << 0)
#define TIM_CCMR1_CC1S_IN_TI1 (0x2 << 0)
#define TIM_CCMR1_CC1S_IN_TRC (0x3 << 0)
+#define TIM_CCMR1_CC1S_MASK (0x3 << 0)
/* --- Input capture mode --- */
@@ -548,12 +557,14 @@
#define TIM_CCMR1_IC2F_DTF_DIV_32_N_5 (0xD << 12)
#define TIM_CCMR1_IC2F_DTF_DIV_32_N_6 (0xE << 12)
#define TIM_CCMR1_IC2F_DTF_DIV_32_N_8 (0xF << 12)
+#define TIM_CCMR1_IC2F_MASK (0xF << 12)
/* IC2PSC[1:0]: Input capture 2 prescaler */
#define TIM_CCMR1_IC2PSC_OFF (0x0 << 10)
#define TIM_CCMR1_IC2PSC_2 (0x1 << 10)
#define TIM_CCMR1_IC2PSC_4 (0x2 << 10)
#define TIM_CCMR1_IC2PSC_8 (0x3 << 10)
+#define TIM_CCMR1_IC2PSC_MASK (0x3 << 10)
/* IC1F[3:0]: Input capture 1 filter */
#define TIM_CCMR1_IC1F_OFF (0x0 << 4)
@@ -572,12 +583,14 @@
#define TIM_CCMR1_IC1F_DTF_DIV_32_N_5 (0xD << 4)
#define TIM_CCMR1_IC1F_DTF_DIV_32_N_6 (0xE << 4)
#define TIM_CCMR1_IC1F_DTF_DIV_32_N_8 (0xF << 4)
+#define TIM_CCMR1_IC1F_MASK (0xF << 4)
/* IC1PSC[1:0]: Input capture 1 prescaler */
#define TIM_CCMR1_IC1PSC_OFF (0x0 << 2)
#define TIM_CCMR1_IC1PSC_2 (0x1 << 2)
#define TIM_CCMR1_IC1PSC_4 (0x2 << 2)
#define TIM_CCMR1_IC1PSC_8 (0x3 << 2)
+#define TIM_CCMR1_IC1PSC_MASK (0x3 << 2)
/* --- TIMx_CCMR2 values --------------------------------------------------- */
@@ -595,6 +608,7 @@
#define TIM_CCMR2_OC4M_FORCE_HIGH (0x5 << 12)
#define TIM_CCMR2_OC4M_PWM1 (0x6 << 12)
#define TIM_CCMR2_OC4M_PWM2 (0x7 << 12)
+#define TIM_CCMR2_OC4M_MASK (0x7 << 12)
/* OC4PE: Output compare 4 preload enable */
#define TIM_CCMR2_OC4PE (1 << 11)
@@ -609,9 +623,10 @@
#define TIM_CCMR2_CC4S_IN_TI2 (0x1 << 8)
#define TIM_CCMR2_CC4S_IN_TI1 (0x2 << 8)
#define TIM_CCMR2_CC4S_IN_TRC (0x3 << 8)
+#define TIM_CCMR2_CC4S_MASK (0x3 << 8)
/* OC3CE: Output compare 3 clear enable */
-#define TIM_CCMR2_OC1CE (1 << 7)
+#define TIM_CCMR2_OC3CE (1 << 7)
/* OC3M[2:0]: Output compare 3 mode */
#define TIM_CCMR2_OC3M_FROZEN (0x0 << 4)
@@ -622,6 +637,7 @@
#define TIM_CCMR2_OC3M_FORCE_HIGH (0x5 << 4)
#define TIM_CCMR2_OC3M_PWM1 (0x6 << 4)
#define TIM_CCMR2_OC3M_PWM2 (0x7 << 4)
+#define TIM_CCMR2_OC3M_MASK (0x7 << 4)
/* OC3PE: Output compare 3 preload enable */
#define TIM_CCMR2_OC3PE (1 << 3)
@@ -636,6 +652,7 @@
#define TIM_CCMR2_CC3S_IN_TI2 (0x1 << 0)
#define TIM_CCMR2_CC3S_IN_TI1 (0x2 << 0)
#define TIM_CCMR2_CC3S_IN_TRC (0x3 << 0)
+#define TIM_CCMR2_CC3S_MASK (0x3 << 0)
/* --- Input capture mode --- */
@@ -656,12 +673,14 @@
#define TIM_CCMR2_IC4F_DTF_DIV_32_N_5 (0xD << 12)
#define TIM_CCMR2_IC4F_DTF_DIV_32_N_6 (0xE << 12)
#define TIM_CCMR2_IC4F_DTF_DIV_32_N_8 (0xF << 12)
+#define TIM_CCMR2_IC4F_MASK (0xF << 12)
/* IC4PSC[1:0]: Input capture 4 prescaler */
#define TIM_CCMR2_IC4PSC_OFF (0x0 << 10)
#define TIM_CCMR2_IC4PSC_2 (0x1 << 10)
#define TIM_CCMR2_IC4PSC_4 (0x2 << 10)
#define TIM_CCMR2_IC4PSC_8 (0x3 << 10)
+#define TIM_CCMR2_IC4PSC_MASK (0x3 << 10)
/* IC3F[3:0]: Input capture 3 filter */
#define TIM_CCMR2_IC3F_OFF (0x0 << 4)
@@ -680,12 +699,14 @@
#define TIM_CCMR2_IC3F_DTF_DIV_32_N_5 (0xD << 4)
#define TIM_CCMR2_IC3F_DTF_DIV_32_N_6 (0xE << 4)
#define TIM_CCMR2_IC3F_DTF_DIV_32_N_8 (0xF << 4)
+#define TIM_CCMR2_IC3F_MASK (0xF << 4)
/* IC3PSC[1:0]: Input capture 3 prescaler */
#define TIM_CCMR2_IC3PSC_OFF (0x0 << 2)
#define TIM_CCMR2_IC3PSC_2 (0x1 << 2)
#define TIM_CCMR2_IC3PSC_4 (0x2 << 2)
#define TIM_CCMR2_IC3PSC_8 (0x3 << 2)
+#define TIM_CCMR2_IC3PSC_MASK (0x3 << 2)
/* --- TIMx_CCER values ---------------------------------------------------- */
@@ -788,6 +809,7 @@
#define TIM_BDTR_LOCK_LEVEL_1 (0x1 << 8)
#define TIM_BDTR_LOCK_LEVEL_2 (0x2 << 8)
#define TIM_BDTR_LOCK_LEVEL_3 (0x3 << 8)
+#define TIM_BDTR_LOCK_MASK (0x3 << 8)
/* DTG[7:0]: Dead-time generator set-up */
#define TIM_BDTR_DTG_MASK 0x00FF
@@ -804,4 +826,33 @@
/* DMAB[15:0]: DMA register for burst accesses */
+/* --- TIM functions ------------------------------------------------------- */
+void timer_set_mode(u32 timer_peripheral, u8 clock_div,
+ u8 alignment, u8 direction);
+void timer_set_clock_division(u32 timer_peripheral, u32 clock_div);
+void timer_enable_preload(u32 timer_peripheral);
+void timer_disable_preload(u32 timer_peripheral);
+void timer_set_alignment(u32 timer_peripheral, u32 alignment);
+void timer_direction_up(u32 timer_peripheral);
+void timer_direction_down(u32 timer_peripheral);
+void timer_one_shot_mode(u32 timer_peripheral);
+void timer_continuous_mode(u32 timer_peripheral);
+void timer_update_on_any(u32 timer_peripheral);
+void timer_update_on_overflow(u32 timer_peripheral);
+void timer_enable_update_event(u32 timer_peripheral);
+void timer_disable_update_event(u32 timer_peripheral);
+void timer_enable_counter(u32 timer_peripheral);
+void timer_disable_counter(u32 timer_peripheral);
+void timer_set_output_idle_state(u32 timer_peripheral, u32 outputs);
+void timer_reset_output_idle_state(u32 timer_peripheral, u32 outputs);
+void timer_set_ti1_ch123_xor(u32 timer_peripheral);
+void timer_set_ti1_ch1(u32 timer_peripheral);
+void timer_set_master_mode(u32 timer_peripheral, u32 mode);
+void timer_set_dma_on_compare_event(u32 timer_peripheral);
+void timer_set_dma_on_update_event(u32 timer_peripheral);
+void timer_enable_compare_control_update_on_trigger(u32 timer_peripheral);
+void timer_disable_compare_control_update_on_trigger(u32 timer_peripheral);
+void timer_enable_preload_complementry_enable_bits(u32 timer_peripheral);
+void timer_disable_preload_complementry_enable_bits(u32 timer_peripheral);
+
#endif
diff --git a/lib/stm32/Makefile b/lib/stm32/Makefile
index 4c7ac4e..966cb03 100644
--- a/lib/stm32/Makefile
+++ b/lib/stm32/Makefile
@@ -30,7 +30,8 @@ CFLAGS = -Os -g -Wall -Wextra -I../../include -fno-common \
ARFLAGS = rcs
OBJS = vector.o rcc.o gpio.o usart.o adc.o spi.o flash.o nvic.o \
rtc.o i2c.o dma.o systick.o exti.o scb.o ethernet.o \
- usb_f103.o usb.o usb_control.o usb_standard.o can.o
+ usb_f103.o usb.o usb_control.o usb_standard.o can.o \
+ timer.o
VPATH += ../usb
diff --git a/lib/stm32/timer.c b/lib/stm32/timer.c
index ae51f1e..929469a 100644
--- a/lib/stm32/timer.c
+++ b/lib/stm32/timer.c
@@ -27,17 +27,24 @@
#include <libopencm3/stm32/timer.h>
-void timer_set_mode(u32 timer_peripheral, u8 clock_div, u8 alignment,
- u8 direction)
+void timer_set_mode(u32 timer_peripheral, u8 clock_div,
+ u8 alignment, u8 direction)
{
- /* Bad, will reset lots of other stuff. */
- // TIM_CR1(timer_peripheral) = clock_div | alignment | direction;
+ u32 cr1 = TIM_CR1(timer_peripheral);
+
+ cr1 &= ~(TIM_CR1_CKD_CK_INT_MASK |
+ TIM_CR1_CMS_MASK |
+ TIM_CR1_DIR_DOWN);
+
+ cr1 |= clock_div | alignment | direction;
+
+ TIM_CR1(timer_peripheral) = cr1;
}
void timer_set_clock_division(u32 timer_peripheral, u32 clock_div)
{
clock_div &= TIM_CR1_CKD_CK_INT_MASK;
- TIM_CR1(timer_peripheral) &= !TIM_CR1_CKD_CK_INT_MASK;
+ TIM_CR1(timer_peripheral) &= ~TIM_CR1_CKD_CK_INT_MASK;
TIM_CR1(timer_peripheral) |= clock_div;
}
@@ -48,7 +55,7 @@ void timer_enable_preload(u32 timer_peripheral)
void timer_disable_preload(u32 timer_peripheral)
{
- TIM_CR1(timer_peripheral) &= !TIM_CR1_ARPE;
+ TIM_CR1(timer_peripheral) &= ~TIM_CR1_ARPE;
}
void timer_set_alignment(u32 timer_peripheral, u32 alignment)
@@ -130,7 +137,6 @@ void timer_set_ti1_ch1(u32 timer_peripheral)
void timer_set_master_mode(u32 timer_peripheral, u32 mode)
{
- mode &= mode & TIM_CR2_MASK;
TIM_CR2(timer_peripheral) &= ~TIM_CR2_MMS_MASK;
TIM_CR2(timer_peripheral) |= mode;
}