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-rw-r--r--Makefile2
-rw-r--r--include/libopencm3/stm32/f4/flash.h153
-rw-r--r--include/libopencm3/stm32/f4/gpio.h278
-rw-r--r--include/libopencm3/stm32/f4/memorymap.h131
-rw-r--r--include/libopencm3/stm32/f4/nvic_f4.h112
-rw-r--r--include/libopencm3/stm32/f4/pwr.h57
-rw-r--r--include/libopencm3/stm32/f4/rcc.h515
-rw-r--r--include/libopencm3/stm32/f4/scb.h300
-rw-r--r--include/libopencm3/stm32/f4/spi.h42
-rw-r--r--include/libopencm3/stm32/f4/syscfg.h46
-rw-r--r--include/libopencm3/stm32/f4/timer.h54
-rw-r--r--include/libopencm3/stm32/f4/usart.h35
-rw-r--r--include/libopencm3/stm32/memorymap.h4
-rw-r--r--include/libopencm3/stm32/nvic.h4
-rw-r--r--lib/stm32/f4/Makefile59
-rw-r--r--lib/stm32/f4/exti.c146
-rw-r--r--lib/stm32/f4/flash.c250
-rw-r--r--lib/stm32/f4/gpio.c139
-rw-r--r--lib/stm32/f4/libopencm3_stm32f4.ld63
-rw-r--r--lib/stm32/f4/pwr.c28
-rw-r--r--lib/stm32/f4/rcc.c434
-rw-r--r--lib/stm32/f4/scb.c30
-rw-r--r--lib/stm32/f4/vector.c336
23 files changed, 3217 insertions, 1 deletions
diff --git a/Makefile b/Makefile
index 4799358..f1f7998 100644
--- a/Makefile
+++ b/Makefile
@@ -25,7 +25,7 @@ LIBDIR = $(DESTDIR)/$(PREFIX)/lib
SHAREDIR = $(DESTDIR)/$(PREFIX)/share/libopencm3/scripts
INSTALL = install
-TARGETS = stm32/f1 stm32/f2 lpc13xx lm3s
+TARGETS = stm32/f1 stm32/f2 stm32/f4 lpc13xx lm3s
# Be silent per default, but 'make V=1' will show all compiler calls.
ifneq ($(V),1)
diff --git a/include/libopencm3/stm32/f4/flash.h b/include/libopencm3/stm32/f4/flash.h
new file mode 100644
index 0000000..15529ea
--- /dev/null
+++ b/include/libopencm3/stm32/f4/flash.h
@@ -0,0 +1,153 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
+ * Copyright (C) 2010 Mark Butler <mbutler@physics.otago.ac.nz>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/*
+ * For details see:
+ * PM0042 Programming manual: STM32F10xxx Flash programming
+ * October 2009, Doc ID 13259 Rev 7
+ * http://www.st.com/stonline/products/literature/pm/13259.pdf
+ */
+
+#ifndef LIBOPENCM3_FLASH_H
+#define LIBOPENCM3_FLASH_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/* --- FLASH registers ----------------------------------------------------- */
+
+#define FLASH_ACR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x00)
+#define FLASH_KEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x04)
+#define FLASH_OPTKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x08)
+#define FLASH_SR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x0C)
+#define FLASH_CR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x10)
+#define FLASH_OPTCR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14)
+
+/* --- FLASH_ACR values ---------------------------------------------------- */
+
+#define FLASH_DCRST (1 << 12)
+#define FLASH_ICRST (1 << 11)
+#define FLASH_DCE (1 << 10)
+#define FLASH_ICE (1 << 9)
+#define FLASH_PRFTEN (1 << 8)
+#define FLASH_LATENCY_0WS 0x00
+#define FLASH_LATENCY_1WS 0x01
+#define FLASH_LATENCY_2WS 0x02
+#define FLASH_LATENCY_3WS 0x03
+#define FLASH_LATENCY_4WS 0x04
+#define FLASH_LATENCY_5WS 0x05
+#define FLASH_LATENCY_6WS 0x06
+#define FLASH_LATENCY_7WS 0x07
+
+/* --- FLASH_SR values ----------------------------------------------------- */
+
+#define FLASH_BSY (1 << 16)
+#define FLASH_PGSERR (1 << 7)
+#define FLASH_PGPERR (1 << 6)
+#define FLASH_PGAERR (1 << 5)
+#define FLASH_WRPERR (1 << 4)
+#define FLASH_OPERR (1 << 1)
+#define FLASH_EOP (1 << 0)
+
+/* --- FLASH_CR values ----------------------------------------------------- */
+
+#define FLASH_LOCK (1 << 31)
+#define FLASH_ERRIE (1 << 25)
+#define FLASH_EOPIE (1 << 24)
+#define FLASH_STRT (1 << 16)
+#define FLASH_MER (1 << 2)
+#define FLASH_SER (1 << 1)
+#define FLASH_PG (1 << 0)
+#define FLASH_SECTOR_0 (0x00 << 3)
+#define FLASH_SECTOR_1 (0x01 << 3)
+#define FLASH_SECTOR_2 (0x02 << 3)
+#define FLASH_SECTOR_3 (0x03 << 3)
+#define FLASH_SECTOR_4 (0x04 << 3)
+#define FLASH_SECTOR_5 (0x05 << 3)
+#define FLASH_SECTOR_6 (0x06 << 3)
+#define FLASH_SECTOR_7 (0x07 << 3)
+#define FLASH_SECTOR_8 (0x08 << 3)
+#define FLASH_SECTOR_9 (0x09 << 3)
+#define FLASH_SECTOR_10 (0x0a << 3)
+#define FLASH_SECTOR_11 (0x0b << 3)
+#define FLASH_PROGRAM_X8 (0x00 << 8)
+#define FLASH_PROGRAM_X16 (0x01 << 8)
+#define FLASH_PROGRAM_X32 (0x02 << 8)
+#define FLASH_PROGRAM_X64 (0x03 << 8)
+
+/* --- FLASH_OPTCR values -------------------------------------------------- */
+
+/* FLASH_OPTCR[27:16]: nWRP */
+/* FLASH_OBR[15:8]: RDP */
+#define FLASH_NRST_STDBY (1 << 7)
+#define FLASH_NRST_STOP (1 << 6)
+#define FLASH_WDG_SW (1 << 5)
+#define FLASH_OPTSTRT (1 << 1)
+#define FLASH_OPTLOCK (1 << 0)
+#define FLASH_BOR_LEVEL_3 (0x00 << 2)
+#define FLASH_BOR_LEVEL_2 (0x01 << 2)
+#define FLASH_BOR_LEVEL_1 (0x02 << 2)
+#define FLASH_BOR_OFF (0x03 << 2)
+
+/* --- FLASH Keys -----------------------------------------------------------*/
+
+#define FLASH_KEY1 ((u32)0x45670123)
+#define FLASH_KEY2 ((u32)0xcdef89ab)
+#define FLASH_OPTKEY1 ((u32)0x08192a3b)
+#define FLASH_OPTKEY2 ((u32)0x4c5d6e7f)
+
+/* --- Function prototypes ------------------------------------------------- */
+
+void flash_dcache_enable(void);
+void flash_dcache_disable(void);
+void flash_icache_enable(void);
+void flash_icache_disable(void);
+void flash_prefetch_enable(void);
+void flash_prefetch_disable(void);
+void flash_dcache_reset(void);
+void flash_icache_reset(void);
+void flash_set_ws(u32 ws);
+void flash_unlock(void);
+void flash_lock(void);
+void flash_clear_pgserr_flag(void);
+void flash_clear_pgperr_flag(void);
+void flash_clear_pgaerr_flag(void);
+void flash_clear_eop_flag(void);
+void flash_clear_wrperr_flag(void);
+void flash_clear_bsy_flag(void);
+void flash_clear_status_flags(void);
+void flash_unlock_option_bytes(void);
+void flash_lock_option_bytes(void);
+void flash_erase_all_sectors(u32 program_size);
+void flash_erase_sector(u32 sector, u32 program_size);
+void flash_program_double_word(u32 address, u64 data, u32 program_size);
+void flash_program_word(u32 address, u32 data, u32 program_size);
+void flash_program_half_word(u32 address, u16 data, u32 program_size);
+void flash_program_byte(u32 address, u8 data, u32 program_size);
+void flash_wait_for_last_operation(void);
+void flash_program_option_bytes(u32 data);
+
+#if 0
+// TODO: Implement support for option bytes
+void flash_erase_option_bytes(void);
+void flash_program_option_bytes(u32 address, u16 data);
+#endif
+
+#endif
diff --git a/include/libopencm3/stm32/f4/gpio.h b/include/libopencm3/stm32/f4/gpio.h
new file mode 100644
index 0000000..7832075
--- /dev/null
+++ b/include/libopencm3/stm32/f4/gpio.h
@@ -0,0 +1,278 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_GPIO_H
+#define LIBOPENCM3_GPIO_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/* --- Convenience macros -------------------------------------------------- */
+
+/* GPIO port base addresses (for convenience) */
+#define GPIOA GPIO_PORT_A_BASE
+#define GPIOB GPIO_PORT_B_BASE
+#define GPIOC GPIO_PORT_C_BASE
+#define GPIOD GPIO_PORT_D_BASE
+#define GPIOE GPIO_PORT_E_BASE
+#define GPIOF GPIO_PORT_F_BASE
+#define GPIOG GPIO_PORT_G_BASE
+#define GPIOH GPIO_PORT_H_BASE
+#define GPIOI GPIO_PORT_I_BASE
+
+/* GPIO number definitions (for convenience) */
+#define GPIO0 (1 << 0)
+#define GPIO1 (1 << 1)
+#define GPIO2 (1 << 2)
+#define GPIO3 (1 << 3)
+#define GPIO4 (1 << 4)
+#define GPIO5 (1 << 5)
+#define GPIO6 (1 << 6)
+#define GPIO7 (1 << 7)
+#define GPIO8 (1 << 8)
+#define GPIO9 (1 << 9)
+#define GPIO10 (1 << 10)
+#define GPIO11 (1 << 11)
+#define GPIO12 (1 << 12)
+#define GPIO13 (1 << 13)
+#define GPIO14 (1 << 14)
+#define GPIO15 (1 << 15)
+#define GPIO_ALL 0xffff
+
+/* --- GPIO registers ------------------------------------------------------ */
+
+/* Port mode register (GPIOx_MODER) */
+#define GPIO_MODER(port) MMIO32(port + 0x00)
+#define GPIOA_MODER GPIO_MODER(GPIOA)
+#define GPIOB_MODER GPIO_MODER(GPIOB)
+#define GPIOC_MODER GPIO_MODER(GPIOC)
+#define GPIOD_MODER GPIO_MODER(GPIOD)
+#define GPIOE_MODER GPIO_MODER(GPIOE)
+#define GPIOF_MODER GPIO_MODER(GPIOF)
+#define GPIOG_MODER GPIO_MODER(GPIOG)
+#define GPIOH_MODER GPIO_MODER(GPIOH)
+#define GPIOI_MODER GPIO_MODER(GPIOI)
+
+/* Port output type register (GPIOx_OTYPER) */
+#define GPIO_OTYPER(port) MMIO32(port + 0x04)
+#define GPIOA_OTYPER GPIO_OTYPER(GPIOA)
+#define GPIOB_OTYPER GPIO_OTYPER(GPIOB)
+#define GPIOC_OTYPER GPIO_OTYPER(GPIOC)
+#define GPIOD_OTYPER GPIO_OTYPER(GPIOD)
+#define GPIOE_OTYPER GPIO_OTYPER(GPIOE)
+#define GPIOF_OTYPER GPIO_OTYPER(GPIOF)
+#define GPIOG_OTYPER GPIO_OTYPER(GPIOG)
+#define GPIOH_OTYPER GPIO_OTYPER(GPIOH)
+#define GPIOI_OTYPER GPIO_OTYPER(GPIOI)
+
+/* Port output speed register (GPIOx_OSPEEDR) */
+#define GPIO_OSPEEDR(port) MMIO32(port + 0x08)
+#define GPIOA_OSPEEDR GPIO_OSPEEDR(GPIOA)
+#define GPIOB_OSPEEDR GPIO_OSPEEDR(GPIOB)
+#define GPIOC_OSPEEDR GPIO_OSPEEDR(GPIOC)
+#define GPIOD_OSPEEDR GPIO_OSPEEDR(GPIOD)
+#define GPIOE_OSPEEDR GPIO_OSPEEDR(GPIOE)
+#define GPIOF_OSPEEDR GPIO_OSPEEDR(GPIOF)
+#define GPIOG_OSPEEDR GPIO_OSPEEDR(GPIOG)
+#define GPIOH_OSPEEDR GPIO_OSPEEDR(GPIOH)
+#define GPIOI_OSPEEDR GPIO_OSPEEDR(GPIOI)
+
+/* Port pull-up/pull-down register (GPIOx_PUPDR) */
+#define GPIO_PUPDR(port) MMIO32(port + 0x0c)
+#define GPIOA_PUPDR GPIO_PUPDR(GPIOA)
+#define GPIOB_PUPDR GPIO_PUPDR(GPIOB)
+#define GPIOC_PUPDR GPIO_PUPDR(GPIOC)
+#define GPIOD_PUPDR GPIO_PUPDR(GPIOD)
+#define GPIOE_PUPDR GPIO_PUPDR(GPIOE)
+#define GPIOF_PUPDR GPIO_PUPDR(GPIOF)
+#define GPIOG_PUPDR GPIO_PUPDR(GPIOG)
+#define GPIOH_PUPDR GPIO_PUPDR(GPIOH)
+#define GPIOI_PUPDR GPIO_PUPDR(GPIOI)
+
+/* Port input data register (GPIOx_IDR) */
+#define GPIO_IDR(port) MMIO32(port + 0x10)
+#define GPIOA_IDR GPIO_IDR(GPIOA)
+#define GPIOB_IDR GPIO_IDR(GPIOB)
+#define GPIOC_IDR GPIO_IDR(GPIOC)
+#define GPIOD_IDR GPIO_IDR(GPIOD)
+#define GPIOE_IDR GPIO_IDR(GPIOE)
+#define GPIOF_IDR GPIO_IDR(GPIOF)
+#define GPIOG_IDR GPIO_IDR(GPIOG)
+#define GPIOH_IDR GPIO_IDR(GPIOH)
+#define GPIOI_IDR GPIO_IDR(GPIOI)
+
+/* Port output data register (GPIOx_ODR) */
+#define GPIO_ODR(port) MMIO32(port + 0x14)
+#define GPIOA_ODR GPIO_ODR(GPIOA)
+#define GPIOB_ODR GPIO_ODR(GPIOB)
+#define GPIOC_ODR GPIO_ODR(GPIOC)
+#define GPIOD_ODR GPIO_ODR(GPIOD)
+#define GPIOE_ODR GPIO_ODR(GPIOE)
+#define GPIOF_ODR GPIO_ODR(GPIOF)
+#define GPIOG_ODR GPIO_ODR(GPIOG)
+#define GPIOH_ODR GPIO_ODR(GPIOH)
+#define GPIOI_ODR GPIO_ODR(GPIOI)
+
+/* Port bit set/reset register (GPIOx_BSRR) */
+#define GPIO_BSRR(port) MMIO32(port + 0x18)
+#define GPIOA_BSRR GPIO_BSRR(GPIOA)
+#define GPIOB_BSRR GPIO_BSRR(GPIOB)
+#define GPIOC_BSRR GPIO_BSRR(GPIOC)
+#define GPIOD_BSRR GPIO_BSRR(GPIOD)
+#define GPIOE_BSRR GPIO_BSRR(GPIOE)
+#define GPIOF_BSRR GPIO_BSRR(GPIOF)
+#define GPIOG_BSRR GPIO_BSRR(GPIOG)
+#define GPIOH_BSRR GPIO_BSRR(GPIOH)
+#define GPIOI_BSRR GPIO_BSRR(GPIOI)
+
+/* Port configuration lock register (GPIOx_LCKR) */
+#define GPIO_LCKR(port) MMIO32(port + 0x1c)
+#define GPIOA_LCKR GPIO_LCKR(GPIOA)
+#define GPIOB_LCKR GPIO_LCKR(GPIOB)
+#define GPIOC_LCKR GPIO_LCKR(GPIOC)
+#define GPIOD_LCKR GPIO_LCKR(GPIOD)
+#define GPIOE_LCKR GPIO_LCKR(GPIOE)
+#define GPIOF_LCKR GPIO_LCKR(GPIOF)
+#define GPIOG_LCKR GPIO_LCKR(GPIOG)
+#define GPIOH_LCKR GPIO_LCKR(GPIOH)
+#define GPIOI_LCKR GPIO_LCKR(GPIOI)
+
+/* Alternate function low register (GPIOx_AFRL) */
+#define GPIO_AFRL(port) MMIO32(port + 0x20)
+#define GPIOA_AFRL GPIO_AFRL(GPIOA)
+#define GPIOB_AFRL GPIO_AFRL(GPIOB)
+#define GPIOC_AFRL GPIO_AFRL(GPIOC)
+#define GPIOD_AFRL GPIO_AFRL(GPIOD)
+#define GPIOE_AFRL GPIO_AFRL(GPIOE)
+#define GPIOF_AFRL GPIO_AFRL(GPIOF)
+#define GPIOG_AFRL GPIO_AFRL(GPIOG)
+#define GPIOH_AFRL GPIO_AFRL(GPIOH)
+#define GPIOI_AFRL GPIO_AFRL(GPIOI)
+
+/* Alternate function high register (GPIOx_AFRH) */
+#define GPIO_AFRH(port) MMIO32(port + 0x24)
+#define GPIOA_AFRH GPIO_AFRH(GPIOA)
+#define GPIOB_AFRH GPIO_AFRH(GPIOB)
+#define GPIOC_AFRH GPIO_AFRH(GPIOC)
+#define GPIOD_AFRH GPIO_AFRH(GPIOD)
+#define GPIOE_AFRH GPIO_AFRH(GPIOE)
+#define GPIOF_AFRH GPIO_AFRH(GPIOF)
+#define GPIOG_AFRH GPIO_AFRH(GPIOG)
+#define GPIOH_AFRH GPIO_AFRH(GPIOH)
+#define GPIOI_AFRH GPIO_AFRH(GPIOI)
+
+/* --- GPIOx_MODER values -------------------------------------------------- */
+
+#define GPIO_MODE(n, mode) (mode << (2*(n)))
+#define GPIO_MODE_MASK(n) (0x3 << (2*(n)))
+#define GPIO_MODE_INPUT 0x0
+#define GPIO_MODE_OUTPUT 0x1
+#define GPIO_MODE_AF 0x2
+#define GPIO_MODE_ANALOG 0x3
+
+/* --- GPIOx_OTYPER values ------------------------------------------------- */
+
+#define GPIO_OTYPE_PP 0x0
+#define GPIO_OTYPE_OD 0x1
+
+/* --- GPIOx_OSPEEDR values ------------------------------------------------ */
+
+#define GPIO_OSPEED(n, speed) (speed << (2*(n)))
+#define GPIO_OSPEED_MASK(n) (0x3 << (2*(n)))
+#define GPIO_OSPEED_2MHZ 0x0
+#define GPIO_OSPEED_25MHZ 0x1
+#define GPIO_OSPEED_50MHZ 0x2
+#define GPIO_OSPEED_100MHZ 0x3
+
+/* --- GPIOx_PUPDR values -------------------------------------------------- */
+
+#define GPIO_PUPD(n, pupd) (pupd << (2*(n)))
+#define GPIO_PUPD_MASK(n) (0x3 << (2*(n)))
+#define GPIO_PUPD_NONE 0x0
+#define GPIO_PUPD_PULLUP 0x1
+#define GPIO_PUPD_PULLDOWN 0x2
+
+/* --- GPIOx_IDR values ---------------------------------------------------- */
+
+/* GPIOx_IDR[15:0]: IDRy[15:0]: Port input data (y = 0..15) */
+
+/* --- GPIOx_ODR values ---------------------------------------------------- */
+
+/* GPIOx_ODR[15:0]: ODRy[15:0]: Port output data (y = 0..15) */
+
+/* --- GPIOx_BSRR values --------------------------------------------------- */
+
+/* GPIOx_BSRR[31:16]: BRy: Port x reset bit y (y = 0..15) */
+/* GPIOx_BSRR[15:0]: BSy: Port x set bit y (y = 0..15) */
+
+/* --- GPIOx_LCKR values --------------------------------------------------- */
+
+#define GPIO_LCKK (1 << 16)
+/* GPIOx_LCKR[15:0]: LCKy: Port x lock bit y (y = 0..15) */
+
+/* --- GPIOx_AFRL/H values ------------------------------------------------- */
+
+/* Note: AFRL is used for bits 0..7, AFRH is used for 8..15 */
+/* See Datasheet Table 6 (pg. 48) for alternate function mappings. */
+
+#define GPIO_AFR(n, af) (af << ((n)*4))
+#define GPIO_AFR_MASK(n) (0xf << ((n)*4))
+#define GPIO_AF0 0x0
+#define GPIO_AF1 0x1
+#define GPIO_AF2 0x2
+#define GPIO_AF3 0x3
+#define GPIO_AF4 0x4
+#define GPIO_AF5 0x5
+#define GPIO_AF6 0x6
+#define GPIO_AF7 0x7
+#define GPIO_AF8 0x8
+#define GPIO_AF9 0x9
+#define GPIO_AF10 0xa
+#define GPIO_AF11 0xb
+#define GPIO_AF12 0xc
+#define GPIO_AF13 0xd
+#define GPIO_AF14 0xe
+#define GPIO_AF15 0xf
+
+/* Note: EXTI source selection is now in the SYSCFG peripheral. */
+
+/* --- Function prototypes ------------------------------------------------- */
+
+/*
+ * Note: The F2 series has a completely new GPIO peripheral with different
+ * configuration options. Here we implement a different API partly to more
+ * closely match the peripheral capabilities and also to deliberately break
+ * compatibility with old F1 code so there is no confusion with similar
+ * sounding functions that have very different functionality.
+ */
+
+void gpio_mode_setup(u32 gpioport, u8 mode, u8 pull_up_down, u16 gpios);
+void gpio_set_output_options(u32 gpioport, u8 otype, u8 speed, u16 gpios);
+void gpio_set_af(u32 gpioport, u8 alt_func_num, u16 gpios);
+
+/* This part of the API is compatible with the F1 series ------------------- */
+void gpio_set(u32 gpioport, u16 gpios);
+void gpio_clear(u32 gpioport, u16 gpios);
+u16 gpio_get(u32 gpioport, u16 gpios);
+void gpio_toggle(u32 gpioport, u16 gpios);
+u16 gpio_port_read(u32 gpioport);
+void gpio_port_write(u32 gpioport, u16 data);
+void gpio_port_config_lock(u32 gpioport, u16 gpios);
+
+#endif
diff --git a/include/libopencm3/stm32/f4/memorymap.h b/include/libopencm3/stm32/f4/memorymap.h
new file mode 100644
index 0000000..9fe77fa
--- /dev/null
+++ b/include/libopencm3/stm32/f4/memorymap.h
@@ -0,0 +1,131 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_MEMORYMAP_H
+#define LIBOPENCM3_MEMORYMAP_H
+
+#include <libopencm3/cm3/memorymap.h>
+
+/* --- STM32F20x specific peripheral definitions ------------------------------- */
+
+/* Memory map for all busses */
+#define PERIPH_BASE 0x40000000
+#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)
+#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)
+#define PERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000)
+#define PERIPH_BASE_AHB2 0x50000000
+#define PERIPH_BASE_AHB3 0x60000000
+
+/* Register boundary addresses */
+
+/* APB1 */
+#define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000)
+#define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400)
+#define TIM4_BASE (PERIPH_BASE_APB1 + 0x0800)
+#define TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00)
+#define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000)
+#define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400)
+#define TIM12_BASE (PERIPH_BASE_APB1 + 0x1800)
+#define TIM13_BASE (PERIPH_BASE_APB1 + 0x1c00)
+#define TIM14_BASE (PERIPH_BASE_APB1 + 0x2000)
+/* PERIPH_BASE_APB1 + 0x2400 (0x4000 2400 - 0x4000 27FF): Reserved */
+#define RTC_BASE (PERIPH_BASE_APB1 + 0x2800)
+#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00)
+#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000)
+/* PERIPH_BASE_APB1 + 0x3400 (0x4000 3400 - 0x4000 37FF): Reserved */
+#define SPI2_I2S_BASE (PERIPH_BASE_APB1 + 0x3800)
+#define SPI3_I2S_BASE (PERIPH_BASE_APB1 + 0x3c00)
+/* PERIPH_BASE_APB1 + 0x4000 (0x4000 4000 - 0x4000 3FFF): Reserved */
+#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400)
+#define USART3_BASE (PERIPH_BASE_APB1 + 0x4800)
+#define UART4_BASE (PERIPH_BASE_APB1 + 0x4c00)
+#define UART5_BASE (PERIPH_BASE_APB1 + 0x5000)
+#define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400)
+#define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800)
+#define I2C3_BASE (PERIPH_BASE_APB1 + 0x5C00)
+/* PERIPH_BASE_APB1 + 0x6000 (0x4000 6000 - 0x4000 63FF): Reserved */
+#define BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400)
+#define BX_CAN2_BASE (PERIPH_BASE_APB1 + 0x6800)
+/* PERIPH_BASE_APB1 + 0x6C00 (0x4000 6C00 - 0x4000 6FFF): Reserved */
+#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)
+#define DAC_BASE (PERIPH_BASE_APB1 + 0x7400)
+/* PERIPH_BASE_APB1 + 0x7800 (0x4000 7800 - 0x4000 FFFF): Reserved */
+
+/* APB2 */
+#define TIM1_BASE (PERIPH_BASE_APB2 + 0x0000)
+#define TIM8_BASE (PERIPH_BASE_APB2 + 0x0400)
+/* PERIPH_BASE_APB2 + 0x0800 (0x4001 0800 - 0x4001 0FFF): Reserved */
+#define USART1_BASE (PERIPH_BASE_APB2 + 0x1000)
+#define USART6_BASE (PERIPH_BASE_APB2 + 0x1400)
+/* PERIPH_BASE_APB2 + 0x1800 (0x4001 1800 - 0x4001 1FFF): Reserved */
+#define ADC1_BASE (PERIPH_BASE_APB2 + 0x2000)
+#define ADC2_BASE (PERIPH_BASE_APB2 + 0x2000)
+#define ADC3_BASE (PERIPH_BASE_APB2 + 0x2000)
+/* PERIPH_BASE_APB2 + 0x2400 (0x4001 2400 - 0x4001 27FF): Reserved */
+#define SDIO_BASE (PERIPH_BASE_APB2 + 0x2800)
+/* PERIPH_BASE_APB2 + 0x2C00 (0x4001 2C00 - 0x4001 2FFF): Reserved */
+#define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000)
+/* PERIPH_BASE_APB2 + 0x3400 (0x4001 3400 - 0x4001 37FF): Reserved */
+#define SYSCFG_BASE (PERIPH_BASE_APB2 + 0x3800)
+#define EXTI_BASE (PERIPH_BASE_APB2 + 0x3C00)
+#define TIM9_BASE (PERIPH_BASE_APB2 + 0x4000)
+#define TIM10_BASE (PERIPH_BASE_APB2 + 0x4400)
+#define TIM11_BASE (PERIPH_BASE_APB2 + 0x4800)
+/* PERIPH_BASE_APB2 + 0x4C00 (0x4001 4C00 - 0x4001 FFFF): Reserved */
+
+/* AHB1 */
+#define GPIO_PORT_A_BASE (PERIPH_BASE_AHB1 + 0x0000)
+#define GPIO_PORT_B_BASE (PERIPH_BASE_AHB1 + 0x0400)
+#define GPIO_PORT_C_BASE (PERIPH_BASE_AHB1 + 0x0800)
+#define GPIO_PORT_D_BASE (PERIPH_BASE_AHB1 + 0x0C00)
+#define GPIO_PORT_E_BASE (PERIPH_BASE_AHB1 + 0x1000)
+#define GPIO_PORT_F_BASE (PERIPH_BASE_AHB1 + 0x1400)
+#define GPIO_PORT_G_BASE (PERIPH_BASE_AHB1 + 0x1800)
+#define GPIO_PORT_H_BASE (PERIPH_BASE_AHB1 + 0x1C00)
+#define GPIO_PORT_I_BASE (PERIPH_BASE_AHB1 + 0x2000)
+/* PERIPH_BASE_AHB1 + 0x2400 (0x4002 2400 - 0x4002 2FFF): Reserved */
+#define CRC_BASE (PERIPH_BASE_AHB1 + 0x3000)
+/* PERIPH_BASE_AHB1 + 0x3400 (0x4002 3400 - 0x4002 37FF): Reserved */
+#define RCC_BASE (PERIPH_BASE_AHB1 + 0x3800)
+#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x3C00)
+#define BKPSRAM_BASE (PERIPH_BASE_AHB1 + 0x4000)
+/* PERIPH_BASE_AHB1 + 0x5000 (0x4002 5000 - 0x4002 5FFF): Reserved */
+#define DMA1_BASE (PERIPH_BASE_AHB1 + 0x6000)
+#define DMA2_BASE (PERIPH_BASE_AHB1 + 0x6400)
+/* PERIPH_BASE_AHB1 + 0x6800 (0x4002 6800 - 0x4002 7FFF): Reserved */
+#define ETHERNET_BASE (PERIPH_BASE_AHB1 + 0x8000)
+/* PERIPH_BASE_AHB1 + 0x9400 (0x4002 9400 - 0x4003 FFFF): Reserved */
+#define USB_OTG_HS_BASE (PERIPH_BASE_AHB1 + 0x20000)
+/* PERIPH_BASE_AHB1 + 0x60000 (0x4008 0000 - 0x4FFF FFFF): Reserved */
+
+/* AHB2 */
+#define USB_OTG_FS_BASE (PERIPH_BASE_AHB2 + 0x0000)
+/* PERIPH_BASE_AHB2 + 0x40000 (0x5004 0000 - 0x5004 FFFF): Reserved */
+#define DCMI_BASE (PERIPH_BASE_AHB2 + 0x50000)
+/* PERIPH_BASE_AHB2 + 0x50400 (0x5005 0400 - 0x5006 07FF): Reserved */
+#define RNG_BASE (PERIPH_BASE_AHB2 + 0x60800)
+/* PERIPH_BASE_AHB2 + 0x61000 (0x5006 1000 - 0x5FFF FFFF): Reserved */
+
+/* AHB3 */
+#define FSMC_BASE (PERIPH_BASE_AHB3 + 0x40000000)
+
+/* PPIB */
+#define DBGMCU_BASE (PPBI_BASE + 0x00042000)
+
+#endif
diff --git a/include/libopencm3/stm32/f4/nvic_f4.h b/include/libopencm3/stm32/f4/nvic_f4.h
new file mode 100644
index 0000000..6375d41
--- /dev/null
+++ b/include/libopencm3/stm32/f4/nvic_f4.h
@@ -0,0 +1,112 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_NVIC_F4_H
+#define LIBOPENCM3_NVIC_F4_H
+
+/* --- IRQ channel numbers-------------------------------------------------- */
+
+/* Note: These F2 specific user interrupt definitions supplement the
+ * general NVIC definitions in ../nvic.h
+ */
+
+/* User Interrupts */
+#define NVIC_NVIC_WWDG_IRQ 0
+#define NVIC_PVD_IRQ 1
+#define NVIC_TAMP_STAMP_IRQ 2
+#define NVIC_RTC_WKUP_IRQ 3
+#define NVIC_FLASH_IRQ 4
+#define NVIC_RCC_IRQ 5
+#define NVIC_EXTI0_IRQ 6
+#define NVIC_EXTI1_IRQ 7
+#define NVIC_EXTI2_IRQ 8
+#define NVIC_EXTI3_IRQ 9
+#define NVIC_EXTI4_IRQ 10
+#define NVIC_DMA1_STREAM0_IRQ 11
+#define NVIC_DMA1_STREAM1_IRQ 12
+#define NVIC_DMA1_STREAM2_IRQ 13
+#define NVIC_DMA1_STREAM3_IRQ 14
+#define NVIC_DMA1_STREAM4_IRQ 15
+#define NVIC_DMA1_STREAM5_IRQ 16
+#define NVIC_DMA1_STREAM6_IRQ 17
+#define NVIC_ADC_IRQ 18
+#define NVIC_CAN1_TX_IRQ 19
+#define NVIC_CAN1_RX0_IRQ 20
+#define NVIC_CAN1_RX1_IRQ 21
+#define NVIC_CAN1_SCE_IRQ 22
+#define NVIC_EXTI9_5_IRQ 23
+#define NVIC_TIM1_BRK_TIM9_IRQ 24
+#define NVIC_TIM1_UP_TIM10_IRQ 25
+#define NVIC_TIM1_TRG_COM_TIM11_IRQ 26
+#define NVIC_TIM1_CC_IRQ 27
+#define NVIC_TIM2_IRQ 28
+#define NVIC_TIM3_IRQ 29
+#define NVIC_TIM4_IRQ 30
+#define NVIC_I2C1_EV_IRQ 31
+#define NVIC_I2C1_ER_IRQ 32
+#define NVIC_I2C2_EV_IRQ 33
+#define NVIC_I2C2_ER_IRQ 34
+#define NVIC_SPI1_IRQ 35
+#define NVIC_SPI2_IRQ 36
+#define NVIC_USART1_IRQ 37
+#define NVIC_USART2_IRQ 38
+#define NVIC_USART3_IRQ 39
+#define NVIC_EXTI15_10_IRQ 40
+#define NVIC_RTC_ALARM_IRQ 41
+#define NVIC_USB_FS_WKUP_IRQ 42
+#define NVIC_TIM8_BRK_TIM12_IRQ 43
+#define NVIC_TIM8_UP_TIM13_IRQ 44
+#define NVIC_TIM8_TRG_COM_TIM14_IRQ 45
+#define NVIC_TIM8_CC_IRQ 46
+#define NVIC_DMA1_STREAM7_IRQ 47
+#define NVIC_FSMC_IRQ 48
+#define NVIC_SDIO_IRQ 49
+#define NVIC_TIM5_IRQ 50
+#define NVIC_SPI3_IRQ 51
+#define NVIC_USART4_IRQ 52
+#define NVIC_USART5_IRQ 53
+#define NVIC_TIM6_DAC_IRQ 54
+#define NVIC_TIM7_IRQ 55
+#define NVIC_DMA2_STREAM0_IRQ 56
+#define NVIC_DMA2_STREAM1_IRQ 57
+#define NVIC_DMA2_STREAM2_IRQ 58
+#define NVIC_DMA2_STREAM3_IRQ 59
+#define NVIC_DMA2_STREAM4_IRQ 60
+#define NVIC_ETH_IRQ 61
+#define NVIC_ETH_WKUP_IRQ 62
+#define NVIC_CAN2_TX_IRQ 63
+#define NVIC_CAN2_RX0_IRQ 64
+#define NVIC_CAN2_RX1_IRQ 65
+#define NVIC_CAN2_SCE_IRQ 66
+#define NVIC_OTG_FS_IRQ 67
+#define NVIC_DMA2_STREAM5_IRQ 68
+#define NVIC_DMA2_STREAM6_IRQ 69
+#define NVIC_DMA2_STREAM7_IRQ 70
+#define NVIC_USART6_IRQ 71
+#define NVIC_I2C3_EV_IRQ 72
+#define NVIC_I2C3_ER_IRQ 73
+#define NVIC_OTG_HS_EP1_OUT_IRQ 74
+#define NVIC_OTG_HS_EP1_IN_IRQ 75
+#define NVIC_OTG_HS_WKUP_IRQ 76
+#define NVIC_OTG_HS_IRQ 77
+#define NVIC_DCMI_IRQ 78
+#define NVIC_CRYP_IRQ 79
+#define NVIC_HASH_RNG_IRQ 80
+
+#endif
diff --git a/include/libopencm3/stm32/f4/pwr.h b/include/libopencm3/stm32/f4/pwr.h
new file mode 100644
index 0000000..66cfc10
--- /dev/null
+++ b/include/libopencm3/stm32/f4/pwr.h
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2011 Stephen Caudle <scaudle@doceme.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_PWR_F4_H
+#define LIBOPENCM3_PWR_F4_H
+
+#include <libopencm3/stm32/pwr.h>
+
+/*
+ * This file extends the version in stm_common with definitions only
+ * applicable to the STM32F4 series of devices.
+ */
+
+/* --- PWR_CR values ------------------------------------------------------- */
+
+/* VOS: Regulator voltage scaling output selection */
+#define PWR_CR_VOS (1 << 14)
+
+/* FPDS: Flash power down in stop mode, only available in F2 family devices. */
+#define PWR_CR_FPDS (1 << 9)
+
+/* --- PWR_CSR values ------------------------------------------------------ */
+
+/* VOSRDY: Regulator voltage scaling output selection ready */
+#define PWR_CSR_VOSRDY (1 << 14)
+
+/* BRE: Backup regulator enable */
+#define PWR_CSR_BRE (1 << 9)
+
+/* BRR: Backup regulator ready */
+#define PWR_CSR_BRR (1 << 3)
+
+/* --- Function prototypes ------------------------------------------------- */
+
+typedef enum {
+ SCALE1, SCALE2
+} vos_scale_t;
+
+void pwr_set_vos_scale(vos_scale_t scale);
+
+#endif
diff --git a/include/libopencm3/stm32/f4/rcc.h b/include/libopencm3/stm32/f4/rcc.h
new file mode 100644
index 0000000..debeeda
--- /dev/null
+++ b/include/libopencm3/stm32/f4/rcc.h
@@ -0,0 +1,515 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+ * Copyright (C) 2009 Federico Ruiz-Ugalde <memeruiz at gmail dot com>
+ * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
+ * Copyright (C) 2011 Stephen Caudle <scaudle@doceme.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_RCC_H
+#define LIBOPENCM3_RCC_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/* --- RCC registers ------------------------------------------------------- */
+
+#define RCC_CR MMIO32(RCC_BASE + 0x00)
+#define RCC_PLLCFGR MMIO32(RCC_BASE + 0x04)
+#define RCC_CFGR MMIO32(RCC_BASE + 0x08)
+#define RCC_CIR MMIO32(RCC_BASE + 0x0c)
+#define RCC_AHB1RSTR MMIO32(RCC_BASE + 0x10)
+#define RCC_AHB2RSTR MMIO32(RCC_BASE + 0x14)
+#define RCC_AHB3RSTR MMIO32(RCC_BASE + 0x18)
+/* RCC_BASE + 0x1c Reserved */
+#define RCC_APB1RSTR MMIO32(RCC_BASE + 0x20)
+#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x24)
+/* RCC_BASE + 0x28 Reserved */
+/* RCC_BASE + 0x2c Reserved */
+#define RCC_AHB1ENR MMIO32(RCC_BASE + 0x30)
+#define RCC_AHB2ENR MMIO32(RCC_BASE + 0x34)
+#define RCC_AHB3ENR MMIO32(RCC_BASE + 0x38)
+/* RCC_BASE + 0x3c Reserved */
+#define RCC_APB1ENR MMIO32(RCC_BASE + 0x40)
+#define RCC_APB2ENR MMIO32(RCC_BASE + 0x44)
+/* RCC_BASE + 0x48 Reserved */
+/* RCC_BASE + 0x4c Reserved */
+#define RCC_AHB1LPENR MMIO32(RCC_BASE + 0x50)
+#define RCC_AHB2LPENR MMIO32(RCC_BASE + 0x54)
+#define RCC_AHB3LPENR MMIO32(RCC_BASE + 0x58)
+/* RCC_BASE + 0x5c Reserved */
+#define RCC_APB1LPENR MMIO32(RCC_BASE + 0x60)
+#define RCC_APB2LPENR MMIO32(RCC_BASE + 0x64)
+/* RCC_BASE + 0x68 Reserved */
+/* RCC_BASE + 0x6c Reserved */
+#define RCC_BDCR MMIO32(RCC_BASE + 0x70)
+#define RCC_CSR MMIO32(RCC_BASE + 0x74)
+/* RCC_BASE + 0x78 Reserved */
+/* RCC_BASE + 0x7c Reserved */
+#define RCC_SSCGR MMIO32(RCC_BASE + 0x80)
+#define RCC_PLLI2SCFGR MMIO32(RCC_BASE + 0x84)
+
+/* --- RCC_CR values ------------------------------------------------------- */
+
+#define RCC_CR_PLLI2SRDY (1 << 27)
+#define RCC_CR_PLLI2SON (1 << 26)
+#define RCC_CR_PLLRDY (1 << 25)
+#define RCC_CR_PLLON (1 << 24)
+#define RCC_CR_CSSON (1 << 19)
+#define RCC_CR_HSEBYP (1 << 18)
+#define RCC_CR_HSERDY (1 << 17)
+#define RCC_CR_HSEON (1 << 16)
+/* HSICAL: [15:8] */
+/* HSITRIM: [7:3] */
+#define RCC_CR_HSIRDY (1 << 1)
+#define RCC_CR_HSION (1 << 0)
+
+/* --- RCC_PLLCFGR values ------------------------------------------------------- */
+
+/* PLLQ: [27:24] */
+#define RCC_PLLCFGR_PLLQ_SHIFT 24
+#define RCC_PLLCFGR_PLLSRC (1 << 22)
+/* PLLP: [17:16] */
+#define RCC_PLLCFGR_PLLP_SHIFT 16
+/* PLLN: [14:6] */
+#define RCC_PLLCFGR_PLLN_SHIFT 6
+/* PLLM: [5:0] */
+#define RCC_PLLCFGR_PLLM_SHIFT 0
+
+/* --- RCC_CFGR values ----------------------------------------------------- */
+
+/* MCO2: Microcontroller clock output 2 */
+#define RCC_CFGR_MCO2_SHIFT 30
+#define RCC_CFGR_MCO2_SYSCLK 0x0
+#define RCC_CFGR_MCO2_PLLI2S 0x1
+#define RCC_CFGR_MCO2_HSE 0x2
+#define RCC_CFGR_MCO2_PLL 0x3
+
+/* MCO1/2PRE: MCO Prescalers */
+#define RCC_CFGR_MCO2PRE_SHIFT 27
+#define RCC_CFGR_MCO1PRE_SHIFT 24
+#define RCC_CFGR_MCOPRE_DIV_NONE 0x0
+#define RCC_CFGR_MCOPRE_DIV_2 0x4
+#define RCC_CFGR_MCOPRE_DIV_3 0x5
+#define RCC_CFGR_MCOPRE_DIV_4 0x6
+#define RCC_CFGR_MCOPRE_DIV_5 0x7
+
+/* I2SSRC: I2S clock selection */
+#define RCC_CFGR_I2SSRC (1 << 23)
+
+/* MCO1: Microcontroller clock output 1 */
+#define RCC_CFGR_MCO1_SHIFT 21
+#define RCC_CFGR_MCO1_HSI 0x0
+#define RCC_CFGR_MCO1_LSE 0x1
+#define RCC_CFGR_MCO1_HSE 0x2
+#define RCC_CFGR_MCO1_PLL 0x3
+
+/* RTCPRE: HSE division factor for RTC clock */
+#define RCC_CFGR_RTCPRE_SHIFT 21
+
+/* PPRE1/2: APB high-speed prescalers */
+#define RCC_CFGR_PPRE2_SHIFT 13
+#define RCC_CFGR_PPRE1_SHIFT 10
+#define RCC_CFGR_PPRE_DIV_NONE 0x0
+#define RCC_CFGR_PPRE_DIV_2 0x4
+#define RCC_CFGR_PPRE_DIV_4 0x5
+#define RCC_CFGR_PPRE_DIV_8 0x6
+#define RCC_CFGR_PPRE_DIV_16 0x7
+
+/* HPRE: AHB high-speed prescaler */
+#define RCC_CFGR_HPRE_SHIFT 4
+#define RCC_CFGR_HPRE_DIV_NONE 0x0
+#define RCC_CFGR_HPRE_DIV_2 (0x8+0)
+#define RCC_CFGR_HPRE_DIV_4 (0x8+1)
+#define RCC_CFGR_HPRE_DIV_8 (0x8+2)
+#define RCC_CFGR_HPRE_DIV_16 (0x8+3)
+#define RCC_CFGR_HPRE_DIV_64 (0x8+4)
+#define RCC_CFGR_HPRE_DIV_128 (0x8+5)
+#define RCC_CFGR_HPRE_DIV_256 (0x8+6)
+#define RCC_CFGR_HPRE_DIV_512 (0x8+7)
+
+/* SWS: System clock switch status */
+#define RCC_CFGR_SWS_SHIFT 2
+#define RCC_CFGR_SWS_HSI 0x0
+#define RCC_CFGR_SWS_HSE 0x1
+#define RCC_CFGR_SWS_PLL 0x2
+
+/* SW: System clock switch */
+#define RCC_CFGR_SW_SHIFT 0
+#define RCC_CFGR_SW_HSI 0x0
+#define RCC_CFGR_SW_HSE 0x1
+#define RCC_CFGR_SW_PLL 0x2
+
+/* --- RCC_CIR values ------------------------------------------------------ */
+
+/* Clock security system interrupt clear bit */
+#define RCC_CIR_CSSC (1 << 23)
+
+/* OSC ready interrupt clear bits */
+#define RCC_CIR_PLLI2SRDYC (1 << 21)
+#define RCC_CIR_PLLRDYC (1 << 20)
+#define RCC_CIR_HSERDYC (1 << 19)
+#define RCC_CIR_HSIRDYC (1 << 18)
+#define RCC_CIR_LSERDYC (1 << 17)
+#define RCC_CIR_LSIRDYC (1 << 16)
+
+/* OSC ready interrupt enable bits */
+#define RCC_CIR_PLLI2SRDYIE (1 << 13)
+#define RCC_CIR_PLLRDYIE (1 << 12)
+#define RCC_CIR_HSERDYIE (1 << 11)
+#define RCC_CIR_HSIRDYIE (1 << 10)
+#define RCC_CIR_LSERDYIE (1 << 9)
+#define RCC_CIR_LSIRDYIE (1 << 8)
+
+/* Clock security system interrupt flag bit */
+#define RCC_CIR_CSSF (1 << 7)
+
+/* OSC ready interrupt flag bits */
+#define RCC_CIR_PLLI2SRDYF (1 << 5)
+#define RCC_CIR_PLLRDYF (1 << 4)
+#define RCC_CIR_HSERDYF (1 << 3)
+#define RCC_CIR_HSIRDYF (1 << 2)
+#define RCC_CIR_LSERDYF (1 << 1)
+#define RCC_CIR_LSIRDYF (1 << 0)
+
+/* --- RCC_AHB1RSTR values ------------------------------------------------- */
+
+#define RCC_AHB1RSTR_OTGHSRST (1 << 29)
+#define RCC_AHB1RSTR_ETHMACRST (1 << 25)
+#define RCC_AHB1RSTR_DMA2RST (1 << 22)
+#define RCC_AHB1RSTR_DMA1RST (1 << 21)
+#define RCC_AHB1RSTR_CRCRST (1 << 12)
+#define RCC_AHB1RSTR_IOPIRST (1 << 8)
+#define RCC_AHB1RSTR_IOPHRST (1 << 7)
+#define RCC_AHB1RSTR_IOPGRST (1 << 6)
+#define RCC_AHB1RSTR_IOPFRST (1 << 5)
+#define RCC_AHB1RSTR_IOPERST (1 << 4)
+#define RCC_AHB1RSTR_IOPDRST (1 << 3)
+#define RCC_AHB1RSTR_IOPCRST (1 << 2)
+#define RCC_AHB1RSTR_IOPBRST (1 << 1)
+#define RCC_AHB1RSTR_IOPARST (1 << 0)
+
+/* --- RCC_AHB2RSTR values ------------------------------------------------- */
+
+#define RCC_AHB2RSTR_OTGFSRST (1 << 7)
+#define RCC_AHB2RSTR_RNGRST (1 << 6)
+#define RCC_AHB2RSTR_HASHRST (1 << 5)
+#define RCC_AHB2RSTR_CRYPRST (1 << 4)
+#define RCC_AHB2RSTR_DCMIRST (1 << 0)
+
+/* --- RCC_AHB3RSTR values ------------------------------------------------- */
+
+#define RCC_AHB3RSTR_FSMCRST (1 << 0)
+
+/* --- RCC_APB1RSTR values ------------------------------------------------- */
+
+#define RCC_APB1RSTR_DACRST (1 << 29)
+#define RCC_APB1RSTR_PWRRST (1 << 28)
+#define RCC_APB1RSTR_CAN2RST (1 << 26)
+#define RCC_APB1RSTR_CAN1RST (1 << 25)
+#define RCC_APB1RSTR_I2C3RST (1 << 23)
+#define RCC_APB1RSTR_I2C2RST (1 << 22)
+#define RCC_APB1RSTR_I2C1RST (1 << 21)
+#define RCC_APB1RSTR_USART5RST (1 << 20)
+#define RCC_APB1RSTR_USART4RST (1 << 19)
+#define RCC_APB1RSTR_USART3RST (1 << 18)
+#define RCC_APB1RSTR_USART2RST (1 << 17)
+#define RCC_APB1RSTR_SPI3RST (1 << 15)
+#define RCC_APB1RSTR_SPI2RST (1 << 14)
+#define RCC_APB1RSTR_WWDGRST (1 << 11)
+#define RCC_APB1RSTR_TIM14RST (1 << 8)
+#define RCC_APB1RSTR_TIM13RST (1 << 7)
+#define RCC_APB1RSTR_TIM12RST (1 << 6)
+#define RCC_APB1RSTR_TIM7RST (1 << 5)
+#define RCC_APB1RSTR_TIM6RST (1 << 4)
+#define RCC_APB1RSTR_TIM5RST (1 << 3)
+#define RCC_APB1RSTR_TIM4RST (1 << 2)
+#define RCC_APB1RSTR_TIM3RST (1 << 1)
+#define RCC_APB1RSTR_TIM2RST (1 << 0)
+
+/* --- RCC_APB2RSTR values ------------------------------------------------- */
+
+#define RCC_APB2RSTR_TIM11RST (1 << 18)
+#define RCC_APB2RSTR_TIM10RST (1 << 17)
+#define RCC_APB2RSTR_TIM9RST (1 << 16)
+#define RCC_APB2RSTR_SYSCFGRST (1 << 14)
+#define RCC_APB2RSTR_SPI1RST (1 << 12)
+#define RCC_APB2RSTR_SDIORST (1 << 11)
+#define RCC_APB2RSTR_ADCRST (1 << 8)
+#define RCC_APB2RSTR_USART6RST (1 << 5)
+#define RCC_APB2RSTR_USART1RST (1 << 4)
+#define RCC_APB2RSTR_TIM8RST (1 << 1)
+#define RCC_APB2RSTR_TIM1RST (1 << 0)
+
+/* --- RCC_AHB1ENR values ------------------------------------------------- */
+
+#define RCC_AHB1ENR_OTGHSULPIEN (1 << 30)
+#define RCC_AHB1ENR_OTGHSEN (1 << 29)
+#define RCC_AHB1ENR_ETHMACPTPEN (1 << 28)
+#define RCC_AHB1ENR_ETHMACRXEN (1 << 27)
+#define RCC_AHB1ENR_ETHMACTXEN (1 << 26)
+#define RCC_AHB1ENR_ETHMACEN (1 << 25)
+#define RCC_AHB1ENR_DMA2EN (1 << 22)
+#define RCC_AHB1ENR_DMA1EN (1 << 21)
+#define RCC_AHB1ENR_BKPSRAMEN (1 << 18)
+#define RCC_AHB1ENR_CRCEN (1 << 12)
+#define RCC_AHB1ENR_IOPIEN (1 << 8)
+#define RCC_AHB1ENR_IOPHEN (1 << 7)
+#define RCC_AHB1ENR_IOPGEN (1 << 6)
+#define RCC_AHB1ENR_IOPFEN (1 << 5)
+#define RCC_AHB1ENR_IOPEEN (1 << 4)
+#define RCC_AHB1ENR_IOPDEN (1 << 3)
+#define RCC_AHB1ENR_IOPCEN (1 << 2)
+#define RCC_AHB1ENR_IOPBEN (1 << 1)
+#define RCC_AHB1ENR_IOPAEN (1 << 0)
+
+/* --- RCC_AHB2ENR values ------------------------------------------------- */
+
+#define RCC_AHB2ENR_OTGFSEN (1 << 7)
+#define RCC_AHB2ENR_RNGEN (1 << 6)
+#define RCC_AHB2ENR_HASHEN (1 << 5)
+#define RCC_AHB2ENR_CRYPEN (1 << 4)
+#define RCC_AHB2ENR_DCMIEN (1 << 0)
+
+/* --- RCC_AHB3ENR values ------------------------------------------------- */
+
+#define RCC_AHB3ENR_FSMCEN (1 << 0)
+
+/* --- RCC_APB1ENR values ------------------------------------------------- */
+
+#define RCC_APB1ENR_DACEN (1 << 29)
+#define RCC_APB1ENR_PWREN (1 << 28)
+#define RCC_APB1ENR_CAN2EN (1 << 26)
+#define RCC_APB1ENR_CAN1EN (1 << 25)
+#define RCC_APB1ENR_I2C3EN (1 << 23)
+#define RCC_APB1ENR_I2C2EN (1 << 22)
+#define RCC_APB1ENR_I2C1EN (1 << 21)
+#define RCC_APB1ENR_USART5EN (1 << 20)
+#define RCC_APB1ENR_USART4EN (1 << 19)
+#define RCC_APB1ENR_USART3EN (1 << 18)
+#define RCC_APB1ENR_USART2EN (1 << 17)
+#define RCC_APB1ENR_SPI3EN (1 << 15)
+#define RCC_APB1ENR_SPI2EN (1 << 14)
+#define RCC_APB1ENR_WWDGEN (1 << 11)
+#define RCC_APB1ENR_TIM14EN (1 << 8)
+#define RCC_APB1ENR_TIM13EN (1 << 7)
+#define RCC_APB1ENR_TIM12EN (1 << 6)
+#define RCC_APB1ENR_TIM7EN (1 << 5)
+#define RCC_APB1ENR_TIM6EN (1 << 4)
+#define RCC_APB1ENR_TIM5EN (1 << 3)
+#define RCC_APB1ENR_TIM4EN (1 << 2)
+#define RCC_APB1ENR_TIM3EN (1 << 1)
+#define RCC_APB1ENR_TIM2EN (1 << 0)
+
+/* --- RCC_APB2ENR values ------------------------------------------------- */
+
+#define RCC_APB2ENR_TIM11EN (1 << 18)
+#define RCC_APB2ENR_TIM10EN (1 << 17)
+#define RCC_APB2ENR_TIM9EN (1 << 16)
+#define RCC_APB2ENR_SYSCFGEN (1 << 14)
+#define RCC_APB2ENR_SPI1EN (1 << 12)
+#define RCC_APB2ENR_SDIOEN (1 << 11)
+#define RCC_APB2ENR_ADC3EN (1 << 10)
+#define RCC_APB2ENR_ADC2EN (1 << 9)
+#define RCC_APB2ENR_ADC1EN (1 << 8)
+#define RCC_APB2ENR_USART6EN (1 << 5)
+#define RCC_APB2ENR_USART1EN (1 << 4)
+#define RCC_APB2ENR_TIM8EN (1 << 1)
+#define RCC_APB2ENR_TIM1EN (1 << 0)
+
+/* --- RCC_AHB1LPENR values ------------------------------------------------- */
+
+#define RCC_AHB1LPENR_OTGHSULPILPEN (1 << 30)
+#define RCC_AHB1LPENR_OTGHSLPEN (1 << 29)
+#define RCC_AHB1LPENR_ETHMACPTPLPEN (1 << 28)
+#define RCC_AHB1LPENR_ETHMACRXLPEN (1 << 27)
+#define RCC_AHB1LPENR_ETHMACTXLPEN (1 << 26)
+#define RCC_AHB1LPENR_ETHMACLPEN (1 << 25)
+#define RCC_AHB1LPENR_DMA2LPEN (1 << 22)
+#define RCC_AHB1LPENR_DMA1LPEN (1 << 21)
+#define RCC_AHB1LPENR_BKPSRAMLPEN (1 << 18)
+#define RCC_AHB1LPENR_SRAM2LPEN (1 << 17)
+#define RCC_AHB1LPENR_SRAM1LPEN (1 << 16)
+#define RCC_AHB1LPENR_FLITFLPEN (1 << 15)
+#define RCC_AHB1LPENR_CRCLPEN (1 << 12)
+#define RCC_AHB1LPENR_IOPILPEN (1 << 8)
+#define RCC_AHB1LPENR_IOPHLPEN (1 << 7)
+#define RCC_AHB1LPENR_IOPGLPEN (1 << 6)
+#define RCC_AHB1LPENR_IOPFLPEN (1 << 5)
+#define RCC_AHB1LPENR_IOPELPEN (1 << 4)
+#define RCC_AHB1LPENR_IOPDLPEN (1 << 3)
+#define RCC_AHB1LPENR_IOPCLPEN (1 << 2)
+#define RCC_AHB1LPENR_IOPBLPEN (1 << 1)
+#define RCC_AHB1LPENR_IOPALPEN (1 << 0)
+
+/* --- RCC_AHB2LPENR values ------------------------------------------------- */
+
+#define RCC_AHB2LPENR_OTGFSLPEN (1 << 7)
+#define RCC_AHB2LPENR_RNGLPEN (1 << 6)
+#define RCC_AHB2LPENR_HASHLPEN (1 << 5)
+#define RCC_AHB2LPENR_CRYPLPEN (1 << 4)
+#define RCC_AHB2LPENR_DCMILPEN (1 << 0)
+
+/* --- RCC_AHB3LPENR values ------------------------------------------------- */
+
+#define RCC_AHB3LPENR_FSMCLPEN (1 << 0)
+
+/* --- RCC_APB1LPENR values ------------------------------------------------- */
+
+#define RCC_APB1LPENR_DACLPEN (1 << 29)
+#define RCC_APB1LPENR_PWRLPEN (1 << 28)
+#define RCC_APB1LPENR_CAN2LPEN (1 << 26)
+#define RCC_APB1LPENR_CAN1LPEN (1 << 25)
+#define RCC_APB1LPENR_I2C3LPEN (1 << 23)
+#define RCC_APB1LPENR_I2C2LPEN (1 << 22)
+#define RCC_APB1LPENR_I2C1LPEN (1 << 21)
+#define RCC_APB1LPENR_USART5LPEN (1 << 20)
+#define RCC_APB1LPENR_USART4LPEN (1 << 19)
+#define RCC_APB1LPENR_USART3LPEN (1 << 18)
+#define RCC_APB1LPENR_USART2LPEN (1 << 17)
+#define RCC_APB1LPENR_SPI3LPEN (1 << 15)
+#define RCC_APB1LPENR_SPI2LPEN (1 << 14)
+#define RCC_APB1LPENR_WWDGLPEN (1 << 11)
+#define RCC_APB1LPENR_TIM14LPEN (1 << 8)
+#define RCC_APB1LPENR_TIM13LPEN (1 << 7)
+#define RCC_APB1LPENR_TIM12LPEN (1 << 6)
+#define RCC_APB1LPENR_TIM7LPEN (1 << 5)
+#define RCC_APB1LPENR_TIM6LPEN (1 << 4)
+#define RCC_APB1LPENR_TIM5LPEN (1 << 3)
+#define RCC_APB1LPENR_TIM4LPEN (1 << 2)
+#define RCC_APB1LPENR_TIM3LPEN (1 << 1)
+#define RCC_APB1LPENR_TIM2LPEN (1 << 0)
+
+/* --- RCC_APB2LPENR values ------------------------------------------------- */
+
+#define RCC_APB2LPENR_TIM11LPEN (1 << 18)
+#define RCC_APB2LPENR_TIM10LPEN (1 << 17)
+#define RCC_APB2LPENR_TIM9LPEN (1 << 16)
+#define RCC_APB2LPENR_SYSCFGLPEN (1 << 14)
+#define RCC_APB2LPENR_SPI1LPEN (1 << 12)
+#define RCC_APB2LPENR_SDIOLPEN (1 << 11)
+#define RCC_APB2LPENR_ADC3LPEN (1 << 10)
+#define RCC_APB2LPENR_ADC2LPEN (1 << 9)
+#define RCC_APB2LPENR_ADC1LPEN (1 << 8)
+#define RCC_APB2LPENR_USART6LPEN (1 << 5)
+#define RCC_APB2LPENR_USART1LPEN (1 << 4)
+#define RCC_APB2LPENR_TIM8LPEN (1 << 1)
+#define RCC_APB2LPENR_TIM1LPEN (1 << 0)
+
+/* --- RCC_BDCR values ----------------------------------------------------- */
+
+#define RCC_BDCR_BDRST (1 << 16)
+#define RCC_BDCR_RTCEN (1 << 15)
+/* RCC_BDCR[9:8]: RTCSEL */
+#define RCC_BDCR_LSEBYP (1 << 2)
+#define RCC_BDCR_LSERDY (1 << 1)
+#define RCC_BDCR_LSEON (1 << 0)
+
+/* --- RCC_CSR values ------------------------------------------------------ */
+
+#define RCC_CSR_LPWRRSTF (1 << 31)
+#define RCC_CSR_WWDGRSTF (1 << 30)
+#define RCC_CSR_IWDGRSTF (1 << 29)
+#define RCC_CSR_SFTRSTF (1 << 28)
+#define RCC_CSR_PORRSTF (1 << 27)
+#define RCC_CSR_PINRSTF (1 << 26)
+#define RCC_CSR_BORRSTF (1 << 26)
+#define RCC_CSR_RMVF (1 << 24)
+#define RCC_CSR_LSIRDY (1 << 1)
+#define RCC_CSR_LSION (1 << 0)
+
+/* --- RCC_SSCGR values ---------------------------------------------------- */
+
+/* PLL spread spectrum clock generation documented in Datasheet. */
+
+#define RCC_SSCGR_SSCGEN (1 << 31)
+#define RCC_SSCGR_SPREADSEL (1 << 30)
+/* RCC_SSCGR[27:16]: INCSTEP */
+#define RCC_SSCGR_INCSTEP_SHIFT 16
+/* RCC_SSCGR[15:0]: MODPER */
+#define RCC_SSCGR_MODPER_SHIFT 15
+
+/* --- RCC_PLLI2SCFGR values ----------------------------------------------- */
+
+/* RCC_PLLI2SCFGR[30:28]: PLLI2SR */
+#define RCC_PLLI2SCFGR_PLLI2SR_SHIFT 28
+/* RCC_PLLI2SCFGR[14:6]: PLLI2SN */
+#define RCC_PLLI2SCFGR_PLLI2SN_SHIFT 6
+
+/* --- Variable definitions ------------------------------------------------ */
+extern u32 rcc_ppre1_frequency;
+extern u32 rcc_ppre2_frequency;
+
+/* --- Function prototypes ------------------------------------------------- */
+
+typedef enum {
+ CLOCK_3V3_120MHZ,
+ CLOCK_3V3_168MHZ,
+ CLOCK_3V3_END
+} clock_3v3_t;
+
+typedef struct {
+ uint8_t pllm;
+ uint16_t plln;
+ uint8_t pllp;
+ uint8_t pllq;
+ uint32_t flash_config;
+ uint8_t hpre;
+ uint8_t ppre1;
+ uint8_t ppre2;
+ uint8_t power_save;
+ uint32_t apb1_frequency;
+ uint32_t apb2_frequency;
+} clock_scale_t;
+
+extern const clock_scale_t hse_8mhz_3v3[CLOCK_3V3_END];
+
+typedef enum {
+ PLL, HSE, HSI, LSE, LSI
+} osc_t;
+
+void rcc_osc_ready_int_clear(osc_t osc);
+void rcc_osc_ready_int_enable(osc_t osc);
+void rcc_osc_ready_int_disable(osc_t osc);
+int rcc_osc_ready_int_flag(osc_t osc);
+void rcc_css_int_clear(void);
+int rcc_css_int_flag(void);
+void rcc_wait_for_osc_ready(osc_t osc);
+void rcc_wait_for_sysclk_status(osc_t osc);
+void rcc_osc_on(osc_t osc);
+void rcc_osc_off(osc_t osc);
+void rcc_css_enable(void);
+void rcc_css_disable(void);
+void rcc_osc_bypass_enable(osc_t osc);
+void rcc_osc_bypass_disable(osc_t osc);
+void rcc_peripheral_enable_clock(volatile u32 *reg, u32 en);
+void rcc_peripheral_disable_clock(volatile u32 *reg, u32 en);
+void rcc_peripheral_reset(volatile u32 *reg, u32 reset);
+void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset);
+void rcc_set_sysclk_source(u32 clk);
+void rcc_set_pll_source(u32 pllsrc);
+void rcc_set_ppre2(u32 ppre2);
+void rcc_set_ppre1(u32 ppre1);
+void rcc_set_hpre(u32 hpre);
+void rcc_set_rtcpre(u32 rtcpre);
+void rcc_set_main_pll_hsi(u32 pllm, u32 plln, u32 pllp, u32 pllq);
+void rcc_set_main_pll_hse(u32 pllm, u32 plln, u32 pllp, u32 pllq);
+u32 rcc_get_system_clock_source(int i);
+void rcc_clock_setup_hse_3v3(const clock_scale_t *clock);
+void rcc_backupdomain_reset(void);
+
+#endif
diff --git a/include/libopencm3/stm32/f4/scb.h b/include/libopencm3/stm32/f4/scb.h
new file mode 100644
index 0000000..9594cf1
--- /dev/null
+++ b/include/libopencm3/stm32/f4/scb.h
@@ -0,0 +1,300 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
+ * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_SCB_H
+#define LIBOPENCM3_SCB_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/* --- SCB: Registers ------------------------------------------------------ */
+
+/* CPUID: CPUID base register */
+#define SCB_CPUID MMIO32(SCB_BASE + 0x00)
+
+/* ICSR: Interrupt Control State Register */
+#define SCB_ICSR MMIO32(SCB_BASE + 0x04)
+
+/* VTOR: Vector Table Offset Register */
+#define SCB_VTOR MMIO32(SCB_BASE + 0x08)
+
+/* AIRCR: Application Interrupt and Reset Control Register */
+#define SCB_AIRCR MMIO32(SCB_BASE + 0x0C)
+
+/* SCR: System Control Register */
+#define SCB_SCR MMIO32(SCB_BASE + 0x10)
+
+/* CCR: Configuration Control Register */
+#define SCB_CCR MMIO32(SCB_BASE + 0x14)
+
+/* SHP: System Handler Priority Registers */
+/* Note: 12 8bit registers */
+#define SCB_SHPR(shpr_id) MMIO8(SCB_BASE + 0x18 + shpr_id)
+#define SCB_SHPR1 MMIO8(SCB_BASE + 0x18 + 1)
+#define SCB_SHPR2 MMIO8(SCB_BASE + 0x18 + 2)
+#define SCB_SHPR3 MMIO8(SCB_BASE + 0x18 + 3)
+
+/* SHCSR: System Handler Control and State Register */
+#define SCB_SHCSR MMIO32(SCB_BASE + 0x24)
+
+/* CFSR: Configurable Fault Status Registers */
+#define SCB_CFSR MMIO32(SCB_BASE + 0x28)
+
+/* HFSR: Hard Fault Status Register */
+#define SCB_HFSR MMIO32(SCB_BASE + 0x2C)
+
+/* DFSR: Debug Fault Status Register */
+#define SCB_DFSR MMIO32(SCB_BASE + 0x30)
+
+/* MMFAR: Memory Manage Fault Address Register */
+#define SCB_MMFAR MMIO32(SCB_BASE + 0x34)
+
+/* BFAR: Bus Fault Address Register */
+#define SCB_BFAR MMIO32(SCB_BASE + 0x38)
+
+/* AFSR: Auxiliary Fault Status Register */
+#define SCB_AFSR MMIO32(SCB_BASE + 0x3C)
+
+/* --- SCB values ---------------------------------------------------------- */
+
+/* --- SCB_CPUID values ---------------------------------------------------- */
+
+/* Implementer[31:24]: Implementer code */
+#define SCP_CPUID_IMPLEMENTER_LSB 24
+/* Variant[23:20]: Variant number */
+#define SCP_CPUID_VARIANT_LSB 20
+/* Constant[19:16]: Reads as 0xF */
+#define SCP_CPUID_CONSTANT_LSB 16
+/* PartNo[15:4]: Part number of the processor */
+#define SCP_CPUID_PARTNO_LSB 4
+/* Revision[3:0]: Revision number */
+#define SCP_CPUID_REVISION_LSB 0
+
+/* --- SCB_ICSR values ----------------------------------------------------- */
+
+/* NMIPENDSET: NMI set-pending bit */
+#define SCB_ICSR_NMIPENDSET (1 << 31)
+/* Bits [30:29]: reserved - must be kept cleared */
+/* PENDSVSET: PendSV set-pending bit */
+#define SCB_ICSR_PENDSVSET (1 << 28)
+/* PENDSVCLR: PendSV clear-pending bit */
+#define SCB_ICSR_PENDSVCLR (1 << 27)
+/* PENDSTSET: SysTick exception set-pending bit */
+#define SCB_ICSR_PENDSTSET (1 << 26)
+/* PENDSTCLR: SysTick exception clear-pending bit */
+#define SCB_ICSR_PENDSTCLR (1 << 25)
+/* Bit 24: reserved - must be kept cleared */
+/* Bit 23: reserved for debug - reads as 0 when not in debug mode */
+/* ISRPENDING: Interrupt pending flag, excluding NMI and Faults */
+#define SCB_ICSR_ISRPENDING (1 << 22)
+/* VECTPENDING[21:12] Pending vector */
+#define SCB_ICSR_VECTPENDING_LSB 12
+/* RETOBASE: Return to base level */
+#define SCB_ICSR_RETOBASE (1 << 11)
+/* Bits [10:9]: reserved - must be kept cleared */
+/* VECTACTIVE[8:0] Active vector */
+#define SCB_ICSR_VECTACTIVE_LSB 0
+
+/* --- SCB_VTOR values ----------------------------------------------------- */
+
+/* Bits [31:30]: reserved - must be kept cleared */
+/* TBLOFF[29:9]: Vector table base offset field */
+#define SCB_VTOR_TBLOFF_LSB 9 /* inconsistent datasheet - LSB could be 11 */
+
+/* --- SCB_AIRCR values ---------------------------------------------------- */
+
+/* VECTKEYSTAT[31:16]/ VECTKEY[31:16] Register key */
+#define SCB_AIRCR_VECTKEYSTAT_LSB 16
+#define SCB_AIRCR_VECTKEY 0x05FA0000
+/* ENDIANESS Data endianness bit */
+#define SCB_AIRCR_ENDIANESS (1 << 15)
+/* Bits [14:11]: reserved - must be kept cleared */
+/* PRIGROUP[10:8]: Interrupt priority grouping field */
+#define SCB_AIRCR_PRIGROUP_LSB 8
+#define SCB_AIRCR_PRIGROUP_GROUP16_NOSUB 0x3
+#define SCB_AIRCR_PRIGROUP_GROUP8_SUB2 0x4
+#define SCB_AIRCR_PRIGROUP_GROUP4_SUB4 0x5
+#define SCB_AIRCR_PRIGROUP_GROUP2_SUB8 0x6
+#define SCB_AIRCR_PRIGROUP_NOGROUP_SUB16 0x7
+/* Bits [7:3]: reserved - must be kept cleared */
+/* SYSRESETREQ System reset request */
+#define SCB_AIRCR_SYSRESETREQ (1 << 2)
+/* VECTCLRACTIVE */
+#define SCB_AIRCR_VECTCLRACTIVE (1 << 1)
+/* VECTRESET */
+#define SCB_AIRCR_VECTRESET (1 << 0)
+
+/* --- SCB_SCR values ------------------------------------------------------ */
+
+/* Bits [31:5]: reserved - must be kept cleared */
+/* SEVEONPEND Send Event on Pending bit */
+#define SCB_SCR_SEVEONPEND (1 << 4)
+/* Bit 3: reserved - must be kept cleared */
+/* SLEEPDEEP */
+#define SCB_SCR_SLEEPDEEP (1 << 2)
+/* SLEEPONEXIT */
+#define SCB_SCR_SLEEPONEXIT (1 << 1)
+/* Bit 0: reserved - must be kept cleared */
+
+/* --- SCB_CCR values ------------------------------------------------------ */
+
+/* Bits [31:10]: reserved - must be kept cleared */
+/* STKALIGN */
+#define SCB_CCR_STKALIGN (1 << 9)
+/* BFHFNMIGN */
+#define SCB_CCR_BFHFNMIGN (1 << 8)
+/* Bits [7:5]: reserved - must be kept cleared */
+/* DIV_0_TRP */
+#define SCB_CCR_DIV_0_TRP (1 << 4)
+/* UNALIGN_TRP */
+#define SCB_CCR_UNALIGN_TRP (1 << 3)
+/* Bit 2: reserved - must be kept cleared */
+/* USERSETMPEND */
+#define SCB_CCR_USERSETMPEND (1 << 1)
+/* NONBASETHRDENA */
+#define SCB_CCR_NONBASETHRDENA (1 << 0)
+
+/* --- SCB_SHPR1 values ---------------------------------------------------- */
+
+/* Bits [31:24]: reserved - must be kept cleared */
+/* PRI_6[23:16]: Priority of system handler 6, usage fault */
+#define SCB_SHPR1_PRI_6_LSB 16
+/* PRI_5[15:8]: Priority of system handler 5, bus fault */
+#define SCB_SHPR1_PRI_5_LSB 8
+/* PRI_4[7:0]: Priority of system handler 4, memory management fault */
+#define SCB_SHPR1_PRI_4_LSB 0
+
+/* --- SCB_SHPR2 values ---------------------------------------------------- */
+
+/* PRI_11[31:24]: Priority of system handler 11, SVCall */
+#define SCB_SHPR2_PRI_11_LSB 24
+/* Bits [23:0]: reserved - must be kept cleared */
+
+/* --- SCB_SHPR3 values ---------------------------------------------------- */
+
+/* PRI_15[31:24]: Priority of system handler 15, SysTick exception */
+#define SCB_SHPR3_PRI_15_LSB 24
+/* PRI_14[23:16]: Priority of system handler 14, PendSV */
+#define SCB_SHPR3_PRI_14_LSB 16
+/* Bits [15:0]: reserved - must be kept cleared */
+
+/* --- SCB_SHCSR values ---------------------------------------------------- */
+
+/* Bits [31:19]: reserved - must be kept cleared */
+/* USGFAULTENA: Usage fault enable */
+#define SCB_SHCSR_USGFAULTENA (1 << 18)
+/* BUSFAULTENA: Bus fault enable */
+#define SCB_SHCSR_BUSFAULTENA (1 << 17)
+/* MEMFAULTENA: Memory management fault enable */
+#define SCB_SHCSR_MEMFAULTENA (1 << 16)
+/* SVCALLPENDED: SVC call pending */
+#define SCB_SHCSR_SVCALLPENDED (1 << 15)
+/* BUSFAULTPENDED: Bus fault exception pending */
+#define SCB_SHCSR_BUSFAULTPENDED (1 << 14)
+/* MEMFAULTPENDED: Memory management fault exception pending */
+#define SCB_SHCSR_MEMFAULTPENDED (1 << 13)
+/* USGFAULTPENDED: Usage fault exception pending */
+#define SCB_SHCSR_USGFAULTPENDED (1 << 12)
+/* SYSTICKACT: SysTick exception active */
+#define SCB_SHCSR_SYSTICKACT (1 << 11)
+/* PENDSVACT: PendSV exception active */
+#define SCB_SHCSR_PENDSVACT (1 << 10)
+/* Bit 9: reserved - must be kept cleared */
+/* MONITORACT: Debug monitor active */
+#define SCB_SHCSR_MONITORACT (1 << 8)
+/* SVCALLACT: SVC call active */
+#define SCB_SHCSR_SVCALLACT (1 << 7)
+/* Bits [6:4]: reserved - must be kept cleared */
+/* USGFAULTACT: Usage fault exception active */
+#define SCB_SHCSR_USGFAULTACT (1 << 3)
+/* Bit 2: reserved - must be kept cleared */
+/* BUSFAULTACT: Bus fault exception active */
+#define SCB_SHCSR_BUSFAULTACT (1 << 1)
+/* MEMFAULTACT: Memory management fault exception active */
+#define SCB_SHCSR_MEMFAULTACT (1 << 0)
+
+/* --- SCB_CFSR values ----------------------------------------------------- */
+
+/* Bits [31:26]: reserved - must be kept cleared */
+/* DIVBYZERO: Divide by zero usage fault */
+#define SCB_CFSR_DIVBYZERO (1 << 25)
+/* UNALIGNED: Unaligned access usage fault */
+#define SCB_CFSR_UNALIGNED (1 << 24)
+/* Bits [23:20]: reserved - must be kept cleared */
+/* NOCP: No coprocessor usage fault */
+#define SCB_CFSR_NOCP (1 << 19)
+/* INVPC: Invalid PC load usage fault */
+#define SCB_CFSR_INVPC (1 << 18)
+/* INVSTATE: Invalid state usage fault */
+#define SCB_CFSR_INVSTATE (1 << 17)
+/* UNDEFINSTR: Undefined instruction usage fault */
+#define SCB_CFSR_UNDEFINSTR (1 << 16)
+/* BFARVALID: Bus Fault Address Register (BFAR) valid flag */
+#define SCB_CFSR_BFARVALID (1 << 15)
+/* Bits [14:13]: reserved - must be kept cleared */
+/* STKERR: Bus fault on stacking for exception entry */
+#define SCB_CFSR_STKERR (1 << 12)
+/* UNSTKERR: Bus fault on unstacking for a return from exception */
+#define SCB_CFSR_UNSTKERR (1 << 11)
+/* IMPRECISERR: Imprecise data bus error */
+#define SCB_CFSR_IMPRECISERR (1 << 10)
+/* PRECISERR: Precise data bus error */
+#define SCB_CFSR_PRECISERR (1 << 9)
+/* IBUSERR: Instruction bus error */
+#define SCB_CFSR_IBUSERR (1 << 8)
+/* MMARVALID: Memory Management Fault Address Register (MMAR) valid flag */
+#define SCB_CFSR_MMARVALID (1 << 7)
+/* Bits [6:5]: reserved - must be kept cleared */
+/* MSTKERR: Memory manager fault on stacking for exception entry */
+#define SCB_CFSR_MSTKERR (1 << 4)
+/* MUNSTKERR: Memory manager fault on unstacking for a return from exception */
+#define SCB_CFSR_MUNSTKERR (1 << 3)
+/* Bit 2: reserved - must be kept cleared */
+/* DACCVIOL: Data access violation flag */
+#define SCB_CFSR_DACCVIOL (1 << 1)
+/* IACCVIOL: Instruction access violation flag */
+#define SCB_CFSR_IACCVIOL (1 << 0)
+
+/* --- SCB_HFSR values ----------------------------------------------------- */
+
+/* DEBUG_VT: reserved for debug use */
+#define SCB_HFSR_DEBUG_VT (1 << 31)
+/* FORCED: Forced hard fault */
+#define SCB_HFSR_FORCED (1 << 30)
+/* Bits [29:2]: reserved - must be kept cleared */
+/* VECTTBL: Vector table hard fault */
+#define SCB_HFSR_VECTTBL (1 << 1)
+/* Bit 0: reserved - must be kept cleared */
+
+/* --- SCB_MMFAR values ---------------------------------------------------- */
+
+/* MMFAR [31:0]: Memory management fault address */
+
+/* --- SCB_BFAR values ----------------------------------------------------- */
+
+/* BFAR [31:0]: Bus fault address */
+
+/* --- SCB functions ------------------------------------------------------- */
+void scb_reset_core(void);
+void scb_reset_system(void);
+
+/* TODO: */
+
+#endif
diff --git a/include/libopencm3/stm32/f4/spi.h b/include/libopencm3/stm32/f4/spi.h
new file mode 100644
index 0000000..23c9479
--- /dev/null
+++ b/include/libopencm3/stm32/f4/spi.h
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_SPI_F4_H
+#define LIBOPENCM3_SPI_F4_H
+
+#include <libopencm3/stm32/spi.h>
+
+/*
+ * This file extends the version in stm_common with definitions only
+ * applicable to the STM32F2 series of devices.
+ */
+
+/* --- SPI_CR2 values ------------------------------------------------------ */
+
+/* FRF: Frame format. */
+#define SPI_CR2_FRF (1 << 4)
+#define SPI_CR2_FRF_TI (1 << 4)
+#define SPI_CR2_FRF_MOTOROLA (1 << 4)
+
+/* --- SPI_SR values ------------------------------------------------------- */
+
+/* TIFRFE: TI frame format error. */
+#define SPI_SR_RXNE (1 << 0)
+
+#endif
diff --git a/include/libopencm3/stm32/f4/syscfg.h b/include/libopencm3/stm32/f4/syscfg.h
new file mode 100644
index 0000000..b0d93f9
--- /dev/null
+++ b/include/libopencm3/stm32/f4/syscfg.h
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_SYSCFG_H
+#define LIBOPENCM3_SYSCFG_H
+
+#include <libopencm3/stm32/memorymap.h>
+
+/* --- SYSCFG registers ------------------------------------------------------ */
+
+#define SYSCFG_MEMRM MMIO32(SYSCFG_BASE + 0x00)
+
+#define SYSCFG_PMC MMIO32(SYSCFG_BASE + 0x04)
+
+/* External interrupt configuration register 1 (SYSCFG_EXTICR1) */
+#define SYSCFG_EXTICR1 MMIO32(SYSCFG_BASE + 0x08)
+
+/* External interrupt configuration register 2 (SYSCFG_EXTICR2) */
+#define SYSCFG_EXTICR2 MMIO32(SYSCFG_BASE + 0x0c)
+
+/* External interrupt configuration register 3 (SYSCFG_EXTICR3) */
+#define SYSCFG_EXTICR3 MMIO32(SYSCFG_BASE + 0x10)
+
+/* External interrupt configuration register 4 (SYSCFG_EXTICR4) */
+#define SYSCFG_EXTICR4 MMIO32(SYSCFG_BASE + 0x14)
+
+#define SYSCFG_CMPCR MMIO32(SYSCFG_BASE + 0x20)
+
+#endif
+
diff --git a/include/libopencm3/stm32/f4/timer.h b/include/libopencm3/stm32/f4/timer.h
new file mode 100644
index 0000000..a76c7ef
--- /dev/null
+++ b/include/libopencm3/stm32/f4/timer.h
@@ -0,0 +1,54 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_TIMER_F4_H
+#define LIBOPENCM3_TIMER_F4_H
+
+#include <libopencm3/stm32/timer.h>
+
+
+/*
+ * TIM2 and TIM5 are now 32bit and the following registers are now 32-bit wide:
+ * CNT, ARR, CCR1, CCR2, CCR3, CCR4
+ */
+
+/* Timer 2/5 option register (TIMx_OR) */
+#define TIM_OR(tim_base) MMIO32(tim_base + 0x50)
+#define TIM2_OR TIM_OR(TIM2)
+#define TIM5_OR TIM_OR(TIM5)
+
+/* --- TIM2_OR values ---------------------------------------------------- */
+
+/* MOE: Main output enable */
+#define TIM2_OR_ITR1_RMP_TIM8_TRGOUT (0x0 << 10)
+#define TIM2_OR_ITR1_RMP_PTP (0x1 << 10)
+#define TIM2_OR_ITR1_RMP_OTG_FS_SOF (0x2 << 10)
+#define TIM2_OR_ITR1_RMP_OTG_HS_SOF (0x3 << 10)
+#define TIM2_OR_ITR1_RMP_MASK (0x3 << 10)
+
+/* --- TIM5_OR values ---------------------------------------------------- */
+
+/* MOE: Main output enable */
+#define TIM5_OR_TI4_RMP_GPIO (0x0 << 6)
+#define TIM5_OR_TI4_RMP_LSI (0x1 << 6)
+#define TIM5_OR_TI4_RMP_LSE (0x2 << 6)
+#define TIM5_OR_TI4_RMP_RTC (0x3 << 6)
+#define TIM5_OR_TI4_RMP_MASK (0x3 << 6)
+
+#endif
diff --git a/include/libopencm3/stm32/f4/usart.h b/include/libopencm3/stm32/f4/usart.h
new file mode 100644
index 0000000..5c4f939
--- /dev/null
+++ b/include/libopencm3/stm32/f4/usart.h
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_USART_F4_H
+#define LIBOPENCM3_USART_F4_H
+
+#include <libopencm3/stm32/usart.h>
+
+/* --- USART_CR1 values ---------------------------------------------------- */
+
+/* OVER8: Oversampling mode */
+#define USART_CR1_OVER8 (1 << 15)
+
+/* --- USART_CR3 values ---------------------------------------------------- */
+
+/* ONEBIT: One sample bit method enable */
+#define USART_CR3_ONEBIT (1 << 11)
+
+#endif
diff --git a/include/libopencm3/stm32/memorymap.h b/include/libopencm3/stm32/memorymap.h
index 63f2ef0..4700e4e 100644
--- a/include/libopencm3/stm32/memorymap.h
+++ b/include/libopencm3/stm32/memorymap.h
@@ -26,8 +26,12 @@
#ifdef STM32F2
#include <libopencm3/stm32/f2/memorymap.h>
#else
+#ifdef STM32F4
+#include <libopencm3/stm32/f4/memorymap.h>
+#else
#error "stm32 family not defined."
#endif
#endif
+#endif
#endif
diff --git a/include/libopencm3/stm32/nvic.h b/include/libopencm3/stm32/nvic.h
index 339a159..61b231e 100644
--- a/include/libopencm3/stm32/nvic.h
+++ b/include/libopencm3/stm32/nvic.h
@@ -88,9 +88,13 @@
#ifdef STM32F2
#include <libopencm3/stm32/f2/nvic_f2.h>
#else
+#ifdef STM32F4
+#include <libopencm3/stm32/f4/nvic_f4.h>
+#else
#error "stm32 family not defined."
#endif
#endif
+#endif
/* --- NVIC functions ------------------------------------------------------ */
diff --git a/lib/stm32/f4/Makefile b/lib/stm32/f4/Makefile
new file mode 100644
index 0000000..267ef42
--- /dev/null
+++ b/lib/stm32/f4/Makefile
@@ -0,0 +1,59 @@
+##
+## This file is part of the libopencm3 project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+##
+## This program is free software: you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation, either version 3 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program. If not, see <http://www.gnu.org/licenses/>.
+##
+
+LIBNAME = libopencm3_stm32f4
+
+PREFIX ?= arm-none-eabi
+# PREFIX ?= arm-elf
+CC = $(PREFIX)-gcc
+AR = $(PREFIX)-ar
+CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \
+ -mcpu=cortex-m3 -mthumb -Wstrict-prototypes \
+ -ffunction-sections -fdata-sections -MD -DSTM32F4
+# ARFLAGS = rcsv
+ARFLAGS = rcs
+OBJS = vector.o rcc.o gpio.o usart.o spi.o flash.o nvic.o \
+ i2c.o systick.o exti.o scb.o \
+
+VPATH += ../../usb:../
+
+# Be silent per default, but 'make V=1' will show all compiler calls.
+ifneq ($(V),1)
+Q := @
+endif
+
+all: $(LIBNAME).a
+
+$(LIBNAME).a: $(OBJS)
+ @printf " AR $(subst $(shell pwd)/,,$(@))\n"
+ $(Q)$(AR) $(ARFLAGS) $@ $^
+
+%.o: %.c
+ @printf " CC $(subst $(shell pwd)/,,$(@))\n"
+ $(Q)$(CC) $(CFLAGS) -o $@ -c $<
+
+clean:
+ @printf " CLEAN lib/stm32/f4\n"
+ $(Q)rm -f *.o *.d
+ $(Q)rm -f $(LIBNAME).a
+
+.PHONY: clean
+
+-include $(OBJS:.o=.d)
+
diff --git a/lib/stm32/f4/exti.c b/lib/stm32/f4/exti.c
new file mode 100644
index 0000000..1a2a7a1
--- /dev/null
+++ b/lib/stm32/f4/exti.c
@@ -0,0 +1,146 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Mark Butler <mbutler@physics.otago.ac.nz>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopencm3/stm32/exti.h>
+#include <libopencm3/stm32/f4/syscfg.h>
+#include <libopencm3/stm32/f4/gpio.h>
+
+void exti_set_trigger(u32 extis, exti_trigger_type trig)
+{
+ switch (trig) {
+ case EXTI_TRIGGER_RISING:
+ EXTI_RTSR |= extis;
+ EXTI_FTSR &= ~extis;
+ break;
+ case EXTI_TRIGGER_FALLING:
+ EXTI_RTSR &= ~extis;
+ EXTI_FTSR |= extis;
+ break;
+ case EXTI_TRIGGER_BOTH:
+ EXTI_RTSR |= extis;
+ EXTI_FTSR |= extis;
+ break;
+ }
+}
+
+void exti_enable_request(u32 extis)
+{
+ /* Enable interrupts. */
+ EXTI_IMR |= extis;
+
+ /* Enable events. */
+ EXTI_EMR |= extis;
+}
+
+void exti_disable_request(u32 extis)
+{
+ /* Disable interrupts. */
+ EXTI_IMR &= ~extis;
+
+ /* Disable events. */
+ EXTI_EMR &= ~extis;
+}
+
+/*
+ * Reset the interrupt request by writing a 1 to the corresponding
+ * pending bit register.
+ */
+void exti_reset_request(u32 extis)
+{
+ EXTI_PR = extis;
+}
+
+/*
+ * Remap an external interrupt line to the corresponding pin on the
+ * specified GPIO port.
+ *
+ * TODO: This could be rewritten in fewer lines of code.
+ */
+void exti_select_source(u32 exti, u32 gpioport)
+{
+ u8 shift, bits;
+
+ shift = bits = 0;
+
+ switch (exti) {
+ case EXTI0:
+ case EXTI4:
+ case EXTI8:
+ case EXTI12:
+ shift = 0;
+ break;
+ case EXTI1:
+ case EXTI5:
+ case EXTI9:
+ case EXTI13:
+ shift = 4;
+ break;
+ case EXTI2:
+ case EXTI6:
+ case EXTI10:
+ case EXTI14:
+ shift = 8;
+ break;
+ case EXTI3:
+ case EXTI7:
+ case EXTI11:
+ case EXTI15:
+ shift = 12;
+ break;
+ }
+
+ switch (gpioport) {
+ case GPIOA:
+ bits = 0xf;
+ break;
+ case GPIOB:
+ bits = 0xe;
+ break;
+ case GPIOC:
+ bits = 0xd;
+ break;
+ case GPIOD:
+ bits = 0xc;
+ break;
+ case GPIOE:
+ bits = 0xb;
+ break;
+ case GPIOF:
+ bits = 0xa;
+ break;
+ case GPIOG:
+ bits = 0x9;
+ break;
+ }
+
+ /* Ensure that only valid EXTI lines are used. */
+ if (exti < EXTI4) {
+ SYSCFG_EXTICR1 &= ~(0x000F << shift);
+ SYSCFG_EXTICR1 |= (~bits << shift);
+ } else if (exti < EXTI8) {
+ SYSCFG_EXTICR2 &= ~(0x000F << shift);
+ SYSCFG_EXTICR2 |= (~bits << shift);
+ } else if (exti < EXTI12) {
+ SYSCFG_EXTICR3 &= ~(0x000F << shift);
+ SYSCFG_EXTICR3 |= (~bits << shift);
+ } else if (exti < EXTI16) {
+ SYSCFG_EXTICR4 &= ~(0x000F << shift);
+ SYSCFG_EXTICR4 |= (~bits << shift);
+ }
+}
diff --git a/lib/stm32/f4/flash.c b/lib/stm32/f4/flash.c
new file mode 100644
index 0000000..a51b954
--- /dev/null
+++ b/lib/stm32/f4/flash.c
@@ -0,0 +1,250 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
+ * Copyright (C) 2010 Mark Butler <mbutler@physics.otago.ac.nz>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopencm3/stm32/f4/flash.h>
+
+static inline void flash_set_program_size(u32 psize)
+{
+ FLASH_CR &= ~(((1 << 0) | (1 << 1)) << 8);
+ FLASH_CR |= psize;
+}
+
+void flash_data_cache_enable(void)
+{
+ FLASH_ACR |= FLASH_DCE;
+}
+
+void flash_dcache_disable(void)
+{
+ FLASH_ACR &= ~FLASH_DCE;
+}
+
+void flash_icache_enable(void)
+{
+ FLASH_ACR |= FLASH_ICE;
+}
+
+void flash_icache_disable(void)
+{
+ FLASH_ACR &= ~FLASH_ICE;
+}
+
+void flash_prefetch_enable(void)
+{
+ FLASH_ACR |= FLASH_PRFTEN;
+}
+
+void flash_prefetch_disable(void)
+{
+ FLASH_ACR &= ~FLASH_PRFTEN;
+}
+
+void flash_dcache_reset(void)
+{
+ FLASH_ACR |= FLASH_DCRST;
+}
+
+void flash_icache_reset(void)
+{
+ FLASH_ACR |= FLASH_ICRST;
+}
+
+void flash_set_ws(u32 ws)
+{
+ u32 reg32;
+
+ reg32 = FLASH_ACR;
+ reg32 &= ~((1 << 0) | (1 << 1) | (1 << 2));
+ reg32 |= ws;
+ FLASH_ACR = reg32;
+}
+
+void flash_unlock(void)
+{
+ /* Authorize the FPEC access. */
+ FLASH_KEYR = FLASH_KEY1;
+ FLASH_KEYR = FLASH_KEY2;
+}
+
+void flash_lock(void)
+{
+ FLASH_CR |= FLASH_LOCK;
+}
+
+void flash_clear_pgserr_flag(void)
+{
+ FLASH_SR |= FLASH_PGSERR;
+}
+
+void flash_clear_pgperr_flag(void)
+{
+ FLASH_SR |= FLASH_PGPERR;
+}
+
+void flash_clear_pgaerr_flag(void)
+{
+ FLASH_SR |= FLASH_PGAERR;
+}
+
+void flash_clear_eop_flag(void)
+{
+ FLASH_SR |= FLASH_EOP;
+}
+
+void flash_clear_wrperr_flag(void)
+{
+ FLASH_SR |= FLASH_WRPERR;
+}
+
+void flash_clear_bsy_flag(void)
+{
+ FLASH_SR &= ~FLASH_BSY;
+}
+
+void flash_clear_status_flags(void)
+{
+ flash_clear_pgserr_flag();
+ flash_clear_pgperr_flag();
+ flash_clear_pgaerr_flag();
+ flash_clear_eop_flag();
+ flash_clear_wrperr_flag();
+ flash_clear_bsy_flag();
+}
+
+void flash_unlock_option_bytes(void)
+{
+ FLASH_OPTKEYR = FLASH_OPTKEY1;
+ FLASH_OPTKEYR = FLASH_OPTKEY2;
+}
+
+void flash_lock_option_bytes(void)
+{
+ FLASH_OPTCR |= FLASH_OPTLOCK;
+}
+
+void flash_wait_for_last_operation(void)
+{
+ while ((FLASH_SR & FLASH_BSY) == FLASH_BSY)
+ ;
+}
+
+void flash_program_double_word(u32 address, u64 data, u32 program_size)
+{
+ /* Ensure that all flash operations are complete. */
+ flash_wait_for_last_operation();
+ flash_set_program_size(program_size);
+
+ /* Enable writes to flash. */
+ FLASH_CR |= FLASH_PG;
+
+ /* Program the first half of the word. */
+ MMIO64(address) = data;
+
+ /* Wait for the write to complete. */
+ flash_wait_for_last_operation();
+
+ /* Disable writes to flash. */
+ FLASH_CR &= ~FLASH_PG;
+}
+
+void flash_program_word(u32 address, u32 data, u32 program_size)
+{
+ /* Ensure that all flash operations are complete. */
+ flash_wait_for_last_operation();
+ flash_set_program_size(program_size);
+
+ /* Enable writes to flash. */
+ FLASH_CR |= FLASH_PG;
+
+ /* Program the first half of the word. */
+ MMIO32(address) = data;
+
+ /* Wait for the write to complete. */
+ flash_wait_for_last_operation();
+
+ /* Disable writes to flash. */
+ FLASH_CR &= ~FLASH_PG;
+}
+
+void flash_program_half_word(u32 address, u16 data, u32 program_size)
+{
+ flash_wait_for_last_operation();
+ flash_set_program_size(program_size);
+
+ FLASH_CR |= FLASH_PG;
+
+ MMIO16(address) = data;
+
+ flash_wait_for_last_operation();
+
+ FLASH_CR &= ~FLASH_PG; /* Disable the PG bit. */
+}
+
+void flash_program_byte(u32 address, u8 data, u32 program_size)
+{
+ flash_wait_for_last_operation();
+ flash_set_program_size(program_size);
+
+ FLASH_CR |= FLASH_PG;
+
+ MMIO8(address) = data;
+
+ flash_wait_for_last_operation();
+
+ FLASH_CR &= ~FLASH_PG; /* Disable the PG bit. */
+}
+
+void flash_erase_sector(u32 sector, u32 program_size)
+{
+ flash_wait_for_last_operation();
+ flash_set_program_size(program_size);
+
+ FLASH_CR &= ~(((1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)) << 3);
+ FLASH_CR |= sector;
+ FLASH_CR |= FLASH_STRT;
+
+ flash_wait_for_last_operation();
+ FLASH_CR &= ~FLASH_SER;
+ FLASH_CR &= ~(((1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)) << 3);
+}
+
+void flash_erase_all_sectors(u32 program_size)
+{
+ flash_wait_for_last_operation();
+ flash_set_program_size(program_size);
+
+ FLASH_CR |= FLASH_MER; /* Enable mass erase. */
+ FLASH_CR |= FLASH_STRT; /* Trigger the erase. */
+
+ flash_wait_for_last_operation();
+ FLASH_CR &= ~FLASH_MER; /* Disable mass erase. */
+}
+
+void flash_program_option_bytes(u32 data)
+{
+ flash_wait_for_last_operation();
+
+ if (FLASH_OPTCR & FLASH_OPTLOCK)
+ flash_unlock_option_bytes();
+
+ FLASH_OPTCR = data & ~0x3;
+ FLASH_OPTCR |= FLASH_OPTSTRT; /* Enable option byte programming. */
+ flash_wait_for_last_operation();
+}
diff --git a/lib/stm32/f4/gpio.c b/lib/stm32/f4/gpio.c
new file mode 100644
index 0000000..c2b396b
--- /dev/null
+++ b/lib/stm32/f4/gpio.c
@@ -0,0 +1,139 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopencm3/stm32/f4/gpio.h>
+
+void gpio_mode_setup(u32 gpioport, u8 mode, u8 pull_up_down, u16 gpios)
+{
+ u16 i;
+ u32 moder, pupd;
+
+ /*
+ * We want to set the config only for the pins mentioned in gpios,
+ * but keeping the others, so read out the actual config first.
+ */
+ moder = GPIO_MODER(gpioport);
+ pupd = GPIO_PUPDR(gpioport);
+
+ for (i = 0; i < 16; i++) {
+ if (!((1 << i) & gpios))
+ continue;
+
+ moder &= ~GPIO_MODE_MASK(i);
+ moder |= GPIO_MODE(i, mode);
+ pupd &= ~GPIO_PUPD_MASK(i);
+ pupd |= GPIO_PUPD(i, pull_up_down);
+ }
+
+ /* Set mode and pull up/down control registers. */
+ GPIO_MODER(gpioport) = moder;
+ GPIO_PUPDR(gpioport) = pupd;
+}
+
+void gpio_set_output_options(u32 gpioport, u8 otype, u8 speed, u16 gpios)
+{
+ u16 i;
+ u32 ospeedr;
+
+ if (otype == 0x1)
+ GPIO_OTYPER(gpioport) |= gpios;
+ else
+ GPIO_OTYPER(gpioport) &= ~gpios;
+
+ ospeedr = GPIO_OSPEEDR(gpioport);
+
+ for (i = 0; i < 16; i++) {
+ if (!((1 << i) & gpios))
+ continue;
+ ospeedr &= ~GPIO_OSPEED_MASK(i);
+ ospeedr |= GPIO_OSPEED(i, speed);
+ }
+
+ GPIO_OSPEEDR(gpioport) = ospeedr;
+}
+
+void gpio_set_af(u32 gpioport, u8 alt_func_num, u16 gpios)
+{
+ u16 i;
+ u32 afrl, afrh;
+
+ afrl = GPIO_AFRL(gpioport);
+ afrh = GPIO_AFRH(gpioport);
+
+ for (i = 0; i < 8; i++) {
+ if (!((1 << i) & gpios))
+ continue;
+ afrl &= GPIO_AFR_MASK(i);
+ afrl |= GPIO_AFR(i, alt_func_num);
+ }
+
+ for (i = 8; i < 16; i++) {
+ if (!((1 << i) & gpios))
+ continue;
+ afrl &= GPIO_AFR_MASK(i-8);
+ afrh |= GPIO_AFR(i-8, alt_func_num);
+ }
+
+ GPIO_AFRL(gpioport) = afrl;
+ GPIO_AFRH(gpioport) = afrh;
+}
+
+void gpio_set(u32 gpioport, u16 gpios)
+{
+ GPIO_BSRR(gpioport) = gpios;
+}
+
+void gpio_clear(u32 gpioport, u16 gpios)
+{
+ GPIO_BSRR(gpioport) = gpios << 16;
+}
+
+u16 gpio_get(u32 gpioport, u16 gpios)
+{
+ return gpio_port_read(gpioport) & gpios;
+}
+
+void gpio_toggle(u32 gpioport, u16 gpios)
+{
+ GPIO_ODR(gpioport) = GPIO_IDR(gpioport) ^ gpios;
+}
+
+u16 gpio_port_read(u32 gpioport)
+{
+ return (u16)GPIO_IDR(gpioport);
+}
+
+void gpio_port_write(u32 gpioport, u16 data)
+{
+ GPIO_ODR(gpioport) = data;
+}
+
+void gpio_port_config_lock(u32 gpioport, u16 gpios)
+{
+ u32 reg32;
+
+ /* Special "Lock Key Writing Sequence", see datasheet. */
+ GPIO_LCKR(gpioport) = GPIO_LCKK | gpios; /* Set LCKK. */
+ GPIO_LCKR(gpioport) = ~GPIO_LCKK & gpios; /* Clear LCKK. */
+ GPIO_LCKR(gpioport) = GPIO_LCKK | gpios; /* Set LCKK. */
+ reg32 = GPIO_LCKR(gpioport); /* Read LCKK. */
+ reg32 = GPIO_LCKR(gpioport); /* Read LCKK again. */
+
+ /* If (reg32 & GPIO_LCKK) is true, the lock is now active. */
+}
diff --git a/lib/stm32/f4/libopencm3_stm32f4.ld b/lib/stm32/f4/libopencm3_stm32f4.ld
new file mode 100644
index 0000000..fda7d02
--- /dev/null
+++ b/lib/stm32/f4/libopencm3_stm32f4.ld
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Generic linker script for STM32 targets using libopencm3. */
+
+/* Memory regions must be defined in the ld script which includes this one. */
+
+/* Enforce emmition of the vector table. */
+EXTERN (vector_table)
+
+/* Define sections. */
+SECTIONS
+{
+ . = ORIGIN(rom);
+
+ .text : {
+ *(.vectors) /* Vector table */
+ *(.text*) /* Program code */
+ *(.rodata*) /* Read-only data */
+ _etext = .;
+ } >rom
+
+ . = ORIGIN(ram);
+
+ .data : {
+ _data = .;
+ *(.data*) /* Read-write initialized data */
+ _edata = .;
+ } >ram AT >rom
+
+ .bss : {
+ *(.bss*) /* Read-write zero initialized data */
+ *(COMMON)
+ _ebss = .;
+ } >ram AT >rom
+
+ /*
+ * The .eh_frame section appears to be used for C++ exception handling.
+ * You may need to fix this if you're using C++.
+ */
+ /DISCARD/ : { *(.eh_frame) }
+
+ end = .;
+}
+
+PROVIDE(_stack = 0x20000800);
+
diff --git a/lib/stm32/f4/pwr.c b/lib/stm32/f4/pwr.c
new file mode 100644
index 0000000..c7cdd6a
--- /dev/null
+++ b/lib/stm32/f4/pwr.c
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2011 Stephen Caudle <scaudle@doceme.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopencm3/stm32/f4/pwr.h>
+
+void pwr_set_vos_scale(vos_scale_t scale)
+{
+ if (scale == SCALE1)
+ PWR_CR |= PWR_CR_VOS;
+ else if (scale == SCALE2)
+ PWR_CR &= PWR_CR_VOS;
+}
diff --git a/lib/stm32/f4/rcc.c b/lib/stm32/f4/rcc.c
new file mode 100644
index 0000000..1a874c0
--- /dev/null
+++ b/lib/stm32/f4/rcc.c
@@ -0,0 +1,434 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2009 Federico Ruiz-Ugalde <memeruiz at gmail dot com>
+ * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+ * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopencm3/stm32/f4/rcc.h>
+#include <libopencm3/stm32/f4/pwr.h>
+#include <libopencm3/stm32/f4/flash.h>
+
+/* Set the default ppre1 and ppre2 peripheral clock frequencies after reset */
+u32 rcc_ppre1_frequency = 16000000;
+u32 rcc_ppre2_frequency = 16000000;
+
+const clock_scale_t hse_8mhz_3v3[CLOCK_3V3_END] =
+{
+ { /* 120MHz */
+ .pllm = 8,
+ .plln = 240,
+ .pllp = 2,
+ .pllq = 5,
+ .hpre = RCC_CFGR_HPRE_DIV_NONE,
+ .ppre1 = RCC_CFGR_HPRE_DIV_4,
+ .ppre2 = RCC_CFGR_HPRE_DIV_2,
+ .flash_config = FLASH_ICE | FLASH_DCE | FLASH_LATENCY_3WS,
+ .apb1_frequency = 30000000,
+ .apb2_frequency = 60000000,
+ },
+ { /* 168MHz */
+ .pllm = 8,
+ .plln = 336,
+ .pllp = 2,
+ .pllq = 7,
+ .hpre = RCC_CFGR_HPRE_DIV_NONE,
+ .ppre1 = RCC_CFGR_HPRE_DIV_4,
+ .ppre2 = RCC_CFGR_HPRE_DIV_2,
+ .flash_config = FLASH_ICE | FLASH_DCE | FLASH_LATENCY_5WS,
+ .apb1_frequency = 30000000,
+ .apb2_frequency = 60000000,
+ },
+};
+
+void rcc_osc_ready_int_clear(osc_t osc)
+{
+ switch (osc) {
+ case PLL:
+ RCC_CIR |= RCC_CIR_PLLRDYC;
+ break;
+ case HSE:
+ RCC_CIR |= RCC_CIR_HSERDYC;
+ break;
+ case HSI:
+ RCC_CIR |= RCC_CIR_HSIRDYC;
+ break;
+ case LSE:
+ RCC_CIR |= RCC_CIR_LSERDYC;
+ break;
+ case LSI:
+ RCC_CIR |= RCC_CIR_LSIRDYC;
+ break;
+ }
+}
+
+void rcc_osc_ready_int_enable(osc_t osc)
+{
+ switch (osc) {
+ case PLL:
+ RCC_CIR |= RCC_CIR_PLLRDYIE;
+ break;
+ case HSE:
+ RCC_CIR |= RCC_CIR_HSERDYIE;
+ break;
+ case HSI:
+ RCC_CIR |= RCC_CIR_HSIRDYIE;
+ break;
+ case LSE:
+ RCC_CIR |= RCC_CIR_LSERDYIE;
+ break;
+ case LSI:
+ RCC_CIR |= RCC_CIR_LSIRDYIE;
+ break;
+ }
+}
+
+void rcc_osc_ready_int_disable(osc_t osc)
+{
+ switch (osc) {
+ case PLL:
+ RCC_CIR &= ~RCC_CIR_PLLRDYIE;
+ break;
+ case HSE:
+ RCC_CIR &= ~RCC_CIR_HSERDYIE;
+ break;
+ case HSI:
+ RCC_CIR &= ~RCC_CIR_HSIRDYIE;
+ break;
+ case LSE:
+ RCC_CIR &= ~RCC_CIR_LSERDYIE;
+ break;
+ case LSI:
+ RCC_CIR &= ~RCC_CIR_LSIRDYIE;
+ break;
+ }
+}
+
+int rcc_osc_ready_int_flag(osc_t osc)
+{
+ switch (osc) {
+ case PLL:
+ return ((RCC_CIR & RCC_CIR_PLLRDYF) != 0);
+ break;
+ case HSE:
+ return ((RCC_CIR & RCC_CIR_HSERDYF) != 0);
+ break;
+ case HSI:
+ return ((RCC_CIR & RCC_CIR_HSIRDYF) != 0);
+ break;
+ case LSE:
+ return ((RCC_CIR & RCC_CIR_LSERDYF) != 0);
+ break;
+ case LSI:
+ return ((RCC_CIR & RCC_CIR_LSIRDYF) != 0);
+ break;
+ }
+
+ /* Shouldn't be reached. */
+ return -1;
+}
+
+void rcc_css_int_clear(void)
+{
+ RCC_CIR |= RCC_CIR_CSSC;
+}
+
+int rcc_css_int_flag(void)
+{
+ return ((RCC_CIR & RCC_CIR_CSSF) != 0);
+}
+
+void rcc_wait_for_osc_ready(osc_t osc)
+{
+ switch (osc) {
+ case PLL:
+ while ((RCC_CR & RCC_CR_PLLRDY) == 0);
+ break;
+ case HSE:
+ while ((RCC_CR & RCC_CR_HSERDY) == 0);
+ break;
+ case HSI:
+ while ((RCC_CR & RCC_CR_HSIRDY) == 0);
+ break;
+ case LSE:
+ while ((RCC_BDCR & RCC_BDCR_LSERDY) == 0);
+ break;
+ case LSI:
+ while ((RCC_CSR & RCC_CSR_LSIRDY) == 0);
+ break;
+ }
+}
+
+void rcc_wait_for_sysclk_status(osc_t osc)
+{
+ switch (osc) {
+ case PLL:
+ while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_PLL);
+ break;
+ case HSE:
+ while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_HSE);
+ break;
+ case HSI:
+ while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_HSI);
+ break;
+ default:
+ /* Shouldn't be reached. */
+ break;
+ }
+}
+
+void rcc_osc_on(osc_t osc)
+{
+ switch (osc) {
+ case PLL:
+ RCC_CR |= RCC_CR_PLLON;
+ break;
+ case HSE:
+ RCC_CR |= RCC_CR_HSEON;
+ break;
+ case HSI:
+ RCC_CR |= RCC_CR_HSION;
+ break;
+ case LSE:
+ RCC_BDCR |= RCC_BDCR_LSEON;
+ break;
+ case LSI:
+ RCC_CSR |= RCC_CSR_LSION;
+ break;
+ }
+}
+
+void rcc_osc_off(osc_t osc)
+{
+ switch (osc) {
+ case PLL:
+ RCC_CR &= ~RCC_CR_PLLON;
+ break;
+ case HSE:
+ RCC_CR &= ~RCC_CR_HSEON;
+ break;
+ case HSI:
+ RCC_CR &= ~RCC_CR_HSION;
+ break;
+ case LSE:
+ RCC_BDCR &= ~RCC_BDCR_LSEON;
+ break;
+ case LSI:
+ RCC_CSR &= ~RCC_CSR_LSION;
+ break;
+ }
+}
+
+void rcc_css_enable(void)
+{
+ RCC_CR |= RCC_CR_CSSON;
+}
+
+void rcc_css_disable(void)
+{
+ RCC_CR &= ~RCC_CR_CSSON;
+}
+
+void rcc_osc_bypass_enable(osc_t osc)
+{
+ switch (osc) {
+ case HSE:
+ RCC_CR |= RCC_CR_HSEBYP;
+ break;
+ case LSE:
+ RCC_BDCR |= RCC_BDCR_LSEBYP;
+ break;
+ case PLL:
+ case HSI:
+ case LSI:
+ /* Do nothing, only HSE/LSE allowed here. */
+ break;
+ }
+}
+
+void rcc_osc_bypass_disable(osc_t osc)
+{
+ switch (osc) {
+ case HSE:
+ RCC_CR &= ~RCC_CR_HSEBYP;
+ break;
+ case LSE:
+ RCC_BDCR &= ~RCC_BDCR_LSEBYP;
+ break;
+ case PLL:
+ case HSI:
+ case LSI:
+ /* Do nothing, only HSE/LSE allowed here. */
+ break;
+ }
+}
+
+void rcc_peripheral_enable_clock(volatile u32 *reg, u32 en)
+{
+ *reg |= en;
+}
+
+void rcc_peripheral_disable_clock(volatile u32 *reg, u32 en)
+{
+ *reg &= ~en;
+}
+
+void rcc_peripheral_reset(volatile u32 *reg, u32 reset)
+{
+ *reg |= reset;
+}
+
+void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset)
+{
+ *reg &= ~clear_reset;
+}
+
+void rcc_set_sysclk_source(u32 clk)
+{
+ u32 reg32;
+
+ reg32 = RCC_CFGR;
+ reg32 &= ~((1 << 1) | (1 << 0));
+ RCC_CFGR = (reg32 | clk);
+}
+
+void rcc_set_pll_source(u32 pllsrc)
+{
+ u32 reg32;
+
+ reg32 = RCC_PLLCFGR;
+ reg32 &= ~(1 << 22);
+ RCC_PLLCFGR = (reg32 | (pllsrc << 22));
+}
+
+void rcc_set_ppre2(u32 ppre2)
+{
+ u32 reg32;
+
+ reg32 = RCC_CFGR;
+ reg32 &= ~((1 << 11) | (1 << 12) | (1 << 13));
+ RCC_CFGR = (reg32 | (ppre2 << 11));
+}
+
+void rcc_set_ppre1(u32 ppre1)
+{
+ u32 reg32;
+
+ reg32 = RCC_CFGR;
+ reg32 &= ~((1 << 8) | (1 << 9) | (1 << 10));
+ RCC_CFGR = (reg32 | (ppre1 << 8));
+}
+
+void rcc_set_hpre(u32 hpre)
+{
+ u32 reg32;
+
+ reg32 = RCC_CFGR;
+ reg32 &= ~((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7));
+ RCC_CFGR = (reg32 | (hpre << 4));
+}
+
+void rcc_set_rtcpre(u32 rtcpre)
+{
+ u32 reg32;
+
+ reg32 = RCC_CFGR;
+ reg32 &= ~((1 << 16) | (1 << 17) | (1 << 18) | (1 << 19) | (1 << 20));
+ RCC_CFGR = (reg32 | (rtcpre << 16));
+}
+
+void rcc_set_main_pll_hsi(u32 pllm, u32 plln, u32 pllp, u32 pllq)
+{
+ RCC_PLLCFGR = (pllm << RCC_PLLCFGR_PLLM_SHIFT) |
+ (plln << RCC_PLLCFGR_PLLN_SHIFT) |
+ (((pllp >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT) |
+ (pllq << RCC_PLLCFGR_PLLQ_SHIFT);
+}
+
+void rcc_set_main_pll_hse(u32 pllm, u32 plln, u32 pllp, u32 pllq)
+{
+ RCC_PLLCFGR = (pllm << RCC_PLLCFGR_PLLM_SHIFT) |
+ (plln << RCC_PLLCFGR_PLLN_SHIFT) |
+ (((pllp >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT) |
+ RCC_PLLCFGR_PLLSRC |
+ (pllq << RCC_PLLCFGR_PLLQ_SHIFT);
+}
+
+u32 rcc_system_clock_source(void)
+{
+ /* Return the clock source which is used as system clock. */
+ return ((RCC_CFGR & 0x000c) >> 2);
+}
+
+void rcc_clock_setup_hse_3v3(const clock_scale_t *clock)
+{
+ /* Enable internal high-speed oscillator. */
+ rcc_osc_on(HSI);
+ rcc_wait_for_osc_ready(HSI);
+
+ /* Select HSI as SYSCLK source. */
+ rcc_set_sysclk_source(RCC_CFGR_SW_HSI);
+
+ /* Enable external high-speed oscillator 8MHz. */
+ rcc_osc_on(HSE);
+ rcc_wait_for_osc_ready(HSE);
+
+ /* Enable/disable high performance mode */
+ if (!clock->power_save)
+ pwr_set_vos_scale(SCALE1);
+ else
+ pwr_set_vos_scale(SCALE2);
+
+ /*
+ * Set prescalers for AHB, ADC, ABP1, ABP2.
+ * Do this before touching the PLL (TODO: why?).
+ */
+ rcc_set_hpre(clock->hpre);
+ rcc_set_ppre1(clock->ppre1);
+ rcc_set_ppre2(clock->ppre2);
+
+ rcc_set_main_pll_hse(clock->pllm,
+ clock->plln,
+ clock->pllp,
+ clock->pllq);
+
+ /* Enable PLL oscillator and wait for it to stabilize. */
+ rcc_osc_on(PLL);
+ rcc_wait_for_osc_ready(PLL);
+
+ /* Configure flash settings */
+ flash_set_ws(clock->flash_config);
+
+ /* Select PLL as SYSCLK source. */
+ rcc_set_sysclk_source(RCC_CFGR_SW_PLL);
+
+ /* Wait for PLL clock to be selected. */
+ rcc_wait_for_sysclk_status(PLL);
+
+ /* Set the peripheral clock frequencies used */
+ rcc_ppre1_frequency = clock->apb1_frequency;
+ rcc_ppre2_frequency = clock->apb2_frequency;
+}
+
+void rcc_backupdomain_reset(void)
+{
+ /* Set the backup domain software reset. */
+ RCC_BDCR |= RCC_BDCR_BDRST;
+
+ /* Clear the backup domain software reset. */
+ RCC_BDCR &= ~RCC_BDCR_BDRST;
+}
diff --git a/lib/stm32/f4/scb.c b/lib/stm32/f4/scb.c
new file mode 100644
index 0000000..18c1337
--- /dev/null
+++ b/lib/stm32/f4/scb.c
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Gareth McMullin <gareth@blacksphere.co.nz>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopencm3/stm32/f4/scb.h>
+
+void scb_reset_core(void)
+{
+ SCB_AIRCR = SCB_AIRCR_VECTKEY | SCB_AIRCR_VECTRESET;
+}
+
+void scb_reset_system(void)
+{
+ SCB_AIRCR = SCB_AIRCR_VECTKEY | SCB_AIRCR_SYSRESETREQ;
+}
diff --git a/lib/stm32/f4/vector.c b/lib/stm32/f4/vector.c
new file mode 100644
index 0000000..d6f70f8
--- /dev/null
+++ b/lib/stm32/f4/vector.c
@@ -0,0 +1,336 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
+ * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define WEAK __attribute__ ((weak))
+
+/* Symbols exported by linker script */
+extern unsigned _etext, _data, _edata, _ebss, _stack;
+
+void main(void);
+void reset_handler(void);
+void blocking_handler(void);
+void null_handler(void);
+
+void WEAK reset_handler(void);
+void WEAK nmi_handler(void);
+void WEAK hard_fault_handler(void);
+void WEAK mem_manage_handler(void);
+void WEAK bus_fault_handler(void);
+void WEAK usage_fault_handler(void);
+void WEAK sv_call_handler(void);
+void WEAK debug_monitor_handler(void);
+void WEAK pend_sv_handler(void);
+void WEAK sys_tick_handler(void);
+void WEAK wwdg_isr(void);
+void WEAK pvd_isr(void);
+void WEAK tamp_stamp_isr(void);
+void WEAK rtc_wkup_isr(void);
+void WEAK flash_isr(void);
+void WEAK rcc_isr(void);
+void WEAK exti0_isr(void);
+void WEAK exti1_isr(void);
+void WEAK exti2_isr(void);
+void WEAK exti3_isr(void);
+void WEAK exti4_isr(void);
+void WEAK dma1_stream0_isr(void);
+void WEAK dma1_stream1_isr(void);
+void WEAK dma1_stream2_isr(void);
+void WEAK dma1_stream3_isr(void);
+void WEAK dma1_stream4_isr(void);
+void WEAK dma1_stream5_isr(void);
+void WEAK dma1_stream6_isr(void);
+void WEAK adc_isr(void);
+void WEAK can1_tx_isr(void);
+void WEAK can1_rx0_isr(void);
+void WEAK can1_rx1_isr(void);
+void WEAK can1_sce_isr(void);
+void WEAK exti9_5_isr(void);
+void WEAK tim1_brk_tim9_isr(void);
+void WEAK tim1_up_tim10_isr(void);
+void WEAK tim1_trg_com_tim11_isr(void);
+void WEAK tim1_cc_isr(void);
+void WEAK tim2_isr(void);
+void WEAK tim3_isr(void);
+void WEAK tim4_isr(void);
+void WEAK i2c1_ev_isr(void);
+void WEAK i2c1_er_isr(void);
+void WEAK i2c2_ev_isr(void);
+void WEAK i2c2_er_isr(void);
+void WEAK spi1_isr(void);
+void WEAK spi2_isr(void);
+void WEAK usart1_isr(void);
+void WEAK usart2_isr(void);
+void WEAK usart3_isr(void);
+void WEAK exti15_10_isr(void);
+void WEAK rtc_alarm_isr(void);
+void WEAK usb_fs_wkup_isr(void);
+void WEAK tim8_brk_tim12_isr(void);
+void WEAK tim8_up_tim13_isr(void);
+void WEAK tim8_trg_com_tim14_isr(void);
+void WEAK tim8_cc_isr(void);
+void WEAK dma1_stream7_isr(void);
+void WEAK fsmc_isr(void);
+void WEAK sdio_isr(void);
+void WEAK tim5_isr(void);
+void WEAK spi3_isr(void);
+void WEAK usart4_isr(void);
+void WEAK usart5_isr(void);
+void WEAK tim6_dac_isr(void);
+void WEAK tim7_isr(void);
+void WEAK dma2_stream0_isr(void);
+void WEAK dma2_stream1_isr(void);
+void WEAK dma2_stream2_isr(void);
+void WEAK dma2_stream3_isr(void);
+void WEAK dma2_stream4_isr(void);
+void WEAK eth_isr(void);
+void WEAK eth_wkup_isr(void);
+void WEAK can2_tx_isr(void);
+void WEAK can2_rx0_isr(void);
+void WEAK can2_rx1_isr(void);
+void WEAK can2_sce_isr(void);
+void WEAK otg_fs_isr(void);
+void WEAK dma2_stream5_isr(void);
+void WEAK dma2_stream6_isr(void);
+void WEAK dma2_stream7_isr(void);
+void WEAK usart6_isr(void);
+void WEAK i2c3_ev_isr(void);
+void WEAK i2c3_er_isr(void);
+void WEAK otg_hs_ep1_out_isr(void);
+void WEAK otg_hs_ep1_in_isr(void);
+void WEAK otg_hs_wkup_isr(void);
+void WEAK otg_hs_isr(void);
+void WEAK dcmi_isr(void);
+void WEAK cryp_isr(void);
+void WEAK hash_rng_isr(void);
+
+__attribute__ ((section(".vectors")))
+void (*const vector_table[]) (void) = {
+ (void*)&_stack,
+ reset_handler,
+ nmi_handler,
+ hard_fault_handler,
+ mem_manage_handler,
+ bus_fault_handler,
+ usage_fault_handler,
+ 0, 0, 0, 0, /* Reserved */
+ sv_call_handler,
+ debug_monitor_handler,
+ 0, /* Reserved */
+ pend_sv_handler,
+ sys_tick_handler,
+ wwdg_isr,
+ pvd_isr,
+ tamp_stamp_isr,
+ rtc_wkup_isr,
+ flash_isr,
+ rcc_isr,
+ exti0_isr,
+ exti1_isr,
+ exti2_isr,
+ exti3_isr,
+ exti4_isr,
+ dma1_stream0_isr,
+ dma1_stream1_isr,
+ dma1_stream2_isr,
+ dma1_stream3_isr,
+ dma1_stream4_isr,
+ dma1_stream5_isr,
+ dma1_stream6_isr,
+ adc_isr,
+ can1_tx_isr,
+ can1_rx0_isr,
+ can1_rx1_isr,
+ can1_sce_isr,
+ exti9_5_isr,
+ tim1_brk_tim9_isr,
+ tim1_up_tim10_isr,
+ tim1_trg_com_tim11_isr,
+ tim1_cc_isr,
+ tim2_isr,
+ tim3_isr,
+ tim4_isr,
+ i2c1_ev_isr,
+ i2c1_er_isr,
+ i2c2_ev_isr,
+ i2c2_er_isr,
+ spi1_isr,
+ spi2_isr,
+ usart1_isr,
+ usart2_isr,
+ usart3_isr,
+ exti15_10_isr,
+ rtc_alarm_isr,
+ usb_fs_wkup_isr,
+ tim8_brk_tim12_isr,
+ tim8_up_tim13_isr,
+ tim8_trg_com_tim14_isr,
+ tim8_cc_isr,
+ dma1_stream7_isr,
+ fsmc_isr,
+ sdio_isr,
+ tim5_isr,
+ spi3_isr,
+ usart4_isr,
+ usart5_isr,
+ tim6_dac_isr,
+ tim7_isr,
+ dma2_stream0_isr,
+ dma2_stream1_isr,
+ dma2_stream2_isr,
+ dma2_stream3_isr,
+ dma2_stream4_isr,
+ eth_isr,
+ eth_wkup_isr,
+ can2_tx_isr,
+ can2_rx0_isr,
+ can2_rx1_isr,
+ can2_sce_isr,
+ otg_fs_isr,
+ dma2_stream5_isr,
+ dma2_stream6_isr,
+ dma2_stream7_isr,
+ usart6_isr,
+ i2c3_ev_isr,
+ i2c3_er_isr,
+ otg_hs_ep1_out_isr,
+ otg_hs_ep1_in_isr,
+ otg_hs_wkup_isr,
+ otg_hs_isr,
+ dcmi_isr,
+ cryp_isr,
+ hash_rng_isr,
+};
+
+void reset_handler(void)
+{
+ volatile unsigned *src, *dest;
+ asm("MSR msp, %0" : : "r"(&_stack));
+
+ for (src = &_etext, dest = &_data; dest < &_edata; src++, dest++)
+ *dest = *src;
+
+ while (dest < &_ebss)
+ *dest++ = 0;
+
+ /* Call the application's entry point. */
+ main();
+}
+
+void blocking_handler(void)
+{
+ while (1) ;
+}
+
+void null_handler(void)
+{
+ /* Do nothing. */
+}
+
+#pragma weak nmi_handler = null_handler
+#pragma weak hard_fault_handler = blocking_handler
+#pragma weak mem_manage_handler = blocking_handler
+#pragma weak bus_fault_handler = blocking_handler
+#pragma weak usage_fault_handler = blocking_handler
+#pragma weak sv_call_handler = null_handler
+#pragma weak debug_monitor_handler = null_handler
+#pragma weak pend_sv_handler = null_handler
+#pragma weak sys_tick_handler = null_handler
+#pragma weak wwdg_isr = null_handler
+#pragma weak pvd_isr = null_handler
+#pragma weak tamp_stamp_isr = null_handler
+#pragma weak rtc_wkup_isr = null_handler
+#pragma weak flash_isr = null_handler
+#pragma weak rcc_isr = null_handler
+#pragma weak exti0_isr = null_handler
+#pragma weak exti1_isr = null_handler
+#pragma weak exti2_isr = null_handler
+#pragma weak exti3_isr = null_handler
+#pragma weak exti4_isr = null_handler
+#pragma weak dma1_stream0_isr = null_handler
+#pragma weak dma1_stream1_isr = null_handler
+#pragma weak dma1_stream2_isr = null_handler
+#pragma weak dma1_stream3_isr = null_handler
+#pragma weak dma1_stream4_isr = null_handler
+#pragma weak dma1_stream5_isr = null_handler
+#pragma weak dma1_stream6_isr = null_handler
+#pragma weak adc_isr = null_handler
+#pragma weak can1_tx_isr = null_handler
+#pragma weak can1_rx0_isr = null_handler
+#pragma weak can1_rx1_isr = null_handler
+#pragma weak can1_sce_isr = null_handler
+#pragma weak exti9_5_isr = null_handler
+#pragma weak tim1_brk_tim9_isr = null_handler
+#pragma weak tim1_up_tim10_isr = null_handler
+#pragma weak tim1_trg_com_tim11_isr = null_handler
+#pragma weak tim1_cc_isr = null_handler
+#pragma weak tim2_isr = null_handler
+#pragma weak tim3_isr = null_handler
+#pragma weak tim4_isr = null_handler
+#pragma weak i2c1_ev_isr = null_handler
+#pragma weak i2c1_er_isr = null_handler
+#pragma weak i2c2_ev_isr = null_handler
+#pragma weak i2c2_er_isr = null_handler
+#pragma weak spi1_isr = null_handler
+#pragma weak spi2_isr = null_handler
+#pragma weak usart1_isr = null_handler
+#pragma weak usart2_isr = null_handler
+#pragma weak usart3_isr = null_handler
+#pragma weak exti15_10_isr = null_handler
+#pragma weak rtc_alarm_isr = null_handler
+#pragma weak usb_fs_wkup_isr = null_handler
+#pragma weak tim8_brk_tim12_isr = null_handler
+#pragma weak tim8_up_tim13_isr = null_handler
+#pragma weak tim8_trg_com_tim14_isr = null_handler
+#pragma weak tim8_cc_isr = null_handler
+#pragma weak dma1_stream7_isr = null_handler
+#pragma weak fsmc_isr = null_handler
+#pragma weak sdio_isr = null_handler
+#pragma weak tim5_isr = null_handler
+#pragma weak spi3_isr = null_handler
+#pragma weak usart4_isr = null_handler
+#pragma weak usart5_isr = null_handler
+#pragma weak tim6_dac_isr = null_handler
+#pragma weak tim7_isr = null_handler
+#pragma weak dma2_stream0_isr = null_handler
+#pragma weak dma2_stream1_isr = null_handler
+#pragma weak dma2_stream2_isr = null_handler
+#pragma weak dma2_stream3_isr = null_handler
+#pragma weak dma2_stream4_isr = null_handler
+#pragma weak eth_isr = null_handler
+#pragma weak eth_wkup_isr = null_handler
+#pragma weak can2_tx_isr = null_handler
+#pragma weak can2_rx0_isr = null_handler
+#pragma weak can2_rx1_isr = null_handler
+#pragma weak can2_sce_isr = null_handler
+#pragma weak otg_fs_isr = null_handler
+#pragma weak dma2_stream5_isr = null_handler
+#pragma weak dma2_stream6_isr = null_handler
+#pragma weak dma2_stream7_isr = null_handler
+#pragma weak usart6_isr = null_handler
+#pragma weak i2c3_ev_isr = null_handler
+#pragma weak i2c3_er_isr = null_handler
+#pragma weak otg_hs_ep1_out_isr = null_handler
+#pragma weak otg_hs_ep1_in_isr = null_handler
+#pragma weak otg_hs_wkup_isr = null_handler
+#pragma weak otg_hs_isr = null_handler
+#pragma weak dcmi_isr = null_handler
+#pragma weak cryp_isr = null_handler
+#pragma weak hash_rng_isr = null_handler
+