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authorStephen Caudle2011-10-28 15:44:29 -0400
committerStephen Caudle2011-10-30 17:42:49 -0400
commitb3a710b0bcc8e765b32cc255dc5047323933d22e (patch)
treeb77acc4dfa1a0b7170121124f0563faac906a0ee /lib/stm32f2
parent3900d16740b790ea2603b8fa7f627da7ff5a9753 (diff)
Rename stm32 lib folders to be consistent with include
Diffstat (limited to 'lib/stm32f2')
-rw-r--r--lib/stm32f2/Makefile59
-rw-r--r--lib/stm32f2/exti.c146
-rw-r--r--lib/stm32f2/flash.c250
-rw-r--r--lib/stm32f2/gpio.c139
-rw-r--r--lib/stm32f2/libopencm3_stm32f2.ld63
-rw-r--r--lib/stm32f2/rcc.c412
-rw-r--r--lib/stm32f2/vector.c336
7 files changed, 0 insertions, 1405 deletions
diff --git a/lib/stm32f2/Makefile b/lib/stm32f2/Makefile
deleted file mode 100644
index 496f4a5..0000000
--- a/lib/stm32f2/Makefile
+++ /dev/null
@@ -1,59 +0,0 @@
-##
-## This file is part of the libopencm3 project.
-##
-## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software: you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation, either version 3 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program. If not, see <http://www.gnu.org/licenses/>.
-##
-
-LIBNAME = libopencm3_stm32f2
-
-PREFIX ?= arm-none-eabi
-# PREFIX ?= arm-elf
-CC = $(PREFIX)-gcc
-AR = $(PREFIX)-ar
-CFLAGS = -Os -g -Wall -Wextra -I../../include -fno-common \
- -mcpu=cortex-m3 -mthumb -Wstrict-prototypes \
- -ffunction-sections -fdata-sections -MD -DSTM32F2
-# ARFLAGS = rcsv
-ARFLAGS = rcs
-OBJS = vector.o gpio.o systick.o i2c.o spi.o nvic.o usart.o exti.o rcc.o flash.o
-
-#VPATH += ../usb
-VPATH += ../stm32_common
-
-# Be silent per default, but 'make V=1' will show all compiler calls.
-ifneq ($(V),1)
-Q := @
-endif
-
-all: $(LIBNAME).a
-
-$(LIBNAME).a: $(OBJS)
- @printf " AR $(subst $(shell pwd)/,,$(@))\n"
- $(Q)$(AR) $(ARFLAGS) $@ $^
-
-%.o: %.c
- @printf " CC $(subst $(shell pwd)/,,$(@))\n"
- $(Q)$(CC) $(CFLAGS) -o $@ -c $<
-
-clean:
- @printf " CLEAN lib/stm32f2\n"
- $(Q)rm -f *.o *.d
- $(Q)rm -f $(LIBNAME).a
-
-.PHONY: clean
-
--include $(OBJS:.o=.d)
-
diff --git a/lib/stm32f2/exti.c b/lib/stm32f2/exti.c
deleted file mode 100644
index 1db9ad7..0000000
--- a/lib/stm32f2/exti.c
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * This file is part of the libopencm3 project.
- *
- * Copyright (C) 2010 Mark Butler <mbutler@physics.otago.ac.nz>
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <libopencm3/stm32/exti.h>
-#include <libopencm3/stm32/f2/syscfg.h>
-#include <libopencm3/stm32/f2/gpio.h>
-
-void exti_set_trigger(u32 extis, exti_trigger_type trig)
-{
- switch (trig) {
- case EXTI_TRIGGER_RISING:
- EXTI_RTSR |= extis;
- EXTI_FTSR &= ~extis;
- break;
- case EXTI_TRIGGER_FALLING:
- EXTI_RTSR &= ~extis;
- EXTI_FTSR |= extis;
- break;
- case EXTI_TRIGGER_BOTH:
- EXTI_RTSR |= extis;
- EXTI_FTSR |= extis;
- break;
- }
-}
-
-void exti_enable_request(u32 extis)
-{
- /* Enable interrupts. */
- EXTI_IMR |= extis;
-
- /* Enable events. */
- EXTI_EMR |= extis;
-}
-
-void exti_disable_request(u32 extis)
-{
- /* Disable interrupts. */
- EXTI_IMR &= ~extis;
-
- /* Disable events. */
- EXTI_EMR &= ~extis;
-}
-
-/*
- * Reset the interrupt request by writing a 1 to the corresponding
- * pending bit register.
- */
-void exti_reset_request(u32 extis)
-{
- EXTI_PR = extis;
-}
-
-/*
- * Remap an external interrupt line to the corresponding pin on the
- * specified GPIO port.
- *
- * TODO: This could be rewritten in fewer lines of code.
- */
-void exti_select_source(u32 exti, u32 gpioport)
-{
- u8 shift, bits;
-
- shift = bits = 0;
-
- switch (exti) {
- case EXTI0:
- case EXTI4:
- case EXTI8:
- case EXTI12:
- shift = 0;
- break;
- case EXTI1:
- case EXTI5:
- case EXTI9:
- case EXTI13:
- shift = 4;
- break;
- case EXTI2:
- case EXTI6:
- case EXTI10:
- case EXTI14:
- shift = 8;
- break;
- case EXTI3:
- case EXTI7:
- case EXTI11:
- case EXTI15:
- shift = 12;
- break;
- }
-
- switch (gpioport) {
- case GPIOA:
- bits = 0xf;
- break;
- case GPIOB:
- bits = 0xe;
- break;
- case GPIOC:
- bits = 0xd;
- break;
- case GPIOD:
- bits = 0xc;
- break;
- case GPIOE:
- bits = 0xb;
- break;
- case GPIOF:
- bits = 0xa;
- break;
- case GPIOG:
- bits = 0x9;
- break;
- }
-
- /* Ensure that only valid EXTI lines are used. */
- if (exti < EXTI4) {
- SYSCFG_EXTICR1 &= ~(0x000F << shift);
- SYSCFG_EXTICR1 |= (~bits << shift);
- } else if (exti < EXTI8) {
- SYSCFG_EXTICR2 &= ~(0x000F << shift);
- SYSCFG_EXTICR2 |= (~bits << shift);
- } else if (exti < EXTI12) {
- SYSCFG_EXTICR3 &= ~(0x000F << shift);
- SYSCFG_EXTICR3 |= (~bits << shift);
- } else if (exti < EXTI16) {
- SYSCFG_EXTICR4 &= ~(0x000F << shift);
- SYSCFG_EXTICR4 |= (~bits << shift);
- }
-}
diff --git a/lib/stm32f2/flash.c b/lib/stm32f2/flash.c
deleted file mode 100644
index e9bc73e..0000000
--- a/lib/stm32f2/flash.c
+++ /dev/null
@@ -1,250 +0,0 @@
-/*
- * This file is part of the libopencm3 project.
- *
- * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
- * Copyright (C) 2010 Mark Butler <mbutler@physics.otago.ac.nz>
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <libopencm3/stm32/f2/flash.h>
-
-static inline void flash_set_program_size(u32 psize)
-{
- FLASH_CR &= ~(((1 << 0) | (1 << 1)) << 8);
- FLASH_CR |= psize;
-}
-
-void flash_data_cache_enable(void)
-{
- FLASH_ACR |= FLASH_DCE;
-}
-
-void flash_dcache_disable(void)
-{
- FLASH_ACR &= ~FLASH_DCE;
-}
-
-void flash_icache_enable(void)
-{
- FLASH_ACR |= FLASH_ICE;
-}
-
-void flash_icache_disable(void)
-{
- FLASH_ACR &= ~FLASH_ICE;
-}
-
-void flash_prefetch_enable(void)
-{
- FLASH_ACR |= FLASH_PRFTEN;
-}
-
-void flash_prefetch_disable(void)
-{
- FLASH_ACR &= ~FLASH_PRFTEN;
-}
-
-void flash_dcache_reset(void)
-{
- FLASH_ACR |= FLASH_DCRST;
-}
-
-void flash_icache_reset(void)
-{
- FLASH_ACR |= FLASH_ICRST;
-}
-
-void flash_set_ws(u32 ws)
-{
- u32 reg32;
-
- reg32 = FLASH_ACR;
- reg32 &= ~((1 << 0) | (1 << 1) | (1 << 2));
- reg32 |= ws;
- FLASH_ACR = reg32;
-}
-
-void flash_unlock(void)
-{
- /* Authorize the FPEC access. */
- FLASH_KEYR = FLASH_KEY1;
- FLASH_KEYR = FLASH_KEY2;
-}
-
-void flash_lock(void)
-{
- FLASH_CR |= FLASH_LOCK;
-}
-
-void flash_clear_pgserr_flag(void)
-{
- FLASH_SR |= FLASH_PGSERR;
-}
-
-void flash_clear_pgperr_flag(void)
-{
- FLASH_SR |= FLASH_PGPERR;
-}
-
-void flash_clear_pgaerr_flag(void)
-{
- FLASH_SR |= FLASH_PGAERR;
-}
-
-void flash_clear_eop_flag(void)
-{
- FLASH_SR |= FLASH_EOP;
-}
-
-void flash_clear_wrperr_flag(void)
-{
- FLASH_SR |= FLASH_WRPERR;
-}
-
-void flash_clear_bsy_flag(void)
-{
- FLASH_SR &= ~FLASH_BSY;
-}
-
-void flash_clear_status_flags(void)
-{
- flash_clear_pgserr_flag();
- flash_clear_pgperr_flag();
- flash_clear_pgaerr_flag();
- flash_clear_eop_flag();
- flash_clear_wrperr_flag();
- flash_clear_bsy_flag();
-}
-
-void flash_unlock_option_bytes(void)
-{
- FLASH_OPTKEYR = FLASH_OPTKEY1;
- FLASH_OPTKEYR = FLASH_OPTKEY2;
-}
-
-void flash_lock_option_bytes(void)
-{
- FLASH_OPTCR |= FLASH_OPTLOCK;
-}
-
-void flash_wait_for_last_operation(void)
-{
- while ((FLASH_SR & FLASH_BSY) == FLASH_BSY)
- ;
-}
-
-void flash_program_double_word(u32 address, u64 data, u32 program_size)
-{
- /* Ensure that all flash operations are complete. */
- flash_wait_for_last_operation();
- flash_set_program_size(program_size);
-
- /* Enable writes to flash. */
- FLASH_CR |= FLASH_PG;
-
- /* Program the first half of the word. */
- MMIO64(address) = data;
-
- /* Wait for the write to complete. */
- flash_wait_for_last_operation();
-
- /* Disable writes to flash. */
- FLASH_CR &= ~FLASH_PG;
-}
-
-void flash_program_word(u32 address, u32 data, u32 program_size)
-{
- /* Ensure that all flash operations are complete. */
- flash_wait_for_last_operation();
- flash_set_program_size(program_size);
-
- /* Enable writes to flash. */
- FLASH_CR |= FLASH_PG;
-
- /* Program the first half of the word. */
- MMIO32(address) = data;
-
- /* Wait for the write to complete. */
- flash_wait_for_last_operation();
-
- /* Disable writes to flash. */
- FLASH_CR &= ~FLASH_PG;
-}
-
-void flash_program_half_word(u32 address, u16 data, u32 program_size)
-{
- flash_wait_for_last_operation();
- flash_set_program_size(program_size);
-
- FLASH_CR |= FLASH_PG;
-
- MMIO16(address) = data;
-
- flash_wait_for_last_operation();
-
- FLASH_CR &= ~FLASH_PG; /* Disable the PG bit. */
-}
-
-void flash_program_byte(u32 address, u8 data, u32 program_size)
-{
- flash_wait_for_last_operation();
- flash_set_program_size(program_size);
-
- FLASH_CR |= FLASH_PG;
-
- MMIO8(address) = data;
-
- flash_wait_for_last_operation();
-
- FLASH_CR &= ~FLASH_PG; /* Disable the PG bit. */
-}
-
-void flash_erase_sector(u32 sector, u32 program_size)
-{
- flash_wait_for_last_operation();
- flash_set_program_size(program_size);
-
- FLASH_CR &= ~(((1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)) << 3);
- FLASH_CR |= sector;
- FLASH_CR |= FLASH_STRT;
-
- flash_wait_for_last_operation();
- FLASH_CR &= ~FLASH_SER;
- FLASH_CR &= ~(((1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)) << 3);
-}
-
-void flash_erase_all_sectors(u32 program_size)
-{
- flash_wait_for_last_operation();
- flash_set_program_size(program_size);
-
- FLASH_CR |= FLASH_MER; /* Enable mass erase. */
- FLASH_CR |= FLASH_STRT; /* Trigger the erase. */
-
- flash_wait_for_last_operation();
- FLASH_CR &= ~FLASH_MER; /* Disable mass erase. */
-}
-
-void flash_program_option_bytes(u32 data)
-{
- flash_wait_for_last_operation();
-
- if (FLASH_OPTCR & FLASH_OPTLOCK)
- flash_unlock_option_bytes();
-
- FLASH_OPTCR = data & ~0x3;
- FLASH_OPTCR |= FLASH_OPTSTRT; /* Enable option byte programming. */
- flash_wait_for_last_operation();
-}
diff --git a/lib/stm32f2/gpio.c b/lib/stm32f2/gpio.c
deleted file mode 100644
index 6e1ef08..0000000
--- a/lib/stm32f2/gpio.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
- * This file is part of the libopencm3 project.
- *
- * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <libopencm3/stm32/f2/gpio.h>
-
-void gpio_mode_setup(u32 gpioport, u8 mode, u8 pull_up_down, u16 gpios)
-{
- u16 i;
- u32 moder, pupd;
-
- /*
- * We want to set the config only for the pins mentioned in gpios,
- * but keeping the others, so read out the actual config first.
- */
- moder = GPIO_MODER(gpioport);
- pupd = GPIO_PUPDR(gpioport);
-
- for (i = 0; i < 16; i++) {
- if (!((1 << i) & gpios))
- continue;
-
- moder &= ~GPIO_MODE_MASK(i);
- moder |= GPIO_MODE(i, mode);
- pupd &= ~GPIO_PUPD_MASK(i);
- pupd |= GPIO_PUPD(i, pull_up_down);
- }
-
- /* Set mode and pull up/down control registers. */
- GPIO_MODER(gpioport) = moder;
- GPIO_PUPDR(gpioport) = pupd;
-}
-
-void gpio_set_output_options(u32 gpioport, u8 otype, u8 speed, u16 gpios)
-{
- u16 i;
- u32 ospeedr;
-
- if (otype == 0x1)
- GPIO_OTYPER(gpioport) |= gpios;
- else
- GPIO_OTYPER(gpioport) &= ~gpios;
-
- ospeedr = GPIO_OSPEEDR(gpioport);
-
- for (i = 0; i < 16; i++) {
- if (!((1 << i) & gpios))
- continue;
- ospeedr &= ~GPIO_OSPEED_MASK(i);
- ospeedr |= GPIO_OSPEED(i, speed);
- }
-
- GPIO_OSPEEDR(gpioport) = ospeedr;
-}
-
-void gpio_set_af(u32 gpioport, u8 alt_func_num, u16 gpios)
-{
- u16 i;
- u32 afrl, afrh;
-
- afrl = GPIO_AFRL(gpioport);
- afrh = GPIO_AFRH(gpioport);
-
- for (i = 0; i < 8; i++) {
- if (!((1 << i) & gpios))
- continue;
- afrl &= GPIO_AFR_MASK(i);
- afrl |= GPIO_AFR(i, alt_func_num);
- }
-
- for (i = 8; i < 16; i++) {
- if (!((1 << i) & gpios))
- continue;
- afrl &= GPIO_AFR_MASK(i-8);
- afrh |= GPIO_AFR(i-8, alt_func_num);
- }
-
- GPIO_AFRL(gpioport) = afrl;
- GPIO_AFRH(gpioport) = afrh;
-}
-
-void gpio_set(u32 gpioport, u16 gpios)
-{
- GPIO_BSRR(gpioport) = gpios;
-}
-
-void gpio_clear(u32 gpioport, u16 gpios)
-{
- GPIO_BSRR(gpioport) = gpios << 16;
-}
-
-u16 gpio_get(u32 gpioport, u16 gpios)
-{
- return gpio_port_read(gpioport) & gpios;
-}
-
-void gpio_toggle(u32 gpioport, u16 gpios)
-{
- GPIO_ODR(gpioport) = GPIO_IDR(gpioport) ^ gpios;
-}
-
-u16 gpio_port_read(u32 gpioport)
-{
- return (u16)GPIO_IDR(gpioport);
-}
-
-void gpio_port_write(u32 gpioport, u16 data)
-{
- GPIO_ODR(gpioport) = data;
-}
-
-void gpio_port_config_lock(u32 gpioport, u16 gpios)
-{
- u32 reg32;
-
- /* Special "Lock Key Writing Sequence", see datasheet. */
- GPIO_LCKR(gpioport) = GPIO_LCKK | gpios; /* Set LCKK. */
- GPIO_LCKR(gpioport) = ~GPIO_LCKK & gpios; /* Clear LCKK. */
- GPIO_LCKR(gpioport) = GPIO_LCKK | gpios; /* Set LCKK. */
- reg32 = GPIO_LCKR(gpioport); /* Read LCKK. */
- reg32 = GPIO_LCKR(gpioport); /* Read LCKK again. */
-
- /* If (reg32 & GPIO_LCKK) is true, the lock is now active. */
-}
diff --git a/lib/stm32f2/libopencm3_stm32f2.ld b/lib/stm32f2/libopencm3_stm32f2.ld
deleted file mode 100644
index fda7d02..0000000
--- a/lib/stm32f2/libopencm3_stm32f2.ld
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * This file is part of the libopencm3 project.
- *
- * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-/* Generic linker script for STM32 targets using libopencm3. */
-
-/* Memory regions must be defined in the ld script which includes this one. */
-
-/* Enforce emmition of the vector table. */
-EXTERN (vector_table)
-
-/* Define sections. */
-SECTIONS
-{
- . = ORIGIN(rom);
-
- .text : {
- *(.vectors) /* Vector table */
- *(.text*) /* Program code */
- *(.rodata*) /* Read-only data */
- _etext = .;
- } >rom
-
- . = ORIGIN(ram);
-
- .data : {
- _data = .;
- *(.data*) /* Read-write initialized data */
- _edata = .;
- } >ram AT >rom
-
- .bss : {
- *(.bss*) /* Read-write zero initialized data */
- *(COMMON)
- _ebss = .;
- } >ram AT >rom
-
- /*
- * The .eh_frame section appears to be used for C++ exception handling.
- * You may need to fix this if you're using C++.
- */
- /DISCARD/ : { *(.eh_frame) }
-
- end = .;
-}
-
-PROVIDE(_stack = 0x20000800);
-
diff --git a/lib/stm32f2/rcc.c b/lib/stm32f2/rcc.c
deleted file mode 100644
index 048f0ff..0000000
--- a/lib/stm32f2/rcc.c
+++ /dev/null
@@ -1,412 +0,0 @@
-/*
- * This file is part of the libopencm3 project.
- *
- * Copyright (C) 2009 Federico Ruiz-Ugalde <memeruiz at gmail dot com>
- * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
- * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <libopencm3/stm32/f2/rcc.h>
-#include <libopencm3/stm32/f2/flash.h>
-
-/* Set the default ppre1 and ppre2 peripheral clock frequencies after reset */
-u32 rcc_ppre1_frequency = 8000000;
-u32 rcc_ppre2_frequency = 8000000;
-
-/* TODO: Create a table for these values */
-#define RCC_PLL_M 8
-#define RCC_PLL_N 336
-#define RCC_PLL_P 2
-#define RCC_PLL_Q 7
-#define RCC_PLLI2S_N 192
-#define RCC_PLLI2S_R 5
-
-void rcc_osc_ready_int_clear(osc_t osc)
-{
- switch (osc) {
- case PLL:
- RCC_CIR |= RCC_CIR_PLLRDYC;
- break;
- case HSE:
- RCC_CIR |= RCC_CIR_HSERDYC;
- break;
- case HSI:
- RCC_CIR |= RCC_CIR_HSIRDYC;
- break;
- case LSE:
- RCC_CIR |= RCC_CIR_LSERDYC;
- break;
- case LSI:
- RCC_CIR |= RCC_CIR_LSIRDYC;
- break;
- }
-}
-
-void rcc_osc_ready_int_enable(osc_t osc)
-{
- switch (osc) {
- case PLL:
- RCC_CIR |= RCC_CIR_PLLRDYIE;
- break;
- case HSE:
- RCC_CIR |= RCC_CIR_HSERDYIE;
- break;
- case HSI:
- RCC_CIR |= RCC_CIR_HSIRDYIE;
- break;
- case LSE:
- RCC_CIR |= RCC_CIR_LSERDYIE;
- break;
- case LSI:
- RCC_CIR |= RCC_CIR_LSIRDYIE;
- break;
- }
-}
-
-void rcc_osc_ready_int_disable(osc_t osc)
-{
- switch (osc) {
- case PLL:
- RCC_CIR &= ~RCC_CIR_PLLRDYIE;
- break;
- case HSE:
- RCC_CIR &= ~RCC_CIR_HSERDYIE;
- break;
- case HSI:
- RCC_CIR &= ~RCC_CIR_HSIRDYIE;
- break;
- case LSE:
- RCC_CIR &= ~RCC_CIR_LSERDYIE;
- break;
- case LSI:
- RCC_CIR &= ~RCC_CIR_LSIRDYIE;
- break;
- }
-}
-
-int rcc_osc_ready_int_flag(osc_t osc)
-{
- switch (osc) {
- case PLL:
- return ((RCC_CIR & RCC_CIR_PLLRDYF) != 0);
- break;
- case HSE:
- return ((RCC_CIR & RCC_CIR_HSERDYF) != 0);
- break;
- case HSI:
- return ((RCC_CIR & RCC_CIR_HSIRDYF) != 0);
- break;
- case LSE:
- return ((RCC_CIR & RCC_CIR_LSERDYF) != 0);
- break;
- case LSI:
- return ((RCC_CIR & RCC_CIR_LSIRDYF) != 0);
- break;
- }
-
- /* Shouldn't be reached. */
- return -1;
-}
-
-void rcc_css_int_clear(void)
-{
- RCC_CIR |= RCC_CIR_CSSC;
-}
-
-int rcc_css_int_flag(void)
-{
- return ((RCC_CIR & RCC_CIR_CSSF) != 0);
-}
-
-void rcc_wait_for_osc_ready(osc_t osc)
-{
- switch (osc) {
- case PLL:
- while ((RCC_CR & RCC_CR_PLLRDY) == 0);
- break;
- case HSE:
- while ((RCC_CR & RCC_CR_HSERDY) == 0);
- break;
- case HSI:
- while ((RCC_CR & RCC_CR_HSIRDY) == 0);
- break;
- case LSE:
- while ((RCC_BDCR & RCC_BDCR_LSERDY) == 0);
- break;
- case LSI:
- while ((RCC_CSR & RCC_CSR_LSIRDY) == 0);
- break;
- }
-}
-
-void rcc_wait_for_sysclk_status(osc_t osc)
-{
- switch (osc) {
- case PLL:
- while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_PLL);
- break;
- case HSE:
- while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_HSE);
- break;
- case HSI:
- while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_HSI);
- break;
- default:
- /* Shouldn't be reached. */
- break;
- }
-}
-
-void rcc_osc_on(osc_t osc)
-{
- switch (osc) {
- case PLL:
- RCC_CR |= RCC_CR_PLLON;
- break;
- case HSE:
- RCC_CR |= RCC_CR_HSEON;
- break;
- case HSI:
- RCC_CR |= RCC_CR_HSION;
- break;
- case LSE:
- RCC_BDCR |= RCC_BDCR_LSEON;
- break;
- case LSI:
- RCC_CSR |= RCC_CSR_LSION;
- break;
- }
-}
-
-void rcc_osc_off(osc_t osc)
-{
- switch (osc) {
- case PLL:
- RCC_CR &= ~RCC_CR_PLLON;
- break;
- case HSE:
- RCC_CR &= ~RCC_CR_HSEON;
- break;
- case HSI:
- RCC_CR &= ~RCC_CR_HSION;
- break;
- case LSE:
- RCC_BDCR &= ~RCC_BDCR_LSEON;
- break;
- case LSI:
- RCC_CSR &= ~RCC_CSR_LSION;
- break;
- }
-}
-
-void rcc_css_enable(void)
-{
- RCC_CR |= RCC_CR_CSSON;
-}
-
-void rcc_css_disable(void)
-{
- RCC_CR &= ~RCC_CR_CSSON;
-}
-
-void rcc_osc_bypass_enable(osc_t osc)
-{
- switch (osc) {
- case HSE:
- RCC_CR |= RCC_CR_HSEBYP;
- break;
- case LSE:
- RCC_BDCR |= RCC_BDCR_LSEBYP;
- break;
- case PLL:
- case HSI:
- case LSI:
- /* Do nothing, only HSE/LSE allowed here. */
- break;
- }
-}
-
-void rcc_osc_bypass_disable(osc_t osc)
-{
- switch (osc) {
- case HSE:
- RCC_CR &= ~RCC_CR_HSEBYP;
- break;
- case LSE:
- RCC_BDCR &= ~RCC_BDCR_LSEBYP;
- break;
- case PLL:
- case HSI:
- case LSI:
- /* Do nothing, only HSE/LSE allowed here. */
- break;
- }
-}
-
-void rcc_peripheral_enable_clock(volatile u32 *reg, u32 en)
-{
- *reg |= en;
-}
-
-void rcc_peripheral_disable_clock(volatile u32 *reg, u32 en)
-{
- *reg &= ~en;
-}
-
-void rcc_peripheral_reset(volatile u32 *reg, u32 reset)
-{
- *reg |= reset;
-}
-
-void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset)
-{
- *reg &= ~clear_reset;
-}
-
-void rcc_set_sysclk_source(u32 clk)
-{
- u32 reg32;
-
- reg32 = RCC_CFGR;
- reg32 &= ~((1 << 1) | (1 << 0));
- RCC_CFGR = (reg32 | clk);
-}
-
-void rcc_set_pll_source(u32 pllsrc)
-{
- u32 reg32;
-
- reg32 = RCC_PLLCFGR;
- reg32 &= ~(1 << 22);
- RCC_PLLCFGR = (reg32 | (pllsrc << 22));
-}
-
-void rcc_set_ppre2(u32 ppre2)
-{
- u32 reg32;
-
- reg32 = RCC_CFGR;
- reg32 &= ~((1 << 11) | (1 << 12) | (1 << 13));
- RCC_CFGR = (reg32 | (ppre2 << 11));
-}
-
-void rcc_set_ppre1(u32 ppre1)
-{
- u32 reg32;
-
- reg32 = RCC_CFGR;
- reg32 &= ~((1 << 8) | (1 << 9) | (1 << 10));
- RCC_CFGR = (reg32 | (ppre1 << 8));
-}
-
-void rcc_set_hpre(u32 hpre)
-{
- u32 reg32;
-
- reg32 = RCC_CFGR;
- reg32 &= ~((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7));
- RCC_CFGR = (reg32 | (hpre << 4));
-}
-
-void rcc_set_rtcpre(u32 rtcpre)
-{
- u32 reg32;
-
- reg32 = RCC_CFGR;
- reg32 &= ~((1 << 16) | (1 << 17) | (1 << 18) | (1 << 19) | (1 << 20));
- RCC_CFGR = (reg32 | (rtcpre << 16));
-}
-
-void rcc_set_main_pll_hsi(u32 pllm, u32 plln, u32 pllp, u32 pllq)
-{
- RCC_PLLCFGR = pllm |
- (plln << 6) |
- (((pllp >> 1) - 1) << 16) |
- (pllq << 24);
-}
-
-void rcc_set_main_pll_hse(u32 pllm, u32 plln, u32 pllp, u32 pllq)
-{
- RCC_PLLCFGR = pllm |
- (plln << 6) |
- (((pllp >> 1) - 1) << 16) |
- RCC_PLLCFGR_PLLSRC |
- (pllq << 24);
-}
-
-u32 rcc_system_clock_source(void)
-{
- /* Return the clock source which is used as system clock. */
- return ((RCC_CFGR & 0x000c) >> 2);
-}
-
-void rcc_clock_setup_in_hse_8mhz_out_120mhz(void)
-{
- /* Enable internal high-speed oscillator. */
- rcc_osc_on(HSI);
- rcc_wait_for_osc_ready(HSI);
-
- /* Select HSI as SYSCLK source. */
- rcc_set_sysclk_source(RCC_CFGR_SW_HSI);
-
- /* Enable external high-speed oscillator 8MHz. */
- rcc_osc_on(HSE);
- rcc_wait_for_osc_ready(HSE);
- rcc_set_sysclk_source(RCC_CFGR_SW_HSE);
-
- /*
- * Set prescalers for AHB, ADC, ABP1, ABP2.
- * Do this before touching the PLL (TODO: why?).
- */
- rcc_set_hpre(RCC_CFGR_HPRE_DIV_NONE); /* Set. 120MHz Max. 120MHz */
- rcc_set_ppre1(RCC_CFGR_PPRE_DIV_4); /* Set. 30MHz Max. 30MHz */
- rcc_set_ppre2(RCC_CFGR_PPRE_DIV_2); /* Set. 60MHz Max. 60MHz */
-
- rcc_set_main_pll_hse(RCC_PLL_M, RCC_PLL_N, RCC_PLL_P, RCC_PLL_Q);
-
- /* Enable PLL oscillator and wait for it to stabilize. */
- rcc_osc_on(PLL);
- rcc_wait_for_osc_ready(PLL);
-
- /*
- * @3.3V
- * Sysclk runs with 120MHz -> 3 waitstates.
- * 0WS from 0-30MHz
- * 1WS from 30-60MHz
- * 2WS from 60-90MHz
- * 3WS from 90-120MHz
- */
- flash_set_ws(FLASH_PRFTEN | FLASH_ICE | FLASH_DCE | FLASH_LATENCY_3WS);
-
- /* Select PLL as SYSCLK source. */
- rcc_set_sysclk_source(RCC_CFGR_SW_PLL);
-
- /* Wait for PLL clock to be selected. */
- rcc_wait_for_sysclk_status(PLL);
-
- /* Set the peripheral clock frequencies used */
- rcc_ppre1_frequency = 30000000;
- rcc_ppre2_frequency = 60000000;
-}
-
-void rcc_backupdomain_reset(void)
-{
- /* Set the backup domain software reset. */
- RCC_BDCR |= RCC_BDCR_BDRST;
-
- /* Clear the backup domain software reset. */
- RCC_BDCR &= ~RCC_BDCR_BDRST;
-}
diff --git a/lib/stm32f2/vector.c b/lib/stm32f2/vector.c
deleted file mode 100644
index d6f70f8..0000000
--- a/lib/stm32f2/vector.c
+++ /dev/null
@@ -1,336 +0,0 @@
-/*
- * This file is part of the libopencm3 project.
- *
- * Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
- * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#define WEAK __attribute__ ((weak))
-
-/* Symbols exported by linker script */
-extern unsigned _etext, _data, _edata, _ebss, _stack;
-
-void main(void);
-void reset_handler(void);
-void blocking_handler(void);
-void null_handler(void);
-
-void WEAK reset_handler(void);
-void WEAK nmi_handler(void);
-void WEAK hard_fault_handler(void);
-void WEAK mem_manage_handler(void);
-void WEAK bus_fault_handler(void);
-void WEAK usage_fault_handler(void);
-void WEAK sv_call_handler(void);
-void WEAK debug_monitor_handler(void);
-void WEAK pend_sv_handler(void);
-void WEAK sys_tick_handler(void);
-void WEAK wwdg_isr(void);
-void WEAK pvd_isr(void);
-void WEAK tamp_stamp_isr(void);
-void WEAK rtc_wkup_isr(void);
-void WEAK flash_isr(void);
-void WEAK rcc_isr(void);
-void WEAK exti0_isr(void);
-void WEAK exti1_isr(void);
-void WEAK exti2_isr(void);
-void WEAK exti3_isr(void);
-void WEAK exti4_isr(void);
-void WEAK dma1_stream0_isr(void);
-void WEAK dma1_stream1_isr(void);
-void WEAK dma1_stream2_isr(void);
-void WEAK dma1_stream3_isr(void);
-void WEAK dma1_stream4_isr(void);
-void WEAK dma1_stream5_isr(void);
-void WEAK dma1_stream6_isr(void);
-void WEAK adc_isr(void);
-void WEAK can1_tx_isr(void);
-void WEAK can1_rx0_isr(void);
-void WEAK can1_rx1_isr(void);
-void WEAK can1_sce_isr(void);
-void WEAK exti9_5_isr(void);
-void WEAK tim1_brk_tim9_isr(void);
-void WEAK tim1_up_tim10_isr(void);
-void WEAK tim1_trg_com_tim11_isr(void);
-void WEAK tim1_cc_isr(void);
-void WEAK tim2_isr(void);
-void WEAK tim3_isr(void);
-void WEAK tim4_isr(void);
-void WEAK i2c1_ev_isr(void);
-void WEAK i2c1_er_isr(void);
-void WEAK i2c2_ev_isr(void);
-void WEAK i2c2_er_isr(void);
-void WEAK spi1_isr(void);
-void WEAK spi2_isr(void);
-void WEAK usart1_isr(void);
-void WEAK usart2_isr(void);
-void WEAK usart3_isr(void);
-void WEAK exti15_10_isr(void);
-void WEAK rtc_alarm_isr(void);
-void WEAK usb_fs_wkup_isr(void);
-void WEAK tim8_brk_tim12_isr(void);
-void WEAK tim8_up_tim13_isr(void);
-void WEAK tim8_trg_com_tim14_isr(void);
-void WEAK tim8_cc_isr(void);
-void WEAK dma1_stream7_isr(void);
-void WEAK fsmc_isr(void);
-void WEAK sdio_isr(void);
-void WEAK tim5_isr(void);
-void WEAK spi3_isr(void);
-void WEAK usart4_isr(void);
-void WEAK usart5_isr(void);
-void WEAK tim6_dac_isr(void);
-void WEAK tim7_isr(void);
-void WEAK dma2_stream0_isr(void);
-void WEAK dma2_stream1_isr(void);
-void WEAK dma2_stream2_isr(void);
-void WEAK dma2_stream3_isr(void);
-void WEAK dma2_stream4_isr(void);
-void WEAK eth_isr(void);
-void WEAK eth_wkup_isr(void);
-void WEAK can2_tx_isr(void);
-void WEAK can2_rx0_isr(void);
-void WEAK can2_rx1_isr(void);
-void WEAK can2_sce_isr(void);
-void WEAK otg_fs_isr(void);
-void WEAK dma2_stream5_isr(void);
-void WEAK dma2_stream6_isr(void);
-void WEAK dma2_stream7_isr(void);
-void WEAK usart6_isr(void);
-void WEAK i2c3_ev_isr(void);
-void WEAK i2c3_er_isr(void);
-void WEAK otg_hs_ep1_out_isr(void);
-void WEAK otg_hs_ep1_in_isr(void);
-void WEAK otg_hs_wkup_isr(void);
-void WEAK otg_hs_isr(void);
-void WEAK dcmi_isr(void);
-void WEAK cryp_isr(void);
-void WEAK hash_rng_isr(void);
-
-__attribute__ ((section(".vectors")))
-void (*const vector_table[]) (void) = {
- (void*)&_stack,
- reset_handler,
- nmi_handler,
- hard_fault_handler,
- mem_manage_handler,
- bus_fault_handler,
- usage_fault_handler,
- 0, 0, 0, 0, /* Reserved */
- sv_call_handler,
- debug_monitor_handler,
- 0, /* Reserved */
- pend_sv_handler,
- sys_tick_handler,
- wwdg_isr,
- pvd_isr,
- tamp_stamp_isr,
- rtc_wkup_isr,
- flash_isr,
- rcc_isr,
- exti0_isr,
- exti1_isr,
- exti2_isr,
- exti3_isr,
- exti4_isr,
- dma1_stream0_isr,
- dma1_stream1_isr,
- dma1_stream2_isr,
- dma1_stream3_isr,
- dma1_stream4_isr,
- dma1_stream5_isr,
- dma1_stream6_isr,
- adc_isr,
- can1_tx_isr,
- can1_rx0_isr,
- can1_rx1_isr,
- can1_sce_isr,
- exti9_5_isr,
- tim1_brk_tim9_isr,
- tim1_up_tim10_isr,
- tim1_trg_com_tim11_isr,
- tim1_cc_isr,
- tim2_isr,
- tim3_isr,
- tim4_isr,
- i2c1_ev_isr,
- i2c1_er_isr,
- i2c2_ev_isr,
- i2c2_er_isr,
- spi1_isr,
- spi2_isr,
- usart1_isr,
- usart2_isr,
- usart3_isr,
- exti15_10_isr,
- rtc_alarm_isr,
- usb_fs_wkup_isr,
- tim8_brk_tim12_isr,
- tim8_up_tim13_isr,
- tim8_trg_com_tim14_isr,
- tim8_cc_isr,
- dma1_stream7_isr,
- fsmc_isr,
- sdio_isr,
- tim5_isr,
- spi3_isr,
- usart4_isr,
- usart5_isr,
- tim6_dac_isr,
- tim7_isr,
- dma2_stream0_isr,
- dma2_stream1_isr,
- dma2_stream2_isr,
- dma2_stream3_isr,
- dma2_stream4_isr,
- eth_isr,
- eth_wkup_isr,
- can2_tx_isr,
- can2_rx0_isr,
- can2_rx1_isr,
- can2_sce_isr,
- otg_fs_isr,
- dma2_stream5_isr,
- dma2_stream6_isr,
- dma2_stream7_isr,
- usart6_isr,
- i2c3_ev_isr,
- i2c3_er_isr,
- otg_hs_ep1_out_isr,
- otg_hs_ep1_in_isr,
- otg_hs_wkup_isr,
- otg_hs_isr,
- dcmi_isr,
- cryp_isr,
- hash_rng_isr,
-};
-
-void reset_handler(void)
-{
- volatile unsigned *src, *dest;
- asm("MSR msp, %0" : : "r"(&_stack));
-
- for (src = &_etext, dest = &_data; dest < &_edata; src++, dest++)
- *dest = *src;
-
- while (dest < &_ebss)
- *dest++ = 0;
-
- /* Call the application's entry point. */
- main();
-}
-
-void blocking_handler(void)
-{
- while (1) ;
-}
-
-void null_handler(void)
-{
- /* Do nothing. */
-}
-
-#pragma weak nmi_handler = null_handler
-#pragma weak hard_fault_handler = blocking_handler
-#pragma weak mem_manage_handler = blocking_handler
-#pragma weak bus_fault_handler = blocking_handler
-#pragma weak usage_fault_handler = blocking_handler
-#pragma weak sv_call_handler = null_handler
-#pragma weak debug_monitor_handler = null_handler
-#pragma weak pend_sv_handler = null_handler
-#pragma weak sys_tick_handler = null_handler
-#pragma weak wwdg_isr = null_handler
-#pragma weak pvd_isr = null_handler
-#pragma weak tamp_stamp_isr = null_handler
-#pragma weak rtc_wkup_isr = null_handler
-#pragma weak flash_isr = null_handler
-#pragma weak rcc_isr = null_handler
-#pragma weak exti0_isr = null_handler
-#pragma weak exti1_isr = null_handler
-#pragma weak exti2_isr = null_handler
-#pragma weak exti3_isr = null_handler
-#pragma weak exti4_isr = null_handler
-#pragma weak dma1_stream0_isr = null_handler
-#pragma weak dma1_stream1_isr = null_handler
-#pragma weak dma1_stream2_isr = null_handler
-#pragma weak dma1_stream3_isr = null_handler
-#pragma weak dma1_stream4_isr = null_handler
-#pragma weak dma1_stream5_isr = null_handler
-#pragma weak dma1_stream6_isr = null_handler
-#pragma weak adc_isr = null_handler
-#pragma weak can1_tx_isr = null_handler
-#pragma weak can1_rx0_isr = null_handler
-#pragma weak can1_rx1_isr = null_handler
-#pragma weak can1_sce_isr = null_handler
-#pragma weak exti9_5_isr = null_handler
-#pragma weak tim1_brk_tim9_isr = null_handler
-#pragma weak tim1_up_tim10_isr = null_handler
-#pragma weak tim1_trg_com_tim11_isr = null_handler
-#pragma weak tim1_cc_isr = null_handler
-#pragma weak tim2_isr = null_handler
-#pragma weak tim3_isr = null_handler
-#pragma weak tim4_isr = null_handler
-#pragma weak i2c1_ev_isr = null_handler
-#pragma weak i2c1_er_isr = null_handler
-#pragma weak i2c2_ev_isr = null_handler
-#pragma weak i2c2_er_isr = null_handler
-#pragma weak spi1_isr = null_handler
-#pragma weak spi2_isr = null_handler
-#pragma weak usart1_isr = null_handler
-#pragma weak usart2_isr = null_handler
-#pragma weak usart3_isr = null_handler
-#pragma weak exti15_10_isr = null_handler
-#pragma weak rtc_alarm_isr = null_handler
-#pragma weak usb_fs_wkup_isr = null_handler
-#pragma weak tim8_brk_tim12_isr = null_handler
-#pragma weak tim8_up_tim13_isr = null_handler
-#pragma weak tim8_trg_com_tim14_isr = null_handler
-#pragma weak tim8_cc_isr = null_handler
-#pragma weak dma1_stream7_isr = null_handler
-#pragma weak fsmc_isr = null_handler
-#pragma weak sdio_isr = null_handler
-#pragma weak tim5_isr = null_handler
-#pragma weak spi3_isr = null_handler
-#pragma weak usart4_isr = null_handler
-#pragma weak usart5_isr = null_handler
-#pragma weak tim6_dac_isr = null_handler
-#pragma weak tim7_isr = null_handler
-#pragma weak dma2_stream0_isr = null_handler
-#pragma weak dma2_stream1_isr = null_handler
-#pragma weak dma2_stream2_isr = null_handler
-#pragma weak dma2_stream3_isr = null_handler
-#pragma weak dma2_stream4_isr = null_handler
-#pragma weak eth_isr = null_handler
-#pragma weak eth_wkup_isr = null_handler
-#pragma weak can2_tx_isr = null_handler
-#pragma weak can2_rx0_isr = null_handler
-#pragma weak can2_rx1_isr = null_handler
-#pragma weak can2_sce_isr = null_handler
-#pragma weak otg_fs_isr = null_handler
-#pragma weak dma2_stream5_isr = null_handler
-#pragma weak dma2_stream6_isr = null_handler
-#pragma weak dma2_stream7_isr = null_handler
-#pragma weak usart6_isr = null_handler
-#pragma weak i2c3_ev_isr = null_handler
-#pragma weak i2c3_er_isr = null_handler
-#pragma weak otg_hs_ep1_out_isr = null_handler
-#pragma weak otg_hs_ep1_in_isr = null_handler
-#pragma weak otg_hs_wkup_isr = null_handler
-#pragma weak otg_hs_isr = null_handler
-#pragma weak dcmi_isr = null_handler
-#pragma weak cryp_isr = null_handler
-#pragma weak hash_rng_isr = null_handler
-