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authorchrysn2012-05-01 13:49:34 +0200
committerchrysn2012-05-01 13:49:34 +0200
commit282891f8a61d6be822da978e44f0ed3e807c0cd6 (patch)
treef53552961e26bf1a81d0ba015bcc6e876186205b /lib/stm32
parent99975d9a058690f6faa3077dccadbdd5353db4fe (diff)
parent3596075ee0f189f8a95090c4fb5522844255a029 (diff)
Merge branch 'master' into efm32
Diffstat (limited to 'lib/stm32')
-rw-r--r--lib/stm32/f1/libopencm3_stm32f1.ld35
-rw-r--r--lib/stm32/f1/rtc.c5
-rw-r--r--lib/stm32/f1/timer.c129
-rw-r--r--lib/stm32/f1/vector.c4
-rw-r--r--lib/stm32/f2/libopencm3_stm32f2.ld35
-rw-r--r--lib/stm32/f2/timer.c4
-rw-r--r--lib/stm32/f2/vector.c4
-rw-r--r--lib/stm32/f4/timer.c4
8 files changed, 179 insertions, 41 deletions
diff --git a/lib/stm32/f1/libopencm3_stm32f1.ld b/lib/stm32/f1/libopencm3_stm32f1.ld
index 0624b96..a64a1f7 100644
--- a/lib/stm32/f1/libopencm3_stm32f1.ld
+++ b/lib/stm32/f1/libopencm3_stm32f1.ld
@@ -38,36 +38,43 @@ SECTIONS
. = ALIGN(4);
*(.rodata*) /* Read-only data */
. = ALIGN(4);
+ _etext = .;
} >rom
- /* exception index - required due to libgcc.a issuing /0 exceptions */
- __exidx_start = .;
+ /*
+ * Another section used by C++ stuff, appears when using newlib with
+ * 64bit (long long) printf support
+ */
+ .ARM.extab : {
+ *(.ARM.extab*)
+ } >rom
.ARM.exidx : {
- *(.ARM.exidx*)
- } > rom
- __exidx_end = .;
-
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } >rom
- _etext = .;
+ . = ORIGIN(ram);
- .data : {
+ .data : AT (__exidx_end) {
_data = .;
*(.data*) /* Read-write initialized data */
. = ALIGN(4);
_edata = .;
- } >ram AT >rom
+ } >ram
.bss : {
*(.bss*) /* Read-write zero initialized data */
*(COMMON)
. = ALIGN(4);
_ebss = .;
- } >ram
+ } >ram AT >rom
- /* exception unwind data - required due to libgcc.a issuing /0 exceptions */
- .ARM.extab : {
- *(.ARM.extab*)
- } >ram
+ /*
+ * The .eh_frame section appears to be used for C++ exception handling.
+ * You may need to fix this if you're using C++.
+ */
+ /DISCARD/ : { *(.eh_frame) }
. = ALIGN(4);
end = .;
diff --git a/lib/stm32/f1/rtc.c b/lib/stm32/f1/rtc.c
index 0b7769e..08a4953 100644
--- a/lib/stm32/f1/rtc.c
+++ b/lib/stm32/f1/rtc.c
@@ -99,14 +99,13 @@ void rtc_enter_config_mode(void)
void rtc_exit_config_mode(void)
{
- /* u32 reg32; */
+ u32 reg32;
/* Exit configuration mode. */
RTC_CRL &= ~RTC_CRL_CNF;
/* Wait until the RTOFF bit is 1 (our RTC register write finished). */
- /* while ((reg32 = (RTC_CRL & RTC_CRL_RTOFF)) == 0); */
- /* TODO: Unnecessary since we poll the bit on config entry(?) */
+ while ((reg32 = (RTC_CRL & RTC_CRL_RTOFF)) == 0);
}
void rtc_set_alarm_time(u32 alarm_time)
diff --git a/lib/stm32/f1/timer.c b/lib/stm32/f1/timer.c
index 8c32670..cf5b411 100644
--- a/lib/stm32/f1/timer.c
+++ b/lib/stm32/f1/timer.c
@@ -118,8 +118,8 @@ void timer_clear_flag(u32 timer_peripheral, u32 flag)
TIM_SR(timer_peripheral) &= ~flag;
}
-void timer_set_mode(u32 timer_peripheral, u8 clock_div,
- u8 alignment, u8 direction)
+void timer_set_mode(u32 timer_peripheral, u32 clock_div,
+ u32 alignment, u32 direction)
{
u32 cr1;
@@ -914,3 +914,128 @@ u32 timer_get_counter(u32 timer_peripheral)
{
return TIM_CNT(timer_peripheral);
}
+
+void timer_ic_set_filter(u32 timer, enum tim_ic_id ic, enum tim_ic_filter flt)
+{
+ switch (ic) {
+ case TIM_IC1:
+ TIM_CCMR1(timer) &= ~TIM_CCMR1_IC1F_MASK;
+ TIM_CCMR1(timer) |= flt << 4;
+ break;
+ case TIM_IC2:
+ TIM_CCMR1(timer) &= ~TIM_CCMR1_IC2F_MASK;
+ TIM_CCMR1(timer) |= flt << 12;
+ break;
+ case TIM_IC3:
+ TIM_CCMR2(timer) &= ~TIM_CCMR2_IC3F_MASK;
+ TIM_CCMR2(timer) |= flt << 4;
+ break;
+ case TIM_IC4:
+ TIM_CCMR2(timer) &= ~TIM_CCMR2_IC4F_MASK;
+ TIM_CCMR2(timer) |= flt << 12;
+ break;
+ }
+}
+
+void timer_ic_set_prescaler(u32 timer, enum tim_ic_id ic, enum tim_ic_psc psc)
+{
+ switch (ic) {
+ case TIM_IC1:
+ TIM_CCMR1(timer) &= ~TIM_CCMR1_IC1PSC_MASK;
+ TIM_CCMR1(timer) |= psc << 2;
+ break;
+ case TIM_IC2:
+ TIM_CCMR1(timer) &= ~TIM_CCMR1_IC2PSC_MASK;
+ TIM_CCMR1(timer) |= psc << 10;
+ break;
+ case TIM_IC3:
+ TIM_CCMR2(timer) &= ~TIM_CCMR2_IC3PSC_MASK;
+ TIM_CCMR2(timer) |= psc << 4;
+ break;
+ case TIM_IC4:
+ TIM_CCMR2(timer) &= ~TIM_CCMR2_IC4PSC_MASK;
+ TIM_CCMR2(timer) |= psc << 10;
+ break;
+ }
+}
+
+void timer_ic_set_input(u32 timer, enum tim_ic_id ic, enum tim_ic_input in)
+{
+ in &= 3;
+
+ if (((ic == TIM_IC2) || (ic == TIM_IC4)) &&
+ ((in == TIM_IC_IN_TI1) || (in = TIM_IC_IN_TI2))) {
+ /* Input select bits are flipped for these combinations */
+ in ^= 3;
+ }
+
+ switch (ic) {
+ case TIM_IC1:
+ TIM_CCMR1(timer) &= ~TIM_CCMR1_CC1S_MASK;
+ TIM_CCMR1(timer) |= in;
+ break;
+ case TIM_IC2:
+ TIM_CCMR1(timer) &= ~TIM_CCMR1_CC2S_MASK;
+ TIM_CCMR1(timer) |= in << 8;
+ break;
+ case TIM_IC3:
+ TIM_CCMR2(timer) &= ~TIM_CCMR2_CC3S_MASK;
+ TIM_CCMR2(timer) |= in;
+ break;
+ case TIM_IC4:
+ TIM_CCMR2(timer) &= ~TIM_CCMR2_CC4S_MASK;
+ TIM_CCMR2(timer) |= in << 8;
+ break;
+ }
+}
+
+void timer_ic_set_polarity(u32 timer, enum tim_ic_id ic, enum tim_ic_pol pol)
+{
+ if (pol)
+ TIM_CCER(timer) |= (0x2 << (ic * 4));
+ else
+ TIM_CCER(timer) &= ~(0x2 << (ic * 4));
+}
+
+void timer_ic_enable(u32 timer, enum tim_ic_id ic)
+{
+ TIM_CCER(timer) |= (0x1 << (ic * 4));
+}
+
+void timer_ic_disable(u32 timer, enum tim_ic_id ic)
+{
+ TIM_CCER(timer) &= ~(0x1 << (ic * 4));
+}
+
+void timer_slave_set_filter(u32 timer, enum tim_ic_filter flt)
+{
+ TIM_SMCR(timer) &= ~TIM_SMCR_ETF_MASK;
+ TIM_SMCR(timer) |= flt << 8;
+}
+
+void timer_slave_set_prescaler(u32 timer, enum tim_ic_psc psc)
+{
+ TIM_SMCR(timer) &= ~TIM_SMCR_ETPS_MASK;
+ TIM_SMCR(timer) |= psc << 12;
+}
+
+void timer_slave_set_polarity(u32 timer, enum tim_ic_pol pol)
+{
+ if (pol)
+ TIM_SMCR(timer) |= TIM_SMCR_ETP;
+ else
+ TIM_SMCR(timer) &= ~TIM_SMCR_ETP;
+}
+
+void timer_slave_set_mode(u32 timer, u8 mode)
+{
+ TIM_SMCR(timer) &= ~TIM_SMCR_SMS_MASK;
+ TIM_SMCR(timer) |= mode;
+}
+
+void timer_slave_set_trigger(u32 timer, u8 trigger)
+{
+ TIM_SMCR(timer) &= ~TIM_SMCR_TS_MASK;
+ TIM_SMCR(timer) |= trigger;
+}
+
diff --git a/lib/stm32/f1/vector.c b/lib/stm32/f1/vector.c
index fe61e29..119ce30 100644
--- a/lib/stm32/f1/vector.c
+++ b/lib/stm32/f1/vector.c
@@ -20,7 +20,7 @@
#define WEAK __attribute__ ((weak))
/* Symbols exported by the linker script(s). */
-extern unsigned _etext, _data, _edata, _ebss, _stack;
+extern unsigned __exidx_end, _data, _edata, _ebss, _stack;
void main(void);
void reset_handler(void);
@@ -197,7 +197,7 @@ void reset_handler(void)
__asm__("MSR msp, %0" : : "r"(&_stack));
- for (src = &_etext, dest = &_data; dest < &_edata; src++, dest++)
+ for (src = &__exidx_end, dest = &_data; dest < &_edata; src++, dest++)
*dest = *src;
while (dest < &_ebss)
diff --git a/lib/stm32/f2/libopencm3_stm32f2.ld b/lib/stm32/f2/libopencm3_stm32f2.ld
index 0624b96..a64a1f7 100644
--- a/lib/stm32/f2/libopencm3_stm32f2.ld
+++ b/lib/stm32/f2/libopencm3_stm32f2.ld
@@ -38,36 +38,43 @@ SECTIONS
. = ALIGN(4);
*(.rodata*) /* Read-only data */
. = ALIGN(4);
+ _etext = .;
} >rom
- /* exception index - required due to libgcc.a issuing /0 exceptions */
- __exidx_start = .;
+ /*
+ * Another section used by C++ stuff, appears when using newlib with
+ * 64bit (long long) printf support
+ */
+ .ARM.extab : {
+ *(.ARM.extab*)
+ } >rom
.ARM.exidx : {
- *(.ARM.exidx*)
- } > rom
- __exidx_end = .;
-
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } >rom
- _etext = .;
+ . = ORIGIN(ram);
- .data : {
+ .data : AT (__exidx_end) {
_data = .;
*(.data*) /* Read-write initialized data */
. = ALIGN(4);
_edata = .;
- } >ram AT >rom
+ } >ram
.bss : {
*(.bss*) /* Read-write zero initialized data */
*(COMMON)
. = ALIGN(4);
_ebss = .;
- } >ram
+ } >ram AT >rom
- /* exception unwind data - required due to libgcc.a issuing /0 exceptions */
- .ARM.extab : {
- *(.ARM.extab*)
- } >ram
+ /*
+ * The .eh_frame section appears to be used for C++ exception handling.
+ * You may need to fix this if you're using C++.
+ */
+ /DISCARD/ : { *(.eh_frame) }
. = ALIGN(4);
end = .;
diff --git a/lib/stm32/f2/timer.c b/lib/stm32/f2/timer.c
index 3cd5e91..659f8a9 100644
--- a/lib/stm32/f2/timer.c
+++ b/lib/stm32/f2/timer.c
@@ -119,8 +119,8 @@ void timer_clear_flag(u32 timer_peripheral, u32 flag)
TIM_SR(timer_peripheral) &= ~flag;
}
-void timer_set_mode(u32 timer_peripheral, u8 clock_div,
- u8 alignment, u8 direction)
+void timer_set_mode(u32 timer_peripheral, u32 clock_div,
+ u32 alignment, u32 direction)
{
u32 cr1;
diff --git a/lib/stm32/f2/vector.c b/lib/stm32/f2/vector.c
index 1c901da..64d2426 100644
--- a/lib/stm32/f2/vector.c
+++ b/lib/stm32/f2/vector.c
@@ -21,7 +21,7 @@
#define WEAK __attribute__ ((weak))
/* Symbols exported by the linker script(s): */
-extern unsigned _etext, _data, _edata, _ebss, _stack;
+extern unsigned __exidx_end, _data, _edata, _ebss, _stack;
void main(void);
void reset_handler(void);
@@ -224,7 +224,7 @@ void reset_handler(void)
__asm__("MSR msp, %0" : : "r"(&_stack));
- for (src = &_etext, dest = &_data; dest < &_edata; src++, dest++)
+ for (src = &__exidx_end, dest = &_data; dest < &_edata; src++, dest++)
*dest = *src;
while (dest < &_ebss)
diff --git a/lib/stm32/f4/timer.c b/lib/stm32/f4/timer.c
index bb7b0e7..6d5ab9d 100644
--- a/lib/stm32/f4/timer.c
+++ b/lib/stm32/f4/timer.c
@@ -119,8 +119,8 @@ void timer_clear_flag(u32 timer_peripheral, u32 flag)
TIM_SR(timer_peripheral) &= ~flag;
}
-void timer_set_mode(u32 timer_peripheral, u8 clock_div,
- u8 alignment, u8 direction)
+void timer_set_mode(u32 timer_peripheral, u32 clock_div,
+ u32 alignment, u32 direction)
{
u32 cr1;