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authorUwe Hermann2010-01-22 01:48:02 +0100
committerUwe Hermann2010-01-22 01:48:02 +0100
commit1f9479e673430ecd346f5ab49510540817001246 (patch)
tree6967392adfe7462b504214928ae7950c20a52ee5 /lib/rtc.c
parent3e29876d98973f03ee19911b688076cd81463d70 (diff)
Add initial (unfinished, untested) RTC support.
Diffstat (limited to 'lib/rtc.c')
-rw-r--r--lib/rtc.c77
1 files changed, 77 insertions, 0 deletions
diff --git a/lib/rtc.c b/lib/rtc.c
new file mode 100644
index 0000000..9cad527
--- /dev/null
+++ b/lib/rtc.c
@@ -0,0 +1,77 @@
+/*
+ * This file is part of the libopenstm32 project.
+ *
+ * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopenstm32.h>
+
+void rtc_init(void)
+{
+ /* Enable power and backup interface clocks. */
+ RCC_APB1ENR |= (PWREN | BKPEN);
+
+ /* Enable access to the backup registers and the RTC. */
+ /* TODO: PWR component not yet implemented in libopenstm32. */
+ /* PWR_CR |= PWR_CR_DBP; */
+
+ /* TODO: Wait for the RSF bit in RTC_CRL to be set by hardware? */
+}
+
+void rtc_enter_config_mode(void)
+{
+ u32 reg32;
+
+ /* Wait until the RTOFF bit is 1 (no RTC register writes ongoing). */
+ while ((reg32 = (RTC_CRL & RTC_CRL_RTOFF)) == 0);
+
+ /* Enter configuration mode. */
+ RTC_CRL |= RTC_CRL_CNF;
+}
+
+void rtc_exit_config_mode(void)
+{
+ u32 reg32;
+
+ /* Exit configuration mode. */
+ RTC_CRL &= ~RTC_CRL_CNF;
+
+ /* Wait until the RTOFF bit is 1 (our RTC register write finished). */
+ while ((reg32 = (RTC_CRL & RTC_CRL_RTOFF)) == 0);
+}
+
+void rtc_set_alarm_time(u32 alarm_time)
+{
+ rtc_enter_config_mode();
+ RTC_ALRL = (alarm_time & 0x0000ffff);
+ RTC_ALRH = (alarm_time & 0xffff0000) >> 16;
+ rtc_exit_config_mode();
+}
+
+void rtc_enable_alarm(void)
+{
+ rtc_enter_config_mode();
+ RTC_CRH |= RTC_CRH_ALRIE;
+ rtc_exit_config_mode();
+}
+
+void rtc_disable_alarm(void)
+{
+ rtc_enter_config_mode();
+ RTC_CRH &= ~RTC_CRH_ALRIE;
+ rtc_exit_config_mode();
+}
+