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authorJeff Ciesielski2012-11-13 11:06:21 -0800
committerJeff Ciesielski2012-11-13 13:13:40 -0800
commitdb35fbb7ba97a8a6d7481edf07cb82cae06aa834 (patch)
treec213211778736d5ce2f06b4cf186a6900f522b20 /include
parent1768df7edae1cd430183c03f3d0ad7f7b4d13c90 (diff)
parent4691568ca476177dc338e8c62872ceca6b4b4999 (diff)
Merge branch 'master' of git://github.com/libopencm3/libopencm3 into upstream-merge
Diffstat (limited to 'include')
-rw-r--r--include/libopencm3/cm3/nvic.h (renamed from include/libopencm3/stm32/nvic.h)52
-rw-r--r--include/libopencm3/cm3/scb.h (renamed from include/libopencm3/stm32/f4/scb.h)2
-rw-r--r--include/libopencm3/cm3/systick.h (renamed from include/libopencm3/stm32/systick.h)36
-rw-r--r--include/libopencm3/cm3/vector.h64
-rw-r--r--include/libopencm3/dispatch/nvic.h34
-rw-r--r--include/libopencm3/efm32/efm32g/irq.yaml35
-rw-r--r--include/libopencm3/efm32/efm32gg/irq.yaml43
-rw-r--r--include/libopencm3/efm32/efm32lg/irq.yaml43
-rw-r--r--include/libopencm3/efm32/efm32tg/irq.yaml28
-rw-r--r--include/libopencm3/efm32/efm32tg/memorymap.h76
-rw-r--r--include/libopencm3/efm32/memorymap.h37
-rw-r--r--include/libopencm3/lm3s/irq.yaml120
-rw-r--r--include/libopencm3/lpc13xx/irq.yaml62
-rw-r--r--include/libopencm3/lpc17xx/irq.yaml39
-rw-r--r--include/libopencm3/lpc43xx/irq.yaml55
-rw-r--r--include/libopencm3/lpc43xx/nvic.h151
-rw-r--r--include/libopencm3/lpc43xx/systick.h88
-rw-r--r--include/libopencm3/stm32/can.h2
-rw-r--r--include/libopencm3/stm32/desig.h (renamed from include/libopencm3/stm32/f1/desig.h)0
-rw-r--r--include/libopencm3/stm32/exti.h3
-rw-r--r--include/libopencm3/stm32/f1/dma.h59
-rw-r--r--include/libopencm3/stm32/f1/gpio.h12
-rw-r--r--include/libopencm3/stm32/f1/irq.yaml72
-rw-r--r--include/libopencm3/stm32/f1/nvic_f1.h114
-rw-r--r--include/libopencm3/stm32/f1/scb.h307
-rw-r--r--include/libopencm3/stm32/f2/irq.yaml85
-rw-r--r--include/libopencm3/stm32/f2/nvic_f2.h112
-rw-r--r--include/libopencm3/stm32/f2/scb.h307
-rw-r--r--include/libopencm3/stm32/f4/adc.h873
-rw-r--r--include/libopencm3/stm32/f4/dma.h693
-rw-r--r--include/libopencm3/stm32/f4/irq.yaml85
-rw-r--r--include/libopencm3/stm32/f4/nvic_f4.h112
-rw-r--r--include/libopencm3/stm32/f4/syscfg.h46
-rw-r--r--include/libopencm3/stm32/l1/gpio.h241
-rw-r--r--include/libopencm3/stm32/l1/irq.yaml49
-rw-r--r--include/libopencm3/stm32/l1/memorymap.h108
-rw-r--r--include/libopencm3/stm32/l1/rcc.h408
-rw-r--r--include/libopencm3/stm32/memorymap.h2
-rw-r--r--include/libopencm3/stm32/otg_fs.h105
-rw-r--r--include/libopencm3/stm32/otg_hs.h396
-rw-r--r--include/libopencm3/stm32/syscfg.h (renamed from include/libopencm3/stm32/f2/syscfg.h)0
-rw-r--r--include/libopencm3/usb/cdc.h2
-rw-r--r--include/libopencm3/usb/usbd.h67
-rw-r--r--include/libopencm3/usb/usbstd.h3
-rw-r--r--include/libopencmsis/core_cm3.h177
-rw-r--r--include/libopencmsis/dispatch/irqhandlers.h23
46 files changed, 4044 insertions, 1384 deletions
diff --git a/include/libopencm3/stm32/nvic.h b/include/libopencm3/cm3/nvic.h
index 694fab8..3f83285 100644
--- a/include/libopencm3/stm32/nvic.h
+++ b/include/libopencm3/cm3/nvic.h
@@ -1,21 +1,9 @@
-/** @defgroup STM32F_nvic_defines NVIC Defines
-
-@brief <b>libopencm3 STM32F Nested Vectored Interrupt Controller</b>
-
-@ingroup STM32F_defines
-
-@version 1.0.0
-
-@author @htmlonly &copy; @endhtmlonly 2010 Piotr Esden-Tempski <piotr@esden.net>
-
-@date 18 August 2012
-
-LGPL License Terms @ref lgpl_license
- */
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
+ * Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
+ * Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
@@ -30,13 +18,27 @@ LGPL License Terms @ref lgpl_license
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
+/** @defgroup CM3_nvic_defines NVIC Defines
+
+@brief <b>libopencm3 Cortex Nested Vectored Interrupt Controller</b>
+
+@ingroup CM3_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2010 Piotr Esden-Tempski <piotr@esden.net>
+
+@date 18 August 2012
+
+LGPL License Terms @ref lgpl_license
+ */
/**@{*/
#ifndef LIBOPENCM3_NVIC_H
#define LIBOPENCM3_NVIC_H
-#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/cm3/common.h>
+#include <libopencm3/cm3/memorymap.h>
/* --- NVIC Registers ------------------------------------------------------ */
@@ -79,9 +81,9 @@ LGPL License Terms @ref lgpl_license
/* --- IRQ channel numbers-------------------------------------------------- */
-/* Cortex M3 System Interrupts */
-/** @defgroup nvic_sysint Cortex M3 System Interrupts
-@ingroup STM32F_nvic_defines
+/* Cortex M3 and M4 System Interrupts */
+/** @defgroup nvic_sysint Cortex M3/M4 System Interrupts
+@ingroup CM3_nvic_defines
IRQ numbers -3 and -6 to -9 are reserved
@{*/
@@ -98,21 +100,11 @@ IRQ numbers -3 and -6 to -9 are reserved
#define NVIC_SYSTICK_IRQ -1
/**@}*/
-
/* Note: User interrupts are family specific and are defined in a family
* specific header file in the corresponding subfolder.
*/
-#if defined(STM32F1)
-# include <libopencm3/stm32/f1/nvic_f1.h>
-#elif defined(STM32F2)
-# include <libopencm3/stm32/f2/nvic_f2.h>
-#elif defined(STM32F4)
-# include <libopencm3/stm32/f4/nvic_f4.h>
-#else
-# error "stm32 family not defined."
-#endif
-
+#include <libopencm3/dispatch/nvic.h>
/* --- NVIC functions ------------------------------------------------------ */
@@ -131,5 +123,3 @@ void nvic_generate_software_interrupt(u16 irqn);
END_DECLS
#endif
-/**@}*/
-
diff --git a/include/libopencm3/stm32/f4/scb.h b/include/libopencm3/cm3/scb.h
index 7187ca9..8e9c757 100644
--- a/include/libopencm3/stm32/f4/scb.h
+++ b/include/libopencm3/cm3/scb.h
@@ -21,7 +21,7 @@
#ifndef LIBOPENCM3_SCB_H
#define LIBOPENCM3_SCB_H
-#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/cm3/memorymap.h>
#include <libopencm3/cm3/common.h>
/* --- SCB: Registers ------------------------------------------------------ */
diff --git a/include/libopencm3/stm32/systick.h b/include/libopencm3/cm3/systick.h
index e42c4e6..5e7715b 100644
--- a/include/libopencm3/stm32/systick.h
+++ b/include/libopencm3/cm3/systick.h
@@ -1,22 +1,8 @@
-/** @defgroup STM32F_systick_defines SysTick Defines
-
-@brief <b>libopencm3 Defined Constants and Types for the STM32F SysTick </b>
-
-@ingroup STM32F_defines
-
-@version 1.0.0
-
-@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
-
-@date 19 August 2012
-
-LGPL License Terms @ref lgpl_license
- */
-
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
+ * Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
@@ -31,13 +17,27 @@ LGPL License Terms @ref lgpl_license
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
+/** @defgroup CM3_systick_defines SysTick Defines
+
+@brief <b>libopencm3 Defined Constants and Types for the Cortex SysTick </b>
+
+@ingroup CM3_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
+
+@date 19 August 2012
+
+LGPL License Terms @ref lgpl_license
+ */
/**@{*/
#ifndef LIBOPENCM3_SYSTICK_H
#define LIBOPENCM3_SYSTICK_H
-#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/cm3/memorymap.h>
#include <libopencm3/cm3/common.h>
/* --- SYSTICK registers --------------------------------------------------- */
@@ -63,7 +63,7 @@ LGPL License Terms @ref lgpl_license
#define STK_CTRL_CLKSOURCE (1 << 2)
#define STK_CTRL_CLKSOURCE_LSB 2
/** @defgroup systick_clksource Clock source selection
-@ingroup STM32F_systick_defines
+@ingroup CM3_systick_defines
@{*/
#define STK_CTRL_CLKSOURCE_AHB_DIV8 0
@@ -104,6 +104,8 @@ void systick_counter_enable(void);
void systick_counter_disable(void);
u8 systick_get_countflag(void);
+u32 systick_get_calib(void);
+
END_DECLS
#endif
diff --git a/include/libopencm3/cm3/vector.h b/include/libopencm3/cm3/vector.h
new file mode 100644
index 0000000..f78e9d8
--- /dev/null
+++ b/include/libopencm3/cm3/vector.h
@@ -0,0 +1,64 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 chrysn <chrysn@fsfe.org>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/** @file
+ *
+ * Definitions for handling vector tables.
+ *
+ * This implements d0002_efm32_cortex-m3_reference_manual.pdf's figure 2.2
+ * (from the EFM32 documentation at
+ * http://www.energymicro.com/downloads/datasheets), and was seen analogously
+ * in other ARM implementations' libopencm3 files.
+ *
+ * The structure of the vector table is implemented independently of the system
+ * vector table starting at memory position 0x0, as it can be relocated to
+ * other memory locations too.
+ *
+ * The exact size of a vector interrupt table depends on the number of
+ * interrupts IRQ_COUNT, which is defined per family.
+ */
+
+#ifndef LIBOPENCM3_VECTOR_H
+#define LIBOPENCM3_VECTOR_H
+
+#include <libopencm3/cm3/common.h>
+#include <libopencm3/cm3/nvic.h>
+
+/** Type of an interrupt function. Only used to avoid hard-to-read function
+ * pointers in the efm32_vector_table_t struct. */
+typedef void (*vector_table_entry_t)(void);
+
+typedef struct {
+ unsigned int *initial_sp_value; /**< The value the stack pointer is set to initially */
+ vector_table_entry_t reset;
+ vector_table_entry_t nmi;
+ vector_table_entry_t hard_fault;
+ vector_table_entry_t memory_manage_fault;
+ vector_table_entry_t bus_fault;
+ vector_table_entry_t usage_fault;
+ vector_table_entry_t reserved_x001c[4];
+ vector_table_entry_t sv_call;
+ vector_table_entry_t debug_monitor;
+ vector_table_entry_t reserved_x0034;
+ vector_table_entry_t pend_sv;
+ vector_table_entry_t systick;
+ vector_table_entry_t irq[NVIC_IRQ_COUNT];
+} vector_table_t;
+
+#endif
diff --git a/include/libopencm3/dispatch/nvic.h b/include/libopencm3/dispatch/nvic.h
new file mode 100644
index 0000000..08074e3
--- /dev/null
+++ b/include/libopencm3/dispatch/nvic.h
@@ -0,0 +1,34 @@
+#if defined(STM32F1)
+# include <libopencm3/stm32/f1/nvic.h>
+#elif defined(STM32F2)
+# include <libopencm3/stm32/f2/nvic.h>
+#elif defined(STM32F4)
+# include <libopencm3/stm32/f4/nvic.h>
+#elif defined(STM32L1)
+# include <libopencm3/stm32/l1/nvic.h>
+
+#elif defined(EFM32TG)
+# include <libopencm3/efm32/efm32tg/nvic.h>
+#elif defined(EFM32G)
+# include <libopencm3/efm32/efm32g/nvic.h>
+#elif defined(EFM32LG)
+# include <libopencm3/efm32/efm32lg/nvic.h>
+#elif defined(EFM32GG)
+# include <libopencm3/efm32/efm32gg/nvic.h>
+
+#elif defined(LPC13XX)
+# include <libopencm3/lpc13xx/nvic.h>
+#elif defined(LPC17XX)
+# include <libopencm3/lpc17xx/nvic.h>
+#elif defined(LPC43XX)
+# include <libopencm3/lpc43xx/nvic.h>
+
+#elif defined(LM3S)
+# include <libopencm3/lm3s/nvic.h>
+
+#else
+# warning"no interrupts defined for chipset; NVIC_IRQ_COUNT = 0"
+
+#define NVIC_IRQ_COUNT 0
+
+#endif
diff --git a/include/libopencm3/efm32/efm32g/irq.yaml b/include/libopencm3/efm32/efm32g/irq.yaml
new file mode 100644
index 0000000..770f755
--- /dev/null
+++ b/include/libopencm3/efm32/efm32g/irq.yaml
@@ -0,0 +1,35 @@
+includeguard: LIBOPENCM3_EFM32G_NVIC_H
+partname_humanreadable: EFM32 Gecko series
+partname_doxygen: EFM32G
+# The names and sequence are taken from d0001_efm32g_reference_manual.pdf table 4.1.
+irqs:
+ - dma
+ - gpio_even
+ - timer0
+ - usart0_rx
+ - usart0_tx
+ - acmp01
+ - adc0
+ - dac0
+ - i2c0
+ - gpio_odd
+ - timer1
+ - timer2
+ - usart1_rx
+ - usart1_tx
+ - usart2_rx
+ - usart2_tx
+ - uart0_rx
+ - uart0_tx
+ - leuart0
+ - leuart1
+ - letimer0
+ - pcnt0
+ - pcnt1
+ - pcnt2
+ - rtc
+ - cmu
+ - vcmp
+ - lcd
+ - msc
+ - aes
diff --git a/include/libopencm3/efm32/efm32gg/irq.yaml b/include/libopencm3/efm32/efm32gg/irq.yaml
new file mode 100644
index 0000000..1cb4601
--- /dev/null
+++ b/include/libopencm3/efm32/efm32gg/irq.yaml
@@ -0,0 +1,43 @@
+includeguard: LIBOPENCM3_EFM32GG_NVIC_H
+partname_humanreadable: EFM32 Giant Gecko series
+partname_doxygen: EFM32GG
+# The names and sequence are taken from d0053_efm32gg_refreence_manual.pdf table 4.1.
+irqs:
+ - dma
+ - gpio_even
+ - timer0
+ - usart0_rx
+ - usart0_tx
+ - usb
+ - acmp01
+ - adc0
+ - dac0
+ - i2c0
+ - i2c1
+ - gpio_odd
+ - timer1
+ - timer2
+ - timer3
+ - usart1_rx
+ - usart1_tx
+ - lesense
+ - usart2_rx
+ - usart2_tx
+ - uart0_rx
+ - uart0_tx
+ - uart1_rx
+ - uart1_tx
+ - leuart0
+ - leuart1
+ - letimer0
+ - pcnt0
+ - pcnt1
+ - pcnt2
+ - rtc
+ - burtc
+ - cmu
+ - vcmp
+ - lcd
+ - msc
+ - aes
+ - ebi
diff --git a/include/libopencm3/efm32/efm32lg/irq.yaml b/include/libopencm3/efm32/efm32lg/irq.yaml
new file mode 100644
index 0000000..ec38bc1
--- /dev/null
+++ b/include/libopencm3/efm32/efm32lg/irq.yaml
@@ -0,0 +1,43 @@
+includeguard: LIBOPENCM3_EFM32LG_NVIC_H
+partname_humanreadable: EFM32 Leopard Gecko series
+partname_doxygen: EFM32LG
+# The names and sequence are taken from d0183_efm32lg_reference_manual.pdf table 4.1.
+irqs:
+ - dma
+ - gpio_even
+ - timer0
+ - usart0_rx
+ - usart0_tx
+ - usb
+ - acmp01
+ - adc0
+ - dac0
+ - i2c0
+ - i2c1
+ - gpio_odd
+ - timer1
+ - timer2
+ - timer3
+ - usart1_rx
+ - usart1_tx
+ - lesense
+ - usart2_rx
+ - usart2_tx
+ - uart0_rx
+ - uart0_tx
+ - uart1_rx
+ - uart1_tx
+ - leuart0
+ - leuart1
+ - letimer0
+ - pcnt0
+ - pcnt1
+ - pcnt2
+ - rtc
+ - burtc
+ - cmu
+ - vcmp
+ - lcd
+ - msc
+ - aes
+ - ebi
diff --git a/include/libopencm3/efm32/efm32tg/irq.yaml b/include/libopencm3/efm32/efm32tg/irq.yaml
new file mode 100644
index 0000000..f4aaba3
--- /dev/null
+++ b/include/libopencm3/efm32/efm32tg/irq.yaml
@@ -0,0 +1,28 @@
+includeguard: LIBOPENCM3_EFM32TG_NVIC_H
+partname_humanreadable: EFM32 Tiny Gecko series
+partname_doxygen: EFM32TG
+# The names and sequence are taken from d0034_efm32tg_reference_manual.pdf table 4.1.
+irqs:
+ - dma
+ - gpio_even
+ - timer0
+ - usart0_rx
+ - usart0_tx
+ - acmp01
+ - adc0
+ - dac0
+ - i2c0
+ - gpio_odd
+ - timer1
+ - usart1_rx
+ - usart1_tx
+ - lesense
+ - leuart0
+ - letimer0
+ - pcnt0
+ - rtc
+ - cmu
+ - vcmp
+ - lcd
+ - msc
+ - aes
diff --git a/include/libopencm3/efm32/efm32tg/memorymap.h b/include/libopencm3/efm32/efm32tg/memorymap.h
new file mode 100644
index 0000000..abf37ce
--- /dev/null
+++ b/include/libopencm3/efm32/efm32tg/memorymap.h
@@ -0,0 +1,76 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 chrysn <chrysn@fsfe.org>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/** @file
+ *
+ * Layout of the system address space of Tiny Gecko devices.
+ *
+ * This reflects d0034_efm32tg_reference_manual.pdf figure 5.2.
+ */
+
+/* The common cortex-m3 definitions were verified from
+ * d0034_efm32tg_reference_manual.pdf figure 5.2. The CM3 ROM Table seems to be
+ * missing there. The details (everything based on SCS_BASE) was verified from
+ * d0002_efm32_cortex-m3_reference_manual.pdf table 4.1, and seems to fit, but
+ * there are discrepancies. */
+#include <libopencm3/cm3/memorymap.h>
+
+#define CODE_BASE 0x00000000
+
+#define SRAM_BASE 0x20000000
+#define SRAM_BASE_BITBAND 0x22000000
+
+#define PERIPH_BASE 0x40000000
+#define PERIPH_BASE_BITBAND 0x42000000
+
+/* Details of the "Code" section */
+
+#define FLASH_BASE (CODE_BASE + 0x00000000)
+#define USERDATA_BASE (CODE_BASE + 0x0fe00000)
+#define LOCKBITS_BASE (CODE_BASE + 0x0fe04000)
+#define CHIPCONFIG_BASE (CODE_BASE + 0x0fe08000)
+#define CODESPACESRAM_BASE (CODE_BASE + 0x10000000)
+
+/* Tiny Gecko peripherial definitions */
+
+#define VCMP_BASE (PERIPH_BASE + 0x00000000)
+#define ACMP0_BASE (PERIPH_BASE + 0x00001000)
+#define ACMP1_BASE (PERIPH_BASE + 0x00001400)
+#define ADC_BASE (PERIPH_BASE + 0x00002000)
+#define DAC0_BASE (PERIPH_BASE + 0x00004000)
+#define GPIO_BASE (PERIPH_BASE + 0x00006000) /**< @see gpio.h */
+#define I2C0_BASE (PERIPH_BASE + 0x0000a000)
+#define USART0_BASE (PERIPH_BASE + 0x0000c000)
+#define USART1_BASE (PERIPH_BASE + 0x0000c400)
+#define TIMER0_BASE (PERIPH_BASE + 0x00010000)
+#define TIMER1_BASE (PERIPH_BASE + 0x00010400)
+#define RTC_BASE (PERIPH_BASE + 0x00080000)
+#define LETIMER0_BASE (PERIPH_BASE + 0x00082000)
+#define LEUART0_BASE (PERIPH_BASE + 0x00084000)
+#define PCNT0_BASE (PERIPH_BASE + 0x00086000)
+#define WDOG_BASE (PERIPH_BASE + 0x00088000)
+#define LCD_BASE (PERIPH_BASE + 0x0008a000)
+#define LESENSE_BASE (PERIPH_BASE + 0x0008c000)
+#define MSC_BASE (PERIPH_BASE + 0x000c0000)
+#define DMA_BASE (PERIPH_BASE + 0x000c2000)
+#define EMU_BASE (PERIPH_BASE + 0x000c6000)
+#define CMU_BASE (PERIPH_BASE + 0x000c8000) /**< @see cmu.h */
+#define RMU_BASE (PERIPH_BASE + 0x000ca000)
+#define PRS_BASE (PERIPH_BASE + 0x000cc000)
+#define AES_BASE (PERIPH_BASE + 0x000e0000)
diff --git a/include/libopencm3/efm32/memorymap.h b/include/libopencm3/efm32/memorymap.h
new file mode 100644
index 0000000..ff0e544
--- /dev/null
+++ b/include/libopencm3/efm32/memorymap.h
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 chrysn <chrysn@fsfe.org>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/** @file
+ *
+ * Dispatcher for the base address definitions, depending on the particular
+ * Gecko family.
+ *
+ * @see tinygecko/memorymap.h
+ */
+
+#ifndef LIBOPENCM3_EFM32_MEMORYMAP_H
+#define LIBOPENCM3_EFM32_MEMORYMAP_H
+
+#ifdef TINYGECKO
+# include <libopencm3/efm32/tinygecko/memorymap.h>
+#else
+# error "efm32 family not defined."
+#endif
+
+#endif
diff --git a/include/libopencm3/lm3s/irq.yaml b/include/libopencm3/lm3s/irq.yaml
new file mode 100644
index 0000000..7d5ff3a
--- /dev/null
+++ b/include/libopencm3/lm3s/irq.yaml
@@ -0,0 +1,120 @@
+includeguard: LIBOPENCM3_LM3S_NVIC_H
+partname_humanreadable: LM3S series
+partname_doxygen: LM3S
+irqs:
+ 0: GPIOA
+ 1: GPIOB
+ 2: GPIOC
+ 3: GPIOD
+ 4: GPIOE
+ 5: UART0
+ 6: UART1
+ 7: SSI0
+ 8: I2C0
+ 9: PWM0_FAULT
+ 10: PWM0_0
+ 11: PWM0_1
+ 12: PWM0_2
+ 13: QEI0
+ 14: ADC0SS0
+ 15: ADC0SS1
+ 16: ADC0SS2
+ 17: ADC0SS3
+ 18: WATCHDOG
+ 19: TIMER0A
+ 20: TIMER0B
+ 21: TIMER1A
+ 22: TIMER1B
+ 23: TIMER2A
+ 24: TIMER2B
+ 25: COMP0
+ 26: COMP1
+ 27: COMP2
+ 28: SYSCTL
+ 29: FLASH
+ 30: GPIOF
+ 31: GPIOG
+ 32: GPIOH
+ 33: UART2
+ 34: SSI1
+ 35: TIMER3A
+ 36: TIMER3B
+ 37: I2C1
+ 38: QEI1
+ 39: CAN0
+ 40: CAN1
+ 41: CAN2
+ 42: ETH
+ 43: HIBERNATE
+ 44: USB0
+ 45: PWM0_3
+ 46: UDMA
+ 47: UDMAERR
+ 48: ADC1SS0
+ 49: ADC1SS1
+ 50: ADC1SS2
+ 51: ADC1SS3
+ 52: I2S0
+ 53: EPI0
+ 54: GPIOJ
+ 55: GPIOK
+ 56: GPIOL
+ 57: SSI2
+ 58: SSI3
+ 59: UART3
+ 60: UART4
+ 61: UART5
+ 62: UART6
+ 63: UART7
+# undefined: slot 64 - 67
+ 68: I2C2
+ 69: I2C3
+ 70: TIMER4A
+ 71: TIMER4B
+# undefined: slot 72 - 91
+ 92: TIMER5A
+ 93: TIMER5B
+ 94: WTIMER0A
+ 95: WTIMER0B
+ 96: WTIMER1A
+ 97: WTIMER1B
+ 98: WTIMER2A
+ 99: WTIMER2B
+ 100: WTIMER3A
+ 101: WTIMER3B
+ 102: WTIMER4A
+ 103: WTIMER4B
+ 104: WTIMER5A
+ 105: WTIMER5B
+ 106: SYSEXC
+ 107: PECI0
+ 108: LPC0
+ 109: I2C4
+ 110: I2C5
+ 111: GPIOM
+ 112: GPION
+# undefined: slot 113
+ 114: FAN0
+# undefined: slot 115
+ 116: GPIOP0
+ 117: GPIOP1
+ 118: GPIOP2
+ 119: GPIOP3
+ 120: GPIOP4
+ 121: GPIOP5
+ 122: GPIOP6
+ 123: GPIOP7
+ 124: GPIOQ0
+ 125: GPIOQ1
+ 126: GPIOQ2
+ 127: GPIOQ3
+ 128: GPIOQ4
+ 129: GPIOQ5
+ 130: GPIOQ6
+ 131: GPIOQ7
+# undefined: slot 132 - 133
+ 134: PWM1_0
+ 135: PWM1_1
+ 136: PWM1_2
+ 137: PWM1_3
+ 138: PWM1_FAULT
diff --git a/include/libopencm3/lpc13xx/irq.yaml b/include/libopencm3/lpc13xx/irq.yaml
new file mode 100644
index 0000000..5a372db
--- /dev/null
+++ b/include/libopencm3/lpc13xx/irq.yaml
@@ -0,0 +1,62 @@
+includeguard: LIBOPENCM3_LPC13xx_NVIC_H
+partname_humanreadable: LPC 13xx series
+partname_doxygen: LPC13xx
+irqs:
+ 0: pio0_0
+ 1: pio0_1
+ 2: pio0_2
+ 3: pio0_3
+ 4: pio0_4
+ 5: pio0_5
+ 6: pio0_6
+ 7: pio0_7
+ 8: pio0_8
+ 9: pio0_9
+ 10: pio0_10
+ 11: pio0_11
+ 12: pio1_0
+ 13: pio1_1
+ 14: pio1_2
+ 15: pio1_3
+ 16: pio1_4
+ 17: pio1_5
+ 18: pio1_6
+ 19: pio1_7
+ 20: pio1_8
+ 21: pio1_9
+ 22: pio1_10
+ 23: pio1_11
+ 24: pio2_0
+ 25: pio2_1
+ 26: pio2_2
+ 27: pio2_3
+ 28: pio2_4
+ 29: pio2_5
+ 30: pio2_6
+ 31: pio2_7
+ 32: pio2_8
+ 33: pio2_9
+ 34: pio2_10
+ 35: pio2_11
+ 36: pio3_0
+ 37: pio3_1
+ 38: pio3_2
+ 39: pio3_3
+ 40: i2c0
+ 41: ct16b0
+ 42: ct16b1
+ 43: ct32b0
+ 44: ct32b1
+ 45: ssp0
+ 46: uart
+ 47: usb
+ 48: usb_fiq
+ 49: adc
+ 50: wdt
+ 51: bod
+# 52: reserved
+ 53: pio3
+ 54: pio2
+ 55: pio1
+ 56: pio0
+ 56: ssp1
diff --git a/include/libopencm3/lpc17xx/irq.yaml b/include/libopencm3/lpc17xx/irq.yaml
new file mode 100644
index 0000000..faa140f
--- /dev/null
+++ b/include/libopencm3/lpc17xx/irq.yaml
@@ -0,0 +1,39 @@
+includeguard: LIBOPENCM3_LPC17xx_NVIC_H
+partname_humanreadable: LPC 17xx series
+partname_doxygen: LPC17xx
+irqs:
+ 0: wdt
+ 1: timer0
+ 2: timer1
+ 3: timer2
+ 4: timer3
+ 5: uart0
+ 6: uart1
+ 7: uart2
+ 8: uart3
+ 9: pwm
+ 10: i2c0
+ 11: i2c1
+ 12: i2c2
+ 13: spi
+ 14: ssp0
+ 15: ssp1
+ 16: pll0
+ 17: rtc
+ 18: eint0
+ 19: eint1
+ 20: eint2
+ 21: eint3
+ 22: adc
+ 23: bod
+ 24: usb
+ 25: can
+ 26: gpdma
+ 27: i2s
+ 28: ethernet
+ 29: rit
+ 30: motor_pwm
+ 31: qei
+ 32: pll1
+ 33: usb_act
+ 34: can_act
diff --git a/include/libopencm3/lpc43xx/irq.yaml b/include/libopencm3/lpc43xx/irq.yaml
new file mode 100644
index 0000000..bc9536b
--- /dev/null
+++ b/include/libopencm3/lpc43xx/irq.yaml
@@ -0,0 +1,55 @@
+includeguard: LIBOPENCM3_LPC43xx_NVIC_H
+partname_humanreadable: LPC 43xx series
+partname_doxygen: LPC43xx
+irqs:
+ 0: dac
+ 1: m0core
+ 2: dma
+# reserved: 3, 4
+ 5: ethernet
+ 6: sdio
+ 7: lcd
+ 8: usb0
+ 9: usb1
+ 10: sct
+ 11: ritimer
+ 12: timer0
+ 13: timer1
+ 14: timer2
+ 15: timer3
+ 16: mcpwm
+ 17: adc0
+ 18: i2c0
+ 19: i2c1
+ 20: spi
+ 21: adc1
+ 22: ssp0
+ 23: ssp1
+ 24: usart0
+ 25: uart1
+ 26: usart2
+ 27: usart3
+ 28: i2s0
+ 29: i2s1
+ 30: spifi
+ 31: sgpio
+ 32: pin_int0
+ 33: pin_int1
+ 34: pin_int2
+ 35: pin_int3
+ 36: pin_int4
+ 37: pin_int5
+ 38: pin_int6
+ 39: pin_int7
+ 40: gint0
+ 41: gint1
+ 42: eventrouter
+ 43: c_can1
+# reserved: 44, 45
+ 46: atimer
+ 47: rtc
+# reserved: 48
+ 49: wwdt
+# reserved: 50
+ 51: c_can0
+ 52: qei
diff --git a/include/libopencm3/lpc43xx/nvic.h b/include/libopencm3/lpc43xx/nvic.h
deleted file mode 100644
index cdbf070..0000000
--- a/include/libopencm3/lpc43xx/nvic.h
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * This file is part of the libopencm3 project.
- *
- * Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
- * Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
- * Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef LPC43XX_NVIC_H
-#define LPC43XX_NVIC_H
-
-#include <libopencm3/cm3/common.h>
-#include <libopencm3/cm3/memorymap.h>
-#include <libopencm3/lpc43xx/memorymap.h>
-
-/* --- NVIC Registers ------------------------------------------------------ */
-
-/* ISER: Interrupt Set Enable Registers */
-/* Note: 8 32bit Registers */
-#define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + (iser_id * 4))
-
-/* NVIC_BASE + 0x020 (0xE000 E120 - 0xE000 E17F): Reserved */
-
-/* ICER: Interrupt Clear Enable Registers */
-/* Note: 8 32bit Registers */
-#define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + (icer_id * 4))
-
-/* NVIC_BASE + 0x0A0 (0xE000 E1A0 - 0xE000 E1FF): Reserved */
-
-/* ISPR: Interrupt Set Pending Registers */
-/* Note: 8 32bit Registers */
-#define NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + (ispr_id * 4))
-
-/* NVIC_BASE + 0x120 (0xE000 E220 - 0xE000 E27F): Reserved */
-
-/* ICPR: Interrupt Clear Pending Registers */
-/* Note: 8 32bit Registers */
-#define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + (icpr_id * 4))
-
-/* NVIC_BASE + 0x1A0 (0xE000 E2A0 - 0xE00 E2FF): Reserved */
-
-/* IABR: Interrupt Active Bit Register */
-/* Note: 8 32bit Registers */
-#define NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + (iabr_id * 4))
-
-/* NVIC_BASE + 0x220 (0xE000 E320 - 0xE000 E3FF): Reserved */
-
-/* IPR: Interrupt Priority Registers */
-/* Note: 240 8bit Registers */
-#define NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + ipr_id)
-
-/* STIR: Software Trigger Interrupt Register */
-#define NVIC_STIR MMIO32(STIR_BASE)
-
-/* --- IRQ channel numbers-------------------------------------------------- */
-
-/* Cortex M4 System Interrupts */
-#define NVIC_NMI_IRQ -14
-#define NVIC_HARD_FAULT_IRQ -13
-#define NVIC_MEM_MANAGE_IRQ -12
-#define NVIC_BUS_FAULT_IRQ -11
-#define NVIC_USAGE_FAULT_IRQ -10
-/* irq numbers -6 to -9 are reserved */
-#define NVIC_SV_CALL_IRQ -5
-#define DEBUG_MONITOR_IRQ -4
-/* irq number -3 reserved */
-#define NVIC_PENDSV_IRQ -2
-#define NVIC_SYSTICK_IRQ -1
-
-/* LPC43xx M4 specific user interrupts */
-#define NVIC_M4_DAC_IRQ 0
-#define NVIC_M4_M0CORE_IRQ 1
-#define NVIC_M4_DMA_IRQ 2
-#define NVIC_M4_ETHERNET_IRQ 5
-#define NVIC_M4_SDIO_IRQ 6
-#define NVIC_M4_LCD_IRQ 7
-#define NVIC_M4_USB0_IRQ 8
-#define NVIC_M4_USB1_IRQ 9
-#define NVIC_M4_SCT_IRQ 10
-#define NVIC_M4_RITIMER_IRQ 11
-#define NVIC_M4_TIMER0_IRQ 12
-#define NVIC_M4_TIMER1_IRQ 13
-#define NVIC_M4_TIMER2_IRQ 14
-#define NVIC_M4_TIMER3_IRQ 15
-#define NVIC_M4_MCPWM_IRQ 16
-#define NVIC_M4_ADC0_IRQ 17
-#define NVIC_M4_I2C0_IRQ 18
-#define NVIC_M4_I2C1_IRQ 19
-#define NVIC_M4_SPI_IRQ 20
-#define NVIC_M4_ADC1_IRQ 21
-#define NVIC_M4_SSP0_IRQ 22
-#define NVIC_M4_SSP1_IRQ 23
-#define NVIC_M4_USART0_IRQ 24
-#define NVIC_M4_UART1_IRQ 25
-#define NVIC_M4_USART2_IRQ 26
-#define NVIC_M4_USART3_IRQ 27
-#define NVIC_M4_I2S0_IRQ 28
-#define NVIC_M4_I2S1_IRQ 29
-#define NVIC_M4_SPIFI_IRQ 30
-#define NVIC_M4_SGPIO_IRQ 31
-#define NVIC_M4_PIN_INT0_IRQ 32
-#define NVIC_M4_PIN_INT1_IRQ 33
-#define NVIC_M4_PIN_INT2_IRQ 34
-#define NVIC_M4_PIN_INT3_IRQ 35
-#define NVIC_M4_PIN_INT4_IRQ 36
-#define NVIC_M4_PIN_INT5_IRQ 37
-#define NVIC_M4_PIN_INT6_IRQ 38
-#define NVIC_M4_PIN_INT7_IRQ 39
-#define NVIC_M4_GINT0_IRQ 40
-#define NVIC_M4_GINT1_IRQ 41
-#define NVIC_M4_EVENTROUTER_IRQ 42
-#define NVIC_M4_C_CAN1_IRQ 43
-#define NVIC_M4_ATIMER_IRQ 46
-#define NVIC_M4_RTC_IRQ 47
-#define NVIC_M4_WWDT_IRQ 49
-#define NVIC_M4_C_CAN0_IRQ 51
-#define NVIC_M4_QEI_IRQ 52
-
-/* LPC43xx M0 specific user interrupts */
-//TODO
-
-/* --- NVIC functions ------------------------------------------------------ */
-
-BEGIN_DECLS
-
-void nvic_enable_irq(u8 irqn);
-void nvic_disable_irq(u8 irqn);
-u8 nvic_get_pending_irq(u8 irqn);
-void nvic_set_pending_irq(u8 irqn);
-void nvic_clear_pending_irq(u8 irqn);
-u8 nvic_get_active_irq(u8 irqn);
-u8 nvic_get_irq_enabled(u8 irqn);
-void nvic_set_priority(u8 irqn, u8 priority);
-void nvic_generate_software_interrupt(u8 irqn);
-
-END_DECLS
-
-#endif
diff --git a/include/libopencm3/lpc43xx/systick.h b/include/libopencm3/lpc43xx/systick.h
deleted file mode 100644
index 2ae52c2..0000000
--- a/include/libopencm3/lpc43xx/systick.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * This file is part of the libopencm3 project.
- *
- * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
- * Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef LIBOPENCM3_SYSTICK_H
-#define LIBOPENCM3_SYSTICK_H
-
-#include <libopencm3/lpc43xx/memorymap.h>
-#include <libopencm3/cm3/memorymap.h>
-#include <libopencm3/cm3/common.h>
-
-/* --- SYSTICK registers --------------------------------------------------- */
-/* See also libopencm3\cm3\scs.h for details on SysTicks registers */
-
-/* Control and status register (STK_CTRL) */
-#define STK_CTRL MMIO32(SYS_TICK_BASE + 0x00)
-
-/* reload value register (STK_LOAD) */
-#define STK_LOAD MMIO32(SYS_TICK_BASE + 0x04)
-
-/* current value register (STK_VAL) */
-#define STK_VAL MMIO32(SYS_TICK_BASE + 0x08)
-
-/* calibration value register (STK_CALIB) */
-#define STK_CALIB MMIO32(SYS_TICK_BASE + 0x0C)
-
-/* --- STK_CTRL values ----------------------------------------------------- */
-/* Bits [31:17] Reserved, must be kept cleared. */
-/* COUNTFLAG: */
-#define STK_CTRL_COUNTFLAG (1 << 16)
-/* Bits [15:3] Reserved, must be kept cleared. */
-/* CLKSOURCE: Clock source selection */
-#define STK_CTRL_CLKSOURCE (1 << 2)
-/* TICKINT: SysTick exception request enable */
-#define STK_CTRL_TICKINT (1 << 1)
-/* ENABLE: Counter enable */
-#define STK_CTRL_ENABLE (1 << 0)
-
-/* --- STK_LOAD values ----------------------------------------------------- */
-/* Bits [31:24] Reserved, must be kept cleared. */
-/* RELOAD[23:0]: RELOAD value */
-
-/* --- STK_VAL values ------------------------------------------------------ */
-/* Bits [31:24] Reserved, must be kept cleared. */
-/* CURRENT[23:0]: Current counter value */
-
-/* --- STK_CALIB values ---------------------------------------------------- */
-/* NOREF: NOREF flag */
-#define STK_CALIB_NOREF (1 << 31)
-/* SKEW: SKEW flag */
-#define STK_CALIB_SKEW (1 << 30)
-/* Bits [29:24] Reserved, must be kept cleared. */
-/* TENMS[23:0]: Calibration value */
-
-/* --- Function Prototypes ------------------------------------------------- */
-
-BEGIN_DECLS
-
-void systick_set_reload(u32 value);
-u32 systick_get_value(void);
-void systick_set_clocksource(u8 clocksource);
-void systick_interrupt_enable(void);
-void systick_interrupt_disable(void);
-void systick_counter_enable(void);
-void systick_counter_disable(void);
-u8 systick_get_countflag(void);
-
-u32 systick_get_calib(void);
-
-END_DECLS
-
-#endif
diff --git a/include/libopencm3/stm32/can.h b/include/libopencm3/stm32/can.h
index 1919da4..c6c9d48 100644
--- a/include/libopencm3/stm32/can.h
+++ b/include/libopencm3/stm32/can.h
@@ -461,7 +461,7 @@
/* --- CAN_TIxR values ------------------------------------------------------ */
/* STID[10:0]: Standard identifier */
-#define CAN_TIxR_STID_MASK (0x3FF << 21)
+#define CAN_TIxR_STID_MASK (0x7FF << 21)
#define CAN_TIxR_STID_SHIFT 21
/* EXID[15:0]: Extended identifier */
diff --git a/include/libopencm3/stm32/f1/desig.h b/include/libopencm3/stm32/desig.h
index 6ceb665..6ceb665 100644
--- a/include/libopencm3/stm32/f1/desig.h
+++ b/include/libopencm3/stm32/desig.h
diff --git a/include/libopencm3/stm32/exti.h b/include/libopencm3/stm32/exti.h
index 7645825..48065b9 100644
--- a/include/libopencm3/stm32/exti.h
+++ b/include/libopencm3/stm32/exti.h
@@ -53,6 +53,9 @@
#define EXTI17 (1 << 17)
#define EXTI18 (1 << 18)
#define EXTI19 (1 << 19)
+#define EXTI20 (1 << 20)
+#define EXTI21 (1 << 21)
+#define EXTI22 (1 << 22)
/* Trigger types */
typedef enum trigger_e {
diff --git a/include/libopencm3/stm32/f1/dma.h b/include/libopencm3/stm32/f1/dma.h
index 8a2edba..6257394 100644
--- a/include/libopencm3/stm32/f1/dma.h
+++ b/include/libopencm3/stm32/f1/dma.h
@@ -141,9 +141,30 @@ LGPL License Terms @ref lgpl_license
/* --- DMA_ISR values ------------------------------------------------------ */
+/* --- DMA Interrupt Flag offset values ------------------------------------- */
+/* These are based on every interrupt flag and flag clear being at the same relative location */
+/** @defgroup dma_if_offset DMA Interrupt Flag Offsets within stream flag group.
+@ingroup STM32F1xx_dma_defines
+
+@{*/
+/** Transfer Error Interrupt Flag */
+#define DMA_TEIF (1 << 3)
+/** Half Transfer Interrupt Flag */
+#define DMA_HTIF (1 << 2)
+/** Transfer Complete Interrupt Flag */
+#define DMA_TCIF (1 << 1)
+/** Global Interrupt Flag */
+#define DMA_GIF (1 << 0)
+/**@}*/
+
+/* Offset within interrupt status register to start of stream interrupt flag field */
+#define DMA_FLAG_OFFSET(channel) (4*(channel - 1))
+#define DMA_FLAGS (DMA_TEIF | DMA_TCIF | DMA_HTIF | DMA_GIF)
+#define DMA_ISR_MASK(channel) DMA_FLAGS << DMA_FLAG_OFFSET(channel)
+
/* TEIF: Transfer error interrupt flag */
-#define DMA_ISR_TEIF_BIT (1 << 3)
-#define DMA_ISR_TEIF(channel) (DMA_ISR_TEIF_BIT << (4 * ((channel) -1)))
+#define DMA_ISR_TEIF_BIT DMA_ISR_TEIF
+#define DMA_ISR_TEIF(channel) (DMA_ISR_TEIF_BIT << DMA_FLAG_OFFSET(channel)))
#define DMA_ISR_TEIF1 DMA_ISR_TEIF(DMA_CHANNEL1)
#define DMA_ISR_TEIF2 DMA_ISR_TEIF(DMA_CHANNEL2)
@@ -154,8 +175,8 @@ LGPL License Terms @ref lgpl_license
#define DMA_ISR_TEIF7 DMA_ISR_TEIF(DMA_CHANNEL7)
/* HTIF: Half transfer interrupt flag */
-#define DMA_ISR_HTIF_BIT (1 << 2)
-#define DMA_ISR_HTIF(channel) (DMA_ISR_HTIF_BIT << (4 * ((channel) -1)))
+#define DMA_ISR_HTIF_BIT DMA_HTIF
+#define DMA_ISR_HTIF(channel) (DMA_ISR_HTIF_BIT << DMA_FLAG_OFFSET(channel)))
#define DMA_ISR_HTIF1 DMA_ISR_HTIF(DMA_CHANNEL1)
#define DMA_ISR_HTIF2 DMA_ISR_HTIF(DMA_CHANNEL2)
@@ -166,8 +187,8 @@ LGPL License Terms @ref lgpl_license
#define DMA_ISR_HTIF7 DMA_ISR_HTIF(DMA_CHANNEL7)
/* TCIF: Transfer complete interrupt flag */
-#define DMA_ISR_TCIF_BIT (1 << 1)
-#define DMA_ISR_TCIF(channel) (DMA_ISR_TCIF_BIT << (4 * ((channel) -1)))
+#define DMA_ISR_TCIF_BIT DMA_TCIF
+#define DMA_ISR_TCIF(channel) (DMA_ISR_TCIF_BIT << (DMA_FLAG_OFFSET(channel)))
#define DMA_ISR_TCIF1 DMA_ISR_TCIF(DMA_CHANNEL1)
#define DMA_ISR_TCIF2 DMA_ISR_TCIF(DMA_CHANNEL2)
@@ -178,8 +199,8 @@ LGPL License Terms @ref lgpl_license
#define DMA_ISR_TCIF7 DMA_ISR_TCIF(DMA_CHANNEL7)
/* GIF: Global interrupt flag */
-#define DMA_ISR_GIF_BIT (1 << 0)
-#define DMA_ISR_GIF(channel) (DMA_ISR_GIF_BIT << (4 * ((channel) -1)))
+#define DMA_ISR_GIF_BIT DMA_GIF
+#define DMA_ISR_GIF(channel) (DMA_ISR_GIF_BIT << (DMA_FLAG_OFFSET(channel)))
#define DMA_ISR_GIF1 DMA_ISR_GIF(DMA_CHANNEL1)
#define DMA_ISR_GIF2 DMA_ISR_GIF(DMA_CHANNEL2)
@@ -192,8 +213,8 @@ LGPL License Terms @ref lgpl_license
/* --- DMA_IFCR values ----------------------------------------------------- */
/* CTEIF: Transfer error clear */
-#define DMA_IFCR_CTEIF_BIT (1 << 3)
-#define DMA_IFCR_CTEIF(channel) (DMA_IFCR_CTEIF_BIT << (4 * ((channel) -1)))
+#define DMA_IFCR_CTEIF_BIT DMA_TEIF
+#define DMA_IFCR_CTEIF(channel) (DMA_IFCR_CTEIF_BIT << (DMA_FLAG_OFFSET(channel)))
#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF(DMA_CHANNEL1)
#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF(DMA_CHANNEL2)
@@ -204,8 +225,8 @@ LGPL License Terms @ref lgpl_license
#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF(DMA_CHANNEL7)
/* CHTIF: Half transfer clear */
-#define DMA_IFCR_CHTIF_BIT (1 << 2)
-#define DMA_IFCR_CHTIF(channel) (DMA_IFCR_CHTIF_BIT << (4 * ((channel) -1)))
+#define DMA_IFCR_CHTIF_BIT DMA_HTIF
+#define DMA_IFCR_CHTIF(channel) (DMA_IFCR_CHTIF_BIT << (DMA_FLAG_OFFSET(channel)))
#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF(DMA_CHANNEL1)
#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF(DMA_CHANNEL2)
@@ -216,8 +237,8 @@ LGPL License Terms @ref lgpl_license
#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF(DMA_CHANNEL7)
/* CTCIF: Transfer complete clear */
-#define DMA_IFCR_CTCIF_BIT (1 << 1)
-#define DMA_IFCR_CTCIF(channel) (DMA_IFCR_CTCIF_BIT << (4 * ((channel) -1)))
+#define DMA_IFCR_CTCIF_BIT DMA_TCIF
+#define DMA_IFCR_CTCIF(channel) (DMA_IFCR_CTCIF_BIT << (DMA_FLAG_OFFSET(channel)))
#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF(DMA_CHANNEL1)
#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF(DMA_CHANNEL2)
@@ -228,8 +249,8 @@ LGPL License Terms @ref lgpl_license
#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF(DMA_CHANNEL7)
/* CGIF: Global interrupt clear */
-#define DMA_IFCR_CGIF_BIT (1 << 0)
-#define DMA_IFCR_CGIF(channel) (DMA_IFCR_CGIF_BIT << (4 * ((channel) -1)))
+#define DMA_IFCR_CGIF_BIT DMA_GIF
+#define DMA_IFCR_CGIF(channel) (DMA_IFCR_CGIF_BIT << (DMA_FLAG_OFFSET(channel)))
#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF(DMA_CHANNEL1)
#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF(DMA_CHANNEL2)
@@ -241,7 +262,7 @@ LGPL License Terms @ref lgpl_license
/* Clear interrupts mask */
#define DMA_IFCR_CIF_BIT 0xF
-#define DMA_IFCR_CIF(channel) (DMA_IFCR_CIF_BIT << (4 * ((channel) - 1)))
+#define DMA_IFCR_CIF(channel) (DMA_IFCR_CIF_BIT << (DMA_FLAG_OFFSET(channel)))
#define DMA_IFCR_CIF1 DMA_IFCR_CIF(DMA_CHANNEL1)
#define DMA_IFCR_CIF2 DMA_IFCR_CIF(DMA_CHANNEL2)
@@ -349,12 +370,16 @@ LGPL License Terms @ref lgpl_license
BEGIN_DECLS
void dma_channel_reset(u32 dma, u8 channel);
+void dma_clear_interrupt_flags(u32 dma, u8 channel, u32 interrupts);
+bool dma_get_interrupt_flag(u32 dma, u8 channel, u32 interrupts);
void dma_enable_mem2mem_mode(u32 dma, u8 channel);
void dma_set_priority(u32 dma, u8 channel, u32 prio);
void dma_set_memory_size(u32 dma, u8 channel, u32 mem_size);
void dma_set_peripheral_size(u32 dma, u8 channel, u32 peripheral_size);
void dma_enable_memory_increment_mode(u32 dma, u8 channel);
+void dma_disable_memory_increment_mode(u32 dma, u8 channel);
void dma_enable_peripheral_increment_mode(u32 dma, u8 channel);
+void dma_disable_peripheral_increment_mode(u32 dma, u8 channel);
void dma_enable_circular_mode(u32 dma, u8 channel);
void dma_set_read_from_peripheral(u32 dma, u8 channel);
void dma_set_read_from_memory(u32 dma, u8 channel);
diff --git a/include/libopencm3/stm32/f1/gpio.h b/include/libopencm3/stm32/f1/gpio.h
index a1e74cc..f342504 100644
--- a/include/libopencm3/stm32/f1/gpio.h
+++ b/include/libopencm3/stm32/f1/gpio.h
@@ -103,18 +103,18 @@ LGPL License Terms @ref lgpl_license
/* CAN1 / CAN BANK */
#define GPIO_BANK_CAN1_RX GPIOA /* PA11 */
#define GPIO_BANK_CAN1_TX GPIOA /* PA12 */
-#define GPIO_BANK_CAN_RX GPIO_CAN1_RX /* Alias */
-#define GPIO_BANK_CAN_TX GPIO_CAN1_TX /* Alias */
+#define GPIO_BANK_CAN_RX GPIO_BANK_CAN1_RX /* Alias */
+#define GPIO_BANK_CAN_TX GPIO_BANK_CAN1_TX /* Alias */
#define GPIO_BANK_CAN_PB_RX GPIOB /* PB8 */
#define GPIO_BANK_CAN_PB_TX GPIOB /* PB9 */
-#define GPIO_BANK_CAN1_PB_RX GPIO_CAN_PB_RX /* Alias */
-#define GPIO_BANK_CAN1_PB_TX GPIO_CAN_PB_TX /* Alias */
+#define GPIO_BANK_CAN1_PB_RX GPIO_BANK_CAN_PB_RX /* Alias */
+#define GPIO_BANK_CAN1_PB_TX GPIO_BANK_CAN_PB_TX /* Alias */
#define GPIO_BANK_CAN_PD_RX GPIOD /* PD0 */
#define GPIO_BANK_CAN_PD_TX GPIOD /* PD1 */
-#define GPIO_BANK_CAN1_PD_RX GPIO_CAN_PD_RX /* Alias */
-#define GPIO_BANK_CAN1_PD_TX GPIO_CAN_PD_TX /* Alias */
+#define GPIO_BANK_CAN1_PD_RX GPIO_BANK_CAN_PD_RX /* Alias */
+#define GPIO_BANK_CAN1_PD_TX GPIO_BANK_CAN_PD_TX /* Alias */
/* CAN2 GPIO */
#define GPIO_CAN2_RX GPIO12 /* PB12 */
diff --git a/include/libopencm3/stm32/f1/irq.yaml b/include/libopencm3/stm32/f1/irq.yaml
new file mode 100644
index 0000000..14cbcc0
--- /dev/null
+++ b/include/libopencm3/stm32/f1/irq.yaml
@@ -0,0 +1,72 @@
+includeguard: LIBOPENCM3_STM32_F1_NVIC_H
+partname_humanreadable: STM32 F1 series
+partname_doxygen: STM32F1
+irqs:
+ - wwdg
+ - pvd
+ - tamper
+ - rtc
+ - flash
+ - rcc
+ - exti0
+ - exti1
+ - exti2
+ - exti3
+ - exti4
+ - dma1_channel1
+ - dma1_channel2
+ - dma1_channel3
+ - dma1_channel4
+ - dma1_channel5
+ - dma1_channel6
+ - dma1_channel7
+ - adc1_2
+ - usb_hp_can_tx
+ - usb_lp_can_rx0
+ - can_rx1
+ - can_sce
+ - exti9_5
+ - tim1_brk
+ - tim1_up
+ - tim1_trg_com
+ - tim1_cc
+ - tim2
+ - tim3
+ - tim4
+ - i2c1_ev
+ - i2c1_er
+ - i2c2_ev
+ - i2c2_er
+ - spi1
+ - spi2
+ - usart1
+ - usart2
+ - usart3
+ - exti15_10
+ - rtc_alarm
+ - usb_wakeup
+ - tim8_brk
+ - tim8_up
+ - tim8_trg_com
+ - tim8_cc
+ - adc3
+ - fsmc
+ - sdio
+ - tim5
+ - spi3
+ - uart4
+ - uart5
+ - tim6
+ - tim7
+ - dma2_channel1
+ - dma2_channel2
+ - dma2_channel3
+ - dma2_channel4_5
+ - dma2_channel5
+ - eth
+ - eth_wkup
+ - can2_tx
+ - can2_rx0
+ - can2_rx1
+ - can2_sce
+ - otg_fs
diff --git a/include/libopencm3/stm32/f1/nvic_f1.h b/include/libopencm3/stm32/f1/nvic_f1.h
deleted file mode 100644
index 5223bb6..0000000
--- a/include/libopencm3/stm32/f1/nvic_f1.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/** @brief <b>Defined Constants and Types for the STM32F1xx Nested Vectored Interrupt Controller</b>
-
-@version 1.0.0
-
-@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
-
-@date 18 August 2012
-
-LGPL License Terms @ref lgpl_license
- */
-/*
- * This file is part of the libopencm3 project.
- *
- * Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef LIBOPENCM3_NVIC_F1_H
-#define LIBOPENCM3_NVIC_F1_H
-
-/* --- IRQ channel numbers-------------------------------------------------- */
-
-/* Note: These F1 specific user interrupt definitions supplement the
- * general NVIC definitions in ../nvic.h
- */
-
-/* User Interrupts */
-/** @defgroup nvic_stm32f1_userint STM32F1xx User Interrupts
-@ingroup STM32F_nvic_defines
-
-@{*/
-#define NVIC_WWDG_IRQ 0
-#define NVIC_PVD_IRQ 1
-#define NVIC_TAMPER_IRQ 2
-#define NVIC_RTC_IRQ 3
-#define NVIC_FLASH_IRQ 4
-#define NVIC_RCC_IRQ 5
-#define NVIC_EXTI0_IRQ 6
-#define NVIC_EXTI1_IRQ 7
-#define NVIC_EXTI2_IRQ 8
-#define NVIC_EXTI3_IRQ 9
-#define NVIC_EXTI4_IRQ 10
-#define NVIC_DMA1_CHANNEL1_IRQ 11
-#define NVIC_DMA1_CHANNEL2_IRQ 12
-#define NVIC_DMA1_CHANNEL3_IRQ 13
-#define NVIC_DMA1_CHANNEL4_IRQ 14
-#define NVIC_DMA1_CHANNEL5_IRQ 15
-#define NVIC_DMA1_CHANNEL6_IRQ 16
-#define NVIC_DMA1_CHANNEL7_IRQ 17
-#define NVIC_ADC1_2_IRQ 18
-#define NVIC_USB_HP_CAN_TX_IRQ 19
-#define NVIC_USB_LP_CAN_RX0_IRQ 20
-#define NVIC_CAN_RX1_IRQ 21
-#define NVIC_CAN_SCE_IRQ 22
-#define NVIC_EXTI9_5_IRQ 23
-#define NVIC_TIM1_BRK_IRQ 24
-#define NVIC_TIM1_UP_IRQ 25
-#define NVIC_TIM1_TRG_COM_IRQ 26
-#define NVIC_TIM1_CC_IRQ 27
-#define NVIC_TIM2_IRQ 28
-#define NVIC_TIM3_IRQ 29
-#define NVIC_TIM4_IRQ 30
-#define NVIC_I2C1_EV_IRQ 31
-#define NVIC_I2C1_ER_IRQ 32
-#define NVIC_I2C2_EV_IRQ 33
-#define NVIC_I2C2_ER_IRQ 34
-#define NVIC_SPI1_IRQ 35
-#define NVIC_SPI2_IRQ 36
-#define NVIC_USART1_IRQ 37
-#define NVIC_USART2_IRQ 38
-#define NVIC_USART3_IRQ 39
-#define NVIC_EXTI15_10_IRQ 40
-#define NVIC_RTC_ALARM_IRQ 41
-#define NVIC_USB_WAKEUP_IRQ 42
-#define NVIC_TIM8_BRK_IRQ 43
-#define NVIC_TIM8_UP_IRQ 44
-#define NVIC_TIM8_TRG_COM_IRQ 45
-#define NVIC_TIM8_CC_IRQ 46
-#define NVIC_ADC3_IRQ 47
-#define NVIC_FSMC_IRQ 48
-#define NVIC_SDIO_IRQ 49
-#define NVIC_TIM5_IRQ 50
-#define NVIC_SPI3_IRQ 51
-#define NVIC_UART4_IRQ 52
-#define NVIC_UART5_IRQ 53
-#define NVIC_TIM6_IRQ 54
-#define NVIC_TIM7_IRQ 55
-#define NVIC_DMA2_CHANNEL1_IRQ 56
-#define NVIC_DMA2_CHANNEL2_IRQ 57
-#define NVIC_DMA2_CHANNEL3_IRQ 58
-#define NVIC_DMA2_CHANNEL4_5_IRQ 59
-#define NVIC_DMA2_CHANNEL5_IRQ 60
-#define NVIC_ETH_IRQ 61
-#define NVIC_ETH_WKUP_IRQ 62
-#define NVIC_CAN2_TX_IRQ 63
-#define NVIC_CAN2_RX0_IRQ 64
-#define NVIC_CAN2_RX1_IRQ 65
-#define NVIC_CAN2_SCE_IRQ 66
-#define NVIC_OTG_FS_IRQ 67
-/**@}*/
-
-#endif
diff --git a/include/libopencm3/stm32/f1/scb.h b/include/libopencm3/stm32/f1/scb.h
deleted file mode 100644
index 181aa7a..0000000
--- a/include/libopencm3/stm32/f1/scb.h
+++ /dev/null
@@ -1,307 +0,0 @@
-/*
- * This file is part of the libopencm3 project.
- *
- * Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
- * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef LIBOPENCM3_SCB_H
-#define LIBOPENCM3_SCB_H
-
-#include <libopencm3/stm32/memorymap.h>
-#include <libopencm3/cm3/common.h>
-
-/* --- SCB: Registers ------------------------------------------------------ */
-
-/* CPUID: CPUID base register */
-#define SCB_CPUID MMIO32(SCB_BASE + 0x00)
-
-/* ICSR: Interrupt Control State Register */
-#define SCB_ICSR MMIO32(SCB_BASE + 0x04)
-
-/* VTOR: Vector Table Offset Register */
-#define SCB_VTOR MMIO32(SCB_BASE + 0x08)
-
-/* AIRCR: Application Interrupt and Reset Control Register */
-#define SCB_AIRCR MMIO32(SCB_BASE + 0x0C)
-
-/* SCR: System Control Register */
-#define SCB_SCR MMIO32(SCB_BASE + 0x10)
-
-/* CCR: Configuration Control Register */
-#define SCB_CCR MMIO32(SCB_BASE + 0x14)
-
-/* SHP: System Handler Priority Registers */
-/* Note: 12 8bit registers */
-#define SCB_SHPR(shpr_id) MMIO8(SCB_BASE + 0x18 + shpr_id)
-#define SCB_SHPR1 MMIO8(SCB_BASE + 0x18 + 1)
-#define SCB_SHPR2 MMIO8(SCB_BASE + 0x18 + 2)
-#define SCB_SHPR3 MMIO8(SCB_BASE + 0x18 + 3)
-
-/* SHCSR: System Handler Control and State Register */
-#define SCB_SHCSR MMIO32(SCB_BASE + 0x24)
-
-/* CFSR: Configurable Fault Status Registers */
-#define SCB_CFSR MMIO32(SCB_BASE + 0x28)
-
-/* HFSR: Hard Fault Status Register */
-#define SCB_HFSR MMIO32(SCB_BASE + 0x2C)
-
-/* DFSR: Debug Fault Status Register */
-#define SCB_DFSR MMIO32(SCB_BASE + 0x30)
-
-/* MMFAR: Memory Manage Fault Address Register */
-#define SCB_MMFAR MMIO32(SCB_BASE + 0x34)
-
-/* BFAR: Bus Fault Address Register */
-#define SCB_BFAR MMIO32(SCB_BASE + 0x38)
-
-/* AFSR: Auxiliary Fault Status Register */
-#define SCB_AFSR MMIO32(SCB_BASE + 0x3C)
-
-/* --- SCB values ---------------------------------------------------------- */
-
-/* --- SCB_CPUID values ---------------------------------------------------- */
-
-/* Implementer[31:24]: Implementer code */
-#define SCP_CPUID_IMPLEMENTER_LSB 24
-/* Variant[23:20]: Variant number */
-#define SCP_CPUID_VARIANT_LSB 20
-/* Constant[19:16]: Reads as 0xF */
-#define SCP_CPUID_CONSTANT_LSB 16
-/* PartNo[15:4]: Part number of the processor */
-#define SCP_CPUID_PARTNO_LSB 4
-/* Revision[3:0]: Revision number */
-#define SCP_CPUID_REVISION_LSB 0
-
-/* --- SCB_ICSR values ----------------------------------------------------- */
-
-/* NMIPENDSET: NMI set-pending bit */
-#define SCB_ICSR_NMIPENDSET (1 << 31)
-/* Bits [30:29]: reserved - must be kept cleared */
-/* PENDSVSET: PendSV set-pending bit */
-#define SCB_ICSR_PENDSVSET (1 << 28)
-/* PENDSVCLR: PendSV clear-pending bit */
-#define SCB_ICSR_PENDSVCLR (1 << 27)
-/* PENDSTSET: SysTick exception set-pending bit */
-#define SCB_ICSR_PENDSTSET (1 << 26)
-/* PENDSTCLR: SysTick exception clear-pending bit */
-#define SCB_ICSR_PENDSTCLR (1 << 25)
-/* Bit 24: reserved - must be kept cleared */
-/* Bit 23: reserved for debug - reads as 0 when not in debug mode */
-/* ISRPENDING: Interrupt pending flag, excluding NMI and Faults */
-#define SCB_ICSR_ISRPENDING (1 << 22)
-/* VECTPENDING[21:12] Pending vector */
-#define SCB_ICSR_VECTPENDING_LSB 12
-/* RETOBASE: Return to base level */
-#define SCB_ICSR_RETOBASE (1 << 11)
-/* Bits [10:9]: reserved - must be kept cleared */
-/* VECTACTIVE[8:0] Active vector */
-#define SCB_ICSR_VECTACTIVE_LSB 0
-
-/* --- SCB_VTOR values ----------------------------------------------------- */
-
-/* Bits [31:30]: reserved - must be kept cleared */
-/* TBLOFF[29:9]: Vector table base offset field */
-#define SCB_VTOR_TBLOFF_LSB 9 /* inconsistent datasheet - LSB could be 11 */
-
-/* --- SCB_AIRCR values ---------------------------------------------------- */
-
-/* VECTKEYSTAT[31:16]/ VECTKEY[31:16] Register key */
-#define SCB_AIRCR_VECTKEYSTAT_LSB 16
-#define SCB_AIRCR_VECTKEY 0x05FA0000
-/* ENDIANESS Data endianness bit */
-#define SCB_AIRCR_ENDIANESS (1 << 15)
-/* Bits [14:11]: reserved - must be kept cleared */
-/* PRIGROUP[10:8]: Interrupt priority grouping field */
-#define SCB_AIRCR_PRIGROUP_GROUP16_NOSUB (0x3 << 8)
-#define SCB_AIRCR_PRIGROUP_GROUP8_SUB2 (0x4 << 8)
-#define SCB_AIRCR_PRIGROUP_GROUP4_SUB4 (0x5 << 8)
-#define SCB_AIRCR_PRIGROUP_GROUP2_SUB8 (0x6 << 8)
-#define SCB_AIRCR_PRIGROUP_NOGROUP_SUB16 (0x7 << 8)
-#define SCB_AIRCR_PRIGROUP_MASK (0x7 << 8)
-#define SCB_AIRCR_PRIGROUP_SHIFT 8
-/* Bits [7:3]: reserved - must be kept cleared */
-/* SYSRESETREQ System reset request */
-#define SCB_AIRCR_SYSRESETREQ (1 << 2)
-/* VECTCLRACTIVE */
-#define SCB_AIRCR_VECTCLRACTIVE (1 << 1)
-/* VECTRESET */
-#define SCB_AIRCR_VECTRESET (1 << 0)
-
-/* --- SCB_SCR values ------------------------------------------------------ */
-
-/* Bits [31:5]: reserved - must be kept cleared */
-/* SEVEONPEND Send Event on Pending bit */
-#define SCB_SCR_SEVEONPEND (1 << 4)
-/* Bit 3: reserved - must be kept cleared */
-/* SLEEPDEEP */
-#define SCB_SCR_SLEEPDEEP (1 << 2)
-/* SLEEPONEXIT */
-#define SCB_SCR_SLEEPONEXIT (1 << 1)
-/* Bit 0: reserved - must be kept cleared */
-
-/* --- SCB_CCR values ------------------------------------------------------ */
-
-/* Bits [31:10]: reserved - must be kept cleared */
-/* STKALIGN */
-#define SCB_CCR_STKALIGN (1 << 9)
-/* BFHFNMIGN */
-#define SCB_CCR_BFHFNMIGN (1 << 8)
-/* Bits [7:5]: reserved - must be kept cleared */
-/* DIV_0_TRP */
-#define SCB_CCR_DIV_0_TRP (1 << 4)
-/* UNALIGN_TRP */
-#define SCB_CCR_UNALIGN_TRP (1 << 3)
-/* Bit 2: reserved - must be kept cleared */
-/* USERSETMPEND */
-#define SCB_CCR_USERSETMPEND (1 << 1)
-/* NONBASETHRDENA */
-#define SCB_CCR_NONBASETHRDENA (1 << 0)
-
-/* --- SCB_SHPR1 values ---------------------------------------------------- */
-
-/* Bits [31:24]: reserved - must be kept cleared */
-/* PRI_6[23:16]: Priority of system handler 6, usage fault */
-#define SCB_SHPR1_PRI_6_LSB 16
-/* PRI_5[15:8]: Priority of system handler 5, bus fault */
-#define SCB_SHPR1_PRI_5_LSB 8
-/* PRI_4[7:0]: Priority of system handler 4, memory management fault */
-#define SCB_SHPR1_PRI_4_LSB 0
-
-/* --- SCB_SHPR2 values ---------------------------------------------------- */
-
-/* PRI_11[31:24]: Priority of system handler 11, SVCall */
-#define SCB_SHPR2_PRI_11_LSB 24
-/* Bits [23:0]: reserved - must be kept cleared */
-
-/* --- SCB_SHPR3 values ---------------------------------------------------- */
-
-/* PRI_15[31:24]: Priority of system handler 15, SysTick exception */
-#define SCB_SHPR3_PRI_15_LSB 24
-/* PRI_14[23:16]: Priority of system handler 14, PendSV */
-#define SCB_SHPR3_PRI_14_LSB 16
-/* Bits [15:0]: reserved - must be kept cleared */
-
-/* --- SCB_SHCSR values ---------------------------------------------------- */
-
-/* Bits [31:19]: reserved - must be kept cleared */
-/* USGFAULTENA: Usage fault enable */
-#define SCB_SHCSR_USGFAULTENA (1 << 18)
-/* BUSFAULTENA: Bus fault enable */
-#define SCB_SHCSR_BUSFAULTENA (1 << 17)
-/* MEMFAULTENA: Memory management fault enable */
-#define SCB_SHCSR_MEMFAULTENA (1 << 16)
-/* SVCALLPENDED: SVC call pending */
-#define SCB_SHCSR_SVCALLPENDED (1 << 15)
-/* BUSFAULTPENDED: Bus fault exception pending */
-#define SCB_SHCSR_BUSFAULTPENDED (1 << 14)
-/* MEMFAULTPENDED: Memory management fault exception pending */
-#define SCB_SHCSR_MEMFAULTPENDED (1 << 13)
-/* USGFAULTPENDED: Usage fault exception pending */
-#define SCB_SHCSR_USGFAULTPENDED (1 << 12)
-/* SYSTICKACT: SysTick exception active */
-#define SCB_SHCSR_SYSTICKACT (1 << 11)
-/* PENDSVACT: PendSV exception active */
-#define SCB_SHCSR_PENDSVACT (1 << 10)
-/* Bit 9: reserved - must be kept cleared */
-/* MONITORACT: Debug monitor active */
-#define SCB_SHCSR_MONITORACT (1 << 8)
-/* SVCALLACT: SVC call active */
-#define SCB_SHCSR_SVCALLACT (1 << 7)
-/* Bits [6:4]: reserved - must be kept cleared */
-/* USGFAULTACT: Usage fault exception active */
-#define SCB_SHCSR_USGFAULTACT (1 << 3)
-/* Bit 2: reserved - must be kept cleared */
-/* BUSFAULTACT: Bus fault exception active */
-#define SCB_SHCSR_BUSFAULTACT (1 << 1)
-/* MEMFAULTACT: Memory management fault exception active */
-#define SCB_SHCSR_MEMFAULTACT (1 << 0)
-
-/* --- SCB_CFSR values ----------------------------------------------------- */
-
-/* Bits [31:26]: reserved - must be kept cleared */
-/* DIVBYZERO: Divide by zero usage fault */
-#define SCB_CFSR_DIVBYZERO (1 << 25)
-/* UNALIGNED: Unaligned access usage fault */
-#define SCB_CFSR_UNALIGNED (1 << 24)
-/* Bits [23:20]: reserved - must be kept cleared */
-/* NOCP: No coprocessor usage fault */
-#define SCB_CFSR_NOCP (1 << 19)
-/* INVPC: Invalid PC load usage fault */
-#define SCB_CFSR_INVPC (1 << 18)
-/* INVSTATE: Invalid state usage fault */
-#define SCB_CFSR_INVSTATE (1 << 17)
-/* UNDEFINSTR: Undefined instruction usage fault */
-#define SCB_CFSR_UNDEFINSTR (1 << 16)
-/* BFARVALID: Bus Fault Address Register (BFAR) valid flag */
-#define SCB_CFSR_BFARVALID (1 << 15)
-/* Bits [14:13]: reserved - must be kept cleared */
-/* STKERR: Bus fault on stacking for exception entry */
-#define SCB_CFSR_STKERR (1 << 12)
-/* UNSTKERR: Bus fault on unstacking for a return from exception */
-#define SCB_CFSR_UNSTKERR (1 << 11)
-/* IMPRECISERR: Imprecise data bus error */
-#define SCB_CFSR_IMPRECISERR (1 << 10)
-/* PRECISERR: Precise data bus error */
-#define SCB_CFSR_PRECISERR (1 << 9)
-/* IBUSERR: Instruction bus error */
-#define SCB_CFSR_IBUSERR (1 << 8)
-/* MMARVALID: Memory Management Fault Address Register (MMAR) valid flag */
-#define SCB_CFSR_MMARVALID (1 << 7)
-/* Bits [6:5]: reserved - must be kept cleared */
-/* MSTKERR: Memory manager fault on stacking for exception entry */
-#define SCB_CFSR_MSTKERR (1 << 4)
-/* MUNSTKERR: Memory manager fault on unstacking for a return from exception */
-#define SCB_CFSR_MUNSTKERR (1 << 3)
-/* Bit 2: reserved - must be kept cleared */
-/* DACCVIOL: Data access violation flag */
-#define SCB_CFSR_DACCVIOL (1 << 1)
-/* IACCVIOL: Instruction access violation flag */
-#define SCB_CFSR_IACCVIOL (1 << 0)
-
-/* --- SCB_HFSR values ----------------------------------------------------- */
-
-/* DEBUG_VT: reserved for debug use */
-#define SCB_HFSR_DEBUG_VT (1 << 31)
-/* FORCED: Forced hard fault */
-#define SCB_HFSR_FORCED (1 << 30)
-/* Bits [29:2]: reserved - must be kept cleared */
-/* VECTTBL: Vector table hard fault */
-#define SCB_HFSR_VECTTBL (1 << 1)
-/* Bit 0: reserved - must be kept cleared */
-
-/* --- SCB_MMFAR values ---------------------------------------------------- */
-
-/* MMFAR [31:0]: Memory management fault address */
-
-/* --- SCB_BFAR values ----------------------------------------------------- */
-
-/* BFAR [31:0]: Bus fault address */
-
-/* --- SCB functions ------------------------------------------------------- */
-
-BEGIN_DECLS
-
-void scb_reset_core(void);
-void scb_reset_system(void);
-void scb_set_priority_grouping(u32 prigroup);
-
-/* TODO: */
-
-END_DECLS
-
-#endif
diff --git a/include/libopencm3/stm32/f2/irq.yaml b/include/libopencm3/stm32/f2/irq.yaml
new file mode 100644
index 0000000..c3600b3
--- /dev/null
+++ b/include/libopencm3/stm32/f2/irq.yaml
@@ -0,0 +1,85 @@
+includeguard: LIBOPENCM3_STM32_F2_NVIC_H
+partname_humanreadable: STM32 F2 series
+partname_doxygen: STM32F2
+irqs:
+ - nvic_wwdg
+ - pvd
+ - tamp_stamp
+ - rtc_wkup
+ - flash
+ - rcc
+ - exti0
+ - exti1
+ - exti2
+ - exti3
+ - exti4
+ - dma1_stream0
+ - dma1_stream1
+ - dma1_stream2
+ - dma1_stream3
+ - dma1_stream4
+ - dma1_stream5
+ - dma1_stream6
+ - adc
+ - can1_tx
+ - can1_rx0
+ - can1_rx1
+ - can1_sce
+ - exti9_5
+ - tim1_brk_tim9
+ - tim1_up_tim10
+ - tim1_trg_com_tim11
+ - tim1_cc
+ - tim2
+ - tim3
+ - tim4
+ - i2c1_ev
+ - i2c1_er
+ - i2c2_ev
+ - i2c2_er
+ - spi1
+ - spi2
+ - usart1
+ - usart2
+ - usart3
+ - exti15_10
+ - rtc_alarm
+ - usb_fs_wkup
+ - tim8_brk_tim12
+ - tim8_up_tim13
+ - tim8_trg_com_tim14
+ - tim8_cc
+ - dma1_stream7
+ - fsmc
+ - sdio
+ - tim5
+ - spi3
+ - uart4
+ - uart5
+ - tim6_dac
+ - tim7
+ - dma2_stream0
+ - dma2_stream1
+ - dma2_stream2
+ - dma2_stream3
+ - dma2_stream4
+ - eth
+ - eth_wkup
+ - can2_tx
+ - can2_rx0
+ - can2_rx1
+ - can2_sce
+ - otg_fs
+ - dma2_stream5
+ - dma2_stream6
+ - dma2_stream7
+ - usart6
+ - i2c3_ev
+ - i2c3_er
+ - otg_hs_ep1_out
+ - otg_hs_ep1_in
+ - otg_hs_wkup
+ - otg_hs
+ - dcmi
+ - cryp
+ - hash_rng
diff --git a/include/libopencm3/stm32/f2/nvic_f2.h b/include/libopencm3/stm32/f2/nvic_f2.h
deleted file mode 100644
index 2bf2997..0000000
--- a/include/libopencm3/stm32/f2/nvic_f2.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * This file is part of the libopencm3 project.
- *
- * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef LIBOPENCM3_NVIC_F2_H
-#define LIBOPENCM3_NVIC_F2_H
-
-/* --- IRQ channel numbers-------------------------------------------------- */
-
-/* Note: These F2 specific user interrupt definitions supplement the
- * general NVIC definitions in ../nvic.h
- */
-
-/* User Interrupts */
-#define NVIC_NVIC_WWDG_IRQ 0
-#define NVIC_PVD_IRQ 1
-#define NVIC_TAMP_STAMP_IRQ 2
-#define NVIC_RTC_WKUP_IRQ 3
-#define NVIC_FLASH_IRQ 4
-#define NVIC_RCC_IRQ 5
-#define NVIC_EXTI0_IRQ 6
-#define NVIC_EXTI1_IRQ 7
-#define NVIC_EXTI2_IRQ 8
-#define NVIC_EXTI3_IRQ 9
-#define NVIC_EXTI4_IRQ 10
-#define NVIC_DMA1_STREAM0_IRQ 11
-#define NVIC_DMA1_STREAM1_IRQ 12
-#define NVIC_DMA1_STREAM2_IRQ 13
-#define NVIC_DMA1_STREAM3_IRQ 14
-#define NVIC_DMA1_STREAM4_IRQ 15
-#define NVIC_DMA1_STREAM5_IRQ 16
-#define NVIC_DMA1_STREAM6_IRQ 17
-#define NVIC_ADC_IRQ 18
-#define NVIC_CAN1_TX_IRQ 19
-#define NVIC_CAN1_RX0_IRQ 20
-#define NVIC_CAN1_RX1_IRQ 21
-#define NVIC_CAN1_SCE_IRQ 22
-#define NVIC_EXTI9_5_IRQ 23
-#define NVIC_TIM1_BRK_TIM9_IRQ 24
-#define NVIC_TIM1_UP_TIM10_IRQ 25
-#define NVIC_TIM1_TRG_COM_TIM11_IRQ 26
-#define NVIC_TIM1_CC_IRQ 27
-#define NVIC_TIM2_IRQ 28
-#define NVIC_TIM3_IRQ 29
-#define NVIC_TIM4_IRQ 30
-#define NVIC_I2C1_EV_IRQ 31
-#define NVIC_I2C1_ER_IRQ 32
-#define NVIC_I2C2_EV_IRQ 33
-#define NVIC_I2C2_ER_IRQ 34
-#define NVIC_SPI1_IRQ 35
-#define NVIC_SPI2_IRQ 36
-#define NVIC_USART1_IRQ 37
-#define NVIC_USART2_IRQ 38
-#define NVIC_USART3_IRQ 39
-#define NVIC_EXTI15_10_IRQ 40
-#define NVIC_RTC_ALARM_IRQ 41
-#define NVIC_USB_FS_WKUP_IRQ 42
-#define NVIC_TIM8_BRK_TIM12_IRQ 43
-#define NVIC_TIM8_UP_TIM13_IRQ 44
-#define NVIC_TIM8_TRG_COM_TIM14_IRQ 45
-#define NVIC_TIM8_CC_IRQ 46
-#define NVIC_DMA1_STREAM7_IRQ 47
-#define NVIC_FSMC_IRQ 48
-#define NVIC_SDIO_IRQ 49
-#define NVIC_TIM5_IRQ 50
-#define NVIC_SPI3_IRQ 51
-#define NVIC_UART4_IRQ 52
-#define NVIC_UART5_IRQ 53
-#define NVIC_TIM6_DAC_IRQ 54
-#define NVIC_TIM7_IRQ 55
-#define NVIC_DMA2_STREAM0_IRQ 56
-#define NVIC_DMA2_STREAM1_IRQ 57
-#define NVIC_DMA2_STREAM2_IRQ 58
-#define NVIC_DMA2_STREAM3_IRQ 59
-#define NVIC_DMA2_STREAM4_IRQ 60
-#define NVIC_ETH_IRQ 61
-#define NVIC_ETH_WKUP_IRQ 62
-#define NVIC_CAN2_TX_IRQ 63
-#define NVIC_CAN2_RX0_IRQ 64
-#define NVIC_CAN2_RX1_IRQ 65
-#define NVIC_CAN2_SCE_IRQ 66
-#define NVIC_OTG_FS_IRQ 67
-#define NVIC_DMA2_STREAM5_IRQ 68
-#define NVIC_DMA2_STREAM6_IRQ 69
-#define NVIC_DMA2_STREAM7_IRQ 70
-#define NVIC_USART6_IRQ 71
-#define NVIC_I2C3_EV_IRQ 72
-#define NVIC_I2C3_ER_IRQ 73
-#define NVIC_OTG_HS_EP1_OUT_IRQ 74
-#define NVIC_OTG_HS_EP1_IN_IRQ 75
-#define NVIC_OTG_HS_WKUP_IRQ 76
-#define NVIC_OTG_HS_IRQ 77
-#define NVIC_DCMI_IRQ 78
-#define NVIC_CRYP_IRQ 79
-#define NVIC_HASH_RNG_IRQ 80
-
-#endif
diff --git a/include/libopencm3/stm32/f2/scb.h b/include/libopencm3/stm32/f2/scb.h
deleted file mode 100644
index 181aa7a..0000000
--- a/include/libopencm3/stm32/f2/scb.h
+++ /dev/null
@@ -1,307 +0,0 @@
-/*
- * This file is part of the libopencm3 project.
- *
- * Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
- * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef LIBOPENCM3_SCB_H
-#define LIBOPENCM3_SCB_H
-
-#include <libopencm3/stm32/memorymap.h>
-#include <libopencm3/cm3/common.h>
-
-/* --- SCB: Registers ------------------------------------------------------ */
-
-/* CPUID: CPUID base register */
-#define SCB_CPUID MMIO32(SCB_BASE + 0x00)
-
-/* ICSR: Interrupt Control State Register */
-#define SCB_ICSR MMIO32(SCB_BASE + 0x04)
-
-/* VTOR: Vector Table Offset Register */
-#define SCB_VTOR MMIO32(SCB_BASE + 0x08)
-
-/* AIRCR: Application Interrupt and Reset Control Register */
-#define SCB_AIRCR MMIO32(SCB_BASE + 0x0C)
-
-/* SCR: System Control Register */
-#define SCB_SCR MMIO32(SCB_BASE + 0x10)
-
-/* CCR: Configuration Control Register */
-#define SCB_CCR MMIO32(SCB_BASE + 0x14)
-
-/* SHP: System Handler Priority Registers */
-/* Note: 12 8bit registers */
-#define SCB_SHPR(shpr_id) MMIO8(SCB_BASE + 0x18 + shpr_id)
-#define SCB_SHPR1 MMIO8(SCB_BASE + 0x18 + 1)
-#define SCB_SHPR2 MMIO8(SCB_BASE + 0x18 + 2)
-#define SCB_SHPR3 MMIO8(SCB_BASE + 0x18 + 3)
-
-/* SHCSR: System Handler Control and State Register */
-#define SCB_SHCSR MMIO32(SCB_BASE + 0x24)
-
-/* CFSR: Configurable Fault Status Registers */
-#define SCB_CFSR MMIO32(SCB_BASE + 0x28)
-
-/* HFSR: Hard Fault Status Register */
-#define SCB_HFSR MMIO32(SCB_BASE + 0x2C)
-
-/* DFSR: Debug Fault Status Register */
-#define SCB_DFSR MMIO32(SCB_BASE + 0x30)
-
-/* MMFAR: Memory Manage Fault Address Register */
-#define SCB_MMFAR MMIO32(SCB_BASE + 0x34)
-
-/* BFAR: Bus Fault Address Register */
-#define SCB_BFAR MMIO32(SCB_BASE + 0x38)
-
-/* AFSR: Auxiliary Fault Status Register */
-#define SCB_AFSR MMIO32(SCB_BASE + 0x3C)
-
-/* --- SCB values ---------------------------------------------------------- */
-
-/* --- SCB_CPUID values ---------------------------------------------------- */
-
-/* Implementer[31:24]: Implementer code */
-#define SCP_CPUID_IMPLEMENTER_LSB 24
-/* Variant[23:20]: Variant number */
-#define SCP_CPUID_VARIANT_LSB 20
-/* Constant[19:16]: Reads as 0xF */
-#define SCP_CPUID_CONSTANT_LSB 16
-/* PartNo[15:4]: Part number of the processor */
-#define SCP_CPUID_PARTNO_LSB 4
-/* Revision[3:0]: Revision number */
-#define SCP_CPUID_REVISION_LSB 0
-
-/* --- SCB_ICSR values ----------------------------------------------------- */
-
-/* NMIPENDSET: NMI set-pending bit */
-#define SCB_ICSR_NMIPENDSET (1 << 31)
-/* Bits [30:29]: reserved - must be kept cleared */
-/* PENDSVSET: PendSV set-pending bit */
-#define SCB_ICSR_PENDSVSET (1 << 28)
-/* PENDSVCLR: PendSV clear-pending bit */
-#define SCB_ICSR_PENDSVCLR (1 << 27)
-/* PENDSTSET: SysTick exception set-pending bit */
-#define SCB_ICSR_PENDSTSET (1 << 26)
-/* PENDSTCLR: SysTick exception clear-pending bit */
-#define SCB_ICSR_PENDSTCLR (1 << 25)
-/* Bit 24: reserved - must be kept cleared */
-/* Bit 23: reserved for debug - reads as 0 when not in debug mode */
-/* ISRPENDING: Interrupt pending flag, excluding NMI and Faults */
-#define SCB_ICSR_ISRPENDING (1 << 22)
-/* VECTPENDING[21:12] Pending vector */
-#define SCB_ICSR_VECTPENDING_LSB 12
-/* RETOBASE: Return to base level */
-#define SCB_ICSR_RETOBASE (1 << 11)
-/* Bits [10:9]: reserved - must be kept cleared */
-/* VECTACTIVE[8:0] Active vector */
-#define SCB_ICSR_VECTACTIVE_LSB 0
-
-/* --- SCB_VTOR values ----------------------------------------------------- */
-
-/* Bits [31:30]: reserved - must be kept cleared */
-/* TBLOFF[29:9]: Vector table base offset field */
-#define SCB_VTOR_TBLOFF_LSB 9 /* inconsistent datasheet - LSB could be 11 */
-
-/* --- SCB_AIRCR values ---------------------------------------------------- */
-
-/* VECTKEYSTAT[31:16]/ VECTKEY[31:16] Register key */
-#define SCB_AIRCR_VECTKEYSTAT_LSB 16
-#define SCB_AIRCR_VECTKEY 0x05FA0000
-/* ENDIANESS Data endianness bit */
-#define SCB_AIRCR_ENDIANESS (1 << 15)
-/* Bits [14:11]: reserved - must be kept cleared */
-/* PRIGROUP[10:8]: Interrupt priority grouping field */
-#define SCB_AIRCR_PRIGROUP_GROUP16_NOSUB (0x3 << 8)
-#define SCB_AIRCR_PRIGROUP_GROUP8_SUB2 (0x4 << 8)
-#define SCB_AIRCR_PRIGROUP_GROUP4_SUB4 (0x5 << 8)
-#define SCB_AIRCR_PRIGROUP_GROUP2_SUB8 (0x6 << 8)
-#define SCB_AIRCR_PRIGROUP_NOGROUP_SUB16 (0x7 << 8)
-#define SCB_AIRCR_PRIGROUP_MASK (0x7 << 8)
-#define SCB_AIRCR_PRIGROUP_SHIFT 8
-/* Bits [7:3]: reserved - must be kept cleared */
-/* SYSRESETREQ System reset request */
-#define SCB_AIRCR_SYSRESETREQ (1 << 2)
-/* VECTCLRACTIVE */
-#define SCB_AIRCR_VECTCLRACTIVE (1 << 1)
-/* VECTRESET */
-#define SCB_AIRCR_VECTRESET (1 << 0)
-
-/* --- SCB_SCR values ------------------------------------------------------ */
-
-/* Bits [31:5]: reserved - must be kept cleared */
-/* SEVEONPEND Send Event on Pending bit */
-#define SCB_SCR_SEVEONPEND (1 << 4)
-/* Bit 3: reserved - must be kept cleared */
-/* SLEEPDEEP */
-#define SCB_SCR_SLEEPDEEP (1 << 2)
-/* SLEEPONEXIT */
-#define SCB_SCR_SLEEPONEXIT (1 << 1)
-/* Bit 0: reserved - must be kept cleared */
-
-/* --- SCB_CCR values ------------------------------------------------------ */
-
-/* Bits [31:10]: reserved - must be kept cleared */
-/* STKALIGN */
-#define SCB_CCR_STKALIGN (1 << 9)
-/* BFHFNMIGN */
-#define SCB_CCR_BFHFNMIGN (1 << 8)
-/* Bits [7:5]: reserved - must be kept cleared */
-/* DIV_0_TRP */
-#define SCB_CCR_DIV_0_TRP (1 << 4)
-/* UNALIGN_TRP */
-#define SCB_CCR_UNALIGN_TRP (1 << 3)
-/* Bit 2: reserved - must be kept cleared */
-/* USERSETMPEND */
-#define SCB_CCR_USERSETMPEND (1 << 1)
-/* NONBASETHRDENA */
-#define SCB_CCR_NONBASETHRDENA (1 << 0)
-
-/* --- SCB_SHPR1 values ---------------------------------------------------- */
-
-/* Bits [31:24]: reserved - must be kept cleared */
-/* PRI_6[23:16]: Priority of system handler 6, usage fault */
-#define SCB_SHPR1_PRI_6_LSB 16
-/* PRI_5[15:8]: Priority of system handler 5, bus fault */
-#define SCB_SHPR1_PRI_5_LSB 8
-/* PRI_4[7:0]: Priority of system handler 4, memory management fault */
-#define SCB_SHPR1_PRI_4_LSB 0
-
-/* --- SCB_SHPR2 values ---------------------------------------------------- */
-
-/* PRI_11[31:24]: Priority of system handler 11, SVCall */
-#define SCB_SHPR2_PRI_11_LSB 24
-/* Bits [23:0]: reserved - must be kept cleared */
-
-/* --- SCB_SHPR3 values ---------------------------------------------------- */
-
-/* PRI_15[31:24]: Priority of system handler 15, SysTick exception */
-#define SCB_SHPR3_PRI_15_LSB 24
-/* PRI_14[23:16]: Priority of system handler 14, PendSV */
-#define SCB_SHPR3_PRI_14_LSB 16
-/* Bits [15:0]: reserved - must be kept cleared */
-
-/* --- SCB_SHCSR values ---------------------------------------------------- */
-
-/* Bits [31:19]: reserved - must be kept cleared */
-/* USGFAULTENA: Usage fault enable */
-#define SCB_SHCSR_USGFAULTENA (1 << 18)
-/* BUSFAULTENA: Bus fault enable */
-#define SCB_SHCSR_BUSFAULTENA (1 << 17)
-/* MEMFAULTENA: Memory management fault enable */
-#define SCB_SHCSR_MEMFAULTENA (1 << 16)
-/* SVCALLPENDED: SVC call pending */
-#define SCB_SHCSR_SVCALLPENDED (1 << 15)
-/* BUSFAULTPENDED: Bus fault exception pending */
-#define SCB_SHCSR_BUSFAULTPENDED (1 << 14)
-/* MEMFAULTPENDED: Memory management fault exception pending */
-#define SCB_SHCSR_MEMFAULTPENDED (1 << 13)
-/* USGFAULTPENDED: Usage fault exception pending */
-#define SCB_SHCSR_USGFAULTPENDED (1 << 12)
-/* SYSTICKACT: SysTick exception active */
-#define SCB_SHCSR_SYSTICKACT (1 << 11)
-/* PENDSVACT: PendSV exception active */
-#define SCB_SHCSR_PENDSVACT (1 << 10)
-/* Bit 9: reserved - must be kept cleared */
-/* MONITORACT: Debug monitor active */
-#define SCB_SHCSR_MONITORACT (1 << 8)
-/* SVCALLACT: SVC call active */
-#define SCB_SHCSR_SVCALLACT (1 << 7)
-/* Bits [6:4]: reserved - must be kept cleared */
-/* USGFAULTACT: Usage fault exception active */
-#define SCB_SHCSR_USGFAULTACT (1 << 3)
-/* Bit 2: reserved - must be kept cleared */
-/* BUSFAULTACT: Bus fault exception active */
-#define SCB_SHCSR_BUSFAULTACT (1 << 1)
-/* MEMFAULTACT: Memory management fault exception active */
-#define SCB_SHCSR_MEMFAULTACT (1 << 0)
-
-/* --- SCB_CFSR values ----------------------------------------------------- */
-
-/* Bits [31:26]: reserved - must be kept cleared */
-/* DIVBYZERO: Divide by zero usage fault */
-#define SCB_CFSR_DIVBYZERO (1 << 25)
-/* UNALIGNED: Unaligned access usage fault */
-#define SCB_CFSR_UNALIGNED (1 << 24)
-/* Bits [23:20]: reserved - must be kept cleared */
-/* NOCP: No coprocessor usage fault */
-#define SCB_CFSR_NOCP (1 << 19)
-/* INVPC: Invalid PC load usage fault */
-#define SCB_CFSR_INVPC (1 << 18)
-/* INVSTATE: Invalid state usage fault */
-#define SCB_CFSR_INVSTATE (1 << 17)
-/* UNDEFINSTR: Undefined instruction usage fault */
-#define SCB_CFSR_UNDEFINSTR (1 << 16)
-/* BFARVALID: Bus Fault Address Register (BFAR) valid flag */
-#define SCB_CFSR_BFARVALID (1 << 15)
-/* Bits [14:13]: reserved - must be kept cleared */
-/* STKERR: Bus fault on stacking for exception entry */
-#define SCB_CFSR_STKERR (1 << 12)
-/* UNSTKERR: Bus fault on unstacking for a return from exception */
-#define SCB_CFSR_UNSTKERR (1 << 11)
-/* IMPRECISERR: Imprecise data bus error */
-#define SCB_CFSR_IMPRECISERR (1 << 10)
-/* PRECISERR: Precise data bus error */
-#define SCB_CFSR_PRECISERR (1 << 9)
-/* IBUSERR: Instruction bus error */
-#define SCB_CFSR_IBUSERR (1 << 8)
-/* MMARVALID: Memory Management Fault Address Register (MMAR) valid flag */
-#define SCB_CFSR_MMARVALID (1 << 7)
-/* Bits [6:5]: reserved - must be kept cleared */
-/* MSTKERR: Memory manager fault on stacking for exception entry */
-#define SCB_CFSR_MSTKERR (1 << 4)
-/* MUNSTKERR: Memory manager fault on unstacking for a return from exception */
-#define SCB_CFSR_MUNSTKERR (1 << 3)
-/* Bit 2: reserved - must be kept cleared */
-/* DACCVIOL: Data access violation flag */
-#define SCB_CFSR_DACCVIOL (1 << 1)
-/* IACCVIOL: Instruction access violation flag */
-#define SCB_CFSR_IACCVIOL (1 << 0)
-
-/* --- SCB_HFSR values ----------------------------------------------------- */
-
-/* DEBUG_VT: reserved for debug use */
-#define SCB_HFSR_DEBUG_VT (1 << 31)
-/* FORCED: Forced hard fault */
-#define SCB_HFSR_FORCED (1 << 30)
-/* Bits [29:2]: reserved - must be kept cleared */
-/* VECTTBL: Vector table hard fault */
-#define SCB_HFSR_VECTTBL (1 << 1)
-/* Bit 0: reserved - must be kept cleared */
-
-/* --- SCB_MMFAR values ---------------------------------------------------- */
-
-/* MMFAR [31:0]: Memory management fault address */
-
-/* --- SCB_BFAR values ----------------------------------------------------- */
-
-/* BFAR [31:0]: Bus fault address */
-
-/* --- SCB functions ------------------------------------------------------- */
-
-BEGIN_DECLS
-
-void scb_reset_core(void);
-void scb_reset_system(void);
-void scb_set_priority_grouping(u32 prigroup);
-
-/* TODO: */
-
-END_DECLS
-
-#endif
diff --git a/include/libopencm3/stm32/f4/adc.h b/include/libopencm3/stm32/f4/adc.h
new file mode 100644
index 0000000..272c4c2
--- /dev/null
+++ b/include/libopencm3/stm32/f4/adc.h
@@ -0,0 +1,873 @@
+/** @defgroup STM32F4xx_adc_defines ADC Defines
+
+@brief <b>Defined Constants and Types for the STM32F4xx Analog to Digital Converters</b>
+
+@ingroup STM32F4xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2012 Matthew Lai <m@matthewlai.ca>
+@author @htmlonly &copy; @endhtmlonly 2009 Edward Cheeseman <evbuilder@users.sourceforge.net>
+
+@date 31 August 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Matthew Lai <m@matthewlai.ca>
+ * Copyright (C) 2009 Edward Cheeseman <evbuilder@users.sourceforge.net>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_ADC_H
+#define LIBOPENCM3_ADC_H
+
+#include <libopencm3/stm32/f4/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/* --- Convenience macros -------------------------------------------------- */
+
+/* ADC port base addresses (for convenience) */
+/****************************************************************************/
+/** @defgroup adc_reg_base ADC register base addresses
+@ingroup STM32F4xx_adc_defines
+
+@{*/
+#define ADC1 ADC1_BASE
+#define ADC2 ADC2_BASE
+#define ADC3 ADC3_BASE
+/**@}*/
+
+/* --- ADC registers ------------------------------------------------------- */
+
+/* ADC status register (ADC_SR) */
+#define ADC_SR(block) MMIO32(block + 0x00)
+#define ADC1_SR ADC_SR(ADC1)
+#define ADC2_SR ADC_SR(ADC2)
+#define ADC3_SR ADC_SR(ADC3)
+
+/* ADC control register 1 (ADC_CR1) */
+#define ADC_CR1(block) MMIO32(block + 0x04)
+#define ADC1_CR1 ADC_CR1(ADC1)
+#define ADC2_CR1 ADC_CR1(ADC2)
+#define ADC3_CR1 ADC_CR1(ADC3)
+
+/* ADC control register 2 (ADC_CR2) */
+#define ADC_CR2(block) MMIO32(block + 0x08)
+#define ADC1_CR2 ADC_CR2(ADC1)
+#define ADC2_CR2 ADC_CR2(ADC2)
+#define ADC3_CR2 ADC_CR2(ADC3)
+
+/* ADC sample time register 1 (ADC_SMPR1) */
+#define ADC_SMPR1(block) MMIO32(block + 0x0c)
+#define ADC1_SMPR1 ADC_SMPR1(ADC1)
+#define ADC2_SMPR1 ADC_SMPR1(ADC2)
+#define ADC3_SMPR1 ADC_SMPR1(ADC3)
+
+/* ADC sample time register 2 (ADC_SMPR2) */
+#define ADC_SMPR2(block) MMIO32(block + 0x10)
+#define ADC1_SMPR2 ADC_SMPR2(ADC1)
+#define ADC2_SMPR2 ADC_SMPR2(ADC2)
+#define ADC3_SMPR2 ADC_SMPR2(ADC3)
+
+/* ADC injected channel data offset register x (ADC_JOFRx) (x=1..4) */
+#define ADC_JOFR1(block) MMIO32(block + 0x14)
+#define ADC_JOFR2(block) MMIO32(block + 0x18)
+#define ADC_JOFR3(block) MMIO32(block + 0x1c)
+#define ADC_JOFR4(block) MMIO32(block + 0x20)
+#define ADC1_JOFR1 ADC_JOFR1(ADC1)
+#define ADC2_JOFR1 ADC_JOFR1(ADC2)
+#define ADC3_JOFR1 ADC_JOFR1(ADC3)
+#define ADC1_JOFR2 ADC_JOFR2(ADC1)
+#define ADC2_JOFR2 ADC_JOFR2(ADC2)
+#define ADC3_JOFR2 ADC_JOFR2(ADC3)
+#define ADC1_JOFR3 ADC_JOFR3(ADC1)
+#define ADC2_JOFR3 ADC_JOFR3(ADC2)
+#define ADC3_JOFR3 ADC_JOFR3(ADC3)
+#define ADC1_JOFR4 ADC_JOFR4(ADC1)
+#define ADC2_JOFR4 ADC_JOFR4(ADC2)
+#define ADC3_JOFR4 ADC_JOFR4(ADC3)
+
+/* ADC watchdog high threshold register (ADC_HTR) */
+#define ADC_HTR(block) MMIO32(block + 0x24)
+#define ADC1_HTR ADC_HTR(ADC1)
+#define ADC2_HTR ADC_HTR(ADC2)
+#define ADC3_HTR ADC_HTR(ADC3)
+
+/* ADC watchdog low threshold register (ADC_LTR) */
+#define ADC_LTR(block) MMIO32(block + 0x28)
+#define ADC1_LTR ADC_LTR(ADC1_BASE)
+#define ADC2_LTR ADC_LTR(ADC2_BASE)
+#define ADC3_LTR ADC_LTR(ADC3_BASE)
+
+/* ADC regular sequence register 1 (ADC_SQR1) */
+#define ADC_SQR1(block) MMIO32(block + 0x2c)
+#define ADC1_SQR1 ADC_SQR1(ADC1)
+#define ADC2_SQR1 ADC_SQR1(ADC2)
+#define ADC3_SQR1 ADC_SQR1(ADC3)
+
+/* ADC regular sequence register 2 (ADC_SQR2) */
+#define ADC_SQR2(block) MMIO32(block + 0x30)
+#define ADC1_SQR2 ADC_SQR2(ADC1)
+#define ADC2_SQR2 ADC_SQR2(ADC2)
+#define ADC3_SQR2 ADC_SQR2(ADC3)
+
+/* ADC regular sequence register 3 (ADC_SQR3) */
+#define ADC_SQR3(block) MMIO32(block + 0x34)
+#define ADC1_SQR3 ADC_SQR3(ADC1)
+#define ADC2_SQR3 ADC_SQR3(ADC2)
+#define ADC3_SQR3 ADC_SQR3(ADC3)
+
+/* ADC injected sequence register (ADC_JSQR) */
+#define ADC_JSQR(block) MMIO32(block + 0x38)
+#define ADC1_JSQR ADC_JSQR(ADC1_BASE)
+#define ADC2_JSQR ADC_JSQR(ADC2_BASE)
+#define ADC3_JSQR ADC_JSQR(ADC3_BASE)
+
+/* ADC injected data register x (ADC_JDRx) (x=1..4) */
+#define ADC_JDR1(block) MMIO32(block + 0x3c)
+#define ADC_JDR2(block) MMIO32(block + 0x40)
+#define ADC_JDR3(block) MMIO32(block + 0x44)
+#define ADC_JDR4(block) MMIO32(block + 0x48)
+#define ADC1_JDR1 ADC_JDR1(ADC1)
+#define ADC2_JDR1 ADC_JDR1(ADC2)
+#define ADC3_JDR1 ADC_JDR1(ADC3)
+#define ADC1_JDR2 ADC_JDR2(ADC1)
+#define ADC2_JDR2 ADC_JDR2(ADC2)
+#define ADC3_JDR2 ADC_JDR2(ADC3)
+#define ADC1_JDR3 ADC_JDR3(ADC1)
+#define ADC2_JDR3 ADC_JDR3(ADC2)
+#define ADC3_JDR3 ADC_JDR3(ADC3)
+#define ADC1_JDR4 ADC_JDR4(ADC1)
+#define ADC2_JDR4 ADC_JDR4(ADC2)
+#define ADC3_JDR4 ADC_JDR4(ADC3)
+
+/* ADC regular data register (ADC_DR) */
+#define ADC_DR(block) MMIO32(block + 0x4c)
+#define ADC1_DR ADC_DR(ADC1)
+#define ADC2_DR ADC_DR(ADC2)
+#define ADC3_DR ADC_DR(ADC3)
+
+/* ADC common (shared) registers */
+#define ADC_COMMON_REGISTERS_BASE (ADC1_BASE+0x300)
+#define ADC_CSR MMIO32(ADC_COMMON_REGISTERS_BASE + 0x0)
+#define ADC_CCR MMIO32(ADC_COMMON_REGISTERS_BASE + 0x4)
+#define ADC_CDR MMIO32(ADC_COMMON_REGISTERS_BASE + 0x8)
+
+/* --- ADC Channels ------------------------------------------------------- */
+
+/****************************************************************************/
+/** @defgroup adc_channel ADC Channel Numbers
+@ingroup STM32F4xx_adc_defines
+
+@{*/
+#define ADC_CHANNEL0 0x00
+#define ADC_CHANNEL1 0x01
+#define ADC_CHANNEL2 0x02
+#define ADC_CHANNEL3 0x03
+#define ADC_CHANNEL4 0x04
+#define ADC_CHANNEL5 0x05
+#define ADC_CHANNEL6 0x06
+#define ADC_CHANNEL7 0x07
+#define ADC_CHANNEL8 0x08
+#define ADC_CHANNEL9 0x09
+#define ADC_CHANNEL10 0x0A
+#define ADC_CHANNEL11 0x0B
+#define ADC_CHANNEL12 0x0C
+#define ADC_CHANNEL13 0x0D
+#define ADC_CHANNEL14 0x0E
+#define ADC_CHANNEL15 0x0F
+#define ADC_CHANNEL16 0x10
+#define ADC_CHANNEL17 0x11
+#define ADC_CHANNEL18 0x12
+/**@}*/
+#define ADC_MASK 0x1F
+#define ADC_SHIFT 0
+
+/* --- ADC_SR values ------------------------------------------------------- */
+
+#define ADC_SR_OVR (1 << 5)
+#define ADC_SR_STRT (1 << 4)
+#define ADC_SR_JSTRT (1 << 3)
+#define ADC_SR_JEOC (1 << 2)
+#define ADC_SR_EOC (1 << 1)
+#define ADC_SR_AWD (1 << 0)
+
+/* --- ADC_CR1 values specific to STM32F2,4------------------------------------ */
+
+/* OVRIE: Overrun interrupt enable */
+#define ADC_CR1_OVRIE (1 << 26)
+
+/* RES[1:0]: Resolution */
+/****************************************************************************/
+/** @defgroup adc_cr1_res ADC Resolution.
+@ingroup STM32F4xx_adc_defines
+
+@{*/
+#define ADC_CR1_RES_12BIT (0x0 << 24)
+#define ADC_CR1_RES_10BIT (0x1 << 24)
+#define ADC_CR1_RES_8BIT (0x2 << 24)
+#define ADC_CR1_RES_6BIT (0x3 << 24)
+/**@}*/
+#define ADC_CR1_RES_MASK (0x3 << 24)
+#define ADC_CR1_RES_SHIFT 24
+
+/* Note: Bits [21:16] are reserved, and must be kept at reset value. */
+
+/* --- ADC_CR1 values (note some of these are defined elsewhere) ----------- */
+
+/* AWDEN: Analog watchdog enable on regular channels */
+#define ADC_CR1_AWDEN (1 << 23)
+
+/* JAWDEN: Analog watchdog enable on injected channels */
+#define ADC_CR1_JAWDEN (1 << 22)
+
+/* DISCNUM[2:0]: Discontinuous mode channel count. */
+/****************************************************************************/
+/** @defgroup adc_cr1_discnum ADC Number of channels in discontinuous mode.
+@ingroup STM32F4xx_adc_defines
+
+@{*/
+#define ADC_CR1_DISCNUM_1CHANNELS (0x0 << 13)
+#define ADC_CR1_DISCNUM_2CHANNELS (0x1 << 13)
+#define ADC_CR1_DISCNUM_3CHANNELS (0x2 << 13)
+#define ADC_CR1_DISCNUM_4CHANNELS (0x3 << 13)
+#define ADC_CR1_DISCNUM_5CHANNELS (0x4 << 13)
+#define ADC_CR1_DISCNUM_6CHANNELS (0x5 << 13)
+#define ADC_CR1_DISCNUM_7CHANNELS (0x6 << 13)
+#define ADC_CR1_DISCNUM_8CHANNELS (0x7 << 13)
+/**@}*/
+#define ADC_CR1_DISCNUM_MASK (0x7 << 13)
+#define ADC_CR1_DISCNUM_SHIFT 13
+
+/* JDISCEN: */ /** Discontinuous mode on injected channels. */
+#define ADC_CR1_JDISCEN (1 << 12)
+
+/* DISCEN: */ /** Discontinuous mode on regular channels. */
+#define ADC_CR1_DISCEN (1 << 11)
+
+/* JAUTO: */ /** Automatic Injection Group conversion. */
+#define ADC_CR1_JAUTO (1 << 10)
+
+/* AWDSGL: */ /** Enable the watchdog on a single channel in scan mode. */
+#define ADC_CR1_AWDSGL (1 << 9)
+
+/* SCAN: */ /** Scan mode. */
+#define ADC_CR1_SCAN (1 << 8)
+
+/* JEOCIE: */ /** Interrupt enable for injected channels. */
+#define ADC_CR1_JEOCIE (1 << 7)
+
+/* AWDIE: */ /** Analog watchdog interrupt enable. */
+#define ADC_CR1_AWDIE (1 << 6)
+
+/* EOCIE: */ /** Interrupt enable EOC. */
+#define ADC_CR1_EOCIE (1 << 5)
+
+/* AWDCH[4:0]: Analog watchdog channel bits. (Up to 17 other values reserved) */
+/* Notes:
+ * ADC1: Analog channel 16 and 17 are internally connected to the temperature
+ * sensor and V_REFINT, respectively.
+ * ADC2: Analog channel 16 and 17 are internally connected to V_SS.
+ * ADC3: Analog channel 9, 14, 15, 16 and 17 are internally connected to V_SS.
+ */
+/****************************************************************************/
+/* ADC_CR1 AWDCH[4:0] ADC watchdog channel */
+/** @defgroup adc_watchdog_channel ADC watchdog channel
+@ingroup STM32F4xx_adc_defines
+
+@{*/
+#define ADC_CR1_AWDCH_CHANNEL0 (0x00 << 0)
+#define ADC_CR1_AWDCH_CHANNEL1 (0x01 << 0)
+#define ADC_CR1_AWDCH_CHANNEL2 (0x02 << 0)
+#define ADC_CR1_AWDCH_CHANNEL3 (0x03 << 0)
+#define ADC_CR1_AWDCH_CHANNEL4 (0x04 << 0)
+#define ADC_CR1_AWDCH_CHANNEL5 (0x05 << 0)
+#define ADC_CR1_AWDCH_CHANNEL6 (0x06 << 0)
+#define ADC_CR1_AWDCH_CHANNEL7 (0x07 << 0)
+#define ADC_CR1_AWDCH_CHANNEL8 (0x08 << 0)
+#define ADC_CR1_AWDCH_CHANNEL9 (0x09 << 0)
+#define ADC_CR1_AWDCH_CHANNEL10 (0x0A << 0)
+#define ADC_CR1_AWDCH_CHANNEL11 (0x0B << 0)
+#define ADC_CR1_AWDCH_CHANNEL12 (0x0C << 0)
+#define ADC_CR1_AWDCH_CHANNEL13 (0x0D << 0)
+#define ADC_CR1_AWDCH_CHANNEL14 (0x0E << 0)
+#define ADC_CR1_AWDCH_CHANNEL15 (0x0F << 0)
+#define ADC_CR1_AWDCH_CHANNEL16 (0x10 << 0)
+#define ADC_CR1_AWDCH_CHANNEL17 (0x11 << 0)
+/**@}*/
+#define ADC_CR1_AWDCH_MASK (0x1F << 0)
+#define ADC_CR1_AWDCH_SHIFT 0
+
+/* --- ADC_CR2 values ------------------------------------------------------ */
+
+/* SWSTART: Start conversion of regular channels. */
+#define ADC_CR2_SWSTART (1 << 30)
+
+/* EXTEN[1:0]: External trigger enable for regular channels. */
+/****************************************************************************/
+/** @defgroup adc_trigger_polarity_regular ADC Trigger Polarity
+@ingroup STM32F4xx_adc_defines
+
+@{*/
+#define ADC_CR2_EXTEN_DISABLED (0x0 << 28)
+#define ADC_CR2_EXTEN_RISING_EDGE (0x1 << 28)
+#define ADC_CR2_EXTEN_FALLING_EDGE (0x2 << 28)
+#define ADC_CR2_EXTEN_BOTH_EDGES (0x3 << 28)
+/**@}*/
+#define ADC_CR2_EXTEN_MASK (0x3 << 28)
+#define ADC_CR2_EXTEN_SHIFT 28
+
+/* EXTSEL[3:0]: External event selection for regular group. */
+/****************************************************************************/
+/** @defgroup adc_trigger_regular ADC Trigger Identifier for Regular group
+@ingroup STM32F4xx_adc_defines
+
+@{*/
+/** Timer 1 Compare Output 1 */
+#define ADC_CR2_EXTSEL_TIM1_CC1 (0x0 << 24)
+/** Timer 1 Compare Output 2 */
+#define ADC_CR2_EXTSEL_TIM1_CC2 (0x1 << 24)
+/** Timer 1 Compare Output 3 */
+#define ADC_CR2_EXTSEL_TIM1_CC3 (0x2 << 24)
+/** Timer 2 Compare Output 2 */
+#define ADC_CR2_EXTSEL_TIM2_CC2 (0x3 << 24)
+/** Timer 2 Compare Output 3 */
+#define ADC_CR2_EXTSEL_TIM2_CC3 (0x4 << 24)
+/** Timer 2 Compare Output 4 */
+#define ADC_CR2_EXTSEL_TIM2_CC4 (0x5 << 24)
+/** Timer 2 TRGO Event */
+#define ADC_CR2_EXTSEL_TIM2_TRGO (0x6 << 24)
+/** Timer 3 Compare Output 1 */
+#define ADC_CR2_EXTSEL_TIM3_CC1 (0x7 << 24)
+/** Timer 3 TRGO Event */
+#define ADC_CR2_EXTSEL_TIM3_TRGO (0x8 << 24)
+/** Timer 4 Compare Output 4 */
+#define ADC_CR2_EXTSEL_TIM4_CC4 (0x9 << 24)
+/** Timer 5 Compare Output 1 */
+#define ADC_CR2_EXTSEL_TIM5_CC1 (0xA << 24)
+/** Timer 5 Compare Output 2 */
+#define ADC_CR2_EXTSEL_TIM5_CC2 (0xB << 24)
+/** Timer 5 Compare Output 3 */
+#define ADC_CR2_EXTSEL_TIM5_CC3 (0xC << 24)
+/** Timer 8 Compare Output 1 */
+#define ADC_CR2_EXTSEL_TIM8_CC1 (0xD << 24)
+/** Timer 8 TRGO Event */
+#define ADC_CR2_EXTSEL_TIM8_TRGO (0xE << 24)
+/** EXTI Line 11 Event */
+#define ADC_CR2_EXTSEL_EXTI_LINE_11 (0xF << 24)
+/**@}*/
+#define ADC_CR2_EXTSEL_MASK (0xF << 24)
+#define ADC_CR2_EXTSEL_SHIFT 24
+
+/* Bit 23 is reserved */
+
+/* JSWSTART: Start conversion of injected channels. */
+#define ADC_CR2_JSWSTART (1 << 22)
+
+/* JEXTEN[1:0]: External trigger enable for injected channels. */
+/****************************************************************************/
+/** @defgroup adc_trigger_polarity_injected ADC Injected Trigger Polarity
+@ingroup STM32F4xx_adc_defines
+
+@{*/
+#define ADC_CR2_JEXTEN_DISABLED (0x0 << 20)
+#define ADC_CR2_JEXTEN_RISING_EDGE (0x1 << 20)
+#define ADC_CR2_JEXTEN_FALLING_EDGE (0x2 << 20)
+#define ADC_CR2_JEXTEN_BOTH_EDGES (0x3 << 20)
+/**@}*/
+#define ADC_CR2_JEXTEN_MASK (0x3 << 20)
+#define ADC_CR2_JEXTEN_SHIFT 20
+
+/* JEXTSEL[3:0]: External event selection for injected group. */
+/****************************************************************************/
+/** @defgroup adc_trigger_injected ADC Trigger Identifier for Injected group
+@ingroup STM32F4xx_adc_defines
+
+@{*/
+#define ADC_CR2_JEXTSEL_TIM1_CC4 (0x0 << 16)
+#define ADC_CR2_JEXTSEL_TIM1_TRGO (0x1 << 16)
+#define ADC_CR2_JEXTSEL_TIM2_CC1 (0x2 << 16)
+#define ADC_CR2_JEXTSEL_TIM2_TRGO (0x3 << 16)
+#define ADC_CR2_JEXTSEL_TIM3_CC2 (0x4 << 16)
+#define ADC_CR2_JEXTSEL_TIM3_CC4 (0x5 << 16)
+#define ADC_CR2_JEXTSEL_TIM4_CC1 (0x6 << 16)
+#define ADC_CR2_JEXTSEL_TIM4_CC2 (0x7 << 16)
+#define ADC_CR2_JEXTSEL_TIM4_CC3 (0x8 << 16)
+#define ADC_CR2_JEXTSEL_TIM4_TRGO (0x9 << 16)
+#define ADC_CR2_JEXTSEL_TIM5_CC4 (0xA << 16)
+#define ADC_CR2_JEXTSEL_TIM5_TRGO (0xB << 16)
+#define ADC_CR2_JEXTSEL_TIM8_CC2 (0xC << 16)
+#define ADC_CR2_JEXTSEL_TIM8_CC3 (0xD << 16)
+#define ADC_CR2_JEXTSEL_TIM8_CC4 (0xE << 16)
+#define ADC_CR2_JEXTSEL_EXTI_LINE_15 (0xF << 16)
+/**@}*/
+#define ADC_CR2_JEXTSEL_MASK (0xF << 16)
+#define ADC_CR2_JEXTSEL_SHIFT 16
+
+/* ALIGN: Data alignement. */
+#define ADC_CR2_ALIGN_RIGHT (0 << 11)
+#define ADC_CR2_ALIGN_LEFT (1 << 11)
+#define ADC_CR2_ALIGN (1 << 11)
+
+/* EOCS: End of conversion selection. */
+#define ADC_CR2_EOCS (1 << 10)
+
+/* DDS: DMA disable selection */
+#define ADC_CR2_DDS (1 << 9)
+
+/* DMA: Direct memory access mode. (ADC1 and ADC3 only!) */
+#define ADC_CR2_DMA (1 << 8)
+
+/* Note: Bits [7:2] are reserved and must be kept at reset value. */
+
+/* CONT: Continous conversion. */
+#define ADC_CR2_CONT (1 << 1)
+
+/* ADON: A/D converter On/Off. */
+/* Note: If any other bit in this register apart from ADON is changed at the
+ * same time, then conversion is not triggered. This is to prevent triggering
+ * an erroneous conversion.
+ * Conclusion: Must be separately written.
+ */
+#define ADC_CR2_ADON (1 << 0)
+
+/* --- ADC_SMPR1 values ---------------------------------------------------- */
+
+#define ADC_SMPR1_SMP17_LSB 21
+#define ADC_SMPR1_SMP16_LSB 18
+#define ADC_SMPR1_SMP15_LSB 15
+#define ADC_SMPR1_SMP14_LSB 12
+#define ADC_SMPR1_SMP13_LSB 9
+#define ADC_SMPR1_SMP12_LSB 6
+#define ADC_SMPR1_SMP11_LSB 3
+#define ADC_SMPR1_SMP10_LSB 0
+#define ADC_SMPR1_SMP17_MSK (0x7 << ADC_SMP17_LSB)
+#define ADC_SMPR1_SMP16_MSK (0x7 << ADC_SMP16_LSB)
+#define ADC_SMPR1_SMP15_MSK (0x7 << ADC_SMP15_LSB)
+#define ADC_SMPR1_SMP14_MSK (0x7 << ADC_SMP14_LSB)
+#define ADC_SMPR1_SMP13_MSK (0x7 << ADC_SMP13_LSB)
+#define ADC_SMPR1_SMP12_MSK (0x7 << ADC_SMP12_LSB)
+#define ADC_SMPR1_SMP11_MSK (0x7 << ADC_SMP11_LSB)
+#define ADC_SMPR1_SMP10_MSK (0x7 << ADC_SMP10_LSB)
+/****************************************************************************/
+/* ADC_SMPR1 ADC Sample Time Selection for Channels */
+/** @defgroup adc_sample_r1 ADC Sample Time Selection for ADC1
+@ingroup STM32F4xx_adc_defines
+
+@{*/
+#define ADC_SMPR1_SMP_1DOT5CYC 0x0
+#define ADC_SMPR1_SMP_7DOT5CYC 0x1
+#define ADC_SMPR1_SMP_13DOT5CYC 0x2
+#define ADC_SMPR1_SMP_28DOT5CYC 0x3
+#define ADC_SMPR1_SMP_41DOT5CYC 0x4
+#define ADC_SMPR1_SMP_55DOT5CYC 0x5
+#define ADC_SMPR1_SMP_71DOT5CYC 0x6
+#define ADC_SMPR1_SMP_239DOT5CYC 0x7
+/**@}*/
+
+/* --- ADC_SMPR2 values ---------------------------------------------------- */
+
+#define ADC_SMPR2_SMP9_LSB 27
+#define ADC_SMPR2_SMP8_LSB 24
+#define ADC_SMPR2_SMP7_LSB 21
+#define ADC_SMPR2_SMP6_LSB 18
+#define ADC_SMPR2_SMP5_LSB 15
+#define ADC_SMPR2_SMP4_LSB 12
+#define ADC_SMPR2_SMP3_LSB 9
+#define ADC_SMPR2_SMP2_LSB 6
+#define ADC_SMPR2_SMP1_LSB 3
+#define ADC_SMPR2_SMP0_LSB 0
+#define ADC_SMPR2_SMP9_MSK (0x7 << ADC_SMP9_LSB)
+#define ADC_SMPR2_SMP8_MSK (0x7 << ADC_SMP8_LSB)
+#define ADC_SMPR2_SMP7_MSK (0x7 << ADC_SMP7_LSB)
+#define ADC_SMPR2_SMP6_MSK (0x7 << ADC_SMP6_LSB)
+#define ADC_SMPR2_SMP5_MSK (0x7 << ADC_SMP5_LSB)
+#define ADC_SMPR2_SMP4_MSK (0x7 << ADC_SMP4_LSB)
+#define ADC_SMPR2_SMP3_MSK (0x7 << ADC_SMP3_LSB)
+#define ADC_SMPR2_SMP2_MSK (0x7 << ADC_SMP2_LSB)
+#define ADC_SMPR2_SMP1_MSK (0x7 << ADC_SMP1_LSB)
+#define ADC_SMPR2_SMP0_MSK (0x7 << ADC_SMP0_LSB)
+/****************************************************************************/
+/* ADC_SMPR2 ADC Sample Time Selection for Channels */
+/** @defgroup adc_sample_r2 ADC Sample Time Selection for ADC2
+@ingroup STM32F4xx_adc_defines
+
+@{*/
+#define ADC_SMPR2_SMP_1DOT5CYC 0x0
+#define ADC_SMPR2_SMP_7DOT5CYC 0x1
+#define ADC_SMPR2_SMP_13DOT5CYC 0x2
+#define ADC_SMPR2_SMP_28DOT5CYC 0x3
+#define ADC_SMPR2_SMP_41DOT5CYC 0x4
+#define ADC_SMPR2_SMP_55DOT5CYC 0x5
+#define ADC_SMPR2_SMP_71DOT5CYC 0x6
+#define ADC_SMPR2_SMP_239DOT5CYC 0x7
+/**@}*/
+
+/* --- ADC_SMPRx generic values -------------------------------------------- */
+/****************************************************************************/
+/* ADC_SMPRG ADC Sample Time Selection for Channels */
+/** @defgroup adc_sample_rg ADC Sample Time Selection for All Channels
+@ingroup STM32F4xx_adc_defines
+
+@{*/
+#define ADC_SMPR_SMP_1DOT5CYC 0x0
+#define ADC_SMPR_SMP_7DOT5CYC 0x1
+#define ADC_SMPR_SMP_13DOT5CYC 0x2
+#define ADC_SMPR_SMP_28DOT5CYC 0x3
+#define ADC_SMPR_SMP_41DOT5CYC 0x4
+#define ADC_SMPR_SMP_55DOT5CYC 0x5
+#define ADC_SMPR_SMP_71DOT5CYC 0x6
+#define ADC_SMPR_SMP_239DOT5CYC 0x7
+/**@}*/
+
+/* --- ADC_JOFRx, ADC_HTR, ADC_LTR values ---------------------------------- */
+
+#define ADC_JOFFSET_LSB 0
+#define ADC_JOFFSET_MSK (0x7ff << 0)
+#define ADC_HT_LSB 0
+#define ADC_HT_MSK (0x7ff << 0)
+#define ADC_LT_LSB 0
+#define ADC_LT_MSK (0x7ff << 0)
+
+/* --- ADC_SQR1 values ----------------------------------------------------- */
+
+#define ADC_SQR1_L_LSB 20
+#define ADC_SQR1_SQ16_LSB 15
+#define ADC_SQR1_SQ15_LSB 10
+#define ADC_SQR1_SQ14_LSB 5
+#define ADC_SQR1_SQ13_LSB 0
+#define ADC_SQR1_L_MSK (0xf << ADC_SQR1_L_LSB)
+#define ADC_SQR1_SQ16_MSK (0x1f << ADC_SQR1_SQ16_LSB)
+#define ADC_SQR1_SQ15_MSK (0x1f << ADC_SQR1_SQ15_LSB)
+#define ADC_SQR1_SQ14_MSK (0x1f << ADC_SQR1_SQ14_LSB)
+#define ADC_SQR1_SQ13_MSK (0x1f << ADC_SQR1_SQ13_LSB)
+
+/* --- ADC_SQR2 values ----------------------------------------------------- */
+
+#define ADC_SQR2_SQ12_LSB 25
+#define ADC_SQR2_SQ11_LSB 20
+#define ADC_SQR2_SQ10_LSB 15
+#define ADC_SQR2_SQ9_LSB 10
+#define ADC_SQR2_SQ8_LSB 5
+#define ADC_SQR2_SQ7_LSB 0
+#define ADC_SQR2_SQ12_MSK (0x1f << ADC_SQR2_SQ12_LSB)
+#define ADC_SQR2_SQ11_MSK (0x1f << ADC_SQR2_SQ11_LSB)
+#define ADC_SQR2_SQ10_MSK (0x1f << ADC_SQR2_SQ10_LSB)
+#define ADC_SQR2_SQ9_MSK (0x1f << ADC_SQR2_SQ9_LSB)
+#define ADC_SQR2_SQ8_MSK (0x1f << ADC_SQR2_SQ8_LSB)
+#define ADC_SQR2_SQ7_MSK (0x1f << ADC_SQR2_SQ7_LSB)
+
+/* --- ADC_SQR3 values ----------------------------------------------------- */
+
+#define ADC_SQR3_SQ6_LSB 25
+#define ADC_SQR3_SQ5_LSB 20
+#define ADC_SQR3_SQ4_LSB 15
+#define ADC_SQR3_SQ3_LSB 10
+#define ADC_SQR3_SQ2_LSB 5
+#define ADC_SQR3_SQ1_LSB 0
+#define ADC_SQR3_SQ6_MSK (0x1f << ADC_SQR3_SQ6_LSB)
+#define ADC_SQR3_SQ5_MSK (0x1f << ADC_SQR3_SQ5_LSB)
+#define ADC_SQR3_SQ4_MSK (0x1f << ADC_SQR3_SQ4_LSB)
+#define ADC_SQR3_SQ3_MSK (0x1f << ADC_SQR3_SQ3_LSB)
+#define ADC_SQR3_SQ2_MSK (0x1f << ADC_SQR3_SQ2_LSB)
+#define ADC_SQR3_SQ1_MSK (0x1f << ADC_SQR3_SQ1_LSB)
+
+/* --- ADC_JSQR values ----------------------------------------------------- */
+
+#define ADC_JSQR_JL_LSB 20
+#define ADC_JSQR_JSQ4_LSB 15
+#define ADC_JSQR_JSQ3_LSB 10
+#define ADC_JSQR_JSQ2_LSB 5
+#define ADC_JSQR_JSQ1_LSB 0
+
+/* JL[2:0]: Discontinous mode channel count injected channels. */
+/****************************************************************************/
+/** @defgroup adc_jsqr_jl ADC Number of channels in discontinuous mode fro injected channels.
+@ingroup STM32F4xx_adc_defines
+
+@{*/
+#define ADC_JSQR_JL_1CHANNELS (0x0 << ADC_JSQR_JL_LSB)
+#define ADC_JSQR_JL_2CHANNELS (0x1 << ADC_JSQR_JL_LSB)
+#define ADC_JSQR_JL_3CHANNELS (0x2 << ADC_JSQR_JL_LSB)
+#define ADC_JSQR_JL_4CHANNELS (0x3 << ADC_JSQR_JL_LSB)
+/**@}*/
+#define ADC_JSQR_JL_SHIFT 13
+#define ADC_JSQR_JL_MSK (0x2 << ADC_JSQR_JL_LSB)
+#define ADC_JSQR_JSQ4_MSK (0x1f << ADC_JSQR_JSQ4_LSB)
+#define ADC_JSQR_JSQ3_MSK (0x1f << ADC_JSQR_JSQ3_LSB)
+#define ADC_JSQR_JSQ2_MSK (0x1f << ADC_JSQR_JSQ2_LSB)
+#define ADC_JSQR_JSQ1_MSK (0x1f << ADC_JSQR_JSQ1_LSB)
+
+/* --- ADC_JDRx, ADC_DR values --------------------------------------------- */
+
+#define ADC_JDATA_LSB 0
+#define ADC_DATA_LSB 0
+#define ADC_JDATA_MSK (0xffff << ADC_JDATA_LSB)
+#define ADC_DATA_MSK (0xffff << ADC_DA)
+
+/* --- Common Registers ---------------------------------------------------- */
+
+/* --- ADC_CSR values (read only images) ------------------------------------ */
+
+/* OVR3: Overrun ADC3. */
+#define ADC_CSR_OVR3 (1 << 21)
+
+/* STRT3: Regular channel start ADC3. */
+#define ADC_CSR_STRT3 (1 << 20)
+
+/* JSTRT3: Injected channel start ADC3. */
+#define ADC_CSR_JSTRT3 (1 << 19)
+
+/* JEOC3: Injected channel end of conversion ADC3. */
+#define ADC_CSR_JEOC3 (1 << 18)
+
+/* EOC3: Regular channel end of conversion ADC3. */
+#define ADC_CSR_EOC3 (1 << 17)
+
+/* EOC3: Regular channel end of conversion ADC3. */
+#define ADC_CSR_AWD3 (1 << 16)
+
+/* Bits 15:14 Reserved, must be kept at reset value */
+
+/* OVR2: Overrun ADC2. */
+#define ADC_CSR_OVR2 (1 << 13)
+
+/* STRT2: Regular channel start ADC2. */
+#define ADC_CSR_STRT2 (1 << 12)
+
+/* JSTRT2: Injected channel start ADC2. */
+#define ADC_CSR_JSTRT2 (1 << 11)
+
+/* JEOC2: Injected channel end of conversion ADC2. */
+#define ADC_CSR_JEOC2 (1 << 10)
+
+/* EOC2: Regular channel end of conversion ADC2. */
+#define ADC_CSR_EOC2 (1 << 9)
+
+/* EOC2: Regular channel end of conversion ADC2. */
+#define ADC_CSR_AWD2 (1 << 8)
+
+/* Bits 7:6 Reserved, must be kept at reset value */
+
+/* OVR1: Overrun ADC1. */
+#define ADC_CSR_OVR1 (1 << 5)
+
+/* STRT1: Regular channel start ADC1. */
+#define ADC_CSR_STRT1 (1 << 4)
+
+/* JSTRT1: Injected channel start ADC1. */
+#define ADC_CSR_JSTRT1 (1 << 3)
+
+/* JEOC1: Injected channel end of conversion ADC1. */
+#define ADC_CSR_JEOC1 (1 << 2)
+
+/* EOC1: Regular channel end of conversion ADC1. */
+#define ADC_CSR_EOC1 (1 << 1)
+
+/* EOC1: Regular channel end of conversion ADC1. */
+#define ADC_CSR_AWD1 (1 << 0)
+
+/* --- ADC_CCR values ------------------------------------------------------ */
+
+/* TSVREFE: Temperature sensor and Vrefint enable. */
+#define ADC_CCR_TSVREFE (1 << 23)
+
+/* VBATE: VBat enable. */
+#define ADC_CCR_VBATE (1 << 22)
+
+/* Bit 18:21 reserved, must be kept at reset value. */
+
+/* ADCPRE: ADC prescaler. */
+/****************************************************************************/
+/** @defgroup adc_ccr_adcpre ADC Prescale
+@ingroup STM32F4xx_adc_defines
+
+@{*/
+#define ADC_CCR_ADCPRE_BY2 (0x0 << 16)
+#define ADC_CCR_ADCPRE_BY4 (0x1 << 16)
+#define ADC_CCR_ADCPRE_BY6 (0x2 << 16)
+#define ADC_CCR_ADCPRE_BY8 (0x3 << 16)
+/**@}*/
+#define ADC_CCR_ADCPRE_MASK (0x3 << 16)
+#define ADC_CCR_ADCPRE_SHIFT 16
+
+/* DMA: Direct memory access mode for multi ADC mode. */
+/****************************************************************************/
+/** @defgroup adc_dma_mode ADC DMA mode for multi ADC mode
+@ingroup STM32F4xx_adc_defines
+
+@{*/
+#define ADC_CCR_DMA_DISABLE (0x0 << 14)
+#define ADC_CCR_DMA_MODE_1 (0x1 << 14)
+#define ADC_CCR_DMA_MODE_2 (0x2 << 14)
+#define ADC_CCR_DMA_MODE_3 (0x3 << 14)
+/**@}*/
+#define ADC_CCR_DMA_MASK (0x3 << 14)
+#define ADC_CCR_DMA_SHIFT 14
+
+/* DDS: DMA disable selection (for multi-ADC mode). */
+#define ADC_CCR_DDS (1 << 13)
+
+/* Bit 12 reserved, must be kept at reset value */
+
+/* DELAY: Delay between 2 sampling phases. */
+/****************************************************************************/
+/** @defgroup adc_delay ADC Delay between 2 sampling phases
+@ingroup STM32F4xx_adc_defines
+
+@{*/
+#define ADC_CCR_DELAY_5ADCCLK (0x0 << 8)
+#define ADC_CCR_DELAY_6ADCCLK (0x1 << 8)
+#define ADC_CCR_DELAY_7ADCCLK (0x2 << 8)
+#define ADC_CCR_DELAY_8ADCCLK (0x3 << 8)
+#define ADC_CCR_DELAY_9ADCCLK (0x4 << 8)
+#define ADC_CCR_DELAY_10ADCCLK (0x5 << 8)
+#define ADC_CCR_DELAY_11ADCCLK (0x6 << 8)
+#define ADC_CCR_DELAY_12ADCCLK (0x7 << 8)
+#define ADC_CCR_DELAY_13ADCCLK (0x8 << 8)
+#define ADC_CCR_DELAY_14ADCCLK (0x9 << 8)
+#define ADC_CCR_DELAY_15ADCCLK (0xa << 8)
+#define ADC_CCR_DELAY_16ADCCLK (0xb << 8)
+#define ADC_CCR_DELAY_17ADCCLK (0xc << 8)
+#define ADC_CCR_DELAY_18ADCCLK (0xd << 8)
+#define ADC_CCR_DELAY_19ADCCLK (0xe << 8)
+#define ADC_CCR_DELAY_20ADCCLK (0xf << 8)
+/**@}*/
+#define ADC_CCR_DELAY_MASK (0xf << 8)
+#define ADC_CCR_DELAY_SHIFT 8
+
+/* Bit 7:5 reserved, must be kept at reset value */
+
+/* MULTI: Multi ADC mode selection. */
+/****************************************************************************/
+/** @defgroup adc_multi_mode ADC Multi mode selection
+@ingroup STM32F4xx_adc_defines
+
+@{*/
+
+/** All ADCs independent */
+#define ADC_CCR_MULTI_INDEPENDENT (0x00 << 0)
+
+/* dual modes (ADC1 + ADC2) */
+/** Dual modes (ADC1 + ADC2) Combined regular simultaneous + injected simultaneous mode */
+#define ADC_CCR_MULTI_DUAL_REG_SIMUL_AND_INJECTED_SIMUL (0x01 << 0)
+/** Dual modes (ADC1 + ADC2) Combined regular simultaneous + alternate trigger mode. */
+#define ADC_CCR_MULTI_DUAL_REG_SIMUL_AND_ALTERNATE_TRIG (0x02 << 0)
+/** Dual modes (ADC1 + ADC2) Injected simultaneous mode only. */
+#define ADC_CCR_MULTI_DUAL_INJECTED_SIMUL (0x05 << 0)
+/** Dual modes (ADC1 + ADC2) Regular simultaneous mode only. */
+#define ADC_CCR_MULTI_DUAL_REGULAR_SIMUL (0x06 << 0)
+/** Dual modes (ADC1 + ADC2) Interleaved mode only. */
+#define ADC_CCR_MULTI_DUAL_INTERLEAVED (0x07 << 0)
+/** Dual modes (ADC1 + ADC2) Alternate trigger mode only. */
+#define ADC_CCR_MULTI_DUAL_ALTERNATE_TRIG (0x09 << 0)
+
+/* Triple modes (ADC1 + ADC2 + ADC3) */
+/** Triple modes (ADC1 + ADC2 + ADC3) Combined regular simultaneous + injected simultaneous mode */
+#define ADC_CCR_MULTI_TRIPLE_REG_SIMUL_AND_INJECTED_SIMUL (0x11 << 0)
+/** Triple modes (ADC1 + ADC2 + ADC3) Combined regular simultaneous + alternate trigger mode. */
+#define ADC_CCR_MULTI_TRIPLE_REG_SIMUL_AND_ALTERNATE_TRIG (0x12 << 0)
+/** Triple modes (ADC1 + ADC2 + ADC3) Injected simultaneous mode only. */
+#define ADC_CCR_MULTI_TRIPLE_INJECTED_SIMUL (0x15 << 0)
+/** Triple modes (ADC1 + ADC2 + ADC3) Regular simultaneous mode only. */
+#define ADC_CCR_MULTI_TRIPLE_REGULAR_SIMUL (0x16 << 0)
+/** Triple modes (ADC1 + ADC2 + ADC3) Interleaved mode only. */
+#define ADC_CCR_MULTI_TRIPLE_INTERLEAVED (0x17 << 0)
+/** Triple modes (ADC1 + ADC2 + ADC3) Alternate trigger mode only. */
+#define ADC_CCR_MULTI_TRIPLE_ALTERNATE_TRIG (0x19 << 0)
+/**@}*/
+
+#define ADC_CCR_MULTI_MASK (0x1f << 0)
+#define ADC_CCR_MULTI_SHIFT 0
+
+/* --- ADC_CDR values ------------------------------------------------------ */
+
+#define ADC_CDR_DATA2_MASK (0xffff << 16)
+#define ADC_CDR_DATA2_SHIFT 16
+
+#define ADC_CDR_DATA1_MASK (0xffff << 0)
+#define ADC_CDR_DATA1_SHIFT 0
+
+BEGIN_DECLS
+
+void adc_power_on(u32 adc);
+void adc_off(u32 adc);
+void adc_enable_analog_watchdog_regular(u32 adc);
+void adc_disable_analog_watchdog_regular(u32 adc);
+void adc_enable_analog_watchdog_injected(u32 adc);
+void adc_disable_analog_watchdog_injected(u32 adc);
+void adc_enable_discontinuous_mode_regular(u32 adc, u8 length);
+void adc_disable_discontinuous_mode_regular(u32 adc);
+void adc_enable_discontinuous_mode_injected(u32 adc);
+void adc_disable_discontinuous_mode_injected(u32 adc);
+void adc_enable_automatic_injected_group_conversion(u32 adc);
+void adc_disable_automatic_injected_group_conversion(u32 adc);
+void adc_enable_analog_watchdog_on_all_channels(u32 adc);
+void adc_enable_analog_watchdog_on_selected_channel(u32 adc, u8 channel);
+void adc_enable_scan_mode(u32 adc);
+void adc_disable_scan_mode(u32 adc);
+void adc_enable_eoc_interrupt_injected(u32 adc);
+void adc_disable_eoc_interrupt_injected(u32 adc);
+void adc_enable_awd_interrupt(u32 adc);
+void adc_disable_awd_interrupt(u32 adc);
+void adc_enable_eoc_interrupt(u32 adc);
+void adc_disable_eoc_interrupt(u32 adc);
+void adc_start_conversion_regular(u32 adc);
+void adc_start_conversion_injected(u32 adc);
+void adc_disable_external_trigger_regular(u32 adc);
+void adc_disable_external_trigger_injected(u32 adc);
+void adc_set_left_aligned(u32 adc);
+void adc_set_right_aligned(u32 adc);
+void adc_enable_dma(u32 adc);
+void adc_disable_dma(u32 adc);
+void adc_set_continuous_conversion_mode(u32 adc);
+void adc_set_single_conversion_mode(u32 adc);
+void adc_set_sample_time(u32 adc, u8 channel, u8 time);
+void adc_set_sample_time_on_all_channels(u32 adc, u8 time);
+void adc_set_watchdog_high_threshold(u32 adc, u16 threshold);
+void adc_set_watchdog_low_threshold(u32 adc, u16 threshold);
+void adc_set_regular_sequence(u32 adc, u8 length, u8 channel[]);
+void adc_set_injected_sequence(u32 adc, u8 length, u8 channel[]);
+bool adc_eoc(u32 adc);
+bool adc_eoc_injected(u32 adc);
+u32 adc_read_regular(u32 adc);
+u32 adc_read_injected(u32 adc, u8 reg);
+void adc_set_injected_offset(u32 adc, u8 reg, u32 offset);
+
+void adc_set_clk_prescale(u32 prescaler);
+void adc_set_multi_mode(u32 mode);
+void adc_enable_external_trigger_regular(u32 adc, u32 trigger, u32 polarity);
+void adc_enable_external_trigger_injected(u32 adc, u32 trigger, u32 polarity);
+void adc_set_resolution(u32 adc, u16 resolution);
+void adc_enable_overrun_interrupt(u32 adc);
+void adc_disable_overrun_interrupt(u32 adc);
+bool adc_get_overrun_flag(u32 adc);
+void adc_clear_overrun_flag(u32 adc);
+bool adc_awd(u32 adc);
+void adc_eoc_after_each(u32 adc);
+void adc_eoc_after_group(u32 adc);
+void adc_set_dma_continue(u32 adc);
+void adc_set_dma_terminate(u32 adc);
+void adc_enable_temperature_sensor(void);
+void adc_disable_temperature_sensor(void);
+
+END_DECLS
+
+/**@}*/
+
+#endif
diff --git a/include/libopencm3/stm32/f4/dma.h b/include/libopencm3/stm32/f4/dma.h
new file mode 100644
index 0000000..c765a79
--- /dev/null
+++ b/include/libopencm3/stm32/f4/dma.h
@@ -0,0 +1,693 @@
+/** @defgroup STM32F4xx_dma_defines DMA Defines
+
+@ingroup STM32F4xx_defines
+
+@brief Defined Constants and Types for the STM32F4xx DMA Controller
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 18 October 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Ken Sarkies <ksarkies@internode.on.net>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/**@{*/
+
+#ifndef LIBOPENCM3_DMA_H
+#define LIBOPENCM3_DMA_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/* --- Convenience macros -------------------------------------------------- */
+
+/* DMA register base adresses (for convenience) */
+#define DMA1 DMA1_BASE
+#define DMA2 DMA2_BASE
+
+/* --- DMA registers ------------------------------------------------------- */
+
+/* DMA low interrupt status register (DMAx_ISR) */
+#define DMA_LISR(dma_base) MMIO32(dma_base + 0x00)
+#define DMA1_LISR DMA_ISR(DMA1)
+#define DMA2_LISR DMA_ISR(DMA2)
+
+/* DMA high interrupt status register (DMAx_ISR) */
+#define DMA_HISR(dma_base) MMIO32(dma_base + 0x04)
+#define DMA1_HISR DMA_ISR(DMA1)
+#define DMA2_HISR DMA_ISR(DMA2)
+
+/* DMA low interrupt flag clear register (DMAx_IFCR) */
+#define DMA_LIFCR(dma_base) MMIO32(dma_base + 0x08)
+#define DMA1_LIFCR DMA_IFCR(DMA1)
+#define DMA2_LIFCR DMA_IFCR(DMA2)
+
+/* DMA high interrupt flag clear register (DMAx_IFCR) */
+#define DMA_HIFCR(dma_base) MMIO32(dma_base + 0x0C)
+#define DMA1_HIFCR DMA_IFCR(DMA1)
+#define DMA2_HIFCR DMA_IFCR(DMA2)
+
+/* DMA stream configuration register (DMAx_SyCR) */
+#define DMA_SCR(dma_base, stream) MMIO32(dma_base + 0x10 + \
+ (0x18 * (stream)))
+
+#define DMA1_SCR(stream) DMA_SCR(DMA1, stream)
+#define DMA1_S0CR DMA1_SCR(DMA_STREAM0)
+#define DMA1_S1CR DMA1_SCR(DMA_STREAM1)
+#define DMA1_S2CR DMA1_SCR(DMA_STREAM2)
+#define DMA1_S3CR DMA1_SCR(DMA_STREAM3)
+#define DMA1_S4CR DMA1_SCR(DMA_STREAM4)
+#define DMA1_S5CR DMA1_SCR(DMA_STREAM5)
+#define DMA1_S6CR DMA1_SCR(DMA_STREAM6)
+#define DMA1_S7CR DMA1_SCR(DMA_STREAM7)
+
+#define DMA2_SCR(stream) DMA_SCR(DMA2, stream)
+#define DMA2_S0CR DMA2_SCR(DMA_STREAM0)
+#define DMA2_S1CR DMA2_SCR(DMA_STREAM1)
+#define DMA2_S2CR DMA2_SCR(DMA_STREAM2)
+#define DMA2_S3CR DMA2_SCR(DMA_STREAM3)
+#define DMA2_S4CR DMA2_SCR(DMA_STREAM4)
+#define DMA2_S5CR DMA2_SCR(DMA_STREAM5)
+#define DMA2_S6CR DMA2_SCR(DMA_STREAM6)
+#define DMA2_S7CR DMA2_SCR(DMA_STREAM7)
+
+/* DMA number of data register (DMAx_SyNDTR) */
+#define DMA_SNDTR(dma_base, stream) MMIO32(dma_base + 0x14 + \
+ (0x18 * (stream)))
+
+#define DMA1_SNDTR(stream) DMA_SNDTR(DMA1, stream)
+#define DMA1_S0NDTR DMA1_SNDTR(DMA_STREAM0)
+#define DMA1_S1NDTR DMA1_SNDTR(DMA_STREAM1)
+#define DMA1_S2NDTR DMA1_SNDTR(DMA_STREAM2)
+#define DMA1_S3NDTR DMA1_SNDTR(DMA_STREAM3)
+#define DMA1_S4NDTR DMA1_SNDTR(DMA_STREAM4)
+#define DMA1_S5NDTR DMA1_SNDTR(DMA_STREAM5)
+#define DMA1_S6NDTR DMA1_SNDTR(DMA_STREAM6)
+#define DMA1_S7NDTR DMA1_SNDTR(DMA_STREAM7)
+
+#define DMA2_SNDTR(stream) DMA_CNDTR(DMA2, stream)
+#define DMA2_S0NDTR DMA2_SNDTR(DMA_STREAM0)
+#define DMA2_S1NDTR DMA2_SNDTR(DMA_STREAM1)
+#define DMA2_S2NDTR DMA2_SNDTR(DMA_STREAM2)
+#define DMA2_S3NDTR DMA2_SNDTR(DMA_STREAM3)
+#define DMA2_S4NDTR DMA2_SNDTR(DMA_STREAM4)
+#define DMA2_S5NDTR DMA2_SNDTR(DMA_STREAM5)
+#define DMA2_S6NDTR DMA2_SNDTR(DMA_STREAM6)
+#define DMA2_S7NDTR DMA2_SNDTR(DMA_STREAM7)
+
+/* DMA peripheral address register (DMAx_SyPAR) */
+#define DMA_SPAR(dma_base, stream) MMIO32(dma_base + 0x18 + \
+ (0x18 * (stream)))
+
+#define DMA1_SPAR(stream) DMA_SPAR(DMA1, stream)
+#define DMA1_S0PAR DMA1_SPAR(DMA_STREAM0)
+#define DMA1_S1PAR DMA1_SPAR(DMA_STREAM1)
+#define DMA1_S2PAR DMA1_SPAR(DMA_STREAM2)
+#define DMA1_S3PAR DMA1_SPAR(DMA_STREAM3)
+#define DMA1_S4PAR DMA1_SPAR(DMA_STREAM4)
+#define DMA1_S5PAR DMA1_SPAR(DMA_STREAM5)
+#define DMA1_S6PAR DMA1_SPAR(DMA_STREAM6)
+#define DMA1_S7PAR DMA1_SPAR(DMA_STREAM7)
+
+#define DMA2_SPAR(stream) DMA_SPAR(DMA2, stream)
+#define DMA2_S0PAR DMA2_SPAR(DMA_STREAM0)
+#define DMA2_S1PAR DMA2_SPAR(DMA_STREAM1)
+#define DMA2_S2PAR DMA2_SPAR(DMA_STREAM2)
+#define DMA2_S3PAR DMA2_SPAR(DMA_STREAM3)
+#define DMA2_S4PAR DMA2_SPAR(DMA_STREAM4)
+#define DMA2_S5PAR DMA2_SPAR(DMA_STREAM5)
+#define DMA2_S6PAR DMA2_SPAR(DMA_STREAM6)
+#define DMA2_S7PAR DMA2_SPAR(DMA_STREAM7)
+
+/* DMA memory 0 address register (DMAx_SyM0AR) */
+
+#define DMA_SM0AR(dma_base, stream) MMIO32(dma_base + 0x1C + \
+ (0x18 * (stream)))
+
+#define DMA1_SM0AR(stream) DMA_SM0AR(DMA1, stream)
+#define DMA1_S0M0AR DMA1_SM0AR(DMA_STREAM0)
+#define DMA1_S1M0AR DMA1_SM0AR(DMA_STREAM1)
+#define DMA1_S2M0AR DMA1_SM0AR(DMA_STREAM2)
+#define DMA1_S3M0AR DMA1_SM0AR(DMA_STREAM3)
+#define DMA1_S4M0AR DMA1_SM0AR(DMA_STREAM4)
+#define DMA1_S5M0AR DMA1_SM0AR(DMA_STREAM5)
+#define DMA1_S6M0AR DMA1_SM0AR(DMA_STREAM6)
+#define DMA1_S7M0AR DMA1_SM0AR(DMA_STREAM7)
+
+#define DMA2_SM0AR(stream) DMA_CM0AR(DMA2, stream)
+#define DMA2_S0M0AR DMA2_SM0AR(DMA_STREAM0)
+#define DMA2_S1M0AR DMA2_SM0AR(DMA_STREAM1)
+#define DMA2_S2M0AR DMA2_SM0AR(DMA_STREAM2)
+#define DMA2_S3M0AR DMA2_SM0AR(DMA_STREAM3)
+#define DMA2_S4M0AR DMA2_SM0AR(DMA_STREAM4)
+#define DMA2_S5M0AR DMA2_SM0AR(DMA_STREAM5)
+#define DMA2_S6M0AR DMA2_SM0AR(DMA_STREAM6)
+#define DMA2_S7M0AR DMA2_SM0AR(DMA_STREAM7)
+
+/* DMA memory 1 address register (DMAx_SyM1AR) */
+
+#define DMA_SM1AR(dma_base, stream) MMIO32(dma_base + 0x20 + \
+ (0x18 * (stream)))
+
+#define DMA1_SM1AR(stream) DMA_SM1AR(DMA1, stream)
+#define DMA1_S0M1AR DMA1_SM1AR(DMA_STREAM0)
+#define DMA1_S1M1AR DMA1_SM1AR(DMA_STREAM1)
+#define DMA1_S2M1AR DMA1_SM1AR(DMA_STREAM2)
+#define DMA1_S3M1AR DMA1_SM1AR(DMA_STREAM3)
+#define DMA1_S4M1AR DMA1_SM1AR(DMA_STREAM4)
+#define DMA1_S5M1AR DMA1_SM1AR(DMA_STREAM5)
+#define DMA1_S6M1AR DMA1_SM1AR(DMA_STREAM6)
+#define DMA1_S7M1AR DMA1_SM1AR(DMA_STREAM7)
+
+#define DMA2_SM1AR(stream) DMA_CM1AR(DMA2, stream)
+#define DMA2_S0M1AR DMA2_SM1AR(DMA_STREAM0)
+#define DMA2_S1M1AR DMA2_SM1AR(DMA_STREAM1)
+#define DMA2_S2M1AR DMA2_SM1AR(DMA_STREAM2)
+#define DMA2_S3M1AR DMA2_SM1AR(DMA_STREAM3)
+#define DMA2_S4M1AR DMA2_SM1AR(DMA_STREAM4)
+#define DMA2_S5M1AR DMA2_SM1AR(DMA_STREAM5)
+#define DMA2_S6M1AR DMA2_SM1AR(DMA_STREAM6)
+#define DMA2_S7M1AR DMA2_SM1AR(DMA_STREAM7)
+
+/* DMA FIFO Control Register register (DMAx_SyFCR) */
+
+#define DMA_SFCR(dma_base, stream) MMIO32(dma_base + 0x24 + \
+ (0x18 * (stream)))
+
+#define DMA1_SFCR(stream) DMA_SFCR(DMA1, stream)
+#define DMA1_S0FCR DMA1_SFCR(DMA_STREAM0)
+#define DMA1_S1FCR DMA1_SFCR(DMA_STREAM1)
+#define DMA1_S2FCR DMA1_SFCR(DMA_STREAM2)
+#define DMA1_S3FCR DMA1_SFCR(DMA_STREAM3)
+#define DMA1_S4FCR DMA1_SFCR(DMA_STREAM4)
+#define DMA1_S5FCR DMA1_SFCR(DMA_STREAM5)
+#define DMA1_S6FCR DMA1_SFCR(DMA_STREAM6)
+#define DMA1_S7FCR DMA1_SFCR(DMA_STREAM7)
+
+#define DMA2_SFCR(stream) DMA_CFCR(DMA2, stream)
+#define DMA2_S0FCR DMA2_SFCR(DMA_STREAM0)
+#define DMA2_S1FCR DMA2_SFCR(DMA_STREAM1)
+#define DMA2_S2FCR DMA2_SFCR(DMA_STREAM2)
+#define DMA2_S3FCR DMA2_SFCR(DMA_STREAM3)
+#define DMA2_S4FCR DMA2_SFCR(DMA_STREAM4)
+#define DMA2_S5FCR DMA2_SFCR(DMA_STREAM5)
+#define DMA2_S6FCR DMA2_SFCR(DMA_STREAM6)
+#define DMA2_S7FCR DMA2_SFCR(DMA_STREAM7)
+
+/* --- DMA Interrupt Flag offset values ------------------------------------- */
+/* These are based on every interrupt flag and flag clear being at the same relative location */
+/** @defgroup dma_if_offset DMA Interrupt Flag Offsets within stream flag group.
+@ingroup STM32F4xx_dma_defines
+
+@{*/
+/** Transfer Complete Interrupt Flag */
+#define DMA_ISR_TCIF (1 << 5)
+/** Half Transfer Interrupt Flag */
+#define DMA_ISR_HTIF (1 << 4)
+/** Transfer Error Interrupt Flag */
+#define DMA_ISR_TEIF (1 << 3)
+/** Direct Mode Error Interrupt Flag */
+#define DMA_ISR_DMEIF (1 << 2)
+/** FIFO Error Interrupt Flag */
+#define DMA_ISR_FEIF (1 << 0)
+/**@}*/
+
+/* Offset within interrupt status register to start of stream interrupt flag field */
+#define DMA_ISR_OFFSET(stream) (6*(stream & 0x01)+16*((stream & 0x02) >> 1))
+#define DMA_ISR_FLAGS (DMA_ISR_TCIF | DMA_ISR_HTIF | DMA_ISR_TEIF | DMA_ISR_DMEIF | DMA_ISR_FEIF)
+#define DMA_ISR_MASK(stream) DMA_ISR_FLAGS << DMA_ISR_OFFSET(stream)
+
+/* --- DMA_LISR values ------------------------------------------------------ */
+
+/* TCIF: Transfer complete interrupt flag, streams 0-3 only */
+#define DMA_LISR_TCIF_BIT DMA_ISR_TCIF
+#define DMA_LISR_TCIF(stream) (DMA_LISR_TCIF_BIT << DMA_ISR_OFFSET(stream))
+
+#define DMA_LISR_TCIF0 DMA_LISR_TCIF(DMA_STREAM0)
+#define DMA_LISR_TCIF1 DMA_LISR_TCIF(DMA_STREAM1)
+#define DMA_LISR_TCIF2 DMA_LISR_TCIF(DMA_STREAM2)
+#define DMA_LISR_TCIF3 DMA_LISR_TCIF(DMA_STREAM3)
+
+/* HTIF: Half transfer interrupt flag, streams 0-3 only */
+#define DMA_LISR_HTIF_BIT DMA_ISR_HTIF
+#define DMA_LISR_HTIF(stream) (DMA_LISR_HTIF_BIT << DMA_ISR_OFFSET(stream))
+
+#define DMA_LISR_HTIF0 DMA_LISR_HTIF(DMA_STREAM0)
+#define DMA_LISR_HTIF1 DMA_LISR_HTIF(DMA_STREAM1)
+#define DMA_LISR_HTIF2 DMA_LISR_HTIF(DMA_STREAM2)
+#define DMA_LISR_HTIF3 DMA_LISR_HTIF(DMA_STREAM3)
+
+/* TEIF: Transfer error interrupt flag, streams 0-3 only */
+#define DMA_LISR_TEIF_BIT DMA_ISR_TEIF
+#define DMA_LISR_TEIF(stream) (DMA_LISR_TEIF_BIT << DMA_ISR_OFFSET(stream))
+
+#define DMA_LISR_TEIF0 DMA_LISR_TEIF(DMA_STREAM0)
+#define DMA_LISR_TEIF1 DMA_LISR_TEIF(DMA_STREAM1)
+#define DMA_LISR_TEIF2 DMA_LISR_TEIF(DMA_STREAM2)
+#define DMA_LISR_TEIF3 DMA_LISR_TEIF(DMA_STREAM3)
+
+/* DMEIF: Direct Mode Error interrupt flag, streams 0-3 only */
+#define DMA_LISR_DMEIF_BIT DMA_ISR_DMEIF
+#define DMA_LISR_DMEIF(stream) (DMA_LISR_DMEIF_BIT << DMA_ISR_OFFSET(stream))
+
+#define DMA_LISR_DMEIF0 DMA_LISR_DMEIF(DMA_STREAM0)
+#define DMA_LISR_DMEIF1 DMA_LISR_DMEIF(DMA_STREAM1)
+#define DMA_LISR_DMEIF2 DMA_LISR_DMEIF(DMA_STREAM2)
+#define DMA_LISR_DMEIF3 DMA_LISR_DMEIF(DMA_STREAM3)
+
+/* Interrupt #1 is reserved */
+
+/* FEIF: FIFO Error interrupt flag, streams 0-3 only */
+#define DMA_LISR_FEIF_BIT DMA_ISR_FEIF
+#define DMA_LISR_FEIF(stream) (DMA_LISR_FEIF_BIT << DMA_ISR_OFFSET(stream))
+
+#define DMA_LISR_FEIF0 DMA_LISR_FEIF(DMA_STREAM0)
+#define DMA_LISR_FEIF1 DMA_LISR_FEIF(DMA_STREAM1)
+#define DMA_LISR_FEIF2 DMA_LISR_FEIF(DMA_STREAM2)
+#define DMA_LISR_FEIF3 DMA_LISR_FEIF(DMA_STREAM3)
+
+/* --- DMA_HISR values ------------------------------------------------------ */
+
+/* TCIF: Transfer complete interrupt flag, streams 4-7 only */
+#define DMA_HISR_TCIF_BIT DMA_ISR_TCIF
+#define DMA_HISR_TCIF(stream) (DMA_HISR_TCIF_BIT << (DMA_ISR_OFFSET(stream - 4))
+
+#define DMA_HISR_TCIF4 DMA_HISR_TCIF(DMA_STREAM4)
+#define DMA_HISR_TCIF5 DMA_HISR_TCIF(DMA_STREAM5)
+#define DMA_HISR_TCIF6 DMA_HISR_TCIF(DMA_STREAM6)
+#define DMA_HISR_TCIF7 DMA_HISR_TCIF(DMA_STREAM7)
+
+/* HTIF: Half transfer interrupt flag, streams 4-7 only */
+#define DMA_HISR_HTIF_BIT DMA_ISR_HTIF
+#define DMA_HISR_HTIF(stream) (DMA_HISR_HTIF_BIT << (DMA_ISR_OFFSET(stream - 4))
+
+#define DMA_HISR_HTIF4 DMA_HISR_HTIF(DMA_STREAM4)
+#define DMA_HISR_HTIF5 DMA_HISR_HTIF(DMA_STREAM5)
+#define DMA_HISR_HTIF6 DMA_HISR_HTIF(DMA_STREAM6)
+#define DMA_HISR_HTIF7 DMA_HISR_HTIF(DMA_STREAM7)
+
+/* TEIF: Transfer error interrupt flag, streams 4-7 only */
+#define DMA_HISR_TEIF_BIT DMA_ISR_TEIF
+#define DMA_HISR_TEIF(stream) (DMA_HISR_TEIF_BIT << (DMA_ISR_OFFSET(stream - 4))
+
+#define DMA_HISR_TEIF4 DMA_HISR_TEIF(DMA_STREAM4)
+#define DMA_HISR_TEIF5 DMA_HISR_TEIF(DMA_STREAM5)
+#define DMA_HISR_TEIF6 DMA_HISR_TEIF(DMA_STREAM6)
+#define DMA_HISR_TEIF7 DMA_HISR_TEIF(DMA_STREAM7)
+
+/* DMEIF: Direct Mode Error interrupt flag, streams 4-7 only */
+#define DMA_HISR_DMEIF_BIT DMA_ISR_DMEIF
+#define DMA_HISR_DMEIF(stream) (DMA_HISR_DMEIF_BIT << (DMA_ISR_OFFSET(stream - 4))
+
+#define DMA_HISR_DMEIF4 DMA_HISR_DMEIF(DMA_STREAM4)
+#define DMA_HISR_DMEIF5 DMA_HISR_DMEIF(DMA_STREAM5)
+#define DMA_HISR_DMEIF6 DMA_HISR_DMEIF(DMA_STREAM6)
+#define DMA_HISR_DMEIF7 DMA_HISR_DMEIF(DMA_STREAM7)
+
+/* Interrupt #1 is reserved */
+
+/* FEIF: FIFO Error interrupt flag, streams 4-7 only */
+#define DMA_HISR_FEIF_BIT DMA_ISR_FEIF
+#define DMA_HISR_FEIF(stream) (DMA_HISR_FEIF_BIT << (DMA_ISR_OFFSET(stream - 4))
+
+#define DMA_HISR_FEIF4 DMA_HISR_FEIF(DMA_STREAM4)
+#define DMA_HISR_FEIF5 DMA_HISR_FEIF(DMA_STREAM5)
+#define DMA_HISR_FEIF6 DMA_HISR_FEIF(DMA_STREAM6)
+#define DMA_HISR_FEIF7 DMA_HISR_FEIF(DMA_STREAM7)
+
+/* --- DMA_LIFCR values ------------------------------------------------------ */
+
+/* TCIF: Transfer complete interrupt flag, streams 0-3 only */
+#define DMA_LIFCR_CTCIF_BIT DMA_ISR_TCIF
+#define DMA_LIFCR_CTCIF(stream) (DMA_LIFCR_CTCIF_BIT << DMA_ISR_OFFSET(stream))
+
+#define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF(DMA_STREAM0)
+#define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF(DMA_STREAM1)
+#define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF(DMA_STREAM2)
+#define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF(DMA_STREAM3)
+
+/* HTIF: Half transfer interrupt flag, streams 0-3 only */
+#define DMA_LIFCR_CHTIF_BIT DMA_ISR_HTIF
+#define DMA_LIFCR_CHTIF(stream) (DMA_LIFCR_CHTIF_BIT << DMA_ISR_OFFSET(stream))
+
+#define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF(DMA_STREAM0)
+#define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF(DMA_STREAM1)
+#define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF(DMA_STREAM2)
+#define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF(DMA_STREAM3)
+
+/* TEIF: Transfer error interrupt flag, streams 0-3 only */
+#define DMA_LIFCR_CTEIF_BIT DMA_ISR_TEIF
+#define DMA_LIFCR_CTEIF(stream) (DMA_LIFCR_CTEIF_BIT << DMA_ISR_OFFSET(stream))
+
+#define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF(DMA_STREAM0)
+#define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF(DMA_STREAM1)
+#define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF(DMA_STREAM2)
+#define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF(DMA_STREAM3)
+
+/* DMEIF: Direct Mode Error interrupt flag, streams 0-3 only */
+#define DMA_LIFCR_CDMEIF_BIT DMA_ISR_DMEIF
+#define DMA_LIFCR_CDMEIF(stream) (DMA_LIFCR_CDMEIF_BIT << DMA_ISR_OFFSET(stream))
+
+#define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF(DMA_STREAM0)
+#define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF(DMA_STREAM1)
+#define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF(DMA_STREAM2)
+#define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF(DMA_STREAM3)
+
+/* Interrupt #1 is reserved */
+
+/* FEIF: FIFO Error interrupt flag, streams 0-3 only */
+#define DMA_LIFCR_CFEIF_BIT DMA_ISR_FEIF
+#define DMA_LIFCR_CFEIF(stream) (DMA_LIFCR_CFEIF_BIT << DMA_ISR_OFFSET(stream))
+
+#define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF(DMA_STREAM0)
+#define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF(DMA_STREAM1)
+#define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF(DMA_STREAM2)
+#define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF(DMA_STREAM3)
+
+/* --- DMA_HIFCR values ------------------------------------------------------ */
+
+/* TCIF: Transfer complete interrupt flag, streams 4-7 only */
+#define DMA_HIFCR_CTCIF_BIT DMA_ISR_TCIF
+#define DMA_HIFCR_CTCIF(stream) (DMA_HIFCR_CTCIF_BIT << (DMA_ISR_OFFSET(stream - 4))
+
+#define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF(DMA_STREAM4)
+#define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF(DMA_STREAM5)
+#define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF(DMA_STREAM6)
+#define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF(DMA_STREAM7)
+
+/* HTIF: Half transfer interrupt flag, streams 4-7 only */
+#define DMA_HIFCR_CHTIF_BIT DMA_ISR_HTIF
+#define DMA_HIFCR_CHTIF(stream) (DMA_HIFCR_CHTIF_BIT << (DMA_ISR_OFFSET(stream - 4))
+
+#define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF(DMA_STREAM4)
+#define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF(DMA_STREAM5)
+#define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF(DMA_STREAM6)
+#define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF(DMA_STREAM7)
+
+/* TEIF: Transfer error interrupt flag, streams 4-7 only */
+#define DMA_HIFCR_CTEIF_BIT DMA_ISR_TEIF
+#define DMA_HIFCR_CTEIF(stream) (DMA_HIFCR_CTEIF_BIT << (DMA_ISR_OFFSET(stream - 4))
+
+#define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF(DMA_STREAM4)
+#define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF(DMA_STREAM5)
+#define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF(DMA_STREAM6)
+#define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF(DMA_STREAM7)
+
+/* DMEIF: Direct Mode Error interrupt flag, streams 4-7 only */
+#define DMA_HIFCR_CDMEIF_BIT DMA_ISR_DMEIF
+#define DMA_HIFCR_CDMEIF(stream) (DMA_HIFCR_CDMEIF_BIT << (DMA_ISR_OFFSET(stream - 4))
+
+#define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF(DMA_STREAM4)
+#define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF(DMA_STREAM5)
+#define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF(DMA_STREAM6)
+#define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF(DMA_STREAM7)
+
+/* Interrupt #1 is reserved */
+
+/* FEIF: FIFO Error interrupt flag, streams 4-7 only */
+#define DMA_HIFCR_CFEIF_BIT DMA_ISR_FEIF
+#define DMA_HIFCR_CFEIF(stream) (DMA_HIFCR_CFEIF_BIT << (DMA_ISR_OFFSET(stream - 4))
+
+#define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF(DMA_STREAM4)
+#define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF(DMA_STREAM5)
+#define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF(DMA_STREAM6)
+#define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF(DMA_STREAM7)
+
+/* --- DMA_SxCR generic values --------------------------------------------- */
+
+/* Reserved [31:28] */
+
+/* CHSEL[13:12]: Channel Select */
+/** @defgroup dma_ch_sel DMA Channel Select
+@ingroup STM32F4xx_dma_defines
+
+@{*/
+#define DMA_SCR_CHSEL_0 (0x0 << 25)
+#define DMA_SCR_CHSEL_1 (0x1 << 25)
+#define DMA_SCR_CHSEL_2 (0x2 << 25)
+#define DMA_SCR_CHSEL_3 (0x3 << 25)
+#define DMA_SCR_CHSEL_4 (0x4 << 25)
+#define DMA_SCR_CHSEL_5 (0x5 << 25)
+#define DMA_SCR_CHSEL_6 (0x6 << 25)
+#define DMA_SCR_CHSEL_7 (0x7 << 25)
+/**@}*/
+#define DMA_SCR_CHSEL_MASK (0x7 << 25)
+#define DMA_SCR_CHSEL_SHIFT 25
+
+/* MBURST[13:12]: Memory Burst Configuration */
+/** @defgroup dma_mburst DMA Memory Burst Length
+@ingroup STM32F4xx_dma_defines
+
+@{*/
+#define DMA_SCR_MBURST_INCR0 (0x0 << 23)
+#define DMA_SCR_MBURST_INCR4 (0x1 << 23)
+#define DMA_SCR_MBURST_INCR8 (0x2 << 23)
+#define DMA_SCR_MBURST_INCR16 (0x3 << 23)
+/**@}*/
+#define DMA_SCR_MBURST_MASK (0x3 << 23)
+#define DMA_SCR_MBURST_SHIFT 23
+
+/* PBURST[13:12]: Peripheral Burst Configuration */
+/** @defgroup dma_pburst DMA Peripheral Burst Length
+@ingroup STM32F4xx_dma_defines
+
+@{*/
+#define DMA_SCR_PBURST_INCR0 (0x0 << 21)
+#define DMA_SCR_PBURST_INCR4 (0x1 << 21)
+#define DMA_SCR_PBURST_INCR8 (0x2 << 21)
+#define DMA_SCR_PBURST_INCR16 (0x3 << 21)
+/**@}*/
+#define DMA_SCR_PBURST_MASK (0x3 << 21)
+#define DMA_SCR_PBURST_SHIFT 21
+
+/* Bit 20 reserved */
+
+/* CT: Current target (in double buffered mode) */
+#define DMA_SCR_CT (1 << 19)
+
+/* DBM: Double buffered mode */
+#define DMA_SCR_DBM (1 << 18)
+
+/* PL[17:16]: Stream priority level */
+/** @defgroup dma_st_pri DMA Stream Priority Levels
+@ingroup STM32F4xx_dma_defines
+
+@{*/
+#define DMA_SCR_PL_LOW (0x0 << 16)
+#define DMA_SCR_PL_MEDIUM (0x1 << 16)
+#define DMA_SCR_PL_HIGH (0x2 << 16)
+#define DMA_SCR_PL_VERY_HIGH (0x3 << 16)
+/**@}*/
+#define DMA_SCR_PL_MASK (0x3 << 16)
+#define DMA_SCR_PL_SHIFT 16
+
+/* PINCOS: Peripheral increment offset size */
+#define DMA_SCR_PINCOS (1 << 15)
+
+/* MSIZE[14:13]: Memory size */
+/** @defgroup dma_st_memwidth DMA Stream Memory Word Width
+@ingroup STM32F4xx_dma_defines
+
+@{*/
+#define DMA_SCR_MSIZE_8BIT (0x0 << 13)
+#define DMA_SCR_MSIZE_16BIT (0x1 << 13)
+#define DMA_SCR_MSIZE_32BIT (0x2 << 13)
+/**@}*/
+#define DMA_SCR_MSIZE_MASK (0x3 << 13)
+#define DMA_SCR_MSIZE_SHIFT 13
+
+/* PSIZE[12:11]: Peripheral size */
+/** @defgroup dma_st_perwidth DMA Stream Peripheral Word Width
+@ingroup STM32F4xx_dma_defines
+
+@{*/
+#define DMA_SCR_PSIZE_8BIT (0x0 << 11)
+#define DMA_SCR_PSIZE_16BIT (0x1 << 11)
+#define DMA_SCR_PSIZE_32BIT (0x2 << 11)
+/**@}*/
+#define DMA_SCR_PSIZE_MASK (0x3 << 11)
+#define DMA_SCR_PSIZE_SHIFT 11
+
+/* MINC: Memory increment mode */
+#define DMA_SCR_MINC (1 << 10)
+
+/* PINC: Peripheral increment mode */
+#define DMA_SCR_PINC (1 << 9)
+
+/* CIRC: Circular mode */
+#define DMA_SCR_CIRC (1 << 8)
+
+/* DIR[7:6]: Data transfer direction */
+/** @defgroup dma_st_dir DMA Stream Data transfer direction
+@ingroup STM32F4xx_dma_defines
+
+@{*/
+#define DMA_SCR_DIR_PER2MEM (0x0 << 6)
+#define DMA_SCR_DIR_MEM2PER (0x1 << 6)
+#define DMA_SCR_DIR_MEM2MEM (0x2 << 6)
+/**@}*/
+#define DMA_SCR_DIR_MASK (0x3 << 6)
+#define DMA_SCR_DIR_SHIFT 6
+
+/* PFCTRL: Peripheral Flow Controller */
+#define DMA_SCR_PFCTRL (1 << 5)
+
+/* TCIE: Transfer complete interrupt enable */
+#define DMA_SCR_TCIE (1 << 4)
+
+/* HTIE: Half transfer interrupt enable */
+#define DMA_SCR_HTIE (1 << 3)
+
+/* TEIE: Transfer error interrupt enable */
+#define DMA_SCR_TEIE (1 << 2)
+
+/* DMEIE: Direct Mode error interrupt enable */
+#define DMA_SCR_DMEIE (1 << 1)
+
+/* EN: Stream enable */
+#define DMA_SCR_EN (1 << 0)
+
+/* --- DMA_SxNDTR values --------------------------------------------------- */
+
+/* NDT[15:0]: Number of data to transfer */
+
+/* --- DMA_SxPAR values ---------------------------------------------------- */
+
+/* PA[31:0]: Peripheral address */
+
+/* --- DMA_SxM0AR values ---------------------------------------------------- */
+
+/* M0A[31:0]: Memory address */
+
+/* --- DMA_SxM1AR values ---------------------------------------------------- */
+
+/* M1A[31:0]: Memory address */
+
+/* --- DMA_SxFCR generic values --------------------------------------------- */
+
+/* Reserved [31:8] */
+
+/* FEIE: FIFO error interrupt enable */
+#define DMA_FCR_FEIE (1 << 7)
+
+/* Bit 6 reserved */
+
+/* FS[5:3]: FIFO Status */
+/** @defgroup dma_fifo_status FIFO Status
+@ingroup STM32F4xx_dma_defines
+
+@{*/
+#define DMA_FCR_FS_LOW (0x0 << 3)
+#define DMA_FCR_FS_UNDER_HALF (0x1 << 3)
+#define DMA_FCR_FS_MEDIUM (0x2 << 3)
+#define DMA_FCR_FS_HIGH (0x3 << 3)
+#define DMA_FCR_FS_EMPTY (0x4 << 3)
+#define DMA_FCR_FS_FULL (0x5 << 3)
+/**@}*/
+#define DMA_FCR_FS_MASK (0x7 << 3)
+#define DMA_FCR_FS_SHIFT 3
+
+/* DMDIS: Direct Mode disable */
+#define DMA_FCR_DMDIS (1 << 2)
+
+/* FTH[1:0]: FIFO Threshold selection */
+/** @defgroup dma_fifo_thresh FIFO Threshold selection
+@ingroup STM32F4xx_dma_defines
+
+@{*/
+#define DMA_FCR_FTH_LOW (0x0 << 0)
+#define DMA_FCR_FTH_HALF (0x1 << 0)
+#define DMA_FCR_FTH_MEDIUM (0x2 << 0)
+#define DMA_FCR_FTH_FULL (0x3 << 0)
+/**@}*/
+#define DMA_FCR_FTH_MASK (0x3 << 0)
+#define DMA_FCR_FTH_SHIFT 3
+
+/* --- Generic values ------------------------------------------------------ */
+
+/** @defgroup dma_st_number DMA Stream Number
+@ingroup STM32F4xx_dma_defines
+
+@{*/
+#define DMA_STREAM0 0
+#define DMA_STREAM1 1
+#define DMA_STREAM2 2
+#define DMA_STREAM3 3
+#define DMA_STREAM4 4
+#define DMA_STREAM5 5
+#define DMA_STREAM6 6
+#define DMA_STREAM7 7
+/**@}*/
+
+/* --- function prototypes ------------------------------------------------- */
+
+BEGIN_DECLS
+
+void dma_stream_reset(u32 dma, u8 stream);
+void dma_clear_interrupt_flags(u32 dma, u8 stream, u32 interrupts);
+bool dma_get_interrupt_flag(u32 dma, u8 stream, u32 interrupt);
+void dma_set_transfer_mode(u32 dma, u8 stream, u32 direction);
+void dma_set_priority(u32 dma, u8 stream, u32 prio);
+void dma_set_memory_size(u32 dma, u8 stream, u32 mem_size);
+void dma_set_peripheral_size(u32 dma, u8 stream, u32 peripheral_size);
+void dma_enable_memory_increment_mode(u32 dma, u8 stream);
+void dma_disable_memory_increment_mode(u32 dma, u8 channel);
+void dma_enable_peripheral_increment_mode(u32 dma, u8 stream);
+void dma_disable_peripheral_increment_mode(u32 dma, u8 channel);
+void dma_enable_fixed_peripheral_increment_mode(u32 dma, u8 stream);
+void dma_enable_circular_mode(u32 dma, u8 stream);
+void dma_channel_select(u32 dma, u8 stream, u32 channel);
+void dma_channel_select(u32 dma, u8 stream, u32 channel);
+void dma_set_memory_burst(u32 dma, u8 stream, u32 burst);
+void dma_set_peripheral_burst(u32 dma, u8 stream, u32 burst);
+void dma_set_initial_target(u32 dma, u8 stream, u8 memory);
+u8 dma_get_target(u32 dma, u8 stream);
+void dma_enable_double_buffer_mode(u32 dma, u8 stream);
+void dma_set_peripheral_flow_control(u32 dma, u8 stream);
+void dma_set_dma_flow_control(u32 dma, u8 stream);
+void dma_enable_transfer_error_interrupt(u32 dma, u8 stream);
+void dma_disable_transfer_error_interrupt(u32 dma, u8 stream);
+void dma_enable_half_transfer_interrupt(u32 dma, u8 stream);
+void dma_disable_half_transfer_interrupt(u32 dma, u8 stream);
+void dma_enable_transfer_complete_interrupt(u32 dma, u8 stream);
+void dma_disable_transfer_complete_interrupt(u32 dma, u8 stream);
+u32 dma_fifo_status(u32 dma, u8 stream);
+void dma_enable_direct_mode_error_interrupt(u32 dma, u8 stream);
+void dma_disable_direct_mode_error_interrupt(u32 dma, u8 stream);
+void dma_enable_fifo_error_interrupt(u32 dma, u8 stream);
+void dma_disable_fifo_error_interrupt(u32 dma, u8 stream);
+void dma_enable_direct_mode(u32 dma, u8 stream);
+void dma_enable_fifo_mode(u32 dma, u8 stream);
+void dma_set_fifo_threshold(u32 dma, u8 stream, u32 threshold);
+void dma_enable_stream(u32 dma, u8 stream);
+void dma_disable_stream(u32 dma, u8 stream);
+void dma_set_peripheral_address(u32 dma, u8 stream, u32 address);
+void dma_set_memory_address(u32 dma, u8 stream, u32 address);
+void dma_set_memory_address_1(u32 dma, u8 stream, u32 address);
+void dma_set_number_of_data(u32 dma, u8 stream, u16 number);
+
+END_DECLS
+
+#endif
+/**@}*/
+
diff --git a/include/libopencm3/stm32/f4/irq.yaml b/include/libopencm3/stm32/f4/irq.yaml
new file mode 100644
index 0000000..2d4bae9
--- /dev/null
+++ b/include/libopencm3/stm32/f4/irq.yaml
@@ -0,0 +1,85 @@
+includeguard: LIBOPENCM3_STM32_F4_NVIC_H
+partname_humanreadable: STM32 F4 series
+partname_doxygen: STM32F4
+irqs:
+ - nvic_wwdg
+ - pvd
+ - tamp_stamp
+ - rtc_wkup
+ - flash
+ - rcc
+ - exti0
+ - exti1
+ - exti2
+ - exti3
+ - exti4
+ - dma1_stream0
+ - dma1_stream1
+ - dma1_stream2
+ - dma1_stream3
+ - dma1_stream4
+ - dma1_stream5
+ - dma1_stream6
+ - adc
+ - can1_tx
+ - can1_rx0
+ - can1_rx1
+ - can1_sce
+ - exti9_5
+ - tim1_brk_tim9
+ - tim1_up_tim10
+ - tim1_trg_com_tim11
+ - tim1_cc
+ - tim2
+ - tim3
+ - tim4
+ - i2c1_ev
+ - i2c1_er
+ - i2c2_ev
+ - i2c2_er
+ - spi1
+ - spi2
+ - usart1
+ - usart2
+ - usart3
+ - exti15_10
+ - rtc_alarm
+ - usb_fs_wkup
+ - tim8_brk_tim12
+ - tim8_up_tim13
+ - tim8_trg_com_tim14
+ - tim8_cc
+ - dma1_stream7
+ - fsmc
+ - sdio
+ - tim5
+ - spi3
+ - uart4
+ - uart5
+ - tim6_dac
+ - tim7
+ - dma2_stream0
+ - dma2_stream1
+ - dma2_stream2
+ - dma2_stream3
+ - dma2_stream4
+ - eth
+ - eth_wkup
+ - can2_tx
+ - can2_rx0
+ - can2_rx1
+ - can2_sce
+ - otg_fs
+ - dma2_stream5
+ - dma2_stream6
+ - dma2_stream7
+ - usart6
+ - i2c3_ev
+ - i2c3_er
+ - otg_hs_ep1_out
+ - otg_hs_ep1_in
+ - otg_hs_wkup
+ - otg_hs
+ - dcmi
+ - cryp
+ - hash_rng
diff --git a/include/libopencm3/stm32/f4/nvic_f4.h b/include/libopencm3/stm32/f4/nvic_f4.h
deleted file mode 100644
index 91b6c25..0000000
--- a/include/libopencm3/stm32/f4/nvic_f4.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * This file is part of the libopencm3 project.
- *
- * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef LIBOPENCM3_NVIC_F4_H
-#define LIBOPENCM3_NVIC_F4_H
-
-/* --- IRQ channel numbers-------------------------------------------------- */
-
-/* Note: These F4 specific user interrupt definitions supplement the
- * general NVIC definitions in ../nvic.h
- */
-
-/* User Interrupts */
-#define NVIC_NVIC_WWDG_IRQ 0
-#define NVIC_PVD_IRQ 1
-#define NVIC_TAMP_STAMP_IRQ 2
-#define NVIC_RTC_WKUP_IRQ 3
-#define NVIC_FLASH_IRQ 4
-#define NVIC_RCC_IRQ 5
-#define NVIC_EXTI0_IRQ 6
-#define NVIC_EXTI1_IRQ 7
-#define NVIC_EXTI2_IRQ 8
-#define NVIC_EXTI3_IRQ 9
-#define NVIC_EXTI4_IRQ 10
-#define NVIC_DMA1_STREAM0_IRQ 11
-#define NVIC_DMA1_STREAM1_IRQ 12
-#define NVIC_DMA1_STREAM2_IRQ 13
-#define NVIC_DMA1_STREAM3_IRQ 14
-#define NVIC_DMA1_STREAM4_IRQ 15
-#define NVIC_DMA1_STREAM5_IRQ 16
-#define NVIC_DMA1_STREAM6_IRQ 17
-#define NVIC_ADC_IRQ 18
-#define NVIC_CAN1_TX_IRQ 19
-#define NVIC_CAN1_RX0_IRQ 20
-#define NVIC_CAN1_RX1_IRQ 21
-#define NVIC_CAN1_SCE_IRQ 22
-#define NVIC_EXTI9_5_IRQ 23
-#define NVIC_TIM1_BRK_TIM9_IRQ 24
-#define NVIC_TIM1_UP_TIM10_IRQ 25
-#define NVIC_TIM1_TRG_COM_TIM11_IRQ 26
-#define NVIC_TIM1_CC_IRQ 27
-#define NVIC_TIM2_IRQ 28
-#define NVIC_TIM3_IRQ 29
-#define NVIC_TIM4_IRQ 30
-#define NVIC_I2C1_EV_IRQ 31
-#define NVIC_I2C1_ER_IRQ 32
-#define NVIC_I2C2_EV_IRQ 33
-#define NVIC_I2C2_ER_IRQ 34
-#define NVIC_SPI1_IRQ 35
-#define NVIC_SPI2_IRQ 36
-#define NVIC_USART1_IRQ 37
-#define NVIC_USART2_IRQ 38
-#define NVIC_USART3_IRQ 39
-#define NVIC_EXTI15_10_IRQ 40
-#define NVIC_RTC_ALARM_IRQ 41
-#define NVIC_USB_FS_WKUP_IRQ 42
-#define NVIC_TIM8_BRK_TIM12_IRQ 43
-#define NVIC_TIM8_UP_TIM13_IRQ 44
-#define NVIC_TIM8_TRG_COM_TIM14_IRQ 45
-#define NVIC_TIM8_CC_IRQ 46
-#define NVIC_DMA1_STREAM7_IRQ 47
-#define NVIC_FSMC_IRQ 48
-#define NVIC_SDIO_IRQ 49
-#define NVIC_TIM5_IRQ 50
-#define NVIC_SPI3_IRQ 51
-#define NVIC_UART4_IRQ 52
-#define NVIC_UART5_IRQ 53
-#define NVIC_TIM6_DAC_IRQ 54
-#define NVIC_TIM7_IRQ 55
-#define NVIC_DMA2_STREAM0_IRQ 56
-#define NVIC_DMA2_STREAM1_IRQ 57
-#define NVIC_DMA2_STREAM2_IRQ 58
-#define NVIC_DMA2_STREAM3_IRQ 59
-#define NVIC_DMA2_STREAM4_IRQ 60
-#define NVIC_ETH_IRQ 61
-#define NVIC_ETH_WKUP_IRQ 62
-#define NVIC_CAN2_TX_IRQ 63
-#define NVIC_CAN2_RX0_IRQ 64
-#define NVIC_CAN2_RX1_IRQ 65
-#define NVIC_CAN2_SCE_IRQ 66
-#define NVIC_OTG_FS_IRQ 67
-#define NVIC_DMA2_STREAM5_IRQ 68
-#define NVIC_DMA2_STREAM6_IRQ 69
-#define NVIC_DMA2_STREAM7_IRQ 70
-#define NVIC_USART6_IRQ 71
-#define NVIC_I2C3_EV_IRQ 72
-#define NVIC_I2C3_ER_IRQ 73
-#define NVIC_OTG_HS_EP1_OUT_IRQ 74
-#define NVIC_OTG_HS_EP1_IN_IRQ 75
-#define NVIC_OTG_HS_WKUP_IRQ 76
-#define NVIC_OTG_HS_IRQ 77
-#define NVIC_DCMI_IRQ 78
-#define NVIC_CRYP_IRQ 79
-#define NVIC_HASH_RNG_IRQ 80
-
-#endif
diff --git a/include/libopencm3/stm32/f4/syscfg.h b/include/libopencm3/stm32/f4/syscfg.h
deleted file mode 100644
index 7426f16..0000000
--- a/include/libopencm3/stm32/f4/syscfg.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * This file is part of the libopencm3 project.
- *
- * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef LIBOPENCM3_SYSCFG_H
-#define LIBOPENCM3_SYSCFG_H
-
-#include <libopencm3/stm32/memorymap.h>
-
-/* --- SYSCFG registers ------------------------------------------------------ */
-
-#define SYSCFG_MEMRM MMIO32(SYSCFG_BASE + 0x00)
-
-#define SYSCFG_PMC MMIO32(SYSCFG_BASE + 0x04)
-
-/* External interrupt configuration register 1 (SYSCFG_EXTICR1) */
-#define SYSCFG_EXTICR1 MMIO32(SYSCFG_BASE + 0x08)
-
-/* External interrupt configuration register 2 (SYSCFG_EXTICR2) */
-#define SYSCFG_EXTICR2 MMIO32(SYSCFG_BASE + 0x0c)
-
-/* External interrupt configuration register 3 (SYSCFG_EXTICR3) */
-#define SYSCFG_EXTICR3 MMIO32(SYSCFG_BASE + 0x10)
-
-/* External interrupt configuration register 4 (SYSCFG_EXTICR4) */
-#define SYSCFG_EXTICR4 MMIO32(SYSCFG_BASE + 0x14)
-
-#define SYSCFG_CMPCR MMIO32(SYSCFG_BASE + 0x20)
-
-#endif
-
diff --git a/include/libopencm3/stm32/l1/gpio.h b/include/libopencm3/stm32/l1/gpio.h
new file mode 100644
index 0000000..a39c9f6
--- /dev/null
+++ b/include/libopencm3/stm32/l1/gpio.h
@@ -0,0 +1,241 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+ * Copyright (C) 2012 Piotr Esden-Tempski <piotr@esden.net>
+ * Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_GPIO_H
+#define LIBOPENCM3_GPIO_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/* --- Convenience macros -------------------------------------------------- */
+
+/* GPIO port base addresses (for convenience) */
+#define GPIOA GPIO_PORT_A_BASE
+#define GPIOB GPIO_PORT_B_BASE
+#define GPIOC GPIO_PORT_C_BASE
+#define GPIOD GPIO_PORT_D_BASE
+#define GPIOE GPIO_PORT_E_BASE
+#define GPIOH GPIO_PORT_H_BASE
+
+/* GPIO number definitions (for convenience) */
+#define GPIO0 (1 << 0)
+#define GPIO1 (1 << 1)
+#define GPIO2 (1 << 2)
+#define GPIO3 (1 << 3)
+#define GPIO4 (1 << 4)
+#define GPIO5 (1 << 5)
+#define GPIO6 (1 << 6)
+#define GPIO7 (1 << 7)
+#define GPIO8 (1 << 8)
+#define GPIO9 (1 << 9)
+#define GPIO10 (1 << 10)
+#define GPIO11 (1 << 11)
+#define GPIO12 (1 << 12)
+#define GPIO13 (1 << 13)
+#define GPIO14 (1 << 14)
+#define GPIO15 (1 << 15)
+#define GPIO_ALL 0xffff
+
+/* --- GPIO registers ------------------------------------------------------ */
+
+/* Port mode register (GPIOx_MODER) */
+#define GPIO_MODER(port) MMIO32(port + 0x00)
+#define GPIOA_MODER GPIO_MODER(GPIOA)
+#define GPIOB_MODER GPIO_MODER(GPIOB)
+#define GPIOC_MODER GPIO_MODER(GPIOC)
+#define GPIOD_MODER GPIO_MODER(GPIOD)
+#define GPIOE_MODER GPIO_MODER(GPIOE)
+#define GPIOH_MODER GPIO_MODER(GPIOH)
+
+/* Port output type register (GPIOx_OTYPER) */
+#define GPIO_OTYPER(port) MMIO32(port + 0x04)
+#define GPIOA_OTYPER GPIO_OTYPER(GPIOA)
+#define GPIOB_OTYPER GPIO_OTYPER(GPIOB)
+#define GPIOC_OTYPER GPIO_OTYPER(GPIOC)
+#define GPIOD_OTYPER GPIO_OTYPER(GPIOD)
+#define GPIOE_OTYPER GPIO_OTYPER(GPIOE)
+#define GPIOH_OTYPER GPIO_OTYPER(GPIOH)
+
+/* Port output speed register (GPIOx_OSPEEDR) */
+#define GPIO_OSPEEDR(port) MMIO32(port + 0x08)
+#define GPIOA_OSPEEDR GPIO_OSPEEDR(GPIOA)
+#define GPIOB_OSPEEDR GPIO_OSPEEDR(GPIOB)
+#define GPIOC_OSPEEDR GPIO_OSPEEDR(GPIOC)
+#define GPIOD_OSPEEDR GPIO_OSPEEDR(GPIOD)
+#define GPIOE_OSPEEDR GPIO_OSPEEDR(GPIOE)
+#define GPIOH_OSPEEDR GPIO_OSPEEDR(GPIOH)
+
+/* Port pull-up/pull-down register (GPIOx_PUPDR) */
+#define GPIO_PUPDR(port) MMIO32(port + 0x0c)
+#define GPIOA_PUPDR GPIO_PUPDR(GPIOA)
+#define GPIOB_PUPDR GPIO_PUPDR(GPIOB)
+#define GPIOC_PUPDR GPIO_PUPDR(GPIOC)
+#define GPIOD_PUPDR GPIO_PUPDR(GPIOD)
+#define GPIOE_PUPDR GPIO_PUPDR(GPIOE)
+#define GPIOH_PUPDR GPIO_PUPDR(GPIOH)
+
+/* Port input data register (GPIOx_IDR) */
+#define GPIO_IDR(port) MMIO32(port + 0x10)
+#define GPIOA_IDR GPIO_IDR(GPIOA)
+#define GPIOB_IDR GPIO_IDR(GPIOB)
+#define GPIOC_IDR GPIO_IDR(GPIOC)
+#define GPIOD_IDR GPIO_IDR(GPIOD)
+#define GPIOE_IDR GPIO_IDR(GPIOE)
+#define GPIOH_IDR GPIO_IDR(GPIOH)
+
+/* Port output data register (GPIOx_ODR) */
+#define GPIO_ODR(port) MMIO32(port + 0x14)
+#define GPIOA_ODR GPIO_ODR(GPIOA)
+#define GPIOB_ODR GPIO_ODR(GPIOB)
+#define GPIOC_ODR GPIO_ODR(GPIOC)
+#define GPIOD_ODR GPIO_ODR(GPIOD)
+#define GPIOE_ODR GPIO_ODR(GPIOE)
+#define GPIOH_ODR GPIO_ODR(GPIOH)
+
+/* Port bit set/reset register (GPIOx_BSRR) */
+#define GPIO_BSRR(port) MMIO32(port + 0x18)
+#define GPIOA_BSRR GPIO_BSRR(GPIOA)
+#define GPIOB_BSRR GPIO_BSRR(GPIOB)
+#define GPIOC_BSRR GPIO_BSRR(GPIOC)
+#define GPIOD_BSRR GPIO_BSRR(GPIOD)
+#define GPIOE_BSRR GPIO_BSRR(GPIOE)
+#define GPIOH_BSRR GPIO_BSRR(GPIOH)
+
+/* Port configuration lock register (GPIOx_LCKR) */
+#define GPIO_LCKR(port) MMIO32(port + 0x1C)
+#define GPIOA_LCKR GPIO_LCKR(GPIOA)
+#define GPIOB_LCKR GPIO_LCKR(GPIOB)
+#define GPIOC_LCKR GPIO_LCKR(GPIOC)
+#define GPIOD_LCKR GPIO_LCKR(GPIOD)
+#define GPIOE_LCKR GPIO_LCKR(GPIOE)
+#define GPIOH_LCKR GPIO_LCKR(GPIOH)
+
+/* Alternate function low register (GPIOx_AFRL) */
+#define GPIO_AFRL(port) MMIO32(port + 0x20)
+#define GPIOA_AFRL GPIO_AFRL(GPIOA)
+#define GPIOB_AFRL GPIO_AFRL(GPIOB)
+#define GPIOC_AFRL GPIO_AFRL(GPIOC)
+#define GPIOD_AFRL GPIO_AFRL(GPIOD)
+#define GPIOE_AFRL GPIO_AFRL(GPIOE)
+#define GPIOH_AFRL GPIO_AFRL(GPIOH)
+
+/* Alternate function high register (GPIOx_AFRH) */
+#define GPIO_AFRH(port) MMIO32(port + 0x24)
+#define GPIOA_AFRH GPIO_AFRH(GPIOA)
+#define GPIOB_AFRH GPIO_AFRH(GPIOB)
+#define GPIOC_AFRH GPIO_AFRH(GPIOC)
+#define GPIOD_AFRH GPIO_AFRH(GPIOD)
+#define GPIOE_AFRH GPIO_AFRH(GPIOE)
+#define GPIOH_AFRH GPIO_AFRH(GPIOH)
+
+/* --- GPIOx_MODER values-------------------------------------------- */
+
+#define GPIO_MODE(n, mode) (mode << (2 * (n)))
+#define GPIO_MODE_MASK(n) (0x3 << (2 * (n)))
+#define GPIO_MODE_INPUT 0x00 /* Default */
+#define GPIO_MODE_OUTPUT 0x01
+#define GPIO_MODE_AF 0x02
+#define GPIO_MODE_ANALOG 0x03
+
+/* --- GPIOx_OTYPER values -------------------------------------------- */
+/* Output type (OTx values) */
+#define GPIO_OTYPE_PP 0x0
+#define GPIO_OTYPE_OD 0x1
+
+/* Output speed values */
+#define GPIO_OSPEED(n, speed) (speed << (2 * (n)))
+#define GPIO_OSPEED_MASK(n) (0x3 << (2 * (n)))
+#define GPIO_OSPEED_400KHZ 0x0
+#define GPIO_OSPEED_2MHZ 0x1
+#define GPIO_OSPEED_10MHZ 0x2
+#define GPIO_OSPEED_40MHZ 0x3
+
+/* --- GPIOx_PUPDR values ------------------------------------------- */
+
+#define GPIO_PUPD(n, pupd) (pupd << (2 * (n)))
+#define GPIO_PUPD_MASK(n) (0x3 << (2 * (n)))
+#define GPIO_PUPD_NONE 0x0
+#define GPIO_PUPD_PULLUP 0x1
+#define GPIO_PUPD_PULLDOWN 0x2
+
+/* --- GPIO_IDR values ----------------------------------------------------- */
+
+/* GPIO_IDR[15:0]: IDRy[15:0]: Port input data (y = 0..15) */
+
+/* --- GPIO_ODR values ----------------------------------------------------- */
+
+/* GPIO_ODR[15:0]: ODRy[15:0]: Port output data (y = 0..15) */
+
+/* --- GPIO_BSRR values ---------------------------------------------------- */
+
+/* GPIO_BSRR[31:16]: BRy: Port x reset bit y (y = 0..15) */
+/* GPIO_BSRR[15:0]: BSy: Port x set bit y (y = 0..15) */
+
+/* --- GPIO_LCKR values ---------------------------------------------------- */
+
+#define GPIO_LCKK (1 << 16)
+/* GPIO_LCKR[15:0]: LCKy: Port x lock bit y (y = 0..15) */
+
+/* --- GPIOx_AFRL/H values ------------------------------------------------- */
+
+/* Note: AFRL is used for bits 0..7, AFRH is used for 8..15 */
+/* See datasheet table 5, page 35 for the definitions */
+
+#define GPIO_AFR(n, af) (af << ((n) * 4))
+#define GPIO_AFR_MASK(n) (0xf << ((n) * 4))
+#define GPIO_AF0 0x0
+#define GPIO_AF1 0x1
+#define GPIO_AF2 0x2
+#define GPIO_AF3 0x3
+#define GPIO_AF4 0x4
+#define GPIO_AF5 0x5
+#define GPIO_AF6 0x6
+#define GPIO_AF7 0x7
+#define GPIO_AF8 0x8
+#define GPIO_AF9 0x9
+#define GPIO_AF10 0xa
+#define GPIO_AF11 0xb
+#define GPIO_AF12 0xc
+#define GPIO_AF13 0xd
+#define GPIO_AF14 0xe
+#define GPIO_AF15 0xf
+
+/* --- Function prototypes ------------------------------------------------- */
+
+/*
+ * L1, like F2 and F4, has the "new" GPIO peripheral, so use that style
+ * TODO: this should all really be moved to a "common" gpio header
+ */
+
+void gpio_mode_setup(u32 gpioport, u8 mode, u8 pull_up_down, u16 gpios);
+void gpio_set_output_options(u32 gpioport, u8 otype, u8 speed, u16 gpios);
+void gpio_set_af(u32 gpioport, u8 alt_func_num, u16 gpios);
+
+/* F1 compatible api */
+void gpio_set(u32 gpioport, u16 gpios);
+void gpio_clear(u32 gpioport, u16 gpios);
+u16 gpio_get(u32 gpioport, u16 gpios);
+void gpio_toggle(u32 gpioport, u16 gpios);
+u16 gpio_port_read(u32 gpioport);
+void gpio_port_write(u32 gpioport, u16 data);
+void gpio_port_config_lock(u32 gpioport, u16 gpios);
+
+#endif
diff --git a/include/libopencm3/stm32/l1/irq.yaml b/include/libopencm3/stm32/l1/irq.yaml
new file mode 100644
index 0000000..c2f118f
--- /dev/null
+++ b/include/libopencm3/stm32/l1/irq.yaml
@@ -0,0 +1,49 @@
+includeguard: LIBOPENCM3_STM32_L1_NVIC_H
+partname_humanreadable: STM32 L1 series
+partname_doxygen: STM32L1
+irqs:
+ - wwdg
+ - pvd
+ - tamper
+ - rtc
+ - flash
+ - rcc
+ - exti0
+ - exti1
+ - exti2
+ - exti3
+ - exti4
+ - dma1_channel1
+ - dma1_channel2
+ - dma1_channel3
+ - dma1_channel4
+ - dma1_channel5
+ - dma1_channel6
+ - dma1_channel7
+ - adc1
+ - usb_hp
+ - usb_lp
+ - dac
+ - comp
+ - exti9_5
+ - lcd
+ - tim9
+ - tim10
+ - tim11
+ - tim2
+ - tim3
+ - tim4
+ - i2c1_ev
+ - i2c1_er
+ - i2c2_ev
+ - i2c2_er
+ - spi1
+ - spi2
+ - usart1
+ - usart2
+ - usart3
+ - exti15_10
+ - rtc_alarm
+ - usb_wakeup
+ - tim6
+ - tim7
diff --git a/include/libopencm3/stm32/l1/memorymap.h b/include/libopencm3/stm32/l1/memorymap.h
new file mode 100644
index 0000000..950dd18
--- /dev/null
+++ b/include/libopencm3/stm32/l1/memorymap.h
@@ -0,0 +1,108 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+ * Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_MEMORYMAP_H
+#define LIBOPENCM3_MEMORYMAP_H
+
+#include <libopencm3/cm3/memorymap.h>
+
+/* --- STM32 specific peripheral definitions ------------------------------- */
+
+/* Memory map for all busses */
+#define PERIPH_BASE ((u32)0x40000000)
+#define INFO_BASE ((u32)0x1ff00000)
+#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)
+#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)
+#define PERIPH_BASE_AHB (PERIPH_BASE + 0x20000)
+
+/* Register boundary addresses */
+
+/* APB1 */
+#define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000)
+#define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400)
+#define TIM4_BASE (PERIPH_BASE_APB1 + 0x0800)
+#define TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00)
+#define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000)
+#define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400)
+#define LCD_BASE (PERIPH_BASE_APB1 + 0x2400)
+#define RTC_BASE (PERIPH_BASE_APB1 + 0x2800)
+#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00)
+#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000)
+/* PERIPH_BASE_APB1 + 0x3400 (0x4000 3400 - 0x4000 37FF): Reserved */
+#define SPI2_BASE (PERIPH_BASE_APB1 + 0x3800)
+// datasheet has an error? here
+#define SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00)
+/* PERIPH_BASE_APB1 + 0x4000 (0x4000 4000 - 0x4000 3FFF): Reserved */
+#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400)
+#define USART3_BASE (PERIPH_BASE_APB1 + 0x4800)
+#define USART4_BASE (PERIPH_BASE_APB1 + 0x4c00)
+#define USART5_BASE (PERIPH_BASE_APB1 + 0x5000)
+#define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400)
+#define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800)
+#define USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x5c00)
+#define USB_SRAM_BASE (PERIPH_BASE_APB1 + 0x6000)
+/* gap */
+#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)
+#define DAC_BASE (PERIPH_BASE_APB1 + 0x7400)
+#define COMP_BASE (PERIPH_BASE_APB1 + 0x7c00)
+#define ROUTING_BASE (PERIPH_BASE_APB1 + 0x7c04)
+
+/* APB2 */
+#define SYSCFG_BASE (PERIPH_BASE_APB2 + 0x0000)
+#define EXTI_BASE (PERIPH_BASE_APB2 + 0x0400)
+#define TIM9_BASE (PERIPH_BASE_APB2 + 0x0800)
+#define TIM10_BASE (PERIPH_BASE_APB2 + 0x0c00)
+#define TIM11_BASE (PERIPH_BASE_APB2 + 0x1000)
+/* gap */
+#define ADC_BASE (PERIPH_BASE_APB2 + 0x2400)
+/* gap */
+#define SDIO_BASE (PERIPH_BASE_APB2 + 0x2c00)
+#define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000)
+/* gap */
+#define USART1_BASE (PERIPH_BASE_APB2 + 0x3800)
+
+/* AHB */
+#define GPIO_PORT_A_BASE (PERIPH_BASE_AHB + 0x00000)
+#define GPIO_PORT_B_BASE (PERIPH_BASE_AHB + 0x00400)
+#define GPIO_PORT_C_BASE (PERIPH_BASE_AHB + 0x00800)
+#define GPIO_PORT_D_BASE (PERIPH_BASE_AHB + 0x00c00)
+#define GPIO_PORT_E_BASE (PERIPH_BASE_AHB + 0x01000)
+#define GPIO_PORT_H_BASE (PERIPH_BASE_AHB + 0x01400)
+/* gap */
+#define CRC_BASE (PERIPH_BASE_AHB + 0x03000)
+/* gap */
+#define RCC_BASE (PERIPH_BASE_AHB + 0x03800)
+#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB + 0x03c00)
+/* gap */
+#define DMA_BASE (PERIPH_BASE_AHB + 0x06000)
+
+/* PPIB */
+#define DBGMCU_BASE (PPBI_BASE + 0x00042000)
+
+/* FSMC */
+#define FSMC_BASE (PERIPH_BASE + 0x60000000)
+/* AES */
+#define AES_BASE (PERIPH_BASE + 0x10000000)
+
+/* Device Electronic Signature */
+#define DESIG_FLASH_SIZE_BASE (INFO_BASE + 0x8004C)
+#define DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x80050)
+
+#endif
diff --git a/include/libopencm3/stm32/l1/rcc.h b/include/libopencm3/stm32/l1/rcc.h
new file mode 100644
index 0000000..209d24f
--- /dev/null
+++ b/include/libopencm3/stm32/l1/rcc.h
@@ -0,0 +1,408 @@
+/** @file
+
+@ingroup STM32L1xx
+
+@brief <b>libopencm3 STM32L1xx Reset and Clock Control</b>
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2009 Federico Ruiz-Ugalde \<memeruiz at gmail dot com\>
+@author @htmlonly &copy; @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
+@author @htmlonly &copy; @endhtmlonly 2012 Karl Palsson <karlp@tweak.net.au>
+
+@date 18 May 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+/** @defgroup STM32L1xx_rcc_defines
+
+@brief Defined Constants and Types for the STM32L1xx Reset and Clock Control
+
+@ingroup STM32L1xx_defines
+
+LGPL License Terms @ref lgpl_license
+
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+ * Copyright (C) 2009 Federico Ruiz-Ugalde <memeruiz at gmail dot com>
+ * Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ *
+ * Originally based on the F1 code, as it seemed most similar to the L1
+ * TODO: very incomplete still!
+ */
+
+#ifndef LIBOPENCM3_RCC_H
+#define LIBOPENCM3_RCC_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/* --- RCC registers ------------------------------------------------------- */
+
+#define RCC_CR MMIO32(RCC_BASE + 0x00)
+#define RCC_ICSCR MMIO32(RCC_BASE + 0x04)
+#define RCC_CFGR MMIO32(RCC_BASE + 0x08)
+#define RCC_CIR MMIO32(RCC_BASE + 0x0c)
+#define RCC_AHBRSTR MMIO32(RCC_BASE + 0x10)
+#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x14)
+#define RCC_APB1RSTR MMIO32(RCC_BASE + 0x18)
+#define RCC_AHBENR MMIO32(RCC_BASE + 0x1c)
+#define RCC_APB2ENR MMIO32(RCC_BASE + 0x20)
+#define RCC_APB1ENR MMIO32(RCC_BASE + 0x24)
+#define RCC_AHBLPENR MMIO32(RCC_BASE + 0x28)
+#define RCC_APB2LPENR MMIO32(RCC_BASE + 0x2c)
+#define RCC_APB1LPENR MMIO32(RCC_BASE + 0x30)
+#define RCC_CSR MMIO32(RCC_BASE + 0x34)
+
+/* --- RCC_CR values ------------------------------------------------------- */
+
+/* RTCPRE[1:0] at 30:29 */
+#define RCC_CR_CSSON (1 << 28)
+#define RCC_CR_PLLRDY (1 << 25)
+#define RCC_CR_PLLON (1 << 24)
+#define RCC_CR_HSEBYP (1 << 18)
+#define RCC_CR_HSERDY (1 << 17)
+#define RCC_CR_HSEON (1 << 16)
+#define RCC_CR_MSIRDY (1 << 9)
+#define RCC_CR_MSION (1 << 8)
+#define RCC_CR_HSIRDY (1 << 1)
+#define RCC_CR_HSION (1 << 0)
+
+#define RCC_CR_RTCPRE_DIV2 0
+#define RCC_CR_RTCPRE_DIV4 1
+#define RCC_CR_RTCPRE_DIV8 2
+#define RCC_CR_RTCPRE_DIV18 3
+
+/* --- RCC_ICSCR values ---------------------------------------------------- */
+
+// TODO
+
+/* --- RCC_CFGR values ----------------------------------------------------- */
+
+/* MCOPRE */
+#define RCC_CFGR_MCOPRE_DIV1 0
+#define RCC_CFGR_MCOPRE_DIV2 1
+#define RCC_CFGR_MCOPRE_DIV4 2
+#define RCC_CFGR_MCOPRE_DIV8 3
+#define RCC_CFGR_MCOPRE_DIV16 4
+
+/* MCO: Microcontroller clock output */
+#define RCC_CFGR_MCO_NOCLK 0x0
+#define RCC_CFGR_MCO_SYSCLK 0x1
+#define RCC_CFGR_MCO_HSICLK 0x2
+#define RCC_CFGR_MCO_MSICLK 0x3
+#define RCC_CFGR_MCO_HSECLK 0x4
+#define RCC_CFGR_MCO_PLLCLK 0x5
+#define RCC_CFGR_MCO_LSICLK 0x6
+#define RCC_CFGR_MCO_LSECLK 0x7
+
+/* PLL Output division selection */
+#define RCC_CFGR_PLLDIV_DIV2 0x1
+#define RCC_CFGR_PLLDIV_DIV3 0x2
+#define RCC_CFGR_PLLDIV_DIV4 0x3
+
+/* PLLMUL: PLL multiplication factor */
+#define RCC_CFGR_PLLMUL_MUL3 0x0
+#define RCC_CFGR_PLLMUL_MUL4 0x1
+#define RCC_CFGR_PLLMUL_MUL6 0x2
+#define RCC_CFGR_PLLMUL_MUL8 0x3
+#define RCC_CFGR_PLLMUL_MUL12 0x4
+#define RCC_CFGR_PLLMUL_MUL16 0x5
+#define RCC_CFGR_PLLMUL_MUL24 0x6
+#define RCC_CFGR_PLLMUL_MUL32 0x7
+#define RCC_CFGR_PLLMUL_MUL48 0x8
+
+/* PLLSRC: PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSI_CLK 0x0
+#define RCC_CFGR_PLLSRC_HSE_CLK 0x1
+
+/* PPRE2: APB high-speed prescaler (APB2) */
+#define RCC_CFGR_PPRE2_HCLK_NODIV 0x0
+#define RCC_CFGR_PPRE2_HCLK_DIV2 0x4
+#define RCC_CFGR_PPRE2_HCLK_DIV4 0x5
+#define RCC_CFGR_PPRE2_HCLK_DIV8 0x6
+#define RCC_CFGR_PPRE2_HCLK_DIV16 0x7
+
+/* PPRE1: APB low-speed prescaler (APB1) */
+#define RCC_CFGR_PPRE1_HCLK_NODIV 0x0
+#define RCC_CFGR_PPRE1_HCLK_DIV2 0x4
+#define RCC_CFGR_PPRE1_HCLK_DIV4 0x5
+#define RCC_CFGR_PPRE1_HCLK_DIV8 0x6
+#define RCC_CFGR_PPRE1_HCLK_DIV16 0x7
+
+/* HPRE: AHB prescaler */
+#define RCC_CFGR_HPRE_SYSCLK_NODIV 0x0
+#define RCC_CFGR_HPRE_SYSCLK_DIV2 0x8
+#define RCC_CFGR_HPRE_SYSCLK_DIV4 0x9
+#define RCC_CFGR_HPRE_SYSCLK_DIV8 0xa
+#define RCC_CFGR_HPRE_SYSCLK_DIV16 0xb
+#define RCC_CFGR_HPRE_SYSCLK_DIV64 0xc
+#define RCC_CFGR_HPRE_SYSCLK_DIV128 0xd
+#define RCC_CFGR_HPRE_SYSCLK_DIV256 0xe
+#define RCC_CFGR_HPRE_SYSCLK_DIV512 0xf
+
+/* SWS: System clock switch status */
+#define RCC_CFGR_SWS_SYSCLKSEL_MSICLK 0x0
+#define RCC_CFGR_SWS_SYSCLKSEL_HSICLK 0x1
+#define RCC_CFGR_SWS_SYSCLKSEL_HSECLK 0x2
+#define RCC_CFGR_SWS_SYSCLKSEL_PLLCLK 0x3
+
+/* SW: System clock switch */
+#define RCC_CFGR_SW_SYSCLKSEL_MSICLK 0x0
+#define RCC_CFGR_SW_SYSCLKSEL_HSICLK 0x1
+#define RCC_CFGR_SW_SYSCLKSEL_HSECLK 0x2
+#define RCC_CFGR_SW_SYSCLKSEL_PLLCLK 0x3
+
+/* --- RCC_CIR values ------------------------------------------------------ */
+
+/* Clock security system interrupt clear bit */
+#define RCC_CIR_CSSC (1 << 23)
+
+/* OSC ready interrupt clear bits */
+#define RCC_CIR_MSIRDYC (1 << 21)
+#define RCC_CIR_PLLRDYC (1 << 20)
+#define RCC_CIR_HSERDYC (1 << 19)
+#define RCC_CIR_HSIRDYC (1 << 18)
+#define RCC_CIR_LSERDYC (1 << 17)
+#define RCC_CIR_LSIRDYC (1 << 16)
+
+/* OSC ready interrupt enable bits */
+#define RCC_CIR_MSIRDYIE (1 << 13)
+#define RCC_CIR_PLLRDYIE (1 << 12)
+#define RCC_CIR_HSERDYIE (1 << 11)
+#define RCC_CIR_HSIRDYIE (1 << 10)
+#define RCC_CIR_LSERDYIE (1 << 9)
+#define RCC_CIR_LSIRDYIE (1 << 8)
+
+/* Clock security system interrupt flag bit */
+#define RCC_CIR_CSSF (1 << 7)
+
+/* OSC ready interrupt flag bits */
+#define RCC_CIR_MSIRDYF (1 << 5) /* (**) */
+#define RCC_CIR_PLLRDYF (1 << 4)
+#define RCC_CIR_HSERDYF (1 << 3)
+#define RCC_CIR_HSIRDYF (1 << 2)
+#define RCC_CIR_LSERDYF (1 << 1)
+#define RCC_CIR_LSIRDYF (1 << 0)
+
+/* --- RCC_AHBRSTR values ------------------------------------------------- */
+#define RCC_AHBRSTR_DMA1RST (1 << 24)
+#define RCC_AHBRSTR_FLITFRST (1 << 15)
+#define RCC_AHBRSTR_CRCRST (1 << 12)
+#define RCC_AHBRSTR_GPIOHRST (1 << 5)
+#define RCC_AHBRSTR_GPIOERST (1 << 4)
+#define RCC_AHBRSTR_GPIODRST (1 << 3)
+#define RCC_AHBRSTR_GPIOCRST (1 << 2)
+#define RCC_AHBRSTR_GPIOBRST (1 << 1)
+#define RCC_AHBRSTR_GPIOARST (1 << 0)
+
+/* --- RCC_APB2RSTR values ------------------------------------------------- */
+
+#define RCC_APB2RSTR_USART1RST (1 << 14)
+#define RCC_APB2RSTR_SPI1RST (1 << 12)
+#define RCC_APB2RSTR_ADC1RST (1 << 9)
+#define RCC_APB2RSTR_TIM11RST (1 << 4)
+#define RCC_APB2RSTR_TIM10RST (1 << 3)
+#define RCC_APB2RSTR_TIM9RST (1 << 2)
+#define RCC_APB2RSTR_SYSCFGRST (1 << 0)
+
+/* --- RCC_APB1RSTR values ------------------------------------------------- */
+
+#define RCC_APB1RSTR_COMPRST (1 << 31)
+#define RCC_APB1RSTR_DACRST (1 << 29)
+#define RCC_APB1RSTR_PWRRST (1 << 28)
+#define RCC_APB1RSTR_USBRST (1 << 23)
+#define RCC_APB1RSTR_I2C2RST (1 << 22)
+#define RCC_APB1RSTR_I2C1RST (1 << 21)
+#define RCC_APB1RSTR_USART3RST (1 << 18)
+#define RCC_APB1RSTR_USART2RST (1 << 17)
+#define RCC_APB1RSTR_SPI2RST (1 << 14)
+#define RCC_APB1RSTR_WWDGRST (1 << 11)
+#define RCC_APB1RSTR_LCDRST (1 << 9)
+#define RCC_APB1RSTR_TIM7RST (1 << 5)
+#define RCC_APB1RSTR_TIM6RST (1 << 4)
+#define RCC_APB1RSTR_TIM4RST (1 << 2)
+#define RCC_APB1RSTR_TIM3RST (1 << 1)
+#define RCC_APB1RSTR_TIM2RST (1 << 0)
+
+/* --- RCC_AHBENR values --------------------------------------------------- */
+
+/** @defgroup rcc_ahbenr_en RCC_AHBENR enable values
+@ingroup STM32L1xx_rcc_defines
+
+@{*/
+#define RCC_AHBENR_DMA1EN (1 << 24)
+#define RCC_AHBENR_FLITFEN (1 << 15)
+#define RCC_AHBENR_CRCEN (1 << 12)
+#define RCC_AHBENR_GPIOHEN (1 << 5)
+#define RCC_AHBENR_GPIOEEN (1 << 4)
+#define RCC_AHBENR_GPIODEN (1 << 3)
+#define RCC_AHBENR_GPIOCEN (1 << 2)
+#define RCC_AHBENR_GPIOBEN (1 << 1)
+#define RCC_AHBENR_GPIOAEN (1 << 0)
+/*@}*/
+
+/* --- RCC_APB2ENR values -------------------------------------------------- */
+
+/** @defgroup rcc_apb2enr_en RCC_APB2ENR enable values
+@ingroup STM32L1xx_rcc_defines
+
+@{*/
+#define RCC_APB2ENR_USART1EN (1 << 14)
+#define RCC_APB2ENR_SPI1EN (1 << 12)
+#define RCC_APB2ENR_ADC1EN (1 << 9)
+#define RCC_APB2ENR_TIM11EN (1 << 4)
+#define RCC_APB2ENR_TIM10EN (1 << 3)
+#define RCC_APB2ENR_TIM9EN (1 << 2)
+#define RCC_APB2ENR_SYSCFGEN (1 << 0)
+/*@}*/
+
+/* --- RCC_APB1ENR values -------------------------------------------------- */
+
+/** @defgroup rcc_apb1enr_en RCC_APB1ENR enable values
+@ingroup STM32L1xx_rcc_defines
+
+@{*/
+#define RCC_APB1ENR_COMPEN (1 << 31)
+#define RCC_APB1ENR_DACEN (1 << 29)
+#define RCC_APB1ENR_PWREN (1 << 28)
+#define RCC_APB1ENR_USBEN (1 << 23)
+#define RCC_APB1ENR_I2C2EN (1 << 22)
+#define RCC_APB1ENR_I2C1EN (1 << 21)
+#define RCC_APB1ENR_USART3EN (1 << 18)
+#define RCC_APB1ENR_USART2EN (1 << 17)
+#define RCC_APB1ENR_SPI2EN (1 << 14)
+#define RCC_APB1ENR_WWDGEN (1 << 11)
+#define RCC_APB1ENR_LCDEN (1 << 9)
+#define RCC_APB1ENR_TIM7EN (1 << 5)
+#define RCC_APB1ENR_TIM6EN (1 << 4)
+#define RCC_APB1ENR_TIM4EN (1 << 2)
+#define RCC_APB1ENR_TIM3EN (1 << 1)
+#define RCC_APB1ENR_TIM2EN (1 << 0)
+/*@}*/
+
+/* --- RCC_AHBLPENR -------------------------------------------------------- */
+#define RCC_AHBLPENR_DMA1LPEN (1 << 24)
+#define RCC_AHBLPENR_SRAMLPEN (1 << 16)
+#define RCC_AHBLPENR_FLITFLPEN (1 << 15)
+#define RCC_AHBLPENR_CRCLPEN (1 << 12)
+#define RCC_AHBLPENR_GPIOHLPEN (1 << 5)
+#define RCC_AHBLPENR_GPIOELPEN (1 << 4)
+#define RCC_AHBLPENR_GPIODLPEN (1 << 3)
+#define RCC_AHBLPENR_GPIOCLPEN (1 << 2)
+#define RCC_AHBLPENR_GPIOBLPEN (1 << 1)
+#define RCC_AHBLPENR_GPIOALPEN (1 << 0)
+
+#define RCC_APB2LPENR_USART1LPEN (1 << 14)
+#define RCC_APB2LPENR_SPI1LPEN (1 << 12)
+#define RCC_APB2LPENR_ADC1LPEN (1 << 9)
+#define RCC_APB2LPENR_TIM11LPEN (1 << 4)
+#define RCC_APB2LPENR_TIM10LPEN (1 << 3)
+#define RCC_APB2LPENR_TIM9LPEN (1 << 2)
+#define RCC_APB2LPENR_SYSCFGLPEN (1 << 0)
+
+#define RCC_APB1LPENR_COMPLPEN (1 << 31)
+#define RCC_APB1LPENR_DACLPEN (1 << 29)
+#define RCC_APB1LPENR_PWRLPEN (1 << 28)
+#define RCC_APB1LPENR_USBLPEN (1 << 23)
+#define RCC_APB1LPENR_I2C2LPEN (1 << 22)
+#define RCC_APB1LPENR_I2C1LPEN (1 << 21)
+#define RCC_APB1LPENR_USART3LPEN (1 << 18)
+#define RCC_APB1LPENR_USART2LPEN (1 << 17)
+#define RCC_APB1LPENR_SPI2LPEN (1 << 14)
+#define RCC_APB1LPENR_WWDGLPEN (1 << 11)
+#define RCC_APB1LPENR_LCDLPEN (1 << 9)
+#define RCC_APB1LPENR_TIM7LPEN (1 << 5)
+#define RCC_APB1LPENR_TIM6LPEN (1 << 4)
+#define RCC_APB1LPENR_TIM4LPEN (1 << 2)
+#define RCC_APB1LPENR_TIM3LPEN (1 << 1)
+#define RCC_APB1LPENR_TIM2LPEN (1 << 0)
+
+
+/* --- RCC_CSR values ------------------------------------------------------ */
+
+#define RCC_CSR_LPWRRSTF (1 << 31)
+#define RCC_CSR_WWDGRSTF (1 << 30)
+#define RCC_CSR_IWDGRSTF (1 << 29)
+#define RCC_CSR_SFTRSTF (1 << 28)
+#define RCC_CSR_PORRSTF (1 << 27)
+#define RCC_CSR_PINRSTF (1 << 26)
+#define RCC_CSR_OBLRSTF (1 << 25)
+#define RCC_CSR_RMVF (1 << 24)
+#define RCC_CSR_RTCRST (1 << 23)
+#define RCC_CSR_RTCEN (1 << 22)
+/* RTCSEL[1:0] */
+#define RCC_CSR_LSEBYP (1 << 10)
+#define RCC_CSR_LSERDY (1 << 9)
+#define RCC_CSR_LSEON (1 << 8)
+#define RCC_CSR_LSIRDY (1 << 1)
+#define RCC_CSR_LSION (1 << 0)
+
+
+/* --- Variable definitions ------------------------------------------------ */
+extern u32 rcc_ppre1_frequency;
+extern u32 rcc_ppre2_frequency;
+
+/* --- Function prototypes ------------------------------------------------- */
+
+typedef enum {
+ PLL, HSE, HSI, MSI, LSE, LSI
+} osc_t;
+
+void rcc_osc_ready_int_clear(osc_t osc);
+void rcc_osc_ready_int_enable(osc_t osc);
+void rcc_osc_ready_int_disable(osc_t osc);
+int rcc_osc_ready_int_flag(osc_t osc);
+void rcc_css_int_clear(void);
+int rcc_css_int_flag(void);
+void rcc_wait_for_osc_ready(osc_t osc);
+void rcc_osc_on(osc_t osc);
+void rcc_osc_off(osc_t osc);
+void rcc_css_enable(void);
+void rcc_css_disable(void);
+void rcc_osc_bypass_enable(osc_t osc);
+void rcc_osc_bypass_disable(osc_t osc);
+void rcc_peripheral_enable_clock(volatile u32 *reg, u32 en);
+void rcc_peripheral_disable_clock(volatile u32 *reg, u32 en);
+void rcc_peripheral_reset(volatile u32 *reg, u32 reset);
+void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset);
+void rcc_set_sysclk_source(u32 clk);
+void rcc_set_pll_multiplication_factor(u32 mul);
+void rcc_set_pll_source(u32 pllsrc);
+void rcc_set_pllxtpre(u32 pllxtpre);
+void rcc_set_adcpre(u32 adcpre);
+void rcc_set_ppre2(u32 ppre2);
+void rcc_set_ppre1(u32 ppre1);
+void rcc_set_hpre(u32 hpre);
+void rcc_set_usbpre(u32 usbpre);
+u32 rcc_get_system_clock_source(int i);
+void rcc_clock_setup_in_hsi_out_64mhz(void);
+void rcc_clock_setup_in_hsi_out_48mhz(void);
+
+/**
+ * Maximum speed possible for F100 (Value Line) on HSI
+ */
+void rcc_clock_setup_in_hsi_out_24mhz(void);
+void rcc_clock_setup_in_hse_8mhz_out_24mhz(void);
+void rcc_clock_setup_in_hse_8mhz_out_72mhz(void);
+void rcc_clock_setup_in_hse_12mhz_out_72mhz(void);
+void rcc_clock_setup_in_hse_16mhz_out_72mhz(void);
+void rcc_backupdomain_reset(void);
+
+#endif
diff --git a/include/libopencm3/stm32/memorymap.h b/include/libopencm3/stm32/memorymap.h
index 6f213da..9b757ce 100644
--- a/include/libopencm3/stm32/memorymap.h
+++ b/include/libopencm3/stm32/memorymap.h
@@ -26,6 +26,8 @@
# include <libopencm3/stm32/f2/memorymap.h>
#elif defined(STM32F4)
# include <libopencm3/stm32/f4/memorymap.h>
+#elif defined(STM32L1)
+# include <libopencm3/stm32/l1/memorymap.h>
#else
# error "stm32 family not defined."
#endif
diff --git a/include/libopencm3/stm32/otg_fs.h b/include/libopencm3/stm32/otg_fs.h
index 5680e43..d8ee393 100644
--- a/include/libopencm3/stm32/otg_fs.h
+++ b/include/libopencm3/stm32/otg_fs.h
@@ -24,7 +24,7 @@
#include <libopencm3/cm3/common.h>
/* Core Global Control and Status Registers */
-#define OTG_FS_OTGCTL MMIO32(USB_OTG_FS_BASE + 0x000)
+#define OTG_FS_GOTGCTL MMIO32(USB_OTG_FS_BASE + 0x000)
#define OTG_FS_GOTGINT MMIO32(USB_OTG_FS_BASE + 0x004)
#define OTG_FS_GAHBCFG MMIO32(USB_OTG_FS_BASE + 0x008)
#define OTG_FS_GUSBCFG MMIO32(USB_OTG_FS_BASE + 0x00C)
@@ -42,40 +42,40 @@
#define OTG_FS_DIEPTXF(x) MMIO32(USB_OTG_FS_BASE + 0x104 + 4*(x-1))
/* Host-mode Control and Status Registers */
-#define OTG_FS_HCFG MMIO32(USB_OTG_FS_BASE + 0x400)
-#define OTG_FS_HFIR MMIO32(USB_OTG_FS_BASE + 0x404)
-#define OTG_FS_HFNUM MMIO32(USB_OTG_FS_BASE + 0x408)
-#define OTG_FS_HPTXSTS MMIO32(USB_OTG_FS_BASE + 0x410)
-#define OTG_FS_HAINT MMIO32(USB_OTG_FS_BASE + 0x414)
-#define OTG_FS_HAINTMSK MMIO32(USB_OTG_FS_BASE + 0x418)
-#define OTG_FS_HPRT MMIO32(USB_OTG_FS_BASE + 0x440)
-#define OTG_FS_HCCHARx MMIO32(USB_OTG_FS_BASE + 0x500)
-#define OTG_FS_HCINTx MMIO32(USB_OTG_FS_BASE + 0x508)
-#define OTG_FS_HCINTMSKx MMIO32(USB_OTG_FS_BASE + 0x50C)
-#define OTG_FS_HCTSIZx MMIO32(USB_OTG_FS_BASE + 0x510)
+#define OTG_FS_HCFG MMIO32(USB_OTG_FS_BASE + 0x400)
+#define OTG_FS_HFIR MMIO32(USB_OTG_FS_BASE + 0x404)
+#define OTG_FS_HFNUM MMIO32(USB_OTG_FS_BASE + 0x408)
+#define OTG_FS_HPTXSTS MMIO32(USB_OTG_FS_BASE + 0x410)
+#define OTG_FS_HAINT MMIO32(USB_OTG_FS_BASE + 0x414)
+#define OTG_FS_HAINTMSK MMIO32(USB_OTG_FS_BASE + 0x418)
+#define OTG_FS_HPRT MMIO32(USB_OTG_FS_BASE + 0x440)
+#define OTG_FS_HCCHARx MMIO32(USB_OTG_FS_BASE + 0x500)
+#define OTG_FS_HCINTx MMIO32(USB_OTG_FS_BASE + 0x508)
+#define OTG_FS_HCINTMSKx MMIO32(USB_OTG_FS_BASE + 0x50C)
+#define OTG_FS_HCTSIZx MMIO32(USB_OTG_FS_BASE + 0x510)
/* Device-mode Control and Status Registers */
-#define OTG_FS_DCFG MMIO32(USB_OTG_FS_BASE + 0x800)
-#define OTG_FS_DCTL MMIO32(USB_OTG_FS_BASE + 0x804)
-#define OTG_FS_DSTS MMIO32(USB_OTG_FS_BASE + 0x808)
-#define OTG_FS_DIEPMSK MMIO32(USB_OTG_FS_BASE + 0x810)
-#define OTG_FS_DOEPMSK MMIO32(USB_OTG_FS_BASE + 0x814)
-#define OTG_FS_DAINT MMIO32(USB_OTG_FS_BASE + 0x818)
-#define OTG_FS_DAINTMSK MMIO32(USB_OTG_FS_BASE + 0x81C)
-#define OTG_FS_DVBUSDIS MMIO32(USB_OTG_FS_BASE + 0x828)
-#define OTG_FS_DVBUSPULSE MMIO32(USB_OTG_FS_BASE + 0x82C)
-#define OTG_FS_DIEPEMPMSK MMIO32(USB_OTG_FS_BASE + 0x834)
-#define OTG_FS_DIEPCTL0 MMIO32(USB_OTG_FS_BASE + 0x900)
-#define OTG_FS_DIEPCTL(x) MMIO32(USB_OTG_FS_BASE + 0x900 + 0x20*(x))
-#define OTG_FS_DOEPCTL0 MMIO32(USB_OTG_FS_BASE + 0xB00)
-#define OTG_FS_DOEPCTL(x) MMIO32(USB_OTG_FS_BASE + 0xB00 + 0x20*(x))
-#define OTG_FS_DIEPINT(x) MMIO32(USB_OTG_FS_BASE + 0x908 + 0x20*(x))
-#define OTG_FS_DOEPINT(x) MMIO32(USB_OTG_FS_BASE + 0xB08 + 0x20*(x))
-#define OTG_FS_DIEPTSIZ0 MMIO32(USB_OTG_FS_BASE + 0x910)
-#define OTG_FS_DOEPTSIZ0 MMIO32(USB_OTG_FS_BASE + 0xB10)
-#define OTG_FS_DIEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + 0x910 + 0x20*(x))
-#define OTG_FS_DTXFSTS(x) MMIO32(USB_OTG_FS_BASE + 0x918 + 0x20*(x))
-#define OTG_FS_DOEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + 0xB10 + 0x20*(x))
+#define OTG_FS_DCFG MMIO32(USB_OTG_FS_BASE + 0x800)
+#define OTG_FS_DCTL MMIO32(USB_OTG_FS_BASE + 0x804)
+#define OTG_FS_DSTS MMIO32(USB_OTG_FS_BASE + 0x808)
+#define OTG_FS_DIEPMSK MMIO32(USB_OTG_FS_BASE + 0x810)
+#define OTG_FS_DOEPMSK MMIO32(USB_OTG_FS_BASE + 0x814)
+#define OTG_FS_DAINT MMIO32(USB_OTG_FS_BASE + 0x818)
+#define OTG_FS_DAINTMSK MMIO32(USB_OTG_FS_BASE + 0x81C)
+#define OTG_FS_DVBUSDIS MMIO32(USB_OTG_FS_BASE + 0x828)
+#define OTG_FS_DVBUSPULSE MMIO32(USB_OTG_FS_BASE + 0x82C)
+#define OTG_FS_DIEPEMPMSK MMIO32(USB_OTG_FS_BASE + 0x834)
+#define OTG_FS_DIEPCTL0 MMIO32(USB_OTG_FS_BASE + 0x900)
+#define OTG_FS_DIEPCTL(x) MMIO32(USB_OTG_FS_BASE + 0x900 + 0x20*(x))
+#define OTG_FS_DOEPCTL0 MMIO32(USB_OTG_FS_BASE + 0xB00)
+#define OTG_FS_DOEPCTL(x) MMIO32(USB_OTG_FS_BASE + 0xB00 + 0x20*(x))
+#define OTG_FS_DIEPINT(x) MMIO32(USB_OTG_FS_BASE + 0x908 + 0x20*(x))
+#define OTG_FS_DOEPINT(x) MMIO32(USB_OTG_FS_BASE + 0xB08 + 0x20*(x))
+#define OTG_FS_DIEPTSIZ0 MMIO32(USB_OTG_FS_BASE + 0x910)
+#define OTG_FS_DOEPTSIZ0 MMIO32(USB_OTG_FS_BASE + 0xB10)
+#define OTG_FS_DIEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + 0x910 + 0x20*(x))
+#define OTG_FS_DTXFSTS(x) MMIO32(USB_OTG_FS_BASE + 0x918 + 0x20*(x))
+#define OTG_FS_DOEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + 0xB10 + 0x20*(x))
/* Power and clock gating control and status register */
#define OTG_FS_PCGCCTL MMIO32(USB_OTG_FS_BASE + 0xE00)
@@ -84,6 +84,18 @@
#define OTG_FS_FIFO(x) ((volatile u32*)(USB_OTG_FS_BASE + (((x) + 1) << 12)))
/* Global CSRs */
+/* OTG_FS USB control registers (OTG_HS_GOTGCTL) */
+#define OTG_FS_GOTGCTL_BSVLD (1 << 19)
+#define OTG_FS_GOTGCTL_ASVLD (1 << 18)
+#define OTG_FS_GOTGCTL_DBCT (1 << 17)
+#define OTG_FS_GOTGCTL_CIDSTS (1 << 16)
+#define OTG_FS_GOTGCTL_DHNPEN (1 << 11)
+#define OTG_FS_GOTGCTL_HSHNPEN (1 << 10)
+#define OTG_FS_GOTGCTL_HNPRQ (1 << 9)
+#define OTG_FS_GOTGCTL_HNGSCS (1 << 8)
+#define OTG_FS_GOTGCTL_SRQ (1 << 1)
+#define OTG_FS_GOTGCTL_SRQSCS (1 << 0)
+
/* OTG_FS AHB configuration register (OTG_FS_GAHBCFG) */
#define OTG_FS_GAHBCFG_GINT 0x0001
#define OTG_FS_GAHBCFG_TXFELVL 0x0080
@@ -175,20 +187,20 @@
/* OTG_FS Receive Status Pop Register (OTG_FS_GRXSTSP) */
/* Bits 31:25 - Reserved */
-#define OTG_FS_GRXSTSP_FRMNUM_MASK (0xf << 21)
-#define OTG_FS_GRXSTSP_PKTSTS_MASK (0xf << 17)
-#define OTG_FS_GRXSTSP_PKTSTS_GOUTNAK (0x1 << 17)
-#define OTG_FS_GRXSTSP_PKTSTS_OUT (0x2 << 17)
-#define OTG_FS_GRXSTSP_PKTSTS_OUT_COMP (0x3 << 17)
+#define OTG_FS_GRXSTSP_FRMNUM_MASK (0xf << 21)
+#define OTG_FS_GRXSTSP_PKTSTS_MASK (0xf << 17)
+#define OTG_FS_GRXSTSP_PKTSTS_GOUTNAK (0x1 << 17)
+#define OTG_FS_GRXSTSP_PKTSTS_OUT (0x2 << 17)
+#define OTG_FS_GRXSTSP_PKTSTS_OUT_COMP (0x3 << 17)
#define OTG_FS_GRXSTSP_PKTSTS_SETUP_COMP (0x4 << 17)
-#define OTG_FS_GRXSTSP_PKTSTS_SETUP (0x6 << 17)
-#define OTG_FS_GRXSTSP_DPID_MASK (0x3 << 15)
-#define OTG_FS_GRXSTSP_DPID_DATA0 (0x0 << 15)
-#define OTG_FS_GRXSTSP_DPID_DATA1 (0x2 << 15)
-#define OTG_FS_GRXSTSP_DPID_DATA2 (0x1 << 15)
-#define OTG_FS_GRXSTSP_DPID_MDATA (0x3 << 15)
-#define OTG_FS_GRXSTSP_BCNT_MASK (0x7ff << 4)
-#define OTG_FS_GRXSTSP_EPNUM_MASK (0xf << 0)
+#define OTG_FS_GRXSTSP_PKTSTS_SETUP (0x6 << 17)
+#define OTG_FS_GRXSTSP_DPID_MASK (0x3 << 15)
+#define OTG_FS_GRXSTSP_DPID_DATA0 (0x0 << 15)
+#define OTG_FS_GRXSTSP_DPID_DATA1 (0x2 << 15)
+#define OTG_FS_GRXSTSP_DPID_DATA2 (0x1 << 15)
+#define OTG_FS_GRXSTSP_DPID_MDATA (0x3 << 15)
+#define OTG_FS_GRXSTSP_BCNT_MASK (0x7ff << 4)
+#define OTG_FS_GRXSTSP_EPNUM_MASK (0xf << 0)
/* OTG_FS general core configuration register (OTG_FS_GCCFG) */
/* Bits 31:21 - Reserved */
@@ -320,4 +332,3 @@
#define OTG_FS_DIEPSIZ0_XFRSIZ_MASK (0x7f << 0)
#endif
-
diff --git a/include/libopencm3/stm32/otg_hs.h b/include/libopencm3/stm32/otg_hs.h
new file mode 100644
index 0000000..2f59ddd
--- /dev/null
+++ b/include/libopencm3/stm32/otg_hs.h
@@ -0,0 +1,396 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Gareth McMullin <gareth@blacksphere.co.nz>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_OTG_HS_H
+#define LIBOPENCM3_OTG_HS_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/* Core Global Control and Status Registers */
+#define OTG_GOTGCTL 0x000
+#define OTG_GOTGIN 0x004
+#define OTG_GAHBCFG 0x008
+#define OTG_GUSBCFG 0x00C
+#define OTG_GRSTCTL 0x010
+#define OTG_GINTSTS 0x014
+#define OTG_GINTMSK 0x018
+#define OTG_GRXSTSR 0x01C
+#define OTG_GRXSTSP 0x020
+#define OTG_GRXFSIZ 0x024
+#define OTG_GNPTXFSIZ 0x028
+#define OTG_GNPTXSTS 0x02C
+#define OTG_GCCFG 0x038
+#define OTG_CID 0x03C
+#define OTG_HPTXFSIZ 0x100
+#define OTG_DIEPTXF(x) (0x104 + 4*(x-1))
+
+/* Host-mode Control and Status Registers */
+#define OTG_HCFG 0x400
+#define OTG_HFIR 0x404
+#define OTG_HFNUM 0x408
+#define OTG_HPTXSTS 0x410
+#define OTG_HAINT 0x414
+#define OTG_HAINTMSK 0x418
+#define OTG_HPRT 0x440
+#define OTG_HCCHARx 0x500
+#define OTG_HCINTx 0x508
+#define OTG_HCINTMSKx 0x50C
+#define OTG_HCTSIZx 0x510
+
+/* Device-mode Control and Status Registers */
+#define OTG_DCFG 0x800
+#define OTG_DCTL 0x804
+#define OTG_DSTS 0x808
+#define OTG_DIEPMSK 0x810
+#define OTG_DOEPMSK 0x814
+#define OTG_DAINT 0x818
+#define OTG_DAINTMSK 0x81C
+#define OTG_DVBUSDIS 0x828
+#define OTG_DVBUSPULSE 0x82C
+#define OTG_DIEPEMPMSK 0x834
+#define OTG_DIEPCTL0 0x900
+#define OTG_DIEPCTL(x) (0x900 + 0x20*(x))
+#define OTG_DOEPCTL0 0xB00
+#define OTG_DOEPCTL(x) (0xB00 + 0x20*(x))
+#define OTG_DIEPINT(x) (0x908 + 0x20*(x))
+#define OTG_DOEPINT(x) (0xB08 + 0x20*(x))
+#define OTG_DIEPTSIZ0 0x910
+#define OTG_DOEPTSIZ0 0xB10
+#define OTG_DIEPTSIZ(x) (0x910 + 0x20*(x))
+#define OTG_DTXFSTS(x) (0x918 + 0x20*(x))
+#define OTG_DOEPTSIZ(x) (0xB10 + 0x20*(x))
+
+/* Power and clock gating control and status register */
+#define OTG_PCGCCTL 0xE00
+
+/* Data FIFO */
+#define OTG_FIFO(x) (((x) + 1) << 12)
+
+/***********************************************************************/
+
+/* Core Global Control and Status Registers */
+#define OTG_HS_GOTGCTL MMIO32(USB_OTG_HS_BASE + OTG_GOTGCTL)
+#define OTG_HS_GOTGINT MMIO32(USB_OTG_HS_BASE + OTG_GOTGINT)
+#define OTG_HS_GAHBCFG MMIO32(USB_OTG_HS_BASE + OTG_GAHBCFG)
+#define OTG_HS_GUSBCFG MMIO32(USB_OTG_HS_BASE + OTG_GUSBCFG)
+#define OTG_HS_GRSTCTL MMIO32(USB_OTG_HS_BASE + OTG_GRSTCTL)
+#define OTG_HS_GINTSTS MMIO32(USB_OTG_HS_BASE + OTG_GINTSTS)
+#define OTG_HS_GINTMSK MMIO32(USB_OTG_HS_BASE + OTG_GINTMSK)
+#define OTG_HS_GRXSTSR MMIO32(USB_OTG_HS_BASE + OTG_GRXSTSR)
+#define OTG_HS_GRXSTSP MMIO32(USB_OTG_HS_BASE + OTG_GRXSTSP)
+#define OTG_HS_GRXFSIZ MMIO32(USB_OTG_HS_BASE + OTG_GRXFSIZ)
+#define OTG_HS_GNPTXFSIZ MMIO32(USB_OTG_HS_BASE + OTG_GNPTXFSIZ)
+#define OTG_HS_GNPTXSTS MMIO32(USB_OTG_HS_BASE + OTG_GNPTXSTS)
+#define OTG_HS_GCCFG MMIO32(USB_OTG_HS_BASE + OTG_GCCFG)
+#define OTG_HS_CID MMIO32(USB_OTG_HS_BASE + OTG_CID)
+#define OTG_HS_HPTXFSIZ MMIO32(USB_OTG_HS_BASE + OTG_HPTXFSIZ)
+#define OTG_HS_DIEPTXF(x) MMIO32(USB_OTG_HS_BASE + OTG_DIEPTXF(x))
+
+/* Host-mode Control and Status Registers */
+#define OTG_HS_HCFG MMIO32(USB_OTG_HS_BASE + OTG_HCFG)
+#define OTG_HS_HFIR MMIO32(USB_OTG_HS_BASE + OTG_HFIR)
+#define OTG_HS_HFNUM MMIO32(USB_OTG_HS_BASE + OTG_HFNUM)
+#define OTG_HS_HPTXSTS MMIO32(USB_OTG_HS_BASE + OTG_HPTXSTS)
+#define OTG_HS_HAINT MMIO32(USB_OTG_HS_BASE + OTG_HAINT)
+#define OTG_HS_HAINTMSK MMIO32(USB_OTG_HS_BASE + OTG_HAINTMSK)
+#define OTG_HS_HPRT MMIO32(USB_OTG_HS_BASE + OTG_HPRT)
+#define OTG_HS_HCCHARx MMIO32(USB_OTG_HS_BASE + OTG_HCCHARx)
+#define OTG_HS_HCINTx MMIO32(USB_OTG_HS_BASE + OTG_HCINTx)
+#define OTG_HS_HCINTMSKx MMIO32(USB_OTG_HS_BASE + OTG_HCINTMSKx)
+#define OTG_HS_HCTSIZx MMIO32(USB_OTG_HS_BASE + OTG_HCTSIZx)
+
+/* Device-mode Control and Status Registers */
+#define OTG_HS_DCFG MMIO32(USB_OTG_HS_BASE + OTG_DCFG)
+#define OTG_HS_DCTL MMIO32(USB_OTG_HS_BASE + OTG_DCTL)
+#define OTG_HS_DSTS MMIO32(USB_OTG_HS_BASE + OTG_DSTS)
+#define OTG_HS_DIEPMSK MMIO32(USB_OTG_HS_BASE + OTG_DIEPMSK)
+#define OTG_HS_DOEPMSK MMIO32(USB_OTG_HS_BASE + OTG_DOEPMSK)
+#define OTG_HS_DAINT MMIO32(USB_OTG_HS_BASE + OTG_DAINT)
+#define OTG_HS_DAINTMSK MMIO32(USB_OTG_HS_BASE + OTG_DAINTMSK)
+#define OTG_HS_DVBUSDIS MMIO32(USB_OTG_HS_BASE + OTG_DVBUSDIS)
+#define OTG_HS_DVBUSPULSE MMIO32(USB_OTG_HS_BASE + OTG_DVBUSPULSE)
+#define OTG_HS_DIEPEMPMSK MMIO32(USB_OTG_HS_BASE + OTG_DIEPEMPMSK)
+#define OTG_HS_DIEPCTL0 MMIO32(USB_OTG_HS_BASE + OTG_DIEPCTL0)
+#define OTG_HS_DIEPCTL(x) MMIO32(USB_OTG_HS_BASE + OTG_DIEPCTL(x))
+#define OTG_HS_DOEPCTL0 MMIO32(USB_OTG_HS_BASE + OTG_DOEPCTL0)
+#define OTG_HS_DOEPCTL(x) MMIO32(USB_OTG_HS_BASE + OTG_DOEPCTL(x))
+#define OTG_HS_DIEPINT(x) MMIO32(USB_OTG_HS_BASE + OTG_DIEPINT(x))
+#define OTG_HS_DOEPINT(x) MMIO32(USB_OTG_HS_BASE + OTG_DOEPINT(x))
+#define OTG_HS_DIEPTSIZ0 MMIO32(USB_OTG_HS_BASE + OTG_DIEPTSIZ0)
+#define OTG_HS_DOEPTSIZ0 MMIO32(USB_OTG_HS_BASE + OTG_DOEPTSIZ0)
+#define OTG_HS_DIEPTSIZ(x) MMIO32(USB_OTG_HS_BASE + OTG_DIEPTSIZ(x)))
+#define OTG_HS_DTXFSTS(x) MMIO32(USB_OTG_HS_BASE + OTG_DTXFSTS(x))
+#define OTG_HS_DOEPTSIZ(x) MMIO32(USB_OTG_HS_BASE + OTG_DOEPTSIZ(x))
+
+/* Power and clock gating control and status register */
+#define OTG_HS_PCGCCTL MMIO32(USB_OTG_HS_BASE + OTG_PCGCCTL)
+
+/* Data FIFO */
+#define OTG_HS_FIFO(x) ((volatile u32*)(USB_OTG_HS_BASE + OTG_FIFO(x)))
+
+/* Global CSRs */
+/* OTG_HS USB control registers (OTG_FS_GOTGCTL) */
+#define OTG_HS_GOTGCTL_BSVLD (1 << 19)
+#define OTG_HS_GOTGCTL_ASVLD (1 << 18)
+#define OTG_HS_GOTGCTL_DBCT (1 << 17)
+#define OTG_HS_GOTGCTL_CIDSTS (1 << 16)
+#define OTG_HS_GOTGCTL_DHNPEN (1 << 11)
+#define OTG_HS_GOTGCTL_HSHNPEN (1 << 10)
+#define OTG_HS_GOTGCTL_HNPRQ (1 << 9)
+#define OTG_HS_GOTGCTL_HNGSCS (1 << 8)
+#define OTG_HS_GOTGCTL_SRQ (1 << 1)
+#define OTG_HS_GOTGCTL_SRQSCS (1 << 0)
+
+/* OTG_FS AHB configuration register (OTG_HS_GAHBCFG) */
+#define OTG_HS_GAHBCFG_GINT 0x0001
+#define OTG_HS_GAHBCFG_TXFELVL 0x0080
+#define OTG_HS_GAHBCFG_PTXFELVL 0x0100
+
+/* OTG_FS USB configuration register (OTG_HS_GUSBCFG) */
+#define OTG_HS_GUSBCFG_TOCAL 0x00000003
+#define OTG_HS_GUSBCFG_SRPCAP 0x00000100
+#define OTG_HS_GUSBCFG_HNPCAP 0x00000200
+#define OTG_HS_GUSBCFG_TRDT_MASK (0xf << 10)
+#define OTG_HS_GUSBCFG_TRDT_16BIT (0x5 << 10)
+#define OTG_HS_GUSBCFG_TRDT_8BIT (0x9 << 10)
+#define OTG_HS_GUSBCFG_NPTXRWEN 0x00004000
+#define OTG_HS_GUSBCFG_FHMOD 0x20000000
+#define OTG_HS_GUSBCFG_FDMOD 0x40000000
+#define OTG_HS_GUSBCFG_CTXPKT 0x80000000
+#define OTG_HS_GUSBCFG_PHYSEL (1 << 6)
+
+/* OTG_FS reset register (OTG_HS_GRSTCTL) */
+#define OTG_HS_GRSTCTL_AHBIDL (1 << 31)
+/* Bits 30:11 - Reserved */
+#define OTG_HS_GRSTCTL_TXFNUM_MASK (0x1f << 6)
+#define OTG_HS_GRSTCTL_TXFFLSH (1 << 5)
+#define OTG_HS_GRSTCTL_RXFFLSH (1 << 4)
+/* Bit 3 - Reserved */
+#define OTG_HS_GRSTCTL_FCRST (1 << 2)
+#define OTG_HS_GRSTCTL_HSRST (1 << 1)
+#define OTG_HS_GRSTCTL_CSRST (1 << 0)
+
+/* OTG_FS interrupt status register (OTG_HS_GINTSTS) */
+#define OTG_HS_GINTSTS_WKUPINT (1 << 31)
+#define OTG_HS_GINTSTS_SRQINT (1 << 30)
+#define OTG_HS_GINTSTS_DISCINT (1 << 29)
+#define OTG_HS_GINTSTS_CIDSCHG (1 << 28)
+/* Bit 27 - Reserved */
+#define OTG_HS_GINTSTS_PTXFE (1 << 26)
+#define OTG_HS_GINTSTS_HCINT (1 << 25)
+#define OTG_HS_GINTSTS_HPRTINT (1 << 24)
+/* Bits 23:22 - Reserved */
+#define OTG_HS_GINTSTS_IPXFR (1 << 21)
+#define OTG_HS_GINTSTS_INCOMPISOOUT (1 << 21)
+#define OTG_HS_GINTSTS_IISOIXFR (1 << 20)
+#define OTG_HS_GINTSTS_OEPINT (1 << 19)
+#define OTG_HS_GINTSTS_IEPINT (1 << 18)
+/* Bits 17:16 - Reserved */
+#define OTG_HS_GINTSTS_EOPF (1 << 15)
+#define OTG_HS_GINTSTS_ISOODRP (1 << 14)
+#define OTG_HS_GINTSTS_ENUMDNE (1 << 13)
+#define OTG_HS_GINTSTS_USBRST (1 << 12)
+#define OTG_HS_GINTSTS_USBSUSP (1 << 11)
+#define OTG_HS_GINTSTS_ESUSP (1 << 10)
+/* Bits 9:8 - Reserved */
+#define OTG_HS_GINTSTS_GONAKEFF (1 << 7)
+#define OTG_HS_GINTSTS_GINAKEFF (1 << 6)
+#define OTG_HS_GINTSTS_NPTXFE (1 << 5)
+#define OTG_HS_GINTSTS_RXFLVL (1 << 4)
+#define OTG_HS_GINTSTS_SOF (1 << 3)
+#define OTG_HS_GINTSTS_OTGINT (1 << 2)
+#define OTG_HS_GINTSTS_MMIS (1 << 1)
+#define OTG_HS_GINTSTS_CMOD (1 << 0)
+
+/* OTG_FS interrupt mask register (OTG_HS_GINTMSK) */
+#define OTG_HS_GINTMSK_MMISM 0x00000002
+#define OTG_HS_GINTMSK_OTGINT 0x00000004
+#define OTG_HS_GINTMSK_SOFM 0x00000008
+#define OTG_HS_GINTMSK_RXFLVLM 0x00000010
+#define OTG_HS_GINTMSK_NPTXFEM 0x00000020
+#define OTG_HS_GINTMSK_GINAKEFFM 0x00000040
+#define OTG_HS_GINTMSK_GONAKEFFM 0x00000080
+#define OTG_HS_GINTMSK_ESUSPM 0x00000400
+#define OTG_HS_GINTMSK_USBSUSPM 0x00000800
+#define OTG_HS_GINTMSK_USBRST 0x00001000
+#define OTG_HS_GINTMSK_ENUMDNEM 0x00002000
+#define OTG_HS_GINTMSK_ISOODRPM 0x00004000
+#define OTG_HS_GINTMSK_EOPFM 0x00008000
+#define OTG_HS_GINTMSK_EPMISM 0x00020000
+#define OTG_HS_GINTMSK_IEPINT 0x00040000
+#define OTG_HS_GINTMSK_OEPINT 0x00080000
+#define OTG_HS_GINTMSK_IISOIXFRM 0x00100000
+#define OTG_HS_GINTMSK_IISOOXFRM 0x00200000
+#define OTG_HS_GINTMSK_IPXFRM 0x00200000
+#define OTG_HS_GINTMSK_PRTIM 0x01000000
+#define OTG_HS_GINTMSK_HCIM 0x02000000
+#define OTG_HS_GINTMSK_PTXFEM 0x04000000
+#define OTG_HS_GINTMSK_CIDSCHGM 0x10000000
+#define OTG_HS_GINTMSK_DISCINT 0x20000000
+#define OTG_HS_GINTMSK_SRQIM 0x40000000
+#define OTG_HS_GINTMSK_WUIM 0x80000000
+
+/* OTG_FS Receive Status Pop Register (OTG_HS_GRXSTSP) */
+/* Bits 31:25 - Reserved */
+#define OTG_HS_GRXSTSP_FRMNUM_MASK (0xf << 21)
+#define OTG_HS_GRXSTSP_PKTSTS_MASK (0xf << 17)
+#define OTG_HS_GRXSTSP_PKTSTS_GOUTNAK (0x1 << 17)
+#define OTG_HS_GRXSTSP_PKTSTS_OUT (0x2 << 17)
+#define OTG_HS_GRXSTSP_PKTSTS_OUT_COMP (0x3 << 17)
+#define OTG_HS_GRXSTSP_PKTSTS_SETUP_COMP (0x4 << 17)
+#define OTG_HS_GRXSTSP_PKTSTS_SETUP (0x6 << 17)
+#define OTG_HS_GRXSTSP_DPID_MASK (0x3 << 15)
+#define OTG_HS_GRXSTSP_DPID_DATA0 (0x0 << 15)
+#define OTG_HS_GRXSTSP_DPID_DATA1 (0x2 << 15)
+#define OTG_HS_GRXSTSP_DPID_DATA2 (0x1 << 15)
+#define OTG_HS_GRXSTSP_DPID_MDATA (0x3 << 15)
+#define OTG_HS_GRXSTSP_BCNT_MASK (0x7ff << 4)
+#define OTG_HS_GRXSTSP_EPNUM_MASK (0xf << 0)
+
+/* OTG_FS general core configuration register (OTG_HS_GCCFG) */
+/* Bits 31:21 - Reserved */
+#define OTG_HS_GCCFG_SOFOUTEN (1 << 20)
+#define OTG_HS_GCCFG_VBUSBSEN (1 << 19)
+#define OTG_HS_GCCFG_VBUSASEN (1 << 18)
+/* Bit 17 - Reserved */
+#define OTG_HS_GCCFG_PWRDWN (1 << 16)
+/* Bits 15:0 - Reserved */
+
+
+/* Device-mode CSRs */
+/* OTG_FS device control register (OTG_HS_DCTL) */
+/* Bits 31:12 - Reserved */
+#define OTG_HS_DCTL_POPRGDNE (1 << 11)
+#define OTG_HS_DCTL_CGONAK (1 << 10)
+#define OTG_HS_DCTL_SGONAK (1 << 9)
+#define OTG_HS_DCTL_SGINAK (1 << 8)
+#define OTG_HS_DCTL_TCTL_MASK (7 << 4)
+#define OTG_HS_DCTL_GONSTS (1 << 3)
+#define OTG_HS_DCTL_GINSTS (1 << 2)
+#define OTG_HS_DCTL_SDIS (1 << 1)
+#define OTG_HS_DCTL_RWUSIG (1 << 0)
+
+/* OTG_FS device configuration register (OTG_HS_DCFG) */
+#define OTG_HS_DCFG_DSPD 0x0003
+#define OTG_HS_DCFG_NZLSOHSK 0x0004
+#define OTG_HS_DCFG_DAD 0x07F0
+#define OTG_HS_DCFG_PFIVL 0x1800
+
+/* OTG_FS Device IN Endpoint Common Interrupt Mask Register (OTG_HS_DIEPMSK) */
+/* Bits 31:10 - Reserved */
+#define OTG_HS_DIEPMSK_BIM (1 << 9)
+#define OTG_HS_DIEPMSK_TXFURM (1 << 8)
+/* Bit 7 - Reserved */
+#define OTG_HS_DIEPMSK_INEPNEM (1 << 6)
+#define OTG_HS_DIEPMSK_INEPNMM (1 << 5)
+#define OTG_HS_DIEPMSK_ITTXFEMSK (1 << 4)
+#define OTG_HS_DIEPMSK_TOM (1 << 3)
+/* Bit 2 - Reserved */
+#define OTG_HS_DIEPMSK_EPDM (1 << 1)
+#define OTG_HS_DIEPMSK_XFRCM (1 << 0)
+
+/* OTG_FS Device OUT Endpoint Common Interrupt Mask Register (OTG_HS_DOEPMSK) */
+/* Bits 31:10 - Reserved */
+#define OTG_HS_DOEPMSK_BOIM (1 << 9)
+#define OTG_HS_DOEPMSK_OPEM (1 << 8)
+/* Bit 7 - Reserved */
+#define OTG_HS_DOEPMSK_B2BSTUP (1 << 6)
+/* Bit 5 - Reserved */
+#define OTG_HS_DOEPMSK_OTEPDM (1 << 4)
+#define OTG_HS_DOEPMSK_STUPM (1 << 3)
+/* Bit 2 - Reserved */
+#define OTG_HS_DOEPMSK_EPDM (1 << 1)
+#define OTG_HS_DOEPMSK_XFRCM (1 << 0)
+
+/* OTG_FS Device Control IN Endpoint 0 Control Register (OTG_HS_DIEPCTL0) */
+#define OTG_HS_DIEPCTL0_EPENA (1 << 31)
+#define OTG_HS_DIEPCTL0_EPDIS (1 << 30)
+/* Bits 29:28 - Reserved */
+#define OTG_HS_DIEPCTLX_SD0PID (1 << 28)
+#define OTG_HS_DIEPCTL0_SNAK (1 << 27)
+#define OTG_HS_DIEPCTL0_CNAK (1 << 26)
+#define OTG_HS_DIEPCTL0_TXFNUM_MASK (0xf << 22)
+#define OTG_HS_DIEPCTL0_STALL (1 << 21)
+/* Bit 20 - Reserved */
+#define OTG_HS_DIEPCTL0_EPTYP_MASK (0x3 << 18)
+#define OTG_HS_DIEPCTL0_NAKSTS (1 << 17)
+/* Bit 16 - Reserved */
+#define OTG_HS_DIEPCTL0_USBAEP (1 << 15)
+/* Bits 14:2 - Reserved */
+#define OTG_HS_DIEPCTL0_MPSIZ_MASK (0x3 << 0)
+#define OTG_HS_DIEPCTL0_MPSIZ_64 (0x0 << 0)
+#define OTG_HS_DIEPCTL0_MPSIZ_32 (0x1 << 0)
+#define OTG_HS_DIEPCTL0_MPSIZ_16 (0x2 << 0)
+#define OTG_HS_DIEPCTL0_MPSIZ_8 (0x3 << 0)
+
+/* OTG_FS Device Control OUT Endpoint 0 Control Register (OTG_HS_DOEPCTL0) */
+#define OTG_HS_DOEPCTL0_EPENA (1 << 31)
+#define OTG_HS_DOEPCTL0_EPDIS (1 << 30)
+/* Bits 29:28 - Reserved */
+#define OTG_HS_DOEPCTLX_SD0PID (1 << 28)
+#define OTG_HS_DOEPCTL0_SNAK (1 << 27)
+#define OTG_HS_DOEPCTL0_CNAK (1 << 26)
+/* Bits 25:22 - Reserved */
+#define OTG_HS_DOEPCTL0_STALL (1 << 21)
+#define OTG_HS_DOEPCTL0_SNPM (1 << 20)
+#define OTG_HS_DOEPCTL0_EPTYP_MASK (0x3 << 18)
+#define OTG_HS_DOEPCTL0_NAKSTS (1 << 17)
+/* Bit 16 - Reserved */
+#define OTG_HS_DOEPCTL0_USBAEP (1 << 15)
+/* Bits 14:2 - Reserved */
+#define OTG_HS_DOEPCTL0_MPSIZ_MASK (0x3 << 0)
+#define OTG_HS_DOEPCTL0_MPSIZ_64 (0x0 << 0)
+#define OTG_HS_DOEPCTL0_MPSIZ_32 (0x1 << 0)
+#define OTG_HS_DOEPCTL0_MPSIZ_16 (0x2 << 0)
+#define OTG_HS_DOEPCTL0_MPSIZ_8 (0x3 << 0)
+
+/* OTG_FS Device IN Endpoint Interrupt Register (OTG_HS_DIEPINTx) */
+/* Bits 31:8 - Reserved */
+#define OTG_HS_DIEPINTX_TXFE (1 << 7)
+#define OTG_HS_DIEPINTX_INEPNE (1 << 6)
+/* Bit 5 - Reserved */
+#define OTG_HS_DIEPINTX_ITTXFE (1 << 4)
+#define OTG_HS_DIEPINTX_TOC (1 << 3)
+/* Bit 2 - Reserved */
+#define OTG_HS_DIEPINTX_EPDISD (1 << 1)
+#define OTG_HS_DIEPINTX_XFRC (1 << 0)
+
+/* OTG_FS Device IN Endpoint Interrupt Register (OTG_HS_DOEPINTx) */
+/* Bits 31:7 - Reserved */
+#define OTG_HS_DOEPINTX_B2BSTUP (1 << 6)
+/* Bit 5 - Reserved */
+#define OTG_HS_DOEPINTX_OTEPDIS (1 << 4)
+#define OTG_HS_DOEPINTX_STUP (1 << 3)
+/* Bit 2 - Reserved */
+#define OTG_HS_DOEPINTX_EPDISD (1 << 1)
+#define OTG_HS_DOEPINTX_XFRC (1 << 0)
+
+/* OTG_FS Device OUT Endpoint 0 Transfer Size Regsiter (OTG_HS_DOEPTSIZ0) */
+/* Bit 31 - Reserved */
+#define OTG_HS_DIEPSIZ0_STUPCNT_1 (0x1 << 29)
+#define OTG_HS_DIEPSIZ0_STUPCNT_2 (0x2 << 29)
+#define OTG_HS_DIEPSIZ0_STUPCNT_3 (0x3 << 29)
+#define OTG_HS_DIEPSIZ0_STUPCNT_MASK (0x3 << 29)
+/* Bits 28:20 - Reserved */
+#define OTG_HS_DIEPSIZ0_PKTCNT (1 << 19)
+/* Bits 18:7 - Reserved */
+#define OTG_HS_DIEPSIZ0_XFRSIZ_MASK (0x7f << 0)
+
+#endif
diff --git a/include/libopencm3/stm32/f2/syscfg.h b/include/libopencm3/stm32/syscfg.h
index 7426f16..7426f16 100644
--- a/include/libopencm3/stm32/f2/syscfg.h
+++ b/include/libopencm3/stm32/syscfg.h
diff --git a/include/libopencm3/usb/cdc.h b/include/libopencm3/usb/cdc.h
index 4b54961..5036411 100644
--- a/include/libopencm3/usb/cdc.h
+++ b/include/libopencm3/usb/cdc.h
@@ -112,7 +112,7 @@ struct usb_cdc_line_coding {
/* Table 30: Class-Specific Notification Codes for PSTN subclasses */
/* ... */
-#define USB_CDC_NOTIFY_SERIAL_STATE 0x20
+#define USB_CDC_NOTIFY_SERIAL_STATE 0x20
/* ... */
/* Notification Structure */
diff --git a/include/libopencm3/usb/usbd.h b/include/libopencm3/usb/usbd.h
index 8f68555..2e5b7fb 100644
--- a/include/libopencm3/usb/usbd.h
+++ b/include/libopencm3/usb/usbd.h
@@ -32,9 +32,13 @@ enum usbd_request_return_codes {
};
typedef struct _usbd_driver usbd_driver;
+typedef struct _usbd_device usbd_device;
+
extern const usbd_driver stm32f103_usb_driver;
extern const usbd_driver stm32f107_usb_driver;
+extern const usbd_driver stm32f207_usb_driver;
#define otgfs_usb_driver stm32f107_usb_driver
+#define otghs_usb_driver stm32f207_usb_driver
/* Static buffer for control transactions:
* This is defined as weak in the library, applicaiton
@@ -42,45 +46,56 @@ extern const usbd_driver stm32f107_usb_driver;
extern u8 usbd_control_buffer[];
/* <usb.c> */
-extern int usbd_init(const usbd_driver *driver,
- const struct usb_device_descriptor *dev,
- const struct usb_config_descriptor *conf,
- const char **strings, int num_strings);
-extern void usbd_set_control_buffer_size(u16 size);
-
-extern void usbd_register_reset_callback(void (*callback)(void));
-extern void usbd_register_suspend_callback(void (*callback)(void));
-extern void usbd_register_resume_callback(void (*callback)(void));
-extern void usbd_register_sof_callback(void (*callback)(void));
-
-typedef int (*usbd_control_callback)(struct usb_setup_data *req, u8 **buf,
- u16 *len, void (**complete)(struct usb_setup_data *req));
+extern usbd_device *usbd_init(const usbd_driver *driver,
+ const struct usb_device_descriptor *dev,
+ const struct usb_config_descriptor *conf,
+ const char **strings, int num_strings);
+
+extern void usbd_set_control_buffer_size(usbd_device *usbd_dev, u16 size);
+
+extern void usbd_register_reset_callback(usbd_device *usbd_dev,
+ void (*callback)(void));
+extern void usbd_register_suspend_callback(usbd_device *usbd_dev,
+ void (*callback)(void));
+extern void usbd_register_resume_callback(usbd_device *usbd_dev,
+ void (*callback)(void));
+extern void usbd_register_sof_callback(usbd_device *usbd_dev,
+ void (*callback)(void));
+
+typedef int (*usbd_control_callback)(usbd_device *usbd_dev,
+ struct usb_setup_data *req, u8 **buf, u16 *len,
+ void (**complete)(usbd_device *usbd_dev,
+ struct usb_setup_data *req));
/* <usb_control.c> */
-extern int usbd_register_control_callback(u8 type, u8 type_mask,
- usbd_control_callback callback);
+extern int usbd_register_control_callback(usbd_device *usbd_dev, u8 type,
+ u8 type_mask,
+ usbd_control_callback callback);
/* <usb_standard.c> */
-extern void usbd_register_set_config_callback(void (*callback)(u16 wValue));
+extern void usbd_register_set_config_callback(usbd_device *usbd_dev,
+ void (*callback)(usbd_device *usbd_dev, u16 wValue));
/* Functions to be provided by the hardware abstraction layer */
-extern void usbd_poll(void);
-extern void usbd_disconnect(bool disconnected);
+extern void usbd_poll(usbd_device *usbd_dev);
+extern void usbd_disconnect(usbd_device *usbd_dev, bool disconnected);
-extern void usbd_ep_setup(u8 addr, u8 type, u16 max_size,
- void (*callback)(u8 ep));
+extern void usbd_ep_setup(usbd_device *usbd_dev, u8 addr, u8 type, u16 max_size,
+ void (*callback)(usbd_device *usbd_dev, u8 ep));
-extern u16 usbd_ep_write_packet(u8 addr, const void *buf, u16 len);
+extern u16 usbd_ep_write_packet(usbd_device *usbd_dev, u8 addr,
+ const void *buf, u16 len);
-extern u16 usbd_ep_read_packet(u8 addr, void *buf, u16 len);
+extern u16 usbd_ep_read_packet(usbd_device *usbd_dev, u8 addr,
+ void *buf, u16 len);
-extern void usbd_ep_stall_set(u8 addr, u8 stall);
-extern u8 usbd_ep_stall_get(u8 addr);
+extern void usbd_ep_stall_set(usbd_device *usbd_dev, u8 addr, u8 stall);
+extern u8 usbd_ep_stall_get(usbd_device *usbd_dev, u8 addr);
-extern void usbd_ep_nak_set(u8 addr, u8 nak);
+extern void usbd_ep_nak_set(usbd_device *usbd_dev, u8 addr, u8 nak);
/* Optional */
-extern void usbd_cable_connect(u8 on);
+extern void usbd_cable_connect(usbd_device *usbd_dev, u8 on);
END_DECLS
diff --git a/include/libopencm3/usb/usbstd.h b/include/libopencm3/usb/usbstd.h
index 01fc7e3..7908280 100644
--- a/include/libopencm3/usb/usbstd.h
+++ b/include/libopencm3/usb/usbstd.h
@@ -38,6 +38,9 @@ struct usb_setup_data {
u16 wLength;
} __attribute__((packed));
+/* Class Definition */
+#define USB_CLASS_VENDOR 0xFF
+
/* bmRequestType bit definitions */
#define USB_REQ_TYPE_IN 0x80
#define USB_REQ_TYPE_STANDARD 0x00
diff --git a/include/libopencmsis/core_cm3.h b/include/libopencmsis/core_cm3.h
new file mode 100644
index 0000000..0a89381
--- /dev/null
+++ b/include/libopencmsis/core_cm3.h
@@ -0,0 +1,177 @@
+/* big fat FIXME: this should use a consistent structure, and reference
+ * functionality from libopencm3 instead of copypasting.
+ *
+ * particularly unimplemented features are FIXME'd extra
+ * */
+
+/* the original core_cm3.h is nonfree by arm; this provides libopencm3 variant of the symbols efm32lib needs of CMSIS. */
+
+#ifndef OPENCMSIS_CORECM3_H
+#define OPENCMSIS_CORECM3_H
+
+#include <libopencm3/cm3/common.h>
+#include <libopencm3/cm3/memorymap.h>
+#include <libopencm3/cm3/systick.h>
+#include <libopencm3/cm3/nvic.h>
+#include <libopencm3/cm3/scb.h>
+
+/* needed by system_efm32.h:196, guessing */
+#define __INLINE inline
+/* new since emlib 3.0 */
+#define __STATIC_INLINE static inline
+
+/* needed around efm32tg840f32.h:229. comparing the efm32lib definitions to the
+ * libopencm3 ones, "volatile" is all that's missing. */
+#define __IO volatile
+#define __O volatile
+#define __I volatile
+
+/* -> style access for what is defined in libopencm3/stm32/f1/scb.h /
+ * cm3/memorymap.h, as it's needed by efm32lib/inc/efm32_emu.h */
+
+/* from cm3/scb.h */
+#define SCB_SCR_SLEEPDEEP_Msk SCB_SCR_SLEEPDEEP
+
+/* structure as in, for example,
+ * DeviceSupport/EnergyMicro/EFM32/efm32tg840f32.h, data from
+ * libopencm3/cm3/scb.h. FIXME incomplete. */
+typedef struct
+{
+ __IO uint32_t CPUID;
+ __IO uint32_t ICSR;
+ __IO uint32_t VTOR;
+ __IO uint32_t AIRCR;
+ __IO uint32_t SCR;
+ __IO uint32_t CCR;
+ __IO uint8_t SHPR[12]; /* FIXME: how is this properly indexed? */
+ __IO uint32_t SHCSR;
+} SCB_TypeDef;
+#define SCB ((SCB_TypeDef *) SCB_BASE)
+
+/* needed by efm32_emu.h, guessing and taking the implementation used in
+ * lightswitch-interrupt.c */
+#define __WFI() __asm__("wfi")
+
+/* needed by efm32_cmu.h, probably it's just what gcc provides anyway */
+#define __CLZ(div) __builtin_clz(div)
+
+/* needed by efm32_aes.c. __builtin_bswap32 does the same thing as the rev instruction according to https://bugzilla.mozilla.org/show_bug.cgi?id=600106 */
+#define __REV(x) __builtin_bswap32(x)
+
+/* stubs for efm32_dbg.h */
+typedef struct
+{
+ uint32_t DHCSR;
+ uint32_t DEMCR; /* needed by efm32tg stk trace.c */
+} CoreDebug_TypeDef;
+/* FIXME let's just hope writes to flash are protected */
+#define CoreDebug ((CoreDebug_TypeDef *) 0)
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk 0
+#define CoreDebug_DEMCR_TRCENA_Msk 0
+
+/* stubs for efm32_dma */
+
+static inline void NVIC_ClearPendingIRQ(uint8_t irqn)
+{
+ nvic_clear_pending_irq(irqn);
+}
+static inline void NVIC_EnableIRQ(uint8_t irqn)
+{
+ nvic_enable_irq(irqn);
+}
+static inline void NVIC_DisableIRQ(uint8_t irqn)
+{
+ nvic_disable_irq(irqn);
+}
+
+/* stubs for efm32_int. FIXME: how do they do that? nvic documentation in the
+ * efm32 core manual doesn't tell anything of a global on/off switch */
+
+#define __enable_irq() 1
+#define __disable_irq() 1
+
+/* stubs for efm32_mpu FIXME */
+
+#define SCB_SHCSR_MEMFAULTENA_Msk 0
+
+typedef struct
+{
+ uint32_t CTRL;
+ uint32_t RNR;
+ uint32_t RBAR;
+ uint32_t RASR;
+} MPU_TypeDef;
+/* FIXME struct at NULL */
+#define MPU ((MPU_TypeDef *) 0)
+#define MPU_CTRL_ENABLE_Msk 0
+#define MPU_RASR_XN_Pos 0
+#define MPU_RASR_AP_Pos 0
+#define MPU_RASR_TEX_Pos 0
+#define MPU_RASR_S_Pos 0
+#define MPU_RASR_C_Pos 0
+#define MPU_RASR_B_Pos 0
+#define MPU_RASR_SRD_Pos 0
+#define MPU_RASR_SIZE_Pos 0
+#define MPU_RASR_ENABLE_Pos 0
+
+/* required for the blink example */
+
+/* if if (SysTick_Config(CMU_ClockFreqGet(cmuClock_CORE) / 1000)) while (1) ;
+ * configures the sys ticks to 1ms, then the argument to SysTick_Config
+ * describes how many cycles to wait between two systicks.
+ *
+ * the endless loop part looks like an "if it returns an error condition,
+ * rather loop here than continue"; every other solution would involve things
+ * that are dark magic to my understanding.
+ *
+ * implementation more or less copypasted from lib/stm32/systick.c, FIXME until
+ * the generic cm3 functionality is moved out from stm32 and can be used here
+ * easily (systick_set_reload, systick_interrupt_enable, systick_counter_enable
+ * and systick_set_clocksource).
+ *
+ * modified for CMSIS style array as the powertest example needs it.
+ * */
+
+/* from d0002_efm32_cortex-m3_reference_manual.pdf section 4.4 */
+typedef struct
+{
+ uint32_t CTRL;
+ uint32_t LOAD;
+ uint32_t VAL;
+ uint32_t CALIB;
+} SysTick_TypeDef;
+#define SysTick ((SysTick_TypeDef *) SYS_TICK_BASE)
+
+static inline uint32_t SysTick_Config(uint32_t n_ticks)
+{
+ /* constant from systick_set_reload -- as this returns something that's
+ * not void, this is the only possible error condition */
+ if (n_ticks & ~0x00FFFFFF) return 1;
+
+ systick_set_reload(n_ticks);
+ systick_set_clocksource(true);
+ systick_interrupt_enable();
+ systick_counter_enable();
+
+ return 0;
+}
+
+/* stubs for efm32tg stk trace.c */
+typedef struct
+{
+ uint32_t LAR;
+ uint32_t TCR;
+} ITM_TypeDef;
+/* FIXME struct at NULL */
+#define ITM ((ITM_TypeDef *) 0)
+
+/* blink.h expects the isr for systicks to be named SysTick_Handler. with this,
+ * its Systick_Handler function gets renamed to the weak symbol exported by
+ * vector.c */
+
+#define SysTick_Handler sys_tick_handler
+/* FIXME: this needs to be done for all of the 14 hard vectors */
+
+#include <libopencmsis/dispatch/irqhandlers.h>
+
+#endif
diff --git a/include/libopencmsis/dispatch/irqhandlers.h b/include/libopencmsis/dispatch/irqhandlers.h
new file mode 100644
index 0000000..65e071d
--- /dev/null
+++ b/include/libopencmsis/dispatch/irqhandlers.h
@@ -0,0 +1,23 @@
+#if defined(STM32F1)
+# include <libopencmsis/stm32/f1/irqhandlers.h>
+#elif defined(STM32F2)
+# include <libopencmsis/stm32/f2/irqhandlers.h>
+#elif defined(STM32F4)
+# include <libopencmsis/stm32/f4/irqhandlers.h>
+
+#elif defined(EFM32TG)
+# include <libopencmsis/efm32/efm32tg/irqhandlers.h>
+#elif defined(EFM32G)
+# include <libopencmsis/efm32/efm32g/irqhandlers.h>
+#elif defined(EFM32LG)
+# include <libopencmsis/efm32/efm32lg/irqhandlers.h>
+#elif defined(EFM32GG)
+# include <libopencmsis/efm32/efm32gg/irqhandlers.h>
+
+#elif defined(LPC43XX)
+# include <libopencmsis/lpc43xx/irqhandlers.h>
+
+#else
+# warning"no chipset defined; user interrupts are not redirected"
+
+#endif