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authorchrysn2012-10-29 14:44:37 +0100
committerchrysn2012-10-29 14:44:37 +0100
commita1f4c29872980f84a06c0bc610b1314c43187f06 (patch)
treef520fc88e1d8cdd4a3e7a44739829d0bda20c9c3 /include
parenta01e5c201bca79b9dc4fe4363d843f8c7dad5290 (diff)
parent1e88ad186fe362aeb8a6994d6d88775dc689ddfb (diff)
Merge branch 'efm32'
this adds support for energy micro's efm32 tiny gecko, gecko, leopard gecko and giant gecko series. also, the experimental libopencmsis is included in this branch, as it is required for full operation of the free energymicro standard library
Diffstat (limited to 'include')
-rw-r--r--include/libopencm3/dispatch/nvic.h10
-rw-r--r--include/libopencm3/efm32/efm32g/irq.yaml35
-rw-r--r--include/libopencm3/efm32/efm32gg/irq.yaml43
-rw-r--r--include/libopencm3/efm32/efm32lg/irq.yaml43
-rw-r--r--include/libopencm3/efm32/efm32tg/irq.yaml (renamed from include/libopencm3/efm32/tinygecko/irq.yaml)2
-rw-r--r--include/libopencm3/efm32/efm32tg/memorymap.h76
-rw-r--r--include/libopencm3/efm32/memorymap.h37
-rw-r--r--include/libopencmsis/core_cm3.h177
-rw-r--r--include/libopencmsis/dispatch/irqhandlers.h23
9 files changed, 443 insertions, 3 deletions
diff --git a/include/libopencm3/dispatch/nvic.h b/include/libopencm3/dispatch/nvic.h
index ff08269..c797d40 100644
--- a/include/libopencm3/dispatch/nvic.h
+++ b/include/libopencm3/dispatch/nvic.h
@@ -5,8 +5,14 @@
#elif defined(STM32F4)
# include <libopencm3/stm32/f4/nvic.h>
-#elif defined(TINYGECKO)
-# include <libopencm3/efm32/tinygecko/nvic.h>
+#elif defined(EFM32TG)
+# include <libopencm3/efm32/efm32tg/nvic.h>
+#elif defined(EFM32G)
+# include <libopencm3/efm32/efm32g/nvic.h>
+#elif defined(EFM32LG)
+# include <libopencm3/efm32/efm32lg/nvic.h>
+#elif defined(EFM32GG)
+# include <libopencm3/efm32/efm32gg/nvic.h>
#elif defined(LPC13XX)
# include <libopencm3/lpc13xx/nvic.h>
diff --git a/include/libopencm3/efm32/efm32g/irq.yaml b/include/libopencm3/efm32/efm32g/irq.yaml
new file mode 100644
index 0000000..770f755
--- /dev/null
+++ b/include/libopencm3/efm32/efm32g/irq.yaml
@@ -0,0 +1,35 @@
+includeguard: LIBOPENCM3_EFM32G_NVIC_H
+partname_humanreadable: EFM32 Gecko series
+partname_doxygen: EFM32G
+# The names and sequence are taken from d0001_efm32g_reference_manual.pdf table 4.1.
+irqs:
+ - dma
+ - gpio_even
+ - timer0
+ - usart0_rx
+ - usart0_tx
+ - acmp01
+ - adc0
+ - dac0
+ - i2c0
+ - gpio_odd
+ - timer1
+ - timer2
+ - usart1_rx
+ - usart1_tx
+ - usart2_rx
+ - usart2_tx
+ - uart0_rx
+ - uart0_tx
+ - leuart0
+ - leuart1
+ - letimer0
+ - pcnt0
+ - pcnt1
+ - pcnt2
+ - rtc
+ - cmu
+ - vcmp
+ - lcd
+ - msc
+ - aes
diff --git a/include/libopencm3/efm32/efm32gg/irq.yaml b/include/libopencm3/efm32/efm32gg/irq.yaml
new file mode 100644
index 0000000..1cb4601
--- /dev/null
+++ b/include/libopencm3/efm32/efm32gg/irq.yaml
@@ -0,0 +1,43 @@
+includeguard: LIBOPENCM3_EFM32GG_NVIC_H
+partname_humanreadable: EFM32 Giant Gecko series
+partname_doxygen: EFM32GG
+# The names and sequence are taken from d0053_efm32gg_refreence_manual.pdf table 4.1.
+irqs:
+ - dma
+ - gpio_even
+ - timer0
+ - usart0_rx
+ - usart0_tx
+ - usb
+ - acmp01
+ - adc0
+ - dac0
+ - i2c0
+ - i2c1
+ - gpio_odd
+ - timer1
+ - timer2
+ - timer3
+ - usart1_rx
+ - usart1_tx
+ - lesense
+ - usart2_rx
+ - usart2_tx
+ - uart0_rx
+ - uart0_tx
+ - uart1_rx
+ - uart1_tx
+ - leuart0
+ - leuart1
+ - letimer0
+ - pcnt0
+ - pcnt1
+ - pcnt2
+ - rtc
+ - burtc
+ - cmu
+ - vcmp
+ - lcd
+ - msc
+ - aes
+ - ebi
diff --git a/include/libopencm3/efm32/efm32lg/irq.yaml b/include/libopencm3/efm32/efm32lg/irq.yaml
new file mode 100644
index 0000000..ec38bc1
--- /dev/null
+++ b/include/libopencm3/efm32/efm32lg/irq.yaml
@@ -0,0 +1,43 @@
+includeguard: LIBOPENCM3_EFM32LG_NVIC_H
+partname_humanreadable: EFM32 Leopard Gecko series
+partname_doxygen: EFM32LG
+# The names and sequence are taken from d0183_efm32lg_reference_manual.pdf table 4.1.
+irqs:
+ - dma
+ - gpio_even
+ - timer0
+ - usart0_rx
+ - usart0_tx
+ - usb
+ - acmp01
+ - adc0
+ - dac0
+ - i2c0
+ - i2c1
+ - gpio_odd
+ - timer1
+ - timer2
+ - timer3
+ - usart1_rx
+ - usart1_tx
+ - lesense
+ - usart2_rx
+ - usart2_tx
+ - uart0_rx
+ - uart0_tx
+ - uart1_rx
+ - uart1_tx
+ - leuart0
+ - leuart1
+ - letimer0
+ - pcnt0
+ - pcnt1
+ - pcnt2
+ - rtc
+ - burtc
+ - cmu
+ - vcmp
+ - lcd
+ - msc
+ - aes
+ - ebi
diff --git a/include/libopencm3/efm32/tinygecko/irq.yaml b/include/libopencm3/efm32/efm32tg/irq.yaml
index da954f6..f4aaba3 100644
--- a/include/libopencm3/efm32/tinygecko/irq.yaml
+++ b/include/libopencm3/efm32/efm32tg/irq.yaml
@@ -1,4 +1,4 @@
-includeguard: LIBOPENCM3_EFM32_TINYGECKO_NVIC_H
+includeguard: LIBOPENCM3_EFM32TG_NVIC_H
partname_humanreadable: EFM32 Tiny Gecko series
partname_doxygen: EFM32TG
# The names and sequence are taken from d0034_efm32tg_reference_manual.pdf table 4.1.
diff --git a/include/libopencm3/efm32/efm32tg/memorymap.h b/include/libopencm3/efm32/efm32tg/memorymap.h
new file mode 100644
index 0000000..abf37ce
--- /dev/null
+++ b/include/libopencm3/efm32/efm32tg/memorymap.h
@@ -0,0 +1,76 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 chrysn <chrysn@fsfe.org>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/** @file
+ *
+ * Layout of the system address space of Tiny Gecko devices.
+ *
+ * This reflects d0034_efm32tg_reference_manual.pdf figure 5.2.
+ */
+
+/* The common cortex-m3 definitions were verified from
+ * d0034_efm32tg_reference_manual.pdf figure 5.2. The CM3 ROM Table seems to be
+ * missing there. The details (everything based on SCS_BASE) was verified from
+ * d0002_efm32_cortex-m3_reference_manual.pdf table 4.1, and seems to fit, but
+ * there are discrepancies. */
+#include <libopencm3/cm3/memorymap.h>
+
+#define CODE_BASE 0x00000000
+
+#define SRAM_BASE 0x20000000
+#define SRAM_BASE_BITBAND 0x22000000
+
+#define PERIPH_BASE 0x40000000
+#define PERIPH_BASE_BITBAND 0x42000000
+
+/* Details of the "Code" section */
+
+#define FLASH_BASE (CODE_BASE + 0x00000000)
+#define USERDATA_BASE (CODE_BASE + 0x0fe00000)
+#define LOCKBITS_BASE (CODE_BASE + 0x0fe04000)
+#define CHIPCONFIG_BASE (CODE_BASE + 0x0fe08000)
+#define CODESPACESRAM_BASE (CODE_BASE + 0x10000000)
+
+/* Tiny Gecko peripherial definitions */
+
+#define VCMP_BASE (PERIPH_BASE + 0x00000000)
+#define ACMP0_BASE (PERIPH_BASE + 0x00001000)
+#define ACMP1_BASE (PERIPH_BASE + 0x00001400)
+#define ADC_BASE (PERIPH_BASE + 0x00002000)
+#define DAC0_BASE (PERIPH_BASE + 0x00004000)
+#define GPIO_BASE (PERIPH_BASE + 0x00006000) /**< @see gpio.h */
+#define I2C0_BASE (PERIPH_BASE + 0x0000a000)
+#define USART0_BASE (PERIPH_BASE + 0x0000c000)
+#define USART1_BASE (PERIPH_BASE + 0x0000c400)
+#define TIMER0_BASE (PERIPH_BASE + 0x00010000)
+#define TIMER1_BASE (PERIPH_BASE + 0x00010400)
+#define RTC_BASE (PERIPH_BASE + 0x00080000)
+#define LETIMER0_BASE (PERIPH_BASE + 0x00082000)
+#define LEUART0_BASE (PERIPH_BASE + 0x00084000)
+#define PCNT0_BASE (PERIPH_BASE + 0x00086000)
+#define WDOG_BASE (PERIPH_BASE + 0x00088000)
+#define LCD_BASE (PERIPH_BASE + 0x0008a000)
+#define LESENSE_BASE (PERIPH_BASE + 0x0008c000)
+#define MSC_BASE (PERIPH_BASE + 0x000c0000)
+#define DMA_BASE (PERIPH_BASE + 0x000c2000)
+#define EMU_BASE (PERIPH_BASE + 0x000c6000)
+#define CMU_BASE (PERIPH_BASE + 0x000c8000) /**< @see cmu.h */
+#define RMU_BASE (PERIPH_BASE + 0x000ca000)
+#define PRS_BASE (PERIPH_BASE + 0x000cc000)
+#define AES_BASE (PERIPH_BASE + 0x000e0000)
diff --git a/include/libopencm3/efm32/memorymap.h b/include/libopencm3/efm32/memorymap.h
new file mode 100644
index 0000000..ff0e544
--- /dev/null
+++ b/include/libopencm3/efm32/memorymap.h
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 chrysn <chrysn@fsfe.org>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/** @file
+ *
+ * Dispatcher for the base address definitions, depending on the particular
+ * Gecko family.
+ *
+ * @see tinygecko/memorymap.h
+ */
+
+#ifndef LIBOPENCM3_EFM32_MEMORYMAP_H
+#define LIBOPENCM3_EFM32_MEMORYMAP_H
+
+#ifdef TINYGECKO
+# include <libopencm3/efm32/tinygecko/memorymap.h>
+#else
+# error "efm32 family not defined."
+#endif
+
+#endif
diff --git a/include/libopencmsis/core_cm3.h b/include/libopencmsis/core_cm3.h
new file mode 100644
index 0000000..0a89381
--- /dev/null
+++ b/include/libopencmsis/core_cm3.h
@@ -0,0 +1,177 @@
+/* big fat FIXME: this should use a consistent structure, and reference
+ * functionality from libopencm3 instead of copypasting.
+ *
+ * particularly unimplemented features are FIXME'd extra
+ * */
+
+/* the original core_cm3.h is nonfree by arm; this provides libopencm3 variant of the symbols efm32lib needs of CMSIS. */
+
+#ifndef OPENCMSIS_CORECM3_H
+#define OPENCMSIS_CORECM3_H
+
+#include <libopencm3/cm3/common.h>
+#include <libopencm3/cm3/memorymap.h>
+#include <libopencm3/cm3/systick.h>
+#include <libopencm3/cm3/nvic.h>
+#include <libopencm3/cm3/scb.h>
+
+/* needed by system_efm32.h:196, guessing */
+#define __INLINE inline
+/* new since emlib 3.0 */
+#define __STATIC_INLINE static inline
+
+/* needed around efm32tg840f32.h:229. comparing the efm32lib definitions to the
+ * libopencm3 ones, "volatile" is all that's missing. */
+#define __IO volatile
+#define __O volatile
+#define __I volatile
+
+/* -> style access for what is defined in libopencm3/stm32/f1/scb.h /
+ * cm3/memorymap.h, as it's needed by efm32lib/inc/efm32_emu.h */
+
+/* from cm3/scb.h */
+#define SCB_SCR_SLEEPDEEP_Msk SCB_SCR_SLEEPDEEP
+
+/* structure as in, for example,
+ * DeviceSupport/EnergyMicro/EFM32/efm32tg840f32.h, data from
+ * libopencm3/cm3/scb.h. FIXME incomplete. */
+typedef struct
+{
+ __IO uint32_t CPUID;
+ __IO uint32_t ICSR;
+ __IO uint32_t VTOR;
+ __IO uint32_t AIRCR;
+ __IO uint32_t SCR;
+ __IO uint32_t CCR;
+ __IO uint8_t SHPR[12]; /* FIXME: how is this properly indexed? */
+ __IO uint32_t SHCSR;
+} SCB_TypeDef;
+#define SCB ((SCB_TypeDef *) SCB_BASE)
+
+/* needed by efm32_emu.h, guessing and taking the implementation used in
+ * lightswitch-interrupt.c */
+#define __WFI() __asm__("wfi")
+
+/* needed by efm32_cmu.h, probably it's just what gcc provides anyway */
+#define __CLZ(div) __builtin_clz(div)
+
+/* needed by efm32_aes.c. __builtin_bswap32 does the same thing as the rev instruction according to https://bugzilla.mozilla.org/show_bug.cgi?id=600106 */
+#define __REV(x) __builtin_bswap32(x)
+
+/* stubs for efm32_dbg.h */
+typedef struct
+{
+ uint32_t DHCSR;
+ uint32_t DEMCR; /* needed by efm32tg stk trace.c */
+} CoreDebug_TypeDef;
+/* FIXME let's just hope writes to flash are protected */
+#define CoreDebug ((CoreDebug_TypeDef *) 0)
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk 0
+#define CoreDebug_DEMCR_TRCENA_Msk 0
+
+/* stubs for efm32_dma */
+
+static inline void NVIC_ClearPendingIRQ(uint8_t irqn)
+{
+ nvic_clear_pending_irq(irqn);
+}
+static inline void NVIC_EnableIRQ(uint8_t irqn)
+{
+ nvic_enable_irq(irqn);
+}
+static inline void NVIC_DisableIRQ(uint8_t irqn)
+{
+ nvic_disable_irq(irqn);
+}
+
+/* stubs for efm32_int. FIXME: how do they do that? nvic documentation in the
+ * efm32 core manual doesn't tell anything of a global on/off switch */
+
+#define __enable_irq() 1
+#define __disable_irq() 1
+
+/* stubs for efm32_mpu FIXME */
+
+#define SCB_SHCSR_MEMFAULTENA_Msk 0
+
+typedef struct
+{
+ uint32_t CTRL;
+ uint32_t RNR;
+ uint32_t RBAR;
+ uint32_t RASR;
+} MPU_TypeDef;
+/* FIXME struct at NULL */
+#define MPU ((MPU_TypeDef *) 0)
+#define MPU_CTRL_ENABLE_Msk 0
+#define MPU_RASR_XN_Pos 0
+#define MPU_RASR_AP_Pos 0
+#define MPU_RASR_TEX_Pos 0
+#define MPU_RASR_S_Pos 0
+#define MPU_RASR_C_Pos 0
+#define MPU_RASR_B_Pos 0
+#define MPU_RASR_SRD_Pos 0
+#define MPU_RASR_SIZE_Pos 0
+#define MPU_RASR_ENABLE_Pos 0
+
+/* required for the blink example */
+
+/* if if (SysTick_Config(CMU_ClockFreqGet(cmuClock_CORE) / 1000)) while (1) ;
+ * configures the sys ticks to 1ms, then the argument to SysTick_Config
+ * describes how many cycles to wait between two systicks.
+ *
+ * the endless loop part looks like an "if it returns an error condition,
+ * rather loop here than continue"; every other solution would involve things
+ * that are dark magic to my understanding.
+ *
+ * implementation more or less copypasted from lib/stm32/systick.c, FIXME until
+ * the generic cm3 functionality is moved out from stm32 and can be used here
+ * easily (systick_set_reload, systick_interrupt_enable, systick_counter_enable
+ * and systick_set_clocksource).
+ *
+ * modified for CMSIS style array as the powertest example needs it.
+ * */
+
+/* from d0002_efm32_cortex-m3_reference_manual.pdf section 4.4 */
+typedef struct
+{
+ uint32_t CTRL;
+ uint32_t LOAD;
+ uint32_t VAL;
+ uint32_t CALIB;
+} SysTick_TypeDef;
+#define SysTick ((SysTick_TypeDef *) SYS_TICK_BASE)
+
+static inline uint32_t SysTick_Config(uint32_t n_ticks)
+{
+ /* constant from systick_set_reload -- as this returns something that's
+ * not void, this is the only possible error condition */
+ if (n_ticks & ~0x00FFFFFF) return 1;
+
+ systick_set_reload(n_ticks);
+ systick_set_clocksource(true);
+ systick_interrupt_enable();
+ systick_counter_enable();
+
+ return 0;
+}
+
+/* stubs for efm32tg stk trace.c */
+typedef struct
+{
+ uint32_t LAR;
+ uint32_t TCR;
+} ITM_TypeDef;
+/* FIXME struct at NULL */
+#define ITM ((ITM_TypeDef *) 0)
+
+/* blink.h expects the isr for systicks to be named SysTick_Handler. with this,
+ * its Systick_Handler function gets renamed to the weak symbol exported by
+ * vector.c */
+
+#define SysTick_Handler sys_tick_handler
+/* FIXME: this needs to be done for all of the 14 hard vectors */
+
+#include <libopencmsis/dispatch/irqhandlers.h>
+
+#endif
diff --git a/include/libopencmsis/dispatch/irqhandlers.h b/include/libopencmsis/dispatch/irqhandlers.h
new file mode 100644
index 0000000..65e071d
--- /dev/null
+++ b/include/libopencmsis/dispatch/irqhandlers.h
@@ -0,0 +1,23 @@
+#if defined(STM32F1)
+# include <libopencmsis/stm32/f1/irqhandlers.h>
+#elif defined(STM32F2)
+# include <libopencmsis/stm32/f2/irqhandlers.h>
+#elif defined(STM32F4)
+# include <libopencmsis/stm32/f4/irqhandlers.h>
+
+#elif defined(EFM32TG)
+# include <libopencmsis/efm32/efm32tg/irqhandlers.h>
+#elif defined(EFM32G)
+# include <libopencmsis/efm32/efm32g/irqhandlers.h>
+#elif defined(EFM32LG)
+# include <libopencmsis/efm32/efm32lg/irqhandlers.h>
+#elif defined(EFM32GG)
+# include <libopencmsis/efm32/efm32gg/irqhandlers.h>
+
+#elif defined(LPC43XX)
+# include <libopencmsis/lpc43xx/irqhandlers.h>
+
+#else
+# warning"no chipset defined; user interrupts are not redirected"
+
+#endif