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authorThomas Otto2010-03-28 15:19:32 +0200
committerThomas Otto2010-03-28 15:19:32 +0200
commit9d2e074b3d634dfe103dd50c8624c089a2a4da88 (patch)
treed232c3d545540cefb7891682e853e95199e286b1 /include
parent9132e6b9f552da9bcd1bf9a04a83b21882e7c6d9 (diff)
Cosmetic fixes.
Diffstat (limited to 'include')
-rw-r--r--include/libopenstm32/dma.h1
-rw-r--r--include/libopenstm32/nvic.h1
-rw-r--r--include/libopenstm32/scb.h15
3 files changed, 17 insertions, 0 deletions
diff --git a/include/libopenstm32/dma.h b/include/libopenstm32/dma.h
index b1eb052..389019f 100644
--- a/include/libopenstm32/dma.h
+++ b/include/libopenstm32/dma.h
@@ -688,6 +688,7 @@
/* MA[31:0]: Memory address */
/* --- Generic values ------------------------------------------------------ */
+
#define DMA_CHANNEL1 1
#define DMA_CHANNEL2 2
#define DMA_CHANNEL3 3
diff --git a/include/libopenstm32/nvic.h b/include/libopenstm32/nvic.h
index 03ac38f..bb2c35d 100644
--- a/include/libopenstm32/nvic.h
+++ b/include/libopenstm32/nvic.h
@@ -64,6 +64,7 @@
/* --- IRQ channel numbers-------------------------------------------------- */
+
/* Cortex M3 System Interrupts */
#define NVIC_NMI_IRQ -14
#define NVIC_HARD_FAULT_IRQ -13
diff --git a/include/libopenstm32/scb.h b/include/libopenstm32/scb.h
index b0a3677..17d892f 100644
--- a/include/libopenstm32/scb.h
+++ b/include/libopenstm32/scb.h
@@ -75,6 +75,7 @@
/* --- SCB values ---------------------------------------------------------- */
/* --- SCB_CPUID values ---------------------------------------------------- */
+
/* Implementer[31:24]: Implementer code */
#define SCP_CPUID_IMPLEMENTER_LSB 24
/* Variant[23:20]: Variant number */
@@ -87,6 +88,7 @@
#define SCP_CPUID_REVISION_LSB 0
/* --- SCB_ICSR values ----------------------------------------------------- */
+
/* NMIPENDSET: NMI set-pending bit */
#define SCB_ICSR_NMIPENDSET (1 << 31)
/* Bits [30:29]: reserved - must be kept cleared */
@@ -111,11 +113,13 @@
#define SCB_ICSR_VECTACTIVE_LSB 0
/* --- SCB_VTOR values ----------------------------------------------------- */
+
/* Bits [31:30]: reserved - must be kept cleared */
/* TBLOFF[29:9]: Vector table base offset field */
#define SCB_VTOR_TBLOFF_LSB 9 /* inconsistent datasheet - LSB could be 11 */
/* --- SCB_AIRCR values ---------------------------------------------------- */
+
/* VECTKEYSTAT[31:16]/ VECTKEY[31:16] Register key */
#define SCB_AIRCR_VECTKEYSTAT_LSB 16
/* ENDIANESS Data endianness bit */
@@ -137,6 +141,7 @@
#define SCB_AIRCR_VECTRESET (1 << 0)
/* --- SCB_SCR values ------------------------------------------------------ */
+
/* Bits [31:5]: reserved - must be kept cleared */
/* SEVEONPEND Send Event on Pending bit */
#define SCB_SCR_SEVEONPEND (1 << 4)
@@ -148,6 +153,7 @@
/* Bit 0: reserved - must be kept cleared */
/* --- SCB_CCR values ------------------------------------------------------ */
+
/* Bits [31:10]: reserved - must be kept cleared */
/* STKALIGN */
#define SCB_CCR_STKALIGN (1 << 9)
@@ -165,6 +171,7 @@
#define SCB_CCR_NONBASETHRDENA (1 << 0)
/* --- SCB_SHPR1 values ---------------------------------------------------- */
+
/* Bits [31:24]: reserved - must be kept cleared */
/* PRI_6[23:16]: Priority of system handler 6, usage fault */
#define SCB_SHPR1_PRI_6_LSB 16
@@ -174,11 +181,13 @@
#define SCB_SHPR1_PRI_4_LSB 0
/* --- SCB_SHPR2 values ---------------------------------------------------- */
+
/* PRI_11[31:24]: Priority of system handler 11, SVCall */
#define SCB_SHPR2_PRI_11_LSB 24
/* Bits [23:0]: reserved - must be kept cleared */
/* --- SCB_SHPR3 values ---------------------------------------------------- */
+
/* PRI_15[31:24]: Priority of system handler 15, SysTick exception */
#define SCB_SHPR3_PRI_15_LSB 24
/* PRI_14[23:16]: Priority of system handler 14, PendSV */
@@ -186,6 +195,7 @@
/* Bits [15:0]: reserved - must be kept cleared */
/* --- SCB_SHCSR values ---------------------------------------------------- */
+
/* Bits [31:19]: reserved - must be kept cleared */
/* USGFAULTENA: Usage fault enable */
#define SCB_SHCSR_USGFAULTENA (1 << 18)
@@ -220,6 +230,7 @@
#define SCB_SHCSR_MEMFAULTACT (1 << 0)
/* --- SCB_CFSR values ----------------------------------------------------- */
+
/* Bits [31:26]: reserved - must be kept cleared */
/* DIVBYZERO: Divide by zero usage fault */
#define SCB_CFSR_DIVBYZERO (1 << 25)
@@ -261,6 +272,7 @@
#define SCB_CFSR_IACCVIOL (1 << 0)
/* --- SCB_HFSR values ----------------------------------------------------- */
+
/* DEBUG_VT: reserved for debug use */
#define SCB_HFSR_DEBUG_VT (1 << 31)
/* FORCED: Forced hard fault */
@@ -271,12 +283,15 @@
/* Bit 0: reserved - must be kept cleared */
/* --- SCB_MMFAR values ---------------------------------------------------- */
+
/* MMFAR [31:0]: Memory management fault address */
/* --- SCB_BFAR values ----------------------------------------------------- */
+
/* BFAR [31:0]: Bus fault address */
/* --- SCB functions ------------------------------------------------------- */
+
/* TODO: */
#endif