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authorUwe Hermann2010-03-06 15:22:09 +0100
committerUwe Hermann2010-03-06 15:22:09 +0100
commita6342d4968c05c62638b09102fb3f8859227bd1e (patch)
tree3cbe00cf6341397db85b494e5ed26983067cb102 /include
parente6c72d5cfc23fae9fc2eebff002c233ea3c5323e (diff)
Cosmetic fixes.
Diffstat (limited to 'include')
-rw-r--r--include/libopenstm32/gpio.h1
-rw-r--r--include/libopenstm32/nvic.h2
-rw-r--r--include/libopenstm32/tools.h42
3 files changed, 26 insertions, 19 deletions
diff --git a/include/libopenstm32/gpio.h b/include/libopenstm32/gpio.h
index cfdc08b..a96c999 100644
--- a/include/libopenstm32/gpio.h
+++ b/include/libopenstm32/gpio.h
@@ -152,7 +152,6 @@
#define GPIO_ETH_RXD2 GPIO0 /* PB0 */
#define GPIO_ETH_RXD3 GPIO1 /* PB1 */
-
/* --- GPIO registers ------------------------------------------------------ */
/* Port configuration register low (GPIOx_CRL) */
diff --git a/include/libopenstm32/nvic.h b/include/libopenstm32/nvic.h
index aa427e4..3ccea79 100644
--- a/include/libopenstm32/nvic.h
+++ b/include/libopenstm32/nvic.h
@@ -24,6 +24,7 @@
#include <libopenstm32/common.h>
/* --- NVIC Registers ------------------------------------------------------ */
+
/* ISER: Interrupt Set Enable Registers */
/* Note: 8 32bit Registers */
#define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + (iser_id * 4))
@@ -107,6 +108,7 @@
#define SCB_AFSR MMIO32(SCB_BASE + 0x3C)
/* --- NVIC functions ------------------------------------------------------ */
+
void nvic_enable_irq(s32 irqn);
void nvic_disable_irq(s32 irqn);
s32 nvic_get_pending_irq(s32 irqn);
diff --git a/include/libopenstm32/tools.h b/include/libopenstm32/tools.h
index 246477a..54c3ce7 100644
--- a/include/libopenstm32/tools.h
+++ b/include/libopenstm32/tools.h
@@ -20,20 +20,24 @@
#ifndef LIBOPENSTM32_TOOLS_H
#define LIBOPENSTM32_TOOLS_H
-/******************************************************************************
+/*
* Register accessors / manipulators
- ******************************************************************************/
+ */
-/* Get register content */
+/* Get register content. */
#define GET_REG(REG) ((u16) *REG)
-/* Set register content */
+
+/* Set register content. */
#define SET_REG(REG, VAL) (*REG = (u16)VAL)
-/* Clear register bit */
+
+/* Clear register bit. */
#define CLR_REG_BIT(REG, BIT) SET_REG(REG, (~BIT))
-/* Clear register bit masking out some bits that must not be touched */
-#define CLR_REG_BIT_MSK(REG, MSK, BIT) SET_REG(REG, (GET_REG(REG) & \
- MSK & (~BIT)))
-/* Get masked out bit value */
+
+/* Clear register bit masking out some bits that must not be touched. */
+#define CLR_REG_BIT_MSK(REG, MSK, BIT) \
+ SET_REG(REG, (GET_REG(REG) & MSK & (~BIT)))
+
+/* Get masked out bit value. */
#define GET_REG_BIT(REG, BIT) (GET_REG(REG) & BIT)
/*
@@ -44,15 +48,17 @@
* bitmask BIT then we write 1 and if the bit in the masked window is
* matching the bitmask BIT we write 0.
*
- * TODO: we may need a faster implementation of that one?
+ * TODO: We may need a faster implementation of that one?
*/
-#define TOG_SET_REG_BIT_MSK(REG, MSK, BIT) { \
- register u16 toggle_mask = GET_REG(REG) & MSK; \
- register u16 bit_selector; \
- for(bit_selector = 1; bit_selector; bit_selector <<= 1){ \
- if((bit_selector & BIT) != 0) toggle_mask ^= bit_selector; \
- } \
- SET_REG(REG, toggle_mask); \
- }
+#define TOG_SET_REG_BIT_MSK(REG, MSK, BIT) \
+{ \
+ register u16 toggle_mask = GET_REG(REG) & MSK; \
+ register u16 bit_selector; \
+ for (bit_selector = 1; bit_selector; bit_selector <<= 1) { \
+ if ((bit_selector & BIT) != 0) \
+ toggle_mask ^= bit_selector; \
+ } \
+ SET_REG(REG, toggle_mask); \
+}
#endif