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authorUwe Hermann2011-03-07 13:37:30 +0100
committerUwe Hermann2011-03-07 13:37:30 +0100
commitef766da46811b7cbc7202ce01aa0fb51e785dfee (patch)
treef857013d2fb1708d15faf3ab4245b643b85bd13c /include/libopencm3
parent6694f3dc0c0cde00a4f5723dc602de731c63fd84 (diff)
parent554feb7f274d853fc024165b3c3074d38a01e0c0 (diff)
Merge remote-tracking branch 'gsmcmullin/master'
Diffstat (limited to 'include/libopencm3')
-rw-r--r--include/libopencm3/cm3/itm.h74
-rw-r--r--include/libopencm3/cm3/memorymap.h1
-rw-r--r--include/libopencm3/cm3/scs.h27
-rw-r--r--include/libopencm3/cm3/tpiu.h98
-rw-r--r--include/libopencm3/stm32/dbgmcu.h2
-rw-r--r--include/libopencm3/stm32/otg_fs.h179
-rw-r--r--include/libopencm3/stm32/rcc.h4
-rw-r--r--include/libopencm3/usb/cdc.h2
-rw-r--r--include/libopencm3/usb/usbd.h1
9 files changed, 373 insertions, 15 deletions
diff --git a/include/libopencm3/cm3/itm.h b/include/libopencm3/cm3/itm.h
new file mode 100644
index 0000000..232c2a7
--- /dev/null
+++ b/include/libopencm3/cm3/itm.h
@@ -0,0 +1,74 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_CM3_ITM_H
+#define LIBOPENCM3_CM3_ITM_H
+
+/* Cortex-M3 Instrumentation Trace Macrocell (ITM) */
+
+/* --- ITM registers ------------------------------------------------------- */
+
+/* Stimulus Port x (ITM_STIM[x]) */
+#define ITM_STIM ((volatile u32*)(ITM_BASE))
+
+/* Trace Enable ports (ITM_TER[x]) */
+#define ITM_TER ((volatile u32*)(ITM_BASE + 0xE00))
+
+/* Trace Privilege (ITM_TPR) */
+#define ITM_TPR MMIO32(ITM_BASE + 0xE40)
+
+/* Trace Control (ITM_TCR) */
+#define ITM_TCR MMIO32(ITM_BASE + 0xE80)
+
+/* TODO: PID, CID */
+
+/* --- ITM_STIM values ----------------------------------------------------- */
+/* Bits 31:0 - Write to port FIFO for forwarding as software event packet */
+/* Bits 31:1 - RAZ */
+#define ITM_STIM_FIFOREADY (1 << 0)
+
+/* --- ITM_TER values ------------------------------------------------------ */
+/* Bits 31:0 - Stimulus port #N is enabled with STIMENA[N] is set */
+
+/* --- ITM_TPR values ------------------------------------------------------ */
+/*
+ * Bits 31:0 - Bit [N] of PRIVMASK controls stimulus ports 8N to 8N+7
+ * 0: User access allowed to stimulus ports
+ * 1: Privileged access only to stimulus ports
+ */
+
+/* --- ITM_TCR values ------------------------------------------------------ */
+/* Bits 31:24 - Reserved */
+#define ITM_TCR_BUSY (1 << 23)
+#define ITM_TCR_TRACE_BUS_ID_MASK (0x3f << 16)
+/* Bits 15:10 - Reserved */
+#define ITM_TCR_TSPRESCALE_NONE (0 << 8)
+#define ITM_TCR_TSPRESCALE_DIV4 (1 << 8)
+#define ITM_TCR_TSPRESCALE_DIV16 (2 << 8)
+#define ITM_TCR_TSPRESCALE_DIV64 (3 << 8)
+#define ITM_TCR_TSPRESCALE_MASK (3 << 8)
+/* Bits 7:5 - Reserved */
+#define ITM_TCR_SWOENA (1 << 4)
+#define ITM_TCR_TXENA (1 << 3)
+#define ITM_TCR_SYNCENA (1 << 2)
+#define ITM_TCR_TSENA (1 << 1)
+#define ITM_TCR_ITMENA (1 << 0)
+
+
+#endif
diff --git a/include/libopencm3/cm3/memorymap.h b/include/libopencm3/cm3/memorymap.h
index b1b5172..13c3a8f 100644
--- a/include/libopencm3/cm3/memorymap.h
+++ b/include/libopencm3/cm3/memorymap.h
@@ -30,6 +30,7 @@
/* PPBI_BASE + 0x3000 (0xE000 3000 - 0xE000 DFFF): Reserved */
#define SCS_BASE (PPBI_BASE + 0xE000)
/* PPBI_BASE + 0xF000 (0xE000 F000 - 0xE003 FFFF): Reserved */
+#define TPIU_BASE (PPBI_BASE + 0x40000)
/* --- ITM: Instrumentation Trace Macrocell --- */
/* TODO */
diff --git a/include/libopencm3/cm3/scs.h b/include/libopencm3/cm3/scs.h
index 5646a18..d4dbca4 100644
--- a/include/libopencm3/cm3/scs.h
+++ b/include/libopencm3/cm3/scs.h
@@ -46,15 +46,22 @@
#define SCS_DCRSR_REGSEL_PSP 0x00000012
/* Debug Exception and Monitor Control Register (DEMCR) */
-#define SCS_DEMCR_VC_CORERESET 0x00000001
-#define SCS_DEMCR_VC_MMERR 0x00000010
-#define SCS_DEMCR_VC_NOCPERR 0x00000020
-#define SCS_DEMCR_VC_CHKERR 0x00000040
-#define SCS_DEMCR_VC_STATERR 0x00000080
-#define SCS_DEMCR_VC_BUSERR 0x00000100
-#define SCS_DEMCR_VC_INTERR 0x00000200
-#define SCS_DEMCR_VC_HARDERR 0x00000400
-#define SCS_DEMCR_VC_MON_EN 0x00010000
-#define SCS_DEMCR_VC_MON_PEND 0x00020000
+/* Bits 31:25 - Reserved */
+#define SCS_DEMCR_TRCENA (1 << 24)
+/* Bits 23:20 - Reserved */
+#define SCS_DEMCR_MON_REQ (1 << 19)
+#define SCS_DEMCR_MON_STEP (1 << 18)
+#define SCS_DEMCR_VC_MON_PEND (1 << 17)
+#define SCS_DEMCR_VC_MON_EN (1 << 16)
+/* Bits 15:11 - Reserved */
+#define SCS_DEMCR_VC_HARDERR (1 << 10)
+#define SCS_DEMCR_VC_INTERR (1 << 9)
+#define SCS_DEMCR_VC_BUSERR (1 << 8)
+#define SCS_DEMCR_VC_STATERR (1 << 7)
+#define SCS_DEMCR_VC_CHKERR (1 << 6)
+#define SCS_DEMCR_VC_NOCPERR (1 << 5)
+#define SCS_DEMCR_VC_MMERR (1 << 4)
+/* Bits 3:1 - Reserved */
+#define SCS_DEMCR_VC_CORERESET (1 << 0)
#endif
diff --git a/include/libopencm3/cm3/tpiu.h b/include/libopencm3/cm3/tpiu.h
new file mode 100644
index 0000000..5dfdcbd
--- /dev/null
+++ b/include/libopencm3/cm3/tpiu.h
@@ -0,0 +1,98 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_CM3_TPIU_H
+#define LIBOPENCM3_CM3_TPIU_H
+
+/* Cortex-M3 Trace Port Interface Unit (TPIU) */
+
+/* --- TPIU registers ------------------------------------------------------ */
+
+/* Supported Synchronous Port Size (TPIU_SSPSR) */
+#define TPIU_SSPSR MMIO32(TPIU_BASE + 0x000)
+
+/* Current Synchronous Port Size (TPIU_CSPSR) */
+#define TPIU_CSPSR MMIO32(TPIU_BASE + 0x004)
+
+/* Asynchronous Clock Prescaler (TPIU_ACPR) */
+#define TPIU_ACPR MMIO32(TPIU_BASE + 0x010)
+
+/* Selected Pin Protocol (TPIU_SPPR) */
+#define TPIU_SPPR MMIO32(TPIU_BASE + 0x0F0)
+
+/* Formatter and Flush Status Register (TPIU_FFSR) */
+#define TPIU_FFSR MMIO32(TPIU_BASE + 0x300)
+
+/* Formatter and Flush Control Register (TPIU_FFCR) */
+#define TPIU_FFCR MMIO32(TPIU_BASE + 0x304)
+
+/* (TPIU_DEVID) */
+#define TPIU_DEVID MMIO32(TPIU_BASE + 0xFC8)
+
+/* TODO: PID, CID */
+
+/* --- TPIU_SSPSR values --------------------------------------------------- */
+/*
+ * bit[N] == 0, trace port width of (N+1) not supported
+ * bit[N] == 1, trace port width of (N+1) supported
+ */
+#define TPIU_SSPSR_BYTE (1 << 0)
+#define TPIU_SSPSR_HALFWORD (1 << 1)
+#define TPIU_SSPSR_WORD (1 << 3)
+
+/* --- TPIU_SSPSR values --------------------------------------------------- */
+/* Same format as TPIU_SSPSR, except only one is set */
+#define TPIU_CSPSR_BYTE (1 << 0)
+#define TPIU_CSPSR_HALFWORD (1 << 1)
+#define TPIU_CSPSR_WORD (1 << 3)
+
+/* --- TPIU_ACPR values ---------------------------------------------------- */
+/* Bits 31:16 - Reserved */
+/* Bits 15:0 - SWO output clock = Asynchronous_Reference_Clock/(value +1) */
+
+/* --- TPIU_SPPR values ---------------------------------------------------- */
+/* Bits 31:2 - Reserved */
+#define TPIU_SPPR_SYNC (0x0)
+#define TPIU_SPPR_ASYNC_MANCHESTER (0x1)
+#define TPIU_SPPR_ASYNC_NRZ (0x2)
+
+/* --- TPIU_FFSR values ---------------------------------------------------- */
+/* Bits 31:4 - Reserved */
+#define TPIU_FFSR_FTNONSTOP (1 << 3)
+#define TPIU_FFSR_TCPRESENT (1 << 2)
+#define TPIU_FFSR_FTSTOPPED (1 << 1)
+#define TPIU_FFSR_FLINPROG (1 << 0)
+
+/* --- TPIU_FFCR values ---------------------------------------------------- */
+/* Bits 31:9 - Reserved */
+#define TPIU_FFCR_TRIGIN (1 << 8)
+/* Bits 7:2 - Reserved */
+#define TPIU_FFCR_ENFCONT (1 << 1)
+/* Bit 0 - Reserved */
+
+/* --- TPIU_DEVID values ---------------------------------------------------- */
+/* Bits 31:16 - Reserved */
+/* Bits 15:12 - Implementation defined */
+#define TPUI_DEVID_NRZ_SUPPORTED (1 << 11)
+#define TPUI_DEVID_MANCHESTER_SUPPORTED (1 << 10)
+/* Bit 9 - RAZ, indicated that trace data and clock are supported */
+#define TPUI_DEVID_FIFO_SIZE_MASK (7 << 6)
+/* Bits 5:0 - Implementation defined */
+
+#endif
diff --git a/include/libopencm3/stm32/dbgmcu.h b/include/libopencm3/stm32/dbgmcu.h
index 1229e90..e753f5e 100644
--- a/include/libopencm3/stm32/dbgmcu.h
+++ b/include/libopencm3/stm32/dbgmcu.h
@@ -26,7 +26,7 @@
/* --- DBGMCU registers ---------------------------------------------------- */
#define DBGMCU_IDCODE MMIO32(DBGMCU_BASE + 0x00)
-#define DBGMCU_CR MMIO32(DBGCMU_BASE + 0x04)
+#define DBGMCU_CR MMIO32(DBGMCU_BASE + 0x04)
/* DBGMCU_CR bits */
#define DBGMCU_CR_SLEEP 0x00000001
diff --git a/include/libopencm3/stm32/otg_fs.h b/include/libopencm3/stm32/otg_fs.h
index e7a4a23..d39593e 100644
--- a/include/libopencm3/stm32/otg_fs.h
+++ b/include/libopencm3/stm32/otg_fs.h
@@ -21,7 +21,7 @@
#define LIBOPENCM3_OTG_FS_H
#include <libopencm3/stm32/memorymap.h>
-#include <libopencm3/common.h>
+#include <libopencm3/cm3/common.h>
/* Core Global Control and Status Registers */
#define OTG_FS_OTGCTL MMIO32(USB_OTG_FS_BASE + 0x000)
@@ -78,8 +78,10 @@
#define OTG_FS_DOEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + 0xB10 + 0x20*(x))
/* Power and clock gating control and status register */
-#define OTH_FS_PCGCR MMIO32(USB_OTG_FS_BASE + 0xE00)
+#define OTG_FS_PCGCCTL MMIO32(USB_OTG_FS_BASE + 0xE00)
+/* Data FIFO */
+#define OTG_FS_FIFO(x) ((u32*)(USB_OTG_FS_BASE + (((x) + 1) << 12)))
/* Global CSRs */
/* OTG_FS AHB configuration register (OTG_FS_GAHBCFG) */
@@ -91,11 +93,58 @@
#define OTG_FS_GUSBCFG_TOCAL 0x00000003
#define OTG_FS_GUSBCFG_SRPCAP 0x00000100
#define OTG_FS_GUSBCFG_HNPCAP 0x00000200
-#define OTG_FS_GUSBCFG_TRDT 0x00003C00
+#define OTG_FS_GUSBCFG_TRDT_MASK (0xf << 10)
+#define OTG_FS_GUSBCFG_TRDT_16BIT (0x5 << 10)
+#define OTG_FS_GUSBCFG_TRDT_8BIT (0x9 << 10)
#define OTG_FS_GUSBCFG_NPTXRWEN 0x00004000
#define OTG_FS_GUSBCFG_FHMOD 0x20000000
#define OTG_FS_GUSBCFG_FDMOD 0x40000000
#define OTG_FS_GUSBCFG_CTXPKT 0x80000000
+/* WARNING: not in reference manual */
+#define OTG_FS_GUSBCFG_PHYSEL (1 << 6)
+
+/* OTG_FS reset register (OTG_FS_GRSTCTL) */
+#define OTG_FS_GRSTCTL_AHBIDL (1 << 31)
+/* Bits 30:11 - Reserved */
+#define OTG_FS_GRSTCTL_TXFNUM_MASK (0x1f << 6)
+#define OTG_FS_GRSTCTL_TXFFLSH (1 << 5)
+#define OTG_FS_GRSTCTL_RXFFLSH (1 << 4)
+/* Bit 3 - Reserved */
+#define OTG_FS_GRSTCTL_FCRST (1 << 2)
+#define OTG_FS_GRSTCTL_HSRST (1 << 1)
+#define OTG_FS_GRSTCTL_CSRST (1 << 0)
+
+/* OTG_FS interrupt status register (OTG_FS_GINTSTS) */
+#define OTG_FS_GINTSTS_WKUPINT (1 << 31)
+#define OTG_FS_GINTSTS_SRQINT (1 << 30)
+#define OTG_FS_GINTSTS_DISCINT (1 << 29)
+#define OTG_FS_GINTSTS_CIDSCHG (1 << 28)
+/* Bit 27 - Reserved */
+#define OTG_FS_GINTSTS_PTXFE (1 << 26)
+#define OTG_FS_GINTSTS_HCINT (1 << 25)
+#define OTG_FS_GINTSTS_HPRTINT (1 << 24)
+/* Bits 23:22 - Reserved */
+#define OTG_FS_GINTSTS_IPXFR (1 << 21)
+#define OTG_FS_GINTSTS_INCOMPISOOUT (1 << 21)
+#define OTG_FS_GINTSTS_IISOIXFR (1 << 20)
+#define OTG_FS_GINTSTS_OEPINT (1 << 19)
+#define OTG_FS_GINTSTS_IEPINT (1 << 18)
+/* Bits 17:16 - Reserved */
+#define OTG_FS_GINTSTS_EOPF (1 << 15)
+#define OTG_FS_GINTSTS_ISOODRP (1 << 14)
+#define OTG_FS_GINTSTS_ENUMDNE (1 << 13)
+#define OTG_FS_GINTSTS_USBRST (1 << 12)
+#define OTG_FS_GINTSTS_USBSUSP (1 << 11)
+#define OTG_FS_GINTSTS_ESUSP (1 << 10)
+/* Bits 9:8 - Reserved */
+#define OTG_FS_GINTSTS_GONAKEFF (1 << 7)
+#define OTG_FS_GINTSTS_GINAKEFF (1 << 6)
+#define OTG_FS_GINTSTS_NPTXFE (1 << 5)
+#define OTG_FS_GINTSTS_RXFLVL (1 << 4)
+#define OTG_FS_GINTSTS_SOF (1 << 3)
+#define OTG_FS_GINTSTS_OTGINT (1 << 2)
+#define OTG_FS_GINTSTS_MMIS (1 << 1)
+#define OTG_FS_GINTSTS_CMOD (1 << 0)
/* OTG_FS interrupt mask register (OTG_FS_GINTMSK) */
#define OTG_FS_GINTMSK_MMISM 0x00000002
@@ -125,15 +174,139 @@
#define OTG_FS_GINTMSK_SRQIM 0x40000000
#define OTG_FS_GINTMSK_WUIM 0x80000000
+/* OTG_FS Receive Status Pop Register (OTG_FS_GRXSTSP) */
+/* Bits 31:25 - Reserved */
+#define OTG_FS_GRXSTSP_FRMNUM_MASK (0xf << 21)
+#define OTG_FS_GRXSTSP_PKTSTS_MASK (0xf << 17)
+#define OTG_FS_GRXSTSP_PKTSTS_GOUTNAK (0x1 << 17)
+#define OTG_FS_GRXSTSP_PKTSTS_OUT (0x2 << 17)
+#define OTG_FS_GRXSTSP_PKTSTS_OUT_COMP (0x3 << 17)
+#define OTG_FS_GRXSTSP_PKTSTS_SETUP_COMP (0x4 << 17)
+#define OTG_FS_GRXSTSP_PKTSTS_SETUP (0x6 << 17)
+#define OTG_FS_GRXSTSP_DPID_MASK (0x3 << 15)
+#define OTG_FS_GRXSTSP_DPID_DATA0 (0x0 << 15)
+#define OTG_FS_GRXSTSP_DPID_DATA1 (0x2 << 15)
+#define OTG_FS_GRXSTSP_DPID_DATA2 (0x1 << 15)
+#define OTG_FS_GRXSTSP_DPID_MDATA (0x3 << 15)
+#define OTG_FS_GRXSTSP_BCNT_MASK (0x7ff << 4)
+#define OTG_FS_GRXSTSP_EPNUM_MASK (0xf << 0)
+
+/* OTG_FS general core configuration register (OTG_FS_GCCFG) */
+/* Bits 31:21 - Reserved */
+#define OTG_FS_GCCFG_SOFOUTEN (1 << 20)
+#define OTG_FS_GCCFG_VBUSBSEN (1 << 19)
+#define OTG_FS_GCCFG_VBUSASEN (1 << 18)
+/* Bit 17 - Reserved */
+#define OTG_FS_GCCFG_PWRDWN (1 << 16)
+/* Bits 15:0 - Reserved */
+
/* Device-mode CSRs */
+/* OTG_FS device control register (OTG_FS_DCTL) */
+/* Bits 31:12 - Reserved */
+#define OTG_FS_DCTL_POPRGDNE (1 << 11)
+#define OTG_FS_DCTL_CGONAK (1 << 10)
+#define OTG_FS_DCTL_SGONAK (1 << 9)
+#define OTG_FS_DCTL_SGINAK (1 << 8)
+#define OTG_FS_DCTL_TCTL_MASK (7 << 4)
+#define OTG_FS_DCTL_GONSTS (1 << 3)
+#define OTG_FS_DCTL_GINSTS (1 << 2)
+#define OTG_FS_DCTL_SDIS (1 << 1)
+#define OTG_FS_DCTL_RWUSIG (1 << 0)
+
/* OTG_FS device configuration register (OTG_FS_DCFG) */
#define OTG_FS_DCFG_DSPD 0x0003
#define OTG_FS_DCFG_NZLSOHSK 0x0004
#define OTG_FS_DCFG_DAD 0x07F0
#define OTG_FS_DCFG_PFIVL 0x1800
+/* OTG_FS Device IN Endpoint Common Interrupt Mask Register (OTG_FS_DIEPMSK) */
+/* Bits 31:10 - Reserved */
+#define OTG_FS_DIEPMSK_BIM (1 << 9)
+#define OTG_FS_DIEPMSK_TXFURM (1 << 8)
+/* Bit 7 - Reserved */
+#define OTG_FS_DIEPMSK_INEPNEM (1 << 6)
+#define OTG_FS_DIEPMSK_INEPNMM (1 << 5)
+#define OTG_FS_DIEPMSK_ITTXFEMSK (1 << 4)
+#define OTG_FS_DIEPMSK_TOM (1 << 3)
+/* Bit 2 - Reserved */
+#define OTG_FS_DIEPMSK_EPDM (1 << 1)
+#define OTG_FS_DIEPMSK_XFRCM (1 << 0)
+
+/* OTG_FS Device OUT Endpoint Common Interrupt Mask Register (OTG_FS_DOEPMSK) */
+/* Bits 31:10 - Reserved */
+#define OTG_FS_DOEPMSK_BOIM (1 << 9)
+#define OTG_FS_DOEPMSK_OPEM (1 << 8)
+/* Bit 7 - Reserved */
+#define OTG_FS_DOEPMSK_B2BSTUP (1 << 6)
+/* Bit 5 - Reserved */
+#define OTG_FS_DOEPMSK_OTEPDM (1 << 4)
+#define OTG_FS_DOEPMSK_STUPM (1 << 3)
+/* Bit 2 - Reserved */
+#define OTG_FS_DOEPMSK_EPDM (1 << 1)
+#define OTG_FS_DOEPMSK_XFRCM (1 << 0)
+
+/* OTG_FS Device Control IN Endpoint 0 Control Register (OTG_FS_DIEPCTL0) */
+#define OTG_FS_DIEPCTL0_EPENA (1 << 31)
+#define OTG_FS_DIEPCTL0_EPDIS (1 << 30)
+/* Bits 29:28 - Reserved */
+#define OTG_FS_DIEPCTL0_SNAK (1 << 27)
+#define OTG_FS_DIEPCTL0_CNAK (1 << 26)
+#define OTG_FS_DIEPCTL0_TXFNUM_MASK (0xf << 22)
+#define OTG_FS_DIEPCTL0_STALL (1 << 21)
+/* Bit 20 - Reserved */
+#define OTG_FS_DIEPCTL0_EPTYP_MASK (0x3 << 18)
+#define OTG_FS_DIEPCTL0_NAKSTS (1 << 17)
+/* Bit 16 - Reserved */
+#define OTG_FS_DIEPCTL0_USBAEP (1 << 15)
+/* Bits 14:2 - Reserved */
+#define OTG_FS_DIEPCTL0_MPSIZ_MASK (0x3 << 0)
+#define OTG_FS_DIEPCTL0_MPSIZ_64 (0x0 << 0)
+#define OTG_FS_DIEPCTL0_MPSIZ_32 (0x1 << 0)
+#define OTG_FS_DIEPCTL0_MPSIZ_16 (0x2 << 0)
+#define OTG_FS_DIEPCTL0_MPSIZ_8 (0x3 << 0)
+
+/* OTG_FS Device Control OUT Endpoint 0 Control Register (OTG_FS_DOEPCTL0) */
+#define OTG_FS_DOEPCTL0_EPENA (1 << 31)
+#define OTG_FS_DOEPCTL0_EPDIS (1 << 30)
+/* Bits 29:28 - Reserved */
+#define OTG_FS_DOEPCTL0_SNAK (1 << 27)
+#define OTG_FS_DOEPCTL0_CNAK (1 << 26)
+/* Bits 25:22 - Reserved */
+#define OTG_FS_DOEPCTL0_STALL (1 << 21)
+#define OTG_FS_DOEPCTL0_SNPM (1 << 20)
+#define OTG_FS_DOEPCTL0_EPTYP_MASK (0x3 << 18)
+#define OTG_FS_DOEPCTL0_NAKSTS (1 << 17)
+/* Bit 16 - Reserved */
+#define OTG_FS_DOEPCTL0_USBAEP (1 << 15)
+/* Bits 14:2 - Reserved */
+#define OTG_FS_DOEPCTL0_MPSIZ_MASK (0x3 << 0)
+#define OTG_FS_DOEPCTL0_MPSIZ_64 (0x0 << 0)
+#define OTG_FS_DOEPCTL0_MPSIZ_32 (0x1 << 0)
+#define OTG_FS_DOEPCTL0_MPSIZ_16 (0x2 << 0)
+#define OTG_FS_DOEPCTL0_MPSIZ_8 (0x3 << 0)
+
+/* OTG_FS Device IN Endpoint Interrupt Register (OTG_FS_DIEPINTx) */
+/* Bits 31:8 - Reserved */
+#define OTG_FS_DIEPINTX_TXFE (1 << 7)
+#define OTG_FS_DIEPINTX_INEPNE (1 << 6)
+/* Bit 5 - Reserved */
+#define OTG_FS_DIEPINTX_ITTXFE (1 << 4)
+#define OTG_FS_DIEPINTX_TOC (1 << 3)
+/* Bit 2 - Reserved */
+#define OTG_FS_DIEPINTX_EPDISD (1 << 1)
+#define OTG_FS_DIEPINTX_XFRC (1 << 0)
+/* OTG_FS Device OUT Endpoint 0 Transfer Size Regsiter (OTG_FS_DOEPTSIZ0) */
+/* Bit 31 - Reserved */
+#define OTG_FS_DIEPSIZ0_STUPCNT_1 (0x1 << 29)
+#define OTG_FS_DIEPSIZ0_STUPCNT_2 (0x2 << 29)
+#define OTG_FS_DIEPSIZ0_STUPCNT_3 (0x3 << 29)
+#define OTG_FS_DIEPSIZ0_STUPCNT_MASK (0x3 << 29)
+/* Bits 28:20 - Reserved */
+#define OTG_FS_DIEPSIZ0_PKTCNT (1 << 19)
+/* Bits 18:7 - Reserved */
+#define OTG_FS_DIEPSIZ0_XFRSIZ_MASK (0x7f << 0)
#endif
diff --git a/include/libopencm3/stm32/rcc.h b/include/libopencm3/stm32/rcc.h
index 0880627..a618439 100644
--- a/include/libopencm3/stm32/rcc.h
+++ b/include/libopencm3/stm32/rcc.h
@@ -230,6 +230,10 @@
/* --- RCC_AHBENR values --------------------------------------------------- */
+#define RCC_AHBENR_ETHMACENRX (1 << 16)
+#define RCC_AHBENR_ETHMACENTX (1 << 15)
+#define RCC_AHBENR_ETHMACEN (1 << 14)
+#define RCC_AHBENR_OTGFSEN (1 << 12)
#define RCC_AHBENR_SDIOEN (1 << 10)
#define RCC_AHBENR_FSMCEN (1 << 8)
#define RCC_AHBENR_CRCEN (1 << 6)
diff --git a/include/libopencm3/usb/cdc.h b/include/libopencm3/usb/cdc.h
index 2bdc18b..808d004 100644
--- a/include/libopencm3/usb/cdc.h
+++ b/include/libopencm3/usb/cdc.h
@@ -112,7 +112,7 @@ struct usb_cdc_line_coding {
/* Table 30: Class-Specific Notification Codes for PSTN subclasses */
/* ... */
-#define USB_CDC_NOTIFY_SERIAL_STATE 0x28
+#define USB_CDC_NOTIFY_SERIAL_STATE 0x20
/* ... */
/* Notification Structure */
diff --git a/include/libopencm3/usb/usbd.h b/include/libopencm3/usb/usbd.h
index e3c75f5..fab6304 100644
--- a/include/libopencm3/usb/usbd.h
+++ b/include/libopencm3/usb/usbd.h
@@ -24,6 +24,7 @@
typedef struct _usbd_driver usbd_driver;
extern const usbd_driver stm32f103_usb_driver;
+extern const usbd_driver stm32f107_usb_driver;
/* Static buffer for control transactions:
* This is defined as weak in the library, applicaiton