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authorUwe Hermann2011-11-02 02:19:51 +0100
committerUwe Hermann2011-11-02 02:19:51 +0100
commit9f821a5dd49b369a134327ec86eae0bd0d706c93 (patch)
tree5544e2c50a2f85062233baa3d753df39f49e1330 /include/libopencm3
parent25e30fab8efb7cec613f743ad5b43fc6cadfd1df (diff)
Minor whitespace fixes.
Diffstat (limited to 'include/libopencm3')
-rw-r--r--include/libopencm3/cm3/itm.h4
-rw-r--r--include/libopencm3/cm3/tpiu.h6
2 files changed, 9 insertions, 1 deletions
diff --git a/include/libopencm3/cm3/itm.h b/include/libopencm3/cm3/itm.h
index 232c2a7..40988aa 100644
--- a/include/libopencm3/cm3/itm.h
+++ b/include/libopencm3/cm3/itm.h
@@ -39,11 +39,13 @@
/* TODO: PID, CID */
/* --- ITM_STIM values ----------------------------------------------------- */
+
/* Bits 31:0 - Write to port FIFO for forwarding as software event packet */
/* Bits 31:1 - RAZ */
#define ITM_STIM_FIFOREADY (1 << 0)
/* --- ITM_TER values ------------------------------------------------------ */
+
/* Bits 31:0 - Stimulus port #N is enabled with STIMENA[N] is set */
/* --- ITM_TPR values ------------------------------------------------------ */
@@ -54,6 +56,7 @@
*/
/* --- ITM_TCR values ------------------------------------------------------ */
+
/* Bits 31:24 - Reserved */
#define ITM_TCR_BUSY (1 << 23)
#define ITM_TCR_TRACE_BUS_ID_MASK (0x3f << 16)
@@ -70,5 +73,4 @@
#define ITM_TCR_TSENA (1 << 1)
#define ITM_TCR_ITMENA (1 << 0)
-
#endif
diff --git a/include/libopencm3/cm3/tpiu.h b/include/libopencm3/cm3/tpiu.h
index 5dfdcbd..9251686 100644
--- a/include/libopencm3/cm3/tpiu.h
+++ b/include/libopencm3/cm3/tpiu.h
@@ -48,6 +48,7 @@
/* TODO: PID, CID */
/* --- TPIU_SSPSR values --------------------------------------------------- */
+
/*
* bit[N] == 0, trace port width of (N+1) not supported
* bit[N] == 1, trace port width of (N+1) supported
@@ -57,22 +58,26 @@
#define TPIU_SSPSR_WORD (1 << 3)
/* --- TPIU_SSPSR values --------------------------------------------------- */
+
/* Same format as TPIU_SSPSR, except only one is set */
#define TPIU_CSPSR_BYTE (1 << 0)
#define TPIU_CSPSR_HALFWORD (1 << 1)
#define TPIU_CSPSR_WORD (1 << 3)
/* --- TPIU_ACPR values ---------------------------------------------------- */
+
/* Bits 31:16 - Reserved */
/* Bits 15:0 - SWO output clock = Asynchronous_Reference_Clock/(value +1) */
/* --- TPIU_SPPR values ---------------------------------------------------- */
+
/* Bits 31:2 - Reserved */
#define TPIU_SPPR_SYNC (0x0)
#define TPIU_SPPR_ASYNC_MANCHESTER (0x1)
#define TPIU_SPPR_ASYNC_NRZ (0x2)
/* --- TPIU_FFSR values ---------------------------------------------------- */
+
/* Bits 31:4 - Reserved */
#define TPIU_FFSR_FTNONSTOP (1 << 3)
#define TPIU_FFSR_TCPRESENT (1 << 2)
@@ -80,6 +85,7 @@
#define TPIU_FFSR_FLINPROG (1 << 0)
/* --- TPIU_FFCR values ---------------------------------------------------- */
+
/* Bits 31:9 - Reserved */
#define TPIU_FFCR_TRIGIN (1 << 8)
/* Bits 7:2 - Reserved */