aboutsummaryrefslogtreecommitdiff
path: root/include/libopencm3/stm32/f2
diff options
context:
space:
mode:
authorJeff Ciesielski2012-11-13 13:27:36 -0800
committerJeff Ciesielski2012-11-13 13:27:36 -0800
commit88d4f020816c018e31ba48cdd975a9738ba56eed (patch)
treec213211778736d5ce2f06b4cf186a6900f522b20 /include/libopencm3/stm32/f2
parentffe392c11bdc7c45f61c652ecabd79fecbe1938a (diff)
parentdb35fbb7ba97a8a6d7481edf07cb82cae06aa834 (diff)
Merge pull request #3 from Jeff-Ciesielski/master
Integrate ICDs changes into the upstream opencm3 repository
Diffstat (limited to 'include/libopencm3/stm32/f2')
-rw-r--r--include/libopencm3/stm32/f2/irq.yaml85
-rw-r--r--include/libopencm3/stm32/f2/nvic_f2.h112
-rw-r--r--include/libopencm3/stm32/f2/scb.h307
-rw-r--r--include/libopencm3/stm32/f2/syscfg.h46
4 files changed, 85 insertions, 465 deletions
diff --git a/include/libopencm3/stm32/f2/irq.yaml b/include/libopencm3/stm32/f2/irq.yaml
new file mode 100644
index 0000000..c3600b3
--- /dev/null
+++ b/include/libopencm3/stm32/f2/irq.yaml
@@ -0,0 +1,85 @@
+includeguard: LIBOPENCM3_STM32_F2_NVIC_H
+partname_humanreadable: STM32 F2 series
+partname_doxygen: STM32F2
+irqs:
+ - nvic_wwdg
+ - pvd
+ - tamp_stamp
+ - rtc_wkup
+ - flash
+ - rcc
+ - exti0
+ - exti1
+ - exti2
+ - exti3
+ - exti4
+ - dma1_stream0
+ - dma1_stream1
+ - dma1_stream2
+ - dma1_stream3
+ - dma1_stream4
+ - dma1_stream5
+ - dma1_stream6
+ - adc
+ - can1_tx
+ - can1_rx0
+ - can1_rx1
+ - can1_sce
+ - exti9_5
+ - tim1_brk_tim9
+ - tim1_up_tim10
+ - tim1_trg_com_tim11
+ - tim1_cc
+ - tim2
+ - tim3
+ - tim4
+ - i2c1_ev
+ - i2c1_er
+ - i2c2_ev
+ - i2c2_er
+ - spi1
+ - spi2
+ - usart1
+ - usart2
+ - usart3
+ - exti15_10
+ - rtc_alarm
+ - usb_fs_wkup
+ - tim8_brk_tim12
+ - tim8_up_tim13
+ - tim8_trg_com_tim14
+ - tim8_cc
+ - dma1_stream7
+ - fsmc
+ - sdio
+ - tim5
+ - spi3
+ - uart4
+ - uart5
+ - tim6_dac
+ - tim7
+ - dma2_stream0
+ - dma2_stream1
+ - dma2_stream2
+ - dma2_stream3
+ - dma2_stream4
+ - eth
+ - eth_wkup
+ - can2_tx
+ - can2_rx0
+ - can2_rx1
+ - can2_sce
+ - otg_fs
+ - dma2_stream5
+ - dma2_stream6
+ - dma2_stream7
+ - usart6
+ - i2c3_ev
+ - i2c3_er
+ - otg_hs_ep1_out
+ - otg_hs_ep1_in
+ - otg_hs_wkup
+ - otg_hs
+ - dcmi
+ - cryp
+ - hash_rng
diff --git a/include/libopencm3/stm32/f2/nvic_f2.h b/include/libopencm3/stm32/f2/nvic_f2.h
deleted file mode 100644
index 2bf2997..0000000
--- a/include/libopencm3/stm32/f2/nvic_f2.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * This file is part of the libopencm3 project.
- *
- * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef LIBOPENCM3_NVIC_F2_H
-#define LIBOPENCM3_NVIC_F2_H
-
-/* --- IRQ channel numbers-------------------------------------------------- */
-
-/* Note: These F2 specific user interrupt definitions supplement the
- * general NVIC definitions in ../nvic.h
- */
-
-/* User Interrupts */
-#define NVIC_NVIC_WWDG_IRQ 0
-#define NVIC_PVD_IRQ 1
-#define NVIC_TAMP_STAMP_IRQ 2
-#define NVIC_RTC_WKUP_IRQ 3
-#define NVIC_FLASH_IRQ 4
-#define NVIC_RCC_IRQ 5
-#define NVIC_EXTI0_IRQ 6
-#define NVIC_EXTI1_IRQ 7
-#define NVIC_EXTI2_IRQ 8
-#define NVIC_EXTI3_IRQ 9
-#define NVIC_EXTI4_IRQ 10
-#define NVIC_DMA1_STREAM0_IRQ 11
-#define NVIC_DMA1_STREAM1_IRQ 12
-#define NVIC_DMA1_STREAM2_IRQ 13
-#define NVIC_DMA1_STREAM3_IRQ 14
-#define NVIC_DMA1_STREAM4_IRQ 15
-#define NVIC_DMA1_STREAM5_IRQ 16
-#define NVIC_DMA1_STREAM6_IRQ 17
-#define NVIC_ADC_IRQ 18
-#define NVIC_CAN1_TX_IRQ 19
-#define NVIC_CAN1_RX0_IRQ 20
-#define NVIC_CAN1_RX1_IRQ 21
-#define NVIC_CAN1_SCE_IRQ 22
-#define NVIC_EXTI9_5_IRQ 23
-#define NVIC_TIM1_BRK_TIM9_IRQ 24
-#define NVIC_TIM1_UP_TIM10_IRQ 25
-#define NVIC_TIM1_TRG_COM_TIM11_IRQ 26
-#define NVIC_TIM1_CC_IRQ 27
-#define NVIC_TIM2_IRQ 28
-#define NVIC_TIM3_IRQ 29
-#define NVIC_TIM4_IRQ 30
-#define NVIC_I2C1_EV_IRQ 31
-#define NVIC_I2C1_ER_IRQ 32
-#define NVIC_I2C2_EV_IRQ 33
-#define NVIC_I2C2_ER_IRQ 34
-#define NVIC_SPI1_IRQ 35
-#define NVIC_SPI2_IRQ 36
-#define NVIC_USART1_IRQ 37
-#define NVIC_USART2_IRQ 38
-#define NVIC_USART3_IRQ 39
-#define NVIC_EXTI15_10_IRQ 40
-#define NVIC_RTC_ALARM_IRQ 41
-#define NVIC_USB_FS_WKUP_IRQ 42
-#define NVIC_TIM8_BRK_TIM12_IRQ 43
-#define NVIC_TIM8_UP_TIM13_IRQ 44
-#define NVIC_TIM8_TRG_COM_TIM14_IRQ 45
-#define NVIC_TIM8_CC_IRQ 46
-#define NVIC_DMA1_STREAM7_IRQ 47
-#define NVIC_FSMC_IRQ 48
-#define NVIC_SDIO_IRQ 49
-#define NVIC_TIM5_IRQ 50
-#define NVIC_SPI3_IRQ 51
-#define NVIC_UART4_IRQ 52
-#define NVIC_UART5_IRQ 53
-#define NVIC_TIM6_DAC_IRQ 54
-#define NVIC_TIM7_IRQ 55
-#define NVIC_DMA2_STREAM0_IRQ 56
-#define NVIC_DMA2_STREAM1_IRQ 57
-#define NVIC_DMA2_STREAM2_IRQ 58
-#define NVIC_DMA2_STREAM3_IRQ 59
-#define NVIC_DMA2_STREAM4_IRQ 60
-#define NVIC_ETH_IRQ 61
-#define NVIC_ETH_WKUP_IRQ 62
-#define NVIC_CAN2_TX_IRQ 63
-#define NVIC_CAN2_RX0_IRQ 64
-#define NVIC_CAN2_RX1_IRQ 65
-#define NVIC_CAN2_SCE_IRQ 66
-#define NVIC_OTG_FS_IRQ 67
-#define NVIC_DMA2_STREAM5_IRQ 68
-#define NVIC_DMA2_STREAM6_IRQ 69
-#define NVIC_DMA2_STREAM7_IRQ 70
-#define NVIC_USART6_IRQ 71
-#define NVIC_I2C3_EV_IRQ 72
-#define NVIC_I2C3_ER_IRQ 73
-#define NVIC_OTG_HS_EP1_OUT_IRQ 74
-#define NVIC_OTG_HS_EP1_IN_IRQ 75
-#define NVIC_OTG_HS_WKUP_IRQ 76
-#define NVIC_OTG_HS_IRQ 77
-#define NVIC_DCMI_IRQ 78
-#define NVIC_CRYP_IRQ 79
-#define NVIC_HASH_RNG_IRQ 80
-
-#endif
diff --git a/include/libopencm3/stm32/f2/scb.h b/include/libopencm3/stm32/f2/scb.h
deleted file mode 100644
index 181aa7a..0000000
--- a/include/libopencm3/stm32/f2/scb.h
+++ /dev/null
@@ -1,307 +0,0 @@
-/*
- * This file is part of the libopencm3 project.
- *
- * Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
- * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef LIBOPENCM3_SCB_H
-#define LIBOPENCM3_SCB_H
-
-#include <libopencm3/stm32/memorymap.h>
-#include <libopencm3/cm3/common.h>
-
-/* --- SCB: Registers ------------------------------------------------------ */
-
-/* CPUID: CPUID base register */
-#define SCB_CPUID MMIO32(SCB_BASE + 0x00)
-
-/* ICSR: Interrupt Control State Register */
-#define SCB_ICSR MMIO32(SCB_BASE + 0x04)
-
-/* VTOR: Vector Table Offset Register */
-#define SCB_VTOR MMIO32(SCB_BASE + 0x08)
-
-/* AIRCR: Application Interrupt and Reset Control Register */
-#define SCB_AIRCR MMIO32(SCB_BASE + 0x0C)
-
-/* SCR: System Control Register */
-#define SCB_SCR MMIO32(SCB_BASE + 0x10)
-
-/* CCR: Configuration Control Register */
-#define SCB_CCR MMIO32(SCB_BASE + 0x14)
-
-/* SHP: System Handler Priority Registers */
-/* Note: 12 8bit registers */
-#define SCB_SHPR(shpr_id) MMIO8(SCB_BASE + 0x18 + shpr_id)
-#define SCB_SHPR1 MMIO8(SCB_BASE + 0x18 + 1)
-#define SCB_SHPR2 MMIO8(SCB_BASE + 0x18 + 2)
-#define SCB_SHPR3 MMIO8(SCB_BASE + 0x18 + 3)
-
-/* SHCSR: System Handler Control and State Register */
-#define SCB_SHCSR MMIO32(SCB_BASE + 0x24)
-
-/* CFSR: Configurable Fault Status Registers */
-#define SCB_CFSR MMIO32(SCB_BASE + 0x28)
-
-/* HFSR: Hard Fault Status Register */
-#define SCB_HFSR MMIO32(SCB_BASE + 0x2C)
-
-/* DFSR: Debug Fault Status Register */
-#define SCB_DFSR MMIO32(SCB_BASE + 0x30)
-
-/* MMFAR: Memory Manage Fault Address Register */
-#define SCB_MMFAR MMIO32(SCB_BASE + 0x34)
-
-/* BFAR: Bus Fault Address Register */
-#define SCB_BFAR MMIO32(SCB_BASE + 0x38)
-
-/* AFSR: Auxiliary Fault Status Register */
-#define SCB_AFSR MMIO32(SCB_BASE + 0x3C)
-
-/* --- SCB values ---------------------------------------------------------- */
-
-/* --- SCB_CPUID values ---------------------------------------------------- */
-
-/* Implementer[31:24]: Implementer code */
-#define SCP_CPUID_IMPLEMENTER_LSB 24
-/* Variant[23:20]: Variant number */
-#define SCP_CPUID_VARIANT_LSB 20
-/* Constant[19:16]: Reads as 0xF */
-#define SCP_CPUID_CONSTANT_LSB 16
-/* PartNo[15:4]: Part number of the processor */
-#define SCP_CPUID_PARTNO_LSB 4
-/* Revision[3:0]: Revision number */
-#define SCP_CPUID_REVISION_LSB 0
-
-/* --- SCB_ICSR values ----------------------------------------------------- */
-
-/* NMIPENDSET: NMI set-pending bit */
-#define SCB_ICSR_NMIPENDSET (1 << 31)
-/* Bits [30:29]: reserved - must be kept cleared */
-/* PENDSVSET: PendSV set-pending bit */
-#define SCB_ICSR_PENDSVSET (1 << 28)
-/* PENDSVCLR: PendSV clear-pending bit */
-#define SCB_ICSR_PENDSVCLR (1 << 27)
-/* PENDSTSET: SysTick exception set-pending bit */
-#define SCB_ICSR_PENDSTSET (1 << 26)
-/* PENDSTCLR: SysTick exception clear-pending bit */
-#define SCB_ICSR_PENDSTCLR (1 << 25)
-/* Bit 24: reserved - must be kept cleared */
-/* Bit 23: reserved for debug - reads as 0 when not in debug mode */
-/* ISRPENDING: Interrupt pending flag, excluding NMI and Faults */
-#define SCB_ICSR_ISRPENDING (1 << 22)
-/* VECTPENDING[21:12] Pending vector */
-#define SCB_ICSR_VECTPENDING_LSB 12
-/* RETOBASE: Return to base level */
-#define SCB_ICSR_RETOBASE (1 << 11)
-/* Bits [10:9]: reserved - must be kept cleared */
-/* VECTACTIVE[8:0] Active vector */
-#define SCB_ICSR_VECTACTIVE_LSB 0
-
-/* --- SCB_VTOR values ----------------------------------------------------- */
-
-/* Bits [31:30]: reserved - must be kept cleared */
-/* TBLOFF[29:9]: Vector table base offset field */
-#define SCB_VTOR_TBLOFF_LSB 9 /* inconsistent datasheet - LSB could be 11 */
-
-/* --- SCB_AIRCR values ---------------------------------------------------- */
-
-/* VECTKEYSTAT[31:16]/ VECTKEY[31:16] Register key */
-#define SCB_AIRCR_VECTKEYSTAT_LSB 16
-#define SCB_AIRCR_VECTKEY 0x05FA0000
-/* ENDIANESS Data endianness bit */
-#define SCB_AIRCR_ENDIANESS (1 << 15)
-/* Bits [14:11]: reserved - must be kept cleared */
-/* PRIGROUP[10:8]: Interrupt priority grouping field */
-#define SCB_AIRCR_PRIGROUP_GROUP16_NOSUB (0x3 << 8)
-#define SCB_AIRCR_PRIGROUP_GROUP8_SUB2 (0x4 << 8)
-#define SCB_AIRCR_PRIGROUP_GROUP4_SUB4 (0x5 << 8)
-#define SCB_AIRCR_PRIGROUP_GROUP2_SUB8 (0x6 << 8)
-#define SCB_AIRCR_PRIGROUP_NOGROUP_SUB16 (0x7 << 8)
-#define SCB_AIRCR_PRIGROUP_MASK (0x7 << 8)
-#define SCB_AIRCR_PRIGROUP_SHIFT 8
-/* Bits [7:3]: reserved - must be kept cleared */
-/* SYSRESETREQ System reset request */
-#define SCB_AIRCR_SYSRESETREQ (1 << 2)
-/* VECTCLRACTIVE */
-#define SCB_AIRCR_VECTCLRACTIVE (1 << 1)
-/* VECTRESET */
-#define SCB_AIRCR_VECTRESET (1 << 0)
-
-/* --- SCB_SCR values ------------------------------------------------------ */
-
-/* Bits [31:5]: reserved - must be kept cleared */
-/* SEVEONPEND Send Event on Pending bit */
-#define SCB_SCR_SEVEONPEND (1 << 4)
-/* Bit 3: reserved - must be kept cleared */
-/* SLEEPDEEP */
-#define SCB_SCR_SLEEPDEEP (1 << 2)
-/* SLEEPONEXIT */
-#define SCB_SCR_SLEEPONEXIT (1 << 1)
-/* Bit 0: reserved - must be kept cleared */
-
-/* --- SCB_CCR values ------------------------------------------------------ */
-
-/* Bits [31:10]: reserved - must be kept cleared */
-/* STKALIGN */
-#define SCB_CCR_STKALIGN (1 << 9)
-/* BFHFNMIGN */
-#define SCB_CCR_BFHFNMIGN (1 << 8)
-/* Bits [7:5]: reserved - must be kept cleared */
-/* DIV_0_TRP */
-#define SCB_CCR_DIV_0_TRP (1 << 4)
-/* UNALIGN_TRP */
-#define SCB_CCR_UNALIGN_TRP (1 << 3)
-/* Bit 2: reserved - must be kept cleared */
-/* USERSETMPEND */
-#define SCB_CCR_USERSETMPEND (1 << 1)
-/* NONBASETHRDENA */
-#define SCB_CCR_NONBASETHRDENA (1 << 0)
-
-/* --- SCB_SHPR1 values ---------------------------------------------------- */
-
-/* Bits [31:24]: reserved - must be kept cleared */
-/* PRI_6[23:16]: Priority of system handler 6, usage fault */
-#define SCB_SHPR1_PRI_6_LSB 16
-/* PRI_5[15:8]: Priority of system handler 5, bus fault */
-#define SCB_SHPR1_PRI_5_LSB 8
-/* PRI_4[7:0]: Priority of system handler 4, memory management fault */
-#define SCB_SHPR1_PRI_4_LSB 0
-
-/* --- SCB_SHPR2 values ---------------------------------------------------- */
-
-/* PRI_11[31:24]: Priority of system handler 11, SVCall */
-#define SCB_SHPR2_PRI_11_LSB 24
-/* Bits [23:0]: reserved - must be kept cleared */
-
-/* --- SCB_SHPR3 values ---------------------------------------------------- */
-
-/* PRI_15[31:24]: Priority of system handler 15, SysTick exception */
-#define SCB_SHPR3_PRI_15_LSB 24
-/* PRI_14[23:16]: Priority of system handler 14, PendSV */
-#define SCB_SHPR3_PRI_14_LSB 16
-/* Bits [15:0]: reserved - must be kept cleared */
-
-/* --- SCB_SHCSR values ---------------------------------------------------- */
-
-/* Bits [31:19]: reserved - must be kept cleared */
-/* USGFAULTENA: Usage fault enable */
-#define SCB_SHCSR_USGFAULTENA (1 << 18)
-/* BUSFAULTENA: Bus fault enable */
-#define SCB_SHCSR_BUSFAULTENA (1 << 17)
-/* MEMFAULTENA: Memory management fault enable */
-#define SCB_SHCSR_MEMFAULTENA (1 << 16)
-/* SVCALLPENDED: SVC call pending */
-#define SCB_SHCSR_SVCALLPENDED (1 << 15)
-/* BUSFAULTPENDED: Bus fault exception pending */
-#define SCB_SHCSR_BUSFAULTPENDED (1 << 14)
-/* MEMFAULTPENDED: Memory management fault exception pending */
-#define SCB_SHCSR_MEMFAULTPENDED (1 << 13)
-/* USGFAULTPENDED: Usage fault exception pending */
-#define SCB_SHCSR_USGFAULTPENDED (1 << 12)
-/* SYSTICKACT: SysTick exception active */
-#define SCB_SHCSR_SYSTICKACT (1 << 11)
-/* PENDSVACT: PendSV exception active */
-#define SCB_SHCSR_PENDSVACT (1 << 10)
-/* Bit 9: reserved - must be kept cleared */
-/* MONITORACT: Debug monitor active */
-#define SCB_SHCSR_MONITORACT (1 << 8)
-/* SVCALLACT: SVC call active */
-#define SCB_SHCSR_SVCALLACT (1 << 7)
-/* Bits [6:4]: reserved - must be kept cleared */
-/* USGFAULTACT: Usage fault exception active */
-#define SCB_SHCSR_USGFAULTACT (1 << 3)
-/* Bit 2: reserved - must be kept cleared */
-/* BUSFAULTACT: Bus fault exception active */
-#define SCB_SHCSR_BUSFAULTACT (1 << 1)
-/* MEMFAULTACT: Memory management fault exception active */
-#define SCB_SHCSR_MEMFAULTACT (1 << 0)
-
-/* --- SCB_CFSR values ----------------------------------------------------- */
-
-/* Bits [31:26]: reserved - must be kept cleared */
-/* DIVBYZERO: Divide by zero usage fault */
-#define SCB_CFSR_DIVBYZERO (1 << 25)
-/* UNALIGNED: Unaligned access usage fault */
-#define SCB_CFSR_UNALIGNED (1 << 24)
-/* Bits [23:20]: reserved - must be kept cleared */
-/* NOCP: No coprocessor usage fault */
-#define SCB_CFSR_NOCP (1 << 19)
-/* INVPC: Invalid PC load usage fault */
-#define SCB_CFSR_INVPC (1 << 18)
-/* INVSTATE: Invalid state usage fault */
-#define SCB_CFSR_INVSTATE (1 << 17)
-/* UNDEFINSTR: Undefined instruction usage fault */
-#define SCB_CFSR_UNDEFINSTR (1 << 16)
-/* BFARVALID: Bus Fault Address Register (BFAR) valid flag */
-#define SCB_CFSR_BFARVALID (1 << 15)
-/* Bits [14:13]: reserved - must be kept cleared */
-/* STKERR: Bus fault on stacking for exception entry */
-#define SCB_CFSR_STKERR (1 << 12)
-/* UNSTKERR: Bus fault on unstacking for a return from exception */
-#define SCB_CFSR_UNSTKERR (1 << 11)
-/* IMPRECISERR: Imprecise data bus error */
-#define SCB_CFSR_IMPRECISERR (1 << 10)
-/* PRECISERR: Precise data bus error */
-#define SCB_CFSR_PRECISERR (1 << 9)
-/* IBUSERR: Instruction bus error */
-#define SCB_CFSR_IBUSERR (1 << 8)
-/* MMARVALID: Memory Management Fault Address Register (MMAR) valid flag */
-#define SCB_CFSR_MMARVALID (1 << 7)
-/* Bits [6:5]: reserved - must be kept cleared */
-/* MSTKERR: Memory manager fault on stacking for exception entry */
-#define SCB_CFSR_MSTKERR (1 << 4)
-/* MUNSTKERR: Memory manager fault on unstacking for a return from exception */
-#define SCB_CFSR_MUNSTKERR (1 << 3)
-/* Bit 2: reserved - must be kept cleared */
-/* DACCVIOL: Data access violation flag */
-#define SCB_CFSR_DACCVIOL (1 << 1)
-/* IACCVIOL: Instruction access violation flag */
-#define SCB_CFSR_IACCVIOL (1 << 0)
-
-/* --- SCB_HFSR values ----------------------------------------------------- */
-
-/* DEBUG_VT: reserved for debug use */
-#define SCB_HFSR_DEBUG_VT (1 << 31)
-/* FORCED: Forced hard fault */
-#define SCB_HFSR_FORCED (1 << 30)
-/* Bits [29:2]: reserved - must be kept cleared */
-/* VECTTBL: Vector table hard fault */
-#define SCB_HFSR_VECTTBL (1 << 1)
-/* Bit 0: reserved - must be kept cleared */
-
-/* --- SCB_MMFAR values ---------------------------------------------------- */
-
-/* MMFAR [31:0]: Memory management fault address */
-
-/* --- SCB_BFAR values ----------------------------------------------------- */
-
-/* BFAR [31:0]: Bus fault address */
-
-/* --- SCB functions ------------------------------------------------------- */
-
-BEGIN_DECLS
-
-void scb_reset_core(void);
-void scb_reset_system(void);
-void scb_set_priority_grouping(u32 prigroup);
-
-/* TODO: */
-
-END_DECLS
-
-#endif
diff --git a/include/libopencm3/stm32/f2/syscfg.h b/include/libopencm3/stm32/f2/syscfg.h
deleted file mode 100644
index 7426f16..0000000
--- a/include/libopencm3/stm32/f2/syscfg.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * This file is part of the libopencm3 project.
- *
- * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef LIBOPENCM3_SYSCFG_H
-#define LIBOPENCM3_SYSCFG_H
-
-#include <libopencm3/stm32/memorymap.h>
-
-/* --- SYSCFG registers ------------------------------------------------------ */
-
-#define SYSCFG_MEMRM MMIO32(SYSCFG_BASE + 0x00)
-
-#define SYSCFG_PMC MMIO32(SYSCFG_BASE + 0x04)
-
-/* External interrupt configuration register 1 (SYSCFG_EXTICR1) */
-#define SYSCFG_EXTICR1 MMIO32(SYSCFG_BASE + 0x08)
-
-/* External interrupt configuration register 2 (SYSCFG_EXTICR2) */
-#define SYSCFG_EXTICR2 MMIO32(SYSCFG_BASE + 0x0c)
-
-/* External interrupt configuration register 3 (SYSCFG_EXTICR3) */
-#define SYSCFG_EXTICR3 MMIO32(SYSCFG_BASE + 0x10)
-
-/* External interrupt configuration register 4 (SYSCFG_EXTICR4) */
-#define SYSCFG_EXTICR4 MMIO32(SYSCFG_BASE + 0x14)
-
-#define SYSCFG_CMPCR MMIO32(SYSCFG_BASE + 0x20)
-
-#endif
-