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authorFergus Noble2011-09-15 16:26:39 -0700
committerFergus Noble2011-09-15 16:26:39 -0700
commit3a426b34aa38397aca3efc17f83a524fb05ea1ed (patch)
treed7c5792ea07d1ee344530e38c4cf1645b0215652 /include/libopencm3/stm32/f1
parent97413a83f8aecea15a79953703c8a2c320993bc4 (diff)
Moving nvic code to common, adding F1 and F2 specific user interrupt definition headers.
Diffstat (limited to 'include/libopencm3/stm32/f1')
-rw-r--r--include/libopencm3/stm32/f1/nvic_f1.h (renamed from include/libopencm3/stm32/f1/nvic.h)73
1 files changed, 5 insertions, 68 deletions
diff --git a/include/libopencm3/stm32/f1/nvic.h b/include/libopencm3/stm32/f1/nvic_f1.h
index d29c425..b0b32a0 100644
--- a/include/libopencm3/stm32/f1/nvic.h
+++ b/include/libopencm3/stm32/f1/nvic_f1.h
@@ -17,65 +17,14 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
-#ifndef LIBOPENCM3_NVIC_H
-#define LIBOPENCM3_NVIC_H
-
-#include <libopencm3/stm32/memorymap.h>
-#include <libopencm3/cm3/common.h>
-
-/* --- NVIC Registers ------------------------------------------------------ */
-
-/* ISER: Interrupt Set Enable Registers */
-/* Note: 8 32bit Registers */
-#define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + (iser_id * 4))
-
-/* NVIC_BASE + 0x020 (0xE000 E120 - 0xE000 E17F): Reserved */
-
-/* ICER: Interrupt Clear Enable Registers */
-/* Note: 8 32bit Registers */
-#define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + (icer_id * 4))
-
-/* NVIC_BASE + 0x0A0 (0xE000 E1A0 - 0xE000 E1FF): Reserved */
-
-/* ISPR: Interrupt Set Pending Registers */
-/* Note: 8 32bit Registers */
-#define NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + (ispr_id * 4))
-
-/* NVIC_BASE + 0x120 (0xE000 E220 - 0xE000 E27F): Reserved */
-
-/* ICPR: Interrupt Clear Pending Registers */
-/* Note: 8 32bit Registers */
-#define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + (icpr_id * 4))
-
-/* NVIC_BASE + 0x1A0 (0xE000 E2A0 - 0xE00 E2FF): Reserved */
-
-/* IABR: Interrupt Active Bit Register */
-/* Note: 8 32bit Registers */
-#define NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + (iabr_id * 4))
-
-/* NVIC_BASE + 0x220 (0xE000 E320 - 0xE000 E3FF): Reserved */
-
-/* IPR: Interrupt Priority Registers */
-/* Note: 240 8bit Registers */
-#define NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + ipr_id)
-
-/* STIR: Software Trigger Interrupt Register */
-#define NVIC_STIR MMIO32(STIR_BASE)
+#ifndef LIBOPENCM3_NVIC_F1_H
+#define LIBOPENCM3_NVIC_F1_H
/* --- IRQ channel numbers-------------------------------------------------- */
-/* Cortex M3 System Interrupts */
-#define NVIC_NMI_IRQ -14
-#define NVIC_HARD_FAULT_IRQ -13
-#define NVIC_MEM_MANAGE_IRQ -12
-#define NVIC_BUS_FAULT_IRQ -11
-#define NVIC_USAGE_FAULT_IRQ -10
-/* irq numbers -6 to -9 are reserved */
-#define NVIC_SV_CALL_IRQ -5
-#define DEBUG_MONITOR_IRQ -4
-/* irq number -3 reserved */
-#define NVIC_PENDSV_IRQ -2
-#define NVIC_SYSTICK_IRQ -1
+/* Note: These F1 specific user interrupt definitions supplement the
+ * general NVIC definitions in ../nvic.h
+ */
/* User Interrupts */
#define NVIC_WWDG_IRQ 0
@@ -147,16 +96,4 @@
#define NVIC_CAN2_SCE_IRQ 66
#define NVIC_OTG_FS_IRQ 67
-/* --- NVIC functions ------------------------------------------------------ */
-
-void nvic_enable_irq(u8 irqn);
-void nvic_disable_irq(u8 irqn);
-u8 nvic_get_pending_irq(u8 irqn);
-void nvic_set_pending_irq(u8 irqn);
-void nvic_clear_pending_irq(u8 irqn);
-u8 nvic_get_active_irq(u8 irqn);
-u8 nvic_get_irq_enabled(u8 irqn);
-void nvic_set_priority(u8 irqn, u8 priority);
-void nvic_generate_software_interrupt(u8 irqn);
-
#endif