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authorStephen Caudle2011-10-31 11:11:03 -0400
committerStephen Caudle2011-10-31 11:11:03 -0400
commit1fea1df39abde97d1e84f5b99f9793701b1691b7 (patch)
treeec0122ab2b80cea63969cbfb12d19eee15741a5e /include/libopencm3/stm32/f1
parent6da485f06dedb5a0401bdec2ce5ea1c9752f5397 (diff)
Fix more STM32 whitespace issues
Diffstat (limited to 'include/libopencm3/stm32/f1')
-rw-r--r--include/libopencm3/stm32/f1/dma.h166
-rw-r--r--include/libopencm3/stm32/f1/flash.h56
-rw-r--r--include/libopencm3/stm32/f1/gpio.h138
-rw-r--r--include/libopencm3/stm32/f1/scb.h34
-rw-r--r--include/libopencm3/stm32/f1/usb.h221
5 files changed, 308 insertions, 307 deletions
diff --git a/include/libopencm3/stm32/f1/dma.h b/include/libopencm3/stm32/f1/dma.h
index 7d0a856..6fe316e 100644
--- a/include/libopencm3/stm32/f1/dma.h
+++ b/include/libopencm3/stm32/f1/dma.h
@@ -26,152 +26,152 @@
/* --- Convenience macros -------------------------------------------------- */
/* DMA register base adresses (for convenience) */
-#define DMA1 DMA1_BASE
-#define DMA2 DMA2_BASE
+#define DMA1 DMA1_BASE
+#define DMA2 DMA2_BASE
/* --- DMA registers ------------------------------------------------------- */
/* DMA interrupt status register (DMAx_ISR) */
-#define DMA_ISR(dma_base) MMIO32(dma_base + 0x00)
-#define DMA1_ISR DMA_ISR(DMA1)
-#define DMA2_ISR DMA_ISR(DMA2)
+#define DMA_ISR(dma_base) MMIO32(dma_base + 0x00)
+#define DMA1_ISR DMA_ISR(DMA1)
+#define DMA2_ISR DMA_ISR(DMA2)
/* DMA interrupt flag clear register (DMAx_IFCR) */
-#define DMA_IFCR(dma_base) MMIO32(dma_base + 0x04)
-#define DMA1_IFCR DMA_IFCR(DMA1)
-#define DMA2_IFCR DMA_IFCR(DMA2)
+#define DMA_IFCR(dma_base) MMIO32(dma_base + 0x04)
+#define DMA1_IFCR DMA_IFCR(DMA1)
+#define DMA2_IFCR DMA_IFCR(DMA2)
/* DMA channel 1 configuration register (DMAx_CCR1) */
-#define DMA_CCR1(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 0)
-#define DMA1_CCR1 DMA_CCR1(DMA1)
-#define DMA2_CCR1 DMA_CCR1(DMA2)
+#define DMA_CCR1(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 0)
+#define DMA1_CCR1 DMA_CCR1(DMA1)
+#define DMA2_CCR1 DMA_CCR1(DMA2)
/* DMA channel 2 configuration register (DMAx_CCR2) */
-#define DMA_CCR2(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 1)
-#define DMA1_CCR2 DMA_CCR2(DMA1)
-#define DMA2_CCR2 DMA_CCR2(DMA2)
+#define DMA_CCR2(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 1)
+#define DMA1_CCR2 DMA_CCR2(DMA1)
+#define DMA2_CCR2 DMA_CCR2(DMA2)
/* DMA channel 3 configuration register (DMAx_CCR3) */
-#define DMA_CCR3(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 2)
-#define DMA1_CCR3 DMA_CCR3(DMA1)
-#define DMA2_CCR3 DMA_CCR3(DMA2)
+#define DMA_CCR3(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 2)
+#define DMA1_CCR3 DMA_CCR3(DMA1)
+#define DMA2_CCR3 DMA_CCR3(DMA2)
/* DMA channel 4 configuration register (DMAx_CCR4) */
#define DMA_CCR4(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 3)
-#define DMA1_CCR4 DMA_CCR4(DMA1)
-#define DMA2_CCR4 DMA_CCR4(DMA2)
+#define DMA1_CCR4 DMA_CCR4(DMA1)
+#define DMA2_CCR4 DMA_CCR4(DMA2)
/* DMA channel 5 configuration register (DMAx_CCR5) */
-#define DMA_CCR5(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 4)
-#define DMA1_CCR5 DMA_CCR5(DMA1)
-#define DMA2_CCR5 DMA_CCR5(DMA2)
+#define DMA_CCR5(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 4)
+#define DMA1_CCR5 DMA_CCR5(DMA1)
+#define DMA2_CCR5 DMA_CCR5(DMA2)
/* DMA channel 6 configuration register (DMAx_CCR6) */
-#define DMA_CCR6(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 5)
-#define DMA1_CCR6 DMA_CCR6(DMA1)
+#define DMA_CCR6(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 5)
+#define DMA1_CCR6 DMA_CCR6(DMA1)
/* DMA channel 7 configuration register (DMAx_CCR7) */
-#define DMA_CCR7(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 6)
-#define DMA1_CCR7 DMA_CCR7(DMA1)
+#define DMA_CCR7(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 6)
+#define DMA1_CCR7 DMA_CCR7(DMA1)
/* DMA channel 1 number of data register (DMAx_CNDTR1) */
-#define DMA_CNDTR1(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 0)
-#define DMA1_CNDTR1 DMA_CNDTR1(DMA1)
-#define DMA2_CNDTR1 DMA_CNDTR1(DMA2)
+#define DMA_CNDTR1(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 0)
+#define DMA1_CNDTR1 DMA_CNDTR1(DMA1)
+#define DMA2_CNDTR1 DMA_CNDTR1(DMA2)
/* DMA channel 2 number of data register (DMAx_CNDTR2) */
-#define DMA_CNDTR2(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 1)
-#define DMA1_CNDTR2 DMA_CNDTR2(DMA1)
-#define DMA2_CNDTR2 DMA_CNDTR2(DMA2)
+#define DMA_CNDTR2(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 1)
+#define DMA1_CNDTR2 DMA_CNDTR2(DMA1)
+#define DMA2_CNDTR2 DMA_CNDTR2(DMA2)
/* DMA channel 3 number of data register (DMAx_CNDTR3) */
-#define DMA_CNDTR3(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 2)
-#define DMA1_CNDTR3 DMA_CNDTR3(DMA1)
-#define DMA2_CNDTR3 DMA_CNDTR3(DMA2)
+#define DMA_CNDTR3(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 2)
+#define DMA1_CNDTR3 DMA_CNDTR3(DMA1)
+#define DMA2_CNDTR3 DMA_CNDTR3(DMA2)
/* DMA channel 4 number of data register (DMAx_CNDTR4) */
-#define DMA_CNDTR4(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 3)
-#define DMA1_CNDTR4 DMA_CNDTR4(DMA1)
-#define DMA2_CNDTR4 DMA_CNDTR4(DMA2)
+#define DMA_CNDTR4(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 3)
+#define DMA1_CNDTR4 DMA_CNDTR4(DMA1)
+#define DMA2_CNDTR4 DMA_CNDTR4(DMA2)
/* DMA channel 5 number of data register (DMAx_CNDTR5) */
-#define DMA_CNDTR5(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 4)
-#define DMA1_CNDTR5 DMA_CNDTR5(DMA1)
-#define DMA2_CNDTR5 DMA_CNDTR5(DMA2)
+#define DMA_CNDTR5(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 4)
+#define DMA1_CNDTR5 DMA_CNDTR5(DMA1)
+#define DMA2_CNDTR5 DMA_CNDTR5(DMA2)
/* DMA channel 6 number of data register (DMAx_CNDTR6) */
-#define DMA_CNDTR6(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 5)
-#define DMA1_CNDTR6 DMA_CNDTR6(DMA1)
+#define DMA_CNDTR6(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 5)
+#define DMA1_CNDTR6 DMA_CNDTR6(DMA1)
/* DMA channel 7 number of data register (DMAx_CNDTR7) */
-#define DMA_CNDTR7(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 6)
-#define DMA1_CNDTR7 DMA_CNDTR7(DMA1)
+#define DMA_CNDTR7(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 6)
+#define DMA1_CNDTR7 DMA_CNDTR7(DMA1)
/* DMA channel 1 peripheral address register (DMAx_CPAR1) */
-#define DMA_CPAR1(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 0)
-#define DMA1_CPAR1 DMA_CPAR1(DMA1)
-#define DMA2_CPAR1 DMA_CPAR1(DMA2)
+#define DMA_CPAR1(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 0)
+#define DMA1_CPAR1 DMA_CPAR1(DMA1)
+#define DMA2_CPAR1 DMA_CPAR1(DMA2)
/* DMA channel 2 peripheral address register (DMAx_CPAR2) */
-#define DMA_CPAR2(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 1)
-#define DMA1_CPAR2 DMA_CPAR2(DMA1)
-#define DMA2_CPAR2 DMA_CPAR2(DMA2)
+#define DMA_CPAR2(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 1)
+#define DMA1_CPAR2 DMA_CPAR2(DMA1)
+#define DMA2_CPAR2 DMA_CPAR2(DMA2)
/* DMA channel 3 peripheral address register (DMAx_CPAR3) */
-#define DMA_CPAR3(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 2)
-#define DMA1_CPAR3 DMA_CPAR3(DMA1)
-#define DMA2_CPAR3 DMA_CPAR3(DMA2)
+#define DMA_CPAR3(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 2)
+#define DMA1_CPAR3 DMA_CPAR3(DMA1)
+#define DMA2_CPAR3 DMA_CPAR3(DMA2)
/* DMA channel 4 peripheral address register (DMAx_CPAR4) */
-#define DMA_CPAR4(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 3)
-#define DMA1_CPAR4 DMA_CPAR4(DMA1)
-#define DMA2_CPAR4 DMA_CPAR4(DMA2)
+#define DMA_CPAR4(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 3)
+#define DMA1_CPAR4 DMA_CPAR4(DMA1)
+#define DMA2_CPAR4 DMA_CPAR4(DMA2)
/* DMA channel 5 peripheral address register (DMAx_CPAR5) */
-#define DMA_CPAR5(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 4)
-#define DMA1_CPAR5 DMA_CPAR5(DMA1)
-#define DMA2_CPAR5 DMA_CPAR5(DMA2)
+#define DMA_CPAR5(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 4)
+#define DMA1_CPAR5 DMA_CPAR5(DMA1)
+#define DMA2_CPAR5 DMA_CPAR5(DMA2)
/* DMA channel 6 peripheral address register (DMAx_CPAR6) */
-#define DMA_CPAR6(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 5)
-#define DMA1_CPAR6 DMA_CPAR6(DMA1)
+#define DMA_CPAR6(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 5)
+#define DMA1_CPAR6 DMA_CPAR6(DMA1)
/* DMA channel 7 peripheral address register (DMAx_CPAR7) */
-#define DMA_CPAR7(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 6)
-#define DMA1_CPAR7 DMA_CPAR7(DMA1)
+#define DMA_CPAR7(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 6)
+#define DMA1_CPAR7 DMA_CPAR7(DMA1)
/* DMA channel 1 memory address register (DMAx_CMAR1) */
-#define DMA_CMAR1(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 0)
-#define DMA1_CMAR1 DMA_CMAR1(DMA1)
-#define DMA2_CMAR1 DMA_CMAR1(DMA2)
+#define DMA_CMAR1(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 0)
+#define DMA1_CMAR1 DMA_CMAR1(DMA1)
+#define DMA2_CMAR1 DMA_CMAR1(DMA2)
/* DMA channel 2 memory address register (DMAx_CMAR2) */
-#define DMA_CMAR2(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 1)
-#define DMA1_CMAR2 DMA_CMAR2(DMA1)
-#define DMA2_CMAR2 DMA_CMAR2(DMA2)
+#define DMA_CMAR2(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 1)
+#define DMA1_CMAR2 DMA_CMAR2(DMA1)
+#define DMA2_CMAR2 DMA_CMAR2(DMA2)
/* DMA channel 3 memory address register (DMAx_CMAR3) */
-#define DMA_CMAR3(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 2)
-#define DMA1_CMAR3 DMA_CMAR3(DMA1)
-#define DMA2_CMAR3 DMA_CMAR3(DMA2)
+#define DMA_CMAR3(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 2)
+#define DMA1_CMAR3 DMA_CMAR3(DMA1)
+#define DMA2_CMAR3 DMA_CMAR3(DMA2)
/* DMA channel 4 memory address register (DMAx_CMAR4) */
-#define DMA_CMAR4(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 3)
-#define DMA1_CMAR4 DMA_CMAR4(DMA1)
-#define DMA2_CMAR4 DMA_CMAR4(DMA2)
+#define DMA_CMAR4(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 3)
+#define DMA1_CMAR4 DMA_CMAR4(DMA1)
+#define DMA2_CMAR4 DMA_CMAR4(DMA2)
/* DMA channel 5 memory address register (DMAx_CMAR5) */
-#define DMA_CMAR5(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 4)
-#define DMA1_CMAR5 DMA_CMAR5(DMA1)
-#define DMA2_CMAR5 DMA_CMAR5(DMA2)
+#define DMA_CMAR5(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 4)
+#define DMA1_CMAR5 DMA_CMAR5(DMA1)
+#define DMA2_CMAR5 DMA_CMAR5(DMA2)
/* DMA channel 6 memory address register (DMAx_CMAR6) */
-#define DMA_CMAR6(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 5)
-#define DMA1_CMAR6 DMA_CMAR6(DMA1)
+#define DMA_CMAR6(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 5)
+#define DMA1_CMAR6 DMA_CMAR6(DMA1)
/* DMA channel 7 memory address register (DMAx_CMAR7) */
-#define DMA_CMAR7(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 6)
-#define DMA1_CMAR7 DMA_CMAR7(DMA1)
+#define DMA_CMAR7(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 6)
+#define DMA1_CMAR7 DMA_CMAR7(DMA1)
/* --- DMA_ISR values ------------------------------------------------------ */
diff --git a/include/libopencm3/stm32/f1/flash.h b/include/libopencm3/stm32/f1/flash.h
index 9787f45..8512394 100644
--- a/include/libopencm3/stm32/f1/flash.h
+++ b/include/libopencm3/stm32/f1/flash.h
@@ -44,48 +44,48 @@
/* --- FLASH_ACR values ---------------------------------------------------- */
-#define FLASH_PRFTBS (1 << 5)
-#define FLASH_PRFTBE (1 << 4)
-#define FLASH_HLFCYA (1 << 3)
-#define FLASH_LATENCY_0WS 0x00
-#define FLASH_LATENCY_1WS 0x01
-#define FLASH_LATENCY_2WS 0x02
+#define FLASH_PRFTBS (1 << 5)
+#define FLASH_PRFTBE (1 << 4)
+#define FLASH_HLFCYA (1 << 3)
+#define FLASH_LATENCY_0WS 0x00
+#define FLASH_LATENCY_1WS 0x01
+#define FLASH_LATENCY_2WS 0x02
/* --- FLASH_SR values ----------------------------------------------------- */
-#define FLASH_EOP (1 << 5)
-#define FLASH_WRPRTERR (1 << 4)
-#define FLASH_PGERR (1 << 2)
-#define FLASH_BSY (1 << 0)
+#define FLASH_EOP (1 << 5)
+#define FLASH_WRPRTERR (1 << 4)
+#define FLASH_PGERR (1 << 2)
+#define FLASH_BSY (1 << 0)
/* --- FLASH_CR values ----------------------------------------------------- */
-#define FLASH_EOPIE (1 << 12)
-#define FLASH_ERRIE (1 << 10)
-#define FLASH_OPTWRE (1 << 9)
-#define FLASH_LOCK (1 << 7)
-#define FLASH_STRT (1 << 6)
-#define FLASH_OPTER (1 << 5)
-#define FLASH_OPTPG (1 << 4)
-#define FLASH_MER (1 << 2)
-#define FLASH_PER (1 << 1)
-#define FLASH_PG (1 << 0)
+#define FLASH_EOPIE (1 << 12)
+#define FLASH_ERRIE (1 << 10)
+#define FLASH_OPTWRE (1 << 9)
+#define FLASH_LOCK (1 << 7)
+#define FLASH_STRT (1 << 6)
+#define FLASH_OPTER (1 << 5)
+#define FLASH_OPTPG (1 << 4)
+#define FLASH_MER (1 << 2)
+#define FLASH_PER (1 << 1)
+#define FLASH_PG (1 << 0)
/* --- FLASH_OBR values ---------------------------------------------------- */
/* FLASH_OBR[25:18]: Data1 */
/* FLASH_OBR[17:10]: Data0 */
-#define FLASH_NRST_STDBY (1 << 4)
-#define FLASH_NRST_STOP (1 << 3)
-#define FLASH_WDG_SW (1 << 2)
-#define FLASH_RDPRT (1 << 1)
-#define FLASH_OPTERR (1 << 0)
+#define FLASH_NRST_STDBY (1 << 4)
+#define FLASH_NRST_STOP (1 << 3)
+#define FLASH_WDG_SW (1 << 2)
+#define FLASH_RDPRT (1 << 1)
+#define FLASH_OPTERR (1 << 0)
/* --- FLASH Keys -----------------------------------------------------------*/
-#define RDP_KEY ((u16)0x00a5)
-#define FLASH_KEY1 ((u32)0x45670123)
-#define FLASH_KEY2 ((u32)0xcdef89ab)
+#define RDP_KEY ((u16)0x00a5)
+#define FLASH_KEY1 ((u32)0x45670123)
+#define FLASH_KEY2 ((u32)0xcdef89ab)
/* --- Function prototypes ------------------------------------------------- */
diff --git a/include/libopencm3/stm32/f1/gpio.h b/include/libopencm3/stm32/f1/gpio.h
index f1463a3..b812876 100644
--- a/include/libopencm3/stm32/f1/gpio.h
+++ b/include/libopencm3/stm32/f1/gpio.h
@@ -63,22 +63,22 @@
#define GPIO_CAN_RX GPIO_CAN1_RX /* Alias */
#define GPIO_CAN_TX GPIO_CAN1_TX /* Alias */
-#define GPIO_CAN_PB_RX GPIO8 /* PB8 */
-#define GPIO_CAN_PB_TX GPIO9 /* PB9 */
-#define GPIO_CAN1_PB_RX GPIO_CAN_PB_RX /* Alias */
-#define GPIO_CAN1_PB_TX GPIO_CAN_PB_TX /* Alias */
+#define GPIO_CAN_PB_RX GPIO8 /* PB8 */
+#define GPIO_CAN_PB_TX GPIO9 /* PB9 */
+#define GPIO_CAN1_PB_RX GPIO_CAN_PB_RX /* Alias */
+#define GPIO_CAN1_PB_TX GPIO_CAN_PB_TX /* Alias */
-#define GPIO_CAN_PD_RX GPIO0 /* PD0 */
-#define GPIO_CAN_PD_TX GPIO1 /* PD1 */
-#define GPIO_CAN1_PD_RX GPIO_CAN_PD_RX /* Alias */
-#define GPIO_CAN1_PD_TX GPIO_CAN_PD_TX /* Alias */
+#define GPIO_CAN_PD_RX GPIO0 /* PD0 */
+#define GPIO_CAN_PD_TX GPIO1 /* PD1 */
+#define GPIO_CAN1_PD_RX GPIO_CAN_PD_RX /* Alias */
+#define GPIO_CAN1_PD_TX GPIO_CAN_PD_TX /* Alias */
/* CAN2 */
#define GPIO_CAN2_RX GPIO12 /* PB12 */
#define GPIO_CAN2_TX GPIO13 /* PB13 */
-#define GPIO_CAN2_RE_RX GPIO5 /* PB5 */
-#define GPIO_CAN2_RE_TX GPIO6 /* PB6 */
+#define GPIO_CAN2_RE_RX GPIO5 /* PB5 */
+#define GPIO_CAN2_RE_TX GPIO6 /* PB6 */
/* JTAG/SWD */
#define GPIO_JTMS_SWDIO GPIO13 /* PA13 */
@@ -404,32 +404,32 @@
/* --- AFIO_EVCR values ---------------------------------------------------- */
/* EVOE: Event output enable */
-#define AFIO_EVCR_EVOE (1 << 7)
+#define AFIO_EVCR_EVOE (1 << 7)
/* PORT[2:0]: Port selection */
-#define AFIO_EVCR_PORT_PA (0x0 << 4)
-#define AFIO_EVCR_PORT_PB (0x1 << 4)
-#define AFIO_EVCR_PORT_PC (0x2 << 4)
-#define AFIO_EVCR_PORT_PD (0x3 << 4)
-#define AFIO_EVCR_PORT_PE (0x4 << 4)
+#define AFIO_EVCR_PORT_PA (0x0 << 4)
+#define AFIO_EVCR_PORT_PB (0x1 << 4)
+#define AFIO_EVCR_PORT_PC (0x2 << 4)
+#define AFIO_EVCR_PORT_PD (0x3 << 4)
+#define AFIO_EVCR_PORT_PE (0x4 << 4)
/* PIN[3:0]: Pin selection */
-#define AFIO_EVCR_PIN_Px0 (0x0 << 0)
-#define AFIO_EVCR_PIN_Px1 (0x1 << 0)
-#define AFIO_EVCR_PIN_Px2 (0x2 << 0)
-#define AFIO_EVCR_PIN_Px3 (0x3 << 0)
-#define AFIO_EVCR_PIN_Px4 (0x4 << 0)
-#define AFIO_EVCR_PIN_Px5 (0x5 << 0)
-#define AFIO_EVCR_PIN_Px6 (0x6 << 0)
-#define AFIO_EVCR_PIN_Px7 (0x7 << 0)
-#define AFIO_EVCR_PIN_Px8 (0x8 << 0)
-#define AFIO_EVCR_PIN_Px9 (0x9 << 0)
-#define AFIO_EVCR_PIN_Px10 (0xA << 0)
-#define AFIO_EVCR_PIN_Px11 (0xB << 0)
-#define AFIO_EVCR_PIN_Px12 (0xC << 0)
-#define AFIO_EVCR_PIN_Px13 (0xD << 0)
-#define AFIO_EVCR_PIN_Px14 (0xE << 0)
-#define AFIO_EVCR_PIN_Px15 (0xF << 0)
+#define AFIO_EVCR_PIN_Px0 (0x0 << 0)
+#define AFIO_EVCR_PIN_Px1 (0x1 << 0)
+#define AFIO_EVCR_PIN_Px2 (0x2 << 0)
+#define AFIO_EVCR_PIN_Px3 (0x3 << 0)
+#define AFIO_EVCR_PIN_Px4 (0x4 << 0)
+#define AFIO_EVCR_PIN_Px5 (0x5 << 0)
+#define AFIO_EVCR_PIN_Px6 (0x6 << 0)
+#define AFIO_EVCR_PIN_Px7 (0x7 << 0)
+#define AFIO_EVCR_PIN_Px8 (0x8 << 0)
+#define AFIO_EVCR_PIN_Px9 (0x9 << 0)
+#define AFIO_EVCR_PIN_Px10 (0xA << 0)
+#define AFIO_EVCR_PIN_Px11 (0xB << 0)
+#define AFIO_EVCR_PIN_Px12 (0xC << 0)
+#define AFIO_EVCR_PIN_Px13 (0xD << 0)
+#define AFIO_EVCR_PIN_Px14 (0xE << 0)
+#define AFIO_EVCR_PIN_Px15 (0xF << 0)
/* --- AFIO_MAPR values ---------------------------------------------------- */
@@ -437,98 +437,98 @@
/* PTP_PPS_REMAP: Ethernet PTP PPS remapping
* (only connectivity line devices) */
-#define AFIO_MAPR_PTP_PPS_REMAP (1 << 30)
+#define AFIO_MAPR_PTP_PPS_REMAP (1 << 30)
/* TIM2ITR1_IREMAP: TIM2 internal trigger 1 remapping
* (only connectivity line devices) */
-#define AFIO_MAPR_TIM2ITR1_IREMAP (1 << 29)
+#define AFIO_MAPR_TIM2ITR1_IREMAP (1 << 29)
/* SPI3_REMAP: SPI3/I2S3 remapping
* (only connectivity line devices) */
-#define AFIO_MAPR_SPI3_REMAP (1 << 28)
+#define AFIO_MAPR_SPI3_REMAP (1 << 28)
/* 27 reserved */
/* SWJ_CFG[2:0]: Serial wire JTAG configuration */
-#define AFIO_MAPR_SWJ_CFG_FULL_SWJ (0x0 << 24)
-#define AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_JNTRST (0x1 << 24)
-#define AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_ON (0x2 << 24)
-#define AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_OFF (0x4 << 24)
+#define AFIO_MAPR_SWJ_CFG_FULL_SWJ (0x0 << 24)
+#define AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_JNTRST (0x1 << 24)
+#define AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_ON (0x2 << 24)
+#define AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_OFF (0x4 << 24)
/* MII_REMAP: MII or RMII selection
* (only connectivity line devices) */
-#define AFIO_MAPR_MII_RMII_SEL (1 << 23)
+#define AFIO_MAPR_MII_RMII_SEL (1 << 23)
/* CAN2_REMAP: CAN2 I/O remapping
* (only connectivity line devices) */
-#define AFIO_MAPR_CAN2_REMAP (1 << 22)
+#define AFIO_MAPR_CAN2_REMAP (1 << 22)
/* ETH_REMAP: Ethernet MAC I/O remapping
* (only connectivity line devices) */
-#define AFIO_MAPR_ETH_REMAP (1 << 21)
+#define AFIO_MAPR_ETH_REMAP (1 << 21)
/* ADC2_ETRGREG_REMAP: ADC2 external trigger regulator conversion remapping
* (only low-, medium-, high- and XL-densitiy devices) */
-#define AFIO_MAPR_ADC2_ETRGREG_REMAP (1 << 20)
+#define AFIO_MAPR_ADC2_ETRGREG_REMAP (1 << 20)
/* ADC2_ETRGINJ_REMAP: ADC2 external trigger injected conversion remapping
* (only low-, medium-, high- and XL-densitiy devices) */
-#define AFIO_MAPR_ADC2_ETRGINJ_REMAP (1 << 19)
+#define AFIO_MAPR_ADC2_ETRGINJ_REMAP (1 << 19)
/* ADC1_ETRGREG_REMAP: ADC1 external trigger regulator conversion remapping
* (only low-, medium-, high- and XL-densitiy devices) */
-#define AFIO_MAPR_ADC1_ETRGREG_REMAP (1 << 18)
+#define AFIO_MAPR_ADC1_ETRGREG_REMAP (1 << 18)
/* ADC1_ETRGINJ_REMAP: ADC1 external trigger injected conversion remapping
* (only low-, medium-, high- and XL-densitiy devices) */
-#define AFIO_MAPR_ADC1_ETRGINJ_REMAP (1 << 17)
+#define AFIO_MAPR_ADC1_ETRGINJ_REMAP (1 << 17)
/* TIM5CH4_IREMAP: TIM5 channel4 internal remap */
-#define AFIO_MAPR_TIM5CH4_IREMAP (1 << 16)
+#define AFIO_MAPR_TIM5CH4_IREMAP (1 << 16)
/* PD01_REMAP: Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
-#define AFIO_MAPR_PD01_REMAP (1 << 15)
+#define AFIO_MAPR_PD01_REMAP (1 << 15)
/* CAN_REMAP[1:0]: CAN1 alternate function remapping */
-#define AFIO_MAPR_CAN1_REMAP_PORTA (0x0 << 13)
-#define AFIO_MAPR_CAN1_REMAP_PORTB (0x2 << 13) /* Not on 36pin pkg */
-#define AFIO_MAPR_CAN1_REMAP_PORTD (0x3 << 13)
+#define AFIO_MAPR_CAN1_REMAP_PORTA (0x0 << 13)
+#define AFIO_MAPR_CAN1_REMAP_PORTB (0x2 << 13) /* Not on 36pin pkg */
+#define AFIO_MAPR_CAN1_REMAP_PORTD (0x3 << 13)
/* TIM4_REMAP: TIM4 remapping */
-#define AFIO_MAPR_TIM4_REMAP (1 << 12)
+#define AFIO_MAPR_TIM4_REMAP (1 << 12)
/* TIM3_REMAP[1:0]: TIM3 remapping */
-#define AFIO_MAPR_TIM3_REMAP_NO_REMAP (0x0 << 10)
-#define AFIO_MAPR_TIM3_REMAP_PARTIAL_REMAP (0x2 << 10)
-#define AFIO_MAPR_TIM3_REMAP_FULL_REMAP (0x3 << 10)
+#define AFIO_MAPR_TIM3_REMAP_NO_REMAP (0x0 << 10)
+#define AFIO_MAPR_TIM3_REMAP_PARTIAL_REMAP (0x2 << 10)
+#define AFIO_MAPR_TIM3_REMAP_FULL_REMAP (0x3 << 10)
/* TIM2_REMAP[1:0]: TIM2 remapping */
-#define AFIO_MAPR_TIM2_REMAP_NO_REMAP (0x0 << 8)
-#define AFIO_MAPR_TIM2_REMAP_PARTIAL_REMAP1 (0x1 << 8)
-#define AFIO_MAPR_TIM2_REMAP_PARTIAL_REMAP2 (0x2 << 8)
-#define AFIO_MAPR_TIM2_REMAP_FULL_REMAP (0x3 << 8)
+#define AFIO_MAPR_TIM2_REMAP_NO_REMAP (0x0 << 8)
+#define AFIO_MAPR_TIM2_REMAP_PARTIAL_REMAP1 (0x1 << 8)
+#define AFIO_MAPR_TIM2_REMAP_PARTIAL_REMAP2 (0x2 << 8)
+#define AFIO_MAPR_TIM2_REMAP_FULL_REMAP (0x3 << 8)
/* TIM1_REMAP[1:0]: TIM1 remapping */
-#define AFIO_MAPR_TIM1_REMAP_NO_REMAP (0x0 << 6)
-#define AFIO_MAPR_TIM1_REMAP_PARTIAL_REMAP (0x1 << 6)
-#define AFIO_MAPR_TIM1_REMAP_FULL_REMAP (0x3 << 6)
+#define AFIO_MAPR_TIM1_REMAP_NO_REMAP (0x0 << 6)
+#define AFIO_MAPR_TIM1_REMAP_PARTIAL_REMAP (0x1 << 6)
+#define AFIO_MAPR_TIM1_REMAP_FULL_REMAP (0x3 << 6)
/* USART3_REMAP[1:0]: USART3 remapping */
-#define AFIO_MAPR_USART3_REMAP_NO_REMAP (0x0 << 4)
-#define AFIO_MAPR_USART3_REMAP_PARTIAL_REMAP (0x1 << 4)
-#define AFIO_MAPR_USART3_REMAP_FULL_REMAP (0x3 << 4)
+#define AFIO_MAPR_USART3_REMAP_NO_REMAP (0x0 << 4)
+#define AFIO_MAPR_USART3_REMAP_PARTIAL_REMAP (0x1 << 4)
+#define AFIO_MAPR_USART3_REMAP_FULL_REMAP (0x3 << 4)
/* USART2_REMAP[1:0]: USART2 remapping */
-#define AFIO_MAPR_USART2_REMAP (1 << 3)
+#define AFIO_MAPR_USART2_REMAP (1 << 3)
/* USART1_REMAP[1:0]: USART1 remapping */
-#define AFIO_MAPR_USART1_REMAP (1 << 2)
+#define AFIO_MAPR_USART1_REMAP (1 << 2)
/* I2C1_REMAP[1:0]: I2C1 remapping */
-#define AFIO_MAPR_I2C1_REMAP (1 << 1)
+#define AFIO_MAPR_I2C1_REMAP (1 << 1)
/* SPI1_REMAP[1:0]: SPI1 remapping */
-#define AFIO_MAPR_SPI1_REMAP (1 << 0)
+#define AFIO_MAPR_SPI1_REMAP (1 << 0)
/* --- AFIO_EXTICR1 values ------------------------------------------------- */
/* --- AFIO_EXTICR2 values ------------------------------------------------- */
diff --git a/include/libopencm3/stm32/f1/scb.h b/include/libopencm3/stm32/f1/scb.h
index 9594cf1..b73ada3 100644
--- a/include/libopencm3/stm32/f1/scb.h
+++ b/include/libopencm3/stm32/f1/scb.h
@@ -27,50 +27,50 @@
/* --- SCB: Registers ------------------------------------------------------ */
/* CPUID: CPUID base register */
-#define SCB_CPUID MMIO32(SCB_BASE + 0x00)
+#define SCB_CPUID MMIO32(SCB_BASE + 0x00)
/* ICSR: Interrupt Control State Register */
-#define SCB_ICSR MMIO32(SCB_BASE + 0x04)
+#define SCB_ICSR MMIO32(SCB_BASE + 0x04)
/* VTOR: Vector Table Offset Register */
-#define SCB_VTOR MMIO32(SCB_BASE + 0x08)
+#define SCB_VTOR MMIO32(SCB_BASE + 0x08)
/* AIRCR: Application Interrupt and Reset Control Register */
-#define SCB_AIRCR MMIO32(SCB_BASE + 0x0C)
+#define SCB_AIRCR MMIO32(SCB_BASE + 0x0C)
/* SCR: System Control Register */
-#define SCB_SCR MMIO32(SCB_BASE + 0x10)
+#define SCB_SCR MMIO32(SCB_BASE + 0x10)
/* CCR: Configuration Control Register */
-#define SCB_CCR MMIO32(SCB_BASE + 0x14)
+#define SCB_CCR MMIO32(SCB_BASE + 0x14)
/* SHP: System Handler Priority Registers */
/* Note: 12 8bit registers */
-#define SCB_SHPR(shpr_id) MMIO8(SCB_BASE + 0x18 + shpr_id)
-#define SCB_SHPR1 MMIO8(SCB_BASE + 0x18 + 1)
-#define SCB_SHPR2 MMIO8(SCB_BASE + 0x18 + 2)
-#define SCB_SHPR3 MMIO8(SCB_BASE + 0x18 + 3)
+#define SCB_SHPR(shpr_id) MMIO8(SCB_BASE + 0x18 + shpr_id)
+#define SCB_SHPR1 MMIO8(SCB_BASE + 0x18 + 1)
+#define SCB_SHPR2 MMIO8(SCB_BASE + 0x18 + 2)
+#define SCB_SHPR3 MMIO8(SCB_BASE + 0x18 + 3)
/* SHCSR: System Handler Control and State Register */
-#define SCB_SHCSR MMIO32(SCB_BASE + 0x24)
+#define SCB_SHCSR MMIO32(SCB_BASE + 0x24)
/* CFSR: Configurable Fault Status Registers */
-#define SCB_CFSR MMIO32(SCB_BASE + 0x28)
+#define SCB_CFSR MMIO32(SCB_BASE + 0x28)
/* HFSR: Hard Fault Status Register */
-#define SCB_HFSR MMIO32(SCB_BASE + 0x2C)
+#define SCB_HFSR MMIO32(SCB_BASE + 0x2C)
/* DFSR: Debug Fault Status Register */
-#define SCB_DFSR MMIO32(SCB_BASE + 0x30)
+#define SCB_DFSR MMIO32(SCB_BASE + 0x30)
/* MMFAR: Memory Manage Fault Address Register */
-#define SCB_MMFAR MMIO32(SCB_BASE + 0x34)
+#define SCB_MMFAR MMIO32(SCB_BASE + 0x34)
/* BFAR: Bus Fault Address Register */
-#define SCB_BFAR MMIO32(SCB_BASE + 0x38)
+#define SCB_BFAR MMIO32(SCB_BASE + 0x38)
/* AFSR: Auxiliary Fault Status Register */
-#define SCB_AFSR MMIO32(SCB_BASE + 0x3C)
+#define SCB_AFSR MMIO32(SCB_BASE + 0x3C)
/* --- SCB values ---------------------------------------------------------- */
diff --git a/include/libopencm3/stm32/f1/usb.h b/include/libopencm3/stm32/f1/usb.h
index e35075d..0aed34c 100644
--- a/include/libopencm3/stm32/f1/usb.h
+++ b/include/libopencm3/stm32/f1/usb.h
@@ -26,134 +26,135 @@
/* --- USB base addresses -------------------------------------------------- */
-#define USB_PMA_BASE 0x40006000L /* USB packet buffer memory base addr. */
+/* USB packet buffer memory base addr. */
+#define USB_PMA_BASE 0x40006000L
/* --- USB general registers ----------------------------------------------- */
/* USB Control register */
-#define USB_CNTR_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x40))
+#define USB_CNTR_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x40))
/* USB Interrupt status register */
-#define USB_ISTR_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x44))
+#define USB_ISTR_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x44))
/* USB Frame number register */
-#define USB_FNR_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x48))
+#define USB_FNR_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x48))
/* USB Device address register */
-#define USB_DADDR_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x4C))
+#define USB_DADDR_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x4C))
/* USB Buffer table address register */
-#define USB_BTABLE_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x50))
+#define USB_BTABLE_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x50))
/* USB EP register */
-#define USB_EP_REG(EP) ((volatile u32 *)(USB_DEV_FS_BASE) + (EP))
+#define USB_EP_REG(EP) ((volatile u32 *)(USB_DEV_FS_BASE) + (EP))
/* --- USB control register masks / bits ----------------------------------- */
/* Interrupt mask bits, set to 1 to enable interrupt generation */
-#define USB_CNTR_CTRM 0x8000
-#define USB_CNTR_PMAOVRM 0x4000
-#define USB_CNTR_ERRM 0x2000
-#define USB_CNTR_WKUPM 0x1000
-#define USB_CNTR_SUSPM 0x0800
-#define USB_CNTR_RESETM 0x0400
-#define USB_CNTR_SOFM 0x0200
-#define USB_CNTR_ESOFM 0x0100
+#define USB_CNTR_CTRM 0x8000
+#define USB_CNTR_PMAOVRM 0x4000
+#define USB_CNTR_ERRM 0x2000
+#define USB_CNTR_WKUPM 0x1000
+#define USB_CNTR_SUSPM 0x0800
+#define USB_CNTR_RESETM 0x0400
+#define USB_CNTR_SOFM 0x0200
+#define USB_CNTR_ESOFM 0x0100
/* Request/Force bits */
-#define USB_CNTR_RESUME 0x0010 /* Resume request */
-#define USB_CNTR_FSUSP 0x0008 /* Force suspend */
-#define USB_CNTR_LP_MODE 0x0004 /* Low-power mode */
-#define USB_CNTR_PWDN 0x0002 /* Power down */
-#define USB_CNTR_FRES 0x0001 /* Force reset */
+#define USB_CNTR_RESUME 0x0010 /* Resume request */
+#define USB_CNTR_FSUSP 0x0008 /* Force suspend */
+#define USB_CNTR_LP_MODE 0x0004 /* Low-power mode */
+#define USB_CNTR_PWDN 0x0002 /* Power down */
+#define USB_CNTR_FRES 0x0001 /* Force reset */
/* --- USB interrupt status register masks / bits -------------------------- */
-#define USB_ISTR_CTR 0x8000 /* Correct Transfer */
-#define USB_ISTR_PMAOVR 0x4000 /* Packet Memory Area Over / Underrun */
-#define USB_ISTR_ERR 0x2000 /* Error */
-#define USB_ISTR_WKUP 0x1000 /* Wake up */
-#define USB_ISTR_SUSP 0x0800 /* Suspend mode request */
-#define USB_ISTR_RESET 0x0400 /* USB RESET request */
-#define USB_ISTR_SOF 0x0200 /* Start Of Frame */
-#define USB_ISTR_ESOF 0x0100 /* Expected Start Of Frame */
-#define USB_ISTR_DIR 0x0010 /* Direction of transaction */
-#define USB_ISTR_EP_ID 0x000F /* Endpoint Identifier */
+#define USB_ISTR_CTR 0x8000 /* Correct Transfer */
+#define USB_ISTR_PMAOVR 0x4000 /* Packet Memory Area Over / Underrun */
+#define USB_ISTR_ERR 0x2000 /* Error */
+#define USB_ISTR_WKUP 0x1000 /* Wake up */
+#define USB_ISTR_SUSP 0x0800 /* Suspend mode request */
+#define USB_ISTR_RESET 0x0400 /* USB RESET request */
+#define USB_ISTR_SOF 0x0200 /* Start Of Frame */
+#define USB_ISTR_ESOF 0x0100 /* Expected Start Of Frame */
+#define USB_ISTR_DIR 0x0010 /* Direction of transaction */
+#define USB_ISTR_EP_ID 0x000F /* Endpoint Identifier */
/* --- USB interrupt status register manipulators -------------------------- */
/* Note: CTR is read only! */
-#define USB_CLR_ISTR_PMAOVR() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_PMAOVR)
-#define USB_CLR_ISTR_ERR() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_ERR)
-#define USB_CLR_ISTR_WKUP() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_WKUP)
-#define USB_CLR_ISTR_SUSP() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_SUSP)
-#define USB_CLR_ISTR_RESET() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_RESET)
-#define USB_CLR_ISTR_SOF() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_SOF)
-#define USB_CLR_ISTR_ESOF() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_ESOF)
+#define USB_CLR_ISTR_PMAOVR() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_PMAOVR)
+#define USB_CLR_ISTR_ERR() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_ERR)
+#define USB_CLR_ISTR_WKUP() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_WKUP)
+#define USB_CLR_ISTR_SUSP() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_SUSP)
+#define USB_CLR_ISTR_RESET() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_RESET)
+#define USB_CLR_ISTR_SOF() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_SOF)
+#define USB_CLR_ISTR_ESOF() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_ESOF)
/* --- USB device addres register masks / bits ----------------------------- */
-#define USB_DADDR_ENABLE 0x0080
-#define USB_DADDR_ADDR 0x007F
+#define USB_DADDR_ENABLE 0x0080
+#define USB_DADDR_ADDR 0x007F
/* --- USB device addres register manipulators ----------------------------- */
/* --- USB endpoint register offsets --------------------------------------- */
-#define USB_EP0 0
-#define USB_EP1 1
-#define USB_EP2 2
-#define USB_EP3 3
-#define USB_EP4 4
-#define USB_EP5 5
-#define USB_EP6 6
-#define USB_EP7 7
+#define USB_EP0 0
+#define USB_EP1 1
+#define USB_EP2 2
+#define USB_EP3 3
+#define USB_EP4 4
+#define USB_EP5 5
+#define USB_EP6 6
+#define USB_EP7 7
/* --- USB endpoint register masks / bits ---------------------------------- */
/* Masks and toggle bits */
-#define USB_EP_RX_CTR 0x8000 /* Correct transfer RX */
-#define USB_EP_RX_DTOG 0x4000 /* Data toggle RX */
-#define USB_EP_RX_STAT 0x3000 /* Endpoint status for RX */
+#define USB_EP_RX_CTR 0x8000 /* Correct transfer RX */
+#define USB_EP_RX_DTOG 0x4000 /* Data toggle RX */
+#define USB_EP_RX_STAT 0x3000 /* Endpoint status for RX */
-#define USB_EP_SETUP 0x0800 /* Setup transaction completed */
-#define USB_EP_TYPE 0x0600 /* Endpoint type */
-#define USB_EP_KIND 0x0100 /* Endpoint kind.
+#define USB_EP_SETUP 0x0800 /* Setup transaction completed */
+#define USB_EP_TYPE 0x0600 /* Endpoint type */
+#define USB_EP_KIND 0x0100 /* Endpoint kind.
* When set and type=bulk -> double buffer
* When set and type=control -> status out
*/
-#define USB_EP_TX_CTR 0x0080 /* Correct transfer TX */
-#define USB_EP_TX_DTOG 0x0040 /* Data toggle TX */
-#define USB_EP_TX_STAT 0x0030 /* Endpoint status for TX */
+#define USB_EP_TX_CTR 0x0080 /* Correct transfer TX */
+#define USB_EP_TX_DTOG 0x0040 /* Data toggle TX */
+#define USB_EP_TX_STAT 0x0030 /* Endpoint status for TX */
-#define USB_EP_ADDR 0x000F /* Endpoint Address */
+#define USB_EP_ADDR 0x000F /* Endpoint Address */
/* Masking all toggle bits */
-#define USB_EP_NTOGGLE_MSK (USB_EP_RX_CTR | \
- USB_EP_SETUP | \
- USB_EP_TYPE | \
- USB_EP_KIND | \
- USB_EP_TX_CTR | \
- USB_EP_ADDR)
+#define USB_EP_NTOGGLE_MSK (USB_EP_RX_CTR | \
+ USB_EP_SETUP | \
+ USB_EP_TYPE | \
+ USB_EP_KIND | \
+ USB_EP_TX_CTR | \
+ USB_EP_ADDR)
/* All non toggle bits plus EP_RX toggle bits */
-#define USB_EP_RX_STAT_TOG_MSK (USB_EP_RX_STAT | USB_EP_NTOGGLE_MSK)
+#define USB_EP_RX_STAT_TOG_MSK (USB_EP_RX_STAT | USB_EP_NTOGGLE_MSK)
/* All non toggle bits plus EP_TX toggle bits */
-#define USB_EP_TX_STAT_TOG_MSK (USB_EP_TX_STAT | USB_EP_NTOGGLE_MSK)
+#define USB_EP_TX_STAT_TOG_MSK (USB_EP_TX_STAT | USB_EP_NTOGGLE_MSK)
/* Endpoint status bits for USB_EP_RX_STAT bit field */
-#define USB_EP_RX_STAT_DISABLED 0x0000
-#define USB_EP_RX_STAT_STALL 0x1000
-#define USB_EP_RX_STAT_NAK 0x2000
-#define USB_EP_RX_STAT_VALID 0x3000
+#define USB_EP_RX_STAT_DISABLED 0x0000
+#define USB_EP_RX_STAT_STALL 0x1000
+#define USB_EP_RX_STAT_NAK 0x2000
+#define USB_EP_RX_STAT_VALID 0x3000
/* Endpoint status bits for USB_EP_TX_STAT bit field */
-#define USB_EP_TX_STAT_DISABLED 0x0000
-#define USB_EP_TX_STAT_STALL 0x0010
-#define USB_EP_TX_STAT_NAK 0x0020
-#define USB_EP_TX_STAT_VALID 0x0030
+#define USB_EP_TX_STAT_DISABLED 0x0000
+#define USB_EP_TX_STAT_STALL 0x0010
+#define USB_EP_TX_STAT_NAK 0x0020
+#define USB_EP_TX_STAT_VALID 0x0030
/* Endpoint type bits for USB_EP_TYPE bit field */
-#define USB_EP_TYPE_BULK 0x0000
-#define USB_EP_TYPE_CONTROL 0x0200
-#define USB_EP_TYPE_ISO 0x0400
-#define USB_EP_TYPE_INTERRUPT 0x0600
+#define USB_EP_TYPE_BULK 0x0000
+#define USB_EP_TYPE_CONTROL 0x0200
+#define USB_EP_TYPE_ISO 0x0400
+#define USB_EP_TYPE_INTERRUPT 0x0600
/* --- USB endpoint register manipulators ---------------------------------- */
@@ -185,46 +186,46 @@
#define USB_CLR_EP_TX_CTR(EP) \
USB_CLR_EP_NTOGGLE_BIT(EP, USB_EP_TX_CTR)
-#define USB_SET_EP_TYPE(EP, TYPE) \
- SET_REG(USB_EP_REG(EP), \
- (GET_REG(USB_EP_REG(EP)) & \
- (USB_EP_NTOGGLE_MSK & \
- (~USB_EP_TYPE))) | TYPE)
+#define USB_SET_EP_TYPE(EP, TYPE) \
+ SET_REG(USB_EP_REG(EP), \
+ (GET_REG(USB_EP_REG(EP)) & \
+ (USB_EP_NTOGGLE_MSK & \
+ (~USB_EP_TYPE))) | TYPE)
-#define USB_SET_EP_KIND(EP) \
- SET_REG(USB_EP_REG(EP), \
- (GET_REG(USB_EP_REG(EP)) & \
- (USB_EP_NTOGGLE_MSK & \
- (~USB_EP_KIND))) | USB_EP_KIND)
+#define USB_SET_EP_KIND(EP) \
+ SET_REG(USB_EP_REG(EP), \
+ (GET_REG(USB_EP_REG(EP)) & \
+ (USB_EP_NTOGGLE_MSK & \
+ (~USB_EP_KIND))) | USB_EP_KIND)
#define USB_CLR_EP_KIND(EP) \
SET_REG(USB_EP_REG(EP), \
(GET_REG(USB_EP_REG(EP)) & \
- (USB_EP_NTOGGLE_MSK & (~USB_EP_KIND))))
+ (USB_EP_NTOGGLE_MSK & (~USB_EP_KIND))))
-#define USB_SET_EP_STAT_OUT(EP) USB_SET_EP_KIND(EP)
-#define USB_CLR_EP_STAT_OUT(EP) USB_CLR_EP_KIND(EP)
+#define USB_SET_EP_STAT_OUT(EP) USB_SET_EP_KIND(EP)
+#define USB_CLR_EP_STAT_OUT(EP) USB_CLR_EP_KIND(EP)
-#define USB_SET_EP_ADDR(EP, ADDR) \
- SET_REG(USB_EP_REG(EP), \
- ((GET_REG(USB_EP_REG(EP)) & \
- (USB_EP_NTOGGLE_MSK & \
- (~USB_EP_ADDR))) | ADDR))
+#define USB_SET_EP_ADDR(EP, ADDR) \
+ SET_REG(USB_EP_REG(EP), \
+ ((GET_REG(USB_EP_REG(EP)) & \
+ (USB_EP_NTOGGLE_MSK & \
+ (~USB_EP_ADDR))) | ADDR))
/* Macros for clearing DTOG bits */
-#define USB_CLR_EP_TX_DTOG(EP) \
- SET_REG(USB_EP_REG(EP), \
- GET_REG(USB_EP_REG(EP)) & \
+#define USB_CLR_EP_TX_DTOG(EP) \
+ SET_REG(USB_EP_REG(EP), \
+ GET_REG(USB_EP_REG(EP)) & \
(USB_EP_NTOGGLE_MSK | USB_EP_TX_DTOG))
-#define USB_CLR_EP_RX_DTOG(EP) \
- SET_REG(USB_EP_REG(EP), \
- GET_REG(USB_EP_REG(EP)) & \
+#define USB_CLR_EP_RX_DTOG(EP) \
+ SET_REG(USB_EP_REG(EP), \
+ GET_REG(USB_EP_REG(EP)) & \
(USB_EP_NTOGGLE_MSK | USB_EP_RX_DTOG))
/* --- USB BTABLE registers ------------------------------------------------ */
-#define USB_GET_BTABLE GET_REG(USB_BTABLE_REG)
+#define USB_GET_BTABLE GET_REG(USB_BTABLE_REG)
#define USB_EP_TX_ADDR(EP) \
((u32 *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 0) * 2))
@@ -240,14 +241,14 @@
/* --- USB BTABLE manipulators --------------------------------------------- */
-#define USB_GET_EP_TX_ADDR(EP) GET_REG(USB_EP_TX_ADDR(EP))
-#define USB_GET_EP_TX_COUNT(EP) GET_REG(USB_EP_TX_COUNT(EP))
-#define USB_GET_EP_RX_ADDR(EP) GET_REG(USB_EP_RX_ADDR(EP))
-#define USB_GET_EP_RX_COUNT(EP) GET_REG(USB_EP_RX_COUNT(EP))
-#define USB_SET_EP_TX_ADDR(EP, ADDR) SET_REG(USB_EP_TX_ADDR(EP), ADDR)
-#define USB_SET_EP_TX_COUNT(EP, COUNT) SET_REG(USB_EP_TX_COUNT(EP), COUNT)
-#define USB_SET_EP_RX_ADDR(EP, ADDR) SET_REG(USB_EP_RX_ADDR(EP), ADDR)
-#define USB_SET_EP_RX_COUNT(EP, COUNT) SET_REG(USB_EP_RX_COUNT(EP), COUNT)
+#define USB_GET_EP_TX_ADDR(EP) GET_REG(USB_EP_TX_ADDR(EP))
+#define USB_GET_EP_TX_COUNT(EP) GET_REG(USB_EP_TX_COUNT(EP))
+#define USB_GET_EP_RX_ADDR(EP) GET_REG(USB_EP_RX_ADDR(EP))
+#define USB_GET_EP_RX_COUNT(EP) GET_REG(USB_EP_RX_COUNT(EP))
+#define USB_SET_EP_TX_ADDR(EP, ADDR) SET_REG(USB_EP_TX_ADDR(EP), ADDR)
+#define USB_SET_EP_TX_COUNT(EP, COUNT) SET_REG(USB_EP_TX_COUNT(EP), COUNT)
+#define USB_SET_EP_RX_ADDR(EP, ADDR) SET_REG(USB_EP_RX_ADDR(EP), ADDR)
+#define USB_SET_EP_RX_COUNT(EP, COUNT) SET_REG(USB_EP_RX_COUNT(EP), COUNT)
#define USB_GET_EP_TX_BUFF(EP) \
(USB_PMA_BASE + (u8 *)(USB_GET_EP_TX_ADDR(EP) * 2))