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authorchrysn2012-09-15 01:29:31 +0200
committerchrysn2012-09-15 01:29:31 +0200
commit4a6f4c0f7d62858a4a9afba18f11289cb0bb8358 (patch)
treea6259c55c4e0d924bde842cb5669df63e4327813 /include/libopencm3/efm32
parent50b3c92d7ff7230b1527ba391ace74a876e404f1 (diff)
remove the support libraries for efm32
i don't plan to extend or support them, and they'll just grow stale
Diffstat (limited to 'include/libopencm3/efm32')
-rw-r--r--include/libopencm3/efm32/tinygecko/README.dox14
-rw-r--r--include/libopencm3/efm32/tinygecko/cmu.convenienceheaders63
-rw-r--r--include/libopencm3/efm32/tinygecko/cmu.h678
-rw-r--r--include/libopencm3/efm32/tinygecko/cmu.yaml458
-rw-r--r--include/libopencm3/efm32/tinygecko/devicerevision.h49
-rw-r--r--include/libopencm3/efm32/tinygecko/emu.convenienceheaders18
-rw-r--r--include/libopencm3/efm32/tinygecko/emu.h127
-rw-r--r--include/libopencm3/efm32/tinygecko/emu.yaml50
-rw-r--r--include/libopencm3/efm32/tinygecko/generate-license.yaml19
-rw-r--r--include/libopencm3/efm32/tinygecko/generate.py176
-rw-r--r--include/libopencm3/efm32/tinygecko/generate.yaml3
-rw-r--r--include/libopencm3/efm32/tinygecko/gpio.h498
-rw-r--r--include/libopencm3/efm32/tinygecko/irq.h55
-rw-r--r--include/libopencm3/efm32/tinygecko/lcd.convenienceheaders0
-rw-r--r--include/libopencm3/efm32/tinygecko/lcd.h295
-rw-r--r--include/libopencm3/efm32/tinygecko/lcd.yaml241
16 files changed, 0 insertions, 2744 deletions
diff --git a/include/libopencm3/efm32/tinygecko/README.dox b/include/libopencm3/efm32/tinygecko/README.dox
deleted file mode 100644
index 04da755..0000000
--- a/include/libopencm3/efm32/tinygecko/README.dox
+++ /dev/null
@@ -1,14 +0,0 @@
-/**
-
-@brief EFM32 Tiny Gecko headers
-
-This directory contains all headers specific to the Tiny Gecko family of the
-Energy Micro EFM32 series.
-
-The individual peripherials described here all include hints at where the
-information was taken from, but usually it stems from
-d0034_efm32tg_reference_manual.pdf.
-
-@defgroup EFM32TG EFM32 Tiny Gecko
-
-*/
diff --git a/include/libopencm3/efm32/tinygecko/cmu.convenienceheaders b/include/libopencm3/efm32/tinygecko/cmu.convenienceheaders
deleted file mode 100644
index 212405d..0000000
--- a/include/libopencm3/efm32/tinygecko/cmu.convenienceheaders
+++ /dev/null
@@ -1,63 +0,0 @@
-/** CMU convenience functions
- *
- * These functions assist in clock switching, and are intended to be safer to
- * use than direct fiddling with registers. They try to be suitable for typical
- * applications, and will invest some bytes of code in order to minimize power
- * consumption.
- *
- * @todo Work on this module is stalled until I can figure out if there is a
- * way to have a cmu_shutdown_unused function at all.
- *
- * @defgroup EFM32TG_CMU_convenience CMU convenience functions
- * @{
- */
-
-/** Disable all oscillators not currently in use.
- *
- * The implementation follows d0034_efm32tg_reference_manual.pdf figure 11.1.
- * The clock out pin configurations are not depicted there, but described in
- * section 11.3.4.
- *
- * @todo This function is ignorant of ongoing calibrations.
- *
- * @todo This doesn't work at all: Fields like HFCLKSEL are write-only.
- * */
-static void cmu_shutdown_unused(void)
-{
- /* Is HFXO needed? */
- if (!(
- (CMU_CMD & CMU_CMD_HFCLKSEL_MASK) == CMU_CMD_HFCLKSEL_HFXO ||
- (
- (CMU_CTRL & CMU_CTRL_CLKOUTSEL1_MASK) == CMU_CTRL_CLKOUTSEL1_HFXOQ &&
- (CMU_ROUTE & CMU_ROUTE_CLKOUT1PEN)
- ) || (
- (CMU_CTRL & CMU_CTRL_CLKOUTSEL0_MASK) == CMU_CTRL_CLKOUTSEL0_HFXO &&
- (CMU_ROUTE & CMU_ROUTE_CLKOUT0PEN)
- )))
- CMU_OSCENCMD = CMU_OSCENCMD_HFXODIS;
-
- /* Is HFRCO neede? */
- if (!(
- (CMU_CMD & CMU_CMD_HFCLKSEL_MASK) == CMU_CMD_HFCLKSEL_HFRCO ||
- (
- (CMU_CTRL & CMU_CTRL_CLKOUTSEL1_MASK) == CMU_CTRL_CLKOUTSEL1_HFRCOQ &&
- (CMU_ROUTE & CMU_ROUTE_CLKOUT1PEN)
- ) || (
- (CMU_CTRL & CMU_CTRL_CLKOUTSEL0_MASK) == CMU_CTRL_CLKOUTSEL0_HFRCO &&
- (CMU_ROUTE & CMU_ROUTE_CLKOUT0PEN)
- )))
- {}
-// CMU_OSCENCMD = CMU_OSCENCMD_HFRCODIS;
-}
-
-/** Switch HFCLK to LFRC. This call is not only blocking, but even freezes
- * everything depending on HFCLK until LFRC is stable. The procedure is
- * sketched in d0034_efm32tg_reference_manual.pdf figure 11.2. */
-static void cmu_hfclk_switch_blocking(void)
-{
- CMU_OSCENCMD = CMU_OSCENCMD_LFRCOEN;
- CMU_CMD = CMU_CMD_HFCLKSEL_LFRCO;
- CMU_OSCENCMD = CMU_OSCENCMD_HFRCODIS;
-}
-
-/** @} */
diff --git a/include/libopencm3/efm32/tinygecko/cmu.h b/include/libopencm3/efm32/tinygecko/cmu.h
deleted file mode 100644
index 80c959f..0000000
--- a/include/libopencm3/efm32/tinygecko/cmu.h
+++ /dev/null
@@ -1,678 +0,0 @@
-/*
- * This file is part of the libopencm3 project.
- *
- * Copyright (C) 2012 chrysn <chrysn@fsfe.org>
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library. If not, see <http://www.gnu.org/licenses/>.
- */
-
-/** @file
- * @see EFM32TG_CMU
- */
-
-/** Definitions for the CMU subsystem (Clock Management Unit).
- *
- * This corresponds to the description in d0034_efm32tg_reference_manual.pdf
- * section 11.
- *
- * @ingroup EFM32TG
- * @defgroup EFM32TG_CMU CMU (Clock Management Unit)
- * @{
- */
-
-#ifndef LIBOPENCM3_EFM32_TINYGECKO_CMU_H
-#define LIBOPENCM3_EFM32_TINYGECKO_CMU_H
-
-#include <libopencm3/cm3/common.h>
-#include <libopencm3/efm32/memorymap.h>
-
-/** Register definitions and register value definitions for the CMU subsystem
- *
- * @defgroup EFM32TG_CMU_regsandvals CMU registers and values
- * @{
- */
-
-/** These definitions reflect d0034_efm32tg_reference_manual.pdf section 11.4
- *
- * @defgroup EFM32TG_CMU_registers CMU registers
- * @{
- */
-
-#define CMU_CTRL MMIO32(CMU_BASE + 0x000) /**< @see EFM32TG_CMU_CTRL_bits */
-#define CMU_HFCORECLKDIV MMIO32(CMU_BASE + 0x004) /**< @see EFM32TG_CMU_HFCORECLKDIV_values */
-#define CMU_HFPERCLKDIV MMIO32(CMU_BASE + 0x008) /**< @see EFM32TG_CMU_HFPERCLKDIV_bits */
-#define CMU_HFRCOCTRL MMIO32(CMU_BASE + 0x00c) /**< @see EFM32TG_CMU_HFRCOCTRL_bits */
-#define CMU_LFRCOCTRL MMIO32(CMU_BASE + 0x010)
-#define CMU_AUXHFRCOCTRL MMIO32(CMU_BASE + 0x014) /**< @see EFM32TG_CMU_AUXHFRCOCTRL_bits */
-#define CMU_CALCTRL MMIO32(CMU_BASE + 0x018) /**< @see EFM32TG_CMU_CALCTRL_bits */
-#define CMU_CALCNT MMIO32(CMU_BASE + 0x01c)
-#define CMU_OSCENCMD MMIO32(CMU_BASE + 0x020) /**< @see EFM32TG_CMU_OSCENCMD_bits */
-#define CMU_CMD MMIO32(CMU_BASE + 0x024) /**< @see EFM32TG_CMU_CMD_bits */
-#define CMU_LFCLKSEL MMIO32(CMU_BASE + 0x028) /**< @see EFM32TG_CMU_LFCLKSEL_bits */
-#define CMU_STATUS MMIO32(CMU_BASE + 0x02c) /**< @see EFM32TG_CMU_STATUS_bits */
-#define CMU_IF MMIO32(CMU_BASE + 0x030) /**< @see EFM32TG_CMU_I_bits */
-#define CMU_IFS MMIO32(CMU_BASE + 0x034) /**< @see EFM32TG_CMU_I_bits */
-#define CMU_IFC MMIO32(CMU_BASE + 0x038) /**< @see EFM32TG_CMU_I_bits */
-#define CMU_IEN MMIO32(CMU_BASE + 0x03c) /**< @see EFM32TG_CMU_I_bits */
-#define CMU_HFCORECLKEN0 MMIO32(CMU_BASE + 0x040) /**< @see EFM32TG_CMU_HFCORECLKEN0_bits */
-#define CMU_HFPERCLKEN0 MMIO32(CMU_BASE + 0x044) /**< @see EFM32TG_CMU_HFPERCLKEN0_bits */
-#define CMU_SYNCBUSY MMIO32(CMU_BASE + 0x050) /**< @see EFM32TG_CMU_SYNCBUSY_bits */
-#define CMU_FREEZE MMIO32(CMU_BASE + 0x054) /**< @see EFM32TG_CMU_FREEZE_bits */
-#define CMU_LFACLKEN0 MMIO32(CMU_BASE + 0x058) /**< @see EFM32TG_CMU_LFACLKEN0_bits */
-#define CMU_LFBCLKEN0 MMIO32(CMU_BASE + 0x060) /**< @see EFM32TG_CMU_LFBCLKEN0_bits */
-#define CMU_LFAPRESC0 MMIO32(CMU_BASE + 0x068) /**< @see EFM32TG_CMU_LFAPRESC0_bits */
-#define CMU_LFBPRESC0 MMIO32(CMU_BASE + 0x070) /**< @see EFM32TG_CMU_LFBPRESC0_bits */
-#define CMU_PCNTCTRL MMIO32(CMU_BASE + 0x078) /**< @see EFM32TG_CMU_PCNTCTRL_bits */
-#define CMU_LCDCTRL MMIO32(CMU_BASE + 0x07c) /**< @see EFM32TG_CMU_LCDCTRL_bits */
-#define CMU_ROUTE MMIO32(CMU_BASE + 0x080) /**< @see EFM32TG_CMU_ROUTE_bits */
-#define CMU_LOCK MMIO32(CMU_BASE + 0x084) /**< @see EFM32TG_CMU_LOCK_values */
-
-/** @} */
-
-/** Bit states for the CMU_CTRL register
- *
- * See d0034_efm32tg_reference_manual.pdf section 11.5.1 for definitions.
- *
- * @defgroup EFM32TG_CMU_CTRL_bits CMU CTRL bits
- * @{
- */
-
-#define CMU_CTRL_DBGCLK_AUXHFRCO (0<<28)
-#define CMU_CTRL_DBGCLK_HFCLK (1<<28)
-#define CMU_CTRL_DBGCLK_MASK (0x1<<28)
-#define CMU_CTRL_CLKOUTSEL1_LFRCO (0<<23)
-#define CMU_CTRL_CLKOUTSEL1_LFXO (1<<23)
-#define CMU_CTRL_CLKOUTSEL1_HFCLK (2<<23)
-#define CMU_CTRL_CLKOUTSEL1_LFXOQ (3<<23)
-#define CMU_CTRL_CLKOUTSEL1_HFXOQ (4<<23)
-#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (5<<23)
-#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (6<<23)
-#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (7<<23)
-#define CMU_CTRL_CLKOUTSEL1_MASK (0x7<<23)
-#define CMU_CTRL_CLKOUTSEL0_HFRCO (0<<20)
-#define CMU_CTRL_CLKOUTSEL0_HFXO (1<<20)
-#define CMU_CTRL_CLKOUTSEL0_HFCLK2 (2<<20)
-#define CMU_CTRL_CLKOUTSEL0_HFCLK4 (3<<20)
-#define CMU_CTRL_CLKOUTSEL0_HFCLK8 (4<<20)
-#define CMU_CTRL_CLKOUTSEL0_HFCLK16 (5<<20)
-#define CMU_CTRL_CLKOUTSEL0_ULFRCO (6<<20)
-#define CMU_CTRL_CLKOUTSEL0_AUXHFRCO (7<<20)
-#define CMU_CTRL_CLKOUTSEL0_MASK (0x7<<20)
-#define CMU_CTRL_LFXOTIMEOUT_8CYCLES (0<<18)
-#define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (1<<18)
-#define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (2<<18)
-#define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (3<<18)
-#define CMU_CTRL_LFXOTIMEOUT_MASK (0x3<<18)
-#define CMU_CTRL_LFXOBUFCUR (1<<17)
-#define CMU_CTRL_LXFOBOOST_70PCENT (0<<13)
-#define CMU_CTRL_LXFOBOOST_100PCENT (1<<13)
-#define CMU_CTRL_LXFOBOOST_MASK (0x1<<13)
-#define CMU_CTRL_LFXOMODE_XTAL (0<<11)
-#define CMU_CTRL_LFXOMODE_BUFEXTCLK (1<<11)
-#define CMU_CTRL_LFXOMODE_DIGEXTCLK (2<<11)
-#define CMU_CTRL_LFXOMODE_MASK (0x3<<11)
-#define CMU_CTRL_HFXOTIMEOUT_8CYCLES (0<<9)
-#define CMU_CTRL_HFXOTIMEOUT_256CYCLES (1<<9)
-#define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (2<<9)
-#define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (3<<9)
-#define CMU_CTRL_HFXOTIMEOUT_MASK (0x3<<9)
-#define CMU_CTRL_HFXOGLITCHDETEN (1<<7)
-#define CMU_CTRL_HFXOBUFCUR_MASK (0x3<<5)
-#define CMU_CTRL_HFXOBOOST_50PCENT (0<<2)
-#define CMU_CTRL_HFXOBOOST_70PCENT (1<<2)
-#define CMU_CTRL_HFXOBOOST_80PCENT (2<<2)
-#define CMU_CTRL_HFXOBOOST_100PCENT (3<<2)
-#define CMU_CTRL_HFXOBOOST_MASK (0x3<<2)
-#define CMU_CTRL_HFXOMODE_XTAL (0<<0)
-#define CMU_CTRL_HFXOMODE_BUFEXTCLK (1<<0)
-#define CMU_CTRL_HFXOMODE_DIGEXTCLK (2<<0)
-#define CMU_CTRL_HFXOMODE_MASK (0x3<<0)
-
-/** @} */
-
-/** Values for the CMU_HFCORECLKDIV register
- *
- * See d0034_efm32tg_reference_manual.pdf section 11.5.2 for definitions.
- *
- * @defgroup EFM32TG_CMU_HFCORECLKDIV_values CMU HFCORECLKDIV values
- * @{
- */
-
-#define CMU_HFCORECLKDIV_HFCLK 0
-#define CMU_HFCORECLKDIV_HFCLK2 1
-#define CMU_HFCORECLKDIV_HFCLK4 2
-#define CMU_HFCORECLKDIV_HFCLK8 3
-#define CMU_HFCORECLKDIV_HFCLK16 4
-#define CMU_HFCORECLKDIV_HFCLK32 5
-#define CMU_HFCORECLKDIV_HFCLK64 6
-#define CMU_HFCORECLKDIV_HFCLK128 7
-#define CMU_HFCORECLKDIV_HFCLK256 8
-#define CMU_HFCORECLKDIV_HFCLK512 9
-
-/** @} */
-
-/** Bit states for the CMU_HFPERCLKDIV register
- *
- * See d0034_efm32tg_reference_manual.pdf section 11.5.3 for definitions.
- *
- * @defgroup EFM32TG_CMU_HFPERCLKDIV_bits CMU HFPERCLKDIV bits
- * @{
- */
-
-#define CMU_HFPERCLKDIV_HFPERCLKEN (1<<8)
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (0<<0)
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (1<<0)
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (2<<0)
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (3<<0)
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (4<<0)
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (5<<0)
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (6<<0)
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (7<<0)
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (8<<0)
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (9<<0)
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_MASK (0x7<<0)
-
-/** @} */
-
-/** Bit states for the CMU_HFRCOCTRL register
- *
- * See d0034_efm32tg_reference_manual.pdf section 11.5.4 for definitions.
- *
- * @defgroup EFM32TG_CMU_HFRCOCTRL_bits CMU HFRCOCTRL bits
- * @{
- */
-
-#define CMU_HFRCOCTRL_SUDELAY_MASK (0x1f<<12)
-#define CMU_HFRCOCTRL_BAND_1MHZ (0<<8)
-#define CMU_HFRCOCTRL_BAND_7MHZ (1<<8)
-#define CMU_HFRCOCTRL_BAND_11MHZ (2<<8)
-#define CMU_HFRCOCTRL_BAND_14MHZ (3<<8)
-#define CMU_HFRCOCTRL_BAND_21MHZ (4<<8)
-#define CMU_HFRCOCTRL_BAND_28MHZ (5<<8)
-#define CMU_HFRCOCTRL_BAND_MASK (0x7<<8)
-#define CMU_HFRCOCTRL_TUNING_MASK (0xff<<0)
-
-/** @} */
-
-/** Bit states for the CMU_AUXHFRCOCTRL register
- *
- * See d0034_efm32tg_reference_manual.pdf section 11.5.6 for definitions.
- *
- * @defgroup EFM32TG_CMU_AUXHFRCOCTRL_bits CMU AUXHFRCOCTRL bits
- * @{
- */
-
-#define CMU_AUXHFRCOCTRL_BAND_14MHZ (0<<8)
-#define CMU_AUXHFRCOCTRL_BAND_11MHZ (1<<8)
-#define CMU_AUXHFRCOCTRL_BAND_7MHZ (2<<8)
-#define CMU_AUXHFRCOCTRL_BAND_1MHZ (3<<8)
-#define CMU_AUXHFRCOCTRL_BAND_28MHZ (6<<8)
-#define CMU_AUXHFRCOCTRL_BAND_21MHZ (7<<8)
-#define CMU_AUXHFRCOCTRL_BAND_MASK (0x7<<8)
-#define CMU_AUXHFRCOCTRL_TUNING_MASK (0xff<<0)
-
-/** @} */
-
-/** Bit states for the CMU_CALCTRL register
- *
- * See d0034_efm32tg_reference_manual.pdf section 11.6.7 for definitions.
- *
- * @defgroup EFM32TG_CMU_CALCTRL_bits CMU CALCTRL bits
- * @{
- */
-
-#define CMU_CALCTRL_CONT (1<<6)
-#define CMU_CALCTRL_DOWNSEL_HFCLK (0<<3)
-#define CMU_CALCTRL_DOWNSEL_HFXO (1<<3)
-#define CMU_CALCTRL_DOWNSEL_LFXO (2<<3)
-#define CMU_CALCTRL_DOWNSEL_HFRCO (3<<3)
-#define CMU_CALCTRL_DOWNSEL_LFRCO (4<<3)
-#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (5<<3)
-#define CMU_CALCTRL_DOWNSEL_MASK (0x7<<3)
-#define CMU_CALCTRL_UPSEL_HFXO (0<<0)
-#define CMU_CALCTRL_UPSEL_LFXO (1<<0)
-#define CMU_CALCTRL_UPSEL_HFRCO (2<<0)
-#define CMU_CALCTRL_UPSEL_LFRCO (3<<0)
-#define CMU_CALCTRL_UPSEL_AUXHFRCO (4<<0)
-#define CMU_CALCTRL_UPSEL_MASK (0x7<<0)
-
-/** @} */
-
-/** Bit states for the CMU_OSCENCMD register
- *
- * See d0034_efm32tg_reference_manual.pdf section 11.5.9 for definitions.
- *
- * @defgroup EFM32TG_CMU_OSCENCMD_bits CMU OSCENCMD bits
- * @{
- */
-
-#define CMU_OSCENCMD_LFXODIS (1<<9)
-#define CMU_OSCENCMD_LFXOEN (1<<8)
-#define CMU_OSCENCMD_LFRCODIS (1<<7)
-#define CMU_OSCENCMD_LFRCOEN (1<<6)
-#define CMU_OSCENCMD_AUXHFRCODIS (1<<5)
-#define CMU_OSCENCMD_AUXHFRCOEN (1<<4)
-#define CMU_OSCENCMD_HFXODIS (1<<3)
-#define CMU_OSCENCMD_HFXOEN (1<<2)
-#define CMU_OSCENCMD_HFRCODIS (1<<1)
-#define CMU_OSCENCMD_HFRCOEN (1<<0)
-
-/** @} */
-
-/** Bit states for the CMU_CMD register
- *
- * See d0034_efm32tg_reference_manual.pdf section 11.5.10 for definitions.
- *
- * @defgroup EFM32TG_CMU_CMD_bits CMU CMD bits
- * @{
- */
-
-#define CMU_CMD_CALSTOP (1<<4)
-#define CMU_CMD_CALSTART (1<<3)
-#define CMU_CMD_HFCLKSEL_HFRCO (1<<0)
-#define CMU_CMD_HFCLKSEL_HFXO (2<<0)
-#define CMU_CMD_HFCLKSEL_LFRCO (3<<0)
-#define CMU_CMD_HFCLKSEL_LFXO (4<<0)
-#define CMU_CMD_HFCLKSEL_MASK (0x7<<0)
-
-/** @} */
-
-/** Bit states for the CMU_LFCLKSEL register
- *
- * See d0034_efm32tg_reference_manual.pdf section 11.5.11 for definitions.
- *
- * @defgroup EFM32TG_CMU_LFCLKSEL_bits CMU LFCLKSEL bits
- * @{
- */
-
-#define CMU_LFCLKSEL_LFBE_DISABLED (0<<20)
-#define CMU_LFCLKSEL_LFBE_ULFRCO (1<<20)
-#define CMU_LFCLKSEL_LFBE_MASK (0x1<<20)
-#define CMU_LFCLKSEL_LFAE_DISABLED (0<<16)
-#define CMU_LFCLKSEL_LFAE_ULFRCO (1<<16)
-#define CMU_LFCLKSEL_LFAE_MASK (0x1<<16)
-#define CMU_LFCLKSEL_LFB_DISABLED (0<<2)
-#define CMU_LFCLKSEL_LFB_LFRCO (1<<2)
-#define CMU_LFCLKSEL_LFB_LFXO (2<<2)
-#define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (3<<2)
-#define CMU_LFCLKSEL_LFB_MASK (0x3<<2)
-#define CMU_LFCLKSEL_LFA_DISABLED (0<<0)
-#define CMU_LFCLKSEL_LFA_LFRCO (1<<0)
-#define CMU_LFCLKSEL_LFA_LFXO (2<<0)
-#define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (3<<0)
-#define CMU_LFCLKSEL_LFA_MASK (0x3<<0)
-
-/** @} */
-
-/** Bit states for the CMU_STATUS register
- *
- * See d0034_efm32tg_reference_manual.pdf section 11.5.12 for definitions.
- *
- * @defgroup EFM32TG_CMU_STATUS_bits CMU STATUS bits
- * @{
- */
-
-#define CMU_STATUS_CALBSY (1<<14)
-#define CMU_STATUS_LFXOSEL (1<<13)
-#define CMU_STATUS_LFRCOSEL (1<<12)
-#define CMU_STATUS_HFXOSEL (1<<11)
-#define CMU_STATUS_HFRCOSEL (1<<10)
-#define CMU_STATUS_LFXORDY (1<<9)
-#define CMU_STATUS_LFXOENS (1<<8)
-#define CMU_STATUS_LFRCORDY (1<<7)
-#define CMU_STATUS_LFRCOENS (1<<6)
-#define CMU_STATUS_AUXHFRCORDY (1<<5)
-#define CMU_STATUS_AUXHFRCOENS (1<<4)
-#define CMU_STATUS_HFXORDY (1<<3)
-#define CMU_STATUS_HFXOENS (1<<2)
-#define CMU_STATUS_HFRCORDY (1<<1)
-#define CMU_STATUS_HFRCOENS (1<<0)
-
-/** @} */
-
-/** Bit states for the CMU_HFCORECLKEN0 register
- *
- * See d0034_efm32tg_reference_manual.pdf section 11.5.17 for definitions.
- *
- * @defgroup EFM32TG_CMU_HFCORECLKEN0_bits CMU HFCORECLKEN0 bits
- * @{
- */
-
-#define CMU_HFCORECLKEN0_LE (1<<2)
-#define CMU_HFCORECLKEN0_DMA (1<<1)
-#define CMU_HFCORECLKEN0_AES (1<<0)
-
-/** @} */
-
-/** Bit states for the CMU_HFPERCLKEN0 register
- *
- * See d0034_efm32tg_reference_manual.pdf section 11.5.18 for definitions.
- *
- * @defgroup EFM32TG_CMU_HFPERCLKEN0_bits CMU HFPERCLKEN0 bits
- * @{
- */
-
-#define CMU_HFPERCLKEN0_I2C0 (1<<11)
-#define CMU_HFPERCLKEN0_DAC0 (1<<10)
-#define CMU_HFPERCLKEN0_ADC0 (1<<9)
-#define CMU_HFPERCLKEN0_PRS (1<<8)
-#define CMU_HFPERCLKEN0_VCMP (1<<7)
-#define CMU_HFPERCLKEN0_GPIO (1<<6)
-#define CMU_HFPERCLKEN0_TIMER1 (1<<5)
-#define CMU_HFPERCLKEN0_TIMER0 (1<<4)
-#define CMU_HFPERCLKEN0_USART1 (1<<3)
-#define CMU_HFPERCLKEN0_USART0 (1<<2)
-#define CMU_HFPERCLKEN0_ACMP1 (1<<1)
-#define CMU_HFPERCLKEN0_ACMP0 (1<<0)
-
-/** @} */
-
-/** Bit states for the CMU_SYNCBUSY register
- *
- * See d0034_efm32tg_reference_manual.pdf section 11.5.19 for definitions.
- *
- * @defgroup EFM32TG_CMU_SYNCBUSY_bits CMU SYNCBUSY bits
- * @{
- */
-
-#define CMU_SYNCBUSY_LFBPRESC0 (1<<6)
-#define CMU_SYNCBUSY_LFBCLKEN0 (1<<4)
-#define CMU_SYNCBUSY_LFAPRESC0 (1<<2)
-#define CMU_SYNCBUSY_LFACLKEN0 (1<<0)
-
-/** @} */
-
-/** Bit states for the CMU_FREEZE register
- *
- * See d0034_efm32tg_reference_manual.pdf section 11.5.20 for definitions.
- *
- * @defgroup EFM32TG_CMU_FREEZE_bits CMU FREEZE bits
- * @{
- */
-
-#define CMU_FREEZE_REGFREEZE_UPDATE (0<<0)
-#define CMU_FREEZE_REGFREEZE_FREEZE (1<<0)
-#define CMU_FREEZE_REGFREEZE_MASK (0x1<<0)
-
-/** @} */
-
-/** Bit states for the CMU_LFACLKEN0 register
- *
- * See d0034_efm32tg_reference_manual.pdf section 11.5.21 for definitions.
- *
- * @defgroup EFM32TG_CMU_LFACLKEN0_bits CMU LFACLKEN0 bits
- * @{
- */
-
-#define CMU_LFACLKEN0_LCD (1<<3)
-#define CMU_LFACLKEN0_LETIMER0 (1<<2)
-#define CMU_LFACLKEN0_RTC (1<<1)
-#define CMU_LFACLKEN0_LESENSE (1<<0)
-
-/** @} */
-
-/** Bit states for the CMU_LFBCLKEN0 register
- *
- * See d0034_efm32tg_reference_manual.pdf section 11.5.22 for definitions.
- *
- * @defgroup EFM32TG_CMU_LFBCLKEN0_bits CMU LFBCLKEN0 bits
- * @{
- */
-
-#define CMU_LFBCLKEN0_LEUART0 (1<<0)
-
-/** @} */
-
-/** Bit states for the CMU_LFAPRESC0 register
- *
- * See d0034_efm32tg_reference_manual.pdf section 11.5.23 for definitions.
- *
- * @defgroup EFM32TG_CMU_LFAPRESC0_bits CMU LFAPRESC0 bits
- * @{
- */
-
-#define CMU_LFAPRESC0_LCD_DIV16 (0<<12)
-#define CMU_LFAPRESC0_LCD_DIV32 (1<<12)
-#define CMU_LFAPRESC0_LCD_DIV64 (2<<12)
-#define CMU_LFAPRESC0_LCD_DIV128 (3<<12)
-#define CMU_LFAPRESC0_LCD_MASK (0x3<<12)
-#define CMU_LFAPRESC0_LETIMER0_DIV1 (0<<8)
-#define CMU_LFAPRESC0_LETIMER0_DIV2 (1<<8)
-#define CMU_LFAPRESC0_LETIMER0_DIV4 (2<<8)
-#define CMU_LFAPRESC0_LETIMER0_DIV8 (3<<8)
-#define CMU_LFAPRESC0_LETIMER0_DIV16 (4<<8)
-#define CMU_LFAPRESC0_LETIMER0_DIV32 (5<<8)
-#define CMU_LFAPRESC0_LETIMER0_DIV64 (6<<8)
-#define CMU_LFAPRESC0_LETIMER0_DIV128 (7<<8)
-#define CMU_LFAPRESC0_LETIMER0_DIV256 (8<<8)
-#define CMU_LFAPRESC0_LETIMER0_DIV512 (9<<8)
-#define CMU_LFAPRESC0_LETIMER0_DIV1024 (10<<8)
-#define CMU_LFAPRESC0_LETIMER0_DIV2048 (11<<8)
-#define CMU_LFAPRESC0_LETIMER0_DIV4096 (12<<8)
-#define CMU_LFAPRESC0_LETIMER0_DIV8192 (13<<8)
-#define CMU_LFAPRESC0_LETIMER0_DIV16384 (14<<8)
-#define CMU_LFAPRESC0_LETIMER0_DIV32768 (15<<8)
-#define CMU_LFAPRESC0_LETIMER0_MASK (0xf<<8)
-#define CMU_LFAPRESC0_RTC_DIV1 (0<<4)
-#define CMU_LFAPRESC0_RTC_DIV2 (1<<4)
-#define CMU_LFAPRESC0_RTC_DIV4 (2<<4)
-#define CMU_LFAPRESC0_RTC_DIV8 (3<<4)
-#define CMU_LFAPRESC0_RTC_DIV16 (4<<4)
-#define CMU_LFAPRESC0_RTC_DIV32 (5<<4)
-#define CMU_LFAPRESC0_RTC_DIV64 (6<<4)
-#define CMU_LFAPRESC0_RTC_DIV128 (7<<4)
-#define CMU_LFAPRESC0_RTC_DIV256 (8<<4)
-#define CMU_LFAPRESC0_RTC_DIV512 (9<<4)
-#define CMU_LFAPRESC0_RTC_DIV1024 (10<<4)
-#define CMU_LFAPRESC0_RTC_DIV2048 (11<<4)
-#define CMU_LFAPRESC0_RTC_DIV4096 (12<<4)
-#define CMU_LFAPRESC0_RTC_DIV8192 (13<<4)
-#define CMU_LFAPRESC0_RTC_DIV16384 (14<<4)
-#define CMU_LFAPRESC0_RTC_DIV32768 (15<<4)
-#define CMU_LFAPRESC0_RTC_MASK (0xf<<4)
-#define CMU_LFAPRESC0_LESENSE_DIV1 (0<<0)
-#define CMU_LFAPRESC0_LESENSE_DIV2 (1<<0)
-#define CMU_LFAPRESC0_LESENSE_DIV4 (2<<0)
-#define CMU_LFAPRESC0_LESENSE_DIV8 (3<<0)
-#define CMU_LFAPRESC0_LESENSE_MASK (0x3<<0)
-
-/** @} */
-
-/** Bit states for the CMU_LFBPRESC0 register
- *
- * See d0034_efm32tg_reference_manual.pdf section 11.5.24 for definitions.
- *
- * @defgroup EFM32TG_CMU_LFBPRESC0_bits CMU LFBPRESC0 bits
- * @{
- */
-
-#define CMU_LFBPRESC0_LEUART0_DIV1 (0<<0)
-#define CMU_LFBPRESC0_LEUART0_DIV2 (1<<0)
-#define CMU_LFBPRESC0_LEUART0_DIV4 (2<<0)
-#define CMU_LFBPRESC0_LEUART0_DIV8 (3<<0)
-#define CMU_LFBPRESC0_LEUART0_MASK (0x3<<0)
-
-/** @} */
-
-/** Bit states for the CMU_PCNTCTRL register
- *
- * See d0034_efm32tg_reference_manual.pdf section 11.5.25 for definitions.
- *
- * @defgroup EFM32TG_CMU_PCNTCTRL_bits CMU PCNTCTRL bits
- * @{
- */
-
-#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (0<<1)
-#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (1<<1)
-#define CMU_PCNTCTRL_PCNT0CLKSEL_MASK (0x1<<1)
-#define CMU_PCNTCTRL_PCNT0CLKEN (1<<0)
-
-/** @} */
-
-/** Bit states for the CMU_LCDCTRL register
- *
- * See d0034_efm32tg_reference_manual.pdf section 11.5.26 for definitions.
- *
- * @defgroup EFM32TG_CMU_LCDCTRL_bits CMU LCDCTRL bits
- * @{
- */
-
-#define CMU_LCDCTRL_VBFDIV_DIV1 (0<<4)
-#define CMU_LCDCTRL_VBFDIV_DIV2 (1<<4)
-#define CMU_LCDCTRL_VBFDIV_DIV4 (2<<4)
-#define CMU_LCDCTRL_VBFDIV_DIV8 (3<<4)
-#define CMU_LCDCTRL_VBFDIV_DIV16 (4<<4)
-#define CMU_LCDCTRL_VBFDIV_DIV32 (5<<4)
-#define CMU_LCDCTRL_VBFDIV_DIV64 (6<<4)
-#define CMU_LCDCTRL_VBFDIV_DIV128 (7<<4)
-#define CMU_LCDCTRL_VBFDIV_MASK (0x7<<4)
-#define CMU_LCDCTRL_VBOOSTEN (1<<3)
-#define CMU_LCDCTRL_FDIV_MASK (0x7<<0)
-
-/** @} */
-
-/** Bit states for the CMU_ROUTE register
- *
- * See d0034_efm32tg_reference_manual.pdf section 11.5.27 for definitions.
- *
- * @defgroup EFM32TG_CMU_ROUTE_bits CMU ROUTE bits
- * @{
- */
-
-#define CMU_ROUTE_LOCATION_LOC0 (0<<4)
-#define CMU_ROUTE_LOCATION_LOC1 (1<<4)
-#define CMU_ROUTE_LOCATION_MASK (0x7<<4)
-#define CMU_ROUTE_CLKOUT1PEN (1<<1)
-#define CMU_ROUTE_CLKOUT0PEN (1<<0)
-
-/** @} */
-
-/** Values for the CMU_LOCK register
- *
- * See d0034_efm32tg_reference_manual.pdf section 11.5.28 for definitions.
- *
- * @defgroup EFM32TG_CMU_LOCK_values CMU LOCK values
- * @{
- */
-
-#define CMU_LOCK_IS_UNLOCKED 0
-#define CMU_LOCK_IS_LOCKED 1
-#define CMU_LOCK_SET_LOCKED 0
-#define CMU_LOCK_SET_UNLOCKED 0x580E
-
-/** @} */
-
-/** Bit states for the CMU "I" group of registers (IF, IFS, IFC, IEN)
- *
- * These registers use this:
- *
- * <ul>
- *
- * <li>The CMU_IF register; see d0034_efm32tg_reference_manual.pdf section
- * 11.5.13 for definitions.</li>
- *
- * <li>The CMU_IFS register; see d0034_efm32tg_reference_manual.pdf section
- * 11.5.14 for definitions.</li>
- *
- * <li>The CMU_IFC register; see d0034_efm32tg_reference_manual.pdf section
- * 11.5.15 for definitions.</li>
- *
- * <li>The CMU_IEN register; see d0034_efm32tg_reference_manual.pdf section
- * 11.5.16 for definitions.</li>
- *
- * </ul>
- *
- * @defgroup EFM32TG_CMU_I_bits CMU I bits group
- * @{
- */
-
-#define CMU_I_CALOF (1<<6)
-#define CMU_I_CALRDY (1<<5)
-#define CMU_I_AUXHFRCORDY (1<<4)
-#define CMU_I_LFXORDY (1<<3)
-#define CMU_I_LFRCORDY (1<<2)
-#define CMU_I_HFXORDY (1<<1)
-#define CMU_I_HFRCORDY (1<<0)
-
-/** @} */
-
-/** @} */
-
-/** CMU convenience functions
- *
- * These functions assist in clock switching, and are intended to be safer to
- * use than direct fiddling with registers. They try to be suitable for typical
- * applications, and will invest some bytes of code in order to minimize power
- * consumption.
- *
- * @todo Work on this module is stalled until I can figure out if there is a
- * way to have a cmu_shutdown_unused function at all.
- *
- * @defgroup EFM32TG_CMU_convenience CMU convenience functions
- * @{
- */
-
-/** Disable all oscillators not currently in use.
- *
- * The implementation follows d0034_efm32tg_reference_manual.pdf figure 11.1.
- * The clock out pin configurations are not depicted there, but described in
- * section 11.3.4.
- *
- * @todo This function is ignorant of ongoing calibrations.
- *
- * @todo This doesn't work at all: Fields like HFCLKSEL are write-only.
- * */
-static void cmu_shutdown_unused(void)
-{
- /* Is HFXO needed? */
- if (!(
- (CMU_CMD & CMU_CMD_HFCLKSEL_MASK) == CMU_CMD_HFCLKSEL_HFXO ||
- (
- (CMU_CTRL & CMU_CTRL_CLKOUTSEL1_MASK) == CMU_CTRL_CLKOUTSEL1_HFXOQ &&
- (CMU_ROUTE & CMU_ROUTE_CLKOUT1PEN)
- ) || (
- (CMU_CTRL & CMU_CTRL_CLKOUTSEL0_MASK) == CMU_CTRL_CLKOUTSEL0_HFXO &&
- (CMU_ROUTE & CMU_ROUTE_CLKOUT0PEN)
- )))
- CMU_OSCENCMD = CMU_OSCENCMD_HFXODIS;
-
- /* Is HFRCO neede? */
- if (!(
- (CMU_CMD & CMU_CMD_HFCLKSEL_MASK) == CMU_CMD_HFCLKSEL_HFRCO ||
- (
- (CMU_CTRL & CMU_CTRL_CLKOUTSEL1_MASK) == CMU_CTRL_CLKOUTSEL1_HFRCOQ &&
- (CMU_ROUTE & CMU_ROUTE_CLKOUT1PEN)
- ) || (
- (CMU_CTRL & CMU_CTRL_CLKOUTSEL0_MASK) == CMU_CTRL_CLKOUTSEL0_HFRCO &&
- (CMU_ROUTE & CMU_ROUTE_CLKOUT0PEN)
- )))
- {}
-// CMU_OSCENCMD = CMU_OSCENCMD_HFRCODIS;
-}
-
-/** Switch HFCLK to LFRC. This call is not only blocking, but even freezes
- * everything depending on HFCLK until LFRC is stable. The procedure is
- * sketched in d0034_efm32tg_reference_manual.pdf figure 11.2. */
-static void cmu_hfclk_switch_blocking(void)
-{
- CMU_OSCENCMD = CMU_OSCENCMD_LFRCOEN;
- CMU_CMD = CMU_CMD_HFCLKSEL_LFRCO;
- CMU_OSCENCMD = CMU_OSCENCMD_HFRCODIS;
-}
-
-/** @} */
-
-/** @} */
-
-#endif
diff --git a/include/libopencm3/efm32/tinygecko/cmu.yaml b/include/libopencm3/efm32/tinygecko/cmu.yaml
deleted file mode 100644
index 7b83b7f..0000000
--- a/include/libopencm3/efm32/tinygecko/cmu.yaml
+++ /dev/null
@@ -1,458 +0,0 @@
-copyright: "2012 chrysn <chrysn@fsfe.org>"
-license: lgpl-3+
-ingroup: EFM32TG
-shortdocname: EFM32TG_CMU
-shortname: CMU
-longname: Clock Management Unit
-baseref: d0034_efm32tg_reference_manual.pdf section 11
-registers_baserefext: ".4"
-templateregs:
- - name: I
- comment: Bits for the various CMU interrupt registers
- fields:
- - {name: CALOF, shift: 6}
- - {name: CALRDY, shift: 5}
- - {name: AUXHFRCORDY, shift: 4}
- - {name: LFXORDY, shift: 3}
- - {name: LFRCORDY, shift: 2}
- - {name: HFXORDY, shift: 1}
- - {name: HFRCORDY, shift: 0}
-registers:
- - name: CTRL
- offset: 0x000
- definition_baserefext: ".5.1"
- fields:
- - name: DBGCLK
- shift: 28
- values:
- - {name: AUXHFRCO, value: 0}
- - {name: HFCLK, value: 1}
- - name: CLKOUTSEL1
- shift: 23
- length: 3
- values:
- - {name: LFRCO, value: 0}
- - {name: LFXO, value: 1}
- - {name: HFCLK, value: 2}
- - {name: LFXOQ, value: 3}
- - {name: HFXOQ, value: 4}
- - {name: LFRCOQ, value: 5}
- - {name: HFRCOQ, value: 6}
- - {name: AUXHFRCOQ, value: 7}
- - name: CLKOUTSEL0
- shift: 20
- length: 3
- values:
- - {name: HFRCO, value: 0}
- - {name: HFXO, value: 1}
- - {name: HFCLK2, value: 2}
- - {name: HFCLK4, value: 3}
- - {name: HFCLK8, value: 4}
- - {name: HFCLK16, value: 5}
- - {name: ULFRCO, value: 6}
- - {name: AUXHFRCO, value: 7}
- - name: LFXOTIMEOUT
- shift: 18
- length: 2
- values:
- - {name: 8CYCLES, value: 0}
- - {name: 1KCYCLES, value: 1}
- - {name: 16KCYCLES, value: 2}
- - {name: 32KCYCLES, value: 3}
- - name: LFXOBUFCUR
- shift: 17
- - name: LXFOBOOST
- shift: 13
- values:
- - {name: 70PCENT, value: 0}
- - {name: 100PCENT, value: 1}
- - name: LFXOMODE
- shift: 11
- length: 2
- values:
- - {name: XTAL, value: 0}
- - {name: BUFEXTCLK, value: 1}
- - {name: DIGEXTCLK, value: 2}
- - name: HFXOTIMEOUT
- shift: 9
- length: 2
- values:
- - {name: 8CYCLES, value: 0}
- - {name: 256CYCLES, value: 1}
- - {name: 1KCYCLES, value: 2}
- - {name: 16KCYCLES, value: 3}
- - name: HFXOGLITCHDETEN
- shift: 7
- - name: HFXOBUFCUR
- shift: 5
- length: 2
- type: undocumented
- - name: HFXOBOOST
- shift: 2
- length: 2
- values:
- - {name: 50PCENT, value: 0}
- - {name: 70PCENT, value: 1}
- - {name: 80PCENT, value: 2}
- - {name: 100PCENT, value: 3}
- - name: HFXOMODE
- shift: 0
- length: 2
- values:
- - {name: XTAL, value: 0}
- - {name: BUFEXTCLK, value: 1}
- - {name: DIGEXTCLK, value: 2}
- - name: HFCORECLKDIV
- offset: 0x004
- definition_baserefext: ".5.2"
- values: &HFCORECLKDIV_values
- - {value: 0, name: HFCLK}
- - {value: 1, name: HFCLK2}
- - {value: 2, name: HFCLK4}
- - {value: 3, name: HFCLK8}
- - {value: 4, name: HFCLK16}
- - {value: 5, name: HFCLK32}
- - {value: 6, name: HFCLK64}
- - {value: 7, name: HFCLK128}
- - {value: 8, name: HFCLK256}
- - {value: 9, name: HFCLK512}
- - name: HFPERCLKDIV
- offset: 0x008
- definition_baserefext: ".5.3"
- fields:
- - name: HFPERCLKEN
- shift: 8
- - name: HFPERCLKDIV
- shift: 0
- length: 3
- # not using generically named values here due to different register structure
- values: *HFCORECLKDIV_values
- - name: HFRCOCTRL
- offset: 0x00c
- definition_baserefext: ".5.4"
- fields:
- - name: SUDELAY
- shift: 12
- length: 5
- type: undocumented
- - name: BAND
- shift: 8
- length: 3
- values:
- - {value: 0, name: 1MHZ}
- - {value: 1, name: 7MHZ}
- - {value: 2, name: 11MHZ}
- - {value: 3, name: 14MHZ}
- - {value: 4, name: 21MHZ}
- - {value: 5, name: 28MHZ}
- - name: TUNING
- shift: 0
- length: 8
- type: uint
- - name: LFRCOCTRL
- offset: 0x010
- definition_baserefext: ".5.5"
- length: 7
- type: uint
- - name: AUXHFRCOCTRL
- offset: 0x014
- definition_baserefext: ".5.6"
- fields:
- - name: BAND
- shift: 8
- length: 3
- values:
- - {value: 0, name: 14MHZ}
- - {value: 1, name: 11MHZ}
- - {value: 2, name: 7MHZ}
- - {value: 3, name: 1MHZ}
- - {value: 6, name: 28MHZ}
- - {value: 7, name: 21MHZ}
- - name: TUNING
- shift: 0
- length: 8
- type: uint
- - name: CALCTRL
- offset: 0x018
- definition_baserefext: ".6.7"
- fields:
- - name: CONT
- shift: 6
- - name: DOWNSEL
- shift: 3
- length: 3
- values:
- - {value: 0, name: HFCLK}
- - {value: 1, name: HFXO}
- - {value: 2, name: LFXO}
- - {value: 3, name: HFRCO}
- - {value: 4, name: LFRCO}
- - {value: 5, name: AUXHFRCO}
- - name: UPSEL
- shift: 0
- length: 3
- values:
- - {value: 0, name: HFXO}
- - {value: 1, name: LFXO}
- - {value: 2, name: HFRCO}
- - {value: 3, name: LFRCO}
- - {value: 4, name: AUXHFRCO}
- - name: CALCNT
- offset: 0x01c
- definition_baserefext: ".5.8"
- length: 19
- type: uint
- - name: OSCENCMD
- offset: 0x020
- definition_baserefext: ".5.9"
- fields:
- - {name: LFXODIS, shift: 9}
- - {name: LFXOEN, shift: 8}
- - {name: LFRCODIS, shift: 7}
- - {name: LFRCOEN, shift: 6}
- - {name: AUXHFRCODIS, shift: 5}
- - {name: AUXHFRCOEN, shift: 4}
- - {name: HFXODIS, shift: 3}
- - {name: HFXOEN, shift: 2}
- - {name: HFRCODIS, shift: 1}
- - {name: HFRCOEN, shift: 0}
- - name: CMD
- offset: 0x024
- definition_baserefext: ".5.10"
- fields:
- - name: CALSTOP
- shift: 4
- - name: CALSTART
- shift: 3
- - name: HFCLKSEL
- shift: 0
- length: 3
- values:
- - {value: 1, name: HFRCO}
- - {value: 2, name: HFXO}
- - {value: 3, name: LFRCO}
- - {value: 4, name: LFXO}
- - name: LFCLKSEL
- offset: 0x028
- definition_baserefext: ".5.11"
- fields:
- - name: LFBE
- shift: 20
- values: &LFCLKSEL_LFBE
- - {value: 0, name: DISABLED}
- - {value: 1, name: ULFRCO}
- - name: LFAE
- shift: 16
- values: *LFCLKSEL_LFBE
- - name: LFB
- shift: 2
- length: 2
- values: &LFCLKSEL_LFB
- - {value: 0, name: DISABLED}
- - {value: 1, name: LFRCO}
- - {value: 2, name: LFXO}
- - {value: 3, name: HFCORECLKLEDIV2}
- - name: LFA
- shift: 0
- length: 2
- values: *LFCLKSEL_LFB
- - name: STATUS
- offset: 0x02c
- definition_baserefext: ".5.12"
- fields:
- - {name: CALBSY, shift: 14}
- - {name: LFXOSEL, shift: 13}
- - {name: LFRCOSEL, shift: 12}
- - {name: HFXOSEL, shift: 11}
- - {name: HFRCOSEL, shift: 10}
- - {name: LFXORDY, shift: 9}
- - {name: LFXOENS, shift: 8}
- - {name: LFRCORDY, shift: 7}
- - {name: LFRCOENS, shift: 6}
- - {name: AUXHFRCORDY, shift: 5}
- - {name: AUXHFRCOENS, shift: 4}
- - {name: HFXORDY, shift: 3}
- - {name: HFXOENS, shift: 2}
- - {name: HFRCORDY, shift: 1}
- - {name: HFRCOENS, shift: 0}
- - name: IF
- offset: 0x030
- definition_baserefext: ".5.13"
- fields: I
- - name: IFS
- offset: 0x034
- definition_baserefext: ".5.14"
- fields: I
- - name: IFC
- offset: 0x038
- definition_baserefext: ".5.15"
- fields: I
- - name: IEN
- offset: 0x03c
- definition_baserefext: ".5.16"
- fields: I
- - name: HFCORECLKEN0
- offset: 0x040
- definition_baserefext: ".5.17"
- fields:
- - {name: LE, shift: 2}
- - {name: DMA, shift: 1}
- - {name: AES, shift: 0}
- - name: HFPERCLKEN0
- offset: 0x044
- definition_baserefext: ".5.18"
- fields:
- - {name: I2C0, shift: 11}
- - {name: DAC0, shift: 10}
- - {name: ADC0, shift: 9}
- - {name: PRS, shift: 8}
- - {name: VCMP, shift: 7}
- - {name: GPIO, shift: 6}
- - {name: TIMER1, shift: 5}
- - {name: TIMER0, shift: 4}
- - {name: USART1, shift: 3}
- - {name: USART0, shift: 2}
- - {name: ACMP1, shift: 1}
- - {name: ACMP0, shift: 0}
- - name: SYNCBUSY
- offset: 0x050
- definition_baserefext: ".5.19"
- fields:
- - {name: LFBPRESC0, shift: 6}
- - {name: LFBCLKEN0, shift: 4}
- - {name: LFAPRESC0, shift: 2}
- - {name: LFACLKEN0, shift: 0}
- - name: FREEZE
- offset: 0x054
- definition_baserefext: ".5.20"
- fields:
- - name: REGFREEZE
- shift: 0
- values:
- - {value: 0, name: UPDATE}
- - {value: 1, name: FREEZE}
- - name: LFACLKEN0
- offset: 0x058
- definition_baserefext: ".5.21"
- fields:
- - {name: LCD, shift: 3}
- - {name: LETIMER0, shift: 2}
- - {name: RTC, shift: 1}
- - {name: LESENSE, shift: 0}
- - name: LFBCLKEN0
- offset: 0x060
- definition_baserefext: ".5.22"
- fields:
- - {name: LEUART0, shift: 0}
- - name: LFAPRESC0
- offset: 0x068
- definition_baserefext: ".5.23"
- fields:
- - name: LCD
- shift: 12
- length: 2
- values:
- - {value: 0, name: DIV16}
- - {value: 1, name: DIV32}
- - {value: 2, name: DIV64}
- - {value: 3, name: DIV128}
- - name: LETIMER0
- shift: 8
- length: 4
- values: &LFAPRESC0_LETIMER0_values
- - {value: 0, name: DIV1}
- - {value: 1, name: DIV2}
- - {value: 2, name: DIV4}
- - {value: 3, name: DIV8}
- - {value: 4, name: DIV16}
- - {value: 5, name: DIV32}
- - {value: 6, name: DIV64}
- - {value: 7, name: DIV128}
- - {value: 8, name: DIV256}
- - {value: 9, name: DIV512}
- - {value: 10, name: DIV1024}
- - {value: 11, name: DIV2048}
- - {value: 12, name: DIV4096}
- - {value: 13, name: DIV8192}
- - {value: 14, name: DIV16384}
- - {value: 15, name: DIV32768}
- - name: RTC
- shift: 4
- length: 4
- values: *LFAPRESC0_LETIMER0_values
- - name: LESENSE
- shift: 0
- length: 2
- values:
- - {value: 0, name: DIV1}
- - {value: 1, name: DIV2}
- - {value: 2, name: DIV4}
- - {value: 3, name: DIV8}
- - name: LFBPRESC0
- offset: 0x070
- definition_baserefext: ".5.24"
- fields:
- - name: LEUART0
- shift: 0
- length: 2
- values:
- - {value: 0, name: DIV1}
- - {value: 1, name: DIV2}
- - {value: 2, name: DIV4}
- - {value: 3, name: DIV8}
- - name: PCNTCTRL
- offset: 0x078
- definition_baserefext: ".5.25"
- fields:
- - name: PCNT0CLKSEL
- shift: 1
- values:
- - {value: 0, name: LFACLK}
- - {value: 1, name: PCNT0S0}
- - name: PCNT0CLKEN
- shift: 0
- - name: LCDCTRL
- offset: 0x07c
- definition_baserefext: ".5.26"
- fields:
- - name: VBFDIV
- shift: 4
- length: 3
- values:
- - {value: 0, name: DIV1}
- - {value: 1, name: DIV2}
- - {value: 2, name: DIV4}
- - {value: 3, name: DIV8}
- - {value: 4, name: DIV16}
- - {value: 5, name: DIV32}
- - {value: 6, name: DIV64}
- - {value: 7, name: DIV128}
- - name: VBOOSTEN
- shift: 3
- - name: FDIV
- shift: 0
- length: 3
- type: uint
- - name: ROUTE
- offset: 0x080
- definition_baserefext: ".5.27"
- fields:
- - name: LOCATION
- shift: 4
- length: 3
- values:
- - {value: 0, name: LOC0}
- - {value: 1, name: LOC1}
- - name: CLKOUT1PEN
- shift: 1
- - name: CLKOUT0PEN
- shift: 0
- - name: LOCK
- offset: 0x084
- definition_baserefext: ".5.28"
- length: 16
- values:
- - {name: IS_UNLOCKED, value: 0}
- - {name: IS_LOCKED, value: 1}
- - {name: SET_LOCKED, value: 0}
- - {name: SET_UNLOCKED, value: "0x580E"}
diff --git a/include/libopencm3/efm32/tinygecko/devicerevision.h b/include/libopencm3/efm32/tinygecko/devicerevision.h
deleted file mode 100644
index 45da408..0000000
--- a/include/libopencm3/efm32/tinygecko/devicerevision.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * This file is part of the libopencm3 project.
- *
- * Copyright (C) 2012 chrysn <chrysn@fsfe.org>
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library. If not, see <http://www.gnu.org/licenses/>.
- */
-
-/* FIXME: proper documentation, see where this fits, if we need this at all
- * etc. this was just a first attempt at implementing something easy with
- * MMIO32. */
-
-/* this implements d0034_efm32tg_reference_manual.pdf's 7.3.4 "Device Revision"
- * section */
-
-#ifndef LIBOPENCM3_EFM32_TINYGECKO_DEVICEREVISION_H
-#define LIBOPENCM3_EFM32_TINYGECKO_DEVICEREVISION_H
-
-#include <libopencm3/cm3/common.h>
-
-#define DEVICEREVISION_PID2 MMIO32(0xE00FFFE8)
-#define DEVICEREVISION_PID3 MMIO32(0xE00FFFEC)
-
-/* devicerevision_revision_get has a comment that would make these definitions
- * obsolete; i'm not sure how far it is reasonable to parameterize everythin
- * g*/
-#define DEVICEREVISION_REVISION_LENGTH 4
-#define DEVICEREVISION_REVISION_SHIFT 4
-#define DEVICEREVISION_REVISION_MASK (~(~0<<DEVICEREVISION_REVISION_LENGTH)<<DEVICEREVISION_REVISION_SHIFT) /* 0x000000f0, bits 7:4 */
-
-#define DEVICEREVISION_REVISION_A 0x00
-
-/* Read the device's hardcoded Revision. Return values can be compared against
- * the DEVICEREVISION_REVISION_A constant, the only value given in the current
- * specification. */
-extern u8 devicerevision_revision_get(void);
-
-#endif
diff --git a/include/libopencm3/efm32/tinygecko/emu.convenienceheaders b/include/libopencm3/efm32/tinygecko/emu.convenienceheaders
deleted file mode 100644
index 7d5893d..0000000
--- a/include/libopencm3/efm32/tinygecko/emu.convenienceheaders
+++ /dev/null
@@ -1,18 +0,0 @@
-/** EMU convenience functions
- *
- * These functions can be used to send the chip to low energy modes.
- *
- * @todo Implement other sleep modes than EM1. Implement WFI vs WFE waits.
- *
- * @defgroup EFM32TG_EMU_convenience EMU convenience functions
- * @{
- */
-
-/** Put the system into EM1 low energy mode. */
-static void emu_sleep_em1(void)
-{
- /* FIXME: set SLEEPDEEP to 0 */
- __asm__("wfi");
-}
-
-/** @} */
diff --git a/include/libopencm3/efm32/tinygecko/emu.h b/include/libopencm3/efm32/tinygecko/emu.h
deleted file mode 100644
index 9a043cb..0000000
--- a/include/libopencm3/efm32/tinygecko/emu.h
+++ /dev/null
@@ -1,127 +0,0 @@
-/*
- * This file is part of the libopencm3 project.
- *
- * Copyright (C) 2012 chrysn <chrysn@fsfe.org>
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library. If not, see <http://www.gnu.org/licenses/>.
- */
-
-/** @file
- * @see EFM32TG_EMU
- */
-
-/** Definitions for the EMU subsystem (Energy Management Unit).
- *
- * This corresponds to the description in d0034_efm32tg_reference_manual.pdf
- * section 10.
- *
- * @ingroup EFM32TG
- * @defgroup EFM32TG_EMU EMU (Energy Management Unit)
- * @{
- */
-
-#ifndef LIBOPENCM3_EFM32_TINYGECKO_EMU_H
-#define LIBOPENCM3_EFM32_TINYGECKO_EMU_H
-
-#include <libopencm3/cm3/common.h>
-#include <libopencm3/efm32/memorymap.h>
-
-/** Register definitions and register value definitions for the EMU subsystem
- *
- * @defgroup EFM32TG_EMU_regsandvals EMU registers and values
- * @{
- */
-
-/** These definitions reflect d0034_efm32tg_reference_manual.pdf section 10.4
- *
- * @defgroup EFM32TG_EMU_registers EMU registers
- * @{
- */
-
-#define EMU_CTRL MMIO32(EMU_BASE + 0x000) /**< @see EFM32TG_EMU_CTRL_bits */
-#define EMU_LOCK MMIO32(EMU_BASE + 0x008) /**< @see EFM32TG_EMU_LOCK_values */
-#define EMU_AUXCTRL MMIO32(EMU_BASE + 0x024) /**< @see EFM32TG_EMU_AUXCTRL_bits */
-
-/** @} */
-
-/** Bit states for the EMU_CTRL register
- *
- * See d0034_efm32tg_reference_manual.pdf section 10.5.1 for definitions, and
- * 10.3.2 for details (especially on why EM4CTRL_TWO and _THREE are defined).
- *
- * @defgroup EFM32TG_EMU_CTRL_bits EMU CTRL bits
- * @{
- */
-
-#define EMU_CTRL_EM4CTRL_TWO (2<<2)
-#define EMU_CTRL_EM4CTRL_THREE (3<<2)
-#define EMU_CTRL_EM4CTRL_MASK (0x3<<2)
-#define EMU_CTRL_EM2BLOCK (1<<1) /**< When this bit is set, no mode lower than EM1 will be entered */
-#define EMU_CTRL_EMVREG (1<<0) /**< When this bit is set, the voltage regulator will stay on in modes lower than EM1 */
-
-/** @} */
-
-/** Values for the EMU_LOCK register
- *
- * See d0034_efm32tg_reference_manual.pdf section 10.5.2 for definitions. There
- * seems not to be another mention of it.
- *
- * @defgroup EFM32TG_EMU_LOCK_values EMU LOCK values
- * @{
- */
-
-#define EMU_LOCK_IS_UNLOCKED 0 /**< When the LOCK register reads as this value, it is open */
-#define EMU_LOCK_IS_LOCKED 1 /**< When the LOCK register reads as this value, it is locked */
-#define EMU_LOCK_SET_LOCKED 0 /**< Write this to the LOCK register to lock the EMU */
-#define EMU_LOCK_SET_UNLOCKED 0xade8 /**< Write this to the LOCK register to unlock the EMU */
-
-/** @} */
-
-/** Bit states for the EMU_AUXCTRL register
- *
- * See d0034_efm32tg_reference_manual.pdf section 10.5.3 for definitions, and
- * 9.5.3 for details.
- *
- * @defgroup EFM32TG_EMU_AUXCTRL_bits EMU AUXCTRL bits
- * @{
- */
-
-#define EMU_AUXCTRL_HRCCLR (1<<0)
-
-/** @} */
-
-/** @} */
-
-/** EMU convenience functions
- *
- * These functions can be used to send the chip to low energy modes.
- *
- * @todo Implement other sleep modes than EM1. Implement WFI vs WFE waits.
- *
- * @defgroup EFM32TG_EMU_convenience EMU convenience functions
- * @{
- */
-
-/** Put the system into EM1 low energy mode. */
-static void emu_sleep_em1(void)
-{
- /* FIXME: set SLEEPDEEP to 0 */
- __asm__("wfi");
-}
-
-/** @} */
-
-/** @} */
-
-#endif
diff --git a/include/libopencm3/efm32/tinygecko/emu.yaml b/include/libopencm3/efm32/tinygecko/emu.yaml
deleted file mode 100644
index 4e0b30e..0000000
--- a/include/libopencm3/efm32/tinygecko/emu.yaml
+++ /dev/null
@@ -1,50 +0,0 @@
-copyright: "2012 chrysn <chrysn@fsfe.org>"
-license: lgpl-3+
-ingroup: EFM32TG
-shortdocname: EFM32TG_EMU
-shortname: EMU
-longname: Energy Management Unit
-baseref: d0034_efm32tg_reference_manual.pdf section 10
-registers_baserefext: ".4"
-registers:
- - name: CTRL
- definition_baserefext: .5.1
- details: ", and 10.3.2 for details (especially on why EM4CTRL_TWO and _THREE are defined)."
- offset: 0x000
- fields:
- - name: EM4CTRL
- shift: 2
- length: 2
- values:
- - {name: TWO, value: 2}
- - {name: THREE, value: 3}
- - name: EM2BLOCK
- shift: 1
- doc: When this bit is set, no mode lower than EM1 will be entered
- - name: EMVREG
- shift: 0
- doc: When this bit is set, the voltage regulator will stay on in modes lower than EM1
- - name: LOCK
- definition_baserefext: .5.2
- details: ". There seems not to be another mention of it."
- offset: 0x008
- values:
- - name: IS_UNLOCKED
- value: 0
- doc: When the LOCK register reads as this value, it is open
- - name: IS_LOCKED
- value: 1
- doc: When the LOCK register reads as this value, it is locked
- - name: SET_LOCKED
- value: 0
- doc: Write this to the LOCK register to lock the EMU
- - name: SET_UNLOCKED
- value: "0xade8"
- doc: Write this to the LOCK register to unlock the EMU
- - name: AUXCTRL
- definition_baserefext: .5.3
- details: ", and 9.5.3 for details."
- offset: 0x024
- fields:
- - name: HRCCLR
- shift: 0
diff --git a/include/libopencm3/efm32/tinygecko/generate-license.yaml b/include/libopencm3/efm32/tinygecko/generate-license.yaml
deleted file mode 100644
index baeef88..0000000
--- a/include/libopencm3/efm32/tinygecko/generate-license.yaml
+++ /dev/null
@@ -1,19 +0,0 @@
-"lgpl-3+": |
- /*
- * This file is part of the {projectname} project.
- *
- * Copyright (C) {copyright}
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library. If not, see <http://www.gnu.org/licenses/>.
- */
diff --git a/include/libopencm3/efm32/tinygecko/generate.py b/include/libopencm3/efm32/tinygecko/generate.py
deleted file mode 100644
index 7f426a4..0000000
--- a/include/libopencm3/efm32/tinygecko/generate.py
+++ /dev/null
@@ -1,176 +0,0 @@
-#!/usr/bin/env python
-
-import yaml
-import logging
-import textwrap
-
-def commentblock(*textblocks, **formatargs):
- ret = []
- nowrapcommands = set("@defgroup")
- ret.extend(textwrap.wrap(textblocks[0].format(**formatargs), 80, initial_indent="/** ", subsequent_indent=" * "))
- last_block_was_at = textblocks[0].startswith('@')
- for b in textblocks[1:]:
- formatted = b.format(**formatargs)
-
- if not (last_block_was_at and b.startswith('@')):
- ret.append(" *")
- if any(b.startswith(c) for c in nowrapcommands):
- ret.append(" * " + formatted)
- else:
- ret.extend(textwrap.wrap(formatted, 80, initial_indent=" * ", subsequent_indent=" * "))
- last_block_was_at = b.startswith('@')
- return "\n".join(ret) + "\n */\n"
-
-def yaml2h(filenamebase):
- headername = "%s.h"%filenamebase
- yamlname = "%s.yaml"%filenamebase
- conveniencename = "%s.convenienceheaders"%filenamebase
-
- logging.info("Generating %s from %s", headername, yamlname)
-
- data = yaml.load(open(yamlname))
- # some defaults
- data.setdefault("projectname", "libopencm3")
- data.setdefault("includeguard", "LIBOPENCM3_EFM32_TINYGECKO_%s_H"%data['shortname'])
-
- with open(headername, 'w') as outfile:
- def wc(*args, **kwargs): # wrap "outfile" and "data" (as default) arguments -- i'm a lazy typer
- final_kwargs = data.copy()
- final_kwargs.update(kwargs)
- outfile.write(commentblock(*args, **final_kwargs))
- def wc_close():
- outfile.write("/** @} */\n")
- def nl(): outfile.write("\n")
- def define(key, value, comment=None):
- outfile.write("#define ")
- outfile.write(key)
- outfile.write(" "*max(24-len(key), 1))
- outfile.write(str(value))
- if comment is not None:
- outfile.write(" /**< %s */"%comment)
- nl()
-
- outfile.write(licensedata[data['license']].format(**data))
- nl()
- wc("@file", "@see {shortdocname}")
- nl()
- wc("Definitions for the {shortname} subsystem ({longname}).", "This corresponds to the description in {baseref}.", "@ingroup {ingroup}", "@defgroup {shortdocname} {shortname} ({longname})", "@{{")
- nl()
- outfile.write("#ifndef {includeguard}\n#define {includeguard}\n".format(**data))
- nl()
- outfile.write("#include <libopencm3/cm3/common.h>\n#include <libopencm3/efm32/memorymap.h>\n")
- nl()
- wc("Register definitions and register value definitions for the {shortname} subsystem", "@defgroup {shortdocname}_regsandvals {shortname} registers and values", "@{{")
- nl()
-
- regs = data['registers']
-
- for template in data.get('templateregs', []):
- template['is_template'] = []
- regs.append(template)
-
- regs_dict = dict((x['name'], x) for x in regs) # for easier access. they've got to be a list in yaml to preserve order
-
- wc("These definitions reflect {baseref}{registers_baserefext}", "@defgroup {shortdocname}_registers {shortname} registers", "@{{")
- nl()
-
- for regdata in regs:
- has_bits = "fields" in regdata
- has_values = "values" in regdata
- is_template = "is_template" in regdata
- if is_template:
- # this isn't a real register, just a template
- continue
- secondcomponent_name = regdata['name']
- if (has_bits and isinstance(regdata['fields'], str)) or (has_values and isinstance(regdata['values'], str)):
- # uses a template
- secondcomponent_name = regdata['fields'] if has_bits else regdata['values']
- regs_dict[secondcomponent_name]['is_template'].append(regdata['name'])
-
- define("%s_%s"%(data['shortname'], regdata['name']), "MMIO32(%s_BASE + %#.003x)"%(data['shortname'], regdata['offset']), "@see %s_%s_%s"%(data['shortdocname'], secondcomponent_name, 'values' if 'values' in regdata else 'bits') if has_bits or has_values else None)
- nl()
- wc_close() # close register definitions
- nl()
-
- for regdata in regs:
- has_bits = "fields" in regdata
- has_values = "values" in regdata
- is_template = "is_template" in regdata
- if not has_bits and not has_values:
- continue
-
- if (has_bits and isinstance(regdata['fields'], str)) or (has_values and isinstance(regdata['values'], str)):
- # uses a template, doesn't need own section
- continue
-
- commentlines = []
- if is_template:
- commentlines.append("%s for the {shortname} \"{name}\" group of registers (%s)"%("Bit states" if has_bits else "Values", ", ".join(regdata['is_template'])))
- assert len(regdata['is_template']) > 0, "What should I talk about when nobody uses this template?"
- if 'override_backref' in regdata:
- commentlines.append(regdata['override_backref'])
- else:
- commentlines.append("These registers use this:")
- commentlines.append("<ul>") # FIXME: once we're using markdown 1.8, this can be changed to markdown
- for user in regdata['is_template']:
- userdata = regs_dict[user]
- # FIXME: this is an ugly hack around this being in a single wc() line which doesn't take per-line contexts
- mergeddata = data.copy()
- mergeddata.update(userdata)
- commentlines.append(("<li>The {shortname}_{name} register; see {baseref}{definition_baserefext} for definitions"+regdata.get("details", "."+"</li>")).format(**mergeddata))
- commentlines.append("</ul>")
- commentlines.append('@defgroup {shortdocname}_{name}_%s {shortname} {name} %s'%(('bits' if has_bits else 'values', 'bits group' if has_bits else 'values group')))
- else:
- commentlines.append("%s for the {shortname}_{name} register"%("Bit states" if has_bits else "Values"))
- commentlines.append("See {baseref}{definition_baserefext} for definitions"+regdata.get("details", "."))
- commentlines.append('@defgroup {shortdocname}_{name}_%s {shortname} {name} %s'%(('bits' if has_bits else 'values',)*2))
- commentlines.append('@{{')
- wc(*commentlines, **regdata)
- nl()
-
- if has_bits:
- for field in regdata['fields']:
- #shiftdefine = "_%s_%s_%s_shift"%(shortname, regdata['name'], field['name'])
- #define(shiftdefine, field['shift'])
-
- # there is one condition under which field's doc would get shown; show it immediately otherwise
- if 'doc' in field and not ("values" not in field and field.get("length", 1) == 1):
- wc(field['doc'])
-
- if "values" in field:
- for value in field.get("values"):
- define("%s_%s_%s_%s"%(data['shortname'], regdata['name'], field['name'], value['name']), value['value'] if "mask" in field else "(%s<<%s)"%(value['value'], field['shift']), value.get('doc', None))
- else:
- if field.get('length', 1) == 1:
- define("%s_%s_%s"%(data['shortname'], regdata['name'], field['name']), "(1<<%s)"%field['shift'], field.get('doc', None))
- else:
- # FIXME: this should require the 'type' parameter to be set on this field
- pass
-
- if "values" in field or field.get("length", 1) != 1:
- if "mask" in field:
- mask = field['mask']
- else:
- mask = "(%#x<<%s)"%(~(~0<<field.get('length', 1)), field['shift'])
- define("%s_%s_%s_MASK"%(data['shortname'], regdata['name'], field['name']), mask)
- else:
- for value in regdata['values']:
- define("%s_%s_%s"%(data['shortname'], regdata['name'], value['name']), value['value'], value.get('doc', None))
-
- nl()
- wc_close()
- nl()
- wc_close() # close registers and values
- nl()
-
- outfile.write(open(conveniencename).read())
-
- nl()
- wc_close() # close convenience
- nl()
- outfile.write("#endif\n")
-
-if __name__ == "__main__":
- licensedata = yaml.load(open("generate-license.yaml"))
- for basename in yaml.load(open('generate.yaml')):
- yaml2h(basename)
diff --git a/include/libopencm3/efm32/tinygecko/generate.yaml b/include/libopencm3/efm32/tinygecko/generate.yaml
deleted file mode 100644
index b7ade5d..0000000
--- a/include/libopencm3/efm32/tinygecko/generate.yaml
+++ /dev/null
@@ -1,3 +0,0 @@
-- emu
-- cmu
-- lcd
diff --git a/include/libopencm3/efm32/tinygecko/gpio.h b/include/libopencm3/efm32/tinygecko/gpio.h
deleted file mode 100644
index 2c65d0d..0000000
--- a/include/libopencm3/efm32/tinygecko/gpio.h
+++ /dev/null
@@ -1,498 +0,0 @@
-/*
- * This file is part of the libopencm3 project.
- *
- * Copyright (C) 2012 chrysn <chrysn@fsfe.org>
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library. If not, see <http://www.gnu.org/licenses/>.
- */
-
-/** @file
- * @see EFM32TG_GPIO
- */
-
-/** Definitions for the GPIO subsystem (General Purpose Input Output).
- *
- * This corresponds to the description in d0034_efm32tg_reference_manual.pdf
- * section 28.
- *
- * @ingroup EFM32TG
- * @defgroup EFM32TG_GPIO GPIO (General Purpose Input Output)
- * @{
- */
-
-#ifndef LIBOPENCM3_EFM32_TINYGECKO_GPIO_H
-#define LIBOPENCM3_EFM32_TINYGECKO_GPIO_H
-
-#include <libopencm3/cm3/common.h>
-#include <libopencm3/efm32/memorymap.h>
-
-/** Register definitions and register value definitions for the GPIO subsystem
- *
- * @defgroup EFM32TG_GPIO_regsandvals GPIO registers and values
- * @{
- */
-
-/** These definitions reflect d0034_efm32tg_reference_manual.pdf section 28.4
- *
- * The bulk of the registers defined here (like GPIO_PA_CTRL) will not be used
- * inside the convenience functions, but are provided for direct access.
- *
- * @todo This section could profit from bit-banding.
- *
- * @defgroup EFM32TG_GPIO_registers GPIO registers
- * @{
- */
-#define GPIO_Px_CTRL(port) MMIO32(port + 0x000) /**< @see EFM32TG_GPIO_Px_CTRL_bits */
-#define GPIO_Px_MODEL(port) MMIO32(port + 0x004) /**< @see EFM32TG_GPIO_MODE_values */
-#define GPIO_Px_MODEH(port) MMIO32(port + 0x008) /**< @see EFM32TG_GPIO_MODE_values */
-#define GPIO_Px_DOUT(port) MMIO32(port + 0x00C) /**< @see EFM32TG_GPIO_pinnumberbits */
-#define GPIO_Px_DOUTSET(port) MMIO32(port + 0x010) /**< @see EFM32TG_GPIO_pinnumberbits */
-#define GPIO_Px_DOUTCLR(port) MMIO32(port + 0x014) /**< @see EFM32TG_GPIO_pinnumberbits */
-#define GPIO_Px_DOUTTGL(port) MMIO32(port + 0x018) /**< @see EFM32TG_GPIO_pinnumberbits */
-#define GPIO_Px_DIN(port) MMIO32(port + 0x01C) /**< @see EFM32TG_GPIO_pinnumberbits */
-#define GPIO_Px_PINLOCKN(port) MMIO32(port + 0x020) /**< @see EFM32TG_GPIO_pinnumberbits */
-
-#define GPIO_PA (GPIO_BASE + 0x000)
-#define GPIO_PA_CTRL GPIO_Px_CTRL(GPIO_PA)
-#define GPIO_PA_MODEL GPIO_Px_MODEL(GPIO_PA)
-#define GPIO_PA_MODEH GPIO_Px_MODEH(GPIO_PA)
-#define GPIO_PA_DOUT GPIO_Px_DOUT(GPIO_PA)
-#define GPIO_PA_DOUTSET GPIO_Px_DOUTSET(GPIO_PA)
-#define GPIO_PA_DOUTCLR GPIO_Px_DOUTCLR(GPIO_PA)
-#define GPIO_PA_DOUTTGL GPIO_Px_DOUTTGL(GPIO_PA)
-#define GPIO_PA_DIN GPIO_Px_DIN(GPIO_PA)
-#define GPIO_PA_PINLOCKN GPIO_Px_PINLOCKN(GPIO_PA)
-
-#define GPIO_PB (GPIO_BASE + 0x024)
-#define GPIO_PB_CTRL GPIO_Px_CTRL(GPIO_PB)
-#define GPIO_PB_MODEL GPIO_Px_MODEL(GPIO_PB)
-#define GPIO_PB_MODEH GPIO_Px_MODEH(GPIO_PB)
-#define GPIO_PB_DOUT GPIO_Px_DOUT(GPIO_PB)
-#define GPIO_PB_DOUTSET GPIO_Px_DOUTSET(GPIO_PB)
-#define GPIO_PB_DOUTCLR GPIO_Px_DOUTCLR(GPIO_PB)
-#define GPIO_PB_DOUTTGL GPIO_Px_DOUTTGL(GPIO_PB)
-#define GPIO_PB_DIN GPIO_Px_DIN(GPIO_PB)
-#define GPIO_PB_PINLOCKN GPIO_Px_PINLOCKN(GPIO_PB)
-
-#define GPIO_PC (GPIO_BASE + 0x048)
-#define GPIO_PC_CTRL GPIO_Px_CTRL(GPIO_PC)
-#define GPIO_PC_MODEL GPIO_Px_MODEL(GPIO_PC)
-#define GPIO_PC_MODEH GPIO_Px_MODEH(GPIO_PC)
-#define GPIO_PC_DOUT GPIO_Px_DOUT(GPIO_PC)
-#define GPIO_PC_DOUTSET GPIO_Px_DOUTSET(GPIO_PC)
-#define GPIO_PC_DOUTCLR GPIO_Px_DOUTCLR(GPIO_PC)
-#define GPIO_PC_DOUTTGL GPIO_Px_DOUTTGL(GPIO_PC)
-#define GPIO_PC_DIN GPIO_Px_DIN(GPIO_PC)
-#define GPIO_PC_PINLOCKN GPIO_Px_PINLOCKN(GPIO_PC)
-
-#define GPIO_PD (GPIO_BASE + 0x06C)
-#define GPIO_PD_CTRL GPIO_Px_CTRL(GPIO_PD)
-#define GPIO_PD_MODEL GPIO_Px_MODEL(GPIO_PD)
-#define GPIO_PD_MODEH GPIO_Px_MODEH(GPIO_PD)
-#define GPIO_PD_DOUT GPIO_Px_DOUT(GPIO_PD)
-#define GPIO_PD_DOUTSET GPIO_Px_DOUTSET(GPIO_PD)
-#define GPIO_PD_DOUTCLR GPIO_Px_DOUTCLR(GPIO_PD)
-#define GPIO_PD_DOUTTGL GPIO_Px_DOUTTGL(GPIO_PD)
-#define GPIO_PD_DIN GPIO_Px_DIN(GPIO_PD)
-#define GPIO_PD_PINLOCKN GPIO_Px_PINLOCKN(GPIO_PD)
-
-#define GPIO_PE (GPIO_BASE + 0x090)
-#define GPIO_PE_CTRL GPIO_Px_CTRL(GPIO_PE)
-#define GPIO_PE_MODEL GPIO_Px_MODEL(GPIO_PE)
-#define GPIO_PE_MODEH GPIO_Px_MODEH(GPIO_PE)
-#define GPIO_PE_DOUT GPIO_Px_DOUT(GPIO_PE)
-#define GPIO_PE_DOUTSET GPIO_Px_DOUTSET(GPIO_PE)
-#define GPIO_PE_DOUTCLR GPIO_Px_DOUTCLR(GPIO_PE)
-#define GPIO_PE_DOUTTGL GPIO_Px_DOUTTGL(GPIO_PE)
-#define GPIO_PE_DIN GPIO_Px_DIN(GPIO_PE)
-#define GPIO_PE_PINLOCKN GPIO_Px_PINLOCKN(GPIO_PE)
-
-#define GPIO_PF (GPIO_BASE + 0x0B4)
-#define GPIO_PF_CTRL GPIO_Px_CTRL(GPIO_PF)
-#define GPIO_PF_MODEL GPIO_Px_MODEL(GPIO_PF)
-#define GPIO_PF_MODEH GPIO_Px_MODEH(GPIO_PF)
-#define GPIO_PF_DOUT GPIO_Px_DOUT(GPIO_PF)
-#define GPIO_PF_DOUTSET GPIO_Px_DOUTSET(GPIO_PF)
-#define GPIO_PF_DOUTCLR GPIO_Px_DOUTCLR(GPIO_PF)
-#define GPIO_PF_DOUTTGL GPIO_Px_DOUTTGL(GPIO_PF)
-#define GPIO_PF_DIN GPIO_Px_DIN(GPIO_PF)
-#define GPIO_PF_PINLOCKN GPIO_Px_PINLOCKN(GPIO_PF)
-
-#define GPIO_EXTIPSELL MMIO32(GPIO_BASE + 0x100) /**< @see EFM32TG_GPIO_EXTIP_values */
-#define GPIO_EXTIPSELH MMIO32(GPIO_BASE + 0x104) /**< @see EFM32TG_GPIO_EXTIP_values */
-#define GPIO_EXTIRISE MMIO32(GPIO_BASE + 0x108) /**< @see EFM32TG_GPIO_pinnumberbits */
-#define GPIO_EXTIFALL MMIO32(GPIO_BASE + 0x10C) /**< @see EFM32TG_GPIO_pinnumberbits */
-#define GPIO_IEN MMIO32(GPIO_BASE + 0x110) /**< @see EFM32TG_GPIO_pinnumberbits */
-#define GPIO_IF MMIO32(GPIO_BASE + 0x114) /**< @see EFM32TG_GPIO_pinnumberbits */
-#define GPIO_IFS MMIO32(GPIO_BASE + 0x118) /**< @see EFM32TG_GPIO_pinnumberbits */
-#define GPIO_IFC MMIO32(GPIO_BASE + 0x11C) /**< @see EFM32TG_GPIO_pinnumberbits */
-#define GPIO_ROUTE MMIO32(GPIO_BASE + 0x120) /**< @see EFM32TG_GPIO_ROUTE_bits */
-#define GPIO_INSENSE MMIO32(GPIO_BASE + 0x124) /**< @see EFM32TG_GPIO_INSENSE_bits */
-#define GPIO_LOCK MMIO32(GPIO_BASE + 0x128) /**< @see EFM32TG_GPIO_LOCK_values */
-#define GPIO_CTRL MMIO32(GPIO_BASE + 0x12C) /**< @see EFM32TG_GPIO_CTRL_bits */
-#define GPIO_CMD MMIO32(GPIO_BASE + 0x130) /**< @see EFM32TG_GPIO_CMD_bits */
-#define GPIO_EM4WUEN MMIO32(GPIO_BASE + 0x134) /**< @see EFM32TG_GPIO_EM4WUEN_bits */
-#define GPIO_EM4WUPOL MMIO32(GPIO_BASE + 0x138) /**< @see EFM32TG_GPIO_EM4WUPOL_bits */
-#define GPIO_EM4WUCAUSE MMIO32(GPIO_BASE + 0x13C) /**< @see EFM32TG_GPIO_EM4WUCAUSE_bits */
-
-/** @} */
-
-/** Pin number bits
- *
- * Provided for convenience. They can be used on the GPIO_Px_DOUT,
- * GPIO_Px_DOUTSET, GPIO_Px_DOUTCLR, GPIO_Px_DOUTTGL, GPIO_Px_DIN,
- * GPIO_Px_PINLOCKN, GPIO_Px_EXTIRISE, GPIO_Px_EXTIFALL, GPIO_IEN, GPIO_IF,
- * GPIO_IFS, and GPIO_IFC registers.
- *
- * @defgroup EFM32TG_GPIO_pinnumberbits GPIO pin number bits
- * @{
- */
-
-#define GPIO0 (1 << 0)
-#define GPIO1 (1 << 1)
-#define GPIO2 (1 << 2)
-#define GPIO3 (1 << 3)
-#define GPIO4 (1 << 4)
-#define GPIO5 (1 << 5)
-#define GPIO6 (1 << 6)
-#define GPIO7 (1 << 7)
-#define GPIO8 (1 << 8)
-#define GPIO9 (1 << 9)
-#define GPIO10 (1 << 10)
-#define GPIO11 (1 << 11)
-#define GPIO12 (1 << 12)
-#define GPIO13 (1 << 13)
-#define GPIO14 (1 << 14)
-#define GPIO15 (1 << 15)
-#define GPIO_ALL 0xffff
-
-/** @} */
-
-/** Bit states for the GPIO_Px_CTRL register
- *
- * They are named as in d0034_efm32tg_reference_manual.pdf's section
- * 28.5.1.
- *
- * @defgroup EFM32TG_GPIO_Px_CTRL_bits GPIO Px CTRL bits
- * @{
- */
-
-#define GPIO_CTRL_DRIVEMODE_STANDARD 0 /**< 6mA drive current */
-#define GPIO_CTRL_DRIVEMODE_LOWEST 1 /**< 0.5mA drive current */
-#define GPIO_CTRL_DRIVEMODE_HIGH 2 /**< 20mA drive current */
-#define GPIO_CTRL_DRIVEMODE_LOW 3 /**< 2mA drive current */
-
-/** @} */
-
-/** These are the modes defined for the MODEx fields in the GPIO_Px_MODEL and
- * GPIO_Px_MODEH registers.
- *
- * These bit state definitions are not localized, meaning that they have to be
- * bitshifted by multiples of 4 to configure other pins than 0; configurations
- * for pins 0 to 7 go to GPIO_Px_MODEL (shifted by 4*pin), configurations for
- * pins 8 to 15 go to GPIO_Px_MODEH (shifted by 4*(pin-8)).
- *
- * For example, to set the mode for the 3rd pin of port A to pushpull, set
- * `GPIO_PA_MODEL = GPIO_MODE_PUSHPULL << (3*4);`.
- *
- * @todo Update the example as soon as there are convenience functions to do
- * this properly.
- *
- * They are named as in d0034_efm32tg_reference_manual.pdf's sections
- * 28.5.2/28.5.3. For explanations of what they really do, rather see section
- * 28.3.1.
- *
- * @defgroup EFM32TG_GPIO_MODE_values GPIO MODE values
- * @{
- */
-
-#define GPIO_MODE_DISABLED 0
-#define GPIO_MODE_INPUT 1
-#define GPIO_MODE_INPUTPULL 2
-#define GPIO_MODE_INPUTPULLFILTER 3
-#define GPIO_MODE_PUSHPULL 4
-#define GPIO_MODE_PUSHPULLDRIVE 5
-#define GPIO_MODE_WIREDOR 6
-#define GPIO_MODE_WIREDORPULLDOWN 7
-#define GPIO_MODE_WIREDAND 8
-#define GPIO_MODE_WIREDANDFILTER 9
-#define GPIO_MODE_WIREDANDPULLUP 10
-#define GPIO_MODE_WIREDANDPULLUPFILTER 11
-#define GPIO_MODE_WIREDANDDRIVE 12
-#define GPIO_MODE_WIREDANDDRIVEFILTER 13
-#define GPIO_MODE_WIREDANDDRIVEPULLUP 14
-#define GPIO_MODE_WIREDANDDRIVEPULLUPFILTER 15
-#define GPIO_MODE_MASK 0x0f
-
-/** @} */
-
-/** These are the modes defined for the EXTIPSELx fields in the GPIO_EXTIPSELL
- * and GPIO_EXTIPSELH registers.
- *
- * These bit state definitions are not localized, meaning that they have to be
- * bitshifted by multiples of 4 to configure other pins than 0; configurations
- * for pins 0 to 7 go to GPIO_EXTIPSELL (shifted by 4*pin), configurations for
- * pins 8 to 15 go to GPIO_EXTIPSELH (shifted by 4*(pin-8)).
- *
- * They are named as in d0034_efm32tg_reference_manual.pdf's sections
- * 28.5.10/28.5.11. For explanations of what they do, rather see section
- * 28.3.5.
- *
- * @defgroup EFM32TG_GPIO_EXTIP_values GPIO EXTIPSEL values
- * @{
- */
-
-#define GPIO_EXTIPSEL_PORTA 0 /**< Port A pin x selected for external interrupt x */
-#define GPIO_EXTIPSEL_PORTB 1 /**< Port B pin x selected for external interrupt x */
-#define GPIO_EXTIPSEL_PORTC 2 /**< Port C pin x selected for external interrupt x */
-#define GPIO_EXTIPSEL_PORTD 3 /**< Port D pin x selected for external interrupt x */
-#define GPIO_EXTIPSEL_PORTE 4 /**< Port E pin x selected for external interrupt x */
-#define GPIO_EXTIPSEL_PORTF 5 /**< Port F pin x selected for external interrupt x */
-
-/** @} */
-
-/** Bit states for the GPIO_ROUTE register
- *
- * See d0034_efm32tg_reference_manual.pdf section 28.5.18 for definitions, and
- * 28.3.4.1 for explanations.
- *
- * @defgroup EFM32TG_GPIO_ROUTE_bits GPIO ROUTE bits
- * @{
- */
-
-#define GPIO_ROUTE_SWLOCATION_MASK (0x03<<8)
-#define GPIO_ROUTE_SWLOCATION_LOC0 (0<<8) /**< Route SW pins to location 0 (see chip data sheet for exact pins */
-#define GPIO_ROUTE_SWLOCATION_LOC1 (1<<8) /**< Route SW pins to location 1 (see chip data sheet for exact pins */
-#define GPIO_ROUTE_SWLOCATION_LOC2 (2<<8) /**< Route SW pins to location 2 (see chip data sheet for exact pins */
-#define GPIO_ROUTE_SWLOCATION_LOC3 (3<<8) /**< Route SW pins to location 3 (see chip data sheet for exact pins */
-
-#define GPIO_ROUTE_SWOPEN (1<<2) /**< Serial Wire Viewer Output pin enabled */
-#define GPIO_ROUTE_SWDIOPEN (1<<1) /**< Serial Wire Data pin enabled */
-#define GPIO_ROUTE_SWCLKPEN (1<<0) /**< Serial Wire Clock pin enabled */
-
-/** @} */
-
-/** Bit states for the GPIO_INSENSE register
- *
- * See d0034_efm32tg_reference_manual.pdf section 28.5.19 for definitions, and
- * 28.3.7 for details.
- *
- * @defgroup EFM32TG_GPIO_INSENSE_bits GPIO INSENSE bits
- * @{
- */
-
-#define GPIO_INSENSE_PRS (1<<1) /**< Input sensing for PRS enabled */
-#define GPIO_INSENSE_INT (1<<0) /**< Input sensing for interrupts enabled */
-
-/** @} */
-
-/** Values for the GPIO_LOCK register
- *
- * See d0034_efm32tg_reference_manual.pdf section 28.5.20 for definitions, and
- * 28.3.1.1 for explanations.
- *
- * @defgroup EFM32TG_GPIO_LOCK_values GPIO LOCK bits
- * @{
- */
-
-#define GPIO_LOCK_IS_UNLOCKED 0 /**< When the LOCK register reads as this value, it is open */
-#define GPIO_LOCK_IS_LOCKED 1 /**< When the LOCK register reads as this value, it is locked */
-#define GPIO_LOCK_SET_LOCKED 0 /**< Write this to the LOCK register to lock down GPIO */
-#define GPIO_LOCK_SET_UNLOCKED 0xa543 /**< Write this to the LOCK register to unlock the GPIO */
-
-/** @} */
-
-/** Bit states for the GPIO_CTRL register
- *
- * See d0034_efm32tg_reference_manual.pdf section 28.5.21 for definitions, and
- * 28.3.4 for explanations.
- *
- * @defgroup EFM32TG_GPIO_CTRL_bits GPIO CTRL bits
- * @{
- */
-
-#define GPIO_CTRL_EM4RET (1<<0) /**< Retention of states in EM4 */
-
-/** @} */
-
-/** Bit states for the GPIO_CMD register
- *
- * See d0034_efm32tg_reference_manual.pdf section 28.5.22 for definitions and
- * figure 28.5 in case you wonder if that register is mentioned anywhere else
- * at all.
- *
- * @defgroup EFM32TG_GPIO_CMD_bits GPIO CMD bits
- * @{
- */
-
-#define GPIO_CMD_EM4WUCLR (1<<0) /**< Write this flag to clear EM4 wakeup requests */
-
-/** @} */
-
-/** Bit states for the GPIO_EM4WUEN register
- *
- * See d0034_efm32tg_reference_manual.pdf section 28.5.23 for definitions, and
- * 28.3.2 for explanations.
- *
- * @defgroup EFM32TG_GPIO_EM4WUEN_bits GPIO EM4WUEN bits
- * @{
- */
-
-#define GPIO_EM4WUEN_A0 0x01 /**< Wake up from EM4 on A0 activity */
-#define GPIO_EM4WUEN_A6 0x02 /**< Wake up from EM4 on A6 activity */
-#define GPIO_EM4WUEN_C9 0x04 /**< Wake up from EM4 on C9 activity */
-#define GPIO_EM4WUEN_F1 0x08 /**< Wake up from EM4 on F1 activity */
-#define GPIO_EM4WUEN_F3 0x10 /**< Wake up from EM4 on F3 activity */
-#define GPIO_EM4WUEN_E13 0x20 /**< Wake up from EM4 on E13 activity */
-
-/** @} */
-
-/** Bit states for the GPIO_EM4WUPOL register
- *
- * See d0034_efm32tg_reference_manual.pdf section 28.5.24 for definitions, and
- * 28.3.2 for explanations.
- *
- * @defgroup EFM32TG_GPIO_EM4WUPOL_bits GPIO EM4WUPOL bits
- * @{
- */
-
-#define GPIO_EM4WUPOL_A0 0x01 /**< High wake up from EM4 on A0 */
-#define GPIO_EM4WUPOL_A6 0x02 /**< High wake up from EM4 on A6 */
-#define GPIO_EM4WUPOL_C9 0x04 /**< High wake up from EM4 on C9 */
-#define GPIO_EM4WUPOL_F1 0x08 /**< High wake up from EM4 on F1 */
-#define GPIO_EM4WUPOL_F3 0x10 /**< High wake up from EM4 on F3 */
-#define GPIO_EM4WUPOL_E13 0x20 /**< High wake up from EM4 on E13 */
-
-/** @} */
-
-/** Bit states for the GPIO_EM4WUCAUSE register
- *
- * See d0034_efm32tg_reference_manual.pdf section 28.5.25 for definitions, and
- * 28.3.2 for explanations.
- *
- * @defgroup EFM32TG_GPIO_EM4WUCAUSE_bits GPIO EM4WUCAUSE bits
- * @{
- */
-
-#define GPIO_EM4WUCAUSE_A0 0x01 /**< Woke up from EM4 on A0 */
-#define GPIO_EM4WUCAUSE_A6 0x02 /**< Woke up from EM4 on A6 */
-#define GPIO_EM4WUCAUSE_C9 0x04 /**< Woke up from EM4 on C9 */
-#define GPIO_EM4WUCAUSE_F1 0x08 /**< Woke up from EM4 on F1 */
-#define GPIO_EM4WUCAUSE_F3 0x10 /**< Woke up from EM4 on F3 */
-#define GPIO_EM4WUCAUSE_E13 0x20 /**< Woke up from EM4 on E13 */
-
-/** @} */
-
-/** @} */
-
-/** GPIO convenience functions
- *
- * These functions try to be close to the STM32 F1 utility functions where
- * possible.
- *
- * The functions intentionally don't cover all the possible read- and write
- * operations to the GPIO registers. For example, reading the configured output
- * strength for a port is rarely required.
- *
- * Many convenience functions are static to allow inlining by the compiler.
- *
- * @todo Implement all the non-trivial but useful convenience functions.
- *
- * @defgroup EFM32TG_GPIO_convenience GPIO convenience functions
- * @{
- */
-
-/** Set a whole GPIO port's out data to a particular value
- *
- * \param gpioport Address of a GPIO port to use (eg GPIO_PA)
- * \param gpios Bit pattern the output of the port will be configured to (eg GPIO6|GPIO3 to switch pins 6 and 3 to high and all the others to low)
- */
-static void gpio_port_write(u32 gpioport, u16 data)
-{
- GPIO_Px_DOUT(gpioport) = data;
-}
-/** Set some bits in a GPIO port's out data
- *
- * \param gpioport Address of a GPIO port to use (eg GPIO_PA)
- * \param gpios GPIO pin(s) to be set to 1 (eg GPIO6|GPIO3 to switch pins 6 and 3 to high and leave all the others in their previous state)
- */
-static void gpio_set(u32 gpioport, u16 gpios)
-{
- GPIO_Px_DOUTSET(gpioport) = gpios;
-}
-/** Clear some bits in a GPIO port's out data
- *
- * \param gpioport Address of a GPIO port to use (eg GPIO_PA)
- * \param gpios GPIO pin(s) to be set to 0 (eg GPIO6|GPIO3 to switch pins 6 and 3 to low and leave all the others in their previous state)
- */
-static void gpio_clear(u32 gpioport, u16 gpios)
-{
- GPIO_Px_DOUTCLR(gpioport) = gpios;
-}
-/** Toggle some bits in a GPIO port's out data
- *
- * \param gpioport Address of a GPIO port to use (eg GPIO_PA)
- * \param gpios GPIO pin(s) that will be toggled (eg GPIO6|GPIO3 to toggle the output directions of pins 6 and 3 and leave all the others in their previous state)
- */
-static void gpio_toggle(u32 gpioport, u16 gpios)
-{
- GPIO_Px_DOUTTGL(gpioport) = gpios;
-}
-
-/** Read input bits from a GPIO's port in data
- *
- * \param gpioport Address of a GPIO port to use (eg GPIO_PA)
- * \returns Current value of the in register of the given port
- */
-static u16 gpio_port_read(u32 gpioport)
-{
- return GPIO_Px_DIN(gpioport);
-}
-/** Read input bits from a GPIO's port in data
- *
- * \param gpioport Address of a GPIO port to use (eg GPIO_PA)
- * \param gpios Bits that will be read (eg GPIO6|GPIO3 to read pins 6 and 3)
- * \returns Bit pattern that contains 1 in all pin positions that currently read as high (eg GPIO6 if port A's 6th pin is currently high and the 3rd pin is low)
- */
-static u16 gpio_get(u32 gpioport, u16 gpios)
-{
- return gpio_port_read(gpioport) & gpios;
-}
-
-/** Configure a particular pin configuration on one or more pins
- *
- * This function is not atomic. It has to be made sure that it is not
- * interrupted by other code that modifies the port's configuration.
- *
- * \param gpioport Address of a GPIO port to use (eg GPIO_PA)
- * \param mode Pin configuration mode to set (eg GPIO_MODE_INPUT)
- * \param gpios Pins to configure (eg GPIO6|GPIO3 to set the mode on pins 6 and 3)
- */
-void gpio_set_mode(u32 gpioport, u8 mode, u16 gpios);
-
-/** Configure the alternate drive strength for a port
- *
- * \param gpioport Address of a GPIO port to use (eg GPIO_PA)
- * \param strength Alternate drive strength to configure for the port (eg GPIO_CTRL_DRIVEMODE_HIGH)
- */
-static void gpio_set_strength(u32 gpioport, u8 strength)
-{
- GPIO_Px_CTRL(gpioport) = strength;
-}
-
-/** @} */
-
-/** @} */
-
-#endif
diff --git a/include/libopencm3/efm32/tinygecko/irq.h b/include/libopencm3/efm32/tinygecko/irq.h
deleted file mode 100644
index 1b0a484..0000000
--- a/include/libopencm3/efm32/tinygecko/irq.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * This file is part of the libopencm3 project.
- *
- * Copyright (C) 2012 chrysn <chrysn@fsfe.org>
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library. If not, see <http://www.gnu.org/licenses/>.
- */
-
-/** @file
- *
- * Definitions of interrupt names on EFM32 Tiny Gecko systems
- *
- * The names and numbers are taken from d0034_efm32tg_reference_manual.pdf table 4.1.
- */
-
-#ifndef LIBOPENCM3_EFM32_TINYGECKO_VECTOR_H
-#define LIBOPENCM3_EFM32_TINYGECKO_VECTOR_H
-
-#define IRQ_DMA 0
-#define IRQ_GPIO_EVEN 1
-#define IRQ_TIMER0 2
-#define IRQ_USART0_RX 3
-#define IRQ_USART0_TX 4
-#define IRQ_ACMP01 5
-#define IRQ_ADC0 6
-#define IRQ_DAC0 7
-#define IRQ_I2C0 8
-#define IRQ_GPIO_ODD 9
-#define IRQ_TIMER1 10
-#define IRQ_USART1_RX 11
-#define IRQ_USART1_TX 12
-#define IRQ_LESENSE 13
-#define IRQ_LEUART0 14
-#define IRQ_LETIMER0 15
-#define IRQ_PCNT0 16
-#define IRQ_RTC 17
-#define IRQ_CMU 18
-#define IRQ_VCMP 19
-#define IRQ_LCD 20
-#define IRQ_MSC 21
-#define IRQ_AES 22
-#define IRQ_COUNT 23 /**< See also d0002_efm32_cortex-m3_reference_manual.pdf's table 1.1's "number of interrupts" line, which shows that there are really no more interrupts and it is sufficient to allocate only 23 slots. */
-
-#endif
diff --git a/include/libopencm3/efm32/tinygecko/lcd.convenienceheaders b/include/libopencm3/efm32/tinygecko/lcd.convenienceheaders
deleted file mode 100644
index e69de29..0000000
--- a/include/libopencm3/efm32/tinygecko/lcd.convenienceheaders
+++ /dev/null
diff --git a/include/libopencm3/efm32/tinygecko/lcd.h b/include/libopencm3/efm32/tinygecko/lcd.h
deleted file mode 100644
index d46ef24..0000000
--- a/include/libopencm3/efm32/tinygecko/lcd.h
+++ /dev/null
@@ -1,295 +0,0 @@
-/*
- * This file is part of the libopencm3 project.
- *
- * Copyright (C) 2012 chrysn <chrysn@fsfe.org>
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library. If not, see <http://www.gnu.org/licenses/>.
- */
-
-/** @file
- * @see EFM32TG_LCD
- */
-
-/** Definitions for the LCD subsystem (Liquid Crystal Display driver).
- *
- * This corresponds to the description in d0034_efm32tg_reference_manual.pdf
- * section 29.
- *
- * @ingroup EFM32TG
- * @defgroup EFM32TG_LCD LCD (Liquid Crystal Display driver)
- * @{
- */
-
-#ifndef LIBOPENCM3_EFM32_TINYGECKO_LCD_H
-#define LIBOPENCM3_EFM32_TINYGECKO_LCD_H
-
-#include <libopencm3/cm3/common.h>
-#include <libopencm3/efm32/memorymap.h>
-
-/** Register definitions and register value definitions for the LCD subsystem
- *
- * @defgroup EFM32TG_LCD_regsandvals LCD registers and values
- * @{
- */
-
-/** These definitions reflect d0034_efm32tg_reference_manual.pdf section 29.4
- *
- * @defgroup EFM32TG_LCD_registers LCD registers
- * @{
- */
-
-#define LCD_CTRL MMIO32(LCD_BASE + 0x000) /**< @see EFM32TG_LCD_CTRL_bits */
-#define LCD_DISPCTRL MMIO32(LCD_BASE + 0x004) /**< @see EFM32TG_LCD_DISPCTRL_bits */
-#define LCD_SEGEN MMIO32(LCD_BASE + 0x008)
-#define LCD_BACTRL MMIO32(LCD_BASE + 0x00c) /**< @see EFM32TG_LCD_BACTRL_bits */
-#define LCD_STATUS MMIO32(LCD_BASE + 0x010) /**< @see EFM32TG_LCD_STATUS_bits */
-#define LCD_AREGA MMIO32(LCD_BASE + 0x014)
-#define LCD_AREGB MMIO32(LCD_BASE + 0x018)
-#define LCD_IF MMIO32(LCD_BASE + 0x01c) /**< @see EFM32TG_LCD_I_bits */
-#define LCD_IFS MMIO32(LCD_BASE + 0x020) /**< @see EFM32TG_LCD_I_bits */
-#define LCD_IFC MMIO32(LCD_BASE + 0x024) /**< @see EFM32TG_LCD_I_bits */
-#define LCD_IEN MMIO32(LCD_BASE + 0x028) /**< @see EFM32TG_LCD_I_bits */
-#define LCD_SEGD0L MMIO32(LCD_BASE + 0x040) /**< @see EFM32TG_LCD_SEG_bits */
-#define LCD_SEGD1L MMIO32(LCD_BASE + 0x044) /**< @see EFM32TG_LCD_SEG_bits */
-#define LCD_SEGD2L MMIO32(LCD_BASE + 0x048) /**< @see EFM32TG_LCD_SEG_bits */
-#define LCD_SEGD3L MMIO32(LCD_BASE + 0x04c) /**< @see EFM32TG_LCD_SEG_bits */
-#define LCD_FREEZE MMIO32(LCD_BASE + 0x060) /**< @see EFM32TG_LCD_FREEZE_bits */
-#define LCD_SYNCBUSY MMIO32(LCD_BASE + 0x064) /**< @see EFM32TG_LCD_SYNCBUSY_bits */
-#define LCD_SEGD4L MMIO32(LCD_BASE + 0x0cc) /**< @see EFM32TG_LCD_SEG_bits */
-#define LCD_SEGD5L MMIO32(LCD_BASE + 0x0d0) /**< @see EFM32TG_LCD_SEG_bits */
-#define LCD_SEGD6L MMIO32(LCD_BASE + 0x0d4) /**< @see EFM32TG_LCD_SEG_bits */
-#define LCD_SEGD7L MMIO32(LCD_BASE + 0x0d8) /**< @see EFM32TG_LCD_SEG_bits */
-
-/** @} */
-
-/** Bit states for the LCD_CTRL register
- *
- * See d0034_efm32tg_reference_manual.pdf section 29.5.1 for definitions.
- *
- * @defgroup EFM32TG_LCD_CTRL_bits LCD CTRL bits
- * @{
- */
-
-#define LCD_CTRL_DSC (1<<23)
-#define LCD_CTRL_UDCTRL_REGULAR (0<<1)
-#define LCD_CTRL_UDCTRL_FCEVENT (1<<1)
-#define LCD_CTRL_UDCTRL_FRAMESTART (2<<1)
-#define LCD_CTRL_UDCTRL_MASK (0x3<<1)
-#define LCD_CTRL_EN (1<<0)
-
-/** @} */
-
-/** Bit states for the LCD_DISPCTRL register
- *
- * See d0034_efm32tg_reference_manual.pdf section 29.5.2 for definitions.
- *
- * @defgroup EFM32TG_LCD_DISPCTRL_bits LCD DISPCTRL bits
- * @{
- */
-
-#define LCD_DISPCTRL_VBLEV_LEVEL0 (0<<18)
-#define LCD_DISPCTRL_VBLEV_LEVEL1 (1<<18)
-#define LCD_DISPCTRL_VBLEV_LEVEL2 (2<<18)
-#define LCD_DISPCTRL_VBLEV_LEVEL3 (3<<18)
-#define LCD_DISPCTRL_VBLEV_LEVEL4 (4<<18)
-#define LCD_DISPCTRL_VBLEV_LEVEL5 (5<<18)
-#define LCD_DISPCTRL_VBLEV_LEVEL6 (6<<18)
-#define LCD_DISPCTRL_VBLEV_LEVEL7 (7<<18)
-#define LCD_DISPCTRL_VBLEV_MASK (0x7<<18)
-#define LCD_DISPCTRL_VLCDSEL_VDD (0<<16)
-#define LCD_DISPCTRL_VLCDSEL_VEXTBOOST (1<<16)
-#define LCD_DISPCTRL_VLCDSEL_MASK (0x1<<16)
-#define LCD_DISPCTRL_CONCONF_VLCD (0<<15)
-#define LCD_DISPCTRL_CONCONF_GND (1<<15)
-#define LCD_DISPCTRL_CONCONF_MASK (0x1<<15)
-/** By this parameter, the voltage V_LCD_OUT is interpolated linearly from
- * 0.5V_LCD to V_LCD.
- */
-#define LCD_DISPCTRL_CONLEV_MIN (0<<8)
-#define LCD_DISPCTRL_CONLEV_MAX (31<<8)
-#define LCD_DISPCTRL_CONLEV_MASK (0x1f<<8)
-#define LCD_DISPCTRL_WAVE_LOWPOWER (0<<4)
-#define LCD_DISPCTRL_WAVE_NORMAL (1<<4)
-#define LCD_DISPCTRL_WAVE_MASK (0x1<<4)
-#define LCD_DISPCTRL_BIAS_STATIC (0<<2)
-#define LCD_DISPCTRL_BIAS_ONEHALF (1<<2)
-#define LCD_DISPCTRL_BIAS_ONETHIRD (2<<2)
-#define LCD_DISPCTRL_BIAS_ONEFOURTH (3<<2)
-#define LCD_DISPCTRL_BIAS_MASK (0x3<<2)
-/** These definitions munge the MUX and the MUXE fields, as they are described
- * in the documentation only together too.
- */
-#define LCD_DISPCTRL_MUX_STATIC 0x00000000
-#define LCD_DISPCTRL_MUX_DUPLEX 0x00000001
-#define LCD_DISPCTRL_MUX_TRIPLEX 0x00000002
-#define LCD_DISPCTRL_MUX_QUADRUPLEX 0x00000003
-#define LCD_DISPCTRL_MUX_SEXTAPLEX 0x00400001
-#define LCD_DISPCTRL_MUX_OCTAPLEX 0x00400003
-#define LCD_DISPCTRL_MUX_MASK 0x00400003
-
-/** @} */
-
-/** Bit states for the LCD_BACTRL register
- *
- * See d0034_efm32tg_reference_manual.pdf section 29.5.4 for definitions.
- *
- * @defgroup EFM32TG_LCD_BACTRL_bits LCD BACTRL bits
- * @{
- */
-
-#define LCD_BACTRL_FCTOP_MASK (0x3f<<18)
-#define LCD_BACTRL_FCPRESC_DIV1 (0<<16)
-#define LCD_BACTRL_FCPRESC_DIV2 (1<<16)
-#define LCD_BACTRL_FCPRESC_DIV4 (2<<16)
-#define LCD_BACTRL_FCPRESC_DIV8 (3<<16)
-#define LCD_BACTRL_FCPRESC_MASK (0x3<<16)
-#define LCD_BACTRL_FCEN (1<<8)
-#define LCD_BACTRL_ALGOSEL_AND (0<<7)
-#define LCD_BACTRL_ALGOSEL_OR (1<<7)
-#define LCD_BACTRL_ALGOSEL_MASK (0x1<<7)
-#define LCD_BACTRL_AREGBSC_NOSHIFT (0<<5)
-#define LCD_BACTRL_AREGBSC_SHIFTLEFT (1<<5)
-#define LCD_BACTRL_AREGBSC_SHIFTRIGHT (2<<5)
-#define LCD_BACTRL_AREGBSC_MASK (0x3<<5)
-#define LCD_BACTRL_AREGASC_NOSHIFT (0<<3)
-#define LCD_BACTRL_AREGASC_SHIFTLEFT (1<<3)
-#define LCD_BACTRL_AREGASC_SHIFTRIGHT (2<<3)
-#define LCD_BACTRL_AREGASC_MASK (0x3<<3)
-#define LCD_BACTRL_AEN (1<<2)
-#define LCD_BACTRL_BLANK (1<<1)
-#define LCD_BACTRL_BLINKEN (1<<0)
-
-/** @} */
-
-/** Bit states for the LCD_STATUS register
- *
- * See d0034_efm32tg_reference_manual.pdf section 29.5.5 for definitions.
- *
- * @defgroup EFM32TG_LCD_STATUS_bits LCD STATUS bits
- * @{
- */
-
-#define LCD_STATUS_BLINK (1<<8)
-#define LCD_STATUS_ASTATE_MASK (0xf<<0)
-
-/** @} */
-
-/** Bit states for the LCD_FREEZE register
- *
- * See d0034_efm32tg_reference_manual.pdf section 29.5.16 for definitions.
- *
- * @defgroup EFM32TG_LCD_FREEZE_bits LCD FREEZE bits
- * @{
- */
-
-#define LCD_FREEZE_REGFREEZE_UPDATE (0<<0)
-#define LCD_FREEZE_REGFREEZE_FREEZE (1<<0)
-#define LCD_FREEZE_REGFREEZE_MASK (0x1<<0)
-
-/** @} */
-
-/** Bit states for the LCD_SYNCBUSY register
- *
- * See d0034_efm32tg_reference_manual.pdf section 29.5.17 for definitions.
- *
- * @defgroup EFM32TG_LCD_SYNCBUSY_bits LCD SYNCBUSY bits
- * @{
- */
-
-#define LCD_SYNCBUSY_SEGD7L (1<<19)
-#define LCD_SYNCBUSY_SEGD6L (1<<18)
-#define LCD_SYNCBUSY_SEGD5L (1<<17)
-#define LCD_SYNCBUSY_SEGD4L (1<<16)
-#define LCD_SYNCBUSY_SEGD3L (1<<7)
-#define LCD_SYNCBUSY_SEGD2L (1<<6)
-#define LCD_SYNCBUSY_SEGD1L (1<<5)
-#define LCD_SYNCBUSY_SEGD0L (1<<4)
-#define LCD_SYNCBUSY_AREGB (1<<3)
-#define LCD_SYNCBUSY_AREGA (1<<2)
-#define LCD_SYNCBUSY_BACTRL (1<<1)
-#define LCD_SYNCBUSY_CTRL (1<<0)
-
-/** @} */
-
-/** Bit states for the LCD "I" group of registers (IF, IFS, IFC, IEN)
- *
- * These registers use this:
- *
- * <ul>
- *
- * <li>The LCD_IF register; see d0034_efm32tg_reference_manual.pdf section
- * 29.5.8 for definitions.</li>
- *
- * <li>The LCD_IFS register; see d0034_efm32tg_reference_manual.pdf section
- * 29.5.9 for definitions.</li>
- *
- * <li>The LCD_IFC register; see d0034_efm32tg_reference_manual.pdf section
- * 29.5.10 for definitions.</li>
- *
- * <li>The LCD_IEN register; see d0034_efm32tg_reference_manual.pdf section
- * 29.5.11 for definitions.</li>
- *
- * </ul>
- *
- * @defgroup EFM32TG_LCD_I_bits LCD I bits group
- * @{
- */
-
-#define LCD_I_FC (1<<0)
-
-/** @} */
-
-/** Bit states for the LCD "SEG" group of registers (SEGD0L, SEGD1L, SEGD2L,
- * SEGD3L, SEGD4L, SEGD5L, SEGD6L, SEGD7L)
- *
- * These values are used by the SEGDxL registers, as defined in
- * d0034_efm32tg_reference_manual.pdf sections 29.5.12 to .15 and .18 to .21.
- *
- * @defgroup EFM32TG_LCD_SEG_bits LCD SEG bits group
- * @{
- */
-
-#define LCD_SEG_23 (1<<23)
-#define LCD_SEG_22 (1<<22)
-#define LCD_SEG_21 (1<<21)
-#define LCD_SEG_20 (1<<20)
-#define LCD_SEG_19 (1<<19)
-#define LCD_SEG_18 (1<<18)
-#define LCD_SEG_17 (1<<17)
-#define LCD_SEG_16 (1<<16)
-#define LCD_SEG_15 (1<<15)
-#define LCD_SEG_14 (1<<14)
-#define LCD_SEG_13 (1<<13)
-#define LCD_SEG_12 (1<<12)
-#define LCD_SEG_11 (1<<11)
-#define LCD_SEG_10 (1<<10)
-#define LCD_SEG_9 (1<<9)
-#define LCD_SEG_8 (1<<8)
-#define LCD_SEG_7 (1<<7)
-#define LCD_SEG_6 (1<<6)
-#define LCD_SEG_5 (1<<5)
-#define LCD_SEG_4 (1<<4)
-#define LCD_SEG_3 (1<<3)
-#define LCD_SEG_2 (1<<2)
-#define LCD_SEG_1 (1<<1)
-#define LCD_SEG_0 (1<<0)
-
-/** @} */
-
-/** @} */
-
-
-/** @} */
-
-#endif
diff --git a/include/libopencm3/efm32/tinygecko/lcd.yaml b/include/libopencm3/efm32/tinygecko/lcd.yaml
deleted file mode 100644
index 0e003bd..0000000
--- a/include/libopencm3/efm32/tinygecko/lcd.yaml
+++ /dev/null
@@ -1,241 +0,0 @@
-copyright: "2012 chrysn <chrysn@fsfe.org>"
-license: lgpl-3+
-ingroup: EFM32TG
-shortdocname: EFM32TG_LCD
-shortname: LCD
-longname: Liquid Crystal Display driver
-baseref: d0034_efm32tg_reference_manual.pdf section 29
-registers_baserefext: ".4"
-templateregs:
- - name: I
- comment: Bits for the various LCD interrupt registers
- fields:
- - {name: FC, shift: 0}
- - name: SEG
- comment: Bits for the individual SEG pins
- override_backref: These values are used by the SEGDxL registers, as defined in d0034_efm32tg_reference_manual.pdf sections 29.5.12 to .15 and .18 to .21.
- fields:
- - {name: 23, shift: 23}
- - {name: 22, shift: 22}
- - {name: 21, shift: 21}
- - {name: 20, shift: 20}
- - {name: 19, shift: 19}
- - {name: 18, shift: 18}
- - {name: 17, shift: 17}
- - {name: 16, shift: 16}
- - {name: 15, shift: 15}
- - {name: 14, shift: 14}
- - {name: 13, shift: 13}
- - {name: 12, shift: 12}
- - {name: 11, shift: 11}
- - {name: 10, shift: 10}
- - {name: 9, shift: 9}
- - {name: 8, shift: 8}
- - {name: 7, shift: 7}
- - {name: 6, shift: 6}
- - {name: 5, shift: 5}
- - {name: 4, shift: 4}
- - {name: 3, shift: 3}
- - {name: 2, shift: 2}
- - {name: 1, shift: 1}
- - {name: 0, shift: 0}
-registers:
- - name: CTRL
- offset: 0x000
- definition_baserefext: .5.1
- fields:
- - name: DSC
- shift: 23
- - name: UDCTRL
- shift: 1
- length: 2
- values:
- - {name: REGULAR, value: 0}
- - {name: FCEVENT, value: 1}
- - {name: FRAMESTART, value: 2}
- - name: EN
- shift: 0
- - name: DISPCTRL
- offset: 0x004
- definition_baserefext: .5.2
- fields:
- # MUXE left out and defined manually at the end
- - name: VBLEV
- shift: 18
- length: 3
- values:
- - {name: LEVEL0, value: 0}
- - {name: LEVEL1, value: 1}
- - {name: LEVEL2, value: 2}
- - {name: LEVEL3, value: 3}
- - {name: LEVEL4, value: 4}
- - {name: LEVEL5, value: 5}
- - {name: LEVEL6, value: 6}
- - {name: LEVEL7, value: 7}
- - name: VLCDSEL
- shift: 16
- values:
- - {name: VDD, value: 0}
- - {name: VEXTBOOST, value: 1}
- - name: CONCONF
- shift: 15
- values:
- - {value: 0, name: VLCD}
- - {value: 1, name: GND}
- - name: CONLEV
- shift: 8
- length: 5
- type: uint
- doc: "By this parameter, the voltage V_LCD_OUT is interpolated linearly from 0.5V_LCD to V_LCD."
- values:
- - {value: 0, name: MIN}
- - {value: 31, name: MAX}
- - name: WAVE
- shift: 4
- values:
- - {value: 0, name: LOWPOWER}
- - {value: 1, name: NORMAL}
- - name: BIAS
- shift: 2
- length: 2
- values:
- - {value: 0, name: STATIC}
- - {value: 1, name: ONEHALF}
- - {value: 2, name: ONETHIRD}
- - {value: 3, name: ONEFOURTH}
- - name: MUX
- mask: "0x00400003"
- values:
- - {value: "0x00000000", name: STATIC}
- - {value: "0x00000001", name: DUPLEX}
- - {value: "0x00000002", name: TRIPLEX}
- - {value: "0x00000003", name: QUADRUPLEX}
- - {value: "0x00400001", name: SEXTAPLEX}
- - {value: "0x00400003", name: OCTAPLEX}
- doc: These definitions munge the MUX and the MUXE fields, as they are described in the documentation only together too.
- - name: SEGEN
- offset: 0x008
- definition_baserefext: .5.3
- # FIXME how do we reperesent this best?
- - name: BACTRL
- offset: 0x00c
- definition_baserefext: .5.4
- fields:
- - name: FCTOP
- shift: 18
- length: 6
- type: uint
- - name: FCPRESC
- shift: 16
- length: 2
- values:
- - {value: 0, name: DIV1}
- - {value: 1, name: DIV2}
- - {value: 2, name: DIV4}
- - {value: 3, name: DIV8}
- - name: FCEN
- shift: 8
- - name: ALGOSEL
- shift: 7
- values:
- - {value: 0, name: AND}
- - {value: 1, name: OR}
- - name: AREGBSC
- shift: 5
- length: 2
- values: &BACTRL_AREGBSC
- - {value: 0, name: NOSHIFT}
- - {value: 1, name: SHIFTLEFT}
- - {value: 2, name: SHIFTRIGHT}
- - name: AREGASC
- shift: 3
- length: 2
- values: *BACTRL_AREGBSC
- - name: AEN
- shift: 2
- - name: BLANK
- shift: 1
- - name: BLINKEN
- shift: 0
- - name: STATUS
- offset: 0x010
- definition_baserefext: .5.5
- fields:
- - name: BLINK
- shift: 8
- - name: ASTATE
- shift: 0
- length: 4
- type: uint
- - name: AREGA
- offset: 0x014
- # FIXME: how do we represent this in the header?
- - name: AREGB
- offset: 0x018
- # FIXME: how do we represent this in the header?
- - name: IF
- offset: 0x01c
- definition_baserefext: .5.8
- fields: I
- - name: IFS
- offset: 0x020
- definition_baserefext: .5.9
- fields: I
- - name: IFC
- offset: 0x024
- definition_baserefext: .5.10
- fields: I
- - name: IEN
- offset: 0x028
- definition_baserefext: .5.11
- fields: I
- - name: SEGD0L
- offset: 0x040
- fields: SEG
- - name: SEGD1L
- offset: 0x044
- fields: SEG
- - name: SEGD2L
- offset: 0x048
- fields: SEG
- - name: SEGD3L
- offset: 0x04c
- fields: SEG
- - name: FREEZE
- offset: 0x060
- definition_baserefext: .5.16
- fields:
- - name: REGFREEZE
- shift: 0
- values:
- - {value: 0, name: UPDATE}
- - {value: 1, name: FREEZE}
- # FIXME: this seems to be a typical FREEZE register
- - name: SYNCBUSY
- offset: 0x064
- definition_baserefext: .5.17
- fields:
- - {name: SEGD7L, shift: 19}
- - {name: SEGD6L, shift: 18}
- - {name: SEGD5L, shift: 17}
- - {name: SEGD4L, shift: 16}
- - {name: SEGD3L, shift: 7}
- - {name: SEGD2L, shift: 6}
- - {name: SEGD1L, shift: 5}
- - {name: SEGD0L, shift: 4}
- - {name: AREGB, shift: 3}
- - {name: AREGA, shift: 2}
- - {name: BACTRL, shift: 1}
- - {name: CTRL, shift: 0}
- - name: SEGD4L
- offset: 0x0CC
- fields: SEG
- - name: SEGD5L
- offset: 0x0D0
- fields: SEG
- - name: SEGD6L
- offset: 0x0D4
- fields: SEG
- - name: SEGD7L
- offset: 0x0D8
- fields: SEG