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authorGareth McMullin2011-02-17 21:38:38 +1300
committerGareth McMullin2011-02-17 21:38:38 +1300
commitf0a1282d429023958e750a7821c577c132365485 (patch)
tree769f7dca52e4ae88bbad8958db7b9487ebe094d2 /include/libopencm3/cm3
parente64a9d2bf9751e505d344eb5024da4772c3f4e50 (diff)
Added ITM and TPIU register definitions.
Diffstat (limited to 'include/libopencm3/cm3')
-rw-r--r--include/libopencm3/cm3/itm.h74
-rw-r--r--include/libopencm3/cm3/memorymap.h1
-rw-r--r--include/libopencm3/cm3/scs.h27
-rw-r--r--include/libopencm3/cm3/tpiu.h98
4 files changed, 190 insertions, 10 deletions
diff --git a/include/libopencm3/cm3/itm.h b/include/libopencm3/cm3/itm.h
new file mode 100644
index 0000000..232c2a7
--- /dev/null
+++ b/include/libopencm3/cm3/itm.h
@@ -0,0 +1,74 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_CM3_ITM_H
+#define LIBOPENCM3_CM3_ITM_H
+
+/* Cortex-M3 Instrumentation Trace Macrocell (ITM) */
+
+/* --- ITM registers ------------------------------------------------------- */
+
+/* Stimulus Port x (ITM_STIM[x]) */
+#define ITM_STIM ((volatile u32*)(ITM_BASE))
+
+/* Trace Enable ports (ITM_TER[x]) */
+#define ITM_TER ((volatile u32*)(ITM_BASE + 0xE00))
+
+/* Trace Privilege (ITM_TPR) */
+#define ITM_TPR MMIO32(ITM_BASE + 0xE40)
+
+/* Trace Control (ITM_TCR) */
+#define ITM_TCR MMIO32(ITM_BASE + 0xE80)
+
+/* TODO: PID, CID */
+
+/* --- ITM_STIM values ----------------------------------------------------- */
+/* Bits 31:0 - Write to port FIFO for forwarding as software event packet */
+/* Bits 31:1 - RAZ */
+#define ITM_STIM_FIFOREADY (1 << 0)
+
+/* --- ITM_TER values ------------------------------------------------------ */
+/* Bits 31:0 - Stimulus port #N is enabled with STIMENA[N] is set */
+
+/* --- ITM_TPR values ------------------------------------------------------ */
+/*
+ * Bits 31:0 - Bit [N] of PRIVMASK controls stimulus ports 8N to 8N+7
+ * 0: User access allowed to stimulus ports
+ * 1: Privileged access only to stimulus ports
+ */
+
+/* --- ITM_TCR values ------------------------------------------------------ */
+/* Bits 31:24 - Reserved */
+#define ITM_TCR_BUSY (1 << 23)
+#define ITM_TCR_TRACE_BUS_ID_MASK (0x3f << 16)
+/* Bits 15:10 - Reserved */
+#define ITM_TCR_TSPRESCALE_NONE (0 << 8)
+#define ITM_TCR_TSPRESCALE_DIV4 (1 << 8)
+#define ITM_TCR_TSPRESCALE_DIV16 (2 << 8)
+#define ITM_TCR_TSPRESCALE_DIV64 (3 << 8)
+#define ITM_TCR_TSPRESCALE_MASK (3 << 8)
+/* Bits 7:5 - Reserved */
+#define ITM_TCR_SWOENA (1 << 4)
+#define ITM_TCR_TXENA (1 << 3)
+#define ITM_TCR_SYNCENA (1 << 2)
+#define ITM_TCR_TSENA (1 << 1)
+#define ITM_TCR_ITMENA (1 << 0)
+
+
+#endif
diff --git a/include/libopencm3/cm3/memorymap.h b/include/libopencm3/cm3/memorymap.h
index b1b5172..13c3a8f 100644
--- a/include/libopencm3/cm3/memorymap.h
+++ b/include/libopencm3/cm3/memorymap.h
@@ -30,6 +30,7 @@
/* PPBI_BASE + 0x3000 (0xE000 3000 - 0xE000 DFFF): Reserved */
#define SCS_BASE (PPBI_BASE + 0xE000)
/* PPBI_BASE + 0xF000 (0xE000 F000 - 0xE003 FFFF): Reserved */
+#define TPIU_BASE (PPBI_BASE + 0x40000)
/* --- ITM: Instrumentation Trace Macrocell --- */
/* TODO */
diff --git a/include/libopencm3/cm3/scs.h b/include/libopencm3/cm3/scs.h
index 5646a18..d4dbca4 100644
--- a/include/libopencm3/cm3/scs.h
+++ b/include/libopencm3/cm3/scs.h
@@ -46,15 +46,22 @@
#define SCS_DCRSR_REGSEL_PSP 0x00000012
/* Debug Exception and Monitor Control Register (DEMCR) */
-#define SCS_DEMCR_VC_CORERESET 0x00000001
-#define SCS_DEMCR_VC_MMERR 0x00000010
-#define SCS_DEMCR_VC_NOCPERR 0x00000020
-#define SCS_DEMCR_VC_CHKERR 0x00000040
-#define SCS_DEMCR_VC_STATERR 0x00000080
-#define SCS_DEMCR_VC_BUSERR 0x00000100
-#define SCS_DEMCR_VC_INTERR 0x00000200
-#define SCS_DEMCR_VC_HARDERR 0x00000400
-#define SCS_DEMCR_VC_MON_EN 0x00010000
-#define SCS_DEMCR_VC_MON_PEND 0x00020000
+/* Bits 31:25 - Reserved */
+#define SCS_DEMCR_TRCENA (1 << 24)
+/* Bits 23:20 - Reserved */
+#define SCS_DEMCR_MON_REQ (1 << 19)
+#define SCS_DEMCR_MON_STEP (1 << 18)
+#define SCS_DEMCR_VC_MON_PEND (1 << 17)
+#define SCS_DEMCR_VC_MON_EN (1 << 16)
+/* Bits 15:11 - Reserved */
+#define SCS_DEMCR_VC_HARDERR (1 << 10)
+#define SCS_DEMCR_VC_INTERR (1 << 9)
+#define SCS_DEMCR_VC_BUSERR (1 << 8)
+#define SCS_DEMCR_VC_STATERR (1 << 7)
+#define SCS_DEMCR_VC_CHKERR (1 << 6)
+#define SCS_DEMCR_VC_NOCPERR (1 << 5)
+#define SCS_DEMCR_VC_MMERR (1 << 4)
+/* Bits 3:1 - Reserved */
+#define SCS_DEMCR_VC_CORERESET (1 << 0)
#endif
diff --git a/include/libopencm3/cm3/tpiu.h b/include/libopencm3/cm3/tpiu.h
new file mode 100644
index 0000000..5dfdcbd
--- /dev/null
+++ b/include/libopencm3/cm3/tpiu.h
@@ -0,0 +1,98 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_CM3_TPIU_H
+#define LIBOPENCM3_CM3_TPIU_H
+
+/* Cortex-M3 Trace Port Interface Unit (TPIU) */
+
+/* --- TPIU registers ------------------------------------------------------ */
+
+/* Supported Synchronous Port Size (TPIU_SSPSR) */
+#define TPIU_SSPSR MMIO32(TPIU_BASE + 0x000)
+
+/* Current Synchronous Port Size (TPIU_CSPSR) */
+#define TPIU_CSPSR MMIO32(TPIU_BASE + 0x004)
+
+/* Asynchronous Clock Prescaler (TPIU_ACPR) */
+#define TPIU_ACPR MMIO32(TPIU_BASE + 0x010)
+
+/* Selected Pin Protocol (TPIU_SPPR) */
+#define TPIU_SPPR MMIO32(TPIU_BASE + 0x0F0)
+
+/* Formatter and Flush Status Register (TPIU_FFSR) */
+#define TPIU_FFSR MMIO32(TPIU_BASE + 0x300)
+
+/* Formatter and Flush Control Register (TPIU_FFCR) */
+#define TPIU_FFCR MMIO32(TPIU_BASE + 0x304)
+
+/* (TPIU_DEVID) */
+#define TPIU_DEVID MMIO32(TPIU_BASE + 0xFC8)
+
+/* TODO: PID, CID */
+
+/* --- TPIU_SSPSR values --------------------------------------------------- */
+/*
+ * bit[N] == 0, trace port width of (N+1) not supported
+ * bit[N] == 1, trace port width of (N+1) supported
+ */
+#define TPIU_SSPSR_BYTE (1 << 0)
+#define TPIU_SSPSR_HALFWORD (1 << 1)
+#define TPIU_SSPSR_WORD (1 << 3)
+
+/* --- TPIU_SSPSR values --------------------------------------------------- */
+/* Same format as TPIU_SSPSR, except only one is set */
+#define TPIU_CSPSR_BYTE (1 << 0)
+#define TPIU_CSPSR_HALFWORD (1 << 1)
+#define TPIU_CSPSR_WORD (1 << 3)
+
+/* --- TPIU_ACPR values ---------------------------------------------------- */
+/* Bits 31:16 - Reserved */
+/* Bits 15:0 - SWO output clock = Asynchronous_Reference_Clock/(value +1) */
+
+/* --- TPIU_SPPR values ---------------------------------------------------- */
+/* Bits 31:2 - Reserved */
+#define TPIU_SPPR_SYNC (0x0)
+#define TPIU_SPPR_ASYNC_MANCHESTER (0x1)
+#define TPIU_SPPR_ASYNC_NRZ (0x2)
+
+/* --- TPIU_FFSR values ---------------------------------------------------- */
+/* Bits 31:4 - Reserved */
+#define TPIU_FFSR_FTNONSTOP (1 << 3)
+#define TPIU_FFSR_TCPRESENT (1 << 2)
+#define TPIU_FFSR_FTSTOPPED (1 << 1)
+#define TPIU_FFSR_FLINPROG (1 << 0)
+
+/* --- TPIU_FFCR values ---------------------------------------------------- */
+/* Bits 31:9 - Reserved */
+#define TPIU_FFCR_TRIGIN (1 << 8)
+/* Bits 7:2 - Reserved */
+#define TPIU_FFCR_ENFCONT (1 << 1)
+/* Bit 0 - Reserved */
+
+/* --- TPIU_DEVID values ---------------------------------------------------- */
+/* Bits 31:16 - Reserved */
+/* Bits 15:12 - Implementation defined */
+#define TPUI_DEVID_NRZ_SUPPORTED (1 << 11)
+#define TPUI_DEVID_MANCHESTER_SUPPORTED (1 << 10)
+/* Bit 9 - RAZ, indicated that trace data and clock are supported */
+#define TPUI_DEVID_FIFO_SIZE_MASK (7 << 6)
+/* Bits 5:0 - Implementation defined */
+
+#endif