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authorGareth McMullin2011-02-17 21:38:38 +1300
committerGareth McMullin2011-02-17 21:38:38 +1300
commitf0a1282d429023958e750a7821c577c132365485 (patch)
tree769f7dca52e4ae88bbad8958db7b9487ebe094d2 /include/libopencm3/cm3/scs.h
parente64a9d2bf9751e505d344eb5024da4772c3f4e50 (diff)
Added ITM and TPIU register definitions.
Diffstat (limited to 'include/libopencm3/cm3/scs.h')
-rw-r--r--include/libopencm3/cm3/scs.h27
1 files changed, 17 insertions, 10 deletions
diff --git a/include/libopencm3/cm3/scs.h b/include/libopencm3/cm3/scs.h
index 5646a18..d4dbca4 100644
--- a/include/libopencm3/cm3/scs.h
+++ b/include/libopencm3/cm3/scs.h
@@ -46,15 +46,22 @@
#define SCS_DCRSR_REGSEL_PSP 0x00000012
/* Debug Exception and Monitor Control Register (DEMCR) */
-#define SCS_DEMCR_VC_CORERESET 0x00000001
-#define SCS_DEMCR_VC_MMERR 0x00000010
-#define SCS_DEMCR_VC_NOCPERR 0x00000020
-#define SCS_DEMCR_VC_CHKERR 0x00000040
-#define SCS_DEMCR_VC_STATERR 0x00000080
-#define SCS_DEMCR_VC_BUSERR 0x00000100
-#define SCS_DEMCR_VC_INTERR 0x00000200
-#define SCS_DEMCR_VC_HARDERR 0x00000400
-#define SCS_DEMCR_VC_MON_EN 0x00010000
-#define SCS_DEMCR_VC_MON_PEND 0x00020000
+/* Bits 31:25 - Reserved */
+#define SCS_DEMCR_TRCENA (1 << 24)
+/* Bits 23:20 - Reserved */
+#define SCS_DEMCR_MON_REQ (1 << 19)
+#define SCS_DEMCR_MON_STEP (1 << 18)
+#define SCS_DEMCR_VC_MON_PEND (1 << 17)
+#define SCS_DEMCR_VC_MON_EN (1 << 16)
+/* Bits 15:11 - Reserved */
+#define SCS_DEMCR_VC_HARDERR (1 << 10)
+#define SCS_DEMCR_VC_INTERR (1 << 9)
+#define SCS_DEMCR_VC_BUSERR (1 << 8)
+#define SCS_DEMCR_VC_STATERR (1 << 7)
+#define SCS_DEMCR_VC_CHKERR (1 << 6)
+#define SCS_DEMCR_VC_NOCPERR (1 << 5)
+#define SCS_DEMCR_VC_MMERR (1 << 4)
+/* Bits 3:1 - Reserved */
+#define SCS_DEMCR_VC_CORERESET (1 << 0)
#endif