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authorPiotr Esden-Tempski2011-01-28 15:11:52 -0800
committerPiotr Esden-Tempski2011-01-28 15:11:52 -0800
commita1bd228c87d1b73f6cfecf000eec0a8765a11b01 (patch)
tree22dbeb035df8b1d8709f061190bbcf15eac76d49 /examples/stm32/stm32-h103
parent5975750e5e22ffb047303a1e1e7700012e09e18c (diff)
Replaced OC mode selection with an enum, makes it simpler to use.
Diffstat (limited to 'examples/stm32/stm32-h103')
-rw-r--r--examples/stm32/stm32-h103/pwm_6step/pwm_6step.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/examples/stm32/stm32-h103/pwm_6step/pwm_6step.c b/examples/stm32/stm32-h103/pwm_6step/pwm_6step.c
index b35a4ba..d769e3a 100644
--- a/examples/stm32/stm32-h103/pwm_6step/pwm_6step.c
+++ b/examples/stm32/stm32-h103/pwm_6step/pwm_6step.c
@@ -104,7 +104,7 @@ void tim_setup(void)
timer_disable_oc_clear(TIM1, TIM_OC1);
timer_enable_oc_preload(TIM1, TIM_OC1);
timer_set_oc_slow_mode(TIM1, TIM_OC1);
- timer_set_oc_mode(TIM1, TIM_OC1, TIM_CCMR1_OC1M_PWM1);
+ timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_PWM1);
/* Configure OC1. */
timer_set_oc_polarity_high(TIM1, TIM_OC1);
@@ -131,7 +131,7 @@ void tim_setup(void)
timer_disable_oc_clear(TIM1, TIM_OC2);
timer_enable_oc_preload(TIM1, TIM_OC2);
timer_set_oc_slow_mode(TIM1, TIM_OC2);
- timer_set_oc_mode(TIM1, TIM_OC2, TIM_CCMR1_OC2M_PWM1);
+ timer_set_oc_mode(TIM1, TIM_OC2, TIM_OCM_PWM1);
/* Configure OC2. */
timer_set_oc_polarity_high(TIM1, TIM_OC2);
@@ -158,7 +158,7 @@ void tim_setup(void)
timer_disable_oc_clear(TIM1, TIM_OC3);
timer_enable_oc_preload(TIM1, TIM_OC3);
timer_set_oc_slow_mode(TIM1, TIM_OC3);
- timer_set_oc_mode(TIM1, TIM_OC3, TIM_CCMR2_OC3M_PWM1);
+ timer_set_oc_mode(TIM1, TIM_OC3, TIM_OCM_PWM1);
/* Configure OC3. */
timer_set_oc_polarity_high(TIM1, TIM_OC3);