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authorUwe Hermann2010-12-17 06:04:28 +0100
committerUwe Hermann2010-12-17 06:04:28 +0100
commiteebbd508fc0a8d570c12c1c89b5e33dc16de4c80 (patch)
treed2755daf7ee78620687017987287f8656c9fb7e4
parent9539f3bf06633a178e8f9eaebbcf350c21f90619 (diff)
TIM1 GPIO remapping + gpio_port_config_lock().
Thanks to Philip Court <philip@greenstage.co.nz> for the patch.
-rw-r--r--include/libopenstm32/gpio.h10
-rw-r--r--lib/gpio.c14
2 files changed, 24 insertions, 0 deletions
diff --git a/include/libopenstm32/gpio.h b/include/libopenstm32/gpio.h
index a96c999..8bf8d4b 100644
--- a/include/libopenstm32/gpio.h
+++ b/include/libopenstm32/gpio.h
@@ -103,6 +103,15 @@
#define GPIO_TIM1_CH2N GPIO14 /* PB14 */
#define GPIO_TIM1_CH3N GPIO15 /* PB15 */
+#define GPIO_TIM1_ETR_REMAP GPIO7 /* PE7 */
+#define GPIO_TIM1_CH1_REMAP GPIO9 /* PE9 */
+#define GPIO_TIM1_CH2_REMAP GPIO11 /* PE11 */
+#define GPIO_TIM1_CH3_REMAP GPIO13 /* PE13 */
+#define GPIO_TIM1_CH4_REMAP GPIO14 /* PE14 */
+#define GPIO_TIM1_BKIN_REMAP GPIO15 /* PE15 */
+#define GPIO_TIM1_CH1N_REMAP GPIO8 /* PE8 */
+#define GPIO_TIM1_CH2N_REMAP GPIO10 /* PE10 */
+#define GPIO_TIM1_CH3N_REMAP GPIO12 /* PE12 */
/* USART */
#define GPIO_USART3_TX GPIO10 /* PB10 */
#define GPIO_USART3_RX GPIO11 /* PB11 */
@@ -402,5 +411,6 @@ u16 gpio_get(u32 gpioport, u16 gpios);
void gpio_toggle(u32 gpioport, u16 gpios);
u16 gpio_port_read(u32 gpioport);
void gpio_port_write(u32 gpioport, u16 data);
+void gpio_port_config_lock(u32 gpioport, u16 gpios);
#endif
diff --git a/lib/gpio.c b/lib/gpio.c
index abf47cf..747977d 100644
--- a/lib/gpio.c
+++ b/lib/gpio.c
@@ -106,3 +106,17 @@ void gpio_port_write(u32 gpioport, u16 data)
{
GPIO_ODR(gpioport) = data;
}
+
+void gpio_port_config_lock(u32 gpioport, u16 gpios)
+{
+ u32 reg32;
+
+ /* Special "Lock Key Writing Sequence", see datasheet. */
+ GPIO_LCKR(gpioport) = GPIO_LCKK | gpios; /* Set LCKK. */
+ GPIO_LCKR(gpioport) = ~GPIO_LCKK & gpios; /* Clear LCKK. */
+ GPIO_LCKR(gpioport) = GPIO_LCKK | gpios; /* Set LCKK. */
+ reg32 = GPIO_LCKR(gpioport); /* Read LCKK. */
+ reg32 = GPIO_LCKR(gpioport); /* Read LCKK again. */
+
+ /* If (reg32 & GPIO_LCKK) is true, the lock is now active. */
+}