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authorKarl Palsson2013-02-06 11:41:10 +0000
committerKarl Palsson2013-02-06 11:43:20 +0000
commite4c0a50286cd7bdca76f7bc4dfa973668114e9ec (patch)
treeba676aa76aba2df46b7768ce6878fc866fe2fc35
parentc9276b7aa26a45290ee5081da093bcb372cc644c (diff)
[stm32-dma] Eliminate redundant write.
Clearing a single bit in DMA_CCR, then immediately writing a 0 over the entire register is completely redundant on the F1, F3 and L1 DMA peripherals. (Unlike the F2 & F4 DMA Peripheral, where this is required)
-rw-r--r--lib/stm32/common/dma_common_f13.c4
1 files changed, 1 insertions, 3 deletions
diff --git a/lib/stm32/common/dma_common_f13.c b/lib/stm32/common/dma_common_f13.c
index 0a708aa..35b9da6 100644
--- a/lib/stm32/common/dma_common_f13.c
+++ b/lib/stm32/common/dma_common_f13.c
@@ -55,9 +55,7 @@ The channel is disabled and configuration registers are cleared.
void dma_channel_reset(u32 dma, u8 channel)
{
- /* Disable channel. */
- DMA_CCR(dma, channel) &= ~DMA_CCR_EN;
- /* Reset config bits. */
+ /* Disable channel and reset config bits. */
DMA_CCR(dma, channel) = 0;
/* Reset data transfer number. */
DMA_CNDTR(dma, channel) = 0;