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authorUwe Hermann2010-01-22 01:48:02 +0100
committerUwe Hermann2010-01-22 01:48:02 +0100
commit1f9479e673430ecd346f5ab49510540817001246 (patch)
tree6967392adfe7462b504214928ae7950c20a52ee5
parent3e29876d98973f03ee19911b688076cd81463d70 (diff)
Add initial (unfinished, untested) RTC support.
-rw-r--r--include/libopenstm32.h1
-rw-r--r--include/libopenstm32/rtc.h124
-rw-r--r--lib/Makefile2
-rw-r--r--lib/rtc.c77
4 files changed, 203 insertions, 1 deletions
diff --git a/include/libopenstm32.h b/include/libopenstm32.h
index 059b6e2..73f35be 100644
--- a/include/libopenstm32.h
+++ b/include/libopenstm32.h
@@ -33,5 +33,6 @@
#include <libopenstm32/usb.h>
#include <libopenstm32/usb_desc.h>
#include <libopenstm32/nvic.h>
+#include <libopenstm32/rtc.h>
#endif
diff --git a/include/libopenstm32/rtc.h b/include/libopenstm32/rtc.h
new file mode 100644
index 0000000..076c8a2
--- /dev/null
+++ b/include/libopenstm32/rtc.h
@@ -0,0 +1,124 @@
+/*
+ * This file is part of the libopenstm32 project.
+ *
+ * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENSTM32_RTC_H
+#define LIBOPENSTM32_RTC_H
+
+#include <libopenstm32.h>
+
+/* --- RTC registers ------------------------------------------------------- */
+
+/* RTC control register high (RTC_CRH) */
+#define RTC_CRH MMIO32(RTC_BASE + 0x00)
+
+/* RTC control register low (RTC_CRL) */
+#define RTC_CRL MMIO32(RTC_BASE + 0x04)
+
+/* RTC prescaler load register (RTC_PRLH / RTC_PRLL) */
+#define RTC_PRLH MMIO32(RTC_BASE + 0x08)
+#define RTC_PRLL MMIO32(RTC_BASE + 0x0c)
+
+/* RTC prescaler divider register (RTC_DIVH / RTC_DIVL) */
+#define RTC_DIVH MMIO32(RTC_BASE + 0x10)
+#define RTC_DIVL MMIO32(RTC_BASE + 0x14)
+
+/* RTC counter register (RTC_CNTH / RTC_CNTL) */
+#define RTC_CNTH MMIO32(RTC_BASE + 0x18)
+#define RTC_CNTL MMIO32(RTC_BASE + 0x1c)
+
+/* RTC alarm register high (RTC_ALRH / RTC_ALRL) */
+#define RTC_ALRH MMIO32(RTC_BASE + 0x20)
+#define RTC_ALRL MMIO32(RTC_BASE + 0x24)
+
+/* --- RTC_CRH values -------------------------------------------------------*/
+
+/* Note: Bits [15:3] are reserved, and forced to 0 by hardware. */
+
+/* OWIE: Overflow interrupt enable */
+#define RTC_CRH_OWIE (1 << 2)
+
+/* ALRIE: Alarm interrupt enable */
+#define RTC_CRH_ALRIE (1 << 1)
+
+/* SECIE: Second interrupt enable */
+#define RTC_CRH_SECIE (1 << 0)
+
+/* --- RTC_CRL values -------------------------------------------------------*/
+
+/* Note: Bits [15:6] are reserved, and forced to 0 by hardware. */
+
+/* RTOFF: RTC operation OFF */
+#define RTC_CRL_RTOFF (1 << 5)
+
+/* CNF: Configuration flag */
+#define RTC_CRL_CNF (1 << 4)
+
+/* RSF: Registers synchronized flag */
+#define RTC_CRL_RSF (1 << 3)
+
+/* OWF: Overflow flag */
+#define RTC_CRL_OWF (1 << 2)
+
+/* ALRF: Alarm flag */
+#define RTC_CRL_ALRF (1 << 1)
+
+/* SECF: Second flag */
+#define RTC_CRL_SECF (1 << 0)
+
+/* --- RTC_PRLH values ------------------------------------------------------*/
+
+/* Note: Bits [15:4] are reserved, and forced to 0 by hardware. */
+
+/* TODO */
+
+/* --- RTC_PRLL values ------------------------------------------------------*/
+
+/* TODO */
+
+/* --- RTC_DIVH values ------------------------------------------------------*/
+
+/* Bits [15:4] are reserved. */
+
+/* TODO */
+
+/* --- RTC_DIVL values ------------------------------------------------------*/
+
+/* TODO */
+
+/* --- RTC_CNTH values ------------------------------------------------------*/
+
+/* TODO */
+
+/* --- RTC_CNTL values ------------------------------------------------------*/
+
+/* TODO */
+
+/* --- RTC_ALRH values ------------------------------------------------------*/
+
+/* TODO */
+
+/* --- RTC_ALRL values ------------------------------------------------------*/
+
+/* TODO */
+
+/* --- Function prototypes --------------------------------------------------*/
+
+/* TODO */
+
+#endif /* LIBOPENSTM32_RTC_H */
diff --git a/lib/Makefile b/lib/Makefile
index c183967..383fa93 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -27,7 +27,7 @@ CFLAGS = -Os -g -Wall -Wextra -I../include -fno-common \
-mcpu=cortex-m3 -mthumb -Wstrict-prototypes
# ARFLAGS = rcsv
ARFLAGS = rcs
-OBJS = rcc.o gpio.o usart.o adc.o spi.o flash.o nvic.o
+OBJS = rcc.o gpio.o usart.o adc.o spi.o flash.o nvic.o rtc.o
# Be silent per default, but 'make V=1' will show all compiler calls.
ifneq ($(V),1)
diff --git a/lib/rtc.c b/lib/rtc.c
new file mode 100644
index 0000000..9cad527
--- /dev/null
+++ b/lib/rtc.c
@@ -0,0 +1,77 @@
+/*
+ * This file is part of the libopenstm32 project.
+ *
+ * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopenstm32.h>
+
+void rtc_init(void)
+{
+ /* Enable power and backup interface clocks. */
+ RCC_APB1ENR |= (PWREN | BKPEN);
+
+ /* Enable access to the backup registers and the RTC. */
+ /* TODO: PWR component not yet implemented in libopenstm32. */
+ /* PWR_CR |= PWR_CR_DBP; */
+
+ /* TODO: Wait for the RSF bit in RTC_CRL to be set by hardware? */
+}
+
+void rtc_enter_config_mode(void)
+{
+ u32 reg32;
+
+ /* Wait until the RTOFF bit is 1 (no RTC register writes ongoing). */
+ while ((reg32 = (RTC_CRL & RTC_CRL_RTOFF)) == 0);
+
+ /* Enter configuration mode. */
+ RTC_CRL |= RTC_CRL_CNF;
+}
+
+void rtc_exit_config_mode(void)
+{
+ u32 reg32;
+
+ /* Exit configuration mode. */
+ RTC_CRL &= ~RTC_CRL_CNF;
+
+ /* Wait until the RTOFF bit is 1 (our RTC register write finished). */
+ while ((reg32 = (RTC_CRL & RTC_CRL_RTOFF)) == 0);
+}
+
+void rtc_set_alarm_time(u32 alarm_time)
+{
+ rtc_enter_config_mode();
+ RTC_ALRL = (alarm_time & 0x0000ffff);
+ RTC_ALRH = (alarm_time & 0xffff0000) >> 16;
+ rtc_exit_config_mode();
+}
+
+void rtc_enable_alarm(void)
+{
+ rtc_enter_config_mode();
+ RTC_CRH |= RTC_CRH_ALRIE;
+ rtc_exit_config_mode();
+}
+
+void rtc_disable_alarm(void)
+{
+ rtc_enter_config_mode();
+ RTC_CRH &= ~RTC_CRH_ALRIE;
+ rtc_exit_config_mode();
+}
+