From 12aeaad441a251e91ecb48528c6446a7461b435a Mon Sep 17 00:00:00 2001 From: Frantisek Burian Date: Thu, 13 Feb 2014 18:21:16 +0100 Subject: [locm3] Use the new clock-enabling mechanisms in locm3. --- src/platforms/swlink/platform.c | 19 +++++++++---------- src/platforms/swlink/platform.h | 7 +++---- src/platforms/swlink/usbdfu.c | 18 ++++++++---------- 3 files changed, 20 insertions(+), 24 deletions(-) (limited to 'src/platforms/swlink') diff --git a/src/platforms/swlink/platform.c b/src/platforms/swlink/platform.c index ea88dcb..28db60f 100644 --- a/src/platforms/swlink/platform.c +++ b/src/platforms/swlink/platform.c @@ -47,11 +47,11 @@ int platform_init(void) rcc_clock_setup_in_hse_8mhz_out_72mhz(); /* Enable peripherals */ - rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_USBEN); - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPBEN); - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_AFIOEN); - rcc_peripheral_enable_clock(&RCC_AHBENR, RCC_AHBENR_CRCEN); + rcc_periph_clock_enable(RCC_USB); + rcc_periph_clock_enable(RCC_GPIOA); + rcc_periph_clock_enable(RCC_GPIOB); + rcc_periph_clock_enable(RCC_AFIO); + rcc_periph_clock_enable(RCC_CRC); /* Unmap JTAG Pins so we can reuse as GPIO */ data = AFIO_MAPR; @@ -135,10 +135,9 @@ const char *platform_target_voltage(void) void disconnect_usb(void) { /* Disconnect USB cable by resetting USB Device and pulling USB_DP low*/ - rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1ENR_USBEN); - rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1ENR_USBEN); - rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_USBEN); - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); + rcc_periph_reset_pulse(RST_USB); + rcc_periph_clock_enable(RCC_USB); + rcc_periph_clock_enable(RCC_GPIOA); gpio_clear(GPIOA, GPIO12); gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_2_MHZ, GPIO_CNF_OUTPUT_OPENDRAIN, GPIO12); @@ -147,7 +146,7 @@ void disconnect_usb(void) void assert_boot_pin(void) { uint32_t crl = GPIOA_CRL; - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); + rcc_periph_clock_enable(RCC_GPIOA); /* Enable Pull on GPIOA1. We don't rely on the external pin * really pulled, but only on the value of the CNF register * changed from the reset value diff --git a/src/platforms/swlink/platform.h b/src/platforms/swlink/platform.h index 90acfb3..dd2ac8a 100644 --- a/src/platforms/swlink/platform.h +++ b/src/platforms/swlink/platform.h @@ -115,18 +115,17 @@ extern usbd_device *usbdev; #define USBUSART USART1 #define USBUSART_CR1 USART1_CR1 #define USBUSART_IRQ NVIC_USART1_IRQ -#define USBUSART_APB_ENR RCC_APB2ENR -#define USBUSART_CLK_ENABLE RCC_APB2ENR_USART1EN +#define USBUSART_CLK RCC_USART1 #define USBUSART_PORT GPIOB #define USBUSART_TX_PIN GPIO6 #define USBUSART_ISR usart1_isr #define USBUSART_TIM TIM4 -#define USBUSART_TIM_CLK_EN() rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_TIM4EN) +#define USBUSART_TIM_CLK_EN() rcc_periph_clock_enable(RCC_TIM4) #define USBUSART_TIM_IRQ NVIC_TIM4_IRQ #define USBUSART_TIM_ISR tim4_isr #define TRACE_TIM TIM2 -#define TRACE_TIM_CLK_EN() rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_TIM2EN) +#define TRACE_TIM_CLK_EN() rcc_periph_clock_enable(RCC_TIM2) #define TRACE_IRQ NVIC_TIM2_IRQ #define TRACE_ISR tim2_isr #define TRACE_IC_IN TIM_IC_IN_TI2 diff --git a/src/platforms/swlink/usbdfu.c b/src/platforms/swlink/usbdfu.c index de0b7ab..f87ccf4 100644 --- a/src/platforms/swlink/usbdfu.c +++ b/src/platforms/swlink/usbdfu.c @@ -31,10 +31,9 @@ void dfu_detach(void) { /* Disconnect USB cable by resetting USB Device and pulling USB_DP low*/ - rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1ENR_USBEN); - rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1ENR_USBEN); - rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_USBEN); - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); + rcc_periph_reset_pulse(RST_USB); + rcc_periph_clock_enable(RCC_USB); + rcc_periph_clock_enable(RCC_GPIOA); gpio_clear(GPIOA, GPIO12); gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_2_MHZ, GPIO_CNF_OUTPUT_OPENDRAIN, GPIO12); @@ -45,8 +44,8 @@ int main(void) { /* Check the force bootloader pin*/ uint16_t pin_b; - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPBEN); + rcc_periph_clock_enable(RCC_GPIOA); + rcc_periph_clock_enable(RCC_GPIOB); /* Switch PB5 (SWIM_RST_IN) up */ gpio_set(GPIOB, GPIO5); gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_2_MHZ, @@ -70,10 +69,9 @@ int main(void) /* Just in case: Disconnect USB cable by resetting USB Device * and pulling USB_DP low * Device will reconnect automatically as Pull-Up is hard wired*/ - rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1ENR_USBEN); - rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1ENR_USBEN); - rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_USBEN); - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); + rcc_periph_reset_pulse(RST_USB); + rcc_periph_clock_enable(RCC_USB); + rcc_periph_clock_enable(RCC_GPIOA); gpio_clear(GPIOA, GPIO12); gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_2_MHZ, GPIO_CNF_OUTPUT_OPENDRAIN, GPIO12); -- cgit v1.2.3