From 9009ed6581fddbd5c7cc1353aaec7144c4f778f6 Mon Sep 17 00:00:00 2001 From: Gareth McMullin Date: Sat, 11 Apr 2015 16:08:59 -0700 Subject: cortexm: Add target option to inhibit assersion of SRST. --- src/cortexm.c | 6 ++++-- src/include/cortexm.h | 2 ++ src/lpc43xx.c | 1 + 3 files changed, 7 insertions(+), 2 deletions(-) diff --git a/src/cortexm.c b/src/cortexm.c index e7bed5b..028af21 100644 --- a/src/cortexm.c +++ b/src/cortexm.c @@ -418,8 +418,10 @@ static void cortexm_pc_write(target *t, const uint32_t val) * using the core debug registers in the NVIC. */ static void cortexm_reset(target *t) { - jtagtap_srst(true); - jtagtap_srst(false); + if ((t->target_options & CORTEXM_TOPT_INHIBIT_SRST) == 0) { + jtagtap_srst(true); + jtagtap_srst(false); + } /* Read DHCSR here to clear S_RESET_ST bit before reset */ target_mem_read32(t, CORTEXM_DHCSR); diff --git a/src/include/cortexm.h b/src/include/cortexm.h index 0a9c3ae..de57112 100644 --- a/src/include/cortexm.h +++ b/src/include/cortexm.h @@ -153,6 +153,8 @@ #define ARM_THUMB_BREAKPOINT 0xBE00 +#define CORTEXM_TOPT_INHIBIT_SRST (1 << 2) + bool cortexm_attach(target *t); void cortexm_detach(target *t); void cortexm_halt_resume(target *t, bool step); diff --git a/src/lpc43xx.c b/src/lpc43xx.c index 99ceb00..b6c499a 100644 --- a/src/lpc43xx.c +++ b/src/lpc43xx.c @@ -110,6 +110,7 @@ bool lpc43xx_probe(target *t) 0x1B010000, 0x70000, 0x10000); target_add_commands(t, lpc43xx_cmd_list, "LPC43xx"); target_add_ram(t, 0x1B080000, 0xE4F80000UL); + t->target_options |= CORTEXM_TOPT_INHIBIT_SRST; } break; case 0x4100C200: -- cgit v1.2.3