From 64ffbbb9e5f2aeb1a0b6019decffa0d143768886 Mon Sep 17 00:00:00 2001 From: Nicolas Schodet Date: Thu, 6 Mar 2008 22:14:54 +0100 Subject: * digital/asserv/src/hdlcounter: - added a dummy test design. --- digital/asserv/src/hdlcounter/counter_top.v | 3 +++ 1 file changed, 3 insertions(+) (limited to 'digital/asserv/src/hdlcounter/counter_top.v') diff --git a/digital/asserv/src/hdlcounter/counter_top.v b/digital/asserv/src/hdlcounter/counter_top.v index 525ba367..b761f378 100644 --- a/digital/asserv/src/hdlcounter/counter_top.v +++ b/digital/asserv/src/hdlcounter/counter_top.v @@ -35,6 +35,7 @@ module counter_top(clk, rst, q0, q1, q2, q3, ale, rd, wr, ad); wire [1:0] qf0, qf1, qf2, qf3; wire [size-1:0] count0, count1, count2, count3; + // Decode encoders outputs. noise_filter f0[1:0] (clk, rst, q0, qf0); quad_decoder_div4 qd0 (clk, rst, qf0, count0); @@ -49,6 +50,7 @@ module counter_top(clk, rst, q0, q1, q2, q3, ale, rd, wr, ad); reg [size-1:0] lcount; + // Latch a counter when its address is given. always @(negedge ale or negedge rst) begin if (!rst) lcount <= 0; @@ -60,6 +62,7 @@ module counter_top(clk, rst, q0, q1, q2, q3, ale, rd, wr, ad); end end + // Tri-state output unless rd is active (0). assign ad = rd ? 8'bz : lcount; endmodule -- cgit v1.2.3