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-rw-r--r--digital/asserv/src/hdlcounter/counter_top.v23
-rw-r--r--digital/asserv/src/hdlcounter/test_counter_top.v29
-rw-r--r--digital/asserv/src/hdlcounter/test_counter_top.wave5
-rw-r--r--digital/asserv/src/hdlcounter/xilinx/counter_top.ucf27
4 files changed, 49 insertions, 35 deletions
diff --git a/digital/asserv/src/hdlcounter/counter_top.v b/digital/asserv/src/hdlcounter/counter_top.v
index 0c313704..525ba367 100644
--- a/digital/asserv/src/hdlcounter/counter_top.v
+++ b/digital/asserv/src/hdlcounter/counter_top.v
@@ -24,14 +24,13 @@
// }}}
`timescale 1ns / 1ps
-module counter_top(clk, rst, q0, q1, q2, q3, oe, sel, count);
+module counter_top(clk, rst, q0, q1, q2, q3, ale, rd, wr, ad);
parameter size = 8;
input clk;
input rst;
input [1:0] q0, q1, q2, q3;
- input oe;
- input [1:0] sel;
- output [size-1:0] count;
+ input ale, rd, wr;
+ inout [size-1:0] ad;
wire [1:0] qf0, qf1, qf2, qf3;
wire [size-1:0] count0, count1, count2, count3;
@@ -49,20 +48,18 @@ module counter_top(clk, rst, q0, q1, q2, q3, oe, sel, count);
quad_decoder_full qd3 (clk, rst, qf3, count3);
reg [size-1:0] lcount;
-
- always @(posedge clk or negedge rst) begin
+
+ always @(negedge ale or negedge rst) begin
if (!rst)
lcount <= 0;
else begin
- if (!oe) begin
- lcount <= sel == 0 ? count0 :
- sel == 1 ? count1 :
- sel == 2 ? count2 :
- count3;
- end
+ lcount <= ad[1:0] == 0 ? count0 :
+ ad[1:0] == 1 ? count1 :
+ ad[1:0] == 2 ? count2 :
+ count3;
end
end
- assign count = !oe ? 8'bz : lcount;
+ assign ad = rd ? 8'bz : lcount;
endmodule
diff --git a/digital/asserv/src/hdlcounter/test_counter_top.v b/digital/asserv/src/hdlcounter/test_counter_top.v
index 820cea4a..3cbed2e8 100644
--- a/digital/asserv/src/hdlcounter/test_counter_top.v
+++ b/digital/asserv/src/hdlcounter/test_counter_top.v
@@ -30,9 +30,10 @@ module test_counter_top();
reg clk;
reg rst;
reg [1:0] q[0:nc-1];
- reg oe;
+ reg oe, ale, rd, aord;
reg [1:0] sel;
- wire [7:0] countout;
+ wire [7:0] ad;
+ wire wr = 1;
`include "common.v"
@@ -51,7 +52,8 @@ module test_counter_top();
end
// Instantiation.
- counter_top uut (clk, rst, q[0], q[1], q[2], q[3], oe, sel, countout);
+ assign ad = aord ? { 6'b0, sel } : 8'bz;
+ counter_top uut (clk, rst, q[0], q[1], q[2], q[3], ale, rd, wr, ad);
// The count variable is the true encoder position, multiplied by 32,
// which is more than one encoder minimum period with a noise filter of
@@ -70,7 +72,7 @@ module test_counter_top();
initial begin
$dumpfile ("test_counter_top.vcd");
$dumpvars (1, clk, rst, countdiv32_0, countdiv32_1, countdiv32_2,
- countdiv32_3, uut, oe, sel, countout, countassert, a);
+ countdiv32_3, uut, ale, rd, sel, ad, countassert, a);
clk <= 1;
rst <= 0;
for (i = 0; i < nc; i = i + 1) begin
@@ -111,6 +113,9 @@ module test_counter_top();
wire [27:0] a = countdiv32_smp[0*max_filter+4];
initial begin
+ oe = 1;
+ ale = 0;
+ rd = 1;
forever begin
@(posedge clk)
// Sample countdiv32 at rising edge.
@@ -127,20 +132,30 @@ module test_counter_top();
// This is more difficult to find the exact expected value (I
// mean, without copy-paste the unit under test verbatim).
if (filter_size[sel] > 1)
- assert ((countassert8 - countout) | 1, 1);
+ assert ((countassert8 - ad) | 1, 1);
else
- assertv8 (countassert8, countout);
+ assertv8 (countassert8, ad);
end
else begin
- assertv8 (8'bz, countout);
+ assertv8 (8'bz, ad);
end
// Prepare next check.
if (oe == 1) begin
oe = 0;
+ rd = 1;
sel = $random & 2'b11;
+ aord = 1;
+ #1
+ ale = 1;
+ #1
+ ale = 0;
+ #1
+ aord = 0;
end
else begin
oe = 1;
+ aord = 0;
+ rd = 0;
end
end
end
diff --git a/digital/asserv/src/hdlcounter/test_counter_top.wave b/digital/asserv/src/hdlcounter/test_counter_top.wave
index 338660ef..0cf65f3c 100644
--- a/digital/asserv/src/hdlcounter/test_counter_top.wave
+++ b/digital/asserv/src/hdlcounter/test_counter_top.wave
@@ -8,10 +8,11 @@ test_counter_top.countdiv32_1[27:0]
test_counter_top.countdiv32_2[27:0]
test_counter_top.countdiv32_3[27:0]
@28
-test_counter_top.oe
+test_counter_top.ale
+test_counter_top.rd
test_counter_top.sel[1:0]
@22
-test_counter_top.countout[7:0]
+test_counter_top.ad[7:0]
test_counter_top.uut.count0[7:0]
test_counter_top.uut.count1[7:0]
test_counter_top.uut.count2[7:0]
diff --git a/digital/asserv/src/hdlcounter/xilinx/counter_top.ucf b/digital/asserv/src/hdlcounter/xilinx/counter_top.ucf
index fe801a47..0614d055 100644
--- a/digital/asserv/src/hdlcounter/xilinx/counter_top.ucf
+++ b/digital/asserv/src/hdlcounter/xilinx/counter_top.ucf
@@ -2,17 +2,21 @@ NET "clk" TNM_NET = "clk";
TIMESPEC "TS_clk" = PERIOD "clk" 16 MHz HIGH 50 %;
OFFSET = IN 20 ns BEFORE "clk" ;
OFFSET = OUT 20 ns AFTER "clk" ;
+OFFSET = IN 26 ns BEFORE "ale" LOW ;
-NET "clk" LOC = "P5" | BUFG = CLK;
-NET "count<0>" LOC = "P28";
-NET "count<1>" LOC = "P29";
-NET "count<2>" LOC = "P33";
-NET "count<3>" LOC = "P34";
-NET "count<4>" LOC = "P35";
-NET "count<5>" LOC = "P36";
-NET "count<6>" LOC = "P37";
-NET "count<7>" LOC = "P38";
-NET "oe" LOC = "P42";
+NET "clk" LOC = "P5" | BUFG = CLK;
+NET "ale" LOC = "P6";
+NET "rd" LOC = "P42";
+NET "rst" LOC = "P39";
+NET "wr" LOC = "P4";
+NET "ad<0>" LOC = "P28";
+NET "ad<1>" LOC = "P29";
+NET "ad<2>" LOC = "P33";
+NET "ad<3>" LOC = "P34";
+NET "ad<4>" LOC = "P35";
+NET "ad<5>" LOC = "P36";
+NET "ad<6>" LOC = "P37";
+NET "ad<7>" LOC = "P38";
NET "q0<0>" LOC = "P3";
NET "q0<1>" LOC = "P2";
NET "q1<0>" LOC = "P9";
@@ -21,6 +25,3 @@ NET "q2<0>" LOC = "P12";
NET "q2<1>" LOC = "P11";
NET "q3<0>" LOC = "P14";
NET "q3<1>" LOC = "P13";
-NET "rst" LOC = "P39";
-NET "sel<0>" LOC = "P26";
-NET "sel<1>" LOC = "P27";