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authorFlorent Duchon2012-12-26 17:36:00 +0100
committerFlorent Duchon2013-02-13 21:21:12 +0100
commitb24866225a6301d3a663f874725e83c012dc25d3 (patch)
treeca527a2aab9abcdfbaf244c53ca63f0c531892b0 /digital/zigbit/bitcloud/stack/Components/HAL/avr/atmega1281/common/src/halClkCtrl.c
parent2ba279f4eb2f23fa08a7c13465d16ae6ba5d0f96 (diff)
digital/beacon: add bitcloud stack into common directory digital/zigbit
Diffstat (limited to 'digital/zigbit/bitcloud/stack/Components/HAL/avr/atmega1281/common/src/halClkCtrl.c')
-rw-r--r--digital/zigbit/bitcloud/stack/Components/HAL/avr/atmega1281/common/src/halClkCtrl.c122
1 files changed, 122 insertions, 0 deletions
diff --git a/digital/zigbit/bitcloud/stack/Components/HAL/avr/atmega1281/common/src/halClkCtrl.c b/digital/zigbit/bitcloud/stack/Components/HAL/avr/atmega1281/common/src/halClkCtrl.c
new file mode 100644
index 00000000..e6f968d1
--- /dev/null
+++ b/digital/zigbit/bitcloud/stack/Components/HAL/avr/atmega1281/common/src/halClkCtrl.c
@@ -0,0 +1,122 @@
+/**************************************************************************//**
+ \file halClkCtrl.c
+
+ \brief Implementation of clock control module.
+
+ \author
+ Atmel Corporation: http://www.atmel.com \n
+ Support email: avr@atmel.com
+
+ Copyright (c) 2008-2011, Atmel Corporation. All rights reserved.
+ Licensed under Atmel's Limited License Agreement (BitCloudTM).
+
+ \internal
+ History:
+ 29/05/07 E. Ivanov - Created
+ 16/04/09 A. Khromykh - Refactored
+ ******************************************************************************/
+/******************************************************************************
+ * WARNING: CHANGING THIS FILE MAY AFFECT CORE FUNCTIONALITY OF THE STACK. *
+ * EXPERT USERS SHOULD PROCEED WITH CAUTION. *
+ ******************************************************************************/
+
+/******************************************************************************
+ Includes section
+******************************************************************************/
+#include <halClkCtrl.h>
+#include <halRfCtrl.h>
+#include <atomic.h>
+#include <halDbg.h>
+#include <halDiagnostic.h>
+/******************************************************************************
+ Define(s) section
+******************************************************************************/
+// defines fuse mask for RC oscillator
+#define HAL_RC_OSCILLATOR_CLOCK 0x02
+// mask for CKSEL bits
+#define HAL_CKSEL_MASK 0x0F
+
+/******************************************************************************
+ Prototypes section
+******************************************************************************/
+void halStartingCalibrate(void);
+
+/******************************************************************************
+ Global variables section
+******************************************************************************/
+static volatile ClkSource_t clkClockSource;
+
+/******************************************************************************
+ Implementations section
+******************************************************************************/
+/**************************************************************************//**
+\brief Initialization system clock.
+******************************************************************************/
+void halInitFreq(void)
+{
+ uint8_t lowFuseByte;
+
+ // wait for end of eeprom writing
+ while (EECR & (1 << EEPE));
+ ATOMIC_SECTION_ENTER
+ BEGIN_MEASURE
+ lowFuseByte = SF_GET_LOW_FUSES();
+ END_MEASURE(HALATOM_SETLOWFUSES_TIME_LIMIT)
+ ATOMIC_SECTION_LEAVE
+
+ if (HAL_RC_OSCILLATOR_CLOCK == (lowFuseByte & HAL_CKSEL_MASK))
+ clkClockSource = INTERNAL_RC;
+ else
+ clkClockSource = OTHER_SOURCE;
+
+ if (INTERNAL_RC == clkClockSource)
+ {
+ ATOMIC_SECTION_ENTER
+ BEGIN_MEASURE
+ ASM (
+ "push r21 \n\t"
+
+ "ldi r21, 0x80 \n\t" /* CLKPR = 1 << CLKPCE */
+ "sts 0x0061, r21 \n\t" /* CLKPR = 1 << CLKPCE */
+
+#if (F_CPU == 4000000ul)
+ "ldi r21, 0x01 \n\t" /* CLKPR = 1 << CLKPS0 (1 cycle) */
+ "sts 0x0061, r21 \n\t" /* CLKPR = 1 << CLKPS0 (2 cycle) */
+#endif
+#if (F_CPU == 8000000ul)
+ "ldi r21, 0x00 \n\t" /* CLKPR = 0 (1 cycle) */
+ "sts 0x0061, r21 \n\t" /* CLKPR = 0 (2 cycle) */
+#endif
+
+ "pop r21 \n\t"
+ );
+
+ END_MEASURE(HALATOM_INITFREQ_TIME_LIMIT)
+ ATOMIC_SECTION_LEAVE
+ halStartingCalibrate();
+ }
+}
+
+/**************************************************************************//**
+\brief Return clock source
+
+\return
+ clock source.
+******************************************************************************/
+ClkSource_t halGetClockSource(void)
+{
+ return clkClockSource;
+}
+
+/**************************************************************************//**
+\brief System clock.
+
+\return
+ system clock in Hz.
+******************************************************************************/
+uint32_t HAL_ReadFreq(void)
+{
+ return (uint32_t)F_CPU;
+}
+
+// eof halClkCtrl.c