From ba78bd9ba834260d035a9830726afc34fdad2a15 Mon Sep 17 00:00:00 2001 From: Nicolas Schodet Date: Sun, 18 Oct 2009 23:32:54 +0200 Subject: import firmware from LEGO v1.05 --- AT91SAM7S256/Resource/BITMAPS/Connections.bmp | Bin 0 -> 446 bytes AT91SAM7S256/Resource/BITMAPS/Cursor.bmp | Bin 0 -> 94 bytes AT91SAM7S256/Resource/BITMAPS/Display.bmp | Bin 0 -> 350 bytes AT91SAM7S256/Resource/BITMAPS/Fail.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/BITMAPS/FileTypes.bmp | Bin 0 -> 638 bytes AT91SAM7S256/Resource/BITMAPS/GetUserString.bmp | Bin 0 -> 446 bytes AT91SAM7S256/Resource/BITMAPS/Incomming.bmp | Bin 0 -> 734 bytes AT91SAM7S256/Resource/BITMAPS/Info.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/BITMAPS/LowBattery.bmp | Bin 0 -> 734 bytes AT91SAM7S256/Resource/BITMAPS/Ok.bmp | Bin 0 -> 126 bytes AT91SAM7S256/Resource/BITMAPS/Program.bmp | Bin 0 -> 830 bytes AT91SAM7S256/Resource/BITMAPS/Running.bmp | Bin 0 -> 1598 bytes AT91SAM7S256/Resource/BITMAPS/Step.bmp | Bin 0 -> 830 bytes AT91SAM7S256/Resource/BITMAPS/Wait.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/DEMO PROGRAM/Demo.rxe | Bin 0 -> 9436 bytes AT91SAM7S256/Resource/FONT/Font.bmp | Bin 0 -> 638 bytes AT91SAM7S256/Resource/FONT/Port.bmp | Bin 0 -> 94 bytes AT91SAM7S256/Resource/INPUTICONS/Light.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/INPUTICONS/LightAmb.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/INPUTICONS/LightOld.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/INPUTICONS/MotorDeg.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/INPUTICONS/MotorRot.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/INPUTICONS/Rotation.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/INPUTICONS/SoundDb.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/INPUTICONS/SoundDba.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/INPUTICONS/TempC.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/INPUTICONS/TempF.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/INPUTICONS/Touch.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/INPUTICONS/UltrasonicCm.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/INPUTICONS/UltrasonicIn.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/INTRO/Intro.txt | 21 + AT91SAM7S256/Resource/INTRO/RCXintro_1.bmp | Bin 0 -> 574 bytes AT91SAM7S256/Resource/INTRO/RCXintro_10.bmp | Bin 0 -> 126 bytes AT91SAM7S256/Resource/INTRO/RCXintro_11.bmp | Bin 0 -> 126 bytes AT91SAM7S256/Resource/INTRO/RCXintro_12.bmp | Bin 0 -> 254 bytes AT91SAM7S256/Resource/INTRO/RCXintro_13.bmp | Bin 0 -> 254 bytes AT91SAM7S256/Resource/INTRO/RCXintro_14.bmp | Bin 0 -> 254 bytes AT91SAM7S256/Resource/INTRO/RCXintro_15.bmp | Bin 0 -> 254 bytes AT91SAM7S256/Resource/INTRO/RCXintro_16.bmp | Bin 0 -> 254 bytes AT91SAM7S256/Resource/INTRO/RCXintro_2.bmp | Bin 0 -> 574 bytes AT91SAM7S256/Resource/INTRO/RCXintro_3.bmp | Bin 0 -> 574 bytes AT91SAM7S256/Resource/INTRO/RCXintro_4.bmp | Bin 0 -> 574 bytes AT91SAM7S256/Resource/INTRO/RCXintro_5.bmp | Bin 0 -> 574 bytes AT91SAM7S256/Resource/INTRO/RCXintro_6.bmp | Bin 0 -> 446 bytes AT91SAM7S256/Resource/INTRO/RCXintro_7.bmp | Bin 0 -> 382 bytes AT91SAM7S256/Resource/INTRO/RCXintro_8.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/INTRO/RCXintro_9.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/MAINMENU/Bluetooth.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/MAINMENU/Datalog.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/MAINMENU/Mainmenu.txt | 20 + AT91SAM7S256/Resource/MAINMENU/MyFiles.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/MAINMENU/NXTProgram.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/MAINMENU/No.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/MAINMENU/Program.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/MAINMENU/Settings.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/MAINMENU/TestProgram.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/MAINMENU/TryMe.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/MAINMENU/View.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/MAINMENU/Yes.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/MENUES/IconNos.txt | 98 + AT91SAM7S256/Resource/MENUES/Icons.bmp | Bin 0 -> 9278 bytes AT91SAM7S256/Resource/MENUES/Mainmenu.txt | 20 + AT91SAM7S256/Resource/MENUES/Submenu01.txt | 38 + AT91SAM7S256/Resource/MENUES/Submenu02.txt | 78 + AT91SAM7S256/Resource/MENUES/Submenu04.txt | 20 + AT91SAM7S256/Resource/MENUES/Submenu05.txt | 29 + AT91SAM7S256/Resource/MENUES/Submenu06.txt | 38 + AT91SAM7S256/Resource/MENUES/Submenu07.txt | 49 + .../Resource/OnBrickProgramming/RPGReader.sys | Bin 0 -> 14346 bytes AT91SAM7S256/Resource/SOUNDS/! Attention.rso | Bin 0 -> 1755 bytes AT91SAM7S256/Resource/SOUNDS/! Click.rso | Bin 0 -> 451 bytes AT91SAM7S256/Resource/SOUNDS/! Startup.rso | Bin 0 -> 8161 bytes AT91SAM7S256/Resource/STATUS/Status.bmp | Bin 0 -> 638 bytes AT91SAM7S256/Resource/SUBMENU01/DatalogFile.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU01/Delete.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU01/LMSFile.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU01/MerlotFile.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU01/NXTFile.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU01/No.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU01/ProgramFile.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU01/Run.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU01/Send.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU01/SoundFile.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU01/Submenu01.txt | 38 + AT91SAM7S256/Resource/SUBMENU01/Yes.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU02/BackTurnLeft1.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU02/BackTurnLeft2.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU02/BackTurnRight1.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU02/BackTurnRight2.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU02/Backward1.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU02/Backward2.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU02/Backward3.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU02/Dark.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU02/Delete.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU02/Empty.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU02/Forward1.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU02/Forward2.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU02/Forward3.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU02/Light.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU02/Loop.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU02/MainMenu.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU02/No.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU02/ProgramFile.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU02/Run.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU02/SeekObj.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU02/Send.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU02/Sound.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU02/Stop.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU02/Submenu02.txt | 78 + AT91SAM7S256/Resource/SUBMENU02/Tone1.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU02/Tone2.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU02/Touch.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU02/TurnLeft1.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU02/TurnLeft2.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU02/TurnLeft3.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU02/TurnRight1.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU02/TurnRight2.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU02/TurnRight3.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU02/Wait1.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU02/Wait2.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU02/Wait3.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU02/Yes.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU03/ArrowLeft.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU03/ArrowRight.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU03/DatalogFile.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU03/Delete.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU03/Done.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU03/Light.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU03/LightAmb.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU03/LightOld.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU03/MainMenu.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU03/Motor.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU03/MotorDeg.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU03/MotorRot.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU03/No.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU03/Port1.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU03/Port2.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU03/Port3.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU03/Port4.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU03/PortA.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU03/PortB.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU03/PortC.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU03/Rcx.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU03/Rotation.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU03/Run.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU03/Sound.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU03/SoundDb.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU03/SoundDba.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU03/Submenu03.txt | 58 + AT91SAM7S256/Resource/SUBMENU03/TempC.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU03/TempF.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU03/Time.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU03/Touch.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU03/Ultrasonic.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU03/UltrasonicCm.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU03/UltrasonicIn.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU03/Yes.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU04/Light.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU04/LightAmb.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU04/LightOld.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU04/Motor.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU04/MotorDeg.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU04/MotorRot.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU04/Port1.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU04/Port2.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU04/Port3.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU04/Port4.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU04/PortA.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU04/PortB.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU04/PortC.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU04/Rotation.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU04/Run.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU04/Sound.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU04/SoundDb.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU04/SoundDba.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU04/Submenu04.txt | 20 + AT91SAM7S256/Resource/SUBMENU04/TempC.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU04/TempF.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU04/Touch.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU04/Ultrasonic.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU04/UltrasonicCm.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU04/UltrasonicIn.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU05/ArrowLeft.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU05/ArrowRight.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU05/BTSetup.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU05/DatalogFile.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU05/Delete.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU05/LMSFile.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU05/NXTFile.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU05/No.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU05/Sleep.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU05/SoundFile.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU05/Submenu05.txt | 29 + AT91SAM7S256/Resource/SUBMENU05/TestProgram.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU05/TryMeFile.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU05/Volume.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU05/Volume0.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU05/Volume1.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU05/Volume2.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU05/Volume3.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU05/Volume4.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU05/Yes.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU06/Delete.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU06/No.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU06/Run.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU06/Submenu06.txt | 28 + AT91SAM7S256/Resource/SUBMENU06/TryMeFile.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU06/Yes.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU07/BTOff.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU07/BTOn.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU07/BTSearching.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU07/BtPc.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU07/BtRcx.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU07/BtTlf.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU07/BtUnknown.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU07/Connect.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU07/Delete.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU07/Disconnect.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU07/Invisibel.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU07/MyUnits.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU07/MyUnits0.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU07/MyUnits1.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU07/MyUnits2.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU07/MyUnits3.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU07/No.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU07/OnOff.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU07/SelectDevices.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU07/Settings.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU07/ShowDevices.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU07/Submenu07.txt | 63 + AT91SAM7S256/Resource/SUBMENU07/Visiability.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU07/Visibel.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU07/Yes.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU10/MyUnits0.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU10/MyUnits1.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU10/MyUnits2.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU10/MyUnits3.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU10/Submenu10.txt | 20 + AT91SAM7S256/Resource/SUBMENU11/OnOff.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU11/Range.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU11/Range1.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU11/Range2.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU11/Range3.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU11/Submenu11.txt | 8 + AT91SAM7S256/Resource/SUBMENU11/TestProgram.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/SUBMENU11/Visiability.bmp | Bin 0 -> 158 bytes AT91SAM7S256/Resource/TEXT/Ui.txt | 51 + AT91SAM7S256/Resource/TRYME PROGRAMS/Try-Light.rbt | Bin 0 -> 272458 bytes AT91SAM7S256/Resource/TRYME PROGRAMS/Try-Light.rtm | Bin 0 -> 4456 bytes AT91SAM7S256/Resource/TRYME PROGRAMS/Try-Motor.rbt | Bin 0 -> 309442 bytes .../Resource/TRYME PROGRAMS/Try-Ultrasonic.rtm | Bin 0 -> 3756 bytes AT91SAM7S256/Resource/TRYME PROGRAMS/Woops.rso | Bin 0 -> 4699 bytes .../Resource/TRYME PROGRAMS/faceclosed.ric | Bin 0 -> 316 bytes AT91SAM7S256/Resource/TRYME PROGRAMS/faceopen.ric | Bin 0 -> 316 bytes AT91SAM7S256/SAM7S256/Include/AT91SAM7S256.h | 1920 ++++++ AT91SAM7S256/SAM7S256/Include/AT91SAM7S256_inc.h | 1710 ++++++ AT91SAM7S256/SAM7S256/Include/Cstartup.s79 | 347 ++ AT91SAM7S256/SAM7S256/Include/Cstartup_SAM7.c | 88 + AT91SAM7S256/SAM7S256/Include/ioat91sam7s256.h | 3307 ++++++++++ AT91SAM7S256/SAM7S256/Include/lib_AT91SAM7S256.h | 3664 ++++++++++++ AT91SAM7S256/SAM7S256/Include/sam7s256.c | 28 + AT91SAM7S256/SAM7S256/Include/sam7s256.h | 45 + AT91SAM7S256/SAM7S256/Tools/AT91SAM7S256.i79 | 38 + AT91SAM7S256/SAM7S256/Tools/LMS_ARM.dep | 2453 ++++++++ AT91SAM7S256/SAM7S256/Tools/LMS_ARM.ewd | 1354 +++++ AT91SAM7S256/SAM7S256/Tools/LMS_ARM.ewp | 2538 ++++++++ AT91SAM7S256/SAM7S256/Tools/LMS_ARM.eww | 10 + AT91SAM7S256/SAM7S256/Tools/SAM7.mac | 178 + .../SAM7S256/Tools/at91SAM7S256_NoRemap.xcl | 138 + AT91SAM7S256/SAM7S256/Tools/at91SAM7S256_Remap.xcl | 143 + .../SAM7S256/Tools/at91SAM7S64_NoRemap.xcl | 139 + AT91SAM7S256/SAM7S256/Tools/ioat91sam7s256.ddf | 1577 +++++ AT91SAM7S256/SAM7S256/Tools/settings/LMS_ARM.dbgdt | 54 + AT91SAM7S256/SAM7S256/Tools/settings/LMS_ARM.dni | 19 + AT91SAM7S256/SAM7S256/Tools/settings/LMS_ARM.wsdt | 80 + AT91SAM7S256/Source/BtTest.inc | 1642 +++++ AT91SAM7S256/Source/Connections.txt | 21 + AT91SAM7S256/Source/Cursor.txt | 10 + AT91SAM7S256/Source/Devices.txt | 21 + AT91SAM7S256/Source/Display.txt | 12 + AT91SAM7S256/Source/Fail.txt | 12 + AT91SAM7S256/Source/Font.txt | 15 + AT91SAM7S256/Source/Functions.inl | 3730 ++++++++++++ AT91SAM7S256/Source/Icons.txt | 297 + AT91SAM7S256/Source/Info.txt | 12 + AT91SAM7S256/Source/LowBattery.txt | 16 + AT91SAM7S256/Source/Mainmenu.rms | 65 + AT91SAM7S256/Source/Ok.txt | 11 + AT91SAM7S256/Source/Port.txt | 10 + AT91SAM7S256/Source/RCXintro_1.txt | 17 + AT91SAM7S256/Source/RCXintro_10.txt | 11 + AT91SAM7S256/Source/RCXintro_11.txt | 11 + AT91SAM7S256/Source/RCXintro_12.txt | 11 + AT91SAM7S256/Source/RCXintro_13.txt | 11 + AT91SAM7S256/Source/RCXintro_14.txt | 11 + AT91SAM7S256/Source/RCXintro_15.txt | 11 + AT91SAM7S256/Source/RCXintro_16.txt | 11 + AT91SAM7S256/Source/RCXintro_2.txt | 17 + AT91SAM7S256/Source/RCXintro_3.txt | 17 + AT91SAM7S256/Source/RCXintro_4.txt | 17 + AT91SAM7S256/Source/RCXintro_5.txt | 17 + AT91SAM7S256/Source/RCXintro_6.txt | 15 + AT91SAM7S256/Source/RCXintro_7.txt | 14 + AT91SAM7S256/Source/RCXintro_8.txt | 12 + AT91SAM7S256/Source/RCXintro_9.txt | 12 + AT91SAM7S256/Source/Running.txt | 57 + AT91SAM7S256/Source/Status.txt | 15 + AT91SAM7S256/Source/Step.txt | 17 + AT91SAM7S256/Source/Submenu01.rms | 128 + AT91SAM7S256/Source/Submenu02.rms | 401 ++ AT91SAM7S256/Source/Submenu03.rms | 324 + AT91SAM7S256/Source/Submenu04.rms | 170 + AT91SAM7S256/Source/Submenu05.rms | 128 + AT91SAM7S256/Source/Submenu06.rms | 51 + AT91SAM7S256/Source/Submenu07.rms | 142 + AT91SAM7S256/Source/Test1.txt | 17 + AT91SAM7S256/Source/Test2.txt | 17 + AT91SAM7S256/Source/Ui.txt | 60 + AT91SAM7S256/Source/Wait.txt | 12 + AT91SAM7S256/Source/c_button.c | 134 + AT91SAM7S256/Source/c_button.h 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Turn_off? +10200401 10200001 +2 0 +0 0 +0 0 +1 1 + + +00000011 00000021 00000031 00000041 00000051 00000061 +3B 3C 3E 51 3F 40 +My_Files NXT_Program View Bluetooth Settings Try_Me +01040000 01040000 01040000 01040000 01040000 01040000 +0 0 0 0 0 0 +0 0 0 0 0 0 +1 2 4 7 5 6 +1 1 1 2 1 1 + + diff --git a/AT91SAM7S256/Resource/MENUES/Submenu01.txt b/AT91SAM7S256/Resource/MENUES/Submenu01.txt new file mode 100644 index 0000000..9a9ace5 --- /dev/null +++ b/AT91SAM7S256/Resource/MENUES/Submenu01.txt @@ -0,0 +1,38 @@ +00000001 00000002 00000003 00000004 +1C 1D 1B 1F +Software_files NXT_files Sound_files Datalog_files +10008001 10008001 10008001 00808000 +6 6 6 6 +2 3 1 5 +0 0 0 0 +1 1 1 2 + + +00000011 00000014 +00 00 +_ _ +00000300 00000300 +6 6 +F2 F2 +0 0 +1 1 + + +00000111 00000211 00000311 00000114 00000214 +32 33 34 34 33 +Run Send Delete Delete Send +00000120 00400000 00000000 00000000 00400000 +8 0 0 0 0 +F8 0 0 0 0 +0 0 0 0 0 +0 1 2 2 1 + + + 00001211 00001311 00002311 00001114 00002114 00001214 + 00 31 30 31 30 00 + _ Are_you_sure? Are_you_sure? Are_you_sure? Are_you_sure? _ + 00000300 0000008 00000004 00000008 00000004 00000300 + 10 9 0 9 0 10 + F9 0 0 0 0 F9 + 0 0 0 0 0 0 + 0 0 0 0 0 0 \ No newline at end of file diff --git a/AT91SAM7S256/Resource/MENUES/Submenu02.txt b/AT91SAM7S256/Resource/MENUES/Submenu02.txt new file mode 100644 index 0000000..53c2f7b --- /dev/null +++ b/AT91SAM7S256/Resource/MENUES/Submenu02.txt @@ -0,0 +1,78 @@ +00000001 +00 +_ +00000300 +B +F7 +0 +1 + + +00000011 00000021 00000031 00000041 00000051 00000061 00000071 00000081 00000091 000000A1 000000B1 000000C1 000000D1 000000E1 000000F1 +23 22 29 28 2F 27 2B 2C 24 2A 25 26 21 2D 2E +Forward_5 Forward Turn_right_2 Turn_right Back_right_2 Back_right Tone_1 Tone_2 Back_left_2 Back_left Turn_left Turn_left_2 Empty Backward Backward_5 +10000061 10000061 10000061 10000061 10000061 10000061 10000061 10000061 10000061 10000061 10000061 10000061 10000061 10000061 10000061 +B B B B B B B B B B B B B B B +23 22 29 28 2F 27 2B 2C 24 2A 25 26 21 2D 2E +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 + + +00000111 00000211 00000311 00000411 00000511 00000611 00000711 00000811 00000911 +21 46 47 48 43 44 42 49 45 +Empty Wait_2 Wait_5 Wait_10 Object Sound Light Dark Touch +10000061 10000061 10000061 10000061 10000061 10000061 10000061 10000061 10000061 +B B B B B B B B B +41 46 47 48 43 44 42 49 45 +0 0 0 0 0 0 0 0 0 +1 1 1 1 1 1 1 1 1 + + +00001111 00002111 00003111 00004111 00005111 00006111 00007111 00008111 00009111 0000A111 0000B111 0000C111 0000D111 0000E111 0000F111 +23 22 29 28 2F 27 2B 2C 24 2A 25 26 21 2D 2E +Forward_5 Forward Turn_right_2 Turn_right Back_right_2 Back_right Tone_1 Tone_2 Back_left_2 Back_left Turn_left Turn_left_2 Empty Backward Backward_5 +10000061 10000061 10000061 10000061 10000061 10000061 10000061 10000061 10000061 10000061 10000061 10000061 10000061 10000061 10000061 +B B B B B B B B B B B B B B B +23 22 29 28 2F 27 2B 2C 24 2A 25 26 21 2D 2E +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 + + +00011111 00021111 00031111 00041111 00051111 00061111 00071111 00081111 00091111 +21 46 47 48 43 44 42 49 45 +Empty Wait_2 Wait_5 Wait_10 Object Sound Light Dark Touch +10000061 10000061 10000061 10000061 10000061 10000061 10000061 10000061 10000061 +B B B B B B B B B +41 46 47 48 43 44 42 49 45 +0 0 0 0 0 0 0 0 0 +1 1 1 1 1 1 1 1 1 + + +00111111 00211111 +4D 4E +Stop Loop +10000061 10000061 +B B +FB FC +0 0 +1 1 + + +01111111 02111111 04111111 +32 37 1D +Run Main_menu Save +00000060 00002060 00000060 +B 0 B +F8 0 FA +0 0 0 +0 0 2 + + + 14111111 24111111 + 31 30 + Yes No + 00002020 00080024 + B B + ED F6 + 0 0 + 0 0 \ No newline at end of file diff --git a/AT91SAM7S256/Resource/MENUES/Submenu04.txt b/AT91SAM7S256/Resource/MENUES/Submenu04.txt new file mode 100644 index 0000000..917be20 --- /dev/null +++ b/AT91SAM7S256/Resource/MENUES/Submenu04.txt @@ -0,0 +1,20 @@ +00000001 00000002 00000003 00000004 00000005 00000006 00000007 00000008 00000009 0000000A 0000000B 0000000C 0000000D +02 03 04 05 06 0D 0E 0A 09 08 07 0B 0C +Sound_dB Sound_dBA Reflected_light Ambient_light Light_Sensor* Temperature_`C* Temperature_`F* Rotation* Motor_rotations Motor_degrees Touch Ultrasonic_inch Ultrasonic_cm +10000121 10000021 10000021 10000021 10000021 10000021 10000021 10000021 00000020 00000020 10000021 10000021 10000021 +E E E E E E E E E E E E E +2 3 4 5 6 D E A 9 8 7 B C +0 0 0 0 0 0 0 0 0 0 0 0 0 +1 1 1 1 1 1 1 1 1 1 1 1 1 + + +00000011 00000021 00000031 00000041 00000019 00000029 00000039 0000001A 0000002A 0000003A +12 13 14 15 16 17 18 16 17 18 +Port_1 Port_2 Port_3 Port_4 Port_A Port_B Port_C Port_A Port_B Port_C +00000020 00000020 00000020 00000020 00000020 00000020 00000020 00000020 00000020 00000020 +E E E E E E E E E E +12 13 14 15 16 17 18 16 17 18 +0 0 0 0 0 0 0 0 0 0 +0 0 0 0 0 0 0 0 0 0 + + diff --git a/AT91SAM7S256/Resource/MENUES/Submenu05.txt b/AT91SAM7S256/Resource/MENUES/Submenu05.txt new file mode 100644 index 0000000..2808a4f --- /dev/null +++ b/AT91SAM7S256/Resource/MENUES/Submenu05.txt @@ -0,0 +1,29 @@ +00000001 00000002 00000003 00000004 +39 3A 4F 34 +Volume Sleep NXT_Version Delete_files +00008000 00008000 00000000 00008000 +0 0 1 0 +0 0 0 0 +0 0 0 0 +1 1 0 1 + + +00000011 00000021 00000031 00000012 00000022 00000032 00000014 00000024 00000034 00000044 00000054 +39 35 36 3A 35 36 1C 1D 1B 1F 1E +_ _ _ _ _ _ Software_files NXT_files Sound_files Datalog_files Try_me_files +00000360 00000000 00000000 00000320 00000000 00000000 10000001 10000001 10000001 10800001 10000001 +7 0 0 4 0 0 5 5 5 5 5 +EF 0 0 EF 0 0 2 3 1 5 4 +0 0 0 0 0 0 0 0 0 0 0 +0 0 0 0 0 0 2 2 2 2 2 + + + 00000114 00000214 + 31 30 + Are_you_sure? Are_you_sure? + 00000108 00000104 + 5 5 + F1 0 + 0 0 + 0 0 + diff --git a/AT91SAM7S256/Resource/MENUES/Submenu06.txt b/AT91SAM7S256/Resource/MENUES/Submenu06.txt new file mode 100644 index 0000000..f7857b6 --- /dev/null +++ b/AT91SAM7S256/Resource/MENUES/Submenu06.txt @@ -0,0 +1,38 @@ +00000001 +1E +_ +00001000 +6 +4 +0 +1 + + +00000011 +1E +_ +00000380 +6 +F2 +0 +2 + + +00000111 00000211 +34 32 +Delete Run +00000000 00000120 +0 8 +0 F8 +0 0 +2 0 + + +00001111 00002111 +31 30 +Are_you_sure? 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files /dev/null and b/AT91SAM7S256/Resource/SUBMENU05/No.bmp differ diff --git a/AT91SAM7S256/Resource/SUBMENU05/Sleep.bmp b/AT91SAM7S256/Resource/SUBMENU05/Sleep.bmp new file mode 100644 index 0000000..d361ac2 Binary files /dev/null and b/AT91SAM7S256/Resource/SUBMENU05/Sleep.bmp differ diff --git a/AT91SAM7S256/Resource/SUBMENU05/SoundFile.bmp b/AT91SAM7S256/Resource/SUBMENU05/SoundFile.bmp new file mode 100644 index 0000000..4a31d70 Binary files /dev/null and b/AT91SAM7S256/Resource/SUBMENU05/SoundFile.bmp differ diff --git a/AT91SAM7S256/Resource/SUBMENU05/Submenu05.txt b/AT91SAM7S256/Resource/SUBMENU05/Submenu05.txt new file mode 100644 index 0000000..e71f05c --- /dev/null +++ b/AT91SAM7S256/Resource/SUBMENU05/Submenu05.txt @@ -0,0 +1,29 @@ +00000001 00000002 00000003 00000004 +VOLUME SLEEP TESTPROGRAM DELETE +Volume Sleep Test_Program Delete_files +00008000 00008000 00000000 00008000 +0 0 1 0 +0 0 0 0 +0 0 0 0 +1 1 0 1 + + +00000011 00000021 00000031 00000012 00000022 00000032 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Are_you_sure? + 00000108 00000104 + 5 5 + F1 0 + 0 0 + 0 0 + diff --git a/AT91SAM7S256/Resource/SUBMENU05/TestProgram.bmp b/AT91SAM7S256/Resource/SUBMENU05/TestProgram.bmp new file mode 100644 index 0000000..5b2b937 Binary files /dev/null and b/AT91SAM7S256/Resource/SUBMENU05/TestProgram.bmp differ diff --git a/AT91SAM7S256/Resource/SUBMENU05/TryMeFile.bmp b/AT91SAM7S256/Resource/SUBMENU05/TryMeFile.bmp new file mode 100644 index 0000000..6efe7a5 Binary files /dev/null and b/AT91SAM7S256/Resource/SUBMENU05/TryMeFile.bmp differ diff --git a/AT91SAM7S256/Resource/SUBMENU05/Volume.bmp b/AT91SAM7S256/Resource/SUBMENU05/Volume.bmp new file mode 100644 index 0000000..a9bc681 Binary files /dev/null and b/AT91SAM7S256/Resource/SUBMENU05/Volume.bmp differ diff --git a/AT91SAM7S256/Resource/SUBMENU05/Volume0.bmp b/AT91SAM7S256/Resource/SUBMENU05/Volume0.bmp new file mode 100644 index 0000000..97ff68a Binary files /dev/null and b/AT91SAM7S256/Resource/SUBMENU05/Volume0.bmp differ diff --git a/AT91SAM7S256/Resource/SUBMENU05/Volume1.bmp b/AT91SAM7S256/Resource/SUBMENU05/Volume1.bmp new file mode 100644 index 0000000..63b8e78 Binary files /dev/null and b/AT91SAM7S256/Resource/SUBMENU05/Volume1.bmp differ diff --git a/AT91SAM7S256/Resource/SUBMENU05/Volume2.bmp b/AT91SAM7S256/Resource/SUBMENU05/Volume2.bmp new file mode 100644 index 0000000..b9ed6a5 Binary files /dev/null and b/AT91SAM7S256/Resource/SUBMENU05/Volume2.bmp differ diff --git a/AT91SAM7S256/Resource/SUBMENU05/Volume3.bmp b/AT91SAM7S256/Resource/SUBMENU05/Volume3.bmp new file mode 100644 index 0000000..318e27c Binary files /dev/null and b/AT91SAM7S256/Resource/SUBMENU05/Volume3.bmp differ diff --git a/AT91SAM7S256/Resource/SUBMENU05/Volume4.bmp b/AT91SAM7S256/Resource/SUBMENU05/Volume4.bmp new file mode 100644 index 0000000..5e4c0ba Binary files /dev/null and b/AT91SAM7S256/Resource/SUBMENU05/Volume4.bmp differ diff --git a/AT91SAM7S256/Resource/SUBMENU05/Yes.bmp b/AT91SAM7S256/Resource/SUBMENU05/Yes.bmp new file mode 100644 index 0000000..a49fe7d Binary files /dev/null and b/AT91SAM7S256/Resource/SUBMENU05/Yes.bmp differ diff --git a/AT91SAM7S256/Resource/SUBMENU06/Delete.bmp b/AT91SAM7S256/Resource/SUBMENU06/Delete.bmp new file mode 100644 index 0000000..61b6fb4 Binary files /dev/null and b/AT91SAM7S256/Resource/SUBMENU06/Delete.bmp differ diff --git a/AT91SAM7S256/Resource/SUBMENU06/No.bmp b/AT91SAM7S256/Resource/SUBMENU06/No.bmp new file mode 100644 index 0000000..d5da68c Binary files /dev/null and b/AT91SAM7S256/Resource/SUBMENU06/No.bmp differ diff --git a/AT91SAM7S256/Resource/SUBMENU06/Run.bmp b/AT91SAM7S256/Resource/SUBMENU06/Run.bmp new file mode 100644 index 0000000..9774de5 Binary files /dev/null and b/AT91SAM7S256/Resource/SUBMENU06/Run.bmp differ diff --git a/AT91SAM7S256/Resource/SUBMENU06/Submenu06.txt b/AT91SAM7S256/Resource/SUBMENU06/Submenu06.txt new file mode 100644 index 0000000..7b9233e --- /dev/null +++ b/AT91SAM7S256/Resource/SUBMENU06/Submenu06.txt @@ -0,0 +1,28 @@ +00000001 +TRYMEFILE +_ +00009002 +6 +4 +0 +2 + + +00000011 00000021 +DELETE RUN +Delete Run +00000080 00000084 +0 8 +0 0 +0 0 +2 0 + + +00000111 00000211 +YES NO +Are_you_sure? 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b/AT91SAM7S256/Resource/SUBMENU07/Settings.bmp new file mode 100644 index 0000000..3e8a947 Binary files /dev/null and b/AT91SAM7S256/Resource/SUBMENU07/Settings.bmp differ diff --git a/AT91SAM7S256/Resource/SUBMENU07/ShowDevices.bmp b/AT91SAM7S256/Resource/SUBMENU07/ShowDevices.bmp new file mode 100644 index 0000000..34565b8 Binary files /dev/null and b/AT91SAM7S256/Resource/SUBMENU07/ShowDevices.bmp differ diff --git a/AT91SAM7S256/Resource/SUBMENU07/Submenu07.txt b/AT91SAM7S256/Resource/SUBMENU07/Submenu07.txt new file mode 100644 index 0000000..b5bfd18 --- /dev/null +++ b/AT91SAM7S256/Resource/SUBMENU07/Submenu07.txt @@ -0,0 +1,63 @@ +00000001 00000002 00000003 00000004 00000005 +SELECTDEVICES MYUNITS SHOWDEVICES VISIABILITY ONOFF +Search My_contacts Connections Visibility On/Off +00408000 00408000 00408000 00408000 00008000 +0 0 0 0 0 +0 0 0 0 0 +0 0 0 0 0 +1 1 1 1 1 + + +00000011 00000012 00000013 00000014 00000024 00000015 00000025 +BTUNKNOWN BTUNKNOWN MYUNITS0 VISIBEL INVISIBEL BTON BTOFF +_ _ Slot_0 Visible Invisible On Off +00000302 00001002 00001002 00000000 00000000 00000080 00400080 +12 0 0 11 11 3 3 +FF 0 0 EB EA EB EA +0 0 0 0 0 0 0 +1 1 1 0 0 0 0 + + +00000111 00000112 00000113 00000213 00000313 +BTUNKNOWN BTUNKNOWN MYUNITS1 MYUNITS2 MYUNITS3 +_ _ Slot_1 Slot_2 Slot_3 +00000308 00100208 00000308 00000000 00000000 +13 13 14 0 0 +F2 F2 F6 0 0 +0 0 0 0 0 +1 2 1 0 0 + + +00001111 00002111 00003111 00001112 00002112 00001113 00002113 +MYUNITS1 MYUNITS2 MYUNITS3 DELETE CONNECT CONNECT DISCONNECT +Slot_1 Slot_2 Slot_3 Remove Connect Open_stream Disconnect +00000300 00000000 00000000 00000000 00000000 00000000 00000000 +10 0 0 13 0 14 14 +F5 0 0 F1 0 EC F0 +0 0 0 0 0 0 0 +0 0 0 0 1 0 0 + + + 00012112 00022112 00032112 + MYUNITS1 MYUNITS2 MYUNITS3 + Slot_1 Slot_2 Slot_3 + 00000308 00000000 00000000 + 10 0 0 + F5 0 0 + 0 0 0 + 0 0 0 + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/AT91SAM7S256/Resource/SUBMENU07/Visiability.bmp b/AT91SAM7S256/Resource/SUBMENU07/Visiability.bmp new file mode 100644 index 0000000..611359c Binary files /dev/null and b/AT91SAM7S256/Resource/SUBMENU07/Visiability.bmp differ diff --git a/AT91SAM7S256/Resource/SUBMENU07/Visibel.bmp b/AT91SAM7S256/Resource/SUBMENU07/Visibel.bmp new file mode 100644 index 0000000..611359c Binary files /dev/null and b/AT91SAM7S256/Resource/SUBMENU07/Visibel.bmp differ diff --git a/AT91SAM7S256/Resource/SUBMENU07/Yes.bmp b/AT91SAM7S256/Resource/SUBMENU07/Yes.bmp new file mode 100644 index 0000000..a49fe7d Binary files /dev/null and b/AT91SAM7S256/Resource/SUBMENU07/Yes.bmp differ diff --git a/AT91SAM7S256/Resource/SUBMENU10/MyUnits0.bmp b/AT91SAM7S256/Resource/SUBMENU10/MyUnits0.bmp new file mode 100644 index 0000000..0bfc9d9 Binary files /dev/null and b/AT91SAM7S256/Resource/SUBMENU10/MyUnits0.bmp differ diff --git a/AT91SAM7S256/Resource/SUBMENU10/MyUnits1.bmp b/AT91SAM7S256/Resource/SUBMENU10/MyUnits1.bmp new file mode 100644 index 0000000..431568b Binary files /dev/null and b/AT91SAM7S256/Resource/SUBMENU10/MyUnits1.bmp differ diff --git a/AT91SAM7S256/Resource/SUBMENU10/MyUnits2.bmp b/AT91SAM7S256/Resource/SUBMENU10/MyUnits2.bmp new file mode 100644 index 0000000..89ef012 Binary files /dev/null and b/AT91SAM7S256/Resource/SUBMENU10/MyUnits2.bmp differ diff --git a/AT91SAM7S256/Resource/SUBMENU10/MyUnits3.bmp b/AT91SAM7S256/Resource/SUBMENU10/MyUnits3.bmp new file mode 100644 index 0000000..0b38c45 Binary files /dev/null and b/AT91SAM7S256/Resource/SUBMENU10/MyUnits3.bmp differ diff --git a/AT91SAM7S256/Resource/SUBMENU10/Submenu10.txt b/AT91SAM7S256/Resource/SUBMENU10/Submenu10.txt new file mode 100644 index 0000000..3c538ad --- /dev/null +++ b/AT91SAM7S256/Resource/SUBMENU10/Submenu10.txt @@ -0,0 +1,20 @@ +00000001 +MYUNITS0 +Slot_0 +00001002 +0 +0 +0 +1 + + +00000011 00000021 00000031 +MYUNITS1 MYUNITS2 MYUNITS3 +Slot_1 Slot_2 Slot_3 +00000380 00000000 00000000 +14 0 0 +F9 0 0 +0 0 0 +0 0 0 + + diff --git a/AT91SAM7S256/Resource/SUBMENU11/OnOff.bmp b/AT91SAM7S256/Resource/SUBMENU11/OnOff.bmp new file mode 100644 index 0000000..96dd6e3 Binary files /dev/null and b/AT91SAM7S256/Resource/SUBMENU11/OnOff.bmp differ diff --git a/AT91SAM7S256/Resource/SUBMENU11/Range.bmp b/AT91SAM7S256/Resource/SUBMENU11/Range.bmp new file mode 100644 index 0000000..53a1179 Binary files /dev/null and b/AT91SAM7S256/Resource/SUBMENU11/Range.bmp differ diff --git a/AT91SAM7S256/Resource/SUBMENU11/Range1.bmp b/AT91SAM7S256/Resource/SUBMENU11/Range1.bmp new file mode 100644 index 0000000..d26cb28 Binary files /dev/null and b/AT91SAM7S256/Resource/SUBMENU11/Range1.bmp differ diff --git a/AT91SAM7S256/Resource/SUBMENU11/Range2.bmp b/AT91SAM7S256/Resource/SUBMENU11/Range2.bmp new file mode 100644 index 0000000..a496529 Binary files /dev/null and b/AT91SAM7S256/Resource/SUBMENU11/Range2.bmp differ diff --git a/AT91SAM7S256/Resource/SUBMENU11/Range3.bmp b/AT91SAM7S256/Resource/SUBMENU11/Range3.bmp new file mode 100644 index 0000000..187121e Binary files /dev/null and b/AT91SAM7S256/Resource/SUBMENU11/Range3.bmp differ diff --git a/AT91SAM7S256/Resource/SUBMENU11/Submenu11.txt b/AT91SAM7S256/Resource/SUBMENU11/Submenu11.txt new file mode 100644 index 0000000..1d9b495 --- /dev/null +++ b/AT91SAM7S256/Resource/SUBMENU11/Submenu11.txt @@ -0,0 +1,8 @@ +00000004 00000005 +VISIABILITY ONOFF +Visiability on/off +00000100 00000100 +11 3 +F4 F4 +0 0 +0 0 diff --git a/AT91SAM7S256/Resource/SUBMENU11/TestProgram.bmp b/AT91SAM7S256/Resource/SUBMENU11/TestProgram.bmp new file mode 100644 index 0000000..5b2b937 Binary files /dev/null and b/AT91SAM7S256/Resource/SUBMENU11/TestProgram.bmp differ diff --git a/AT91SAM7S256/Resource/SUBMENU11/Visiability.bmp b/AT91SAM7S256/Resource/SUBMENU11/Visiability.bmp new file mode 100644 index 0000000..611359c Binary files /dev/null and b/AT91SAM7S256/Resource/SUBMENU11/Visiability.bmp differ diff --git a/AT91SAM7S256/Resource/TEXT/Ui.txt b/AT91SAM7S256/Resource/TEXT/Ui.txt new file mode 100644 index 0000000..98769e6 --- /dev/null +++ b/AT91SAM7S256/Resource/TEXT/Ui.txt @@ -0,0 +1,51 @@ +Connecting +Line is busy +Failed! +Connection? +Sending file +Failed! +Turning on +Failed! +Turning off +Failed! +Searching +Aborted! +Failed! +Failed! +Failed! +Memory full! +File saved +File exists +overwrite! +File deleted +Files +deleted +Running +Aborted! +Done +File error! +Deleting all +%s files! +Sound +Software +NXT +Try Me +Datalog +Passkey: +File name: +Please use port: +1 - Touch Sensor +2 - Sound Sensor +3 - Light Sensor +4 - Ultrasonic +B/C - L/R motors +Select +Select +Select +BT save data +error! +BT store is +full error! +BT unknown +addr. error! +Never diff --git a/AT91SAM7S256/Resource/TRYME PROGRAMS/Try-Light.rbt b/AT91SAM7S256/Resource/TRYME PROGRAMS/Try-Light.rbt new file mode 100644 index 0000000..1a401f8 Binary files /dev/null and b/AT91SAM7S256/Resource/TRYME PROGRAMS/Try-Light.rbt differ diff --git a/AT91SAM7S256/Resource/TRYME PROGRAMS/Try-Light.rtm b/AT91SAM7S256/Resource/TRYME PROGRAMS/Try-Light.rtm new file mode 100644 index 0000000..fe7509a Binary files /dev/null and b/AT91SAM7S256/Resource/TRYME PROGRAMS/Try-Light.rtm differ diff --git a/AT91SAM7S256/Resource/TRYME PROGRAMS/Try-Motor.rbt b/AT91SAM7S256/Resource/TRYME PROGRAMS/Try-Motor.rbt new file mode 100644 index 0000000..84cb64d Binary files /dev/null and b/AT91SAM7S256/Resource/TRYME PROGRAMS/Try-Motor.rbt differ diff --git a/AT91SAM7S256/Resource/TRYME PROGRAMS/Try-Ultrasonic.rtm b/AT91SAM7S256/Resource/TRYME PROGRAMS/Try-Ultrasonic.rtm new file mode 100644 index 0000000..89bba47 Binary files /dev/null and b/AT91SAM7S256/Resource/TRYME PROGRAMS/Try-Ultrasonic.rtm differ diff --git a/AT91SAM7S256/Resource/TRYME PROGRAMS/Woops.rso b/AT91SAM7S256/Resource/TRYME PROGRAMS/Woops.rso new file mode 100644 index 0000000..f6179d1 Binary files /dev/null and b/AT91SAM7S256/Resource/TRYME PROGRAMS/Woops.rso differ diff --git a/AT91SAM7S256/Resource/TRYME PROGRAMS/faceclosed.ric b/AT91SAM7S256/Resource/TRYME PROGRAMS/faceclosed.ric new file mode 100644 index 0000000..1f9e91d Binary files /dev/null and b/AT91SAM7S256/Resource/TRYME PROGRAMS/faceclosed.ric differ diff --git a/AT91SAM7S256/Resource/TRYME PROGRAMS/faceopen.ric b/AT91SAM7S256/Resource/TRYME PROGRAMS/faceopen.ric new file mode 100644 index 0000000..64819f0 Binary files /dev/null and b/AT91SAM7S256/Resource/TRYME PROGRAMS/faceopen.ric differ diff --git a/AT91SAM7S256/SAM7S256/Include/AT91SAM7S256.h b/AT91SAM7S256/SAM7S256/Include/AT91SAM7S256.h new file mode 100644 index 0000000..168e5ac --- /dev/null +++ b/AT91SAM7S256/SAM7S256/Include/AT91SAM7S256.h @@ -0,0 +1,1920 @@ +// ---------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// ---------------------------------------------------------------------------- +// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// ---------------------------------------------------------------------------- +// File Name : AT91SAM7S256.h +// Object : AT91SAM7S256 definitions +// Generated : AT91 SW Application Group 03/08/2005 (15:46:13) +// +// CVS Reference : /AT91SAM7S256.pl/1.8/Wed Feb 9 15:29:26 2005// +// CVS Reference : /SYS_SAM7S.pl/1.2/Tue Feb 1 17:01:52 2005// +// CVS Reference : /MC_SAM7S.pl/1.2/Tue Feb 1 17:01:00 2005// +// CVS Reference : /PMC_SAM7S_USB.pl/1.4/Tue Feb 8 13:58:22 2005// +// CVS Reference : /RSTC_SAM7S.pl/1.1/Tue Feb 1 16:16:35 2005// +// CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// +// CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// +// CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// +// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// +// CVS Reference : /UDP_6083C.pl/1.1/Mon Jan 31 13:01:46 2005// +// CVS Reference : /AIC_6075A.pl/1.1/Fri Jun 28 10:36:48 2002// +// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// +// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// +// CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// +// CVS Reference : /SPI_6088D.pl/1.2/Mon Feb 14 07:24:18 2005// +// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// +// CVS Reference : /TC_6082A.pl/1.6/Fri Feb 18 13:53:30 2005// +// CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// +// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// +// CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// +// CVS Reference : /PWM_6044D.pl/1.1/Tue Apr 27 14:53:52 2004// +// ---------------------------------------------------------------------------- + +#ifndef AT91SAM7S256_H +#define AT91SAM7S256_H + +typedef volatile unsigned int AT91_REG;// Hardware register definition + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Peripherals +// ***************************************************************************** +typedef struct _AT91S_SYS { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register + AT91_REG Reserved2[45]; // + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved3[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved4[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register + AT91_REG Reserved5[54]; // + AT91_REG PIOA_PER; // PIO Enable Register + AT91_REG PIOA_PDR; // PIO Disable Register + AT91_REG PIOA_PSR; // PIO Status Register + AT91_REG Reserved6[1]; // + AT91_REG PIOA_OER; // Output Enable Register + AT91_REG PIOA_ODR; // Output Disable Registerr + AT91_REG PIOA_OSR; // Output Status Register + AT91_REG Reserved7[1]; // + AT91_REG PIOA_IFER; // Input Filter Enable Register + AT91_REG PIOA_IFDR; // Input Filter Disable Register + AT91_REG PIOA_IFSR; // Input Filter Status Register + AT91_REG Reserved8[1]; // + AT91_REG PIOA_SODR; // Set Output Data Register + AT91_REG PIOA_CODR; // Clear Output Data Register + AT91_REG PIOA_ODSR; // Output Data Status Register + AT91_REG PIOA_PDSR; // Pin Data Status Register + AT91_REG PIOA_IER; // Interrupt Enable Register + AT91_REG PIOA_IDR; // Interrupt Disable Register + AT91_REG PIOA_IMR; // Interrupt Mask Register + AT91_REG PIOA_ISR; // Interrupt Status Register + AT91_REG PIOA_MDER; // Multi-driver Enable Register + AT91_REG PIOA_MDDR; // Multi-driver Disable Register + AT91_REG PIOA_MDSR; // Multi-driver Status Register + AT91_REG Reserved9[1]; // + AT91_REG PIOA_PPUDR; // Pull-up Disable Register + AT91_REG PIOA_PPUER; // Pull-up Enable Register + AT91_REG PIOA_PPUSR; // Pull-up Status Register + AT91_REG Reserved10[1]; // + AT91_REG PIOA_ASR; // Select A Register + AT91_REG PIOA_BSR; // Select B Register + AT91_REG PIOA_ABSR; // AB Select Status Register + AT91_REG Reserved11[9]; // + AT91_REG PIOA_OWER; // Output Write Enable Register + AT91_REG PIOA_OWDR; // Output Write Disable Register + AT91_REG PIOA_OWSR; // Output Write Status Register + AT91_REG Reserved12[469]; // + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved13[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved14[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved15[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved16[3]; // + AT91_REG PMC_PCKR[3]; // Programmable Clock Register + AT91_REG Reserved17[5]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register + AT91_REG Reserved18[36]; // + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register + AT91_REG Reserved19[5]; // + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register + AT91_REG Reserved20[5]; // + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_SYS, *AT91PS_SYS; + + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +typedef struct _AT91S_AIC { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register +} AT91S_AIC, *AT91PS_AIC; + +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive +#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode +#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral DMA Controller +// ***************************************************************************** +typedef struct _AT91S_PDC { + AT91_REG PDC_RPR; // Receive Pointer Register + AT91_REG PDC_RCR; // Receive Counter Register + AT91_REG PDC_TPR; // Transmit Pointer Register + AT91_REG PDC_TCR; // Transmit Counter Register + AT91_REG PDC_RNPR; // Receive Next Pointer Register + AT91_REG PDC_RNCR; // Receive Next Counter Register + AT91_REG PDC_TNPR; // Transmit Next Pointer Register + AT91_REG PDC_TNCR; // Transmit Next Counter Register + AT91_REG PDC_PTCR; // PDC Transfer Control Register + AT91_REG PDC_PTSR; // PDC Transfer Status Register +} AT91S_PDC, *AT91PS_PDC; + +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable +#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable +#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable +#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Debug Unit +// ***************************************************************************** +typedef struct _AT91S_DBGU { + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved0[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved1[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register +} AT91S_DBGU, *AT91PS_DBGU; + +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver +#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter +#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable +#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable +#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable +#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable +#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type +#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity +#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity +#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity +#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode +#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode +#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt +#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt +#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt +#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt +#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt +#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt +#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt +#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt +#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt +#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt +#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +typedef struct _AT91S_PIO { + AT91_REG PIO_PER; // PIO Enable Register + AT91_REG PIO_PDR; // PIO Disable Register + AT91_REG PIO_PSR; // PIO Status Register + AT91_REG Reserved0[1]; // + AT91_REG PIO_OER; // Output Enable Register + AT91_REG PIO_ODR; // Output Disable Registerr + AT91_REG PIO_OSR; // Output Status Register + AT91_REG Reserved1[1]; // + AT91_REG PIO_IFER; // Input Filter Enable Register + AT91_REG PIO_IFDR; // Input Filter Disable Register + AT91_REG PIO_IFSR; // Input Filter Status Register + AT91_REG Reserved2[1]; // + AT91_REG PIO_SODR; // Set Output Data Register + AT91_REG PIO_CODR; // Clear Output Data Register + AT91_REG PIO_ODSR; // Output Data Status Register + AT91_REG PIO_PDSR; // Pin Data Status Register + AT91_REG PIO_IER; // Interrupt Enable Register + AT91_REG PIO_IDR; // Interrupt Disable Register + AT91_REG PIO_IMR; // Interrupt Mask Register + AT91_REG PIO_ISR; // Interrupt Status Register + AT91_REG PIO_MDER; // Multi-driver Enable Register + AT91_REG PIO_MDDR; // Multi-driver Disable Register + AT91_REG PIO_MDSR; // Multi-driver Status Register + AT91_REG Reserved3[1]; // + AT91_REG PIO_PPUDR; // Pull-up Disable Register + AT91_REG PIO_PPUER; // Pull-up Enable Register + AT91_REG PIO_PPUSR; // Pull-up Status Register + AT91_REG Reserved4[1]; // + AT91_REG PIO_ASR; // Select A Register + AT91_REG PIO_BSR; // Select B Register + AT91_REG PIO_ABSR; // AB Select Status Register + AT91_REG Reserved5[9]; // + AT91_REG PIO_OWER; // Output Write Enable Register + AT91_REG PIO_OWDR; // Output Write Disable Register + AT91_REG PIO_OWSR; // Output Write Status Register +} AT91S_PIO, *AT91PS_PIO; + + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Clock Generator Controler +// ***************************************************************************** +typedef struct _AT91S_CKGR { + AT91_REG CKGR_MOR; // Main Oscillator Register + AT91_REG CKGR_MCFR; // Main Clock Frequency Register + AT91_REG Reserved0[1]; // + AT91_REG CKGR_PLLR; // PLL Register +} AT91S_CKGR, *AT91PS_CKGR; + +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable +#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass +#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency +#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready +// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- +#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected +#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0 +#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed +#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter +#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range +#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier +#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks +#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output +#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 +#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Management Controler +// ***************************************************************************** +typedef struct _AT91S_PMC { + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved0[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved1[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved2[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved3[3]; // + AT91_REG PMC_PCKR[3]; // Programmable Clock Register + AT91_REG Reserved4[5]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register +} AT91S_PMC, *AT91PS_PMC; + +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock +#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock +#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection +#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected +#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected +#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected +#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler +#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock +#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2 +#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4 +#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8 +#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16 +#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32 +#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64 +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask +#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask +#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Reset Controller Interface +// ***************************************************************************** +typedef struct _AT91S_RSTC { + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register +} AT91S_RSTC, *AT91PS_RSTC; + +// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +#define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset +#define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset +#define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset +#define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password +// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +#define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status +#define AT91C_RSTC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brownout Detection Status +#define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type +#define AT91C_RSTC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. +#define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. +#define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low. +#define AT91C_RSTC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brownout Reset occured. +#define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level +#define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress. +// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +#define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable +#define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable +#define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable +#define AT91C_RSTC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_RTTC { + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register +} AT91S_RTTC, *AT91PS_RTTC; + +// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +#define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value +#define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable +#define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable +#define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart +// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +#define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value +// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +#define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value +// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +#define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status +#define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_PITC { + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register +} AT91S_PITC, *AT91PS_PITC; + +// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +#define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value +#define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled +#define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable +// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +#define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status +// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +#define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value +#define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter +// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_WDTC { + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register +} AT91S_WDTC, *AT91PS_WDTC; + +// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +#define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart +#define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password +// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +#define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable +#define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable +#define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable +#define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value +#define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt +#define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt +// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +#define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow +#define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface +// ***************************************************************************** +typedef struct _AT91S_VREG { + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_VREG, *AT91PS_VREG; + +// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- +#define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Memory Controller Interface +// ***************************************************************************** +typedef struct _AT91S_MC { + AT91_REG MC_RCR; // MC Remap Control Register + AT91_REG MC_ASR; // MC Abort Status Register + AT91_REG MC_AASR; // MC Abort Address Status Register + AT91_REG Reserved0[21]; // + AT91_REG MC_FMR; // MC Flash Mode Register + AT91_REG MC_FCR; // MC Flash Command Register + AT91_REG MC_FSR; // MC Flash Status Register +} AT91S_MC, *AT91PS_MC; + +// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit +// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status +#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status +#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status +#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte +#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word +#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word +#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status +#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read +#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write +#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch +#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source +#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source +#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source +#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source +// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- +#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready +#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error +#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error +#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming +#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State +#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations +#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations +#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations +#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations +#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number +// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- +#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command +#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN. +#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. +#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. +#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits. +#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits. +#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit. +#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number +#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key +// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- +#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status +#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status +#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status +#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status +#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status +#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status +#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status +#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status +#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status +#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status +#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status +#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status +#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status +#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status +#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status +#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status +#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status +#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status +#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status +#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status +#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status +#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status +#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +typedef struct _AT91S_SPI { + AT91_REG SPI_CR; // Control Register + AT91_REG SPI_MR; // Mode Register + AT91_REG SPI_RDR; // Receive Data Register + AT91_REG SPI_TDR; // Transmit Data Register + AT91_REG SPI_SR; // Status Register + AT91_REG SPI_IER; // Interrupt Enable Register + AT91_REG SPI_IDR; // Interrupt Disable Register + AT91_REG SPI_IMR; // Interrupt Mask Register + AT91_REG Reserved0[4]; // + AT91_REG SPI_CSR[4]; // Chip Select Register + AT91_REG Reserved1[48]; // + AT91_REG SPI_RPR; // Receive Pointer Register + AT91_REG SPI_RCR; // Receive Counter Register + AT91_REG SPI_TPR; // Transmit Pointer Register + AT91_REG SPI_TCR; // Transmit Counter Register + AT91_REG SPI_RNPR; // Receive Next Pointer Register + AT91_REG SPI_RNCR; // Receive Next Counter Register + AT91_REG SPI_TNPR; // Transmit Next Pointer Register + AT91_REG SPI_TNCR; // Transmit Next Counter Register + AT91_REG SPI_PTCR; // PDC Transfer Control Register + AT91_REG SPI_PTSR; // PDC Transfer Status Register +} AT91S_SPI, *AT91PS_SPI; + +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset +#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt +#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt +#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer +#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// ***************************************************************************** +typedef struct _AT91S_ADC { + AT91_REG ADC_CR; // ADC Control Register + AT91_REG ADC_MR; // ADC Mode Register + AT91_REG Reserved0[2]; // + AT91_REG ADC_CHER; // ADC Channel Enable Register + AT91_REG ADC_CHDR; // ADC Channel Disable Register + AT91_REG ADC_CHSR; // ADC Channel Status Register + AT91_REG ADC_SR; // ADC Status Register + AT91_REG ADC_LCDR; // ADC Last Converted Data Register + AT91_REG ADC_IER; // ADC Interrupt Enable Register + AT91_REG ADC_IDR; // ADC Interrupt Disable Register + AT91_REG ADC_IMR; // ADC Interrupt Mask Register + AT91_REG ADC_CDR0; // ADC Channel Data Register 0 + AT91_REG ADC_CDR1; // ADC Channel Data Register 1 + AT91_REG ADC_CDR2; // ADC Channel Data Register 2 + AT91_REG ADC_CDR3; // ADC Channel Data Register 3 + AT91_REG ADC_CDR4; // ADC Channel Data Register 4 + AT91_REG ADC_CDR5; // ADC Channel Data Register 5 + AT91_REG ADC_CDR6; // ADC Channel Data Register 6 + AT91_REG ADC_CDR7; // ADC Channel Data Register 7 + AT91_REG Reserved1[44]; // + AT91_REG ADC_RPR; // Receive Pointer Register + AT91_REG ADC_RCR; // Receive Counter Register + AT91_REG ADC_TPR; // Transmit Pointer Register + AT91_REG ADC_TCR; // Transmit Counter Register + AT91_REG ADC_RNPR; // Receive Next Pointer Register + AT91_REG ADC_RNCR; // Receive Next Counter Register + AT91_REG ADC_TNPR; // Transmit Next Pointer Register + AT91_REG ADC_TNCR; // Transmit Next Counter Register + AT91_REG ADC_PTCR; // PDC Transfer Control Register + AT91_REG ADC_PTSR; // PDC Transfer Status Register +} AT91S_ADC, *AT91PS_ADC; + +// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset +#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion +// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable +#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. +#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection +#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 +#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 +#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 +#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 +#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 +#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 +#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger +#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution. +#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution +#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution +#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode +#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection +#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time +#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time +// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0 +#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1 +#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2 +#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3 +#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4 +#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5 +#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6 +#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7 +// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion +#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion +#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion +#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion +#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion +#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion +#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion +#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion +#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error +#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error +#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error +#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error +#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error +#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error +#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error +#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error +#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready +#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun +#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer +#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt +// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted +// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data +// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// ***************************************************************************** +typedef struct _AT91S_SSC { + AT91_REG SSC_CR; // Control Register + AT91_REG SSC_CMR; // Clock Mode Register + AT91_REG Reserved0[2]; // + AT91_REG SSC_RCMR; // Receive Clock ModeRegister + AT91_REG SSC_RFMR; // Receive Frame Mode Register + AT91_REG SSC_TCMR; // Transmit Clock Mode Register + AT91_REG SSC_TFMR; // Transmit Frame Mode Register + AT91_REG SSC_RHR; // Receive Holding Register + AT91_REG SSC_THR; // Transmit Holding Register + AT91_REG Reserved1[2]; // + AT91_REG SSC_RSHR; // Receive Sync Holding Register + AT91_REG SSC_TSHR; // Transmit Sync Holding Register + AT91_REG Reserved2[2]; // + AT91_REG SSC_SR; // Status Register + AT91_REG SSC_IER; // Interrupt Enable Register + AT91_REG SSC_IDR; // Interrupt Disable Register + AT91_REG SSC_IMR; // Interrupt Mask Register + AT91_REG Reserved3[44]; // + AT91_REG SSC_RPR; // Receive Pointer Register + AT91_REG SSC_RCR; // Receive Counter Register + AT91_REG SSC_TPR; // Transmit Pointer Register + AT91_REG SSC_TCR; // Transmit Counter Register + AT91_REG SSC_RNPR; // Receive Next Pointer Register + AT91_REG SSC_RNCR; // Receive Next Counter Register + AT91_REG SSC_TNPR; // Transmit Next Pointer Register + AT91_REG SSC_TNCR; // Transmit Next Counter Register + AT91_REG SSC_PTCR; // PDC Transfer Control Register + AT91_REG SSC_PTSR; // PDC Transfer Status Register +} AT91S_SSC, *AT91PS_SSC; + +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable +#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable +#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable +#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable +#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection +#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock +#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal +#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin +#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection +#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output +#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion +#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection +#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start +#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input +#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input +#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input +#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input +#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input +#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input +#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0 +#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay +#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length +#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode +#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First +#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame +#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length +#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection +#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value +#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready +#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty +#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission +#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty +#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready +#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun +#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception +#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full +#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync +#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync +#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable +#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +typedef struct _AT91S_USART { + AT91_REG US_CR; // Control Register + AT91_REG US_MR; // Mode Register + AT91_REG US_IER; // Interrupt Enable Register + AT91_REG US_IDR; // Interrupt Disable Register + AT91_REG US_IMR; // Interrupt Mask Register + AT91_REG US_CSR; // Channel Status Register + AT91_REG US_RHR; // Receiver Holding Register + AT91_REG US_THR; // Transmitter Holding Register + AT91_REG US_BRGR; // Baud Rate Generator Register + AT91_REG US_RTOR; // Receiver Time-out Register + AT91_REG US_TTGR; // Transmitter Time-guard Register + AT91_REG Reserved0[5]; // + AT91_REG US_FIDI; // FI_DI_Ratio Register + AT91_REG US_NER; // Nb Errors Register + AT91_REG Reserved1[1]; // + AT91_REG US_IF; // IRDA_FILTER Register + AT91_REG Reserved2[44]; // + AT91_REG US_RPR; // Receive Pointer Register + AT91_REG US_RCR; // Receive Counter Register + AT91_REG US_TPR; // Transmit Pointer Register + AT91_REG US_TCR; // Transmit Counter Register + AT91_REG US_RNPR; // Receive Next Pointer Register + AT91_REG US_RNCR; // Receive Next Counter Register + AT91_REG US_TNPR; // Transmit Next Pointer Register + AT91_REG US_TNCR; // Transmit Next Counter Register + AT91_REG US_PTCR; // PDC Transfer Control Register + AT91_REG US_PTSR; // PDC Transfer Status Register +} AT91S_USART, *AT91PS_USART; + +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address +#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations +#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge +#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out +#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable +#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable +#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable +#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode +#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal +#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485 +#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking +#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem +#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0 +#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1 +#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA +#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking +#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order +#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select +#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode +#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge +#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK +#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions +#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached +#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge +#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag +#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag +#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag +#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input +#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input +#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input +#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Two-wire Interface +// ***************************************************************************** +typedef struct _AT91S_TWI { + AT91_REG TWI_CR; // Control Register + AT91_REG TWI_MMR; // Master Mode Register + AT91_REG Reserved0[1]; // + AT91_REG TWI_IADR; // Internal Address Register + AT91_REG TWI_CWGR; // Clock Waveform Generator Register + AT91_REG Reserved1[3]; // + AT91_REG TWI_SR; // Status Register + AT91_REG TWI_IER; // Interrupt Enable Register + AT91_REG TWI_IDR; // Interrupt Disable Register + AT91_REG TWI_IMR; // Interrupt Mask Register + AT91_REG TWI_RHR; // Receive Holding Register + AT91_REG TWI_THR; // Transmit Holding Register +} AT91S_TWI, *AT91PS_TWI; + +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition +#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition +#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled +#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled +#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size +#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address +#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address +#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address +#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address +#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction +#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider +#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider +#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY +#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error +#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error +#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +typedef struct _AT91S_TC { + AT91_REG TC_CCR; // Channel Control Register + AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) + AT91_REG Reserved0[2]; // + AT91_REG TC_CV; // Counter Value + AT91_REG TC_RA; // Register A + AT91_REG TC_RB; // Register B + AT91_REG TC_RC; // Register C + AT91_REG TC_SR; // Status Register + AT91_REG TC_IER; // Interrupt Enable Register + AT91_REG TC_IDR; // Interrupt Disable Register + AT91_REG TC_IMR; // Interrupt Mask Register +} AT91S_TC, *AT91PS_TC; + +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK +#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0 +#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1 +#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2 +#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert +#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection +#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal +#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock +#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock +#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock +#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading +#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading +#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection +#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None +#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection +#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC) +#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection +#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None +#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection +#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None +#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA +#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger +#define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +typedef struct _AT91S_TCB { + AT91S_TC TCB_TC0; // TC Channel 0 + AT91_REG Reserved0[4]; // + AT91S_TC TCB_TC1; // TC Channel 1 + AT91_REG Reserved1[4]; // + AT91S_TC TCB_TC2; // TC Channel 2 + AT91_REG Reserved2[4]; // + AT91_REG TCB_BCR; // TC Block Control Register + AT91_REG TCB_BMR; // TC Block Mode Register +} AT91S_TCB, *AT91PS_TCB; + +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR PWMC Channel Interface +// ***************************************************************************** +typedef struct _AT91S_PWMC_CH { + AT91_REG PWMC_CMR; // Channel Mode Register + AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register + AT91_REG PWMC_CPRDR; // Channel Period Register + AT91_REG PWMC_CCNTR; // Channel Counter Register + AT91_REG PWMC_CUPDR; // Channel Update Register + AT91_REG PWMC_Reserved[3]; // Reserved +} AT91S_PWMC_CH, *AT91PS_PWMC_CH; + +// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- +#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx +#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH) +#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment +#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity +#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period +// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- +#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle +// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- +#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period +// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- +#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter +// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- +#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface +// ***************************************************************************** +typedef struct _AT91S_PWMC { + AT91_REG PWMC_MR; // PWMC Mode Register + AT91_REG PWMC_ENA; // PWMC Enable Register + AT91_REG PWMC_DIS; // PWMC Disable Register + AT91_REG PWMC_SR; // PWMC Status Register + AT91_REG PWMC_IER; // PWMC Interrupt Enable Register + AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register + AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register + AT91_REG PWMC_ISR; // PWMC Interrupt Status Register + AT91_REG Reserved0[55]; // + AT91_REG PWMC_VR; // PWMC Version Register + AT91_REG Reserved1[64]; // + AT91S_PWMC_CH PWMC_CH[32]; // PWMC Channel 0 +} AT91S_PWMC, *AT91PS_PWMC; + +// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- +#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor. +#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A +#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC) +#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor. +#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B +#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC) +// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- +#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0 +#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1 +#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2 +#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3 +#define AT91C_PWMC_CHID4 ((unsigned int) 0x1 << 4) // (PWMC) Channel ID 4 +#define AT91C_PWMC_CHID5 ((unsigned int) 0x1 << 5) // (PWMC) Channel ID 5 +#define AT91C_PWMC_CHID6 ((unsigned int) 0x1 << 6) // (PWMC) Channel ID 6 +#define AT91C_PWMC_CHID7 ((unsigned int) 0x1 << 7) // (PWMC) Channel ID 7 +// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- +// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- +// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- +// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- +// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- +// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Device Interface +// ***************************************************************************** +typedef struct _AT91S_UDP { + AT91_REG UDP_NUM; // Frame Number Register + AT91_REG UDP_GLBSTATE; // Global State Register + AT91_REG UDP_FADDR; // Function Address Register + AT91_REG Reserved0[1]; // + AT91_REG UDP_IER; // Interrupt Enable Register + AT91_REG UDP_IDR; // Interrupt Disable Register + AT91_REG UDP_IMR; // Interrupt Mask Register + AT91_REG UDP_ISR; // Interrupt Status Register + AT91_REG UDP_ICR; // Interrupt Clear Register + AT91_REG Reserved1[1]; // + AT91_REG UDP_RSTEP; // Reset Endpoint Register + AT91_REG Reserved2[1]; // + AT91_REG UDP_CSR[8]; // Endpoint Control and Status Register + AT91_REG UDP_FDR[8]; // Endpoint FIFO Data Register + AT91_REG Reserved3[1]; // + AT91_REG UDP_TXVC; // Transceiver Control Register +} AT91S_UDP, *AT91PS_UDP; + +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats +#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error +#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable +#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured +#define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume +#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host +#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value +#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt +#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt +#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt +#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt +#define AT91C_UDP_EPINT6 ((unsigned int) 0x1 << 6) // (UDP) Endpoint 6 Interrupt +#define AT91C_UDP_EPINT7 ((unsigned int) 0x1 << 7) // (UDP) Endpoint 7 Interrupt +#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt +#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt +#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt +#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt +#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0 +#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1 +#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2 +#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3 +#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4 +#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5 +#define AT91C_UDP_EP6 ((unsigned int) 0x1 << 6) // (UDP) Reset Endpoint 6 +#define AT91C_UDP_EP7 ((unsigned int) 0x1 << 7) // (UDP) Reset Endpoint 7 +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR +#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0 +#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) +#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) +#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready +#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction +#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type +#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control +#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT +#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT +#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT +#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN +#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN +#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN +#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle +#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable +#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO +// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- +#define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP) +#define AT91C_UDP_PUON ((unsigned int) 0x1 << 9) // (UDP) Pull-up ON + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91SAM7S256 +// ***************************************************************************** +// ========== Register definition for SYS peripheral ========== +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register +#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) +#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register +#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register +#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register +#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register +#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register +#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register +#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register +// ========== Register definition for PDC_DBGU peripheral ========== +#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register +#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register +#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register +#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register +#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register +#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register +#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register +#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register +#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register +#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register +// ========== Register definition for DBGU peripheral ========== +#define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register +#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register +#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register +#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register +#define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register +#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register +#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register +#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register +#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register +#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register +#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register +#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register +// ========== Register definition for PIOA peripheral ========== +#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register +#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register +#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register +#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register +#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register +#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register +#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register +#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register +#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register +#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register +#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register +#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register +#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register +// ========== Register definition for CKGR peripheral ========== +#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register +#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register +#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register +// ========== Register definition for PMC peripheral ========== +#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register +#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register +#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register +#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register +#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register +#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register +#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register +#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register +#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register +#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register +#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register +#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register +#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register +#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register +#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register +// ========== Register definition for RSTC peripheral ========== +#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register +#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register +#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register +// ========== Register definition for RTTC peripheral ========== +#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register +#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register +#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register +#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register +// ========== Register definition for PITC peripheral ========== +#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register +#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register +#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register +#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register +// ========== Register definition for WDTC peripheral ========== +#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register +#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register +#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register +// ========== Register definition for VREG peripheral ========== +#define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register +// ========== Register definition for MC peripheral ========== +#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register +#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register +#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register +#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register +#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register +#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register +// ========== Register definition for PDC_SPI peripheral ========== +#define AT91C_SPI_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register +#define AT91C_SPI_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI) Transmit Pointer Register +#define AT91C_SPI_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI) Transmit Counter Register +#define AT91C_SPI_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI) Receive Counter Register +#define AT91C_SPI_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register +#define AT91C_SPI_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register +#define AT91C_SPI_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI) Receive Pointer Register +#define AT91C_SPI_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register +#define AT91C_SPI_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI) Receive Next Counter Register +#define AT91C_SPI_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register +// ========== Register definition for SPI peripheral ========== +#define AT91C_SPI_IER ((AT91_REG *) 0xFFFE0014) // (SPI) Interrupt Enable Register +#define AT91C_SPI_SR ((AT91_REG *) 0xFFFE0010) // (SPI) Status Register +#define AT91C_SPI_IDR ((AT91_REG *) 0xFFFE0018) // (SPI) Interrupt Disable Register +#define AT91C_SPI_CR ((AT91_REG *) 0xFFFE0000) // (SPI) Control Register +#define AT91C_SPI_MR ((AT91_REG *) 0xFFFE0004) // (SPI) Mode Register +#define AT91C_SPI_IMR ((AT91_REG *) 0xFFFE001C) // (SPI) Interrupt Mask Register +#define AT91C_SPI_TDR ((AT91_REG *) 0xFFFE000C) // (SPI) Transmit Data Register +#define AT91C_SPI_RDR ((AT91_REG *) 0xFFFE0008) // (SPI) Receive Data Register +#define AT91C_SPI_CSR ((AT91_REG *) 0xFFFE0030) // (SPI) Chip Select Register +// ========== Register definition for PDC_ADC peripheral ========== +#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register +#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register +#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register +#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register +#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register +#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register +#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register +#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register +#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register +#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register +// ========== Register definition for ADC peripheral ========== +#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 +#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 +#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 +#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 +#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register +#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register +#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 +#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 +#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register +#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register +#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register +#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 +#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 +#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register +#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register +#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register +#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register +#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register +// ========== Register definition for PDC_SSC peripheral ========== +#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register +#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register +#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register +#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register +#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register +#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register +#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register +#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register +#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register +#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register +// ========== Register definition for SSC peripheral ========== +#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register +#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register +#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register +#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register +#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register +#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister +#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register +#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register +#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register +#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register +#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register +#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register +#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register +#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register +#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register +#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register +#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register +#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register +#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register +#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register +#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register +#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register +#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register +#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register +#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register +#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register +#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register +#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register +#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register +#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register +#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register +#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register +#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register +#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register +#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register +#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register +#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register +#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register +#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register +#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register +#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register +#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register +#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register +#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register +#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register +#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register +#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register +#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register +#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register +#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register +#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register +#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register +// ========== Register definition for TWI peripheral ========== +#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register +#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register +#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register +#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register +#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register +#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register +#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register +#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register +#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register +#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register +#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C +#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B +#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register +#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A +#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value +#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B +#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register +#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register +#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A +#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C +#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register +#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value +#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A +#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B +#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C +#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register +// ========== Register definition for TCB peripheral ========== +#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register +#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register +// ========== Register definition for PWMC_CH3 peripheral ========== +#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register +#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved +#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register +#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register +#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register +#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register +// ========== Register definition for PWMC_CH2 peripheral ========== +#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved +#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register +#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register +#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register +#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register +#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH1 peripheral ========== +#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved +#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register +#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register +#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register +#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register +#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register +// ========== Register definition for PWMC_CH0 peripheral ========== +#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved +#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register +#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register +#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register +#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register +#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register +// ========== Register definition for PWMC peripheral ========== +#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register +#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register +#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register +#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register +#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register +#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register +#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register +#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register +#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register +// ========== Register definition for UDP peripheral ========== +#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register +#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register +#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register +#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register +#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register +#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register +#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register +#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register +#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register +#define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register +#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register +#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91SAM7S256 +// ***************************************************************************** +#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_PWM0 ((unsigned int) AT91C_PIO_PA0) // PWM Channel 0 +#define AT91C_PA0_TIOA0 ((unsigned int) AT91C_PIO_PA0) // Timer Counter 0 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_PWM1 ((unsigned int) AT91C_PIO_PA1) // PWM Channel 1 +#define AT91C_PA1_TIOB0 ((unsigned int) AT91C_PIO_PA1) // Timer Counter 0 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10 +#define AT91C_PA10_DTXD ((unsigned int) AT91C_PIO_PA10) // DBGU Debug Transmit Data +#define AT91C_PA10_NPCS2 ((unsigned int) AT91C_PIO_PA10) // SPI Peripheral Chip Select 2 +#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11 +#define AT91C_PA11_NPCS0 ((unsigned int) AT91C_PIO_PA11) // SPI Peripheral Chip Select 0 +#define AT91C_PA11_PWM0 ((unsigned int) AT91C_PIO_PA11) // PWM Channel 0 +#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12 +#define AT91C_PA12_MISO ((unsigned int) AT91C_PIO_PA12) // SPI Master In Slave +#define AT91C_PA12_PWM1 ((unsigned int) AT91C_PIO_PA12) // PWM Channel 1 +#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13 +#define AT91C_PA13_MOSI ((unsigned int) AT91C_PIO_PA13) // SPI Master Out Slave +#define AT91C_PA13_PWM2 ((unsigned int) AT91C_PIO_PA13) // PWM Channel 2 +#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14 +#define AT91C_PA14_SPCK ((unsigned int) AT91C_PIO_PA14) // SPI Serial Clock +#define AT91C_PA14_PWM3 ((unsigned int) AT91C_PIO_PA14) // PWM Channel 3 +#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15 +#define AT91C_PA15_TF ((unsigned int) AT91C_PIO_PA15) // SSC Transmit Frame Sync +#define AT91C_PA15_TIOA1 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 1 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16 +#define AT91C_PA16_TK ((unsigned int) AT91C_PIO_PA16) // SSC Transmit Clock +#define AT91C_PA16_TIOB1 ((unsigned int) AT91C_PIO_PA16) // Timer Counter 1 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17 +#define AT91C_PA17_TD ((unsigned int) AT91C_PIO_PA17) // SSC Transmit data +#define AT91C_PA17_PCK1 ((unsigned int) AT91C_PIO_PA17) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18 +#define AT91C_PA18_RD ((unsigned int) AT91C_PIO_PA18) // SSC Receive Data +#define AT91C_PA18_PCK2 ((unsigned int) AT91C_PIO_PA18) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19 +#define AT91C_PA19_RK ((unsigned int) AT91C_PIO_PA19) // SSC Receive Clock +#define AT91C_PA19_FIQ ((unsigned int) AT91C_PIO_PA19) // AIC Fast Interrupt Input +#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_PWM2 ((unsigned int) AT91C_PIO_PA2) // PWM Channel 2 +#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock +#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20 +#define AT91C_PA20_RF ((unsigned int) AT91C_PIO_PA20) // SSC Receive Frame Sync +#define AT91C_PA20_IRQ0 ((unsigned int) AT91C_PIO_PA20) // External Interrupt 0 +#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21 +#define AT91C_PA21_RXD1 ((unsigned int) AT91C_PIO_PA21) // USART 1 Receive Data +#define AT91C_PA21_PCK1 ((unsigned int) AT91C_PIO_PA21) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_TXD1 ((unsigned int) AT91C_PIO_PA22) // USART 1 Transmit Data +#define AT91C_PA22_NPCS3 ((unsigned int) AT91C_PIO_PA22) // SPI Peripheral Chip Select 3 +#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_SCK1 ((unsigned int) AT91C_PIO_PA23) // USART 1 Serial Clock +#define AT91C_PA23_PWM0 ((unsigned int) AT91C_PIO_PA23) // PWM Channel 0 +#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24 +#define AT91C_PA24_RTS1 ((unsigned int) AT91C_PIO_PA24) // USART 1 Ready To Send +#define AT91C_PA24_PWM1 ((unsigned int) AT91C_PIO_PA24) // PWM Channel 1 +#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25 +#define AT91C_PA25_CTS1 ((unsigned int) AT91C_PIO_PA25) // USART 1 Clear To Send +#define AT91C_PA25_PWM2 ((unsigned int) AT91C_PIO_PA25) // PWM Channel 2 +#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26 +#define AT91C_PA26_DCD1 ((unsigned int) AT91C_PIO_PA26) // USART 1 Data Carrier Detect +#define AT91C_PA26_TIOA2 ((unsigned int) AT91C_PIO_PA26) // Timer Counter 2 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27 +#define AT91C_PA27_DTR1 ((unsigned int) AT91C_PIO_PA27) // USART 1 Data Terminal ready +#define AT91C_PA27_TIOB2 ((unsigned int) AT91C_PIO_PA27) // Timer Counter 2 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_DSR1 ((unsigned int) AT91C_PIO_PA28) // USART 1 Data Set ready +#define AT91C_PA28_TCLK1 ((unsigned int) AT91C_PIO_PA28) // Timer Counter 1 external clock input +#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29 +#define AT91C_PA29_RI1 ((unsigned int) AT91C_PIO_PA29) // USART 1 Ring Indicator +#define AT91C_PA29_TCLK2 ((unsigned int) AT91C_PIO_PA29) // Timer Counter 2 external clock input +#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_TWD ((unsigned int) AT91C_PIO_PA3) // TWI Two-wire Serial Data +#define AT91C_PA3_NPCS3 ((unsigned int) AT91C_PIO_PA3) // SPI Peripheral Chip Select 3 +#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30 +#define AT91C_PA30_IRQ1 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 1 +#define AT91C_PA30_NPCS2 ((unsigned int) AT91C_PIO_PA30) // SPI Peripheral Chip Select 2 +#define AT91C_PIO_PA31 ((unsigned int) 1 << 31) // Pin Controlled by PA31 +#define AT91C_PA31_NPCS1 ((unsigned int) AT91C_PIO_PA31) // SPI Peripheral Chip Select 1 +#define AT91C_PA31_PCK2 ((unsigned int) AT91C_PIO_PA31) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_TWCK ((unsigned int) AT91C_PIO_PA4) // TWI Two-wire Serial Clock +#define AT91C_PA4_TCLK0 ((unsigned int) AT91C_PIO_PA4) // Timer Counter 0 external clock input +#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_RXD0 ((unsigned int) AT91C_PIO_PA5) // USART 0 Receive Data +#define AT91C_PA5_NPCS3 ((unsigned int) AT91C_PIO_PA5) // SPI Peripheral Chip Select 3 +#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6 +#define AT91C_PA6_TXD0 ((unsigned int) AT91C_PIO_PA6) // USART 0 Transmit Data +#define AT91C_PA6_PCK0 ((unsigned int) AT91C_PIO_PA6) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7 +#define AT91C_PA7_RTS0 ((unsigned int) AT91C_PIO_PA7) // USART 0 Ready To Send +#define AT91C_PA7_PWM3 ((unsigned int) AT91C_PIO_PA7) // PWM Channel 3 +#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8 +#define AT91C_PA8_CTS0 ((unsigned int) AT91C_PIO_PA8) // USART 0 Clear To Send +#define AT91C_PA8_ADTRG ((unsigned int) AT91C_PIO_PA8) // ADC External Trigger +#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9 +#define AT91C_PA9_DRXD ((unsigned int) AT91C_PIO_PA9) // DBGU Debug Receive Data +#define AT91C_PA9_NPCS1 ((unsigned int) AT91C_PIO_PA9) // SPI Peripheral Chip Select 1 + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91SAM7S256 +// ***************************************************************************** +#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral +#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller +#define AT91C_ID_3_Reserved ((unsigned int) 3) // Reserved +#define AT91C_ID_ADC ((unsigned int) 4) // Analog-to-Digital Converter +#define AT91C_ID_SPI ((unsigned int) 5) // Serial Peripheral Interface +#define AT91C_ID_US0 ((unsigned int) 6) // USART 0 +#define AT91C_ID_US1 ((unsigned int) 7) // USART 1 +#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller +#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface +#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller +#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port +#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0 +#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1 +#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2 +#define AT91C_ID_15_Reserved ((unsigned int) 15) // Reserved +#define AT91C_ID_16_Reserved ((unsigned int) 16) // Reserved +#define AT91C_ID_17_Reserved ((unsigned int) 17) // Reserved +#define AT91C_ID_18_Reserved ((unsigned int) 18) // Reserved +#define AT91C_ID_19_Reserved ((unsigned int) 19) // Reserved +#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved +#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved +#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved +#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved +#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved +#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved +#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved +#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved +#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved +#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved +#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1) + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91SAM7S256 +// ***************************************************************************** +#define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address +#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address +#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address +#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address +#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address +#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address +#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address +#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address +#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address +#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address +#define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address +#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address +#define AT91C_BASE_PDC_SPI ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI) Base Address +#define AT91C_BASE_SPI ((AT91PS_SPI) 0xFFFE0000) // (SPI) Base Address +#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address +#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address +#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address +#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address +#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address +#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address +#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address +#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address +#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address +#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address +#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address +#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address +#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address +#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address +#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address +#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address +#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address +#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address +#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91SAM7S256 +// ***************************************************************************** +#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address +#define AT91C_ISRAM_SIZE ((unsigned int) 0x00010000) // Internal SRAM size in byte (64 Kbyte) +#define AT91C_IFLASH ((char *) 0x00100000) // Internal ROM base address +#define AT91C_IFLASH_SIZE ((unsigned int) 0x00040000) // Internal ROM size in byte (256 Kbyte) + +#endif diff --git a/AT91SAM7S256/SAM7S256/Include/AT91SAM7S256_inc.h b/AT91SAM7S256/SAM7S256/Include/AT91SAM7S256_inc.h new file mode 100644 index 0000000..92b28bd --- /dev/null +++ b/AT91SAM7S256/SAM7S256/Include/AT91SAM7S256_inc.h @@ -0,0 +1,1710 @@ +// ---------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// ---------------------------------------------------------------------------- +// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// ---------------------------------------------------------------------------- +// File Name : AT91SAM7S256.h +// Object : AT91SAM7S256 definitions +// Generated : AT91 SW Application Group 03/08/2005 (15:46:14) +// +// CVS Reference : /AT91SAM7S256.pl/1.8/Wed Feb 9 15:29:26 2005// +// CVS Reference : /SYS_SAM7S.pl/1.2/Tue Feb 1 17:01:52 2005// +// CVS Reference : /MC_SAM7S.pl/1.2/Tue Feb 1 17:01:00 2005// +// CVS Reference : /PMC_SAM7S_USB.pl/1.4/Tue Feb 8 13:58:22 2005// +// CVS Reference : /RSTC_SAM7S.pl/1.1/Tue Feb 1 16:16:35 2005// +// CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// +// CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// +// CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// +// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// +// CVS Reference : /UDP_6083C.pl/1.1/Mon Jan 31 13:01:46 2005// +// CVS Reference : /AIC_6075A.pl/1.1/Fri Jun 28 10:36:48 2002// +// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// +// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// +// CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// +// CVS Reference : /SPI_6088D.pl/1.2/Mon Feb 14 07:24:18 2005// +// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// +// CVS Reference : /TC_6082A.pl/1.6/Fri Feb 18 13:53:30 2005// +// CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// +// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// +// CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// +// CVS Reference : /PWM_6044D.pl/1.1/Tue Apr 27 14:53:52 2004// +// ---------------------------------------------------------------------------- + +// Hardware register definition + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Peripherals +// ***************************************************************************** + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +// *** Register offset in AT91S_AIC structure *** +#define AIC_SMR ( 0) // Source Mode Register +#define AIC_SVR (128) // Source Vector Register +#define AIC_IVR (256) // IRQ Vector Register +#define AIC_FVR (260) // FIQ Vector Register +#define AIC_ISR (264) // Interrupt Status Register +#define AIC_IPR (268) // Interrupt Pending Register +#define AIC_IMR (272) // Interrupt Mask Register +#define AIC_CISR (276) // Core Interrupt Status Register +#define AIC_IECR (288) // Interrupt Enable Command Register +#define AIC_IDCR (292) // Interrupt Disable Command Register +#define AIC_ICCR (296) // Interrupt Clear Command Register +#define AIC_ISCR (300) // Interrupt Set Command Register +#define AIC_EOICR (304) // End of Interrupt Command Register +#define AIC_SPU (308) // Spurious Vector Register +#define AIC_DCR (312) // Debug Control Register (Protect) +#define AIC_FFER (320) // Fast Forcing Enable Register +#define AIC_FFDR (324) // Fast Forcing Disable Register +#define AIC_FFSR (328) // Fast Forcing Status Register +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE (0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive +#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED (0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL (0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE (0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode +#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral DMA Controller +// ***************************************************************************** +// *** Register offset in AT91S_PDC structure *** +#define PDC_RPR ( 0) // Receive Pointer Register +#define PDC_RCR ( 4) // Receive Counter Register +#define PDC_TPR ( 8) // Transmit Pointer Register +#define PDC_TCR (12) // Transmit Counter Register +#define PDC_RNPR (16) // Receive Next Pointer Register +#define PDC_RNCR (20) // Receive Next Counter Register +#define PDC_TNPR (24) // Transmit Next Pointer Register +#define PDC_TNCR (28) // Transmit Next Counter Register +#define PDC_PTCR (32) // PDC Transfer Control Register +#define PDC_PTSR (36) // PDC Transfer Status Register +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable +#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable +#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable +#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Debug Unit +// ***************************************************************************** +// *** Register offset in AT91S_DBGU structure *** +#define DBGU_CR ( 0) // Control Register +#define DBGU_MR ( 4) // Mode Register +#define DBGU_IER ( 8) // Interrupt Enable Register +#define DBGU_IDR (12) // Interrupt Disable Register +#define DBGU_IMR (16) // Interrupt Mask Register +#define DBGU_CSR (20) // Channel Status Register +#define DBGU_RHR (24) // Receiver Holding Register +#define DBGU_THR (28) // Transmitter Holding Register +#define DBGU_BRGR (32) // Baud Rate Generator Register +#define DBGU_CIDR (64) // Chip ID Register +#define DBGU_EXID (68) // Chip ID Extension Register +#define DBGU_FNTR (72) // Force NTRST Register +#define DBGU_RPR (256) // Receive Pointer Register +#define DBGU_RCR (260) // Receive Counter Register +#define DBGU_TPR (264) // Transmit Pointer Register +#define DBGU_TCR (268) // Transmit Counter Register +#define DBGU_RNPR (272) // Receive Next Pointer Register +#define DBGU_RNCR (276) // Receive Next Counter Register +#define DBGU_TNPR (280) // Transmit Next Pointer Register +#define DBGU_TNCR (284) // Transmit Next Counter Register +#define DBGU_PTCR (288) // PDC Transfer Control Register +#define DBGU_PTSR (292) // PDC Transfer Status Register +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver +#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter +#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable +#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable +#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable +#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable +#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type +#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity +#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity +#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity +#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode +#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode +#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt +#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt +#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt +#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt +#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt +#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt +#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt +#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt +#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt +#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt +#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +// *** Register offset in AT91S_PIO structure *** +#define PIO_PER ( 0) // PIO Enable Register +#define PIO_PDR ( 4) // PIO Disable Register +#define PIO_PSR ( 8) // PIO Status Register +#define PIO_OER (16) // Output Enable Register +#define PIO_ODR (20) // Output Disable Registerr +#define PIO_OSR (24) // Output Status Register +#define PIO_IFER (32) // Input Filter Enable Register +#define PIO_IFDR (36) // Input Filter Disable Register +#define PIO_IFSR (40) // Input Filter Status Register +#define PIO_SODR (48) // Set Output Data Register +#define PIO_CODR (52) // Clear Output Data Register +#define PIO_ODSR (56) // Output Data Status Register +#define PIO_PDSR (60) // Pin Data Status Register +#define PIO_IER (64) // Interrupt Enable Register +#define PIO_IDR (68) // Interrupt Disable Register +#define PIO_IMR (72) // Interrupt Mask Register +#define PIO_ISR (76) // Interrupt Status Register +#define PIO_MDER (80) // Multi-driver Enable Register +#define PIO_MDDR (84) // Multi-driver Disable Register +#define PIO_MDSR (88) // Multi-driver Status Register +#define PIO_PPUDR (96) // Pull-up Disable Register +#define PIO_PPUER (100) // Pull-up Enable Register +#define PIO_PPUSR (104) // Pull-up Status Register +#define PIO_ASR (112) // Select A Register +#define PIO_BSR (116) // Select B Register +#define PIO_ABSR (120) // AB Select Status Register +#define PIO_OWER (160) // Output Write Enable Register +#define PIO_OWDR (164) // Output Write Disable Register +#define PIO_OWSR (168) // Output Write Status Register + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Clock Generator Controler +// ***************************************************************************** +// *** Register offset in AT91S_CKGR structure *** +#define CKGR_MOR ( 0) // Main Oscillator Register +#define CKGR_MCFR ( 4) // Main Clock Frequency Register +#define CKGR_PLLR (12) // PLL Register +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable +#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass +#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency +#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready +// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- +#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected +#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0 +#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed +#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter +#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range +#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier +#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks +#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output +#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 +#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Management Controler +// ***************************************************************************** +// *** Register offset in AT91S_PMC structure *** +#define PMC_SCER ( 0) // System Clock Enable Register +#define PMC_SCDR ( 4) // System Clock Disable Register +#define PMC_SCSR ( 8) // System Clock Status Register +#define PMC_PCER (16) // Peripheral Clock Enable Register +#define PMC_PCDR (20) // Peripheral Clock Disable Register +#define PMC_PCSR (24) // Peripheral Clock Status Register +#define PMC_MOR (32) // Main Oscillator Register +#define PMC_MCFR (36) // Main Clock Frequency Register +#define PMC_PLLR (44) // PLL Register +#define PMC_MCKR (48) // Master Clock Register +#define PMC_PCKR (64) // Programmable Clock Register +#define PMC_IER (96) // Interrupt Enable Register +#define PMC_IDR (100) // Interrupt Disable Register +#define PMC_SR (104) // Status Register +#define PMC_IMR (108) // Interrupt Mask Register +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock +#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock +#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection +#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected +#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected +#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected +#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler +#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock +#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 +#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 +#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 +#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 +#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 +#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask +#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask +#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Reset Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_RSTC structure *** +#define RSTC_RCR ( 0) // Reset Control Register +#define RSTC_RSR ( 4) // Reset Status Register +#define RSTC_RMR ( 8) // Reset Mode Register +// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset +#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset +#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset +#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password +// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status +#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status +#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type +#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. +#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. +#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low. +#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured. +#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level +#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress. +// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable +#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable +#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Enable +#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_RTTC structure *** +#define RTTC_RTMR ( 0) // Real-time Mode Register +#define RTTC_RTAR ( 4) // Real-time Alarm Register +#define RTTC_RTVR ( 8) // Real-time Value Register +#define RTTC_RTSR (12) // Real-time Status Register +// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value +#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable +#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable +#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart +// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value +// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value +// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status +#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_PITC structure *** +#define PITC_PIMR ( 0) // Period Interval Mode Register +#define PITC_PISR ( 4) // Period Interval Status Register +#define PITC_PIVR ( 8) // Period Interval Value Register +#define PITC_PIIR (12) // Period Interval Image Register +// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value +#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled +#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable +// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status +// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value +#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter +// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_WDTC structure *** +#define WDTC_WDCR ( 0) // Watchdog Control Register +#define WDTC_WDMR ( 4) // Watchdog Mode Register +#define WDTC_WDSR ( 8) // Watchdog Status Register +// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart +#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password +// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable +#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable +#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable +#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value +#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt +#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt +// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow +#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_VREG structure *** +#define VREG_MR ( 0) // Voltage Regulator Mode Register +// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- +#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Memory Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_MC structure *** +#define MC_RCR ( 0) // MC Remap Control Register +#define MC_ASR ( 4) // MC Abort Status Register +#define MC_AASR ( 8) // MC Abort Address Status Register +#define MC_FMR (96) // MC Flash Mode Register +#define MC_FCR (100) // MC Flash Command Register +#define MC_FSR (104) // MC Flash Status Register +// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit +// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status +#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status +#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status +#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte +#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word +#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word +#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status +#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read +#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write +#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch +#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source +#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source +#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source +#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source +// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- +#define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready +#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error +#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error +#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming +#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State +#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations +#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations +#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations +#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations +#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number +// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- +#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command +#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN. +#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. +#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. +#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits. +#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits. +#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit. +#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number +#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key +// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- +#define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status +#define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status +#define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status +#define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status +#define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status +#define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status +#define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status +#define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status +#define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status +#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status +#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status +#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status +#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status +#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status +#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status +#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status +#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status +#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status +#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status +#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status +#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status +#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status +#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +// *** Register offset in AT91S_SPI structure *** +#define SPI_CR ( 0) // Control Register +#define SPI_MR ( 4) // Mode Register +#define SPI_RDR ( 8) // Receive Data Register +#define SPI_TDR (12) // Transmit Data Register +#define SPI_SR (16) // Status Register +#define SPI_IER (20) // Interrupt Enable Register +#define SPI_IDR (24) // Interrupt Disable Register +#define SPI_IMR (28) // Interrupt Mask Register +#define SPI_CSR (48) // Chip Select Register +#define SPI_RPR (256) // Receive Pointer Register +#define SPI_RCR (260) // Receive Counter Register +#define SPI_TPR (264) // Transmit Pointer Register +#define SPI_TCR (268) // Transmit Counter Register +#define SPI_RNPR (272) // Receive Next Pointer Register +#define SPI_RNCR (276) // Receive Next Counter Register +#define SPI_TNPR (280) // Transmit Next Pointer Register +#define SPI_TNCR (284) // Transmit Next Counter Register +#define SPI_PTCR (288) // PDC Transfer Control Register +#define SPI_PTSR (292) // PDC Transfer Status Register +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset +#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt +#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt +#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer +#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// ***************************************************************************** +// *** Register offset in AT91S_ADC structure *** +#define ADC_CR ( 0) // ADC Control Register +#define ADC_MR ( 4) // ADC Mode Register +#define ADC_CHER (16) // ADC Channel Enable Register +#define ADC_CHDR (20) // ADC Channel Disable Register +#define ADC_CHSR (24) // ADC Channel Status Register +#define ADC_SR (28) // ADC Status Register +#define ADC_LCDR (32) // ADC Last Converted Data Register +#define ADC_IER (36) // ADC Interrupt Enable Register +#define ADC_IDR (40) // ADC Interrupt Disable Register +#define ADC_IMR (44) // ADC Interrupt Mask Register +#define ADC_CDR0 (48) // ADC Channel Data Register 0 +#define ADC_CDR1 (52) // ADC Channel Data Register 1 +#define ADC_CDR2 (56) // ADC Channel Data Register 2 +#define ADC_CDR3 (60) // ADC Channel Data Register 3 +#define ADC_CDR4 (64) // ADC Channel Data Register 4 +#define ADC_CDR5 (68) // ADC Channel Data Register 5 +#define ADC_CDR6 (72) // ADC Channel Data Register 6 +#define ADC_CDR7 (76) // ADC Channel Data Register 7 +#define ADC_RPR (256) // Receive Pointer Register +#define ADC_RCR (260) // Receive Counter Register +#define ADC_TPR (264) // Transmit Pointer Register +#define ADC_TCR (268) // Transmit Counter Register +#define ADC_RNPR (272) // Receive Next Pointer Register +#define ADC_RNCR (276) // Receive Next Counter Register +#define ADC_TNPR (280) // Transmit Next Pointer Register +#define ADC_TNCR (284) // Transmit Next Counter Register +#define ADC_PTCR (288) // PDC Transfer Control Register +#define ADC_PTSR (292) // PDC Transfer Status Register +// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset +#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion +// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable +#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. +#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection +#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 +#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 +#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 +#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 +#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 +#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 +#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger +#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution. +#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution +#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution +#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode +#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection +#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time +#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time +// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0 +#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1 +#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2 +#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3 +#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4 +#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5 +#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6 +#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7 +// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion +#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion +#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion +#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion +#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion +#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion +#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion +#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion +#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error +#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error +#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error +#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error +#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error +#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error +#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error +#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error +#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready +#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun +#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer +#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt +// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted +// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data +// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_SSC structure *** +#define SSC_CR ( 0) // Control Register +#define SSC_CMR ( 4) // Clock Mode Register +#define SSC_RCMR (16) // Receive Clock ModeRegister +#define SSC_RFMR (20) // Receive Frame Mode Register +#define SSC_TCMR (24) // Transmit Clock Mode Register +#define SSC_TFMR (28) // Transmit Frame Mode Register +#define SSC_RHR (32) // Receive Holding Register +#define SSC_THR (36) // Transmit Holding Register +#define SSC_RSHR (48) // Receive Sync Holding Register +#define SSC_TSHR (52) // Transmit Sync Holding Register +#define SSC_SR (64) // Status Register +#define SSC_IER (68) // Interrupt Enable Register +#define SSC_IDR (72) // Interrupt Disable Register +#define SSC_IMR (76) // Interrupt Mask Register +#define SSC_RPR (256) // Receive Pointer Register +#define SSC_RCR (260) // Receive Counter Register +#define SSC_TPR (264) // Transmit Pointer Register +#define SSC_TCR (268) // Transmit Counter Register +#define SSC_RNPR (272) // Receive Next Pointer Register +#define SSC_RNCR (276) // Receive Next Counter Register +#define SSC_TNPR (280) // Transmit Next Pointer Register +#define SSC_TNCR (284) // Transmit Next Counter Register +#define SSC_PTCR (288) // PDC Transfer Control Register +#define SSC_PTSR (292) // PDC Transfer Status Register +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable +#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable +#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable +#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable +#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection +#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock +#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal +#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin +#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection +#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output +#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion +#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection +#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start +#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input +#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input +#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input +#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input +#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input +#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input +#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0 +#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay +#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length +#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode +#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First +#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame +#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length +#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection +#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value +#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready +#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty +#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission +#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty +#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready +#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun +#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception +#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full +#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync +#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync +#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable +#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +// *** Register offset in AT91S_USART structure *** +#define US_CR ( 0) // Control Register +#define US_MR ( 4) // Mode Register +#define US_IER ( 8) // Interrupt Enable Register +#define US_IDR (12) // Interrupt Disable Register +#define US_IMR (16) // Interrupt Mask Register +#define US_CSR (20) // Channel Status Register +#define US_RHR (24) // Receiver Holding Register +#define US_THR (28) // Transmitter Holding Register +#define US_BRGR (32) // Baud Rate Generator Register +#define US_RTOR (36) // Receiver Time-out Register +#define US_TTGR (40) // Transmitter Time-guard Register +#define US_FIDI (64) // FI_DI_Ratio Register +#define US_NER (68) // Nb Errors Register +#define US_IF (76) // IRDA_FILTER Register +#define US_RPR (256) // Receive Pointer Register +#define US_RCR (260) // Receive Counter Register +#define US_TPR (264) // Transmit Pointer Register +#define US_TCR (268) // Transmit Counter Register +#define US_RNPR (272) // Receive Next Pointer Register +#define US_RNCR (276) // Receive Next Counter Register +#define US_TNPR (280) // Transmit Next Pointer Register +#define US_TNCR (284) // Transmit Next Counter Register +#define US_PTCR (288) // PDC Transfer Control Register +#define US_PTSR (292) // PDC Transfer Status Register +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address +#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations +#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge +#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out +#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable +#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable +#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable +#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode +#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal +#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485 +#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking +#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem +#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0 +#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1 +#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA +#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking +#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order +#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select +#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode +#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge +#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK +#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions +#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached +#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge +#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag +#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag +#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag +#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input +#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input +#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input +#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Two-wire Interface +// ***************************************************************************** +// *** Register offset in AT91S_TWI structure *** +#define TWI_CR ( 0) // Control Register +#define TWI_MMR ( 4) // Master Mode Register +#define TWI_IADR (12) // Internal Address Register +#define TWI_CWGR (16) // Clock Waveform Generator Register +#define TWI_SR (32) // Status Register +#define TWI_IER (36) // Interrupt Enable Register +#define TWI_IDR (40) // Interrupt Disable Register +#define TWI_IMR (44) // Interrupt Mask Register +#define TWI_RHR (48) // Receive Holding Register +#define TWI_THR (52) // Transmit Holding Register +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition +#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition +#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled +#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled +#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size +#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address +#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address +#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address +#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address +#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction +#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider +#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider +#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY +#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error +#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error +#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +// *** Register offset in AT91S_TC structure *** +#define TC_CCR ( 0) // Channel Control Register +#define TC_CMR ( 4) // Channel Mode Register (Capture Mode / Waveform Mode) +#define TC_CV (16) // Counter Value +#define TC_RA (20) // Register A +#define TC_RB (24) // Register B +#define TC_RC (28) // Register C +#define TC_SR (32) // Status Register +#define TC_IER (36) // Interrupt Enable Register +#define TC_IDR (40) // Interrupt Disable Register +#define TC_IMR (44) // Interrupt Mask Register +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK +#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0 +#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1 +#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2 +#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert +#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection +#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal +#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock +#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock +#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock +#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading +#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading +#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection +#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection +#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE (0x1 << 15) // (TC) +#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection +#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None +#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection +#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None +#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA +#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger +#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +// *** Register offset in AT91S_TCB structure *** +#define TCB_TC0 ( 0) // TC Channel 0 +#define TCB_TC1 (64) // TC Channel 1 +#define TCB_TC2 (128) // TC Channel 2 +#define TCB_BCR (192) // TC Block Control Register +#define TCB_BMR (196) // TC Block Mode Register +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR PWMC Channel Interface +// ***************************************************************************** +// *** Register offset in AT91S_PWMC_CH structure *** +#define PWMC_CMR ( 0) // Channel Mode Register +#define PWMC_CDTYR ( 4) // Channel Duty Cycle Register +#define PWMC_CPRDR ( 8) // Channel Period Register +#define PWMC_CCNTR (12) // Channel Counter Register +#define PWMC_CUPDR (16) // Channel Update Register +#define PWMC_Reserved (20) // Reserved +// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- +#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx +#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH) +#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment +#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity +#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period +// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- +#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle +// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- +#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period +// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- +#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter +// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- +#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_PWMC structure *** +#define PWMC_MR ( 0) // PWMC Mode Register +#define PWMC_ENA ( 4) // PWMC Enable Register +#define PWMC_DIS ( 8) // PWMC Disable Register +#define PWMC_SR (12) // PWMC Status Register +#define PWMC_IER (16) // PWMC Interrupt Enable Register +#define PWMC_IDR (20) // PWMC Interrupt Disable Register +#define PWMC_IMR (24) // PWMC Interrupt Mask Register +#define PWMC_ISR (28) // PWMC Interrupt Status Register +#define PWMC_VR (252) // PWMC Version Register +#define PWMC_CH (512) // PWMC Channel 0 +// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- +#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor. +#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A +#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC) +#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor. +#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B +#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC) +// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- +#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0 +#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1 +#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2 +#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3 +#define AT91C_PWMC_CHID4 (0x1 << 4) // (PWMC) Channel ID 4 +#define AT91C_PWMC_CHID5 (0x1 << 5) // (PWMC) Channel ID 5 +#define AT91C_PWMC_CHID6 (0x1 << 6) // (PWMC) Channel ID 6 +#define AT91C_PWMC_CHID7 (0x1 << 7) // (PWMC) Channel ID 7 +// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- +// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- +// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- +// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- +// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- +// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Device Interface +// ***************************************************************************** +// *** Register offset in AT91S_UDP structure *** +#define UDP_NUM ( 0) // Frame Number Register +#define UDP_GLBSTATE ( 4) // Global State Register +#define UDP_FADDR ( 8) // Function Address Register +#define UDP_IER (16) // Interrupt Enable Register +#define UDP_IDR (20) // Interrupt Disable Register +#define UDP_IMR (24) // Interrupt Mask Register +#define UDP_ISR (28) // Interrupt Status Register +#define UDP_ICR (32) // Interrupt Clear Register +#define UDP_RSTEP (40) // Reset Endpoint Register +#define UDP_CSR (48) // Endpoint Control and Status Register +#define UDP_FDR (80) // Endpoint FIFO Data Register +#define UDP_TXVC (116) // Transceiver Control Register +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats +#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error +#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable +#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured +#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume +#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host +#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value +#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt +#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt +#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt +#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt +#define AT91C_UDP_EPINT6 (0x1 << 6) // (UDP) Endpoint 6 Interrupt +#define AT91C_UDP_EPINT7 (0x1 << 7) // (UDP) Endpoint 7 Interrupt +#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt +#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt +#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt +#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt +#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0 +#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1 +#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2 +#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3 +#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4 +#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5 +#define AT91C_UDP_EP6 (0x1 << 6) // (UDP) Reset Endpoint 6 +#define AT91C_UDP_EP7 (0x1 << 7) // (UDP) Reset Endpoint 7 +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR +#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0 +#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) +#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) +#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready +#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction +#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type +#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control +#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT +#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT +#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT +#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN +#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN +#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN +#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle +#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable +#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO +// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- +#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP) +#define AT91C_UDP_PUON (0x1 << 9) // (UDP) Pull-up ON + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91SAM7S256 +// ***************************************************************************** +// ========== Register definition for SYS peripheral ========== +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_IVR (0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_SMR (0xFFFFF000) // (AIC) Source Mode Register +#define AT91C_AIC_FVR (0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_DCR (0xFFFFF138) // (AIC) Debug Control Register (Protect) +#define AT91C_AIC_EOICR (0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_SVR (0xFFFFF080) // (AIC) Source Vector Register +#define AT91C_AIC_FFSR (0xFFFFF148) // (AIC) Fast Forcing Status Register +#define AT91C_AIC_ICCR (0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_ISR (0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IMR (0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_IPR (0xFFFFF10C) // (AIC) Interrupt Pending Register +#define AT91C_AIC_FFER (0xFFFFF140) // (AIC) Fast Forcing Enable Register +#define AT91C_AIC_IECR (0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_ISCR (0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_FFDR (0xFFFFF144) // (AIC) Fast Forcing Disable Register +#define AT91C_AIC_CISR (0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IDCR (0xFFFFF124) // (AIC) Interrupt Disable Command Register +#define AT91C_AIC_SPU (0xFFFFF134) // (AIC) Spurious Vector Register +// ========== Register definition for PDC_DBGU peripheral ========== +#define AT91C_DBGU_TCR (0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register +#define AT91C_DBGU_RNPR (0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register +#define AT91C_DBGU_TNPR (0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register +#define AT91C_DBGU_TPR (0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register +#define AT91C_DBGU_RPR (0xFFFFF300) // (PDC_DBGU) Receive Pointer Register +#define AT91C_DBGU_RCR (0xFFFFF304) // (PDC_DBGU) Receive Counter Register +#define AT91C_DBGU_RNCR (0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register +#define AT91C_DBGU_PTCR (0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register +#define AT91C_DBGU_PTSR (0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register +#define AT91C_DBGU_TNCR (0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register +// ========== Register definition for DBGU peripheral ========== +#define AT91C_DBGU_EXID (0xFFFFF244) // (DBGU) Chip ID Extension Register +#define AT91C_DBGU_BRGR (0xFFFFF220) // (DBGU) Baud Rate Generator Register +#define AT91C_DBGU_IDR (0xFFFFF20C) // (DBGU) Interrupt Disable Register +#define AT91C_DBGU_CSR (0xFFFFF214) // (DBGU) Channel Status Register +#define AT91C_DBGU_CIDR (0xFFFFF240) // (DBGU) Chip ID Register +#define AT91C_DBGU_MR (0xFFFFF204) // (DBGU) Mode Register +#define AT91C_DBGU_IMR (0xFFFFF210) // (DBGU) Interrupt Mask Register +#define AT91C_DBGU_CR (0xFFFFF200) // (DBGU) Control Register +#define AT91C_DBGU_FNTR (0xFFFFF248) // (DBGU) Force NTRST Register +#define AT91C_DBGU_THR (0xFFFFF21C) // (DBGU) Transmitter Holding Register +#define AT91C_DBGU_RHR (0xFFFFF218) // (DBGU) Receiver Holding Register +#define AT91C_DBGU_IER (0xFFFFF208) // (DBGU) Interrupt Enable Register +// ========== Register definition for PIOA peripheral ========== +#define AT91C_PIOA_ODR (0xFFFFF414) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_SODR (0xFFFFF430) // (PIOA) Set Output Data Register +#define AT91C_PIOA_ISR (0xFFFFF44C) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_ABSR (0xFFFFF478) // (PIOA) AB Select Status Register +#define AT91C_PIOA_IER (0xFFFFF440) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_PPUDR (0xFFFFF460) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_IMR (0xFFFFF448) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_PER (0xFFFFF400) // (PIOA) PIO Enable Register +#define AT91C_PIOA_IFDR (0xFFFFF424) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_OWDR (0xFFFFF4A4) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_MDSR (0xFFFFF458) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_IDR (0xFFFFF444) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_ODSR (0xFFFFF438) // (PIOA) Output Data Status Register +#define AT91C_PIOA_PPUSR (0xFFFFF468) // (PIOA) Pull-up Status Register +#define AT91C_PIOA_OWSR (0xFFFFF4A8) // (PIOA) Output Write Status Register +#define AT91C_PIOA_BSR (0xFFFFF474) // (PIOA) Select B Register +#define AT91C_PIOA_OWER (0xFFFFF4A0) // (PIOA) Output Write Enable Register +#define AT91C_PIOA_IFER (0xFFFFF420) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_PDSR (0xFFFFF43C) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_PPUER (0xFFFFF464) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_OSR (0xFFFFF418) // (PIOA) Output Status Register +#define AT91C_PIOA_ASR (0xFFFFF470) // (PIOA) Select A Register +#define AT91C_PIOA_MDDR (0xFFFFF454) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_CODR (0xFFFFF434) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_MDER (0xFFFFF450) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PDR (0xFFFFF404) // (PIOA) PIO Disable Register +#define AT91C_PIOA_IFSR (0xFFFFF428) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_OER (0xFFFFF410) // (PIOA) Output Enable Register +#define AT91C_PIOA_PSR (0xFFFFF408) // (PIOA) PIO Status Register +// ========== Register definition for CKGR peripheral ========== +#define AT91C_CKGR_MOR (0xFFFFFC20) // (CKGR) Main Oscillator Register +#define AT91C_CKGR_PLLR (0xFFFFFC2C) // (CKGR) PLL Register +#define AT91C_CKGR_MCFR (0xFFFFFC24) // (CKGR) Main Clock Frequency Register +// ========== Register definition for PMC peripheral ========== +#define AT91C_PMC_IDR (0xFFFFFC64) // (PMC) Interrupt Disable Register +#define AT91C_PMC_MOR (0xFFFFFC20) // (PMC) Main Oscillator Register +#define AT91C_PMC_PLLR (0xFFFFFC2C) // (PMC) PLL Register +#define AT91C_PMC_PCER (0xFFFFFC10) // (PMC) Peripheral Clock Enable Register +#define AT91C_PMC_PCKR (0xFFFFFC40) // (PMC) Programmable Clock Register +#define AT91C_PMC_MCKR (0xFFFFFC30) // (PMC) Master Clock Register +#define AT91C_PMC_SCDR (0xFFFFFC04) // (PMC) System Clock Disable Register +#define AT91C_PMC_PCDR (0xFFFFFC14) // (PMC) Peripheral Clock Disable Register +#define AT91C_PMC_SCSR (0xFFFFFC08) // (PMC) System Clock Status Register +#define AT91C_PMC_PCSR (0xFFFFFC18) // (PMC) Peripheral Clock Status Register +#define AT91C_PMC_MCFR (0xFFFFFC24) // (PMC) Main Clock Frequency Register +#define AT91C_PMC_SCER (0xFFFFFC00) // (PMC) System Clock Enable Register +#define AT91C_PMC_IMR (0xFFFFFC6C) // (PMC) Interrupt Mask Register +#define AT91C_PMC_IER (0xFFFFFC60) // (PMC) Interrupt Enable Register +#define AT91C_PMC_SR (0xFFFFFC68) // (PMC) Status Register +// ========== Register definition for RSTC peripheral ========== +#define AT91C_RSTC_RCR (0xFFFFFD00) // (RSTC) Reset Control Register +#define AT91C_RSTC_RMR (0xFFFFFD08) // (RSTC) Reset Mode Register +#define AT91C_RSTC_RSR (0xFFFFFD04) // (RSTC) Reset Status Register +// ========== Register definition for RTTC peripheral ========== +#define AT91C_RTTC_RTSR (0xFFFFFD2C) // (RTTC) Real-time Status Register +#define AT91C_RTTC_RTMR (0xFFFFFD20) // (RTTC) Real-time Mode Register +#define AT91C_RTTC_RTVR (0xFFFFFD28) // (RTTC) Real-time Value Register +#define AT91C_RTTC_RTAR (0xFFFFFD24) // (RTTC) Real-time Alarm Register +// ========== Register definition for PITC peripheral ========== +#define AT91C_PITC_PIVR (0xFFFFFD38) // (PITC) Period Interval Value Register +#define AT91C_PITC_PISR (0xFFFFFD34) // (PITC) Period Interval Status Register +#define AT91C_PITC_PIIR (0xFFFFFD3C) // (PITC) Period Interval Image Register +#define AT91C_PITC_PIMR (0xFFFFFD30) // (PITC) Period Interval Mode Register +// ========== Register definition for WDTC peripheral ========== +#define AT91C_WDTC_WDCR (0xFFFFFD40) // (WDTC) Watchdog Control Register +#define AT91C_WDTC_WDSR (0xFFFFFD48) // (WDTC) Watchdog Status Register +#define AT91C_WDTC_WDMR (0xFFFFFD44) // (WDTC) Watchdog Mode Register +// ========== Register definition for VREG peripheral ========== +#define AT91C_VREG_MR (0xFFFFFD60) // (VREG) Voltage Regulator Mode Register +// ========== Register definition for MC peripheral ========== +#define AT91C_MC_ASR (0xFFFFFF04) // (MC) MC Abort Status Register +#define AT91C_MC_RCR (0xFFFFFF00) // (MC) MC Remap Control Register +#define AT91C_MC_FCR (0xFFFFFF64) // (MC) MC Flash Command Register +#define AT91C_MC_AASR (0xFFFFFF08) // (MC) MC Abort Address Status Register +#define AT91C_MC_FSR (0xFFFFFF68) // (MC) MC Flash Status Register +#define AT91C_MC_FMR (0xFFFFFF60) // (MC) MC Flash Mode Register +// ========== Register definition for PDC_SPI peripheral ========== +#define AT91C_SPI_PTCR (0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register +#define AT91C_SPI_TPR (0xFFFE0108) // (PDC_SPI) Transmit Pointer Register +#define AT91C_SPI_TCR (0xFFFE010C) // (PDC_SPI) Transmit Counter Register +#define AT91C_SPI_RCR (0xFFFE0104) // (PDC_SPI) Receive Counter Register +#define AT91C_SPI_PTSR (0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register +#define AT91C_SPI_RNPR (0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register +#define AT91C_SPI_RPR (0xFFFE0100) // (PDC_SPI) Receive Pointer Register +#define AT91C_SPI_TNCR (0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register +#define AT91C_SPI_RNCR (0xFFFE0114) // (PDC_SPI) Receive Next Counter Register +#define AT91C_SPI_TNPR (0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register +// ========== Register definition for SPI peripheral ========== +#define AT91C_SPI_IER (0xFFFE0014) // (SPI) Interrupt Enable Register +#define AT91C_SPI_SR (0xFFFE0010) // (SPI) Status Register +#define AT91C_SPI_IDR (0xFFFE0018) // (SPI) Interrupt Disable Register +#define AT91C_SPI_CR (0xFFFE0000) // (SPI) Control Register +#define AT91C_SPI_MR (0xFFFE0004) // (SPI) Mode Register +#define AT91C_SPI_IMR (0xFFFE001C) // (SPI) Interrupt Mask Register +#define AT91C_SPI_TDR (0xFFFE000C) // (SPI) Transmit Data Register +#define AT91C_SPI_RDR (0xFFFE0008) // (SPI) Receive Data Register +#define AT91C_SPI_CSR (0xFFFE0030) // (SPI) Chip Select Register +// ========== Register definition for PDC_ADC peripheral ========== +#define AT91C_ADC_PTSR (0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register +#define AT91C_ADC_PTCR (0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register +#define AT91C_ADC_TNPR (0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register +#define AT91C_ADC_TNCR (0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register +#define AT91C_ADC_RNPR (0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register +#define AT91C_ADC_RNCR (0xFFFD8114) // (PDC_ADC) Receive Next Counter Register +#define AT91C_ADC_RPR (0xFFFD8100) // (PDC_ADC) Receive Pointer Register +#define AT91C_ADC_TCR (0xFFFD810C) // (PDC_ADC) Transmit Counter Register +#define AT91C_ADC_TPR (0xFFFD8108) // (PDC_ADC) Transmit Pointer Register +#define AT91C_ADC_RCR (0xFFFD8104) // (PDC_ADC) Receive Counter Register +// ========== Register definition for ADC peripheral ========== +#define AT91C_ADC_CDR2 (0xFFFD8038) // (ADC) ADC Channel Data Register 2 +#define AT91C_ADC_CDR3 (0xFFFD803C) // (ADC) ADC Channel Data Register 3 +#define AT91C_ADC_CDR0 (0xFFFD8030) // (ADC) ADC Channel Data Register 0 +#define AT91C_ADC_CDR5 (0xFFFD8044) // (ADC) ADC Channel Data Register 5 +#define AT91C_ADC_CHDR (0xFFFD8014) // (ADC) ADC Channel Disable Register +#define AT91C_ADC_SR (0xFFFD801C) // (ADC) ADC Status Register +#define AT91C_ADC_CDR4 (0xFFFD8040) // (ADC) ADC Channel Data Register 4 +#define AT91C_ADC_CDR1 (0xFFFD8034) // (ADC) ADC Channel Data Register 1 +#define AT91C_ADC_LCDR (0xFFFD8020) // (ADC) ADC Last Converted Data Register +#define AT91C_ADC_IDR (0xFFFD8028) // (ADC) ADC Interrupt Disable Register +#define AT91C_ADC_CR (0xFFFD8000) // (ADC) ADC Control Register +#define AT91C_ADC_CDR7 (0xFFFD804C) // (ADC) ADC Channel Data Register 7 +#define AT91C_ADC_CDR6 (0xFFFD8048) // (ADC) ADC Channel Data Register 6 +#define AT91C_ADC_IER (0xFFFD8024) // (ADC) ADC Interrupt Enable Register +#define AT91C_ADC_CHER (0xFFFD8010) // (ADC) ADC Channel Enable Register +#define AT91C_ADC_CHSR (0xFFFD8018) // (ADC) ADC Channel Status Register +#define AT91C_ADC_MR (0xFFFD8004) // (ADC) ADC Mode Register +#define AT91C_ADC_IMR (0xFFFD802C) // (ADC) ADC Interrupt Mask Register +// ========== Register definition for PDC_SSC peripheral ========== +#define AT91C_SSC_TNCR (0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register +#define AT91C_SSC_RPR (0xFFFD4100) // (PDC_SSC) Receive Pointer Register +#define AT91C_SSC_RNCR (0xFFFD4114) // (PDC_SSC) Receive Next Counter Register +#define AT91C_SSC_TPR (0xFFFD4108) // (PDC_SSC) Transmit Pointer Register +#define AT91C_SSC_PTCR (0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register +#define AT91C_SSC_TCR (0xFFFD410C) // (PDC_SSC) Transmit Counter Register +#define AT91C_SSC_RCR (0xFFFD4104) // (PDC_SSC) Receive Counter Register +#define AT91C_SSC_RNPR (0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register +#define AT91C_SSC_TNPR (0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register +#define AT91C_SSC_PTSR (0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register +// ========== Register definition for SSC peripheral ========== +#define AT91C_SSC_RHR (0xFFFD4020) // (SSC) Receive Holding Register +#define AT91C_SSC_RSHR (0xFFFD4030) // (SSC) Receive Sync Holding Register +#define AT91C_SSC_TFMR (0xFFFD401C) // (SSC) Transmit Frame Mode Register +#define AT91C_SSC_IDR (0xFFFD4048) // (SSC) Interrupt Disable Register +#define AT91C_SSC_THR (0xFFFD4024) // (SSC) Transmit Holding Register +#define AT91C_SSC_RCMR (0xFFFD4010) // (SSC) Receive Clock ModeRegister +#define AT91C_SSC_IER (0xFFFD4044) // (SSC) Interrupt Enable Register +#define AT91C_SSC_TSHR (0xFFFD4034) // (SSC) Transmit Sync Holding Register +#define AT91C_SSC_SR (0xFFFD4040) // (SSC) Status Register +#define AT91C_SSC_CMR (0xFFFD4004) // (SSC) Clock Mode Register +#define AT91C_SSC_TCMR (0xFFFD4018) // (SSC) Transmit Clock Mode Register +#define AT91C_SSC_CR (0xFFFD4000) // (SSC) Control Register +#define AT91C_SSC_IMR (0xFFFD404C) // (SSC) Interrupt Mask Register +#define AT91C_SSC_RFMR (0xFFFD4014) // (SSC) Receive Frame Mode Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_RNCR (0xFFFC4114) // (PDC_US1) Receive Next Counter Register +#define AT91C_US1_PTCR (0xFFFC4120) // (PDC_US1) PDC Transfer Control Register +#define AT91C_US1_TCR (0xFFFC410C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_PTSR (0xFFFC4124) // (PDC_US1) PDC Transfer Status Register +#define AT91C_US1_TNPR (0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register +#define AT91C_US1_RCR (0xFFFC4104) // (PDC_US1) Receive Counter Register +#define AT91C_US1_RNPR (0xFFFC4110) // (PDC_US1) Receive Next Pointer Register +#define AT91C_US1_RPR (0xFFFC4100) // (PDC_US1) Receive Pointer Register +#define AT91C_US1_TNCR (0xFFFC411C) // (PDC_US1) Transmit Next Counter Register +#define AT91C_US1_TPR (0xFFFC4108) // (PDC_US1) Transmit Pointer Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_IF (0xFFFC404C) // (US1) IRDA_FILTER Register +#define AT91C_US1_NER (0xFFFC4044) // (US1) Nb Errors Register +#define AT91C_US1_RTOR (0xFFFC4024) // (US1) Receiver Time-out Register +#define AT91C_US1_CSR (0xFFFC4014) // (US1) Channel Status Register +#define AT91C_US1_IDR (0xFFFC400C) // (US1) Interrupt Disable Register +#define AT91C_US1_IER (0xFFFC4008) // (US1) Interrupt Enable Register +#define AT91C_US1_THR (0xFFFC401C) // (US1) Transmitter Holding Register +#define AT91C_US1_TTGR (0xFFFC4028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_RHR (0xFFFC4018) // (US1) Receiver Holding Register +#define AT91C_US1_BRGR (0xFFFC4020) // (US1) Baud Rate Generator Register +#define AT91C_US1_IMR (0xFFFC4010) // (US1) Interrupt Mask Register +#define AT91C_US1_FIDI (0xFFFC4040) // (US1) FI_DI_Ratio Register +#define AT91C_US1_CR (0xFFFC4000) // (US1) Control Register +#define AT91C_US1_MR (0xFFFC4004) // (US1) Mode Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_TNPR (0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register +#define AT91C_US0_RNPR (0xFFFC0110) // (PDC_US0) Receive Next Pointer Register +#define AT91C_US0_TCR (0xFFFC010C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_PTCR (0xFFFC0120) // (PDC_US0) PDC Transfer Control Register +#define AT91C_US0_PTSR (0xFFFC0124) // (PDC_US0) PDC Transfer Status Register +#define AT91C_US0_TNCR (0xFFFC011C) // (PDC_US0) Transmit Next Counter Register +#define AT91C_US0_TPR (0xFFFC0108) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_RCR (0xFFFC0104) // (PDC_US0) Receive Counter Register +#define AT91C_US0_RPR (0xFFFC0100) // (PDC_US0) Receive Pointer Register +#define AT91C_US0_RNCR (0xFFFC0114) // (PDC_US0) Receive Next Counter Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_BRGR (0xFFFC0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_NER (0xFFFC0044) // (US0) Nb Errors Register +#define AT91C_US0_CR (0xFFFC0000) // (US0) Control Register +#define AT91C_US0_IMR (0xFFFC0010) // (US0) Interrupt Mask Register +#define AT91C_US0_FIDI (0xFFFC0040) // (US0) FI_DI_Ratio Register +#define AT91C_US0_TTGR (0xFFFC0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_MR (0xFFFC0004) // (US0) Mode Register +#define AT91C_US0_RTOR (0xFFFC0024) // (US0) Receiver Time-out Register +#define AT91C_US0_CSR (0xFFFC0014) // (US0) Channel Status Register +#define AT91C_US0_RHR (0xFFFC0018) // (US0) Receiver Holding Register +#define AT91C_US0_IDR (0xFFFC000C) // (US0) Interrupt Disable Register +#define AT91C_US0_THR (0xFFFC001C) // (US0) Transmitter Holding Register +#define AT91C_US0_IF (0xFFFC004C) // (US0) IRDA_FILTER Register +#define AT91C_US0_IER (0xFFFC0008) // (US0) Interrupt Enable Register +// ========== Register definition for TWI peripheral ========== +#define AT91C_TWI_IER (0xFFFB8024) // (TWI) Interrupt Enable Register +#define AT91C_TWI_CR (0xFFFB8000) // (TWI) Control Register +#define AT91C_TWI_SR (0xFFFB8020) // (TWI) Status Register +#define AT91C_TWI_IMR (0xFFFB802C) // (TWI) Interrupt Mask Register +#define AT91C_TWI_THR (0xFFFB8034) // (TWI) Transmit Holding Register +#define AT91C_TWI_IDR (0xFFFB8028) // (TWI) Interrupt Disable Register +#define AT91C_TWI_IADR (0xFFFB800C) // (TWI) Internal Address Register +#define AT91C_TWI_MMR (0xFFFB8004) // (TWI) Master Mode Register +#define AT91C_TWI_CWGR (0xFFFB8010) // (TWI) Clock Waveform Generator Register +#define AT91C_TWI_RHR (0xFFFB8030) // (TWI) Receive Holding Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_SR (0xFFFA0020) // (TC0) Status Register +#define AT91C_TC0_RC (0xFFFA001C) // (TC0) Register C +#define AT91C_TC0_RB (0xFFFA0018) // (TC0) Register B +#define AT91C_TC0_CCR (0xFFFA0000) // (TC0) Channel Control Register +#define AT91C_TC0_CMR (0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC0_IER (0xFFFA0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RA (0xFFFA0014) // (TC0) Register A +#define AT91C_TC0_IDR (0xFFFA0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_CV (0xFFFA0010) // (TC0) Counter Value +#define AT91C_TC0_IMR (0xFFFA002C) // (TC0) Interrupt Mask Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_RB (0xFFFA0058) // (TC1) Register B +#define AT91C_TC1_CCR (0xFFFA0040) // (TC1) Channel Control Register +#define AT91C_TC1_IER (0xFFFA0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_IDR (0xFFFA0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR (0xFFFA0060) // (TC1) Status Register +#define AT91C_TC1_CMR (0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC1_RA (0xFFFA0054) // (TC1) Register A +#define AT91C_TC1_RC (0xFFFA005C) // (TC1) Register C +#define AT91C_TC1_IMR (0xFFFA006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_CV (0xFFFA0050) // (TC1) Counter Value +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_CMR (0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC2_CCR (0xFFFA0080) // (TC2) Channel Control Register +#define AT91C_TC2_CV (0xFFFA0090) // (TC2) Counter Value +#define AT91C_TC2_RA (0xFFFA0094) // (TC2) Register A +#define AT91C_TC2_RB (0xFFFA0098) // (TC2) Register B +#define AT91C_TC2_IDR (0xFFFA00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_IMR (0xFFFA00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_RC (0xFFFA009C) // (TC2) Register C +#define AT91C_TC2_IER (0xFFFA00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_SR (0xFFFA00A0) // (TC2) Status Register +// ========== Register definition for TCB peripheral ========== +#define AT91C_TCB_BMR (0xFFFA00C4) // (TCB) TC Block Mode Register +#define AT91C_TCB_BCR (0xFFFA00C0) // (TCB) TC Block Control Register +// ========== Register definition for PWMC_CH3 peripheral ========== +#define AT91C_PWMC_CH3_CUPDR (0xFFFCC270) // (PWMC_CH3) Channel Update Register +#define AT91C_PWMC_CH3_Reserved (0xFFFCC274) // (PWMC_CH3) Reserved +#define AT91C_PWMC_CH3_CPRDR (0xFFFCC268) // (PWMC_CH3) Channel Period Register +#define AT91C_PWMC_CH3_CDTYR (0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register +#define AT91C_PWMC_CH3_CCNTR (0xFFFCC26C) // (PWMC_CH3) Channel Counter Register +#define AT91C_PWMC_CH3_CMR (0xFFFCC260) // (PWMC_CH3) Channel Mode Register +// ========== Register definition for PWMC_CH2 peripheral ========== +#define AT91C_PWMC_CH2_Reserved (0xFFFCC254) // (PWMC_CH2) Reserved +#define AT91C_PWMC_CH2_CMR (0xFFFCC240) // (PWMC_CH2) Channel Mode Register +#define AT91C_PWMC_CH2_CCNTR (0xFFFCC24C) // (PWMC_CH2) Channel Counter Register +#define AT91C_PWMC_CH2_CPRDR (0xFFFCC248) // (PWMC_CH2) Channel Period Register +#define AT91C_PWMC_CH2_CUPDR (0xFFFCC250) // (PWMC_CH2) Channel Update Register +#define AT91C_PWMC_CH2_CDTYR (0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH1 peripheral ========== +#define AT91C_PWMC_CH1_Reserved (0xFFFCC234) // (PWMC_CH1) Reserved +#define AT91C_PWMC_CH1_CUPDR (0xFFFCC230) // (PWMC_CH1) Channel Update Register +#define AT91C_PWMC_CH1_CPRDR (0xFFFCC228) // (PWMC_CH1) Channel Period Register +#define AT91C_PWMC_CH1_CCNTR (0xFFFCC22C) // (PWMC_CH1) Channel Counter Register +#define AT91C_PWMC_CH1_CDTYR (0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register +#define AT91C_PWMC_CH1_CMR (0xFFFCC220) // (PWMC_CH1) Channel Mode Register +// ========== Register definition for PWMC_CH0 peripheral ========== +#define AT91C_PWMC_CH0_Reserved (0xFFFCC214) // (PWMC_CH0) Reserved +#define AT91C_PWMC_CH0_CPRDR (0xFFFCC208) // (PWMC_CH0) Channel Period Register +#define AT91C_PWMC_CH0_CDTYR (0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register +#define AT91C_PWMC_CH0_CMR (0xFFFCC200) // (PWMC_CH0) Channel Mode Register +#define AT91C_PWMC_CH0_CUPDR (0xFFFCC210) // (PWMC_CH0) Channel Update Register +#define AT91C_PWMC_CH0_CCNTR (0xFFFCC20C) // (PWMC_CH0) Channel Counter Register +// ========== Register definition for PWMC peripheral ========== +#define AT91C_PWMC_IDR (0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register +#define AT91C_PWMC_DIS (0xFFFCC008) // (PWMC) PWMC Disable Register +#define AT91C_PWMC_IER (0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register +#define AT91C_PWMC_VR (0xFFFCC0FC) // (PWMC) PWMC Version Register +#define AT91C_PWMC_ISR (0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register +#define AT91C_PWMC_SR (0xFFFCC00C) // (PWMC) PWMC Status Register +#define AT91C_PWMC_IMR (0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register +#define AT91C_PWMC_MR (0xFFFCC000) // (PWMC) PWMC Mode Register +#define AT91C_PWMC_ENA (0xFFFCC004) // (PWMC) PWMC Enable Register +// ========== Register definition for UDP peripheral ========== +#define AT91C_UDP_IMR (0xFFFB0018) // (UDP) Interrupt Mask Register +#define AT91C_UDP_FADDR (0xFFFB0008) // (UDP) Function Address Register +#define AT91C_UDP_NUM (0xFFFB0000) // (UDP) Frame Number Register +#define AT91C_UDP_FDR (0xFFFB0050) // (UDP) Endpoint FIFO Data Register +#define AT91C_UDP_ISR (0xFFFB001C) // (UDP) Interrupt Status Register +#define AT91C_UDP_CSR (0xFFFB0030) // (UDP) Endpoint Control and Status Register +#define AT91C_UDP_IDR (0xFFFB0014) // (UDP) Interrupt Disable Register +#define AT91C_UDP_ICR (0xFFFB0020) // (UDP) Interrupt Clear Register +#define AT91C_UDP_RSTEP (0xFFFB0028) // (UDP) Reset Endpoint Register +#define AT91C_UDP_TXVC (0xFFFB0074) // (UDP) Transceiver Control Register +#define AT91C_UDP_GLBSTATE (0xFFFB0004) // (UDP) Global State Register +#define AT91C_UDP_IER (0xFFFB0010) // (UDP) Interrupt Enable Register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91SAM7S256 +// ***************************************************************************** +#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_PWM0 (AT91C_PIO_PA0) // PWM Channel 0 +#define AT91C_PA0_TIOA0 (AT91C_PIO_PA0) // Timer Counter 0 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_PWM1 (AT91C_PIO_PA1) // PWM Channel 1 +#define AT91C_PA1_TIOB0 (AT91C_PIO_PA1) // Timer Counter 0 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 +#define AT91C_PA10_DTXD (AT91C_PIO_PA10) // DBGU Debug Transmit Data +#define AT91C_PA10_NPCS2 (AT91C_PIO_PA10) // SPI Peripheral Chip Select 2 +#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 +#define AT91C_PA11_NPCS0 (AT91C_PIO_PA11) // SPI Peripheral Chip Select 0 +#define AT91C_PA11_PWM0 (AT91C_PIO_PA11) // PWM Channel 0 +#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 +#define AT91C_PA12_MISO (AT91C_PIO_PA12) // SPI Master In Slave +#define AT91C_PA12_PWM1 (AT91C_PIO_PA12) // PWM Channel 1 +#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 +#define AT91C_PA13_MOSI (AT91C_PIO_PA13) // SPI Master Out Slave +#define AT91C_PA13_PWM2 (AT91C_PIO_PA13) // PWM Channel 2 +#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 +#define AT91C_PA14_SPCK (AT91C_PIO_PA14) // SPI Serial Clock +#define AT91C_PA14_PWM3 (AT91C_PIO_PA14) // PWM Channel 3 +#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 +#define AT91C_PA15_TF (AT91C_PIO_PA15) // SSC Transmit Frame Sync +#define AT91C_PA15_TIOA1 (AT91C_PIO_PA15) // Timer Counter 1 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 +#define AT91C_PA16_TK (AT91C_PIO_PA16) // SSC Transmit Clock +#define AT91C_PA16_TIOB1 (AT91C_PIO_PA16) // Timer Counter 1 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 +#define AT91C_PA17_TD (AT91C_PIO_PA17) // SSC Transmit data +#define AT91C_PA17_PCK1 (AT91C_PIO_PA17) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 +#define AT91C_PA18_RD (AT91C_PIO_PA18) // SSC Receive Data +#define AT91C_PA18_PCK2 (AT91C_PIO_PA18) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 +#define AT91C_PA19_RK (AT91C_PIO_PA19) // SSC Receive Clock +#define AT91C_PA19_FIQ (AT91C_PIO_PA19) // AIC Fast Interrupt Input +#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_PWM2 (AT91C_PIO_PA2) // PWM Channel 2 +#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock +#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 +#define AT91C_PA20_RF (AT91C_PIO_PA20) // SSC Receive Frame Sync +#define AT91C_PA20_IRQ0 (AT91C_PIO_PA20) // External Interrupt 0 +#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 +#define AT91C_PA21_RXD1 (AT91C_PIO_PA21) // USART 1 Receive Data +#define AT91C_PA21_PCK1 (AT91C_PIO_PA21) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_TXD1 (AT91C_PIO_PA22) // USART 1 Transmit Data +#define AT91C_PA22_NPCS3 (AT91C_PIO_PA22) // SPI Peripheral Chip Select 3 +#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_SCK1 (AT91C_PIO_PA23) // USART 1 Serial Clock +#define AT91C_PA23_PWM0 (AT91C_PIO_PA23) // PWM Channel 0 +#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 +#define AT91C_PA24_RTS1 (AT91C_PIO_PA24) // USART 1 Ready To Send +#define AT91C_PA24_PWM1 (AT91C_PIO_PA24) // PWM Channel 1 +#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 +#define AT91C_PA25_CTS1 (AT91C_PIO_PA25) // USART 1 Clear To Send +#define AT91C_PA25_PWM2 (AT91C_PIO_PA25) // PWM Channel 2 +#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 +#define AT91C_PA26_DCD1 (AT91C_PIO_PA26) // USART 1 Data Carrier Detect +#define AT91C_PA26_TIOA2 (AT91C_PIO_PA26) // Timer Counter 2 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 +#define AT91C_PA27_DTR1 (AT91C_PIO_PA27) // USART 1 Data Terminal ready +#define AT91C_PA27_TIOB2 (AT91C_PIO_PA27) // Timer Counter 2 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_DSR1 (AT91C_PIO_PA28) // USART 1 Data Set ready +#define AT91C_PA28_TCLK1 (AT91C_PIO_PA28) // Timer Counter 1 external clock input +#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 +#define AT91C_PA29_RI1 (AT91C_PIO_PA29) // USART 1 Ring Indicator +#define AT91C_PA29_TCLK2 (AT91C_PIO_PA29) // Timer Counter 2 external clock input +#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_TWD (AT91C_PIO_PA3) // TWI Two-wire Serial Data +#define AT91C_PA3_NPCS3 (AT91C_PIO_PA3) // SPI Peripheral Chip Select 3 +#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 +#define AT91C_PA30_IRQ1 (AT91C_PIO_PA30) // External Interrupt 1 +#define AT91C_PA30_NPCS2 (AT91C_PIO_PA30) // SPI Peripheral Chip Select 2 +#define AT91C_PIO_PA31 (1 << 31) // Pin Controlled by PA31 +#define AT91C_PA31_NPCS1 (AT91C_PIO_PA31) // SPI Peripheral Chip Select 1 +#define AT91C_PA31_PCK2 (AT91C_PIO_PA31) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_TWCK (AT91C_PIO_PA4) // TWI Two-wire Serial Clock +#define AT91C_PA4_TCLK0 (AT91C_PIO_PA4) // Timer Counter 0 external clock input +#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_RXD0 (AT91C_PIO_PA5) // USART 0 Receive Data +#define AT91C_PA5_NPCS3 (AT91C_PIO_PA5) // SPI Peripheral Chip Select 3 +#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 +#define AT91C_PA6_TXD0 (AT91C_PIO_PA6) // USART 0 Transmit Data +#define AT91C_PA6_PCK0 (AT91C_PIO_PA6) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 +#define AT91C_PA7_RTS0 (AT91C_PIO_PA7) // USART 0 Ready To Send +#define AT91C_PA7_PWM3 (AT91C_PIO_PA7) // PWM Channel 3 +#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 +#define AT91C_PA8_CTS0 (AT91C_PIO_PA8) // USART 0 Clear To Send +#define AT91C_PA8_ADTRG (AT91C_PIO_PA8) // ADC External Trigger +#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 +#define AT91C_PA9_DRXD (AT91C_PIO_PA9) // DBGU Debug Receive Data +#define AT91C_PA9_NPCS1 (AT91C_PIO_PA9) // SPI Peripheral Chip Select 1 + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91SAM7S256 +// ***************************************************************************** +#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ( 1) // System Peripheral +#define AT91C_ID_PIOA ( 2) // Parallel IO Controller +#define AT91C_ID_3_Reserved ( 3) // Reserved +#define AT91C_ID_ADC ( 4) // Analog-to-Digital Converter +#define AT91C_ID_SPI ( 5) // Serial Peripheral Interface +#define AT91C_ID_US0 ( 6) // USART 0 +#define AT91C_ID_US1 ( 7) // USART 1 +#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller +#define AT91C_ID_TWI ( 9) // Two-Wire Interface +#define AT91C_ID_PWMC (10) // PWM Controller +#define AT91C_ID_UDP (11) // USB Device Port +#define AT91C_ID_TC0 (12) // Timer Counter 0 +#define AT91C_ID_TC1 (13) // Timer Counter 1 +#define AT91C_ID_TC2 (14) // Timer Counter 2 +#define AT91C_ID_15_Reserved (15) // Reserved +#define AT91C_ID_16_Reserved (16) // Reserved +#define AT91C_ID_17_Reserved (17) // Reserved +#define AT91C_ID_18_Reserved (18) // Reserved +#define AT91C_ID_19_Reserved (19) // Reserved +#define AT91C_ID_20_Reserved (20) // Reserved +#define AT91C_ID_21_Reserved (21) // Reserved +#define AT91C_ID_22_Reserved (22) // Reserved +#define AT91C_ID_23_Reserved (23) // Reserved +#define AT91C_ID_24_Reserved (24) // Reserved +#define AT91C_ID_25_Reserved (25) // Reserved +#define AT91C_ID_26_Reserved (26) // Reserved +#define AT91C_ID_27_Reserved (27) // Reserved +#define AT91C_ID_28_Reserved (28) // Reserved +#define AT91C_ID_29_Reserved (29) // Reserved +#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1) + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91SAM7S256 +// ***************************************************************************** +#define AT91C_BASE_SYS (0xFFFFF000) // (SYS) Base Address +#define AT91C_BASE_AIC (0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_PDC_DBGU (0xFFFFF300) // (PDC_DBGU) Base Address +#define AT91C_BASE_DBGU (0xFFFFF200) // (DBGU) Base Address +#define AT91C_BASE_PIOA (0xFFFFF400) // (PIOA) Base Address +#define AT91C_BASE_CKGR (0xFFFFFC20) // (CKGR) Base Address +#define AT91C_BASE_PMC (0xFFFFFC00) // (PMC) Base Address +#define AT91C_BASE_RSTC (0xFFFFFD00) // (RSTC) Base Address +#define AT91C_BASE_RTTC (0xFFFFFD20) // (RTTC) Base Address +#define AT91C_BASE_PITC (0xFFFFFD30) // (PITC) Base Address +#define AT91C_BASE_WDTC (0xFFFFFD40) // (WDTC) Base Address +#define AT91C_BASE_VREG (0xFFFFFD60) // (VREG) Base Address +#define AT91C_BASE_MC (0xFFFFFF00) // (MC) Base Address +#define AT91C_BASE_PDC_SPI (0xFFFE0100) // (PDC_SPI) Base Address +#define AT91C_BASE_SPI (0xFFFE0000) // (SPI) Base Address +#define AT91C_BASE_PDC_ADC (0xFFFD8100) // (PDC_ADC) Base Address +#define AT91C_BASE_ADC (0xFFFD8000) // (ADC) Base Address +#define AT91C_BASE_PDC_SSC (0xFFFD4100) // (PDC_SSC) Base Address +#define AT91C_BASE_SSC (0xFFFD4000) // (SSC) Base Address +#define AT91C_BASE_PDC_US1 (0xFFFC4100) // (PDC_US1) Base Address +#define AT91C_BASE_US1 (0xFFFC4000) // (US1) Base Address +#define AT91C_BASE_PDC_US0 (0xFFFC0100) // (PDC_US0) Base Address +#define AT91C_BASE_US0 (0xFFFC0000) // (US0) Base Address +#define AT91C_BASE_TWI (0xFFFB8000) // (TWI) Base Address +#define AT91C_BASE_TC0 (0xFFFA0000) // (TC0) Base Address +#define AT91C_BASE_TC1 (0xFFFA0040) // (TC1) Base Address +#define AT91C_BASE_TC2 (0xFFFA0080) // (TC2) Base Address +#define AT91C_BASE_TCB (0xFFFA0000) // (TCB) Base Address +#define AT91C_BASE_PWMC_CH3 (0xFFFCC260) // (PWMC_CH3) Base Address +#define AT91C_BASE_PWMC_CH2 (0xFFFCC240) // (PWMC_CH2) Base Address +#define AT91C_BASE_PWMC_CH1 (0xFFFCC220) // (PWMC_CH1) Base Address +#define AT91C_BASE_PWMC_CH0 (0xFFFCC200) // (PWMC_CH0) Base Address +#define AT91C_BASE_PWMC (0xFFFCC000) // (PWMC) Base Address +#define AT91C_BASE_UDP (0xFFFB0000) // (UDP) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91SAM7S256 +// ***************************************************************************** +#define AT91C_ISRAM (0x00200000) // Internal SRAM base address +#define AT91C_ISRAM_SIZE (0x00010000) // Internal SRAM size in byte (64 Kbyte) +#define AT91C_IFLASH (0x00100000) // Internal ROM base address +#define AT91C_IFLASH_SIZE (0x00040000) // Internal ROM size in byte (256 Kbyte) + + diff --git a/AT91SAM7S256/SAM7S256/Include/Cstartup.s79 b/AT91SAM7S256/SAM7S256/Include/Cstartup.s79 new file mode 100644 index 0000000..550ae1e --- /dev/null +++ b/AT91SAM7S256/SAM7S256/Include/Cstartup.s79 @@ -0,0 +1,347 @@ +;------------------------------------------------------------------------------ +;- ATMEL Microcontroller Software Support - ROUSSET - +;------------------------------------------------------------------------------ +; The software is delivered "AS IS" without warranty or condition of any +; kind, either express, implied or statutory. This includes without +; limitation any warranty or condition with respect to merchantability or +; fitness for any particular purpose, or against the infringements of +; intellectual property rights of others. +;----------------------------------------------------------------------------- +;- File source : Cstartup.s79 +;- Object : Generic CStartup for IAR No Use REMAP +;- Compilation flag : None +;- +;- 1.0 15/Jun/04 JPP : Creation +;- 1.2 04/Feb/05 JPP : Add Copy Flash vector to RAM and remap +;- 1.3 08/Feb/05 JPP : Remap +;- 1.4 01/Apr/05 JPP : save SPSR +;------------------------------------------------------------------------------ + +#include "AT91SAM7S256_inc.h" + +#define ARM_MODE_FIQ ( 0x11) // Core Mode +#define ARM_MODE_IRQ ( 0x12) // Core Mode +#define ARM_MODE_SVC ( 0x13) // Core Mode +#define I_BIT ( 0x80) // Core Mode +#define F_BIT ( 0x40) // Core Mode + +;------------------------------------------------------------------------------ +;- Area Definition +;------------------------------------------------------------------------------ + +;--------------------------------------------------------------- +; ?RESET +; Reset Vector. +; Normally, segment INTVEC is linked at address 0. +; For debugging purposes, INTVEC may be placed at other +; addresses. +;------------------------------------------------------------- + + PROGRAM ?RESET + + RSEG ICODE:CODE:ROOT(2) + CODE32 ; Always ARM mode after reset + ORG 0 + PUBLIC reset + EXTERN InitReset + +reset +;------------------------------------------------------------------------------ +;- Program RESET +;-------------------- +;- These vectors can be read at address 0 or at RAM address +;- They ABSOLUTELY requires to be in relative addresssing mode in order to +;- guarantee a valid jump. For the moment, all are just looping. +;- If an exception occurs before remap, this would result in an infinite loop. +;- To ensure if a exeption occurs before start application to infinite loop. +;------------------------------------------------------------------------------ + + B InitReset ; 0x00 Reset handler +undefvec: + B undefvec ; 0x04 Undefined Instruction +swivec: + B swivec ; 0x08 Software Interrupt +pabtvec: + B pabtvec ; 0x0C Prefetch Abort +dabtvec: + B dabtvec ; 0x10 Data Abort +rsvdvec: + B rsvdvec ; 0x14 reserved +irqvec: + B IRQ_Handler_Entry ; 0x18 IRQ +fiqvec: ; 0x1c FIQ +;------------------------------------------------------------------------------ +;- Function : FIQ_Handler_Entry +;- Treatments : FIQ Controller Interrupt Handler. +;- Called Functions : AIC_FVR[interrupt] +;------------------------------------------------------------------------------ +FIQ_Handler_Entry: + +;- Switch in SVC/User Mode to allow User Stack access for C code +; because the FIQ is not yet acknowledged + +;- Save and r0 in FIQ_Register + mov r9,r0 + ldr r0 , [r8, #AIC_FVR] + msr CPSR_c,#I_BIT | F_BIT | ARM_MODE_SVC + +;- Save scratch/used registers and LR in User Stack + stmfd sp!, { r1-r3, r12, lr} + +;- Branch to the routine pointed by the AIC_FVR + mov r14, pc + bx r0 + +;- Restore scratch/used registers and LR from User Stack + ldmia sp!, { r1-r3, r12, lr} + +;- Leave Interrupts disabled and switch back in FIQ mode + msr CPSR_c, #I_BIT | F_BIT | ARM_MODE_FIQ + +;- Restore the R0 ARM_MODE_SVC register + mov r0,r9 + +;- Restore the Program Counter using the LR_fiq directly in the PC + subs pc,lr,#4 + +;------------------------------------------------------------------------------ +;- Manage exception +;--------------- +;- This module The exception must be ensure in ARM mode +;------------------------------------------------------------------------------ +;------------------------------------------------------------------------------ +;- Function : IRQ_Handler_Entry +;- Treatments : IRQ Controller Interrupt Handler. +;- Called Functions : AIC_IVR[interrupt] +;------------------------------------------------------------------------------ +IRQ_Handler_Entry: + +;- Manage Exception Entry +;- Adjust and save LR_irq in IRQ stack + sub lr, lr, #4 + stmfd sp!, {lr} + +;- Save SPSR need to be saved for nested interrupt + mrs r14, SPSR + stmfd sp!, {r14} + +;- Save and r0 in IRQ stack + stmfd sp!, {r0} + +;- Write in the IVR to support Protect Mode +;- No effect in Normal Mode +;- De-assert the NIRQ and clear the source in Protect Mode + ldr r14, =AT91C_BASE_AIC + ldr r0 , [r14, #AIC_IVR] + str r14, [r14, #AIC_IVR] + +;- Enable Interrupt and Switch in Supervisor Mode + msr CPSR_c, #ARM_MODE_SVC + +;- Save scratch/used registers and LR in User Stack + stmfd sp!, { r1-r3, r12, r14} + +;- Branch to the routine pointed by the AIC_IVR + mov r14, pc + bx r0 + +;- Restore scratch/used registers and LR from User Stack + ldmia sp!, { r1-r3, r12, r14} + +;- Disable Interrupt and switch back in IRQ mode + msr CPSR_c, #I_BIT | ARM_MODE_IRQ + +;- Mark the End of Interrupt on the AIC + ldr r14, =AT91C_BASE_AIC + str r14, [r14, #AIC_EOICR] + +;- Restore R0 + ldmia sp!, {r0} + +;- Restore SPSR_irq and r0 from IRQ stack + ldmia sp!, {r14} + msr SPSR_cxsf, r14 + +;- Restore adjusted LR_irq from IRQ stack directly in the PC + ldmia sp!, {pc}^ + +;--------------------------------------------------------------- +; ?EXEPTION_VECTOR +; This module is only linked if needed for closing files. +;--------------------------------------------------------------- + PUBLIC AT91F_Default_FIQ_handler + PUBLIC AT91F_Default_IRQ_handler + PUBLIC AT91F_Spurious_handler + +AT91F_Default_FIQ_handler + b AT91F_Default_FIQ_handler + +AT91F_Default_IRQ_handler + b AT91F_Default_IRQ_handler + +AT91F_Spurious_handler + b AT91F_Spurious_handler + + ENDMOD + +;------------------------------------------------------------------------------ +;- Program RESET_init +;-------------------- +;- This Program continous the initialization. +;------------------------------------------------------------------------------ + PROGRAM ?RESET_init + RSEG INTRAMEND_REMAP + RSEG INTRAMSTART + RSEG INTRAMEND_BEFORE_REMAP + + RSEG ICODE:CODE:ROOT(2) + CODE32 ; Always ARM mode after reset + PUBLIC InitReset + EXTERN AT91F_LowLevelInit + +InitReset: +;------------------------------------------------------------------------------ +;- Low level Init (PMC, AIC, ? ....) by C function AT91F_LowLevelInit +;------------------------------------------------------------------------------ + +#define __iStack_end SFB(INTRAMEND_BEFORE_REMAP) + +;- minumum C initialization +;- call AT91F_LowLevelInit( void) +; note this fonction can be write in Assembeler + + ldr r13,=__iStack_end ; temporary stack in internal RAM +;--Call Low level init function in ABSOLUTE through the Interworking + + ldr r0,=AT91F_LowLevelInit + ldr r1,=0x0000FFFF + and r0,r0,r1 + mov lr, pc + bx r0 +;--------------------------------------------------------------- +; ?CSTARTUP +;--------------------------------------------------------------- +; copy the flash code to RAM code this product use a very littel RAM +; and no need to get the code size +#define __intram SFB(INTRAMSTART) + + ldr r12, = __intram + +; get the relative address offset + EXTERN reset + +add_pc: sub r11,pc,#((add_pc+8)-InitReset) +#ifndef RAM_DEBUG +add_pc_1: sub r10,pc,#((add_pc_1+4)-reset) +; copy the UndefVec at Software vec to protect a software reset + ldr r1,[r10],#4 + str r1,[r12],#4 +#else +add_pc_1: sub r10,pc,#((add_pc_1+8)-reset) +; copy the UndefVec at Software vec to protect a software reset + ldr r1,[r10],#4 + str r1,[r12],#4 + ldr r1,[r10],#4 +#endif + str r1,[r12],#4 + +; copy next address +copy: + ldr r1,[r10],#4 + str r1,[r12],#4 + cmp r10,r11 + BNE copy + +;------------------------------------------------------------------------------ +;- Stack Sizes Definition +;------------------------ +;- Interrupt Stack requires 2 words x 8 priority level x 4 bytes when using +;- the vectoring. This assume that the IRQ management. +;- The Interrupt Stack must be adjusted depending on the interrupt handlers. +;- Fast Interrupt not requires stack If in your application it required you must +;- be definehere. +;- The System stack size is not defined and is limited by the free internal +;- SRAM. +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +;- Top of Stack Definition +;------------------------- +;- Interrupt and Supervisor Stack are located at the top of internal memory in +;- order to speed the exception handling context saving and restoring. +;- ARM_MODE_SVC (Application, C) Stack is located at the top of the external memory. +;------------------------------------------------------------------------------ + +IRQ_STACK_SIZE EQU (3*8*4) ; 3 words per interrupt priority level + + +;------------------------------------------------------------------------------ +;- Setup the stack for each mode +;------------------------------- +#define __iramend SFB(INTRAMEND_REMAP) + + ldr r0, =__iramend + +;- Set up Fast Interrupt Mode and set FIQ Mode Stack + msr CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT +;- Init the FIQ register + ldr r8, =AT91C_BASE_AIC + +;- Set up Interrupt Mode and set IRQ Mode Stack + msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT + mov r13, r0 ; Init stack IRQ + sub r0, r0, #IRQ_STACK_SIZE + +;- Enable interrupt & Set up Supervisor Mode and set Supervisor Mode Stack + msr CPSR_c, #ARM_MODE_SVC + mov r13, r0 + +;-------------------------------------------- +;- Remap Command and jump on ABSOLUT address +;-------------------------------------------- + ldr r12, PtInitRemap ; Get the real jump address ( after remap ) + ldr r0,=AT91C_MC_RCR ; Get remap address + mov r1,#1 ; Get the REMAP value + +#ifndef RAM_DEBUG + str r1,[r0] +#endif +;- Jump to LINK address at its absolut address + mov pc, r12 ; Jump and break the pipeline +PtInitRemap: + DCD InitRemap ; Address where to jump after REMAP +InitRemap: +;--------------------------------------------------------------- +; ?CSTARTUP +;--------------------------------------------------------------- + EXTERN __segment_init + EXTERN main +; Initialize segments. +; __segment_init is assumed to use +; instruction set and to be reachable by BL from the ICODE segment +; (it is safest to link them in segment ICODE). + ldr r0,=__segment_init + mov lr, pc + bx r0 + + PUBLIC __main +?jump_to_main: + ldr lr,=?call_exit + ldr r0,=main +__main: + bx r0 + +;------------------------------------------------------------------------------ +;- Loop for ever +;--------------- +;- End of application. Normally, never occur. +;- Could jump on Software Reset ( B 0x0 ). +;------------------------------------------------------------------------------ +?call_exit: +End + b End + + ENDMOD + + END + diff --git a/AT91SAM7S256/SAM7S256/Include/Cstartup_SAM7.c b/AT91SAM7S256/SAM7S256/Include/Cstartup_SAM7.c new file mode 100644 index 0000000..b23e3ac --- /dev/null +++ b/AT91SAM7S256/SAM7S256/Include/Cstartup_SAM7.c @@ -0,0 +1,88 @@ +//*---------------------------------------------------------------------------- +//* ATMEL Microcontroller Software Support - ROUSSET - +//*---------------------------------------------------------------------------- +//* The software is delivered "AS IS" without warranty or condition of any +//* kind, either express, implied or statutory. This includes without +//* limitation any warranty or condition with respect to merchantability or +//* fitness for any particular purpose, or against the infringements of +//* intellectual property rights of others. +//*---------------------------------------------------------------------------- +//* File Name : Cstartup_SAM7.c +//* Object : Low level initializations written in C for IAR Tools +//* Creation : 12/Jun/04 +//* 1.2 28/Feb/05 JPP : LIB change AT91C_WDTC_WDDIS & PLL +//* 1.3 21/Mar/05 JPP : Change PLL Wait time +//*---------------------------------------------------------------------------- + +// Include the board file description +#include "AT91SAM7S256.h" + +// The following functions must be write in ARM mode this function called directly +// by exception vector +extern void AT91F_Spurious_handler(void); +extern void AT91F_Default_IRQ_handler(void); +extern void AT91F_Default_FIQ_handler(void); + +//*---------------------------------------------------------------------------- +//* \fn AT91F_LowLevelInit +//* \brief This function performs very low level HW initialization +//* this function can be use a Stack, depending the compilation +//* optimization mode +//*---------------------------------------------------------------------------- +void AT91F_LowLevelInit( void) @ "ICODE" +{ + int i; + AT91PS_PMC pPMC = AT91C_BASE_PMC; + + //* Set Flash Waite sate + // Single Cycle Access at Up to 30 MHz, or 40 + // if MCK = 47923200 I have 72 Cycle for 1,5 usecond ( flied MC_FMR->FMCN + AT91C_BASE_MC->MC_FMR = ((AT91C_MC_FMCN)&(72 <<16)) | AT91C_MC_FWS_1FWS ; + + //* Watchdog Disable + AT91C_BASE_WDTC->WDTC_WDMR= AT91C_WDTC_WDDIS; + + //* Set MCK at 47 923 200 + // 1 Enabling the Main Oscillator: + // SCK = 1/32768 = 30.51 uSecond + // Start up time = 8 * 6 / SCK = 56 * 30.51 = 1,46484375 ms + pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x06 <<8) | AT91C_CKGR_MOSCEN )); + + // Wait the startup time + while(!(pPMC->PMC_SR & AT91C_PMC_MOSCS)); + + // 2 Checking the Main Oscillator Frequency (Optional) + // 3 Setting PLL and divider: + // - div by 14 Fin = 1.3165 =(18,432 / 14) + // - Mul 72+1: Fout = 96.1097 =(3,6864 *73) + // for 96 MHz the erroe is 0.11% + // Field out NOT USED = 0 + // PLLCOUNT pll startup time estimate at : 0.844 ms + // PLLCOUNT 28 = 0.000844 /(1/32768) + pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 14) | + (AT91C_CKGR_PLLCOUNT & (28<<8)) | + (AT91C_CKGR_MUL & (72<<16))); + + // Wait the startup time + while(!(pPMC->PMC_SR & AT91C_PMC_LOCK)); + while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY)); + + // 4. Selection of Master Clock and Processor Clock + // select the PLL clock divided by 2 + pPMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2 ; + while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY)); + + pPMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK ; + while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY)); + + // Set up the default interrupts handler vectors + AT91C_BASE_AIC->AIC_SVR[0] = (int) AT91F_Default_FIQ_handler ; + for (i=1;i < 31; i++) + { + AT91C_BASE_AIC->AIC_SVR[i] = (int) AT91F_Default_IRQ_handler ; + } + AT91C_BASE_AIC->AIC_SPU = (int) AT91F_Spurious_handler ; +} + + + diff --git a/AT91SAM7S256/SAM7S256/Include/ioat91sam7s256.h b/AT91SAM7S256/SAM7S256/Include/ioat91sam7s256.h new file mode 100644 index 0000000..5bb9fda --- /dev/null +++ b/AT91SAM7S256/SAM7S256/Include/ioat91sam7s256.h @@ -0,0 +1,3307 @@ +// - ---------------------------------------------------------------------------- +// - ATMEL Microcontroller Software Support - ROUSSET - +// - ---------------------------------------------------------------------------- +// - DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +// - IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +// - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +// - DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +// - INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// - LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +// - OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// - LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// - NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// - EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// - ---------------------------------------------------------------------------- +// - File Name : AT91SAM7S256.h +// - Object : AT91SAM7S256 definitions +// - Generated : AT91 SW Application Group 03/08/2005 (15:46:14) +// - +// - CVS Reference : /AT91SAM7S256.pl/1.8/Wed Feb 9 15:29:26 2005// +// - CVS Reference : /SYS_SAM7S.pl/1.2/Tue Feb 1 17:01:52 2005// +// - CVS Reference : /MC_SAM7S.pl/1.2/Tue Feb 1 17:01:00 2005// +// - CVS Reference : /PMC_SAM7S_USB.pl/1.4/Tue Feb 8 13:58:22 2005// +// - CVS Reference : /RSTC_SAM7S.pl/1.1/Tue Feb 1 16:16:35 2005// +// - CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// +// - CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// +// - CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// +// - CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// +// - CVS Reference : /UDP_6083C.pl/1.1/Mon Jan 31 13:01:46 2005// +// - CVS Reference : /AIC_6075A.pl/1.1/Fri Jun 28 10:36:48 2002// +// - CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// +// - CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// +// - CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// +// - CVS Reference : /SPI_6088D.pl/1.2/Mon Feb 14 07:24:18 2005// +// - CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// +// - CVS Reference : /TC_6082A.pl/1.6/Fri Feb 18 13:53:30 2005// +// - CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// +// - CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// +// - CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// +// - CVS Reference : /PWM_6044D.pl/1.1/Tue Apr 27 14:53:52 2004// +// - ---------------------------------------------------------------------------- + +#ifndef AT91SAM7S256_H +#define AT91SAM7S256_H + +#ifdef __IAR_SYSTEMS_ICC__ + +typedef volatile unsigned int AT91_REG;// Hardware register definition + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Peripherals +// ***************************************************************************** +typedef struct _AT91S_SYS { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register + AT91_REG Reserved2[45]; // + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved3[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved4[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register + AT91_REG Reserved5[54]; // + AT91_REG PIOA_PER; // PIO Enable Register + AT91_REG PIOA_PDR; // PIO Disable Register + AT91_REG PIOA_PSR; // PIO Status Register + AT91_REG Reserved6[1]; // + AT91_REG PIOA_OER; // Output Enable Register + AT91_REG PIOA_ODR; // Output Disable Registerr + AT91_REG PIOA_OSR; // Output Status Register + AT91_REG Reserved7[1]; // + AT91_REG PIOA_IFER; // Input Filter Enable Register + AT91_REG PIOA_IFDR; // Input Filter Disable Register + AT91_REG PIOA_IFSR; // Input Filter Status Register + AT91_REG Reserved8[1]; // + AT91_REG PIOA_SODR; // Set Output Data Register + AT91_REG PIOA_CODR; // Clear Output Data Register + AT91_REG PIOA_ODSR; // Output Data Status Register + AT91_REG PIOA_PDSR; // Pin Data Status Register + AT91_REG PIOA_IER; // Interrupt Enable Register + AT91_REG PIOA_IDR; // Interrupt Disable Register + AT91_REG PIOA_IMR; // Interrupt Mask Register + AT91_REG PIOA_ISR; // Interrupt Status Register + AT91_REG PIOA_MDER; // Multi-driver Enable Register + AT91_REG PIOA_MDDR; // Multi-driver Disable Register + AT91_REG PIOA_MDSR; // Multi-driver Status Register + AT91_REG Reserved9[1]; // + AT91_REG PIOA_PPUDR; // Pull-up Disable Register + AT91_REG PIOA_PPUER; // Pull-up Enable Register + AT91_REG PIOA_PPUSR; // Pull-up Status Register + AT91_REG Reserved10[1]; // + AT91_REG PIOA_ASR; // Select A Register + AT91_REG PIOA_BSR; // Select B Register + AT91_REG PIOA_ABSR; // AB Select Status Register + AT91_REG Reserved11[9]; // + AT91_REG PIOA_OWER; // Output Write Enable Register + AT91_REG PIOA_OWDR; // Output Write Disable Register + AT91_REG PIOA_OWSR; // Output Write Status Register + AT91_REG Reserved12[469]; // + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved13[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved14[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved15[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved16[3]; // + AT91_REG PMC_PCKR[3]; // Programmable Clock Register + AT91_REG Reserved17[5]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register + AT91_REG Reserved18[36]; // + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register + AT91_REG Reserved19[5]; // + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register + AT91_REG Reserved20[5]; // + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_SYS, *AT91PS_SYS; + + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +typedef struct _AT91S_AIC { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register +} AT91S_AIC, *AT91PS_AIC; + +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive +#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode +#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral DMA Controller +// ***************************************************************************** +typedef struct _AT91S_PDC { + AT91_REG PDC_RPR; // Receive Pointer Register + AT91_REG PDC_RCR; // Receive Counter Register + AT91_REG PDC_TPR; // Transmit Pointer Register + AT91_REG PDC_TCR; // Transmit Counter Register + AT91_REG PDC_RNPR; // Receive Next Pointer Register + AT91_REG PDC_RNCR; // Receive Next Counter Register + AT91_REG PDC_TNPR; // Transmit Next Pointer Register + AT91_REG PDC_TNCR; // Transmit Next Counter Register + AT91_REG PDC_PTCR; // PDC Transfer Control Register + AT91_REG PDC_PTSR; // PDC Transfer Status Register +} AT91S_PDC, *AT91PS_PDC; + +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable +#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable +#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable +#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Debug Unit +// ***************************************************************************** +typedef struct _AT91S_DBGU { + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved0[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved1[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register +} AT91S_DBGU, *AT91PS_DBGU; + +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver +#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter +#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable +#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable +#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable +#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable +#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type +#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity +#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity +#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity +#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode +#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode +#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt +#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt +#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt +#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt +#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt +#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt +#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt +#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt +#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt +#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt +#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +typedef struct _AT91S_PIO { + AT91_REG PIO_PER; // PIO Enable Register + AT91_REG PIO_PDR; // PIO Disable Register + AT91_REG PIO_PSR; // PIO Status Register + AT91_REG Reserved0[1]; // + AT91_REG PIO_OER; // Output Enable Register + AT91_REG PIO_ODR; // Output Disable Registerr + AT91_REG PIO_OSR; // Output Status Register + AT91_REG Reserved1[1]; // + AT91_REG PIO_IFER; // Input Filter Enable Register + AT91_REG PIO_IFDR; // Input Filter Disable Register + AT91_REG PIO_IFSR; // Input Filter Status Register + AT91_REG Reserved2[1]; // + AT91_REG PIO_SODR; // Set Output Data Register + AT91_REG PIO_CODR; // Clear Output Data Register + AT91_REG PIO_ODSR; // Output Data Status Register + AT91_REG PIO_PDSR; // Pin Data Status Register + AT91_REG PIO_IER; // Interrupt Enable Register + AT91_REG PIO_IDR; // Interrupt Disable Register + AT91_REG PIO_IMR; // Interrupt Mask Register + AT91_REG PIO_ISR; // Interrupt Status Register + AT91_REG PIO_MDER; // Multi-driver Enable Register + AT91_REG PIO_MDDR; // Multi-driver Disable Register + AT91_REG PIO_MDSR; // Multi-driver Status Register + AT91_REG Reserved3[1]; // + AT91_REG PIO_PPUDR; // Pull-up Disable Register + AT91_REG PIO_PPUER; // Pull-up Enable Register + AT91_REG PIO_PPUSR; // Pull-up Status Register + AT91_REG Reserved4[1]; // + AT91_REG PIO_ASR; // Select A Register + AT91_REG PIO_BSR; // Select B Register + AT91_REG PIO_ABSR; // AB Select Status Register + AT91_REG Reserved5[9]; // + AT91_REG PIO_OWER; // Output Write Enable Register + AT91_REG PIO_OWDR; // Output Write Disable Register + AT91_REG PIO_OWSR; // Output Write Status Register +} AT91S_PIO, *AT91PS_PIO; + + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Clock Generator Controler +// ***************************************************************************** +typedef struct _AT91S_CKGR { + AT91_REG CKGR_MOR; // Main Oscillator Register + AT91_REG CKGR_MCFR; // Main Clock Frequency Register + AT91_REG Reserved0[1]; // + AT91_REG CKGR_PLLR; // PLL Register +} AT91S_CKGR, *AT91PS_CKGR; + +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable +#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass +#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency +#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready +// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- +#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected +#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0 +#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed +#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter +#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range +#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier +#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks +#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output +#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 +#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Management Controler +// ***************************************************************************** +typedef struct _AT91S_PMC { + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved0[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved1[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved2[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved3[3]; // + AT91_REG PMC_PCKR[3]; // Programmable Clock Register + AT91_REG Reserved4[5]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register +} AT91S_PMC, *AT91PS_PMC; + +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock +#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock +#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection +#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected +#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected +#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected +#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler +#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock +#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2 +#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4 +#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8 +#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16 +#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32 +#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64 +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask +#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask +#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Reset Controller Interface +// ***************************************************************************** +typedef struct _AT91S_RSTC { + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register +} AT91S_RSTC, *AT91PS_RSTC; + +// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +#define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset +#define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset +#define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset +#define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password +// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +#define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status +#define AT91C_RSTC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brownout Detection Status +#define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type +#define AT91C_RSTC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. +#define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. +#define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low. +#define AT91C_RSTC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brownout Reset occured. +#define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level +#define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress. +// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +#define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable +#define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable +#define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable +#define AT91C_RSTC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_RTTC { + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register +} AT91S_RTTC, *AT91PS_RTTC; + +// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +#define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value +#define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable +#define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable +#define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart +// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +#define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value +// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +#define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value +// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +#define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status +#define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_PITC { + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register +} AT91S_PITC, *AT91PS_PITC; + +// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +#define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value +#define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled +#define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable +// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +#define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status +// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +#define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value +#define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter +// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_WDTC { + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register +} AT91S_WDTC, *AT91PS_WDTC; + +// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +#define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart +#define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password +// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +#define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable +#define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable +#define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable +#define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value +#define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt +#define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt +// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +#define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow +#define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface +// ***************************************************************************** +typedef struct _AT91S_VREG { + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_VREG, *AT91PS_VREG; + +// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- +#define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Memory Controller Interface +// ***************************************************************************** +typedef struct _AT91S_MC { + AT91_REG MC_RCR; // MC Remap Control Register + AT91_REG MC_ASR; // MC Abort Status Register + AT91_REG MC_AASR; // MC Abort Address Status Register + AT91_REG Reserved0[21]; // + AT91_REG MC_FMR; // MC Flash Mode Register + AT91_REG MC_FCR; // MC Flash Command Register + AT91_REG MC_FSR; // MC Flash Status Register +} AT91S_MC, *AT91PS_MC; + +// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit +// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status +#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status +#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status +#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte +#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word +#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word +#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status +#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read +#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write +#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch +#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source +#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source +#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source +#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source +// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- +#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready +#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error +#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error +#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming +#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State +#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations +#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations +#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations +#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations +#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number +// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- +#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command +#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN. +#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. +#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. +#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits. +#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits. +#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit. +#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number +#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key +// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- +#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status +#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status +#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status +#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status +#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status +#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status +#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status +#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status +#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status +#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status +#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status +#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status +#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status +#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status +#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status +#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status +#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status +#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status +#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status +#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status +#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status +#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status +#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +typedef struct _AT91S_SPI { + AT91_REG SPI_CR; // Control Register + AT91_REG SPI_MR; // Mode Register + AT91_REG SPI_RDR; // Receive Data Register + AT91_REG SPI_TDR; // Transmit Data Register + AT91_REG SPI_SR; // Status Register + AT91_REG SPI_IER; // Interrupt Enable Register + AT91_REG SPI_IDR; // Interrupt Disable Register + AT91_REG SPI_IMR; // Interrupt Mask Register + AT91_REG Reserved0[4]; // + AT91_REG SPI_CSR[4]; // Chip Select Register + AT91_REG Reserved1[48]; // + AT91_REG SPI_RPR; // Receive Pointer Register + AT91_REG SPI_RCR; // Receive Counter Register + AT91_REG SPI_TPR; // Transmit Pointer Register + AT91_REG SPI_TCR; // Transmit Counter Register + AT91_REG SPI_RNPR; // Receive Next Pointer Register + AT91_REG SPI_RNCR; // Receive Next Counter Register + AT91_REG SPI_TNPR; // Transmit Next Pointer Register + AT91_REG SPI_TNCR; // Transmit Next Counter Register + AT91_REG SPI_PTCR; // PDC Transfer Control Register + AT91_REG SPI_PTSR; // PDC Transfer Status Register +} AT91S_SPI, *AT91PS_SPI; + +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset +#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt +#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt +#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer +#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// ***************************************************************************** +typedef struct _AT91S_ADC { + AT91_REG ADC_CR; // ADC Control Register + AT91_REG ADC_MR; // ADC Mode Register + AT91_REG Reserved0[2]; // + AT91_REG ADC_CHER; // ADC Channel Enable Register + AT91_REG ADC_CHDR; // ADC Channel Disable Register + AT91_REG ADC_CHSR; // ADC Channel Status Register + AT91_REG ADC_SR; // ADC Status Register + AT91_REG ADC_LCDR; // ADC Last Converted Data Register + AT91_REG ADC_IER; // ADC Interrupt Enable Register + AT91_REG ADC_IDR; // ADC Interrupt Disable Register + AT91_REG ADC_IMR; // ADC Interrupt Mask Register + AT91_REG ADC_CDR0; // ADC Channel Data Register 0 + AT91_REG ADC_CDR1; // ADC Channel Data Register 1 + AT91_REG ADC_CDR2; // ADC Channel Data Register 2 + AT91_REG ADC_CDR3; // ADC Channel Data Register 3 + AT91_REG ADC_CDR4; // ADC Channel Data Register 4 + AT91_REG ADC_CDR5; // ADC Channel Data Register 5 + AT91_REG ADC_CDR6; // ADC Channel Data Register 6 + AT91_REG ADC_CDR7; // ADC Channel Data Register 7 + AT91_REG Reserved1[44]; // + AT91_REG ADC_RPR; // Receive Pointer Register + AT91_REG ADC_RCR; // Receive Counter Register + AT91_REG ADC_TPR; // Transmit Pointer Register + AT91_REG ADC_TCR; // Transmit Counter Register + AT91_REG ADC_RNPR; // Receive Next Pointer Register + AT91_REG ADC_RNCR; // Receive Next Counter Register + AT91_REG ADC_TNPR; // Transmit Next Pointer Register + AT91_REG ADC_TNCR; // Transmit Next Counter Register + AT91_REG ADC_PTCR; // PDC Transfer Control Register + AT91_REG ADC_PTSR; // PDC Transfer Status Register +} AT91S_ADC, *AT91PS_ADC; + +// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset +#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion +// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable +#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. +#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection +#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 +#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 +#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 +#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 +#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 +#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 +#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger +#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution. +#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution +#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution +#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode +#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection +#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time +#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time +// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0 +#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1 +#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2 +#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3 +#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4 +#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5 +#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6 +#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7 +// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion +#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion +#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion +#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion +#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion +#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion +#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion +#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion +#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error +#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error +#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error +#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error +#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error +#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error +#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error +#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error +#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready +#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun +#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer +#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt +// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted +// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data +// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// ***************************************************************************** +typedef struct _AT91S_SSC { + AT91_REG SSC_CR; // Control Register + AT91_REG SSC_CMR; // Clock Mode Register + AT91_REG Reserved0[2]; // + AT91_REG SSC_RCMR; // Receive Clock ModeRegister + AT91_REG SSC_RFMR; // Receive Frame Mode Register + AT91_REG SSC_TCMR; // Transmit Clock Mode Register + AT91_REG SSC_TFMR; // Transmit Frame Mode Register + AT91_REG SSC_RHR; // Receive Holding Register + AT91_REG SSC_THR; // Transmit Holding Register + AT91_REG Reserved1[2]; // + AT91_REG SSC_RSHR; // Receive Sync Holding Register + AT91_REG SSC_TSHR; // Transmit Sync Holding Register + AT91_REG Reserved2[2]; // + AT91_REG SSC_SR; // Status Register + AT91_REG SSC_IER; // Interrupt Enable Register + AT91_REG SSC_IDR; // Interrupt Disable Register + AT91_REG SSC_IMR; // Interrupt Mask Register + AT91_REG Reserved3[44]; // + AT91_REG SSC_RPR; // Receive Pointer Register + AT91_REG SSC_RCR; // Receive Counter Register + AT91_REG SSC_TPR; // Transmit Pointer Register + AT91_REG SSC_TCR; // Transmit Counter Register + AT91_REG SSC_RNPR; // Receive Next Pointer Register + AT91_REG SSC_RNCR; // Receive Next Counter Register + AT91_REG SSC_TNPR; // Transmit Next Pointer Register + AT91_REG SSC_TNCR; // Transmit Next Counter Register + AT91_REG SSC_PTCR; // PDC Transfer Control Register + AT91_REG SSC_PTSR; // PDC Transfer Status Register +} AT91S_SSC, *AT91PS_SSC; + +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable +#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable +#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable +#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable +#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection +#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock +#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal +#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin +#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection +#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output +#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion +#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection +#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start +#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input +#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input +#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input +#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input +#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input +#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input +#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0 +#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay +#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length +#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode +#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First +#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame +#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length +#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection +#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value +#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready +#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty +#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission +#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty +#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready +#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun +#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception +#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full +#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync +#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync +#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable +#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +typedef struct _AT91S_USART { + AT91_REG US_CR; // Control Register + AT91_REG US_MR; // Mode Register + AT91_REG US_IER; // Interrupt Enable Register + AT91_REG US_IDR; // Interrupt Disable Register + AT91_REG US_IMR; // Interrupt Mask Register + AT91_REG US_CSR; // Channel Status Register + AT91_REG US_RHR; // Receiver Holding Register + AT91_REG US_THR; // Transmitter Holding Register + AT91_REG US_BRGR; // Baud Rate Generator Register + AT91_REG US_RTOR; // Receiver Time-out Register + AT91_REG US_TTGR; // Transmitter Time-guard Register + AT91_REG Reserved0[5]; // + AT91_REG US_FIDI; // FI_DI_Ratio Register + AT91_REG US_NER; // Nb Errors Register + AT91_REG Reserved1[1]; // + AT91_REG US_IF; // IRDA_FILTER Register + AT91_REG Reserved2[44]; // + AT91_REG US_RPR; // Receive Pointer Register + AT91_REG US_RCR; // Receive Counter Register + AT91_REG US_TPR; // Transmit Pointer Register + AT91_REG US_TCR; // Transmit Counter Register + AT91_REG US_RNPR; // Receive Next Pointer Register + AT91_REG US_RNCR; // Receive Next Counter Register + AT91_REG US_TNPR; // Transmit Next Pointer Register + AT91_REG US_TNCR; // Transmit Next Counter Register + AT91_REG US_PTCR; // PDC Transfer Control Register + AT91_REG US_PTSR; // PDC Transfer Status Register +} AT91S_USART, *AT91PS_USART; + +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address +#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations +#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge +#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out +#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable +#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable +#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable +#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode +#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal +#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485 +#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking +#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem +#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0 +#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1 +#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA +#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking +#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order +#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select +#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode +#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge +#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK +#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions +#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached +#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge +#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag +#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag +#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag +#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input +#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input +#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input +#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Two-wire Interface +// ***************************************************************************** +typedef struct _AT91S_TWI { + AT91_REG TWI_CR; // Control Register + AT91_REG TWI_MMR; // Master Mode Register + AT91_REG Reserved0[1]; // + AT91_REG TWI_IADR; // Internal Address Register + AT91_REG TWI_CWGR; // Clock Waveform Generator Register + AT91_REG Reserved1[3]; // + AT91_REG TWI_SR; // Status Register + AT91_REG TWI_IER; // Interrupt Enable Register + AT91_REG TWI_IDR; // Interrupt Disable Register + AT91_REG TWI_IMR; // Interrupt Mask Register + AT91_REG TWI_RHR; // Receive Holding Register + AT91_REG TWI_THR; // Transmit Holding Register +} AT91S_TWI, *AT91PS_TWI; + +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition +#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition +#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled +#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled +#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size +#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address +#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address +#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address +#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address +#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction +#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider +#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider +#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY +#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error +#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error +#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +typedef struct _AT91S_TC { + AT91_REG TC_CCR; // Channel Control Register + AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) + AT91_REG Reserved0[2]; // + AT91_REG TC_CV; // Counter Value + AT91_REG TC_RA; // Register A + AT91_REG TC_RB; // Register B + AT91_REG TC_RC; // Register C + AT91_REG TC_SR; // Status Register + AT91_REG TC_IER; // Interrupt Enable Register + AT91_REG TC_IDR; // Interrupt Disable Register + AT91_REG TC_IMR; // Interrupt Mask Register +} AT91S_TC, *AT91PS_TC; + +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK +#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0 +#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1 +#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2 +#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert +#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection +#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal +#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock +#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock +#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock +#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading +#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading +#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection +#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None +#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection +#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC) +#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection +#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None +#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection +#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None +#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA +#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger +#define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +typedef struct _AT91S_TCB { + AT91S_TC TCB_TC0; // TC Channel 0 + AT91_REG Reserved0[4]; // + AT91S_TC TCB_TC1; // TC Channel 1 + AT91_REG Reserved1[4]; // + AT91S_TC TCB_TC2; // TC Channel 2 + AT91_REG Reserved2[4]; // + AT91_REG TCB_BCR; // TC Block Control Register + AT91_REG TCB_BMR; // TC Block Mode Register +} AT91S_TCB, *AT91PS_TCB; + +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR PWMC Channel Interface +// ***************************************************************************** +typedef struct _AT91S_PWMC_CH { + AT91_REG PWMC_CMR; // Channel Mode Register + AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register + AT91_REG PWMC_CPRDR; // Channel Period Register + AT91_REG PWMC_CCNTR; // Channel Counter Register + AT91_REG PWMC_CUPDR; // Channel Update Register + AT91_REG PWMC_Reserved[3]; // Reserved +} AT91S_PWMC_CH, *AT91PS_PWMC_CH; + +// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- +#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx +#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH) +#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment +#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity +#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period +// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- +#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle +// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- +#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period +// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- +#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter +// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- +#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface +// ***************************************************************************** +typedef struct _AT91S_PWMC { + AT91_REG PWMC_MR; // PWMC Mode Register + AT91_REG PWMC_ENA; // PWMC Enable Register + AT91_REG PWMC_DIS; // PWMC Disable Register + AT91_REG PWMC_SR; // PWMC Status Register + AT91_REG PWMC_IER; // PWMC Interrupt Enable Register + AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register + AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register + AT91_REG PWMC_ISR; // PWMC Interrupt Status Register + AT91_REG Reserved0[55]; // + AT91_REG PWMC_VR; // PWMC Version Register + AT91_REG Reserved1[64]; // + AT91S_PWMC_CH PWMC_CH[32]; // PWMC Channel 0 +} AT91S_PWMC, *AT91PS_PWMC; + +// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- +#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor. +#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A +#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC) +#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor. +#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B +#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC) +// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- +#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0 +#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1 +#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2 +#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3 +#define AT91C_PWMC_CHID4 ((unsigned int) 0x1 << 4) // (PWMC) Channel ID 4 +#define AT91C_PWMC_CHID5 ((unsigned int) 0x1 << 5) // (PWMC) Channel ID 5 +#define AT91C_PWMC_CHID6 ((unsigned int) 0x1 << 6) // (PWMC) Channel ID 6 +#define AT91C_PWMC_CHID7 ((unsigned int) 0x1 << 7) // (PWMC) Channel ID 7 +// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- +// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- +// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- +// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- +// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- +// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Device Interface +// ***************************************************************************** +typedef struct _AT91S_UDP { + AT91_REG UDP_NUM; // Frame Number Register + AT91_REG UDP_GLBSTATE; // Global State Register + AT91_REG UDP_FADDR; // Function Address Register + AT91_REG Reserved0[1]; // + AT91_REG UDP_IER; // Interrupt Enable Register + AT91_REG UDP_IDR; // Interrupt Disable Register + AT91_REG UDP_IMR; // Interrupt Mask Register + AT91_REG UDP_ISR; // Interrupt Status Register + AT91_REG UDP_ICR; // Interrupt Clear Register + AT91_REG Reserved1[1]; // + AT91_REG UDP_RSTEP; // Reset Endpoint Register + AT91_REG Reserved2[1]; // + AT91_REG UDP_CSR[8]; // Endpoint Control and Status Register + AT91_REG UDP_FDR[8]; // Endpoint FIFO Data Register + AT91_REG Reserved3[1]; // + AT91_REG UDP_TXVC; // Transceiver Control Register +} AT91S_UDP, *AT91PS_UDP; + +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats +#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error +#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable +#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured +#define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume +#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host +#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value +#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt +#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt +#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt +#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt +#define AT91C_UDP_EPINT6 ((unsigned int) 0x1 << 6) // (UDP) Endpoint 6 Interrupt +#define AT91C_UDP_EPINT7 ((unsigned int) 0x1 << 7) // (UDP) Endpoint 7 Interrupt +#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt +#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt +#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt +#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt +#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0 +#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1 +#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2 +#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3 +#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4 +#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5 +#define AT91C_UDP_EP6 ((unsigned int) 0x1 << 6) // (UDP) Reset Endpoint 6 +#define AT91C_UDP_EP7 ((unsigned int) 0x1 << 7) // (UDP) Reset Endpoint 7 +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR +#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0 +#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) +#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) +#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready +#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction +#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type +#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control +#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT +#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT +#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT +#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN +#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN +#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN +#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle +#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable +#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO +// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- +#define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP) +#define AT91C_UDP_PUON ((unsigned int) 0x1 << 9) // (UDP) Pull-up ON + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91SAM7S256 +// ***************************************************************************** +// ========== Register definition for SYS peripheral ========== +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register +#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) +#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register +#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register +#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register +#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register +#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register +#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register +#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register +// ========== Register definition for PDC_DBGU peripheral ========== +#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register +#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register +#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register +#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register +#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register +#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register +#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register +#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register +#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register +#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register +// ========== Register definition for DBGU peripheral ========== +#define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register +#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register +#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register +#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register +#define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register +#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register +#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register +#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register +#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register +#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register +#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register +#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register +// ========== Register definition for PIOA peripheral ========== +#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register +#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register +#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register +#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register +#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register +#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register +#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register +#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register +#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register +#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register +#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register +#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register +#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register +// ========== Register definition for CKGR peripheral ========== +#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register +#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register +#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register +// ========== Register definition for PMC peripheral ========== +#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register +#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register +#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register +#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register +#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register +#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register +#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register +#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register +#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register +#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register +#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register +#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register +#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register +#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register +#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register +// ========== Register definition for RSTC peripheral ========== +#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register +#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register +#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register +// ========== Register definition for RTTC peripheral ========== +#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register +#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register +#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register +#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register +// ========== Register definition for PITC peripheral ========== +#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register +#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register +#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register +#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register +// ========== Register definition for WDTC peripheral ========== +#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register +#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register +#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register +// ========== Register definition for VREG peripheral ========== +#define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register +// ========== Register definition for MC peripheral ========== +#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register +#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register +#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register +#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register +#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register +#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register +// ========== Register definition for PDC_SPI peripheral ========== +#define AT91C_SPI_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register +#define AT91C_SPI_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI) Transmit Pointer Register +#define AT91C_SPI_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI) Transmit Counter Register +#define AT91C_SPI_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI) Receive Counter Register +#define AT91C_SPI_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register +#define AT91C_SPI_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register +#define AT91C_SPI_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI) Receive Pointer Register +#define AT91C_SPI_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register +#define AT91C_SPI_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI) Receive Next Counter Register +#define AT91C_SPI_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register +// ========== Register definition for SPI peripheral ========== +#define AT91C_SPI_IER ((AT91_REG *) 0xFFFE0014) // (SPI) Interrupt Enable Register +#define AT91C_SPI_SR ((AT91_REG *) 0xFFFE0010) // (SPI) Status Register +#define AT91C_SPI_IDR ((AT91_REG *) 0xFFFE0018) // (SPI) Interrupt Disable Register +#define AT91C_SPI_CR ((AT91_REG *) 0xFFFE0000) // (SPI) Control Register +#define AT91C_SPI_MR ((AT91_REG *) 0xFFFE0004) // (SPI) Mode Register +#define AT91C_SPI_IMR ((AT91_REG *) 0xFFFE001C) // (SPI) Interrupt Mask Register +#define AT91C_SPI_TDR ((AT91_REG *) 0xFFFE000C) // (SPI) Transmit Data Register +#define AT91C_SPI_RDR ((AT91_REG *) 0xFFFE0008) // (SPI) Receive Data Register +#define AT91C_SPI_CSR ((AT91_REG *) 0xFFFE0030) // (SPI) Chip Select Register +// ========== Register definition for PDC_ADC peripheral ========== +#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register +#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register +#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register +#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register +#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register +#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register +#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register +#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register +#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register +#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register +// ========== Register definition for ADC peripheral ========== +#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 +#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 +#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 +#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 +#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register +#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register +#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 +#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 +#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register +#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register +#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register +#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 +#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 +#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register +#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register +#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register +#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register +#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register +// ========== Register definition for PDC_SSC peripheral ========== +#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register +#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register +#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register +#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register +#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register +#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register +#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register +#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register +#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register +#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register +// ========== Register definition for SSC peripheral ========== +#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register +#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register +#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register +#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register +#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register +#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister +#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register +#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register +#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register +#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register +#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register +#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register +#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register +#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register +#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register +#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register +#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register +#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register +#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register +#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register +#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register +#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register +#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register +#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register +#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register +#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register +#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register +#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register +#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register +#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register +#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register +#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register +#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register +#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register +#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register +#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register +#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register +#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register +#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register +#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register +#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register +#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register +#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register +#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register +#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register +#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register +#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register +#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register +#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register +#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register +#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register +#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register +// ========== Register definition for TWI peripheral ========== +#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register +#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register +#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register +#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register +#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register +#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register +#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register +#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register +#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register +#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register +#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C +#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B +#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register +#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A +#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value +#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B +#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register +#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register +#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A +#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C +#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register +#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value +#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A +#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B +#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C +#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register +// ========== Register definition for TCB peripheral ========== +#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register +#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register +// ========== Register definition for PWMC_CH3 peripheral ========== +#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register +#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved +#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register +#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register +#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register +#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register +// ========== Register definition for PWMC_CH2 peripheral ========== +#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved +#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register +#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register +#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register +#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register +#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH1 peripheral ========== +#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved +#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register +#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register +#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register +#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register +#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register +// ========== Register definition for PWMC_CH0 peripheral ========== +#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved +#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register +#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register +#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register +#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register +#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register +// ========== Register definition for PWMC peripheral ========== +#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register +#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register +#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register +#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register +#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register +#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register +#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register +#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register +#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register +// ========== Register definition for UDP peripheral ========== +#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register +#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register +#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register +#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register +#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register +#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register +#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register +#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register +#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register +#define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register +#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register +#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91SAM7S256 +// ***************************************************************************** +#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_PWM0 ((unsigned int) AT91C_PIO_PA0) // PWM Channel 0 +#define AT91C_PA0_TIOA0 ((unsigned int) AT91C_PIO_PA0) // Timer Counter 0 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_PWM1 ((unsigned int) AT91C_PIO_PA1) // PWM Channel 1 +#define AT91C_PA1_TIOB0 ((unsigned int) AT91C_PIO_PA1) // Timer Counter 0 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10 +#define AT91C_PA10_DTXD ((unsigned int) AT91C_PIO_PA10) // DBGU Debug Transmit Data +#define AT91C_PA10_NPCS2 ((unsigned int) AT91C_PIO_PA10) // SPI Peripheral Chip Select 2 +#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11 +#define AT91C_PA11_NPCS0 ((unsigned int) AT91C_PIO_PA11) // SPI Peripheral Chip Select 0 +#define AT91C_PA11_PWM0 ((unsigned int) AT91C_PIO_PA11) // PWM Channel 0 +#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12 +#define AT91C_PA12_MISO ((unsigned int) AT91C_PIO_PA12) // SPI Master In Slave +#define AT91C_PA12_PWM1 ((unsigned int) AT91C_PIO_PA12) // PWM Channel 1 +#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13 +#define AT91C_PA13_MOSI ((unsigned int) AT91C_PIO_PA13) // SPI Master Out Slave +#define AT91C_PA13_PWM2 ((unsigned int) AT91C_PIO_PA13) // PWM Channel 2 +#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14 +#define AT91C_PA14_SPCK ((unsigned int) AT91C_PIO_PA14) // SPI Serial Clock +#define AT91C_PA14_PWM3 ((unsigned int) AT91C_PIO_PA14) // PWM Channel 3 +#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15 +#define AT91C_PA15_TF ((unsigned int) AT91C_PIO_PA15) // SSC Transmit Frame Sync +#define AT91C_PA15_TIOA1 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 1 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16 +#define AT91C_PA16_TK ((unsigned int) AT91C_PIO_PA16) // SSC Transmit Clock +#define AT91C_PA16_TIOB1 ((unsigned int) AT91C_PIO_PA16) // Timer Counter 1 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17 +#define AT91C_PA17_TD ((unsigned int) AT91C_PIO_PA17) // SSC Transmit data +#define AT91C_PA17_PCK1 ((unsigned int) AT91C_PIO_PA17) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18 +#define AT91C_PA18_RD ((unsigned int) AT91C_PIO_PA18) // SSC Receive Data +#define AT91C_PA18_PCK2 ((unsigned int) AT91C_PIO_PA18) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19 +#define AT91C_PA19_RK ((unsigned int) AT91C_PIO_PA19) // SSC Receive Clock +#define AT91C_PA19_FIQ ((unsigned int) AT91C_PIO_PA19) // AIC Fast Interrupt Input +#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_PWM2 ((unsigned int) AT91C_PIO_PA2) // PWM Channel 2 +#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock +#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20 +#define AT91C_PA20_RF ((unsigned int) AT91C_PIO_PA20) // SSC Receive Frame Sync +#define AT91C_PA20_IRQ0 ((unsigned int) AT91C_PIO_PA20) // External Interrupt 0 +#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21 +#define AT91C_PA21_RXD1 ((unsigned int) AT91C_PIO_PA21) // USART 1 Receive Data +#define AT91C_PA21_PCK1 ((unsigned int) AT91C_PIO_PA21) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_TXD1 ((unsigned int) AT91C_PIO_PA22) // USART 1 Transmit Data +#define AT91C_PA22_NPCS3 ((unsigned int) AT91C_PIO_PA22) // SPI Peripheral Chip Select 3 +#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_SCK1 ((unsigned int) AT91C_PIO_PA23) // USART 1 Serial Clock +#define AT91C_PA23_PWM0 ((unsigned int) AT91C_PIO_PA23) // PWM Channel 0 +#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24 +#define AT91C_PA24_RTS1 ((unsigned int) AT91C_PIO_PA24) // USART 1 Ready To Send +#define AT91C_PA24_PWM1 ((unsigned int) AT91C_PIO_PA24) // PWM Channel 1 +#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25 +#define AT91C_PA25_CTS1 ((unsigned int) AT91C_PIO_PA25) // USART 1 Clear To Send +#define AT91C_PA25_PWM2 ((unsigned int) AT91C_PIO_PA25) // PWM Channel 2 +#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26 +#define AT91C_PA26_DCD1 ((unsigned int) AT91C_PIO_PA26) // USART 1 Data Carrier Detect +#define AT91C_PA26_TIOA2 ((unsigned int) AT91C_PIO_PA26) // Timer Counter 2 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27 +#define AT91C_PA27_DTR1 ((unsigned int) AT91C_PIO_PA27) // USART 1 Data Terminal ready +#define AT91C_PA27_TIOB2 ((unsigned int) AT91C_PIO_PA27) // Timer Counter 2 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_DSR1 ((unsigned int) AT91C_PIO_PA28) // USART 1 Data Set ready +#define AT91C_PA28_TCLK1 ((unsigned int) AT91C_PIO_PA28) // Timer Counter 1 external clock input +#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29 +#define AT91C_PA29_RI1 ((unsigned int) AT91C_PIO_PA29) // USART 1 Ring Indicator +#define AT91C_PA29_TCLK2 ((unsigned int) AT91C_PIO_PA29) // Timer Counter 2 external clock input +#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_TWD ((unsigned int) AT91C_PIO_PA3) // TWI Two-wire Serial Data +#define AT91C_PA3_NPCS3 ((unsigned int) AT91C_PIO_PA3) // SPI Peripheral Chip Select 3 +#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30 +#define AT91C_PA30_IRQ1 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 1 +#define AT91C_PA30_NPCS2 ((unsigned int) AT91C_PIO_PA30) // SPI Peripheral Chip Select 2 +#define AT91C_PIO_PA31 ((unsigned int) 1 << 31) // Pin Controlled by PA31 +#define AT91C_PA31_NPCS1 ((unsigned int) AT91C_PIO_PA31) // SPI Peripheral Chip Select 1 +#define AT91C_PA31_PCK2 ((unsigned int) AT91C_PIO_PA31) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_TWCK ((unsigned int) AT91C_PIO_PA4) // TWI Two-wire Serial Clock +#define AT91C_PA4_TCLK0 ((unsigned int) AT91C_PIO_PA4) // Timer Counter 0 external clock input +#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_RXD0 ((unsigned int) AT91C_PIO_PA5) // USART 0 Receive Data +#define AT91C_PA5_NPCS3 ((unsigned int) AT91C_PIO_PA5) // SPI Peripheral Chip Select 3 +#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6 +#define AT91C_PA6_TXD0 ((unsigned int) AT91C_PIO_PA6) // USART 0 Transmit Data +#define AT91C_PA6_PCK0 ((unsigned int) AT91C_PIO_PA6) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7 +#define AT91C_PA7_RTS0 ((unsigned int) AT91C_PIO_PA7) // USART 0 Ready To Send +#define AT91C_PA7_PWM3 ((unsigned int) AT91C_PIO_PA7) // PWM Channel 3 +#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8 +#define AT91C_PA8_CTS0 ((unsigned int) AT91C_PIO_PA8) // USART 0 Clear To Send +#define AT91C_PA8_ADTRG ((unsigned int) AT91C_PIO_PA8) // ADC External Trigger +#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9 +#define AT91C_PA9_DRXD ((unsigned int) AT91C_PIO_PA9) // DBGU Debug Receive Data +#define AT91C_PA9_NPCS1 ((unsigned int) AT91C_PIO_PA9) // SPI Peripheral Chip Select 1 + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91SAM7S256 +// ***************************************************************************** +#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral +#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller +#define AT91C_ID_3_Reserved ((unsigned int) 3) // Reserved +#define AT91C_ID_ADC ((unsigned int) 4) // Analog-to-Digital Converter +#define AT91C_ID_SPI ((unsigned int) 5) // Serial Peripheral Interface +#define AT91C_ID_US0 ((unsigned int) 6) // USART 0 +#define AT91C_ID_US1 ((unsigned int) 7) // USART 1 +#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller +#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface +#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller +#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port +#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0 +#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1 +#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2 +#define AT91C_ID_15_Reserved ((unsigned int) 15) // Reserved +#define AT91C_ID_16_Reserved ((unsigned int) 16) // Reserved +#define AT91C_ID_17_Reserved ((unsigned int) 17) // Reserved +#define AT91C_ID_18_Reserved ((unsigned int) 18) // Reserved +#define AT91C_ID_19_Reserved ((unsigned int) 19) // Reserved +#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved +#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved +#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved +#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved +#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved +#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved +#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved +#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved +#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved +#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved +#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1) + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91SAM7S256 +// ***************************************************************************** +#define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address +#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address +#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address +#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address +#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address +#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address +#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address +#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address +#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address +#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address +#define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address +#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address +#define AT91C_BASE_PDC_SPI ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI) Base Address +#define AT91C_BASE_SPI ((AT91PS_SPI) 0xFFFE0000) // (SPI) Base Address +#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address +#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address +#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address +#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address +#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address +#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address +#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address +#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address +#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address +#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address +#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address +#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address +#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address +#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address +#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address +#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address +#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address +#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address +#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91SAM7S256 +// ***************************************************************************** +#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address +#define AT91C_ISRAM_SIZE ((unsigned int) 0x00010000) // Internal SRAM size in byte (64 Kbyte) +#define AT91C_IFLASH ((char *) 0x00100000) // Internal ROM base address +#define AT91C_IFLASH_SIZE ((unsigned int) 0x00040000) // Internal ROM size in byte (256 Kbyte) +#endif /* __IAR_SYSTEMS_ICC__ */ + +#ifdef __IAR_SYSTEMS_ASM__ + +// - Hardware register definition + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR System Peripherals +// - ***************************************************************************** + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// - ***************************************************************************** +// - -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +AT91C_AIC_PRIOR EQU (0x7 << 0) ;- (AIC) Priority Level +AT91C_AIC_PRIOR_LOWEST EQU (0x0) ;- (AIC) Lowest priority level +AT91C_AIC_PRIOR_HIGHEST EQU (0x7) ;- (AIC) Highest priority level +AT91C_AIC_SRCTYPE EQU (0x3 << 5) ;- (AIC) Interrupt Source Type +AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE EQU (0x0 << 5) ;- (AIC) Internal Sources Code Label Level Sensitive +AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED EQU (0x1 << 5) ;- (AIC) Internal Sources Code Label Edge triggered +AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL EQU (0x2 << 5) ;- (AIC) External Sources Code Label High-level Sensitive +AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE EQU (0x3 << 5) ;- (AIC) External Sources Code Label Positive Edge triggered +// - -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +AT91C_AIC_NFIQ EQU (0x1 << 0) ;- (AIC) NFIQ Status +AT91C_AIC_NIRQ EQU (0x1 << 1) ;- (AIC) NIRQ Status +// - -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +AT91C_AIC_DCR_PROT EQU (0x1 << 0) ;- (AIC) Protection Mode +AT91C_AIC_DCR_GMSK EQU (0x1 << 1) ;- (AIC) General Mask + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Peripheral DMA Controller +// - ***************************************************************************** +// - -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +AT91C_PDC_RXTEN EQU (0x1 << 0) ;- (PDC) Receiver Transfer Enable +AT91C_PDC_RXTDIS EQU (0x1 << 1) ;- (PDC) Receiver Transfer Disable +AT91C_PDC_TXTEN EQU (0x1 << 8) ;- (PDC) Transmitter Transfer Enable +AT91C_PDC_TXTDIS EQU (0x1 << 9) ;- (PDC) Transmitter Transfer Disable +// - -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Debug Unit +// - ***************************************************************************** +// - -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +AT91C_US_RSTRX EQU (0x1 << 2) ;- (DBGU) Reset Receiver +AT91C_US_RSTTX EQU (0x1 << 3) ;- (DBGU) Reset Transmitter +AT91C_US_RXEN EQU (0x1 << 4) ;- (DBGU) Receiver Enable +AT91C_US_RXDIS EQU (0x1 << 5) ;- (DBGU) Receiver Disable +AT91C_US_TXEN EQU (0x1 << 6) ;- (DBGU) Transmitter Enable +AT91C_US_TXDIS EQU (0x1 << 7) ;- (DBGU) Transmitter Disable +AT91C_US_RSTSTA EQU (0x1 << 8) ;- (DBGU) Reset Status Bits +// - -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +AT91C_US_PAR EQU (0x7 << 9) ;- (DBGU) Parity type +AT91C_US_PAR_EVEN EQU (0x0 << 9) ;- (DBGU) Even Parity +AT91C_US_PAR_ODD EQU (0x1 << 9) ;- (DBGU) Odd Parity +AT91C_US_PAR_SPACE EQU (0x2 << 9) ;- (DBGU) Parity forced to 0 (Space) +AT91C_US_PAR_MARK EQU (0x3 << 9) ;- (DBGU) Parity forced to 1 (Mark) +AT91C_US_PAR_NONE EQU (0x4 << 9) ;- (DBGU) No Parity +AT91C_US_PAR_MULTI_DROP EQU (0x6 << 9) ;- (DBGU) Multi-drop mode +AT91C_US_CHMODE EQU (0x3 << 14) ;- (DBGU) Channel Mode +AT91C_US_CHMODE_NORMAL EQU (0x0 << 14) ;- (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +AT91C_US_CHMODE_AUTO EQU (0x1 << 14) ;- (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +AT91C_US_CHMODE_LOCAL EQU (0x2 << 14) ;- (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +AT91C_US_CHMODE_REMOTE EQU (0x3 << 14) ;- (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// - -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +AT91C_US_RXRDY EQU (0x1 << 0) ;- (DBGU) RXRDY Interrupt +AT91C_US_TXRDY EQU (0x1 << 1) ;- (DBGU) TXRDY Interrupt +AT91C_US_ENDRX EQU (0x1 << 3) ;- (DBGU) End of Receive Transfer Interrupt +AT91C_US_ENDTX EQU (0x1 << 4) ;- (DBGU) End of Transmit Interrupt +AT91C_US_OVRE EQU (0x1 << 5) ;- (DBGU) Overrun Interrupt +AT91C_US_FRAME EQU (0x1 << 6) ;- (DBGU) Framing Error Interrupt +AT91C_US_PARE EQU (0x1 << 7) ;- (DBGU) Parity Error Interrupt +AT91C_US_TXEMPTY EQU (0x1 << 9) ;- (DBGU) TXEMPTY Interrupt +AT91C_US_TXBUFE EQU (0x1 << 11) ;- (DBGU) TXBUFE Interrupt +AT91C_US_RXBUFF EQU (0x1 << 12) ;- (DBGU) RXBUFF Interrupt +AT91C_US_COMM_TX EQU (0x1 << 30) ;- (DBGU) COMM_TX Interrupt +AT91C_US_COMM_RX EQU (0x1 << 31) ;- (DBGU) COMM_RX Interrupt +// - -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// - -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// - -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// - -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +AT91C_US_FORCE_NTRST EQU (0x1 << 0) ;- (DBGU) Force NTRST in JTAG + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// - ***************************************************************************** + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Clock Generator Controler +// - ***************************************************************************** +// - -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +AT91C_CKGR_MOSCEN EQU (0x1 << 0) ;- (CKGR) Main Oscillator Enable +AT91C_CKGR_OSCBYPASS EQU (0x1 << 1) ;- (CKGR) Main Oscillator Bypass +AT91C_CKGR_OSCOUNT EQU (0xFF << 8) ;- (CKGR) Main Oscillator Start-up Time +// - -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +AT91C_CKGR_MAINF EQU (0xFFFF << 0) ;- (CKGR) Main Clock Frequency +AT91C_CKGR_MAINRDY EQU (0x1 << 16) ;- (CKGR) Main Clock Ready +// - -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- +AT91C_CKGR_DIV EQU (0xFF << 0) ;- (CKGR) Divider Selected +AT91C_CKGR_DIV_0 EQU (0x0) ;- (CKGR) Divider output is 0 +AT91C_CKGR_DIV_BYPASS EQU (0x1) ;- (CKGR) Divider is bypassed +AT91C_CKGR_PLLCOUNT EQU (0x3F << 8) ;- (CKGR) PLL Counter +AT91C_CKGR_OUT EQU (0x3 << 14) ;- (CKGR) PLL Output Frequency Range +AT91C_CKGR_OUT_0 EQU (0x0 << 14) ;- (CKGR) Please refer to the PLL datasheet +AT91C_CKGR_OUT_1 EQU (0x1 << 14) ;- (CKGR) Please refer to the PLL datasheet +AT91C_CKGR_OUT_2 EQU (0x2 << 14) ;- (CKGR) Please refer to the PLL datasheet +AT91C_CKGR_OUT_3 EQU (0x3 << 14) ;- (CKGR) Please refer to the PLL datasheet +AT91C_CKGR_MUL EQU (0x7FF << 16) ;- (CKGR) PLL Multiplier +AT91C_CKGR_USBDIV EQU (0x3 << 28) ;- (CKGR) Divider for USB Clocks +AT91C_CKGR_USBDIV_0 EQU (0x0 << 28) ;- (CKGR) Divider output is PLL clock output +AT91C_CKGR_USBDIV_1 EQU (0x1 << 28) ;- (CKGR) Divider output is PLL clock output divided by 2 +AT91C_CKGR_USBDIV_2 EQU (0x2 << 28) ;- (CKGR) Divider output is PLL clock output divided by 4 + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Power Management Controler +// - ***************************************************************************** +// - -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +AT91C_PMC_PCK EQU (0x1 << 0) ;- (PMC) Processor Clock +AT91C_PMC_UDP EQU (0x1 << 7) ;- (PMC) USB Device Port Clock +AT91C_PMC_PCK0 EQU (0x1 << 8) ;- (PMC) Programmable Clock Output +AT91C_PMC_PCK1 EQU (0x1 << 9) ;- (PMC) Programmable Clock Output +AT91C_PMC_PCK2 EQU (0x1 << 10) ;- (PMC) Programmable Clock Output +// - -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// - -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// - -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// - -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// - -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- +// - -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +AT91C_PMC_CSS EQU (0x3 << 0) ;- (PMC) Programmable Clock Selection +AT91C_PMC_CSS_SLOW_CLK EQU (0x0) ;- (PMC) Slow Clock is selected +AT91C_PMC_CSS_MAIN_CLK EQU (0x1) ;- (PMC) Main Clock is selected +AT91C_PMC_CSS_PLL_CLK EQU (0x3) ;- (PMC) Clock from PLL is selected +AT91C_PMC_PRES EQU (0x7 << 2) ;- (PMC) Programmable Clock Prescaler +AT91C_PMC_PRES_CLK EQU (0x0 << 2) ;- (PMC) Selected clock +AT91C_PMC_PRES_CLK_2 EQU (0x1 << 2) ;- (PMC) Selected clock divided by 2 +AT91C_PMC_PRES_CLK_4 EQU (0x2 << 2) ;- (PMC) Selected clock divided by 4 +AT91C_PMC_PRES_CLK_8 EQU (0x3 << 2) ;- (PMC) Selected clock divided by 8 +AT91C_PMC_PRES_CLK_16 EQU (0x4 << 2) ;- (PMC) Selected clock divided by 16 +AT91C_PMC_PRES_CLK_32 EQU (0x5 << 2) ;- (PMC) Selected clock divided by 32 +AT91C_PMC_PRES_CLK_64 EQU (0x6 << 2) ;- (PMC) Selected clock divided by 64 +// - -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// - -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +AT91C_PMC_MOSCS EQU (0x1 << 0) ;- (PMC) MOSC Status/Enable/Disable/Mask +AT91C_PMC_LOCK EQU (0x1 << 2) ;- (PMC) PLL Status/Enable/Disable/Mask +AT91C_PMC_MCKRDY EQU (0x1 << 3) ;- (PMC) MCK_RDY Status/Enable/Disable/Mask +AT91C_PMC_PCK0RDY EQU (0x1 << 8) ;- (PMC) PCK0_RDY Status/Enable/Disable/Mask +AT91C_PMC_PCK1RDY EQU (0x1 << 9) ;- (PMC) PCK1_RDY Status/Enable/Disable/Mask +AT91C_PMC_PCK2RDY EQU (0x1 << 10) ;- (PMC) PCK2_RDY Status/Enable/Disable/Mask +// - -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// - -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// - -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Reset Controller Interface +// - ***************************************************************************** +// - -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +AT91C_RSTC_PROCRST EQU (0x1 << 0) ;- (RSTC) Processor Reset +AT91C_RSTC_PERRST EQU (0x1 << 2) ;- (RSTC) Peripheral Reset +AT91C_RSTC_EXTRST EQU (0x1 << 3) ;- (RSTC) External Reset +AT91C_RSTC_KEY EQU (0xFF << 24) ;- (RSTC) Password +// - -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +AT91C_RSTC_URSTS EQU (0x1 << 0) ;- (RSTC) User Reset Status +AT91C_RSTC_BODSTS EQU (0x1 << 1) ;- (RSTC) Brownout Detection Status +AT91C_RSTC_RSTTYP EQU (0x7 << 8) ;- (RSTC) Reset Type +AT91C_RSTC_RSTTYP_POWERUP EQU (0x0 << 8) ;- (RSTC) Power-up Reset. VDDCORE rising. +AT91C_RSTC_RSTTYP_WAKEUP EQU (0x1 << 8) ;- (RSTC) WakeUp Reset. VDDCORE rising. +AT91C_RSTC_RSTTYP_WATCHDOG EQU (0x2 << 8) ;- (RSTC) Watchdog Reset. Watchdog overflow occured. +AT91C_RSTC_RSTTYP_SOFTWARE EQU (0x3 << 8) ;- (RSTC) Software Reset. Processor reset required by the software. +AT91C_RSTC_RSTTYP_USER EQU (0x4 << 8) ;- (RSTC) User Reset. NRST pin detected low. +AT91C_RSTC_RSTTYP_BROWNOUT EQU (0x5 << 8) ;- (RSTC) Brownout Reset occured. +AT91C_RSTC_NRSTL EQU (0x1 << 16) ;- (RSTC) NRST pin level +AT91C_RSTC_SRCMP EQU (0x1 << 17) ;- (RSTC) Software Reset Command in Progress. +// - -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +AT91C_RSTC_URSTEN EQU (0x1 << 0) ;- (RSTC) User Reset Enable +AT91C_RSTC_URSTIEN EQU (0x1 << 4) ;- (RSTC) User Reset Interrupt Enable +AT91C_RSTC_ERSTL EQU (0xF << 8) ;- (RSTC) User Reset Enable +AT91C_RSTC_BODIEN EQU (0x1 << 16) ;- (RSTC) Brownout Detection Interrupt Enable + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// - ***************************************************************************** +// - -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +AT91C_RTTC_RTPRES EQU (0xFFFF << 0) ;- (RTTC) Real-time Timer Prescaler Value +AT91C_RTTC_ALMIEN EQU (0x1 << 16) ;- (RTTC) Alarm Interrupt Enable +AT91C_RTTC_RTTINCIEN EQU (0x1 << 17) ;- (RTTC) Real Time Timer Increment Interrupt Enable +AT91C_RTTC_RTTRST EQU (0x1 << 18) ;- (RTTC) Real Time Timer Restart +// - -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +AT91C_RTTC_ALMV EQU (0x0 << 0) ;- (RTTC) Alarm Value +// - -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +AT91C_RTTC_CRTV EQU (0x0 << 0) ;- (RTTC) Current Real-time Value +// - -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +AT91C_RTTC_ALMS EQU (0x1 << 0) ;- (RTTC) Real-time Alarm Status +AT91C_RTTC_RTTINC EQU (0x1 << 1) ;- (RTTC) Real-time Timer Increment + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// - ***************************************************************************** +// - -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +AT91C_PITC_PIV EQU (0xFFFFF << 0) ;- (PITC) Periodic Interval Value +AT91C_PITC_PITEN EQU (0x1 << 24) ;- (PITC) Periodic Interval Timer Enabled +AT91C_PITC_PITIEN EQU (0x1 << 25) ;- (PITC) Periodic Interval Timer Interrupt Enable +// - -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +AT91C_PITC_PITS EQU (0x1 << 0) ;- (PITC) Periodic Interval Timer Status +// - -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +AT91C_PITC_CPIV EQU (0xFFFFF << 0) ;- (PITC) Current Periodic Interval Value +AT91C_PITC_PICNT EQU (0xFFF << 20) ;- (PITC) Periodic Interval Counter +// - -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// - ***************************************************************************** +// - -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +AT91C_WDTC_WDRSTT EQU (0x1 << 0) ;- (WDTC) Watchdog Restart +AT91C_WDTC_KEY EQU (0xFF << 24) ;- (WDTC) Watchdog KEY Password +// - -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +AT91C_WDTC_WDV EQU (0xFFF << 0) ;- (WDTC) Watchdog Timer Restart +AT91C_WDTC_WDFIEN EQU (0x1 << 12) ;- (WDTC) Watchdog Fault Interrupt Enable +AT91C_WDTC_WDRSTEN EQU (0x1 << 13) ;- (WDTC) Watchdog Reset Enable +AT91C_WDTC_WDRPROC EQU (0x1 << 14) ;- (WDTC) Watchdog Timer Restart +AT91C_WDTC_WDDIS EQU (0x1 << 15) ;- (WDTC) Watchdog Disable +AT91C_WDTC_WDD EQU (0xFFF << 16) ;- (WDTC) Watchdog Delta Value +AT91C_WDTC_WDDBGHLT EQU (0x1 << 28) ;- (WDTC) Watchdog Debug Halt +AT91C_WDTC_WDIDLEHLT EQU (0x1 << 29) ;- (WDTC) Watchdog Idle Halt +// - -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +AT91C_WDTC_WDUNF EQU (0x1 << 0) ;- (WDTC) Watchdog Underflow +AT91C_WDTC_WDERR EQU (0x1 << 1) ;- (WDTC) Watchdog Error + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface +// - ***************************************************************************** +// - -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- +AT91C_VREG_PSTDBY EQU (0x1 << 0) ;- (VREG) Voltage Regulator Power Standby Mode + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Memory Controller Interface +// - ***************************************************************************** +// - -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +AT91C_MC_RCB EQU (0x1 << 0) ;- (MC) Remap Command Bit +// - -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +AT91C_MC_UNDADD EQU (0x1 << 0) ;- (MC) Undefined Addess Abort Status +AT91C_MC_MISADD EQU (0x1 << 1) ;- (MC) Misaligned Addess Abort Status +AT91C_MC_ABTSZ EQU (0x3 << 8) ;- (MC) Abort Size Status +AT91C_MC_ABTSZ_BYTE EQU (0x0 << 8) ;- (MC) Byte +AT91C_MC_ABTSZ_HWORD EQU (0x1 << 8) ;- (MC) Half-word +AT91C_MC_ABTSZ_WORD EQU (0x2 << 8) ;- (MC) Word +AT91C_MC_ABTTYP EQU (0x3 << 10) ;- (MC) Abort Type Status +AT91C_MC_ABTTYP_DATAR EQU (0x0 << 10) ;- (MC) Data Read +AT91C_MC_ABTTYP_DATAW EQU (0x1 << 10) ;- (MC) Data Write +AT91C_MC_ABTTYP_FETCH EQU (0x2 << 10) ;- (MC) Code Fetch +AT91C_MC_MST0 EQU (0x1 << 16) ;- (MC) Master 0 Abort Source +AT91C_MC_MST1 EQU (0x1 << 17) ;- (MC) Master 1 Abort Source +AT91C_MC_SVMST0 EQU (0x1 << 24) ;- (MC) Saved Master 0 Abort Source +AT91C_MC_SVMST1 EQU (0x1 << 25) ;- (MC) Saved Master 1 Abort Source +// - -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- +AT91C_MC_FRDY EQU (0x1 << 0) ;- (MC) Flash Ready +AT91C_MC_LOCKE EQU (0x1 << 2) ;- (MC) Lock Error +AT91C_MC_PROGE EQU (0x1 << 3) ;- (MC) Programming Error +AT91C_MC_NEBP EQU (0x1 << 7) ;- (MC) No Erase Before Programming +AT91C_MC_FWS EQU (0x3 << 8) ;- (MC) Flash Wait State +AT91C_MC_FWS_0FWS EQU (0x0 << 8) ;- (MC) 1 cycle for Read, 2 for Write operations +AT91C_MC_FWS_1FWS EQU (0x1 << 8) ;- (MC) 2 cycles for Read, 3 for Write operations +AT91C_MC_FWS_2FWS EQU (0x2 << 8) ;- (MC) 3 cycles for Read, 4 for Write operations +AT91C_MC_FWS_3FWS EQU (0x3 << 8) ;- (MC) 4 cycles for Read, 4 for Write operations +AT91C_MC_FMCN EQU (0xFF << 16) ;- (MC) Flash Microsecond Cycle Number +// - -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- +AT91C_MC_FCMD EQU (0xF << 0) ;- (MC) Flash Command +AT91C_MC_FCMD_START_PROG EQU (0x1) ;- (MC) Starts the programming of th epage specified by PAGEN. +AT91C_MC_FCMD_LOCK EQU (0x2) ;- (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +AT91C_MC_FCMD_PROG_AND_LOCK EQU (0x3) ;- (MC) The lock sequence automatically happens after the programming sequence is completed. +AT91C_MC_FCMD_UNLOCK EQU (0x4) ;- (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +AT91C_MC_FCMD_ERASE_ALL EQU (0x8) ;- (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. +AT91C_MC_FCMD_SET_GP_NVM EQU (0xB) ;- (MC) Set General Purpose NVM bits. +AT91C_MC_FCMD_CLR_GP_NVM EQU (0xD) ;- (MC) Clear General Purpose NVM bits. +AT91C_MC_FCMD_SET_SECURITY EQU (0xF) ;- (MC) Set Security Bit. +AT91C_MC_PAGEN EQU (0x3FF << 8) ;- (MC) Page Number +AT91C_MC_KEY EQU (0xFF << 24) ;- (MC) Writing Protect Key +// - -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- +AT91C_MC_SECURITY EQU (0x1 << 4) ;- (MC) Security Bit Status +AT91C_MC_GPNVM0 EQU (0x1 << 8) ;- (MC) Sector 0 Lock Status +AT91C_MC_GPNVM1 EQU (0x1 << 9) ;- (MC) Sector 1 Lock Status +AT91C_MC_GPNVM2 EQU (0x1 << 10) ;- (MC) Sector 2 Lock Status +AT91C_MC_GPNVM3 EQU (0x1 << 11) ;- (MC) Sector 3 Lock Status +AT91C_MC_GPNVM4 EQU (0x1 << 12) ;- (MC) Sector 4 Lock Status +AT91C_MC_GPNVM5 EQU (0x1 << 13) ;- (MC) Sector 5 Lock Status +AT91C_MC_GPNVM6 EQU (0x1 << 14) ;- (MC) Sector 6 Lock Status +AT91C_MC_GPNVM7 EQU (0x1 << 15) ;- (MC) Sector 7 Lock Status +AT91C_MC_LOCKS0 EQU (0x1 << 16) ;- (MC) Sector 0 Lock Status +AT91C_MC_LOCKS1 EQU (0x1 << 17) ;- (MC) Sector 1 Lock Status +AT91C_MC_LOCKS2 EQU (0x1 << 18) ;- (MC) Sector 2 Lock Status +AT91C_MC_LOCKS3 EQU (0x1 << 19) ;- (MC) Sector 3 Lock Status +AT91C_MC_LOCKS4 EQU (0x1 << 20) ;- (MC) Sector 4 Lock Status +AT91C_MC_LOCKS5 EQU (0x1 << 21) ;- (MC) Sector 5 Lock Status +AT91C_MC_LOCKS6 EQU (0x1 << 22) ;- (MC) Sector 6 Lock Status +AT91C_MC_LOCKS7 EQU (0x1 << 23) ;- (MC) Sector 7 Lock Status +AT91C_MC_LOCKS8 EQU (0x1 << 24) ;- (MC) Sector 8 Lock Status +AT91C_MC_LOCKS9 EQU (0x1 << 25) ;- (MC) Sector 9 Lock Status +AT91C_MC_LOCKS10 EQU (0x1 << 26) ;- (MC) Sector 10 Lock Status +AT91C_MC_LOCKS11 EQU (0x1 << 27) ;- (MC) Sector 11 Lock Status +AT91C_MC_LOCKS12 EQU (0x1 << 28) ;- (MC) Sector 12 Lock Status +AT91C_MC_LOCKS13 EQU (0x1 << 29) ;- (MC) Sector 13 Lock Status +AT91C_MC_LOCKS14 EQU (0x1 << 30) ;- (MC) Sector 14 Lock Status +AT91C_MC_LOCKS15 EQU (0x1 << 31) ;- (MC) Sector 15 Lock Status + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Serial Parallel Interface +// - ***************************************************************************** +// - -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +AT91C_SPI_SPIEN EQU (0x1 << 0) ;- (SPI) SPI Enable +AT91C_SPI_SPIDIS EQU (0x1 << 1) ;- (SPI) SPI Disable +AT91C_SPI_SWRST EQU (0x1 << 7) ;- (SPI) SPI Software reset +AT91C_SPI_LASTXFER EQU (0x1 << 24) ;- (SPI) SPI Last Transfer +// - -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +AT91C_SPI_MSTR EQU (0x1 << 0) ;- (SPI) Master/Slave Mode +AT91C_SPI_PS EQU (0x1 << 1) ;- (SPI) Peripheral Select +AT91C_SPI_PS_FIXED EQU (0x0 << 1) ;- (SPI) Fixed Peripheral Select +AT91C_SPI_PS_VARIABLE EQU (0x1 << 1) ;- (SPI) Variable Peripheral Select +AT91C_SPI_PCSDEC EQU (0x1 << 2) ;- (SPI) Chip Select Decode +AT91C_SPI_FDIV EQU (0x1 << 3) ;- (SPI) Clock Selection +AT91C_SPI_MODFDIS EQU (0x1 << 4) ;- (SPI) Mode Fault Detection +AT91C_SPI_LLB EQU (0x1 << 7) ;- (SPI) Clock Selection +AT91C_SPI_PCS EQU (0xF << 16) ;- (SPI) Peripheral Chip Select +AT91C_SPI_DLYBCS EQU (0xFF << 24) ;- (SPI) Delay Between Chip Selects +// - -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +AT91C_SPI_RD EQU (0xFFFF << 0) ;- (SPI) Receive Data +AT91C_SPI_RPCS EQU (0xF << 16) ;- (SPI) Peripheral Chip Select Status +// - -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +AT91C_SPI_TD EQU (0xFFFF << 0) ;- (SPI) Transmit Data +AT91C_SPI_TPCS EQU (0xF << 16) ;- (SPI) Peripheral Chip Select Status +// - -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +AT91C_SPI_RDRF EQU (0x1 << 0) ;- (SPI) Receive Data Register Full +AT91C_SPI_TDRE EQU (0x1 << 1) ;- (SPI) Transmit Data Register Empty +AT91C_SPI_MODF EQU (0x1 << 2) ;- (SPI) Mode Fault Error +AT91C_SPI_OVRES EQU (0x1 << 3) ;- (SPI) Overrun Error Status +AT91C_SPI_ENDRX EQU (0x1 << 4) ;- (SPI) End of Receiver Transfer +AT91C_SPI_ENDTX EQU (0x1 << 5) ;- (SPI) End of Receiver Transfer +AT91C_SPI_RXBUFF EQU (0x1 << 6) ;- (SPI) RXBUFF Interrupt +AT91C_SPI_TXBUFE EQU (0x1 << 7) ;- (SPI) TXBUFE Interrupt +AT91C_SPI_NSSR EQU (0x1 << 8) ;- (SPI) NSSR Interrupt +AT91C_SPI_TXEMPTY EQU (0x1 << 9) ;- (SPI) TXEMPTY Interrupt +AT91C_SPI_SPIENS EQU (0x1 << 16) ;- (SPI) Enable Status +// - -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// - -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// - -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// - -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +AT91C_SPI_CPOL EQU (0x1 << 0) ;- (SPI) Clock Polarity +AT91C_SPI_NCPHA EQU (0x1 << 1) ;- (SPI) Clock Phase +AT91C_SPI_CSAAT EQU (0x1 << 3) ;- (SPI) Chip Select Active After Transfer +AT91C_SPI_BITS EQU (0xF << 4) ;- (SPI) Bits Per Transfer +AT91C_SPI_BITS_8 EQU (0x0 << 4) ;- (SPI) 8 Bits Per transfer +AT91C_SPI_BITS_9 EQU (0x1 << 4) ;- (SPI) 9 Bits Per transfer +AT91C_SPI_BITS_10 EQU (0x2 << 4) ;- (SPI) 10 Bits Per transfer +AT91C_SPI_BITS_11 EQU (0x3 << 4) ;- (SPI) 11 Bits Per transfer +AT91C_SPI_BITS_12 EQU (0x4 << 4) ;- (SPI) 12 Bits Per transfer +AT91C_SPI_BITS_13 EQU (0x5 << 4) ;- (SPI) 13 Bits Per transfer +AT91C_SPI_BITS_14 EQU (0x6 << 4) ;- (SPI) 14 Bits Per transfer +AT91C_SPI_BITS_15 EQU (0x7 << 4) ;- (SPI) 15 Bits Per transfer +AT91C_SPI_BITS_16 EQU (0x8 << 4) ;- (SPI) 16 Bits Per transfer +AT91C_SPI_SCBR EQU (0xFF << 8) ;- (SPI) Serial Clock Baud Rate +AT91C_SPI_DLYBS EQU (0xFF << 16) ;- (SPI) Serial Clock Baud Rate +AT91C_SPI_DLYBCT EQU (0xFF << 24) ;- (SPI) Delay Between Consecutive Transfers + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// - ***************************************************************************** +// - -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +AT91C_ADC_SWRST EQU (0x1 << 0) ;- (ADC) Software Reset +AT91C_ADC_START EQU (0x1 << 1) ;- (ADC) Start Conversion +// - -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +AT91C_ADC_TRGEN EQU (0x1 << 0) ;- (ADC) Trigger Enable +AT91C_ADC_TRGEN_DIS EQU (0x0) ;- (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +AT91C_ADC_TRGEN_EN EQU (0x1) ;- (ADC) Hardware trigger selected by TRGSEL field is enabled. +AT91C_ADC_TRGSEL EQU (0x7 << 1) ;- (ADC) Trigger Selection +AT91C_ADC_TRGSEL_TIOA0 EQU (0x0 << 1) ;- (ADC) Selected TRGSEL = TIAO0 +AT91C_ADC_TRGSEL_TIOA1 EQU (0x1 << 1) ;- (ADC) Selected TRGSEL = TIAO1 +AT91C_ADC_TRGSEL_TIOA2 EQU (0x2 << 1) ;- (ADC) Selected TRGSEL = TIAO2 +AT91C_ADC_TRGSEL_TIOA3 EQU (0x3 << 1) ;- (ADC) Selected TRGSEL = TIAO3 +AT91C_ADC_TRGSEL_TIOA4 EQU (0x4 << 1) ;- (ADC) Selected TRGSEL = TIAO4 +AT91C_ADC_TRGSEL_TIOA5 EQU (0x5 << 1) ;- (ADC) Selected TRGSEL = TIAO5 +AT91C_ADC_TRGSEL_EXT EQU (0x6 << 1) ;- (ADC) Selected TRGSEL = External Trigger +AT91C_ADC_LOWRES EQU (0x1 << 4) ;- (ADC) Resolution. +AT91C_ADC_LOWRES_10_BIT EQU (0x0 << 4) ;- (ADC) 10-bit resolution +AT91C_ADC_LOWRES_8_BIT EQU (0x1 << 4) ;- (ADC) 8-bit resolution +AT91C_ADC_SLEEP EQU (0x1 << 5) ;- (ADC) Sleep Mode +AT91C_ADC_SLEEP_NORMAL_MODE EQU (0x0 << 5) ;- (ADC) Normal Mode +AT91C_ADC_SLEEP_MODE EQU (0x1 << 5) ;- (ADC) Sleep Mode +AT91C_ADC_PRESCAL EQU (0x3F << 8) ;- (ADC) Prescaler rate selection +AT91C_ADC_STARTUP EQU (0x1F << 16) ;- (ADC) Startup Time +AT91C_ADC_SHTIM EQU (0xF << 24) ;- (ADC) Sample & Hold Time +// - -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +AT91C_ADC_CH0 EQU (0x1 << 0) ;- (ADC) Channel 0 +AT91C_ADC_CH1 EQU (0x1 << 1) ;- (ADC) Channel 1 +AT91C_ADC_CH2 EQU (0x1 << 2) ;- (ADC) Channel 2 +AT91C_ADC_CH3 EQU (0x1 << 3) ;- (ADC) Channel 3 +AT91C_ADC_CH4 EQU (0x1 << 4) ;- (ADC) Channel 4 +AT91C_ADC_CH5 EQU (0x1 << 5) ;- (ADC) Channel 5 +AT91C_ADC_CH6 EQU (0x1 << 6) ;- (ADC) Channel 6 +AT91C_ADC_CH7 EQU (0x1 << 7) ;- (ADC) Channel 7 +// - -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// - -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// - -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +AT91C_ADC_EOC0 EQU (0x1 << 0) ;- (ADC) End of Conversion +AT91C_ADC_EOC1 EQU (0x1 << 1) ;- (ADC) End of Conversion +AT91C_ADC_EOC2 EQU (0x1 << 2) ;- (ADC) End of Conversion +AT91C_ADC_EOC3 EQU (0x1 << 3) ;- (ADC) End of Conversion +AT91C_ADC_EOC4 EQU (0x1 << 4) ;- (ADC) End of Conversion +AT91C_ADC_EOC5 EQU (0x1 << 5) ;- (ADC) End of Conversion +AT91C_ADC_EOC6 EQU (0x1 << 6) ;- (ADC) End of Conversion +AT91C_ADC_EOC7 EQU (0x1 << 7) ;- (ADC) End of Conversion +AT91C_ADC_OVRE0 EQU (0x1 << 8) ;- (ADC) Overrun Error +AT91C_ADC_OVRE1 EQU (0x1 << 9) ;- (ADC) Overrun Error +AT91C_ADC_OVRE2 EQU (0x1 << 10) ;- (ADC) Overrun Error +AT91C_ADC_OVRE3 EQU (0x1 << 11) ;- (ADC) Overrun Error +AT91C_ADC_OVRE4 EQU (0x1 << 12) ;- (ADC) Overrun Error +AT91C_ADC_OVRE5 EQU (0x1 << 13) ;- (ADC) Overrun Error +AT91C_ADC_OVRE6 EQU (0x1 << 14) ;- (ADC) Overrun Error +AT91C_ADC_OVRE7 EQU (0x1 << 15) ;- (ADC) Overrun Error +AT91C_ADC_DRDY EQU (0x1 << 16) ;- (ADC) Data Ready +AT91C_ADC_GOVRE EQU (0x1 << 17) ;- (ADC) General Overrun +AT91C_ADC_ENDRX EQU (0x1 << 18) ;- (ADC) End of Receiver Transfer +AT91C_ADC_RXBUFF EQU (0x1 << 19) ;- (ADC) RXBUFF Interrupt +// - -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +AT91C_ADC_LDATA EQU (0x3FF << 0) ;- (ADC) Last Data Converted +// - -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// - -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// - -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// - -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +AT91C_ADC_DATA EQU (0x3FF << 0) ;- (ADC) Converted Data +// - -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// - -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// - -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// - -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// - -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// - -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// - -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// - ***************************************************************************** +// - -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +AT91C_SSC_RXEN EQU (0x1 << 0) ;- (SSC) Receive Enable +AT91C_SSC_RXDIS EQU (0x1 << 1) ;- (SSC) Receive Disable +AT91C_SSC_TXEN EQU (0x1 << 8) ;- (SSC) Transmit Enable +AT91C_SSC_TXDIS EQU (0x1 << 9) ;- (SSC) Transmit Disable +AT91C_SSC_SWRST EQU (0x1 << 15) ;- (SSC) Software Reset +// - -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +AT91C_SSC_CKS EQU (0x3 << 0) ;- (SSC) Receive/Transmit Clock Selection +AT91C_SSC_CKS_DIV EQU (0x0) ;- (SSC) Divided Clock +AT91C_SSC_CKS_TK EQU (0x1) ;- (SSC) TK Clock signal +AT91C_SSC_CKS_RK EQU (0x2) ;- (SSC) RK pin +AT91C_SSC_CKO EQU (0x7 << 2) ;- (SSC) Receive/Transmit Clock Output Mode Selection +AT91C_SSC_CKO_NONE EQU (0x0 << 2) ;- (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +AT91C_SSC_CKO_CONTINOUS EQU (0x1 << 2) ;- (SSC) Continuous Receive/Transmit Clock RK pin: Output +AT91C_SSC_CKO_DATA_TX EQU (0x2 << 2) ;- (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +AT91C_SSC_CKI EQU (0x1 << 5) ;- (SSC) Receive/Transmit Clock Inversion +AT91C_SSC_START EQU (0xF << 8) ;- (SSC) Receive/Transmit Start Selection +AT91C_SSC_START_CONTINOUS EQU (0x0 << 8) ;- (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +AT91C_SSC_START_TX EQU (0x1 << 8) ;- (SSC) Transmit/Receive start +AT91C_SSC_START_LOW_RF EQU (0x2 << 8) ;- (SSC) Detection of a low level on RF input +AT91C_SSC_START_HIGH_RF EQU (0x3 << 8) ;- (SSC) Detection of a high level on RF input +AT91C_SSC_START_FALL_RF EQU (0x4 << 8) ;- (SSC) Detection of a falling edge on RF input +AT91C_SSC_START_RISE_RF EQU (0x5 << 8) ;- (SSC) Detection of a rising edge on RF input +AT91C_SSC_START_LEVEL_RF EQU (0x6 << 8) ;- (SSC) Detection of any level change on RF input +AT91C_SSC_START_EDGE_RF EQU (0x7 << 8) ;- (SSC) Detection of any edge on RF input +AT91C_SSC_START_0 EQU (0x8 << 8) ;- (SSC) Compare 0 +AT91C_SSC_STTDLY EQU (0xFF << 16) ;- (SSC) Receive/Transmit Start Delay +AT91C_SSC_PERIOD EQU (0xFF << 24) ;- (SSC) Receive/Transmit Period Divider Selection +// - -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +AT91C_SSC_DATLEN EQU (0x1F << 0) ;- (SSC) Data Length +AT91C_SSC_LOOP EQU (0x1 << 5) ;- (SSC) Loop Mode +AT91C_SSC_MSBF EQU (0x1 << 7) ;- (SSC) Most Significant Bit First +AT91C_SSC_DATNB EQU (0xF << 8) ;- (SSC) Data Number per Frame +AT91C_SSC_FSLEN EQU (0xF << 16) ;- (SSC) Receive/Transmit Frame Sync length +AT91C_SSC_FSOS EQU (0x7 << 20) ;- (SSC) Receive/Transmit Frame Sync Output Selection +AT91C_SSC_FSOS_NONE EQU (0x0 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +AT91C_SSC_FSOS_NEGATIVE EQU (0x1 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +AT91C_SSC_FSOS_POSITIVE EQU (0x2 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +AT91C_SSC_FSOS_LOW EQU (0x3 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +AT91C_SSC_FSOS_HIGH EQU (0x4 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +AT91C_SSC_FSOS_TOGGLE EQU (0x5 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +AT91C_SSC_FSEDGE EQU (0x1 << 24) ;- (SSC) Frame Sync Edge Detection +// - -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// - -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +AT91C_SSC_DATDEF EQU (0x1 << 5) ;- (SSC) Data Default Value +AT91C_SSC_FSDEN EQU (0x1 << 23) ;- (SSC) Frame Sync Data Enable +// - -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +AT91C_SSC_TXRDY EQU (0x1 << 0) ;- (SSC) Transmit Ready +AT91C_SSC_TXEMPTY EQU (0x1 << 1) ;- (SSC) Transmit Empty +AT91C_SSC_ENDTX EQU (0x1 << 2) ;- (SSC) End Of Transmission +AT91C_SSC_TXBUFE EQU (0x1 << 3) ;- (SSC) Transmit Buffer Empty +AT91C_SSC_RXRDY EQU (0x1 << 4) ;- (SSC) Receive Ready +AT91C_SSC_OVRUN EQU (0x1 << 5) ;- (SSC) Receive Overrun +AT91C_SSC_ENDRX EQU (0x1 << 6) ;- (SSC) End of Reception +AT91C_SSC_RXBUFF EQU (0x1 << 7) ;- (SSC) Receive Buffer Full +AT91C_SSC_TXSYN EQU (0x1 << 10) ;- (SSC) Transmit Sync +AT91C_SSC_RXSYN EQU (0x1 << 11) ;- (SSC) Receive Sync +AT91C_SSC_TXENA EQU (0x1 << 16) ;- (SSC) Transmit Enable +AT91C_SSC_RXENA EQU (0x1 << 17) ;- (SSC) Receive Enable +// - -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// - -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// - -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Usart +// - ***************************************************************************** +// - -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +AT91C_US_STTBRK EQU (0x1 << 9) ;- (USART) Start Break +AT91C_US_STPBRK EQU (0x1 << 10) ;- (USART) Stop Break +AT91C_US_STTTO EQU (0x1 << 11) ;- (USART) Start Time-out +AT91C_US_SENDA EQU (0x1 << 12) ;- (USART) Send Address +AT91C_US_RSTIT EQU (0x1 << 13) ;- (USART) Reset Iterations +AT91C_US_RSTNACK EQU (0x1 << 14) ;- (USART) Reset Non Acknowledge +AT91C_US_RETTO EQU (0x1 << 15) ;- (USART) Rearm Time-out +AT91C_US_DTREN EQU (0x1 << 16) ;- (USART) Data Terminal ready Enable +AT91C_US_DTRDIS EQU (0x1 << 17) ;- (USART) Data Terminal ready Disable +AT91C_US_RTSEN EQU (0x1 << 18) ;- (USART) Request to Send enable +AT91C_US_RTSDIS EQU (0x1 << 19) ;- (USART) Request to Send Disable +// - -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +AT91C_US_USMODE EQU (0xF << 0) ;- (USART) Usart mode +AT91C_US_USMODE_NORMAL EQU (0x0) ;- (USART) Normal +AT91C_US_USMODE_RS485 EQU (0x1) ;- (USART) RS485 +AT91C_US_USMODE_HWHSH EQU (0x2) ;- (USART) Hardware Handshaking +AT91C_US_USMODE_MODEM EQU (0x3) ;- (USART) Modem +AT91C_US_USMODE_ISO7816_0 EQU (0x4) ;- (USART) ISO7816 protocol: T = 0 +AT91C_US_USMODE_ISO7816_1 EQU (0x6) ;- (USART) ISO7816 protocol: T = 1 +AT91C_US_USMODE_IRDA EQU (0x8) ;- (USART) IrDA +AT91C_US_USMODE_SWHSH EQU (0xC) ;- (USART) Software Handshaking +AT91C_US_CLKS EQU (0x3 << 4) ;- (USART) Clock Selection (Baud Rate generator Input Clock +AT91C_US_CLKS_CLOCK EQU (0x0 << 4) ;- (USART) Clock +AT91C_US_CLKS_FDIV1 EQU (0x1 << 4) ;- (USART) fdiv1 +AT91C_US_CLKS_SLOW EQU (0x2 << 4) ;- (USART) slow_clock (ARM) +AT91C_US_CLKS_EXT EQU (0x3 << 4) ;- (USART) External (SCK) +AT91C_US_CHRL EQU (0x3 << 6) ;- (USART) Clock Selection (Baud Rate generator Input Clock +AT91C_US_CHRL_5_BITS EQU (0x0 << 6) ;- (USART) Character Length: 5 bits +AT91C_US_CHRL_6_BITS EQU (0x1 << 6) ;- (USART) Character Length: 6 bits +AT91C_US_CHRL_7_BITS EQU (0x2 << 6) ;- (USART) Character Length: 7 bits +AT91C_US_CHRL_8_BITS EQU (0x3 << 6) ;- (USART) Character Length: 8 bits +AT91C_US_SYNC EQU (0x1 << 8) ;- (USART) Synchronous Mode Select +AT91C_US_NBSTOP EQU (0x3 << 12) ;- (USART) Number of Stop bits +AT91C_US_NBSTOP_1_BIT EQU (0x0 << 12) ;- (USART) 1 stop bit +AT91C_US_NBSTOP_15_BIT EQU (0x1 << 12) ;- (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +AT91C_US_NBSTOP_2_BIT EQU (0x2 << 12) ;- (USART) 2 stop bits +AT91C_US_MSBF EQU (0x1 << 16) ;- (USART) Bit Order +AT91C_US_MODE9 EQU (0x1 << 17) ;- (USART) 9-bit Character length +AT91C_US_CKLO EQU (0x1 << 18) ;- (USART) Clock Output Select +AT91C_US_OVER EQU (0x1 << 19) ;- (USART) Over Sampling Mode +AT91C_US_INACK EQU (0x1 << 20) ;- (USART) Inhibit Non Acknowledge +AT91C_US_DSNACK EQU (0x1 << 21) ;- (USART) Disable Successive NACK +AT91C_US_MAX_ITER EQU (0x1 << 24) ;- (USART) Number of Repetitions +AT91C_US_FILTER EQU (0x1 << 28) ;- (USART) Receive Line Filter +// - -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +AT91C_US_RXBRK EQU (0x1 << 2) ;- (USART) Break Received/End of Break +AT91C_US_TIMEOUT EQU (0x1 << 8) ;- (USART) Receiver Time-out +AT91C_US_ITERATION EQU (0x1 << 10) ;- (USART) Max number of Repetitions Reached +AT91C_US_NACK EQU (0x1 << 13) ;- (USART) Non Acknowledge +AT91C_US_RIIC EQU (0x1 << 16) ;- (USART) Ring INdicator Input Change Flag +AT91C_US_DSRIC EQU (0x1 << 17) ;- (USART) Data Set Ready Input Change Flag +AT91C_US_DCDIC EQU (0x1 << 18) ;- (USART) Data Carrier Flag +AT91C_US_CTSIC EQU (0x1 << 19) ;- (USART) Clear To Send Input Change Flag +// - -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// - -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// - -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +AT91C_US_RI EQU (0x1 << 20) ;- (USART) Image of RI Input +AT91C_US_DSR EQU (0x1 << 21) ;- (USART) Image of DSR Input +AT91C_US_DCD EQU (0x1 << 22) ;- (USART) Image of DCD Input +AT91C_US_CTS EQU (0x1 << 23) ;- (USART) Image of CTS Input + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Two-wire Interface +// - ***************************************************************************** +// - -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +AT91C_TWI_START EQU (0x1 << 0) ;- (TWI) Send a START Condition +AT91C_TWI_STOP EQU (0x1 << 1) ;- (TWI) Send a STOP Condition +AT91C_TWI_MSEN EQU (0x1 << 2) ;- (TWI) TWI Master Transfer Enabled +AT91C_TWI_MSDIS EQU (0x1 << 3) ;- (TWI) TWI Master Transfer Disabled +AT91C_TWI_SWRST EQU (0x1 << 7) ;- (TWI) Software Reset +// - -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +AT91C_TWI_IADRSZ EQU (0x3 << 8) ;- (TWI) Internal Device Address Size +AT91C_TWI_IADRSZ_NO EQU (0x0 << 8) ;- (TWI) No internal device address +AT91C_TWI_IADRSZ_1_BYTE EQU (0x1 << 8) ;- (TWI) One-byte internal device address +AT91C_TWI_IADRSZ_2_BYTE EQU (0x2 << 8) ;- (TWI) Two-byte internal device address +AT91C_TWI_IADRSZ_3_BYTE EQU (0x3 << 8) ;- (TWI) Three-byte internal device address +AT91C_TWI_MREAD EQU (0x1 << 12) ;- (TWI) Master Read Direction +AT91C_TWI_DADR EQU (0x7F << 16) ;- (TWI) Device Address +// - -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +AT91C_TWI_CLDIV EQU (0xFF << 0) ;- (TWI) Clock Low Divider +AT91C_TWI_CHDIV EQU (0xFF << 8) ;- (TWI) Clock High Divider +AT91C_TWI_CKDIV EQU (0x7 << 16) ;- (TWI) Clock Divider +// - -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +AT91C_TWI_TXCOMP EQU (0x1 << 0) ;- (TWI) Transmission Completed +AT91C_TWI_RXRDY EQU (0x1 << 1) ;- (TWI) Receive holding register ReaDY +AT91C_TWI_TXRDY EQU (0x1 << 2) ;- (TWI) Transmit holding register ReaDY +AT91C_TWI_OVRE EQU (0x1 << 6) ;- (TWI) Overrun Error +AT91C_TWI_UNRE EQU (0x1 << 7) ;- (TWI) Underrun Error +AT91C_TWI_NACK EQU (0x1 << 8) ;- (TWI) Not Acknowledged +// - -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// - -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// - -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// - ***************************************************************************** +// - -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +AT91C_TC_CLKEN EQU (0x1 << 0) ;- (TC) Counter Clock Enable Command +AT91C_TC_CLKDIS EQU (0x1 << 1) ;- (TC) Counter Clock Disable Command +AT91C_TC_SWTRG EQU (0x1 << 2) ;- (TC) Software Trigger Command +// - -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +AT91C_TC_CLKS EQU (0x7 << 0) ;- (TC) Clock Selection +AT91C_TC_CLKS_TIMER_DIV1_CLOCK EQU (0x0) ;- (TC) Clock selected: TIMER_DIV1_CLOCK +AT91C_TC_CLKS_TIMER_DIV2_CLOCK EQU (0x1) ;- (TC) Clock selected: TIMER_DIV2_CLOCK +AT91C_TC_CLKS_TIMER_DIV3_CLOCK EQU (0x2) ;- (TC) Clock selected: TIMER_DIV3_CLOCK +AT91C_TC_CLKS_TIMER_DIV4_CLOCK EQU (0x3) ;- (TC) Clock selected: TIMER_DIV4_CLOCK +AT91C_TC_CLKS_TIMER_DIV5_CLOCK EQU (0x4) ;- (TC) Clock selected: TIMER_DIV5_CLOCK +AT91C_TC_CLKS_XC0 EQU (0x5) ;- (TC) Clock selected: XC0 +AT91C_TC_CLKS_XC1 EQU (0x6) ;- (TC) Clock selected: XC1 +AT91C_TC_CLKS_XC2 EQU (0x7) ;- (TC) Clock selected: XC2 +AT91C_TC_CLKI EQU (0x1 << 3) ;- (TC) Clock Invert +AT91C_TC_BURST EQU (0x3 << 4) ;- (TC) Burst Signal Selection +AT91C_TC_BURST_NONE EQU (0x0 << 4) ;- (TC) The clock is not gated by an external signal +AT91C_TC_BURST_XC0 EQU (0x1 << 4) ;- (TC) XC0 is ANDed with the selected clock +AT91C_TC_BURST_XC1 EQU (0x2 << 4) ;- (TC) XC1 is ANDed with the selected clock +AT91C_TC_BURST_XC2 EQU (0x3 << 4) ;- (TC) XC2 is ANDed with the selected clock +AT91C_TC_CPCSTOP EQU (0x1 << 6) ;- (TC) Counter Clock Stopped with RC Compare +AT91C_TC_LDBSTOP EQU (0x1 << 6) ;- (TC) Counter Clock Stopped with RB Loading +AT91C_TC_CPCDIS EQU (0x1 << 7) ;- (TC) Counter Clock Disable with RC Compare +AT91C_TC_LDBDIS EQU (0x1 << 7) ;- (TC) Counter Clock Disabled with RB Loading +AT91C_TC_ETRGEDG EQU (0x3 << 8) ;- (TC) External Trigger Edge Selection +AT91C_TC_ETRGEDG_NONE EQU (0x0 << 8) ;- (TC) Edge: None +AT91C_TC_ETRGEDG_RISING EQU (0x1 << 8) ;- (TC) Edge: rising edge +AT91C_TC_ETRGEDG_FALLING EQU (0x2 << 8) ;- (TC) Edge: falling edge +AT91C_TC_ETRGEDG_BOTH EQU (0x3 << 8) ;- (TC) Edge: each edge +AT91C_TC_EEVTEDG EQU (0x3 << 8) ;- (TC) External Event Edge Selection +AT91C_TC_EEVTEDG_NONE EQU (0x0 << 8) ;- (TC) Edge: None +AT91C_TC_EEVTEDG_RISING EQU (0x1 << 8) ;- (TC) Edge: rising edge +AT91C_TC_EEVTEDG_FALLING EQU (0x2 << 8) ;- (TC) Edge: falling edge +AT91C_TC_EEVTEDG_BOTH EQU (0x3 << 8) ;- (TC) Edge: each edge +AT91C_TC_EEVT EQU (0x3 << 10) ;- (TC) External Event Selection +AT91C_TC_EEVT_TIOB EQU (0x0 << 10) ;- (TC) Signal selected as external event: TIOB TIOB direction: input +AT91C_TC_EEVT_XC0 EQU (0x1 << 10) ;- (TC) Signal selected as external event: XC0 TIOB direction: output +AT91C_TC_EEVT_XC1 EQU (0x2 << 10) ;- (TC) Signal selected as external event: XC1 TIOB direction: output +AT91C_TC_EEVT_XC2 EQU (0x3 << 10) ;- (TC) Signal selected as external event: XC2 TIOB direction: output +AT91C_TC_ABETRG EQU (0x1 << 10) ;- (TC) TIOA or TIOB External Trigger Selection +AT91C_TC_ENETRG EQU (0x1 << 12) ;- (TC) External Event Trigger enable +AT91C_TC_WAVESEL EQU (0x3 << 13) ;- (TC) Waveform Selection +AT91C_TC_WAVESEL_UP EQU (0x0 << 13) ;- (TC) UP mode without atomatic trigger on RC Compare +AT91C_TC_WAVESEL_UPDOWN EQU (0x1 << 13) ;- (TC) UPDOWN mode without automatic trigger on RC Compare +AT91C_TC_WAVESEL_UP_AUTO EQU (0x2 << 13) ;- (TC) UP mode with automatic trigger on RC Compare +AT91C_TC_WAVESEL_UPDOWN_AUTO EQU (0x3 << 13) ;- (TC) UPDOWN mode with automatic trigger on RC Compare +AT91C_TC_CPCTRG EQU (0x1 << 14) ;- (TC) RC Compare Trigger Enable +AT91C_TC_WAVE EQU (0x1 << 15) ;- (TC) +AT91C_TC_ACPA EQU (0x3 << 16) ;- (TC) RA Compare Effect on TIOA +AT91C_TC_ACPA_NONE EQU (0x0 << 16) ;- (TC) Effect: none +AT91C_TC_ACPA_SET EQU (0x1 << 16) ;- (TC) Effect: set +AT91C_TC_ACPA_CLEAR EQU (0x2 << 16) ;- (TC) Effect: clear +AT91C_TC_ACPA_TOGGLE EQU (0x3 << 16) ;- (TC) Effect: toggle +AT91C_TC_LDRA EQU (0x3 << 16) ;- (TC) RA Loading Selection +AT91C_TC_LDRA_NONE EQU (0x0 << 16) ;- (TC) Edge: None +AT91C_TC_LDRA_RISING EQU (0x1 << 16) ;- (TC) Edge: rising edge of TIOA +AT91C_TC_LDRA_FALLING EQU (0x2 << 16) ;- (TC) Edge: falling edge of TIOA +AT91C_TC_LDRA_BOTH EQU (0x3 << 16) ;- (TC) Edge: each edge of TIOA +AT91C_TC_ACPC EQU (0x3 << 18) ;- (TC) RC Compare Effect on TIOA +AT91C_TC_ACPC_NONE EQU (0x0 << 18) ;- (TC) Effect: none +AT91C_TC_ACPC_SET EQU (0x1 << 18) ;- (TC) Effect: set +AT91C_TC_ACPC_CLEAR EQU (0x2 << 18) ;- (TC) Effect: clear +AT91C_TC_ACPC_TOGGLE EQU (0x3 << 18) ;- (TC) Effect: toggle +AT91C_TC_LDRB EQU (0x3 << 18) ;- (TC) RB Loading Selection +AT91C_TC_LDRB_NONE EQU (0x0 << 18) ;- (TC) Edge: None +AT91C_TC_LDRB_RISING EQU (0x1 << 18) ;- (TC) Edge: rising edge of TIOA +AT91C_TC_LDRB_FALLING EQU (0x2 << 18) ;- (TC) Edge: falling edge of TIOA +AT91C_TC_LDRB_BOTH EQU (0x3 << 18) ;- (TC) Edge: each edge of TIOA +AT91C_TC_AEEVT EQU (0x3 << 20) ;- (TC) External Event Effect on TIOA +AT91C_TC_AEEVT_NONE EQU (0x0 << 20) ;- (TC) Effect: none +AT91C_TC_AEEVT_SET EQU (0x1 << 20) ;- (TC) Effect: set +AT91C_TC_AEEVT_CLEAR EQU (0x2 << 20) ;- (TC) Effect: clear +AT91C_TC_AEEVT_TOGGLE EQU (0x3 << 20) ;- (TC) Effect: toggle +AT91C_TC_ASWTRG EQU (0x3 << 22) ;- (TC) Software Trigger Effect on TIOA +AT91C_TC_ASWTRG_NONE EQU (0x0 << 22) ;- (TC) Effect: none +AT91C_TC_ASWTRG_SET EQU (0x1 << 22) ;- (TC) Effect: set +AT91C_TC_ASWTRG_CLEAR EQU (0x2 << 22) ;- (TC) Effect: clear +AT91C_TC_ASWTRG_TOGGLE EQU (0x3 << 22) ;- (TC) Effect: toggle +AT91C_TC_BCPB EQU (0x3 << 24) ;- (TC) RB Compare Effect on TIOB +AT91C_TC_BCPB_NONE EQU (0x0 << 24) ;- (TC) Effect: none +AT91C_TC_BCPB_SET EQU (0x1 << 24) ;- (TC) Effect: set +AT91C_TC_BCPB_CLEAR EQU (0x2 << 24) ;- (TC) Effect: clear +AT91C_TC_BCPB_TOGGLE EQU (0x3 << 24) ;- (TC) Effect: toggle +AT91C_TC_BCPC EQU (0x3 << 26) ;- (TC) RC Compare Effect on TIOB +AT91C_TC_BCPC_NONE EQU (0x0 << 26) ;- (TC) Effect: none +AT91C_TC_BCPC_SET EQU (0x1 << 26) ;- (TC) Effect: set +AT91C_TC_BCPC_CLEAR EQU (0x2 << 26) ;- (TC) Effect: clear +AT91C_TC_BCPC_TOGGLE EQU (0x3 << 26) ;- (TC) Effect: toggle +AT91C_TC_BEEVT EQU (0x3 << 28) ;- (TC) External Event Effect on TIOB +AT91C_TC_BEEVT_NONE EQU (0x0 << 28) ;- (TC) Effect: none +AT91C_TC_BEEVT_SET EQU (0x1 << 28) ;- (TC) Effect: set +AT91C_TC_BEEVT_CLEAR EQU (0x2 << 28) ;- (TC) Effect: clear +AT91C_TC_BEEVT_TOGGLE EQU (0x3 << 28) ;- (TC) Effect: toggle +AT91C_TC_BSWTRG EQU (0x3 << 30) ;- (TC) Software Trigger Effect on TIOB +AT91C_TC_BSWTRG_NONE EQU (0x0 << 30) ;- (TC) Effect: none +AT91C_TC_BSWTRG_SET EQU (0x1 << 30) ;- (TC) Effect: set +AT91C_TC_BSWTRG_CLEAR EQU (0x2 << 30) ;- (TC) Effect: clear +AT91C_TC_BSWTRG_TOGGLE EQU (0x3 << 30) ;- (TC) Effect: toggle +// - -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +AT91C_TC_COVFS EQU (0x1 << 0) ;- (TC) Counter Overflow +AT91C_TC_LOVRS EQU (0x1 << 1) ;- (TC) Load Overrun +AT91C_TC_CPAS EQU (0x1 << 2) ;- (TC) RA Compare +AT91C_TC_CPBS EQU (0x1 << 3) ;- (TC) RB Compare +AT91C_TC_CPCS EQU (0x1 << 4) ;- (TC) RC Compare +AT91C_TC_LDRAS EQU (0x1 << 5) ;- (TC) RA Loading +AT91C_TC_LDRBS EQU (0x1 << 6) ;- (TC) RB Loading +AT91C_TC_ETRGS EQU (0x1 << 7) ;- (TC) External Trigger +AT91C_TC_CLKSTA EQU (0x1 << 16) ;- (TC) Clock Enabling +AT91C_TC_MTIOA EQU (0x1 << 17) ;- (TC) TIOA Mirror +AT91C_TC_MTIOB EQU (0x1 << 18) ;- (TC) TIOA Mirror +// - -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// - -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// - -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Timer Counter Interface +// - ***************************************************************************** +// - -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +AT91C_TCB_SYNC EQU (0x1 << 0) ;- (TCB) Synchro Command +// - -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +AT91C_TCB_TC0XC0S EQU (0x3 << 0) ;- (TCB) External Clock Signal 0 Selection +AT91C_TCB_TC0XC0S_TCLK0 EQU (0x0) ;- (TCB) TCLK0 connected to XC0 +AT91C_TCB_TC0XC0S_NONE EQU (0x1) ;- (TCB) None signal connected to XC0 +AT91C_TCB_TC0XC0S_TIOA1 EQU (0x2) ;- (TCB) TIOA1 connected to XC0 +AT91C_TCB_TC0XC0S_TIOA2 EQU (0x3) ;- (TCB) TIOA2 connected to XC0 +AT91C_TCB_TC1XC1S EQU (0x3 << 2) ;- (TCB) External Clock Signal 1 Selection +AT91C_TCB_TC1XC1S_TCLK1 EQU (0x0 << 2) ;- (TCB) TCLK1 connected to XC1 +AT91C_TCB_TC1XC1S_NONE EQU (0x1 << 2) ;- (TCB) None signal connected to XC1 +AT91C_TCB_TC1XC1S_TIOA0 EQU (0x2 << 2) ;- (TCB) TIOA0 connected to XC1 +AT91C_TCB_TC1XC1S_TIOA2 EQU (0x3 << 2) ;- (TCB) TIOA2 connected to XC1 +AT91C_TCB_TC2XC2S EQU (0x3 << 4) ;- (TCB) External Clock Signal 2 Selection +AT91C_TCB_TC2XC2S_TCLK2 EQU (0x0 << 4) ;- (TCB) TCLK2 connected to XC2 +AT91C_TCB_TC2XC2S_NONE EQU (0x1 << 4) ;- (TCB) None signal connected to XC2 +AT91C_TCB_TC2XC2S_TIOA0 EQU (0x2 << 4) ;- (TCB) TIOA0 connected to XC2 +AT91C_TCB_TC2XC2S_TIOA1 EQU (0x3 << 4) ;- (TCB) TIOA2 connected to XC2 + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR PWMC Channel Interface +// - ***************************************************************************** +// - -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- +AT91C_PWMC_CPRE EQU (0xF << 0) ;- (PWMC_CH) Channel Pre-scaler : PWMC_CLKx +AT91C_PWMC_CPRE_MCK EQU (0x0) ;- (PWMC_CH) +AT91C_PWMC_CPRE_MCKA EQU (0xB) ;- (PWMC_CH) +AT91C_PWMC_CPRE_MCKB EQU (0xC) ;- (PWMC_CH) +AT91C_PWMC_CALG EQU (0x1 << 8) ;- (PWMC_CH) Channel Alignment +AT91C_PWMC_CPOL EQU (0x1 << 9) ;- (PWMC_CH) Channel Polarity +AT91C_PWMC_CPD EQU (0x1 << 10) ;- (PWMC_CH) Channel Update Period +// - -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- +AT91C_PWMC_CDTY EQU (0x0 << 0) ;- (PWMC_CH) Channel Duty Cycle +// - -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- +AT91C_PWMC_CPRD EQU (0x0 << 0) ;- (PWMC_CH) Channel Period +// - -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- +AT91C_PWMC_CCNT EQU (0x0 << 0) ;- (PWMC_CH) Channel Counter +// - -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- +AT91C_PWMC_CUPD EQU (0x0 << 0) ;- (PWMC_CH) Channel Update + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface +// - ***************************************************************************** +// - -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- +AT91C_PWMC_DIVA EQU (0xFF << 0) ;- (PWMC) CLKA divide factor. +AT91C_PWMC_PREA EQU (0xF << 8) ;- (PWMC) Divider Input Clock Prescaler A +AT91C_PWMC_PREA_MCK EQU (0x0 << 8) ;- (PWMC) +AT91C_PWMC_DIVB EQU (0xFF << 16) ;- (PWMC) CLKB divide factor. +AT91C_PWMC_PREB EQU (0xF << 24) ;- (PWMC) Divider Input Clock Prescaler B +AT91C_PWMC_PREB_MCK EQU (0x0 << 24) ;- (PWMC) +// - -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- +AT91C_PWMC_CHID0 EQU (0x1 << 0) ;- (PWMC) Channel ID 0 +AT91C_PWMC_CHID1 EQU (0x1 << 1) ;- (PWMC) Channel ID 1 +AT91C_PWMC_CHID2 EQU (0x1 << 2) ;- (PWMC) Channel ID 2 +AT91C_PWMC_CHID3 EQU (0x1 << 3) ;- (PWMC) Channel ID 3 +AT91C_PWMC_CHID4 EQU (0x1 << 4) ;- (PWMC) Channel ID 4 +AT91C_PWMC_CHID5 EQU (0x1 << 5) ;- (PWMC) Channel ID 5 +AT91C_PWMC_CHID6 EQU (0x1 << 6) ;- (PWMC) Channel ID 6 +AT91C_PWMC_CHID7 EQU (0x1 << 7) ;- (PWMC) Channel ID 7 +// - -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- +// - -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- +// - -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- +// - -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- +// - -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- +// - -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR USB Device Interface +// - ***************************************************************************** +// - -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +AT91C_UDP_FRM_NUM EQU (0x7FF << 0) ;- (UDP) Frame Number as Defined in the Packet Field Formats +AT91C_UDP_FRM_ERR EQU (0x1 << 16) ;- (UDP) Frame Error +AT91C_UDP_FRM_OK EQU (0x1 << 17) ;- (UDP) Frame OK +// - -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +AT91C_UDP_FADDEN EQU (0x1 << 0) ;- (UDP) Function Address Enable +AT91C_UDP_CONFG EQU (0x1 << 1) ;- (UDP) Configured +AT91C_UDP_ESR EQU (0x1 << 2) ;- (UDP) Enable Send Resume +AT91C_UDP_RSMINPR EQU (0x1 << 3) ;- (UDP) A Resume Has Been Sent to the Host +AT91C_UDP_RMWUPE EQU (0x1 << 4) ;- (UDP) Remote Wake Up Enable +// - -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +AT91C_UDP_FADD EQU (0xFF << 0) ;- (UDP) Function Address Value +AT91C_UDP_FEN EQU (0x1 << 8) ;- (UDP) Function Enable +// - -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +AT91C_UDP_EPINT0 EQU (0x1 << 0) ;- (UDP) Endpoint 0 Interrupt +AT91C_UDP_EPINT1 EQU (0x1 << 1) ;- (UDP) Endpoint 0 Interrupt +AT91C_UDP_EPINT2 EQU (0x1 << 2) ;- (UDP) Endpoint 2 Interrupt +AT91C_UDP_EPINT3 EQU (0x1 << 3) ;- (UDP) Endpoint 3 Interrupt +AT91C_UDP_EPINT4 EQU (0x1 << 4) ;- (UDP) Endpoint 4 Interrupt +AT91C_UDP_EPINT5 EQU (0x1 << 5) ;- (UDP) Endpoint 5 Interrupt +AT91C_UDP_EPINT6 EQU (0x1 << 6) ;- (UDP) Endpoint 6 Interrupt +AT91C_UDP_EPINT7 EQU (0x1 << 7) ;- (UDP) Endpoint 7 Interrupt +AT91C_UDP_RXSUSP EQU (0x1 << 8) ;- (UDP) USB Suspend Interrupt +AT91C_UDP_RXRSM EQU (0x1 << 9) ;- (UDP) USB Resume Interrupt +AT91C_UDP_EXTRSM EQU (0x1 << 10) ;- (UDP) USB External Resume Interrupt +AT91C_UDP_SOFINT EQU (0x1 << 11) ;- (UDP) USB Start Of frame Interrupt +AT91C_UDP_WAKEUP EQU (0x1 << 13) ;- (UDP) USB Resume Interrupt +// - -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// - -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// - -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +AT91C_UDP_ENDBUSRES EQU (0x1 << 12) ;- (UDP) USB End Of Bus Reset Interrupt +// - -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// - -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +AT91C_UDP_EP0 EQU (0x1 << 0) ;- (UDP) Reset Endpoint 0 +AT91C_UDP_EP1 EQU (0x1 << 1) ;- (UDP) Reset Endpoint 1 +AT91C_UDP_EP2 EQU (0x1 << 2) ;- (UDP) Reset Endpoint 2 +AT91C_UDP_EP3 EQU (0x1 << 3) ;- (UDP) Reset Endpoint 3 +AT91C_UDP_EP4 EQU (0x1 << 4) ;- (UDP) Reset Endpoint 4 +AT91C_UDP_EP5 EQU (0x1 << 5) ;- (UDP) Reset Endpoint 5 +AT91C_UDP_EP6 EQU (0x1 << 6) ;- (UDP) Reset Endpoint 6 +AT91C_UDP_EP7 EQU (0x1 << 7) ;- (UDP) Reset Endpoint 7 +// - -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +AT91C_UDP_TXCOMP EQU (0x1 << 0) ;- (UDP) Generates an IN packet with data previously written in the DPR +AT91C_UDP_RX_DATA_BK0 EQU (0x1 << 1) ;- (UDP) Receive Data Bank 0 +AT91C_UDP_RXSETUP EQU (0x1 << 2) ;- (UDP) Sends STALL to the Host (Control endpoints) +AT91C_UDP_ISOERROR EQU (0x1 << 3) ;- (UDP) Isochronous error (Isochronous endpoints) +AT91C_UDP_TXPKTRDY EQU (0x1 << 4) ;- (UDP) Transmit Packet Ready +AT91C_UDP_FORCESTALL EQU (0x1 << 5) ;- (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +AT91C_UDP_RX_DATA_BK1 EQU (0x1 << 6) ;- (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +AT91C_UDP_DIR EQU (0x1 << 7) ;- (UDP) Transfer Direction +AT91C_UDP_EPTYPE EQU (0x7 << 8) ;- (UDP) Endpoint type +AT91C_UDP_EPTYPE_CTRL EQU (0x0 << 8) ;- (UDP) Control +AT91C_UDP_EPTYPE_ISO_OUT EQU (0x1 << 8) ;- (UDP) Isochronous OUT +AT91C_UDP_EPTYPE_BULK_OUT EQU (0x2 << 8) ;- (UDP) Bulk OUT +AT91C_UDP_EPTYPE_INT_OUT EQU (0x3 << 8) ;- (UDP) Interrupt OUT +AT91C_UDP_EPTYPE_ISO_IN EQU (0x5 << 8) ;- (UDP) Isochronous IN +AT91C_UDP_EPTYPE_BULK_IN EQU (0x6 << 8) ;- (UDP) Bulk IN +AT91C_UDP_EPTYPE_INT_IN EQU (0x7 << 8) ;- (UDP) Interrupt IN +AT91C_UDP_DTGLE EQU (0x1 << 11) ;- (UDP) Data Toggle +AT91C_UDP_EPEDS EQU (0x1 << 15) ;- (UDP) Endpoint Enable Disable +AT91C_UDP_RXBYTECNT EQU (0x7FF << 16) ;- (UDP) Number Of Bytes Available in the FIFO +// - -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- +AT91C_UDP_TXVDIS EQU (0x1 << 8) ;- (UDP) +AT91C_UDP_PUON EQU (0x1 << 9) ;- (UDP) Pull-up ON + +// - ***************************************************************************** +// - REGISTER ADDRESS DEFINITION FOR AT91SAM7S256 +// - ***************************************************************************** +// - ========== Register definition for SYS peripheral ========== +// - ========== Register definition for AIC peripheral ========== +AT91C_AIC_IVR EQU (0xFFFFF100) ;- (AIC) IRQ Vector Register +AT91C_AIC_SMR EQU (0xFFFFF000) ;- (AIC) Source Mode Register +AT91C_AIC_FVR EQU (0xFFFFF104) ;- (AIC) FIQ Vector Register +AT91C_AIC_DCR EQU (0xFFFFF138) ;- (AIC) Debug Control Register (Protect) +AT91C_AIC_EOICR EQU (0xFFFFF130) ;- (AIC) End of Interrupt Command Register +AT91C_AIC_SVR EQU (0xFFFFF080) ;- (AIC) Source Vector Register +AT91C_AIC_FFSR EQU (0xFFFFF148) ;- (AIC) Fast Forcing Status Register +AT91C_AIC_ICCR EQU (0xFFFFF128) ;- (AIC) Interrupt Clear Command Register +AT91C_AIC_ISR EQU (0xFFFFF108) ;- (AIC) Interrupt Status Register +AT91C_AIC_IMR EQU (0xFFFFF110) ;- (AIC) Interrupt Mask Register +AT91C_AIC_IPR EQU (0xFFFFF10C) ;- (AIC) Interrupt Pending Register +AT91C_AIC_FFER EQU (0xFFFFF140) ;- (AIC) Fast Forcing Enable Register +AT91C_AIC_IECR EQU (0xFFFFF120) ;- (AIC) Interrupt Enable Command Register +AT91C_AIC_ISCR EQU (0xFFFFF12C) ;- (AIC) Interrupt Set Command Register +AT91C_AIC_FFDR EQU (0xFFFFF144) ;- (AIC) Fast Forcing Disable Register +AT91C_AIC_CISR EQU (0xFFFFF114) ;- (AIC) Core Interrupt Status Register +AT91C_AIC_IDCR EQU (0xFFFFF124) ;- (AIC) Interrupt Disable Command Register +AT91C_AIC_SPU EQU (0xFFFFF134) ;- (AIC) Spurious Vector Register +// - ========== Register definition for PDC_DBGU peripheral ========== +AT91C_DBGU_TCR EQU (0xFFFFF30C) ;- (PDC_DBGU) Transmit Counter Register +AT91C_DBGU_RNPR EQU (0xFFFFF310) ;- (PDC_DBGU) Receive Next Pointer Register +AT91C_DBGU_TNPR EQU (0xFFFFF318) ;- (PDC_DBGU) Transmit Next Pointer Register +AT91C_DBGU_TPR EQU (0xFFFFF308) ;- (PDC_DBGU) Transmit Pointer Register +AT91C_DBGU_RPR EQU (0xFFFFF300) ;- (PDC_DBGU) Receive Pointer Register +AT91C_DBGU_RCR EQU (0xFFFFF304) ;- (PDC_DBGU) Receive Counter Register +AT91C_DBGU_RNCR EQU (0xFFFFF314) ;- (PDC_DBGU) Receive Next Counter Register +AT91C_DBGU_PTCR EQU (0xFFFFF320) ;- (PDC_DBGU) PDC Transfer Control Register +AT91C_DBGU_PTSR EQU (0xFFFFF324) ;- (PDC_DBGU) PDC Transfer Status Register +AT91C_DBGU_TNCR EQU (0xFFFFF31C) ;- (PDC_DBGU) Transmit Next Counter Register +// - ========== Register definition for DBGU peripheral ========== +AT91C_DBGU_EXID EQU (0xFFFFF244) ;- (DBGU) Chip ID Extension Register +AT91C_DBGU_BRGR EQU (0xFFFFF220) ;- (DBGU) Baud Rate Generator Register +AT91C_DBGU_IDR EQU (0xFFFFF20C) ;- (DBGU) Interrupt Disable Register +AT91C_DBGU_CSR EQU (0xFFFFF214) ;- (DBGU) Channel Status Register +AT91C_DBGU_CIDR EQU (0xFFFFF240) ;- (DBGU) Chip ID Register +AT91C_DBGU_MR EQU (0xFFFFF204) ;- (DBGU) Mode Register +AT91C_DBGU_IMR EQU (0xFFFFF210) ;- (DBGU) Interrupt Mask Register +AT91C_DBGU_CR EQU (0xFFFFF200) ;- (DBGU) Control Register +AT91C_DBGU_FNTR EQU (0xFFFFF248) ;- (DBGU) Force NTRST Register +AT91C_DBGU_THR EQU (0xFFFFF21C) ;- (DBGU) Transmitter Holding Register +AT91C_DBGU_RHR EQU (0xFFFFF218) ;- (DBGU) Receiver Holding Register +AT91C_DBGU_IER EQU (0xFFFFF208) ;- (DBGU) Interrupt Enable Register +// - ========== Register definition for PIOA peripheral ========== +AT91C_PIOA_ODR EQU (0xFFFFF414) ;- (PIOA) Output Disable Registerr +AT91C_PIOA_SODR EQU (0xFFFFF430) ;- (PIOA) Set Output Data Register +AT91C_PIOA_ISR EQU (0xFFFFF44C) ;- (PIOA) Interrupt Status Register +AT91C_PIOA_ABSR EQU (0xFFFFF478) ;- (PIOA) AB Select Status Register +AT91C_PIOA_IER EQU (0xFFFFF440) ;- (PIOA) Interrupt Enable Register +AT91C_PIOA_PPUDR EQU (0xFFFFF460) ;- (PIOA) Pull-up Disable Register +AT91C_PIOA_IMR EQU (0xFFFFF448) ;- (PIOA) Interrupt Mask Register +AT91C_PIOA_PER EQU (0xFFFFF400) ;- (PIOA) PIO Enable Register +AT91C_PIOA_IFDR EQU (0xFFFFF424) ;- (PIOA) Input Filter Disable Register +AT91C_PIOA_OWDR EQU (0xFFFFF4A4) ;- (PIOA) Output Write Disable Register +AT91C_PIOA_MDSR EQU (0xFFFFF458) ;- (PIOA) Multi-driver Status Register +AT91C_PIOA_IDR EQU (0xFFFFF444) ;- (PIOA) Interrupt Disable Register +AT91C_PIOA_ODSR EQU (0xFFFFF438) ;- (PIOA) Output Data Status Register +AT91C_PIOA_PPUSR EQU (0xFFFFF468) ;- (PIOA) Pull-up Status Register +AT91C_PIOA_OWSR EQU (0xFFFFF4A8) ;- (PIOA) Output Write Status Register +AT91C_PIOA_BSR EQU (0xFFFFF474) ;- (PIOA) Select B Register +AT91C_PIOA_OWER EQU (0xFFFFF4A0) ;- (PIOA) Output Write Enable Register +AT91C_PIOA_IFER EQU (0xFFFFF420) ;- (PIOA) Input Filter Enable Register +AT91C_PIOA_PDSR EQU (0xFFFFF43C) ;- (PIOA) Pin Data Status Register +AT91C_PIOA_PPUER EQU (0xFFFFF464) ;- (PIOA) Pull-up Enable Register +AT91C_PIOA_OSR EQU (0xFFFFF418) ;- (PIOA) Output Status Register +AT91C_PIOA_ASR EQU (0xFFFFF470) ;- (PIOA) Select A Register +AT91C_PIOA_MDDR EQU (0xFFFFF454) ;- (PIOA) Multi-driver Disable Register +AT91C_PIOA_CODR EQU (0xFFFFF434) ;- (PIOA) Clear Output Data Register +AT91C_PIOA_MDER EQU (0xFFFFF450) ;- (PIOA) Multi-driver Enable Register +AT91C_PIOA_PDR EQU (0xFFFFF404) ;- (PIOA) PIO Disable Register +AT91C_PIOA_IFSR EQU (0xFFFFF428) ;- (PIOA) Input Filter Status Register +AT91C_PIOA_OER EQU (0xFFFFF410) ;- (PIOA) Output Enable Register +AT91C_PIOA_PSR EQU (0xFFFFF408) ;- (PIOA) PIO Status Register +// - ========== Register definition for CKGR peripheral ========== +AT91C_CKGR_MOR EQU (0xFFFFFC20) ;- (CKGR) Main Oscillator Register +AT91C_CKGR_PLLR EQU (0xFFFFFC2C) ;- (CKGR) PLL Register +AT91C_CKGR_MCFR EQU (0xFFFFFC24) ;- (CKGR) Main Clock Frequency Register +// - ========== Register definition for PMC peripheral ========== +AT91C_PMC_IDR EQU (0xFFFFFC64) ;- (PMC) Interrupt Disable Register +AT91C_PMC_MOR EQU (0xFFFFFC20) ;- (PMC) Main Oscillator Register +AT91C_PMC_PLLR EQU (0xFFFFFC2C) ;- (PMC) PLL Register +AT91C_PMC_PCER EQU (0xFFFFFC10) ;- (PMC) Peripheral Clock Enable Register +AT91C_PMC_PCKR EQU (0xFFFFFC40) ;- (PMC) Programmable Clock Register +AT91C_PMC_MCKR EQU (0xFFFFFC30) ;- (PMC) Master Clock Register +AT91C_PMC_SCDR EQU (0xFFFFFC04) ;- (PMC) System Clock Disable Register +AT91C_PMC_PCDR EQU (0xFFFFFC14) ;- (PMC) Peripheral Clock Disable Register +AT91C_PMC_SCSR EQU (0xFFFFFC08) ;- (PMC) System Clock Status Register +AT91C_PMC_PCSR EQU (0xFFFFFC18) ;- (PMC) Peripheral Clock Status Register +AT91C_PMC_MCFR EQU (0xFFFFFC24) ;- (PMC) Main Clock Frequency Register +AT91C_PMC_SCER EQU (0xFFFFFC00) ;- (PMC) System Clock Enable Register +AT91C_PMC_IMR EQU (0xFFFFFC6C) ;- (PMC) Interrupt Mask Register +AT91C_PMC_IER EQU (0xFFFFFC60) ;- (PMC) Interrupt Enable Register +AT91C_PMC_SR EQU (0xFFFFFC68) ;- (PMC) Status Register +// - ========== Register definition for RSTC peripheral ========== +AT91C_RSTC_RCR EQU (0xFFFFFD00) ;- (RSTC) Reset Control Register +AT91C_RSTC_RMR EQU (0xFFFFFD08) ;- (RSTC) Reset Mode Register +AT91C_RSTC_RSR EQU (0xFFFFFD04) ;- (RSTC) Reset Status Register +// - ========== Register definition for RTTC peripheral ========== +AT91C_RTTC_RTSR EQU (0xFFFFFD2C) ;- (RTTC) Real-time Status Register +AT91C_RTTC_RTMR EQU (0xFFFFFD20) ;- (RTTC) Real-time Mode Register +AT91C_RTTC_RTVR EQU (0xFFFFFD28) ;- (RTTC) Real-time Value Register +AT91C_RTTC_RTAR EQU (0xFFFFFD24) ;- (RTTC) Real-time Alarm Register +// - ========== Register definition for PITC peripheral ========== +AT91C_PITC_PIVR EQU (0xFFFFFD38) ;- (PITC) Period Interval Value Register +AT91C_PITC_PISR EQU (0xFFFFFD34) ;- (PITC) Period Interval Status Register +AT91C_PITC_PIIR EQU (0xFFFFFD3C) ;- (PITC) Period Interval Image Register +AT91C_PITC_PIMR EQU (0xFFFFFD30) ;- (PITC) Period Interval Mode Register +// - ========== Register definition for WDTC peripheral ========== +AT91C_WDTC_WDCR EQU (0xFFFFFD40) ;- (WDTC) Watchdog Control Register +AT91C_WDTC_WDSR EQU (0xFFFFFD48) ;- (WDTC) Watchdog Status Register +AT91C_WDTC_WDMR EQU (0xFFFFFD44) ;- (WDTC) Watchdog Mode Register +// - ========== Register definition for VREG peripheral ========== +AT91C_VREG_MR EQU (0xFFFFFD60) ;- (VREG) Voltage Regulator Mode Register +// - ========== Register definition for MC peripheral ========== +AT91C_MC_ASR EQU (0xFFFFFF04) ;- (MC) MC Abort Status Register +AT91C_MC_RCR EQU (0xFFFFFF00) ;- (MC) MC Remap Control Register +AT91C_MC_FCR EQU (0xFFFFFF64) ;- (MC) MC Flash Command Register +AT91C_MC_AASR EQU (0xFFFFFF08) ;- (MC) MC Abort Address Status Register +AT91C_MC_FSR EQU (0xFFFFFF68) ;- (MC) MC Flash Status Register +AT91C_MC_FMR EQU (0xFFFFFF60) ;- (MC) MC Flash Mode Register +// - ========== Register definition for PDC_SPI peripheral ========== +AT91C_SPI_PTCR EQU (0xFFFE0120) ;- (PDC_SPI) PDC Transfer Control Register +AT91C_SPI_TPR EQU (0xFFFE0108) ;- (PDC_SPI) Transmit Pointer Register +AT91C_SPI_TCR EQU (0xFFFE010C) ;- (PDC_SPI) Transmit Counter Register +AT91C_SPI_RCR EQU (0xFFFE0104) ;- (PDC_SPI) Receive Counter Register +AT91C_SPI_PTSR EQU (0xFFFE0124) ;- (PDC_SPI) PDC Transfer Status Register +AT91C_SPI_RNPR EQU (0xFFFE0110) ;- (PDC_SPI) Receive Next Pointer Register +AT91C_SPI_RPR EQU (0xFFFE0100) ;- (PDC_SPI) Receive Pointer Register +AT91C_SPI_TNCR EQU (0xFFFE011C) ;- (PDC_SPI) Transmit Next Counter Register +AT91C_SPI_RNCR EQU (0xFFFE0114) ;- (PDC_SPI) Receive Next Counter Register +AT91C_SPI_TNPR EQU (0xFFFE0118) ;- (PDC_SPI) Transmit Next Pointer Register +// - ========== Register definition for SPI peripheral ========== +AT91C_SPI_IER EQU (0xFFFE0014) ;- (SPI) Interrupt Enable Register +AT91C_SPI_SR EQU (0xFFFE0010) ;- (SPI) Status Register +AT91C_SPI_IDR EQU (0xFFFE0018) ;- (SPI) Interrupt Disable Register +AT91C_SPI_CR EQU (0xFFFE0000) ;- (SPI) Control Register +AT91C_SPI_MR EQU (0xFFFE0004) ;- (SPI) Mode Register +AT91C_SPI_IMR EQU (0xFFFE001C) ;- (SPI) Interrupt Mask Register +AT91C_SPI_TDR EQU (0xFFFE000C) ;- (SPI) Transmit Data Register +AT91C_SPI_RDR EQU (0xFFFE0008) ;- (SPI) Receive Data Register +AT91C_SPI_CSR EQU (0xFFFE0030) ;- (SPI) Chip Select Register +// - ========== Register definition for PDC_ADC peripheral ========== +AT91C_ADC_PTSR EQU (0xFFFD8124) ;- (PDC_ADC) PDC Transfer Status Register +AT91C_ADC_PTCR EQU (0xFFFD8120) ;- (PDC_ADC) PDC Transfer Control Register +AT91C_ADC_TNPR EQU (0xFFFD8118) ;- (PDC_ADC) Transmit Next Pointer Register +AT91C_ADC_TNCR EQU (0xFFFD811C) ;- (PDC_ADC) Transmit Next Counter Register +AT91C_ADC_RNPR EQU (0xFFFD8110) ;- (PDC_ADC) Receive Next Pointer Register +AT91C_ADC_RNCR EQU (0xFFFD8114) ;- (PDC_ADC) Receive Next Counter Register +AT91C_ADC_RPR EQU (0xFFFD8100) ;- (PDC_ADC) Receive Pointer Register +AT91C_ADC_TCR EQU (0xFFFD810C) ;- (PDC_ADC) Transmit Counter Register +AT91C_ADC_TPR EQU (0xFFFD8108) ;- (PDC_ADC) Transmit Pointer Register +AT91C_ADC_RCR EQU (0xFFFD8104) ;- (PDC_ADC) Receive Counter Register +// - ========== Register definition for ADC peripheral ========== +AT91C_ADC_CDR2 EQU (0xFFFD8038) ;- (ADC) ADC Channel Data Register 2 +AT91C_ADC_CDR3 EQU (0xFFFD803C) ;- (ADC) ADC Channel Data Register 3 +AT91C_ADC_CDR0 EQU (0xFFFD8030) ;- (ADC) ADC Channel Data Register 0 +AT91C_ADC_CDR5 EQU (0xFFFD8044) ;- (ADC) ADC Channel Data Register 5 +AT91C_ADC_CHDR EQU (0xFFFD8014) ;- (ADC) ADC Channel Disable Register +AT91C_ADC_SR EQU (0xFFFD801C) ;- (ADC) ADC Status Register +AT91C_ADC_CDR4 EQU (0xFFFD8040) ;- (ADC) ADC Channel Data Register 4 +AT91C_ADC_CDR1 EQU (0xFFFD8034) ;- (ADC) ADC Channel Data Register 1 +AT91C_ADC_LCDR EQU (0xFFFD8020) ;- (ADC) ADC Last Converted Data Register +AT91C_ADC_IDR EQU (0xFFFD8028) ;- (ADC) ADC Interrupt Disable Register +AT91C_ADC_CR EQU (0xFFFD8000) ;- (ADC) ADC Control Register +AT91C_ADC_CDR7 EQU (0xFFFD804C) ;- (ADC) ADC Channel Data Register 7 +AT91C_ADC_CDR6 EQU (0xFFFD8048) ;- (ADC) ADC Channel Data Register 6 +AT91C_ADC_IER EQU (0xFFFD8024) ;- (ADC) ADC Interrupt Enable Register +AT91C_ADC_CHER EQU (0xFFFD8010) ;- (ADC) ADC Channel Enable Register +AT91C_ADC_CHSR EQU (0xFFFD8018) ;- (ADC) ADC Channel Status Register +AT91C_ADC_MR EQU (0xFFFD8004) ;- (ADC) ADC Mode Register +AT91C_ADC_IMR EQU (0xFFFD802C) ;- (ADC) ADC Interrupt Mask Register +// - ========== Register definition for PDC_SSC peripheral ========== +AT91C_SSC_TNCR EQU (0xFFFD411C) ;- (PDC_SSC) Transmit Next Counter Register +AT91C_SSC_RPR EQU (0xFFFD4100) ;- (PDC_SSC) Receive Pointer Register +AT91C_SSC_RNCR EQU (0xFFFD4114) ;- (PDC_SSC) Receive Next Counter Register +AT91C_SSC_TPR EQU (0xFFFD4108) ;- (PDC_SSC) Transmit Pointer Register +AT91C_SSC_PTCR EQU (0xFFFD4120) ;- (PDC_SSC) PDC Transfer Control Register +AT91C_SSC_TCR EQU (0xFFFD410C) ;- (PDC_SSC) Transmit Counter Register +AT91C_SSC_RCR EQU (0xFFFD4104) ;- (PDC_SSC) Receive Counter Register +AT91C_SSC_RNPR EQU (0xFFFD4110) ;- (PDC_SSC) Receive Next Pointer Register +AT91C_SSC_TNPR EQU (0xFFFD4118) ;- (PDC_SSC) Transmit Next Pointer Register +AT91C_SSC_PTSR EQU (0xFFFD4124) ;- (PDC_SSC) PDC Transfer Status Register +// - ========== Register definition for SSC peripheral ========== +AT91C_SSC_RHR EQU (0xFFFD4020) ;- (SSC) Receive Holding Register +AT91C_SSC_RSHR EQU (0xFFFD4030) ;- (SSC) Receive Sync Holding Register +AT91C_SSC_TFMR EQU (0xFFFD401C) ;- (SSC) Transmit Frame Mode Register +AT91C_SSC_IDR EQU (0xFFFD4048) ;- (SSC) Interrupt Disable Register +AT91C_SSC_THR EQU (0xFFFD4024) ;- (SSC) Transmit Holding Register +AT91C_SSC_RCMR EQU (0xFFFD4010) ;- (SSC) Receive Clock ModeRegister +AT91C_SSC_IER EQU (0xFFFD4044) ;- (SSC) Interrupt Enable Register +AT91C_SSC_TSHR EQU (0xFFFD4034) ;- (SSC) Transmit Sync Holding Register +AT91C_SSC_SR EQU (0xFFFD4040) ;- (SSC) Status Register +AT91C_SSC_CMR EQU (0xFFFD4004) ;- (SSC) Clock Mode Register +AT91C_SSC_TCMR EQU (0xFFFD4018) ;- (SSC) Transmit Clock Mode Register +AT91C_SSC_CR EQU (0xFFFD4000) ;- (SSC) Control Register +AT91C_SSC_IMR EQU (0xFFFD404C) ;- (SSC) Interrupt Mask Register +AT91C_SSC_RFMR EQU (0xFFFD4014) ;- (SSC) Receive Frame Mode Register +// - ========== Register definition for PDC_US1 peripheral ========== +AT91C_US1_RNCR EQU (0xFFFC4114) ;- (PDC_US1) Receive Next Counter Register +AT91C_US1_PTCR EQU (0xFFFC4120) ;- (PDC_US1) PDC Transfer Control Register +AT91C_US1_TCR EQU (0xFFFC410C) ;- (PDC_US1) Transmit Counter Register +AT91C_US1_PTSR EQU (0xFFFC4124) ;- (PDC_US1) PDC Transfer Status Register +AT91C_US1_TNPR EQU (0xFFFC4118) ;- (PDC_US1) Transmit Next Pointer Register +AT91C_US1_RCR EQU (0xFFFC4104) ;- (PDC_US1) Receive Counter Register +AT91C_US1_RNPR EQU (0xFFFC4110) ;- (PDC_US1) Receive Next Pointer Register +AT91C_US1_RPR EQU (0xFFFC4100) ;- (PDC_US1) Receive Pointer Register +AT91C_US1_TNCR EQU (0xFFFC411C) ;- (PDC_US1) Transmit Next Counter Register +AT91C_US1_TPR EQU (0xFFFC4108) ;- (PDC_US1) Transmit Pointer Register +// - ========== Register definition for US1 peripheral ========== +AT91C_US1_IF EQU (0xFFFC404C) ;- (US1) IRDA_FILTER Register +AT91C_US1_NER EQU (0xFFFC4044) ;- (US1) Nb Errors Register +AT91C_US1_RTOR EQU (0xFFFC4024) ;- (US1) Receiver Time-out Register +AT91C_US1_CSR EQU (0xFFFC4014) ;- (US1) Channel Status Register +AT91C_US1_IDR EQU (0xFFFC400C) ;- (US1) Interrupt Disable Register +AT91C_US1_IER EQU (0xFFFC4008) ;- (US1) Interrupt Enable Register +AT91C_US1_THR EQU (0xFFFC401C) ;- (US1) Transmitter Holding Register +AT91C_US1_TTGR EQU (0xFFFC4028) ;- (US1) Transmitter Time-guard Register +AT91C_US1_RHR EQU (0xFFFC4018) ;- (US1) Receiver Holding Register +AT91C_US1_BRGR EQU (0xFFFC4020) ;- (US1) Baud Rate Generator Register +AT91C_US1_IMR EQU (0xFFFC4010) ;- (US1) Interrupt Mask Register +AT91C_US1_FIDI EQU (0xFFFC4040) ;- (US1) FI_DI_Ratio Register +AT91C_US1_CR EQU (0xFFFC4000) ;- (US1) Control Register +AT91C_US1_MR EQU (0xFFFC4004) ;- (US1) Mode Register +// - ========== Register definition for PDC_US0 peripheral ========== +AT91C_US0_TNPR EQU (0xFFFC0118) ;- (PDC_US0) Transmit Next Pointer Register +AT91C_US0_RNPR EQU (0xFFFC0110) ;- (PDC_US0) Receive Next Pointer Register +AT91C_US0_TCR EQU (0xFFFC010C) ;- (PDC_US0) Transmit Counter Register +AT91C_US0_PTCR EQU (0xFFFC0120) ;- (PDC_US0) PDC Transfer Control Register +AT91C_US0_PTSR EQU (0xFFFC0124) ;- (PDC_US0) PDC Transfer Status Register +AT91C_US0_TNCR EQU (0xFFFC011C) ;- (PDC_US0) Transmit Next Counter Register +AT91C_US0_TPR EQU (0xFFFC0108) ;- (PDC_US0) Transmit Pointer Register +AT91C_US0_RCR EQU (0xFFFC0104) ;- (PDC_US0) Receive Counter Register +AT91C_US0_RPR EQU (0xFFFC0100) ;- (PDC_US0) Receive Pointer Register +AT91C_US0_RNCR EQU (0xFFFC0114) ;- (PDC_US0) Receive Next Counter Register +// - ========== Register definition for US0 peripheral ========== +AT91C_US0_BRGR EQU (0xFFFC0020) ;- (US0) Baud Rate Generator Register +AT91C_US0_NER EQU (0xFFFC0044) ;- (US0) Nb Errors Register +AT91C_US0_CR EQU (0xFFFC0000) ;- (US0) Control Register +AT91C_US0_IMR EQU (0xFFFC0010) ;- (US0) Interrupt Mask Register +AT91C_US0_FIDI EQU (0xFFFC0040) ;- (US0) FI_DI_Ratio Register +AT91C_US0_TTGR EQU (0xFFFC0028) ;- (US0) Transmitter Time-guard Register +AT91C_US0_MR EQU (0xFFFC0004) ;- (US0) Mode Register +AT91C_US0_RTOR EQU (0xFFFC0024) ;- (US0) Receiver Time-out Register +AT91C_US0_CSR EQU (0xFFFC0014) ;- (US0) Channel Status Register +AT91C_US0_RHR EQU (0xFFFC0018) ;- (US0) Receiver Holding Register +AT91C_US0_IDR EQU (0xFFFC000C) ;- (US0) Interrupt Disable Register +AT91C_US0_THR EQU (0xFFFC001C) ;- (US0) Transmitter Holding Register +AT91C_US0_IF EQU (0xFFFC004C) ;- (US0) IRDA_FILTER Register +AT91C_US0_IER EQU (0xFFFC0008) ;- (US0) Interrupt Enable Register +// - ========== Register definition for TWI peripheral ========== +AT91C_TWI_IER EQU (0xFFFB8024) ;- (TWI) Interrupt Enable Register +AT91C_TWI_CR EQU (0xFFFB8000) ;- (TWI) Control Register +AT91C_TWI_SR EQU (0xFFFB8020) ;- (TWI) Status Register +AT91C_TWI_IMR EQU (0xFFFB802C) ;- (TWI) Interrupt Mask Register +AT91C_TWI_THR EQU (0xFFFB8034) ;- (TWI) Transmit Holding Register +AT91C_TWI_IDR EQU (0xFFFB8028) ;- (TWI) Interrupt Disable Register +AT91C_TWI_IADR EQU (0xFFFB800C) ;- (TWI) Internal Address Register +AT91C_TWI_MMR EQU (0xFFFB8004) ;- (TWI) Master Mode Register +AT91C_TWI_CWGR EQU (0xFFFB8010) ;- (TWI) Clock Waveform Generator Register +AT91C_TWI_RHR EQU (0xFFFB8030) ;- (TWI) Receive Holding Register +// - ========== Register definition for TC0 peripheral ========== +AT91C_TC0_SR EQU (0xFFFA0020) ;- (TC0) Status Register +AT91C_TC0_RC EQU (0xFFFA001C) ;- (TC0) Register C +AT91C_TC0_RB EQU (0xFFFA0018) ;- (TC0) Register B +AT91C_TC0_CCR EQU (0xFFFA0000) ;- (TC0) Channel Control Register +AT91C_TC0_CMR EQU (0xFFFA0004) ;- (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +AT91C_TC0_IER EQU (0xFFFA0024) ;- (TC0) Interrupt Enable Register +AT91C_TC0_RA EQU (0xFFFA0014) ;- (TC0) Register A +AT91C_TC0_IDR EQU (0xFFFA0028) ;- (TC0) Interrupt Disable Register +AT91C_TC0_CV EQU (0xFFFA0010) ;- (TC0) Counter Value +AT91C_TC0_IMR EQU (0xFFFA002C) ;- (TC0) Interrupt Mask Register +// - ========== Register definition for TC1 peripheral ========== +AT91C_TC1_RB EQU (0xFFFA0058) ;- (TC1) Register B +AT91C_TC1_CCR EQU (0xFFFA0040) ;- (TC1) Channel Control Register +AT91C_TC1_IER EQU (0xFFFA0064) ;- (TC1) Interrupt Enable Register +AT91C_TC1_IDR EQU (0xFFFA0068) ;- (TC1) Interrupt Disable Register +AT91C_TC1_SR EQU (0xFFFA0060) ;- (TC1) Status Register +AT91C_TC1_CMR EQU (0xFFFA0044) ;- (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +AT91C_TC1_RA EQU (0xFFFA0054) ;- (TC1) Register A +AT91C_TC1_RC EQU (0xFFFA005C) ;- (TC1) Register C +AT91C_TC1_IMR EQU (0xFFFA006C) ;- (TC1) Interrupt Mask Register +AT91C_TC1_CV EQU (0xFFFA0050) ;- (TC1) Counter Value +// - ========== Register definition for TC2 peripheral ========== +AT91C_TC2_CMR EQU (0xFFFA0084) ;- (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +AT91C_TC2_CCR EQU (0xFFFA0080) ;- (TC2) Channel Control Register +AT91C_TC2_CV EQU (0xFFFA0090) ;- (TC2) Counter Value +AT91C_TC2_RA EQU (0xFFFA0094) ;- (TC2) Register A +AT91C_TC2_RB EQU (0xFFFA0098) ;- (TC2) Register B +AT91C_TC2_IDR EQU (0xFFFA00A8) ;- (TC2) Interrupt Disable Register +AT91C_TC2_IMR EQU (0xFFFA00AC) ;- (TC2) Interrupt Mask Register +AT91C_TC2_RC EQU (0xFFFA009C) ;- (TC2) Register C +AT91C_TC2_IER EQU (0xFFFA00A4) ;- (TC2) Interrupt Enable Register +AT91C_TC2_SR EQU (0xFFFA00A0) ;- (TC2) Status Register +// - ========== Register definition for TCB peripheral ========== +AT91C_TCB_BMR EQU (0xFFFA00C4) ;- (TCB) TC Block Mode Register +AT91C_TCB_BCR EQU (0xFFFA00C0) ;- (TCB) TC Block Control Register +// - ========== Register definition for PWMC_CH3 peripheral ========== +AT91C_PWMC_CH3_CUPDR EQU (0xFFFCC270) ;- (PWMC_CH3) Channel Update Register +AT91C_PWMC_CH3_Reserved EQU (0xFFFCC274) ;- (PWMC_CH3) Reserved +AT91C_PWMC_CH3_CPRDR EQU (0xFFFCC268) ;- (PWMC_CH3) Channel Period Register +AT91C_PWMC_CH3_CDTYR EQU (0xFFFCC264) ;- (PWMC_CH3) Channel Duty Cycle Register +AT91C_PWMC_CH3_CCNTR EQU (0xFFFCC26C) ;- (PWMC_CH3) Channel Counter Register +AT91C_PWMC_CH3_CMR EQU (0xFFFCC260) ;- (PWMC_CH3) Channel Mode Register +// - ========== Register definition for PWMC_CH2 peripheral ========== +AT91C_PWMC_CH2_Reserved EQU (0xFFFCC254) ;- (PWMC_CH2) Reserved +AT91C_PWMC_CH2_CMR EQU (0xFFFCC240) ;- (PWMC_CH2) Channel Mode Register +AT91C_PWMC_CH2_CCNTR EQU (0xFFFCC24C) ;- (PWMC_CH2) Channel Counter Register +AT91C_PWMC_CH2_CPRDR EQU (0xFFFCC248) ;- (PWMC_CH2) Channel Period Register +AT91C_PWMC_CH2_CUPDR EQU (0xFFFCC250) ;- (PWMC_CH2) Channel Update Register +AT91C_PWMC_CH2_CDTYR EQU (0xFFFCC244) ;- (PWMC_CH2) Channel Duty Cycle Register +// - ========== Register definition for PWMC_CH1 peripheral ========== +AT91C_PWMC_CH1_Reserved EQU (0xFFFCC234) ;- (PWMC_CH1) Reserved +AT91C_PWMC_CH1_CUPDR EQU (0xFFFCC230) ;- (PWMC_CH1) Channel Update Register +AT91C_PWMC_CH1_CPRDR EQU (0xFFFCC228) ;- (PWMC_CH1) Channel Period Register +AT91C_PWMC_CH1_CCNTR EQU (0xFFFCC22C) ;- (PWMC_CH1) Channel Counter Register +AT91C_PWMC_CH1_CDTYR EQU (0xFFFCC224) ;- (PWMC_CH1) Channel Duty Cycle Register +AT91C_PWMC_CH1_CMR EQU (0xFFFCC220) ;- (PWMC_CH1) Channel Mode Register +// - ========== Register definition for PWMC_CH0 peripheral ========== +AT91C_PWMC_CH0_Reserved EQU (0xFFFCC214) ;- (PWMC_CH0) Reserved +AT91C_PWMC_CH0_CPRDR EQU (0xFFFCC208) ;- (PWMC_CH0) Channel Period Register +AT91C_PWMC_CH0_CDTYR EQU (0xFFFCC204) ;- (PWMC_CH0) Channel Duty Cycle Register +AT91C_PWMC_CH0_CMR EQU (0xFFFCC200) ;- (PWMC_CH0) Channel Mode Register +AT91C_PWMC_CH0_CUPDR EQU (0xFFFCC210) ;- (PWMC_CH0) Channel Update Register +AT91C_PWMC_CH0_CCNTR EQU (0xFFFCC20C) ;- (PWMC_CH0) Channel Counter Register +// - ========== Register definition for PWMC peripheral ========== +AT91C_PWMC_IDR EQU (0xFFFCC014) ;- (PWMC) PWMC Interrupt Disable Register +AT91C_PWMC_DIS EQU (0xFFFCC008) ;- (PWMC) PWMC Disable Register +AT91C_PWMC_IER EQU (0xFFFCC010) ;- (PWMC) PWMC Interrupt Enable Register +AT91C_PWMC_VR EQU (0xFFFCC0FC) ;- (PWMC) PWMC Version Register +AT91C_PWMC_ISR EQU (0xFFFCC01C) ;- (PWMC) PWMC Interrupt Status Register +AT91C_PWMC_SR EQU (0xFFFCC00C) ;- (PWMC) PWMC Status Register +AT91C_PWMC_IMR EQU (0xFFFCC018) ;- (PWMC) PWMC Interrupt Mask Register +AT91C_PWMC_MR EQU (0xFFFCC000) ;- (PWMC) PWMC Mode Register +AT91C_PWMC_ENA EQU (0xFFFCC004) ;- (PWMC) PWMC Enable Register +// - ========== Register definition for UDP peripheral ========== +AT91C_UDP_IMR EQU (0xFFFB0018) ;- (UDP) Interrupt Mask Register +AT91C_UDP_FADDR EQU (0xFFFB0008) ;- (UDP) Function Address Register +AT91C_UDP_NUM EQU (0xFFFB0000) ;- (UDP) Frame Number Register +AT91C_UDP_FDR EQU (0xFFFB0050) ;- (UDP) Endpoint FIFO Data Register +AT91C_UDP_ISR EQU (0xFFFB001C) ;- (UDP) Interrupt Status Register +AT91C_UDP_CSR EQU (0xFFFB0030) ;- (UDP) Endpoint Control and Status Register +AT91C_UDP_IDR EQU (0xFFFB0014) ;- (UDP) Interrupt Disable Register +AT91C_UDP_ICR EQU (0xFFFB0020) ;- (UDP) Interrupt Clear Register +AT91C_UDP_RSTEP EQU (0xFFFB0028) ;- (UDP) Reset Endpoint Register +AT91C_UDP_TXVC EQU (0xFFFB0074) ;- (UDP) Transceiver Control Register +AT91C_UDP_GLBSTATE EQU (0xFFFB0004) ;- (UDP) Global State Register +AT91C_UDP_IER EQU (0xFFFB0010) ;- (UDP) Interrupt Enable Register + +// - ***************************************************************************** +// - PIO DEFINITIONS FOR AT91SAM7S256 +// - ***************************************************************************** +AT91C_PIO_PA0 EQU (1 << 0) ;- Pin Controlled by PA0 +AT91C_PA0_PWM0 EQU (AT91C_PIO_PA0) ;- PWM Channel 0 +AT91C_PA0_TIOA0 EQU (AT91C_PIO_PA0) ;- Timer Counter 0 Multipurpose Timer I/O Pin A +AT91C_PIO_PA1 EQU (1 << 1) ;- Pin Controlled by PA1 +AT91C_PA1_PWM1 EQU (AT91C_PIO_PA1) ;- PWM Channel 1 +AT91C_PA1_TIOB0 EQU (AT91C_PIO_PA1) ;- Timer Counter 0 Multipurpose Timer I/O Pin B +AT91C_PIO_PA10 EQU (1 << 10) ;- Pin Controlled by PA10 +AT91C_PA10_DTXD EQU (AT91C_PIO_PA10) ;- DBGU Debug Transmit Data +AT91C_PA10_NPCS2 EQU (AT91C_PIO_PA10) ;- SPI Peripheral Chip Select 2 +AT91C_PIO_PA11 EQU (1 << 11) ;- Pin Controlled by PA11 +AT91C_PA11_NPCS0 EQU (AT91C_PIO_PA11) ;- SPI Peripheral Chip Select 0 +AT91C_PA11_PWM0 EQU (AT91C_PIO_PA11) ;- PWM Channel 0 +AT91C_PIO_PA12 EQU (1 << 12) ;- Pin Controlled by PA12 +AT91C_PA12_MISO EQU (AT91C_PIO_PA12) ;- SPI Master In Slave +AT91C_PA12_PWM1 EQU (AT91C_PIO_PA12) ;- PWM Channel 1 +AT91C_PIO_PA13 EQU (1 << 13) ;- Pin Controlled by PA13 +AT91C_PA13_MOSI EQU (AT91C_PIO_PA13) ;- SPI Master Out Slave +AT91C_PA13_PWM2 EQU (AT91C_PIO_PA13) ;- PWM Channel 2 +AT91C_PIO_PA14 EQU (1 << 14) ;- Pin Controlled by PA14 +AT91C_PA14_SPCK EQU (AT91C_PIO_PA14) ;- SPI Serial Clock +AT91C_PA14_PWM3 EQU (AT91C_PIO_PA14) ;- PWM Channel 3 +AT91C_PIO_PA15 EQU (1 << 15) ;- Pin Controlled by PA15 +AT91C_PA15_TF EQU (AT91C_PIO_PA15) ;- SSC Transmit Frame Sync +AT91C_PA15_TIOA1 EQU (AT91C_PIO_PA15) ;- Timer Counter 1 Multipurpose Timer I/O Pin A +AT91C_PIO_PA16 EQU (1 << 16) ;- Pin Controlled by PA16 +AT91C_PA16_TK EQU (AT91C_PIO_PA16) ;- SSC Transmit Clock +AT91C_PA16_TIOB1 EQU (AT91C_PIO_PA16) ;- Timer Counter 1 Multipurpose Timer I/O Pin B +AT91C_PIO_PA17 EQU (1 << 17) ;- Pin Controlled by PA17 +AT91C_PA17_TD EQU (AT91C_PIO_PA17) ;- SSC Transmit data +AT91C_PA17_PCK1 EQU (AT91C_PIO_PA17) ;- PMC Programmable Clock Output 1 +AT91C_PIO_PA18 EQU (1 << 18) ;- Pin Controlled by PA18 +AT91C_PA18_RD EQU (AT91C_PIO_PA18) ;- SSC Receive Data +AT91C_PA18_PCK2 EQU (AT91C_PIO_PA18) ;- PMC Programmable Clock Output 2 +AT91C_PIO_PA19 EQU (1 << 19) ;- Pin Controlled by PA19 +AT91C_PA19_RK EQU (AT91C_PIO_PA19) ;- SSC Receive Clock +AT91C_PA19_FIQ EQU (AT91C_PIO_PA19) ;- AIC Fast Interrupt Input +AT91C_PIO_PA2 EQU (1 << 2) ;- Pin Controlled by PA2 +AT91C_PA2_PWM2 EQU (AT91C_PIO_PA2) ;- PWM Channel 2 +AT91C_PA2_SCK0 EQU (AT91C_PIO_PA2) ;- USART 0 Serial Clock +AT91C_PIO_PA20 EQU (1 << 20) ;- Pin Controlled by PA20 +AT91C_PA20_RF EQU (AT91C_PIO_PA20) ;- SSC Receive Frame Sync +AT91C_PA20_IRQ0 EQU (AT91C_PIO_PA20) ;- External Interrupt 0 +AT91C_PIO_PA21 EQU (1 << 21) ;- Pin Controlled by PA21 +AT91C_PA21_RXD1 EQU (AT91C_PIO_PA21) ;- USART 1 Receive Data +AT91C_PA21_PCK1 EQU (AT91C_PIO_PA21) ;- PMC Programmable Clock Output 1 +AT91C_PIO_PA22 EQU (1 << 22) ;- Pin Controlled by PA22 +AT91C_PA22_TXD1 EQU (AT91C_PIO_PA22) ;- USART 1 Transmit Data +AT91C_PA22_NPCS3 EQU (AT91C_PIO_PA22) ;- SPI Peripheral Chip Select 3 +AT91C_PIO_PA23 EQU (1 << 23) ;- Pin Controlled by PA23 +AT91C_PA23_SCK1 EQU (AT91C_PIO_PA23) ;- USART 1 Serial Clock +AT91C_PA23_PWM0 EQU (AT91C_PIO_PA23) ;- PWM Channel 0 +AT91C_PIO_PA24 EQU (1 << 24) ;- Pin Controlled by PA24 +AT91C_PA24_RTS1 EQU (AT91C_PIO_PA24) ;- USART 1 Ready To Send +AT91C_PA24_PWM1 EQU (AT91C_PIO_PA24) ;- PWM Channel 1 +AT91C_PIO_PA25 EQU (1 << 25) ;- Pin Controlled by PA25 +AT91C_PA25_CTS1 EQU (AT91C_PIO_PA25) ;- USART 1 Clear To Send +AT91C_PA25_PWM2 EQU (AT91C_PIO_PA25) ;- PWM Channel 2 +AT91C_PIO_PA26 EQU (1 << 26) ;- Pin Controlled by PA26 +AT91C_PA26_DCD1 EQU (AT91C_PIO_PA26) ;- USART 1 Data Carrier Detect +AT91C_PA26_TIOA2 EQU (AT91C_PIO_PA26) ;- Timer Counter 2 Multipurpose Timer I/O Pin A +AT91C_PIO_PA27 EQU (1 << 27) ;- Pin Controlled by PA27 +AT91C_PA27_DTR1 EQU (AT91C_PIO_PA27) ;- USART 1 Data Terminal ready +AT91C_PA27_TIOB2 EQU (AT91C_PIO_PA27) ;- Timer Counter 2 Multipurpose Timer I/O Pin B +AT91C_PIO_PA28 EQU (1 << 28) ;- Pin Controlled by PA28 +AT91C_PA28_DSR1 EQU (AT91C_PIO_PA28) ;- USART 1 Data Set ready +AT91C_PA28_TCLK1 EQU (AT91C_PIO_PA28) ;- Timer Counter 1 external clock input +AT91C_PIO_PA29 EQU (1 << 29) ;- Pin Controlled by PA29 +AT91C_PA29_RI1 EQU (AT91C_PIO_PA29) ;- USART 1 Ring Indicator +AT91C_PA29_TCLK2 EQU (AT91C_PIO_PA29) ;- Timer Counter 2 external clock input +AT91C_PIO_PA3 EQU (1 << 3) ;- Pin Controlled by PA3 +AT91C_PA3_TWD EQU (AT91C_PIO_PA3) ;- TWI Two-wire Serial Data +AT91C_PA3_NPCS3 EQU (AT91C_PIO_PA3) ;- SPI Peripheral Chip Select 3 +AT91C_PIO_PA30 EQU (1 << 30) ;- Pin Controlled by PA30 +AT91C_PA30_IRQ1 EQU (AT91C_PIO_PA30) ;- External Interrupt 1 +AT91C_PA30_NPCS2 EQU (AT91C_PIO_PA30) ;- SPI Peripheral Chip Select 2 +AT91C_PIO_PA31 EQU (1 << 31) ;- Pin Controlled by PA31 +AT91C_PA31_NPCS1 EQU (AT91C_PIO_PA31) ;- SPI Peripheral Chip Select 1 +AT91C_PA31_PCK2 EQU (AT91C_PIO_PA31) ;- PMC Programmable Clock Output 2 +AT91C_PIO_PA4 EQU (1 << 4) ;- Pin Controlled by PA4 +AT91C_PA4_TWCK EQU (AT91C_PIO_PA4) ;- TWI Two-wire Serial Clock +AT91C_PA4_TCLK0 EQU (AT91C_PIO_PA4) ;- Timer Counter 0 external clock input +AT91C_PIO_PA5 EQU (1 << 5) ;- Pin Controlled by PA5 +AT91C_PA5_RXD0 EQU (AT91C_PIO_PA5) ;- USART 0 Receive Data +AT91C_PA5_NPCS3 EQU (AT91C_PIO_PA5) ;- SPI Peripheral Chip Select 3 +AT91C_PIO_PA6 EQU (1 << 6) ;- Pin Controlled by PA6 +AT91C_PA6_TXD0 EQU (AT91C_PIO_PA6) ;- USART 0 Transmit Data +AT91C_PA6_PCK0 EQU (AT91C_PIO_PA6) ;- PMC Programmable Clock Output 0 +AT91C_PIO_PA7 EQU (1 << 7) ;- Pin Controlled by PA7 +AT91C_PA7_RTS0 EQU (AT91C_PIO_PA7) ;- USART 0 Ready To Send +AT91C_PA7_PWM3 EQU (AT91C_PIO_PA7) ;- PWM Channel 3 +AT91C_PIO_PA8 EQU (1 << 8) ;- Pin Controlled by PA8 +AT91C_PA8_CTS0 EQU (AT91C_PIO_PA8) ;- USART 0 Clear To Send +AT91C_PA8_ADTRG EQU (AT91C_PIO_PA8) ;- ADC External Trigger +AT91C_PIO_PA9 EQU (1 << 9) ;- Pin Controlled by PA9 +AT91C_PA9_DRXD EQU (AT91C_PIO_PA9) ;- DBGU Debug Receive Data +AT91C_PA9_NPCS1 EQU (AT91C_PIO_PA9) ;- SPI Peripheral Chip Select 1 + +// - ***************************************************************************** +// - PERIPHERAL ID DEFINITIONS FOR AT91SAM7S256 +// - ***************************************************************************** +AT91C_ID_FIQ EQU ( 0) ;- Advanced Interrupt Controller (FIQ) +AT91C_ID_SYS EQU ( 1) ;- System Peripheral +AT91C_ID_PIOA EQU ( 2) ;- Parallel IO Controller +AT91C_ID_3_Reserved EQU ( 3) ;- Reserved +AT91C_ID_ADC EQU ( 4) ;- Analog-to-Digital Converter +AT91C_ID_SPI EQU ( 5) ;- Serial Peripheral Interface +AT91C_ID_US0 EQU ( 6) ;- USART 0 +AT91C_ID_US1 EQU ( 7) ;- USART 1 +AT91C_ID_SSC EQU ( 8) ;- Serial Synchronous Controller +AT91C_ID_TWI EQU ( 9) ;- Two-Wire Interface +AT91C_ID_PWMC EQU (10) ;- PWM Controller +AT91C_ID_UDP EQU (11) ;- USB Device Port +AT91C_ID_TC0 EQU (12) ;- Timer Counter 0 +AT91C_ID_TC1 EQU (13) ;- Timer Counter 1 +AT91C_ID_TC2 EQU (14) ;- Timer Counter 2 +AT91C_ID_15_Reserved EQU (15) ;- Reserved +AT91C_ID_16_Reserved EQU (16) ;- Reserved +AT91C_ID_17_Reserved EQU (17) ;- Reserved +AT91C_ID_18_Reserved EQU (18) ;- Reserved +AT91C_ID_19_Reserved EQU (19) ;- Reserved +AT91C_ID_20_Reserved EQU (20) ;- Reserved +AT91C_ID_21_Reserved EQU (21) ;- Reserved +AT91C_ID_22_Reserved EQU (22) ;- Reserved +AT91C_ID_23_Reserved EQU (23) ;- Reserved +AT91C_ID_24_Reserved EQU (24) ;- Reserved +AT91C_ID_25_Reserved EQU (25) ;- Reserved +AT91C_ID_26_Reserved EQU (26) ;- Reserved +AT91C_ID_27_Reserved EQU (27) ;- Reserved +AT91C_ID_28_Reserved EQU (28) ;- Reserved +AT91C_ID_29_Reserved EQU (29) ;- Reserved +AT91C_ID_IRQ0 EQU (30) ;- Advanced Interrupt Controller (IRQ0) +AT91C_ID_IRQ1 EQU (31) ;- Advanced Interrupt Controller (IRQ1) + +// - ***************************************************************************** +// - BASE ADDRESS DEFINITIONS FOR AT91SAM7S256 +// - ***************************************************************************** +AT91C_BASE_SYS EQU (0xFFFFF000) ;- (SYS) Base Address +AT91C_BASE_AIC EQU (0xFFFFF000) ;- (AIC) Base Address +AT91C_BASE_PDC_DBGU EQU (0xFFFFF300) ;- (PDC_DBGU) Base Address +AT91C_BASE_DBGU EQU (0xFFFFF200) ;- (DBGU) Base Address +AT91C_BASE_PIOA EQU (0xFFFFF400) ;- (PIOA) Base Address +AT91C_BASE_CKGR EQU (0xFFFFFC20) ;- (CKGR) Base Address +AT91C_BASE_PMC EQU (0xFFFFFC00) ;- (PMC) Base Address +AT91C_BASE_RSTC EQU (0xFFFFFD00) ;- (RSTC) Base Address +AT91C_BASE_RTTC EQU (0xFFFFFD20) ;- (RTTC) Base Address +AT91C_BASE_PITC EQU (0xFFFFFD30) ;- (PITC) Base Address +AT91C_BASE_WDTC EQU (0xFFFFFD40) ;- (WDTC) Base Address +AT91C_BASE_VREG EQU (0xFFFFFD60) ;- (VREG) Base Address +AT91C_BASE_MC EQU (0xFFFFFF00) ;- (MC) Base Address +AT91C_BASE_PDC_SPI EQU (0xFFFE0100) ;- (PDC_SPI) Base Address +AT91C_BASE_SPI EQU (0xFFFE0000) ;- (SPI) Base Address +AT91C_BASE_PDC_ADC EQU (0xFFFD8100) ;- (PDC_ADC) Base Address +AT91C_BASE_ADC EQU (0xFFFD8000) ;- (ADC) Base Address +AT91C_BASE_PDC_SSC EQU (0xFFFD4100) ;- (PDC_SSC) Base Address +AT91C_BASE_SSC EQU (0xFFFD4000) ;- (SSC) Base Address +AT91C_BASE_PDC_US1 EQU (0xFFFC4100) ;- (PDC_US1) Base Address +AT91C_BASE_US1 EQU (0xFFFC4000) ;- (US1) Base Address +AT91C_BASE_PDC_US0 EQU (0xFFFC0100) ;- (PDC_US0) Base Address +AT91C_BASE_US0 EQU (0xFFFC0000) ;- (US0) Base Address +AT91C_BASE_TWI EQU (0xFFFB8000) ;- (TWI) Base Address +AT91C_BASE_TC0 EQU (0xFFFA0000) ;- (TC0) Base Address +AT91C_BASE_TC1 EQU (0xFFFA0040) ;- (TC1) Base Address +AT91C_BASE_TC2 EQU (0xFFFA0080) ;- (TC2) Base Address +AT91C_BASE_TCB EQU (0xFFFA0000) ;- (TCB) Base Address +AT91C_BASE_PWMC_CH3 EQU (0xFFFCC260) ;- (PWMC_CH3) Base Address +AT91C_BASE_PWMC_CH2 EQU (0xFFFCC240) ;- (PWMC_CH2) Base Address +AT91C_BASE_PWMC_CH1 EQU (0xFFFCC220) ;- (PWMC_CH1) Base Address +AT91C_BASE_PWMC_CH0 EQU (0xFFFCC200) ;- (PWMC_CH0) Base Address +AT91C_BASE_PWMC EQU (0xFFFCC000) ;- (PWMC) Base Address +AT91C_BASE_UDP EQU (0xFFFB0000) ;- (UDP) Base Address + +// - ***************************************************************************** +// - MEMORY MAPPING DEFINITIONS FOR AT91SAM7S256 +// - ***************************************************************************** +AT91C_ISRAM EQU (0x00200000) ;- Internal SRAM base address +AT91C_ISRAM_SIZE EQU (0x00010000) ;- Internal SRAM size in byte (64 Kbyte) +AT91C_IFLASH EQU (0x00100000) ;- Internal ROM base address +AT91C_IFLASH_SIZE EQU (0x00040000) ;- Internal ROM size in byte (256 Kbyte) +#endif /* __IAR_SYSTEMS_ASM__ */ + + +#endif /* AT91SAM7S256_H */ diff --git a/AT91SAM7S256/SAM7S256/Include/lib_AT91SAM7S256.h b/AT91SAM7S256/SAM7S256/Include/lib_AT91SAM7S256.h new file mode 100644 index 0000000..27ad27f --- /dev/null +++ b/AT91SAM7S256/SAM7S256/Include/lib_AT91SAM7S256.h @@ -0,0 +1,3664 @@ +//* ---------------------------------------------------------------------------- +//* ATMEL Microcontroller Software Support - ROUSSET - +//* ---------------------------------------------------------------------------- +//* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//* ---------------------------------------------------------------------------- +//* File Name : lib_AT91SAM7S256.h +//* Object : AT91SAM7S256 inlined functions +//* Generated : AT91 SW Application Group 03/08/2005 (15:46:14) +//* +//* CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// +//* CVS Reference : /lib_pmc_SAM7S.h/1.1/Tue Feb 1 08:32:10 2005// +//* CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005// +//* CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004// +//* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// +//* CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004// +//* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// +//* CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003// +//* CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004// +//* CVS Reference : /lib_aic.h/1.3/Fri Jul 12 08:46:12 2002// +//* CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004// +//* CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003// +//* CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004// +//* CVS Reference : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005// +//* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// +//* CVS Reference : /lib_MC_SAM7S.h/1.1/Thu Mar 25 15:19:14 2004// +//* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// +//* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// +//* CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002// +//* ---------------------------------------------------------------------------- + +#ifndef lib_AT91SAM7S256_H +#define lib_AT91SAM7S256_H + +/* ***************************************************************************** + SOFTWARE API FOR AIC + ***************************************************************************** */ +#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20] + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_ConfigureIt +//* \brief Interrupt Handler Initialization +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_ConfigureIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id, // \arg interrupt number to initialize + unsigned int priority, // \arg priority to give to the interrupt + unsigned int src_type, // \arg activation and sense of activation + void (*newHandler) (void) ) // \arg address of the interrupt handler +{ + unsigned int oldHandler; + unsigned int mask ; + + oldHandler = pAic->AIC_SVR[irq_id]; + + mask = 0x1 << irq_id ; + //* Disable the interrupt on the interrupt controller + pAic->AIC_IDCR = mask ; + //* Save the interrupt handler routine pointer and the interrupt priority + pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ; + //* Store the Source Mode Register + pAic->AIC_SMR[irq_id] = src_type | priority ; + //* Clear the interrupt on the interrupt controller + pAic->AIC_ICCR = mask ; + + return oldHandler; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_EnableIt +//* \brief Enable corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_EnableIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id ) // \arg interrupt number to initialize +{ + //* Enable the interrupt on the interrupt controller + pAic->AIC_IECR = 0x1 << irq_id ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_DisableIt +//* \brief Disable corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_DisableIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id ) // \arg interrupt number to initialize +{ + unsigned int mask = 0x1 << irq_id; + //* Disable the interrupt on the interrupt controller + pAic->AIC_IDCR = mask ; + //* Clear the interrupt on the Interrupt Controller ( if one is pending ) + pAic->AIC_ICCR = mask ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_ClearIt +//* \brief Clear corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_ClearIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg interrupt number to initialize +{ + //* Clear the interrupt on the Interrupt Controller ( if one is pending ) + pAic->AIC_ICCR = (0x1 << irq_id); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_AcknowledgeIt +//* \brief Acknowledge corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_AcknowledgeIt ( + AT91PS_AIC pAic) // \arg pointer to the AIC registers +{ + pAic->AIC_EOICR = pAic->AIC_EOICR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_SetExceptionVector +//* \brief Configure vector handler +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_SetExceptionVector ( + unsigned int *pVector, // \arg pointer to the AIC registers + void (*Handler) () ) // \arg Interrupt Handler +{ + unsigned int oldVector = *pVector; + + if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE) + *pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE; + else + *pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000; + + return oldVector; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_Trig +//* \brief Trig an IT +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_Trig ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg interrupt number +{ + pAic->AIC_ISCR = (0x1 << irq_id) ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_IsActive +//* \brief Test if an IT is active +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_IsActive ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg Interrupt Number +{ + return (pAic->AIC_ISR & (0x1 << irq_id)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_IsPending +//* \brief Test if an IT is pending +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_IsPending ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg Interrupt Number +{ + return (pAic->AIC_IPR & (0x1 << irq_id)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_Open +//* \brief Set exception vectors and AIC registers to default values +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_Open( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + void (*IrqHandler) (), // \arg Default IRQ vector exception + void (*FiqHandler) (), // \arg Default FIQ vector exception + void (*DefaultHandler) (), // \arg Default Handler set in ISR + void (*SpuriousHandler) (), // \arg Default Spurious Handler + unsigned int protectMode) // \arg Debug Control Register +{ + int i; + + // Disable all interrupts and set IVR to the default handler + for (i = 0; i < 32; ++i) { + AT91F_AIC_DisableIt(pAic, i); + AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE, DefaultHandler); + } + + // Set the IRQ exception vector + AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler); + // Set the Fast Interrupt exception vector + AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler); + + pAic->AIC_SPU = (unsigned int) SpuriousHandler; + pAic->AIC_DCR = protectMode; +} +/* ***************************************************************************** + SOFTWARE API FOR PDC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetNextRx +//* \brief Set the next receive transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetNextRx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be received + unsigned int bytes) // \arg number of bytes to be received +{ + pPDC->PDC_RNPR = (unsigned int) address; + pPDC->PDC_RNCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetNextTx +//* \brief Set the next transmit transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetNextTx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be transmitted + unsigned int bytes) // \arg number of bytes to be transmitted +{ + pPDC->PDC_TNPR = (unsigned int) address; + pPDC->PDC_TNCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetRx +//* \brief Set the receive transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetRx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be received + unsigned int bytes) // \arg number of bytes to be received +{ + pPDC->PDC_RPR = (unsigned int) address; + pPDC->PDC_RCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetTx +//* \brief Set the transmit transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetTx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be transmitted + unsigned int bytes) // \arg number of bytes to be transmitted +{ + pPDC->PDC_TPR = (unsigned int) address; + pPDC->PDC_TCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_EnableTx +//* \brief Enable transmit +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_EnableTx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_TXTEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_EnableRx +//* \brief Enable receive +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_EnableRx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_RXTEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_DisableTx +//* \brief Disable transmit +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_DisableTx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_TXTDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_DisableRx +//* \brief Disable receive +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_DisableRx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_RXTDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsTxEmpty +//* \brief Test if the current transfer descriptor has been sent +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_TCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsNextTxEmpty +//* \brief Test if the next transfer descriptor has been moved to the current td +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_TNCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsRxEmpty +//* \brief Test if the current transfer descriptor has been filled +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_RCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsNextRxEmpty +//* \brief Test if the next transfer descriptor has been moved to the current td +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_RNCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_Open +//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_Open ( + AT91PS_PDC pPDC) // \arg pointer to a PDC controller +{ + //* Disable the RX and TX PDC transfer requests + AT91F_PDC_DisableRx(pPDC); + AT91F_PDC_DisableTx(pPDC); + + //* Reset all Counter register Next buffer first + AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); + AT91F_PDC_SetTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetRx(pPDC, (char *) 0, 0); + + //* Enable the RX and TX PDC transfer requests + AT91F_PDC_EnableRx(pPDC); + AT91F_PDC_EnableTx(pPDC); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_Close +//* \brief Close PDC: disable TX and RX reset transfer descriptors +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_Close ( + AT91PS_PDC pPDC) // \arg pointer to a PDC controller +{ + //* Disable the RX and TX PDC transfer requests + AT91F_PDC_DisableRx(pPDC); + AT91F_PDC_DisableTx(pPDC); + + //* Reset all Counter register Next buffer first + AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); + AT91F_PDC_SetTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetRx(pPDC, (char *) 0, 0); + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SendFrame +//* \brief Close PDC: disable TX and RX reset transfer descriptors +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PDC_SendFrame( + AT91PS_PDC pPDC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + if (AT91F_PDC_IsTxEmpty(pPDC)) { + //* Buffer and next buffer can be initialized + AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer); + AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer); + return 2; + } + else if (AT91F_PDC_IsNextTxEmpty(pPDC)) { + //* Only one buffer can be initialized + AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer); + return 1; + } + else { + //* All buffer are in use... + return 0; + } +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_ReceiveFrame +//* \brief Close PDC: disable TX and RX reset transfer descriptors +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PDC_ReceiveFrame ( + AT91PS_PDC pPDC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + if (AT91F_PDC_IsRxEmpty(pPDC)) { + //* Buffer and next buffer can be initialized + AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer); + AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer); + return 2; + } + else if (AT91F_PDC_IsNextRxEmpty(pPDC)) { + //* Only one buffer can be initialized + AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer); + return 1; + } + else { + //* All buffer are in use... + return 0; + } +} +/* ***************************************************************************** + SOFTWARE API FOR DBGU + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_InterruptEnable +//* \brief Enable DBGU Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_InterruptEnable( + AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller + unsigned int flag) // \arg dbgu interrupt to be enabled +{ + pDbgu->DBGU_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_InterruptDisable +//* \brief Disable DBGU Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_InterruptDisable( + AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller + unsigned int flag) // \arg dbgu interrupt to be disabled +{ + pDbgu->DBGU_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_GetInterruptMaskStatus +//* \brief Return DBGU Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status + AT91PS_DBGU pDbgu) // \arg pointer to a DBGU controller +{ + return pDbgu->DBGU_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_IsInterruptMasked +//* \brief Test if DBGU Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_DBGU_IsInterruptMasked( + AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR PIO + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgPeriph +//* \brief Enable pins to be drived by peripheral +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgPeriph( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int periphAEnable, // \arg PERIPH A to enable + unsigned int periphBEnable) // \arg PERIPH B to enable + +{ + pPio->PIO_ASR = periphAEnable; + pPio->PIO_BSR = periphBEnable; + pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgOutput +//* \brief Enable PIO in output mode +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int pioEnable) // \arg PIO to be enabled +{ + pPio->PIO_PER = pioEnable; // Set in PIO mode + pPio->PIO_OER = pioEnable; // Configure in Output +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgInput +//* \brief Enable PIO in input mode +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgInput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int inputEnable) // \arg PIO to be enabled +{ + // Disable output + pPio->PIO_ODR = inputEnable; + pPio->PIO_PER = inputEnable; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgOpendrain +//* \brief Configure PIO in open drain +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgOpendrain( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int multiDrvEnable) // \arg pio to be configured in open drain +{ + // Configure the multi-drive option + pPio->PIO_MDDR = ~multiDrvEnable; + pPio->PIO_MDER = multiDrvEnable; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgPullup +//* \brief Enable pullup on PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgPullup( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int pullupEnable) // \arg enable pullup on PIO +{ + // Connect or not Pullup + pPio->PIO_PPUDR = ~pullupEnable; + pPio->PIO_PPUER = pullupEnable; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgDirectDrive +//* \brief Enable direct drive on PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgDirectDrive( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int directDrive) // \arg PIO to be configured with direct drive + +{ + // Configure the Direct Drive + pPio->PIO_OWDR = ~directDrive; + pPio->PIO_OWER = directDrive; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgInputFilter +//* \brief Enable input filter on input PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgInputFilter( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int inputFilter) // \arg PIO to be configured with input filter + +{ + // Configure the Direct Drive + pPio->PIO_IFDR = ~inputFilter; + pPio->PIO_IFER = inputFilter; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInput +//* \brief Return PIO input value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInput( // \return PIO input + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_PDSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInputSet +//* \brief Test if PIO is input flag is active +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInputSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInput(pPio) & flag); +} + + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_SetOutput +//* \brief Set to 1 output PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_SetOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg output to be set +{ + pPio->PIO_SODR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_ClearOutput +//* \brief Set to 0 output PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_ClearOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg output to be cleared +{ + pPio->PIO_CODR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_ForceOutput +//* \brief Force output when Direct drive option is enabled +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_ForceOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg output to be forced +{ + pPio->PIO_ODSR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_Enable +//* \brief Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_Enable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be enabled +{ + pPio->PIO_PER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_Disable +//* \brief Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_Disable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be disabled +{ + pPio->PIO_PDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetStatus +//* \brief Return PIO Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_PSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsSet +//* \brief Test if PIO is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputEnable +//* \brief Output Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output to be enabled +{ + pPio->PIO_OER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputDisable +//* \brief Output Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output to be disabled +{ + pPio->PIO_ODR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetOutputStatus +//* \brief Return PIO Output Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_OSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsOuputSet +//* \brief Test if PIO Output is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsOutputSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetOutputStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InputFilterEnable +//* \brief Input Filter Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InputFilterEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio input filter to be enabled +{ + pPio->PIO_IFER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InputFilterDisable +//* \brief Input Filter Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InputFilterDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio input filter to be disabled +{ + pPio->PIO_IFDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInputFilterStatus +//* \brief Return PIO Input Filter Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_IFSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInputFilterSet +//* \brief Test if PIO Input filter is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInputFilterSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInputFilterStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetOutputDataStatus +//* \brief Return PIO Output Data Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_ODSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InterruptEnable +//* \brief Enable PIO Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InterruptEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio interrupt to be enabled +{ + pPio->PIO_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InterruptDisable +//* \brief Disable PIO Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InterruptDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio interrupt to be disabled +{ + pPio->PIO_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInterruptMaskStatus +//* \brief Return PIO Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInterruptStatus +//* \brief Return PIO Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_ISR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInterruptMasked +//* \brief Test if PIO Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInterruptMasked( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInterruptSet +//* \brief Test if PIO Interrupt is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInterruptSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInterruptStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_MultiDriverEnable +//* \brief Multi Driver Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_MultiDriverEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be enabled +{ + pPio->PIO_MDER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_MultiDriverDisable +//* \brief Multi Driver Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_MultiDriverDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be disabled +{ + pPio->PIO_MDDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetMultiDriverStatus +//* \brief Return PIO Multi Driver Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_MDSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsMultiDriverSet +//* \brief Test if PIO MultiDriver is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsMultiDriverSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_A_RegisterSelection +//* \brief PIO A Register Selection +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_A_RegisterSelection( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio A register selection +{ + pPio->PIO_ASR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_B_RegisterSelection +//* \brief PIO B Register Selection +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_B_RegisterSelection( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio B register selection +{ + pPio->PIO_BSR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_Get_AB_RegisterStatus +//* \brief Return PIO Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_ABSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsAB_RegisterSet +//* \brief Test if PIO AB Register is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsAB_RegisterSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputWriteEnable +//* \brief Output Write Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputWriteEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output write to be enabled +{ + pPio->PIO_OWER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputWriteDisable +//* \brief Output Write Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputWriteDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output write to be disabled +{ + pPio->PIO_OWDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetOutputWriteStatus +//* \brief Return PIO Output Write Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_OWSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsOutputWriteSet +//* \brief Test if PIO OutputWrite is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsOutputWriteSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetCfgPullup +//* \brief Return PIO Configuration Pullup +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_PPUSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsOutputDataStatusSet +//* \brief Test if PIO Output Data Status is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsOutputDataStatusSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetOutputDataStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsCfgPullupStatusSet +//* \brief Test if PIO Configuration Pullup Status is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsCfgPullupStatusSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (~AT91F_PIO_GetCfgPullup(pPio) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR PMC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgSysClkEnableReg +//* \brief Configure the System Clock Enable Register of the PMC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgSysClkEnableReg ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int mode) +{ + //* Write to the SCER register + pPMC->PMC_SCER = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgSysClkDisableReg +//* \brief Configure the System Clock Disable Register of the PMC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgSysClkDisableReg ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int mode) +{ + //* Write to the SCDR register + pPMC->PMC_SCDR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetSysClkStatusReg +//* \brief Return the System Clock Status Register of the PMC controller +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetSysClkStatusReg ( + AT91PS_PMC pPMC // pointer to a CAN controller + ) +{ + return pPMC->PMC_SCSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_EnablePeriphClock +//* \brief Enable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_EnablePeriphClock ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int periphIds) // \arg IDs of peripherals to enable +{ + pPMC->PMC_PCER = periphIds; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_DisablePeriphClock +//* \brief Disable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_DisablePeriphClock ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int periphIds) // \arg IDs of peripherals to enable +{ + pPMC->PMC_PCDR = periphIds; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetPeriphClock +//* \brief Get peripheral clock status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetPeriphClock ( + AT91PS_PMC pPMC) // \arg pointer to PMC controller +{ + return pPMC->PMC_PCSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_CfgMainOscillatorReg +//* \brief Cfg the main oscillator +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_CfgMainOscillatorReg ( + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int mode) +{ + pCKGR->CKGR_MOR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_GetMainOscillatorReg +//* \brief Cfg the main oscillator +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CKGR_GetMainOscillatorReg ( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + return pCKGR->CKGR_MOR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_EnableMainOscillator +//* \brief Enable the main oscillator +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_EnableMainOscillator( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_DisableMainOscillator +//* \brief Disable the main oscillator +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_DisableMainOscillator ( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_CfgMainOscStartUpTime +//* \brief Cfg MOR Register according to the main osc startup time +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_CfgMainOscStartUpTime ( + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int startup_time, // \arg main osc startup time in microsecond (us) + unsigned int slowClock) // \arg slowClock in Hz +{ + pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT; + pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_GetMainClockFreqReg +//* \brief Cfg the main oscillator +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CKGR_GetMainClockFreqReg ( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + return pCKGR->CKGR_MCFR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_GetMainClock +//* \brief Return Main clock in Hz +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CKGR_GetMainClock ( + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int slowClock) // \arg slowClock in Hz +{ + return ((pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF) * slowClock) >> 4; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgMCKReg +//* \brief Cfg Master Clock Register +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgMCKReg ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int mode) +{ + pPMC->PMC_MCKR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetMCKReg +//* \brief Return Master Clock Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetMCKReg( + AT91PS_PMC pPMC) // \arg pointer to PMC controller +{ + return pPMC->PMC_MCKR; +} + +//*------------------------------------------------------------------------------ +//* \fn AT91F_PMC_GetMasterClock +//* \brief Return master clock in Hz which correponds to processor clock for ARM7 +//*------------------------------------------------------------------------------ +__inline unsigned int AT91F_PMC_GetMasterClock ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int slowClock) // \arg slowClock in Hz +{ + unsigned int reg = pPMC->PMC_MCKR; + unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2)); + unsigned int pllDivider, pllMultiplier; + + switch (reg & AT91C_PMC_CSS) { + case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected + return slowClock / prescaler; + case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected + return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler; + case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected + reg = pCKGR->CKGR_PLLR; + pllDivider = (reg & AT91C_CKGR_DIV); + pllMultiplier = ((reg & AT91C_CKGR_MUL) >> 16) + 1; + return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler; + } + return 0; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_EnablePCK +//* \brief Enable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_EnablePCK ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int pck, // \arg Peripheral clock identifier 0 .. 7 + unsigned int mode) +{ + pPMC->PMC_PCKR[pck] = mode; + pPMC->PMC_SCER = (1 << pck) << 8; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_DisablePCK +//* \brief Enable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_DisablePCK ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int pck) // \arg Peripheral clock identifier 0 .. 7 +{ + pPMC->PMC_SCDR = (1 << pck) << 8; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_EnableIt +//* \brief Enable PMC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_EnableIt ( + AT91PS_PMC pPMC, // pointer to a PMC controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pPMC->PMC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_DisableIt +//* \brief Disable PMC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_DisableIt ( + AT91PS_PMC pPMC, // pointer to a PMC controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pPMC->PMC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetStatus +//* \brief Return PMC Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status + AT91PS_PMC pPMC) // pointer to a PMC controller +{ + return pPMC->PMC_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetInterruptMaskStatus +//* \brief Return PMC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status + AT91PS_PMC pPMC) // pointer to a PMC controller +{ + return pPMC->PMC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_IsInterruptMasked +//* \brief Test if PMC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_IsInterruptMasked( + AT91PS_PMC pPMC, // \arg pointer to a PMC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_IsStatusSet +//* \brief Test if PMC Status is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_IsStatusSet( + AT91PS_PMC pPMC, // \arg pointer to a PMC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PMC_GetStatus(pPMC) & flag); +}/* ***************************************************************************** + SOFTWARE API FOR RSTC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTSoftReset +//* \brief Start Software Reset +//*---------------------------------------------------------------------------- +__inline void AT91F_RSTSoftReset( + AT91PS_RSTC pRSTC, + unsigned int reset) +{ + pRSTC->RSTC_RCR = (0xA5000000 | reset); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTSetMode +//* \brief Set Reset Mode +//*---------------------------------------------------------------------------- +__inline void AT91F_RSTSetMode( + AT91PS_RSTC pRSTC, + unsigned int mode) +{ + pRSTC->RSTC_RMR = (0xA5000000 | mode); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTGetMode +//* \brief Get Reset Mode +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_RSTGetMode( + AT91PS_RSTC pRSTC) +{ + return (pRSTC->RSTC_RMR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTGetStatus +//* \brief Get Reset Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_RSTGetStatus( + AT91PS_RSTC pRSTC) +{ + return (pRSTC->RSTC_RSR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTIsSoftRstActive +//* \brief Return !=0 if software reset is still not completed +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_RSTIsSoftRstActive( + AT91PS_RSTC pRSTC) +{ + return ((pRSTC->RSTC_RSR) & AT91C_RSTC_SRCMP); +} +/* ***************************************************************************** + SOFTWARE API FOR RTTC + ***************************************************************************** */ +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_SetRTT_TimeBase() +//* \brief Set the RTT prescaler according to the TimeBase in ms +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTSetTimeBase( + AT91PS_RTTC pRTTC, + unsigned int ms) +{ + if (ms > 2000) + return 1; // AT91C_TIME_OUT_OF_RANGE + pRTTC->RTTC_RTMR &= ~0xFFFF; + pRTTC->RTTC_RTMR |= (((ms << 15) /1000) & 0xFFFF); + return 0; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTTSetPrescaler() +//* \brief Set the new prescaler value +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTSetPrescaler( + AT91PS_RTTC pRTTC, + unsigned int rtpres) +{ + pRTTC->RTTC_RTMR &= ~0xFFFF; + pRTTC->RTTC_RTMR |= (rtpres & 0xFFFF); + return (pRTTC->RTTC_RTMR); +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTTRestart() +//* \brief Restart the RTT prescaler +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTRestart( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST; +} + + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_SetAlarmINT() +//* \brief Enable RTT Alarm Interrupt +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTSetAlarmINT( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_ClearAlarmINT() +//* \brief Disable RTT Alarm Interrupt +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTClearAlarmINT( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_SetRttIncINT() +//* \brief Enable RTT INC Interrupt +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTSetRttIncINT( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_ClearRttIncINT() +//* \brief Disable RTT INC Interrupt +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTClearRttIncINT( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_SetAlarmValue() +//* \brief Set RTT Alarm Value +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTSetAlarmValue( + AT91PS_RTTC pRTTC, unsigned int alarm) +{ + pRTTC->RTTC_RTAR = alarm; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_GetAlarmValue() +//* \brief Get RTT Alarm Value +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTGetAlarmValue( + AT91PS_RTTC pRTTC) +{ + return(pRTTC->RTTC_RTAR); +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTTGetStatus() +//* \brief Read the RTT status +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTGetStatus( + AT91PS_RTTC pRTTC) +{ + return(pRTTC->RTTC_RTSR); +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_ReadValue() +//* \brief Read the RTT value +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTReadValue( + AT91PS_RTTC pRTTC) +{ + register volatile unsigned int val1,val2; + do + { + val1 = pRTTC->RTTC_RTVR; + val2 = pRTTC->RTTC_RTVR; + } + while(val1 != val2); + return(val1); +} +/* ***************************************************************************** + SOFTWARE API FOR PITC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITInit +//* \brief System timer init : period in µsecond, system clock freq in MHz +//*---------------------------------------------------------------------------- +__inline void AT91F_PITInit( + AT91PS_PITC pPITC, + unsigned int period, + unsigned int pit_frequency) +{ + pPITC->PITC_PIMR = period? (period * pit_frequency + 8) >> 4 : 0; // +8 to avoid %10 and /10 + pPITC->PITC_PIMR |= AT91C_PITC_PITEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITSetPIV +//* \brief Set the PIT Periodic Interval Value +//*---------------------------------------------------------------------------- +__inline void AT91F_PITSetPIV( + AT91PS_PITC pPITC, + unsigned int piv) +{ + pPITC->PITC_PIMR = piv | (pPITC->PITC_PIMR & (AT91C_PITC_PITEN | AT91C_PITC_PITIEN)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITEnableInt +//* \brief Enable PIT periodic interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PITEnableInt( + AT91PS_PITC pPITC) +{ + pPITC->PITC_PIMR |= AT91C_PITC_PITIEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITDisableInt +//* \brief Disable PIT periodic interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PITDisableInt( + AT91PS_PITC pPITC) +{ + pPITC->PITC_PIMR &= ~AT91C_PITC_PITIEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITGetMode +//* \brief Read PIT mode register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PITGetMode( + AT91PS_PITC pPITC) +{ + return(pPITC->PITC_PIMR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITGetStatus +//* \brief Read PIT status register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PITGetStatus( + AT91PS_PITC pPITC) +{ + return(pPITC->PITC_PISR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITGetPIIR +//* \brief Read PIT CPIV and PICNT without ressetting the counters +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PITGetPIIR( + AT91PS_PITC pPITC) +{ + return(pPITC->PITC_PIIR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITGetPIVR +//* \brief Read System timer CPIV and PICNT without ressetting the counters +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PITGetPIVR( + AT91PS_PITC pPITC) +{ + return(pPITC->PITC_PIVR); +} +/* ***************************************************************************** + SOFTWARE API FOR WDTC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTSetMode +//* \brief Set Watchdog Mode Register +//*---------------------------------------------------------------------------- +__inline void AT91F_WDTSetMode( + AT91PS_WDTC pWDTC, + unsigned int Mode) +{ + pWDTC->WDTC_WDMR = Mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTRestart +//* \brief Restart Watchdog +//*---------------------------------------------------------------------------- +__inline void AT91F_WDTRestart( + AT91PS_WDTC pWDTC) +{ + pWDTC->WDTC_WDCR = 0xA5000001; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTSGettatus +//* \brief Get Watchdog Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_WDTSGettatus( + AT91PS_WDTC pWDTC) +{ + return(pWDTC->WDTC_WDSR & 0x3); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTGetPeriod +//* \brief Translate ms into Watchdog Compatible value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_WDTGetPeriod(unsigned int ms) +{ + if ((ms < 4) || (ms > 16000)) + return 0; + return((ms << 8) / 1000); +} +/* ***************************************************************************** + SOFTWARE API FOR VREG + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_VREG_Enable_LowPowerMode +//* \brief Enable VREG Low Power Mode +//*---------------------------------------------------------------------------- +__inline void AT91F_VREG_Enable_LowPowerMode( + AT91PS_VREG pVREG) +{ + pVREG->VREG_MR |= AT91C_VREG_PSTDBY; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_VREG_Disable_LowPowerMode +//* \brief Disable VREG Low Power Mode +//*---------------------------------------------------------------------------- +__inline void AT91F_VREG_Disable_LowPowerMode( + AT91PS_VREG pVREG) +{ + pVREG->VREG_MR &= ~AT91C_VREG_PSTDBY; +}/* ***************************************************************************** + SOFTWARE API FOR MC + ***************************************************************************** */ + +#define AT91C_MC_CORRECT_KEY ((unsigned int) 0x5A << 24) // (MC) Correct Protect Key + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_Remap +//* \brief Make Remap +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_Remap (void) // +{ + AT91PS_MC pMC = (AT91PS_MC) AT91C_BASE_MC; + + pMC->MC_RCR = AT91C_MC_RCB; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_CfgModeReg +//* \brief Configure the EFC Mode Register of the MC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_EFC_CfgModeReg ( + AT91PS_MC pMC, // pointer to a MC controller + unsigned int mode) // mode register +{ + // Write to the FMR register + pMC->MC_FMR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_GetModeReg +//* \brief Return MC EFC Mode Regsiter +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_GetModeReg( + AT91PS_MC pMC) // pointer to a MC controller +{ + return pMC->MC_FMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_ComputeFMCN +//* \brief Return MC EFC Mode Regsiter +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_ComputeFMCN( + int master_clock) // master clock in Hz +{ + return (master_clock/1000000 +2); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_PerformCmd +//* \brief Perform EFC Command +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_EFC_PerformCmd ( + AT91PS_MC pMC, // pointer to a MC controller + unsigned int transfer_cmd) +{ + pMC->MC_FCR = transfer_cmd; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_GetStatus +//* \brief Return MC EFC Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_GetStatus( + AT91PS_MC pMC) // pointer to a MC controller +{ + return pMC->MC_FSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_IsInterruptMasked +//* \brief Test if EFC MC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_IsInterruptMasked( + AT91PS_MC pMC, // \arg pointer to a MC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_MC_EFC_GetModeReg(pMC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_IsInterruptSet +//* \brief Test if EFC MC Interrupt is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_IsInterruptSet( + AT91PS_MC pMC, // \arg pointer to a MC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_MC_EFC_GetStatus(pMC) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR SPI + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Open +//* \brief Open a SPI Port +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_Open ( + const unsigned int null) // \arg +{ + /* NOT DEFINED AT THIS MOMENT */ + return ( 0 ); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgCs +//* \brief Configure SPI chip select register +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_CfgCs ( + AT91PS_SPI pSPI, // pointer to a SPI controller + int cs, // SPI cs number (0 to 3) + int val) // chip select register +{ + //* Write to the CSR register + *(pSPI->SPI_CSR + cs) = val; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_EnableIt +//* \brief Enable SPI interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_EnableIt ( + AT91PS_SPI pSPI, // pointer to a SPI controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pSPI->SPI_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_DisableIt +//* \brief Disable SPI interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_DisableIt ( + AT91PS_SPI pSPI, // pointer to a SPI controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pSPI->SPI_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Reset +//* \brief Reset the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Reset ( + AT91PS_SPI pSPI // pointer to a SPI controller + ) +{ + //* Write to the CR register + pSPI->SPI_CR = AT91C_SPI_SWRST; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Enable +//* \brief Enable the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Enable ( + AT91PS_SPI pSPI // pointer to a SPI controller + ) +{ + //* Write to the CR register + pSPI->SPI_CR = AT91C_SPI_SPIEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Disable +//* \brief Disable the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Disable ( + AT91PS_SPI pSPI // pointer to a SPI controller + ) +{ + //* Write to the CR register + pSPI->SPI_CR = AT91C_SPI_SPIDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgMode +//* \brief Enable the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_CfgMode ( + AT91PS_SPI pSPI, // pointer to a SPI controller + int mode) // mode register +{ + //* Write to the MR register + pSPI->SPI_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgPCS +//* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_CfgPCS ( + AT91PS_SPI pSPI, // pointer to a SPI controller + char PCS_Device) // PCS of the Device +{ + //* Write to the MR register + pSPI->SPI_MR &= 0xFFF0FFFF; + pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS ); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_ReceiveFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_ReceiveFrame ( + AT91PS_SPI pSPI, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_ReceiveFrame( + (AT91PS_PDC) &(pSPI->SPI_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_SendFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_SendFrame( + AT91PS_SPI pSPI, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_SendFrame( + (AT91PS_PDC) &(pSPI->SPI_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Close +//* \brief Close SPI: disable IT disable transfert, close PDC +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Close ( + AT91PS_SPI pSPI) // \arg pointer to a SPI controller +{ + //* Reset all the Chip Select register + pSPI->SPI_CSR[0] = 0 ; + pSPI->SPI_CSR[1] = 0 ; + pSPI->SPI_CSR[2] = 0 ; + pSPI->SPI_CSR[3] = 0 ; + + //* Reset the SPI mode + pSPI->SPI_MR = 0 ; + + //* Disable all interrupts + pSPI->SPI_IDR = 0xFFFFFFFF ; + + //* Abort the Peripheral Data Transfers + AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR)); + + //* Disable receiver and transmitter and stop any activity immediately + pSPI->SPI_CR = AT91C_SPI_SPIDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_PutChar +//* \brief Send a character,does not check if ready to send +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_PutChar ( + AT91PS_SPI pSPI, + unsigned int character, + unsigned int cs_number ) +{ + unsigned int value_for_cs; + value_for_cs = (~(1 << cs_number)) & 0xF; //Place a zero among a 4 ONEs number + pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_GetChar +//* \brief Receive a character,does not check if a character is available +//*---------------------------------------------------------------------------- +__inline int AT91F_SPI_GetChar ( + const AT91PS_SPI pSPI) +{ + return((pSPI->SPI_RDR) & 0xFFFF); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_GetInterruptMaskStatus +//* \brief Return SPI Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status + AT91PS_SPI pSpi) // \arg pointer to a SPI controller +{ + return pSpi->SPI_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_IsInterruptMasked +//* \brief Test if SPI Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_SPI_IsInterruptMasked( + AT91PS_SPI pSpi, // \arg pointer to a SPI controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR ADC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_EnableIt +//* \brief Enable ADC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_EnableIt ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pADC->ADC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_DisableIt +//* \brief Disable ADC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_DisableIt ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pADC->ADC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetStatus +//* \brief Return ADC Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetStatus( // \return ADC Interrupt Status + AT91PS_ADC pADC) // pointer to a ADC controller +{ + return pADC->ADC_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetInterruptMaskStatus +//* \brief Return ADC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetInterruptMaskStatus( // \return ADC Interrupt Mask Status + AT91PS_ADC pADC) // pointer to a ADC controller +{ + return pADC->ADC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_IsInterruptMasked +//* \brief Test if ADC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_IsInterruptMasked( + AT91PS_ADC pADC, // \arg pointer to a ADC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_ADC_GetInterruptMaskStatus(pADC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_IsStatusSet +//* \brief Test if ADC Status is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_IsStatusSet( + AT91PS_ADC pADC, // \arg pointer to a ADC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_ADC_GetStatus(pADC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgModeReg +//* \brief Configure the Mode Register of the ADC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgModeReg ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int mode) // mode register +{ + //* Write to the MR register + pADC->ADC_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetModeReg +//* \brief Return the Mode Register of the ADC controller value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetModeReg ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_MR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgTimings +//* \brief Configure the different necessary timings of the ADC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgTimings ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int mck_clock, // in MHz + unsigned int adc_clock, // in MHz + unsigned int startup_time, // in us + unsigned int sample_and_hold_time) // in ns +{ + unsigned int prescal,startup,shtim; + + prescal = mck_clock/(2*adc_clock) - 1; + startup = adc_clock*startup_time/8 - 1; + shtim = adc_clock*sample_and_hold_time/1000 - 1; + + //* Write to the MR register + pADC->ADC_MR = ( (prescal<<8) & AT91C_ADC_PRESCAL) | ( (startup<<16) & AT91C_ADC_STARTUP) | ( (shtim<<24) & AT91C_ADC_SHTIM); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_EnableChannel +//* \brief Return ADC Timer Register Value +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_EnableChannel ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int channel) // mode register +{ + //* Write to the CHER register + pADC->ADC_CHER = channel; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_DisableChannel +//* \brief Return ADC Timer Register Value +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_DisableChannel ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int channel) // mode register +{ + //* Write to the CHDR register + pADC->ADC_CHDR = channel; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetChannelStatus +//* \brief Return ADC Timer Register Value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetChannelStatus ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CHSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_StartConversion +//* \brief Software request for a analog to digital conversion +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_StartConversion ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + pADC->ADC_CR = AT91C_ADC_START; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_SoftReset +//* \brief Software reset +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_SoftReset ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + pADC->ADC_CR = AT91C_ADC_SWRST; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetLastConvertedData +//* \brief Return the Last Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetLastConvertedData ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_LCDR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH0 +//* \brief Return the Channel 0 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH0 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR0; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH1 +//* \brief Return the Channel 1 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH1 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR1; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH2 +//* \brief Return the Channel 2 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH2 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR2; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH3 +//* \brief Return the Channel 3 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH3 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR3; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH4 +//* \brief Return the Channel 4 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH4 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR4; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH5 +//* \brief Return the Channel 5 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH5 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR5; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH6 +//* \brief Return the Channel 6 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH6 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR6; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH7 +//* \brief Return the Channel 7 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH7 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR7; +} + +/* ***************************************************************************** + SOFTWARE API FOR SSC + ***************************************************************************** */ +//* Define the standard I2S mode configuration + +//* Configuration to set in the SSC Transmit Clock Mode Register +//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits +//* nb_slot_by_frame : number of channels +#define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ + AT91C_SSC_CKS_DIV +\ + AT91C_SSC_CKO_CONTINOUS +\ + AT91C_SSC_CKG_NONE +\ + AT91C_SSC_START_FALL_RF +\ + AT91C_SSC_STTOUT +\ + ((1<<16) & AT91C_SSC_STTDLY) +\ + ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24)) + + +//* Configuration to set in the SSC Transmit Frame Mode Register +//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits +//* nb_slot_by_frame : number of channels +#define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ + (nb_bit_by_slot-1) +\ + AT91C_SSC_MSBF +\ + (((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB) +\ + (((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\ + AT91C_SSC_FSOS_NEGATIVE) + + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_SetBaudrate +//* \brief Set the baudrate according to the CPU clock +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_SetBaudrate ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int mainClock, // \arg peripheral clock + unsigned int speed) // \arg SSC baudrate +{ + unsigned int baud_value; + //* Define the baud rate divisor register + if (speed == 0) + baud_value = 0; + else + { + baud_value = (unsigned int) (mainClock * 10)/(2*speed); + if ((baud_value % 10) >= 5) + baud_value = (baud_value / 10) + 1; + else + baud_value /= 10; + } + + pSSC->SSC_CMR = baud_value; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_Configure +//* \brief Configure SSC +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_Configure ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int syst_clock, // \arg System Clock Frequency + unsigned int baud_rate, // \arg Expected Baud Rate Frequency + unsigned int clock_rx, // \arg Receiver Clock Parameters + unsigned int mode_rx, // \arg mode Register to be programmed + unsigned int clock_tx, // \arg Transmitter Clock Parameters + unsigned int mode_tx) // \arg mode Register to be programmed +{ + //* Disable interrupts + pSSC->SSC_IDR = (unsigned int) -1; + + //* Reset receiver and transmitter + pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ; + + //* Define the Clock Mode Register + AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate); + + //* Write the Receive Clock Mode Register + pSSC->SSC_RCMR = clock_rx; + + //* Write the Transmit Clock Mode Register + pSSC->SSC_TCMR = clock_tx; + + //* Write the Receive Frame Mode Register + pSSC->SSC_RFMR = mode_rx; + + //* Write the Transmit Frame Mode Register + pSSC->SSC_TFMR = mode_tx; + + //* Clear Transmit and Receive Counters + AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR)); + + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_EnableRx +//* \brief Enable receiving datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_EnableRx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Enable receiver + pSSC->SSC_CR = AT91C_SSC_RXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_DisableRx +//* \brief Disable receiving datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_DisableRx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Disable receiver + pSSC->SSC_CR = AT91C_SSC_RXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_EnableTx +//* \brief Enable sending datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_EnableTx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Enable transmitter + pSSC->SSC_CR = AT91C_SSC_TXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_DisableTx +//* \brief Disable sending datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_DisableTx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Disable transmitter + pSSC->SSC_CR = AT91C_SSC_TXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_EnableIt +//* \brief Enable SSC IT +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_EnableIt ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pSSC->SSC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_DisableIt +//* \brief Disable SSC IT +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_DisableIt ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IDR register + pSSC->SSC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_ReceiveFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SSC_ReceiveFrame ( + AT91PS_SSC pSSC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_ReceiveFrame( + (AT91PS_PDC) &(pSSC->SSC_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_SendFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SSC_SendFrame( + AT91PS_SSC pSSC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_SendFrame( + (AT91PS_PDC) &(pSSC->SSC_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_GetInterruptMaskStatus +//* \brief Return SSC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status + AT91PS_SSC pSsc) // \arg pointer to a SSC controller +{ + return pSsc->SSC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_IsInterruptMasked +//* \brief Test if SSC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_SSC_IsInterruptMasked( + AT91PS_SSC pSsc, // \arg pointer to a SSC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR USART + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Baudrate +//* \brief Calculate the baudrate +//* Standard Asynchronous Mode : 8 bits , 1 stop , no parity +#define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_CLOCK ) + +//* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity +#define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_EXT ) + +//* Standard Synchronous Mode : 8 bits , 1 stop , no parity +#define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \ + AT91C_US_USMODE_NORMAL + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_CLOCK ) + +//* SCK used Label +#define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT) + +//* Standard ISO T=0 Mode : 8 bits , 1 stop , parity +#define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \ + AT91C_US_CLKS_CLOCK +\ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_EVEN + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CKLO +\ + AT91C_US_OVER) + +//* Standard IRDA mode +#define AT91C_US_ASYNC_IRDA_MODE ( AT91C_US_USMODE_IRDA + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_CLOCK ) + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Baudrate +//* \brief Caluculate baud_value according to the main clock and the baud rate +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_Baudrate ( + const unsigned int main_clock, // \arg peripheral clock + const unsigned int baud_rate) // \arg UART baudrate +{ + unsigned int baud_value = ((main_clock*10)/(baud_rate * 16)); + if ((baud_value % 10) >= 5) + baud_value = (baud_value / 10) + 1; + else + baud_value /= 10; + return baud_value; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SetBaudrate +//* \brief Set the baudrate according to the CPU clock +//*---------------------------------------------------------------------------- +__inline void AT91F_US_SetBaudrate ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int mainClock, // \arg peripheral clock + unsigned int speed) // \arg UART baudrate +{ + //* Define the baud rate divisor register + pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SetTimeguard +//* \brief Set USART timeguard +//*---------------------------------------------------------------------------- +__inline void AT91F_US_SetTimeguard ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int timeguard) // \arg timeguard value +{ + //* Write the Timeguard Register + pUSART->US_TTGR = timeguard ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_EnableIt +//* \brief Enable USART IT +//*---------------------------------------------------------------------------- +__inline void AT91F_US_EnableIt ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pUSART->US_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_DisableIt +//* \brief Disable USART IT +//*---------------------------------------------------------------------------- +__inline void AT91F_US_DisableIt ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IER register + pUSART->US_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Configure +//* \brief Configure USART +//*---------------------------------------------------------------------------- +__inline void AT91F_US_Configure ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int mainClock, // \arg peripheral clock + unsigned int mode , // \arg mode Register to be programmed + unsigned int baudRate , // \arg baudrate to be programmed + unsigned int timeguard ) // \arg timeguard to be programmed +{ + //* Disable interrupts + pUSART->US_IDR = (unsigned int) -1; + + //* Reset receiver and transmitter + pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ; + + //* Define the baud rate divisor register + AT91F_US_SetBaudrate(pUSART, mainClock, baudRate); + + //* Write the Timeguard Register + AT91F_US_SetTimeguard(pUSART, timeguard); + + //* Clear Transmit and Receive Counters + AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR)); + + //* Define the USART mode + pUSART->US_MR = mode ; + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_EnableRx +//* \brief Enable receiving characters +//*---------------------------------------------------------------------------- +__inline void AT91F_US_EnableRx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Enable receiver + pUSART->US_CR = AT91C_US_RXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_EnableTx +//* \brief Enable sending characters +//*---------------------------------------------------------------------------- +__inline void AT91F_US_EnableTx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Enable transmitter + pUSART->US_CR = AT91C_US_TXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_ResetRx +//* \brief Reset Receiver and re-enable it +//*---------------------------------------------------------------------------- +__inline void AT91F_US_ResetRx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Reset receiver + pUSART->US_CR = AT91C_US_RSTRX; + //* Re-Enable receiver + pUSART->US_CR = AT91C_US_RXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_ResetTx +//* \brief Reset Transmitter and re-enable it +//*---------------------------------------------------------------------------- +__inline void AT91F_US_ResetTx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Reset transmitter + pUSART->US_CR = AT91C_US_RSTTX; + //* Enable transmitter + pUSART->US_CR = AT91C_US_TXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_DisableRx +//* \brief Disable Receiver +//*---------------------------------------------------------------------------- +__inline void AT91F_US_DisableRx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Disable receiver + pUSART->US_CR = AT91C_US_RXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_DisableTx +//* \brief Disable Transmitter +//*---------------------------------------------------------------------------- +__inline void AT91F_US_DisableTx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Disable transmitter + pUSART->US_CR = AT91C_US_TXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Close +//* \brief Close USART: disable IT disable receiver and transmitter, close PDC +//*---------------------------------------------------------------------------- +__inline void AT91F_US_Close ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Reset the baud rate divisor register + pUSART->US_BRGR = 0 ; + + //* Reset the USART mode + pUSART->US_MR = 0 ; + + //* Reset the Timeguard Register + pUSART->US_TTGR = 0; + + //* Disable all interrupts + pUSART->US_IDR = 0xFFFFFFFF ; + + //* Abort the Peripheral Data Transfers + AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR)); + + //* Disable receiver and transmitter and stop any activity immediately + pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_TxReady +//* \brief Return 1 if a character can be written in US_THR +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_TxReady ( + AT91PS_USART pUSART ) // \arg pointer to a USART controller +{ + return (pUSART->US_CSR & AT91C_US_TXRDY); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_RxReady +//* \brief Return 1 if a character can be read in US_RHR +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_RxReady ( + AT91PS_USART pUSART ) // \arg pointer to a USART controller +{ + return (pUSART->US_CSR & AT91C_US_RXRDY); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Error +//* \brief Return the error flag +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_Error ( + AT91PS_USART pUSART ) // \arg pointer to a USART controller +{ + return (pUSART->US_CSR & + (AT91C_US_OVRE | // Overrun error + AT91C_US_FRAME | // Framing error + AT91C_US_PARE)); // Parity error +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_PutChar +//* \brief Send a character,does not check if ready to send +//*---------------------------------------------------------------------------- +__inline void AT91F_US_PutChar ( + AT91PS_USART pUSART, + int character ) +{ + pUSART->US_THR = (character & 0x1FF); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_GetChar +//* \brief Receive a character,does not check if a character is available +//*---------------------------------------------------------------------------- +__inline int AT91F_US_GetChar ( + const AT91PS_USART pUSART) +{ + return((pUSART->US_RHR) & 0x1FF); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SendFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_SendFrame( + AT91PS_USART pUSART, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_SendFrame( + (AT91PS_PDC) &(pUSART->US_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_ReceiveFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_ReceiveFrame ( + AT91PS_USART pUSART, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_ReceiveFrame( + (AT91PS_PDC) &(pUSART->US_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SetIrdaFilter +//* \brief Set the value of IrDa filter tregister +//*---------------------------------------------------------------------------- +__inline void AT91F_US_SetIrdaFilter ( + AT91PS_USART pUSART, + unsigned char value +) +{ + pUSART->US_IF = value; +} + +/* ***************************************************************************** + SOFTWARE API FOR TWI + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_EnableIt +//* \brief Enable TWI IT +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_EnableIt ( + AT91PS_TWI pTWI, // \arg pointer to a TWI controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pTWI->TWI_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_DisableIt +//* \brief Disable TWI IT +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_DisableIt ( + AT91PS_TWI pTWI, // \arg pointer to a TWI controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IDR register + pTWI->TWI_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_Configure +//* \brief Configure TWI in master mode +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI ) // \arg pointer to a TWI controller +{ + //* Disable interrupts + pTWI->TWI_IDR = (unsigned int) -1; + + //* Reset peripheral + pTWI->TWI_CR = AT91C_TWI_SWRST; + + //* Set Master mode + pTWI->TWI_CR = AT91C_TWI_MSEN; + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_GetInterruptMaskStatus +//* \brief Return TWI Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status + AT91PS_TWI pTwi) // \arg pointer to a TWI controller +{ + return pTwi->TWI_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_IsInterruptMasked +//* \brief Test if TWI Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_TWI_IsInterruptMasked( + AT91PS_TWI pTwi, // \arg pointer to a TWI controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR TC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_InterruptEnable +//* \brief Enable TC Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_TC_InterruptEnable( + AT91PS_TC pTc, // \arg pointer to a TC controller + unsigned int flag) // \arg TC interrupt to be enabled +{ + pTc->TC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_InterruptDisable +//* \brief Disable TC Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_TC_InterruptDisable( + AT91PS_TC pTc, // \arg pointer to a TC controller + unsigned int flag) // \arg TC interrupt to be disabled +{ + pTc->TC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_GetInterruptMaskStatus +//* \brief Return TC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status + AT91PS_TC pTc) // \arg pointer to a TC controller +{ + return pTc->TC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_IsInterruptMasked +//* \brief Test if TC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_TC_IsInterruptMasked( + AT91PS_TC pTc, // \arg pointer to a TC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR PWMC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_GetStatus +//* \brief Return PWM Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_GetStatus( // \return PWM Interrupt Status + AT91PS_PWMC pPWM) // pointer to a PWM controller +{ + return pPWM->PWMC_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_InterruptEnable +//* \brief Enable PWM Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_InterruptEnable( + AT91PS_PWMC pPwm, // \arg pointer to a PWM controller + unsigned int flag) // \arg PWM interrupt to be enabled +{ + pPwm->PWMC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_InterruptDisable +//* \brief Disable PWM Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_InterruptDisable( + AT91PS_PWMC pPwm, // \arg pointer to a PWM controller + unsigned int flag) // \arg PWM interrupt to be disabled +{ + pPwm->PWMC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_GetInterruptMaskStatus +//* \brief Return PWM Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( // \return PWM Interrupt Mask Status + AT91PS_PWMC pPwm) // \arg pointer to a PWM controller +{ + return pPwm->PWMC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_IsInterruptMasked +//* \brief Test if PWM Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_IsInterruptMasked( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PWMC_GetInterruptMaskStatus(pPWM) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_IsStatusSet +//* \brief Test if PWM Interrupt is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_IsStatusSet( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PWMC_GetStatus(pPWM) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_CfgChannel +//* \brief Test if PWM Interrupt is Set +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CfgChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int channelId, // \arg PWM channel ID + unsigned int mode, // \arg PWM mode + unsigned int period, // \arg PWM period + unsigned int duty) // \arg PWM duty cycle +{ + pPWM->PWMC_CH[channelId].PWMC_CMR = mode; + pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty; + pPWM->PWMC_CH[channelId].PWMC_CPRDR = period; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_StartChannel +//* \brief Enable channel +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_StartChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg Channels IDs to be enabled +{ + pPWM->PWMC_ENA = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_StopChannel +//* \brief Disable channel +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_StopChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg Channels IDs to be enabled +{ + pPWM->PWMC_DIS = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_UpdateChannel +//* \brief Update Period or Duty Cycle +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_UpdateChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int channelId, // \arg PWM channel ID + unsigned int update) // \arg Channels IDs to be enabled +{ + pPWM->PWMC_CH[channelId].PWMC_CUPDR = update; +} + +/* ***************************************************************************** + SOFTWARE API FOR UDP + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EnableIt +//* \brief Enable UDP IT +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EnableIt ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pUDP->UDP_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_DisableIt +//* \brief Disable UDP IT +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_DisableIt ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IDR register + pUDP->UDP_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_SetAddress +//* \brief Set UDP functional address +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_SetAddress ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char address) // \arg new UDP address +{ + pUDP->UDP_FADDR = (AT91C_UDP_FEN | address); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EnableEp +//* \brief Enable Endpoint +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EnableEp ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + pUDP->UDP_CSR[endpoint] |= AT91C_UDP_EPEDS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_DisableEp +//* \brief Enable Endpoint +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_DisableEp ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + pUDP->UDP_CSR[endpoint] &= ~AT91C_UDP_EPEDS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_SetState +//* \brief Set UDP Device state +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_SetState ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg new UDP address +{ + pUDP->UDP_GLBSTATE &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG); + pUDP->UDP_GLBSTATE |= flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_GetState +//* \brief return UDP Device state +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state + AT91PS_UDP pUDP) // \arg pointer to a UDP controller +{ + return (pUDP->UDP_GLBSTATE & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_ResetEp +//* \brief Reset UDP endpoint +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_ResetEp ( // \return the UDP device state + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg Endpoints to be reset +{ + pUDP->UDP_RSTEP = flag; + pUDP->UDP_RSTEP = 0; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpStall +//* \brief Endpoint will STALL requests +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpStall( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpWrite +//* \brief Write value in the DPR +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpWrite( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint, // \arg endpoint number + unsigned char value) // \arg value to be written in the DPR +{ + pUDP->UDP_FDR[endpoint] = value; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpRead +//* \brief Return value from the DPR +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_EpRead( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + return pUDP->UDP_FDR[endpoint]; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpEndOfWr +//* \brief Notify the UDP that values in DPR are ready to be sent +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpEndOfWr( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpClear +//* \brief Clear flag in the endpoint CSR register +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpClear( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint, // \arg endpoint number + unsigned int flag) // \arg flag to be cleared +{ + pUDP->UDP_CSR[endpoint] &= ~(flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpSet +//* \brief Set flag in the endpoint CSR register +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpSet( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint, // \arg endpoint number + unsigned int flag) // \arg flag to be cleared +{ + pUDP->UDP_CSR[endpoint] |= flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpStatus +//* \brief Return the endpoint CSR register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_EpStatus( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + return pUDP->UDP_CSR[endpoint]; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_GetInterruptMaskStatus +//* \brief Return UDP Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_GetInterruptMaskStatus( // \return UDP Interrupt Mask Status + AT91PS_UDP pUdp) // \arg pointer to a UDP controller +{ + return pUdp->UDP_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_IsInterruptMasked +//* \brief Test if UDP Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_UDP_IsInterruptMasked( + AT91PS_UDP pUdp, // \arg pointer to a UDP controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_CfgPMC +//* \brief Enable Peripheral clock in PMC for DBGU +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_CfgPIO +//* \brief Configure PIO controllers to drive DBGU signals +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA9_DRXD ) | + ((unsigned int) AT91C_PA10_DTXD ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgPMC +//* \brief Enable Peripheral clock in PMC for PMC +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgPIO +//* \brief Configure PIO controllers to drive PMC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA6_PCK0 ) | + ((unsigned int) AT91C_PA18_PCK2 ) | + ((unsigned int) AT91C_PA31_PCK2 ) | + ((unsigned int) AT91C_PA21_PCK1 ) | + ((unsigned int) AT91C_PA17_PCK1 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_VREG_CfgPMC +//* \brief Enable Peripheral clock in PMC for VREG +//*---------------------------------------------------------------------------- +__inline void AT91F_VREG_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTC_CfgPMC +//* \brief Enable Peripheral clock in PMC for RSTC +//*---------------------------------------------------------------------------- +__inline void AT91F_RSTC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_CfgPMC +//* \brief Enable Peripheral clock in PMC for SSC +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SSC)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_CfgPIO +//* \brief Configure PIO controllers to drive SSC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA19_RK ) | + ((unsigned int) AT91C_PA16_TK ) | + ((unsigned int) AT91C_PA15_TF ) | + ((unsigned int) AT91C_PA18_RD ) | + ((unsigned int) AT91C_PA20_RF ) | + ((unsigned int) AT91C_PA17_TD ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTC_CfgPMC +//* \brief Enable Peripheral clock in PMC for WDTC +//*---------------------------------------------------------------------------- +__inline void AT91F_WDTC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US1_CfgPMC +//* \brief Enable Peripheral clock in PMC for US1 +//*---------------------------------------------------------------------------- +__inline void AT91F_US1_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_US1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US1_CfgPIO +//* \brief Configure PIO controllers to drive US1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_US1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA29_RI1 ) | + ((unsigned int) AT91C_PA26_DCD1 ) | + ((unsigned int) AT91C_PA28_DSR1 ) | + ((unsigned int) AT91C_PA27_DTR1 ) | + ((unsigned int) AT91C_PA23_SCK1 ) | + ((unsigned int) AT91C_PA24_RTS1 ) | + ((unsigned int) AT91C_PA22_TXD1 ) | + ((unsigned int) AT91C_PA21_RXD1 ) | + ((unsigned int) AT91C_PA25_CTS1 ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US0_CfgPMC +//* \brief Enable Peripheral clock in PMC for US0 +//*---------------------------------------------------------------------------- +__inline void AT91F_US0_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_US0)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US0_CfgPIO +//* \brief Configure PIO controllers to drive US0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_US0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA5_RXD0 ) | + ((unsigned int) AT91C_PA8_CTS0 ) | + ((unsigned int) AT91C_PA7_RTS0 ) | + ((unsigned int) AT91C_PA6_TXD0 ), // Peripheral A + ((unsigned int) AT91C_PA2_SCK0 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgPMC +//* \brief Enable Peripheral clock in PMC for SPI +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SPI)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgPIO +//* \brief Configure PIO controllers to drive SPI signals +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA13_MOSI ) | + ((unsigned int) AT91C_PA31_NPCS1 ) | + ((unsigned int) AT91C_PA14_SPCK ) | + ((unsigned int) AT91C_PA11_NPCS0 ) | + ((unsigned int) AT91C_PA12_MISO ), // Peripheral A + ((unsigned int) AT91C_PA9_NPCS1 ) | + ((unsigned int) AT91C_PA22_NPCS3 ) | + ((unsigned int) AT91C_PA3_NPCS3 ) | + ((unsigned int) AT91C_PA5_NPCS3 ) | + ((unsigned int) AT91C_PA10_NPCS2 ) | + ((unsigned int) AT91C_PA30_NPCS2 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITC_CfgPMC +//* \brief Enable Peripheral clock in PMC for PITC +//*---------------------------------------------------------------------------- +__inline void AT91F_PITC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_CfgPMC +//* \brief Enable Peripheral clock in PMC for AIC +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_FIQ) | + ((unsigned int) 1 << AT91C_ID_IRQ0) | + ((unsigned int) 1 << AT91C_ID_IRQ1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_CfgPIO +//* \brief Configure PIO controllers to drive AIC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA30_IRQ1 ), // Peripheral A + ((unsigned int) AT91C_PA20_IRQ0 ) | + ((unsigned int) AT91C_PA19_FIQ )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_CfgPMC +//* \brief Enable Peripheral clock in PMC for TWI +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TWI)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_CfgPIO +//* \brief Configure PIO controllers to drive TWI signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA4_TWCK ) | + ((unsigned int) AT91C_PA3_TWD ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH3_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH3 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH3_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA7_PWM3 ) | + ((unsigned int) AT91C_PA14_PWM3 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH2_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH2 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH2_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA2_PWM2 ), // Peripheral A + ((unsigned int) AT91C_PA13_PWM2 ) | + ((unsigned int) AT91C_PA25_PWM2 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH1_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA1_PWM1 ), // Peripheral A + ((unsigned int) AT91C_PA24_PWM1 ) | + ((unsigned int) AT91C_PA12_PWM1 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH0_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA0_PWM0 ), // Peripheral A + ((unsigned int) AT91C_PA23_PWM0 ) | + ((unsigned int) AT91C_PA11_PWM0 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgPMC +//* \brief Enable Peripheral clock in PMC for ADC +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_ADC)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgPIO +//* \brief Configure PIO controllers to drive ADC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA8_ADTRG )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RTTC_CfgPMC +//* \brief Enable Peripheral clock in PMC for RTTC +//*---------------------------------------------------------------------------- +__inline void AT91F_RTTC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_CfgPMC +//* \brief Enable Peripheral clock in PMC for UDP +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_UDP)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC0_CfgPMC +//* \brief Enable Peripheral clock in PMC for TC0 +//*---------------------------------------------------------------------------- +__inline void AT91F_TC0_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TC0)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC0_CfgPIO +//* \brief Configure PIO controllers to drive TC0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TC0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA0_TIOA0 ) | + ((unsigned int) AT91C_PA4_TCLK0 ) | + ((unsigned int) AT91C_PA1_TIOB0 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC1_CfgPMC +//* \brief Enable Peripheral clock in PMC for TC1 +//*---------------------------------------------------------------------------- +__inline void AT91F_TC1_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TC1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC1_CfgPIO +//* \brief Configure PIO controllers to drive TC1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TC1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA15_TIOA1 ) | + ((unsigned int) AT91C_PA28_TCLK1 ) | + ((unsigned int) AT91C_PA16_TIOB1 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC2_CfgPMC +//* \brief Enable Peripheral clock in PMC for TC2 +//*---------------------------------------------------------------------------- +__inline void AT91F_TC2_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TC2)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC2_CfgPIO +//* \brief Configure PIO controllers to drive TC2 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TC2_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA27_TIOB2 ) | + ((unsigned int) AT91C_PA26_TIOA2 ) | + ((unsigned int) AT91C_PA29_TCLK2 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_CfgPMC +//* \brief Enable Peripheral clock in PMC for MC +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIOA_CfgPMC +//* \brief Enable Peripheral clock in PMC for PIOA +//*---------------------------------------------------------------------------- +__inline void AT91F_PIOA_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_PIOA)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CfgPMC +//* \brief Enable Peripheral clock in PMC for PWMC +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_PWMC)); +} + +#endif // lib_AT91SAM7S256_H diff --git a/AT91SAM7S256/SAM7S256/Include/sam7s256.c b/AT91SAM7S256/SAM7S256/Include/sam7s256.c new file mode 100644 index 0000000..f3776f6 --- /dev/null +++ b/AT91SAM7S256/SAM7S256/Include/sam7s256.c @@ -0,0 +1,28 @@ +// +// Date init 14.12.2004 +// +// Revision date $Date:: 16-05-06 10:08 $ +// +// Filename $Workfile:: sam7s256.c $ +// +// Version $Revision:: 2 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Sam7s256/Include/ $ +// +// Platform C +// + +void main(void) +{ + while(TRUE) + { + HARDWAREInit; + mSchedInit(); + while(TRUE == mSchedCtrl()) + { + OSWatchdogWrite; + } + mSchedExit(); + HARDWAREExit; + } +} diff --git a/AT91SAM7S256/SAM7S256/Include/sam7s256.h b/AT91SAM7S256/SAM7S256/Include/sam7s256.h new file mode 100644 index 0000000..5a2d07d --- /dev/null +++ b/AT91SAM7S256/SAM7S256/Include/sam7s256.h @@ -0,0 +1,45 @@ +// +// Date init 14.12.2004 +// +// Revision date $Date:: 16-05-06 10:08 $ +// +// Filename $Workfile:: sam7s256.h $ +// +// Version $Revision:: 7 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Sam7s256/Include/ $ +// +// Platform C +// + +#ifndef SAM7S256_H +#define SAM7S256_H + +#include "ioat91sam7s256.h" + +#define SAM7S256 + +#define HARDWAREInit {\ + ULONG TmpReset;\ + *AT91C_RSTC_RMR = 0xA5000401;\ + *AT91C_AIC_DCR = 1;\ + *AT91C_PITC_PIMR = (0x000FFFFF | 0x01000000);\ + TmpReset = *AT91C_PITC_PIVR;\ + TmpReset = TmpReset;/* Suppress warning*/\ + *AT91C_PMC_PCER = (1L< + + + 1 + + Bin Output + + [ROOT_NODE] + + + XLINK + $PROJ_DIR$\Bin Output\List\LMS_ARM.map + $PROJ_DIR$\Bin Output\Exe\LMS_ARM.d79 + $PROJ_DIR$\Bin Output\Exe\LMS_ARM.a79 + $PROJ_DIR$\..\Object\LMS_ARM.d79 + + + + + $PROJ_DIR$\Bin Output\Exe\LMS_ARM.d79 + + + XLINK + $PROJ_DIR$\Bin Output\List\LMS_ARM.map + $PROJ_DIR$\Bin Output\Exe\LMS_ARM.a79 + + + + + XLINK + $PROJ_DIR$\at91SAM7S256_Remap.xcl + $PROJ_DIR$\Bin Output\Obj\Cstartup.r79 + $PROJ_DIR$\Bin Output\Obj\Cstartup_SAM7.r79 + $PROJ_DIR$\Bin Output\Obj\c_button.r79 + $PROJ_DIR$\Bin Output\Obj\c_cmd.r79 + $PROJ_DIR$\Bin Output\Obj\c_comm.r79 + $PROJ_DIR$\Bin Output\Obj\c_display.r79 + $PROJ_DIR$\Bin Output\Obj\c_input.r79 + $PROJ_DIR$\Bin Output\Obj\c_ioctrl.r79 + $PROJ_DIR$\Bin Output\Obj\c_led.r79 + $PROJ_DIR$\Bin Output\Obj\c_loader.r79 + $PROJ_DIR$\Bin Output\Obj\c_lowspeed.r79 + $PROJ_DIR$\Bin Output\Obj\c_output.r79 + $PROJ_DIR$\Bin Output\Obj\c_sound.r79 + $PROJ_DIR$\Bin Output\Obj\c_ui.r79 + $PROJ_DIR$\Bin Output\Obj\d_bt.r79 + $PROJ_DIR$\Bin Output\Obj\d_button.r79 + $PROJ_DIR$\Bin Output\Obj\d_display.r79 + $PROJ_DIR$\Bin Output\Obj\d_hispeed.r79 + $PROJ_DIR$\Bin Output\Obj\d_input.r79 + $PROJ_DIR$\Bin Output\Obj\d_ioctrl.r79 + $PROJ_DIR$\Bin Output\Obj\d_led.r79 + $PROJ_DIR$\Bin Output\Obj\d_loader.r79 + $PROJ_DIR$\Bin Output\Obj\d_lowspeed.r79 + $PROJ_DIR$\Bin Output\Obj\d_output.r79 + $PROJ_DIR$\Bin Output\Obj\d_sound.r79 + $PROJ_DIR$\Bin Output\Obj\d_timer.r79 + $PROJ_DIR$\Bin Output\Obj\d_usb.r79 + $PROJ_DIR$\Bin Output\Obj\m_sched.r79 + $TOOLKIT_DIR$\lib\dl4tptinl8n.r79 + + + + + $PROJ_DIR$\..\..\Source\c_led.c + + + ICCARM + $PROJ_DIR$\..\Object\c_led.r79 + + + + + ICCARM + $PROJ_DIR$\..\..\Source\stdconst.h + $PROJ_DIR$\..\..\Source\modules.h + $PROJ_DIR$\..\..\Source\c_led.iom + $PROJ_DIR$\..\..\Source\c_led.h + $PROJ_DIR$\..\..\Source\d_led.h + + + + + $PROJ_DIR$\..\..\Source\c_ui.c + + + ICCARM + $PROJ_DIR$\..\Object\c_ui.r79 + + + + + ICCARM + $TOOLKIT_DIR$\inc\stdio.h + $TOOLKIT_DIR$\inc\yvals.h + $TOOLKIT_DIR$\inc\DLib_Defaults.h + $TOOLKIT_DIR$\lib\dl4tptinl8n.h + $TOOLKIT_DIR$\inc\DLib_Product.h + $TOOLKIT_DIR$\inc\xencoding_limits.h + $TOOLKIT_DIR$\inc\ysizet.h + $TOOLKIT_DIR$\inc\string.h + $TOOLKIT_DIR$\inc\ctype.h + $TOOLKIT_DIR$\inc\xlocale.h + $TOOLKIT_DIR$\inc\xtls.h + $TOOLKIT_DIR$\inc\xmtx.h + $TOOLKIT_DIR$\inc\stdlib.h + $TOOLKIT_DIR$\inc\xlocaleuse.h + $TOOLKIT_DIR$\inc\xlocale_c.h + $TOOLKIT_DIR$\inc\xtinfo.h + $TOOLKIT_DIR$\inc\time.h + $TOOLKIT_DIR$\inc\wchar.h + $PROJ_DIR$\..\..\Source\stdconst.h + $PROJ_DIR$\..\..\Source\modules.h + $PROJ_DIR$\..\..\Source\c_ui.iom + $PROJ_DIR$\..\..\Source\c_ui.h + $PROJ_DIR$\..\..\Source\m_sched.h + $PROJ_DIR$\..\Include\sam7s256.h + $PROJ_DIR$\..\Include\ioat91sam7s256.h + $PROJ_DIR$\..\..\Source\c_loader.iom + $PROJ_DIR$\..\..\Source\c_display.iom + $PROJ_DIR$\..\..\Source\c_button.iom + $PROJ_DIR$\..\..\Source\c_sound.iom + $PROJ_DIR$\..\..\Source\c_input.iom + $PROJ_DIR$\..\..\Source\c_output.iom + $PROJ_DIR$\..\..\Source\c_ioctrl.iom + $PROJ_DIR$\..\..\Source\c_cmd.iom + $PROJ_DIR$\..\..\Source\c_comm.iom + $PROJ_DIR$\..\..\Source\Display.txt + $PROJ_DIR$\..\..\Source\LowBattery.txt + $PROJ_DIR$\..\..\Source\Startup.txt + $PROJ_DIR$\..\..\Source\Font.txt + $PROJ_DIR$\..\..\Source\Status.txt + $PROJ_DIR$\..\..\Source\Functions.inc + $PROJ_DIR$\..\..\Source\Test1.txt + $PROJ_DIR$\..\..\Source\Test2.txt + $PROJ_DIR$\..\..\Source\Running.txt + $PROJ_DIR$\..\..\Source\BtTest.inc + $PROJ_DIR$\..\..\Source\Mainmenu.rms + $PROJ_DIR$\..\..\Source\Submenu01.rms + $PROJ_DIR$\..\..\Source\Submenu02.rms + $PROJ_DIR$\..\..\Source\Submenu03.rms + $PROJ_DIR$\..\..\Source\Submenu04.rms + $PROJ_DIR$\..\..\Source\Submenu05.rms + $PROJ_DIR$\..\..\Source\Submenu06.rms + $PROJ_DIR$\..\..\Source\Submenu07.rms + $PROJ_DIR$\..\..\Source\Submenu10.rms + $PROJ_DIR$\..\..\Source\Submenu11.rms + + + + + $PROJ_DIR$\..\..\Source\c_display.c + + + ICCARM + $PROJ_DIR$\..\Object\c_display.r79 + + + + + ICCARM + $PROJ_DIR$\..\..\Source\stdconst.h + $PROJ_DIR$\..\..\Source\modules.h + $PROJ_DIR$\..\..\Source\c_display.iom + $PROJ_DIR$\..\..\Source\c_display.h + $PROJ_DIR$\..\..\Source\d_display.h + + + + + $PROJ_DIR$\..\..\Source\c_input.c + + + ICCARM + $PROJ_DIR$\..\Object\c_input.r79 + + + + + ICCARM + $PROJ_DIR$\..\..\Source\stdconst.h + $PROJ_DIR$\..\..\Source\modules.h + $PROJ_DIR$\..\..\Source\c_input.h + $PROJ_DIR$\..\..\Source\c_input.iom + $PROJ_DIR$\..\..\Source\d_input.h + $PROJ_DIR$\..\..\Source\c_output.iom + + + + + $PROJ_DIR$\..\..\Source\c_ioctrl.c + + + ICCARM + $PROJ_DIR$\..\Object\c_ioctrl.r79 + + + + + ICCARM + $PROJ_DIR$\..\..\Source\stdconst.h + $PROJ_DIR$\..\..\Source\modules.h + $PROJ_DIR$\..\..\Source\c_ioctrl.iom + $PROJ_DIR$\..\..\Source\c_ioctrl.h + $PROJ_DIR$\..\..\Source\d_ioctrl.h + + + + + $PROJ_DIR$\..\..\Source\c_loader.c + + + ICCARM + $PROJ_DIR$\..\Object\c_loader.r79 + + + + + ICCARM + $PROJ_DIR$\..\..\Source\stdconst.h + $PROJ_DIR$\..\..\Source\modules.h + $PROJ_DIR$\..\..\Source\c_loader.iom + $PROJ_DIR$\..\..\Source\c_ioctrl.iom + $PROJ_DIR$\..\..\Source\d_loader.h + $PROJ_DIR$\..\..\Source\c_loader.h + + + + + $PROJ_DIR$\..\..\Source\c_lowspeed.c + + + ICCARM + $PROJ_DIR$\..\Object\c_lowspeed.r79 + + + + + ICCARM + $PROJ_DIR$\..\..\Source\stdconst.h + $PROJ_DIR$\..\..\Source\modules.h + $PROJ_DIR$\..\..\Source\c_lowspeed.iom + $PROJ_DIR$\..\..\Source\c_lowspeed.h + $PROJ_DIR$\..\..\Source\d_lowspeed.h + + + + + $PROJ_DIR$\..\..\Source\c_output.c + + + ICCARM + $PROJ_DIR$\..\Object\c_output.r79 + + + + + ICCARM + $TOOLKIT_DIR$\inc\stdio.h + $TOOLKIT_DIR$\inc\yvals.h + $TOOLKIT_DIR$\inc\DLib_Defaults.h + $TOOLKIT_DIR$\lib\dl4tptinl8n.h + $TOOLKIT_DIR$\inc\DLib_Product.h + $TOOLKIT_DIR$\inc\xencoding_limits.h + $TOOLKIT_DIR$\inc\ysizet.h + $PROJ_DIR$\..\..\Source\stdconst.h + $PROJ_DIR$\..\..\Source\modules.h + $PROJ_DIR$\..\..\Source\c_output.iom + $PROJ_DIR$\..\..\Source\c_output.h + $PROJ_DIR$\..\..\Source\d_output.h + $PROJ_DIR$\..\..\Source\c_display.iom + + + + + $PROJ_DIR$\..\..\Source\c_sound.c + + + ICCARM + $PROJ_DIR$\..\Object\c_sound.r79 + + + + + ICCARM + $TOOLKIT_DIR$\inc\stdlib.h + $TOOLKIT_DIR$\inc\yvals.h + $TOOLKIT_DIR$\inc\DLib_Defaults.h + $TOOLKIT_DIR$\lib\dl4tptinl8n.h + $TOOLKIT_DIR$\inc\DLib_Product.h + $TOOLKIT_DIR$\inc\xencoding_limits.h + $TOOLKIT_DIR$\inc\ysizet.h + $TOOLKIT_DIR$\inc\string.h + $PROJ_DIR$\..\..\Source\stdconst.h + $PROJ_DIR$\..\..\Source\modules.h + $PROJ_DIR$\..\..\Source\c_sound.iom + $PROJ_DIR$\..\..\Source\c_loader.iom + $PROJ_DIR$\..\..\Source\c_sound.h + $PROJ_DIR$\..\..\Source\d_sound.h + + + + + $PROJ_DIR$\..\Include\Cstartup.s79 + + + AARM + $PROJ_DIR$\..\Object\Cstartup.r79 + + + + + AARM + $PROJ_DIR$\..\Include\AT91SAM7S256_inc.h + + + + + $PROJ_DIR$\..\Include\Cstartup_SAM7.c + + + ICCARM + $PROJ_DIR$\..\Object\Cstartup_SAM7.r79 + + + + + ICCARM + $PROJ_DIR$\..\Include\AT91SAM7S256.h + + + + + $PROJ_DIR$\..\..\Source\d_bt.c + + + ICCARM + $PROJ_DIR$\..\Object\d_bt.r79 + + + + + ICCARM + $PROJ_DIR$\..\..\Source\stdconst.h + $PROJ_DIR$\..\..\Source\m_sched.h + $PROJ_DIR$\..\Include\sam7s256.h + $PROJ_DIR$\..\Include\ioat91sam7s256.h + $PROJ_DIR$\..\..\Source\d_bt.h + $PROJ_DIR$\..\..\Source\d_bt.r + + + + + $PROJ_DIR$\..\..\Source\d_usb.c + + + ICCARM + $PROJ_DIR$\..\Object\d_usb.r79 + + + + + ICCARM + $PROJ_DIR$\..\..\Source\stdconst.h + $PROJ_DIR$\..\..\Source\m_sched.h + $PROJ_DIR$\..\Include\sam7s256.h + $PROJ_DIR$\..\Include\ioat91sam7s256.h + $PROJ_DIR$\..\..\Source\d_usb.h + $PROJ_DIR$\..\..\Source\d_usb.r + + + + + $PROJ_DIR$\..\..\Source\d_button.c + + + ICCARM + $PROJ_DIR$\..\Object\d_button.r79 + + + + + ICCARM + $PROJ_DIR$\..\..\Source\stdconst.h + $PROJ_DIR$\..\..\Source\m_sched.h + $PROJ_DIR$\..\Include\sam7s256.h + $PROJ_DIR$\..\Include\ioat91sam7s256.h + $PROJ_DIR$\..\..\Source\d_button.h + $PROJ_DIR$\..\..\Source\d_button.r + + + + + $PROJ_DIR$\..\..\Source\d_display.c + + + ICCARM + $PROJ_DIR$\..\Object\d_display.r79 + + + + + ICCARM + $PROJ_DIR$\..\..\Source\stdconst.h + $PROJ_DIR$\..\..\Source\m_sched.h + $PROJ_DIR$\..\Include\sam7s256.h + $PROJ_DIR$\..\Include\ioat91sam7s256.h + $PROJ_DIR$\..\..\Source\d_display.h + $PROJ_DIR$\..\..\Source\d_display.r + + + + + $PROJ_DIR$\..\..\Source\d_hispeed.c + + + ICCARM + $PROJ_DIR$\..\Object\d_hispeed.r79 + + + + + ICCARM + $PROJ_DIR$\..\..\Source\stdconst.h + $PROJ_DIR$\..\..\Source\m_sched.h + $PROJ_DIR$\..\Include\sam7s256.h + $PROJ_DIR$\..\Include\ioat91sam7s256.h + $PROJ_DIR$\..\..\Source\d_hispeed.h + $PROJ_DIR$\..\..\Source\d_hispeed.r + + + + + $PROJ_DIR$\..\..\Source\d_input.c + + + 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$PROJ_DIR$\..\..\Source\d_motor.r + + + + + $PROJ_DIR$\..\..\Source\d_sensor.c + + + ICCARM + $PROJ_DIR$\RAM_Debug\Obj\d_sensor.r79 + + + + + ICCARM + $PROJ_DIR$\..\..\Source\stdconst.h + $PROJ_DIR$\..\..\Source\m_sched.h + $PROJ_DIR$\..\Include\sam7s256.h + $PROJ_DIR$\..\Include\ioat91sam7s64.h + $PROJ_DIR$\..\..\Source\d_sensor.h + $PROJ_DIR$\..\..\Source\d_sensor.r + + + + + $PROJ_DIR$\RAM_Debug\Exe\LMS_ARM.d79 + + + XLINK + $PROJ_DIR$\RAM_Debug\List\LMS_ARM.map + + + + + XLINK + $PROJ_DIR$\at91SAM7S64_16KRAM.xcl + $PROJ_DIR$\RAM_Debug\Obj\Cstartup.r79 + $PROJ_DIR$\RAM_Debug\Obj\Cstartup_SAM7.r79 + $PROJ_DIR$\RAM_Debug\Obj\c_button.r79 + $PROJ_DIR$\RAM_Debug\Obj\c_cmd.r79 + $PROJ_DIR$\RAM_Debug\Obj\c_comm.r79 + $PROJ_DIR$\RAM_Debug\Obj\c_display.r79 + $PROJ_DIR$\RAM_Debug\Obj\c_ioctrl.r79 + $PROJ_DIR$\RAM_Debug\Obj\c_led.r79 + $PROJ_DIR$\RAM_Debug\Obj\c_loader.r79 + $PROJ_DIR$\RAM_Debug\Obj\c_lowspeed.r79 + $PROJ_DIR$\RAM_Debug\Obj\c_motor.r79 + $PROJ_DIR$\RAM_Debug\Obj\c_sensor.r79 + $PROJ_DIR$\RAM_Debug\Obj\c_sound.r79 + $PROJ_DIR$\RAM_Debug\Obj\d_bt.r79 + $PROJ_DIR$\RAM_Debug\Obj\d_button.r79 + $PROJ_DIR$\RAM_Debug\Obj\d_display.r79 + $PROJ_DIR$\RAM_Debug\Obj\d_hispeed.r79 + $PROJ_DIR$\RAM_Debug\Obj\d_ioctrl.r79 + $PROJ_DIR$\RAM_Debug\Obj\d_led.r79 + $PROJ_DIR$\RAM_Debug\Obj\d_lowspeed.r79 + $PROJ_DIR$\RAM_Debug\Obj\d_motor.r79 + $PROJ_DIR$\RAM_Debug\Obj\d_sensor.r79 + $PROJ_DIR$\RAM_Debug\Obj\d_sound.r79 + $PROJ_DIR$\RAM_Debug\Obj\d_timer.r79 + $PROJ_DIR$\RAM_Debug\Obj\d_usb.r79 + $PROJ_DIR$\RAM_Debug\Obj\m_sched.r79 + $TOOLKIT_DIR$\lib\dl4tptinl8n.r79 + + + + + $PROJ_DIR$\..\..\Source\c_comm.c + + + ICCARM + $PROJ_DIR$\RAM_Debug\Obj\c_comm.r79 + + + + + ICCARM + $PROJ_DIR$\..\..\Source\stdconst.h + $PROJ_DIR$\..\..\Source\modules.h + $PROJ_DIR$\..\..\Source\c_comm.iom + $PROJ_DIR$\..\..\Source\c_comm.h + $PROJ_DIR$\..\..\Source\d_usb.h + $PROJ_DIR$\..\..\Source\d_hispeed.h + $PROJ_DIR$\..\..\Source\d_bt.h + + + + + [MULTI_TOOL] + XLINK + + + + + diff --git a/AT91SAM7S256/SAM7S256/Tools/LMS_ARM.ewd b/AT91SAM7S256/SAM7S256/Tools/LMS_ARM.ewd new file mode 100644 index 0000000..edb35bb --- /dev/null +++ b/AT91SAM7S256/SAM7S256/Tools/LMS_ARM.ewd @@ -0,0 +1,1354 @@ + + + + 1 + + RAM_Debug + + ARM + + 1 + + C-SPY + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 0 + 1 + 1 + + + + + ANGEL_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + IARROM_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + JLINK_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + MACRAIGOR_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + RDI_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin + 1 + + + $EW_DIR$\common\plugins\Profiling\Profiling.ewplugin + 1 + + + $EW_DIR$\common\plugins\Trace\Trace.ewplugin + 1 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin + 0 + + + + + Flash Debug + + ARM + + 1 + + C-SPY + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 0 + 1 + 1 + + + + + ANGEL_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + IARROM_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + JLINK_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + MACRAIGOR_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + RDI_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin + 1 + + + $EW_DIR$\common\plugins\Profiling\Profiling.ewplugin + 1 + + + $EW_DIR$\common\plugins\Trace\Trace.ewplugin + 1 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin + 0 + + + + + Bin Output + + ARM + + 1 + + C-SPY + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 0 + 1 + 1 + + + + + ANGEL_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + IARROM_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + JLINK_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + MACRAIGOR_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + RDI_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin + 1 + + + $EW_DIR$\common\plugins\Profiling\Profiling.ewplugin + 1 + + + $EW_DIR$\common\plugins\Trace\Trace.ewplugin + 1 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin + 0 + + + + + + diff --git a/AT91SAM7S256/SAM7S256/Tools/LMS_ARM.ewp b/AT91SAM7S256/SAM7S256/Tools/LMS_ARM.ewp new file mode 100644 index 0000000..9106c9f --- /dev/null +++ b/AT91SAM7S256/SAM7S256/Tools/LMS_ARM.ewp @@ -0,0 +1,2538 @@ + + + + 1 + + RAM_Debug + + ARM + + 1 + + General + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 11 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 5 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + XLINK + 2 + + 17 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + XAR + 2 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Flash Debug + + ARM + + 1 + + General + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 11 + 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$PROJ_DIR$\..\..\Source\d_lowspeed.c + + + $PROJ_DIR$\..\..\Source\d_output.c + + + $PROJ_DIR$\..\..\Source\d_sound.c + + + $PROJ_DIR$\..\..\Source\d_timer.c + + + $PROJ_DIR$\..\..\Source\d_usb.c + + + $PROJ_DIR$\..\..\Source\Functions.inl + + + $PROJ_DIR$\..\..\Source\m_sched.c + + + + diff --git a/AT91SAM7S256/SAM7S256/Tools/LMS_ARM.eww b/AT91SAM7S256/SAM7S256/Tools/LMS_ARM.eww new file mode 100644 index 0000000..8c43a5a --- /dev/null +++ b/AT91SAM7S256/SAM7S256/Tools/LMS_ARM.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\LMS_ARM.ewp + + + + + diff --git a/AT91SAM7S256/SAM7S256/Tools/SAM7.mac b/AT91SAM7S256/SAM7S256/Tools/SAM7.mac new file mode 100644 index 0000000..1177dc2 --- /dev/null +++ b/AT91SAM7S256/SAM7S256/Tools/SAM7.mac @@ -0,0 +1,178 @@ +// --------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// --------------------------------------------------------- +// The software is delivered "AS IS" without warranty or +// condition of any kind, either express, implied or +// statutory. This includes without limitation any warranty +// or condition with respect to merchantability or fitness +// for any particular purpose, or against the infringements of +// intellectual property rights of others. +// --------------------------------------------------------- +// File: SAM7.mac +// +// 1.0 08/Mar/04 JPP : Creation +// 1.1 23/Mar/05 JPP : Change Variable name +// +// $Revision: 1.5 $ +// +// --------------------------------------------------------- + +__var __mac_i; +__var __mac_pt; + +execUserReset() +{ + CheckRemap(); + ini(); + AIC(); + __message "-------------------------------Set Reset ----------------------------------------"; + __writeMemory32(0x00000000,0xB4,"Register"); +} + + +//----------------------------------------------------------------------------- +// Watchdog +//------------------------------- +// Normally, the Watchdog is enable at the reset for load it's preferable to +// Disable. +//----------------------------------------------------------------------------- +Watchdog() +{ +//* Watchdog Disable +// AT91C_BASE_WDTC->WDTC_WDMR= AT91C_WDTC_WDDIS; + __writeMemory32(0x00008000,0xFFFFFD44,"Memory"); + __message "------------------------------- Watchdog Disable ----------------------------------------"; +} + + +//----------------------------------------------------------------------------- +// Check Remap +//------------- +//----------------------------------------------------------------------------- +CheckRemap() +{ +//* Read the value at 0x0 + __mac_i =__readMemory32(0x00000000,"Memory"); + __mac_i =__mac_i+1; + __writeMemory32(__mac_i,0x00,"Memory"); + __mac_pt =__readMemory32(0x00000000,"Memory"); + + if (__mac_i == __mac_pt) + { + __message "------------------------------- The Remap is done ----------------------------------------"; +//* Toggel RESET The remap + __writeMemory32(0x00000001,0xFFFFFF00,"Memory"); + + } else { + __message "------------------------------- The Remap is NOT -----------------------------------------"; + } + +} + + +execUserSetup() +{ + ini(); + __message "-------------------------------Set PC ----------------------------------------"; + __writeMemory32(0x00000000,0xB4,"Register"); +} + +//----------------------------------------------------------------------------- +// Reset the Interrupt Controller +//------------------------------- +// Normally, the code is executed only if a reset has been actually performed. +// So, the AIC initialization resumes at setting up the default vectors. +//----------------------------------------------------------------------------- +AIC() +{ +// Mask All interrupt pAic->AIC_IDCR = 0xFFFFFFFF; + __writeMemory32(0xffffffff,0xFFFFF124,"Memory"); + __writeMemory32(0xffffffff,0xFFFFF128,"Memory"); +// disable peripheral clock Peripheral Clock Disable Register + __writeMemory32(0xffffffff,0xFFFFFC14,"Memory"); + +// #define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register +// #define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register +// #define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register + __readMemory32(0xFFFA0020,"Memory"); + __readMemory32(0xFFFA0060,"Memory"); + __readMemory32(0xFFFA00A0,"Memory"); + for (__mac_i=0;__mac_i < 8; __mac_i++) + { + // AT91C_BASE_AIC->AIC_EOICR + __mac_pt = __readMemory32(0xFFFFF130,"Memory"); + + } + __message "------------------------------- AIC 2 INIT ---------------------------------------------"; +} + +ini() +{ +__writeMemory32(0x0,0x00,"Register"); +__writeMemory32(0x0,0x04,"Register"); +__writeMemory32(0x0,0x08,"Register"); +__writeMemory32(0x0,0x0C,"Register"); +__writeMemory32(0x0,0x10,"Register"); +__writeMemory32(0x0,0x14,"Register"); +__writeMemory32(0x0,0x18,"Register"); +__writeMemory32(0x0,0x1C,"Register"); +__writeMemory32(0x0,0x20,"Register"); +__writeMemory32(0x0,0x24,"Register"); +__writeMemory32(0x0,0x28,"Register"); +__writeMemory32(0x0,0x2C,"Register"); +__writeMemory32(0x0,0x30,"Register"); +__writeMemory32(0x0,0x34,"Register"); +__writeMemory32(0x0,0x38,"Register"); + +// Set CPSR +__writeMemory32(0x0D3,0x98,"Register"); + + +} + +RG() +{ + +__mac_i =__readMemory32(0x00,"Register"); __message "R00 0x",__mac_i:%X; +__mac_i =__readMemory32(0x04,"Register"); __message "R01 0x",__mac_i:%X; +__mac_i =__readMemory32(0x08,"Register"); __message "R02 0x",__mac_i:%X; +__mac_i =__readMemory32(0x0C,"Register"); __message "R03 0x",__mac_i:%X; +__mac_i =__readMemory32(0x10,"Register"); __message "R04 0x",__mac_i:%X; +__mac_i =__readMemory32(0x14,"Register"); __message "R05 0x",__mac_i:%X; +__mac_i =__readMemory32(0x18,"Register"); __message "R06 0x",__mac_i:%X; +__mac_i =__readMemory32(0x1C,"Register"); __message "R07 0x",__mac_i:%X; +__mac_i =__readMemory32(0x20,"Register"); __message "R08 0x",__mac_i:%X; +__mac_i =__readMemory32(0x24,"Register"); __message "R09 0x",__mac_i:%X; +__mac_i =__readMemory32(0x28,"Register"); __message "R10 0x",__mac_i:%X; +__mac_i =__readMemory32(0x2C,"Register"); __message "R11 0x",__mac_i:%X; +__mac_i =__readMemory32(0x30,"Register"); __message "R12 0x",__mac_i:%X; +__mac_i =__readMemory32(0x34,"Register"); __message "R13 0x",__mac_i:%X; +__mac_i =__readMemory32(0x38,"Register"); __message "R14 0x",__mac_i:%X; +__mac_i =__readMemory32(0x3C,"Register"); __message "R13 SVC 0x",__mac_i:%X; +__mac_i =__readMemory32(0x40,"Register"); __message "R14 SVC 0x",__mac_i:%X; +__mac_i =__readMemory32(0x44,"Register"); __message "R13 ABT 0x",__mac_i:%X; +__mac_i =__readMemory32(0x48,"Register"); __message "R14 ABT 0x",__mac_i:%X; +__mac_i =__readMemory32(0x4C,"Register"); __message "R13 UND 0x",__mac_i:%X; +__mac_i =__readMemory32(0x50,"Register"); __message "R14 UND 0x",__mac_i:%X; +__mac_i =__readMemory32(0x54,"Register"); __message "R13 IRQ 0x",__mac_i:%X; +__mac_i =__readMemory32(0x58,"Register"); __message "R14 IRQ 0x",__mac_i:%X; +__mac_i =__readMemory32(0x5C,"Register"); __message "R08 FIQ 0x",__mac_i:%X; +__mac_i =__readMemory32(0x60,"Register"); __message "R09 FIQ 0x",__mac_i:%X; +__mac_i =__readMemory32(0x64,"Register"); __message "R10 FIQ 0x",__mac_i:%X; +__mac_i =__readMemory32(0x68,"Register"); __message "R11 FIQ 0x",__mac_i:%X; +__mac_i =__readMemory32(0x6C,"Register"); __message "R12 FIQ 0x",__mac_i:%X; +__mac_i =__readMemory32(0x70,"Register"); __message "R13 FIQ 0x",__mac_i:%X; +__mac_i =__readMemory32(0x74,"Register"); __message "R14 FIQ0x",__mac_i:%X; +__mac_i =__readMemory32(0x98,"Register"); __message "CPSR ",__mac_i:%X; +__mac_i =__readMemory32(0x94,"Register"); __message "SPSR ",__mac_i:%X; +__mac_i =__readMemory32(0x9C,"Register"); __message "SPSR ABT ",__mac_i:%X; +__mac_i =__readMemory32(0xA0,"Register"); __message "SPSR ABT ",__mac_i:%X; +__mac_i =__readMemory32(0xA4,"Register"); __message "SPSR UND ",__mac_i:%X; +__mac_i =__readMemory32(0xA8,"Register"); __message "SPSR IRQ ",__mac_i:%X; +__mac_i =__readMemory32(0xAC,"Register"); __message "SPSR FIQ ",__mac_i:%X; + +__mac_i =__readMemory32(0xB4,"Register"); __message "PC 0x",__mac_i:%X; + +} + + diff --git a/AT91SAM7S256/SAM7S256/Tools/at91SAM7S256_NoRemap.xcl b/AT91SAM7S256/SAM7S256/Tools/at91SAM7S256_NoRemap.xcl new file mode 100644 index 0000000..3682046 --- /dev/null +++ b/AT91SAM7S256/SAM7S256/Tools/at91SAM7S256_NoRemap.xcl @@ -0,0 +1,138 @@ +// --------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// --------------------------------------------------------- +// The software is delivered "AS IS" without warranty or +// condition of any kind, either express, implied or +// statutory. This includes without limitation any warranty +// or condition with respect to merchantability or fitness +// for any particular purpose, or against the infringements of +// intellectual property rights of others. +// --------------------------------------------------------- +// File: at91SAM7S256_NoRemap.xlc +// +// 1.1 24/Feb/05 JPP : Creation for 4.11A +// +// $Revision: 1.1.1.1 $ +// +// --------------------------------------------------------- + +//************************************************************************* +// XLINK command file template for EWARM/ICCARM +// +// Usage: xlink -f lnkarm +// -s +// +// $Revision: 1.1.1.1 $ +//************************************************************************* + +//************************************************ +// Inform the linker about the CPU family used. +// AT91SAM7S256 Memory mapping +// No remap +// ROMSTART +// Start address 0x0000 0000 +// Size 256 Kbo 0x0004 0000 +// RAMSTART +// Start address 0x0020 0000 +// Size 64 Kbo 0x0001 0000 +// Remap done +// RAMSTART +// Start address 0x0000 0000 +// Size 64 Kbo 0x0001 0000 +// ROMSTART +// Start address 0x0010 0000 +// Size 256 Kbo 0x0004 0000 + +//************************************************ +-carm + +//************************************************************************* +// Internal Ram segments mapped AFTER REMAP 64 K. +//************************************************************************* +// Use these addresses for the . +// Use these addresses for the . +-Z(CONST)INTRAMSTART_REMAP=00200000 +-Z(CONST)INTRAMEND_REMAP=0020FFFF + +//************************************************************************* +// Read-only segments mapped to Flash 256 K. +//************************************************************************* +-DROMSTART=00000000 +-DROMEND=0003FFFF +//************************************************************************* +// Read/write segments mapped to 64 K RAM. +//************************************************************************* +-DRAMSTART=00200000 +-DRAMEND=0020FFFF + +//************************************************ +// Address range for reset and exception +// vectors (INTVEC). +// The vector area is 32 bytes, +// an additional 32 bytes is allocated for the +// constant table used by ldr PC in cstartup.s79. +//************************************************ +-Z(CODE)INTVEC=00-3F + +//************************************************ +// Startup code and exception routines (ICODE). +//************************************************ +-Z(CODE)ICODE,DIFUNCT=ROMSTART-ROMEND +-Z(CODE)SWITAB=ROMSTART-ROMEND + +//************************************************ +// Code segments may be placed anywhere. +//************************************************ +-Z(CODE)CODE=ROMSTART-ROMEND + +//************************************************ +// Various constants and initializers. +//************************************************ +-Z(CONST)INITTAB,DATA_ID,DATA_C=ROMSTART-ROMEND +-Z(CONST)CHECKSUM=ROMSTART-ROMEND + +//************************************************ +// Data segments. +//************************************************ +-Z(DATA)DATA_I,DATA_Z,DATA_N=RAMSTART-RAMEND + +//************************************************ +// __ramfunc code copied to and executed from RAM. +//************************************************ +-Z(DATA)CODE_I=RAMSTART-RAMEND +-Z(CONST)CODE_ID=ROMSTART-ROMEND // Initializer for +-QCODE_I=CODE_ID + +//************************************************ +// ICCARM produces code for __ramfunc functions in +// CODE_I segments. The -Q XLINK command line +// option redirects XLINK to emit the code in the +// debug information associated with the CODE_I +// segment, where the code will execute. +//************************************************ + +//************************************************************************* +// Stack and heap segments. +//************************************************************************* +-D_CSTACK_SIZE=(100*4) +-D_IRQ_STACK_SIZE=(3*8*4) + +-Z(DATA)CSTACK+_CSTACK_SIZE=RAMSTART-RAMEND +-Z(DATA)IRQ_STACK+_IRQ_STACK_SIZE=RAMSTART-RAMEND + +//************************************************************************* +// ELF/DWARF support. +// +// Uncomment the line "-Felf" below to generate ELF/DWARF output. +// Available format specifiers are: +// +// "-yn": Suppress DWARF debug output +// "-yp": Multiple ELF program sections +// "-yas": Format suitable for debuggers from ARM Ltd (also sets -p flag) +// +// "-Felf" and the format specifiers can also be supplied directly as +// command line options, or selected from the Xlink Output tab in the +// IAR Embedded Workbench. +//************************************************************************* + +// -Felf diff --git a/AT91SAM7S256/SAM7S256/Tools/at91SAM7S256_Remap.xcl b/AT91SAM7S256/SAM7S256/Tools/at91SAM7S256_Remap.xcl new file mode 100644 index 0000000..ebc4205 --- /dev/null +++ b/AT91SAM7S256/SAM7S256/Tools/at91SAM7S256_Remap.xcl @@ -0,0 +1,143 @@ +// --------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// --------------------------------------------------------- +// The software is delivered "AS IS" without warranty or +// condition of any kind, either express, implied or +// statutory. This includes without limitation any warranty +// or condition with respect to merchantability or fitness +// for any particular purpose, or against the infringements of +// intellectual property rights of others. +// --------------------------------------------------------- +// File: at91SAM7S64_Remap.xlc +// +// 1.2 04/Feb/05 JPP : Creation for 4.11A +// 1.2 08/Feb/05 JPP : Add Remap address and CODE_I for __ramfuc +// +// $Revision: 1.2 $ +// +// --------------------------------------------------------- + +//************************************************************************* +// XLINK command file template for EWARM/ICCARM +// +// Usage: xlink -f lnkarm +// -s +// +// $Revision: 1.2 $ +//************************************************************************* + +//************************************************ +// Inform the linker about the CPU family used. +// AT91SAM7S64 Memory mapping +// No remap +// ROMSTART +// Start address 0x0000 0000 +// Size 256 Kbo 0x0004 0000 +// RAMSTART +// Start address 0x0020 0000 +// Size 64 Kbo 0x0001 0000 +// Remap done +// RAMSTART +// Start address 0x0000 0000 +// Size 64 Kbo 0x0001 0000 +// ROMSTART +// Start address 0x0010 0000 +// Size 256 Kbo 0x0004 0000 + +//************************************************ +-carm + +//************************************************************************* +// Internal Ram segments mapped AFTER REMAP 64 K. +//************************************************************************* + +// Base address used to stack before remap +-Z(CONST)INTRAMSTART=00200000 +-Z(CONST)INTRAMEND_BEFORE_REMAP=00210000 +// Base address used to RAM after Reamp +-Z(CONST)INTRAMEND_REMAP=00010000 + +//************************************************************************* +// Read-only segments mapped to Flash 256 K. +//************************************************************************* +-DROMSTART=00100000 +-DROMEND=0013FFFF +//************************************************************************* +// Read/write segments mapped to RAM. +//************************************************************************* +// the first space it used for interrupt vector +-DRAMSTART=00000100 +-DRAMEND=0000FFFF + +//************************************************ +// Address range for reset and exception +// vectors (INTVEC). +// The vector area is 32 bytes, +// an additional 32 bytes is allocated for the +// constant table used by ldr PC in cstartup.s79. +//************************************************ +-Z(CODE)INTVEC=00-3F + +//************************************************ +// Startup code and exception routines (ICODE). +//************************************************ +-Z(CODE)ICODE,DIFUNCT=ROMSTART-ROMEND +-Z(CODE)SWITAB=ROMSTART-ROMEND + +//************************************************ +// Code segments may be placed anywhere. +//************************************************ +-Z(CODE)CODE=ROMSTART-ROMEND + +//************************************************ +// Various constants and initializers. +//************************************************ +-Z(CONST)INITTAB,DATA_ID,DATA_C=ROMSTART-ROMEND +-Z(CONST)CHECKSUM=ROMSTART-ROMEND + + +//************************************************ +// Data segments. +//************************************************ +-Z(DATA)DATA_I,DATA_Z,DATA_N=RAMSTART-RAMEND + +//************************************************ +// ICCARM produces code for __ramfunc functions in +// CODE_I segments. The -Q XLINK command line +// option redirects XLINK to emit the code in the +// debug information associated with the CODE_I +// segment, where the code will execute. +//************************************************ +//************************************************ +// __ramfunc code copied to and executed from RAM. +//************************************************ +-Z(DATA)CODE_I=RAMSTART-RAMEND +-Z(CONST)CODE_ID=ROMSTART-ROMEND // Initializer for +-QCODE_I=CODE_ID + + +//************************************************************************* +// Stack and heap segments. +//************************************************************************* +-D_CSTACK_SIZE=(100*4) +-D_IRQ_STACK_SIZE=(3*8*4) + +-Z(DATA)CSTACK+_CSTACK_SIZE=RAMSTART-RAMEND +-Z(DATA)IRQ_STACK+_IRQ_STACK_SIZE=RAMSTART-RAMEND + +//************************************************************************* +// ELF/DWARF support. +// +// Uncomment the line "-Felf" below to generate ELF/DWARF output. +// Available format specifiers are: +// +// "-yn": Suppress DWARF debug output +// "-yp": Multiple ELF program sections +// "-yas": Format suitable for debuggers from ARM Ltd (also sets -p flag) +// +// "-Felf" and the format specifiers can also be supplied directly as +// command line options, or selected from the Xlink Output tab in the +// IAR Embedded Workbench. +//************************************************************************* + +// -Felf diff --git a/AT91SAM7S256/SAM7S256/Tools/at91SAM7S64_NoRemap.xcl b/AT91SAM7S256/SAM7S256/Tools/at91SAM7S64_NoRemap.xcl new file mode 100644 index 0000000..754cb14 --- /dev/null +++ b/AT91SAM7S256/SAM7S256/Tools/at91SAM7S64_NoRemap.xcl @@ -0,0 +1,139 @@ +// --------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// --------------------------------------------------------- +// The software is delivered "AS IS" without warranty or +// condition of any kind, either express, implied or +// statutory. This includes without limitation any warranty +// or condition with respect to merchantability or fitness +// for any particular purpose, or against the infringements of +// intellectual property rights of others. +// --------------------------------------------------------- +// File: at91SAM7S64_NoRemap.xlc +// +// 1.1 16/Jun/04 JPP : Creation for 4.11A +// 1.2 08/Feb/05 JPP : Add CODE_I for __ramfuc +// +// $Revision: 1.1 $ +// +// --------------------------------------------------------- + +//************************************************************************* +// XLINK command file template for EWARM/ICCARM +// +// Usage: xlink -f lnkarm +// -s +// +// $Revision: 1.1 $ +//************************************************************************* + +//************************************************ +// Inform the linker about the CPU family used. +// AT91SAM7S64 Memory mapping +// No remap +// ROMSTART +// Start address 0x0000 0000 +// Size 64 Kbo 0x0001 0000 +// RAMSTART +// Start address 0x0020 0000 +// Size 16 Kbo 0x0000 4000 +// Remap done +// RAMSTART +// Start address 0x0000 0000 +// Size 16 Kbo 0x0000 4000 +// ROMSTART +// Start address 0x0010 0000 +// Size 64 Kbo 0x0001 0000 + +//************************************************ +-carm + +//************************************************************************* +// Internal Ram segments mapped AFTER REMAP 16 K. +//************************************************************************* +// Use these addresses for the . +-Z(CONST)INTRAMSTART_REMAP=00200000 +-Z(CONST)INTRAMEND_REMAP=00203FFF + +//************************************************************************* +// Read-only segments mapped to Flash 64 K. +//************************************************************************* +-DROMSTART=00000000 +-DROMEND=0000FFFF +//************************************************************************* +// Read/write segments mapped to RAM. +//************************************************************************* +-DRAMSTART=00200000 +-DRAMEND=002003FFF + +//************************************************ +// Address range for reset and exception +// vectors (INTVEC). +// The vector area is 32 bytes, +// an additional 32 bytes is allocated for the +// constant table used by ldr PC in cstartup.s79. +//************************************************ +-Z(CODE)INTVEC=00-3F + +//************************************************ +// Startup code and exception routines (ICODE). +//************************************************ +-Z(CODE)ICODE,DIFUNCT=ROMSTART-ROMEND +-Z(CODE)SWITAB=ROMSTART-ROMEND + +//************************************************ +// Code segments may be placed anywhere. +//************************************************ +-Z(CODE)CODE=ROMSTART-ROMEND + +//************************************************ +// Various constants and initializers. +//************************************************ +-Z(CONST)INITTAB,DATA_ID,DATA_C=ROMSTART-ROMEND +-Z(CONST)CHECKSUM=ROMSTART-ROMEND + + +//************************************************ +// Data segments. +//************************************************ +-Z(DATA)DATA_I,DATA_Z,DATA_N=RAMSTART-RAMEND + +//************************************************ +// __ramfunc code copied to and executed from RAM. +//************************************************ +-Z(DATA)CODE_I=RAMSTART-RAMEND +-Z(CONST)CODE_ID=ROMSTART-ROMEND // Initializer for +-QCODE_I=CODE_ID + +//************************************************ +// ICCARM produces code for __ramfunc functions in +// CODE_I segments. The -Q XLINK command line +// option redirects XLINK to emit the code in the +// debug information associated with the CODE_I +// segment, where the code will execute. +//************************************************ + +//************************************************************************* +// Stack and heap segments. +//************************************************************************* +-D_CSTACK_SIZE=(100*4) +-D_IRQ_STACK_SIZE=(3*8*4) + +-Z(DATA)CSTACK+_CSTACK_SIZE=RAMSTART-RAMEND +-Z(DATA)IRQ_STACK+_IRQ_STACK_SIZE=RAMSTART-RAMEND + +//************************************************************************* +// ELF/DWARF support. +// +// Uncomment the line "-Felf" below to generate ELF/DWARF output. +// Available format specifiers are: +// +// "-yn": Suppress DWARF debug output +// "-yp": Multiple ELF program sections +// "-yas": Format suitable for debuggers from ARM Ltd (also sets -p flag) +// +// "-Felf" and the format specifiers can also be supplied directly as +// command line options, or selected from the Xlink Output tab in the +// IAR Embedded Workbench. +//************************************************************************* + +// -Felf diff --git a/AT91SAM7S256/SAM7S256/Tools/ioat91sam7s256.ddf b/AT91SAM7S256/SAM7S256/Tools/ioat91sam7s256.ddf new file mode 100644 index 0000000..19e5e04 --- /dev/null +++ b/AT91SAM7S256/SAM7S256/Tools/ioat91sam7s256.ddf @@ -0,0 +1,1577 @@ +; ---------------------------------------------------------------------------- +; ATMEL Microcontroller Software Support - ROUSSET - +; ---------------------------------------------------------------------------- +; DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +; IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +; MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +; DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +; INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +; OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +; LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +; NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +; EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; ---------------------------------------------------------------------------- +; File Name : AT91SAM7S256.ddf +; Object : AT91SAM7S256 definitions +; Generated : AT91 SW Application Group 03/08/2005 (15:46:17) +; +; CVS Reference : /AT91SAM7S256.pl/1.8/Wed Feb 9 15:29:26 2005// +; CVS Reference : /SYS_SAM7S.pl/1.2/Tue Feb 1 17:01:52 2005// +; CVS Reference : /MC_SAM7S.pl/1.2/Tue Feb 1 17:01:00 2005// +; CVS Reference : /PMC_SAM7S_USB.pl/1.4/Tue Feb 8 13:58:22 2005// +; CVS Reference : /RSTC_SAM7S.pl/1.1/Tue Feb 1 16:16:35 2005// +; CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// +; CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// +; CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// +; CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// +; CVS Reference : /UDP_6083C.pl/1.1/Mon Jan 31 13:01:46 2005// +; CVS Reference : /AIC_6075A.pl/1.1/Fri Jun 28 10:36:48 2002// +; CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// +; CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// +; CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// +; CVS Reference : /SPI_6088D.pl/1.2/Mon Feb 14 07:24:18 2005// +; CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// +; CVS Reference : /TC_6082A.pl/1.6/Fri Feb 18 13:53:30 2005// +; CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// +; CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// +; CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// +; CVS Reference : /PWM_6044D.pl/1.1/Tue Apr 27 14:53:52 2004// +; ---------------------------------------------------------------------------- + +[Sfr] + +; ========== Register definition for SYS peripheral ========== +; ========== Register definition for AIC peripheral ========== +sfr = "AIC_SMR", "Memory", 0xfffff000, 4, base=16 +sfr = "AIC_SMR.PRIOR", "Memory", 0xfffff000, 4, base=16, bitRange=0-2 +sfr = "AIC_SMR.SRCTYPE", "Memory", 0xfffff000, 4, base=16, bitRange=5-6 +sfr = "AIC_SVR", "Memory", 0xfffff080, 4, base=16 +sfr = "AIC_IVR", "Memory", 0xfffff100, 4, base=16 +sfr = "AIC_FVR", "Memory", 0xfffff104, 4, base=16 +sfr = "AIC_ISR", "Memory", 0xfffff108, 4, base=16 +sfr = "AIC_IPR", "Memory", 0xfffff10c, 4, base=16 +sfr = "AIC_IMR", "Memory", 0xfffff110, 4, base=16 +sfr = "AIC_CISR", "Memory", 0xfffff114, 4, base=16 +sfr = "AIC_CISR.NFIQ", "Memory", 0xfffff114, 4, base=16, bitRange=0 +sfr = "AIC_CISR.NIRQ", "Memory", 0xfffff114, 4, base=16, bitRange=1 +sfr = "AIC_IECR", "Memory", 0xfffff120, 4, base=16 +sfr = "AIC_IDCR", "Memory", 0xfffff124, 4, base=16 +sfr = "AIC_ICCR", "Memory", 0xfffff128, 4, base=16 +sfr = "AIC_ISCR", "Memory", 0xfffff12c, 4, base=16 +sfr = "AIC_EOICR", "Memory", 0xfffff130, 4, base=16 +sfr = "AIC_SPU", "Memory", 0xfffff134, 4, base=16 +sfr = "AIC_DCR", "Memory", 0xfffff138, 4, base=16 +sfr = "AIC_DCR.PROT", "Memory", 0xfffff138, 4, base=16, bitRange=0 +sfr = "AIC_DCR.GMSK", "Memory", 0xfffff138, 4, base=16, bitRange=1 +sfr = "AIC_FFER", "Memory", 0xfffff140, 4, base=16 +sfr = "AIC_FFDR", "Memory", 0xfffff144, 4, base=16 +sfr = "AIC_FFSR", "Memory", 0xfffff148, 4, base=16 +; ========== Register definition for PDC_DBGU peripheral ========== +sfr = "DBGU_RPR", "Memory", 0xfffff300, 4, base=16 +sfr = "DBGU_RCR", "Memory", 0xfffff304, 4, base=16 +sfr = "DBGU_TPR", "Memory", 0xfffff308, 4, base=16 +sfr = "DBGU_TCR", "Memory", 0xfffff30c, 4, base=16 +sfr = "DBGU_RNPR", "Memory", 0xfffff310, 4, base=16 +sfr = "DBGU_RNCR", "Memory", 0xfffff314, 4, base=16 +sfr = "DBGU_TNPR", "Memory", 0xfffff318, 4, base=16 +sfr = "DBGU_TNCR", "Memory", 0xfffff31c, 4, base=16 +sfr = "DBGU_PTCR", "Memory", 0xfffff320, 4, base=16 +sfr = "DBGU_PTCR.RXTEN", "Memory", 0xfffff320, 4, base=16, bitRange=0 +sfr = "DBGU_PTCR.RXTDIS", "Memory", 0xfffff320, 4, base=16, bitRange=1 +sfr = "DBGU_PTCR.TXTEN", "Memory", 0xfffff320, 4, base=16, bitRange=8 +sfr = "DBGU_PTCR.TXTDIS", "Memory", 0xfffff320, 4, base=16, bitRange=9 +sfr = "DBGU_PTSR", "Memory", 0xfffff324, 4, base=16 +sfr = "DBGU_PTSR.RXTEN", "Memory", 0xfffff324, 4, base=16, bitRange=0 +sfr = "DBGU_PTSR.TXTEN", "Memory", 0xfffff324, 4, base=16, bitRange=8 +; ========== Register definition for DBGU peripheral ========== +sfr = "DBGU_CR", "Memory", 0xfffff200, 4, base=16 +sfr = "DBGU_CR.RSTRX", "Memory", 0xfffff200, 4, base=16, bitRange=2 +sfr = "DBGU_CR.RSTTX", "Memory", 0xfffff200, 4, base=16, bitRange=3 +sfr = "DBGU_CR.RXEN", "Memory", 0xfffff200, 4, base=16, bitRange=4 +sfr = "DBGU_CR.RXDIS", "Memory", 0xfffff200, 4, base=16, bitRange=5 +sfr = "DBGU_CR.TXEN", "Memory", 0xfffff200, 4, base=16, bitRange=6 +sfr = "DBGU_CR.TXDIS", "Memory", 0xfffff200, 4, base=16, bitRange=7 +sfr = "DBGU_CR.RSTSTA", "Memory", 0xfffff200, 4, base=16, bitRange=8 +sfr = "DBGU_MR", "Memory", 0xfffff204, 4, base=16 +sfr = "DBGU_MR.PAR", "Memory", 0xfffff204, 4, base=16, bitRange=9-11 +sfr = "DBGU_MR.CHMODE", "Memory", 0xfffff204, 4, base=16, bitRange=14-15 +sfr = "DBGU_IER", "Memory", 0xfffff208, 4, base=16 +sfr = "DBGU_IER.RXRDY", "Memory", 0xfffff208, 4, base=16, bitRange=0 +sfr = "DBGU_IER.TXRDY", "Memory", 0xfffff208, 4, base=16, bitRange=1 +sfr = "DBGU_IER.ENDRX", "Memory", 0xfffff208, 4, base=16, bitRange=3 +sfr = "DBGU_IER.ENDTX", "Memory", 0xfffff208, 4, base=16, bitRange=4 +sfr = "DBGU_IER.OVRE", "Memory", 0xfffff208, 4, base=16, bitRange=5 +sfr = "DBGU_IER.FRAME", "Memory", 0xfffff208, 4, base=16, bitRange=6 +sfr = "DBGU_IER.PARE", "Memory", 0xfffff208, 4, base=16, bitRange=7 +sfr = "DBGU_IER.TXEMPTY", "Memory", 0xfffff208, 4, base=16, bitRange=9 +sfr = "DBGU_IER.TXBUFE", "Memory", 0xfffff208, 4, base=16, bitRange=11 +sfr = "DBGU_IER.RXBUFF", "Memory", 0xfffff208, 4, base=16, bitRange=12 +sfr = "DBGU_IER.TX", "Memory", 0xfffff208, 4, base=16, bitRange=30 +sfr = "DBGU_IER.RX", "Memory", 0xfffff208, 4, base=16, bitRange=31 +sfr = "DBGU_IDR", "Memory", 0xfffff20c, 4, base=16 +sfr = "DBGU_IDR.RXRDY", "Memory", 0xfffff20c, 4, base=16, bitRange=0 +sfr = "DBGU_IDR.TXRDY", "Memory", 0xfffff20c, 4, base=16, bitRange=1 +sfr = "DBGU_IDR.ENDRX", "Memory", 0xfffff20c, 4, base=16, bitRange=3 +sfr = "DBGU_IDR.ENDTX", "Memory", 0xfffff20c, 4, base=16, bitRange=4 +sfr = "DBGU_IDR.OVRE", "Memory", 0xfffff20c, 4, base=16, bitRange=5 +sfr = "DBGU_IDR.FRAME", "Memory", 0xfffff20c, 4, base=16, bitRange=6 +sfr = "DBGU_IDR.PARE", "Memory", 0xfffff20c, 4, base=16, bitRange=7 +sfr = "DBGU_IDR.TXEMPTY", "Memory", 0xfffff20c, 4, base=16, bitRange=9 +sfr = "DBGU_IDR.TXBUFE", "Memory", 0xfffff20c, 4, base=16, bitRange=11 +sfr = "DBGU_IDR.RXBUFF", "Memory", 0xfffff20c, 4, base=16, bitRange=12 +sfr = "DBGU_IDR.TX", "Memory", 0xfffff20c, 4, base=16, bitRange=30 +sfr = "DBGU_IDR.RX", "Memory", 0xfffff20c, 4, base=16, bitRange=31 +sfr = "DBGU_IMR", "Memory", 0xfffff210, 4, base=16 +sfr = "DBGU_IMR.RXRDY", "Memory", 0xfffff210, 4, base=16, bitRange=0 +sfr = "DBGU_IMR.TXRDY", "Memory", 0xfffff210, 4, base=16, bitRange=1 +sfr = "DBGU_IMR.ENDRX", "Memory", 0xfffff210, 4, base=16, bitRange=3 +sfr = "DBGU_IMR.ENDTX", "Memory", 0xfffff210, 4, base=16, bitRange=4 +sfr = "DBGU_IMR.OVRE", "Memory", 0xfffff210, 4, base=16, bitRange=5 +sfr = "DBGU_IMR.FRAME", "Memory", 0xfffff210, 4, base=16, bitRange=6 +sfr = "DBGU_IMR.PARE", "Memory", 0xfffff210, 4, base=16, bitRange=7 +sfr = "DBGU_IMR.TXEMPTY", "Memory", 0xfffff210, 4, base=16, bitRange=9 +sfr = "DBGU_IMR.TXBUFE", "Memory", 0xfffff210, 4, base=16, bitRange=11 +sfr = "DBGU_IMR.RXBUFF", "Memory", 0xfffff210, 4, base=16, bitRange=12 +sfr = "DBGU_IMR.TX", "Memory", 0xfffff210, 4, base=16, bitRange=30 +sfr = "DBGU_IMR.RX", "Memory", 0xfffff210, 4, base=16, bitRange=31 +sfr = "DBGU_CSR", "Memory", 0xfffff214, 4, base=16 +sfr = "DBGU_CSR.RXRDY", "Memory", 0xfffff214, 4, base=16, bitRange=0 +sfr = "DBGU_CSR.TXRDY", "Memory", 0xfffff214, 4, base=16, bitRange=1 +sfr = "DBGU_CSR.ENDRX", "Memory", 0xfffff214, 4, base=16, bitRange=3 +sfr = "DBGU_CSR.ENDTX", "Memory", 0xfffff214, 4, base=16, bitRange=4 +sfr = "DBGU_CSR.OVRE", "Memory", 0xfffff214, 4, base=16, bitRange=5 +sfr = "DBGU_CSR.FRAME", "Memory", 0xfffff214, 4, base=16, bitRange=6 +sfr = "DBGU_CSR.PARE", "Memory", 0xfffff214, 4, base=16, bitRange=7 +sfr = "DBGU_CSR.TXEMPTY", "Memory", 0xfffff214, 4, base=16, bitRange=9 +sfr = "DBGU_CSR.TXBUFE", "Memory", 0xfffff214, 4, base=16, bitRange=11 +sfr = "DBGU_CSR.RXBUFF", "Memory", 0xfffff214, 4, base=16, bitRange=12 +sfr = "DBGU_CSR.TX", "Memory", 0xfffff214, 4, base=16, bitRange=30 +sfr = "DBGU_CSR.RX", "Memory", 0xfffff214, 4, base=16, bitRange=31 +sfr = "DBGU_RHR", "Memory", 0xfffff218, 4, base=16 +sfr = "DBGU_THR", "Memory", 0xfffff21c, 4, base=16 +sfr = "DBGU_BRGR", "Memory", 0xfffff220, 4, base=16 +sfr = "DBGU_CIDR", "Memory", 0xfffff240, 4, base=16 +sfr = "DBGU_EXID", "Memory", 0xfffff244, 4, base=16 +sfr = "DBGU_FNTR", "Memory", 0xfffff248, 4, base=16 +sfr = "DBGU_FNTR.NTRST", "Memory", 0xfffff248, 4, base=16, bitRange=0 +; ========== Register definition for PIOA peripheral ========== +sfr = "PIOA_PER", "Memory", 0xfffff400, 4, base=16 +sfr = "PIOA_PDR", "Memory", 0xfffff404, 4, base=16 +sfr = "PIOA_PSR", "Memory", 0xfffff408, 4, base=16 +sfr = "PIOA_OER", "Memory", 0xfffff410, 4, base=16 +sfr = "PIOA_ODR", "Memory", 0xfffff414, 4, base=16 +sfr = "PIOA_OSR", "Memory", 0xfffff418, 4, base=16 +sfr = "PIOA_IFER", "Memory", 0xfffff420, 4, base=16 +sfr = "PIOA_IFDR", "Memory", 0xfffff424, 4, base=16 +sfr = "PIOA_IFSR", "Memory", 0xfffff428, 4, base=16 +sfr = "PIOA_SODR", "Memory", 0xfffff430, 4, base=16 +sfr = "PIOA_CODR", "Memory", 0xfffff434, 4, base=16 +sfr = "PIOA_ODSR", "Memory", 0xfffff438, 4, base=16 +sfr = "PIOA_PDSR", "Memory", 0xfffff43c, 4, base=16 +sfr = "PIOA_IER", "Memory", 0xfffff440, 4, base=16 +sfr = "PIOA_IDR", "Memory", 0xfffff444, 4, base=16 +sfr = "PIOA_IMR", "Memory", 0xfffff448, 4, base=16 +sfr = "PIOA_ISR", "Memory", 0xfffff44c, 4, base=16 +sfr = "PIOA_MDER", "Memory", 0xfffff450, 4, base=16 +sfr = "PIOA_MDDR", "Memory", 0xfffff454, 4, base=16 +sfr = "PIOA_MDSR", "Memory", 0xfffff458, 4, base=16 +sfr = "PIOA_PPUDR", "Memory", 0xfffff460, 4, base=16 +sfr = "PIOA_PPUER", "Memory", 0xfffff464, 4, base=16 +sfr = "PIOA_PPUSR", "Memory", 0xfffff468, 4, base=16 +sfr = "PIOA_ASR", "Memory", 0xfffff470, 4, base=16 +sfr = "PIOA_BSR", "Memory", 0xfffff474, 4, base=16 +sfr = "PIOA_ABSR", "Memory", 0xfffff478, 4, base=16 +sfr = "PIOA_OWER", "Memory", 0xfffff4a0, 4, base=16 +sfr = "PIOA_OWDR", "Memory", 0xfffff4a4, 4, base=16 +sfr = "PIOA_OWSR", "Memory", 0xfffff4a8, 4, base=16 +; ========== Register definition for CKGR peripheral ========== +sfr = "CKGR_MOR", "Memory", 0xfffffc20, 4, base=16 +sfr = "CKGR_MOR.MOSCEN", "Memory", 0xfffffc20, 4, base=16, bitRange=0 +sfr = "CKGR_MOR.OSCBYPASS", "Memory", 0xfffffc20, 4, base=16, bitRange=1 +sfr = "CKGR_MOR.OSCOUNT", "Memory", 0xfffffc20, 4, base=16, bitRange=8-15 +sfr = "CKGR_MCFR", "Memory", 0xfffffc24, 4, base=16 +sfr = "CKGR_MCFR.MAINF", "Memory", 0xfffffc24, 4, base=16, bitRange=0-15 +sfr = "CKGR_MCFR.MAINRDY", "Memory", 0xfffffc24, 4, base=16, bitRange=16 +sfr = "CKGR_PLLR", "Memory", 0xfffffc2c, 4, base=16 +sfr = "CKGR_PLLR.DIV", "Memory", 0xfffffc2c, 4, base=16, bitRange=0-7 +sfr = "CKGR_PLLR.PLLCOUNT", "Memory", 0xfffffc2c, 4, base=16, bitRange=8-13 +sfr = "CKGR_PLLR.OUT", "Memory", 0xfffffc2c, 4, base=16, bitRange=14-15 +sfr = "CKGR_PLLR.MUL", "Memory", 0xfffffc2c, 4, base=16, bitRange=16-26 +sfr = "CKGR_PLLR.USBDIV", "Memory", 0xfffffc2c, 4, base=16, bitRange=28-29 +; ========== Register definition for PMC peripheral ========== +sfr = "PMC_SCER", "Memory", 0xfffffc00, 4, base=16 +sfr = "PMC_SCER.PCK", "Memory", 0xfffffc00, 4, base=16, bitRange=0 +sfr = "PMC_SCER.UDP", "Memory", 0xfffffc00, 4, base=16, bitRange=7 +sfr = "PMC_SCER.PCK0", "Memory", 0xfffffc00, 4, base=16, bitRange=8 +sfr = "PMC_SCER.PCK1", "Memory", 0xfffffc00, 4, base=16, bitRange=9 +sfr = "PMC_SCER.PCK2", "Memory", 0xfffffc00, 4, base=16, bitRange=10 +sfr = "PMC_SCDR", "Memory", 0xfffffc04, 4, base=16 +sfr = "PMC_SCDR.PCK", "Memory", 0xfffffc04, 4, base=16, bitRange=0 +sfr = "PMC_SCDR.UDP", "Memory", 0xfffffc04, 4, base=16, bitRange=7 +sfr = "PMC_SCDR.PCK0", "Memory", 0xfffffc04, 4, base=16, bitRange=8 +sfr = "PMC_SCDR.PCK1", "Memory", 0xfffffc04, 4, base=16, bitRange=9 +sfr = "PMC_SCDR.PCK2", "Memory", 0xfffffc04, 4, base=16, bitRange=10 +sfr = "PMC_SCSR", "Memory", 0xfffffc08, 4, base=16 +sfr = "PMC_SCSR.PCK", "Memory", 0xfffffc08, 4, base=16, bitRange=0 +sfr = "PMC_SCSR.UDP", "Memory", 0xfffffc08, 4, base=16, bitRange=7 +sfr = "PMC_SCSR.PCK0", "Memory", 0xfffffc08, 4, base=16, bitRange=8 +sfr = "PMC_SCSR.PCK1", "Memory", 0xfffffc08, 4, base=16, bitRange=9 +sfr = "PMC_SCSR.PCK2", "Memory", 0xfffffc08, 4, base=16, bitRange=10 +sfr = "PMC_PCER", "Memory", 0xfffffc10, 4, base=16 +sfr = "PMC_PCDR", "Memory", 0xfffffc14, 4, base=16 +sfr = "PMC_PCSR", "Memory", 0xfffffc18, 4, base=16 +sfr = "PMC_MOR", "Memory", 0xfffffc20, 4, base=16 +sfr = "PMC_MOR.MOSCEN", "Memory", 0xfffffc20, 4, base=16, bitRange=0 +sfr = "PMC_MOR.OSCBYPASS", "Memory", 0xfffffc20, 4, base=16, bitRange=1 +sfr = "PMC_MOR.OSCOUNT", "Memory", 0xfffffc20, 4, base=16, bitRange=8-15 +sfr = "PMC_MCFR", "Memory", 0xfffffc24, 4, base=16 +sfr = "PMC_MCFR.MAINF", "Memory", 0xfffffc24, 4, base=16, bitRange=0-15 +sfr = "PMC_MCFR.MAINRDY", "Memory", 0xfffffc24, 4, base=16, bitRange=16 +sfr = "PMC_PLLR", "Memory", 0xfffffc2c, 4, base=16 +sfr = "PMC_PLLR.DIV", "Memory", 0xfffffc2c, 4, base=16, bitRange=0-7 +sfr = "PMC_PLLR.PLLCOUNT", "Memory", 0xfffffc2c, 4, base=16, bitRange=8-13 +sfr = "PMC_PLLR.OUT", "Memory", 0xfffffc2c, 4, base=16, bitRange=14-15 +sfr = "PMC_PLLR.MUL", "Memory", 0xfffffc2c, 4, base=16, bitRange=16-26 +sfr = "PMC_PLLR.USBDIV", "Memory", 0xfffffc2c, 4, base=16, bitRange=28-29 +sfr = "PMC_MCKR", "Memory", 0xfffffc30, 4, base=16 +sfr = "PMC_MCKR.CSS", "Memory", 0xfffffc30, 4, base=16, bitRange=0-1 +sfr = "PMC_MCKR.PRES", "Memory", 0xfffffc30, 4, base=16, bitRange=2-4 +sfr = "PMC_PCKR", "Memory", 0xfffffc40, 4, base=16 +sfr = "PMC_PCKR.CSS", "Memory", 0xfffffc40, 4, base=16, bitRange=0-1 +sfr = "PMC_PCKR.PRES", "Memory", 0xfffffc40, 4, base=16, bitRange=2-4 +sfr = "PMC_IER", "Memory", 0xfffffc60, 4, base=16 +sfr = "PMC_IER.MOSCS", "Memory", 0xfffffc60, 4, base=16, bitRange=0 +sfr = "PMC_IER.LOCK", "Memory", 0xfffffc60, 4, base=16, bitRange=2 +sfr = "PMC_IER.MCKRDY", "Memory", 0xfffffc60, 4, base=16, bitRange=3 +sfr = "PMC_IER.PCK0RDY", "Memory", 0xfffffc60, 4, base=16, bitRange=8 +sfr = "PMC_IER.PCK1RDY", "Memory", 0xfffffc60, 4, base=16, bitRange=9 +sfr = "PMC_IER.PCK2RDY", "Memory", 0xfffffc60, 4, base=16, bitRange=10 +sfr = "PMC_IDR", "Memory", 0xfffffc64, 4, base=16 +sfr = "PMC_IDR.MOSCS", "Memory", 0xfffffc64, 4, base=16, bitRange=0 +sfr = "PMC_IDR.LOCK", "Memory", 0xfffffc64, 4, base=16, bitRange=2 +sfr = "PMC_IDR.MCKRDY", "Memory", 0xfffffc64, 4, base=16, bitRange=3 +sfr = "PMC_IDR.PCK0RDY", "Memory", 0xfffffc64, 4, base=16, bitRange=8 +sfr = "PMC_IDR.PCK1RDY", "Memory", 0xfffffc64, 4, base=16, bitRange=9 +sfr = "PMC_IDR.PCK2RDY", "Memory", 0xfffffc64, 4, base=16, bitRange=10 +sfr = "PMC_SR", "Memory", 0xfffffc68, 4, base=16 +sfr = "PMC_SR.MOSCS", "Memory", 0xfffffc68, 4, base=16, bitRange=0 +sfr = "PMC_SR.LOCK", "Memory", 0xfffffc68, 4, base=16, bitRange=2 +sfr = "PMC_SR.MCKRDY", "Memory", 0xfffffc68, 4, base=16, bitRange=3 +sfr = "PMC_SR.PCK0RDY", "Memory", 0xfffffc68, 4, base=16, bitRange=8 +sfr = "PMC_SR.PCK1RDY", "Memory", 0xfffffc68, 4, base=16, bitRange=9 +sfr = "PMC_SR.PCK2RDY", "Memory", 0xfffffc68, 4, base=16, bitRange=10 +sfr = "PMC_IMR", "Memory", 0xfffffc6c, 4, base=16 +sfr = "PMC_IMR.MOSCS", "Memory", 0xfffffc6c, 4, base=16, bitRange=0 +sfr = "PMC_IMR.LOCK", "Memory", 0xfffffc6c, 4, base=16, bitRange=2 +sfr = "PMC_IMR.MCKRDY", "Memory", 0xfffffc6c, 4, base=16, bitRange=3 +sfr = "PMC_IMR.PCK0RDY", "Memory", 0xfffffc6c, 4, base=16, bitRange=8 +sfr = "PMC_IMR.PCK1RDY", "Memory", 0xfffffc6c, 4, base=16, bitRange=9 +sfr = "PMC_IMR.PCK2RDY", "Memory", 0xfffffc6c, 4, base=16, bitRange=10 +; ========== Register definition for RSTC peripheral ========== +sfr = "RSTC_RCR", "Memory", 0xfffffd00, 4, base=16 +sfr = "RSTC_RCR.PROCRST", "Memory", 0xfffffd00, 4, base=16, bitRange=0 +sfr = "RSTC_RCR.PERRST", "Memory", 0xfffffd00, 4, base=16, bitRange=2 +sfr = "RSTC_RCR.EXTRST", "Memory", 0xfffffd00, 4, base=16, bitRange=3 +sfr = "RSTC_RCR.KEY", "Memory", 0xfffffd00, 4, base=16, bitRange=24-31 +sfr = "RSTC_RSR", "Memory", 0xfffffd04, 4, base=16 +sfr = "RSTC_RSR.URSTS", "Memory", 0xfffffd04, 4, base=16, bitRange=0 +sfr = "RSTC_RSR.BODSTS", "Memory", 0xfffffd04, 4, base=16, bitRange=1 +sfr = "RSTC_RSR.RSTTYP", "Memory", 0xfffffd04, 4, base=16, bitRange=8-10 +sfr = "RSTC_RSR.NRSTL", "Memory", 0xfffffd04, 4, base=16, bitRange=16 +sfr = "RSTC_RSR.SRCMP", "Memory", 0xfffffd04, 4, base=16, bitRange=17 +sfr = "RSTC_RMR", "Memory", 0xfffffd08, 4, base=16 +sfr = "RSTC_RMR.URSTEN", "Memory", 0xfffffd08, 4, base=16, bitRange=0 +sfr = "RSTC_RMR.URSTIEN", "Memory", 0xfffffd08, 4, base=16, bitRange=4 +sfr = "RSTC_RMR.ERSTL", "Memory", 0xfffffd08, 4, base=16, bitRange=8-11 +sfr = "RSTC_RMR.BODIEN", "Memory", 0xfffffd08, 4, base=16, bitRange=16 +sfr = "RSTC_RMR.KEY", "Memory", 0xfffffd08, 4, base=16, bitRange=24-31 +; ========== Register definition for RTTC peripheral ========== +sfr = "RTTC_RTMR", "Memory", 0xfffffd20, 4, base=16 +sfr = "RTTC_RTMR.RTPRES", "Memory", 0xfffffd20, 4, base=16, bitRange=0-15 +sfr = "RTTC_RTMR.ALMIEN", "Memory", 0xfffffd20, 4, base=16, bitRange=16 +sfr = "RTTC_RTMR.RTTINCIEN", "Memory", 0xfffffd20, 4, base=16, bitRange=17 +sfr = "RTTC_RTMR.RTTRST", "Memory", 0xfffffd20, 4, base=16, bitRange=18 +sfr = "RTTC_RTAR", "Memory", 0xfffffd24, 4, base=16 +sfr = "RTTC_RTAR.ALMV", "Memory", 0xfffffd24, 4, base=16, bitRange=0-31 +sfr = "RTTC_RTVR", "Memory", 0xfffffd28, 4, base=16 +sfr = "RTTC_RTVR.CRTV", "Memory", 0xfffffd28, 4, base=16, bitRange=0-31 +sfr = "RTTC_RTSR", "Memory", 0xfffffd2c, 4, base=16 +sfr = "RTTC_RTSR.ALMS", "Memory", 0xfffffd2c, 4, base=16, bitRange=0 +sfr = "RTTC_RTSR.RTTINC", "Memory", 0xfffffd2c, 4, base=16, bitRange=1 +; ========== Register definition for PITC peripheral ========== +sfr = "PITC_PIMR", "Memory", 0xfffffd30, 4, base=16 +sfr = "PITC_PIMR.PIV", "Memory", 0xfffffd30, 4, base=16, bitRange=0-19 +sfr = "PITC_PIMR.PITEN", "Memory", 0xfffffd30, 4, base=16, bitRange=24 +sfr = "PITC_PIMR.PITIEN", "Memory", 0xfffffd30, 4, base=16, bitRange=25 +sfr = "PITC_PISR", "Memory", 0xfffffd34, 4, base=16 +sfr = "PITC_PISR.PITS", "Memory", 0xfffffd34, 4, base=16, bitRange=0 +sfr = "PITC_PIVR", "Memory", 0xfffffd38, 4, base=16 +sfr = "PITC_PIVR.CPIV", "Memory", 0xfffffd38, 4, base=16, bitRange=0-19 +sfr = "PITC_PIVR.PICNT", "Memory", 0xfffffd38, 4, base=16, bitRange=20-31 +sfr = "PITC_PIIR", "Memory", 0xfffffd3c, 4, base=16 +sfr = "PITC_PIIR.CPIV", "Memory", 0xfffffd3c, 4, base=16, bitRange=0-19 +sfr = "PITC_PIIR.PICNT", "Memory", 0xfffffd3c, 4, base=16, bitRange=20-31 +; ========== Register definition for WDTC peripheral ========== +sfr = "WDTC_WDCR", "Memory", 0xfffffd40, 4, base=16 +sfr = "WDTC_WDCR.WDRSTT", "Memory", 0xfffffd40, 4, base=16, bitRange=0 +sfr = "WDTC_WDCR.KEY", "Memory", 0xfffffd40, 4, base=16, bitRange=24-31 +sfr = "WDTC_WDMR", "Memory", 0xfffffd44, 4, base=16 +sfr = "WDTC_WDMR.WDV", "Memory", 0xfffffd44, 4, base=16, bitRange=0-11 +sfr = "WDTC_WDMR.WDFIEN", "Memory", 0xfffffd44, 4, base=16, bitRange=12 +sfr = "WDTC_WDMR.WDRSTEN", "Memory", 0xfffffd44, 4, base=16, bitRange=13 +sfr = "WDTC_WDMR.WDRPROC", "Memory", 0xfffffd44, 4, base=16, bitRange=14 +sfr = "WDTC_WDMR.WDDIS", "Memory", 0xfffffd44, 4, base=16, bitRange=15 +sfr = "WDTC_WDMR.WDD", "Memory", 0xfffffd44, 4, base=16, bitRange=16-27 +sfr = "WDTC_WDMR.WDDBGHLT", "Memory", 0xfffffd44, 4, base=16, bitRange=28 +sfr = "WDTC_WDMR.WDIDLEHLT", "Memory", 0xfffffd44, 4, base=16, bitRange=29 +sfr = "WDTC_WDSR", "Memory", 0xfffffd48, 4, base=16 +sfr = "WDTC_WDSR.WDUNF", "Memory", 0xfffffd48, 4, base=16, bitRange=0 +sfr = "WDTC_WDSR.WDERR", "Memory", 0xfffffd48, 4, base=16, bitRange=1 +; ========== Register definition for VREG peripheral ========== +sfr = "VREG_MR", "Memory", 0xfffffd60, 4, base=16 +sfr = "VREG_MR.PSTDBY", "Memory", 0xfffffd60, 4, base=16, bitRange=0 +; ========== Register definition for MC peripheral ========== +sfr = "MC_RCR", "Memory", 0xffffff00, 4, base=16 +sfr = "MC_RCR.RCB", "Memory", 0xffffff00, 4, base=16, bitRange=0 +sfr = "MC_ASR", "Memory", 0xffffff04, 4, base=16 +sfr = "MC_ASR.UNDADD", "Memory", 0xffffff04, 4, base=16, bitRange=0 +sfr = "MC_ASR.MISADD", "Memory", 0xffffff04, 4, base=16, bitRange=1 +sfr = "MC_ASR.ABTSZ", "Memory", 0xffffff04, 4, base=16, bitRange=8-9 +sfr = "MC_ASR.ABTTYP", "Memory", 0xffffff04, 4, base=16, bitRange=10-11 +sfr = "MC_ASR.MST0", "Memory", 0xffffff04, 4, base=16, bitRange=16 +sfr = "MC_ASR.MST1", "Memory", 0xffffff04, 4, base=16, bitRange=17 +sfr = "MC_ASR.SVMST0", "Memory", 0xffffff04, 4, base=16, bitRange=24 +sfr = "MC_ASR.SVMST1", "Memory", 0xffffff04, 4, base=16, bitRange=25 +sfr = "MC_AASR", "Memory", 0xffffff08, 4, base=16 +sfr = "MC_FMR", "Memory", 0xffffff60, 4, base=16 +sfr = "MC_FMR.FRDY", "Memory", 0xffffff60, 4, base=16, bitRange=0 +sfr = "MC_FMR.LOCKE", "Memory", 0xffffff60, 4, base=16, bitRange=2 +sfr = "MC_FMR.PROGE", "Memory", 0xffffff60, 4, base=16, bitRange=3 +sfr = "MC_FMR.NEBP", "Memory", 0xffffff60, 4, base=16, bitRange=7 +sfr = "MC_FMR.FWS", "Memory", 0xffffff60, 4, base=16, bitRange=8-9 +sfr = "MC_FMR.FMCN", "Memory", 0xffffff60, 4, base=16, bitRange=16-23 +sfr = "MC_FCR", "Memory", 0xffffff64, 4, base=16 +sfr = "MC_FCR.FCMD", "Memory", 0xffffff64, 4, base=16, bitRange=0-3 +sfr = "MC_FCR.PAGEN", "Memory", 0xffffff64, 4, base=16, bitRange=8-17 +sfr = "MC_FCR.KEY", "Memory", 0xffffff64, 4, base=16, bitRange=24-31 +sfr = "MC_FSR", "Memory", 0xffffff68, 4, base=16 +sfr = "MC_FSR.FRDY", "Memory", 0xffffff68, 4, base=16, bitRange=0 +sfr = "MC_FSR.LOCKE", "Memory", 0xffffff68, 4, base=16, bitRange=2 +sfr = "MC_FSR.PROGE", "Memory", 0xffffff68, 4, base=16, bitRange=3 +sfr = "MC_FSR.SECURITY", "Memory", 0xffffff68, 4, base=16, bitRange=4 +sfr = "MC_FSR.GPNVM0", "Memory", 0xffffff68, 4, base=16, bitRange=8 +sfr = "MC_FSR.GPNVM1", "Memory", 0xffffff68, 4, base=16, bitRange=9 +sfr = "MC_FSR.GPNVM2", "Memory", 0xffffff68, 4, base=16, bitRange=10 +sfr = "MC_FSR.GPNVM3", "Memory", 0xffffff68, 4, base=16, bitRange=11 +sfr = "MC_FSR.GPNVM4", "Memory", 0xffffff68, 4, base=16, bitRange=12 +sfr = "MC_FSR.GPNVM5", "Memory", 0xffffff68, 4, base=16, bitRange=13 +sfr = "MC_FSR.GPNVM6", "Memory", 0xffffff68, 4, base=16, bitRange=14 +sfr = "MC_FSR.GPNVM7", "Memory", 0xffffff68, 4, base=16, bitRange=15 +sfr = "MC_FSR.LOCKS0", "Memory", 0xffffff68, 4, base=16, bitRange=16 +sfr = "MC_FSR.LOCKS1", "Memory", 0xffffff68, 4, base=16, bitRange=17 +sfr = "MC_FSR.LOCKS2", "Memory", 0xffffff68, 4, base=16, bitRange=18 +sfr = "MC_FSR.LOCKS3", "Memory", 0xffffff68, 4, base=16, bitRange=19 +sfr = "MC_FSR.LOCKS4", "Memory", 0xffffff68, 4, base=16, bitRange=20 +sfr = "MC_FSR.LOCKS5", "Memory", 0xffffff68, 4, base=16, bitRange=21 +sfr = "MC_FSR.LOCKS6", "Memory", 0xffffff68, 4, base=16, bitRange=22 +sfr = "MC_FSR.LOCKS7", "Memory", 0xffffff68, 4, base=16, bitRange=23 +sfr = "MC_FSR.LOCKS8", "Memory", 0xffffff68, 4, base=16, bitRange=24 +sfr = "MC_FSR.LOCKS9", "Memory", 0xffffff68, 4, base=16, bitRange=25 +sfr = "MC_FSR.LOCKS10", "Memory", 0xffffff68, 4, base=16, bitRange=26 +sfr = "MC_FSR.LOCKS11", "Memory", 0xffffff68, 4, base=16, bitRange=27 +sfr = "MC_FSR.LOCKS12", "Memory", 0xffffff68, 4, base=16, bitRange=28 +sfr = "MC_FSR.LOCKS13", "Memory", 0xffffff68, 4, base=16, bitRange=29 +sfr = "MC_FSR.LOCKS14", "Memory", 0xffffff68, 4, base=16, bitRange=30 +sfr = "MC_FSR.LOCKS15", "Memory", 0xffffff68, 4, base=16, bitRange=31 +; ========== Register definition for PDC_SPI peripheral ========== +sfr = "SPI_RPR", "Memory", 0xfffe0100, 4, base=16 +sfr = "SPI_RCR", "Memory", 0xfffe0104, 4, base=16 +sfr = "SPI_TPR", "Memory", 0xfffe0108, 4, base=16 +sfr = "SPI_TCR", "Memory", 0xfffe010c, 4, base=16 +sfr = "SPI_RNPR", "Memory", 0xfffe0110, 4, base=16 +sfr = "SPI_RNCR", "Memory", 0xfffe0114, 4, base=16 +sfr = "SPI_TNPR", "Memory", 0xfffe0118, 4, base=16 +sfr = "SPI_TNCR", "Memory", 0xfffe011c, 4, base=16 +sfr = "SPI_PTCR", "Memory", 0xfffe0120, 4, base=16 +sfr = "SPI_PTCR.RXTEN", "Memory", 0xfffe0120, 4, base=16, bitRange=0 +sfr = "SPI_PTCR.RXTDIS", "Memory", 0xfffe0120, 4, base=16, bitRange=1 +sfr = "SPI_PTCR.TXTEN", "Memory", 0xfffe0120, 4, base=16, bitRange=8 +sfr = "SPI_PTCR.TXTDIS", "Memory", 0xfffe0120, 4, base=16, bitRange=9 +sfr = "SPI_PTSR", "Memory", 0xfffe0124, 4, base=16 +sfr = "SPI_PTSR.RXTEN", "Memory", 0xfffe0124, 4, base=16, bitRange=0 +sfr = "SPI_PTSR.TXTEN", "Memory", 0xfffe0124, 4, base=16, bitRange=8 +; ========== Register definition for SPI peripheral ========== +sfr = "SPI_CR", "Memory", 0xfffe0000, 4, base=16 +sfr = "SPI_CR.SPIEN", "Memory", 0xfffe0000, 4, base=16, bitRange=0 +sfr = "SPI_CR.SPIDIS", "Memory", 0xfffe0000, 4, base=16, bitRange=1 +sfr = "SPI_CR.SWRST", "Memory", 0xfffe0000, 4, base=16, bitRange=7 +sfr = "SPI_CR.LASTXFER", "Memory", 0xfffe0000, 4, base=16, bitRange=24 +sfr = "SPI_MR", "Memory", 0xfffe0004, 4, base=16 +sfr = "SPI_MR.MSTR", "Memory", 0xfffe0004, 4, base=16, bitRange=0 +sfr = "SPI_MR.PS", "Memory", 0xfffe0004, 4, base=16, bitRange=1 +sfr = "SPI_MR.PCSDEC", "Memory", 0xfffe0004, 4, base=16, bitRange=2 +sfr = "SPI_MR.FDIV", "Memory", 0xfffe0004, 4, base=16, bitRange=3 +sfr = "SPI_MR.MODFDIS", "Memory", 0xfffe0004, 4, base=16, bitRange=4 +sfr = "SPI_MR.LLB", "Memory", 0xfffe0004, 4, base=16, bitRange=7 +sfr = "SPI_MR.PCS", "Memory", 0xfffe0004, 4, base=16, bitRange=16-19 +sfr = "SPI_MR.DLYBCS", "Memory", 0xfffe0004, 4, base=16, bitRange=24-31 +sfr = "SPI_RDR", "Memory", 0xfffe0008, 4, base=16 +sfr = "SPI_RDR.RD", "Memory", 0xfffe0008, 4, base=16, bitRange=0-15 +sfr = "SPI_RDR.RPCS", "Memory", 0xfffe0008, 4, base=16, bitRange=16-19 +sfr = "SPI_TDR", "Memory", 0xfffe000c, 4, base=16 +sfr = "SPI_TDR.TD", "Memory", 0xfffe000c, 4, base=16, bitRange=0-15 +sfr = "SPI_TDR.TPCS", "Memory", 0xfffe000c, 4, base=16, bitRange=16-19 +sfr = "SPI_TDR.LASTXFER", "Memory", 0xfffe000c, 4, base=16, bitRange=24 +sfr = "SPI_SR", "Memory", 0xfffe0010, 4, base=16 +sfr = "SPI_SR.RDRF", "Memory", 0xfffe0010, 4, base=16, bitRange=0 +sfr = "SPI_SR.TDRE", "Memory", 0xfffe0010, 4, base=16, bitRange=1 +sfr = "SPI_SR.MODF", "Memory", 0xfffe0010, 4, base=16, bitRange=2 +sfr = "SPI_SR.OVRES", "Memory", 0xfffe0010, 4, base=16, bitRange=3 +sfr = "SPI_SR.ENDRX", "Memory", 0xfffe0010, 4, base=16, bitRange=4 +sfr = "SPI_SR.ENDTX", "Memory", 0xfffe0010, 4, base=16, bitRange=5 +sfr = "SPI_SR.RXBUFF", "Memory", 0xfffe0010, 4, base=16, bitRange=6 +sfr = "SPI_SR.TXBUFE", "Memory", 0xfffe0010, 4, base=16, bitRange=7 +sfr = "SPI_SR.NSSR", "Memory", 0xfffe0010, 4, base=16, bitRange=8 +sfr = "SPI_SR.TXEMPTY", "Memory", 0xfffe0010, 4, base=16, bitRange=9 +sfr = "SPI_SR.SPIENS", "Memory", 0xfffe0010, 4, base=16, bitRange=16 +sfr = "SPI_IER", "Memory", 0xfffe0014, 4, base=16 +sfr = "SPI_IER.RDRF", "Memory", 0xfffe0014, 4, base=16, bitRange=0 +sfr = "SPI_IER.TDRE", "Memory", 0xfffe0014, 4, base=16, bitRange=1 +sfr = "SPI_IER.MODF", "Memory", 0xfffe0014, 4, base=16, bitRange=2 +sfr = "SPI_IER.OVRES", "Memory", 0xfffe0014, 4, base=16, bitRange=3 +sfr = "SPI_IER.ENDRX", "Memory", 0xfffe0014, 4, base=16, bitRange=4 +sfr = "SPI_IER.ENDTX", "Memory", 0xfffe0014, 4, base=16, bitRange=5 +sfr = "SPI_IER.RXBUFF", "Memory", 0xfffe0014, 4, base=16, bitRange=6 +sfr = "SPI_IER.TXBUFE", "Memory", 0xfffe0014, 4, base=16, bitRange=7 +sfr = "SPI_IER.NSSR", "Memory", 0xfffe0014, 4, base=16, bitRange=8 +sfr = "SPI_IER.TXEMPTY", "Memory", 0xfffe0014, 4, base=16, bitRange=9 +sfr = "SPI_IDR", "Memory", 0xfffe0018, 4, base=16 +sfr = "SPI_IDR.RDRF", "Memory", 0xfffe0018, 4, base=16, bitRange=0 +sfr = "SPI_IDR.TDRE", "Memory", 0xfffe0018, 4, base=16, bitRange=1 +sfr = "SPI_IDR.MODF", "Memory", 0xfffe0018, 4, base=16, bitRange=2 +sfr = "SPI_IDR.OVRES", "Memory", 0xfffe0018, 4, base=16, bitRange=3 +sfr = "SPI_IDR.ENDRX", "Memory", 0xfffe0018, 4, base=16, bitRange=4 +sfr = "SPI_IDR.ENDTX", "Memory", 0xfffe0018, 4, base=16, bitRange=5 +sfr = "SPI_IDR.RXBUFF", "Memory", 0xfffe0018, 4, base=16, bitRange=6 +sfr = "SPI_IDR.TXBUFE", "Memory", 0xfffe0018, 4, base=16, bitRange=7 +sfr = "SPI_IDR.NSSR", "Memory", 0xfffe0018, 4, base=16, bitRange=8 +sfr = "SPI_IDR.TXEMPTY", "Memory", 0xfffe0018, 4, base=16, bitRange=9 +sfr = "SPI_IMR", "Memory", 0xfffe001c, 4, base=16 +sfr = "SPI_IMR.RDRF", "Memory", 0xfffe001c, 4, base=16, bitRange=0 +sfr = "SPI_IMR.TDRE", "Memory", 0xfffe001c, 4, base=16, bitRange=1 +sfr = "SPI_IMR.MODF", "Memory", 0xfffe001c, 4, base=16, bitRange=2 +sfr = "SPI_IMR.OVRES", "Memory", 0xfffe001c, 4, base=16, bitRange=3 +sfr = "SPI_IMR.ENDRX", "Memory", 0xfffe001c, 4, base=16, bitRange=4 +sfr = "SPI_IMR.ENDTX", "Memory", 0xfffe001c, 4, base=16, bitRange=5 +sfr = "SPI_IMR.RXBUFF", "Memory", 0xfffe001c, 4, base=16, bitRange=6 +sfr = "SPI_IMR.TXBUFE", "Memory", 0xfffe001c, 4, base=16, bitRange=7 +sfr = "SPI_IMR.NSSR", "Memory", 0xfffe001c, 4, base=16, bitRange=8 +sfr = "SPI_IMR.TXEMPTY", "Memory", 0xfffe001c, 4, base=16, bitRange=9 +sfr = "SPI_CSR", "Memory", 0xfffe0030, 4, base=16 +sfr = "SPI_CSR.CPOL", "Memory", 0xfffe0030, 4, base=16, bitRange=0 +sfr = "SPI_CSR.NCPHA", "Memory", 0xfffe0030, 4, base=16, bitRange=1 +sfr = "SPI_CSR.CSAAT", "Memory", 0xfffe0030, 4, base=16, bitRange=3 +sfr = "SPI_CSR.BITS", "Memory", 0xfffe0030, 4, base=16, bitRange=4-7 +sfr = "SPI_CSR.SCBR", "Memory", 0xfffe0030, 4, base=16, bitRange=8-15 +sfr = "SPI_CSR.DLYBS", "Memory", 0xfffe0030, 4, base=16, bitRange=16-23 +sfr = "SPI_CSR.DLYBCT", "Memory", 0xfffe0030, 4, base=16, bitRange=24-31 +; ========== Register definition for PDC_ADC peripheral ========== +sfr = "ADC_RPR", "Memory", 0xfffd8100, 4, base=16 +sfr = "ADC_RCR", "Memory", 0xfffd8104, 4, base=16 +sfr = "ADC_TPR", "Memory", 0xfffd8108, 4, base=16 +sfr = "ADC_TCR", "Memory", 0xfffd810c, 4, base=16 +sfr = "ADC_RNPR", "Memory", 0xfffd8110, 4, base=16 +sfr = "ADC_RNCR", "Memory", 0xfffd8114, 4, base=16 +sfr = "ADC_TNPR", "Memory", 0xfffd8118, 4, base=16 +sfr = "ADC_TNCR", "Memory", 0xfffd811c, 4, base=16 +sfr = "ADC_PTCR", "Memory", 0xfffd8120, 4, base=16 +sfr = "ADC_PTCR.RXTEN", "Memory", 0xfffd8120, 4, base=16, bitRange=0 +sfr = "ADC_PTCR.RXTDIS", "Memory", 0xfffd8120, 4, base=16, bitRange=1 +sfr = "ADC_PTCR.TXTEN", "Memory", 0xfffd8120, 4, base=16, bitRange=8 +sfr = "ADC_PTCR.TXTDIS", "Memory", 0xfffd8120, 4, base=16, bitRange=9 +sfr = "ADC_PTSR", "Memory", 0xfffd8124, 4, base=16 +sfr = "ADC_PTSR.RXTEN", "Memory", 0xfffd8124, 4, base=16, bitRange=0 +sfr = "ADC_PTSR.TXTEN", "Memory", 0xfffd8124, 4, base=16, bitRange=8 +; ========== Register definition for ADC peripheral ========== +sfr = "ADC_CR", "Memory", 0xfffd8000, 4, base=16 +sfr = "ADC_CR.SWRST", "Memory", 0xfffd8000, 4, base=16, bitRange=0 +sfr = "ADC_CR.START", "Memory", 0xfffd8000, 4, base=16, bitRange=1 +sfr = "ADC_MR", "Memory", 0xfffd8004, 4, base=16 +sfr = "ADC_MR.TRGEN", "Memory", 0xfffd8004, 4, base=16, bitRange=0 +sfr = "ADC_MR.TRGSEL", "Memory", 0xfffd8004, 4, base=16, bitRange=1-3 +sfr = "ADC_MR.LOWRES", "Memory", 0xfffd8004, 4, base=16, bitRange=4 +sfr = "ADC_MR.SLEEP", "Memory", 0xfffd8004, 4, base=16, bitRange=5 +sfr = "ADC_MR.PRESCAL", "Memory", 0xfffd8004, 4, base=16, bitRange=8-13 +sfr = "ADC_MR.STARTUP", "Memory", 0xfffd8004, 4, base=16, bitRange=16-20 +sfr = "ADC_MR.SHTIM", "Memory", 0xfffd8004, 4, base=16, bitRange=24-27 +sfr = "ADC_CHER", "Memory", 0xfffd8010, 4, base=16 +sfr = "ADC_CHER.CH0", "Memory", 0xfffd8010, 4, base=16, bitRange=0 +sfr = "ADC_CHER.CH1", "Memory", 0xfffd8010, 4, base=16, bitRange=1 +sfr = "ADC_CHER.CH2", "Memory", 0xfffd8010, 4, base=16, bitRange=2 +sfr = "ADC_CHER.CH3", "Memory", 0xfffd8010, 4, base=16, bitRange=3 +sfr = "ADC_CHER.CH4", "Memory", 0xfffd8010, 4, base=16, bitRange=4 +sfr = "ADC_CHER.CH5", "Memory", 0xfffd8010, 4, base=16, bitRange=5 +sfr = "ADC_CHER.CH6", "Memory", 0xfffd8010, 4, base=16, bitRange=6 +sfr = "ADC_CHER.CH7", "Memory", 0xfffd8010, 4, base=16, bitRange=7 +sfr = "ADC_CHDR", "Memory", 0xfffd8014, 4, base=16 +sfr = "ADC_CHDR.CH0", "Memory", 0xfffd8014, 4, base=16, bitRange=0 +sfr = "ADC_CHDR.CH1", "Memory", 0xfffd8014, 4, base=16, bitRange=1 +sfr = "ADC_CHDR.CH2", "Memory", 0xfffd8014, 4, base=16, bitRange=2 +sfr = "ADC_CHDR.CH3", "Memory", 0xfffd8014, 4, base=16, bitRange=3 +sfr = "ADC_CHDR.CH4", "Memory", 0xfffd8014, 4, base=16, bitRange=4 +sfr = "ADC_CHDR.CH5", "Memory", 0xfffd8014, 4, base=16, bitRange=5 +sfr = "ADC_CHDR.CH6", "Memory", 0xfffd8014, 4, base=16, bitRange=6 +sfr = "ADC_CHDR.CH7", "Memory", 0xfffd8014, 4, base=16, bitRange=7 +sfr = "ADC_CHSR", "Memory", 0xfffd8018, 4, base=16 +sfr = "ADC_CHSR.CH0", "Memory", 0xfffd8018, 4, base=16, bitRange=0 +sfr = "ADC_CHSR.CH1", "Memory", 0xfffd8018, 4, base=16, bitRange=1 +sfr = "ADC_CHSR.CH2", "Memory", 0xfffd8018, 4, base=16, bitRange=2 +sfr = "ADC_CHSR.CH3", "Memory", 0xfffd8018, 4, base=16, bitRange=3 +sfr = "ADC_CHSR.CH4", "Memory", 0xfffd8018, 4, base=16, bitRange=4 +sfr = "ADC_CHSR.CH5", "Memory", 0xfffd8018, 4, base=16, bitRange=5 +sfr = "ADC_CHSR.CH6", "Memory", 0xfffd8018, 4, base=16, bitRange=6 +sfr = "ADC_CHSR.CH7", "Memory", 0xfffd8018, 4, base=16, bitRange=7 +sfr = "ADC_SR", "Memory", 0xfffd801c, 4, base=16 +sfr = "ADC_SR.EOC0", "Memory", 0xfffd801c, 4, base=16, bitRange=0 +sfr = "ADC_SR.EOC1", "Memory", 0xfffd801c, 4, base=16, bitRange=1 +sfr = "ADC_SR.EOC2", "Memory", 0xfffd801c, 4, base=16, bitRange=2 +sfr = "ADC_SR.EOC3", "Memory", 0xfffd801c, 4, base=16, bitRange=3 +sfr = "ADC_SR.EOC4", "Memory", 0xfffd801c, 4, base=16, bitRange=4 +sfr = "ADC_SR.EOC5", "Memory", 0xfffd801c, 4, base=16, bitRange=5 +sfr = "ADC_SR.EOC6", "Memory", 0xfffd801c, 4, base=16, bitRange=6 +sfr = "ADC_SR.EOC7", "Memory", 0xfffd801c, 4, base=16, bitRange=7 +sfr = "ADC_SR.OVRE0", "Memory", 0xfffd801c, 4, base=16, bitRange=8 +sfr = "ADC_SR.OVRE1", "Memory", 0xfffd801c, 4, base=16, bitRange=9 +sfr = "ADC_SR.OVRE2", "Memory", 0xfffd801c, 4, base=16, bitRange=10 +sfr = "ADC_SR.OVRE3", "Memory", 0xfffd801c, 4, base=16, bitRange=11 +sfr = "ADC_SR.OVRE4", "Memory", 0xfffd801c, 4, base=16, bitRange=12 +sfr = "ADC_SR.OVRE5", "Memory", 0xfffd801c, 4, base=16, bitRange=13 +sfr = "ADC_SR.OVRE6", "Memory", 0xfffd801c, 4, base=16, bitRange=14 +sfr = "ADC_SR.OVRE7", "Memory", 0xfffd801c, 4, base=16, bitRange=15 +sfr = "ADC_SR.DRDY", "Memory", 0xfffd801c, 4, base=16, bitRange=16 +sfr = "ADC_SR.GOVRE", "Memory", 0xfffd801c, 4, base=16, bitRange=17 +sfr = "ADC_SR.ENDRX", "Memory", 0xfffd801c, 4, base=16, bitRange=18 +sfr = "ADC_SR.RXBUFF", "Memory", 0xfffd801c, 4, base=16, bitRange=19 +sfr = "ADC_LCDR", "Memory", 0xfffd8020, 4, base=16 +sfr = "ADC_LCDR.LDATA", "Memory", 0xfffd8020, 4, base=16, bitRange=0-9 +sfr = "ADC_IER", "Memory", 0xfffd8024, 4, base=16 +sfr = "ADC_IER.EOC0", "Memory", 0xfffd8024, 4, base=16, bitRange=0 +sfr = "ADC_IER.EOC1", "Memory", 0xfffd8024, 4, base=16, bitRange=1 +sfr = "ADC_IER.EOC2", "Memory", 0xfffd8024, 4, base=16, bitRange=2 +sfr = "ADC_IER.EOC3", "Memory", 0xfffd8024, 4, base=16, bitRange=3 +sfr = "ADC_IER.EOC4", "Memory", 0xfffd8024, 4, base=16, bitRange=4 +sfr = "ADC_IER.EOC5", "Memory", 0xfffd8024, 4, base=16, bitRange=5 +sfr = "ADC_IER.EOC6", "Memory", 0xfffd8024, 4, base=16, bitRange=6 +sfr = "ADC_IER.EOC7", "Memory", 0xfffd8024, 4, base=16, bitRange=7 +sfr = "ADC_IER.OVRE0", "Memory", 0xfffd8024, 4, base=16, bitRange=8 +sfr = "ADC_IER.OVRE1", "Memory", 0xfffd8024, 4, base=16, bitRange=9 +sfr = "ADC_IER.OVRE2", "Memory", 0xfffd8024, 4, base=16, bitRange=10 +sfr = "ADC_IER.OVRE3", "Memory", 0xfffd8024, 4, base=16, bitRange=11 +sfr = "ADC_IER.OVRE4", "Memory", 0xfffd8024, 4, base=16, bitRange=12 +sfr = "ADC_IER.OVRE5", "Memory", 0xfffd8024, 4, base=16, bitRange=13 +sfr = "ADC_IER.OVRE6", "Memory", 0xfffd8024, 4, base=16, bitRange=14 +sfr = "ADC_IER.OVRE7", "Memory", 0xfffd8024, 4, base=16, bitRange=15 +sfr = "ADC_IER.DRDY", "Memory", 0xfffd8024, 4, base=16, bitRange=16 +sfr = "ADC_IER.GOVRE", "Memory", 0xfffd8024, 4, base=16, bitRange=17 +sfr = "ADC_IER.ENDRX", "Memory", 0xfffd8024, 4, base=16, bitRange=18 +sfr = "ADC_IER.RXBUFF", "Memory", 0xfffd8024, 4, base=16, bitRange=19 +sfr = "ADC_IDR", "Memory", 0xfffd8028, 4, base=16 +sfr = "ADC_IDR.EOC0", "Memory", 0xfffd8028, 4, base=16, bitRange=0 +sfr = "ADC_IDR.EOC1", "Memory", 0xfffd8028, 4, base=16, bitRange=1 +sfr = "ADC_IDR.EOC2", "Memory", 0xfffd8028, 4, base=16, bitRange=2 +sfr = "ADC_IDR.EOC3", "Memory", 0xfffd8028, 4, base=16, bitRange=3 +sfr = "ADC_IDR.EOC4", "Memory", 0xfffd8028, 4, base=16, bitRange=4 +sfr = "ADC_IDR.EOC5", "Memory", 0xfffd8028, 4, base=16, bitRange=5 +sfr = "ADC_IDR.EOC6", "Memory", 0xfffd8028, 4, base=16, bitRange=6 +sfr = "ADC_IDR.EOC7", "Memory", 0xfffd8028, 4, base=16, bitRange=7 +sfr = "ADC_IDR.OVRE0", "Memory", 0xfffd8028, 4, base=16, bitRange=8 +sfr = "ADC_IDR.OVRE1", "Memory", 0xfffd8028, 4, base=16, bitRange=9 +sfr = "ADC_IDR.OVRE2", "Memory", 0xfffd8028, 4, base=16, bitRange=10 +sfr = "ADC_IDR.OVRE3", "Memory", 0xfffd8028, 4, base=16, bitRange=11 +sfr = "ADC_IDR.OVRE4", "Memory", 0xfffd8028, 4, base=16, bitRange=12 +sfr = "ADC_IDR.OVRE5", "Memory", 0xfffd8028, 4, base=16, bitRange=13 +sfr = "ADC_IDR.OVRE6", "Memory", 0xfffd8028, 4, base=16, bitRange=14 +sfr = "ADC_IDR.OVRE7", "Memory", 0xfffd8028, 4, base=16, bitRange=15 +sfr = "ADC_IDR.DRDY", "Memory", 0xfffd8028, 4, base=16, bitRange=16 +sfr = "ADC_IDR.GOVRE", "Memory", 0xfffd8028, 4, base=16, bitRange=17 +sfr = "ADC_IDR.ENDRX", "Memory", 0xfffd8028, 4, base=16, bitRange=18 +sfr = "ADC_IDR.RXBUFF", "Memory", 0xfffd8028, 4, base=16, bitRange=19 +sfr = "ADC_IMR", "Memory", 0xfffd802c, 4, base=16 +sfr = "ADC_IMR.EOC0", "Memory", 0xfffd802c, 4, base=16, bitRange=0 +sfr = "ADC_IMR.EOC1", "Memory", 0xfffd802c, 4, base=16, bitRange=1 +sfr = "ADC_IMR.EOC2", "Memory", 0xfffd802c, 4, base=16, bitRange=2 +sfr = "ADC_IMR.EOC3", "Memory", 0xfffd802c, 4, base=16, bitRange=3 +sfr = "ADC_IMR.EOC4", "Memory", 0xfffd802c, 4, base=16, bitRange=4 +sfr = "ADC_IMR.EOC5", "Memory", 0xfffd802c, 4, base=16, bitRange=5 +sfr = "ADC_IMR.EOC6", "Memory", 0xfffd802c, 4, base=16, bitRange=6 +sfr = "ADC_IMR.EOC7", "Memory", 0xfffd802c, 4, base=16, bitRange=7 +sfr = "ADC_IMR.OVRE0", "Memory", 0xfffd802c, 4, base=16, bitRange=8 +sfr = "ADC_IMR.OVRE1", "Memory", 0xfffd802c, 4, base=16, bitRange=9 +sfr = "ADC_IMR.OVRE2", "Memory", 0xfffd802c, 4, base=16, bitRange=10 +sfr = "ADC_IMR.OVRE3", "Memory", 0xfffd802c, 4, base=16, bitRange=11 +sfr = "ADC_IMR.OVRE4", "Memory", 0xfffd802c, 4, base=16, bitRange=12 +sfr = "ADC_IMR.OVRE5", "Memory", 0xfffd802c, 4, base=16, bitRange=13 +sfr = "ADC_IMR.OVRE6", "Memory", 0xfffd802c, 4, base=16, bitRange=14 +sfr = "ADC_IMR.OVRE7", "Memory", 0xfffd802c, 4, base=16, bitRange=15 +sfr = "ADC_IMR.DRDY", "Memory", 0xfffd802c, 4, base=16, bitRange=16 +sfr = "ADC_IMR.GOVRE", "Memory", 0xfffd802c, 4, base=16, bitRange=17 +sfr = "ADC_IMR.ENDRX", "Memory", 0xfffd802c, 4, base=16, bitRange=18 +sfr = "ADC_IMR.RXBUFF", "Memory", 0xfffd802c, 4, base=16, bitRange=19 +sfr = "ADC_CDR0", "Memory", 0xfffd8030, 4, base=16 +sfr = "ADC_CDR0.DATA", "Memory", 0xfffd8030, 4, base=16, bitRange=0-9 +sfr = "ADC_CDR1", "Memory", 0xfffd8034, 4, base=16 +sfr = "ADC_CDR1.DATA", "Memory", 0xfffd8034, 4, base=16, bitRange=0-9 +sfr = "ADC_CDR2", "Memory", 0xfffd8038, 4, base=16 +sfr = "ADC_CDR2.DATA", "Memory", 0xfffd8038, 4, base=16, bitRange=0-9 +sfr = "ADC_CDR3", "Memory", 0xfffd803c, 4, base=16 +sfr = "ADC_CDR3.DATA", "Memory", 0xfffd803c, 4, base=16, bitRange=0-9 +sfr = "ADC_CDR4", "Memory", 0xfffd8040, 4, base=16 +sfr = "ADC_CDR4.DATA", "Memory", 0xfffd8040, 4, base=16, bitRange=0-9 +sfr = "ADC_CDR5", "Memory", 0xfffd8044, 4, base=16 +sfr = "ADC_CDR5.DATA", "Memory", 0xfffd8044, 4, base=16, bitRange=0-9 +sfr = "ADC_CDR6", "Memory", 0xfffd8048, 4, base=16 +sfr = "ADC_CDR6.DATA", "Memory", 0xfffd8048, 4, base=16, bitRange=0-9 +sfr = "ADC_CDR7", "Memory", 0xfffd804c, 4, base=16 +sfr = "ADC_CDR7.DATA", "Memory", 0xfffd804c, 4, base=16, bitRange=0-9 +; ========== Register definition for PDC_SSC peripheral ========== +sfr = "SSC_RPR", "Memory", 0xfffd4100, 4, base=16 +sfr = "SSC_RCR", "Memory", 0xfffd4104, 4, base=16 +sfr = "SSC_TPR", "Memory", 0xfffd4108, 4, base=16 +sfr = "SSC_TCR", "Memory", 0xfffd410c, 4, base=16 +sfr = "SSC_RNPR", "Memory", 0xfffd4110, 4, base=16 +sfr = "SSC_RNCR", "Memory", 0xfffd4114, 4, base=16 +sfr = "SSC_TNPR", "Memory", 0xfffd4118, 4, base=16 +sfr = "SSC_TNCR", "Memory", 0xfffd411c, 4, base=16 +sfr = "SSC_PTCR", "Memory", 0xfffd4120, 4, base=16 +sfr = "SSC_PTCR.RXTEN", "Memory", 0xfffd4120, 4, base=16, bitRange=0 +sfr = "SSC_PTCR.RXTDIS", "Memory", 0xfffd4120, 4, base=16, bitRange=1 +sfr = "SSC_PTCR.TXTEN", "Memory", 0xfffd4120, 4, base=16, bitRange=8 +sfr = "SSC_PTCR.TXTDIS", "Memory", 0xfffd4120, 4, base=16, bitRange=9 +sfr = "SSC_PTSR", "Memory", 0xfffd4124, 4, base=16 +sfr = "SSC_PTSR.RXTEN", "Memory", 0xfffd4124, 4, base=16, bitRange=0 +sfr = "SSC_PTSR.TXTEN", "Memory", 0xfffd4124, 4, base=16, bitRange=8 +; ========== Register definition for SSC peripheral ========== +sfr = "SSC_CR", "Memory", 0xfffd4000, 4, base=16 +sfr = "SSC_CR.RXEN", "Memory", 0xfffd4000, 4, base=16, bitRange=0 +sfr = "SSC_CR.RXDIS", "Memory", 0xfffd4000, 4, base=16, bitRange=1 +sfr = "SSC_CR.TXEN", "Memory", 0xfffd4000, 4, base=16, bitRange=8 +sfr = "SSC_CR.TXDIS", "Memory", 0xfffd4000, 4, base=16, bitRange=9 +sfr = "SSC_CR.SWRST", "Memory", 0xfffd4000, 4, base=16, bitRange=15 +sfr = "SSC_CMR", "Memory", 0xfffd4004, 4, base=16 +sfr = "SSC_RCMR", "Memory", 0xfffd4010, 4, base=16 +sfr = "SSC_RCMR.CKS", "Memory", 0xfffd4010, 4, base=16, bitRange=0-1 +sfr = "SSC_RCMR.CKO", "Memory", 0xfffd4010, 4, base=16, bitRange=2-4 +sfr = "SSC_RCMR.CKI", "Memory", 0xfffd4010, 4, base=16, bitRange=5 +sfr = "SSC_RCMR.START", "Memory", 0xfffd4010, 4, base=16, bitRange=8-11 +sfr = "SSC_RCMR.STTDLY", "Memory", 0xfffd4010, 4, base=16, bitRange=16-23 +sfr = "SSC_RCMR.PERIOD", "Memory", 0xfffd4010, 4, base=16, bitRange=24-31 +sfr = "SSC_RFMR", "Memory", 0xfffd4014, 4, base=16 +sfr = "SSC_RFMR.DATLEN", "Memory", 0xfffd4014, 4, base=16, bitRange=0-4 +sfr = "SSC_RFMR.LOOP", "Memory", 0xfffd4014, 4, base=16, bitRange=5 +sfr = "SSC_RFMR.MSBF", "Memory", 0xfffd4014, 4, base=16, bitRange=7 +sfr = "SSC_RFMR.DATNB", "Memory", 0xfffd4014, 4, base=16, bitRange=8-11 +sfr = "SSC_RFMR.FSLEN", "Memory", 0xfffd4014, 4, base=16, bitRange=16-19 +sfr = "SSC_RFMR.FSOS", "Memory", 0xfffd4014, 4, base=16, bitRange=20-22 +sfr = "SSC_RFMR.FSEDGE", "Memory", 0xfffd4014, 4, base=16, bitRange=24 +sfr = "SSC_TCMR", "Memory", 0xfffd4018, 4, base=16 +sfr = "SSC_TCMR.CKS", "Memory", 0xfffd4018, 4, base=16, bitRange=0-1 +sfr = "SSC_TCMR.CKO", "Memory", 0xfffd4018, 4, base=16, bitRange=2-4 +sfr = "SSC_TCMR.CKI", "Memory", 0xfffd4018, 4, base=16, bitRange=5 +sfr = "SSC_TCMR.START", "Memory", 0xfffd4018, 4, base=16, bitRange=8-11 +sfr = "SSC_TCMR.STTDLY", "Memory", 0xfffd4018, 4, base=16, bitRange=16-23 +sfr = "SSC_TCMR.PERIOD", "Memory", 0xfffd4018, 4, base=16, bitRange=24-31 +sfr = "SSC_TFMR", "Memory", 0xfffd401c, 4, base=16 +sfr = "SSC_TFMR.DATLEN", "Memory", 0xfffd401c, 4, base=16, bitRange=0-4 +sfr = "SSC_TFMR.DATDEF", "Memory", 0xfffd401c, 4, base=16, bitRange=5 +sfr = "SSC_TFMR.MSBF", "Memory", 0xfffd401c, 4, base=16, bitRange=7 +sfr = "SSC_TFMR.DATNB", "Memory", 0xfffd401c, 4, base=16, bitRange=8-11 +sfr = "SSC_TFMR.FSLEN", "Memory", 0xfffd401c, 4, base=16, bitRange=16-19 +sfr = "SSC_TFMR.FSOS", "Memory", 0xfffd401c, 4, base=16, bitRange=20-22 +sfr = "SSC_TFMR.FSDEN", "Memory", 0xfffd401c, 4, base=16, bitRange=23 +sfr = "SSC_TFMR.FSEDGE", "Memory", 0xfffd401c, 4, base=16, bitRange=24 +sfr = "SSC_RHR", "Memory", 0xfffd4020, 4, base=16 +sfr = "SSC_THR", "Memory", 0xfffd4024, 4, base=16 +sfr = "SSC_RSHR", "Memory", 0xfffd4030, 4, base=16 +sfr = "SSC_TSHR", "Memory", 0xfffd4034, 4, base=16 +sfr = "SSC_SR", "Memory", 0xfffd4040, 4, base=16 +sfr = "SSC_SR.TXRDY", "Memory", 0xfffd4040, 4, base=16, bitRange=0 +sfr = "SSC_SR.TXEMPTY", "Memory", 0xfffd4040, 4, base=16, bitRange=1 +sfr = "SSC_SR.ENDTX", "Memory", 0xfffd4040, 4, base=16, bitRange=2 +sfr = "SSC_SR.TXBUFE", "Memory", 0xfffd4040, 4, base=16, bitRange=3 +sfr = "SSC_SR.RXRDY", "Memory", 0xfffd4040, 4, base=16, bitRange=4 +sfr = "SSC_SR.OVRUN", "Memory", 0xfffd4040, 4, base=16, bitRange=5 +sfr = "SSC_SR.ENDRX", "Memory", 0xfffd4040, 4, base=16, bitRange=6 +sfr = "SSC_SR.RXBUFF", "Memory", 0xfffd4040, 4, base=16, bitRange=7 +sfr = "SSC_SR.TXSYN", "Memory", 0xfffd4040, 4, base=16, bitRange=10 +sfr = "SSC_SR.RXSYN", "Memory", 0xfffd4040, 4, base=16, bitRange=11 +sfr = "SSC_SR.TXENA", "Memory", 0xfffd4040, 4, base=16, bitRange=16 +sfr = "SSC_SR.RXENA", "Memory", 0xfffd4040, 4, base=16, bitRange=17 +sfr = "SSC_IER", "Memory", 0xfffd4044, 4, base=16 +sfr = "SSC_IER.TXRDY", "Memory", 0xfffd4044, 4, base=16, bitRange=0 +sfr = "SSC_IER.TXEMPTY", "Memory", 0xfffd4044, 4, base=16, bitRange=1 +sfr = "SSC_IER.ENDTX", "Memory", 0xfffd4044, 4, base=16, bitRange=2 +sfr = "SSC_IER.TXBUFE", "Memory", 0xfffd4044, 4, base=16, bitRange=3 +sfr = "SSC_IER.RXRDY", "Memory", 0xfffd4044, 4, base=16, bitRange=4 +sfr = "SSC_IER.OVRUN", "Memory", 0xfffd4044, 4, base=16, bitRange=5 +sfr = "SSC_IER.ENDRX", "Memory", 0xfffd4044, 4, base=16, bitRange=6 +sfr = "SSC_IER.RXBUFF", "Memory", 0xfffd4044, 4, base=16, bitRange=7 +sfr = "SSC_IER.TXSYN", "Memory", 0xfffd4044, 4, base=16, bitRange=10 +sfr = "SSC_IER.RXSYN", "Memory", 0xfffd4044, 4, base=16, bitRange=11 +sfr = "SSC_IDR", "Memory", 0xfffd4048, 4, base=16 +sfr = "SSC_IDR.TXRDY", "Memory", 0xfffd4048, 4, base=16, bitRange=0 +sfr = "SSC_IDR.TXEMPTY", "Memory", 0xfffd4048, 4, base=16, bitRange=1 +sfr = "SSC_IDR.ENDTX", "Memory", 0xfffd4048, 4, base=16, bitRange=2 +sfr = "SSC_IDR.TXBUFE", "Memory", 0xfffd4048, 4, base=16, bitRange=3 +sfr = "SSC_IDR.RXRDY", "Memory", 0xfffd4048, 4, base=16, bitRange=4 +sfr = "SSC_IDR.OVRUN", "Memory", 0xfffd4048, 4, base=16, bitRange=5 +sfr = "SSC_IDR.ENDRX", "Memory", 0xfffd4048, 4, base=16, bitRange=6 +sfr = "SSC_IDR.RXBUFF", "Memory", 0xfffd4048, 4, base=16, bitRange=7 +sfr = "SSC_IDR.TXSYN", "Memory", 0xfffd4048, 4, base=16, bitRange=10 +sfr = "SSC_IDR.RXSYN", "Memory", 0xfffd4048, 4, base=16, bitRange=11 +sfr = "SSC_IMR", "Memory", 0xfffd404c, 4, base=16 +sfr = "SSC_IMR.TXRDY", "Memory", 0xfffd404c, 4, base=16, bitRange=0 +sfr = "SSC_IMR.TXEMPTY", "Memory", 0xfffd404c, 4, base=16, bitRange=1 +sfr = "SSC_IMR.ENDTX", "Memory", 0xfffd404c, 4, base=16, bitRange=2 +sfr = "SSC_IMR.TXBUFE", "Memory", 0xfffd404c, 4, base=16, bitRange=3 +sfr = "SSC_IMR.RXRDY", "Memory", 0xfffd404c, 4, base=16, bitRange=4 +sfr = "SSC_IMR.OVRUN", "Memory", 0xfffd404c, 4, base=16, bitRange=5 +sfr = "SSC_IMR.ENDRX", "Memory", 0xfffd404c, 4, base=16, bitRange=6 +sfr = "SSC_IMR.RXBUFF", "Memory", 0xfffd404c, 4, base=16, bitRange=7 +sfr = "SSC_IMR.TXSYN", "Memory", 0xfffd404c, 4, base=16, bitRange=10 +sfr = "SSC_IMR.RXSYN", "Memory", 0xfffd404c, 4, base=16, bitRange=11 +; ========== Register definition for PDC_US1 peripheral ========== +sfr = "US1_RPR", "Memory", 0xfffc4100, 4, base=16 +sfr = "US1_RCR", "Memory", 0xfffc4104, 4, base=16 +sfr = "US1_TPR", "Memory", 0xfffc4108, 4, base=16 +sfr = "US1_TCR", "Memory", 0xfffc410c, 4, base=16 +sfr = "US1_RNPR", "Memory", 0xfffc4110, 4, base=16 +sfr = "US1_RNCR", "Memory", 0xfffc4114, 4, base=16 +sfr = "US1_TNPR", "Memory", 0xfffc4118, 4, base=16 +sfr = "US1_TNCR", "Memory", 0xfffc411c, 4, base=16 +sfr = "US1_PTCR", "Memory", 0xfffc4120, 4, base=16 +sfr = "US1_PTCR.RXTEN", "Memory", 0xfffc4120, 4, base=16, bitRange=0 +sfr = "US1_PTCR.RXTDIS", "Memory", 0xfffc4120, 4, base=16, bitRange=1 +sfr = "US1_PTCR.TXTEN", "Memory", 0xfffc4120, 4, base=16, bitRange=8 +sfr = "US1_PTCR.TXTDIS", "Memory", 0xfffc4120, 4, base=16, bitRange=9 +sfr = "US1_PTSR", "Memory", 0xfffc4124, 4, base=16 +sfr = "US1_PTSR.RXTEN", "Memory", 0xfffc4124, 4, base=16, bitRange=0 +sfr = "US1_PTSR.TXTEN", "Memory", 0xfffc4124, 4, base=16, bitRange=8 +; ========== Register definition for US1 peripheral ========== +sfr = "US1_CR", "Memory", 0xfffc4000, 4, base=16 +sfr = "US1_CR.RSTRX", "Memory", 0xfffc4000, 4, base=16, bitRange=2 +sfr = "US1_CR.RSTTX", "Memory", 0xfffc4000, 4, base=16, bitRange=3 +sfr = "US1_CR.RXEN", "Memory", 0xfffc4000, 4, base=16, bitRange=4 +sfr = "US1_CR.RXDIS", "Memory", 0xfffc4000, 4, base=16, bitRange=5 +sfr = "US1_CR.TXEN", "Memory", 0xfffc4000, 4, base=16, bitRange=6 +sfr = "US1_CR.TXDIS", "Memory", 0xfffc4000, 4, base=16, bitRange=7 +sfr = "US1_CR.RSTSTA", "Memory", 0xfffc4000, 4, base=16, bitRange=8 +sfr = "US1_CR.STTBRK", "Memory", 0xfffc4000, 4, base=16, bitRange=9 +sfr = "US1_CR.STPBRK", "Memory", 0xfffc4000, 4, base=16, bitRange=10 +sfr = "US1_CR.STTTO", "Memory", 0xfffc4000, 4, base=16, bitRange=11 +sfr = "US1_CR.SENDA", "Memory", 0xfffc4000, 4, base=16, bitRange=12 +sfr = "US1_CR.RSTIT", "Memory", 0xfffc4000, 4, base=16, bitRange=13 +sfr = "US1_CR.RSTNACK", "Memory", 0xfffc4000, 4, base=16, bitRange=14 +sfr = "US1_CR.RETTO", "Memory", 0xfffc4000, 4, base=16, bitRange=15 +sfr = "US1_CR.DTREN", "Memory", 0xfffc4000, 4, base=16, bitRange=16 +sfr = "US1_CR.DTRDIS", "Memory", 0xfffc4000, 4, base=16, bitRange=17 +sfr = "US1_CR.RTSEN", "Memory", 0xfffc4000, 4, base=16, bitRange=18 +sfr = "US1_CR.RTSDIS", "Memory", 0xfffc4000, 4, base=16, bitRange=19 +sfr = "US1_MR", "Memory", 0xfffc4004, 4, base=16 +sfr = "US1_MR.USMODE", "Memory", 0xfffc4004, 4, base=16, bitRange=0-3 +sfr = "US1_MR.CLKS", "Memory", 0xfffc4004, 4, base=16, bitRange=4-5 +sfr = "US1_MR.CHRL", "Memory", 0xfffc4004, 4, base=16, bitRange=6-7 +sfr = "US1_MR.SYNC", "Memory", 0xfffc4004, 4, base=16, bitRange=8 +sfr = "US1_MR.PAR", "Memory", 0xfffc4004, 4, base=16, bitRange=9-11 +sfr = "US1_MR.NBSTOP", "Memory", 0xfffc4004, 4, base=16, bitRange=12-13 +sfr = "US1_MR.CHMODE", "Memory", 0xfffc4004, 4, base=16, bitRange=14-15 +sfr = "US1_MR.MSBF", "Memory", 0xfffc4004, 4, base=16, bitRange=16 +sfr = "US1_MR.MODE9", "Memory", 0xfffc4004, 4, base=16, bitRange=17 +sfr = "US1_MR.CKLO", "Memory", 0xfffc4004, 4, base=16, bitRange=18 +sfr = "US1_MR.OVER", "Memory", 0xfffc4004, 4, base=16, bitRange=19 +sfr = "US1_MR.INACK", "Memory", 0xfffc4004, 4, base=16, bitRange=20 +sfr = "US1_MR.DSNACK", "Memory", 0xfffc4004, 4, base=16, bitRange=21 +sfr = "US1_MR.ITER", "Memory", 0xfffc4004, 4, base=16, bitRange=24 +sfr = "US1_MR.FILTER", "Memory", 0xfffc4004, 4, base=16, bitRange=28 +sfr = "US1_IER", "Memory", 0xfffc4008, 4, base=16 +sfr = "US1_IER.RXRDY", "Memory", 0xfffc4008, 4, base=16, bitRange=0 +sfr = "US1_IER.TXRDY", "Memory", 0xfffc4008, 4, base=16, bitRange=1 +sfr = "US1_IER.RXBRK", "Memory", 0xfffc4008, 4, base=16, bitRange=2 +sfr = "US1_IER.ENDRX", "Memory", 0xfffc4008, 4, base=16, bitRange=3 +sfr = "US1_IER.ENDTX", "Memory", 0xfffc4008, 4, base=16, bitRange=4 +sfr = "US1_IER.OVRE", "Memory", 0xfffc4008, 4, base=16, bitRange=5 +sfr = "US1_IER.FRAME", "Memory", 0xfffc4008, 4, base=16, bitRange=6 +sfr = "US1_IER.PARE", "Memory", 0xfffc4008, 4, base=16, bitRange=7 +sfr = "US1_IER.TIMEOUT", "Memory", 0xfffc4008, 4, base=16, bitRange=8 +sfr = "US1_IER.TXEMPTY", "Memory", 0xfffc4008, 4, base=16, bitRange=9 +sfr = "US1_IER.ITERATION", "Memory", 0xfffc4008, 4, base=16, bitRange=10 +sfr = "US1_IER.TXBUFE", "Memory", 0xfffc4008, 4, base=16, bitRange=11 +sfr = "US1_IER.RXBUFF", "Memory", 0xfffc4008, 4, base=16, bitRange=12 +sfr = "US1_IER.NACK", "Memory", 0xfffc4008, 4, base=16, bitRange=13 +sfr = "US1_IER.RIIC", "Memory", 0xfffc4008, 4, base=16, bitRange=16 +sfr = "US1_IER.DSRIC", "Memory", 0xfffc4008, 4, base=16, bitRange=17 +sfr = "US1_IER.DCDIC", "Memory", 0xfffc4008, 4, base=16, bitRange=18 +sfr = "US1_IER.CTSIC", "Memory", 0xfffc4008, 4, base=16, bitRange=19 +sfr = "US1_IDR", "Memory", 0xfffc400c, 4, base=16 +sfr = "US1_IDR.RXRDY", "Memory", 0xfffc400c, 4, base=16, bitRange=0 +sfr = "US1_IDR.TXRDY", "Memory", 0xfffc400c, 4, base=16, bitRange=1 +sfr = "US1_IDR.RXBRK", "Memory", 0xfffc400c, 4, base=16, bitRange=2 +sfr = "US1_IDR.ENDRX", "Memory", 0xfffc400c, 4, base=16, bitRange=3 +sfr = "US1_IDR.ENDTX", "Memory", 0xfffc400c, 4, base=16, bitRange=4 +sfr = "US1_IDR.OVRE", "Memory", 0xfffc400c, 4, base=16, bitRange=5 +sfr = "US1_IDR.FRAME", "Memory", 0xfffc400c, 4, base=16, bitRange=6 +sfr = "US1_IDR.PARE", "Memory", 0xfffc400c, 4, base=16, bitRange=7 +sfr = "US1_IDR.TIMEOUT", "Memory", 0xfffc400c, 4, base=16, bitRange=8 +sfr = "US1_IDR.TXEMPTY", "Memory", 0xfffc400c, 4, base=16, bitRange=9 +sfr = "US1_IDR.ITERATION", "Memory", 0xfffc400c, 4, base=16, bitRange=10 +sfr = "US1_IDR.TXBUFE", "Memory", 0xfffc400c, 4, base=16, bitRange=11 +sfr = "US1_IDR.RXBUFF", "Memory", 0xfffc400c, 4, base=16, bitRange=12 +sfr = "US1_IDR.NACK", "Memory", 0xfffc400c, 4, base=16, bitRange=13 +sfr = "US1_IDR.RIIC", "Memory", 0xfffc400c, 4, base=16, bitRange=16 +sfr = "US1_IDR.DSRIC", "Memory", 0xfffc400c, 4, base=16, bitRange=17 +sfr = "US1_IDR.DCDIC", "Memory", 0xfffc400c, 4, base=16, bitRange=18 +sfr = "US1_IDR.CTSIC", "Memory", 0xfffc400c, 4, base=16, bitRange=19 +sfr = "US1_IMR", "Memory", 0xfffc4010, 4, base=16 +sfr = "US1_IMR.RXRDY", "Memory", 0xfffc4010, 4, base=16, bitRange=0 +sfr = "US1_IMR.TXRDY", "Memory", 0xfffc4010, 4, base=16, bitRange=1 +sfr = "US1_IMR.RXBRK", "Memory", 0xfffc4010, 4, base=16, bitRange=2 +sfr = "US1_IMR.ENDRX", "Memory", 0xfffc4010, 4, base=16, bitRange=3 +sfr = "US1_IMR.ENDTX", "Memory", 0xfffc4010, 4, base=16, bitRange=4 +sfr = "US1_IMR.OVRE", "Memory", 0xfffc4010, 4, base=16, bitRange=5 +sfr = "US1_IMR.FRAME", "Memory", 0xfffc4010, 4, base=16, bitRange=6 +sfr = "US1_IMR.PARE", "Memory", 0xfffc4010, 4, base=16, bitRange=7 +sfr = "US1_IMR.TIMEOUT", "Memory", 0xfffc4010, 4, base=16, bitRange=8 +sfr = "US1_IMR.TXEMPTY", "Memory", 0xfffc4010, 4, base=16, bitRange=9 +sfr = "US1_IMR.ITERATION", "Memory", 0xfffc4010, 4, base=16, bitRange=10 +sfr = "US1_IMR.TXBUFE", "Memory", 0xfffc4010, 4, base=16, bitRange=11 +sfr = "US1_IMR.RXBUFF", "Memory", 0xfffc4010, 4, base=16, bitRange=12 +sfr = "US1_IMR.NACK", "Memory", 0xfffc4010, 4, base=16, bitRange=13 +sfr = "US1_IMR.RIIC", "Memory", 0xfffc4010, 4, base=16, bitRange=16 +sfr = "US1_IMR.DSRIC", "Memory", 0xfffc4010, 4, base=16, bitRange=17 +sfr = "US1_IMR.DCDIC", "Memory", 0xfffc4010, 4, base=16, bitRange=18 +sfr = "US1_IMR.CTSIC", "Memory", 0xfffc4010, 4, base=16, bitRange=19 +sfr = "US1_CSR", "Memory", 0xfffc4014, 4, base=16 +sfr = "US1_CSR.RXRDY", "Memory", 0xfffc4014, 4, base=16, bitRange=0 +sfr = "US1_CSR.TXRDY", "Memory", 0xfffc4014, 4, base=16, bitRange=1 +sfr = "US1_CSR.RXBRK", "Memory", 0xfffc4014, 4, base=16, bitRange=2 +sfr = "US1_CSR.ENDRX", "Memory", 0xfffc4014, 4, base=16, bitRange=3 +sfr = "US1_CSR.ENDTX", "Memory", 0xfffc4014, 4, base=16, bitRange=4 +sfr = "US1_CSR.OVRE", "Memory", 0xfffc4014, 4, base=16, bitRange=5 +sfr = "US1_CSR.FRAME", "Memory", 0xfffc4014, 4, base=16, bitRange=6 +sfr = "US1_CSR.PARE", "Memory", 0xfffc4014, 4, base=16, bitRange=7 +sfr = "US1_CSR.TIMEOUT", "Memory", 0xfffc4014, 4, base=16, bitRange=8 +sfr = "US1_CSR.TXEMPTY", "Memory", 0xfffc4014, 4, base=16, bitRange=9 +sfr = "US1_CSR.ITERATION", "Memory", 0xfffc4014, 4, base=16, bitRange=10 +sfr = "US1_CSR.TXBUFE", "Memory", 0xfffc4014, 4, base=16, bitRange=11 +sfr = "US1_CSR.RXBUFF", "Memory", 0xfffc4014, 4, base=16, bitRange=12 +sfr = "US1_CSR.NACK", "Memory", 0xfffc4014, 4, base=16, bitRange=13 +sfr = "US1_CSR.RIIC", "Memory", 0xfffc4014, 4, base=16, bitRange=16 +sfr = "US1_CSR.DSRIC", "Memory", 0xfffc4014, 4, base=16, bitRange=17 +sfr = "US1_CSR.DCDIC", "Memory", 0xfffc4014, 4, base=16, bitRange=18 +sfr = "US1_CSR.CTSIC", "Memory", 0xfffc4014, 4, base=16, bitRange=19 +sfr = "US1_CSR.RI", "Memory", 0xfffc4014, 4, base=16, bitRange=20 +sfr = "US1_CSR.DSR", "Memory", 0xfffc4014, 4, base=16, bitRange=21 +sfr = "US1_CSR.DCD", "Memory", 0xfffc4014, 4, base=16, bitRange=22 +sfr = "US1_CSR.CTS", "Memory", 0xfffc4014, 4, base=16, bitRange=23 +sfr = "US1_RHR", "Memory", 0xfffc4018, 4, base=16 +sfr = "US1_THR", "Memory", 0xfffc401c, 4, base=16 +sfr = "US1_BRGR", "Memory", 0xfffc4020, 4, base=16 +sfr = "US1_RTOR", "Memory", 0xfffc4024, 4, base=16 +sfr = "US1_TTGR", "Memory", 0xfffc4028, 4, base=16 +sfr = "US1_FIDI", "Memory", 0xfffc4040, 4, base=16 +sfr = "US1_NER", "Memory", 0xfffc4044, 4, base=16 +sfr = "US1_IF", "Memory", 0xfffc404c, 4, base=16 +; ========== Register definition for PDC_US0 peripheral ========== +sfr = "US0_RPR", "Memory", 0xfffc0100, 4, base=16 +sfr = "US0_RCR", "Memory", 0xfffc0104, 4, base=16 +sfr = "US0_TPR", "Memory", 0xfffc0108, 4, base=16 +sfr = "US0_TCR", "Memory", 0xfffc010c, 4, base=16 +sfr = "US0_RNPR", "Memory", 0xfffc0110, 4, base=16 +sfr = "US0_RNCR", "Memory", 0xfffc0114, 4, base=16 +sfr = "US0_TNPR", "Memory", 0xfffc0118, 4, base=16 +sfr = "US0_TNCR", "Memory", 0xfffc011c, 4, base=16 +sfr = "US0_PTCR", "Memory", 0xfffc0120, 4, base=16 +sfr = "US0_PTCR.RXTEN", "Memory", 0xfffc0120, 4, base=16, bitRange=0 +sfr = "US0_PTCR.RXTDIS", "Memory", 0xfffc0120, 4, base=16, bitRange=1 +sfr = "US0_PTCR.TXTEN", "Memory", 0xfffc0120, 4, base=16, bitRange=8 +sfr = "US0_PTCR.TXTDIS", "Memory", 0xfffc0120, 4, base=16, bitRange=9 +sfr = "US0_PTSR", "Memory", 0xfffc0124, 4, base=16 +sfr = "US0_PTSR.RXTEN", "Memory", 0xfffc0124, 4, base=16, bitRange=0 +sfr = "US0_PTSR.TXTEN", "Memory", 0xfffc0124, 4, base=16, bitRange=8 +; ========== Register definition for US0 peripheral ========== +sfr = "US0_CR", "Memory", 0xfffc0000, 4, base=16 +sfr = "US0_CR.RSTRX", "Memory", 0xfffc0000, 4, base=16, bitRange=2 +sfr = "US0_CR.RSTTX", "Memory", 0xfffc0000, 4, base=16, bitRange=3 +sfr = "US0_CR.RXEN", "Memory", 0xfffc0000, 4, base=16, bitRange=4 +sfr = "US0_CR.RXDIS", "Memory", 0xfffc0000, 4, base=16, bitRange=5 +sfr = "US0_CR.TXEN", "Memory", 0xfffc0000, 4, base=16, bitRange=6 +sfr = "US0_CR.TXDIS", "Memory", 0xfffc0000, 4, base=16, bitRange=7 +sfr = "US0_CR.RSTSTA", "Memory", 0xfffc0000, 4, base=16, bitRange=8 +sfr = "US0_CR.STTBRK", "Memory", 0xfffc0000, 4, base=16, bitRange=9 +sfr = "US0_CR.STPBRK", "Memory", 0xfffc0000, 4, base=16, bitRange=10 +sfr = "US0_CR.STTTO", "Memory", 0xfffc0000, 4, base=16, bitRange=11 +sfr = "US0_CR.SENDA", "Memory", 0xfffc0000, 4, base=16, bitRange=12 +sfr = "US0_CR.RSTIT", "Memory", 0xfffc0000, 4, base=16, bitRange=13 +sfr = "US0_CR.RSTNACK", "Memory", 0xfffc0000, 4, base=16, bitRange=14 +sfr = "US0_CR.RETTO", "Memory", 0xfffc0000, 4, base=16, bitRange=15 +sfr = "US0_CR.DTREN", "Memory", 0xfffc0000, 4, base=16, bitRange=16 +sfr = "US0_CR.DTRDIS", "Memory", 0xfffc0000, 4, base=16, bitRange=17 +sfr = "US0_CR.RTSEN", "Memory", 0xfffc0000, 4, base=16, bitRange=18 +sfr = "US0_CR.RTSDIS", "Memory", 0xfffc0000, 4, base=16, bitRange=19 +sfr = "US0_MR", "Memory", 0xfffc0004, 4, base=16 +sfr = "US0_MR.USMODE", "Memory", 0xfffc0004, 4, base=16, bitRange=0-3 +sfr = "US0_MR.CLKS", "Memory", 0xfffc0004, 4, base=16, bitRange=4-5 +sfr = "US0_MR.CHRL", "Memory", 0xfffc0004, 4, base=16, bitRange=6-7 +sfr = "US0_MR.SYNC", "Memory", 0xfffc0004, 4, base=16, bitRange=8 +sfr = "US0_MR.PAR", "Memory", 0xfffc0004, 4, base=16, bitRange=9-11 +sfr = "US0_MR.NBSTOP", "Memory", 0xfffc0004, 4, base=16, bitRange=12-13 +sfr = "US0_MR.CHMODE", "Memory", 0xfffc0004, 4, base=16, bitRange=14-15 +sfr = "US0_MR.MSBF", "Memory", 0xfffc0004, 4, base=16, bitRange=16 +sfr = "US0_MR.MODE9", "Memory", 0xfffc0004, 4, base=16, bitRange=17 +sfr = "US0_MR.CKLO", "Memory", 0xfffc0004, 4, base=16, bitRange=18 +sfr = "US0_MR.OVER", "Memory", 0xfffc0004, 4, base=16, bitRange=19 +sfr = "US0_MR.INACK", "Memory", 0xfffc0004, 4, base=16, bitRange=20 +sfr = "US0_MR.DSNACK", "Memory", 0xfffc0004, 4, base=16, bitRange=21 +sfr = "US0_MR.ITER", "Memory", 0xfffc0004, 4, base=16, bitRange=24 +sfr = "US0_MR.FILTER", "Memory", 0xfffc0004, 4, base=16, bitRange=28 +sfr = "US0_IER", "Memory", 0xfffc0008, 4, base=16 +sfr = "US0_IER.RXRDY", "Memory", 0xfffc0008, 4, base=16, bitRange=0 +sfr = "US0_IER.TXRDY", "Memory", 0xfffc0008, 4, base=16, bitRange=1 +sfr = "US0_IER.RXBRK", "Memory", 0xfffc0008, 4, base=16, bitRange=2 +sfr = "US0_IER.ENDRX", "Memory", 0xfffc0008, 4, base=16, bitRange=3 +sfr = "US0_IER.ENDTX", "Memory", 0xfffc0008, 4, base=16, bitRange=4 +sfr = "US0_IER.OVRE", "Memory", 0xfffc0008, 4, base=16, bitRange=5 +sfr = "US0_IER.FRAME", "Memory", 0xfffc0008, 4, base=16, bitRange=6 +sfr = "US0_IER.PARE", "Memory", 0xfffc0008, 4, base=16, bitRange=7 +sfr = "US0_IER.TIMEOUT", "Memory", 0xfffc0008, 4, base=16, bitRange=8 +sfr = "US0_IER.TXEMPTY", "Memory", 0xfffc0008, 4, base=16, bitRange=9 +sfr = "US0_IER.ITERATION", "Memory", 0xfffc0008, 4, base=16, bitRange=10 +sfr = "US0_IER.TXBUFE", "Memory", 0xfffc0008, 4, base=16, bitRange=11 +sfr = "US0_IER.RXBUFF", "Memory", 0xfffc0008, 4, base=16, bitRange=12 +sfr = "US0_IER.NACK", "Memory", 0xfffc0008, 4, base=16, bitRange=13 +sfr = "US0_IER.RIIC", "Memory", 0xfffc0008, 4, base=16, bitRange=16 +sfr = "US0_IER.DSRIC", "Memory", 0xfffc0008, 4, base=16, bitRange=17 +sfr = "US0_IER.DCDIC", "Memory", 0xfffc0008, 4, base=16, bitRange=18 +sfr = "US0_IER.CTSIC", "Memory", 0xfffc0008, 4, base=16, bitRange=19 +sfr = "US0_IDR", "Memory", 0xfffc000c, 4, base=16 +sfr = "US0_IDR.RXRDY", "Memory", 0xfffc000c, 4, base=16, bitRange=0 +sfr = "US0_IDR.TXRDY", "Memory", 0xfffc000c, 4, base=16, bitRange=1 +sfr = "US0_IDR.RXBRK", "Memory", 0xfffc000c, 4, base=16, bitRange=2 +sfr = "US0_IDR.ENDRX", "Memory", 0xfffc000c, 4, base=16, bitRange=3 +sfr = "US0_IDR.ENDTX", "Memory", 0xfffc000c, 4, base=16, bitRange=4 +sfr = "US0_IDR.OVRE", "Memory", 0xfffc000c, 4, base=16, bitRange=5 +sfr = "US0_IDR.FRAME", "Memory", 0xfffc000c, 4, base=16, bitRange=6 +sfr = "US0_IDR.PARE", "Memory", 0xfffc000c, 4, base=16, bitRange=7 +sfr = "US0_IDR.TIMEOUT", "Memory", 0xfffc000c, 4, base=16, bitRange=8 +sfr = "US0_IDR.TXEMPTY", "Memory", 0xfffc000c, 4, base=16, bitRange=9 +sfr = "US0_IDR.ITERATION", "Memory", 0xfffc000c, 4, base=16, bitRange=10 +sfr = "US0_IDR.TXBUFE", "Memory", 0xfffc000c, 4, base=16, bitRange=11 +sfr = "US0_IDR.RXBUFF", "Memory", 0xfffc000c, 4, base=16, bitRange=12 +sfr = "US0_IDR.NACK", "Memory", 0xfffc000c, 4, base=16, bitRange=13 +sfr = "US0_IDR.RIIC", "Memory", 0xfffc000c, 4, base=16, bitRange=16 +sfr = "US0_IDR.DSRIC", "Memory", 0xfffc000c, 4, base=16, bitRange=17 +sfr = "US0_IDR.DCDIC", "Memory", 0xfffc000c, 4, base=16, bitRange=18 +sfr = "US0_IDR.CTSIC", "Memory", 0xfffc000c, 4, base=16, bitRange=19 +sfr = "US0_IMR", "Memory", 0xfffc0010, 4, base=16 +sfr = "US0_IMR.RXRDY", "Memory", 0xfffc0010, 4, base=16, bitRange=0 +sfr = "US0_IMR.TXRDY", "Memory", 0xfffc0010, 4, base=16, bitRange=1 +sfr = "US0_IMR.RXBRK", "Memory", 0xfffc0010, 4, base=16, bitRange=2 +sfr = "US0_IMR.ENDRX", "Memory", 0xfffc0010, 4, base=16, bitRange=3 +sfr = "US0_IMR.ENDTX", "Memory", 0xfffc0010, 4, base=16, bitRange=4 +sfr = "US0_IMR.OVRE", "Memory", 0xfffc0010, 4, base=16, bitRange=5 +sfr = "US0_IMR.FRAME", "Memory", 0xfffc0010, 4, base=16, bitRange=6 +sfr = "US0_IMR.PARE", "Memory", 0xfffc0010, 4, base=16, bitRange=7 +sfr = "US0_IMR.TIMEOUT", "Memory", 0xfffc0010, 4, base=16, bitRange=8 +sfr = "US0_IMR.TXEMPTY", "Memory", 0xfffc0010, 4, base=16, bitRange=9 +sfr = "US0_IMR.ITERATION", "Memory", 0xfffc0010, 4, base=16, bitRange=10 +sfr = "US0_IMR.TXBUFE", "Memory", 0xfffc0010, 4, base=16, bitRange=11 +sfr = "US0_IMR.RXBUFF", "Memory", 0xfffc0010, 4, base=16, bitRange=12 +sfr = "US0_IMR.NACK", "Memory", 0xfffc0010, 4, base=16, bitRange=13 +sfr = "US0_IMR.RIIC", "Memory", 0xfffc0010, 4, base=16, bitRange=16 +sfr = "US0_IMR.DSRIC", "Memory", 0xfffc0010, 4, base=16, bitRange=17 +sfr = "US0_IMR.DCDIC", "Memory", 0xfffc0010, 4, base=16, bitRange=18 +sfr = "US0_IMR.CTSIC", "Memory", 0xfffc0010, 4, base=16, bitRange=19 +sfr = "US0_CSR", "Memory", 0xfffc0014, 4, base=16 +sfr = "US0_CSR.RXRDY", "Memory", 0xfffc0014, 4, base=16, bitRange=0 +sfr = "US0_CSR.TXRDY", "Memory", 0xfffc0014, 4, base=16, bitRange=1 +sfr = "US0_CSR.RXBRK", "Memory", 0xfffc0014, 4, base=16, bitRange=2 +sfr = "US0_CSR.ENDRX", "Memory", 0xfffc0014, 4, base=16, bitRange=3 +sfr = "US0_CSR.ENDTX", "Memory", 0xfffc0014, 4, base=16, bitRange=4 +sfr = "US0_CSR.OVRE", "Memory", 0xfffc0014, 4, base=16, bitRange=5 +sfr = "US0_CSR.FRAME", "Memory", 0xfffc0014, 4, base=16, bitRange=6 +sfr = "US0_CSR.PARE", "Memory", 0xfffc0014, 4, base=16, bitRange=7 +sfr = "US0_CSR.TIMEOUT", "Memory", 0xfffc0014, 4, base=16, bitRange=8 +sfr = "US0_CSR.TXEMPTY", "Memory", 0xfffc0014, 4, base=16, bitRange=9 +sfr = "US0_CSR.ITERATION", "Memory", 0xfffc0014, 4, base=16, bitRange=10 +sfr = "US0_CSR.TXBUFE", "Memory", 0xfffc0014, 4, base=16, bitRange=11 +sfr = "US0_CSR.RXBUFF", "Memory", 0xfffc0014, 4, base=16, bitRange=12 +sfr = "US0_CSR.NACK", "Memory", 0xfffc0014, 4, base=16, bitRange=13 +sfr = "US0_CSR.RIIC", "Memory", 0xfffc0014, 4, base=16, bitRange=16 +sfr = "US0_CSR.DSRIC", "Memory", 0xfffc0014, 4, base=16, bitRange=17 +sfr = "US0_CSR.DCDIC", "Memory", 0xfffc0014, 4, base=16, bitRange=18 +sfr = "US0_CSR.CTSIC", "Memory", 0xfffc0014, 4, base=16, bitRange=19 +sfr = "US0_CSR.RI", "Memory", 0xfffc0014, 4, base=16, bitRange=20 +sfr = "US0_CSR.DSR", "Memory", 0xfffc0014, 4, base=16, bitRange=21 +sfr = "US0_CSR.DCD", "Memory", 0xfffc0014, 4, base=16, bitRange=22 +sfr = "US0_CSR.CTS", "Memory", 0xfffc0014, 4, base=16, bitRange=23 +sfr = "US0_RHR", "Memory", 0xfffc0018, 4, base=16 +sfr = "US0_THR", "Memory", 0xfffc001c, 4, base=16 +sfr = "US0_BRGR", "Memory", 0xfffc0020, 4, base=16 +sfr = "US0_RTOR", "Memory", 0xfffc0024, 4, base=16 +sfr = "US0_TTGR", "Memory", 0xfffc0028, 4, base=16 +sfr = "US0_FIDI", "Memory", 0xfffc0040, 4, base=16 +sfr = "US0_NER", "Memory", 0xfffc0044, 4, base=16 +sfr = "US0_IF", "Memory", 0xfffc004c, 4, base=16 +; ========== Register definition for TWI peripheral ========== +sfr = "TWI_CR", "Memory", 0xfffb8000, 4, base=16 +sfr = "TWI_CR.START", "Memory", 0xfffb8000, 4, base=16, bitRange=0 +sfr = "TWI_CR.STOP", "Memory", 0xfffb8000, 4, base=16, bitRange=1 +sfr = "TWI_CR.MSEN", "Memory", 0xfffb8000, 4, base=16, bitRange=2 +sfr = "TWI_CR.MSDIS", "Memory", 0xfffb8000, 4, base=16, bitRange=3 +sfr = "TWI_CR.SWRST", "Memory", 0xfffb8000, 4, base=16, bitRange=7 +sfr = "TWI_MMR", "Memory", 0xfffb8004, 4, base=16 +sfr = "TWI_MMR.IADRSZ", "Memory", 0xfffb8004, 4, base=16, bitRange=8-9 +sfr = "TWI_MMR.MREAD", "Memory", 0xfffb8004, 4, base=16, bitRange=12 +sfr = "TWI_MMR.DADR", "Memory", 0xfffb8004, 4, base=16, bitRange=16-22 +sfr = "TWI_IADR", "Memory", 0xfffb800c, 4, base=16 +sfr = "TWI_CWGR", "Memory", 0xfffb8010, 4, base=16 +sfr = "TWI_CWGR.CLDIV", "Memory", 0xfffb8010, 4, base=16, bitRange=0-7 +sfr = "TWI_CWGR.CHDIV", "Memory", 0xfffb8010, 4, base=16, bitRange=8-15 +sfr = "TWI_CWGR.CKDIV", "Memory", 0xfffb8010, 4, base=16, bitRange=16-18 +sfr = "TWI_SR", "Memory", 0xfffb8020, 4, base=16 +sfr = "TWI_SR.TXCOMP", "Memory", 0xfffb8020, 4, base=16, bitRange=0 +sfr = "TWI_SR.RXRDY", "Memory", 0xfffb8020, 4, base=16, bitRange=1 +sfr = "TWI_SR.TXRDY", "Memory", 0xfffb8020, 4, base=16, bitRange=2 +sfr = "TWI_SR.OVRE", "Memory", 0xfffb8020, 4, base=16, bitRange=6 +sfr = "TWI_SR.UNRE", "Memory", 0xfffb8020, 4, base=16, bitRange=7 +sfr = "TWI_SR.NACK", "Memory", 0xfffb8020, 4, base=16, bitRange=8 +sfr = "TWI_IER", "Memory", 0xfffb8024, 4, base=16 +sfr = "TWI_IER.TXCOMP", "Memory", 0xfffb8024, 4, base=16, bitRange=0 +sfr = "TWI_IER.RXRDY", "Memory", 0xfffb8024, 4, base=16, bitRange=1 +sfr = "TWI_IER.TXRDY", "Memory", 0xfffb8024, 4, base=16, bitRange=2 +sfr = "TWI_IER.OVRE", "Memory", 0xfffb8024, 4, base=16, bitRange=6 +sfr = "TWI_IER.UNRE", "Memory", 0xfffb8024, 4, base=16, bitRange=7 +sfr = "TWI_IER.NACK", "Memory", 0xfffb8024, 4, base=16, bitRange=8 +sfr = "TWI_IDR", "Memory", 0xfffb8028, 4, base=16 +sfr = "TWI_IDR.TXCOMP", "Memory", 0xfffb8028, 4, base=16, bitRange=0 +sfr = "TWI_IDR.RXRDY", "Memory", 0xfffb8028, 4, base=16, bitRange=1 +sfr = "TWI_IDR.TXRDY", "Memory", 0xfffb8028, 4, base=16, bitRange=2 +sfr = "TWI_IDR.OVRE", "Memory", 0xfffb8028, 4, base=16, bitRange=6 +sfr = "TWI_IDR.UNRE", "Memory", 0xfffb8028, 4, base=16, bitRange=7 +sfr = "TWI_IDR.NACK", "Memory", 0xfffb8028, 4, base=16, bitRange=8 +sfr = "TWI_IMR", "Memory", 0xfffb802c, 4, base=16 +sfr = "TWI_IMR.TXCOMP", "Memory", 0xfffb802c, 4, base=16, bitRange=0 +sfr = "TWI_IMR.RXRDY", "Memory", 0xfffb802c, 4, base=16, bitRange=1 +sfr = "TWI_IMR.TXRDY", "Memory", 0xfffb802c, 4, base=16, bitRange=2 +sfr = "TWI_IMR.OVRE", "Memory", 0xfffb802c, 4, base=16, bitRange=6 +sfr = "TWI_IMR.UNRE", "Memory", 0xfffb802c, 4, base=16, bitRange=7 +sfr = "TWI_IMR.NACK", "Memory", 0xfffb802c, 4, base=16, bitRange=8 +sfr = "TWI_RHR", "Memory", 0xfffb8030, 4, base=16 +sfr = "TWI_THR", "Memory", 0xfffb8034, 4, base=16 +; ========== Register definition for TC0 peripheral ========== +sfr = "TC0_CCR", "Memory", 0xfffa0000, 4, base=16 +sfr = "TC0_CCR.CLKEN", "Memory", 0xfffa0000, 4, base=16, bitRange=0 +sfr = "TC0_CCR.CLKDIS", "Memory", 0xfffa0000, 4, base=16, bitRange=1 +sfr = "TC0_CCR.SWTRG", "Memory", 0xfffa0000, 4, base=16, bitRange=2 +sfr = "TC0_CMR", "Memory", 0xfffa0004, 4, base=16 +sfr = "TC0_CMR.CLKS", "Memory", 0xfffa0004, 4, base=16, bitRange=0-2 +sfr = "TC0_CMR.CLKI", "Memory", 0xfffa0004, 4, base=16, bitRange=3 +sfr = "TC0_CMR.BURST", "Memory", 0xfffa0004, 4, base=16, bitRange=4-5 +sfr = "TC0_CMR.CPCSTOP", "Memory", 0xfffa0004, 4, base=16, bitRange=6 +sfr = "TC0_CMR.LDBSTOP", "Memory", 0xfffa0004, 4, base=16, bitRange=6 +sfr = "TC0_CMR.CPCDIS", "Memory", 0xfffa0004, 4, base=16, bitRange=7 +sfr = "TC0_CMR.LDBDIS", "Memory", 0xfffa0004, 4, base=16, bitRange=7 +sfr = "TC0_CMR.ETRGEDG", "Memory", 0xfffa0004, 4, base=16, bitRange=8-9 +sfr = "TC0_CMR.EEVTEDG", "Memory", 0xfffa0004, 4, base=16, bitRange=8-9 +sfr = "TC0_CMR.EEVT", "Memory", 0xfffa0004, 4, base=16, bitRange=10-11 +sfr = "TC0_CMR.ABETRG", "Memory", 0xfffa0004, 4, base=16, bitRange=10 +sfr = "TC0_CMR.ENETRG", "Memory", 0xfffa0004, 4, base=16, bitRange=12 +sfr = "TC0_CMR.WAVESEL", "Memory", 0xfffa0004, 4, base=16, bitRange=13-14 +sfr = "TC0_CMR.CPCTRG", "Memory", 0xfffa0004, 4, base=16, bitRange=14 +sfr = "TC0_CMR.WAVE", "Memory", 0xfffa0004, 4, base=16, bitRange=15 +sfr = "TC0_CMR.ACPA", "Memory", 0xfffa0004, 4, base=16, bitRange=16-17 +sfr = "TC0_CMR.LDRA", "Memory", 0xfffa0004, 4, base=16, bitRange=16-17 +sfr = "TC0_CMR.ACPC", "Memory", 0xfffa0004, 4, base=16, bitRange=18-19 +sfr = "TC0_CMR.LDRB", "Memory", 0xfffa0004, 4, base=16, bitRange=18-19 +sfr = "TC0_CMR.AEEVT", "Memory", 0xfffa0004, 4, base=16, bitRange=20-21 +sfr = "TC0_CMR.ASWTRG", "Memory", 0xfffa0004, 4, base=16, bitRange=22-23 +sfr = "TC0_CMR.BCPB", "Memory", 0xfffa0004, 4, base=16, bitRange=24-25 +sfr = "TC0_CMR.BCPC", "Memory", 0xfffa0004, 4, base=16, bitRange=26-27 +sfr = "TC0_CMR.BEEVT", "Memory", 0xfffa0004, 4, base=16, bitRange=28-29 +sfr = "TC0_CMR.BSWTRG", "Memory", 0xfffa0004, 4, base=16, bitRange=30-31 +sfr = "TC0_CV", "Memory", 0xfffa0010, 4, base=16 +sfr = "TC0_RA", "Memory", 0xfffa0014, 4, base=16 +sfr = "TC0_RB", "Memory", 0xfffa0018, 4, base=16 +sfr = "TC0_RC", "Memory", 0xfffa001c, 4, base=16 +sfr = "TC0_SR", "Memory", 0xfffa0020, 4, base=16 +sfr = "TC0_SR.COVFS", "Memory", 0xfffa0020, 4, base=16, bitRange=0 +sfr = "TC0_SR.LOVRS", "Memory", 0xfffa0020, 4, base=16, bitRange=1 +sfr = "TC0_SR.CPAS", "Memory", 0xfffa0020, 4, base=16, bitRange=2 +sfr = "TC0_SR.CPBS", "Memory", 0xfffa0020, 4, base=16, bitRange=3 +sfr = "TC0_SR.CPCS", "Memory", 0xfffa0020, 4, base=16, bitRange=4 +sfr = "TC0_SR.LDRAS", "Memory", 0xfffa0020, 4, base=16, bitRange=5 +sfr = "TC0_SR.LDRBS", "Memory", 0xfffa0020, 4, base=16, bitRange=6 +sfr = "TC0_SR.ETRGS", "Memory", 0xfffa0020, 4, base=16, bitRange=7 +sfr = "TC0_SR.CLKSTA", "Memory", 0xfffa0020, 4, base=16, bitRange=16 +sfr = "TC0_SR.MTIOA", "Memory", 0xfffa0020, 4, base=16, bitRange=17 +sfr = "TC0_SR.MTIOB", "Memory", 0xfffa0020, 4, base=16, bitRange=18 +sfr = "TC0_IER", "Memory", 0xfffa0024, 4, base=16 +sfr = "TC0_IER.COVFS", "Memory", 0xfffa0024, 4, base=16, bitRange=0 +sfr = "TC0_IER.LOVRS", "Memory", 0xfffa0024, 4, base=16, bitRange=1 +sfr = "TC0_IER.CPAS", "Memory", 0xfffa0024, 4, base=16, bitRange=2 +sfr = "TC0_IER.CPBS", "Memory", 0xfffa0024, 4, base=16, bitRange=3 +sfr = "TC0_IER.CPCS", "Memory", 0xfffa0024, 4, base=16, bitRange=4 +sfr = "TC0_IER.LDRAS", "Memory", 0xfffa0024, 4, base=16, bitRange=5 +sfr = "TC0_IER.LDRBS", "Memory", 0xfffa0024, 4, base=16, bitRange=6 +sfr = "TC0_IER.ETRGS", "Memory", 0xfffa0024, 4, base=16, bitRange=7 +sfr = "TC0_IDR", "Memory", 0xfffa0028, 4, base=16 +sfr = "TC0_IDR.COVFS", "Memory", 0xfffa0028, 4, base=16, bitRange=0 +sfr = "TC0_IDR.LOVRS", "Memory", 0xfffa0028, 4, base=16, bitRange=1 +sfr = "TC0_IDR.CPAS", "Memory", 0xfffa0028, 4, base=16, bitRange=2 +sfr = "TC0_IDR.CPBS", "Memory", 0xfffa0028, 4, base=16, bitRange=3 +sfr = "TC0_IDR.CPCS", "Memory", 0xfffa0028, 4, base=16, bitRange=4 +sfr = "TC0_IDR.LDRAS", "Memory", 0xfffa0028, 4, base=16, bitRange=5 +sfr = "TC0_IDR.LDRBS", "Memory", 0xfffa0028, 4, base=16, bitRange=6 +sfr = "TC0_IDR.ETRGS", "Memory", 0xfffa0028, 4, base=16, bitRange=7 +sfr = "TC0_IMR", "Memory", 0xfffa002c, 4, base=16 +sfr = "TC0_IMR.COVFS", "Memory", 0xfffa002c, 4, base=16, bitRange=0 +sfr = "TC0_IMR.LOVRS", "Memory", 0xfffa002c, 4, base=16, bitRange=1 +sfr = "TC0_IMR.CPAS", "Memory", 0xfffa002c, 4, base=16, bitRange=2 +sfr = "TC0_IMR.CPBS", "Memory", 0xfffa002c, 4, base=16, bitRange=3 +sfr = "TC0_IMR.CPCS", "Memory", 0xfffa002c, 4, base=16, bitRange=4 +sfr = "TC0_IMR.LDRAS", "Memory", 0xfffa002c, 4, base=16, bitRange=5 +sfr = "TC0_IMR.LDRBS", "Memory", 0xfffa002c, 4, base=16, bitRange=6 +sfr = "TC0_IMR.ETRGS", "Memory", 0xfffa002c, 4, base=16, bitRange=7 +; ========== Register definition for TC1 peripheral ========== +sfr = "TC1_CCR", "Memory", 0xfffa0040, 4, base=16 +sfr = "TC1_CCR.CLKEN", "Memory", 0xfffa0040, 4, base=16, bitRange=0 +sfr = "TC1_CCR.CLKDIS", "Memory", 0xfffa0040, 4, base=16, bitRange=1 +sfr = "TC1_CCR.SWTRG", "Memory", 0xfffa0040, 4, base=16, bitRange=2 +sfr = "TC1_CMR", "Memory", 0xfffa0044, 4, base=16 +sfr = "TC1_CMR.CLKS", "Memory", 0xfffa0044, 4, base=16, bitRange=0-2 +sfr = "TC1_CMR.CLKI", "Memory", 0xfffa0044, 4, base=16, bitRange=3 +sfr = "TC1_CMR.BURST", "Memory", 0xfffa0044, 4, base=16, bitRange=4-5 +sfr = "TC1_CMR.CPCSTOP", "Memory", 0xfffa0044, 4, base=16, bitRange=6 +sfr = "TC1_CMR.LDBSTOP", "Memory", 0xfffa0044, 4, base=16, bitRange=6 +sfr = "TC1_CMR.CPCDIS", "Memory", 0xfffa0044, 4, base=16, bitRange=7 +sfr = "TC1_CMR.LDBDIS", "Memory", 0xfffa0044, 4, base=16, bitRange=7 +sfr = "TC1_CMR.ETRGEDG", "Memory", 0xfffa0044, 4, base=16, bitRange=8-9 +sfr = "TC1_CMR.EEVTEDG", "Memory", 0xfffa0044, 4, base=16, bitRange=8-9 +sfr = "TC1_CMR.EEVT", "Memory", 0xfffa0044, 4, base=16, bitRange=10-11 +sfr = "TC1_CMR.ABETRG", "Memory", 0xfffa0044, 4, base=16, bitRange=10 +sfr = "TC1_CMR.ENETRG", "Memory", 0xfffa0044, 4, base=16, bitRange=12 +sfr = "TC1_CMR.WAVESEL", "Memory", 0xfffa0044, 4, base=16, bitRange=13-14 +sfr = "TC1_CMR.CPCTRG", "Memory", 0xfffa0044, 4, base=16, bitRange=14 +sfr = "TC1_CMR.WAVE", "Memory", 0xfffa0044, 4, base=16, bitRange=15 +sfr = "TC1_CMR.ACPA", "Memory", 0xfffa0044, 4, base=16, bitRange=16-17 +sfr = "TC1_CMR.LDRA", "Memory", 0xfffa0044, 4, base=16, bitRange=16-17 +sfr = "TC1_CMR.ACPC", "Memory", 0xfffa0044, 4, base=16, bitRange=18-19 +sfr = "TC1_CMR.LDRB", "Memory", 0xfffa0044, 4, base=16, bitRange=18-19 +sfr = "TC1_CMR.AEEVT", "Memory", 0xfffa0044, 4, base=16, bitRange=20-21 +sfr = "TC1_CMR.ASWTRG", "Memory", 0xfffa0044, 4, base=16, bitRange=22-23 +sfr = "TC1_CMR.BCPB", "Memory", 0xfffa0044, 4, base=16, bitRange=24-25 +sfr = "TC1_CMR.BCPC", "Memory", 0xfffa0044, 4, base=16, bitRange=26-27 +sfr = "TC1_CMR.BEEVT", "Memory", 0xfffa0044, 4, base=16, bitRange=28-29 +sfr = "TC1_CMR.BSWTRG", "Memory", 0xfffa0044, 4, base=16, bitRange=30-31 +sfr = "TC1_CV", "Memory", 0xfffa0050, 4, base=16 +sfr = "TC1_RA", "Memory", 0xfffa0054, 4, base=16 +sfr = "TC1_RB", "Memory", 0xfffa0058, 4, base=16 +sfr = "TC1_RC", "Memory", 0xfffa005c, 4, base=16 +sfr = "TC1_SR", "Memory", 0xfffa0060, 4, base=16 +sfr = "TC1_SR.COVFS", "Memory", 0xfffa0060, 4, base=16, bitRange=0 +sfr = "TC1_SR.LOVRS", "Memory", 0xfffa0060, 4, base=16, bitRange=1 +sfr = "TC1_SR.CPAS", "Memory", 0xfffa0060, 4, base=16, bitRange=2 +sfr = "TC1_SR.CPBS", "Memory", 0xfffa0060, 4, base=16, bitRange=3 +sfr = "TC1_SR.CPCS", "Memory", 0xfffa0060, 4, base=16, bitRange=4 +sfr = "TC1_SR.LDRAS", "Memory", 0xfffa0060, 4, base=16, bitRange=5 +sfr = "TC1_SR.LDRBS", "Memory", 0xfffa0060, 4, base=16, bitRange=6 +sfr = "TC1_SR.ETRGS", "Memory", 0xfffa0060, 4, base=16, bitRange=7 +sfr = "TC1_SR.CLKSTA", "Memory", 0xfffa0060, 4, base=16, bitRange=16 +sfr = "TC1_SR.MTIOA", "Memory", 0xfffa0060, 4, base=16, bitRange=17 +sfr = "TC1_SR.MTIOB", "Memory", 0xfffa0060, 4, base=16, bitRange=18 +sfr = "TC1_IER", "Memory", 0xfffa0064, 4, base=16 +sfr = "TC1_IER.COVFS", "Memory", 0xfffa0064, 4, base=16, bitRange=0 +sfr = "TC1_IER.LOVRS", "Memory", 0xfffa0064, 4, base=16, bitRange=1 +sfr = "TC1_IER.CPAS", "Memory", 0xfffa0064, 4, base=16, bitRange=2 +sfr = "TC1_IER.CPBS", "Memory", 0xfffa0064, 4, base=16, bitRange=3 +sfr = "TC1_IER.CPCS", "Memory", 0xfffa0064, 4, base=16, bitRange=4 +sfr = "TC1_IER.LDRAS", "Memory", 0xfffa0064, 4, base=16, bitRange=5 +sfr = "TC1_IER.LDRBS", "Memory", 0xfffa0064, 4, base=16, bitRange=6 +sfr = "TC1_IER.ETRGS", "Memory", 0xfffa0064, 4, base=16, bitRange=7 +sfr = "TC1_IDR", "Memory", 0xfffa0068, 4, base=16 +sfr = "TC1_IDR.COVFS", "Memory", 0xfffa0068, 4, base=16, bitRange=0 +sfr = "TC1_IDR.LOVRS", "Memory", 0xfffa0068, 4, base=16, bitRange=1 +sfr = "TC1_IDR.CPAS", "Memory", 0xfffa0068, 4, base=16, bitRange=2 +sfr = "TC1_IDR.CPBS", "Memory", 0xfffa0068, 4, base=16, bitRange=3 +sfr = "TC1_IDR.CPCS", "Memory", 0xfffa0068, 4, base=16, bitRange=4 +sfr = "TC1_IDR.LDRAS", "Memory", 0xfffa0068, 4, base=16, bitRange=5 +sfr = "TC1_IDR.LDRBS", "Memory", 0xfffa0068, 4, base=16, bitRange=6 +sfr = "TC1_IDR.ETRGS", "Memory", 0xfffa0068, 4, base=16, bitRange=7 +sfr = "TC1_IMR", "Memory", 0xfffa006c, 4, base=16 +sfr = "TC1_IMR.COVFS", "Memory", 0xfffa006c, 4, base=16, bitRange=0 +sfr = "TC1_IMR.LOVRS", "Memory", 0xfffa006c, 4, base=16, bitRange=1 +sfr = "TC1_IMR.CPAS", "Memory", 0xfffa006c, 4, base=16, bitRange=2 +sfr = "TC1_IMR.CPBS", "Memory", 0xfffa006c, 4, base=16, bitRange=3 +sfr = "TC1_IMR.CPCS", "Memory", 0xfffa006c, 4, base=16, bitRange=4 +sfr = "TC1_IMR.LDRAS", "Memory", 0xfffa006c, 4, base=16, bitRange=5 +sfr = "TC1_IMR.LDRBS", "Memory", 0xfffa006c, 4, base=16, bitRange=6 +sfr = "TC1_IMR.ETRGS", "Memory", 0xfffa006c, 4, base=16, bitRange=7 +; ========== Register definition for TC2 peripheral ========== +sfr = "TC2_CCR", "Memory", 0xfffa0080, 4, base=16 +sfr = "TC2_CCR.CLKEN", "Memory", 0xfffa0080, 4, base=16, bitRange=0 +sfr = "TC2_CCR.CLKDIS", "Memory", 0xfffa0080, 4, base=16, bitRange=1 +sfr = "TC2_CCR.SWTRG", "Memory", 0xfffa0080, 4, base=16, bitRange=2 +sfr = "TC2_CMR", "Memory", 0xfffa0084, 4, base=16 +sfr = "TC2_CMR.CLKS", "Memory", 0xfffa0084, 4, base=16, bitRange=0-2 +sfr = "TC2_CMR.CLKI", "Memory", 0xfffa0084, 4, base=16, bitRange=3 +sfr = "TC2_CMR.BURST", "Memory", 0xfffa0084, 4, base=16, bitRange=4-5 +sfr = "TC2_CMR.CPCSTOP", "Memory", 0xfffa0084, 4, base=16, bitRange=6 +sfr = "TC2_CMR.LDBSTOP", "Memory", 0xfffa0084, 4, base=16, bitRange=6 +sfr = "TC2_CMR.CPCDIS", "Memory", 0xfffa0084, 4, base=16, bitRange=7 +sfr = "TC2_CMR.LDBDIS", "Memory", 0xfffa0084, 4, base=16, bitRange=7 +sfr = "TC2_CMR.ETRGEDG", "Memory", 0xfffa0084, 4, base=16, bitRange=8-9 +sfr = "TC2_CMR.EEVTEDG", "Memory", 0xfffa0084, 4, base=16, bitRange=8-9 +sfr = "TC2_CMR.EEVT", "Memory", 0xfffa0084, 4, base=16, bitRange=10-11 +sfr = "TC2_CMR.ABETRG", "Memory", 0xfffa0084, 4, base=16, bitRange=10 +sfr = "TC2_CMR.ENETRG", "Memory", 0xfffa0084, 4, base=16, bitRange=12 +sfr = "TC2_CMR.WAVESEL", "Memory", 0xfffa0084, 4, base=16, bitRange=13-14 +sfr = "TC2_CMR.CPCTRG", "Memory", 0xfffa0084, 4, base=16, bitRange=14 +sfr = "TC2_CMR.WAVE", "Memory", 0xfffa0084, 4, base=16, bitRange=15 +sfr = "TC2_CMR.ACPA", "Memory", 0xfffa0084, 4, base=16, bitRange=16-17 +sfr = "TC2_CMR.LDRA", "Memory", 0xfffa0084, 4, base=16, bitRange=16-17 +sfr = "TC2_CMR.ACPC", "Memory", 0xfffa0084, 4, base=16, bitRange=18-19 +sfr = "TC2_CMR.LDRB", "Memory", 0xfffa0084, 4, base=16, bitRange=18-19 +sfr = "TC2_CMR.AEEVT", "Memory", 0xfffa0084, 4, base=16, bitRange=20-21 +sfr = "TC2_CMR.ASWTRG", "Memory", 0xfffa0084, 4, base=16, bitRange=22-23 +sfr = "TC2_CMR.BCPB", "Memory", 0xfffa0084, 4, base=16, bitRange=24-25 +sfr = "TC2_CMR.BCPC", "Memory", 0xfffa0084, 4, base=16, bitRange=26-27 +sfr = "TC2_CMR.BEEVT", "Memory", 0xfffa0084, 4, base=16, bitRange=28-29 +sfr = "TC2_CMR.BSWTRG", "Memory", 0xfffa0084, 4, base=16, bitRange=30-31 +sfr = "TC2_CV", "Memory", 0xfffa0090, 4, base=16 +sfr = "TC2_RA", "Memory", 0xfffa0094, 4, base=16 +sfr = "TC2_RB", "Memory", 0xfffa0098, 4, base=16 +sfr = "TC2_RC", "Memory", 0xfffa009c, 4, base=16 +sfr = "TC2_SR", "Memory", 0xfffa00a0, 4, base=16 +sfr = "TC2_SR.COVFS", "Memory", 0xfffa00a0, 4, base=16, bitRange=0 +sfr = "TC2_SR.LOVRS", "Memory", 0xfffa00a0, 4, base=16, bitRange=1 +sfr = "TC2_SR.CPAS", "Memory", 0xfffa00a0, 4, base=16, bitRange=2 +sfr = "TC2_SR.CPBS", "Memory", 0xfffa00a0, 4, base=16, bitRange=3 +sfr = "TC2_SR.CPCS", "Memory", 0xfffa00a0, 4, base=16, bitRange=4 +sfr = "TC2_SR.LDRAS", "Memory", 0xfffa00a0, 4, base=16, bitRange=5 +sfr = "TC2_SR.LDRBS", "Memory", 0xfffa00a0, 4, base=16, bitRange=6 +sfr = "TC2_SR.ETRGS", "Memory", 0xfffa00a0, 4, base=16, bitRange=7 +sfr = "TC2_SR.CLKSTA", "Memory", 0xfffa00a0, 4, base=16, bitRange=16 +sfr = "TC2_SR.MTIOA", "Memory", 0xfffa00a0, 4, base=16, bitRange=17 +sfr = "TC2_SR.MTIOB", "Memory", 0xfffa00a0, 4, base=16, bitRange=18 +sfr = "TC2_IER", "Memory", 0xfffa00a4, 4, base=16 +sfr = "TC2_IER.COVFS", "Memory", 0xfffa00a4, 4, base=16, bitRange=0 +sfr = "TC2_IER.LOVRS", "Memory", 0xfffa00a4, 4, base=16, bitRange=1 +sfr = "TC2_IER.CPAS", "Memory", 0xfffa00a4, 4, base=16, bitRange=2 +sfr = "TC2_IER.CPBS", "Memory", 0xfffa00a4, 4, base=16, bitRange=3 +sfr = "TC2_IER.CPCS", "Memory", 0xfffa00a4, 4, base=16, bitRange=4 +sfr = "TC2_IER.LDRAS", "Memory", 0xfffa00a4, 4, base=16, bitRange=5 +sfr = "TC2_IER.LDRBS", "Memory", 0xfffa00a4, 4, base=16, bitRange=6 +sfr = "TC2_IER.ETRGS", "Memory", 0xfffa00a4, 4, base=16, bitRange=7 +sfr = "TC2_IDR", "Memory", 0xfffa00a8, 4, base=16 +sfr = "TC2_IDR.COVFS", "Memory", 0xfffa00a8, 4, base=16, bitRange=0 +sfr = "TC2_IDR.LOVRS", "Memory", 0xfffa00a8, 4, base=16, bitRange=1 +sfr = "TC2_IDR.CPAS", "Memory", 0xfffa00a8, 4, base=16, bitRange=2 +sfr = "TC2_IDR.CPBS", "Memory", 0xfffa00a8, 4, base=16, bitRange=3 +sfr = "TC2_IDR.CPCS", "Memory", 0xfffa00a8, 4, base=16, bitRange=4 +sfr = "TC2_IDR.LDRAS", "Memory", 0xfffa00a8, 4, base=16, bitRange=5 +sfr = "TC2_IDR.LDRBS", "Memory", 0xfffa00a8, 4, base=16, bitRange=6 +sfr = "TC2_IDR.ETRGS", "Memory", 0xfffa00a8, 4, base=16, bitRange=7 +sfr = "TC2_IMR", "Memory", 0xfffa00ac, 4, base=16 +sfr = "TC2_IMR.COVFS", "Memory", 0xfffa00ac, 4, base=16, bitRange=0 +sfr = "TC2_IMR.LOVRS", "Memory", 0xfffa00ac, 4, base=16, bitRange=1 +sfr = "TC2_IMR.CPAS", "Memory", 0xfffa00ac, 4, base=16, bitRange=2 +sfr = "TC2_IMR.CPBS", "Memory", 0xfffa00ac, 4, base=16, bitRange=3 +sfr = "TC2_IMR.CPCS", "Memory", 0xfffa00ac, 4, base=16, bitRange=4 +sfr = "TC2_IMR.LDRAS", "Memory", 0xfffa00ac, 4, base=16, bitRange=5 +sfr = "TC2_IMR.LDRBS", "Memory", 0xfffa00ac, 4, base=16, bitRange=6 +sfr = "TC2_IMR.ETRGS", "Memory", 0xfffa00ac, 4, base=16, bitRange=7 +; ========== Register definition for TCB peripheral ========== +sfr = "TCB_BCR", "Memory", 0xfffa00c0, 4, base=16 +sfr = "TCB_BCR.SYNC", "Memory", 0xfffa00c0, 4, base=16, bitRange=0 +sfr = "TCB_BMR", "Memory", 0xfffa00c4, 4, base=16 +sfr = "TCB_BMR.TC0XC0S", "Memory", 0xfffa00c4, 4, base=16, bitRange=0-1 +sfr = "TCB_BMR.TC1XC1S", "Memory", 0xfffa00c4, 4, base=16, bitRange=2-3 +sfr = "TCB_BMR.TC2XC2S", "Memory", 0xfffa00c4, 4, base=16, bitRange=4-5 +; ========== Register definition for PWMC_CH3 peripheral ========== +sfr = "PWMC_CH3_CMR", "Memory", 0xfffcc260, 4, base=16 +sfr = "PWMC_CH3_CMR.CPRE", "Memory", 0xfffcc260, 4, base=16, bitRange=0-3 +sfr = "PWMC_CH3_CMR.CALG", "Memory", 0xfffcc260, 4, base=16, bitRange=8 +sfr = "PWMC_CH3_CMR.CPOL", "Memory", 0xfffcc260, 4, base=16, bitRange=9 +sfr = "PWMC_CH3_CMR.CPD", "Memory", 0xfffcc260, 4, base=16, bitRange=10 +sfr = "PWMC_CH3_CDTYR", "Memory", 0xfffcc264, 4, base=16 +sfr = "PWMC_CH3_CDTYR.CDTY", "Memory", 0xfffcc264, 4, base=16, bitRange=0-31 +sfr = "PWMC_CH3_CPRDR", "Memory", 0xfffcc268, 4, base=16 +sfr = "PWMC_CH3_CPRDR.CPRD", "Memory", 0xfffcc268, 4, base=16, bitRange=0-31 +sfr = "PWMC_CH3_CCNTR", "Memory", 0xfffcc26c, 4, base=16 +sfr = "PWMC_CH3_CCNTR.CCNT", "Memory", 0xfffcc26c, 4, base=16, bitRange=0-31 +sfr = "PWMC_CH3_CUPDR", "Memory", 0xfffcc270, 4, base=16 +sfr = "PWMC_CH3_CUPDR.CUPD", "Memory", 0xfffcc270, 4, base=16, bitRange=0-31 +sfr = "PWMC_CH3_Reserved", "Memory", 0xfffcc274, 4, base=16 +; ========== Register definition for PWMC_CH2 peripheral ========== +sfr = "PWMC_CH2_CMR", "Memory", 0xfffcc240, 4, base=16 +sfr = "PWMC_CH2_CMR.CPRE", "Memory", 0xfffcc240, 4, base=16, bitRange=0-3 +sfr = "PWMC_CH2_CMR.CALG", "Memory", 0xfffcc240, 4, base=16, bitRange=8 +sfr = "PWMC_CH2_CMR.CPOL", "Memory", 0xfffcc240, 4, base=16, bitRange=9 +sfr = "PWMC_CH2_CMR.CPD", "Memory", 0xfffcc240, 4, base=16, bitRange=10 +sfr = "PWMC_CH2_CDTYR", "Memory", 0xfffcc244, 4, base=16 +sfr = "PWMC_CH2_CDTYR.CDTY", "Memory", 0xfffcc244, 4, base=16, bitRange=0-31 +sfr = "PWMC_CH2_CPRDR", "Memory", 0xfffcc248, 4, base=16 +sfr = "PWMC_CH2_CPRDR.CPRD", "Memory", 0xfffcc248, 4, base=16, bitRange=0-31 +sfr = "PWMC_CH2_CCNTR", "Memory", 0xfffcc24c, 4, base=16 +sfr = "PWMC_CH2_CCNTR.CCNT", "Memory", 0xfffcc24c, 4, base=16, bitRange=0-31 +sfr = "PWMC_CH2_CUPDR", "Memory", 0xfffcc250, 4, base=16 +sfr = "PWMC_CH2_CUPDR.CUPD", "Memory", 0xfffcc250, 4, base=16, bitRange=0-31 +sfr = "PWMC_CH2_Reserved", "Memory", 0xfffcc254, 4, base=16 +; ========== Register definition for PWMC_CH1 peripheral ========== +sfr = "PWMC_CH1_CMR", "Memory", 0xfffcc220, 4, base=16 +sfr = "PWMC_CH1_CMR.CPRE", "Memory", 0xfffcc220, 4, base=16, bitRange=0-3 +sfr = "PWMC_CH1_CMR.CALG", "Memory", 0xfffcc220, 4, base=16, bitRange=8 +sfr = "PWMC_CH1_CMR.CPOL", "Memory", 0xfffcc220, 4, base=16, bitRange=9 +sfr = "PWMC_CH1_CMR.CPD", "Memory", 0xfffcc220, 4, base=16, bitRange=10 +sfr = "PWMC_CH1_CDTYR", "Memory", 0xfffcc224, 4, base=16 +sfr = "PWMC_CH1_CDTYR.CDTY", "Memory", 0xfffcc224, 4, base=16, bitRange=0-31 +sfr = "PWMC_CH1_CPRDR", "Memory", 0xfffcc228, 4, base=16 +sfr = "PWMC_CH1_CPRDR.CPRD", "Memory", 0xfffcc228, 4, base=16, bitRange=0-31 +sfr = "PWMC_CH1_CCNTR", "Memory", 0xfffcc22c, 4, base=16 +sfr = "PWMC_CH1_CCNTR.CCNT", "Memory", 0xfffcc22c, 4, base=16, bitRange=0-31 +sfr = "PWMC_CH1_CUPDR", "Memory", 0xfffcc230, 4, base=16 +sfr = "PWMC_CH1_CUPDR.CUPD", "Memory", 0xfffcc230, 4, base=16, bitRange=0-31 +sfr = "PWMC_CH1_Reserved", "Memory", 0xfffcc234, 4, base=16 +; ========== Register definition for PWMC_CH0 peripheral ========== +sfr = "PWMC_CH0_CMR", "Memory", 0xfffcc200, 4, base=16 +sfr = "PWMC_CH0_CMR.CPRE", "Memory", 0xfffcc200, 4, base=16, bitRange=0-3 +sfr = "PWMC_CH0_CMR.CALG", "Memory", 0xfffcc200, 4, base=16, bitRange=8 +sfr = "PWMC_CH0_CMR.CPOL", "Memory", 0xfffcc200, 4, base=16, bitRange=9 +sfr = "PWMC_CH0_CMR.CPD", "Memory", 0xfffcc200, 4, base=16, bitRange=10 +sfr = "PWMC_CH0_CDTYR", "Memory", 0xfffcc204, 4, base=16 +sfr = "PWMC_CH0_CDTYR.CDTY", "Memory", 0xfffcc204, 4, base=16, bitRange=0-31 +sfr = "PWMC_CH0_CPRDR", "Memory", 0xfffcc208, 4, base=16 +sfr = "PWMC_CH0_CPRDR.CPRD", "Memory", 0xfffcc208, 4, base=16, bitRange=0-31 +sfr = "PWMC_CH0_CCNTR", "Memory", 0xfffcc20c, 4, base=16 +sfr = "PWMC_CH0_CCNTR.CCNT", "Memory", 0xfffcc20c, 4, base=16, bitRange=0-31 +sfr = "PWMC_CH0_CUPDR", "Memory", 0xfffcc210, 4, base=16 +sfr = "PWMC_CH0_CUPDR.CUPD", "Memory", 0xfffcc210, 4, base=16, bitRange=0-31 +sfr = "PWMC_CH0_Reserved", "Memory", 0xfffcc214, 4, base=16 +; ========== Register definition for PWMC peripheral ========== +sfr = "PWMC_MR", "Memory", 0xfffcc000, 4, base=16 +sfr = "PWMC_MR.DIVA", "Memory", 0xfffcc000, 4, base=16, bitRange=0-7 +sfr = "PWMC_MR.PREA", "Memory", 0xfffcc000, 4, base=16, bitRange=8-11 +sfr = "PWMC_MR.DIVB", "Memory", 0xfffcc000, 4, base=16, bitRange=16-23 +sfr = "PWMC_MR.PREB", "Memory", 0xfffcc000, 4, base=16, bitRange=24-27 +sfr = "PWMC_ENA", "Memory", 0xfffcc004, 4, base=16 +sfr = "PWMC_ENA.CHID0", "Memory", 0xfffcc004, 4, base=16, bitRange=0 +sfr = "PWMC_ENA.CHID1", "Memory", 0xfffcc004, 4, base=16, bitRange=1 +sfr = "PWMC_ENA.CHID2", "Memory", 0xfffcc004, 4, base=16, bitRange=2 +sfr = "PWMC_ENA.CHID3", "Memory", 0xfffcc004, 4, base=16, bitRange=3 +sfr = "PWMC_ENA.CHID4", "Memory", 0xfffcc004, 4, base=16, bitRange=4 +sfr = "PWMC_ENA.CHID5", "Memory", 0xfffcc004, 4, base=16, bitRange=5 +sfr = "PWMC_ENA.CHID6", "Memory", 0xfffcc004, 4, base=16, bitRange=6 +sfr = "PWMC_ENA.CHID7", "Memory", 0xfffcc004, 4, base=16, bitRange=7 +sfr = "PWMC_DIS", "Memory", 0xfffcc008, 4, base=16 +sfr = "PWMC_DIS.CHID0", "Memory", 0xfffcc008, 4, base=16, bitRange=0 +sfr = "PWMC_DIS.CHID1", "Memory", 0xfffcc008, 4, base=16, bitRange=1 +sfr = "PWMC_DIS.CHID2", "Memory", 0xfffcc008, 4, base=16, bitRange=2 +sfr = "PWMC_DIS.CHID3", "Memory", 0xfffcc008, 4, base=16, bitRange=3 +sfr = "PWMC_DIS.CHID4", "Memory", 0xfffcc008, 4, base=16, bitRange=4 +sfr = "PWMC_DIS.CHID5", "Memory", 0xfffcc008, 4, base=16, bitRange=5 +sfr = "PWMC_DIS.CHID6", "Memory", 0xfffcc008, 4, base=16, bitRange=6 +sfr = "PWMC_DIS.CHID7", "Memory", 0xfffcc008, 4, base=16, bitRange=7 +sfr = "PWMC_SR", "Memory", 0xfffcc00c, 4, base=16 +sfr = "PWMC_SR.CHID0", "Memory", 0xfffcc00c, 4, base=16, bitRange=0 +sfr = "PWMC_SR.CHID1", "Memory", 0xfffcc00c, 4, base=16, bitRange=1 +sfr = "PWMC_SR.CHID2", "Memory", 0xfffcc00c, 4, base=16, bitRange=2 +sfr = "PWMC_SR.CHID3", "Memory", 0xfffcc00c, 4, base=16, bitRange=3 +sfr = "PWMC_SR.CHID4", "Memory", 0xfffcc00c, 4, base=16, bitRange=4 +sfr = "PWMC_SR.CHID5", "Memory", 0xfffcc00c, 4, base=16, bitRange=5 +sfr = "PWMC_SR.CHID6", "Memory", 0xfffcc00c, 4, base=16, bitRange=6 +sfr = "PWMC_SR.CHID7", "Memory", 0xfffcc00c, 4, base=16, bitRange=7 +sfr = "PWMC_IER", "Memory", 0xfffcc010, 4, base=16 +sfr = "PWMC_IER.CHID0", "Memory", 0xfffcc010, 4, base=16, bitRange=0 +sfr = "PWMC_IER.CHID1", "Memory", 0xfffcc010, 4, base=16, bitRange=1 +sfr = "PWMC_IER.CHID2", "Memory", 0xfffcc010, 4, base=16, bitRange=2 +sfr = "PWMC_IER.CHID3", "Memory", 0xfffcc010, 4, base=16, bitRange=3 +sfr = "PWMC_IER.CHID4", "Memory", 0xfffcc010, 4, base=16, bitRange=4 +sfr = "PWMC_IER.CHID5", "Memory", 0xfffcc010, 4, base=16, bitRange=5 +sfr = "PWMC_IER.CHID6", "Memory", 0xfffcc010, 4, base=16, bitRange=6 +sfr = "PWMC_IER.CHID7", "Memory", 0xfffcc010, 4, base=16, bitRange=7 +sfr = "PWMC_IDR", "Memory", 0xfffcc014, 4, base=16 +sfr = "PWMC_IDR.CHID0", "Memory", 0xfffcc014, 4, base=16, bitRange=0 +sfr = "PWMC_IDR.CHID1", "Memory", 0xfffcc014, 4, base=16, bitRange=1 +sfr = "PWMC_IDR.CHID2", "Memory", 0xfffcc014, 4, base=16, bitRange=2 +sfr = "PWMC_IDR.CHID3", "Memory", 0xfffcc014, 4, base=16, bitRange=3 +sfr = "PWMC_IDR.CHID4", "Memory", 0xfffcc014, 4, base=16, bitRange=4 +sfr = "PWMC_IDR.CHID5", "Memory", 0xfffcc014, 4, base=16, bitRange=5 +sfr = "PWMC_IDR.CHID6", "Memory", 0xfffcc014, 4, base=16, bitRange=6 +sfr = "PWMC_IDR.CHID7", "Memory", 0xfffcc014, 4, base=16, bitRange=7 +sfr = "PWMC_IMR", "Memory", 0xfffcc018, 4, base=16 +sfr = "PWMC_IMR.CHID0", "Memory", 0xfffcc018, 4, base=16, bitRange=0 +sfr = "PWMC_IMR.CHID1", "Memory", 0xfffcc018, 4, base=16, bitRange=1 +sfr = "PWMC_IMR.CHID2", "Memory", 0xfffcc018, 4, base=16, bitRange=2 +sfr = "PWMC_IMR.CHID3", "Memory", 0xfffcc018, 4, base=16, bitRange=3 +sfr = "PWMC_IMR.CHID4", "Memory", 0xfffcc018, 4, base=16, bitRange=4 +sfr = "PWMC_IMR.CHID5", "Memory", 0xfffcc018, 4, base=16, bitRange=5 +sfr = "PWMC_IMR.CHID6", "Memory", 0xfffcc018, 4, base=16, bitRange=6 +sfr = "PWMC_IMR.CHID7", "Memory", 0xfffcc018, 4, base=16, bitRange=7 +sfr = "PWMC_ISR", "Memory", 0xfffcc01c, 4, base=16 +sfr = "PWMC_ISR.CHID0", "Memory", 0xfffcc01c, 4, base=16, bitRange=0 +sfr = "PWMC_ISR.CHID1", "Memory", 0xfffcc01c, 4, base=16, bitRange=1 +sfr = "PWMC_ISR.CHID2", "Memory", 0xfffcc01c, 4, base=16, bitRange=2 +sfr = "PWMC_ISR.CHID3", "Memory", 0xfffcc01c, 4, base=16, bitRange=3 +sfr = "PWMC_ISR.CHID4", "Memory", 0xfffcc01c, 4, base=16, bitRange=4 +sfr = "PWMC_ISR.CHID5", "Memory", 0xfffcc01c, 4, base=16, bitRange=5 +sfr = "PWMC_ISR.CHID6", "Memory", 0xfffcc01c, 4, base=16, bitRange=6 +sfr = "PWMC_ISR.CHID7", "Memory", 0xfffcc01c, 4, base=16, bitRange=7 +sfr = "PWMC_VR", "Memory", 0xfffcc0fc, 4, base=16 +; ========== Register definition for UDP peripheral ========== +sfr = "UDP_NUM", "Memory", 0xfffb0000, 4, base=16 +sfr = "UDP_NUM.NUM", "Memory", 0xfffb0000, 4, base=16, bitRange=0-10 +sfr = "UDP_NUM.ERR", "Memory", 0xfffb0000, 4, base=16, bitRange=16 +sfr = "UDP_NUM.OK", "Memory", 0xfffb0000, 4, base=16, bitRange=17 +sfr = "UDP_GLBSTATE", "Memory", 0xfffb0004, 4, base=16 +sfr = "UDP_GLBSTATE.FADDEN", "Memory", 0xfffb0004, 4, base=16, bitRange=0 +sfr = "UDP_GLBSTATE.CONFG", "Memory", 0xfffb0004, 4, base=16, bitRange=1 +sfr = "UDP_GLBSTATE.ESR", "Memory", 0xfffb0004, 4, base=16, bitRange=2 +sfr = "UDP_GLBSTATE.RSMINPR", "Memory", 0xfffb0004, 4, base=16, bitRange=3 +sfr = "UDP_GLBSTATE.RMWUPE", "Memory", 0xfffb0004, 4, base=16, bitRange=4 +sfr = "UDP_FADDR", "Memory", 0xfffb0008, 4, base=16 +sfr = "UDP_FADDR.FADD", "Memory", 0xfffb0008, 4, base=16, bitRange=0-7 +sfr = "UDP_FADDR.FEN", "Memory", 0xfffb0008, 4, base=16, bitRange=8 +sfr = "UDP_IER", "Memory", 0xfffb0010, 4, base=16 +sfr = "UDP_IER.EPINT0", "Memory", 0xfffb0010, 4, base=16, bitRange=0 +sfr = "UDP_IER.EPINT1", "Memory", 0xfffb0010, 4, base=16, bitRange=1 +sfr = "UDP_IER.EPINT2", "Memory", 0xfffb0010, 4, base=16, bitRange=2 +sfr = "UDP_IER.EPINT3", "Memory", 0xfffb0010, 4, base=16, bitRange=3 +sfr = "UDP_IER.EPINT4", "Memory", 0xfffb0010, 4, base=16, bitRange=4 +sfr = "UDP_IER.EPINT5", "Memory", 0xfffb0010, 4, base=16, bitRange=5 +sfr = "UDP_IER.EPINT6", "Memory", 0xfffb0010, 4, base=16, bitRange=6 +sfr = "UDP_IER.EPINT7", "Memory", 0xfffb0010, 4, base=16, bitRange=7 +sfr = "UDP_IER.RXSUSP", "Memory", 0xfffb0010, 4, base=16, bitRange=8 +sfr = "UDP_IER.RXRSM", "Memory", 0xfffb0010, 4, base=16, bitRange=9 +sfr = "UDP_IER.EXTRSM", "Memory", 0xfffb0010, 4, base=16, bitRange=10 +sfr = "UDP_IER.SOFINT", "Memory", 0xfffb0010, 4, base=16, bitRange=11 +sfr = "UDP_IER.WAKEUP", "Memory", 0xfffb0010, 4, base=16, bitRange=13 +sfr = "UDP_IDR", "Memory", 0xfffb0014, 4, base=16 +sfr = "UDP_IDR.EPINT0", "Memory", 0xfffb0014, 4, base=16, bitRange=0 +sfr = "UDP_IDR.EPINT1", "Memory", 0xfffb0014, 4, base=16, bitRange=1 +sfr = "UDP_IDR.EPINT2", "Memory", 0xfffb0014, 4, base=16, bitRange=2 +sfr = "UDP_IDR.EPINT3", "Memory", 0xfffb0014, 4, base=16, bitRange=3 +sfr = "UDP_IDR.EPINT4", "Memory", 0xfffb0014, 4, base=16, bitRange=4 +sfr = "UDP_IDR.EPINT5", "Memory", 0xfffb0014, 4, base=16, bitRange=5 +sfr = "UDP_IDR.EPINT6", "Memory", 0xfffb0014, 4, base=16, bitRange=6 +sfr = "UDP_IDR.EPINT7", "Memory", 0xfffb0014, 4, base=16, bitRange=7 +sfr = "UDP_IDR.RXSUSP", "Memory", 0xfffb0014, 4, base=16, bitRange=8 +sfr = "UDP_IDR.RXRSM", "Memory", 0xfffb0014, 4, base=16, bitRange=9 +sfr = "UDP_IDR.EXTRSM", "Memory", 0xfffb0014, 4, base=16, bitRange=10 +sfr = "UDP_IDR.SOFINT", "Memory", 0xfffb0014, 4, base=16, bitRange=11 +sfr = "UDP_IDR.WAKEUP", "Memory", 0xfffb0014, 4, base=16, bitRange=13 +sfr = "UDP_IMR", "Memory", 0xfffb0018, 4, base=16 +sfr = "UDP_IMR.EPINT0", "Memory", 0xfffb0018, 4, base=16, bitRange=0 +sfr = "UDP_IMR.EPINT1", "Memory", 0xfffb0018, 4, base=16, bitRange=1 +sfr = "UDP_IMR.EPINT2", "Memory", 0xfffb0018, 4, base=16, bitRange=2 +sfr = "UDP_IMR.EPINT3", "Memory", 0xfffb0018, 4, base=16, bitRange=3 +sfr = "UDP_IMR.EPINT4", "Memory", 0xfffb0018, 4, base=16, bitRange=4 +sfr = "UDP_IMR.EPINT5", "Memory", 0xfffb0018, 4, base=16, bitRange=5 +sfr = "UDP_IMR.EPINT6", "Memory", 0xfffb0018, 4, base=16, bitRange=6 +sfr = "UDP_IMR.EPINT7", "Memory", 0xfffb0018, 4, base=16, bitRange=7 +sfr = "UDP_IMR.RXSUSP", "Memory", 0xfffb0018, 4, base=16, bitRange=8 +sfr = "UDP_IMR.RXRSM", "Memory", 0xfffb0018, 4, base=16, bitRange=9 +sfr = "UDP_IMR.EXTRSM", "Memory", 0xfffb0018, 4, base=16, bitRange=10 +sfr = "UDP_IMR.SOFINT", "Memory", 0xfffb0018, 4, base=16, bitRange=11 +sfr = "UDP_IMR.WAKEUP", "Memory", 0xfffb0018, 4, base=16, bitRange=13 +sfr = "UDP_ISR", "Memory", 0xfffb001c, 4, base=16 +sfr = "UDP_ISR.EPINT0", "Memory", 0xfffb001c, 4, base=16, bitRange=0 +sfr = "UDP_ISR.EPINT1", "Memory", 0xfffb001c, 4, base=16, bitRange=1 +sfr = "UDP_ISR.EPINT2", "Memory", 0xfffb001c, 4, base=16, bitRange=2 +sfr = "UDP_ISR.EPINT3", "Memory", 0xfffb001c, 4, base=16, bitRange=3 +sfr = "UDP_ISR.EPINT4", "Memory", 0xfffb001c, 4, base=16, bitRange=4 +sfr = "UDP_ISR.EPINT5", "Memory", 0xfffb001c, 4, base=16, bitRange=5 +sfr = "UDP_ISR.EPINT6", "Memory", 0xfffb001c, 4, base=16, bitRange=6 +sfr = "UDP_ISR.EPINT7", "Memory", 0xfffb001c, 4, base=16, bitRange=7 +sfr = "UDP_ISR.RXSUSP", "Memory", 0xfffb001c, 4, base=16, bitRange=8 +sfr = "UDP_ISR.RXRSM", "Memory", 0xfffb001c, 4, base=16, bitRange=9 +sfr = "UDP_ISR.EXTRSM", "Memory", 0xfffb001c, 4, base=16, bitRange=10 +sfr = "UDP_ISR.SOFINT", "Memory", 0xfffb001c, 4, base=16, bitRange=11 +sfr = "UDP_ISR.ENDBUSRES", "Memory", 0xfffb001c, 4, base=16, bitRange=12 +sfr = "UDP_ISR.WAKEUP", "Memory", 0xfffb001c, 4, base=16, bitRange=13 +sfr = "UDP_ICR", "Memory", 0xfffb0020, 4, base=16 +sfr = "UDP_ICR.EPINT0", "Memory", 0xfffb0020, 4, base=16, bitRange=0 +sfr = "UDP_ICR.EPINT1", "Memory", 0xfffb0020, 4, base=16, bitRange=1 +sfr = "UDP_ICR.EPINT2", "Memory", 0xfffb0020, 4, base=16, bitRange=2 +sfr = "UDP_ICR.EPINT3", "Memory", 0xfffb0020, 4, base=16, bitRange=3 +sfr = "UDP_ICR.EPINT4", "Memory", 0xfffb0020, 4, base=16, bitRange=4 +sfr = "UDP_ICR.EPINT5", "Memory", 0xfffb0020, 4, base=16, bitRange=5 +sfr = "UDP_ICR.EPINT6", "Memory", 0xfffb0020, 4, base=16, bitRange=6 +sfr = "UDP_ICR.EPINT7", "Memory", 0xfffb0020, 4, base=16, bitRange=7 +sfr = "UDP_ICR.RXSUSP", "Memory", 0xfffb0020, 4, base=16, bitRange=8 +sfr = "UDP_ICR.RXRSM", "Memory", 0xfffb0020, 4, base=16, bitRange=9 +sfr = "UDP_ICR.EXTRSM", "Memory", 0xfffb0020, 4, base=16, bitRange=10 +sfr = "UDP_ICR.SOFINT", "Memory", 0xfffb0020, 4, base=16, bitRange=11 +sfr = "UDP_ICR.WAKEUP", "Memory", 0xfffb0020, 4, base=16, bitRange=13 +sfr = "UDP_RSTEP", "Memory", 0xfffb0028, 4, base=16 +sfr = "UDP_RSTEP.EP0", "Memory", 0xfffb0028, 4, base=16, bitRange=0 +sfr = "UDP_RSTEP.EP1", "Memory", 0xfffb0028, 4, base=16, bitRange=1 +sfr = "UDP_RSTEP.EP2", "Memory", 0xfffb0028, 4, base=16, bitRange=2 +sfr = "UDP_RSTEP.EP3", "Memory", 0xfffb0028, 4, base=16, bitRange=3 +sfr = "UDP_RSTEP.EP4", "Memory", 0xfffb0028, 4, base=16, bitRange=4 +sfr = "UDP_RSTEP.EP5", "Memory", 0xfffb0028, 4, base=16, bitRange=5 +sfr = "UDP_RSTEP.EP6", "Memory", 0xfffb0028, 4, base=16, bitRange=6 +sfr = "UDP_RSTEP.EP7", "Memory", 0xfffb0028, 4, base=16, bitRange=7 +sfr = "UDP_CSR", "Memory", 0xfffb0030, 4, base=16 +sfr = "UDP_CSR.TXCOMP", "Memory", 0xfffb0030, 4, base=16, bitRange=0 +sfr = "UDP_CSR.BK0", "Memory", 0xfffb0030, 4, base=16, bitRange=1 +sfr = "UDP_CSR.RXSETUP", "Memory", 0xfffb0030, 4, base=16, bitRange=2 +sfr = "UDP_CSR.ISOERROR", "Memory", 0xfffb0030, 4, base=16, bitRange=3 +sfr = "UDP_CSR.TXPKTRDY", "Memory", 0xfffb0030, 4, base=16, bitRange=4 +sfr = "UDP_CSR.FORCESTALL", "Memory", 0xfffb0030, 4, base=16, bitRange=5 +sfr = "UDP_CSR.BK1", "Memory", 0xfffb0030, 4, base=16, bitRange=6 +sfr = "UDP_CSR.DIR", "Memory", 0xfffb0030, 4, base=16, bitRange=7 +sfr = "UDP_CSR.EPTYPE", "Memory", 0xfffb0030, 4, base=16, bitRange=8-10 +sfr = "UDP_CSR.DTGLE", "Memory", 0xfffb0030, 4, base=16, bitRange=11 +sfr = "UDP_CSR.EPEDS", "Memory", 0xfffb0030, 4, base=16, bitRange=15 +sfr = "UDP_CSR.RXBYTECNT", "Memory", 0xfffb0030, 4, base=16, bitRange=16-26 +sfr = "UDP_FDR", "Memory", 0xfffb0050, 4, base=16 +sfr = "UDP_TXVC", "Memory", 0xfffb0074, 4, base=16 +sfr = "UDP_TXVC.TXVDIS", "Memory", 0xfffb0074, 4, base=16, bitRange=8 +sfr = "UDP_TXVC.PUON", "Memory", 0xfffb0074, 4, base=16, bitRange=9 + + +[SfrGroupInfo] +group = "TC0", "TC0_CCR", "TC0_CMR", "TC0_CV", "TC0_RA", "TC0_RB", "TC0_RC", "TC0_SR", "TC0_IER", "TC0_IDR", "TC0_IMR" +group = "TCB", "TCB_BCR", "TCB_BMR" +group = "TC1", "TC1_CCR", "TC1_CMR", "TC1_CV", "TC1_RA", "TC1_RB", "TC1_RC", "TC1_SR", "TC1_IER", "TC1_IDR", "TC1_IMR" +group = "TC2", "TC2_CCR", "TC2_CMR", "TC2_CV", "TC2_RA", "TC2_RB", "TC2_RC", "TC2_SR", "TC2_IER", "TC2_IDR", "TC2_IMR" +group = "UDP", "UDP_NUM", "UDP_GLBSTATE", "UDP_FADDR", "UDP_IER", "UDP_IDR", "UDP_IMR", "UDP_ISR", "UDP_ICR", "UDP_RSTEP", "UDP_CSR", "UDP_FDR", "UDP_TXVC" +group = "TWI", "TWI_CR", "TWI_MMR", "TWI_IADR", "TWI_CWGR", "TWI_SR", "TWI_IER", "TWI_IDR", "TWI_IMR", "TWI_RHR", "TWI_THR" +group = "US0", "US0_CR", "US0_MR", "US0_IER", "US0_IDR", "US0_IMR", "US0_CSR", "US0_RHR", "US0_THR", "US0_BRGR", "US0_RTOR", "US0_TTGR", "US0_FIDI", "US0_NER", "US0_IF" +group = "PDC_US0", "US0_RPR", "US0_RCR", "US0_TPR", "US0_TCR", "US0_RNPR", "US0_RNCR", "US0_TNPR", "US0_TNCR", "US0_PTCR", "US0_PTSR" +group = "US1", "US1_CR", "US1_MR", "US1_IER", "US1_IDR", "US1_IMR", "US1_CSR", "US1_RHR", "US1_THR", "US1_BRGR", "US1_RTOR", "US1_TTGR", "US1_FIDI", "US1_NER", "US1_IF" +group = "PDC_US1", "US1_RPR", "US1_RCR", "US1_TPR", "US1_TCR", "US1_RNPR", "US1_RNCR", "US1_TNPR", "US1_TNCR", "US1_PTCR", "US1_PTSR" +group = "PWMC", "PWMC_MR", "PWMC_ENA", "PWMC_DIS", "PWMC_SR", "PWMC_IER", "PWMC_IDR", "PWMC_IMR", "PWMC_ISR", "PWMC_VR" +group = "PWMC_CH0", "PWMC_CH0_CMR", "PWMC_CH0_CDTYR", "PWMC_CH0_CPRDR", "PWMC_CH0_CCNTR", "PWMC_CH0_CUPDR", "PWMC_CH0_Reserved" +group = "PWMC_CH1", "PWMC_CH1_CMR", "PWMC_CH1_CDTYR", "PWMC_CH1_CPRDR", "PWMC_CH1_CCNTR", "PWMC_CH1_CUPDR", "PWMC_CH1_Reserved" +group = "PWMC_CH2", "PWMC_CH2_CMR", "PWMC_CH2_CDTYR", "PWMC_CH2_CPRDR", "PWMC_CH2_CCNTR", "PWMC_CH2_CUPDR", "PWMC_CH2_Reserved" +group = "PWMC_CH3", "PWMC_CH3_CMR", "PWMC_CH3_CDTYR", "PWMC_CH3_CPRDR", "PWMC_CH3_CCNTR", "PWMC_CH3_CUPDR", "PWMC_CH3_Reserved" +group = "SSC", "SSC_CR", "SSC_CMR", "SSC_RCMR", "SSC_RFMR", "SSC_TCMR", "SSC_TFMR", "SSC_RHR", "SSC_THR", "SSC_RSHR", "SSC_TSHR", "SSC_SR", "SSC_IER", "SSC_IDR", "SSC_IMR" +group = "PDC_SSC", "SSC_RPR", "SSC_RCR", "SSC_TPR", "SSC_TCR", "SSC_RNPR", "SSC_RNCR", "SSC_TNPR", "SSC_TNCR", "SSC_PTCR", "SSC_PTSR" +group = "ADC", "ADC_CR", "ADC_MR", "ADC_CHER", "ADC_CHDR", "ADC_CHSR", "ADC_SR", "ADC_LCDR", "ADC_IER", "ADC_IDR", "ADC_IMR", "ADC_CDR0", "ADC_CDR1", "ADC_CDR2", "ADC_CDR3", "ADC_CDR4", "ADC_CDR5", "ADC_CDR6", "ADC_CDR7" +group = "PDC_ADC", "ADC_RPR", "ADC_RCR", "ADC_TPR", "ADC_TCR", "ADC_RNPR", "ADC_RNCR", "ADC_TNPR", "ADC_TNCR", "ADC_PTCR", "ADC_PTSR" +group = "SPI", "SPI_CR", "SPI_MR", "SPI_RDR", "SPI_TDR", "SPI_SR", "SPI_IER", "SPI_IDR", "SPI_IMR", "SPI_CSR" +group = "PDC_SPI", "SPI_RPR", "SPI_RCR", "SPI_TPR", "SPI_TCR", "SPI_RNPR", "SPI_RNCR", "SPI_TNPR", "SPI_TNCR", "SPI_PTCR", "SPI_PTSR" +group = "SYS" +group = "AIC", "AIC_SMR", "AIC_SVR", "AIC_IVR", "AIC_FVR", "AIC_ISR", "AIC_IPR", "AIC_IMR", "AIC_CISR", "AIC_IECR", "AIC_IDCR", "AIC_ICCR", "AIC_ISCR", "AIC_EOICR", "AIC_SPU", "AIC_DCR", "AIC_FFER", "AIC_FFDR", "AIC_FFSR" +group = "DBGU", "DBGU_CR", "DBGU_MR", "DBGU_IER", "DBGU_IDR", "DBGU_IMR", "DBGU_CSR", "DBGU_RHR", "DBGU_THR", "DBGU_BRGR", "DBGU_CIDR", "DBGU_EXID", "DBGU_FNTR" +group = "PDC_DBGU", "DBGU_RPR", "DBGU_RCR", "DBGU_TPR", "DBGU_TCR", "DBGU_RNPR", "DBGU_RNCR", "DBGU_TNPR", "DBGU_TNCR", "DBGU_PTCR", "DBGU_PTSR" +group = "PIOA", "PIOA_PER", "PIOA_PDR", "PIOA_PSR", "PIOA_OER", "PIOA_ODR", "PIOA_OSR", "PIOA_IFER", "PIOA_IFDR", "PIOA_IFSR", "PIOA_SODR", "PIOA_CODR", "PIOA_ODSR", "PIOA_PDSR", "PIOA_IER", "PIOA_IDR", "PIOA_IMR", "PIOA_ISR", "PIOA_MDER", "PIOA_MDDR", "PIOA_MDSR", "PIOA_PPUDR", "PIOA_PPUER", "PIOA_PPUSR", "PIOA_ASR", "PIOA_BSR", "PIOA_ABSR", "PIOA_OWER", "PIOA_OWDR", "PIOA_OWSR" +group = "PMC", "PMC_SCER", "PMC_SCDR", "PMC_SCSR", "PMC_PCER", "PMC_PCDR", "PMC_PCSR", "PMC_MOR", "PMC_MCFR", "PMC_PLLR", "PMC_MCKR", "PMC_PCKR", "PMC_IER", "PMC_IDR", "PMC_SR", "PMC_IMR" +group = "CKGR", "CKGR_MOR", "CKGR_MCFR", "CKGR_PLLR" +group = "RSTC", "RSTC_RCR", "RSTC_RSR", "RSTC_RMR" +group = "RTTC", "RTTC_RTMR", "RTTC_RTAR", "RTTC_RTVR", "RTTC_RTSR" +group = "PITC", "PITC_PIMR", "PITC_PISR", "PITC_PIVR", "PITC_PIIR" +group = "WDTC", "WDTC_WDCR", "WDTC_WDMR", "WDTC_WDSR" +group = "VREG", "VREG_MR" +group = "MC", "MC_RCR", "MC_ASR", "MC_AASR", "MC_FMR", "MC_FCR", "MC_FSR" diff --git a/AT91SAM7S256/SAM7S256/Tools/settings/LMS_ARM.dbgdt b/AT91SAM7S256/SAM7S256/Tools/settings/LMS_ARM.dbgdt new file mode 100644 index 0000000..092fee7 --- /dev/null +++ b/AT91SAM7S256/SAM7S256/Tools/settings/LMS_ARM.dbgdt @@ -0,0 +1,54 @@ + + + + + + + + + + + 152272727 + + + + + + 200100 + 300Build + 3002291424360 + 10010010010045527127225100100200300010300 + + + + + + + + TabID-16470-5520 + Workspace + Workspace + + + LMS_ARM + + + + 0TabID-17326-28629RegisterRegister0000TabID-9192-28577DisassemblyDisassemblyTabID-2396-28705WatchWatch11272251001001 + + + + + + TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\d_timer.h0000TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\SAM7S256\include\lib_at91sam7s64.h02825642564TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\d_display.r00591591TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\d_display.c015677677TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\d_hispeed.h00594594TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\d_hispeed.r00591591TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\d_hispeed.c00618618TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\c_sound.c06515515TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\d_sound.h00596596TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\d_sound.r00587587TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\d_sound.c030665665TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\c_sound.h00493493TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\d_timer.r020615615TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\d_button.c00619619TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\SAM7S256\include\ioat91sam7s64.h0000TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\SAM7S256\include\sam7s256.c00584584TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\d_ioctrl.r06738213821TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\SAM7S256\Include\Cstartup_SAM7.c05133363336TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\c_output.iom02811751175TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\SAM7S256\Include\Cstartup.s790010171017TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\d_loader.r00700700TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\d_loader.c0731763176TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\d_timer.c017679679TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\d_lowspeed.c08115631563TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\c_loader.iom0000TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\d_loader.h0000TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\m_sched.h08811521152TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\c_comm.c07526092609TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\d_usb.c06802351723517TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\c_button.c05011521152TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\c_display.c04771051010510TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\c_ioctrl.c03410251025TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\d_ioctrl.c015782782TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\m_sched.c04411961196TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\c_cmd.c01117315743157434TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\c_output.c03210821082TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\c_loader.c033160216020100000010000001 + + + + + + + iaridepm1debuggergui1-2-2624226-2-25548827225222656904624-2-2624245-2-2159140155273202312241210904624 + + + + diff --git a/AT91SAM7S256/SAM7S256/Tools/settings/LMS_ARM.dni b/AT91SAM7S256/SAM7S256/Tools/settings/LMS_ARM.dni new file mode 100644 index 0000000..409b4b4 --- /dev/null +++ b/AT91SAM7S256/SAM7S256/Tools/settings/LMS_ARM.dni @@ -0,0 +1,19 @@ +[JLinkDriver] +WatchVectorCatch=_ 0 +WatchCond=_ 0 +Watch0=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0 +Watch1=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0 +[DisAssemblyWindow] +NumStates=_ 1 +State 1=_ 1 +[Log file] +LoggingEnabled=_ 0 +LogFile=_ "" +Category=_ 0 +[TermIOLog] +LoggingEnabled=_ 0 +LogFile=_ "" +[Disassemble mode] +mode=0 +[Breakpoints] +Count=0 diff --git a/AT91SAM7S256/SAM7S256/Tools/settings/LMS_ARM.wsdt b/AT91SAM7S256/SAM7S256/Tools/settings/LMS_ARM.wsdt new file mode 100644 index 0000000..7183c3d --- /dev/null +++ b/AT91SAM7S256/SAM7S256/Tools/settings/LMS_ARM.wsdt @@ -0,0 +1,80 @@ + + + + + + LMS_ARM/Flash Debug + + + + + + + + 150272727 + + 1891724461 + + + + + + + + 45527 + + + + + + 1004142444 + 01044062754 + + + + + + + TabID-7290-5487 + Build + Build + + + + TabID-5721-5516 + Debug Log + Debug-Log + + + TabID-447-5816Find in FilesFind-in-Files + + 1 + + + TabID-32446-5425 + Workspace + Workspace + + + LMS_ARMLMS_ARM/c_led.c + + + + 0 + + + + + + TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\d_timer.h0000TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\SAM7S256\include\lib_at91sam7s64.h02825642564TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\d_display.r00591591TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\d_display.c015677677TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\d_hispeed.h00594594TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\d_hispeed.r00591591TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\d_hispeed.c00618618TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\c_sound.c06515515TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\d_sound.h00596596TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\d_sound.r00587587TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\d_sound.c030665665TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\c_sound.h00493493TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\d_timer.r020615615TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\d_button.c00619619TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\SAM7S256\include\ioat91sam7s64.h0000TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\SAM7S256\include\sam7s256.c00584584TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\d_ioctrl.r06738213821TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\SAM7S256\Include\Cstartup_SAM7.c05133363336TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\c_output.iom02811751175TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\SAM7S256\Include\Cstartup.s790010171017TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\d_loader.r00700700TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\d_loader.c0731763176TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\d_timer.c017679679TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\d_lowspeed.c08115631563TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\c_loader.iom0000TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\d_loader.h0000TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\m_sched.h08811521152TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\c_comm.c07526092609TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\d_usb.c06802351723517TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\c_button.c05011521152TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\c_display.c04771051010510TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\c_ioctrl.c03410251025TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\d_ioctrl.c015782782TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\m_sched.c04411961196TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\c_cmd.c01117315743157434TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\c_output.c03210821082TextEditorC:\Projects\LMS2006\Sys01\Main\Firmware\Source\c_loader.c033160216020100000010000001 + + + + + + + iaridepm1-2-2526241-2-20000237304763005-2-21221026-2-21028124100390617919000 + + + + diff --git a/AT91SAM7S256/Source/BtTest.inc b/AT91SAM7S256/Source/BtTest.inc new file mode 100644 index 0000000..b4626ab --- /dev/null +++ b/AT91SAM7S256/Source/BtTest.inc @@ -0,0 +1,1642 @@ +//******* TestPrg ************************************************************ + +#include "Test1.txt" +#include "Test2.txt" + + +extern void BtIo(void); + +const char BUILD_DATE[] = __DATE__; +const char BUILD_TIME[] = __TIME__; + +const char MONTH[] = "JanFebMarAprMajJunJulAugSepOktNovDec"; + +void GetProtocolVersion(UBYTE *String) +{ + sprintf((char*)String,"FW %2X.%02X",(FIRMWAREVERSION >> 8),FIRMWAREVERSION & 0x00FF); +} + + +void GetARMBuild(UBYTE *String) +{ + UWORD Tmp; + UWORD Lng; + char String1[4]; + char String2[4]; + + String1[0] = BUILD_DATE[4]; + String1[1] = BUILD_DATE[5]; + String1[2] = 0; + + Tmp = (UWORD)atoi(String1); + Lng = 0; + Lng += sprintf((char*)&String[Lng],"BUILD "); + Lng += sprintf((char*)&String[Lng],"%02u",Tmp); + + String1[0] = BUILD_DATE[0]; + String1[1] = BUILD_DATE[1]; + String1[2] = BUILD_DATE[2]; + String1[3] = 0; + String2[3] = 0; + + Tmp = 0; + do + { + String2[0] = MONTH[0 + 3 * Tmp]; + String2[1] = MONTH[1 + 3 * Tmp]; + String2[2] = MONTH[2 + 3 * Tmp]; + Tmp++; + } + while ((Tmp < 12) && (strcmp(String1,String2) != 0)); + + Lng += sprintf((char*)&String[Lng],"%02u",Tmp); + Lng += sprintf((char*)&String[Lng],"%c%c",BUILD_DATE[9],BUILD_DATE[10]); + Lng += sprintf((char*)&String[Lng],"%c%c",BUILD_TIME[0],BUILD_TIME[1]); + Lng += sprintf((char*)&String[Lng],"%c%c",BUILD_TIME[3],BUILD_TIME[4]); +} + + +void GetBC4Build(UBYTE *String) +{ + sprintf((char*)String,"BC4 %2X.%02X",pMapComm->BrickData.BluecoreVersion[1],pMapComm->BrickData.BluecoreVersion[0]); +} + + +void GetAVRBuild(UBYTE *String) +{ + sprintf((char*)String,"AVR %1u.%02u",((IoFromAvr.Battery >> 13) & 3),((IoFromAvr.Battery >> 10) & 7)); +} + + +void GetBC4Address(UBYTE *String) +{ + UWORD Count; + UBYTE Tmp; + + Count = (UWORD)sprintf((char*)String,"ID "); + for (Tmp = 0;(Tmp < (SIZE_OF_BDADDR - 1)) && (Count <= (DISPLAYLINE_LENGTH - 2));Tmp++) + { + Count += (UWORD)sprintf((char*)&String[Count],"%02X",(UWORD)(pMapComm->BrickData.BdAddr[Tmp]) & 0xFF); + } +} + + +enum TSTPRG +{ + SYSTEM_INIT = 1, + SYSTEM_UNLOCK_INIT, + SYSTEM_UNLOCK, + SYSTEM_PAGE, + TIMER_INIT, + TIMER_SHOW, + TIMER_HOLD, + BT_PAGE, + BT_RESET, + BT_RESETTING, + BT_LIST_INIT, + BT_LIST, + BT_CONN_INIT, + BT_CONN, + BT_UPDATE_FW, + TSTPRG_INIT, + TSTPRG_SELECT_SUBTEST, + + TSTPRG_SENSOR_INIT, + TSTPRG_SELECT_SENSOR, + TSTPRG_TOUCH_SENSOR_INIT, + TSTPRG_TOUCH_SENSOR, + TSTPRG_SOUND_SENSOR_SELECT, + TSTPRG_SOUND_SENSOR_INIT, + TSTPRG_SOUND_SENSOR, + TSTPRG_LIGHT_SENSOR_SELECT, + TSTPRG_LIGHT_SENSOR_INIT, + TSTPRG_LIGHT_SENSOR, + TSTPRG_SKIP_SENSOR, + + TSTPRG_RCX_INIT, + TSTPRG_RCX_SELECT, + TSTPRG_RCX_DISPLAY_INIT, + TSTPRG_RCX_DISPLAY, + TSTPRG_RCX_INPUT_SELECT, + TSTPRG_RCX_INPUT_INIT, + TSTPRG_RCX_INPUT, + TSTPRG_RCX_DIGITAL_INIT, + TSTPRG_RCX_DIGITAL_OK, + TSTPRG_RCX_DIGITAL_FAIL, + TSTPRG_RCX_DIGITAL, + TSTPRG_RCX_MOTOR_INIT, + TSTPRG_RCX_MOTOR, + TSTPRG_SKIP_RCX_MOTOR, + TSTPRG_SKIP_RCX, + + TSTPRG_MOTOR_INIT, + TSTPRG_MOTOR, + TSTPRG_SKIP_MOTOR, + + TSTPRG_SKIP, + TSTPRG_WAIT +}; + +const UBYTE TXT_EMPTY[] = " "; +const UBYTE TXT_LINE[] = "----------------"; + +#ifdef TESTPRG + +const UBYTE TXT_TEST[] = "Timer Test Bt "; + +const UBYTE TXT_TIMER[] = "Reset Hold "; +const UBYTE TXT_TIMER_HOLD[] = " Continue "; + +const UBYTE TXT_LAST[] = "Last UI->BT Cmd."; +const UBYTE TXT_BT_PAGE[] = "Reset List BtIo"; + +const UBYTE TXT_RESETTING[] = " Resetting! "; + +const UBYTE TXT_BT_LIST[] = "Down ConTab Up "; +const UBYTE TXT_BT_CONN[] = "Down Update Up "; + +const UBYTE TXT_BTUPDATE[] = "BT update mode !"; +const UBYTE TXT_DONE[] = " When done "; +const UBYTE TXT_RESET[] = " activate reset "; +const UBYTE TXT_REBOOT[] = "button to reboot"; + +const UBYTE TXT_TESTPRG[] = " TestPrg V0.08 "; +const UBYTE TXT_SELECT[] = "Select sub test "; +const UBYTE TXT_SUBTEST[] = "Sens. RCX Motor"; + +const UBYTE TXT_SELECT_SENSOR[] = " Select sensor "; +const UBYTE TXT_SENSORS[] = "Touch Snd. Light"; + +const UBYTE TXT_SELECT_TYPE[] = " Select type "; +const UBYTE TXT_SOUND_SENSORS[] = " DB DBA "; +const UBYTE TXT_LIGHT_SENSORS[] = "Pasive Active"; + +const UBYTE TXT_SENSOR_TOUCH[] = "Touch Sensor Tst"; +const UBYTE TXT_SENSOR_SOUND_DB[] = "DB Sound Sens."; +const UBYTE TXT_SENSOR_SOUND_DBA[] = "DBA Sound Sens."; +const UBYTE TXT_SOUND_STOP[] = "440Hz Stop 4KHz"; +const UBYTE TXT_SENSOR_LIGHT_PASIVE[] = "Pas. Light Sens."; +const UBYTE TXT_SENSOR_LIGHT_ACTIVE[] = "Act. Light Sens."; + +const UBYTE TXT_SUBTEST_STOP[] = " Stop "; + +const UBYTE TXT_MOTOR[] = " Motor test "; +const UBYTE TXT_MOTOR_HEADER[] = "Outp Set Cnt"; +const UBYTE TXT_MOTOR_STOP[] = "Bwd Stop Fwd"; + +const UBYTE TXT_RCX[] = " RCX test "; +const UBYTE TXT_RCX_STOP[] = "Inp Disp Outp"; +const UBYTE TXT_RCX_INPUT_PASIVE[] = "Input pasive Tst"; +const UBYTE TXT_RCX_INPUT_ACTIVE[] = "Input active Tst"; +const UBYTE TXT_RCX_INPUT_SELECT[] = "Pas. Act. Dig."; +const UBYTE TXT_RCX_INPUT_DIGITAL[] = "Digital I/O Tst"; +const UBYTE TXT_RCX_DIGITAL_OK[] = " OK "; +const UBYTE TXT_RCX_DIGITAL_FAIL[] = " FAIL "; +const UBYTE TXT_MOTOR_NEXT[] = "Bwd Next Fwd"; + + +void TestPrgRunMotor(UBYTE No,SBYTE Speed) +{ + pMapOutPut->Outputs[No].Mode = MOTORON | BRAKE; + pMapOutPut->Outputs[No].Speed = Speed; + pMapOutPut->Outputs[No].TachoLimit = 0; + pMapOutPut->Outputs[No].RunState = MOTOR_RUN_STATE_RUNNING; + pMapOutPut->Outputs[No].Flags = UPDATE_MODE | UPDATE_SPEED | UPDATE_TACHO_LIMIT; +} + +void TestPrgFloatMotor(UBYTE No) +{ + pMapOutPut->Outputs[No].Mode = 0; + pMapOutPut->Outputs[No].Speed = 0; + pMapOutPut->Outputs[No].TachoLimit = 0; + pMapOutPut->Outputs[No].RunState = MOTOR_RUN_STATE_RUNNING; + pMapOutPut->Outputs[No].Flags = UPDATE_MODE | UPDATE_SPEED | UPDATE_TACHO_LIMIT; +} + +SBYTE TestPrgReadMotor(UBYTE No) +{ + return ((SBYTE)(pMapOutPut->Outputs[No].TachoCnt / 360)); +} + +#endif + + +UBYTE TestPrg(UBYTE Dummy) +{ + static UWORD Count; + static UBYTE TxtBuffer[TEXTLINES][DISPLAYLINE_LENGTH + 1]; + static UBYTE State = SYSTEM_INIT; +#ifdef TESTPRG + static UWORD Pointer; + static UWORD InputValues[NO_OF_INPUTS]; + static SWORD OutputValues[NO_OF_OUTPUTS]; + static UBYTE VolumeSave; + static UBYTE Timer; + static UBYTE SubState = 0; + UBYTE Tmp; +#endif + + Dummy = Dummy; + switch (State) + { + case SYSTEM_INIT : + { + GetProtocolVersion(TxtBuffer[0]); + GetAVRBuild(TxtBuffer[1]); + GetBC4Build(TxtBuffer[2]); + GetARMBuild(TxtBuffer[3]); + GetBC4Address(TxtBuffer[4]); + + pMapDisplay->pTextLines[TEXTLINE_3] = (UBYTE*)TxtBuffer[0]; + pMapDisplay->pTextLines[TEXTLINE_4] = (UBYTE*)TxtBuffer[1]; + pMapDisplay->pTextLines[TEXTLINE_5] = (UBYTE*)TxtBuffer[2]; + pMapDisplay->pTextLines[TEXTLINE_6] = (UBYTE*)TxtBuffer[3]; + pMapDisplay->pTextLines[TEXTLINE_7] = (UBYTE*)TxtBuffer[4]; + pMapDisplay->pTextLines[TEXTLINE_8] = (UBYTE*)TXT_EMPTY; + pMapDisplay->UpdateMask |= (TEXTLINE_BIT(TEXTLINE_3) | TEXTLINE_BIT(TEXTLINE_4) | TEXTLINE_BIT(TEXTLINE_5) | TEXTLINE_BIT(TEXTLINE_6) | TEXTLINE_BIT(TEXTLINE_7) | TEXTLINE_BIT(TEXTLINE_8)); + +#ifdef TESTPRG + SubState = 0; +#endif + State = SYSTEM_UNLOCK_INIT; + } + break; + +#ifndef TESTPRG + + case SYSTEM_UNLOCK_INIT : // ENTER * 1 + LEFT * 3 + RIGHT * 2 + ENTER * 1 = TEST MENU + { + if (cUiReadButtons() != BUTTON_NONE) + { + State = TSTPRG_SKIP; + } + } + break; + +#else + + case SYSTEM_UNLOCK_INIT : // ENTER * 1 + LEFT * 3 + RIGHT * 2 + ENTER * 1 = TEST MENU + { + Tmp = cUiReadButtons(); + switch (Tmp) + { + case BUTTON_ENTER : + { + switch (SubState) + { + case 0 : + { + SubState = 1; + Pointer = 0; + Count = 0; + } + break; + + case 3 : + { + State = SYSTEM_UNLOCK; + } + break; + + default : + { + Tmp = BUTTON_EXIT; + } + break; + + } + } + break; + + case BUTTON_NONE : + { + } + break; + + default : + { + switch (SubState) + { + case 0 : + { + Tmp = BUTTON_EXIT; + } + break; + + case 1 : + { + if (Tmp == BUTTON_LEFT) + { + if (++Count >= 3) + { + Count = 0; + SubState = 2; + } + Pointer = 0; + } + else + { + Tmp = BUTTON_EXIT; + } + } + break; + + case 2 : + { + if (Tmp == BUTTON_RIGHT) + { + if (++Count >= 2) + { + SubState = 3; + } + Pointer = 0; + } + else + { + Tmp = BUTTON_EXIT; + } + } + break; + + } + } + break; + + } + Pointer++; + if (((SubState) && (Pointer > 500)) || (Tmp == BUTTON_EXIT)) + { + State = TSTPRG_SKIP; + } + } + break; + + case SYSTEM_UNLOCK : + { + pMapDisplay->pTextLines[TEXTLINE_8] = (UBYTE*)TXT_TEST; + pMapDisplay->UpdateMask |= TEXTLINE_BIT(TEXTLINE_8); + State = SYSTEM_PAGE; + } + break; + + case SYSTEM_PAGE : + { + switch (cUiReadButtons()) + { + case BUTTON_ENTER : + { + IOMapUi.Flags &= ~UI_ENABLE_STATUS_UPDATE; + pMapDisplay->EraseMask |= SCREEN_BIT(SCREEN_BACKGROUND); + State = TSTPRG_INIT; + } + break; + + case BUTTON_EXIT : + { + Count = 0; + State = TSTPRG_SKIP; + } + break; + + case BUTTON_LEFT : + { + IOMapUi.Flags &= ~UI_ENABLE_STATUS_UPDATE; + pMapDisplay->EraseMask |= SCREEN_BIT(SCREEN_BACKGROUND); + pMapDisplay->pTextLines[TEXTLINE_1] = (UBYTE*)TXT_EMPTY; + pMapDisplay->pTextLines[TEXTLINE_2] = (UBYTE*)TXT_EMPTY; + pMapDisplay->pTextLines[TEXTLINE_3] = (UBYTE*)TXT_EMPTY; + pMapDisplay->pTextLines[TEXTLINE_4] = (UBYTE*)TXT_EMPTY; + pMapDisplay->pTextLines[TEXTLINE_5] = (UBYTE*)TXT_EMPTY; + pMapDisplay->pTextLines[TEXTLINE_6] = (UBYTE*)TXT_EMPTY; + pMapDisplay->pTextLines[TEXTLINE_7] = (UBYTE*)TXT_EMPTY; + pMapDisplay->pTextLines[TEXTLINE_8] = (UBYTE*)TXT_TIMER; + pMapDisplay->EraseMask |= TEXTLINE_BITS; + pMapDisplay->UpdateMask |= TEXTLINE_BITS; + State = TIMER_INIT; + } + break; + + case BUTTON_RIGHT : + { + IOMapUi.Flags &= ~UI_ENABLE_STATUS_UPDATE; + pMapDisplay->EraseMask |= SCREEN_BIT(SCREEN_BACKGROUND); + pMapDisplay->pTextLines[TEXTLINE_1] = (UBYTE*)TXT_EMPTY; + pMapDisplay->pTextLines[TEXTLINE_2] = (UBYTE*)TXT_EMPTY; + pMapDisplay->pTextLines[TEXTLINE_3] = (UBYTE*)TXT_EMPTY; + pMapDisplay->pTextLines[TEXTLINE_4] = (UBYTE*)TXT_EMPTY; + pMapDisplay->pTextLines[TEXTLINE_5] = (UBYTE*)TXT_EMPTY; + pMapDisplay->pTextLines[TEXTLINE_6] = (UBYTE*)TXT_EMPTY; + pMapDisplay->pTextLines[TEXTLINE_7] = (UBYTE*)TXT_EMPTY; + pMapDisplay->pTextLines[TEXTLINE_8] = (UBYTE*)TXT_BT_PAGE; + if (DISPLAYLINE_LENGTH >= 16) + { + sprintf((char*)TxtBuffer[2],"Command %02X",(UWORD)VarsUi.BTCommand & 0xFF); + sprintf((char*)TxtBuffer[3],"Parameter 1 %02X",(UWORD)VarsUi.BTPar1 & 0xFF); + sprintf((char*)TxtBuffer[4],"Parameter 2 %02X",(UWORD)VarsUi.BTPar2 & 0xFF); + sprintf((char*)TxtBuffer[5],"Result %04X",(UWORD)VarsUi.BTResult); + pMapDisplay->pTextLines[TEXTLINE_1] = (UBYTE*)TXT_LAST; + pMapDisplay->pTextLines[TEXTLINE_2] = (UBYTE*)TXT_LINE; + pMapDisplay->pTextLines[TEXTLINE_3] = TxtBuffer[2]; + pMapDisplay->pTextLines[TEXTLINE_4] = TxtBuffer[3]; + pMapDisplay->pTextLines[TEXTLINE_5] = TxtBuffer[4]; + pMapDisplay->pTextLines[TEXTLINE_6] = TxtBuffer[5]; + } + pMapDisplay->EraseMask |= TEXTLINE_BITS; + pMapDisplay->UpdateMask |= TEXTLINE_BITS; + State = BT_PAGE; + } + break; + + } + } + break; + + case TIMER_INIT : + { + State = TIMER_SHOW; + } + break; + + case TIMER_SHOW : + { + sprintf((char*)TxtBuffer[2]," %10lu mS ",VarsUi.CRPasskey); + pMapDisplay->pTextLines[TEXTLINE_3] = TxtBuffer[2]; + pMapDisplay->UpdateMask |= TEXTLINE_BIT(TEXTLINE_3); + + switch (cUiReadButtons()) + { + case BUTTON_ENTER : + { + pMapDisplay->pTextLines[TEXTLINE_8] = (UBYTE*)TXT_TIMER_HOLD; + pMapDisplay->UpdateMask |= TEXTLINE_BIT(TEXTLINE_8); + State = TIMER_HOLD; + } + break; + + case BUTTON_LEFT : + { + pMapDisplay->EraseMask |= TEXTLINE_BIT(TEXTLINE_3); + VarsUi.CRPasskey = 0L; + } + break; + + case BUTTON_EXIT : + { + State = TSTPRG_SKIP; + } + break; + + } + } + break; + + case TIMER_HOLD : + { + switch (cUiReadButtons()) + { + case BUTTON_ENTER : + { + pMapDisplay->pTextLines[TEXTLINE_8] = (UBYTE*)TXT_TIMER; + pMapDisplay->UpdateMask |= TEXTLINE_BIT(TEXTLINE_8); + State = TIMER_SHOW; + } + break; + + case BUTTON_EXIT : + { + State = TSTPRG_SKIP; + } + break; + + } + } + break; + + case BT_PAGE : + { + switch (cUiReadButtons()) + { + case BUTTON_ENTER : + { + for (Count = 0;Count < TEXTLINES;Count++) + { + strcpy((char*)TxtBuffer[Count],(char*)TXT_EMPTY); + pMapDisplay->pTextLines[TEXTLINE_1 + Count] = TxtBuffer[Count]; + } + pMapDisplay->pTextLines[TEXTLINE_2] = (UBYTE*)TXT_LINE; + pMapDisplay->pTextLines[TEXTLINE_8] = (UBYTE*)TXT_BT_LIST; + pMapDisplay->EraseMask |= TEXTLINE_BITS; + pMapDisplay->UpdateMask |= TEXTLINE_BITS; + Pointer = 0; + State = BT_LIST_INIT; + } + break; + + case BUTTON_EXIT : + { + Count = 0; + State = TSTPRG_SKIP; + } + break; + + case BUTTON_LEFT : + { + State = BT_RESET; + } + break; + + case BUTTON_RIGHT : + { + pMapDisplay->pTextLines[TEXTLINE_1] = (UBYTE*)TXT_BTUPDATE; + pMapDisplay->pTextLines[TEXTLINE_2] = (UBYTE*)TXT_LINE; + pMapDisplay->pTextLines[TEXTLINE_3] = (UBYTE*)TXT_EMPTY; + pMapDisplay->pTextLines[TEXTLINE_4] = (UBYTE*)TXT_DONE; + pMapDisplay->pTextLines[TEXTLINE_5] = (UBYTE*)TXT_RESET; + pMapDisplay->pTextLines[TEXTLINE_6] = (UBYTE*)TXT_REBOOT; + pMapDisplay->pTextLines[TEXTLINE_7] = (UBYTE*)TXT_EMPTY; + pMapDisplay->pTextLines[TEXTLINE_8] = (UBYTE*)TXT_EMPTY; + pMapDisplay->EraseMask |= TEXTLINE_BITS; + pMapDisplay->UpdateMask |= TEXTLINE_BITS; + Timer = 0; + State = BT_UPDATE_FW; + } + break; + + } + } + break; + + case BT_RESET : + { + VarsUi.BTCommand = (UBYTE)FACTORYRESET; + VarsUi.BTPar1 = (UBYTE)0; + VarsUi.BTPar2 = (UBYTE)0; + if (pMapComm->pFunc(VarsUi.BTCommand,VarsUi.BTPar1,VarsUi.BTPar2,0,NULL,&(VarsUi.BTResult)) == SUCCESS) + { + pMapDisplay->pTextLines[TEXTLINE_1] = (UBYTE*)TXT_EMPTY; + pMapDisplay->pTextLines[TEXTLINE_2] = (UBYTE*)TXT_EMPTY; + pMapDisplay->pTextLines[TEXTLINE_3] = (UBYTE*)TXT_EMPTY; + pMapDisplay->pTextLines[TEXTLINE_4] = (UBYTE*)TXT_RESETTING; + pMapDisplay->pTextLines[TEXTLINE_5] = (UBYTE*)TXT_EMPTY; + pMapDisplay->pTextLines[TEXTLINE_6] = (UBYTE*)TXT_EMPTY; + pMapDisplay->pTextLines[TEXTLINE_7] = (UBYTE*)TXT_EMPTY; + pMapDisplay->pTextLines[TEXTLINE_8] = (UBYTE*)TXT_EMPTY; + pMapDisplay->EraseMask |= TEXTLINE_BITS; + pMapDisplay->UpdateMask |= TEXTLINE_BITS; + State = BT_RESETTING; + } + else + { + State = TSTPRG_SKIP; + } + } + break; + + case BT_RESETTING : + { + if (VarsUi.BTResult != INPROGRESS) + { + State = TSTPRG_SKIP; + } + } + break; + + case BT_UPDATE_FW : + { + if (++Timer >= 100) + { + BtIo(); + } + } + break; + + case BT_LIST_INIT : + { + sprintf((char*)TxtBuffer[0],"DeviceTable No%2u",Pointer); + sprintf((char*)TxtBuffer[2],"%-*.*s",DISPLAYLINE_LENGTH,DISPLAYLINE_LENGTH,(char*)pMapComm->BtDeviceTable[Pointer].Name); + Count = (UWORD)sprintf((char*)TxtBuffer[3],"COD="); + for (Tmp = 0;(Tmp < SIZE_OF_CLASS_OF_DEVICE) && (Count < (DISPLAYLINE_LENGTH - 2));Tmp++) + { + Count += (UWORD)sprintf((char*)&TxtBuffer[3][Count],"%02X",(UWORD)(pMapComm->BtDeviceTable[Pointer].ClassOfDevice[Tmp]) & 0xFF); + } + Count = (UWORD)sprintf((char*)TxtBuffer[4],"A="); + for (Tmp = 0;(Tmp < SIZE_OF_BDADDR) && (Count <= (DISPLAYLINE_LENGTH - 2));Tmp++) + { + Count += (UWORD)sprintf((char*)&TxtBuffer[4][Count],"%02X",(UWORD)(pMapComm->BtDeviceTable[Pointer].BdAddr[Tmp]) & 0xFF); + } + sprintf((char*)TxtBuffer[5],"Status=%02X",(UWORD)(pMapComm->BtDeviceTable[Pointer].DeviceStatus) & 0xFF); + pMapDisplay->EraseMask |= TEXTLINE_BITS; + pMapDisplay->UpdateMask |= TEXTLINE_BITS; + State = BT_LIST; + } + break; + + case BT_LIST : + { + switch (cUiReadButtons()) + { + case BUTTON_ENTER : + { + for (Count = 0;Count < TEXTLINES;Count++) + { + strcpy((char*)TxtBuffer[Count],(char*)TXT_EMPTY); + pMapDisplay->pTextLines[TEXTLINE_1 + Count] = TxtBuffer[Count]; + } + pMapDisplay->pTextLines[TEXTLINE_2] = (UBYTE*)TXT_LINE; + pMapDisplay->pTextLines[TEXTLINE_8] = (UBYTE*)TXT_BT_CONN; + pMapDisplay->EraseMask |= TEXTLINE_BITS; + pMapDisplay->UpdateMask |= TEXTLINE_BITS; + Pointer = 0; + State = BT_CONN_INIT; + } + break; + + case BUTTON_EXIT : + { + State = SYSTEM_INIT; + } + break; + + case BUTTON_LEFT : + { + if (Pointer) + { + Pointer--; + } + else + { + Pointer = (SIZE_OF_BT_DEVICE_TABLE - 1); + } + State = BT_LIST_INIT; + } + break; + + case BUTTON_RIGHT : + { + if (Pointer < (SIZE_OF_BT_DEVICE_TABLE - 1)) + { + Pointer++; + } + else + { + Pointer = 0; + } + State = BT_LIST_INIT; + } + break; + + } + } + break; + + case BT_CONN_INIT : + { + sprintf((char*)TxtBuffer[0],"Conn. Table No%2u",Pointer); + sprintf((char*)TxtBuffer[2],"%-*.*s",DISPLAYLINE_LENGTH,DISPLAYLINE_LENGTH,(char*)pMapComm->BtConnectTable[Pointer].Name); + Count = (UWORD)sprintf((char*)TxtBuffer[3],"COD="); + for (Tmp = 0;(Tmp < SIZE_OF_CLASS_OF_DEVICE) && (Count < (DISPLAYLINE_LENGTH - 2));Tmp++) + { + Count += (UWORD)sprintf((char*)&TxtBuffer[3][Count],"%02X",(UWORD)(pMapComm->BtConnectTable[Pointer].ClassOfDevice[Tmp]) & 0xFF); + } + Count = (UWORD)sprintf((char*)TxtBuffer[4],"A="); + for (Tmp = 0;(Tmp < SIZE_OF_BDADDR) && (Count <= (DISPLAYLINE_LENGTH - 2));Tmp++) + { + Count += (UWORD)sprintf((char*)&TxtBuffer[4][Count],"%02X",(UWORD)(pMapComm->BtConnectTable[Pointer].BdAddr[Tmp]) & 0xFF); + } + sprintf((char*)TxtBuffer[5],"%-*.*s",DISPLAYLINE_LENGTH,DISPLAYLINE_LENGTH,(char*)pMapComm->BtConnectTable[Pointer].PinCode); + if (DISPLAYLINE_LENGTH >= 16) + { + sprintf((char*)TxtBuffer[6],"H=%02X S=%02X Q=%02X",(UWORD)(pMapComm->BtConnectTable[Pointer].HandleNr) & 0xFF,(UWORD)(pMapComm->BtConnectTable[Pointer].StreamStatus) & 0xFF,(UWORD)(pMapComm->BtConnectTable[Pointer].LinkQuality) & 0xFF); + } + pMapDisplay->EraseMask |= TEXTLINE_BITS; + pMapDisplay->UpdateMask |= TEXTLINE_BITS; + State = BT_CONN; + } + break; + + case BT_CONN : + { + switch (cUiReadButtons()) + { + case BUTTON_ENTER : + { + State = BT_CONN_INIT; + } + break; + + case BUTTON_EXIT : + { + State = SYSTEM_INIT; + } + break; + + case BUTTON_LEFT : + { + if (Pointer) + { + Pointer--; + } + else + { + Pointer = (SIZE_OF_BT_CONNECT_TABLE - 1); + } + State = BT_CONN_INIT; + } + break; + + case BUTTON_RIGHT : + { + if (Pointer < (SIZE_OF_BT_CONNECT_TABLE - 1)) + { + Pointer++; + } + else + { + Pointer = 0; + } + State = BT_CONN_INIT; + } + break; + + } + } + break; + + case TSTPRG_INIT : + { + IOMapUi.Flags &= ~UI_ENABLE_STATUS_UPDATE; + + pMapDisplay->EraseMask |= SCREEN_BIT(SCREEN_BACKGROUND); + + pMapDisplay->pTextLines[TEXTLINE_1] = (UBYTE*)TXT_TESTPRG; + pMapDisplay->pTextLines[TEXTLINE_2] = (UBYTE*)TXT_LINE; + pMapDisplay->pTextLines[TEXTLINE_3] = (UBYTE*)TXT_EMPTY; + pMapDisplay->pTextLines[TEXTLINE_4] = (UBYTE*)TXT_EMPTY; + pMapDisplay->pTextLines[TEXTLINE_5] = (UBYTE*)TXT_SELECT; + pMapDisplay->pTextLines[TEXTLINE_6] = (UBYTE*)TXT_EMPTY; + pMapDisplay->pTextLines[TEXTLINE_7] = (UBYTE*)TXT_EMPTY; + pMapDisplay->pTextLines[TEXTLINE_8] = (UBYTE*)TXT_SUBTEST; + pMapDisplay->UpdateMask |= TEXTLINE_BITS; + + State = TSTPRG_SELECT_SUBTEST; + } + break; + + case TSTPRG_SELECT_SUBTEST : + { + switch (cUiReadButtons()) + { + case BUTTON_LEFT : + { + State = TSTPRG_SENSOR_INIT; + } + break; + + case BUTTON_RIGHT : + { + State = TSTPRG_MOTOR_INIT; + } + break; + + case BUTTON_ENTER : + { + State = TSTPRG_RCX_INIT; + } + break; + + case BUTTON_EXIT : + { + Count = 0; + State = TSTPRG_SKIP; + } + break; + + } + } + break; + + case TSTPRG_SENSOR_INIT : + { + pMapDisplay->pTextLines[TEXTLINE_1] = (UBYTE*)TXT_TESTPRG; + pMapDisplay->pTextLines[TEXTLINE_2] = (UBYTE*)TXT_LINE; + pMapDisplay->pTextLines[TEXTLINE_3] = (UBYTE*)TXT_EMPTY; + pMapDisplay->pTextLines[TEXTLINE_4] = (UBYTE*)TXT_EMPTY; + pMapDisplay->pTextLines[TEXTLINE_5] = (UBYTE*)TXT_SELECT_SENSOR; + pMapDisplay->pTextLines[TEXTLINE_6] = (UBYTE*)TXT_EMPTY; + pMapDisplay->pTextLines[TEXTLINE_7] = (UBYTE*)TXT_EMPTY; + pMapDisplay->pTextLines[TEXTLINE_8] = (UBYTE*)TXT_SENSORS; + pMapDisplay->UpdateMask |= TEXTLINE_BITS; + + for (Count = 0;Count < NO_OF_INPUTS;Count++) + { + InputValues[Count] = 0x7FFF; + strcpy((char*)TxtBuffer[Count]," "); + } + + State = TSTPRG_SELECT_SENSOR; + } + break; + + case TSTPRG_SELECT_SENSOR : + { + switch (cUiReadButtons()) + { + case BUTTON_LEFT : + { + State = TSTPRG_TOUCH_SENSOR_INIT; + } + break; + + case BUTTON_ENTER : + { + pMapDisplay->pTextLines[TEXTLINE_5] = (UBYTE*)TXT_SELECT_TYPE; + pMapDisplay->pTextLines[TEXTLINE_8] = (UBYTE*)TXT_SOUND_SENSORS; + pMapDisplay->UpdateMask |= TEXTLINE_BITS; + State = TSTPRG_SOUND_SENSOR_SELECT; + } + break; + + case BUTTON_RIGHT : + { + pMapDisplay->pTextLines[TEXTLINE_5] = (UBYTE*)TXT_SELECT_TYPE; + pMapDisplay->pTextLines[TEXTLINE_8] = (UBYTE*)TXT_LIGHT_SENSORS; + pMapDisplay->UpdateMask |= TEXTLINE_BITS; + State = TSTPRG_LIGHT_SENSOR_SELECT; + } + break; + + case BUTTON_EXIT : + { + State = TSTPRG_INIT; + } + break; + + } + } + break; + + case TSTPRG_TOUCH_SENSOR_INIT : + { + for (Count = 0;Count < NO_OF_INPUTS;Count++) + { + pMapDisplay->pTextLines[TEXTLINE_3 + Count] = TxtBuffer[Count]; + } + pMapDisplay->pTextLines[TEXTLINE_1] = (UBYTE*)TXT_SENSOR_TOUCH; + pMapDisplay->pTextLines[TEXTLINE_8] = (UBYTE*)TXT_SUBTEST_STOP; + pMapDisplay->UpdateMask |= TEXTLINE_BITS; + for (Count = 0;Count < NO_OF_INPUTS;Count++) + { + pMapInput->Inputs[Count].SensorType = SWITCH; + } + State = TSTPRG_TOUCH_SENSOR; + } + break; + + case TSTPRG_TOUCH_SENSOR : + { + for (Count = 0;Count < NO_OF_INPUTS;Count++) + { + if (InputValues[Count] != pMapInput->Inputs[Count].ADRaw) + { + InputValues[Count] = pMapInput->Inputs[Count].ADRaw; + sprintf((char*)TxtBuffer[Count]," Input %u = %4u ",(UWORD)Count + 1,(UWORD)InputValues[Count]); + pMapDisplay->UpdateMask |= TEXTLINE_BIT(TEXTLINE_3 + Count); + } + } + if (cUiReadButtons() != BUTTON_NONE) + { + State = TSTPRG_SKIP_SENSOR; + } + } + break; + + case TSTPRG_SOUND_SENSOR_SELECT : + { + switch (cUiReadButtons()) + { + case BUTTON_LEFT : + { + pMapDisplay->pTextLines[TEXTLINE_1] = (UBYTE*)TXT_SENSOR_SOUND_DB; + for (Count = 0;Count < NO_OF_INPUTS;Count++) + { + pMapInput->Inputs[Count].SensorType = SOUND_DB; + } + State = TSTPRG_SOUND_SENSOR_INIT; + } + break; + + case BUTTON_ENTER : + { + State = TSTPRG_SKIP_SENSOR; + } + break; + + case BUTTON_EXIT : + { + State = TSTPRG_SKIP_SENSOR; + } + break; + + case BUTTON_RIGHT : + { + pMapDisplay->pTextLines[TEXTLINE_1] = (UBYTE*)TXT_SENSOR_SOUND_DBA; + for (Count = 0;Count < NO_OF_INPUTS;Count++) + { + pMapInput->Inputs[Count].SensorType = SOUND_DBA; + } + State = TSTPRG_SOUND_SENSOR_INIT; + } + break; + + } + } + break; + + case TSTPRG_SOUND_SENSOR_INIT : + { + VolumeSave = pMapSound->Volume; + pMapSound->Volume = MAX_VOLUME; + for (Count = 0;Count < NO_OF_INPUTS;Count++) + { + pMapDisplay->pTextLines[TEXTLINE_3 + Count] = TxtBuffer[Count]; + } + pMapDisplay->pTextLines[TEXTLINE_8] = (UBYTE*)TXT_SOUND_STOP; + pMapDisplay->UpdateMask |= TEXTLINE_BITS; + State = TSTPRG_SOUND_SENSOR; + } + break; + + case TSTPRG_SOUND_SENSOR : + { + for (Count = 0;Count < NO_OF_INPUTS;Count++) + { + if (InputValues[Count] != pMapInput->Inputs[Count].ADRaw) + { + InputValues[Count] = pMapInput->Inputs[Count].ADRaw; + sprintf((char*)TxtBuffer[Count]," Input %u = %4u ",(UWORD)Count + 1,(UWORD)InputValues[Count]); + pMapDisplay->UpdateMask |= TEXTLINE_BIT(TEXTLINE_3 + Count); + } + } + switch (cUiReadButtons()) + { + case BUTTON_LEFT : + { + pMapSound->Freq = 440; + pMapSound->Duration = 2000; + pMapSound->Mode = SOUND_TONE; + pMapSound->Flags |= SOUND_UPDATE; + } + break; + + case BUTTON_ENTER : + { + pMapSound->State = SOUND_STOP; + pMapSound->Volume = VolumeSave; + State = TSTPRG_SKIP_SENSOR; + } + break; + + case BUTTON_EXIT : + { + pMapSound->State = SOUND_STOP; + pMapSound->Volume = VolumeSave; + State = TSTPRG_SKIP_SENSOR; + } + break; + + case BUTTON_RIGHT : + { + pMapSound->Freq = 4000; + pMapSound->Duration = 2000; + pMapSound->Mode = SOUND_TONE; + pMapSound->Flags |= SOUND_UPDATE; + } + break; + + } + } + break; + + case TSTPRG_LIGHT_SENSOR_SELECT : + { + switch (cUiReadButtons()) + { + case BUTTON_LEFT : + { + pMapDisplay->pTextLines[TEXTLINE_1] = (UBYTE*)TXT_SENSOR_LIGHT_PASIVE; + for (Count = 0;Count < NO_OF_INPUTS;Count++) + { + pMapInput->Inputs[Count].SensorType = LIGHT_INACTIVE; + } + State = TSTPRG_LIGHT_SENSOR_INIT; + } + break; + + case BUTTON_ENTER : + { + State = TSTPRG_SKIP_SENSOR; + } + break; + + case BUTTON_EXIT : + { + State = TSTPRG_SKIP_SENSOR; + } + break; + + case BUTTON_RIGHT : + { + pMapDisplay->pTextLines[TEXTLINE_1] = (UBYTE*)TXT_SENSOR_LIGHT_ACTIVE; + for (Count = 0;Count < NO_OF_INPUTS;Count++) + { + pMapInput->Inputs[Count].SensorType = LIGHT_ACTIVE; + } + State = TSTPRG_LIGHT_SENSOR_INIT; + } + break; + + } + } + break; + + case TSTPRG_LIGHT_SENSOR_INIT : + { + for (Count = 0;Count < NO_OF_INPUTS;Count++) + { + pMapDisplay->pTextLines[TEXTLINE_3 + Count] = TxtBuffer[Count]; + } + pMapDisplay->pTextLines[TEXTLINE_8] = (UBYTE*)TXT_SUBTEST_STOP; + pMapDisplay->UpdateMask |= TEXTLINE_BITS; + State = TSTPRG_LIGHT_SENSOR; + } + break; + + case TSTPRG_LIGHT_SENSOR : + { + for (Count = 0;Count < NO_OF_INPUTS;Count++) + { + if (InputValues[Count] != pMapInput->Inputs[Count].ADRaw) + { + InputValues[Count] = pMapInput->Inputs[Count].ADRaw; + sprintf((char*)TxtBuffer[Count]," Input %u = %4u ",(UWORD)Count + 1,(UWORD)InputValues[Count]); + pMapDisplay->UpdateMask |= TEXTLINE_BIT(TEXTLINE_3 + Count); + } + } + if (cUiReadButtons() != BUTTON_NONE) + { + State = TSTPRG_SKIP_SENSOR; + } + } + break; + + case TSTPRG_SKIP_SENSOR : + { + for (Count = 0;Count < NO_OF_INPUTS;Count++) + { + pMapInput->Inputs[Count].SensorType = NO_SENSOR; + } + State = TSTPRG_SENSOR_INIT; + } + break; + + case TSTPRG_MOTOR_INIT : + { + pMapDisplay->pTextLines[TEXTLINE_1] = (UBYTE*)TXT_MOTOR; + pMapDisplay->pTextLines[TEXTLINE_2] = (UBYTE*)TXT_LINE; + pMapDisplay->pTextLines[TEXTLINE_3] = (UBYTE*)TXT_MOTOR_HEADER; + pMapDisplay->pTextLines[TEXTLINE_4] = (UBYTE*)TXT_EMPTY; + pMapDisplay->pTextLines[TEXTLINE_5] = (UBYTE*)TXT_EMPTY; + pMapDisplay->pTextLines[TEXTLINE_6] = (UBYTE*)TXT_EMPTY; + pMapDisplay->pTextLines[TEXTLINE_7] = (UBYTE*)TXT_EMPTY; + pMapDisplay->pTextLines[TEXTLINE_8] = (UBYTE*)TXT_MOTOR_STOP; + + for (Count = 0;Count < NO_OF_OUTPUTS;Count++) + { + OutputValues[Count] = 0x7FFF; + TestPrgRunMotor(Count,0); + strcpy((char*)TxtBuffer[Count]," "); + pMapDisplay->pTextLines[TEXTLINE_4 + Count] = TxtBuffer[Count]; + } + + pMapDisplay->UpdateMask |= TEXTLINE_BITS; + State = TSTPRG_MOTOR; + } + break; + + case TSTPRG_MOTOR : + { + for (Count = 0;Count < NO_OF_OUTPUTS;Count++) + { + if (OutputValues[Count] != (SWORD)TestPrgReadMotor(Count)) + { + OutputValues[Count] = (SWORD)TestPrgReadMotor(Count); + sprintf((char*)TxtBuffer[Count]," %c %-4d %4d",(char)Count + 'A',(SWORD)pMapOutPut->Outputs[Count].Speed,OutputValues[Count]); + pMapDisplay->UpdateMask |= TEXTLINE_BIT(TEXTLINE_4 + Count); + } + } + switch (cUiReadButtons()) + { + case BUTTON_LEFT : + { + for (Count = 0;Count < NO_OF_OUTPUTS;Count++) + { + OutputValues[Count] = 0x7FFF; + TestPrgRunMotor(Count,-50); + } + } + break; + + case BUTTON_ENTER : + { + for (Count = 0;Count < NO_OF_OUTPUTS;Count++) + { + OutputValues[Count] = 0x7FFF; + TestPrgRunMotor(Count,0); + } + } + break; + + case BUTTON_EXIT : + { + State = TSTPRG_SKIP_MOTOR; + } + break; + + case BUTTON_RIGHT : + { + for (Count = 0;Count < NO_OF_OUTPUTS;Count++) + { + OutputValues[Count] = 0x7FFF; + TestPrgRunMotor(Count,50); + } + } + break; + + } + } + break; + + case TSTPRG_SKIP_MOTOR : + { + for (Count = 0;Count < NO_OF_OUTPUTS;Count++) + { + TestPrgFloatMotor(Count); + } + State = TSTPRG_INIT; + } + break; + + case TSTPRG_RCX_INIT : + { + pMapDisplay->pTextLines[TEXTLINE_1] = (UBYTE*)TXT_RCX; + pMapDisplay->pTextLines[TEXTLINE_2] = (UBYTE*)TXT_LINE; + pMapDisplay->pTextLines[TEXTLINE_3] = (UBYTE*)TXT_EMPTY; + pMapDisplay->pTextLines[TEXTLINE_4] = (UBYTE*)TXT_EMPTY; + pMapDisplay->pTextLines[TEXTLINE_5] = (UBYTE*)TXT_SELECT; + pMapDisplay->pTextLines[TEXTLINE_6] = (UBYTE*)TXT_EMPTY; + pMapDisplay->pTextLines[TEXTLINE_7] = (UBYTE*)TXT_EMPTY; + pMapDisplay->pTextLines[TEXTLINE_8] = (UBYTE*)TXT_RCX_STOP; + + pMapDisplay->UpdateMask |= TEXTLINE_BITS; + State = TSTPRG_RCX_SELECT; + } + break; + + case TSTPRG_RCX_SELECT : + { + switch (cUiReadButtons()) + { + case BUTTON_LEFT : + { + pMapDisplay->pTextLines[TEXTLINE_5] = (UBYTE*)TXT_SELECT_TYPE; + pMapDisplay->pTextLines[TEXTLINE_8] = (UBYTE*)TXT_RCX_INPUT_SELECT; + pMapDisplay->UpdateMask |= TEXTLINE_BITS; + for (Count = 0;Count < NO_OF_INPUTS;Count++) + { + InputValues[Count] = 0x7FFF; + strcpy((char*)TxtBuffer[Count]," "); + } + State = TSTPRG_RCX_INPUT_SELECT; + } + break; + + case BUTTON_ENTER : + { + State = TSTPRG_RCX_DISPLAY_INIT; + } + break; + + case BUTTON_RIGHT : + { + State = TSTPRG_RCX_MOTOR_INIT; + } + break; + + case BUTTON_EXIT : + { + State = TSTPRG_INIT; + } + break; + + } + } + break; + + case TSTPRG_RCX_DISPLAY_INIT : + { + Count = 0; + pMapDisplay->EraseMask |= SCREEN_BIT(SCREEN_BACKGROUND); + State = TSTPRG_RCX_DISPLAY; + } + break; + + case TSTPRG_RCX_DISPLAY : + { + if ((Count & 0x7FF) == 0x000) + { + pMapDisplay->pScreens[SCREEN_BACKGROUND] = (BMPMAP*)Test1; + pMapDisplay->UpdateMask |= SCREEN_BIT(SCREEN_BACKGROUND); + } + if ((Count & 0x7FF) == 0x3FF) + { + pMapDisplay->pScreens[SCREEN_BACKGROUND] = (BMPMAP*)Test2; + pMapDisplay->UpdateMask |= SCREEN_BIT(SCREEN_BACKGROUND); + } + Count++; + if (cUiReadButtons() != BUTTON_NONE) + { + State = TSTPRG_SKIP_RCX; + } + } + break; + + case TSTPRG_RCX_INPUT_SELECT : + { + switch (cUiReadButtons()) + { + case BUTTON_LEFT : + { + pMapDisplay->pTextLines[TEXTLINE_1] = (UBYTE*)TXT_RCX_INPUT_PASIVE; + for (Count = 0;Count < NO_OF_INPUTS;Count++) + { + pMapInput->Inputs[Count].SensorType = SWITCH; + } + State = TSTPRG_RCX_INPUT_INIT; + } + break; + + case BUTTON_ENTER : + { + pMapDisplay->pTextLines[TEXTLINE_1] = (UBYTE*)TXT_RCX_INPUT_ACTIVE; + for (Count = 0;Count < NO_OF_INPUTS;Count++) + { + pMapInput->Inputs[Count].SensorType = REFLECTION; + } + State = TSTPRG_RCX_INPUT_INIT; + } + break; + + case BUTTON_EXIT : + { + State = TSTPRG_SKIP_RCX; + } + break; + + case BUTTON_RIGHT : + { + pMapDisplay->pTextLines[TEXTLINE_1] = (UBYTE*)TXT_RCX_INPUT_DIGITAL; + pMapDisplay->pTextLines[TEXTLINE_2] = (UBYTE*)TXT_LINE; + pMapDisplay->pTextLines[TEXTLINE_3] = (UBYTE*)TXT_EMPTY; + pMapDisplay->pTextLines[TEXTLINE_4] = (UBYTE*)TXT_EMPTY; + pMapDisplay->pTextLines[TEXTLINE_5] = (UBYTE*)TXT_EMPTY; + pMapDisplay->pTextLines[TEXTLINE_6] = (UBYTE*)TXT_EMPTY; + pMapDisplay->pTextLines[TEXTLINE_7] = (UBYTE*)TXT_EMPTY; + pMapDisplay->pTextLines[TEXTLINE_8] = (UBYTE*)TXT_SUBTEST_STOP; + pMapDisplay->UpdateMask |= TEXTLINE_BITS; + for (Count = 0;Count < NO_OF_INPUTS;Count++) + { + pMapInput->Inputs[Count].SensorType = CUSTOM; + } + SubState = 0; + Timer = 0; + State = TSTPRG_RCX_DIGITAL_INIT; + } + break; + + } + } + break; + + case TSTPRG_RCX_INPUT_INIT : + { + for (Count = 0;Count < NO_OF_INPUTS;Count++) + { + pMapDisplay->pTextLines[TEXTLINE_3 + Count] = TxtBuffer[Count]; + } + pMapDisplay->pTextLines[TEXTLINE_8] = (UBYTE*)TXT_SUBTEST_STOP; + pMapDisplay->UpdateMask |= TEXTLINE_BITS; + State = TSTPRG_RCX_INPUT; + Timer = 0; + } + break; + + case TSTPRG_RCX_INPUT : + { + if (++Timer >= 250) + { + Timer = 0; + for (Count = 0;Count < NO_OF_INPUTS;Count++) + { + if (InputValues[Count] != pMapInput->Inputs[Count].ADRaw) + { + InputValues[Count] = pMapInput->Inputs[Count].ADRaw; + sprintf((char*)TxtBuffer[Count]," Input %u = %4u ",(UWORD)Count + 1,(UWORD)InputValues[Count]); + pMapDisplay->UpdateMask |= TEXTLINE_BIT(TEXTLINE_3 + Count); + } + } + } + if (cUiReadButtons() != BUTTON_NONE) + { + State = TSTPRG_SKIP_RCX; + } + } + break; + + case TSTPRG_RCX_DIGITAL_INIT : + { + if (++Timer >= 20) + { + Timer = 0; + switch (SubState) + { + case 0 : + { + pMapInput->Inputs[0].DigiPinsDir |= DIGI0; // Digi 1-0 output -, + pMapInput->Inputs[0].DigiPinsDir &= ~DIGI1; // Digi 1-1 input -, | + pMapInput->Inputs[2].DigiPinsDir &= ~DIGI0; // Digi 3-0 input | -' + pMapInput->Inputs[2].DigiPinsDir |= DIGI1; // Digi 3-1 output -' + + pMapInput->Inputs[0].DigiPinsOut |= DIGI0; // Digi 1-0 output high + pMapInput->Inputs[2].DigiPinsOut &= ~DIGI1; // Digi 3-1 output low + + SubState++; + } + break; + + case 1 : + { + if ((pMapInput->Inputs[2].DigiPinsIn & DIGI0) && !(pMapInput->Inputs[0].DigiPinsIn & DIGI1)) + { + pMapInput->Inputs[0].DigiPinsOut &= ~DIGI0; // Digi 1-0 output low + pMapInput->Inputs[2].DigiPinsOut |= DIGI1; // Digi 3-1 output high + + SubState++; + } + else + { + State = TSTPRG_RCX_DIGITAL_FAIL; + } + } + break; + + case 2 : + { + if (!(pMapInput->Inputs[2].DigiPinsIn & DIGI0) && (pMapInput->Inputs[0].DigiPinsIn & DIGI1)) + { + pMapInput->Inputs[0].DigiPinsDir &= ~DIGI0; // Digi 1-0 input + pMapInput->Inputs[0].DigiPinsDir &= ~DIGI1; // Digi 1-1 input + pMapInput->Inputs[2].DigiPinsDir &= ~DIGI0; // Digi 3-0 input + pMapInput->Inputs[2].DigiPinsDir &= ~DIGI1; // Digi 3-1 input + + pMapInput->Inputs[1].DigiPinsDir |= DIGI0; // Digi 2-0 output -, + pMapInput->Inputs[1].DigiPinsDir &= ~DIGI1; // Digi 2-1 input -, | + pMapInput->Inputs[3].DigiPinsDir &= ~DIGI0; // Digi 4-0 input | -' + pMapInput->Inputs[3].DigiPinsDir |= DIGI1; // Digi 4-1 output -' + + pMapInput->Inputs[1].DigiPinsOut |= DIGI0; // Digi 2-0 output high + pMapInput->Inputs[3].DigiPinsOut &= ~DIGI1; // Digi 4-1 output low + + SubState++; + } + else + { + State = TSTPRG_RCX_DIGITAL_FAIL; + } + } + break; + + case 3 : + { + if ((pMapInput->Inputs[3].DigiPinsIn & DIGI0) && !(pMapInput->Inputs[1].DigiPinsIn & DIGI1)) + { + pMapInput->Inputs[1].DigiPinsOut &= ~DIGI0; // Digi 2-0 output low + pMapInput->Inputs[3].DigiPinsOut |= DIGI1; // Digi 4-1 output high + + SubState++; + } + else + { + State = TSTPRG_RCX_DIGITAL_FAIL; + } + } + break; + + case 4 : + { + if (!(pMapInput->Inputs[3].DigiPinsIn & DIGI0) && (pMapInput->Inputs[1].DigiPinsIn & DIGI1)) + { + pMapInput->Inputs[1].DigiPinsDir &= ~DIGI0; // Digi 2-0 input + pMapInput->Inputs[1].DigiPinsDir &= ~DIGI1; // Digi 2-1 input + pMapInput->Inputs[3].DigiPinsDir &= ~DIGI0; // Digi 4-0 input + pMapInput->Inputs[3].DigiPinsDir &= ~DIGI1; // Digi 4-1 input + + State = TSTPRG_RCX_DIGITAL_OK; + } + else + { + State = TSTPRG_RCX_DIGITAL_FAIL; + } + } + break; + + } + } + } + break; + + case TSTPRG_RCX_DIGITAL_OK : + { + pMapDisplay->pTextLines[TEXTLINE_5] = (UBYTE*)TXT_RCX_DIGITAL_OK; + pMapDisplay->UpdateMask |= TEXTLINE_BITS; + State = TSTPRG_RCX_DIGITAL; + } + break; + + case TSTPRG_RCX_DIGITAL_FAIL : + { + pMapDisplay->pTextLines[TEXTLINE_5] = (UBYTE*)TXT_RCX_DIGITAL_FAIL; + pMapDisplay->UpdateMask |= TEXTLINE_BITS; + State = TSTPRG_RCX_DIGITAL; + } + break; + + case TSTPRG_RCX_DIGITAL : + { + if (cUiReadButtons() != BUTTON_NONE) + { + State = TSTPRG_SKIP_RCX; + } + } + break; + + case TSTPRG_RCX_MOTOR_INIT : + { + pMapDisplay->pTextLines[TEXTLINE_1] = (UBYTE*)TXT_MOTOR; + pMapDisplay->pTextLines[TEXTLINE_2] = (UBYTE*)TXT_LINE; + pMapDisplay->pTextLines[TEXTLINE_3] = (UBYTE*)TXT_MOTOR_HEADER; + pMapDisplay->pTextLines[TEXTLINE_4] = (UBYTE*)TXT_EMPTY; + pMapDisplay->pTextLines[TEXTLINE_5] = (UBYTE*)TXT_EMPTY; + pMapDisplay->pTextLines[TEXTLINE_6] = (UBYTE*)TXT_EMPTY; + pMapDisplay->pTextLines[TEXTLINE_7] = (UBYTE*)TXT_EMPTY; + pMapDisplay->pTextLines[TEXTLINE_8] = (UBYTE*)TXT_MOTOR_NEXT; + + for (Count = 0;Count < NO_OF_OUTPUTS;Count++) + { + OutputValues[Count] = 0x7FFF; + TestPrgRunMotor(Count,0); + strcpy((char*)TxtBuffer[Count]," "); + pMapDisplay->pTextLines[TEXTLINE_4 + Count] = TxtBuffer[Count]; + } + + Pointer = 0; + pMapDisplay->UpdateMask |= TEXTLINE_BITS; + State = TSTPRG_RCX_MOTOR; + } + break; + + case TSTPRG_RCX_MOTOR : + { + for (Count = 0;Count < NO_OF_OUTPUTS;Count++) + { + if (OutputValues[Count] != (SWORD)TestPrgReadMotor(Count)) + { + OutputValues[Count] = (SWORD)TestPrgReadMotor(Count); + if (Pointer == Count) + { + sprintf((char*)TxtBuffer[Count],"> %c %-4d %4d",(char)Count + 'A',(SWORD)pMapOutPut->Outputs[Count].Speed,OutputValues[Count]); + } + else + { + sprintf((char*)TxtBuffer[Count]," %c %-4d %4d",(char)Count + 'A',(SWORD)pMapOutPut->Outputs[Count].Speed,OutputValues[Count]); + } + pMapDisplay->UpdateMask |= TEXTLINE_BIT(TEXTLINE_4 + Count); + } + } + switch (cUiReadButtons()) + { + case BUTTON_LEFT : + { + for (Count = 0;Count < NO_OF_OUTPUTS;Count++) + { + OutputValues[Count] = 0x7FFF; + if (Pointer == Count) + { + TestPrgRunMotor(Count,-50); + } + else + { + TestPrgRunMotor(Count,0); + } + } + } + break; + + case BUTTON_ENTER : + { + for (Count = 0;Count < NO_OF_OUTPUTS;Count++) + { + OutputValues[Count] = 0x7FFF; + TestPrgRunMotor(Count,0); + } + if (++Pointer >= NO_OF_OUTPUTS) + { + State = TSTPRG_SKIP_RCX_MOTOR; + } + } + break; + + case BUTTON_EXIT : + { + State = TSTPRG_SKIP_RCX_MOTOR; + } + break; + + case BUTTON_RIGHT : + { + for (Count = 0;Count < NO_OF_OUTPUTS;Count++) + { + OutputValues[Count] = 0x7FFF; + if (Pointer == Count) + { + TestPrgRunMotor(Count,50); + } + else + { + TestPrgRunMotor(Count,0); + } + } + } + break; + + } + } + break; + + case TSTPRG_SKIP_RCX_MOTOR : + { + for (Count = 0;Count < NO_OF_OUTPUTS;Count++) + { + TestPrgFloatMotor(Count); + } + State = TSTPRG_RCX_INIT; + } + break; + + case TSTPRG_SKIP_RCX : + { + for (Count = 0;Count < NO_OF_INPUTS;Count++) + { + pMapInput->Inputs[Count].SensorType = NO_SENSOR; + } + pMapDisplay->EraseMask |= SCREEN_BIT(SCREEN_BACKGROUND); + State = TSTPRG_RCX_INIT; + } + break; + +#endif + + case TSTPRG_SKIP : + { + Count++; + if (Count == 100) + { + pMapDisplay->EraseMask |= SCREEN_BIT(SCREEN_BACKGROUND); + } + if (Count >= 200) + { + IOMapUi.Flags |= UI_REDRAW_STATUS; + State = 0; + } + } + break; + + default : + { + State = SYSTEM_INIT; + } + break; + + } + + return (State); +} diff --git a/AT91SAM7S256/Source/Connections.txt b/AT91SAM7S256/Source/Connections.txt new file mode 100644 index 0000000..685304f --- /dev/null +++ b/AT91SAM7S256/Source/Connections.txt @@ -0,0 +1,21 @@ +const ICON Connections[] = +{ + 0x04,0x00, // Graphics Format + 0x01,0x20, // Graphics DataSize + 0x01, // Graphics Count X + 0x04, // Graphics Count Y + 0x18, // Graphics Width + 0x18, // Graphics Height + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x40,0x00,0x40,0x40,0x00,0x40,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xDB,0x00,0x00,0x7E,0x81,0x81,0x7E,0x00,0x00,0xDB,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x02,0x00,0x02,0x02,0x00,0x02,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x40,0x00,0x40,0x40,0x00,0x40,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xDB,0x00,0x00,0x00,0x82,0xFF,0x80,0x00,0x00,0xDB,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x02,0x00,0x02,0x02,0x00,0x02,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x40,0x00,0x40,0x40,0x00,0x40,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xDB,0x00,0x00,0xE2,0x91,0x89,0x86,0x00,0x00,0xDB,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x02,0x00,0x02,0x02,0x00,0x02,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x40,0x00,0x40,0x40,0x00,0x40,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xDB,0x00,0x00,0x42,0x81,0x89,0x76,0x00,0x00,0xDB,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x02,0x00,0x02,0x02,0x00,0x02,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 +}; diff --git a/AT91SAM7S256/Source/Cursor.txt b/AT91SAM7S256/Source/Cursor.txt new file mode 100644 index 0000000..d1e830e --- /dev/null +++ b/AT91SAM7S256/Source/Cursor.txt @@ -0,0 +1,10 @@ +const BMPMAP Cursor[] = +{ + 0x02,0x00, // Graphics Format + 0x00,0x08, // Graphics DataSize + 0x00, // Graphics Start X + 0x00, // Graphics Start Y + 0x07, // Graphics Width + 0x08, // Graphics Height + 0x21,0x31,0x39,0x3D,0x39,0x31,0x21 +}; diff --git a/AT91SAM7S256/Source/Devices.txt b/AT91SAM7S256/Source/Devices.txt new file mode 100644 index 0000000..57be902 --- /dev/null +++ b/AT91SAM7S256/Source/Devices.txt @@ -0,0 +1,21 @@ +const ICON Devices[] = +{ + 0x04,0x00, // Graphics Format + 0x01,0x20, // Graphics DataSize + 0x01, // Graphics Count X + 0x04, // Graphics Count Y + 0x18, // Graphics Width + 0x18, // Graphics Height + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x80,0x80,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x82,0x44,0x28,0xFF,0x11,0xAA,0x44,0x00,0x00,0x06,0x01,0x00,0x40,0x20,0x11,0x0E,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0xF8,0x48,0x48,0x78,0x48,0x48,0x78,0x48,0x48,0x78,0x48,0x48,0xF8,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x9E,0x91,0x51,0x51,0x51,0x91,0x9E,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0x24,0x24,0x24,0x3C,0x25,0x25,0x25,0x3C,0x24,0x24,0x24,0x3F,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x70,0x08,0x30,0x40,0x40,0x40,0x40,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x4E,0x91,0x51,0x91,0x51,0x8E,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0x10,0x11,0x12,0x11,0x12,0x11,0x12,0x10,0x0F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xBF,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xBF,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x06,0x07,0x05,0x06,0x05,0x06,0x05,0x06,0x05,0x06,0x05,0x06,0x05,0x07,0x06,0x00,0x00,0x00,0x00 +}; diff --git a/AT91SAM7S256/Source/Display.txt b/AT91SAM7S256/Source/Display.txt new file mode 100644 index 0000000..049eeaf --- /dev/null +++ b/AT91SAM7S256/Source/Display.txt @@ -0,0 +1,12 @@ +const BMPMAP Display[] = +{ + 0x02,0x00, // Graphics Format + 0x00,0xD8, // Graphics DataSize + 0x0E, // Graphics Start X + 0x10, // Graphics Start Y + 0x48, // Graphics Width + 0x18, // Graphics Height + 0xF8,0xFC,0x0E,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x0E,0xFC,0xF8,0xC0, + 0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF, + 0x0F,0x1F,0x38,0x30,0x30,0x70,0x70,0x70,0x70,0x70,0x70,0x70,0x70,0x70,0x70,0x70,0x70,0x70,0x70,0x70,0x70,0x70,0x70,0x70,0x70,0x70,0x70,0x70,0x70,0x70,0x70,0x70,0x70,0x70,0x70,0x70,0x70,0x70,0x70,0x70,0x70,0x70,0x70,0x70,0x70,0x70,0x70,0x70,0x70,0x70,0x70,0x70,0x70,0x70,0x70,0x70,0x70,0x70,0x70,0x70,0x70,0x70,0x70,0x70,0x70,0x70,0x70,0x70,0x78,0x7F,0x3F,0x1F +}; diff --git a/AT91SAM7S256/Source/Fail.txt b/AT91SAM7S256/Source/Fail.txt new file mode 100644 index 0000000..6048462 --- /dev/null +++ b/AT91SAM7S256/Source/Fail.txt @@ -0,0 +1,12 @@ +const BMPMAP Fail[] = +{ + 0x02,0x00, // Graphics Format + 0x00,0x48, // Graphics DataSize + 0x00, // Graphics Start X + 0x08, // Graphics Start Y + 0x18, // Graphics Width + 0x18, // Graphics Height + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xC0,0x60,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xC0,0x30,0x0C,0x03,0x00,0x7C,0x00,0x03,0x0C,0x30,0xC0,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x04,0x04,0x04,0x04,0x04,0x05,0x04,0x04,0x04,0x04,0x04,0x03,0x00,0x00,0x00,0x00,0x00 +}; diff --git a/AT91SAM7S256/Source/Font.txt b/AT91SAM7S256/Source/Font.txt new file mode 100644 index 0000000..e748f76 --- /dev/null +++ b/AT91SAM7S256/Source/Font.txt @@ -0,0 +1,15 @@ +const ICON Font[] = +{ + 0x04,0x00, // Graphics Format + 0x02,0x40, // Graphics DataSize + 0x10, // Graphics Count X + 0x06, // Graphics Count Y + 0x06, // Graphics Width + 0x08, // Graphics Height + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x5F,0x06,0x00,0x00,0x07,0x03,0x00,0x07,0x03,0x00,0x24,0x7E,0x24,0x7E,0x24,0x00,0x24,0x2B,0x6A,0x12,0x00,0x00,0x63,0x13,0x08,0x64,0x63,0x00,0x30,0x4C,0x52,0x22,0x50,0x00,0x00,0x07,0x03,0x00,0x00,0x00,0x00,0x3E,0x41,0x00,0x00,0x00,0x00,0x41,0x3E,0x00,0x00,0x00,0x08,0x3E,0x1C,0x3E,0x08,0x00,0x08,0x08,0x3E,0x08,0x08,0x00,0x80,0x60,0x60,0x00,0x00,0x00,0x08,0x08,0x08,0x08,0x08,0x00,0x00,0x60,0x60,0x00,0x00,0x00,0x20,0x10,0x08,0x04,0x02,0x00, + 0x3E,0x51,0x49,0x45,0x3E,0x00,0x00,0x42,0x7F,0x40,0x00,0x00,0x62,0x51,0x49,0x49,0x46,0x00,0x22,0x49,0x49,0x49,0x36,0x00,0x18,0x14,0x12,0x7F,0x10,0x00,0x2F,0x49,0x49,0x49,0x31,0x00,0x3C,0x4A,0x49,0x49,0x30,0x00,0x01,0x71,0x09,0x05,0x03,0x00,0x36,0x49,0x49,0x49,0x36,0x00,0x06,0x49,0x49,0x29,0x1E,0x00,0x00,0x6C,0x6C,0x00,0x00,0x00,0x00,0xEC,0x6C,0x00,0x00,0x00,0x08,0x14,0x22,0x41,0x00,0x00,0x24,0x24,0x24,0x24,0x24,0x00,0x00,0x41,0x22,0x14,0x08,0x00,0x02,0x01,0x59,0x09,0x06,0x00, + 0x3E,0x41,0x5D,0x55,0x1E,0x00,0x7E,0x11,0x11,0x11,0x7E,0x00,0x7F,0x49,0x49,0x49,0x36,0x00,0x3E,0x41,0x41,0x41,0x22,0x00,0x7F,0x41,0x41,0x41,0x3E,0x00,0x7F,0x49,0x49,0x49,0x41,0x00,0x7F,0x09,0x09,0x09,0x01,0x00,0x3E,0x41,0x49,0x49,0x7A,0x00,0x7F,0x08,0x08,0x08,0x7F,0x00,0x00,0x41,0x7F,0x41,0x00,0x00,0x30,0x40,0x40,0x40,0x3F,0x00,0x7F,0x08,0x14,0x22,0x41,0x00,0x7F,0x40,0x40,0x40,0x40,0x00,0x7F,0x02,0x04,0x02,0x7F,0x00,0x7F,0x02,0x04,0x08,0x7F,0x00,0x3E,0x41,0x41,0x41,0x3E,0x00, + 0x7F,0x09,0x09,0x09,0x06,0x00,0x3E,0x41,0x51,0x21,0x5E,0x00,0x7F,0x09,0x09,0x19,0x66,0x00,0x26,0x49,0x49,0x49,0x32,0x00,0x01,0x01,0x7F,0x01,0x01,0x00,0x3F,0x40,0x40,0x40,0x3F,0x00,0x1F,0x20,0x40,0x20,0x1F,0x00,0x3F,0x40,0x3C,0x40,0x3F,0x00,0x63,0x14,0x08,0x14,0x63,0x00,0x07,0x08,0x70,0x08,0x07,0x00,0x71,0x49,0x45,0x43,0x00,0x00,0x00,0x7F,0x41,0x41,0x00,0x00,0x02,0x04,0x08,0x10,0x20,0x00,0x00,0x41,0x41,0x7F,0x00,0x00,0x04,0x02,0x01,0x02,0x04,0x00,0x80,0x80,0x80,0x80,0x80,0x00, + 0x00,0x02,0x05,0x02,0x00,0x00,0x20,0x54,0x54,0x54,0x78,0x00,0x7F,0x44,0x44,0x44,0x38,0x00,0x38,0x44,0x44,0x44,0x28,0x00,0x38,0x44,0x44,0x44,0x7F,0x00,0x38,0x54,0x54,0x54,0x08,0x00,0x08,0x7E,0x09,0x09,0x00,0x00,0x18,0x24,0xA4,0xA4,0xFC,0x00,0x7F,0x04,0x04,0x78,0x00,0x00,0x00,0x00,0x7D,0x40,0x00,0x00,0x40,0x80,0x84,0x7D,0x00,0x00,0x7F,0x10,0x28,0x44,0x00,0x00,0x00,0x00,0x7F,0x40,0x00,0x00,0x7C,0x04,0x18,0x04,0x78,0x00,0x7C,0x04,0x04,0x78,0x00,0x00,0x38,0x44,0x44,0x44,0x38,0x00, + 0xFC,0x44,0x44,0x44,0x38,0x00,0x38,0x44,0x44,0x44,0xFC,0x00,0x44,0x78,0x44,0x04,0x08,0x00,0x08,0x54,0x54,0x54,0x20,0x00,0x04,0x3E,0x44,0x24,0x00,0x00,0x3C,0x40,0x20,0x7C,0x00,0x00,0x1C,0x20,0x40,0x20,0x1C,0x00,0x3C,0x60,0x30,0x60,0x3C,0x00,0x6C,0x10,0x10,0x6C,0x00,0x00,0x9C,0xA0,0x60,0x3C,0x00,0x00,0x64,0x54,0x54,0x4C,0x00,0x00,0x08,0x3E,0x41,0x41,0x00,0x00,0x00,0x00,0x77,0x00,0x00,0x00,0x00,0x41,0x41,0x3E,0x08,0x00,0x02,0x01,0x02,0x01,0x00,0x00,0x10,0x20,0x40,0x38,0x07,0x00 +}; diff --git a/AT91SAM7S256/Source/Functions.inl b/AT91SAM7S256/Source/Functions.inl new file mode 100644 index 0000000..e641409 --- /dev/null +++ b/AT91SAM7S256/Source/Functions.inl @@ -0,0 +1,3730 @@ +// +// Programmer +// +// Date init 26.04.2005 +// +// Reviser $Author:: Dktochpe $ +// +// Revision date $Date:: $ +// +// Filename $Workfile:: $ +// +// Version $Revision:: $ +// +// Archive $Archive:: $ +// +// Platform C +// + +//******* cUiBtTest ********************************************************** + +const UBYTE NONVOLATILE_NAME[] = UI_NONVOLATILE; // Non volatile filename without extention +const UBYTE DEFAULT_PROGRAM_NAME[] = UI_PROGRAM_DEFAULT; // On brick programming filename without extention +const UBYTE TEMP_PROGRAM_FILENAME[] = UI_PROGRAM_TEMP; // On brick programming tmp filename +const UBYTE VM_PROGRAM_READER[] = UI_PROGRAM_READER; // On brick programming script reader filename without extention +const UBYTE DEFAULT_PIN_CODE[] = UI_PINCODE_DEFAULT; // Default blue tooth pin code +const UBYTE TXT_INVALID_SENSOR[] = "??????????????"; // Display invalid sensor data + + +#define SENSORS (MENU_SENSOR_INVALID - MENU_SENSOR_EMPTY) + +const UBYTE SENSORTYPE[SENSORS] = // for view and datalog +{ + 0, // MENU_SENSOR_EMPTY + SOUND_DB, // MENU_SENSOR_SOUND_DB + SOUND_DBA, // MENU_SENSOR_SOUND_DBA + LIGHT_ACTIVE, // MENU_SENSOR_LIGHT + LIGHT_INACTIVE, // MENU_SENSOR_LIGHT_AMB + REFLECTION, // MENU_SENSOR_LIGHT_OLD + SWITCH, // MENU_SENSOR_TOUCH + 0, // MENU_SENSOR_MOTOR_DEG + 0, // MENU_SENSOR_MOTOR_ROT + ANGLE, // MENU_SENSOR_ROTATION + LOWSPEED_9V, // MENU_SENSOR_ULTRASONIC_IN + LOWSPEED_9V, // MENU_SENSOR_ULTRASONIC_CM + TEMPERATURE, // MENU_SENSOR_TEMP_C + TEMPERATURE // MENU_SENSOR_TEMP_F +}; + +const UBYTE SENSORMODE[SENSORS] = // for view and datalog +{ + 0, // MENU_SENSOR_EMPTY + PCTFULLSCALEMODE, // MENU_SENSOR_SOUND_DB + PCTFULLSCALEMODE, // MENU_SENSOR_SOUND_DBA + PCTFULLSCALEMODE, // MENU_SENSOR_LIGHT + PCTFULLSCALEMODE, // MENU_SENSOR_LIGHT_AMB + PCTFULLSCALEMODE, // MENU_SENSOR_LIGHT_OLD + BOOLEANMODE, // MENU_SENSOR_TOUCH + 0, // MENU_SENSOR_MOTOR_DEG + 0, // MENU_SENSOR_MOTOR_ROT + ANGLESTEPSMODE, // MENU_SENSOR_ROTATION + 0, // MENU_SENSOR_ULTRASONIC_IN + 0, // MENU_SENSOR_ULTRASONIC_CM + CELSIUSMODE, // MENU_SENSOR_TEMP_C + FAHRENHEITMODE // MENU_SENSOR_TEMP_F +}; + +const UBYTE SENSORFORMAT[SENSORS][10] = +{ + "", // MENU_SENSOR_EMPTY + "%3.0f %%", // MENU_SENSOR_SOUND_DB + "%3.0f %%", // MENU_SENSOR_SOUND_DBA + "%3.0f %%", // MENU_SENSOR_LIGHT + "%3.0f %%", // MENU_SENSOR_LIGHT_AMB + "%3.0f %%", // MENU_SENSOR_LIGHT_OLD + "%1.0f", // MENU_SENSOR_TOUCH + "%8.0f `", // MENU_SENSOR_MOTOR_DEG + "%8.0f R", // MENU_SENSOR_MOTOR_ROT + "%6.0f T", // MENU_SENSOR_ROTATION + "%3.0f In", // MENU_SENSOR_ULTRASONIC_IN + "%3.0f cm", // MENU_SENSOR_ULTRASONIC_CM + "%5.1f `C", // MENU_SENSOR_TEMP_C + "%5.1f `F" // MENU_SENSOR_TEMP_F +}; + +const float SENSORDIVIDER[SENSORS] = +{ + 1.0, // MENU_SENSOR_EMPTY + 1.0, // MENU_SENSOR_SOUND_DB + 1.0, // MENU_SENSOR_SOUND_DBA + 1.0, // MENU_SENSOR_LIGHT + 1.0, // MENU_SENSOR_LIGHT_AMB + 1.0, // MENU_SENSOR_LIGHT_OLD + 1.0, // MENU_SENSOR_TOUCH + 1.0, // MENU_SENSOR_MOTOR_DEG + 360.0, // MENU_SENSOR_MOTOR_ROT + 1.0, // MENU_SENSOR_ROTATION + 2.54, // MENU_SENSOR_ULTRASONIC_IN + 1.0, // MENU_SENSOR_ULTRASONIC_CM + 10.0, // MENU_SENSOR_TEMP_C + 10.0 // MENU_SENSOR_TEMP_F +}; + + +//******* cUiSetupUltrasonic ************************************************* + +void cUiSetupUltrasonic(UBYTE Port) +{ + Port -= MENU_PORT_1; + pMapLowSpeed->OutBuf[Port].InPtr = 0; + pMapLowSpeed->OutBuf[Port].OutPtr = 0; + + pMapLowSpeed->OutBuf[Port].Buf[pMapLowSpeed->OutBuf[Port].InPtr] = ULTRA_SONIC; // Device Adress + pMapLowSpeed->OutBuf[Port].InPtr++; + pMapLowSpeed->OutBuf[Port].Buf[pMapLowSpeed->OutBuf[Port].InPtr] = 0x41; // Function => Set command + pMapLowSpeed->OutBuf[Port].InPtr++; + pMapLowSpeed->OutBuf[Port].Buf[pMapLowSpeed->OutBuf[Port].InPtr] = 0x02; // Function => Set to continiues measurement + pMapLowSpeed->OutBuf[Port].InPtr++; + + pMapLowSpeed->InBuf[Port].BytesToRx = 0; + pMapLowSpeed->ChannelState[Port] = LOWSPEED_INIT; + pMapLowSpeed->State |= (COM_CHANNEL_ONE_ACTIVE << Port); +} + + + +//******* cUiAskUltrasonic *************************************************** + +void cUiAskUltrasonic(UBYTE Port) +{ + Port -= MENU_PORT_1; + pMapLowSpeed->OutBuf[Port].InPtr = 0; + pMapLowSpeed->OutBuf[Port].OutPtr = 0; + + pMapLowSpeed->OutBuf[Port].Buf[pMapLowSpeed->OutBuf[Port].InPtr] = ULTRA_SONIC; // Device Adress + pMapLowSpeed->OutBuf[Port].InPtr++; + pMapLowSpeed->OutBuf[Port].Buf[pMapLowSpeed->OutBuf[Port].InPtr] = 0x42; // Function => Read result 1 + pMapLowSpeed->OutBuf[Port].InPtr++; + + pMapLowSpeed->InBuf[Port].BytesToRx = 1; + pMapLowSpeed->ChannelState[Port] = LOWSPEED_INIT; + pMapLowSpeed->State |= (COM_CHANNEL_ONE_ACTIVE << Port); +} + + + +//******* cUiReadUltrasonic ************************************************** + +UBYTE cUiReadUltrasonic(UBYTE Port) +{ + UBYTE Result; + + Port -= MENU_PORT_1; + if ((pMapLowSpeed->ChannelState[Port] == LOWSPEED_IDLE) || (pMapLowSpeed->ChannelState[Port] == LOWSPEED_DONE)) + { + Result = (UBYTE)pMapLowSpeed->InBuf[Port].Buf[pMapLowSpeed->InBuf[Port].OutPtr]; + pMapLowSpeed->InBuf[Port].OutPtr++; + if (pMapLowSpeed->InBuf[Port].OutPtr >= SIZE_OF_LSBUF) + { + pMapLowSpeed->InBuf[Port].OutPtr = 0; + } + if (Result == 0) + { + Result = 0xFF; + } + } + else + { + Result = 0xFF; + } + + return (Result); +} + + + +//******* cUiResetSensor ***************************************************** + +void cUiResetSensor(UBYTE Port,UBYTE Sensor) // Set sensor parameters +{ + switch (Sensor) + { + case MENU_SENSOR_MOTOR_DEG : + { + pMapOutPut->Outputs[Port - MENU_PORT_A].Flags |= UPDATE_RESET_COUNT; + } + break; + + case MENU_SENSOR_MOTOR_ROT : + { + pMapOutPut->Outputs[Port - MENU_PORT_A].Flags |= UPDATE_RESET_COUNT; + } + break; + + case MENU_SENSOR_ROTATION : + { + pMapInput->Inputs[Port - MENU_PORT_1].SensorValue = 0; + } + break; + + } +} + + + +//******* cUiSetupSensor ***************************************************** + +void cUiSetupSensor(UBYTE Port,UBYTE Sensor) // Set sensor parameters +{ + switch (Sensor) + { + case MENU_SENSOR_MOTOR_DEG : + { + pMapOutPut->Outputs[Port - MENU_PORT_A].Mode &= ~(BRAKE | MOTORON); + pMapOutPut->Outputs[Port - MENU_PORT_A].Flags |= UPDATE_MODE | UPDATE_SPEED; + pMapOutPut->Outputs[Port - MENU_PORT_A].TachoCnt = 0; + } + break; + + case MENU_SENSOR_MOTOR_ROT : + { + pMapOutPut->Outputs[Port - MENU_PORT_A].Mode &= ~(BRAKE | MOTORON); + pMapOutPut->Outputs[Port - MENU_PORT_A].Flags |= UPDATE_MODE | UPDATE_SPEED; + pMapOutPut->Outputs[Port - MENU_PORT_A].TachoCnt = 0; + } + break; + + case MENU_SENSOR_ULTRASONIC_IN : + { + pMapInput->Inputs[Port - MENU_PORT_1].SensorType = SENSORTYPE[Sensor - MENU_SENSOR_EMPTY]; + cUiSetupUltrasonic(Port); + } + break; + + case MENU_SENSOR_ULTRASONIC_CM : + { + pMapInput->Inputs[Port - MENU_PORT_1].SensorType = SENSORTYPE[Sensor - MENU_SENSOR_EMPTY]; + cUiSetupUltrasonic(Port); + } + break; + + default : + { + pMapInput->Inputs[Port - MENU_PORT_1].SensorType = SENSORTYPE[Sensor - MENU_SENSOR_EMPTY]; + pMapInput->Inputs[Port - MENU_PORT_1].SensorMode = SENSORMODE[Sensor - MENU_SENSOR_EMPTY]; + } + break; + + } +} + + + +//******* cUiAskSensor ******************************************************* + +void cUiAskSensor(UBYTE Port,UBYTE Sensor) // Ask for sensor data +{ + switch (Sensor) + { + case MENU_SENSOR_ULTRASONIC_IN : + { + cUiAskUltrasonic(Port); + } + break; + + case MENU_SENSOR_ULTRASONIC_CM : + { + cUiAskUltrasonic(Port); + } + break; + + default : + { + } + break; + + } +} + + + +//******* cUiGetSensorValue ************************************************** + +UBYTE cUiGetSensorValue(UBYTE Port,UBYTE Sensor,SLONG *Value) +{ + UBYTE Result = FALSE; + + *Value = 0L; + switch (Sensor) + { + case MENU_SENSOR_MOTOR_DEG : + { + *Value = pMapOutPut->Outputs[Port - MENU_PORT_A].TachoCnt; + Result = TRUE; + } + break; + + case MENU_SENSOR_MOTOR_ROT : + { + *Value = pMapOutPut->Outputs[Port - MENU_PORT_A].TachoCnt; + Result = TRUE; + } + break; + + case MENU_SENSOR_ULTRASONIC_IN : + { + Result = cUiReadUltrasonic(Port); + if (Result != 0xFF) + { + *Value = Result; + Result = TRUE; + } + else + { + Result = FALSE; + } + } + break; + + case MENU_SENSOR_ULTRASONIC_CM : + { + Result = cUiReadUltrasonic(Port); + if (Result != 0xFF) + { + *Value = Result; + Result = TRUE; + } + else + { + Result = FALSE; + } + } + break; + + default : + { + if (pMapInput->Inputs[Port - MENU_PORT_1].InvalidData != INVALID_DATA) + { + *Value = pMapInput->Inputs[Port - MENU_PORT_1].SensorValue; + Result = TRUE; + } + } + break; + + } + + return (Result); +} + + + +//******* cUiPrintSensorInDisplayBuffer ************************************** + +void cUiPrintSensorInDisplayBuffer(UBYTE Port,UBYTE Sensor,UBYTE Valid,SLONG Value) +{ + SWORD Tmp; + + Tmp = sprintf((char*)VarsUi.DisplayBuffer,(char*)SENSORFORMAT[Sensor - MENU_SENSOR_EMPTY],(float)0); + if (Valid == TRUE) + { + if (Tmp < sprintf((char*)VarsUi.DisplayBuffer,(char*)SENSORFORMAT[Sensor - MENU_SENSOR_EMPTY],(float)Value / SENSORDIVIDER[Sensor - MENU_SENSOR_EMPTY])) + { + sprintf((char*)VarsUi.DisplayBuffer,"%*.*s",Tmp,Tmp,(char*)TXT_INVALID_SENSOR); + } + } + else + { + sprintf((char*)VarsUi.DisplayBuffer,"%*.*s",Tmp,Tmp,(char*)TXT_INVALID_SENSOR); + } +} + + + +//******* cUiReleaseSensors ************************************************** + +void cUiReleaseSensors(void) +{ + UBYTE Tmp; + + for (Tmp = 0;Tmp < NO_OF_INPUTS;Tmp++) + { + pMapInput->Inputs[Tmp].SensorType = NO_SENSOR; + } +} + + + +//******* cUiBtCommand ******************************************************* + +enum +{ + UI_BT_CTRL, + + UI_BT_GET_DEVICES, // (UI_BT_GET_DEVICES,Known,*pDevices,NULL) [Known = 0,1] + UI_BT_GET_DEVICE_NAME, // (UI_BT_GET_DEVICE_NAME,Known,*pIndex,*pDeviceName) [Known = 0,1] + UI_BT_GET_DEVICE_TYPE, // (UI_BT_GET_DEVICE_TYPE,Known,*pIndex,*pDeviceType) [Known = 0,1] + + UI_BT_GET_CONNECTION_NAME, // (UI_BT_GET_CONNECTION_NAME,NULL,*pConnection,*pConnectionName) + UI_BT_GET_CONNECTION_TYPE, // (UI_BT_GET_CONNECTION_TYPE,NULL,*pConnection,*pConnectionType) + UI_BT_GET_CONNECTION_VALID, // (UI_BT_GET_CONNECTION_NAME,NULL,*pConnection,NULL) + + UI_BT_DUMMY +}; + + +#define UI_BT_FAILED 0x8200 // General command failed +#define UI_BT_SUCCES 0x0000 // Command executed succesfully + + +UBYTE cUiBTGetDeviceType(UBYTE *pCOD) +{ + ULONG COD; + UBYTE Result; + UBYTE Tmp; + + COD = 0; + for (Tmp = 0;Tmp < SIZE_OF_CLASS_OF_DEVICE;Tmp++) + { + COD <<= 8; + COD |= (ULONG)*pCOD; + pCOD++; + } + + Result = DEVICETYPE_UNKNOWN; + if ((COD & 0x00001FFF) == 0x00000804) + { + Result = DEVICETYPE_NXT; + } + if ((COD & 0x00001F00) == 0x00000200) + { + Result = DEVICETYPE_PHONE; + } + if ((COD & 0x00001F00) == 0x00000100) + { + Result = DEVICETYPE_PC; + } + + return (Result); +} + + +UBYTE cUiBTGetDeviceIndex(UBYTE Known,UBYTE No,UBYTE *pIndex) +{ + UBYTE Result = 0; + UBYTE Tmp; + + *pIndex = 0; + if (Known) + { + for (Tmp = 0;(Tmp < SIZE_OF_BT_DEVICE_TABLE) && (Result == 0);Tmp++) + { + if ((pMapComm->BtDeviceTable[Tmp].DeviceStatus & BT_DEVICE_KNOWN)) + { + if (No == *pIndex) + { + *pIndex = Tmp; + Result = ~0; + } + else + { + (*pIndex)++; + } + } + } + } + else + { + for (Tmp = 0;(Tmp < SIZE_OF_BT_DEVICE_TABLE) && (Result == 0);Tmp++) + { + if ((pMapComm->BtDeviceTable[Tmp].DeviceStatus & BT_DEVICE_UNKNOWN) || (pMapComm->BtDeviceTable[Tmp].DeviceStatus & BT_DEVICE_KNOWN)) + { + if (No == *pIndex) + { + *pIndex = Tmp; + Result = ~0; + } + else + { + (*pIndex)++; + } + } + } + } + + return (Result); +} + + +UWORD cUiBTCommand(UBYTE Cmd,UBYTE Flag,UBYTE *pParam1,UBYTE *pParam2) +{ + UWORD Result = UI_BT_FAILED; + + switch(Cmd) + { + case UI_BT_GET_DEVICES : + { + cUiBTGetDeviceIndex(Flag,SIZE_OF_BT_DEVICE_TABLE,pParam1); + Result = UI_BT_SUCCES; + } + break; + + case UI_BT_GET_DEVICE_NAME : + { + if ((*pParam1 < SIZE_OF_BT_DEVICE_TABLE) && (pParam2 != NULL)) + { + pParam2[0] = 0; + if (cUiBTGetDeviceIndex(Flag,*pParam1,&VarsUi.BTTmpIndex)) + { + sprintf((char*)pParam2,"%.*s",DISPLAYLINE_LENGTH,(char*)pMapComm->BtDeviceTable[VarsUi.BTTmpIndex].Name); + Result = UI_BT_SUCCES; + } + } + } + break; + + case UI_BT_GET_DEVICE_TYPE : + { + if ((*pParam1 < SIZE_OF_BT_DEVICE_TABLE) && (pParam2 != NULL)) + { + pParam2[0] = 0; + if (cUiBTGetDeviceIndex(Flag,*pParam1,&VarsUi.BTTmpIndex)) + { + pParam2[0] = cUiBTGetDeviceType(pMapComm->BtDeviceTable[VarsUi.BTTmpIndex].ClassOfDevice); + Result = UI_BT_SUCCES; + } + } + } + break; + + case UI_BT_GET_CONNECTION_NAME : + { + if (*pParam1 < SIZE_OF_BT_CONNECT_TABLE) + { + if (pMapComm->BtConnectTable[*pParam1].Name[0]) + { + if (pParam2 != NULL) + { + sprintf((char*)pParam2,"%.*s",DISPLAYLINE_LENGTH,(char*)pMapComm->BtConnectTable[*pParam1].Name); + } + Result = UI_BT_SUCCES; + } + else + { + if (pParam2 != NULL) + { + pParam2[0] = 0; + } + } + } + } + break; + + case UI_BT_GET_CONNECTION_TYPE : + { + if ((*pParam1 < SIZE_OF_BT_CONNECT_TABLE) && (pParam2 != NULL)) + { + pParam2[0] = 0; + if (pMapComm->BtConnectTable[*pParam1].Name[0]) + { + pParam2[0] = cUiBTGetDeviceType(pMapComm->BtConnectTable[*pParam1].ClassOfDevice); + Result = UI_BT_SUCCES; + } + } + } + break; + + case UI_BT_GET_CONNECTION_VALID : + { + if (*pParam1 < SIZE_OF_BT_CONNECT_TABLE) + { + if (pMapComm->BtConnectTable[*pParam1].Name[0]) + { + Result = UI_BT_SUCCES; + } + } + } + break; + + } + + return (Result); +} + + + +#include "BtTest.inc" + +//******* cUiNVxxxxx ********************************************************* + +void cUiNVWriteByte(void) +{ + sprintf((char*)VarsUi.NVFilename,"%s.%s",(char*)NONVOLATILE_NAME,(char*)TXT_SYS_EXT); + VarsUi.NVTmpHandle = pMapLoader->pFunc(FINDFIRST,VarsUi.NVFilename,VarsUi.SearchFilenameBuffer,&VarsUi.NVTmpLength); + if (!(VarsUi.NVTmpHandle & 0x8000)) + { + pMapLoader->pFunc(CLOSE,(UBYTE*)&VarsUi.NVTmpHandle,NULL,NULL); + pMapLoader->pFunc(DELETE,VarsUi.NVFilename,NULL,NULL); + } + VarsUi.NVTmpLength = 1; + VarsUi.NVTmpHandle = pMapLoader->pFunc(OPENWRITE,VarsUi.NVFilename,NULL,&VarsUi.NVTmpLength); + pMapLoader->pFunc(WRITE,(UBYTE*)&VarsUi.NVTmpHandle,(UBYTE*)&VarsUi.NVData,&VarsUi.NVTmpLength); + pMapLoader->pFunc(CLOSE,(UBYTE*)&VarsUi.NVTmpHandle,NULL,NULL); +} + +void cUiNVWritePowerOnTimeCount(UBYTE Count) +{ + VarsUi.NVData &= ~0x07; + VarsUi.NVData |= (Count & 0x07); + cUiNVWriteByte(); +} + +UBYTE cUiNVReadPowerOnTimeCount(void) +{ + return (VarsUi.NVData & 0x07); +} + +void cUiNVWriteVolumeCount(UBYTE Count) +{ + VarsUi.NVData &= ~0x70; + VarsUi.NVData |= ((Count << 4) & 0x70); + cUiNVWriteByte(); +} + +UBYTE cUiNVReadVolumeCount(void) +{ + return ((VarsUi.NVData >> 4) & 0x07); +} + +void cUiNVReadByte(void) +{ + VarsUi.NVData = 0xFF; + sprintf((char*)VarsUi.NVFilename,"%s.%s",(char*)NONVOLATILE_NAME,(char*)TXT_SYS_EXT); + VarsUi.NVTmpHandle = pMapLoader->pFunc(OPENREAD,VarsUi.NVFilename,NULL,&VarsUi.NVTmpLength); + if (!(VarsUi.NVTmpHandle & 0x8000)) + { + VarsUi.NVTmpLength = 1; + pMapLoader->pFunc(READ,(UBYTE*)&VarsUi.NVTmpHandle,&VarsUi.NVData,&VarsUi.NVTmpLength); + pMapLoader->pFunc(CLOSE,(UBYTE*)&VarsUi.NVTmpHandle,NULL,NULL); + } + + if ((cUiNVReadPowerOnTimeCount() > (POWER_OFF_TIME_STEPS - 1)) || (cUiNVReadVolumeCount() > MAX_VOLUME)) + { + VarsUi.NVData = 0xFF; + cUiNVWritePowerOnTimeCount(POWER_OFF_TIME_DEFAULT); + cUiNVWriteVolumeCount(MAX_VOLUME); + } +} + + + +//******* cUiFeedback ******************************************************** + +UBYTE cUiFeedback(BMPMAP *Bitmap,UBYTE TextNo1,UBYTE TextNo2,UWORD Time) // Show bimap and text +{ +// if ((VarsUi.FBState == 0) || ((pMapDisplay->Flags & DISPLAY_POPUP) == 0)) + { + switch (VarsUi.FBState) + { + case 0 : // Set busy + { + VarsUi.FBState++; + } + break; + + case 1 : // Clear line 2,3,4 + { + if (DISPLAY_IDLE) + { + pMapDisplay->EraseMask |= (TEXTLINE_BIT(TEXTLINE_2) | TEXTLINE_BIT(TEXTLINE_3) | TEXTLINE_BIT(TEXTLINE_4)); + VarsUi.FBState++; + } + } + break; + + case 2 : // Show bitmap if pressent + { + if (DISPLAY_IDLE) + { + if (Bitmap != NULL) + { + pMapDisplay->pBitmaps[BITMAP_1] = Bitmap; + pMapDisplay->UpdateMask |= BITMAP_BIT(BITMAP_1); + } + VarsUi.FBState++; + } + } + break; + + case 3 : // Get text string + { + if (DISPLAY_IDLE) + { + pMapDisplay->UpdateMask |= SPECIAL_BIT(TOPLINE); + VarsUi.FBText = cUiGetString(TextNo1); + VarsUi.FBPointer = 0; + if (TextNo2) + { + VarsUi.FBState = 5; + } + else + { + VarsUi.FBState++; + } + } + } + break; + + case 4 : // Show text string + { + if ((VarsUi.FBText[VarsUi.FBPointer]) && (VarsUi.FBPointer < NO_OF_FEEDBACK_CHARS)) + { + pMapDisplay->pFunc(DISPLAY_CHAR,TRUE,24 + VarsUi.FBPointer * 6,16,VarsUi.FBText[VarsUi.FBPointer],0); + VarsUi.FBPointer++; + } + else + { + VarsUi.FBTimer = 0; + VarsUi.FBState = 7; + } + } + break; + + case 5 : // Show text string + { + if ((VarsUi.FBText[VarsUi.FBPointer]) && (VarsUi.FBPointer < NO_OF_FEEDBACK_CHARS)) + { + pMapDisplay->pFunc(DISPLAY_CHAR,TRUE,24 + VarsUi.FBPointer * 6,12,VarsUi.FBText[VarsUi.FBPointer],0); + VarsUi.FBPointer++; + } + else + { + VarsUi.FBText = cUiGetString(TextNo2); + VarsUi.FBPointer = 0; + VarsUi.FBState++; + } + } + break; + + case 6 : // Show text string + { + if ((VarsUi.FBText[VarsUi.FBPointer]) && (VarsUi.FBPointer < NO_OF_FEEDBACK_CHARS)) + { + pMapDisplay->pFunc(DISPLAY_CHAR,TRUE,24 + VarsUi.FBPointer * 6,20,VarsUi.FBText[VarsUi.FBPointer],0); + VarsUi.FBPointer++; + } + else + { + VarsUi.FBTimer = 0; + VarsUi.FBState++; + } + } + break; + + case 7 : // Wait if time provided + { + if (++VarsUi.FBTimer >= (Time + 100)) + { + VarsUi.FBState++; + } + } + break; + + default : // Exit + { + VarsUi.FBState = 0; + } + break; + + } + } + + return (VarsUi.FBState); +} + + + +//******* cUiFileList ******************************************************** + +UBYTE cUiFindNoOfFiles(UBYTE FileType,UBYTE *NoOfFiles) +{ + switch (VarsUi.FNOFState) + { + case 0 : + { + *NoOfFiles = 0; + + if (FileType >= FILETYPES) + { + FileType = FILETYPE_ALL; + } + sprintf((char*)VarsUi.FNOFSearchBuffer,"*.%s",TXT_FILE_EXT[FileType]); + + VarsUi.FNOFHandle = pMapLoader->pFunc(FINDFIRST,VarsUi.FNOFSearchBuffer,VarsUi.FNOFNameBuffer,&VarsUi.FNOFLength); + if (!(VarsUi.FNOFHandle & 0x8000)) + { + *NoOfFiles = 1; + VarsUi.FNOFState++; + } + } + break; + + case 1 : + { + VarsUi.FNOFHandle = pMapLoader->pFunc(FINDNEXT,(UBYTE*)&VarsUi.FNOFHandle,VarsUi.FNOFNameBuffer,&VarsUi.FNOFLength); + if (!(VarsUi.FNOFHandle & 0x8000)) + { + *NoOfFiles += 1; + } + else + { + pMapLoader->pFunc(CLOSE,(UBYTE*)&VarsUi.FNOFHandle,NULL,NULL); + VarsUi.FNOFState = 0; + } + } + break; + + } + + return (VarsUi.FNOFState); +} + + +UBYTE cUiFindNameForFileNo(UBYTE FileType,UBYTE FileNo,UBYTE *Name) +{ + switch (VarsUi.FNOFState) + { + case 0 : + { + Name[0] = 0; + + if (FileNo) + { + if (FileType >= FILETYPES) + { + FileType = FILETYPE_ALL; + } + sprintf((char*)VarsUi.FNOFSearchBuffer,"*.%s",TXT_FILE_EXT[FileType]); + + VarsUi.FNOFHandle = pMapLoader->pFunc(FINDFIRST,VarsUi.FNOFSearchBuffer,Name,&VarsUi.FNOFLength); + if (!(VarsUi.FNOFHandle & 0x8000)) + { + if (FileNo != 1) + { + VarsUi.FNOFFileNo = 1; + VarsUi.FNOFState++; + } + else + { + pMapLoader->pFunc(CLOSE,(UBYTE*)&VarsUi.FNOFHandle,NULL,NULL); + } + } + } + } + break; + + case 1 : + { + VarsUi.FNOFHandle = pMapLoader->pFunc(FINDNEXT,(UBYTE*)&VarsUi.FNOFHandle,Name,&VarsUi.FNOFLength); + if (!(VarsUi.FNOFHandle & 0x8000)) + { + VarsUi.FNOFFileNo++; + if (FileNo == VarsUi.FNOFFileNo) + { + pMapLoader->pFunc(CLOSE,(UBYTE*)&VarsUi.FNOFHandle,NULL,NULL); + VarsUi.FNOFState = 0; + } + } + else + { + pMapLoader->pFunc(CLOSE,(UBYTE*)&VarsUi.FNOFHandle,NULL,NULL); + VarsUi.FNOFState = 0; + } + } + break; + + } + + return (VarsUi.FNOFState); +} + + +UBYTE cUiFileList(UBYTE Action) // Show files and select +{ + switch (Action) + { + case MENU_INIT : + { + if (!VarsUi.State) + { + VarsUi.FileCenter = 1; + VarsUi.NextState = IOMapUi.State; + } + Action = MENU_DRAW; + } + break; + + case MENU_LEFT : + { + if (!VarsUi.State) + { + cUiListLeft(VarsUi.NoOfFiles,&VarsUi.FileCenter); + VarsUi.NextState = TEST_BUTTONS; + } + Action = MENU_DRAW; + } + break; + + case MENU_RIGHT : + { + if (!VarsUi.State) + { + cUiListRight(VarsUi.NoOfFiles,&VarsUi.FileCenter); + VarsUi.NextState = TEST_BUTTONS; + } + Action = MENU_DRAW; + } + break; + + case MENU_SELECT : + { + } + break; + + default : + { + if (Action < FILETYPES) + { + if (!VarsUi.State) + { + VarsUi.FileType = Action; + VarsUi.FileCenter = 1; + VarsUi.NextState = IOMapUi.State; + } + Action = MENU_DRAW; + } + else + { + IOMapUi.State = EXIT_PRESSED; + VarsUi.State = 0; + } + } + break; + + } + + if (Action == MENU_DRAW) + { + switch (VarsUi.State) + { + case 0 : + { + VarsUi.FNOFState = 0; + VarsUi.State++; + } + break; + + case 1 : + { + if (cUiFindNoOfFiles(VarsUi.FileType,&VarsUi.NoOfFiles) == 0) + { + if (VarsUi.NoOfFiles) + { + cUiListCalc(VarsUi.NoOfFiles,&VarsUi.FileCenter,&VarsUi.FileLeft,&VarsUi.FileRight); + VarsUi.State++; + } + else + { + VarsUi.State = 0; + IOMapUi.State = EXIT_PRESSED; + } + } + } + break; + + case 2 : + { + if (cUiFindNameForFileNo(VarsUi.FileType,VarsUi.FileCenter,VarsUi.SelectedFilename) == 0) + { + VarsUi.State++; + } + } + break; + + default : + { + pMapDisplay->pMenuIcons[MENUICON_LEFT] = NULL; + pMapDisplay->pMenuIcons[MENUICON_CENTER] = NULL; + pMapDisplay->pMenuIcons[MENUICON_RIGHT] = NULL; + + if (VarsUi.FileLeft) + { + pMapDisplay->pMenuIcons[MENUICON_LEFT] = (UBYTE*)&Icons->Data[(VarsUi.FileType + ALLFILES) * Icons->ItemPixelsX * (Icons->ItemPixelsY / 8)]; + pMapDisplay->UpdateMask |= MENUICON_BIT(MENUICON_LEFT); + } + if (VarsUi.FileCenter) + { + pMapDisplay->pMenuIcons[MENUICON_CENTER] = (UBYTE*)&Icons->Data[(VarsUi.FileType + ALLFILES) * Icons->ItemPixelsX * (Icons->ItemPixelsY / 8)]; + pMapDisplay->UpdateMask |= MENUICON_BIT(MENUICON_CENTER); + } + if (VarsUi.FileRight) + { + pMapDisplay->pMenuIcons[MENUICON_RIGHT] = (UBYTE*)&Icons->Data[(VarsUi.FileType + ALLFILES) * Icons->ItemPixelsX * (Icons->ItemPixelsY / 8)]; + pMapDisplay->UpdateMask |= MENUICON_BIT(MENUICON_RIGHT); + } + + pMapDisplay->EraseMask |= TEXTLINE_BIT(TEXTLINE_5); + + // Search forward for termination + VarsUi.Tmp = 0; + while ((VarsUi.SelectedFilename[VarsUi.Tmp]) && (VarsUi.Tmp < FILENAME_LENGTH)) + { + VarsUi.Tmp++; + } + + // Search backward for "." + while ((VarsUi.Tmp) && (VarsUi.SelectedFilename[VarsUi.Tmp] != '.')) + { + VarsUi.Tmp--; + } + + if (VarsUi.Tmp > DISPLAYLINE_LENGTH) + { + VarsUi.Tmp = DISPLAYLINE_LENGTH; + } + + VarsUi.DisplayBuffer[VarsUi.Tmp] = 0; + + // Copy only name not ext + while (VarsUi.Tmp) + { + VarsUi.Tmp--; + VarsUi.DisplayBuffer[VarsUi.Tmp] = VarsUi.SelectedFilename[VarsUi.Tmp]; + } + + pMapDisplay->pMenuText = VarsUi.DisplayBuffer; + pMapDisplay->EraseMask |= MENUICON_BITS; + pMapDisplay->UpdateMask |= (SPECIAL_BIT(FRAME_SELECT) | SPECIAL_BIT(MENUTEXT)); + + IOMapUi.State = VarsUi.NextState; + VarsUi.State = 0; + } + break; + + } + } + + return (VarsUi.State); +} + + + +//******* cUiVolume ********************************************************** + +UBYTE cUiVolume(UBYTE Action) // MENU_INIT,MENU_LEFT,MENU_RIGHT,MENU_EXIT +{ + switch (Action) + { + case MENU_INIT : // Init time counter and cursor bitmap + { + VarsUi.Counter = cUiNVReadVolumeCount() + 1; + + VarsUi.pTmp = (UBYTE*)Cursor; + for (VarsUi.Tmp = 0;(VarsUi.Tmp < SIZE_OF_CURSOR) && (VarsUi.Tmp < (UBYTE)sizeof(Cursor));VarsUi.Tmp++) + { + VarsUi.CursorTmp[VarsUi.Tmp] = *VarsUi.pTmp; + VarsUi.pTmp++; + } + Action = MENU_DRAW; + } + break; + + case MENU_LEFT : // Dec + { + cUiListLeft(MAX_VOLUME + 1,&VarsUi.Counter); + IOMapUi.Volume = VarsUi.Counter - 1; + Action = MENU_DRAW; + } + break; + + case MENU_RIGHT : // Inc + { + cUiListRight(MAX_VOLUME + 1,&VarsUi.Counter); + IOMapUi.Volume = VarsUi.Counter - 1; + Action = MENU_DRAW; + } + break; + + case MENU_ENTER : // Enter + { + cUiNVWriteVolumeCount(VarsUi.Counter - 1); + IOMapUi.Volume = cUiNVReadVolumeCount(); + pMapSound->Volume = IOMapUi.Volume; + Action = MENU_EXIT; + } + break; + + case MENU_EXIT : // Leave + { + IOMapUi.Volume = cUiNVReadVolumeCount(); + } + break; + + } + if (Action == MENU_DRAW) + { + sprintf((char*)VarsUi.DisplayBuffer,"%u",(UWORD)VarsUi.Counter - 1); + pMapDisplay->pTextLines[TEXTLINE_3] = VarsUi.DisplayBuffer; + + pMapDisplay->pBitmaps[BITMAP_1] = (BMPMAP*)VarsUi.CursorTmp; + VarsUi.CursorTmp[4] = 46; + VarsUi.CursorTmp[5] = 24; + pMapDisplay->EraseMask |= (TEXTLINE_BIT(TEXTLINE_3) | TEXTLINE_BIT(TEXTLINE_4)); + pMapDisplay->TextLinesCenterFlags |= TEXTLINE_BIT(TEXTLINE_3); + pMapDisplay->UpdateMask |= (TEXTLINE_BIT(TEXTLINE_3) | BITMAP_BIT(BITMAP_1)); + } + if (Action == MENU_EXIT) + { + IOMapUi.State = EXIT_PRESSED; + } + + return (0); +} + + + +//******* cUiGetUserString *************************************************** + +#define STRINGTYPES 2 + +#define TOPTEXT_LINE TEXTLINE_3 +#define STRING_LINE TEXTLINE_5 + +typedef struct +{ + const UBYTE Text; + const UBYTE *Figures; + const UBYTE NoOfFigures; + const UBYTE MaxStringLength; + const UBYTE WindowSize; + const SBYTE DefaultPointer; +} +STRSETS; + +const UBYTE PincodeFigures[] = { "0987654321" "\x7F" "abcdefghijklmnopqrstuvwxyz " }; +const UBYTE FilenameFigures[] = { "0987654321" "\x7F" "abcdefghijklmnopqrstuvwxyz " }; + +const STRSETS StrSets[STRINGTYPES] = +{ + { TXT_GETUSERSTRING_PIN, PincodeFigures, 37, SIZE_OF_BT_PINCODE - 1, 15, 10 }, + { TXT_GETUSERSTRING_FILENAME, FilenameFigures, 37, FILENAME_LENGTH - 4 , 15, 10 } +}; + + +UBYTE cUiGetUserString(UBYTE Type) // 0=Pincode, 1=filename +{ + UBYTE Tmp1; + SBYTE Tmp2; + + if (Type < STRINGTYPES) + { + switch (VarsUi.GUSState) + { + case 0 : // Init screen + { + // Disable update and prepare screen + pMapDisplay->EraseMask |= SCREEN_BIT(SCREEN_LARGE); + pMapDisplay->pBitmaps[BITMAP_1] = (BMPMAP*)Ok; + + // Set figure pointer to default + VarsUi.FigurePointer = (SBYTE)StrSets[Type].DefaultPointer; + + // Calculate cursor from default string + VarsUi.GUSCursor = 0; + while ((VarsUi.GUSCursor < DISPLAYLINE_LENGTH) && VarsUi.UserString[VarsUi.GUSCursor]) + { + VarsUi.GUSCursor++; + } + VarsUi.GUSNoname = TRUE; + + VarsUi.GUSState++; + } + break; + + case 1 : // Update user string + { + if (!(pMapDisplay->EraseMask & SCREEN_BIT(SCREEN_LARGE))) + { + // Display top text + pMapDisplay->pTextLines[TOPTEXT_LINE] = cUiGetString(StrSets[Type].Text); + pMapDisplay->UpdateMask |= TEXTLINE_BIT(TOPTEXT_LINE); + + Tmp1 = 0; + while (VarsUi.UserString[Tmp1] && (Tmp1 < StrSets[Type].MaxStringLength)) + { + VarsUi.DisplayText[Tmp1] = VarsUi.UserString[Tmp1]; + Tmp1++; + } + if (Tmp1 < StrSets[Type].MaxStringLength) + { + VarsUi.DisplayText[Tmp1] = '_'; + Tmp1++; + } + while (Tmp1 < StrSets[Type].MaxStringLength) + { + VarsUi.DisplayText[Tmp1] = ' '; + Tmp1++; + } + VarsUi.DisplayText[Tmp1] = 0; + + pMapDisplay->pTextLines[STRING_LINE] = VarsUi.DisplayText; + pMapDisplay->UpdateMask |= (TEXTLINE_BIT(STRING_LINE) | SPECIAL_BIT(TOPLINE)); + pMapDisplay->EraseMask |= BITMAP_BIT(BITMAP_1); + VarsUi.GUSState++; + } + } + break; + + case 2 : // Update figure string + { + if (!(pMapDisplay->EraseMask & BITMAP_BIT(BITMAP_1))) + { + Tmp2 = VarsUi.FigurePointer; + + for (Tmp1 = 0;Tmp1 < 3;Tmp1++) + { + if (Tmp2) + { + Tmp2--; + } + else + { + Tmp2 = StrSets[Type].NoOfFigures - 1; + } + } + for (Tmp1 = 0;Tmp1 < 7;Tmp1++) + { + if ((Tmp1 == 3) && (StrSets[Type].Figures[Tmp2] == 0x7F)) + { + pMapDisplay->UpdateMask |= BITMAP_BIT(BITMAP_1); + } + else + { + pMapDisplay->pFunc(DISPLAY_CHAR,TRUE,5 + Tmp1 * 14,52,StrSets[Type].Figures[Tmp2],0); + } + if (Tmp2 < (StrSets[Type].NoOfFigures - 1)) + { + Tmp2++; + } + else + { + Tmp2 = 0; + } + } + pMapDisplay->pFunc(DISPLAY_HORISONTAL_LINE,TRUE,42,47,57,0); + pMapDisplay->pFunc(DISPLAY_VERTICAL_LINE,TRUE,42,47,0,63); + pMapDisplay->pFunc(DISPLAY_VERTICAL_LINE,TRUE,57,47,0,63); + + VarsUi.GUSState++; + } + } + break; + + case 3 : // Get user input + { + if ((pMapButton->State[BTN4] & LONG_PRESSED_EV)) + { + if (VarsUi.GUSCursor) + { + if ((VarsUi.UserString[VarsUi.GUSCursor - 1] >= 'a') && (VarsUi.UserString[VarsUi.GUSCursor - 1] <= 'z')) + { + VarsUi.UserString[VarsUi.GUSCursor - 1] -= ' '; + VarsUi.GUSState -= 2; + } + } + } + + switch (cUiReadButtons()) + { + case BUTTON_LEFT : + { + if (VarsUi.FigurePointer) + { + VarsUi.FigurePointer--; + } + else + { + VarsUi.FigurePointer = StrSets[Type].NoOfFigures - 1; + } + pMapDisplay->EraseMask |= BITMAP_BIT(BITMAP_1); + VarsUi.GUSState -= 2; + } + break; + + case BUTTON_ENTER : + { + switch (StrSets[Type].Figures[VarsUi.FigurePointer]) + { + case 0x7F : + { + VarsUi.GUSState = 100; + } + break; + + default : + { + VarsUi.GUSNoname = FALSE; + if (VarsUi.GUSCursor < StrSets[Type].MaxStringLength) + { + VarsUi.UserString[VarsUi.GUSCursor] = StrSets[Type].Figures[VarsUi.FigurePointer]; + VarsUi.GUSCursor++; + VarsUi.UserString[VarsUi.GUSCursor] = 0; + VarsUi.GUSState -= 2; + } + } + break; + + } + } + break; + + case BUTTON_RIGHT : + { + if (VarsUi.FigurePointer < (StrSets[Type].NoOfFigures - 1)) + { + VarsUi.FigurePointer++; + } + else + { + VarsUi.FigurePointer = 0; + } + pMapDisplay->EraseMask |= BITMAP_BIT(BITMAP_1); + VarsUi.GUSState -= 2; + } + break; + + case BUTTON_EXIT : + { + if (VarsUi.GUSCursor) + { + if (VarsUi.GUSNoname == TRUE) + { + VarsUi.GUSNoname = FALSE; + while (VarsUi.GUSCursor) + { + VarsUi.UserString[VarsUi.GUSCursor] = 0; + VarsUi.GUSCursor--; + } + } + else + { + VarsUi.GUSCursor--; + } + VarsUi.UserString[VarsUi.GUSCursor] = 0; + VarsUi.GUSState -= 2; + } + else + { + VarsUi.UserString[0] = 0; + VarsUi.GUSState = 100; + } + } + break; + + } + } + break; + + default : // Clean up screen + { + pMapDisplay->EraseMask |= SCREEN_BIT(SCREEN_BACKGROUND); + pMapDisplay->UpdateMask = 0; + IOMapUi.Flags |= UI_REDRAW_STATUS; + VarsUi.GUSState = 0; + } + break; + } + } + + return (VarsUi.GUSState); +} + + + +//******* cUiDataLogging ***************************************************** + +void cUiDrawPortNo(UBYTE *Bitmap,UBYTE MenuIconNo,UBYTE PortNo) +{ + UBYTE Tmp; + + Bitmap[0] = (UBYTE)(FILEFORMAT_BITMAP >> 8); + Bitmap[1] = (UBYTE)(FILEFORMAT_BITMAP); + Bitmap[2] = (UBYTE)(SIZE_OF_PORTBITMAP >> 8); + Bitmap[3] = (UBYTE)(SIZE_OF_PORTBITMAP); + Bitmap[4] = DISPLAY_MENUICONS_X_OFFS + DISPLAY_MENUICONS_X_DIFF * MenuIconNo + 2; + Bitmap[5] = DISPLAY_MENUICONS_Y; + Bitmap[6] = Port[0].ItemPixelsX; + Bitmap[7] = Port[0].ItemPixelsY; + + Tmp = 0; + while (Tmp < Bitmap[6]) + { + Bitmap[Tmp + FILEHEADER_LENGTH] = Port[0].Data[Tmp + PortNo * Bitmap[6]]; + Tmp++; + } + +} + +//******* cUiRunning ********************************************************** + +void cUiRunning(UBYTE Action) +{ + switch (Action) + { + case MENU_INIT : + { + VarsUi.RunIconSave = pMapDisplay->pMenuIcons[MENUICON_CENTER]; + VarsUi.RunBitmapPointer = 0; + VarsUi.RunTimer = 0; + pMapDisplay->EraseMask |= SCREEN_BIT(SCREEN_LARGE); + pMapDisplay->UpdateMask |= SPECIAL_BIT(TOPLINE); + } + break; + + case MENU_RUN : + { + if ((IOMapUi.Flags & UI_ENABLE_STATUS_UPDATE)) + { + if (++VarsUi.RunTimer >= RUN_BITMAP_CHANGE_TIME) + { + VarsUi.RunTimer = 0; + if (++VarsUi.RunBitmapPointer >= Running->ItemsY ) + { + VarsUi.RunBitmapPointer = 0; + } + pMapDisplay->pMenuIcons[MENUICON_CENTER] = (UBYTE*)&Running->Data[VarsUi.RunBitmapPointer * Running->ItemPixelsX * (Running->ItemPixelsY / 8)]; + pMapDisplay->EraseMask |= MENUICON_BIT(MENUICON_CENTER); + pMapDisplay->UpdateMask |= MENUICON_BIT(MENUICON_CENTER); + } + } + } + break; + + case MENU_UPDATE : + { + pMapDisplay->pMenuIcons[MENUICON_CENTER] = (UBYTE*)&Running->Data[VarsUi.RunBitmapPointer * Running->ItemPixelsX * (Running->ItemPixelsY / 8)]; + pMapDisplay->UpdateMask |= MENUICON_BIT(MENUICON_CENTER); + } + break; + + case MENU_EXIT : + { + pMapDisplay->pMenuIcons[MENUICON_CENTER] = VarsUi.RunIconSave; + pMapDisplay->UpdateMask = MENUICON_BITS | SPECIAL_BIT(MENUTEXT); + } + break; + + } +} + +//******* cUiOnBrickProgramming ********************************************** + +UBYTE cUiOnBrickProgramming(UBYTE Action) // On brick programming +{ + switch (Action) + { + case MENU_INIT : // Show motor / sensor text + { + pMapDisplay->pTextLines[TEXTLINE_3] = cUiGetString(TXT_ONBRICKPROGRAMMING_PLEASE_USE_PORT); + pMapDisplay->pTextLines[TEXTLINE_4] = cUiGetString(TXT_ONBRICKPROGRAMMING_1_TOUCH_SENSOR); + pMapDisplay->pTextLines[TEXTLINE_5] = cUiGetString(TXT_ONBRICKPROGRAMMING_2_SOUND_SENSOR); + pMapDisplay->pTextLines[TEXTLINE_6] = cUiGetString(TXT_ONBRICKPROGRAMMING_3_LIGHT_SENSOR); + pMapDisplay->pTextLines[TEXTLINE_7] = cUiGetString(TXT_ONBRICKPROGRAMMING_4_ULTRA_SONIC); + pMapDisplay->pTextLines[TEXTLINE_8] = cUiGetString(TXT_ONBRICKPROGRAMMING_BC_LR_MOTORS); + pMapDisplay->EraseMask |= (TEXTLINE_BIT(TEXTLINE_3) | TEXTLINE_BIT(TEXTLINE_4) | TEXTLINE_BIT(TEXTLINE_5) | TEXTLINE_BIT(TEXTLINE_6) | TEXTLINE_BIT(TEXTLINE_7) | TEXTLINE_BIT(TEXTLINE_8)); + pMapDisplay->UpdateMask &= ~SPECIAL_BIT(FRAME_SELECT); + pMapDisplay->UpdateMask |= (TEXTLINE_BIT(TEXTLINE_3) | TEXTLINE_BIT(TEXTLINE_4) | TEXTLINE_BIT(TEXTLINE_5) | TEXTLINE_BIT(TEXTLINE_6) | TEXTLINE_BIT(TEXTLINE_7) | TEXTLINE_BIT(TEXTLINE_8) | SPECIAL_BIT(TOPLINE)); + pMapDisplay->TextLinesCenterFlags |= (TEXTLINE_BIT(TEXTLINE_3) | TEXTLINE_BIT(TEXTLINE_4) | TEXTLINE_BIT(TEXTLINE_5) | TEXTLINE_BIT(TEXTLINE_6) | TEXTLINE_BIT(TEXTLINE_7) | TEXTLINE_BIT(TEXTLINE_8)); + IOMapUi.State = TEST_BUTTONS; + } + break; + + case MENU_TEXT : // Show empty program steps + { + pMapDisplay->EraseMask |= SCREEN_BIT(SCREEN_LARGE); + + VarsUi.pTmp = (UBYTE*)Cursor; + for (VarsUi.Tmp = 0;(VarsUi.Tmp < SIZE_OF_CURSOR) && (VarsUi.Tmp < (UBYTE)sizeof(Cursor));VarsUi.Tmp++) + { + VarsUi.CursorTmp[VarsUi.Tmp] = *VarsUi.pTmp; + VarsUi.pTmp++; + } + + for (VarsUi.ProgramStepPointer = 0;VarsUi.ProgramStepPointer < ON_BRICK_PROGRAMSTEPS;VarsUi.ProgramStepPointer++) + { + VarsUi.ProgramSteps[VarsUi.ProgramStepPointer] = MENU_ACTION_EMPTY; + } + VarsUi.ProgramStepPointer = 0; + Action = MENU_DRAW; + } + break; + + case MENU_EXIT : // Delete one steps and exit at the end + { + if (VarsUi.ProgramStepPointer) + { + if (VarsUi.ProgramStepPointer < ON_BRICK_PROGRAMSTEPS) + { + VarsUi.ProgramSteps[VarsUi.ProgramStepPointer] = MENU_ACTION_EMPTY; + } + VarsUi.ProgramStepPointer--; + } + else + { + IOMapUi.State = NEXT_MENU; + } + Action = MENU_DRAW; + } + break; + + case MENU_RUN : // Run program steps until end or user press exit button + { + switch (VarsUi.State) + { + case 0 : + { + VarsUi.pTmp = (UBYTE*)Cursor; + for (VarsUi.Tmp = 0;(VarsUi.Tmp < SIZE_OF_CURSOR) && (VarsUi.Tmp < (UBYTE)sizeof(Cursor));VarsUi.Tmp++) + { + VarsUi.CursorTmp[VarsUi.Tmp] = *VarsUi.pTmp; + VarsUi.pTmp++; + } + pMapDisplay->pBitmaps[BITMAP_1] = (BMPMAP*)VarsUi.CursorTmp; + cUiRunning(MENU_INIT); + Action = MENU_DRAW; + VarsUi.State++; + } + break; + + case 1 : // If sound finished -> Init text and program pointer + { + if (SOUND_IDLE == pMapSound->State) + { + VarsUi.ProgramStepPointer = ON_BRICK_PROGRAMSTEPS; + VarsUi.MenuIconTextSave = pMapDisplay->pMenuText; + pMapDisplay->EraseMask |= SPECIAL_BIT(MENUTEXT); + VarsUi.State++; + } + } + break; + + case 2 : // load file to run + { + if (PROG_IDLE == pMapCmd->ProgStatus) + { + sprintf((char*)pMapCmd->FileName,"%s.%s",(char*)VM_PROGRAM_READER,(char*)TXT_SYS_EXT); + pMapCmd->ActivateFlag = TRUE; + VarsUi.State++; + } + } + break; + + case 3 : // Wait for end of file + { + if (PROG_RUNNING != pMapCmd->ProgStatus) + { + pMapCmd->ProgStatus = PROG_RESET; + VarsUi.State = 99; + VarsUi.ProgramStepPointer = ON_BRICK_PROGRAMSTEPS; + } + else + { + if (VarsUi.OBPTimer >= MIN_DISPLAY_UPDATE_TIME) + { + if (IOMapUi.OBPPointer != VarsUi.ProgramStepPointer) + { + VarsUi.ProgramStepPointer = IOMapUi.OBPPointer; + Action = MENU_DRAW; + } + } + } + } + break; + + default : // Program stopped + { + pMapDisplay->pMenuText = VarsUi.MenuIconTextSave; + pMapDisplay->UpdateMask |= SPECIAL_BIT(MENUTEXT); + Action = MENU_DRAW; + VarsUi.State = 0; + } + break; + + } + if (VarsUi.State) + { + cUiRunning(MENU_RUN); + } + else + { + cUiRunning(MENU_EXIT); + } + } + break; + + case MENU_LEFT : // NA + { + IOMapUi.State = TEST_BUTTONS; + } + break; + + case MENU_RIGHT : // NA + { + IOMapUi.State = TEST_BUTTONS; + } + break; + + case MENU_UPDATE : // NA + { + Action = MENU_DRAW; + } + break; + + case MENU_SAVE : // Save NXT program + { + switch (VarsUi.State) + { + case 0 : + { + // Suggest default filename to user + strcpy((char*)VarsUi.UserString,(char*)DEFAULT_PROGRAM_NAME); + VarsUi.State++; + } + break; + + case 1 : + { + if (!cUiGetUserString(1)) + { + if (VarsUi.UserString[0]) + { + sprintf((char*)VarsUi.SelectedFilename,"%s.%s",VarsUi.UserString,TXT_FILE_EXT[FILETYPE_NXT]); + + // If tmp file exist -> ask for overwrite + VarsUi.TmpHandle = pMapLoader->pFunc(FINDFIRST,(UBYTE*)VarsUi.SelectedFilename,VarsUi.FilenameBuffer,&VarsUi.TmpLength); + if (!(VarsUi.TmpHandle & 0x8000)) + { + pMapLoader->pFunc(CLOSE,(UBYTE*)&VarsUi.TmpHandle,NULL,NULL); + VarsUi.State++; + } + else + { + VarsUi.State += 2; + } + } + else + { + VarsUi.State = 99; + } + } + } + break; + + case 2 : + { + if (!cUiFeedback((BMPMAP*)Fail,TXT_FB_OBP_FILE_EXIST_FAIL,TXT_FB_OBP_OVERWRITE_FAIL,0)) + { + VarsUi.State = 0; + } + } + break; + + case 3 : + { + // Rename TEMP_PROGRAM_FILENAME to VarsUi.SelectedFilename(user filename) + sprintf((char*)VarsUi.FilenameBuffer,"%s.%s",(char*)TEMP_PROGRAM_FILENAME,(char*)TXT_TMP_EXT); + VarsUi.TmpHandle = pMapLoader->pFunc(RENAMEFILE,VarsUi.FilenameBuffer,VarsUi.SelectedFilename,&VarsUi.TmpLength); + pMapLoader->pFunc(CLOSE,(UBYTE*)&VarsUi.TmpHandle,NULL,NULL); + VarsUi.State++; + } + break; + + case 4 : // Display saved text + { + if (!cUiFeedback((BMPMAP*)Info,TXT_FB_OBP_FILE_SAVED_INFO,0,DISPLAY_SHOW_TIME)) + { + VarsUi.State++; + } + } + break; + + default : + { + cUiMenuPrevFile(); + IOMapUi.State = NEXT_MENU; + VarsUi.State = 0; + } + break; + + } + } + break; + + case MENU_OVERWRITE : // Over write existing file + { + switch (VarsUi.State) + { + case 0 : + { + // Delete VarsUi.SelectedFilename(user filename) + VarsUi.TmpHandle = pMapLoader->pFunc(FINDFIRST,(UBYTE*)VarsUi.SelectedFilename,VarsUi.FilenameBuffer,&VarsUi.TmpLength); + if (!(VarsUi.TmpHandle & 0x8000)) + { + pMapLoader->pFunc(CLOSE,(UBYTE*)&VarsUi.TmpHandle,NULL,NULL); + pMapLoader->pFunc(DELETE,VarsUi.SelectedFilename,NULL,NULL); + } + + // Rename TEMP_PROGRAM_FILENAME to VarsUi.SelectedFilename(user filename) + sprintf((char*)VarsUi.FilenameBuffer,"%s.%s",(char*)TEMP_PROGRAM_FILENAME,(char*)TXT_TMP_EXT); + VarsUi.TmpHandle = pMapLoader->pFunc(RENAMEFILE,VarsUi.FilenameBuffer,VarsUi.SelectedFilename,&VarsUi.TmpLength); + pMapLoader->pFunc(CLOSE,(UBYTE*)&VarsUi.TmpHandle,NULL,NULL); + VarsUi.State++; + } + break; + + default : // Display saved text + { + if (!cUiFeedback((BMPMAP*)Info,TXT_FB_OBP_FILE_SAVED_INFO,0,DISPLAY_SHOW_TIME)) + { + VarsUi.State = 0; + } + } + break; + + } + + } + break; + + default : // Insert selected action/waitfor in program and save if finished + { + switch (VarsUi.State) + { + case 0 : + { + VarsUi.ProgramSteps[VarsUi.ProgramStepPointer] = Action; + if (VarsUi.ProgramStepPointer < ON_BRICK_PROGRAMSTEPS) + { + VarsUi.ProgramStepPointer++; + } + if (VarsUi.ProgramStepPointer == ON_BRICK_PROGRAMSTEPS) + { + // If tmp file exist -> delete it + sprintf((char*)VarsUi.FilenameBuffer,"%s.%s",(char*)TEMP_PROGRAM_FILENAME,(char*)TXT_TMP_EXT); + VarsUi.TmpHandle = pMapLoader->pFunc(FINDFIRST,VarsUi.FilenameBuffer,VarsUi.SearchFilenameBuffer,&VarsUi.TmpLength); + if (!(VarsUi.TmpHandle & 0x8000)) + { + pMapLoader->pFunc(CLOSE,(UBYTE*)&VarsUi.TmpHandle,NULL,NULL); + pMapLoader->pFunc(DELETE,VarsUi.FilenameBuffer,NULL,NULL); + } + + // Save program as tmp file + VarsUi.TmpLength = FILEHEADER_LENGTH + ON_BRICK_PROGRAMSTEPS; + VarsUi.TmpHandle = pMapLoader->pFunc(OPENWRITE,VarsUi.FilenameBuffer,NULL,&VarsUi.TmpLength); + if (!(VarsUi.TmpHandle & 0x8000)) + { + VarsUi.FileHeader[0] = (UBYTE)(FILEFORMAT_PROGRAM >> 8); + VarsUi.FileHeader[1] = (UBYTE)(FILEFORMAT_PROGRAM); + VarsUi.FileHeader[2] = (UBYTE)(ON_BRICK_PROGRAMSTEPS >> 8); + VarsUi.FileHeader[3] = (UBYTE)(ON_BRICK_PROGRAMSTEPS); + VarsUi.FileHeader[4] = (UBYTE)(ON_BRICK_PROGRAMSTEPS); + VarsUi.FileHeader[5] = (UBYTE)0; + VarsUi.FileHeader[6] = (UBYTE)0; + VarsUi.FileHeader[7] = (UBYTE)0; + VarsUi.TmpLength = FILEHEADER_LENGTH; + pMapLoader->pFunc(WRITE,(UBYTE*)&VarsUi.TmpHandle,(UBYTE*)VarsUi.FileHeader,&VarsUi.TmpLength); + VarsUi.TmpLength = ON_BRICK_PROGRAMSTEPS; + pMapLoader->pFunc(WRITE,(UBYTE*)&VarsUi.TmpHandle,(UBYTE*)VarsUi.ProgramSteps,&VarsUi.TmpLength); + pMapLoader->pFunc(CLOSE,(UBYTE*)&VarsUi.TmpHandle,NULL,NULL); + } + else + { + VarsUi.State++; + } + } + Action = MENU_DRAW; + } + break; + + default : // Display memory error text + { + if (!cUiFeedback((BMPMAP*)Fail,TXT_FB_OBP_MEMORY_FULL_FAIL,0,DISPLAY_SHOW_ERROR_TIME)) + { + cUiMenuPrevFile(); + IOMapUi.State = NEXT_MENU; + VarsUi.State = 0; + } + } + break; + + } + } + break; + + } + + // Update display screen + if (Action == MENU_DRAW) + { + VarsUi.OBPTimer = 0; + + for (VarsUi.Pointer = 0;VarsUi.Pointer < ON_BRICK_PROGRAMSTEPS;VarsUi.Pointer++) + { + VarsUi.Tmp = VarsUi.ProgramSteps[VarsUi.Pointer]; + if ((VarsUi.Tmp >= MENU_ACTION_EMPTY) && (VarsUi.Tmp < MENU_ACTION_INVALID)) + { + VarsUi.Tmp -= MENU_ACTION_EMPTY; + pMapDisplay->StepIcons[VarsUi.Pointer] = VarsUi.Tmp + 1; + } + if ((VarsUi.Tmp >= MENU_WAIT_EMPTY) && (VarsUi.Tmp < MENU_WAIT_INVALID)) + { + VarsUi.Tmp -= MENU_WAIT_EMPTY; + pMapDisplay->StepIcons[VarsUi.Pointer] = VarsUi.Tmp + 1 + 16; + } + if (VarsUi.Tmp == MENU_LOOP) + { + pMapDisplay->StepIcons[VarsUi.Pointer] = 31; + } + if (VarsUi.Tmp == MENU_STOP) + { + pMapDisplay->StepIcons[VarsUi.Pointer] = 32; + } + pMapDisplay->UpdateMask |= STEPICON_BIT(STEPICON_1 + VarsUi.Pointer); + } + + // and cursor + pMapDisplay->pBitmaps[BITMAP_1] = (BMPMAP*)VarsUi.CursorTmp; + if (VarsUi.ProgramStepPointer < ON_BRICK_PROGRAMSTEPS) + { + VarsUi.CursorTmp[4] = 13 + (VarsUi.ProgramStepPointer * 17); + VarsUi.CursorTmp[5] = 24; + pMapDisplay->UpdateMask |= BITMAP_BIT(BITMAP_1); + } + if (PROG_RUNNING != pMapCmd->ProgStatus) + { + pMapDisplay->EraseMask |= (TEXTLINE_BIT(TEXTLINE_3) | TEXTLINE_BIT(TEXTLINE_2)); + } + pMapDisplay->EraseMask |= TEXTLINE_BIT(TEXTLINE_4); + pMapDisplay->UpdateMask |= (SPECIAL_BIT(STEPLINE) | SPECIAL_BIT(TOPLINE)); + } + + return (VarsUi.State); +} + + + +//******* cUiFileRun ********************************************************** + +UBYTE cUiFindFileType(UBYTE *Filename) // Find file type number +{ + UBYTE Ext[FILENAME_LENGTH + 1]; + UBYTE Result; + UBYTE Tmp1; + UBYTE Tmp2; + + Result = FILETYPE_ALL; + + Tmp1 = 0; + while ((Filename[Tmp1]) && (Tmp1 < FILENAME_LENGTH)) // Search forward for termination + { + Tmp1++; + } + + while ((Tmp1) && (Filename[Tmp1] != '.')) // Search backward for "." + { + Tmp1--; + } + + if (Filename[Tmp1] == '.') // If "." + { + Tmp1++; + Tmp2 = 0; + + while ((Filename[Tmp1]) && (Tmp1 < FILENAME_LENGTH)) // Convert to upper to Ext + { + Ext[Tmp2] = tolower(Filename[Tmp1]); + Tmp1++; + Tmp2++; + } + Ext[Tmp2] = 0; // Inser termination + + // Calculate type + for (Tmp1 = FILETYPE_ALL;(Tmp1 < FILETYPES) && (Result == FILETYPE_ALL);Tmp1++) + { + if (strcmp((char*)TXT_FILE_EXT[Tmp1],(char*)Ext) == 0) + { + Result = Tmp1; + } + } + } + + return (Result); +} + + +#define FILERUN_FILENAMELINE TEXTLINE_4 +#define FILERUN_TEXTLINE TEXTLINE_5 + +UBYTE cUiFileRun(UBYTE Action) // Run selected file +{ + switch (Action) + { + + case MENU_INIT : + { + VarsUi.Tmp = 0; + while ((VarsUi.SelectedFilename[VarsUi.Tmp]) && (VarsUi.Tmp < FILENAME_LENGTH)) // Search forward for termination + { + VarsUi.Tmp++; + } + + while ((VarsUi.Tmp) && (VarsUi.SelectedFilename[VarsUi.Tmp] != '.')) // Search backward for "." + { + VarsUi.Tmp--; + } + + if (VarsUi.Tmp > DISPLAYLINE_LENGTH) + { + VarsUi.Tmp = DISPLAYLINE_LENGTH; + } + + VarsUi.DisplayBuffer[VarsUi.Tmp] = 0; + + while (VarsUi.Tmp) // Copy only name not ext + { + VarsUi.Tmp--; + VarsUi.DisplayBuffer[VarsUi.Tmp] = VarsUi.SelectedFilename[VarsUi.Tmp]; + } + + pMapDisplay->pTextLines[FILERUN_FILENAMELINE] = (UBYTE*)VarsUi.DisplayBuffer; + pMapDisplay->TextLinesCenterFlags = TEXTLINE_BIT(FILERUN_FILENAMELINE); + pMapDisplay->UpdateMask = TEXTLINE_BIT(FILERUN_FILENAMELINE); + } + break; + + case MENU_RUN : + { + if (VarsUi.Timer < DISPLAY_SHOW_TIME) + { + VarsUi.Timer++; + } + + switch (VarsUi.State) + { + case 0 : + { + IOMapUi.Flags |= UI_BUSY; + VarsUi.State++; + } + break; + + case 1 : // Set state from extention when sound is ready + { + if (SOUND_IDLE == pMapSound->State) + { + pMapDisplay->pTextLines[FILERUN_TEXTLINE] = cUiGetString(TXT_FILERUN_RUNNING); + pMapDisplay->UpdateMask = (TEXTLINE_BIT(FILERUN_TEXTLINE) | TEXTLINE_BIT(FILERUN_FILENAMELINE)); + pMapDisplay->TextLinesCenterFlags = (TEXTLINE_BIT(FILERUN_TEXTLINE) | TEXTLINE_BIT(FILERUN_FILENAMELINE)); + cUiRunning(MENU_INIT); + VarsUi.State++; + } + } + break; + + case 2 : + { + if ((!pMapDisplay->EraseMask) && (!pMapDisplay->UpdateMask)) + { + VarsUi.State = 10 * cUiFindFileType(VarsUi.SelectedFilename); + if (VarsUi.State == (FILETYPE_TRYME * 10)) + { + VarsUi.State = FILETYPE_LMS * 10; + } + } + } + break; + + case (FILETYPE_SOUND * 10 + 0) : // Start sound file (*.snd, *.rso) Wait for sound idle + { + strcpy((char*)pMapSound->SoundFilename,(char*)VarsUi.SelectedFilename); + pMapSound->Volume = IOMapUi.Volume; + pMapSound->Mode = SOUND_ONCE; + pMapSound->Flags |= SOUND_UPDATE; + VarsUi.State++; + } + break; + + case (FILETYPE_SOUND * 10 + 1) : // Wait for stop or user break + { + cUiRunning(MENU_RUN); + + if (SOUND_IDLE == pMapSound->State) + { + pMapDisplay->pTextLines[FILERUN_TEXTLINE] = cUiGetString(TXT_FILERUN_ENDED); + VarsUi.State = 99; + } + if (BUTTON_EXIT == cUiReadButtons()) + { + pMapSound->Flags &= ~SOUND_UPDATE; + pMapSound->State = SOUND_STOP; + pMapDisplay->pTextLines[FILERUN_TEXTLINE] = cUiGetString(TXT_FILERUN_ABORTED); + VarsUi.State = 99; + } + } + break; + + case (FILETYPE_LMS * 10 + 0) : // Start LMS file (*.rxe) + { + if ((!pMapDisplay->EraseMask) && (pMapCmd->ProgStatus == PROG_IDLE) && (!pMapButton->State[BTN4])) + { + strcpy((char*)pMapCmd->FileName,(char*)VarsUi.SelectedFilename); + pMapCmd->ActivateFlag = TRUE; + VarsUi.State++; + } + } + break; + + case (FILETYPE_LMS * 10 + 1) : // Wait for program stop or user break + { + cUiRunning(MENU_RUN); + + if ((IOMapUi.Flags & UI_REDRAW_STATUS) && (IOMapUi.Flags & UI_ENABLE_STATUS_UPDATE)) + { + pMapDisplay->pTextLines[FILERUN_FILENAMELINE] = (UBYTE*)VarsUi.DisplayBuffer; + pMapDisplay->TextLinesCenterFlags = TEXTLINE_BIT(FILERUN_FILENAMELINE); + pMapDisplay->UpdateMask = TEXTLINE_BIT(FILERUN_FILENAMELINE); + pMapDisplay->pTextLines[FILERUN_TEXTLINE] = cUiGetString(TXT_FILERUN_RUNNING); + pMapDisplay->UpdateMask = (TEXTLINE_BIT(FILERUN_TEXTLINE) | TEXTLINE_BIT(FILERUN_FILENAMELINE)); + pMapDisplay->TextLinesCenterFlags = (TEXTLINE_BIT(FILERUN_TEXTLINE) | TEXTLINE_BIT(FILERUN_FILENAMELINE)); + } + + switch (pMapCmd->ProgStatus) + { + case PROG_RUNNING : + { + } + break; + + case PROG_OK : + { + pMapDisplay->pTextLines[FILERUN_TEXTLINE] = cUiGetString(TXT_FILERUN_ENDED); + VarsUi.State = 99; + } + break; + + case PROG_ABORT : + { + pMapDisplay->pTextLines[FILERUN_TEXTLINE] = cUiGetString(TXT_FILERUN_ABORTED); + VarsUi.State = 99; + } + break; + + default : + { + pMapDisplay->pTextLines[FILERUN_TEXTLINE] = cUiGetString(TXT_FILERUN_FILE_ERROR); + VarsUi.State = 99; + } + break; + + } + } + break; + + case (FILETYPE_NXT * 10 + 0) :// Start Program file (*.prg) + { + VarsUi.TmpHandle = pMapLoader->pFunc(OPENREAD,VarsUi.SelectedFilename,NULL,&VarsUi.TmpLength); + if (!(VarsUi.TmpHandle & 0x8000)) + { + VarsUi.TmpLength = FILEHEADER_LENGTH; + pMapLoader->pFunc(READ,(UBYTE*)&VarsUi.TmpHandle,VarsUi.FileHeader,&VarsUi.TmpLength); + VarsUi.TmpLength = ON_BRICK_PROGRAMSTEPS; + pMapLoader->pFunc(READ,(UBYTE*)&VarsUi.TmpHandle,VarsUi.ProgramSteps,&VarsUi.TmpLength); + pMapLoader->pFunc(CLOSE,(UBYTE*)&VarsUi.TmpHandle,NULL,NULL); + } + if ((ON_BRICK_PROGRAMSTEPS == VarsUi.TmpLength) && (VarsUi.FileHeader[0] == (UBYTE)(FILEFORMAT_PROGRAM >> 8)) && (VarsUi.FileHeader[1] == (UBYTE)(FILEFORMAT_PROGRAM))) + { + // If tmp file exist -> delete it + sprintf((char*)VarsUi.FilenameBuffer,"%s.%s",(char*)TEMP_PROGRAM_FILENAME,(char*)TXT_TMP_EXT); + VarsUi.TmpHandle = pMapLoader->pFunc(FINDFIRST,VarsUi.FilenameBuffer,VarsUi.SearchFilenameBuffer,&VarsUi.TmpLength); + if (!(VarsUi.TmpHandle & 0x8000)) + { + pMapLoader->pFunc(CLOSE,(UBYTE*)&VarsUi.TmpHandle,NULL,NULL); + pMapLoader->pFunc(DELETE,VarsUi.FilenameBuffer,NULL,NULL); + } + + // Save program as tmp file + VarsUi.TmpLength = FILEHEADER_LENGTH + ON_BRICK_PROGRAMSTEPS; + VarsUi.TmpHandle = pMapLoader->pFunc(OPENWRITE,VarsUi.FilenameBuffer,NULL,&VarsUi.TmpLength); + if (!(VarsUi.TmpHandle & 0x8000)) + { + VarsUi.TmpLength = FILEHEADER_LENGTH; + pMapLoader->pFunc(WRITE,(UBYTE*)&VarsUi.TmpHandle,(UBYTE*)VarsUi.FileHeader,&VarsUi.TmpLength); + VarsUi.TmpLength = ON_BRICK_PROGRAMSTEPS; + pMapLoader->pFunc(WRITE,(UBYTE*)&VarsUi.TmpHandle,(UBYTE*)VarsUi.ProgramSteps,&VarsUi.TmpLength); + pMapLoader->pFunc(CLOSE,(UBYTE*)&VarsUi.TmpHandle,NULL,NULL); + } + + pMapDisplay->UpdateMask &= ~TEXTLINE_BIT(FILERUN_FILENAMELINE); + pMapDisplay->EraseMask |= TEXTLINE_BIT(FILERUN_FILENAMELINE); + VarsUi.State++; + } + else + { + pMapDisplay->pTextLines[FILERUN_TEXTLINE] = cUiGetString(TXT_FILERUN_FILE_ERROR); + VarsUi.State = 99; + } + VarsUi.GUSState = 0; + } + break; + + case (FILETYPE_NXT * 10 + 1) : // Wait for program stop or user break + { + VarsUi.State = VarsUi.GUSState; + cUiOnBrickProgramming(MENU_RUN); + VarsUi.GUSState = VarsUi.State; + if (VarsUi.State) + { + VarsUi.State = (FILETYPE_NXT * 10 + 1); + } + else + { + pMapDisplay->pTextLines[FILERUN_TEXTLINE] = cUiGetString(TXT_FILERUN_ENDED); + VarsUi.State = 99; + } + } + break; + + case 99 : // Wait for display show time or user action + { + pMapDisplay->EraseMask = SCREEN_BIT(SCREEN_LARGE); + pMapDisplay->UpdateMask = (TEXTLINE_BIT(FILERUN_TEXTLINE) | TEXTLINE_BIT(FILERUN_FILENAMELINE)); + pMapDisplay->TextLinesCenterFlags = (TEXTLINE_BIT(FILERUN_TEXTLINE) | TEXTLINE_BIT(FILERUN_FILENAMELINE)); + IOMapUi.Flags |= UI_REDRAW_STATUS | UI_ENABLE_STATUS_UPDATE; + cUiRunning(MENU_UPDATE); + VarsUi.Timer = 0; + VarsUi.State++; + } + break; + + default : + { + if ((++VarsUi.Timer >= DISPLAY_SHOW_TIME) || (BUTTON_NONE != cUiReadButtons())) + { + if (pMapCmd->ProgStatus != PROG_IDLE) + pMapCmd->ProgStatus = PROG_RESET; + pMapDisplay->UpdateMask = 0; + pMapDisplay->TextLinesCenterFlags = 0; + cUiRunning(MENU_EXIT); + pMapDisplay->EraseMask = TEXTLINE_BIT(FILERUN_TEXTLINE); + pMapDisplay->TextLinesCenterFlags |= TEXTLINE_BIT(FILERUN_FILENAMELINE); + pMapDisplay->UpdateMask |= TEXTLINE_BIT(FILERUN_FILENAMELINE); + IOMapUi.Flags &= ~UI_BUSY; + VarsUi.State = 0; + } + } + break; + + } + } + break; + + } + + return (VarsUi.State); +} + + + +//******* cUiFileDelete ******************************************************* + +UBYTE cUiFileDelete(UBYTE Action) +{ + if (MENU_INIT == Action) + { + switch (VarsUi.State) + { + case 0 : + { + VarsUi.State++; + } + break; + + case 1 : + { + if (SOUND_IDLE == pMapSound->State) + { + VarsUi.State++; + } + } + break; + + case 2 : + { + pMapLoader->pFunc(DELETE,VarsUi.SelectedFilename,NULL,NULL); + VarsUi.State++; + } + break; + + default : // Display deleted text + { + if (!cUiFeedback((BMPMAP*)Info,TXT_FB_FD_FILE_DELETED_INFO,0,DISPLAY_SHOW_TIME)) + { + IOMapUi.State = EXIT_PRESSED; + VarsUi.State = 0; + } + } + break; + + } + } + + return (VarsUi.State); +} + + + +//******* cUiView ************************************************************ + +UBYTE cUiView(UBYTE Action) // MENU_INIT +{ + switch (VarsUi.State) + { + case 0 : + { + switch (Action) + { + case MENU_INIT : // Init + { + pMapDisplay->pTextLines[TEXTLINE_3] = cUiGetString(TXT_VIEW_SELECT); + pMapDisplay->TextLinesCenterFlags |= TEXTLINE_BIT(TEXTLINE_3); + pMapDisplay->UpdateMask |= TEXTLINE_BIT(TEXTLINE_3); + pMapDisplay->EraseMask |= SCREEN_BIT(SCREEN_SMALL); + } + break; + + default : + { + if ((Action > MENU_SENSOR_EMPTY) && (Action < MENU_SENSOR_INVALID)) + { + VarsUi.SelectedSensor = Action; + } + if ((Action >= MENU_PORT_1) && (Action <= MENU_PORT_C)) + { + VarsUi.SelectedPort = Action; + IOMapUi.Flags |= UI_BUSY; + + cUiSetupSensor(VarsUi.SelectedPort,VarsUi.SelectedSensor); + cUiResetSensor(VarsUi.SelectedPort,VarsUi.SelectedSensor); + pMapDisplay->EraseMask |= SCREEN_BIT(SCREEN_LARGE); + pMapDisplay->pBitmaps[BITMAP_1] = (BMPMAP*)Display; + pMapDisplay->UpdateMask = BITMAP_BIT(BITMAP_1); + IOMapUi.Flags |= UI_REDRAW_STATUS; + VarsUi.ReadoutTimer = 0;; + VarsUi.Timer = 0; + VarsUi.State++; + } + } + break; + + } + } + break; + + case 1 : + { + VarsUi.ReadoutTimer++; + VarsUi.Timer++; + if (VarsUi.Timer == MIN_SENSOR_READ_TIME) + { + // Ask sensors for data + cUiAskSensor(VarsUi.SelectedPort,VarsUi.SelectedSensor); + } + if (VarsUi.Timer >= (MIN_SENSOR_READ_TIME * 2)) + { + // Read sensor data + VarsUi.ViewSampleValid = cUiGetSensorValue(VarsUi.SelectedPort,VarsUi.SelectedSensor,&VarsUi.ViewSampleValue); + VarsUi.Timer = 0; + } + + if (VarsUi.ReadoutTimer >= DISPLAY_VIEW_UPDATE) + { + VarsUi.ReadoutTimer = 0; + cUiPrintSensorInDisplayBuffer(VarsUi.SelectedPort,VarsUi.SelectedSensor,VarsUi.ViewSampleValid,VarsUi.ViewSampleValue); + pMapDisplay->pTextLines[TEXTLINE_4] = VarsUi.DisplayBuffer; + pMapDisplay->TextLinesCenterFlags |= TEXTLINE_BIT(TEXTLINE_4); + pMapDisplay->UpdateMask |= TEXTLINE_BIT(TEXTLINE_4); + } + + VarsUi.Tmp = cUiReadButtons(); + if (VarsUi.Tmp == BUTTON_EXIT) + { + pMapDisplay->pTextLines[TEXTLINE_3] = cUiGetString(TXT_VIEW_SELECT); + pMapDisplay->TextLinesCenterFlags |= TEXTLINE_BIT(TEXTLINE_3); + pMapDisplay->UpdateMask |= TEXTLINE_BIT(TEXTLINE_3); + pMapDisplay->UpdateMask &= ~TEXTLINE_BIT(TEXTLINE_4); + pMapDisplay->EraseMask |= SCREEN_BIT(SCREEN_SMALL); + VarsUi.State++; + } + if (VarsUi.Tmp == BUTTON_ENTER) + { + cUiResetSensor(VarsUi.SelectedPort,VarsUi.SelectedSensor); + } + } + break; + + default : + { + cUiReleaseSensors(); + IOMapUi.Flags &= ~UI_BUSY; + VarsUi.State = 0; + IOMapUi.State = EXIT_PRESSED; + } + break; + + } + + return (VarsUi.State); +} + + + +//******* cUiBtOn ************************************************************ + +UBYTE cUiBtOn(UBYTE Action) +{ + switch (Action) + { + case MENU_ON : + { + switch (VarsUi.State) + { + case 0 : // Turn BT on + { + VarsUi.BTCommand = (UBYTE)BTON; + VarsUi.BTPar1 = (UBYTE)0; + VarsUi.BTPar2 = (UBYTE)0; + if (pMapComm->pFunc(VarsUi.BTCommand,VarsUi.BTPar1,VarsUi.BTPar2,0,NULL,&(VarsUi.BTResult)) == SUCCESS) + { + VarsUi.State++; + } + else + { + VarsUi.State = 99; + } + } + break; + + case 1 : // Display turning on text + { + if (!cUiFeedback((BMPMAP*)Wait,TXT_FB_BT_TURNING_ON_WAIT,0,0)) + { + VarsUi.State++; + } + } + break; + + case 2 : // Check result + { + if (VarsUi.BTResult != INPROGRESS) + { + if (VarsUi.BTResult == SUCCESS) + { + Action = MENU_EXIT; + } + else + { + VarsUi.State++; + } + } + } + break; + + default : // Display fail text + { + if (!cUiFeedback((BMPMAP*)Fail,TXT_FB_BT_TURNING_ON_FAIL,0,DISPLAY_SHOW_ERROR_TIME)) + { + Action = MENU_EXIT; + } + } + break; + + } + } + break; + + case MENU_OFF : + { + switch (VarsUi.State) + { + case 0 : // Turn BT off + { + VarsUi.BTCommand = (UBYTE)BTOFF; + VarsUi.BTPar1 = (UBYTE)0; + VarsUi.BTPar2 = (UBYTE)0; + if (pMapComm->pFunc(VarsUi.BTCommand,VarsUi.BTPar1,VarsUi.BTPar2,0,NULL,&(VarsUi.BTResult)) == SUCCESS) + { + VarsUi.State++; + } + else + { + VarsUi.State = 99; + } + } + break; + + case 1 : // Display turning off text + { + if (!cUiFeedback((BMPMAP*)Wait,TXT_FB_BT_TURNING_OFF_WAIT,0,0)) + { + VarsUi.State++; + } + } + break; + + case 2 : // Check result + { + if (VarsUi.BTResult != INPROGRESS) + { + if (VarsUi.BTResult == SUCCESS) + { + Action = MENU_EXIT; + } + else + { + VarsUi.State++; + } + } + } + break; + + default : // Display fail text + { + if (!cUiFeedback((BMPMAP*)Fail,TXT_FB_BT_TURNING_OFF_FAIL,0,DISPLAY_SHOW_ERROR_TIME)) + { + Action = MENU_EXIT; + } + } + break; + + } + } + break; + + } + if (Action == MENU_EXIT) + { + VarsUi.State = 0; + IOMapUi.State = EXIT_PRESSED; + } + + return (VarsUi.State); +} + + + +//******* cUiBtVisiability *************************************************** + +UBYTE cUiBtVisiability(UBYTE Action) // Visibility on/off +{ + switch (Action) + { + case MENU_ON : // Set visible + { + switch (VarsUi.State) + { + case 0 : + { + VarsUi.BTCommand = (UBYTE)VISIBILITY; + VarsUi.BTPar1 = (UBYTE)1; + VarsUi.BTPar2 = (UBYTE)0; + if (pMapComm->pFunc(VarsUi.BTCommand,VarsUi.BTPar1,VarsUi.BTPar2,0,NULL,&(VarsUi.BTResult)) == SUCCESS) + { + VarsUi.State++; + } + else + { + Action = MENU_EXIT; + } + } + break; + + default : + { + if (VarsUi.BTResult != INPROGRESS) + { + Action = MENU_EXIT; + } + } + break; + + } + } + break; + + case MENU_OFF : // Set invisible + { + switch (VarsUi.State) + { + case 0 : + { + VarsUi.BTCommand = (UBYTE)VISIBILITY; + VarsUi.BTPar1 = (UBYTE)0; + VarsUi.BTPar2 = (UBYTE)0; + if (pMapComm->pFunc(VarsUi.BTCommand,VarsUi.BTPar1,VarsUi.BTPar2,0,NULL,&(VarsUi.BTResult)) == SUCCESS) + { + VarsUi.State++; + } + else + { + Action = MENU_EXIT; + } + } + break; + + default : + { + if (VarsUi.BTResult != INPROGRESS) + { + Action = MENU_EXIT; + } + } + break; + + } + } + break; + + } + if (Action == MENU_EXIT) + { + VarsUi.State = 0; + IOMapUi.State = EXIT_PRESSED; + } + + return (VarsUi.State); +} + + + +//******* cUiBtSearch ******************************************************** + +UBYTE cUiBtSearch(UBYTE Action) // Search for devices +{ + if (Action == MENU_INIT) // Init + { + switch (VarsUi.State) + { + case 0 : // Show three menu icons + { + pMapDisplay->pMenuIcons[MENUICON_LEFT] = pMapDisplay->pMenuIcons[MENUICON_CENTER]; + pMapDisplay->pMenuIcons[MENUICON_RIGHT] = pMapDisplay->pMenuIcons[MENUICON_CENTER]; + pMapDisplay->UpdateMask |= MENUICON_BITS; + VarsUi.State++; + } + break; + + case 1 : // Display wait text and start search + { + if (!cUiFeedback((BMPMAP*)Wait,TXT_FB_BT_SEARCHING_WAIT,0,0)) + { + VarsUi.BTCommand = (UBYTE)SEARCH; + VarsUi.BTPar1 = (UBYTE)1; + VarsUi.BTPar2 = (UBYTE)0; + if (pMapComm->pFunc(VarsUi.BTCommand,VarsUi.BTPar1,VarsUi.BTPar2,0,NULL,&(VarsUi.BTResult)) == SUCCESS) + { + VarsUi.DisplayBuffer[0] = 0; + pMapDisplay->pMenuText = VarsUi.DisplayBuffer; + pMapDisplay->UpdateMask |= SPECIAL_BIT(MENUTEXT); + VarsUi.NoOfNames = 0; + VarsUi.NoOfDevices = 0; + VarsUi.State++; + } + else + { + VarsUi.State = 99; + } + } + } + break; + + case 2 : // Wait for search finished + { + if (VarsUi.NoOfNames != pMapComm->BtDeviceNameCnt) + { + VarsUi.NoOfNames = pMapComm->BtDeviceNameCnt; + + if ((VarsUi.NoOfNames) && (VarsUi.NoOfNames <= DISPLAYLINE_LENGTH)) + { + sprintf((char*)VarsUi.DisplayBuffer,"%.*s",VarsUi.NoOfNames,"****************"); + pMapDisplay->pMenuText = VarsUi.DisplayBuffer; + pMapDisplay->UpdateMask |= SPECIAL_BIT(MENUTEXT); + } + } + if (VarsUi.NoOfDevices != pMapComm->BtDeviceCnt) + { + VarsUi.NoOfDevices = pMapComm->BtDeviceCnt; + + if ((VarsUi.NoOfDevices) && (VarsUi.NoOfDevices <= DISPLAYLINE_LENGTH)) + { + sprintf((char*)VarsUi.DisplayBuffer,"%.*s",VarsUi.NoOfDevices,"????????????????"); + pMapDisplay->pMenuText = VarsUi.DisplayBuffer; + pMapDisplay->UpdateMask |= SPECIAL_BIT(MENUTEXT); + } + } + + if (VarsUi.BTResult != INPROGRESS) + { + cUiBTCommand(UI_BT_GET_DEVICES,0,&VarsUi.Devices,NULL); + if (VarsUi.Devices) + { + VarsUi.State++; + } + else + { + VarsUi.State = 99; + } + } + + if (cUiReadButtons() == BUTTON_EXIT) + { + VarsUi.BTCommand = (UBYTE)STOPSEARCH; + VarsUi.BTPar1 = (UBYTE)0; + VarsUi.BTPar2 = (UBYTE)0; + pMapComm->pFunc(VarsUi.BTCommand,VarsUi.BTPar1,VarsUi.BTPar2,0,NULL,&(VarsUi.BTResult)); + VarsUi.State = 4; + } + } + break; + + case 3 : // Auto enter to next menu + { + IOMapUi.State = ENTER_PRESSED; + VarsUi.State = 0; + } + break; + + case 4 : // Display info text + { + if (!cUiFeedback((BMPMAP*)Info,TXT_FB_BT_SEARCH_ABORTED_INFO,0,DISPLAY_SHOW_TIME)) + { + VarsUi.State++; + } + } + break; + + case 5 : // Wait for abort + { + if (VarsUi.BTResult != INPROGRESS) + { + cUiBTCommand(UI_BT_GET_DEVICES,0,&VarsUi.Devices,NULL); + if (VarsUi.Devices) + { + VarsUi.State++; + } + else + { + VarsUi.State = 99; + } + } + } + break; + + case 6 : // Auto enter to next menu + { + IOMapUi.State = ENTER_PRESSED; + VarsUi.State = 0; + } + break; + + default : // Display fail text + { + if (!cUiFeedback((BMPMAP*)Fail,TXT_FB_BT_SEARCHING_FAIL,0,DISPLAY_SHOW_ERROR_TIME)) + { + VarsUi.State = 0; + IOMapUi.State = EXIT_PRESSED; + } + } + break; + + } + } + + return (VarsUi.State); +} + + + +//******* cUiBtDeviceList **************************************************** + +UBYTE cUiBtDeviceList(UBYTE Action) // Show devices +{ + switch (Action) + { + case MENU_INIT : // Init "Search" list + { + VarsUi.SelectedDevice = 0; + VarsUi.DevicesKnown = 0; + cUiBTCommand(UI_BT_GET_DEVICES,VarsUi.DevicesKnown,&VarsUi.Devices,NULL); + if (VarsUi.Devices) + { + pMapDisplay->pTextLines[TEXTLINE_3] = cUiGetString(TXT_BTDEVICELIST_SELECT); + pMapDisplay->TextLinesCenterFlags |= TEXTLINE_BIT(TEXTLINE_3); + pMapDisplay->UpdateMask |= TEXTLINE_BIT(TEXTLINE_3); + VarsUi.MenuIconTextSave = pMapDisplay->pMenuText; + VarsUi.DeviceCenter = 1; + Action = MENU_DRAW; + IOMapUi.State = TEST_BUTTONS; + } + else + { + Action = MENU_EXIT; + } + } + break; + + case MENU_INIT_ALTERNATIVE : // Init only "My contacts" + { + VarsUi.SelectedDevice = 0; + VarsUi.DevicesKnown = 1; + cUiBTCommand(UI_BT_GET_DEVICES,VarsUi.DevicesKnown,&VarsUi.Devices,NULL); + if (VarsUi.Devices) + { + pMapDisplay->pTextLines[TEXTLINE_3] = cUiGetString(TXT_BTDEVICELIST_SELECT); + pMapDisplay->TextLinesCenterFlags |= TEXTLINE_BIT(TEXTLINE_3); + pMapDisplay->UpdateMask |= TEXTLINE_BIT(TEXTLINE_3); + VarsUi.MenuIconTextSave = pMapDisplay->pMenuText; + VarsUi.DeviceCenter = 1; + Action = MENU_DRAW; + IOMapUi.State = TEST_BUTTONS; + } + else + { + Action = MENU_EXIT; + } + } + break; + + case MENU_LEFT : // Left button + { + cUiListLeft(VarsUi.Devices,&VarsUi.DeviceCenter); + Action = MENU_DRAW; + IOMapUi.State = TEST_BUTTONS; + } + break; + + case MENU_RIGHT : // Right button + { + cUiListRight(VarsUi.Devices,&VarsUi.DeviceCenter); + Action = MENU_DRAW; + IOMapUi.State = TEST_BUTTONS; + } + break; + + case MENU_SELECT : // Select for connection + { + VarsUi.SelectedDevice = VarsUi.DeviceCenter; + pMapDisplay->pMenuText = VarsUi.MenuIconTextSave; + IOMapUi.State = NEXT_MENU; + } + break; + + case MENU_DELETE : // Remove device from "My contacts" + { + switch (VarsUi.State) + { + case 0 : + { + if (VarsUi.SelectedDevice) + { + if (cUiBTGetDeviceIndex(VarsUi.DevicesKnown,VarsUi.SelectedDevice - 1,&VarsUi.BTIndex)) + { + VarsUi.BTCommand = (UBYTE)REMOVEDEVICE; + VarsUi.BTPar1 = (UBYTE)VarsUi.BTIndex; + VarsUi.BTPar2 = (UBYTE)0; + if (pMapComm->pFunc(VarsUi.BTCommand,VarsUi.BTPar1,VarsUi.BTPar2,0,NULL,&(VarsUi.BTResult)) == SUCCESS) + { + VarsUi.State++; + } + else + { + VarsUi.State = 99; + } + } + else + { + Action = MENU_EXIT; + } + VarsUi.SelectedDevice = 0; + } + else + { + Action = MENU_EXIT; + } + } + break; + + case 1 : + { + if (VarsUi.BTResult != INPROGRESS) + { + if (VarsUi.BTResult == SUCCESS) + { + Action = MENU_EXIT; + } + else + { + VarsUi.State = 99; + } + } + } + break; + + default : // Display fail text + { + if (!cUiFeedback((BMPMAP*)Fail,TXT_FB_BT_REMOVE_FAIL,0,DISPLAY_SHOW_ERROR_TIME)) + { + Action = MENU_EXIT; + } + } + break; + + } + } + break; + + } + + if (Action == MENU_DRAW) + { + cUiListCalc(VarsUi.Devices,&VarsUi.DeviceCenter,&VarsUi.DeviceLeft,&VarsUi.DeviceRight); + + pMapDisplay->pMenuIcons[MENUICON_LEFT] = NULL; + pMapDisplay->pMenuIcons[MENUICON_CENTER] = NULL; + pMapDisplay->pMenuIcons[MENUICON_RIGHT] = NULL; + + if (VarsUi.DeviceLeft) + { + VarsUi.Tmp = VarsUi.DeviceLeft - 1; + cUiBTCommand(UI_BT_GET_DEVICE_TYPE,VarsUi.DevicesKnown,&VarsUi.Tmp,&VarsUi.DeviceType); + pMapDisplay->pMenuIcons[MENUICON_LEFT] = (UBYTE*)&Devices->Data[VarsUi.DeviceType * Devices->ItemPixelsX * (Devices->ItemPixelsY / 8)]; + pMapDisplay->UpdateMask |= MENUICON_BIT(MENUICON_LEFT); + } + if (VarsUi.DeviceCenter) + { + VarsUi.Tmp = VarsUi.DeviceCenter - 1; + cUiBTCommand(UI_BT_GET_DEVICE_TYPE,VarsUi.DevicesKnown,&VarsUi.Tmp,&VarsUi.DeviceType); + pMapDisplay->pMenuIcons[MENUICON_CENTER] = (UBYTE*)&Devices->Data[VarsUi.DeviceType * Devices->ItemPixelsX * (Devices->ItemPixelsY / 8)]; + pMapDisplay->UpdateMask |= MENUICON_BIT(MENUICON_CENTER); + } + if (VarsUi.DeviceRight) + { + VarsUi.Tmp = VarsUi.DeviceRight - 1; + cUiBTCommand(UI_BT_GET_DEVICE_TYPE,VarsUi.DevicesKnown,&VarsUi.Tmp,&VarsUi.DeviceType); + pMapDisplay->pMenuIcons[MENUICON_RIGHT] = (UBYTE*)&Devices->Data[VarsUi.DeviceType * Devices->ItemPixelsX * (Devices->ItemPixelsY / 8)]; + pMapDisplay->UpdateMask |= MENUICON_BIT(MENUICON_RIGHT); + } + + pMapDisplay->EraseMask |= TEXTLINE_BIT(TEXTLINE_5); + + VarsUi.Tmp = VarsUi.DeviceCenter - 1; + cUiBTCommand(UI_BT_GET_DEVICE_NAME,VarsUi.DevicesKnown,&VarsUi.Tmp,VarsUi.DisplayBuffer); + + pMapDisplay->pMenuText = VarsUi.DisplayBuffer; + pMapDisplay->EraseMask |= MENUICON_BITS; + pMapDisplay->UpdateMask |= (SPECIAL_BIT(FRAME_SELECT) | SPECIAL_BIT(MENUTEXT)); + } + if (Action == MENU_EXIT) + { + VarsUi.State = 0; + IOMapUi.State = EXIT_PRESSED; + } + + return (VarsUi.State); +} + + +//******* cUiBtConnectList *************************************************** + +UBYTE cUiBtConnectList(UBYTE Action) // Show connections and maybe disconnect +{ + switch (Action) + { + case MENU_INIT : // Init + { + VarsUi.Slots = SIZE_OF_BT_CONNECT_TABLE; + VarsUi.SlotCenter = 2; + Action = MENU_DRAW; + IOMapUi.State = TEST_BUTTONS; + } + break; + + case MENU_LEFT : // Left button + { + cUiListLeft(VarsUi.Slots,&VarsUi.SlotCenter); + Action = MENU_DRAW; + IOMapUi.State = TEST_BUTTONS; + } + break; + + case MENU_RIGHT : // Right button + { + cUiListRight(VarsUi.Slots,&VarsUi.SlotCenter); + Action = MENU_DRAW; + IOMapUi.State = TEST_BUTTONS; + } + break; + + case MENU_UPDATE : // Check connection valid + { + VarsUi.Tmp = VarsUi.SlotCenter - 1; + if (cUiBTCommand(UI_BT_GET_CONNECTION_VALID,NULL,&VarsUi.Tmp,NULL) != UI_BT_SUCCES) + { + Action = MENU_EXIT; + } + } + break; + + case MENU_DISCONNECT : // Disconnect + { + switch (VarsUi.State) + { + case 0 : + { + VarsUi.SelectedSlot = VarsUi.SlotCenter - 1; + VarsUi.BTCommand = (UBYTE)DISCONNECT; + VarsUi.BTPar1 = (UBYTE)VarsUi.SelectedSlot; + VarsUi.BTPar2 = (UBYTE)0; + if (pMapComm->pFunc(VarsUi.BTCommand,VarsUi.BTPar1,VarsUi.BTPar2,0,NULL,&(VarsUi.BTResult)) == SUCCESS) + { + VarsUi.State++; + } + else + { + VarsUi.State = 99; + } + } + break; + + case 1 : + { + if (VarsUi.BTResult != INPROGRESS) + { + if (VarsUi.BTResult == SUCCESS) + { + Action = MENU_EXIT; + } + else + { + VarsUi.State = 99; + } + } + } + break; + + default : // Display fail text + { + if (!cUiFeedback((BMPMAP*)Fail,TXT_FB_BT_DISCONNECT_FAIL,0,DISPLAY_SHOW_ERROR_TIME)) + { + Action = MENU_EXIT; + } + } + break; + + } + } + break; + + } + if (Action == MENU_DRAW) + { + cUiListCalc(VarsUi.Slots,&VarsUi.SlotCenter,&VarsUi.SlotLeft,&VarsUi.SlotRight); + + pMapDisplay->pBitmaps[BITMAP_2] = (BMPMAP*)VarsUi.PortBitmapLeft; + pMapDisplay->pBitmaps[BITMAP_3] = (BMPMAP*)VarsUi.PortBitmapCenter; + pMapDisplay->pBitmaps[BITMAP_4] = (BMPMAP*)VarsUi.PortBitmapRight; + + VarsUi.Tmp = VarsUi.SlotLeft - 1; + if (cUiBTCommand(UI_BT_GET_CONNECTION_VALID,NULL,&VarsUi.Tmp,NULL) == UI_BT_SUCCES) + { + cUiBTCommand(UI_BT_GET_CONNECTION_TYPE,NULL,&VarsUi.Tmp,&VarsUi.DeviceType); + pMapDisplay->pMenuIcons[MENUICON_LEFT] = (UBYTE*)&Devices->Data[VarsUi.DeviceType * Devices->ItemPixelsX * (Devices->ItemPixelsY / 8)]; + cUiDrawPortNo(VarsUi.PortBitmapLeft,MENUICON_LEFT,VarsUi.Tmp); + pMapDisplay->UpdateMask |= BITMAP_BIT(BITMAP_2); + } + else + { + pMapDisplay->pMenuIcons[MENUICON_LEFT] = (UBYTE*)&Connections->Data[VarsUi.Tmp * Connections->ItemPixelsX * (Connections->ItemPixelsY / 8)]; + } + + VarsUi.Tmp = VarsUi.SlotCenter - 1; + cUiBTCommand(UI_BT_GET_CONNECTION_NAME,NULL,&VarsUi.Tmp,VarsUi.DisplayBuffer); + pMapDisplay->EraseMask |= TEXTLINE_BIT(TEXTLINE_5); + pMapDisplay->pMenuText = VarsUi.DisplayBuffer; + + if (cUiBTCommand(UI_BT_GET_CONNECTION_VALID,NULL,&VarsUi.Tmp,NULL) == UI_BT_SUCCES) + { + cUiBTCommand(UI_BT_GET_CONNECTION_TYPE,NULL,&VarsUi.Tmp,&VarsUi.DeviceType); + pMapDisplay->pMenuIcons[MENUICON_CENTER] = (UBYTE*)&Devices->Data[VarsUi.DeviceType * Devices->ItemPixelsX * (Devices->ItemPixelsY / 8)]; + cUiDrawPortNo(VarsUi.PortBitmapCenter,MENUICON_CENTER,VarsUi.Tmp); + pMapDisplay->UpdateMask |= BITMAP_BIT(BITMAP_3); + } + else + { + pMapDisplay->pMenuIcons[MENUICON_CENTER] = (UBYTE*)&Connections->Data[VarsUi.Tmp * Connections->ItemPixelsX * (Connections->ItemPixelsY / 8)]; + } + VarsUi.Tmp = VarsUi.SlotRight - 1; + if (cUiBTCommand(UI_BT_GET_CONNECTION_VALID,NULL,&VarsUi.Tmp,NULL) == UI_BT_SUCCES) + { + cUiBTCommand(UI_BT_GET_CONNECTION_TYPE,NULL,&VarsUi.Tmp,&VarsUi.DeviceType); + pMapDisplay->pMenuIcons[MENUICON_RIGHT] = (UBYTE*)&Devices->Data[VarsUi.DeviceType * Devices->ItemPixelsX * (Devices->ItemPixelsY / 8)]; + cUiDrawPortNo(VarsUi.PortBitmapRight,MENUICON_RIGHT,VarsUi.Tmp); + pMapDisplay->UpdateMask |= BITMAP_BIT(BITMAP_4); + } + else + { + pMapDisplay->pMenuIcons[MENUICON_RIGHT] = (UBYTE*)&Connections->Data[VarsUi.Tmp * Connections->ItemPixelsX * (Connections->ItemPixelsY / 8)]; + } + pMapDisplay->EraseMask &= ~SCREEN_BIT(SCREEN_LARGE); + pMapDisplay->EraseMask |= MENUICON_BITS; + pMapDisplay->UpdateMask |= (MENUICON_BITS | SPECIAL_BIT(FRAME_SELECT) | SPECIAL_BIT(MENUTEXT)); + } + if (Action == MENU_EXIT) + { + VarsUi.State = 0; + IOMapUi.State = EXIT_PRESSED; + } + + + return (VarsUi.State); +} + + +UBYTE cUiBtConnect(UBYTE Action) // Select connection no and insert device +{ + switch (Action) + { + case MENU_INIT : // Init + { + VarsUi.Slots = SIZE_OF_BT_CONNECT_TABLE - 1; + VarsUi.SlotCenter = 1; + Action = MENU_DRAW; + IOMapUi.State = TEST_BUTTONS; + } + break; + + case MENU_LEFT : // Left button + { + cUiListLeft(VarsUi.Slots,&VarsUi.SlotCenter); + Action = MENU_DRAW; + IOMapUi.State = TEST_BUTTONS; + } + break; + + case MENU_RIGHT : // Right button + { + cUiListRight(VarsUi.Slots,&VarsUi.SlotCenter); + Action = MENU_DRAW; + IOMapUi.State = TEST_BUTTONS; + } + break; + + case MENU_CONNECT : // Insert device + { + switch (VarsUi.State) + { + case 0 : // Check selected device + { + VarsUi.SelectedSlot = (UBYTE)VarsUi.SlotCenter; + if (VarsUi.SelectedDevice) + { + VarsUi.State++; + } + else + { + Action = MENU_EXIT; + } + } + break; + + case 1 : // Display wait text + { + if (!cUiFeedback((BMPMAP*)Wait,TXT_FB_BT_CONNECTING_WAIT,0,0)) + { + if (cUiBTGetDeviceIndex(VarsUi.DevicesKnown,VarsUi.SelectedDevice - 1,&VarsUi.BTIndex)) + { + VarsUi.BTCommand = (UBYTE)CONNECT; + VarsUi.BTPar1 = (UBYTE)VarsUi.BTIndex; + VarsUi.BTPar2 = (UBYTE)VarsUi.SelectedSlot; + if (pMapComm->pFunc(VarsUi.BTCommand,VarsUi.BTPar1,VarsUi.BTPar2,0,NULL,&(VarsUi.BTResult)) == SUCCESS) + { + VarsUi.State++; + } + else + { + VarsUi.State = 99; + } + } + else + { + VarsUi.State = 99; + } + } + } + break; + + case 2 : // Wait for result + { + if (VarsUi.BTResult != INPROGRESS) + { + if (VarsUi.BTResult == SUCCESS) + { + Action = MENU_EXIT; + } + else + { + if (VarsUi.BTResult == REQPIN) + { + sprintf((char*)pMapSound->SoundFilename,"%s.%s",(char*)UI_ATTENTION_SOUND,(char*)TXT_SOUND_EXT); + pMapSound->Volume = IOMapUi.Volume; + pMapSound->Mode = SOUND_ONCE; + pMapSound->Flags |= SOUND_UPDATE; + strcpy((char*)VarsUi.UserString,(char*)DEFAULT_PIN_CODE); + VarsUi.State++; + } + else + { + VarsUi.State = 6; + } + } + } + } + break; + + case 3 : // Get pincode and send + { + if (!cUiGetUserString(0)) + { + if (VarsUi.UserString[0] == 0) + { + sprintf((char*)VarsUi.UserString,"%08lX",VarsUi.CRPasskey); + Action = MENU_EXIT; + } + else + { + VarsUi.State++; + } + pMapComm->pFunc2(VarsUi.UserString); + } + } + break; + + case 4 : // Display wait text + { + if (!cUiFeedback((BMPMAP*)Wait,TXT_FB_BT_CONNECTING_WAIT,0,0)) + { + VarsUi.State++; + } + } + break; + + case 5 : // Wait for result + { + if (VarsUi.BTResult != INPROGRESS) + { + if (VarsUi.BTResult == SUCCESS) + { + Action = MENU_EXIT; + } + else + { + VarsUi.State = 6; + } + } + } + break; + + case 6 : // Display busy text + { + if (!cUiFeedback((BMPMAP*)Fail,TXT_FB_BT_CONNECT_BUSY_FAIL,0,DISPLAY_SHOW_ERROR_TIME)) + { + Action = MENU_EXIT; + } + } + break; + + default : // Display fail text + { + if (!cUiFeedback((BMPMAP*)Fail,TXT_FB_BT_CONNECTING_FAIL,0,DISPLAY_SHOW_ERROR_TIME)) + { + Action = MENU_EXIT; + } + } + break; + + } + } + break; + + case MENU_SEND : + { + switch (VarsUi.State) + { + case 0 : // Check connection + { + VarsUi.SelectedSlot = (UBYTE)VarsUi.SlotCenter; + if (VarsUi.SelectedFilename[0] && (cUiBTCommand(UI_BT_GET_CONNECTION_NAME,NULL,&VarsUi.SelectedSlot,NULL) == UI_BT_SUCCES)) + { + VarsUi.State += 2; + } + else + { + VarsUi.State++; + } + } + break; + + case 1 : // Display fail text + { + if (!cUiFeedback((BMPMAP*)Fail,TXT_FB_BT_SENDING_NO_CONN_FAIL,0,DISPLAY_SHOW_ERROR_TIME)) + { + Action = MENU_EXIT; + } + } + break; + + case 2 : // Display wait text and send file + { + if (!cUiFeedback((BMPMAP*)Wait,TXT_FB_BT_SENDING_WAIT,0,0)) + { + VarsUi.BTCommand = (UBYTE)SENDFILE; + VarsUi.BTPar1 = (UBYTE)VarsUi.SelectedSlot; + VarsUi.BTPar2 = (UBYTE)0; + if (pMapComm->pFunc(VarsUi.BTCommand,VarsUi.BTPar1,VarsUi.BTPar2,0,VarsUi.SelectedFilename,&(VarsUi.BTResult)) == SUCCESS) + { + VarsUi.Timer = 0; + VarsUi.State++; + } + else + { + VarsUi.State = 4; + } + } + } + break; + + case 3 : // Wait for result + { + if (VarsUi.BTResult != INPROGRESS) + { + if (VarsUi.BTResult == SUCCESS) + { + VarsUi.State += 2; + } + else + { + VarsUi.State++; + } + } + VarsUi.Timer++; + } + break; + + case 4 : // Display fail text + { + if (!cUiFeedback((BMPMAP*)Fail,TXT_FB_BT_SENDING_FAIL,0,DISPLAY_SHOW_ERROR_TIME)) + { + Action = MENU_EXIT; + } + } + break; + + case 5 : // Wait min. "DISPLAY_SHOW_TIME" to show "TXT_FB_BT_SENDING_WAIT" + { + if (++VarsUi.Timer >= DISPLAY_SHOW_TIME) + { + Action = MENU_EXIT; + } + } + break; + + } + } + break; + + } + if (Action == MENU_DRAW) // Update display + { + cUiListCalc(VarsUi.Slots,&VarsUi.SlotCenter,&VarsUi.SlotLeft,&VarsUi.SlotRight); + + pMapDisplay->pBitmaps[BITMAP_2] = (BMPMAP*)VarsUi.PortBitmapLeft; + pMapDisplay->pBitmaps[BITMAP_3] = (BMPMAP*)VarsUi.PortBitmapCenter; + pMapDisplay->pBitmaps[BITMAP_4] = (BMPMAP*)VarsUi.PortBitmapRight; + + VarsUi.Tmp = VarsUi.SlotLeft; + if (cUiBTCommand(UI_BT_GET_CONNECTION_VALID,NULL,&VarsUi.Tmp,NULL) == UI_BT_SUCCES) + { + cUiBTCommand(UI_BT_GET_CONNECTION_TYPE,NULL,&VarsUi.Tmp,&VarsUi.DeviceType); + pMapDisplay->pMenuIcons[MENUICON_LEFT] = (UBYTE*)&Devices->Data[VarsUi.DeviceType * Devices->ItemPixelsX * (Devices->ItemPixelsY / 8)]; + cUiDrawPortNo(VarsUi.PortBitmapLeft,MENUICON_LEFT,VarsUi.Tmp); + pMapDisplay->UpdateMask |= BITMAP_BIT(BITMAP_2); + } + else + { + pMapDisplay->pMenuIcons[MENUICON_LEFT] = (UBYTE*)&Connections->Data[VarsUi.Tmp * Connections->ItemPixelsX * (Connections->ItemPixelsY / 8)]; + } + + VarsUi.Tmp = VarsUi.SlotCenter; + cUiBTCommand(UI_BT_GET_CONNECTION_NAME,NULL,&VarsUi.Tmp,VarsUi.DisplayBuffer); + pMapDisplay->EraseMask |= TEXTLINE_BIT(TEXTLINE_5); + pMapDisplay->pMenuText = VarsUi.DisplayBuffer; + + if (cUiBTCommand(UI_BT_GET_CONNECTION_VALID,NULL,&VarsUi.Tmp,NULL) == UI_BT_SUCCES) + { + cUiBTCommand(UI_BT_GET_CONNECTION_TYPE,NULL,&VarsUi.Tmp,&VarsUi.DeviceType); + pMapDisplay->pMenuIcons[MENUICON_CENTER] = (UBYTE*)&Devices->Data[VarsUi.DeviceType * Devices->ItemPixelsX * (Devices->ItemPixelsY / 8)]; + cUiDrawPortNo(VarsUi.PortBitmapCenter,MENUICON_CENTER,VarsUi.Tmp); + pMapDisplay->UpdateMask |= BITMAP_BIT(BITMAP_3); + } + else + { + pMapDisplay->pMenuIcons[MENUICON_CENTER] = (UBYTE*)&Connections->Data[VarsUi.Tmp * Connections->ItemPixelsX * (Connections->ItemPixelsY / 8)]; + } + VarsUi.Tmp = VarsUi.SlotRight; + if (cUiBTCommand(UI_BT_GET_CONNECTION_VALID,NULL,&VarsUi.Tmp,NULL) == UI_BT_SUCCES) + { + cUiBTCommand(UI_BT_GET_CONNECTION_TYPE,NULL,&VarsUi.Tmp,&VarsUi.DeviceType); + pMapDisplay->pMenuIcons[MENUICON_RIGHT] = (UBYTE*)&Devices->Data[VarsUi.DeviceType * Devices->ItemPixelsX * (Devices->ItemPixelsY / 8)]; + cUiDrawPortNo(VarsUi.PortBitmapRight,MENUICON_RIGHT,VarsUi.Tmp); + pMapDisplay->UpdateMask |= BITMAP_BIT(BITMAP_4); + } + else + { + pMapDisplay->pMenuIcons[MENUICON_RIGHT] = (UBYTE*)&Connections->Data[VarsUi.Tmp * Connections->ItemPixelsX * (Connections->ItemPixelsY / 8)]; + } + pMapDisplay->EraseMask &= ~SCREEN_BIT(SCREEN_LARGE); + pMapDisplay->EraseMask |= MENUICON_BITS; + pMapDisplay->UpdateMask |= (MENUICON_BITS | SPECIAL_BIT(FRAME_SELECT) | SPECIAL_BIT(MENUTEXT)); + } + if (Action == MENU_EXIT) + { + IOMapUi.State = EXIT_PRESSED; + VarsUi.State = 0; + } + + return (VarsUi.State); +} + + + +//******* cUiPowerOffTime **************************************************** + +UBYTE cUiPowerOffTime(UBYTE Action) // MENU_INIT,MENU_LEFT,MENU_RIGHT,MENU_EXIT +{ + switch (Action) + { + case MENU_INIT : // Init time counter and cursor bitmap + { + VarsUi.Counter = cUiNVReadPowerOnTimeCount() + 1; + + VarsUi.pTmp = (UBYTE*)Cursor; + for (VarsUi.Tmp = 0;(VarsUi.Tmp < SIZE_OF_CURSOR) && (VarsUi.Tmp < (UBYTE)sizeof(Cursor));VarsUi.Tmp++) + { + VarsUi.CursorTmp[VarsUi.Tmp] = *VarsUi.pTmp; + VarsUi.pTmp++; + } + Action = MENU_DRAW; + } + break; + + case MENU_LEFT : // Dec + { + cUiListLeft(POWER_OFF_TIME_STEPS,&VarsUi.Counter); + Action = MENU_DRAW; + } + break; + + case MENU_RIGHT : // Inc + { + cUiListRight(POWER_OFF_TIME_STEPS,&VarsUi.Counter); + Action = MENU_DRAW; + } + break; + + case MENU_ENTER : // Enter + { + cUiNVWritePowerOnTimeCount(VarsUi.Counter - 1); + IOMapUi.SleepTimeout = PowerOffTimeSteps[cUiNVReadPowerOnTimeCount()]; + Action = MENU_EXIT; + } + break; + + } + + if (Action == MENU_DRAW) + { + if (VarsUi.Counter > 1) + { + sprintf((char*)VarsUi.DisplayBuffer,"%u",(UWORD)PowerOffTimeSteps[VarsUi.Counter - 1]); + } + else + { + sprintf((char*)VarsUi.DisplayBuffer,(char*)cUiGetString(TXT_POWEROFFTIME_NEVER)); + } + pMapDisplay->pTextLines[TEXTLINE_3] = VarsUi.DisplayBuffer; + + pMapDisplay->pBitmaps[BITMAP_1] = (BMPMAP*)VarsUi.CursorTmp; + VarsUi.CursorTmp[4] = 46; + VarsUi.CursorTmp[5] = 24; + pMapDisplay->EraseMask |= (TEXTLINE_BIT(TEXTLINE_3) | TEXTLINE_BIT(TEXTLINE_4)); + pMapDisplay->TextLinesCenterFlags |= TEXTLINE_BIT(TEXTLINE_3); + pMapDisplay->UpdateMask |= (TEXTLINE_BIT(TEXTLINE_3) | BITMAP_BIT(BITMAP_1)); + } + if (Action == MENU_EXIT) + { + IOMapUi.State = EXIT_PRESSED; + } + + return (0); +} + + + +//******* cUiBTConnectRequest ************************************************ + +UBYTE cUiBTConnectRequest(UBYTE Action) +{ + switch (Action) + { + case MENU_INIT : + { + switch (VarsUi.CRState) + { + case 0 : + { + sprintf((char*)pMapSound->SoundFilename,"%s.%s",(char*)UI_ATTENTION_SOUND,(char*)TXT_SOUND_EXT); + pMapSound->Volume = IOMapUi.Volume; + pMapSound->Mode = SOUND_ONCE; + pMapSound->Flags |= SOUND_UPDATE; + VarsUi.CRState++; + } + break; + + case 1 : + { + if (DISPLAY_IDLE) + { + pMapDisplay->Flags |= DISPLAY_POPUP; + VarsUi.CRState++; + } + } + break; + + case 2 : + { + strcpy((char*)VarsUi.UserString,(char*)DEFAULT_PIN_CODE); + IOMapUi.Flags |= UI_REDRAW_STATUS; + VarsUi.CRState++; + } + break; + + case 3 : // Get pincode and send + { + if (!cUiGetUserString(0)) + { + if (VarsUi.UserString[0] == 0) + { + sprintf((char*)VarsUi.UserString,"%08lX",VarsUi.CRPasskey); + } + pMapComm->pFunc2(VarsUi.UserString); + VarsUi.CRState++; + } + } + break; + + case 4 : + { + if (DISPLAY_IDLE) + { + pMapDisplay->Flags &= ~DISPLAY_POPUP; + VarsUi.CRState = 0; + } + } + break; + + } + } + break; + + } + + return (VarsUi.CRState); +} + + + +//******* cUiFilesDelete ***************************************************** + +UBYTE cUiFilesDelete(UBYTE Action) +{ + switch (Action) + { + case MENU_INIT : + { + pMapDisplay->pTextLines[TEXTLINE_3] = cUiGetString(TXT_FILESDELETE_DELETING_ALL); + pMapDisplay->TextLinesCenterFlags |= TEXTLINE_BIT(TEXTLINE_3); + pMapDisplay->UpdateMask |= TEXTLINE_BIT(TEXTLINE_3); + sprintf((char*)VarsUi.DisplayBuffer,(char*)cUiGetString(TXT_FILESDELETE_S_FILES),(char*)cUiGetString(TXT_FILETYPE[VarsUi.SelectedType])); + pMapDisplay->pTextLines[TEXTLINE_4] = VarsUi.DisplayBuffer; + pMapDisplay->TextLinesCenterFlags |= TEXTLINE_BIT(TEXTLINE_4); + pMapDisplay->UpdateMask |= TEXTLINE_BIT(TEXTLINE_4); + IOMapUi.State = TEST_BUTTONS; + } + break; + + case MENU_DELETE : + { + switch (VarsUi.State) + { + case 0 : + { + if (VarsUi.SelectedType < FILETYPES) + { + sprintf((char*)VarsUi.FilenameBuffer,"*.%s",TXT_FILE_EXT[VarsUi.SelectedType]); + } + else + { + sprintf((char*)VarsUi.FilenameBuffer,"*.*"); + } + VarsUi.State++; + } + break; + + case 1 : + { + if (SOUND_IDLE == pMapSound->State) + { + VarsUi.State++; + } + } + break; + + case 2 : // Delete files + { + VarsUi.TmpHandle = pMapLoader->pFunc(FINDFIRST,VarsUi.FilenameBuffer,VarsUi.SelectedFilename,&VarsUi.TmpLength); + if (!(VarsUi.TmpHandle & 0x8000)) + { + pMapLoader->pFunc(CLOSE,(UBYTE*)&VarsUi.TmpHandle,NULL,NULL); + pMapLoader->pFunc(DELETE,VarsUi.SelectedFilename,NULL,NULL); + } + else + { + pMapDisplay->EraseMask |= MENUICON_BITS; + pMapDisplay->EraseMask |= SPECIAL_BIT(MENUTEXT); + VarsUi.State++; + } + } + break; + + default : // Display Files deleted text + { + if (!cUiFeedback((BMPMAP*)Info,TXT_FB_FD_FILES_INFO,TXT_FB_FD_DELETED_INFO,DISPLAY_SHOW_TIME)) + { + IOMapUi.State = EXIT_PRESSED; + VarsUi.State = 0; + } + } + break; + + } + } + break; + + default : + { + if (Action < FILETYPES) + { + VarsUi.SelectedType = Action; + } + else + { + VarsUi.SelectedType = FILETYPE_ALL; + } + } + break; + + } + + return (VarsUi.State); +} + + +//******* cUiOff ************************************************************* + +UBYTE cUiOff(UBYTE Action) // Tell AVR to turn off ARM +{ + if (Action == MENU_INIT) + { + switch (VarsUi.State) + { + case 0 : // Stop VM if running + { + if (pMapCmd->ProgStatus == PROG_RUNNING) + { + pMapCmd->DeactivateFlag = TRUE; + } + VarsUi.State++; + } + break; + + case 1 : // When VM is stopped -> Display off and close all connections + { + if (pMapCmd->ProgStatus != PROG_RUNNING) + { + pMapDisplay->Flags &= ~DISPLAY_ON; + VarsUi.BTCommand = (UBYTE)DISCONNECTALL; + VarsUi.BTPar1 = (UBYTE)0; + VarsUi.BTPar2 = (UBYTE)0; + pMapComm->pFunc(VarsUi.BTCommand,VarsUi.BTPar1,VarsUi.BTPar2,0,NULL,&(VarsUi.BTResult)); + VarsUi.State++; + } + } + break; + + case 2 : // Send off command to AVR + { + if (VarsUi.BTResult != INPROGRESS) + { + pMapIoCtrl->PowerOn = POWERDOWN; + VarsUi.Timer = 0; + VarsUi.State++; + } + } + break; + + case 3 : // Wait for power off + { + if (++VarsUi.Timer >= ARM_WAIT_FOR_POWER_OFF) + { + VarsUi.State++; + } + } + break; + + case 4 : // Vitual off state (if still power) wait for on button + { + pMapIoCtrl->PowerOn = 0; + if (BUTTON_ENTER == cUiReadButtons()) + { + VarsUi.State++; + } + } + break; + + default : // Turn on again + { + IOMapUi.State = INIT_DISPLAY; + VarsUi.State = 0; + } + break; + + } + } + + return (VarsUi.State); +} + + + +//******* FUNCTIONS ********************************************************** + +enum FUNC_NO // Must reffer to entry in Functions +{ // used in Menus to repressent function + FUNC_NO_NOT_USED = 0x00, + FUNC_NO_TEST_PROGRAM = 0x01, + FUNC_NO_OFF = 0x02, + FUNC_NO_BT_ON = 0x03, + FUNC_NO_POWER_OFF_TIME = 0x04, + FUNC_NO_FILES_DELETE = 0x05, + FUNC_NO_FILE_LIST = 0x06, + FUNC_NO_VOLUME = 0x07, + FUNC_NO_FILE_RUN = 0x08, + FUNC_NO_FILE_DELETE = 0x09, + FUNC_NO_FREE1 = 0x0A, + FUNC_NO_ON_BRICK_PROGRAMMING = 0x0B, + FUNC_NO_FREE2 = 0x0C, + FUNC_NO_BT_CONNECT_REQUEST = 0x0D, + FUNC_NO_VIEW = 0x0E, + FUNC_NO_GET_USER_STRING = 0x0F, + FUNC_NO_BT_CONNECT = 0x10, + FUNC_NO_BT_VISIABILITY = 0x11, + FUNC_NO_BT_SEARCH = 0x12, + FUNC_NO_BT_DEVICE_LIST = 0x13, + FUNC_NO_BT_CONNECT_LIST = 0x14, + FUNC_NO_MAX +}; + +FUNCTION Functions[] = // Use same index as FUNC_NO +{ + 0, + TestPrg, + cUiOff, + cUiBtOn, + cUiPowerOffTime, + cUiFilesDelete, + cUiFileList, + cUiVolume, + cUiFileRun, + cUiFileDelete, + 0, + cUiOnBrickProgramming, + 0, + cUiBTConnectRequest, + cUiView, + cUiGetUserString, + cUiBtConnect, + cUiBtVisiability, + cUiBtSearch, + cUiBtDeviceList, + cUiBtConnectList +}; + + diff --git a/AT91SAM7S256/Source/Icons.txt b/AT91SAM7S256/Source/Icons.txt new file mode 100644 index 0000000..34218e2 --- /dev/null +++ b/AT91SAM7S256/Source/Icons.txt @@ -0,0 +1,297 @@ +const ICON Icons[] = +{ + 0x04,0x00, // Graphics Format + 0x1B,0x00, // Graphics DataSize + 0x01, // Graphics Count X + 0x60, // Graphics Count Y + 0x18, // Graphics Width + 0x18, // Graphics Height + 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a/AT91SAM7S256/Source/Info.txt b/AT91SAM7S256/Source/Info.txt new file mode 100644 index 0000000..d56d7e2 --- /dev/null +++ b/AT91SAM7S256/Source/Info.txt @@ -0,0 +1,12 @@ +const BMPMAP Info[] = +{ + 0x02,0x00, // Graphics Format + 0x00,0x48, // Graphics DataSize + 0x00, // Graphics Start X + 0x08, // Graphics Start Y + 0x18, // Graphics Width + 0x18, // Graphics Height + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x40,0x80,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x40,0xA0,0x90,0x20,0x20,0x40,0x40,0x30,0x8C,0x73,0x0C,0x03,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x02,0x02,0x02,0x02,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 +}; diff --git a/AT91SAM7S256/Source/LowBattery.txt b/AT91SAM7S256/Source/LowBattery.txt new file mode 100644 index 0000000..e5a0769 --- /dev/null +++ b/AT91SAM7S256/Source/LowBattery.txt @@ -0,0 +1,16 @@ +const BMPMAP LowBattery[] = +{ + 0x02,0x00, // Graphics Format + 0x02,0xA0, // Graphics DataSize + 0x02, // Graphics Start X + 0x08, // Graphics Start Y + 0x60, // Graphics Width + 0x38, // Graphics Height + 0x02,0xF2,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x92,0x92,0x92,0x92,0x92,0x92,0x92,0x92,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0xF2,0x82,0x02, + 0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xC0,0x20,0x18,0x04,0x02,0x02,0x01,0x01,0x01,0x00,0xF0,0xF8,0xFC,0xFC,0xF8,0xF0,0x00,0x01,0x01,0x01,0x02,0x02,0x04,0x18,0x20,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0x00, + 0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFE,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0x7F,0xFF,0xFF,0x7F,0x3F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0x00, + 0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x0E,0x10,0x60,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x60,0xF0,0xF0,0xF0,0xF0,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x60,0x10,0x0E,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0x00, + 0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xF0,0x00,0x00,0x00,0x00,0x00,0xE0,0x10,0x10,0x10,0xE0,0x00,0xF0,0x00,0xC0,0x00,0xF0,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0xF2,0x92,0x92,0x94,0x64,0x04,0xE4,0x14,0x14,0x14,0xE4,0x02,0x12,0x12,0xF1,0x11,0x10,0x00,0x10,0x10,0xF0,0x10,0x10,0x00,0xF0,0x90,0x90,0x90,0x10,0x00,0xF0,0x90,0x90,0x90,0x60,0x00,0x70,0x80,0x00,0x80,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0x00, + 0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x04,0x04,0x04,0x04,0x00,0x03,0x04,0x04,0x04,0x03,0x00,0x03,0x04,0x03,0x04,0x03,0x00,0x00,0x00,0x00,0xC0,0x40,0xF0,0x17,0x14,0x14,0x14,0x13,0x10,0x17,0x11,0x11,0x11,0x17,0x10,0x10,0xD0,0xD7,0x10,0xF0,0x00,0x00,0x00,0x07,0x00,0x00,0x00,0x07,0x04,0x04,0x04,0x04,0x00,0x07,0x00,0x00,0x01,0x06,0x00,0x00,0x00,0x07,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0x00, + 0x00,0x3F,0x20,0x20,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x63,0x62,0x6F,0x68,0x68,0x68,0x68,0x68,0x68,0x68,0x68,0x68,0x68,0x68,0x68,0x68,0x6B,0x6B,0x68,0x6F,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x7F,0x7F,0x00 +}; diff --git a/AT91SAM7S256/Source/Mainmenu.rms b/AT91SAM7S256/Source/Mainmenu.rms new file mode 100644 index 0000000..f26e744 --- /dev/null +++ b/AT91SAM7S256/Source/Mainmenu.rms @@ -0,0 +1,65 @@ +const UBYTE MAINMENU[] = +{ + 0x07,0x00, // Menu Format + 0x00,0xE8, // Menu DataSize + 0x1D, // Menu item size + 0x08, // Menu items + 0x18, // Menu icon Width + 0x18, // Menu icon Height + + // Turn_off? + 0x00,0x00,0x00,0x01, // 0x00000001 + 0x10,0x20,0x04,0x01, // 0x10200401 + 0x02,0x00,0x00,0x01, // 2 ,0 ,0 ,1 + 0x54,0x75,0x72,0x6E,0x20,0x6F,0x66,0x66,0x3F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x31, // 31 + + // Turn_off? + 0x00,0x00,0x00,0x02, // 0x00000002 + 0x10,0x20,0x00,0x01, // 0x10200001 + 0x00,0x00,0x00,0x01, // 0 ,0 ,0 ,1 + 0x54,0x75,0x72,0x6E,0x20,0x6F,0x66,0x66,0x3F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x30, // 30 + + // My_Files + 0x00,0x00,0x00,0x11, // 0x00000011 + 0x01,0x04,0x00,0x00, // 0x01040000 + 0x00,0x00,0x01,0x01, // 0 ,0 ,1 ,1 + 0x4D,0x79,0x20,0x46,0x69,0x6C,0x65,0x73,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x3B, // 3B + + // NXT_Program + 0x00,0x00,0x00,0x21, // 0x00000021 + 0x01,0x04,0x00,0x00, // 0x01040000 + 0x00,0x00,0x02,0x01, // 0 ,0 ,2 ,1 + 0x4E,0x58,0x54,0x20,0x50,0x72,0x6F,0x67,0x72,0x61,0x6D,0x00,0x00,0x00,0x00,0x00, + 0x3C, // 3C + + // View + 0x00,0x00,0x00,0x31, // 0x00000031 + 0x01,0x04,0x00,0x00, // 0x01040000 + 0x00,0x00,0x04,0x01, // 0 ,0 ,4 ,1 + 0x56,0x69,0x65,0x77,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x3E, // 3E + + // Bluetooth + 0x00,0x00,0x00,0x41, // 0x00000041 + 0x01,0x04,0x00,0x00, // 0x01040000 + 0x00,0x00,0x07,0x02, // 0 ,0 ,7 ,2 + 0x42,0x6C,0x75,0x65,0x74,0x6F,0x6F,0x74,0x68,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x51, // 51 + + // Settings + 0x00,0x00,0x00,0x51, // 0x00000051 + 0x01,0x04,0x00,0x00, // 0x01040000 + 0x00,0x00,0x05,0x01, // 0 ,0 ,5 ,1 + 0x53,0x65,0x74,0x74,0x69,0x6E,0x67,0x73,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x3F, // 3F + + // Try_Me + 0x00,0x00,0x00,0x61, // 0x00000061 + 0x01,0x04,0x00,0x00, // 0x01040000 + 0x00,0x00,0x06,0x01, // 0 ,0 ,6 ,1 + 0x54,0x72,0x79,0x20,0x4D,0x65,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x40, // 40 +}; diff --git a/AT91SAM7S256/Source/Ok.txt b/AT91SAM7S256/Source/Ok.txt new file mode 100644 index 0000000..3a4b186 --- /dev/null +++ b/AT91SAM7S256/Source/Ok.txt @@ -0,0 +1,11 @@ +const BMPMAP Ok[] = +{ + 0x02,0x00, // Graphics Format + 0x00,0x20, // Graphics DataSize + 0x2A, // Graphics Start X + 0x30, // Graphics Start Y + 0x10, // Graphics Width + 0x10, // Graphics Height + 0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xC0,0x38,0xC4,0x34,0x08,0x00,0xFF, + 0xFF,0x04,0x0A,0x19,0x12,0x22,0x24,0x24,0x23,0x18,0x07,0x00,0x00,0x00,0x00,0xFF +}; diff --git a/AT91SAM7S256/Source/Port.txt b/AT91SAM7S256/Source/Port.txt new file mode 100644 index 0000000..9367003 --- /dev/null +++ b/AT91SAM7S256/Source/Port.txt @@ -0,0 +1,10 @@ +const ICON Port[] = +{ + 0x04,0x00, // Graphics Format + 0x00,0x18, // Graphics DataSize + 0x08, // Graphics Count X + 0x01, // Graphics Count Y + 0x03, // Graphics Width + 0x08, // Graphics Height + 0x70,0x88,0x70,0x90,0xF8,0x80,0xC8,0xA8,0x90,0x88,0xA8,0x50,0x38,0x20,0xF8,0xF0,0x28,0xF0,0xF8,0xA8,0x50,0x70,0x88,0x50 +}; diff --git a/AT91SAM7S256/Source/RCXintro_1.txt b/AT91SAM7S256/Source/RCXintro_1.txt new file mode 100644 index 0000000..5ae955c --- /dev/null +++ b/AT91SAM7S256/Source/RCXintro_1.txt @@ -0,0 +1,17 @@ +const BMPMAP RCXintro_1[] = +{ + 0x02,0x00, // Graphics Format + 0x02,0x00, // Graphics DataSize + 0x10, // Graphics Start X + 0x00, // Graphics Start Y + 0x40, // Graphics Width + 0x40, // Graphics Height + 0xFF,0x01,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0x01,0xFF, + 0xFF,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0xFF, + 0xFF,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x7F,0x1F,0x8F,0xC7,0xE7,0x67,0x33,0x33,0x33,0x67,0xE7,0x8F,0xCF,0xE7,0x67,0x63,0x33,0x33,0x33,0x33,0x33,0x27,0x67,0xCF,0xCF,0xE7,0x67,0x63,0x33,0x33,0x33,0x33,0x33,0x63,0x67,0xC7,0x8F,0x8F,0xCF,0x67,0x67,0x23,0x33,0x33,0x33,0x33,0x63,0x67,0xC7,0x8F,0x1F,0x33,0xF3,0xFF,0x00,0xFF, + 0xFF,0x00,0xFF,0xFF,0x7F,0x0F,0x83,0xE0,0x78,0x1E,0x07,0x01,0x00,0x00,0x80,0xE0,0xF8,0x7E,0x1F,0x07,0x01,0x00,0x00,0x00,0x18,0x18,0x18,0xF8,0xF8,0x1C,0x06,0x03,0x00,0x00,0xC0,0x70,0x3C,0x3C,0x30,0x20,0x20,0xE0,0xF0,0x3D,0x0F,0x03,0x00,0x00,0xC0,0xF0,0xFC,0x3C,0x00,0x00,0x00,0x00,0xC0,0xFF,0x1E,0x00,0xC0,0xFF,0x00,0xFF, + 0xFF,0x00,0xFF,0x01,0x00,0xFC,0xFF,0x03,0x00,0x00,0x00,0x00,0x00,0x0E,0x0F,0xFF,0xC7,0x00,0x00,0x00,0x00,0x00,0x0E,0x0E,0x0E,0x0E,0xFE,0xC7,0x80,0x00,0x00,0x00,0x00,0x1F,0x1F,0x0E,0x00,0x00,0x80,0xC0,0xF0,0xFF,0x83,0x00,0x00,0x00,0x1C,0x1F,0x0F,0x03,0x00,0x80,0xC0,0xE0,0x78,0x1E,0x87,0xC1,0xF0,0xFE,0xFF,0xFF,0x00,0xFF, + 0xFF,0x00,0xFF,0xFE,0xFC,0xF8,0xF3,0xF3,0xE6,0xE6,0xE6,0xE6,0xE6,0xF2,0xF3,0xF9,0xF9,0xF3,0xF6,0xE6,0xE6,0xE6,0xE6,0xE6,0xF3,0xF3,0xF9,0xF9,0xF3,0xF3,0xE6,0xE6,0xE6,0xE6,0xE6,0xE6,0xF3,0xF3,0xF9,0xFC,0xFC,0xF9,0xF3,0xF3,0xE6,0xE6,0xE6,0xE6,0xE6,0xE6,0xF3,0xF3,0xF9,0xF8,0xFC,0xFE,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0xFF, + 0xFF,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0xFF, + 0xFF,0x80,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0x80,0xFF +}; diff --git a/AT91SAM7S256/Source/RCXintro_10.txt b/AT91SAM7S256/Source/RCXintro_10.txt new file mode 100644 index 0000000..e5349cc --- /dev/null +++ b/AT91SAM7S256/Source/RCXintro_10.txt @@ -0,0 +1,11 @@ +const BMPMAP RCXintro_10[] = +{ + 0x02,0x00, // Graphics Format + 0x00,0x20, // Graphics DataSize + 0x38, // Graphics Start X + 0x20, // Graphics Start Y + 0x0A, // Graphics Width + 0x10, // Graphics Height + 0xFE,0xFE,0x06,0x06,0x66,0x66,0x06,0x06,0xFE,0xFE, + 0x07,0x07,0x06,0x06,0x00,0x00,0x06,0x06,0x07,0x07 +}; diff --git a/AT91SAM7S256/Source/RCXintro_11.txt b/AT91SAM7S256/Source/RCXintro_11.txt new file mode 100644 index 0000000..a8891b5 --- /dev/null +++ b/AT91SAM7S256/Source/RCXintro_11.txt @@ -0,0 +1,11 @@ +const BMPMAP RCXintro_11[] = +{ + 0x02,0x00, // Graphics Format + 0x00,0x10, // Graphics DataSize + 0x3A, // Graphics Start X + 0x20, // Graphics Start Y + 0x08, // Graphics Width + 0x10, // Graphics Height + 0xF8,0xF8,0x18,0xD8,0xD8,0x18,0xF8,0xF8, + 0x07,0x07,0x06,0x00,0x00,0x06,0x07,0x07 +}; diff --git a/AT91SAM7S256/Source/RCXintro_12.txt b/AT91SAM7S256/Source/RCXintro_12.txt new file mode 100644 index 0000000..386beb2 --- /dev/null +++ b/AT91SAM7S256/Source/RCXintro_12.txt @@ -0,0 +1,11 @@ +const BMPMAP RCXintro_12[] = +{ + 0x02,0x00, // Graphics Format + 0x00,0xC0, // Graphics DataSize + 0x03, // Graphics Start X + 0x20, // Graphics Start Y + 0x5E, // Graphics Width + 0x10, // Graphics Height + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xF8,0xF8,0x18,0xD8,0xD8,0x18,0xF8,0xF8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x07,0x07,0x00,0x00,0x07,0x07,0x00,0x00,0x07,0x07,0x00,0x00,0x07,0x07,0x00,0x00,0x07,0x07,0x00,0x00,0x00,0x00,0x07,0x07,0x00,0x00,0x07,0x07,0x00,0x00,0x00,0x00,0x07,0x07,0x00,0x00,0x06,0x06,0x00,0x00,0x00,0x07,0x07,0x00,0x00,0x00,0x00,0x00,0x07,0x07,0x00,0x00,0x00,0x00,0x00,0x07,0x07,0x06,0x00,0x00,0x06,0x07,0x07,0x00,0x00,0x07,0x07,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x07,0x00,0x00,0x07,0x07,0x00,0x00,0x07,0x07,0x00,0x00,0x06,0x06,0x00,0x00,0x00,0x07,0x07 +}; diff --git a/AT91SAM7S256/Source/RCXintro_13.txt b/AT91SAM7S256/Source/RCXintro_13.txt new file mode 100644 index 0000000..84b1753 --- /dev/null +++ b/AT91SAM7S256/Source/RCXintro_13.txt @@ -0,0 +1,11 @@ +const BMPMAP RCXintro_13[] = +{ + 0x02,0x00, // Graphics Format + 0x00,0xC0, // Graphics DataSize + 0x03, // Graphics Start X + 0x20, // Graphics Start Y + 0x5E, // Graphics Width + 0x10, // Graphics Height + 0xE0,0xE0,0x00,0x00,0xE0,0xE0,0x00,0x00,0xE0,0xE0,0x00,0x00,0xE0,0xE0,0x00,0x00,0xE0,0xE0,0x00,0x00,0x00,0x00,0xE0,0xE0,0x00,0x00,0xE0,0xE0,0x00,0x00,0x00,0x00,0xE0,0xE0,0x00,0x00,0xE0,0xE0,0x00,0x00,0x00,0xC0,0xC0,0x00,0x00,0x00,0x00,0x00,0xE0,0xE0,0x00,0x00,0x00,0x00,0x00,0xF8,0xF8,0x18,0xD8,0xD8,0x18,0xF8,0xF8,0x00,0x00,0xE0,0xE0,0x00,0x00,0x00,0x00,0x20,0x20,0x00,0x00,0xE0,0xE0,0x00,0x00,0xE0,0xE0,0x00,0x00,0xE0,0xE0,0x00,0x00,0xE0,0xE0,0x00,0x00,0x00,0xC0,0xC0, + 0x07,0x07,0x00,0x00,0x07,0x07,0x00,0x00,0x07,0x07,0x00,0x00,0x07,0x07,0x00,0x00,0x07,0x07,0x00,0x00,0x00,0x00,0x07,0x07,0x00,0x00,0x07,0x07,0x00,0x00,0x00,0x00,0x07,0x07,0x00,0x00,0x06,0x06,0x00,0x00,0x00,0x07,0x07,0x00,0x00,0x00,0x00,0x00,0x07,0x07,0x00,0x00,0x00,0x00,0x00,0x07,0x07,0x06,0x00,0x00,0x06,0x07,0x07,0x00,0x00,0x07,0x07,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x07,0x00,0x00,0x07,0x07,0x00,0x00,0x07,0x07,0x00,0x00,0x06,0x06,0x00,0x00,0x00,0x07,0x07 +}; diff --git a/AT91SAM7S256/Source/RCXintro_14.txt b/AT91SAM7S256/Source/RCXintro_14.txt new file mode 100644 index 0000000..dc4254a --- /dev/null +++ b/AT91SAM7S256/Source/RCXintro_14.txt @@ -0,0 +1,11 @@ +const BMPMAP RCXintro_14[] = +{ + 0x02,0x00, // Graphics Format + 0x00,0xC0, // Graphics DataSize + 0x03, // Graphics Start X + 0x20, // Graphics Start Y + 0x5E, // Graphics Width + 0x10, // Graphics Height + 0xF8,0xF8,0x00,0x00,0xF8,0xF8,0x00,0x00,0xF8,0xF8,0x00,0x00,0xF8,0xF8,0x00,0x00,0xF8,0xF8,0x00,0x00,0x00,0x00,0xF8,0xF8,0x00,0x00,0xF8,0xF8,0x00,0x00,0x00,0x00,0xFE,0xFE,0x00,0x00,0xF8,0xF8,0x00,0x00,0x00,0xD8,0xD8,0x00,0x00,0x00,0x00,0x00,0xF8,0xF8,0x00,0x00,0x00,0x00,0x00,0xF8,0xF8,0x18,0xD8,0xD8,0x18,0xF8,0xF8,0x00,0x00,0xF8,0xF8,0x00,0x00,0x00,0x00,0x38,0x38,0x00,0x00,0xF8,0xF8,0x00,0x00,0xF8,0xF8,0x00,0x00,0xF8,0xF8,0x00,0x00,0xF8,0xF8,0x00,0x00,0x00,0xD8,0xD8, + 0x07,0x07,0x00,0x00,0x07,0x07,0x00,0x00,0x07,0x07,0x00,0x00,0x07,0x07,0x00,0x00,0x07,0x07,0x00,0x00,0x00,0x00,0x07,0x07,0x00,0x00,0x07,0x07,0x00,0x00,0x00,0x00,0x07,0x07,0x00,0x00,0x06,0x06,0x00,0x00,0x00,0x07,0x07,0x00,0x00,0x00,0x00,0x00,0x07,0x07,0x00,0x00,0x00,0x00,0x00,0x07,0x07,0x06,0x00,0x00,0x06,0x07,0x07,0x00,0x00,0x07,0x07,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x07,0x00,0x00,0x07,0x07,0x00,0x00,0x07,0x07,0x00,0x00,0x06,0x06,0x00,0x00,0x00,0x07,0x07 +}; diff --git a/AT91SAM7S256/Source/RCXintro_15.txt b/AT91SAM7S256/Source/RCXintro_15.txt new file mode 100644 index 0000000..ae03d45 --- /dev/null +++ b/AT91SAM7S256/Source/RCXintro_15.txt @@ -0,0 +1,11 @@ +const BMPMAP RCXintro_15[] = +{ + 0x02,0x00, // Graphics Format + 0x00,0xC0, // Graphics DataSize + 0x03, // Graphics Start X + 0x20, // Graphics Start Y + 0x5E, // Graphics Width + 0x10, // Graphics Height + 0xF8,0xF8,0x18,0x00,0xF8,0xF8,0x18,0x00,0xF8,0xF8,0x00,0x00,0xF8,0xF8,0x00,0x00,0xF8,0xF8,0x18,0x18,0x00,0x00,0xF8,0xF8,0x00,0x00,0xF8,0xF8,0x18,0x18,0x00,0x00,0xFE,0xFE,0x00,0x00,0xF8,0xF8,0x18,0x00,0xC0,0xD8,0xD8,0x00,0x00,0x18,0x18,0x00,0xF8,0xF8,0x18,0x00,0x00,0x00,0x00,0xF8,0xF8,0x18,0xD8,0xD8,0x18,0xF8,0xF8,0x00,0x00,0xF8,0xF8,0x18,0x00,0x00,0x18,0x38,0x38,0x00,0x00,0xF8,0xF8,0x18,0x00,0xF8,0xF8,0x18,0x00,0xF8,0xF8,0x00,0x00,0xF8,0xF8,0x18,0x00,0xC0,0xD8,0xD8, + 0x07,0x07,0x00,0x00,0x07,0x07,0x00,0x00,0x07,0x07,0x00,0x00,0x07,0x07,0x00,0x00,0x07,0x07,0x00,0x00,0x00,0x00,0x07,0x07,0x00,0x00,0x07,0x07,0x00,0x00,0x06,0x06,0x07,0x07,0x00,0x00,0x06,0x06,0x06,0x00,0x00,0x07,0x07,0x00,0x00,0x00,0x00,0x00,0x07,0x07,0x00,0x00,0x00,0x00,0x00,0x07,0x07,0x06,0x00,0x00,0x06,0x07,0x07,0x00,0x00,0x07,0x07,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x07,0x00,0x00,0x07,0x07,0x00,0x00,0x07,0x07,0x00,0x00,0x06,0x06,0x06,0x00,0x00,0x07,0x07 +}; diff --git a/AT91SAM7S256/Source/RCXintro_16.txt b/AT91SAM7S256/Source/RCXintro_16.txt new file mode 100644 index 0000000..47504a8 --- /dev/null +++ b/AT91SAM7S256/Source/RCXintro_16.txt @@ -0,0 +1,11 @@ +const BMPMAP RCXintro_16[] = +{ + 0x02,0x00, // Graphics Format + 0x00,0xC0, // Graphics DataSize + 0x03, // Graphics Start X + 0x20, // Graphics Start Y + 0x5E, // Graphics Width + 0x10, // Graphics Height + 0xF8,0xF8,0x18,0x18,0xF8,0xF8,0x18,0x18,0xF8,0xF8,0x00,0x00,0xF8,0xF8,0x00,0x00,0xF8,0xF8,0x18,0x18,0x18,0x18,0xF8,0xF8,0x00,0x00,0xF8,0xF8,0x18,0x18,0x18,0x18,0xFE,0xFE,0x00,0x00,0xF8,0xF8,0xD8,0xD8,0xD8,0xD8,0xD8,0x00,0x00,0x18,0x18,0x18,0xF8,0xF8,0x18,0x18,0x18,0x00,0x00,0xF8,0xF8,0x18,0xD8,0xD8,0x18,0xF8,0xF8,0x00,0x00,0xF8,0xF8,0x18,0x18,0x18,0x18,0x38,0x38,0x00,0x00,0xF8,0xF8,0x18,0x18,0xF8,0xF8,0x18,0x18,0xF8,0xF8,0x00,0x00,0xF8,0xF8,0xD8,0xD8,0xD8,0xD8,0xD8, + 0x07,0x07,0x00,0x00,0x07,0x07,0x00,0x00,0x07,0x07,0x00,0x00,0x07,0x07,0x00,0x00,0x07,0x07,0x00,0x00,0x00,0x00,0x07,0x07,0x00,0x00,0x07,0x07,0x06,0x06,0x06,0x06,0x07,0x07,0x00,0x00,0x06,0x06,0x06,0x06,0x06,0x07,0x07,0x00,0x00,0x00,0x00,0x00,0x07,0x07,0x00,0x00,0x00,0x00,0x00,0x07,0x07,0x06,0x00,0x00,0x06,0x07,0x07,0x00,0x00,0x07,0x07,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x07,0x00,0x00,0x07,0x07,0x00,0x00,0x07,0x07,0x00,0x00,0x06,0x06,0x06,0x06,0x06,0x07,0x07 +}; diff --git a/AT91SAM7S256/Source/RCXintro_2.txt b/AT91SAM7S256/Source/RCXintro_2.txt new file mode 100644 index 0000000..42698ea --- /dev/null +++ b/AT91SAM7S256/Source/RCXintro_2.txt @@ -0,0 +1,17 @@ +const BMPMAP RCXintro_2[] = +{ + 0x02,0x00, // Graphics Format + 0x02,0x00, // Graphics DataSize + 0x10, // Graphics Start X + 0x00, // Graphics Start Y + 0x40, // Graphics Width + 0x40, // Graphics Height + 0xFC,0x02,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0xFD,0x02,0xFC, + 0xFF,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x7F,0x3F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x3F,0x7F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0xFF, + 0xFF,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x7F,0x1F,0x8F,0xC7,0xE7,0x67,0x30,0x30,0x30,0x60,0xE0,0x80,0xC0,0xE0,0x60,0x60,0x30,0x30,0x30,0x30,0x30,0x20,0x60,0xC0,0xC0,0xE0,0x60,0x60,0x30,0x30,0x30,0x30,0x30,0x60,0x60,0xC0,0x80,0x80,0xC0,0x60,0x60,0x20,0x33,0x33,0x33,0x33,0x63,0x67,0xC7,0x8F,0x1F,0x33,0xF3,0xFF,0x00,0xFF, + 0xFF,0x00,0xFF,0xFF,0x7F,0x0F,0x83,0xE0,0x78,0x1E,0x07,0x01,0x00,0x00,0x80,0xE0,0xF8,0x7E,0x1F,0x07,0x01,0x00,0x00,0x00,0x18,0x18,0x18,0xF8,0xF8,0x1C,0x06,0x03,0x00,0x00,0xC0,0x70,0x3C,0x3C,0x30,0x20,0x20,0xE0,0xF0,0x3D,0x0F,0x03,0x00,0x00,0xC0,0xF0,0xFC,0x3C,0x00,0x00,0x00,0x00,0xC0,0xFF,0x1E,0x00,0xC0,0xFF,0x00,0xFF, + 0xFF,0x00,0xFF,0x01,0x00,0xFC,0xFF,0x03,0x00,0x00,0x00,0x00,0x00,0x0E,0x0F,0xFF,0xC7,0x00,0x00,0x00,0x00,0x00,0x0E,0x0E,0x0E,0x0E,0xFE,0xC7,0x80,0x00,0x00,0x00,0x00,0x1F,0x1F,0x0E,0x00,0x00,0x80,0xC0,0xF0,0xFF,0x83,0x00,0x00,0x00,0x1C,0x1F,0x0F,0x03,0x00,0x80,0xC0,0xE0,0x78,0x1E,0xC7,0xE1,0xF8,0xFF,0xFF,0xFF,0x00,0xFF, + 0xFF,0x00,0xFF,0xFE,0xFE,0xFC,0xF3,0xF3,0xE6,0xE6,0xE6,0xE6,0xE6,0xF2,0x83,0x01,0x01,0x03,0x06,0x06,0x06,0x06,0x06,0x06,0x03,0x03,0x01,0x01,0x03,0x03,0x06,0x06,0x06,0x06,0x06,0x06,0x03,0x03,0x01,0x00,0x00,0x01,0x03,0x03,0x06,0x06,0x06,0x06,0x06,0x86,0xF3,0xFB,0xF9,0xFC,0xFE,0xFE,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0xFF, + 0xFF,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFE,0xFC,0xF8,0xF8,0xF8,0xF8,0xF8,0xF8,0xF8,0xF8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xF8,0xF8,0xF8,0xF8,0xF8,0xF8,0xF8,0xF8,0xF8,0xFE,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0xFF, + 0x3F,0x40,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0x7F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0xBF,0x40,0x3F +}; diff --git a/AT91SAM7S256/Source/RCXintro_3.txt b/AT91SAM7S256/Source/RCXintro_3.txt new file mode 100644 index 0000000..308de3a --- /dev/null +++ b/AT91SAM7S256/Source/RCXintro_3.txt @@ -0,0 +1,17 @@ +const BMPMAP RCXintro_3[] = +{ + 0x02,0x00, // Graphics Format + 0x02,0x00, // Graphics DataSize + 0x10, // Graphics Start X + 0x00, // Graphics Start Y + 0x40, // Graphics Width + 0x40, // Graphics Height + 0xFC,0xFE,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFE,0xFC, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x7F,0x3F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x3F,0x7F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x7F,0x1F,0x07,0x07,0xC3,0xF1,0x79,0x1F,0x00,0x00,0x00,0x00,0xF8,0x7E,0x07,0x03,0x19,0x18,0xF8,0xFC,0xFC,0xFC,0xFF,0xFF,0xFF,0xFF,0xFD,0xFD,0xFC,0xF8,0x31,0x3F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xC0,0x30,0x0C,0x07,0x81,0xE0,0x3C,0x01,0x01,0xC3,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xC3,0x80,0x80,0x80,0x80,0x8F,0xDF,0x70,0x00,0x00,0x00,0x00,0x00,0x7F,0xC0,0x80,0x80,0xCE,0xCE,0x5F,0x7F,0xFF,0xFF,0xBF,0xBF,0x3F,0x3F,0x3F,0x3F,0xBF,0xDF,0x78,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0x63,0xC0,0x80,0xC6,0xE3,0xC0,0xE0,0xF8,0xFE,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFE,0xFC,0xF8,0xF8,0xF8,0xF8,0xF8,0xF8,0xF8,0xF8,0xF8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xF8,0xF8,0xF8,0xF8,0xF8,0xF8,0xF8,0xF8,0xF8,0xFC,0xFE,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0x3F,0x7F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x7F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x7F,0x3F +}; diff --git a/AT91SAM7S256/Source/RCXintro_4.txt b/AT91SAM7S256/Source/RCXintro_4.txt new file mode 100644 index 0000000..cf969c2 --- /dev/null +++ b/AT91SAM7S256/Source/RCXintro_4.txt @@ -0,0 +1,17 @@ +const BMPMAP RCXintro_4[] = +{ + 0x02,0x00, // Graphics Format + 0x02,0x00, // Graphics DataSize + 0x10, // Graphics Start X + 0x00, // Graphics Start Y + 0x40, // Graphics Width + 0x40, // Graphics Height + 0xFC,0xFE,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFE,0xFC, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x7F,0x3F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x3F,0x7F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xF8,0xFC,0xFC,0xFC,0xFC,0xFC,0xFC,0xFC,0xFC,0xFC,0xFC,0xF8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0x3F,0x3F,0x3F,0x3F,0x3F,0x3F,0x3F,0x3F,0x3F,0x3F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFE,0xFC,0xF8,0xF8,0xF8,0xF8,0xF8,0xF8,0xF8,0xF8,0xF0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xF0,0xF8,0xF8,0xF8,0xF8,0xF8,0xF8,0xF8,0xF8,0xFC,0xFE,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0x3F,0x7F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x7F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x7F,0x3F +}; diff --git a/AT91SAM7S256/Source/RCXintro_5.txt b/AT91SAM7S256/Source/RCXintro_5.txt new file mode 100644 index 0000000..f5bdbd3 --- /dev/null +++ b/AT91SAM7S256/Source/RCXintro_5.txt @@ -0,0 +1,17 @@ +const BMPMAP RCXintro_5[] = +{ + 0x02,0x00, // Graphics Format + 0x01,0xC0, // Graphics DataSize + 0x17, // Graphics Start X + 0x00, // Graphics Start Y + 0x34, // Graphics Width + 0x40, // Graphics Height + 0x80,0xC0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xC0,0x80, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x03,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x03,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xF8,0xFC,0xFC,0xFC,0xFC,0xFC,0xFC,0xFC,0xFC,0xF8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x07,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xF0,0xE0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xE0,0xF0,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0x7F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x7F, + 0x00,0x00,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x00,0x00 +}; diff --git a/AT91SAM7S256/Source/RCXintro_6.txt b/AT91SAM7S256/Source/RCXintro_6.txt new file mode 100644 index 0000000..103a310 --- /dev/null +++ b/AT91SAM7S256/Source/RCXintro_6.txt @@ -0,0 +1,15 @@ +const BMPMAP RCXintro_6[] = +{ + 0x02,0x00, // Graphics Format + 0x01,0x20, // Graphics DataSize + 0x1C, // Graphics Start X + 0x08, // Graphics Start Y + 0x2C, // Graphics Width + 0x30, // Graphics Height + 0xFE,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFE, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x07,0x03,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x03,0x07,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xF8,0xFC,0xFC,0xFC,0xFC,0xFC,0xFC,0xF8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x03,0x03,0x03,0x03,0x03,0x03,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFE,0xFC,0xF8,0xF8,0xF8,0xF8,0xF8,0xF8,0xF0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xF0,0xF8,0xF8,0xF8,0xF8,0xF8,0xF8,0xFC,0xFE,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0x07,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x07,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x07 +}; diff --git a/AT91SAM7S256/Source/RCXintro_7.txt b/AT91SAM7S256/Source/RCXintro_7.txt new file mode 100644 index 0000000..2451fe4 --- /dev/null +++ b/AT91SAM7S256/Source/RCXintro_7.txt @@ -0,0 +1,14 @@ +const BMPMAP RCXintro_7[] = +{ + 0x02,0x00, // Graphics Format + 0x00,0xC8, // Graphics DataSize + 0x23, // Graphics Start X + 0x10, // Graphics Start Y + 0x22, // Graphics Width + 0x28, // Graphics Height + 0xFE,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFE, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0xC0,0xC0,0xC0,0xC0,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x0F,0x0F,0x0F,0x0F,0x07,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFC,0xF8,0xF8,0xF8,0xF8,0xF8,0xF0,0x00,0x00,0x00,0x00,0x00,0x00,0xF0,0xF8,0xF8,0xF8,0xF8,0xF8,0xFC,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0x01,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x01 +}; diff --git a/AT91SAM7S256/Source/RCXintro_8.txt b/AT91SAM7S256/Source/RCXintro_8.txt new file mode 100644 index 0000000..51107b0 --- /dev/null +++ b/AT91SAM7S256/Source/RCXintro_8.txt @@ -0,0 +1,12 @@ +const BMPMAP RCXintro_8[] = +{ + 0x02,0x00, // Graphics Format + 0x00,0x48, // Graphics DataSize + 0x2C, // Graphics Start X + 0x18, // Graphics Start Y + 0x16, // Graphics Width + 0x18, // Graphics Height + 0xFE,0xFF,0xFF,0xFF,0x1F,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x1F,0xFF,0xFF,0xFF,0xFE, + 0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x1E,0x1E,0x1E,0x1E,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF, + 0x1F,0x3F,0x3F,0x3F,0x3E,0x3C,0x3C,0x3C,0x3C,0x00,0x00,0x00,0x00,0x3C,0x3C,0x3C,0x3C,0x3E,0x3F,0x3F,0x3F,0x1F +}; diff --git a/AT91SAM7S256/Source/RCXintro_9.txt b/AT91SAM7S256/Source/RCXintro_9.txt new file mode 100644 index 0000000..479704c --- /dev/null +++ b/AT91SAM7S256/Source/RCXintro_9.txt @@ -0,0 +1,12 @@ +const BMPMAP RCXintro_9[] = +{ + 0x02,0x00, // Graphics Format + 0x00,0x30, // Graphics DataSize + 0x34, // Graphics Start X + 0x18, // Graphics Start Y + 0x0E, // Graphics Width + 0x18, // Graphics Height + 0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0, + 0xFF,0xFF,0xFF,0x00,0x00,0x3C,0x3C,0x3C,0x3C,0x00,0x00,0xFF,0xFF,0xFF, + 0x07,0x07,0x07,0x07,0x07,0x00,0x00,0x00,0x00,0x07,0x07,0x07,0x07,0x07 +}; diff --git a/AT91SAM7S256/Source/Running.txt b/AT91SAM7S256/Source/Running.txt new file mode 100644 index 0000000..963e372 --- /dev/null +++ b/AT91SAM7S256/Source/Running.txt @@ -0,0 +1,57 @@ +const ICON Running[] = +{ + 0x04,0x00, // Graphics Format + 0x04,0x80, // Graphics DataSize + 0x01, // Graphics Count X + 0x10, // Graphics Count Y + 0x18, // Graphics Width + 0x18, // Graphics Height + 0x00,0x00,0x00,0xE0,0xF0,0x38,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x38,0xF0,0xE0,0x00,0x00,0x00, + 0x00,0x00,0x00,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x3C,0x3C,0x3C,0x3C,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0x00,0x00,0x00, + 0x00,0x00,0x00,0x07,0x0F,0x1C,0x18,0x18,0x18,0x18,0x00,0x00,0x00,0x00,0x18,0x18,0x18,0x18,0x1C,0x0F,0x07,0x00,0x00,0x00, + 0x00,0x00,0x00,0xE0,0xF0,0x38,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x38,0xF0,0xE0,0x00,0x00,0x00, + 0x00,0x00,0x00,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x3C,0x3C,0x3C,0x3C,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0x00,0x00,0x00, + 0x00,0x00,0x00,0x07,0x0F,0x1C,0x18,0x00,0x00,0x00,0x00,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x1C,0x0F,0x07,0x00,0x00,0x00, + 0x00,0x00,0x00,0xE0,0xF0,0x38,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x38,0xF0,0xE0,0x00,0x00,0x00, + 0x00,0x00,0x00,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x3C,0x3C,0x3C,0x3C,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0x00,0x00,0x00, + 0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x1C,0x0F,0x07,0x00,0x00,0x00, + 0x00,0x00,0x00,0xE0,0xF0,0x38,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x38,0xF0,0xE0,0x00,0x00,0x00, + 0x00,0x00,0x00,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x3C,0x3C,0x3C,0x3C,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0x00,0x00,0x00, + 0x00,0x00,0x00,0x06,0x0E,0x1C,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x1C,0x0F,0x07,0x00,0x00,0x00, + 0x00,0x00,0x00,0xE0,0xF0,0x38,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x38,0xF0,0xE0,0x00,0x00,0x00, + 0x00,0x00,0x00,0xC3,0xC3,0x00,0x00,0x00,0x00,0x00,0x3C,0x3C,0x3C,0x3C,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0x00,0x00,0x00, + 0x00,0x00,0x00,0x07,0x0F,0x1C,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x1C,0x0F,0x07,0x00,0x00,0x00, + 0x00,0x00,0x00,0x60,0x70,0x38,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x38,0xF0,0xE0,0x00,0x00,0x00, + 0x00,0x00,0x00,0xF8,0xF8,0x00,0x00,0x00,0x00,0x00,0x3C,0x3C,0x3C,0x3C,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0x00,0x00,0x00, + 0x00,0x00,0x00,0x07,0x0F,0x1C,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x1C,0x0F,0x07,0x00,0x00,0x00, + 0x00,0x00,0x00,0x80,0x80,0x00,0x00,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x38,0xF0,0xE0,0x00,0x00,0x00, + 0x00,0x00,0x00,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x3C,0x3C,0x3C,0x3C,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0x00,0x00,0x00, + 0x00,0x00,0x00,0x07,0x0F,0x1C,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x1C,0x0F,0x07,0x00,0x00,0x00, + 0x00,0x00,0x00,0xE0,0xF0,0x38,0x18,0x00,0x00,0x00,0x00,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x38,0xF0,0xE0,0x00,0x00,0x00, + 0x00,0x00,0x00,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x3C,0x3C,0x3C,0x3C,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0x00,0x00,0x00, + 0x00,0x00,0x00,0x07,0x0F,0x1C,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x1C,0x0F,0x07,0x00,0x00,0x00, + 0x00,0x00,0x00,0xE0,0xF0,0x38,0x18,0x18,0x18,0x18,0x00,0x00,0x00,0x00,0x18,0x18,0x18,0x18,0x38,0xF0,0xE0,0x00,0x00,0x00, + 0x00,0x00,0x00,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x3C,0x3C,0x3C,0x3C,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0x00,0x00,0x00, + 0x00,0x00,0x00,0x07,0x0F,0x1C,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x1C,0x0F,0x07,0x00,0x00,0x00, + 0x00,0x00,0x00,0xE0,0xF0,0x38,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x00,0x00,0x00,0x00,0x18,0x38,0xF0,0xE0,0x00,0x00,0x00, + 0x00,0x00,0x00,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x3C,0x3C,0x3C,0x3C,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0x00,0x00,0x00, + 0x00,0x00,0x00,0x07,0x0F,0x1C,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x1C,0x0F,0x07,0x00,0x00,0x00, + 0x00,0x00,0x00,0xE0,0xF0,0x38,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x00,0x00,0x80,0x80,0x00,0x00,0x00, + 0x00,0x00,0x00,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x3C,0x3C,0x3C,0x3C,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0x00,0x00,0x00, + 0x00,0x00,0x00,0x07,0x0F,0x1C,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x1C,0x0F,0x07,0x00,0x00,0x00, + 0x00,0x00,0x00,0xE0,0xF0,0x38,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x38,0x70,0x60,0x00,0x00,0x00, + 0x00,0x00,0x00,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x3C,0x3C,0x3C,0x3C,0x00,0x00,0x00,0x00,0x00,0xF8,0xF8,0x00,0x00,0x00, + 0x00,0x00,0x00,0x07,0x0F,0x1C,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x1C,0x0F,0x07,0x00,0x00,0x00, + 0x00,0x00,0x00,0xE0,0xF0,0x38,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x38,0xF0,0xE0,0x00,0x00,0x00, + 0x00,0x00,0x00,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x3C,0x3C,0x3C,0x3C,0x00,0x00,0x00,0x00,0x00,0xC3,0xC3,0x00,0x00,0x00, + 0x00,0x00,0x00,0x07,0x0F,0x1C,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x1C,0x0F,0x07,0x00,0x00,0x00, + 0x00,0x00,0x00,0xE0,0xF0,0x38,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x38,0xF0,0xE0,0x00,0x00,0x00, + 0x00,0x00,0x00,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x3C,0x3C,0x3C,0x3C,0x00,0x00,0x00,0x00,0x00,0x1F,0x1F,0x00,0x00,0x00, + 0x00,0x00,0x00,0x07,0x0F,0x1C,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x1C,0x0E,0x06,0x00,0x00,0x00, + 0x00,0x00,0x00,0xE0,0xF0,0x38,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x38,0xF0,0xE0,0x00,0x00,0x00, + 0x00,0x00,0x00,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x3C,0x3C,0x3C,0x3C,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0x00,0x00,0x00, + 0x00,0x00,0x00,0x07,0x0F,0x1C,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x00,0x00,0x01,0x01,0x00,0x00,0x00, + 0x00,0x00,0x00,0xE0,0xF0,0x38,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x38,0xF0,0xE0,0x00,0x00,0x00, + 0x00,0x00,0x00,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x3C,0x3C,0x3C,0x3C,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0x00,0x00,0x00, + 0x00,0x00,0x00,0x07,0x0F,0x1C,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x00,0x00,0x00,0x00,0x18,0x1C,0x0F,0x07,0x00,0x00,0x00 +}; diff --git a/AT91SAM7S256/Source/Status.txt b/AT91SAM7S256/Source/Status.txt new file mode 100644 index 0000000..7434a7a --- /dev/null +++ b/AT91SAM7S256/Source/Status.txt @@ -0,0 +1,15 @@ +const ICON Status[] = +{ + 0x04,0x00, // Graphics Format + 0x01,0xB0, // Graphics DataSize + 0x06, // Graphics Count X + 0x06, // Graphics Count Y + 0x0C, // Graphics Width + 0x08, // Graphics Height + 0x00,0x00,0x7E,0x81,0x81,0x19,0x19,0x81,0x81,0x7E,0x00,0x00,0x00,0x00,0x7E,0x01,0x01,0x99,0x99,0x81,0x81,0x7E,0x00,0x00,0x00,0x00,0x1E,0x81,0x81,0x99,0x99,0x81,0x81,0x7E,0x00,0x00,0x00,0x00,0x66,0x81,0x81,0x99,0x99,0x81,0x81,0x7E,0x00,0x00,0x00,0x00,0x78,0x81,0x81,0x99,0x99,0x81,0x81,0x7E,0x00,0x00,0x00,0x00,0x7E,0x80,0x80,0x99,0x99,0x81,0x81,0x7E,0x00,0x00, + 0x00,0x00,0x7E,0x81,0x81,0x98,0x98,0x81,0x81,0x7E,0x00,0x00,0x00,0x00,0x7E,0x81,0x81,0x99,0x99,0x80,0x80,0x7E,0x00,0x00,0x00,0x00,0x7E,0x81,0x81,0x99,0x99,0x81,0x81,0x78,0x00,0x00,0x00,0x00,0x7E,0x81,0x81,0x99,0x99,0x81,0x81,0x66,0x00,0x00,0x00,0x00,0x7E,0x81,0x81,0x99,0x99,0x81,0x81,0x1E,0x00,0x00,0x00,0x00,0x7E,0x81,0x81,0x99,0x99,0x01,0x01,0x7E,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x24,0x24,0x24,0x24,0x24,0x3C,0x3C,0x00,0x00,0x00,0x00,0x18,0x24,0x24,0x24,0x24,0x3C,0x3C,0x3C,0x00,0x00,0x00,0x00,0x18,0x24,0x24,0x3C,0x3C,0x3C,0x3C,0x3C,0x00,0x00,0x00,0x00,0x18,0x3C,0x3C,0x3C,0x3C,0x3C,0x3C,0x3C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x24,0x24,0x24,0x24,0x24,0x3C,0x3C,0x00,0x00,0x00,0x00,0x18,0x24,0x24,0x24,0x24,0x3C,0x3C,0x3C,0x00,0x00,0x00,0x00,0x18,0x24,0x24,0x3C,0x3C,0x3C,0x3C,0x3C,0x00,0x00,0x00,0x00,0x18,0x3C,0x3C,0x3C,0x3C,0x3C,0x3C,0x3C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x22,0x14,0x7F,0x2A,0x14,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x22,0x14,0x7F,0x2A,0x14,0x00,0x08,0x14,0x22,0x00,0x00,0x00,0x22,0x14,0x7F,0x2A,0x14,0x00,0x00,0x00,0x22,0x14,0x08,0x00,0x22,0x14,0x7F,0x2A,0x14,0x00,0x08,0x14,0x22,0x14,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3E,0x22,0x1C,0x00,0x3E,0x0A,0x02,0x00,0x3E,0x20,0x3E,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0x14,0x1C,0x08,0x08,0x08,0x08,0x08,0x1C,0x14,0x14,0x00,0x3E,0x20,0x3E,0x00,0x2E,0x2A,0x3A,0x00,0x3E,0x2A,0x3E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 +}; diff --git a/AT91SAM7S256/Source/Step.txt b/AT91SAM7S256/Source/Step.txt new file mode 100644 index 0000000..dcec616 --- /dev/null +++ b/AT91SAM7S256/Source/Step.txt @@ -0,0 +1,17 @@ +const ICON Step[] = +{ + 0x04,0x00, // Graphics Format + 0x02,0xC0, // Graphics DataSize + 0x08, // Graphics Count X + 0x04, // Graphics Count Y + 0x0B, // Graphics Width + 0x10, // Graphics Height + 0xFF,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0xFF,0xFF,0x01,0x01,0x11,0x19,0x7D,0x19,0x11,0x01,0x01,0xFF,0xFF,0x01,0x01,0x11,0x19,0x7D,0x19,0x11,0x05,0x01,0xFF,0xFF,0x01,0x11,0x39,0x7D,0x11,0x1D,0x01,0x05,0x01,0xFF,0xFF,0x01,0x11,0x39,0x7D,0x11,0x71,0x01,0x01,0x01,0xFF,0xFF,0x01,0x11,0x39,0x7D,0x11,0x71,0x01,0x05,0x01,0xFF,0xFF,0x01,0x01,0x01,0x1D,0x11,0x7D,0x39,0x11,0x01,0xFF,0xFF,0x01,0x01,0x01,0x71,0x11,0x7D,0x39,0x11,0x01,0xFF, + 0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01, + 0xFF,0x01,0x05,0x01,0x71,0x11,0x7D,0x39,0x11,0x01,0xFF,0xFF,0x01,0x11,0x39,0x7D,0x11,0x1D,0x01,0x01,0x01,0xFF,0xFF,0x01,0x01,0x21,0x71,0x71,0x3D,0x01,0x01,0x01,0xFF,0xFF,0x01,0x01,0x21,0x71,0x71,0x3D,0x01,0x01,0x01,0xFF,0xFF,0x01,0x01,0x11,0x31,0x7D,0x31,0x11,0x01,0x01,0xFF,0xFF,0x01,0x01,0x11,0x31,0x7D,0x31,0x11,0x05,0x01,0xFF,0xFF,0x01,0x05,0x01,0x1D,0x11,0x7D,0x39,0x11,0x01,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0xFF,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0xFF,0xFF,0x01,0x01,0x39,0x45,0x45,0x45,0x39,0x01,0x01,0xFF,0xFF,0x01,0xF1,0x39,0x45,0xFF,0x11,0x45,0x39,0x01,0xFF,0xFF,0x01,0x39,0x29,0x29,0x39,0x45,0x45,0x39,0x01,0xFF,0xFF,0x01,0x01,0x01,0x01,0x01,0x39,0x45,0xFF,0x01,0xFF,0xFF,0x01,0x01,0xC7,0xAB,0x93,0xAB,0xC7,0x01,0x01,0xFF,0xFF,0x01,0x01,0xC7,0xAB,0x93,0xAB,0xC7,0x01,0x01,0xFF,0xFF,0x01,0x01,0xC7,0xAB,0x93,0xAB,0xC7,0x01,0x01,0xFF, + 0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01, + 0xFF,0x01,0x01,0x39,0x7D,0x7D,0x7D,0x39,0x01,0x01,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x01,0x39,0x41,0x45,0x4F,0x45,0x39,0x01,0x01,0xFF,0xFF,0x01,0x49,0x55,0x25,0x01,0x05,0x7D,0x05,0x01,0xFF, + 0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01 +}; diff --git a/AT91SAM7S256/Source/Submenu01.rms b/AT91SAM7S256/Source/Submenu01.rms new file mode 100644 index 0000000..aadf93d --- /dev/null +++ b/AT91SAM7S256/Source/Submenu01.rms @@ -0,0 +1,128 @@ +const UBYTE SUBMENU01[] = +{ + 0x07,0x00, // Menu Format + 0x01,0xED, // Menu DataSize + 0x1D, // Menu item size + 0x11, // Menu items + 0x18, // Menu icon Width + 0x18, // Menu icon Height + + // Software_files + 0x00,0x00,0x00,0x01, // 0x00000001 + 0x10,0x00,0x80,0x01, // 0x10008001 + 0x06,0x02,0x00,0x01, // 6 ,2 ,0 ,1 + 0x53,0x6F,0x66,0x74,0x77,0x61,0x72,0x65,0x20,0x66,0x69,0x6C,0x65,0x73,0x00,0x00, + 0x1C, // 1C + + // NXT_files + 0x00,0x00,0x00,0x02, // 0x00000002 + 0x10,0x00,0x80,0x01, // 0x10008001 + 0x06,0x03,0x00,0x01, // 6 ,3 ,0 ,1 + 0x4E,0x58,0x54,0x20,0x66,0x69,0x6C,0x65,0x73,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x1D, // 1D + + // Sound_files + 0x00,0x00,0x00,0x03, // 0x00000003 + 0x10,0x00,0x80,0x01, // 0x10008001 + 0x06,0x01,0x00,0x01, // 6 ,1 ,0 ,1 + 0x53,0x6F,0x75,0x6E,0x64,0x20,0x66,0x69,0x6C,0x65,0x73,0x00,0x00,0x00,0x00,0x00, + 0x1B, // 1B + + // Datalog_files + 0x00,0x00,0x00,0x04, // 0x00000004 + 0x00,0x80,0x80,0x00, // 0x00808000 + 0x06,0x05,0x00,0x02, // 6 ,5 ,0 ,2 + 0x44,0x61,0x74,0x61,0x6C,0x6F,0x67,0x20,0x66,0x69,0x6C,0x65,0x73,0x00,0x00,0x00, + 0x1F, // 1F + + // _ + 0x00,0x00,0x00,0x11, // 0x00000011 + 0x00,0x00,0x03,0x00, // 0x00000300 + 0x06,0xF2,0x00,0x01, // 6 ,242,0 ,1 + 0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00, // 00 + + // _ + 0x00,0x00,0x00,0x14, // 0x00000014 + 0x00,0x00,0x03,0x00, // 0x00000300 + 0x06,0xF2,0x00,0x01, // 6 ,242,0 ,1 + 0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00, // 00 + + // Run + 0x00,0x00,0x01,0x11, // 0x00000111 + 0x00,0x00,0x01,0x20, // 0x00000120 + 0x08,0xF8,0x00,0x00, // 8 ,248,0 ,0 + 0x52,0x75,0x6E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x32, // 32 + + // Send + 0x00,0x00,0x02,0x11, // 0x00000211 + 0x00,0x40,0x00,0x00, // 0x00400000 + 0x00,0x00,0x00,0x01, // 0 ,0 ,0 ,1 + 0x53,0x65,0x6E,0x64,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x33, // 33 + + // Delete + 0x00,0x00,0x03,0x11, // 0x00000311 + 0x00,0x00,0x00,0x00, // 0x00000000 + 0x00,0x00,0x00,0x02, // 0 ,0 ,0 ,2 + 0x44,0x65,0x6C,0x65,0x74,0x65,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x34, // 34 + + // Delete + 0x00,0x00,0x01,0x14, // 0x00000114 + 0x00,0x00,0x00,0x00, // 0x00000000 + 0x00,0x00,0x00,0x02, // 0 ,0 ,0 ,2 + 0x44,0x65,0x6C,0x65,0x74,0x65,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x34, // 34 + + // Send + 0x00,0x00,0x02,0x14, // 0x00000214 + 0x00,0x40,0x00,0x00, // 0x00400000 + 0x00,0x00,0x00,0x01, // 0 ,0 ,0 ,1 + 0x53,0x65,0x6E,0x64,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x33, // 33 + + // _ + 0x00,0x00,0x12,0x11, // 0x00001211 + 0x00,0x00,0x03,0x00, // 0x00000300 + 0x10,0xF9,0x00,0x00, // 16 ,249,0 ,0 + 0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00, // 00 + + // Are_you_sure? + 0x00,0x00,0x13,0x11, // 0x00001311 + 0x00,0x00,0x00,0x08, // 0x00000008 + 0x09,0x00,0x00,0x00, // 9 ,0 ,0 ,0 + 0x41,0x72,0x65,0x20,0x79,0x6F,0x75,0x20,0x73,0x75,0x72,0x65,0x3F,0x00,0x00,0x00, + 0x31, // 31 + + // Are_you_sure? + 0x00,0x00,0x23,0x11, // 0x00002311 + 0x00,0x00,0x00,0x04, // 0x00000004 + 0x00,0x00,0x00,0x00, // 0 ,0 ,0 ,0 + 0x41,0x72,0x65,0x20,0x79,0x6F,0x75,0x20,0x73,0x75,0x72,0x65,0x3F,0x00,0x00,0x00, + 0x30, // 30 + + // Are_you_sure? + 0x00,0x00,0x11,0x14, // 0x00001114 + 0x00,0x00,0x00,0x08, // 0x00000008 + 0x09,0x00,0x00,0x00, // 9 ,0 ,0 ,0 + 0x41,0x72,0x65,0x20,0x79,0x6F,0x75,0x20,0x73,0x75,0x72,0x65,0x3F,0x00,0x00,0x00, + 0x31, // 31 + + // Are_you_sure? + 0x00,0x00,0x21,0x14, // 0x00002114 + 0x00,0x00,0x00,0x04, // 0x00000004 + 0x00,0x00,0x00,0x00, // 0 ,0 ,0 ,0 + 0x41,0x72,0x65,0x20,0x79,0x6F,0x75,0x20,0x73,0x75,0x72,0x65,0x3F,0x00,0x00,0x00, + 0x30, // 30 + + // _ + 0x00,0x00,0x12,0x14, // 0x00001214 + 0x00,0x00,0x03,0x00, // 0x00000300 + 0x10,0xF9,0x00,0x00, // 16 ,249,0 ,0 + 0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00, // 00 +}; diff --git a/AT91SAM7S256/Source/Submenu02.rms b/AT91SAM7S256/Source/Submenu02.rms new file mode 100644 index 0000000..a30478f --- /dev/null +++ b/AT91SAM7S256/Source/Submenu02.rms @@ -0,0 +1,401 @@ +const UBYTE SUBMENU02[] = +{ + 0x07,0x00, // Menu Format + 0x06,0x58, // Menu DataSize + 0x1D, // Menu item size + 0x38, // Menu items + 0x18, // Menu icon Width + 0x18, // Menu icon Height + + // _ + 0x00,0x00,0x00,0x01, // 0x00000001 + 0x00,0x00,0x03,0x00, // 0x00000300 + 0x0B,0xF7,0x00,0x01, // 11 ,247,0 ,1 + 0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00, // 00 + + // Forward_5 + 0x00,0x00,0x00,0x11, // 0x00000011 + 0x10,0x00,0x00,0x61, // 0x10000061 + 0x0B,0x23,0x00,0x01, // 11 ,35 ,0 ,1 + 0x46,0x6F,0x72,0x77,0x61,0x72,0x64,0x20,0x35,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x23, // 23 + + // Forward + 0x00,0x00,0x00,0x21, // 0x00000021 + 0x10,0x00,0x00,0x61, // 0x10000061 + 0x0B,0x22,0x00,0x01, // 11 ,34 ,0 ,1 + 0x46,0x6F,0x72,0x77,0x61,0x72,0x64,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x22, // 22 + + // Turn_right_2 + 0x00,0x00,0x00,0x31, // 0x00000031 + 0x10,0x00,0x00,0x61, // 0x10000061 + 0x0B,0x29,0x00,0x01, // 11 ,41 ,0 ,1 + 0x54,0x75,0x72,0x6E,0x20,0x72,0x69,0x67,0x68,0x74,0x20,0x32,0x00,0x00,0x00,0x00, + 0x29, // 29 + + // Turn_right + 0x00,0x00,0x00,0x41, // 0x00000041 + 0x10,0x00,0x00,0x61, // 0x10000061 + 0x0B,0x28,0x00,0x01, // 11 ,40 ,0 ,1 + 0x54,0x75,0x72,0x6E,0x20,0x72,0x69,0x67,0x68,0x74,0x00,0x00,0x00,0x00,0x00,0x00, + 0x28, // 28 + + // Back_right_2 + 0x00,0x00,0x00,0x51, // 0x00000051 + 0x10,0x00,0x00,0x61, // 0x10000061 + 0x0B,0x2F,0x00,0x01, // 11 ,47 ,0 ,1 + 0x42,0x61,0x63,0x6B,0x20,0x72,0x69,0x67,0x68,0x74,0x20,0x32,0x00,0x00,0x00,0x00, + 0x2F, // 2F + + // Back_right + 0x00,0x00,0x00,0x61, // 0x00000061 + 0x10,0x00,0x00,0x61, // 0x10000061 + 0x0B,0x27,0x00,0x01, // 11 ,39 ,0 ,1 + 0x42,0x61,0x63,0x6B,0x20,0x72,0x69,0x67,0x68,0x74,0x00,0x00,0x00,0x00,0x00,0x00, + 0x27, // 27 + + // Tone_1 + 0x00,0x00,0x00,0x71, // 0x00000071 + 0x10,0x00,0x00,0x61, // 0x10000061 + 0x0B,0x2B,0x00,0x01, // 11 ,43 ,0 ,1 + 0x54,0x6F,0x6E,0x65,0x20,0x31,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x2B, // 2B + + // Tone_2 + 0x00,0x00,0x00,0x81, // 0x00000081 + 0x10,0x00,0x00,0x61, // 0x10000061 + 0x0B,0x2C,0x00,0x01, // 11 ,44 ,0 ,1 + 0x54,0x6F,0x6E,0x65,0x20,0x32,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x2C, // 2C + + // Back_left_2 + 0x00,0x00,0x00,0x91, // 0x00000091 + 0x10,0x00,0x00,0x61, // 0x10000061 + 0x0B,0x24,0x00,0x01, // 11 ,36 ,0 ,1 + 0x42,0x61,0x63,0x6B,0x20,0x6C,0x65,0x66,0x74,0x20,0x32,0x00,0x00,0x00,0x00,0x00, + 0x24, // 24 + + // Back_left + 0x00,0x00,0x00,0xA1, // 0x000000A1 + 0x10,0x00,0x00,0x61, // 0x10000061 + 0x0B,0x2A,0x00,0x01, // 11 ,42 ,0 ,1 + 0x42,0x61,0x63,0x6B,0x20,0x6C,0x65,0x66,0x74,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x2A, // 2A + + // Turn_left + 0x00,0x00,0x00,0xB1, // 0x000000B1 + 0x10,0x00,0x00,0x61, // 0x10000061 + 0x0B,0x25,0x00,0x01, // 11 ,37 ,0 ,1 + 0x54,0x75,0x72,0x6E,0x20,0x6C,0x65,0x66,0x74,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x25, // 25 + + // Turn_left_2 + 0x00,0x00,0x00,0xC1, // 0x000000C1 + 0x10,0x00,0x00,0x61, // 0x10000061 + 0x0B,0x26,0x00,0x01, // 11 ,38 ,0 ,1 + 0x54,0x75,0x72,0x6E,0x20,0x6C,0x65,0x66,0x74,0x20,0x32,0x00,0x00,0x00,0x00,0x00, + 0x26, // 26 + + // Empty + 0x00,0x00,0x00,0xD1, // 0x000000D1 + 0x10,0x00,0x00,0x61, // 0x10000061 + 0x0B,0x21,0x00,0x01, // 11 ,33 ,0 ,1 + 0x45,0x6D,0x70,0x74,0x79,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x21, // 21 + + // Backward + 0x00,0x00,0x00,0xE1, // 0x000000E1 + 0x10,0x00,0x00,0x61, // 0x10000061 + 0x0B,0x2D,0x00,0x01, // 11 ,45 ,0 ,1 + 0x42,0x61,0x63,0x6B,0x77,0x61,0x72,0x64,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x2D, // 2D + + // Backward_5 + 0x00,0x00,0x00,0xF1, // 0x000000F1 + 0x10,0x00,0x00,0x61, // 0x10000061 + 0x0B,0x2E,0x00,0x01, // 11 ,46 ,0 ,1 + 0x42,0x61,0x63,0x6B,0x77,0x61,0x72,0x64,0x20,0x35,0x00,0x00,0x00,0x00,0x00,0x00, + 0x2E, // 2E + + // Empty + 0x00,0x00,0x01,0x11, // 0x00000111 + 0x10,0x00,0x00,0x61, // 0x10000061 + 0x0B,0x41,0x00,0x01, // 11 ,65 ,0 ,1 + 0x45,0x6D,0x70,0x74,0x79,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x21, // 21 + + // Wait_2 + 0x00,0x00,0x02,0x11, // 0x00000211 + 0x10,0x00,0x00,0x61, // 0x10000061 + 0x0B,0x46,0x00,0x01, // 11 ,70 ,0 ,1 + 0x57,0x61,0x69,0x74,0x20,0x32,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x46, // 46 + + // Wait_5 + 0x00,0x00,0x03,0x11, // 0x00000311 + 0x10,0x00,0x00,0x61, // 0x10000061 + 0x0B,0x47,0x00,0x01, // 11 ,71 ,0 ,1 + 0x57,0x61,0x69,0x74,0x20,0x35,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x47, // 47 + + // Wait_10 + 0x00,0x00,0x04,0x11, // 0x00000411 + 0x10,0x00,0x00,0x61, // 0x10000061 + 0x0B,0x48,0x00,0x01, // 11 ,72 ,0 ,1 + 0x57,0x61,0x69,0x74,0x20,0x31,0x30,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x48, // 48 + + // Object + 0x00,0x00,0x05,0x11, // 0x00000511 + 0x10,0x00,0x00,0x61, // 0x10000061 + 0x0B,0x43,0x00,0x01, // 11 ,67 ,0 ,1 + 0x4F,0x62,0x6A,0x65,0x63,0x74,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x43, // 43 + + // Sound + 0x00,0x00,0x06,0x11, // 0x00000611 + 0x10,0x00,0x00,0x61, // 0x10000061 + 0x0B,0x44,0x00,0x01, // 11 ,68 ,0 ,1 + 0x53,0x6F,0x75,0x6E,0x64,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x44, // 44 + + // Light + 0x00,0x00,0x07,0x11, // 0x00000711 + 0x10,0x00,0x00,0x61, // 0x10000061 + 0x0B,0x42,0x00,0x01, // 11 ,66 ,0 ,1 + 0x4C,0x69,0x67,0x68,0x74,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x42, // 42 + + // Dark + 0x00,0x00,0x08,0x11, // 0x00000811 + 0x10,0x00,0x00,0x61, // 0x10000061 + 0x0B,0x49,0x00,0x01, // 11 ,73 ,0 ,1 + 0x44,0x61,0x72,0x6B,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x49, // 49 + + // Touch + 0x00,0x00,0x09,0x11, // 0x00000911 + 0x10,0x00,0x00,0x61, // 0x10000061 + 0x0B,0x45,0x00,0x01, // 11 ,69 ,0 ,1 + 0x54,0x6F,0x75,0x63,0x68,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x45, // 45 + + // Forward_5 + 0x00,0x00,0x11,0x11, // 0x00001111 + 0x10,0x00,0x00,0x61, // 0x10000061 + 0x0B,0x23,0x00,0x01, // 11 ,35 ,0 ,1 + 0x46,0x6F,0x72,0x77,0x61,0x72,0x64,0x20,0x35,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x23, // 23 + + // Forward + 0x00,0x00,0x21,0x11, // 0x00002111 + 0x10,0x00,0x00,0x61, // 0x10000061 + 0x0B,0x22,0x00,0x01, // 11 ,34 ,0 ,1 + 0x46,0x6F,0x72,0x77,0x61,0x72,0x64,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x22, // 22 + + // Turn_right_2 + 0x00,0x00,0x31,0x11, // 0x00003111 + 0x10,0x00,0x00,0x61, // 0x10000061 + 0x0B,0x29,0x00,0x01, // 11 ,41 ,0 ,1 + 0x54,0x75,0x72,0x6E,0x20,0x72,0x69,0x67,0x68,0x74,0x20,0x32,0x00,0x00,0x00,0x00, + 0x29, // 29 + + // Turn_right + 0x00,0x00,0x41,0x11, // 0x00004111 + 0x10,0x00,0x00,0x61, // 0x10000061 + 0x0B,0x28,0x00,0x01, // 11 ,40 ,0 ,1 + 0x54,0x75,0x72,0x6E,0x20,0x72,0x69,0x67,0x68,0x74,0x00,0x00,0x00,0x00,0x00,0x00, + 0x28, // 28 + + // Back_right_2 + 0x00,0x00,0x51,0x11, // 0x00005111 + 0x10,0x00,0x00,0x61, // 0x10000061 + 0x0B,0x2F,0x00,0x01, // 11 ,47 ,0 ,1 + 0x42,0x61,0x63,0x6B,0x20,0x72,0x69,0x67,0x68,0x74,0x20,0x32,0x00,0x00,0x00,0x00, + 0x2F, // 2F + + // Back_right + 0x00,0x00,0x61,0x11, // 0x00006111 + 0x10,0x00,0x00,0x61, // 0x10000061 + 0x0B,0x27,0x00,0x01, // 11 ,39 ,0 ,1 + 0x42,0x61,0x63,0x6B,0x20,0x72,0x69,0x67,0x68,0x74,0x00,0x00,0x00,0x00,0x00,0x00, + 0x27, // 27 + + // Tone_1 + 0x00,0x00,0x71,0x11, // 0x00007111 + 0x10,0x00,0x00,0x61, // 0x10000061 + 0x0B,0x2B,0x00,0x01, // 11 ,43 ,0 ,1 + 0x54,0x6F,0x6E,0x65,0x20,0x31,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x2B, // 2B + + // Tone_2 + 0x00,0x00,0x81,0x11, // 0x00008111 + 0x10,0x00,0x00,0x61, // 0x10000061 + 0x0B,0x2C,0x00,0x01, // 11 ,44 ,0 ,1 + 0x54,0x6F,0x6E,0x65,0x20,0x32,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x2C, // 2C + + // Back_left_2 + 0x00,0x00,0x91,0x11, // 0x00009111 + 0x10,0x00,0x00,0x61, // 0x10000061 + 0x0B,0x24,0x00,0x01, // 11 ,36 ,0 ,1 + 0x42,0x61,0x63,0x6B,0x20,0x6C,0x65,0x66,0x74,0x20,0x32,0x00,0x00,0x00,0x00,0x00, + 0x24, // 24 + + // Back_left + 0x00,0x00,0xA1,0x11, // 0x0000A111 + 0x10,0x00,0x00,0x61, // 0x10000061 + 0x0B,0x2A,0x00,0x01, // 11 ,42 ,0 ,1 + 0x42,0x61,0x63,0x6B,0x20,0x6C,0x65,0x66,0x74,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x2A, // 2A + + // Turn_left + 0x00,0x00,0xB1,0x11, // 0x0000B111 + 0x10,0x00,0x00,0x61, // 0x10000061 + 0x0B,0x25,0x00,0x01, // 11 ,37 ,0 ,1 + 0x54,0x75,0x72,0x6E,0x20,0x6C,0x65,0x66,0x74,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x25, // 25 + + // Turn_left_2 + 0x00,0x00,0xC1,0x11, // 0x0000C111 + 0x10,0x00,0x00,0x61, // 0x10000061 + 0x0B,0x26,0x00,0x01, // 11 ,38 ,0 ,1 + 0x54,0x75,0x72,0x6E,0x20,0x6C,0x65,0x66,0x74,0x20,0x32,0x00,0x00,0x00,0x00,0x00, + 0x26, // 26 + + // Empty + 0x00,0x00,0xD1,0x11, // 0x0000D111 + 0x10,0x00,0x00,0x61, // 0x10000061 + 0x0B,0x21,0x00,0x01, // 11 ,33 ,0 ,1 + 0x45,0x6D,0x70,0x74,0x79,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x21, // 21 + + // Backward + 0x00,0x00,0xE1,0x11, // 0x0000E111 + 0x10,0x00,0x00,0x61, // 0x10000061 + 0x0B,0x2D,0x00,0x01, // 11 ,45 ,0 ,1 + 0x42,0x61,0x63,0x6B,0x77,0x61,0x72,0x64,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x2D, // 2D + + // Backward_5 + 0x00,0x00,0xF1,0x11, // 0x0000F111 + 0x10,0x00,0x00,0x61, // 0x10000061 + 0x0B,0x2E,0x00,0x01, // 11 ,46 ,0 ,1 + 0x42,0x61,0x63,0x6B,0x77,0x61,0x72,0x64,0x20,0x35,0x00,0x00,0x00,0x00,0x00,0x00, + 0x2E, // 2E + + // Empty + 0x00,0x01,0x11,0x11, // 0x00011111 + 0x10,0x00,0x00,0x61, // 0x10000061 + 0x0B,0x41,0x00,0x01, // 11 ,65 ,0 ,1 + 0x45,0x6D,0x70,0x74,0x79,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x21, // 21 + + // Wait_2 + 0x00,0x02,0x11,0x11, // 0x00021111 + 0x10,0x00,0x00,0x61, // 0x10000061 + 0x0B,0x46,0x00,0x01, // 11 ,70 ,0 ,1 + 0x57,0x61,0x69,0x74,0x20,0x32,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x46, // 46 + + // Wait_5 + 0x00,0x03,0x11,0x11, // 0x00031111 + 0x10,0x00,0x00,0x61, // 0x10000061 + 0x0B,0x47,0x00,0x01, // 11 ,71 ,0 ,1 + 0x57,0x61,0x69,0x74,0x20,0x35,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x47, // 47 + + // Wait_10 + 0x00,0x04,0x11,0x11, // 0x00041111 + 0x10,0x00,0x00,0x61, // 0x10000061 + 0x0B,0x48,0x00,0x01, // 11 ,72 ,0 ,1 + 0x57,0x61,0x69,0x74,0x20,0x31,0x30,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x48, // 48 + + // Object + 0x00,0x05,0x11,0x11, // 0x00051111 + 0x10,0x00,0x00,0x61, // 0x10000061 + 0x0B,0x43,0x00,0x01, // 11 ,67 ,0 ,1 + 0x4F,0x62,0x6A,0x65,0x63,0x74,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x43, // 43 + + // Sound + 0x00,0x06,0x11,0x11, // 0x00061111 + 0x10,0x00,0x00,0x61, // 0x10000061 + 0x0B,0x44,0x00,0x01, // 11 ,68 ,0 ,1 + 0x53,0x6F,0x75,0x6E,0x64,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x44, // 44 + + // Light + 0x00,0x07,0x11,0x11, // 0x00071111 + 0x10,0x00,0x00,0x61, // 0x10000061 + 0x0B,0x42,0x00,0x01, // 11 ,66 ,0 ,1 + 0x4C,0x69,0x67,0x68,0x74,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x42, // 42 + + // Dark + 0x00,0x08,0x11,0x11, // 0x00081111 + 0x10,0x00,0x00,0x61, // 0x10000061 + 0x0B,0x49,0x00,0x01, // 11 ,73 ,0 ,1 + 0x44,0x61,0x72,0x6B,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x49, // 49 + + // Touch + 0x00,0x09,0x11,0x11, // 0x00091111 + 0x10,0x00,0x00,0x61, // 0x10000061 + 0x0B,0x45,0x00,0x01, // 11 ,69 ,0 ,1 + 0x54,0x6F,0x75,0x63,0x68,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x45, // 45 + + // Stop + 0x00,0x11,0x11,0x11, // 0x00111111 + 0x10,0x00,0x00,0x61, // 0x10000061 + 0x0B,0xFB,0x00,0x01, // 11 ,251,0 ,1 + 0x53,0x74,0x6F,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x4D, // 4D + + // Loop + 0x00,0x21,0x11,0x11, // 0x00211111 + 0x10,0x00,0x00,0x61, // 0x10000061 + 0x0B,0xFC,0x00,0x01, // 11 ,252,0 ,1 + 0x4C,0x6F,0x6F,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x4E, // 4E + + // Run + 0x01,0x11,0x11,0x11, // 0x01111111 + 0x00,0x00,0x00,0x60, // 0x00000060 + 0x0B,0xF8,0x00,0x00, // 11 ,248,0 ,0 + 0x52,0x75,0x6E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x32, // 32 + + // Main_menu + 0x02,0x11,0x11,0x11, // 0x02111111 + 0x00,0x00,0x20,0x60, // 0x00002060 + 0x00,0x00,0x00,0x00, // 0 ,0 ,0 ,0 + 0x4D,0x61,0x69,0x6E,0x20,0x6D,0x65,0x6E,0x75,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x37, // 37 + + // Save + 0x04,0x11,0x11,0x11, // 0x04111111 + 0x00,0x00,0x00,0x60, // 0x00000060 + 0x0B,0xFA,0x00,0x02, // 11 ,250,0 ,2 + 0x53,0x61,0x76,0x65,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x1D, // 1D + + // Yes + 0x14,0x11,0x11,0x11, // 0x14111111 + 0x00,0x00,0x20,0x20, // 0x00002020 + 0x0B,0xED,0x00,0x00, // 11 ,237,0 ,0 + 0x59,0x65,0x73,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x31, // 31 + + // No + 0x24,0x11,0x11,0x11, // 0x24111111 + 0x00,0x08,0x00,0x24, // 0x00080024 + 0x0B,0xF6,0x00,0x00, // 11 ,246,0 ,0 + 0x4E,0x6F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x30, // 30 +}; diff --git a/AT91SAM7S256/Source/Submenu03.rms b/AT91SAM7S256/Source/Submenu03.rms new file mode 100644 index 0000000..0dd4b6c --- /dev/null +++ b/AT91SAM7S256/Source/Submenu03.rms @@ -0,0 +1,324 @@ +const UBYTE SUBMENU03[] = +{ + 0x07,0x00, // Menu Format + 0x05,0x19, // Menu DataSize + 0x1D, // Menu item size + 0x2D, // Menu items + 0x18, // Menu icon Width + 0x18, // Menu icon Height + + // Sound_dB + 0x00,0x00,0x00,0x01, // 0x00000001 + 0x10,0x00,0x00,0x21, // 0x10000021 + 0x0A,0x02,0x00,0x01, // 10 ,2 ,0 ,1 + 0x53,0x6F,0x75,0x6E,0x64,0x20,0x64,0x42,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x02, // 02 + + // Sound_dBA + 0x00,0x00,0x00,0x02, // 0x00000002 + 0x10,0x00,0x00,0x21, // 0x10000021 + 0x0A,0x03,0x00,0x01, // 10 ,3 ,0 ,1 + 0x53,0x6F,0x75,0x6E,0x64,0x20,0x64,0x42,0x41,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x03, // 03 + + // Reflected_light + 0x00,0x00,0x00,0x03, // 0x00000003 + 0x10,0x00,0x00,0x21, // 0x10000021 + 0x0A,0x04,0x00,0x01, // 10 ,4 ,0 ,1 + 0x52,0x65,0x66,0x6C,0x65,0x63,0x74,0x65,0x64,0x20,0x6C,0x69,0x67,0x68,0x74,0x00, + 0x04, // 04 + + // Ambient_light + 0x00,0x00,0x00,0x04, // 0x00000004 + 0x10,0x00,0x00,0x21, // 0x10000021 + 0x0A,0x05,0x00,0x01, // 10 ,5 ,0 ,1 + 0x41,0x6D,0x62,0x69,0x65,0x6E,0x74,0x20,0x6C,0x69,0x67,0x68,0x74,0x00,0x00,0x00, + 0x05, // 05 + + // Light_sensor* + 0x00,0x00,0x00,0x05, // 0x00000005 + 0x10,0x00,0x00,0x21, // 0x10000021 + 0x0A,0x06,0x00,0x01, // 10 ,6 ,0 ,1 + 0x4C,0x69,0x67,0x68,0x74,0x20,0x73,0x65,0x6E,0x73,0x6F,0x72,0x2A,0x00,0x00,0x00, + 0x06, // 06 + + // Temperature_`C* + 0x00,0x00,0x00,0x06, // 0x00000006 + 0x10,0x00,0x00,0x21, // 0x10000021 + 0x0A,0x0D,0x00,0x01, // 10 ,13 ,0 ,1 + 0x54,0x65,0x6D,0x70,0x65,0x72,0x61,0x74,0x75,0x72,0x65,0x20,0x60,0x43,0x2A,0x00, + 0x0D, // 0D + + // Temperature_`F* + 0x00,0x00,0x00,0x07, // 0x00000007 + 0x10,0x00,0x00,0x21, // 0x10000021 + 0x0A,0x0E,0x00,0x01, // 10 ,14 ,0 ,1 + 0x54,0x65,0x6D,0x70,0x65,0x72,0x61,0x74,0x75,0x72,0x65,0x20,0x60,0x46,0x2A,0x00, + 0x0E, // 0E + + // Rotation* + 0x00,0x00,0x00,0x08, // 0x00000008 + 0x10,0x00,0x00,0x21, // 0x10000021 + 0x0A,0x0A,0x00,0x01, // 10 ,10 ,0 ,1 + 0x52,0x6F,0x74,0x61,0x74,0x69,0x6F,0x6E,0x2A,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x0A, // 0A + + // Motor_Rotations + 0x00,0x00,0x00,0x09, // 0x00000009 + 0x00,0x00,0x00,0x20, // 0x00000020 + 0x0A,0x09,0x00,0x01, // 10 ,9 ,0 ,1 + 0x4D,0x6F,0x74,0x6F,0x72,0x20,0x52,0x6F,0x74,0x61,0x74,0x69,0x6F,0x6E,0x73,0x00, + 0x09, // 09 + + // Motor_Degrees + 0x00,0x00,0x00,0x0A, // 0x0000000A + 0x00,0x00,0x00,0x20, // 0x00000020 + 0x0A,0x08,0x00,0x01, // 10 ,8 ,0 ,1 + 0x4D,0x6F,0x74,0x6F,0x72,0x20,0x44,0x65,0x67,0x72,0x65,0x65,0x73,0x00,0x00,0x00, + 0x08, // 08 + + // Touch + 0x00,0x00,0x00,0x0B, // 0x0000000B + 0x10,0x00,0x00,0x21, // 0x10000021 + 0x0A,0x07,0x00,0x01, // 10 ,7 ,0 ,1 + 0x54,0x6F,0x75,0x63,0x68,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x07, // 07 + + // UltraSonic_inch + 0x00,0x00,0x00,0x0C, // 0x0000000C + 0x10,0x00,0x00,0x21, // 0x10000021 + 0x0A,0x0B,0x00,0x01, // 10 ,11 ,0 ,1 + 0x55,0x6C,0x74,0x72,0x61,0x53,0x6F,0x6E,0x69,0x63,0x20,0x69,0x6E,0x63,0x68,0x00, + 0x0B, // 0B + + // UltraSonic_cm + 0x00,0x00,0x00,0x0D, // 0x0000000D + 0x10,0x00,0x00,0x21, // 0x10000021 + 0x0A,0x0C,0x00,0x01, // 10 ,12 ,0 ,1 + 0x55,0x6C,0x74,0x72,0x61,0x53,0x6F,0x6E,0x69,0x63,0x20,0x63,0x6D,0x00,0x00,0x00, + 0x0C, // 0C + + // Done + 0x00,0x00,0x00,0x0E, // 0x0000000E + 0x00,0x00,0x00,0x20, // 0x00000020 + 0x0A,0xEE,0x00,0x01, // 10 ,238,0 ,1 + 0x44,0x6F,0x6E,0x65,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x31, // 31 + + // Port_1 + 0x00,0x00,0x00,0x11, // 0x00000011 + 0x10,0x00,0x00,0x21, // 0x10000021 + 0x0A,0x12,0x00,0x01, // 10 ,18 ,0 ,1 + 0x50,0x6F,0x72,0x74,0x20,0x31,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x12, // 12 + + // Port_2 + 0x00,0x00,0x00,0x21, // 0x00000021 + 0x10,0x00,0x00,0x21, // 0x10000021 + 0x0A,0x13,0x00,0x01, // 10 ,19 ,0 ,1 + 0x50,0x6F,0x72,0x74,0x20,0x32,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x13, // 13 + + // Port_3 + 0x00,0x00,0x00,0x31, // 0x00000031 + 0x10,0x00,0x00,0x21, // 0x10000021 + 0x0A,0x14,0x00,0x01, // 10 ,20 ,0 ,1 + 0x50,0x6F,0x72,0x74,0x20,0x33,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x14, // 14 + + // Port_4 + 0x00,0x00,0x00,0x41, // 0x00000041 + 0x10,0x00,0x00,0x21, // 0x10000021 + 0x0A,0x15,0x00,0x01, // 10 ,21 ,0 ,1 + 0x50,0x6F,0x72,0x74,0x20,0x34,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x15, // 15 + + // Port_A + 0x00,0x00,0x00,0x19, // 0x00000019 + 0x10,0x00,0x00,0x21, // 0x10000021 + 0x0A,0x16,0x00,0x01, // 10 ,22 ,0 ,1 + 0x50,0x6F,0x72,0x74,0x20,0x41,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x16, // 16 + + // Port_B + 0x00,0x00,0x00,0x29, // 0x00000029 + 0x10,0x00,0x00,0x21, // 0x10000021 + 0x0A,0x17,0x00,0x01, // 10 ,23 ,0 ,1 + 0x50,0x6F,0x72,0x74,0x20,0x42,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x17, // 17 + + // Port_C + 0x00,0x00,0x00,0x39, // 0x00000039 + 0x10,0x00,0x00,0x21, // 0x10000021 + 0x0A,0x18,0x00,0x01, // 10 ,24 ,0 ,1 + 0x50,0x6F,0x72,0x74,0x20,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x18, // 18 + + // Port_A + 0x00,0x00,0x00,0x1A, // 0x0000001A + 0x10,0x00,0x00,0x21, // 0x10000021 + 0x0A,0x16,0x00,0x01, // 10 ,22 ,0 ,1 + 0x50,0x6F,0x72,0x74,0x20,0x41,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x16, // 16 + + // Port_B + 0x00,0x00,0x00,0x2A, // 0x0000002A + 0x10,0x00,0x00,0x21, // 0x10000021 + 0x0A,0x17,0x00,0x01, // 10 ,23 ,0 ,1 + 0x50,0x6F,0x72,0x74,0x20,0x42,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x17, // 17 + + // Port_C + 0x00,0x00,0x00,0x3A, // 0x0000003A + 0x10,0x00,0x00,0x21, // 0x10000021 + 0x0A,0x18,0x00,0x01, // 10 ,24 ,0 ,1 + 0x50,0x6F,0x72,0x74,0x20,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x17, // 17 + + // Logging_time + 0x00,0x00,0x00,0x1E, // 0x0000001E + 0x00,0x00,0x03,0xE0, // 0x000003E0 + 0x0C,0xEF,0x00,0x01, // 12 ,239,0 ,1 + 0x4C,0x6F,0x67,0x67,0x69,0x6E,0x67,0x20,0x74,0x69,0x6D,0x65,0x00,0x00,0x00,0x00, + 0x38, // 38 + + // _ + 0x00,0x00,0x00,0x2E, // 0x0000002E + 0x00,0x00,0x00,0x00, // 0x00000000 + 0x00,0x00,0x00,0x00, // 0 ,0 ,0 ,0 + 0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x35, // 35 + + // _ + 0x00,0x00,0x00,0x3E, // 0x0000003E + 0x00,0x00,0x00,0x00, // 0x00000000 + 0x00,0x00,0x00,0x00, // 0 ,0 ,0 ,0 + 0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x36, // 36 + + // Logging_Rate + 0x00,0x00,0x01,0x11, // 0x00000111 + 0x00,0x00,0x03,0x68, // 0x00000368 + 0x0C,0xEF,0x00,0x01, // 12 ,239,0 ,1 + 0x4C,0x6F,0x67,0x67,0x69,0x6E,0x67,0x20,0x52,0x61,0x74,0x65,0x00,0x00,0x00,0x00, + 0x38, // 38 + + // _ + 0x00,0x00,0x02,0x11, // 0x00000211 + 0x00,0x00,0x00,0x00, // 0x00000000 + 0x00,0x00,0x00,0x00, // 0 ,0 ,0 ,0 + 0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x35, // 35 + + // _ + 0x00,0x00,0x03,0x11, // 0x00000311 + 0x00,0x00,0x00,0x00, // 0x00000000 + 0x00,0x00,0x00,0x00, // 0 ,0 ,0 ,0 + 0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x36, // 36 + + // Logging_Rate + 0x00,0x00,0x01,0x19, // 0x00000119 + 0x00,0x00,0x03,0x68, // 0x00000368 + 0x0C,0xEF,0x00,0x01, // 12 ,239,0 ,1 + 0x4C,0x6F,0x67,0x67,0x69,0x6E,0x67,0x20,0x52,0x61,0x74,0x65,0x00,0x00,0x00,0x00, + 0x38, // 38 + + // _ + 0x00,0x00,0x02,0x19, // 0x00000219 + 0x00,0x00,0x00,0x00, // 0x00000000 + 0x00,0x00,0x00,0x00, // 0 ,0 ,0 ,0 + 0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x35, // 35 + + // _ + 0x00,0x00,0x03,0x19, // 0x00000319 + 0x00,0x00,0x00,0x00, // 0x00000000 + 0x00,0x00,0x00,0x00, // 0 ,0 ,0 ,0 + 0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x36, // 36 + + // Logging_Rate + 0x00,0x00,0x01,0x1A, // 0x0000011A + 0x00,0x00,0x03,0x68, // 0x00000368 + 0x0C,0xEF,0x00,0x01, // 12 ,239,0 ,1 + 0x4C,0x6F,0x67,0x67,0x69,0x6E,0x67,0x20,0x52,0x61,0x74,0x65,0x00,0x00,0x00,0x00, + 0x38, // 38 + + // _ + 0x00,0x00,0x02,0x1A, // 0x0000021A + 0x00,0x00,0x00,0x00, // 0x00000000 + 0x00,0x00,0x00,0x00, // 0 ,0 ,0 ,0 + 0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x35, // 35 + + // _ + 0x00,0x00,0x03,0x1A, // 0x0000031A + 0x00,0x00,0x00,0x00, // 0x00000000 + 0x00,0x00,0x00,0x00, // 0 ,0 ,0 ,0 + 0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x36, // 36 + + // _ + 0x00,0x00,0x01,0x1E, // 0x0000011E + 0x00,0x00,0x10,0x00, // 0x00001000 + 0x0A,0xF7,0x00,0x01, // 10 ,247,0 ,1 + 0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00, // 00 + + // _ + 0x00,0x00,0x11,0x11, // 0x00001111 + 0x0E,0x05,0x10,0x00, // 0x0E051000 + 0x0A,0xF2,0x00,0x00, // 10 ,242,0 ,0 + 0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00, // 00 + + // _ + 0x00,0x00,0x11,0x19, // 0x00001119 + 0x0E,0x05,0x10,0x00, // 0x0E051000 + 0x0A,0xF2,0x00,0x00, // 10 ,242,0 ,0 + 0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00, // 00 + + // _ + 0x00,0x00,0x11,0x1A, // 0x0000111A + 0x0E,0x05,0x10,0x00, // 0x0E051000 + 0x0A,0xF2,0x00,0x00, // 10 ,242,0 ,0 + 0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00, // 00 + + // Run + 0x00,0x00,0x11,0x1E, // 0x0000111E + 0x00,0x00,0x00,0x20, // 0x00000020 + 0x0A,0xF8,0x00,0x02, // 10 ,248,0 ,2 + 0x52,0x75,0x6E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x32, // 32 + + // Main_menu + 0x00,0x01,0x11,0x1E, // 0x0001111E + 0x00,0x02,0x20,0x00, // 0x00022000 + 0x0A,0xF1,0x00,0x00, // 10 ,241,0 ,0 + 0x4D,0x61,0x69,0x6E,0x20,0x6D,0x65,0x6E,0x75,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x37, // 37 + + // Save + 0x00,0x02,0x11,0x1E, // 0x0002111E + 0x00,0x02,0x00,0x00, // 0x00020000 + 0x0A,0xFA,0x00,0x02, // 10 ,250,0 ,2 + 0x53,0x61,0x76,0x65,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x1E, // 1E + + // Yes + 0x00,0x12,0x11,0x1E, // 0x0012111E + 0x00,0x00,0x20,0x20, // 0x00002020 + 0x0A,0xED,0x00,0x00, // 10 ,237,0 ,0 + 0x59,0x65,0x73,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x31, // 31 + + // No + 0x00,0x22,0x11,0x1E, // 0x0022111E + 0x00,0x08,0x00,0x24, // 0x00080024 + 0x00,0x00,0x00,0x00, // 0 ,0 ,0 ,0 + 0x4E,0x6F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x30, // 30 +}; diff --git a/AT91SAM7S256/Source/Submenu04.rms b/AT91SAM7S256/Source/Submenu04.rms new file mode 100644 index 0000000..0bfec3e --- /dev/null +++ b/AT91SAM7S256/Source/Submenu04.rms @@ -0,0 +1,170 @@ +const UBYTE SUBMENU04[] = +{ + 0x07,0x00, // Menu Format + 0x02,0x9B, // Menu DataSize + 0x1D, // Menu item size + 0x17, // Menu items + 0x18, // Menu icon Width + 0x18, // Menu icon Height + + // Sound_dB + 0x00,0x00,0x00,0x01, // 0x00000001 + 0x10,0x00,0x01,0x21, // 0x10000121 + 0x0E,0x02,0x00,0x01, // 14 ,2 ,0 ,1 + 0x53,0x6F,0x75,0x6E,0x64,0x20,0x64,0x42,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x02, // 02 + + // Sound_dBA + 0x00,0x00,0x00,0x02, // 0x00000002 + 0x10,0x00,0x00,0x21, // 0x10000021 + 0x0E,0x03,0x00,0x01, // 14 ,3 ,0 ,1 + 0x53,0x6F,0x75,0x6E,0x64,0x20,0x64,0x42,0x41,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x03, // 03 + + // Reflected_light + 0x00,0x00,0x00,0x03, // 0x00000003 + 0x10,0x00,0x00,0x21, // 0x10000021 + 0x0E,0x04,0x00,0x01, // 14 ,4 ,0 ,1 + 0x52,0x65,0x66,0x6C,0x65,0x63,0x74,0x65,0x64,0x20,0x6C,0x69,0x67,0x68,0x74,0x00, + 0x04, // 04 + + // Ambient_light + 0x00,0x00,0x00,0x04, // 0x00000004 + 0x10,0x00,0x00,0x21, // 0x10000021 + 0x0E,0x05,0x00,0x01, // 14 ,5 ,0 ,1 + 0x41,0x6D,0x62,0x69,0x65,0x6E,0x74,0x20,0x6C,0x69,0x67,0x68,0x74,0x00,0x00,0x00, + 0x05, // 05 + + // Light_Sensor* + 0x00,0x00,0x00,0x05, // 0x00000005 + 0x10,0x00,0x00,0x21, // 0x10000021 + 0x0E,0x06,0x00,0x01, // 14 ,6 ,0 ,1 + 0x4C,0x69,0x67,0x68,0x74,0x20,0x53,0x65,0x6E,0x73,0x6F,0x72,0x2A,0x00,0x00,0x00, + 0x06, // 06 + + // Temperature_`C* + 0x00,0x00,0x00,0x06, // 0x00000006 + 0x10,0x00,0x00,0x21, // 0x10000021 + 0x0E,0x0D,0x00,0x01, // 14 ,13 ,0 ,1 + 0x54,0x65,0x6D,0x70,0x65,0x72,0x61,0x74,0x75,0x72,0x65,0x20,0x60,0x43,0x2A,0x00, + 0x0D, // 0D + + // Temperature_`F* + 0x00,0x00,0x00,0x07, // 0x00000007 + 0x10,0x00,0x00,0x21, // 0x10000021 + 0x0E,0x0E,0x00,0x01, // 14 ,14 ,0 ,1 + 0x54,0x65,0x6D,0x70,0x65,0x72,0x61,0x74,0x75,0x72,0x65,0x20,0x60,0x46,0x2A,0x00, + 0x0E, // 0E + + // Rotation* + 0x00,0x00,0x00,0x08, // 0x00000008 + 0x10,0x00,0x00,0x21, // 0x10000021 + 0x0E,0x0A,0x00,0x01, // 14 ,10 ,0 ,1 + 0x52,0x6F,0x74,0x61,0x74,0x69,0x6F,0x6E,0x2A,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x0A, // 0A + + // Motor_rotations + 0x00,0x00,0x00,0x09, // 0x00000009 + 0x00,0x00,0x00,0x20, // 0x00000020 + 0x0E,0x09,0x00,0x01, // 14 ,9 ,0 ,1 + 0x4D,0x6F,0x74,0x6F,0x72,0x20,0x72,0x6F,0x74,0x61,0x74,0x69,0x6F,0x6E,0x73,0x00, + 0x09, // 09 + + // Motor_degrees + 0x00,0x00,0x00,0x0A, // 0x0000000A + 0x00,0x00,0x00,0x20, // 0x00000020 + 0x0E,0x08,0x00,0x01, // 14 ,8 ,0 ,1 + 0x4D,0x6F,0x74,0x6F,0x72,0x20,0x64,0x65,0x67,0x72,0x65,0x65,0x73,0x00,0x00,0x00, + 0x08, // 08 + + // Touch + 0x00,0x00,0x00,0x0B, // 0x0000000B + 0x10,0x00,0x00,0x21, // 0x10000021 + 0x0E,0x07,0x00,0x01, // 14 ,7 ,0 ,1 + 0x54,0x6F,0x75,0x63,0x68,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x07, // 07 + + // Ultrasonic_inch + 0x00,0x00,0x00,0x0C, // 0x0000000C + 0x10,0x00,0x00,0x21, // 0x10000021 + 0x0E,0x0B,0x00,0x01, // 14 ,11 ,0 ,1 + 0x55,0x6C,0x74,0x72,0x61,0x73,0x6F,0x6E,0x69,0x63,0x20,0x69,0x6E,0x63,0x68,0x00, + 0x0B, // 0B + + // Ultrasonic_cm + 0x00,0x00,0x00,0x0D, // 0x0000000D + 0x10,0x00,0x00,0x21, // 0x10000021 + 0x0E,0x0C,0x00,0x01, // 14 ,12 ,0 ,1 + 0x55,0x6C,0x74,0x72,0x61,0x73,0x6F,0x6E,0x69,0x63,0x20,0x63,0x6D,0x00,0x00,0x00, + 0x0C, // 0C + + // Port_1 + 0x00,0x00,0x00,0x11, // 0x00000011 + 0x00,0x00,0x00,0x20, // 0x00000020 + 0x0E,0x12,0x00,0x00, // 14 ,18 ,0 ,0 + 0x50,0x6F,0x72,0x74,0x20,0x31,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x12, // 12 + + // Port_2 + 0x00,0x00,0x00,0x21, // 0x00000021 + 0x00,0x00,0x00,0x20, // 0x00000020 + 0x0E,0x13,0x00,0x00, // 14 ,19 ,0 ,0 + 0x50,0x6F,0x72,0x74,0x20,0x32,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x13, // 13 + + // Port_3 + 0x00,0x00,0x00,0x31, // 0x00000031 + 0x00,0x00,0x00,0x20, // 0x00000020 + 0x0E,0x14,0x00,0x00, // 14 ,20 ,0 ,0 + 0x50,0x6F,0x72,0x74,0x20,0x33,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x14, // 14 + + // Port_4 + 0x00,0x00,0x00,0x41, // 0x00000041 + 0x00,0x00,0x00,0x20, // 0x00000020 + 0x0E,0x15,0x00,0x00, // 14 ,21 ,0 ,0 + 0x50,0x6F,0x72,0x74,0x20,0x34,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x15, // 15 + + // Port_A + 0x00,0x00,0x00,0x19, // 0x00000019 + 0x00,0x00,0x00,0x20, // 0x00000020 + 0x0E,0x16,0x00,0x00, // 14 ,22 ,0 ,0 + 0x50,0x6F,0x72,0x74,0x20,0x41,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x16, // 16 + + // Port_B + 0x00,0x00,0x00,0x29, // 0x00000029 + 0x00,0x00,0x00,0x20, // 0x00000020 + 0x0E,0x17,0x00,0x00, // 14 ,23 ,0 ,0 + 0x50,0x6F,0x72,0x74,0x20,0x42,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x17, // 17 + + // Port_C + 0x00,0x00,0x00,0x39, // 0x00000039 + 0x00,0x00,0x00,0x20, // 0x00000020 + 0x0E,0x18,0x00,0x00, // 14 ,24 ,0 ,0 + 0x50,0x6F,0x72,0x74,0x20,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x18, // 18 + + // Port_A + 0x00,0x00,0x00,0x1A, // 0x0000001A + 0x00,0x00,0x00,0x20, // 0x00000020 + 0x0E,0x16,0x00,0x00, // 14 ,22 ,0 ,0 + 0x50,0x6F,0x72,0x74,0x20,0x41,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x16, // 16 + + // Port_B + 0x00,0x00,0x00,0x2A, // 0x0000002A + 0x00,0x00,0x00,0x20, // 0x00000020 + 0x0E,0x17,0x00,0x00, // 14 ,23 ,0 ,0 + 0x50,0x6F,0x72,0x74,0x20,0x42,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x17, // 17 + + // Port_C + 0x00,0x00,0x00,0x3A, // 0x0000003A + 0x00,0x00,0x00,0x20, // 0x00000020 + 0x0E,0x18,0x00,0x00, // 14 ,24 ,0 ,0 + 0x50,0x6F,0x72,0x74,0x20,0x43,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x18, // 18 +}; diff --git a/AT91SAM7S256/Source/Submenu05.rms b/AT91SAM7S256/Source/Submenu05.rms new file mode 100644 index 0000000..5e03396 --- /dev/null +++ b/AT91SAM7S256/Source/Submenu05.rms @@ -0,0 +1,128 @@ +const UBYTE SUBMENU05[] = +{ + 0x07,0x00, // Menu Format + 0x01,0xED, // Menu DataSize + 0x1D, // Menu item size + 0x11, // Menu items + 0x18, // Menu icon Width + 0x18, // Menu icon Height + + // Volume + 0x00,0x00,0x00,0x01, // 0x00000001 + 0x00,0x00,0x80,0x00, // 0x00008000 + 0x00,0x00,0x00,0x01, // 0 ,0 ,0 ,1 + 0x56,0x6F,0x6C,0x75,0x6D,0x65,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x39, // 39 + + // Sleep + 0x00,0x00,0x00,0x02, // 0x00000002 + 0x00,0x00,0x80,0x00, // 0x00008000 + 0x00,0x00,0x00,0x01, // 0 ,0 ,0 ,1 + 0x53,0x6C,0x65,0x65,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x3A, // 3A + + // NXT_Version + 0x00,0x00,0x00,0x03, // 0x00000003 + 0x00,0x00,0x00,0x00, // 0x00000000 + 0x01,0x00,0x00,0x00, // 1 ,0 ,0 ,0 + 0x4E,0x58,0x54,0x20,0x56,0x65,0x72,0x73,0x69,0x6F,0x6E,0x00,0x00,0x00,0x00,0x00, + 0x4F, // 4F + + // Delete_files + 0x00,0x00,0x00,0x04, // 0x00000004 + 0x00,0x00,0x80,0x00, // 0x00008000 + 0x00,0x00,0x00,0x01, // 0 ,0 ,0 ,1 + 0x44,0x65,0x6C,0x65,0x74,0x65,0x20,0x66,0x69,0x6C,0x65,0x73,0x00,0x00,0x00,0x00, + 0x34, // 34 + + // _ + 0x00,0x00,0x00,0x11, // 0x00000011 + 0x00,0x00,0x03,0x60, // 0x00000360 + 0x07,0xEF,0x00,0x00, // 7 ,239,0 ,0 + 0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x39, // 39 + + // _ + 0x00,0x00,0x00,0x21, // 0x00000021 + 0x00,0x00,0x00,0x00, // 0x00000000 + 0x00,0x00,0x00,0x00, // 0 ,0 ,0 ,0 + 0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x35, // 35 + + // _ + 0x00,0x00,0x00,0x31, // 0x00000031 + 0x00,0x00,0x00,0x00, // 0x00000000 + 0x00,0x00,0x00,0x00, // 0 ,0 ,0 ,0 + 0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x36, // 36 + + // _ + 0x00,0x00,0x00,0x12, // 0x00000012 + 0x00,0x00,0x03,0x20, // 0x00000320 + 0x04,0xEF,0x00,0x00, // 4 ,239,0 ,0 + 0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x3A, // 3A + + // _ + 0x00,0x00,0x00,0x22, // 0x00000022 + 0x00,0x00,0x00,0x00, // 0x00000000 + 0x00,0x00,0x00,0x00, // 0 ,0 ,0 ,0 + 0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x35, // 35 + + // _ + 0x00,0x00,0x00,0x32, // 0x00000032 + 0x00,0x00,0x00,0x00, // 0x00000000 + 0x00,0x00,0x00,0x00, // 0 ,0 ,0 ,0 + 0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x36, // 36 + + // Software_files + 0x00,0x00,0x00,0x14, // 0x00000014 + 0x10,0x00,0x00,0x01, // 0x10000001 + 0x05,0x02,0x00,0x02, // 5 ,2 ,0 ,2 + 0x53,0x6F,0x66,0x74,0x77,0x61,0x72,0x65,0x20,0x66,0x69,0x6C,0x65,0x73,0x00,0x00, + 0x1C, // 1C + + // NXT_files + 0x00,0x00,0x00,0x24, // 0x00000024 + 0x10,0x00,0x00,0x01, // 0x10000001 + 0x05,0x03,0x00,0x02, // 5 ,3 ,0 ,2 + 0x4E,0x58,0x54,0x20,0x66,0x69,0x6C,0x65,0x73,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x1D, // 1D + + // Sound_files + 0x00,0x00,0x00,0x34, // 0x00000034 + 0x10,0x00,0x00,0x01, // 0x10000001 + 0x05,0x01,0x00,0x02, // 5 ,1 ,0 ,2 + 0x53,0x6F,0x75,0x6E,0x64,0x20,0x66,0x69,0x6C,0x65,0x73,0x00,0x00,0x00,0x00,0x00, + 0x1B, // 1B + + // Datalog_files + 0x00,0x00,0x00,0x44, // 0x00000044 + 0x10,0x80,0x00,0x01, // 0x10800001 + 0x05,0x05,0x00,0x02, // 5 ,5 ,0 ,2 + 0x44,0x61,0x74,0x61,0x6C,0x6F,0x67,0x20,0x66,0x69,0x6C,0x65,0x73,0x00,0x00,0x00, + 0x1F, // 1F + + // Try_me_files + 0x00,0x00,0x00,0x54, // 0x00000054 + 0x10,0x00,0x00,0x01, // 0x10000001 + 0x05,0x04,0x00,0x02, // 5 ,4 ,0 ,2 + 0x54,0x72,0x79,0x20,0x6D,0x65,0x20,0x66,0x69,0x6C,0x65,0x73,0x00,0x00,0x00,0x00, + 0x1E, // 1E + + // Are_you_sure? + 0x00,0x00,0x01,0x14, // 0x00000114 + 0x00,0x00,0x01,0x08, // 0x00000108 + 0x05,0xF1,0x00,0x00, // 5 ,241,0 ,0 + 0x41,0x72,0x65,0x20,0x79,0x6F,0x75,0x20,0x73,0x75,0x72,0x65,0x3F,0x00,0x00,0x00, + 0x31, // 31 + + // Are_you_sure? + 0x00,0x00,0x02,0x14, // 0x00000214 + 0x00,0x00,0x01,0x04, // 0x00000104 + 0x05,0x00,0x00,0x00, // 5 ,0 ,0 ,0 + 0x41,0x72,0x65,0x20,0x79,0x6F,0x75,0x20,0x73,0x75,0x72,0x65,0x3F,0x00,0x00,0x00, + 0x30, // 30 +}; diff --git a/AT91SAM7S256/Source/Submenu06.rms b/AT91SAM7S256/Source/Submenu06.rms new file mode 100644 index 0000000..5cd1b06 --- /dev/null +++ b/AT91SAM7S256/Source/Submenu06.rms @@ -0,0 +1,51 @@ +const UBYTE SUBMENU06[] = +{ + 0x07,0x00, // Menu Format + 0x00,0xAE, // Menu DataSize + 0x1D, // Menu item size + 0x06, // Menu items + 0x18, // Menu icon Width + 0x18, // Menu icon Height + + // _ + 0x00,0x00,0x00,0x01, // 0x00000001 + 0x00,0x00,0x10,0x00, // 0x00001000 + 0x06,0x04,0x00,0x01, // 6 ,4 ,0 ,1 + 0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x1E, // 1E + + // _ + 0x00,0x00,0x00,0x11, // 0x00000011 + 0x00,0x00,0x03,0x80, // 0x00000380 + 0x06,0xF2,0x00,0x02, // 6 ,242,0 ,2 + 0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x1E, // 1E + + // Delete + 0x00,0x00,0x01,0x11, // 0x00000111 + 0x00,0x00,0x00,0x00, // 0x00000000 + 0x00,0x00,0x00,0x02, // 0 ,0 ,0 ,2 + 0x44,0x65,0x6C,0x65,0x74,0x65,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x34, // 34 + + // Run + 0x00,0x00,0x02,0x11, // 0x00000211 + 0x00,0x00,0x01,0x20, // 0x00000120 + 0x08,0xF8,0x00,0x00, // 8 ,248,0 ,0 + 0x52,0x75,0x6E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x32, // 32 + + // Are_you_sure? + 0x00,0x00,0x11,0x11, // 0x00001111 + 0x00,0x00,0x00,0x08, // 0x00000008 + 0x09,0x00,0x00,0x00, // 9 ,0 ,0 ,0 + 0x41,0x72,0x65,0x20,0x79,0x6F,0x75,0x20,0x73,0x75,0x72,0x65,0x3F,0x00,0x00,0x00, + 0x31, // 31 + + // Are_you_sure? + 0x00,0x00,0x21,0x11, // 0x00002111 + 0x00,0x00,0x00,0x04, // 0x00000004 + 0x00,0x00,0x00,0x00, // 0 ,0 ,0 ,0 + 0x41,0x72,0x65,0x20,0x79,0x6F,0x75,0x20,0x73,0x75,0x72,0x65,0x3F,0x00,0x00,0x00, + 0x30, // 30 +}; diff --git a/AT91SAM7S256/Source/Submenu07.rms b/AT91SAM7S256/Source/Submenu07.rms new file mode 100644 index 0000000..43c292e --- /dev/null +++ b/AT91SAM7S256/Source/Submenu07.rms @@ -0,0 +1,142 @@ +const UBYTE SUBMENU07[] = +{ + 0x07,0x00, // Menu Format + 0x02,0x27, // Menu DataSize + 0x1D, // Menu item size + 0x13, // Menu items + 0x18, // Menu icon Width + 0x18, // Menu icon Height + + // Search + 0x00,0x00,0x00,0x01, // 0x00000001 + 0x00,0x40,0x80,0x00, // 0x00408000 + 0x00,0x00,0x00,0x01, // 0 ,0 ,0 ,1 + 0x53,0x65,0x61,0x72,0x63,0x68,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x56, // 56 + + // My_contacts + 0x00,0x00,0x00,0x02, // 0x00000002 + 0x00,0x40,0x80,0x00, // 0x00408000 + 0x00,0x00,0x00,0x01, // 0 ,0 ,0 ,1 + 0x4D,0x79,0x20,0x63,0x6F,0x6E,0x74,0x61,0x63,0x74,0x73,0x00,0x00,0x00,0x00,0x00, + 0x52, // 52 + + // Connections + 0x00,0x00,0x00,0x03, // 0x00000003 + 0x00,0x40,0x80,0x00, // 0x00408000 + 0x00,0x00,0x00,0x01, // 0 ,0 ,0 ,1 + 0x43,0x6F,0x6E,0x6E,0x65,0x63,0x74,0x69,0x6F,0x6E,0x73,0x00,0x00,0x00,0x00,0x00, + 0x53, // 53 + + // Visibility + 0x00,0x00,0x00,0x04, // 0x00000004 + 0x00,0x40,0x80,0x00, // 0x00408000 + 0x00,0x00,0x00,0x01, // 0 ,0 ,0 ,1 + 0x56,0x69,0x73,0x69,0x62,0x69,0x6C,0x69,0x74,0x79,0x00,0x00,0x00,0x00,0x00,0x00, + 0x54, // 54 + + // On/Off + 0x00,0x00,0x00,0x05, // 0x00000005 + 0x00,0x00,0x80,0x00, // 0x00008000 + 0x00,0x00,0x00,0x01, // 0 ,0 ,0 ,1 + 0x4F,0x6E,0x2F,0x4F,0x66,0x66,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x55, // 55 + + // _ + 0x00,0x00,0x00,0x11, // 0x00000011 + 0x00,0x00,0x03,0x00, // 0x00000300 + 0x12,0xFF,0x00,0x01, // 18 ,255,0 ,1 + 0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x57, // 57 + + // _ + 0x00,0x00,0x00,0x12, // 0x00000012 + 0x00,0x00,0x10,0x00, // 0x00001000 + 0x00,0x00,0x00,0x01, // 0 ,0 ,0 ,1 + 0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x57, // 57 + + // _ + 0x00,0x00,0x00,0x13, // 0x00000013 + 0x00,0x00,0x03,0x00, // 0x00000300 + 0x14,0xF6,0x00,0x01, // 20 ,246,0 ,1 + 0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x57, // 57 + + // Visible + 0x00,0x00,0x00,0x14, // 0x00000014 + 0x00,0x00,0x00,0x00, // 0x00000000 + 0x11,0xEB,0x00,0x00, // 17 ,235,0 ,0 + 0x56,0x69,0x73,0x69,0x62,0x6C,0x65,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x5A, // 5A + + // Invisible + 0x00,0x00,0x00,0x24, // 0x00000024 + 0x00,0x00,0x00,0x00, // 0x00000000 + 0x11,0xEA,0x00,0x00, // 17 ,234,0 ,0 + 0x49,0x6E,0x76,0x69,0x73,0x69,0x62,0x6C,0x65,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x5B, // 5B + + // On + 0x00,0x00,0x00,0x15, // 0x00000015 + 0x00,0x00,0x00,0x80, // 0x00000080 + 0x03,0xEB,0x00,0x00, // 3 ,235,0 ,0 + 0x4F,0x6E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x5C, // 5C + + // Off + 0x00,0x00,0x00,0x25, // 0x00000025 + 0x00,0x40,0x00,0x80, // 0x00400080 + 0x03,0xEA,0x00,0x00, // 3 ,234,0 ,0 + 0x4F,0x66,0x66,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x5D, // 5D + + // _ + 0x00,0x00,0x01,0x11, // 0x00000111 + 0x00,0x00,0x03,0x08, // 0x00000308 + 0x13,0xF2,0x00,0x01, // 19 ,242,0 ,1 + 0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x57, // 57 + + // _ + 0x00,0x00,0x01,0x12, // 0x00000112 + 0x00,0x10,0x02,0x08, // 0x00100208 + 0x13,0xF2,0x00,0x02, // 19 ,242,0 ,2 + 0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x57, // 57 + + // Disconnect + 0x00,0x00,0x01,0x13, // 0x00000113 + 0x00,0x00,0x00,0x00, // 0x00000000 + 0x14,0xF0,0x00,0x00, // 20 ,240,0 ,0 + 0x44,0x69,0x73,0x63,0x6F,0x6E,0x6E,0x65,0x63,0x74,0x00,0x00,0x00,0x00,0x00,0x00, + 0x59, // 59 + + // _ + 0x00,0x00,0x11,0x11, // 0x00001111 + 0x00,0x00,0x03,0x00, // 0x00000300 + 0x10,0xF5,0x00,0x00, // 16 ,245,0 ,0 + 0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x57, // 57 + + // Delete + 0x00,0x00,0x11,0x12, // 0x00001112 + 0x00,0x00,0x00,0x00, // 0x00000000 + 0x13,0xF1,0x00,0x00, // 19 ,241,0 ,0 + 0x44,0x65,0x6C,0x65,0x74,0x65,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x34, // 34 + + // Connect + 0x00,0x00,0x21,0x12, // 0x00002112 + 0x00,0x00,0x00,0x00, // 0x00000000 + 0x00,0x00,0x00,0x01, // 0 ,0 ,0 ,1 + 0x43,0x6F,0x6E,0x6E,0x65,0x63,0x74,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x58, // 58 + + // _ + 0x00,0x01,0x21,0x12, // 0x00012112 + 0x00,0x00,0x03,0x08, // 0x00000308 + 0x10,0xF5,0x00,0x00, // 16 ,245,0 ,0 + 0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x57, // 57 +}; diff --git a/AT91SAM7S256/Source/Test1.txt b/AT91SAM7S256/Source/Test1.txt new file mode 100644 index 0000000..9c1d663 --- /dev/null +++ b/AT91SAM7S256/Source/Test1.txt @@ -0,0 +1,17 @@ +const BMPMAP Test1[] = +{ + 0x02,0x00, // Graphics Format + 0x04,0x00, // Graphics DataSize + 0x00, // Graphics Start X + 0x00, // Graphics Start Y + 0x80, // Graphics Width + 0x40, // Graphics Height + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF +}; diff --git a/AT91SAM7S256/Source/Test2.txt b/AT91SAM7S256/Source/Test2.txt new file mode 100644 index 0000000..2419c27 --- /dev/null +++ b/AT91SAM7S256/Source/Test2.txt @@ -0,0 +1,17 @@ +const BMPMAP Test2[] = +{ + 0x02,0x00, // Graphics Format + 0x04,0x00, // Graphics DataSize + 0x00, // Graphics Start X + 0x00, // Graphics Start Y + 0x80, // Graphics Width + 0x40, // Graphics Height + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 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0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 +}; diff --git a/AT91SAM7S256/Source/Ui.txt b/AT91SAM7S256/Source/Ui.txt new file mode 100644 index 0000000..e3f736d --- /dev/null +++ b/AT91SAM7S256/Source/Ui.txt @@ -0,0 +1,60 @@ +const TXT Ui[] = +{ + 0x05,0x00, // Text Format + 0x03,0x63, // Text DataSize + 0x01, // ItemsX + 0x33, // ItemsY + 0x11, // ItemCharsX + 0x01, // ItemCharsY + 'C','o','n','n','e','c','t','i','n','g', 0 , 0 , 0 , 0 , 0 , 0 , 0 , + 'L','i','n','e',' ','i','s',' ','b','u','s','y', 0 , 0 , 0 , 0 , 0 , + 'F','a','i','l','e','d','!', 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , + 'C','o','n','n','e','c','t','i','o','n','?', 0 , 0 , 0 , 0 , 0 , 0 , + 'S','e','n','d','i','n','g',' ','f','i','l','e', 0 , 0 , 0 , 0 , 0 , + 'F','a','i','l','e','d','!', 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , + 'T','u','r','n','i','n','g',' ','o','n', 0 , 0 , 0 , 0 , 0 , 0 , 0 , + 'F','a','i','l','e','d','!', 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , + 'T','u','r','n','i','n','g',' ','o','f','f', 0 , 0 , 0 , 0 , 0 , 0 , + 'F','a','i','l','e','d','!', 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , + 'S','e','a','r','c','h','i','n','g', 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , + 'A','b','o','r','t','e','d','!', 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , + 'F','a','i','l','e','d','!', 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , + 'F','a','i','l','e','d','!', 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , + 'F','a','i','l','e','d','!', 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , + 'M','e','m','o','r','y',' ','f','u','l','l','!', 0 , 0 , 0 , 0 , 0 , + 'F','i','l','e',' ','s','a','v','e','d', 0 , 0 , 0 , 0 , 0 , 0 , 0 , + 'F','i','l','e',' ','e','x','i','s','t','s', 0 , 0 , 0 , 0 , 0 , 0 , + 'o','v','e','r','w','r','i','t','e','!', 0 , 0 , 0 , 0 , 0 , 0 , 0 , + 'F','i','l','e',' ','d','e','l','e','t','e','d', 0 , 0 , 0 , 0 , 0 , + 'F','i','l','e','s', 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , + 'd','e','l','e','t','e','d', 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , + 'R','u','n','n','i','n','g', 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , + 'A','b','o','r','t','e','d','!', 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , + 'D','o','n','e', 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , + 'F','i','l','e',' ','e','r','r','o','r','!', 0 , 0 , 0 , 0 , 0 , 0 , + 'D','e','l','e','t','i','n','g',' ','a','l','l', 0 , 0 , 0 , 0 , 0 , + '%','s',' ','f','i','l','e','s','!', 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , + 'S','o','u','n','d', 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , + 'S','o','f','t','w','a','r','e', 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , + 'N','X','T', 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , + 'T','r','y',' ','M','e', 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , + 'D','a','t','a','l','o','g', 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , + 'P','a','s','s','k','e','y',':', 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , + 'F','i','l','e',' ','n','a','m','e',':', 0 , 0 , 0 , 0 , 0 , 0 , 0 , + 'P','l','e','a','s','e',' ','u','s','e',' ','p','o','r','t',':', 0 , + '1',' ','-',' ','T','o','u','c','h',' ','S','e','n','s','o','r', 0 , + '2',' ','-',' ','S','o','u','n','d',' ','S','e','n','s','o','r', 0 , + '3',' ','-',' ','L','i','g','h','t',' ','S','e','n','s','o','r', 0 , + '4',' ','-',' ','U','l','t','r','a','s','o','n','i','c',' ',' ', 0 , + 'B','/','C',' ','-',' ','L','/','R',' ','m','o','t','o','r','s', 0 , + 'S','e','l','e','c','t', 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , + 'S','e','l','e','c','t', 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , + 'S','e','l','e','c','t', 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , + 'B','T',' ','s','a','v','e',' ','d','a','t','a', 0 , 0 , 0 , 0 , 0 , + 'e','r','r','o','r','!', 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , + 'B','T',' ','s','t','o','r','e',' ','i','s', 0 , 0 , 0 , 0 , 0 , 0 , + 'f','u','l','l',' ','e','r','r','o','r','!', 0 , 0 , 0 , 0 , 0 , 0 , + 'B','T',' ','u','n','k','n','o','w','n', 0 , 0 , 0 , 0 , 0 , 0 , 0 , + 'a','d','d','r','.',' ','e','r','r','o','r','!', 0 , 0 , 0 , 0 , 0 , + 'N','e','v','e','r', 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 +}; diff --git a/AT91SAM7S256/Source/Wait.txt b/AT91SAM7S256/Source/Wait.txt new file mode 100644 index 0000000..a29d06b --- /dev/null +++ b/AT91SAM7S256/Source/Wait.txt @@ -0,0 +1,12 @@ +const BMPMAP Wait[] = +{ + 0x02,0x00, // Graphics Format + 0x00,0x48, // Graphics DataSize + 0x00, // Graphics Start X + 0x08, // Graphics Start Y + 0x18, // Graphics Width + 0x18, // Graphics Height + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xC0,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xC3,0x24,0x98,0xC2,0x98,0x24,0xC3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 +}; diff --git a/AT91SAM7S256/Source/c_button.c b/AT91SAM7S256/Source/c_button.c new file mode 100644 index 0000000..d702dd1 --- /dev/null +++ b/AT91SAM7S256/Source/c_button.c @@ -0,0 +1,134 @@ +// +// Date init 14.12.2004 +// +// Revision date $Date:: 16-05-06 9:58 $ +// +// Filename $Workfile:: c_button.c $ +// +// Version $Revision:: 16 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/c_button.c $ +// +// Platform C +// + +#include "stdconst.h" +#include "modules.h" +#include "c_button.h" +#include "c_button.iom" +#include "c_button.h" +#include "d_button.h" + +#define BTN_PRESCALER 2 + +enum +{ + LONG_TIME = (2000/BTN_PRESCALER) +}; + +static IOMAPBUTTON IOMapButton; +static VARSBUTTON VarsButton; +static UBYTE BtnCnt; + +const HEADER cButton = +{ + 0x00040001L, + "Button", + cButtonInit, + cButtonCtrl, + cButtonExit, + (void *)&IOMapButton, + (void *)&VarsButton, + (UWORD)sizeof(IOMapButton), + (UWORD)sizeof(VarsButton), + 0x0000 //Code size - not used so far +}; + + +void cButtonInit(void* pHeader) +{ + UBYTE Tmp; + + for (Tmp = 0; Tmp < NO_OF_BTNS; Tmp++) + { + IOMapButton.State[Tmp] = 0; + IOMapButton.BtnCnt[Tmp].PressedCnt = 0; + IOMapButton.BtnCnt[Tmp].LongPressCnt = 0; + IOMapButton.BtnCnt[Tmp].ShortRelCnt = 0; + IOMapButton.BtnCnt[Tmp].LongRelCnt = 0; + VarsButton.Cnt[Tmp] = 0; + } + VarsButton.OldState = 0; + BtnCnt = 0; + dButtonInit(BTN_PRESCALER); +} + +void cButtonCtrl(void) +{ + UBYTE ButtonState, Tmp, ButtonNo; + + for (Tmp = 0; Tmp < NO_OF_BTNS; Tmp++) + { + IOMapButton.State[Tmp] &= ~PRESSED_EV; + } + if (++BtnCnt >= BTN_PRESCALER) + { + BtnCnt = 0; + dButtonRead(&ButtonState); + + ButtonNo = 0x01; + for (Tmp = 0; Tmp < NO_OF_BTNS; Tmp++) + { + if (ButtonState & ButtonNo) + { + if (LONG_TIME >= (VarsButton.Cnt[Tmp])) + { + (VarsButton.Cnt[Tmp])++; + } + IOMapButton.State[Tmp] = PRESSED_STATE; + if (!((VarsButton.OldState) & ButtonNo)) + { + + /* Button just pressed */ + (IOMapButton.State[Tmp]) |= PRESSED_EV; + (IOMapButton.BtnCnt[Tmp].PressedCnt)++; + VarsButton.Cnt[Tmp] = 0; + } + else + { + if (LONG_TIME == VarsButton.Cnt[Tmp]) + { + IOMapButton.State[Tmp] |= LONG_PRESSED_EV; + (IOMapButton.BtnCnt[Tmp].LongPressCnt)++; + } + } + } + else + { + IOMapButton.State[Tmp] = 0x00; + if ((VarsButton.OldState) & ButtonNo) + { + if (VarsButton.Cnt[Tmp] > LONG_TIME) + { + IOMapButton.State[Tmp] = LONG_RELEASED_EV; + (IOMapButton.BtnCnt[Tmp].LongRelCnt)++; + + } + else + { + IOMapButton.State[Tmp] = SHORT_RELEASED_EV; + (IOMapButton.BtnCnt[Tmp].ShortRelCnt)++; + } + } + } + ButtonNo <<= 1; + IOMapButton.BtnCnt[Tmp].RelCnt = ((IOMapButton.BtnCnt[Tmp].ShortRelCnt) + (IOMapButton.BtnCnt[Tmp].LongRelCnt)); + } + VarsButton.OldState = ButtonState; + } +} + +void cButtonExit(void) +{ + dButtonExit(); +} diff --git a/AT91SAM7S256/Source/c_button.h b/AT91SAM7S256/Source/c_button.h new file mode 100644 index 0000000..abb1b2b --- /dev/null +++ b/AT91SAM7S256/Source/c_button.h @@ -0,0 +1,37 @@ +// +// Date init 14.12.2004 +// +// Revision date $Date:: 16-05-06 9:58 $ +// +// Filename $Workfile:: c_button.h $ +// +// Version $Revision:: 6 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/c_button.h $ +// +// Platform C +// + +#ifndef C_BUTTON +#define C_BUTTON + +#ifdef INCLUDE_OS +extern const HEADER cButton; +#endif + +#include "c_button.iom" + + +typedef struct +{ + UWORD Cnt[NO_OF_BTNS]; + UBYTE OldState; +}VARSBUTTON; + +void cButtonInit(void* pHeader); +void cButtonCtrl(void); +void cButtonExit(void); + +extern const HEADER cButton; + +#endif diff --git a/AT91SAM7S256/Source/c_button.iom b/AT91SAM7S256/Source/c_button.iom new file mode 100644 index 0000000..24064a2 --- /dev/null +++ b/AT91SAM7S256/Source/c_button.iom @@ -0,0 +1,61 @@ +// +// Date init 14.12.2004 +// +// Revision date $Date:: 16-05-06 9:58 $ +// +// Filename $Workfile:: c_button.iom $ +// +// Version $Revision:: 10 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/c_button.i $ +// +// Platform C +// + +#ifndef CBUTTON_IOM +#define CBUTTON_IOM + +#define pMapButton ((IOMAPBUTTON*)(pHeaders[ENTRY_BUTTON]->pIOMap)) + +enum +{ + BTN1, + BTN2, + BTN3, + BTN4, + NO_OF_BTNS +}; + +/* Costants related to State */ +enum +{ + PRESSED_EV = 0x01, + SHORT_RELEASED_EV = 0x02, + LONG_PRESSED_EV = 0x04, + LONG_RELEASED_EV = 0x08, + PRESSED_STATE = 0x80 +}; + +typedef struct +{ + UBYTE PressedCnt; + UBYTE LongPressCnt; + UBYTE ShortRelCnt; + UBYTE LongRelCnt; + UBYTE RelCnt; + UBYTE SpareOne; + UBYTE SpareTwo; + UBYTE SpareThree; +}BTNCNT; + +typedef struct +{ + BTNCNT BtnCnt[NO_OF_BTNS]; + UBYTE State[NO_OF_BTNS]; +}IOMAPBUTTON; + + +#endif + + + diff --git a/AT91SAM7S256/Source/c_cmd.c b/AT91SAM7S256/Source/c_cmd.c new file mode 100644 index 0000000..9b83c14 --- /dev/null +++ b/AT91SAM7S256/Source/c_cmd.c @@ -0,0 +1,6292 @@ +// +// Date init 14.12.2004 +// +// Revision date $Date:: 28-03-07 14:53 $ +// +// Filename $Workfile:: c_cmd.c $ +// +// Version $Revision:: 67 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/c_cmd.c $ +// +// Platform C +// + +// +// File Description: +// This file contains the virtual machine implementation to run bytecode +// programs compatible with LEGO MINDSTORMS NXT Software 1.0. +// +// This module (c_cmd) is also responsible for reading the system timer +// (d_timer) and returning on 1 ms timer boundaries. +// + +#include "stdconst.h" +#include "modules.h" + +#include "c_cmd.iom" +#include "c_output.iom" +#include "c_input.iom" +#include "c_loader.iom" +#include "c_ui.iom" +#include "c_sound.iom" +#include "c_button.iom" +#include "c_display.iom" +#include "c_comm.iom" +#include "c_lowspeed.iom" + +#include "c_cmd.h" +#include "c_cmd_bytecodes.h" +#include "d_timer.h" +#include +#include +#include + + +static IOMAPCMD IOMapCmd; +static VARSCMD VarsCmd; +static HEADER **pHeaders; + +const HEADER cCmd = +{ + 0x00010001L, + "Command", + cCmdInit, + cCmdCtrl, + cCmdExit, + (void *)&IOMapCmd, + (void *)&VarsCmd, + (UWORD)sizeof(IOMapCmd), + (UWORD)sizeof(VarsCmd), + 0x0000 //Code size - not used so far +}; + +#if ENABLE_VM + +// c_cmd_drawing.inc is just another C source file +// (the graphics implementation was split off for practical file management reasons) +#include "c_cmd_drawing.inc" + + +// +//Function pointers to sub-interpreters +//This table is indexed by arity +//Unary operations can have arity of 1 or 2 (some need a destination) +//All instructions taking 4 or more operands are handled as "Other" +// +static pInterp InterpFuncs[INTERP_COUNT] = +{ + cCmdInterpNoArg, + cCmdInterpUnop1, + cCmdInterpUnop2, + cCmdInterpBinop, + cCmdInterpOther +}; + +// +//Function pointers to SysCall implementations +//See interpreter for OP_SYSCALL +// +static pSysCall SysCallFuncs[SYSCALL_COUNT] = +{ + cCmdWrapFileOpenRead, + cCmdWrapFileOpenWrite, + cCmdWrapFileOpenAppend, + cCmdWrapFileRead, + cCmdWrapFileWrite, + cCmdWrapFileClose, + cCmdWrapFileResolveHandle, + cCmdWrapFileRename, + cCmdWrapFileDelete, + cCmdWrapSoundPlayFile, + cCmdWrapSoundPlayTone, + cCmdWrapSoundGetState, + cCmdWrapSoundSetState, + cCmdWrapDrawText, + cCmdWrapDrawPoint, + cCmdWrapDrawLine, + cCmdWrapDrawCircle, + cCmdWrapDrawRect, + cCmdWrapDrawPicture, + cCmdWrapSetScreenMode, + cCmdWrapReadButton, + cCmdWrapCommLSWrite, + cCmdWrapCommLSRead, + cCmdWrapCommLSCheckStatus, + cCmdWrapRandomNumber, + cCmdWrapGetStartTick, + cCmdWrapMessageWrite, + cCmdWrapMessageRead, + cCmdWrapCommBTCheckStatus, + cCmdWrapCommBTWrite, + cCmdWrapCommBTRead, + cCmdWrapKeepAlive, + cCmdWrapIOMapRead, + cCmdWrapIOMapWrite +}; + +// +//Next set of arrays are lookup tables for IOM access bytecodes +// +TYPE_CODE IO_TYPES_IN[IO_IN_FIELD_COUNT] = +{ + //IO_IN0 + TC_UBYTE, //IO_IN_TYPE + TC_UBYTE, //IO_IN_MODE + TC_UWORD, //IO_IN_ADRAW + TC_UWORD, //IO_IN_NORMRAW + TC_SWORD, //IO_IN_SCALED_VAL + TC_UBYTE, //IO_IN_INVALID_DATA + + //IO_IN1 + TC_UBYTE, //IO_IN_TYPE + TC_UBYTE, //IO_IN_MODE + TC_UWORD, //IO_IN_ADRAW + TC_UWORD, //IO_IN_NORMRAW + TC_SWORD, //IO_IN_SCALED_VAL + TC_UBYTE, //IO_IN_INVALID_DATA + + //IO_IN2 + TC_UBYTE, //IO_IN_TYPE + TC_UBYTE, //IO_IN_MODE + TC_UWORD, //IO_IN_ADRAW + TC_UWORD, //IO_IN_NORMRAW + TC_SWORD, //IO_IN_SCALED_VAL + TC_UBYTE, //IO_IN_INVALID_DATA + + //IO_IN3 + TC_UBYTE, //IO_IN_TYPE + TC_UBYTE, //IO_IN_MODE + TC_UWORD, //IO_IN_ADRAW + TC_UWORD, //IO_IN_NORMRAW + TC_SWORD, //IO_IN_SCALED_VAL + TC_UBYTE, //IO_IN_INVALID_DATA +}; + +TYPE_CODE IO_TYPES_OUT[IO_OUT_FIELD_COUNT] = +{ + //IO_OUT0 + TC_UBYTE, //IO_OUT_FLAGS + TC_UBYTE, //IO_OUT_MODE + TC_SBYTE, //IO_OUT_SPEED + TC_SBYTE, //IO_OUT_ACTUAL_SPEED + TC_SLONG, //IO_OUT_TACH_COUNT + TC_ULONG, //IO_OUT_TACH_LIMIT + TC_UBYTE, //IO_OUT_RUN_STATE + TC_SBYTE, //IO_OUT_TURN_RATIO + TC_UBYTE, //IO_OUT_REG_MODE + TC_UBYTE, //IO_OUT_OVERLOAD + TC_UBYTE, //IO_OUT_REG_P_VAL + TC_UBYTE, //IO_OUT_REG_I_VAL + TC_UBYTE, //IO_OUT_REG_D_VAL + TC_SLONG, //IO_OUT_BLOCK_TACH_COUNT + TC_SLONG, //IO_OUT_ROTATION_COUNT + + //IO_OUT1 + TC_UBYTE, //IO_OUT_FLAGS + TC_UBYTE, //IO_OUT_MODE + TC_SBYTE, //IO_OUT_SPEED + TC_SBYTE, //IO_OUT_ACTUAL_SPEED + TC_SLONG, //IO_OUT_TACH_COUNT + TC_ULONG, //IO_OUT_TACH_LIMIT + TC_UBYTE, //IO_OUT_RUN_STATE + TC_SBYTE, //IO_OUT_TURN_RATIO + TC_UBYTE, //IO_OUT_REG_MODE + TC_UBYTE, //IO_OUT_OVERLOAD + TC_UBYTE, //IO_OUT_REG_P_VAL + TC_UBYTE, //IO_OUT_REG_I_VAL + TC_UBYTE, //IO_OUT_REG_D_VAL + TC_SLONG, //IO_OUT_BLOCK_TACH_COUNT + TC_SLONG, //IO_OUT_ROTATION_COUNT + + //IO_OUT2 + TC_UBYTE, //IO_OUT_FLAGS + TC_UBYTE, //IO_OUT_MODE + TC_SBYTE, //IO_OUT_SPEED + TC_SBYTE, //IO_OUT_ACTUAL_SPEED + TC_SLONG, //IO_OUT_TACH_COUNT + TC_ULONG, //IO_OUT_TACH_LIMIT + TC_UBYTE, //IO_OUT_RUN_STATE + TC_SBYTE, //IO_OUT_TURN_RATIO + TC_UBYTE, //IO_OUT_REG_MODE + TC_UBYTE, //IO_OUT_OVERLOAD + TC_UBYTE, //IO_OUT_REG_P_VAL + TC_UBYTE, //IO_OUT_REG_I_VAL + TC_UBYTE, //IO_OUT_REG_D_VAL + TC_SLONG, //IO_OUT_BLOCK_TACH_COUNT + TC_SLONG, //IO_OUT_ROTATION_COUNT +}; + + +TYPE_CODE * IO_TYPES[2] = +{ + IO_TYPES_IN, + IO_TYPES_OUT +}; + +//Actual pointers filled in during cCmdInit() +void * IO_PTRS_IN[IO_IN_FIELD_COUNT]; +void * IO_PTRS_OUT[IO_OUT_FIELD_COUNT]; + +void ** IO_PTRS[2] = +{ + IO_PTRS_IN, + IO_PTRS_OUT +}; + + +//cCmdHandleRemoteCommands is the registered handler for "direct" command protocol packets +//It is only intended to be called via c_comm's main protocol handler +UWORD cCmdHandleRemoteCommands(UBYTE * pInBuf, UBYTE * pOutBuf, UBYTE * pLen) +{ + NXT_STATUS RCStatus = NO_ERR; + //Response packet length. Always includes RCStatus byte. + ULONG ResponseLen = 1; + //Boolean flag to send a response. TRUE unless overridden below. + ULONG SendResponse = TRUE; + //Boolean flag if we are handling a reply telegram. FALSE unless overridden. + ULONG IncomingReply = FALSE; + ULONG i, FirstPort, LastPort; + UWORD LStatus; + UWORD Count, QueueID; + UBYTE * pData; + + //Illegal call, give up + if (pInBuf == NULL || pLen == NULL) + { + NXT_BREAK; + return (0xFFFF); + } + + //No output buffer provided, so skip any work related to returning a response + if (pOutBuf == NULL) + SendResponse = FALSE; + + //If first byte identifies this as a reply telegram, we have different work to do. + if (pInBuf[0] == 0x02) + { + IncomingReply = TRUE; + //Reply telegrams never get responses, even if caller provided a buffer. + SendResponse = FALSE; + } + + //Advance pInBuf past command type byte + pInBuf++; + + if (!IncomingReply) + { + switch(pInBuf[0]) + { + case RC_START_PROGRAM: + { + //Check that file exists. If not, return error + //!!! Should return standard loader file error in cases like this?? + //!!! Proper solution would also check file mode to avoid confusing errors + if (LOADER_ERR(LStatus = pMapLoader->pFunc(FINDFIRST, (&pInBuf[1]), NULL, NULL)) != SUCCESS) + { + RCStatus = ERR_RC_ILLEGAL_VAL; + break; + } + + //Close file handle returned by FINDFIRST + pMapLoader->pFunc(CLOSE, LOADER_HANDLE_P(LStatus), NULL, NULL); + + //File must exist, so inform UI to attempt execution in the usual way (enables consistent feedback) + pMapUi->Flags |= UI_EXECUTE_LMS_FILE; + strncpy((PSZ)(pMapUi->LMSfilename), (PSZ)(&pInBuf[1]), FILENAME_LENGTH + 1); + } + break; + + case RC_STOP_PROGRAM: + { + if (VarsCmd.ActiveProgHandle == NOT_A_HANDLE) + { + RCStatus = ERR_NO_PROG; + break; + } + + IOMapCmd.DeactivateFlag = TRUE; + } + break; + + case RC_PLAY_SOUND_FILE: + { + if (LOADER_ERR(pMapLoader->pFunc(FINDFIRST, (&pInBuf[2]), NULL, NULL)) != SUCCESS) + { + RCStatus = ERR_RC_ILLEGAL_VAL; + break; + } + + //Close file handle returned by FINDFIRST + pMapLoader->pFunc(CLOSE, LOADER_HANDLE_P(LStatus), NULL, NULL); + + if (pInBuf[1] == FALSE) + pMapSound->Mode = SOUND_ONCE; + else //Any non-zero value treated as TRUE + pMapSound->Mode = SOUND_LOOP; + + strncpy((PSZ)pMapSound->SoundFilename, (PSZ)(&pInBuf[2]), FILENAME_LENGTH + 1); + pMapSound->Flags |= SOUND_UPDATE; + } + break; + + case RC_PLAY_TONE: + { + pMapSound->Mode = SOUND_TONE; + //!!! Range check valid values? + memcpy((PSZ)(&(pMapSound->Freq)), (PSZ)(&pInBuf[1]), 2); + memcpy((PSZ)(&(pMapSound->Duration)), (PSZ)(&pInBuf[3]), 2); + + pMapSound->Flags |= SOUND_UPDATE; + } + break; + + case RC_SET_OUT_STATE: + { + //Don't do anything if illegal port specification is made + if (pInBuf[1] >= NO_OF_OUTPUTS && pInBuf[1] != 0xFF) + { + RCStatus = ERR_RC_ILLEGAL_VAL; + break; + } + + //0xFF is protocol defined to mean "all ports". + if (pInBuf[1] == 0xFF) + { + FirstPort = 0; + LastPort = NO_OF_OUTPUTS - 1; + } + else + FirstPort = LastPort = pInBuf[1]; + + for (i = FirstPort; i <= LastPort; i++) + { + pMapOutPut->Outputs[i].Speed = pInBuf[2]; + pMapOutPut->Outputs[i].Mode = pInBuf[3]; + pMapOutPut->Outputs[i].RegMode = pInBuf[4]; + pMapOutPut->Outputs[i].SyncTurnParameter = pInBuf[5]; + pMapOutPut->Outputs[i].RunState = pInBuf[6]; + memcpy((PSZ)(&(pMapOutPut->Outputs[i].TachoLimit)), (PSZ)(&pInBuf[7]), 4); + + pMapOutPut->Outputs[i].Flags |= UPDATE_MODE | UPDATE_SPEED | UPDATE_TACHO_LIMIT; + } + } + break; + + case RC_SET_IN_MODE: + { + i = pInBuf[1]; + + //Don't do anything if illegal port specification is made + //!!! Should check against legal Types and Modes? (bitmask for Modes?) + if (i >= NO_OF_INPUTS) + { + RCStatus = ERR_RC_ILLEGAL_VAL; + break; + } + + pMapInput->Inputs[i].SensorType = pInBuf[2]; + pMapInput->Inputs[i].SensorMode = pInBuf[3]; + + //Set InvalidData flag automatically since type may have changed + pMapInput->Inputs[i].InvalidData = TRUE; + } + break; + + case RC_GET_OUT_STATE: + { + if (SendResponse == TRUE) + { + i = pInBuf[1]; + + //Return error and all zeros if illegal port specification is made + if (i >= NO_OF_OUTPUTS) + { + RCStatus = ERR_RC_ILLEGAL_VAL; + memset(&(pOutBuf[ResponseLen]), 0, 22); + ResponseLen += 22; + break; + } + + //Echo port + pOutBuf[ResponseLen] = i; + ResponseLen++; + + //Power + pOutBuf[ResponseLen] = pMapOutPut->Outputs[i].Speed; + ResponseLen++; + + //Mode + pOutBuf[ResponseLen] = pMapOutPut->Outputs[i].Mode; + ResponseLen++; + + //RegMode + pOutBuf[ResponseLen] = pMapOutPut->Outputs[i].RegMode; + ResponseLen++; + + //TurnRatio + pOutBuf[ResponseLen] = pMapOutPut->Outputs[i].SyncTurnParameter; + ResponseLen++; + + //RunState + pOutBuf[ResponseLen] = pMapOutPut->Outputs[i].RunState; + ResponseLen++; + + //TachoLimit ULONG + memcpy((PSZ)&(pOutBuf[ResponseLen]), (PSZ)(&(pMapOutPut->Outputs[i].TachoLimit)), 4); + ResponseLen += 4; + + //TachoCount SLONG + memcpy((PSZ)&(pOutBuf[ResponseLen]), (PSZ)(&(pMapOutPut->Outputs[i].TachoCnt)), 4); + ResponseLen += 4; + + //BlockTachoCount SLONG + memcpy((PSZ)&(pOutBuf[ResponseLen]), (PSZ)(&(pMapOutPut->Outputs[i].BlockTachoCount)), 4); + ResponseLen += 4; + + //RotationCount SLONG + memcpy((PSZ)&(pOutBuf[ResponseLen]), (PSZ)(&(pMapOutPut->Outputs[i].RotationCount)), 4); + ResponseLen += 4; + + NXT_ASSERT(ResponseLen == 23); + } + } + break; + + case RC_GET_IN_VALS: + { + if (SendResponse == TRUE) + { + i = pInBuf[1]; + + //Return error and all zeros if illegal port specification is made + if (i >= NO_OF_INPUTS) + { + RCStatus = ERR_RC_ILLEGAL_VAL; + memset(&(pOutBuf[ResponseLen]), 0, 13); + ResponseLen += 13; + break; + } + + //Echo port + pOutBuf[ResponseLen] = i; + ResponseLen++; + + //Set "Valid?" boolean + if (pMapInput->Inputs[i].InvalidData) + pOutBuf[ResponseLen] = FALSE; + else + pOutBuf[ResponseLen] = TRUE; + + ResponseLen++; + + //Set "Calibrated?" boolean + //!!! "Calibrated?" is a placeholder in the protocol. Always FALSE for now. + pOutBuf[ResponseLen] = FALSE; + ResponseLen++; + + pOutBuf[ResponseLen] = pMapInput->Inputs[i].SensorType; + ResponseLen++; + + pOutBuf[ResponseLen] = pMapInput->Inputs[i].SensorMode; + ResponseLen++; + + //Set Raw, Normalized, and Scaled values + memcpy((PSZ)&(pOutBuf[ResponseLen]), (PSZ)(&(pMapInput->Inputs[i].ADRaw)), 2); + ResponseLen += 2; + + memcpy((PSZ)&(pOutBuf[ResponseLen]), (PSZ)(&(pMapInput->Inputs[i].SensorRaw)), 2); + ResponseLen += 2; + + memcpy((PSZ)&(pOutBuf[ResponseLen]), (PSZ)(&(pMapInput->Inputs[i].SensorValue)), 2); + ResponseLen += 2; + + //!!! Return normalized raw value in place of calibrated value for now -- see comment above + memcpy((PSZ)&(pOutBuf[ResponseLen]), (PSZ)(&(pMapInput->Inputs[i].SensorRaw)), 2); + ResponseLen += 2; + + NXT_ASSERT(ResponseLen == 14); + } + } + break; + + case RC_RESET_IN_VAL: + { + i = pInBuf[1]; + + //Don't do anything if illegal port specification is made + if (i >= NO_OF_INPUTS) + { + RCStatus = ERR_RC_ILLEGAL_VAL; + break; + } + + //Clear SensorValue to zero. Leave Raw and Normalized as-is, since they never accumulate running values. + pMapInput->Inputs[i].SensorValue = 0; + } + break; + + case RC_MESSAGE_WRITE: + { + QueueID = pInBuf[1]; + Count = pInBuf[2]; + pData = &(pInBuf[3]); + + //If Count is illegal or MsgData is not null-terminated, + // we can't accept it as a valid string + if (Count == 0 || Count > MAX_MESSAGE_SIZE || pData[Count - 1] != 0x00) + { + RCStatus = ERR_RC_ILLEGAL_VAL; + break; + } + + RCStatus = cCmdMessageWrite(QueueID, pData, Count); + + //ERR_MEM here means we must compact the dataspace and retry message write + if (RCStatus == ERR_MEM) + { + cCmdDSCompact(); + RCStatus = cCmdMessageWrite(QueueID, pData, Count); + } + } + break; + + case RC_RESET_POSITION: + { + i = pInBuf[1]; + + //Don't do anything if illegal port specification is made + if (i >= NO_OF_OUTPUTS) + { + RCStatus = ERR_RC_ILLEGAL_VAL; + break; + } + + //pInBuf[2] is a selector + //FALSE: Position relative to start of last program + //TRUE: Position relative to start of last motor control block + if (pInBuf[2] == FALSE) + { + pMapOutPut->Outputs[i].Flags |= UPDATE_RESET_ROTATION_COUNT; + } + else + { + pMapOutPut->Outputs[i].Flags |= UPDATE_RESET_BLOCK_COUNT; + } + } + break; + + case RC_GET_BATT_LVL: + { + if (SendResponse == TRUE) + { + //Return BatteryVoltage directly from IOMapUI, in mV + memcpy((PSZ)&(pOutBuf[ResponseLen]), (PSZ)&(pMapUi->BatteryVoltage), 2); + ResponseLen += 2; + } + } + break; + + case RC_STOP_SOUND: + { + //Tell sound module to stop playback, no questions asked + pMapSound->State = SOUND_STOP; + } + break; + + case RC_KEEP_ALIVE: + { + pMapUi->Flags |= UI_RESET_SLEEP_TIMER; + + if (SendResponse == TRUE) + { + //Convert to milliseconds to match external conventions + i = (pMapUi->SleepTimeout * 60 * 1000); + memcpy((PSZ)&(pOutBuf[ResponseLen]), (PSZ)&i, 4); + ResponseLen += 4; + } + } + break; + + case RC_LS_GET_STATUS: + { + if (SendResponse == TRUE) + { + i = pInBuf[1]; + + //Don't do anything if illegal port specification is made + if (i >= NO_OF_LOWSPEED_COM_CHANNEL) + { + RCStatus = ERR_RC_ILLEGAL_VAL; + break; + } + + RCStatus = cCmdLSCheckStatus(i); + + pOutBuf[ResponseLen] = cCmdLSCalcBytesReady(i); + ResponseLen++; + } + } + break; + + case RC_LS_WRITE: + { + i = pInBuf[1]; + Count = pInBuf[2]; + + //Don't do anything if illegal port specification is made + if (i >= NO_OF_LOWSPEED_COM_CHANNEL) + { + RCStatus = ERR_RC_ILLEGAL_VAL; + break; + } + + RCStatus = cCmdLSWrite(i, Count, &(pInBuf[4]), pInBuf[3]); + } + break; + + case RC_LS_READ: + { + if (SendResponse == TRUE) + { + i = pInBuf[1]; + + //Don't do anything if illegal port specification is made + if (i >= NO_OF_LOWSPEED_COM_CHANNEL) + { + RCStatus = ERR_RC_ILLEGAL_VAL; + break; + } + + //Get channel status and number of bytes available to read + RCStatus = cCmdLSCheckStatus(i); + Count = cCmdLSCalcBytesReady(i); + + pOutBuf[ResponseLen] = (UBYTE)Count; + ResponseLen++; + + //If channel is ready and has data ready for us, put the data into outgoing buffer + if (!IS_ERR(RCStatus) && Count > 0) + { + RCStatus = cCmdLSRead(i, (UBYTE)Count, &(pOutBuf[ResponseLen])); + ResponseLen += Count; + } + + //Pad remaining data bytes with zeroes + Count = 16 - Count; + memset(&(pOutBuf[ResponseLen]), 0, Count); + ResponseLen += Count; + } + } + break; + + case RC_GET_CURR_PROGRAM: + { + if (SendResponse == TRUE) + { + //If there's no active program, return error and empty name buffer + if (VarsCmd.ActiveProgHandle == NOT_A_HANDLE) + { + RCStatus = ERR_NO_PROG; + memset(&(pOutBuf[ResponseLen]), 0, FILENAME_LENGTH + 1); + } + //Else, copy out stashed program name + else + { + strncpy((PSZ)(&(pOutBuf[ResponseLen])), (PSZ)(VarsCmd.ActiveProgName), FILENAME_LENGTH + 1); + } + + //Regardless, we've copied out a filename's worth of bytes... + ResponseLen += FILENAME_LENGTH + 1; + } + } + break; + + case RC_MESSAGE_READ: + { + if (SendResponse == TRUE) + { + QueueID = pInBuf[1]; + + //Fill in response with remote mailbox number so remote device knows where to store this message. + pOutBuf[ResponseLen] = pInBuf[2]; + ResponseLen++; + + RCStatus = cCmdMessageGetSize(QueueID, &Count); + pOutBuf[ResponseLen] = Count; + ResponseLen++; + + if (!IS_ERR(RCStatus) && Count > 0) + { + pData = &(pOutBuf[ResponseLen]); + RCStatus = cCmdMessageRead(QueueID, pData, Count, (pInBuf[3])); + //If cCmdMessageRead encountered an error, there is no real data in the buffer, so clear it out (below) + if (IS_ERR(RCStatus)) + Count = 0; + else + ResponseLen += Count; + } + + //Pad remaining data bytes with zeroes + Count = MAX_MESSAGE_SIZE - Count; + memset(&(pOutBuf[ResponseLen]), 0, Count); + ResponseLen += Count; + } + } + break; + + default: + { + //Unknown remote command -- still inform client to not expect any response bytes + NXT_BREAK; + RCStatus = ERR_RC_UNKNOWN_CMD; + } + break; + }; + } + //Handle reply telegrams + else + { + switch(pInBuf[0]) + { + case RC_MESSAGE_READ: + { + QueueID = pInBuf[2]; + Count = pInBuf[3]; + pData = &(pInBuf[4]); + + //This is a response to our request to read a message from a remote mailbox. + //If telegram looks valid, write the resulting message into our local mailbox. + //(If MsgData is not null-terminated, we can't accept it as a valid string.) + if (!IS_ERR((SBYTE)(pInBuf[1])) + && Count > 0 + && Count <= MAX_MESSAGE_SIZE + && pData[Count - 1] == 0x00) + { + RCStatus = cCmdMessageWrite(QueueID, pData, Count); + + //ERR_MEM here means we must compact the dataspace + if (RCStatus == ERR_MEM) + { + cCmdDSCompact(); + RCStatus = cCmdMessageWrite(QueueID, pData, Count); + } + } + + //If telegram doesn't check out, do nothing. No errors are ever returned for reply telegrams. + } + break; + + default: + { + //Unhandled reply telegram. Do nothing. + //!!! Could/should stash unhandled/all replies somewhere so a syscall could read them + } + break; + }; + } + + if (SendResponse == TRUE) + { + //Return response length (pointer checked above) + *pLen = (UBYTE)ResponseLen; + //Fill in status byte + pOutBuf[0] = (UBYTE)(RCStatus); + } + else + *pLen = 0; + + return (0); +} + + +// +// Standard interface functions +// + +void cCmdInit(void* pHeader) +{ + ULONG i; + + pHeaders = pHeader; + + IOMapCmd.pRCHandler = &cCmdHandleRemoteCommands; + +#if defined(ARM_DEBUG) + //Init run-time assert tracking variables + VarsCmd.AssertFlag = FALSE; + VarsCmd.AssertLine = 0; +#endif + + //Initialize IO_PTRS_OUT + for (i = 0; i < NO_OF_OUTPUTS; i++) + { + IO_PTRS_OUT[IO_OUT_FLAGS + i * IO_OUT_FPP] = (void*)&(pMapOutPut->Outputs[i].Flags); + IO_PTRS_OUT[IO_OUT_MODE + i * IO_OUT_FPP] = (void*)&(pMapOutPut->Outputs[i].Mode); + IO_PTRS_OUT[IO_OUT_SPEED + i * IO_OUT_FPP] = (void*)&(pMapOutPut->Outputs[i].Speed); + IO_PTRS_OUT[IO_OUT_ACTUAL_SPEED + i * IO_OUT_FPP] = (void*)&(pMapOutPut->Outputs[i].ActualSpeed); + IO_PTRS_OUT[IO_OUT_TACH_COUNT + i * IO_OUT_FPP] = (void*)&(pMapOutPut->Outputs[i].TachoCnt); + IO_PTRS_OUT[IO_OUT_TACH_LIMIT + i * IO_OUT_FPP] = (void*)&(pMapOutPut->Outputs[i].TachoLimit); + IO_PTRS_OUT[IO_OUT_RUN_STATE + i * IO_OUT_FPP] = (void*)&(pMapOutPut->Outputs[i].RunState); + IO_PTRS_OUT[IO_OUT_TURN_RATIO + i * IO_OUT_FPP] = (void*)&(pMapOutPut->Outputs[i].SyncTurnParameter); + IO_PTRS_OUT[IO_OUT_REG_MODE + i * IO_OUT_FPP] = (void*)&(pMapOutPut->Outputs[i].RegMode); + IO_PTRS_OUT[IO_OUT_OVERLOAD + i * IO_OUT_FPP] = (void*)&(pMapOutPut->Outputs[i].Overloaded); + IO_PTRS_OUT[IO_OUT_REG_P_VAL + i * IO_OUT_FPP] = (void*)&(pMapOutPut->Outputs[i].RegPParameter); + IO_PTRS_OUT[IO_OUT_REG_I_VAL + i * IO_OUT_FPP] = (void*)&(pMapOutPut->Outputs[i].RegIParameter); + IO_PTRS_OUT[IO_OUT_REG_D_VAL + i * IO_OUT_FPP] = (void*)&(pMapOutPut->Outputs[i].RegDParameter); + IO_PTRS_OUT[IO_OUT_BLOCK_TACH_COUNT + i * IO_OUT_FPP] = (void*)&(pMapOutPut->Outputs[i].BlockTachoCount); + IO_PTRS_OUT[IO_OUT_ROTATION_COUNT + i * IO_OUT_FPP] = (void*)&(pMapOutPut->Outputs[i].RotationCount); + } + + //Initialize IO_PTRS_IN + for (i = 0; i < NO_OF_INPUTS; i++) + { + IO_PTRS_IN[IO_IN_TYPE + i * IO_IN_FPP] = (void*)&(pMapInput->Inputs[i].SensorType); + IO_PTRS_IN[IO_IN_MODE + i * IO_IN_FPP] = (void*)&(pMapInput->Inputs[i].SensorMode); + IO_PTRS_IN[IO_IN_ADRAW + i * IO_IN_FPP] = (void*)&(pMapInput->Inputs[i].ADRaw); + IO_PTRS_IN[IO_IN_NORMRAW + i * IO_IN_FPP] = (void*)&(pMapInput->Inputs[i].SensorRaw); + IO_PTRS_IN[IO_IN_SCALEDVAL + i * IO_IN_FPP] = (void*)&(pMapInput->Inputs[i].SensorValue); + IO_PTRS_IN[IO_IN_INVALID_DATA + i * IO_IN_FPP] = (void*)&(pMapInput->Inputs[i].InvalidData); + } + + //Clear memory pool and initialize VarsCmd (cCmdDeactivateProgram effectively re-inits VarsCmd) + cCmdInitPool(); + cCmdDeactivateProgram(); + + //Global state variables for BlueTooth communication. + VarsCmd.CommStat = (SWORD)SUCCESS; + VarsCmd.CommStatReset = (SWORD)BTBUSY; + VarsCmd.CommCurrConnection = 1; + + //Global flags for various reset and bookkeeping scenarios + VarsCmd.DirtyComm = FALSE; + VarsCmd.DirtyDisplay = FALSE; + + VarsCmd.VMState = VM_IDLE; + +#if defined (ARM_NXT) + //Make sure Pool is long-aligned + NXT_ASSERT(!((ULONG)(POOL_START) % SIZE_SLONG)); +#endif + + IOMapCmd.ProgStatus = PROG_IDLE; + IOMapCmd.ActivateFlag = FALSE; + IOMapCmd.Awake = TRUE; + + //Default offsets explicitly chosen to cause an error if used with IOMAPREAD/IOMAPWRITE + //Real values will be set when programs run and/or the DS is re-arranged. + IOMapCmd.OffsetDVA = 0xFFFF; + IOMapCmd.OffsetDS = 0xFFFF; + + //Initialize format string and clear out FileName string + strncpy((PSZ)(IOMapCmd.FormatString), VM_FORMAT_STRING, VM_FORMAT_STRING_SIZE); + memset(IOMapCmd.FileName, 0, sizeof(IOMapCmd.FileName)); + + dTimerInit(); + IOMapCmd.Tick = dTimerRead(); + + return; +} + + +void cCmdCtrl(void) +{ + UBYTE Continue = TRUE; + NXT_STATUS Status = NO_ERR; + ULONG i; + CLUMP_ID CurrClumpID; + + switch (VarsCmd.VMState) + { + case VM_IDLE: + { + //If there's a new program to activate... + if (IOMapCmd.ActivateFlag == TRUE) + { + //Clear flag so we only activate once per new file + IOMapCmd.ActivateFlag = FALSE; + + Status = cCmdActivateProgram(IOMapCmd.FileName); + + //If we hit an activation error: + //1. Set PROG_ERROR status + //2. Proceed to VM_RESET1 (some unneeded work, yes, but preserves contract with UI + if (IS_ERR(Status)) + { + IOMapCmd.ProgStatus = PROG_ERROR; + VarsCmd.VMState = VM_RESET1; + } + //Else start running program + else + { + VarsCmd.VMState = VM_RUN_FREE; + IOMapCmd.ProgStatus = PROG_RUNNING; + VarsCmd.StartTick = IOMapCmd.Tick; + +#if VM_BENCHMARK + //Re-init benchmark + VarsCmd.InstrCount = 0; + VarsCmd.Average = 0; + VarsCmd.OverTimeCount = 0; + VarsCmd.MaxOverTimeLength = 0; + VarsCmd.CmdCtrlCount = 0; + VarsCmd.CompactionCount = 0; + VarsCmd.LastCompactionTick = 0; + VarsCmd.MaxCompactionTime = 0; + memset(VarsCmd.OpcodeBenchmarks, 0, sizeof(VarsCmd.OpcodeBenchmarks)); + memset(VarsCmd.SyscallBenchmarks, 0, sizeof(VarsCmd.SyscallBenchmarks)); +#endif + //Reset devices to a known state before we begin running + cCmdResetDevices(); + + pMapUi->Flags |= (UI_DISABLE_LEFT_RIGHT_ENTER | UI_DISABLE_EXIT); + } + } + + break; + } + + //Initialize VM internal state data and devices which must respond immediately to program ending + case VM_RESET1: + { + //If we aborted a program, reset devices (specifically, motors) immediately + //Otherwise, wait for UI to put us into PROG_RESET (gives motors a chance to brake before setting to coast) + //!!! This means cCmdResetDevices will get called twice on abort. Should not be a big deal. + if (IOMapCmd.ProgStatus == PROG_ABORT) + cCmdResetDevices(); + + //Reenable UI access to buttons + pMapUi->Flags &= ~(UI_DISABLE_LEFT_RIGHT_ENTER | UI_DISABLE_EXIT); + +#if VM_BENCHMARK + if (IOMapCmd.Tick != VarsCmd.StartTick) + VarsCmd.Average = VarsCmd.InstrCount / (IOMapCmd.Tick - VarsCmd.StartTick); + else + //It appears that we finished in 0 milliseconds. Very unlikely on ARM, so set a flag value. + VarsCmd.Average = 0xFFFFFFFF; + + cCmdWriteBenchmarkFile(); +#endif + + //Re-initialize program state data (contents of memory pool preserved) + //!!! Skip this step in simulator builds so helper access methods still work +#ifndef SIM_NXT + cCmdDeactivateProgram(); +#endif //SIM_NXT + + //If this program has taken over the display, reset it for the UI + cCmdRestoreDefaultScreen(); + + //Stop any currently playing sound and re-init volume according to UI prefs + pMapSound->State = SOUND_STOP; + pMapSound->Volume = pMapUi->Volume; + + //Artificially set CommStatReset to BTBUSY to force at least one SETCMDMODE call (see VM_RESET2 case) + VarsCmd.CommStatReset = (SWORD)BTBUSY; + + VarsCmd.VMState = VM_RESET2; + } + break; + + case VM_RESET2: + { + //Reset BlueCore into "command mode" (close any open streams) + //Since SETCMDMODE subject to BTBUSY, we may need to make multiple calls + //Any CommStatReset value other than BTBUSY means our request was accepted + //Assumptions: + //Process should never take longer than UI timeout (see below), but if it does, + // we could be left with the stream open to an NXT peer and block out the PC. + //Also assuming that once SETCMDMODE request is accepted, it never fails. + if (VarsCmd.CommStatReset == (SWORD)BTBUSY && VarsCmd.DirtyComm == TRUE) + pMapComm->pFunc(SETCMDMODE, 0, 0, 0, NULL, (UWORD*)&(VarsCmd.CommStatReset)); + + //If UI is done displaying ending program status, move on. + if (IOMapCmd.ProgStatus == PROG_RESET) + { + //Reset devices whenever a program ends for any reason + cCmdResetDevices(); + + VarsCmd.DirtyComm = FALSE; + + //Go to VM_IDLE state + VarsCmd.VMState = VM_IDLE; + IOMapCmd.ProgStatus = PROG_IDLE; + } + break; + } + + case VM_RUN_FREE: + case VM_RUN_SINGLE: + { + +#if VM_BENCHMARK + //IOMapCmd.Tick currently holds the tick from the end of last cCmdCtrl call. + //If we don't come back here before dTimerRead() increments, the m_sched loop has taken *at least* 1 ms. + if (IOMapCmd.Tick != dTimerRead()) + { + VarsCmd.OverTimeCount++; + //Record maximum magnitude of schedule loop overage, in millisecs + if (dTimerRead() - IOMapCmd.Tick > VarsCmd.MaxOverTimeLength) + VarsCmd.MaxOverTimeLength = dTimerRead() - IOMapCmd.Tick; + } + VarsCmd.CmdCtrlCount++; +#endif + //Abort current program if cancel button is pressed + if (IOMapCmd.DeactivateFlag == TRUE || pMapButton->State[BTN1] & PRESSED_EV) + { + IOMapCmd.DeactivateFlag = FALSE; + + //Clear pressed event so it doesn't get double-counted by UI + pMapButton->State[BTN1] &= ~PRESSED_EV; + + //Go to VM_RESET1 state and report abort + VarsCmd.VMState = VM_RESET1; + IOMapCmd.ProgStatus = PROG_ABORT; + break; + } + + //Assert that we have an active program + NXT_ASSERT(VarsCmd.ActiveProgHandle != NOT_A_HANDLE); + + //Execute from at least one clump + do + { + if (cCmdIsClumpIDSane(VarsCmd.RunQ.Head)) + { + //Stash and dequeue RunQ's head clump + CurrClumpID = VarsCmd.RunQ.Head; + + //Execute at least one instruction from current clump + //Execute up to 'Priority' instructions as long as we are in VM_FREE_RUN mode + //Finishing/suspending a clump, BREAKOUT_REQ, or any errors will also end this loop + i = 0; + do + { + //Interpret one instruction per call, advancing PC as needed + Status = cCmdInterpFromClump(CurrClumpID); + +#if VM_BENCHMARK + VarsCmd.InstrCount++; +#endif + + NXT_ASSERT(!IS_ERR(Status)); + if (IS_ERR(Status) || Status == CLUMP_DONE || Status == CLUMP_SUSPEND || Status == BREAKOUT_REQ || Status == STOP_REQ) + { + //We're done with this clump or breaking out prematurely, + //so break the multi-instruction loop + break; + } + else + { + //Count up one more instruction for this pass + i++; + } + } while (VarsCmd.VMState == VM_RUN_FREE && i < VarsCmd.pAllClumps[CurrClumpID].Priority); + + //Only rotate RunQ on a "normal" finish, i.e. no error, clump end, or breakout request + if (!(IS_ERR(Status) || Status == CLUMP_DONE || Status == CLUMP_SUSPEND || Status == BREAKOUT_REQ)) + cCmdRotateQ(&(VarsCmd.RunQ)); + } + + //Re-evaluate conditions for stopping the dataflow scheduler + //Halt program on all errors + if (IS_ERR(Status)) + { + Continue = FALSE; + + VarsCmd.VMState = VM_RESET1; + IOMapCmd.ProgStatus = PROG_ERROR; + } + else if (Status == BREAKOUT_REQ) + { + Continue = FALSE; + } + //If RunQ is empty or user requested early termination, program is done + else if (!cCmdIsClumpIDSane(VarsCmd.RunQ.Head) || Status == STOP_REQ) + { + Continue = FALSE; + + VarsCmd.VMState = VM_RESET1; + IOMapCmd.ProgStatus = PROG_OK; + } + //VM_RUN_FREE means continue executing until a new ms tick rolls over + else if (VarsCmd.VMState == VM_RUN_FREE) + { + Continue = (IOMapCmd.Tick == dTimerRead()); + } + //Otherwise execute only one pass per call + else //VarsCmd.VMState == VM_RUN_SINGLE + { + VarsCmd.VMState = VM_RUN_PAUSE; + Continue = FALSE; + } + + } while (Continue == TRUE); + + break; + } + }//END state machine switch + + //Busy wait to always maintain 1ms period + BUSY_WAIT_NEXT_MS; + + //Set tick to new value for next time 'round + IOMapCmd.Tick = dTimerRead(); + + return; +} + + +void cCmdExit(void) +{ + dTimerExit(); + + return; +} + + +NXT_STATUS cCmdReadFileHeader(UBYTE* pData, ULONG DataSize, + PROG_FILE_OFFSETS* pFileOffsets) +{ + ULONG i; + UBYTE * pCursor; + UWORD CurrOffset = 0; + UBYTE DepCount; + UWORD DopeVectorOffset; + UWORD FileClumpCount; + UBYTE FileMajor, FileMinor, + CompatibleMinor, CompatibleMajor, + CurrentMajor; + + NXT_ASSERT(pData != NULL); + + //Assign pCursor to point to version word inside file header + pCursor = (pData + VM_FORMAT_STRING_SIZE - 2); + + //Decode version numbers into comparable bytes + FileMajor = *pCursor; + FileMinor = *(pCursor + 1); + CompatibleMajor = (UBYTE)(VM_OLDEST_COMPATIBLE_VERSION >> 8); + CompatibleMinor = (UBYTE)(VM_OLDEST_COMPATIBLE_VERSION); + CurrentMajor = (UBYTE)(FIRMWAREVERSION >> 8); + //CurrentMinor = (UBYTE)(FIRMWAREVERSION); + + //Return ERR_VER if file lacks proper format string or version number + //!!! Only checking major version recommended for future development + if (strncmp((PSZ)pData, VM_FORMAT_STRING, VM_FORMAT_STRING_SIZE) + || FileMajor < CompatibleMajor || FileMinor < CompatibleMinor + || FileMajor > CurrentMajor) + { + NXT_BREAK; + return (ERR_VER); + } + + //Advance CurrOffset past header information + CurrOffset += VM_FORMAT_STRING_SIZE; + + // + //Initialize bookkeeping variables + // + VarsCmd.DataspaceCount = *((UWORD*)(pData + CurrOffset)); + CurrOffset += 2; + + VarsCmd.DataspaceSize = *((UWORD*)(pData + CurrOffset)); + CurrOffset += 2; + + VarsCmd.DSStaticSize = *((UWORD*)(pData + CurrOffset)); + CurrOffset += 2; + + pFileOffsets->DSDefaultsSize = *((UWORD*)(pData + CurrOffset)); + CurrOffset += 2; + + pFileOffsets->DynamicDefaults = *((UWORD*)(pData + CurrOffset)); + CurrOffset += 2; + + pFileOffsets->DynamicDefaultsSize = *((UWORD*)(pData + CurrOffset)); + CurrOffset += 2; + + VarsCmd.MemMgr.Head = *((UWORD*)(pData + CurrOffset)); + CurrOffset += 2; + + VarsCmd.MemMgr.Tail = *((UWORD*)(pData + CurrOffset)); + CurrOffset += 2; + + DopeVectorOffset = *((UWORD*)(pData + CurrOffset)); + CurrOffset += 2; + + //!!! Odd code here to deal with type mismatch between file format and CLUMP_ID typedef. + //Neither is trivial to change, so it's best to just check the data for consistency here. + FileClumpCount = *((UWORD*)(pData + CurrOffset)); + CurrOffset += 2; + + //Must have at least one clump and count can't exceed the NOT_A_CLUMP sentinel + if (FileClumpCount == 0 || FileClumpCount >= NOT_A_CLUMP) + return (ERR_FILE); + else + VarsCmd.AllClumpsCount = (CLUMP_ID)FileClumpCount; + + VarsCmd.CodespaceCount = *((UWORD*)(pData + CurrOffset)); + CurrOffset += 2; + + //Can't have a valid program with no code + if (VarsCmd.CodespaceCount == 0) + return (ERR_FILE); + + // + // Now, calculate offsets for each data segment in the file + // + + CurrOffset += CurrOffset % 2; + pFileOffsets->DSTOC = CurrOffset; + CurrOffset += VarsCmd.DataspaceCount * sizeof(DS_TOC_ENTRY); + + CurrOffset += CurrOffset % 2; + pFileOffsets->DSDefaults = CurrOffset; + CurrOffset += pFileOffsets->DSDefaultsSize; + + //ClumpRecs must be aligned on even boundaries + CurrOffset += CurrOffset % 2; + pFileOffsets->Clumps = CurrOffset; + + //Set cursor to start of clump records + pCursor = pData + CurrOffset; + + //Set CurrOffset to start of dependent lists + CurrOffset += VarsCmd.AllClumpsCount * VM_FILE_CLUMP_REC_SIZE; + + //Read dependent count from each clump record, advancing CurrOffset accordingly + for (i = 0; i < VarsCmd.AllClumpsCount; i++) + { + DepCount = *(pCursor + 1); + CurrOffset += DepCount; + pCursor += VM_FILE_CLUMP_REC_SIZE; + } + + //Codespace must be aligned on even boundary + CurrOffset += CurrOffset % 2; + pFileOffsets->Codespace = CurrOffset; + + //No need to read through codespace, but make sure CurrOffset ended up sane + //If not, something went wrong reading the header information + if (CurrOffset != (DataSize - VarsCmd.CodespaceCount * 2)) + { + NXT_BREAK; + return (ERR_FILE); + } + + // + // Finally, update VarsCmd fields + // + + VarsCmd.RunQ.Head = NOT_A_CLUMP; + VarsCmd.RunQ.Tail = NOT_A_CLUMP; + + //Reset codespace pointer + VarsCmd.pCodespace = (CODE_WORD*)(pData + pFileOffsets->Codespace); + + //...placing clump records first... + VarsCmd.pAllClumps = (CLUMP_REC*)(VarsCmd.Pool + VarsCmd.PoolSize); + VarsCmd.PoolSize += VarsCmd.AllClumpsCount * sizeof(CLUMP_REC); + + //...then DSTOC... + VarsCmd.pDataspaceTOC = (DS_TOC_ENTRY*)(pData + pFileOffsets->DSTOC); + + //...then the dataspace itself + ALIGN_TO_MOD(VarsCmd.PoolSize, POOL_ALIGN); + VarsCmd.pDataspace = (VarsCmd.Pool + VarsCmd.PoolSize); + IOMapCmd.OffsetDS = (UWORD)((ULONG)(VarsCmd.pDataspace) - (ULONG)&(IOMapCmd)); + VarsCmd.PoolSize += VarsCmd.DataspaceSize; + + //init rest of MemMgr + VarsCmd.MemMgr.pDopeVectorArray = (DOPE_VECTOR *)(VarsCmd.pDataspace + DopeVectorOffset); + IOMapCmd.OffsetDVA = (UWORD)((ULONG)(VarsCmd.MemMgr.pDopeVectorArray) - (ULONG)&(IOMapCmd)); + VarsCmd.MemMgr.FreeHead = NOT_A_DS_ID; + + + if (VarsCmd.PoolSize > POOL_MAX_SIZE) + { + NXT_BREAK; + return (ERR_FILE); + } + + return (NO_ERR); +} + + +//!!! Recursive function +NXT_STATUS cCmdInflateDSDefaults(UBYTE* pDSDefaults, UWORD *pDefaultsOffset, DS_ELEMENT_ID DSElementID) +{ + NXT_STATUS Status = NO_ERR; + TYPE_CODE TypeCode; + UWORD i, Count; + UBYTE *pVal; + + NXT_ASSERT(cCmdIsDSElementIDSane(DSElementID)); + + TypeCode = cCmdDSType(DSElementID); + + if (TypeCode == TC_CLUSTER) + { + Count = cCmdClusterCount(DSElementID); + //Advance DSElementID to sub-type + DSElementID = INC_ID(DSElementID); + //Loop through sub-types, inflate recursively + for (i = 0; i < Count; i++) + { + Status = cCmdInflateDSDefaults(pDSDefaults, pDefaultsOffset, DSElementID); + if (IS_ERR(Status)) + return Status; + DSElementID = cCmdNextDSElement(DSElementID); + } + } + else + { + if (TypeCode == TC_ARRAY) + { + //Resolve pointer to DVIndex + pVal = VarsCmd.pDataspace + VarsCmd.pDataspaceTOC[DSElementID].DSOffset; + } + else + { + pVal = cCmdResolveDataArg(DSElementID, 0, NULL); + } + + //Check if the element has the "default default" + if (VarsCmd.pDataspaceTOC[DSElementID].Flags & DS_DEFAULT_DEFAULT) + { + //Fill element with the "default default" of zero + memset(pVal, 0, cCmdSizeOf(TypeCode)); + } + else + { + //Get default from stream + memmove(pVal, pDSDefaults + *pDefaultsOffset, cCmdSizeOf(TypeCode)); + *pDefaultsOffset += cCmdSizeOf(TypeCode); + } + } + + //!!! Currently will always return NO_ERR + return Status; +} + + +NXT_STATUS cCmdActivateProgram(UBYTE * pFileName) +{ + UWORD i, j; + UBYTE * pCursor; + + NXT_STATUS Status = NO_ERR; + PROG_FILE_OFFSETS FileOffsets; + + LOADER_STATUS LStatus; + ULONG DataSize; + UBYTE * pData; + ULONG pDataHolder; + UWORD DefaultsOffset; + + LStatus = pMapLoader->pFunc(OPENREADLINEAR, pFileName, (UBYTE*)(&pDataHolder), &DataSize); + pData = (UBYTE*)(pDataHolder); + + //If Loader returned error or bad file pointer, bail out + if (LOADER_ERR(LStatus) != SUCCESS || pData == NULL || DataSize == 0) + return (ERR_FILE); + + //Deactivate current program and re-initialize memory pool + cCmdDeactivateProgram(); + cCmdInitPool(); + + //Stash this program's handle since we hold it open while running + VarsCmd.ActiveProgHandle = LOADER_HANDLE(LStatus); + + //Stash this program's name for easy reference later + strncpy((PSZ)(VarsCmd.ActiveProgName), (PSZ)(pFileName), FILENAME_LENGTH + 1); + + //Consume activation record data stream. + //See TargettingVIs/NXT.PackAR.vi for data stream packing details + + //Read header portion of the file, calculating offsets and initializing VarsCmd + Status = cCmdReadFileHeader(pData, DataSize, &FileOffsets); + if (IS_ERR(Status)) + return Status; + + //Do some spot checks to make sure bad file contents didn't leave us with obviously insane VarsCmd contents + //!!! Should add alignment checks on these pointers to avoid data abort exceptions later + if (((UBYTE*)(VarsCmd.pCodespace) < pData) + || ((UBYTE*)(VarsCmd.pCodespace) >= (pData + DataSize)) + || ((UBYTE*)(VarsCmd.pAllClumps) < POOL_START) + || ((UBYTE*)(VarsCmd.pAllClumps) >= POOL_SENTINEL) + || ((UBYTE*)(VarsCmd.pDataspace) < POOL_START) + || ((UBYTE*)(VarsCmd.pDataspace) >= POOL_SENTINEL) + || (VarsCmd.DataspaceSize == 0) ) + { + NXT_BREAK; + return ERR_FILE; + } + + //Initialize CLUMP_RECs as contiguous list in RAM + pCursor = (pData + FileOffsets.Clumps); + for (i = 0; i < VarsCmd.AllClumpsCount; i++) + { + VarsCmd.pAllClumps[i].InitFireCount = *(UBYTE*)(pCursor + i * VM_FILE_CLUMP_REC_SIZE); + VarsCmd.pAllClumps[i].DependentCount = *(UBYTE*)(pCursor + (i * VM_FILE_CLUMP_REC_SIZE) + 1); + VarsCmd.pAllClumps[i].CodeStart = *(UWORD*)(pCursor + (i * VM_FILE_CLUMP_REC_SIZE) + 2); + + //Initialize remaining CLUMP_REC fields + VarsCmd.pAllClumps[i].PC = 0; + VarsCmd.pAllClumps[i].Priority = 20; + VarsCmd.pAllClumps[i].Link = NOT_A_CLUMP; + + //Activate any clumps with CurrFireCount of 0 + VarsCmd.pAllClumps[i].CurrFireCount = VarsCmd.pAllClumps[i].InitFireCount; + if (VarsCmd.pAllClumps[i].CurrFireCount == 0) + cCmdEnQClump(&(VarsCmd.RunQ), (CLUMP_ID)i); + } + + //Patch up dependents in separate pass (reuse of pCursor) + pCursor += VarsCmd.AllClumpsCount * VM_FILE_CLUMP_REC_SIZE; + for (i = 0; i < VarsCmd.AllClumpsCount; i++) + { + if (VarsCmd.pAllClumps[i].DependentCount > 0) + { + VarsCmd.pAllClumps[i].pDependents = (CLUMP_ID*)(pCursor); + + pCursor += (VarsCmd.pAllClumps[i].DependentCount * sizeof(CLUMP_ID)); + } + else + VarsCmd.pAllClumps[i].pDependents = NULL; + + //Patch up CodeEnd value based on CodeStart of next clump or last overall codeword + if (i < (VarsCmd.AllClumpsCount - 1)) + VarsCmd.pAllClumps[i].CodeEnd = VarsCmd.pAllClumps[i+1].CodeStart - 1; + else + VarsCmd.pAllClumps[i].CodeEnd = VarsCmd.CodespaceCount - 1; + + //Test for empty/insane clump code definitions + NXT_ASSERT(VarsCmd.pAllClumps[i].CodeStart < VarsCmd.pAllClumps[i].CodeEnd); + } + + //Programs with no active clumps constitutes an activation error + if (VarsCmd.RunQ.Head == NOT_A_CLUMP) + return (ERR_FILE); + + //Initialize dataspace with default values from file + //!!! This would be a good place to enforce check against potentially + // unsafe nested types (deeply nested types mean deep recursive calls) + DefaultsOffset = 0; + for (i = 0; i != NOT_A_DS_ID; i = cCmdNextDSElement(i)) + { + + Status = cCmdInflateDSDefaults(pData + FileOffsets.DSDefaults, &DefaultsOffset, i); + if (IS_ERR(Status)) + return Status; + } + + if ((DefaultsOffset != FileOffsets.DynamicDefaults) + || (DefaultsOffset + FileOffsets.DynamicDefaultsSize != FileOffsets.DSDefaultsSize)) + { + NXT_BREAK; + return (ERR_FILE); + } + + //Copy Dynamic defaults from file + memmove(VarsCmd.pDataspace + VarsCmd.DSStaticSize, pData + FileOffsets.DSDefaults + FileOffsets.DynamicDefaults, FileOffsets.DynamicDefaultsSize); + + //Verify the MemMgr ended up where we said it would + if ((UBYTE *)VarsCmd.MemMgr.pDopeVectorArray != VarsCmd.pDataspace + DV_ARRAY[0].Offset) + { + NXT_BREAK; + return (ERR_FILE); + } + + //Initialize message queues + for (i = 0; i < MESSAGE_QUEUE_COUNT; i++) + { + VarsCmd.MessageQueues[i].ReadIndex = 0; + VarsCmd.MessageQueues[i].WriteIndex = 0; + + for (j = 0; j < MESSAGES_PER_QUEUE; j++) + { + VarsCmd.MessageQueues[i].Messages[j] = NOT_A_DS_ID; + } + } + + if (cCmdVerifyMemMgr() != TRUE) + return (ERR_FILE); + + return (Status); +} + + +void cCmdDeactivateProgram() +{ + UBYTE i, tmp; + + //Wipe away all references into the pool and clear all run-time data + VarsCmd.pCodespace = NULL; + VarsCmd.CodespaceCount = 0; + + VarsCmd.pAllClumps = NULL; + VarsCmd.AllClumpsCount = 0; + + VarsCmd.DataspaceCount = 0; + VarsCmd.pDataspaceTOC = NULL; + VarsCmd.pDataspace = NULL; + VarsCmd.DataspaceSize = 0; + VarsCmd.DSStaticSize = 0; + + VarsCmd.MemMgr.Head = NOT_A_DS_ID; + VarsCmd.MemMgr.Tail = NOT_A_DS_ID; + VarsCmd.MemMgr.FreeHead = NOT_A_DS_ID; + VarsCmd.MemMgr.pDopeVectorArray = NULL; + + VarsCmd.RunQ.Head = NOT_A_CLUMP; + VarsCmd.RunQ.Tail = NOT_A_CLUMP; + VarsCmd.ScratchPC = 0; + VarsCmd.CallerClump = NOT_A_CLUMP; + + if (VarsCmd.ActiveProgHandle != NOT_A_HANDLE) + { + //Close handle that we've kept open for this program + pMapLoader->pFunc(CLOSE, &(VarsCmd.ActiveProgHandle), NULL, NULL); + VarsCmd.ActiveProgHandle = NOT_A_HANDLE; + + //Clear internal stashed name + memset(VarsCmd.ActiveProgName, 0, FILENAME_LENGTH + 1); + } + + //Close any files we had opened programatically + for (i = 0; i < MAX_HANDLES; i++) + { + //Copy i to tmp, because we pass a pointer to it to pFunc + tmp = i; + //Close file + if (*(VarsCmd.FileHandleTable[i]) != 0) + pMapLoader->pFunc(CLOSE, &tmp, NULL, NULL); + } + + //Clear FileHandleTable + memset(VarsCmd.FileHandleTable, 0, sizeof(VarsCmd.FileHandleTable)); + + return; +} + + +void cCmdResetDevices(void) +{ + UBYTE i; + + //Clear NXT button counts so 'bumped' will work on first run + for (i = 0; i < NO_OF_BTNS; i++) + { + pMapButton->BtnCnt[i].RelCnt = 0; + //Need to clear short and long counts too, because RelCnt depends on them. No known side effects. + pMapButton->BtnCnt[i].ShortRelCnt = 0; + pMapButton->BtnCnt[i].LongRelCnt = 0; + } + + for (i = 0; i < NO_OF_INPUTS; i++) + { + //Clear type and mode to defaults + pMapInput->Inputs[i].SensorType = NO_SENSOR; + pMapInput->Inputs[i].SensorMode = RAWMODE; + + //Reset input values to 0 prior to running (clear things like stale rotation counts) + pMapInput->Inputs[i].ADRaw = 0; + pMapInput->Inputs[i].SensorRaw = 0; + pMapInput->Inputs[i].SensorValue = 0; + + //Assert invalid data flag so future code is aware of these changes + pMapInput->Inputs[i].InvalidData = TRUE; + } + + for (i = 0; i < NO_OF_OUTPUTS; i++) + { + //Coast and reset all motor parameters + pMapOutPut->Outputs[i].Mode = 0; + pMapOutPut->Outputs[i].RegMode = REGULATION_MODE_IDLE; + pMapOutPut->Outputs[i].RunState = MOTOR_RUN_STATE_IDLE; + pMapOutPut->Outputs[i].Speed = 0; + pMapOutPut->Outputs[i].TachoLimit = 0; + pMapOutPut->Outputs[i].SyncTurnParameter = 0; + pMapOutPut->Outputs[i].Flags = UPDATE_MODE | UPDATE_SPEED | UPDATE_TACHO_LIMIT | UPDATE_RESET_COUNT | UPDATE_RESET_BLOCK_COUNT | UPDATE_RESET_ROTATION_COUNT; + } + + //Lowspeed init, INSERT CODE !!! + for (i = 0; i < NO_OF_LOWSPEED_COM_CHANNEL; i++) + { + pMapLowSpeed->InBuf[i].InPtr = 0; + pMapLowSpeed->InBuf[i].OutPtr = 0; + pMapLowSpeed->InBuf[i].BytesToRx = 0; + pMapLowSpeed->OutBuf[i].InPtr = 0; + pMapLowSpeed->OutBuf[i].OutPtr = 0; + if (pMapLowSpeed->ChannelState[i] != LOWSPEED_IDLE) + { + pMapLowSpeed->ChannelState[i] = LOWSPEED_DONE; + pMapLowSpeed->State |= (0x01<Head == NOT_A_CLUMP) + { + NXT_ASSERT(Queue->Tail == NOT_A_CLUMP); + + Queue->Head = NewClump; + Queue->Tail = NewClump; + } + //Otherwise, tack onto the end + else + { + VarsCmd.pAllClumps[Queue->Tail].Link = NewClump; + Queue->Tail = NewClump; + } + + return; +} + +//Dequeue specified clump +//Normal usage is to dequeue only from the head (i.e. pass Queue.Head as arg) +void cCmdDeQClump(CLUMP_Q * Queue, CLUMP_ID Clump) +{ + CLUMP_ID CurrID, LinkID; + + //Make sure Clump's ID is valid and is already on Queue + NXT_ASSERT(cCmdIsClumpIDSane(Clump)); + NXT_ASSERT(cCmdIsQSane(Queue) == TRUE); + NXT_ASSERT(cCmdIsClumpOnQ(Queue, Clump)); + + CurrID = Queue->Head; + + //If our clump is the head, move up the next and disconnect + if (CurrID == Clump) + { + Queue->Head = VarsCmd.pAllClumps[Clump].Link; + VarsCmd.pAllClumps[Clump].Link = NOT_A_CLUMP; + + //If we just removed the last clump, patch up the queue's tail + if (Queue->Head == NOT_A_CLUMP) + Queue->Tail = NOT_A_CLUMP; + } + //Else, look through rest of list looking for a link to our clump + else + { + do + { + LinkID = VarsCmd.pAllClumps[CurrID].Link; + + //If we find a link to our clump, patch up predecessor's link + if (VarsCmd.pAllClumps[CurrID].Link == Clump) + { + VarsCmd.pAllClumps[CurrID].Link = VarsCmd.pAllClumps[Clump].Link; + VarsCmd.pAllClumps[Clump].Link = NOT_A_CLUMP; + + //If we just removed the tail, patch tail + if (Clump == Queue->Tail) + Queue->Tail = CurrID; + } + + CurrID = LinkID; + } while (CurrID != NOT_A_CLUMP); + } + + return; +} + + +//Rotate head to tail and advance head for given Queue +void cCmdRotateQ(CLUMP_Q * Queue) +{ + CLUMP_ID CurrID; + CLUMP_REC * pClumpRec; + + //Make sure Queue is sane + NXT_ASSERT(cCmdIsQSane(Queue) == TRUE); + + //If queue has at least two clumps + if (Queue->Head != Queue->Tail) + { + CurrID = Queue->Head; + pClumpRec = &(VarsCmd.pAllClumps[CurrID]); + + //Disconnect head + Queue->Head = pClumpRec->Link; + pClumpRec->Link = NOT_A_CLUMP; + + //Reconnect head as tail + pClumpRec = &(VarsCmd.pAllClumps[Queue->Tail]); + pClumpRec->Link = CurrID; + Queue->Tail = CurrID; + + //Make sure we didn't make any really stupid mistakes + NXT_ASSERT(cCmdIsQSane(Queue) == TRUE); + } + + return; +} + + +UBYTE cCmdIsClumpOnQ(CLUMP_Q * Queue, CLUMP_ID Clump) +{ + CLUMP_ID CurrID; + + //Make sure Clump's ID is valid and is already on Queue + NXT_ASSERT(cCmdIsClumpIDSane(Clump)); + NXT_ASSERT(cCmdIsQSane(Queue) == TRUE); + + CurrID = Queue->Head; + + while (CurrID != NOT_A_CLUMP) + { + if (CurrID == Clump) + return TRUE; + + CurrID = VarsCmd.pAllClumps[CurrID].Link; + } + + return FALSE; +} + + +UBYTE cCmdIsQSane(CLUMP_Q * Queue) +{ + CLUMP_ID Head, Tail; + CLUMP_REC * pHead; + + if (Queue == NULL) + { + NXT_BREAK; + return FALSE; + } + + Head = Queue->Head; + Tail = Queue->Tail; + + if (Head == NOT_A_CLUMP && cCmdIsClumpIDSane(Tail)) + return FALSE; + + if (cCmdIsClumpIDSane(Head) && Tail == NOT_A_CLUMP) + return FALSE; + + if (cCmdIsClumpIDSane(Head) && cCmdIsClumpIDSane(Tail)) + { + pHead = &(VarsCmd.pAllClumps[Head]); + + //!!! More comprehensive queue tests could go here + + //Check for mislinked head if there are at least two queue members + if (Head != Tail && pHead->Link == NOT_A_CLUMP) + return FALSE; + } + + return TRUE; +} + +// +// Mutex queuing functions +// + +NXT_STATUS cCmdAcquireMutex(MUTEX_Q * Mutex, CLUMP_ID Clump) +{ + NXT_STATUS Status = NO_ERR; + + NXT_ASSERT(Mutex != NULL && cCmdIsClumpIDSane(Clump)); + + if (Mutex->Owner == NOT_A_CLUMP) + { + //Mutex is open, so just take it + Mutex->Owner = Clump; + + NXT_ASSERT(Mutex->WaitQ.Head == NOT_A_CLUMP && Mutex->WaitQ.Tail == NOT_A_CLUMP); + } + else + { + //Mutex is reserved by someone else, take self off RunQ and add to WaitQ + cCmdDeQClump(&(VarsCmd.RunQ), Clump); + cCmdEnQClump(&(Mutex->WaitQ), Clump); + Status = CLUMP_SUSPEND; + } + + NXT_ASSERT(cCmdIsQSane(&(Mutex->WaitQ))); + + return (Status); +} + + +NXT_STATUS cCmdReleaseMutex(MUTEX_Q * Mutex, CLUMP_ID Clump) +{ + NXT_ASSERT(Mutex != NULL); + //!!! don't actually need to pass in Owner clump, but provides nice error checking for now + // Might want to return an error/warning if we see a Release on an free mutex, though... + NXT_ASSERT(Clump != NOT_A_CLUMP && Mutex->Owner == Clump); + + //Always set new Owner to WaitQ's Head, since NOT_A_CLUMP means mutex is free + Mutex->Owner = Mutex->WaitQ.Head; + + if (Mutex->Owner != NOT_A_CLUMP) + { + cCmdDeQClump(&(Mutex->WaitQ), Mutex->Owner); + cCmdEnQClump(&(VarsCmd.RunQ), Mutex->Owner); + } + + NXT_ASSERT(cCmdIsQSane(&(Mutex->WaitQ))); + NXT_ASSERT(cCmdIsQSane(&(VarsCmd.RunQ))); + + return (NO_ERR); +} + + +NXT_STATUS cCmdSchedDependents(CLUMP_ID Clump, SWORD Begin, SWORD End) +{ + CLUMP_ID CurrDepClumpID; + SWORD i; + + //Begin and End specify range of CLUMP_IDs in dependent list to schedule + //If either equals -1, both should equal -1, and no dependents will be scheduled + //Else schedule specified subset offset from pDependents + + //Check for valid args + NXT_ASSERT(cCmdIsClumpIDSane(Clump)); + NXT_ASSERT((Begin >= 0 && End >= 0 && End < VarsCmd.pAllClumps[Clump].DependentCount) + || (Begin == -1 && End == -1)); + + //If non-empty range + if (Begin != -1 || End != -1) + { + //update dependents, scheduling if their CurrFireCount reaches 0 + for (i = Begin; i <= End; i++) + { + CurrDepClumpID = VarsCmd.pAllClumps[Clump].pDependents[i]; + + NXT_ASSERT(cCmdIsClumpIDSane(CurrDepClumpID)); + + VarsCmd.pAllClumps[CurrDepClumpID].CurrFireCount--; + + if (VarsCmd.pAllClumps[CurrDepClumpID].CurrFireCount == 0) + cCmdEnQClump(&(VarsCmd.RunQ), CurrDepClumpID); + } + } + + return (NO_ERR); +} + + +NXT_STATUS cCmdSchedDependent(CLUMP_ID Clump, CLUMP_ID TargetClump) +{ + //TargetClump specifies the clump number of the target to schedule explicitly. + + //Check for valid args + NXT_ASSERT(cCmdIsClumpIDSane(Clump)); + NXT_ASSERT(cCmdIsClumpIDSane(TargetClump)); + + VarsCmd.pAllClumps[TargetClump].CurrFireCount--; + if (VarsCmd.pAllClumps[TargetClump].CurrFireCount == 0) + cCmdEnQClump(&(VarsCmd.RunQ), TargetClump); + + return (NO_ERR); +} + + +UBYTE cCmdIsClumpIDSane(CLUMP_ID Clump) +{ + if (Clump < VarsCmd.AllClumpsCount) + return TRUE; + else + return FALSE; +} + + +// +// Memory pool management functions +// +void cCmdInitPool(void) +{ + ULONG i; + + //VarsCmd.Pool is a UBYTE pointer to ULONG array + //This was done to enforce portable alignment. + VarsCmd.Pool = (UBYTE*)(IOMapCmd.MemoryPool); + + for (i = 0; i < (POOL_MAX_SIZE / 4); i++) + ((SLONG*)(POOL_START))[i] = 0xDEADBEEF; + + VarsCmd.PoolSize = 0; +} + + +NXT_STATUS cCmdDSArrayAlloc(DS_ELEMENT_ID DSElementID, UWORD Offset, UWORD NewCount) +{ + NXT_STATUS Status = NO_ERR; + UWORD DVIndex; + UWORD OldCount; + UWORD i; + + NXT_ASSERT(cCmdIsDSElementIDSane(DSElementID)); + + //Only arrays are valid here + //!!! Recommended to upgrade NXT_ASSERT to ERR_INSTR return + NXT_ASSERT(cCmdDSType(DSElementID) == TC_ARRAY); + + DVIndex = cCmdGetDVIndex(DSElementID, Offset); + OldCount = DV_ARRAY[DVIndex].Count; + + Status = cCmdDVArrayAlloc(DVIndex, NewCount); + if (Status < NO_ERR) + return Status; + + if (OldCount > NewCount) + { + //Free dope vectors for sub-arrays. + for (i = NewCount; i < OldCount; i++) + { + Status = cCmdFreeSubArrayDopeVectors(INC_ID(DSElementID), ARRAY_ELEM_OFFSET(DVIndex, i)); + if (IS_ERR(Status)) + return Status; + } + } + else if (OldCount < NewCount) + { + //Alloc dope vectors for sub-arrays. Set up DVIndexes + for (i = OldCount; i < NewCount; i++) + { + Status = cCmdAllocSubArrayDopeVectors(INC_ID(DSElementID), ARRAY_ELEM_OFFSET(DVIndex, i)); + if (IS_ERR(Status)) + return Status; + } + } + + NXT_ASSERT(cCmdVerifyMemMgr()); + + return Status; +} + +NXT_STATUS cCmdDVArrayAlloc(DV_INDEX DVIndex, UWORD NewCount) +{ + NXT_STATUS Status = NO_ERR; + UBYTE *pData; + UWORD ArraySize, InplaceSize; + UWORD NextDVIndex; + UWORD OldCount; + + OldCount = DV_ARRAY[DVIndex].Count; + + if (OldCount == NewCount) + { + //Nothing to alloc. Return. + return Status; + } + else if (OldCount > NewCount) + { + //Already have the space. Shrink inplace. + DV_ARRAY[DVIndex].Count = NewCount; + return Status; + } + else // need to grow array + { + //Calculate new array size + ArraySize = NewCount * DV_ARRAY[DVIndex].ElemSize; + + //Try growing inplace + // If the Offset == NOT_AN_OFFSET then the array has never been allocated and can't grow inplace. + if (DV_ARRAY[DVIndex].Offset != NOT_AN_OFFSET) + { + //Get pointer to next dope vector in dataspace + if (DV_ARRAY[DVIndex].Link != NOT_A_DS_ID) + { + NextDVIndex = DV_ARRAY[DVIndex].Link; + InplaceSize = DV_ARRAY[NextDVIndex].Offset - DV_ARRAY[DVIndex].Offset; + } + else + { + //Last element in dataspace. + NXT_ASSERT(DVIndex == VarsCmd.MemMgr.Tail); + InplaceSize = VarsCmd.DataspaceSize - DV_ARRAY[DVIndex].Offset; + } + + if (ArraySize <= InplaceSize) + { + DV_ARRAY[DVIndex].Count = NewCount; + return Status; + } + } + + //Can't grow inplace, have to allocate new space + + //Make sure we properly align for type + //!!! This could also overflow memory (make PoolSize > POOL_MAX_SIZE) if we're within 3 bytes of the end. + // I don't think it matters because if it does happend, we'll trigger the ERR_MEM below and compact. + // During compaction, we'll reclaim these unused bytes. + //!!! Aligning beginning of ALL arrays to 4 byte address + ALIGN_TO_MOD(VarsCmd.PoolSize, SIZE_ULONG); + ALIGN_TO_MOD(VarsCmd.DataspaceSize, SIZE_ULONG); + + if (VarsCmd.PoolSize + ArraySize >= POOL_MAX_SIZE) + { + //Not enough memory available + return ERR_MEM; + } + + //Get data from end of pool + pData = VarsCmd.Pool + VarsCmd.PoolSize; + //Grow pool and dataspace + VarsCmd.PoolSize += ArraySize; + VarsCmd.DataspaceSize += ArraySize; + + //Move Array Data + memmove(pData, VarsCmd.pDataspace + DV_ARRAY[DVIndex].Offset, (UWORD)(DV_ARRAY[DVIndex].ElemSize * DV_ARRAY[DVIndex].Count)); + //!!! Clear mem so we make sure we don't reference stale data. Not strictly needed. + memset(VarsCmd.pDataspace + DV_ARRAY[DVIndex].Offset, 0xFF, (UWORD)(DV_ARRAY[DVIndex].ElemSize * DV_ARRAY[DVIndex].Count)); + + //Update dope vector + DV_ARRAY[DVIndex].Offset = pData - VarsCmd.pDataspace; + DV_ARRAY[DVIndex].Count = NewCount; + + //Move dope vector to end of MemMgr list + Status = cCmdMemMgrMoveToTail(DVIndex); + if (IS_ERR(Status)) + return Status; + + NXT_ASSERT(cCmdVerifyMemMgr()); + } + + return Status; +} + + +//!!! Recursive function +NXT_STATUS cCmdAllocSubArrayDopeVectors(DS_ELEMENT_ID DSElementID, UWORD Offset) +{ + // Walks a single array element to see if it contains arrays + // For any array it finds, a dope vector is allocated and the DVIndex is placed in the dataspace for the parent array. + // This is a non-recursive function. It only walks the immediate array element. + // DSElementID - ID of array sub-entry + // Offset - offset to array element in dataspace + NXT_STATUS Status = NO_ERR; + TYPE_CODE TypeCode; + DV_INDEX DVIndex; + UWORD i; + UWORD DVIndexOffset; //Offset to DVIndex field that points to the DopeVector from pDataspace + UWORD LoopCount = 1; + UWORD ElemSize; + + for (i = 0; i < LoopCount; i++) + { + TypeCode = cCmdDSType((DS_ELEMENT_ID)(DSElementID + i)); + if (TypeCode == TC_CLUSTER) + { + LoopCount += cCmdClusterCount(DSElementID); + } + else if (TypeCode == TC_ARRAY) + { + //!!! ElemSize is a static value, but we don't have anywhere we put it (another TOC sub-entry?) + // It'd be nice to not have to recalculate it. + ElemSize = cCmdCalcArrayElemSize((DS_ELEMENT_ID)(DSElementID + i)); + DVIndexOffset = VarsCmd.pDataspaceTOC[DSElementID + i].DSOffset + Offset; + Status = cCmdAllocDopeVector(&DVIndex, ElemSize, DVIndexOffset); + if (IS_ERR(Status)) + return Status; + + *((UWORD *)(VarsCmd.pDataspace + DVIndexOffset)) = DVIndex; + } + } + + return Status; +} + + +//!!! Recursive function +NXT_STATUS cCmdFreeSubArrayDopeVectors(DS_ELEMENT_ID DSElementID, UWORD Offset) +{ + // Walks a single array element to see if it contains arrays + // Frees all dope vectors associated with the array element. + // Recursively deletes sub-arrays. + // DSElementID - ID of array sub-entry + // Offset - offset to array element in dataspace + NXT_STATUS Status = NO_ERR; + TYPE_CODE TypeCode; + DV_INDEX DVIndex; + UWORD i, Count; + + TypeCode = cCmdDSType(DSElementID); + + if (TypeCode == TC_ARRAY) + { + DVIndex = cCmdGetDVIndex(DSElementID, Offset); + + NXT_ASSERT(DVIndex < DV_ARRAY[0].Count); + + Count = DV_ARRAY[DVIndex].Count; + //Recur on sub-elements + for (i = 0; i < Count; i++) + { + Status = cCmdFreeSubArrayDopeVectors(INC_ID(DSElementID), ARRAY_ELEM_OFFSET(DVIndex, i)); + if (IS_ERR(Status)) + return Status; + } + + //Free Dope Vector + Status = cCmdFreeDopeVector(DVIndex); + } + else if (TypeCode == TC_CLUSTER) + { + Count = cCmdClusterCount(DSElementID); + DSElementID = INC_ID(DSElementID); + //Recur on sub-elements + for (i = 0; i < Count; i++) + { + Status = cCmdFreeSubArrayDopeVectors((DS_ELEMENT_ID)(DSElementID + i), Offset); + if (IS_ERR(Status)) + return Status; + } + } + + return Status; +} + + +NXT_STATUS cCmdAllocDopeVector(DV_INDEX *pIndex, UWORD ElemSize, UWORD BackPtr) +{ + NXT_STATUS Status = NO_ERR; + + if (VarsCmd.MemMgr.FreeHead == NOT_A_DS_ID) + { + //No free DVs. Need to grow DopeVector array. + Status = cCmdGrowDopeVectorArray(DV_ARRAY_GROWTH_COUNT); + if (IS_ERR(Status)) + return Status; + } + + NXT_ASSERT(VarsCmd.MemMgr.FreeHead != NOT_A_DS_ID); + + //Remove DV from free list + *pIndex = VarsCmd.MemMgr.FreeHead; + VarsCmd.MemMgr.FreeHead = DV_ARRAY[VarsCmd.MemMgr.FreeHead].Link; + //Add DV to tail of MemMgr list + Status = cCmdMemMgrInsertAtTail(*pIndex); + + //Initialize values + DV_ARRAY[*pIndex].Offset = NOT_AN_OFFSET; + DV_ARRAY[*pIndex].ElemSize = ElemSize; + DV_ARRAY[*pIndex].Count = 0; + DV_ARRAY[*pIndex].BackPtr = BackPtr; + + NXT_ASSERT(cCmdVerifyMemMgr()); + + return Status; +} + +// +//cCmdFreeDopeVector() - Open up a spot in the DopeVectorArray for future use +// The DopeVectorArray doesn't shrink when arrays (and their dope vectors) are deleted. +// Instead they're pushed on the free list and the array stays the same size. +// Future allocations check the free list before resorting to cCmdGrowDopeVectorArray() +// +NXT_STATUS cCmdFreeDopeVector(DV_INDEX DVIndex) +{ + NXT_STATUS Status = NO_ERR; + DV_INDEX i; + + //Bounds check + NXT_ASSERT(DVIndex < DV_ARRAY[0].Count); + + //Reset dope vector fields + DV_ARRAY[DVIndex].Count = 0; + DV_ARRAY[DVIndex].ElemSize = 0; + DV_ARRAY[DVIndex].Offset = NOT_AN_OFFSET; + DV_ARRAY[DVIndex].BackPtr = NOT_AN_OFFSET; + + //Remove from MemMgr list + if (DVIndex == VarsCmd.MemMgr.Head) + { + VarsCmd.MemMgr.Head = DV_ARRAY[DVIndex].Link; + } + else + { + //Walk MemMgr list to find previous. + //!!! Could speed this up if MemMgr list were doubly linked + for (i = VarsCmd.MemMgr.Head; i != NOT_A_DS_ID; i = DV_ARRAY[i].Link) + { + if (DV_ARRAY[i].Link == DVIndex) + { + DV_ARRAY[i].Link = DV_ARRAY[DVIndex].Link; + if (DVIndex == VarsCmd.MemMgr.Tail) + VarsCmd.MemMgr.Tail = i; + break; + } + } + //Make sure we found the previous DV, otherwise this DV was not in the the list (already freed?) + NXT_ASSERT(i != NOT_A_DS_ID); + } + + //Push on to free list + DV_ARRAY[DVIndex].Link = VarsCmd.MemMgr.FreeHead; + VarsCmd.MemMgr.FreeHead = DVIndex; + + NXT_ASSERT(cCmdVerifyMemMgr()); + + return Status; +} + +// +//cCmdGrowDopeVectorArray() - expand DopeVectorArray to be able to track more dataspace arrays +// +NXT_STATUS cCmdGrowDopeVectorArray(UWORD NewNodesCount) +{ + NXT_STATUS Status = NO_ERR; + UWORD ArraySize; + UWORD OldCount, NewCount, i; + UBYTE * pData; + + NXT_ASSERT(cCmdVerifyMemMgr()); + + OldCount = DV_ARRAY[0].Count; + NewCount = OldCount + NewNodesCount; + NXT_ASSERT(NewCount > OldCount); + + ArraySize = DV_ARRAY[0].ElemSize * NewCount; + + //!!! Aligning beginning of ALL arrays to 4 byte address + ALIGN_TO_MOD(VarsCmd.PoolSize, SIZE_ULONG); + ALIGN_TO_MOD(VarsCmd.DataspaceSize, SIZE_ULONG); + + if (VarsCmd.PoolSize + ArraySize >= POOL_MAX_SIZE) + { + //Not enough memory available + return ERR_MEM; + } + + //Get data from end of pool + pData = VarsCmd.Pool + VarsCmd.PoolSize; + //Grow pool and dataspace + VarsCmd.PoolSize += ArraySize; + VarsCmd.DataspaceSize += ArraySize; + + //Move DopeVector Array + memmove(pData, (UBYTE *)VarsCmd.MemMgr.pDopeVectorArray, (UWORD)(DV_ARRAY[0].ElemSize * DV_ARRAY[0].Count)); + + //Update MemMgr pointer + VarsCmd.MemMgr.pDopeVectorArray = (DOPE_VECTOR *)pData; + IOMapCmd.OffsetDVA = (UWORD)((ULONG)(VarsCmd.MemMgr.pDopeVectorArray) - (ULONG)&(IOMapCmd)); + + //Update dope vector + DV_ARRAY[0].Offset = pData - VarsCmd.pDataspace; + DV_ARRAY[0].Count = NewCount; + + //Add new DopeVectors to free list + //Push in reverse order so they get popped in order (mostly for ease of debugging) + for (i = NewCount - 1; i >= OldCount; i--) + { + DV_ARRAY[i].Offset = 0xFFFF; + DV_ARRAY[i].ElemSize = 0; + DV_ARRAY[i].Count = 0; + DV_ARRAY[i].BackPtr = 0xFFFF; + DV_ARRAY[i].Link = VarsCmd.MemMgr.FreeHead; + VarsCmd.MemMgr.FreeHead = i; + } + + //Move dope vector to end of MemMgr list + Status = cCmdMemMgrMoveToTail(0); + + NXT_ASSERT(cCmdVerifyMemMgr()); + + return Status; +} + +NXT_STATUS cCmdCompactDopeVectorArray(void) +{ + //!!! Not implemented. Needs BackPtr support. + NXT_BREAK; + return ERR_ARG; +} + + +UWORD cCmdCalcArrayElemSize(DS_ELEMENT_ID DSElementID) +{ + TYPE_CODE TypeCode; + UWORD SizeOfType; + UWORD i; + UWORD LoopCount = 1; + UWORD Size = 0; + UWORD Alignment = 0; + + NXT_ASSERT(cCmdDSType(DSElementID) == TC_ARRAY); + + DSElementID = INC_ID(DSElementID); + for (i = 0; i < LoopCount; i++) + { + TypeCode = cCmdDSType((DS_ELEMENT_ID)(DSElementID + i)); + if (TypeCode == TC_CLUSTER) + { + LoopCount += cCmdClusterCount((DS_ELEMENT_ID)(DSElementID + i)); + } + else + { + SizeOfType = cCmdSizeOf(TypeCode); + ALIGN_TO_MOD(Size, SizeOfType); + Size += SizeOfType; + if (SizeOfType > Alignment) + Alignment = SizeOfType; + } + } + ALIGN_TO_MOD(Size, Alignment); + + return Size; +} + + +NXT_STATUS cCmdMemMgrMoveToTail(DV_INDEX DVIndex) +{ + DV_INDEX i; + + //Bounds check + NXT_ASSERT(DVIndex < DV_ARRAY[0].Count); + + //Short circut if its already at the tail + if (DVIndex == VarsCmd.MemMgr.Tail) + return NO_ERR; + + if (DVIndex == VarsCmd.MemMgr.Head) + VarsCmd.MemMgr.Head = DV_ARRAY[DVIndex].Link; + else + { + //Walk MemMgr list to find previous. + //!!! Could speed this up if MemMgr list were doubly linked + for (i = VarsCmd.MemMgr.Head; i != NOT_A_DS_ID; i = DV_ARRAY[i].Link) + { + if (DV_ARRAY[i].Link == DVIndex) + { + DV_ARRAY[i].Link = DV_ARRAY[DVIndex].Link; + break; + } + } + //Make sure we found the previous DV, otherwise this DV was not in the the list + NXT_ASSERT(i != NOT_A_DS_ID); + } + + DV_ARRAY[DVIndex].Link = NOT_A_DS_ID; + DV_ARRAY[VarsCmd.MemMgr.Tail].Link = DVIndex; + VarsCmd.MemMgr.Tail = DVIndex; + + NXT_ASSERT(cCmdVerifyMemMgr()); + + return NO_ERR; +} + + +NXT_STATUS cCmdMemMgrInsertAtTail(DV_INDEX DVIndex) +{ + //Bounds check + NXT_ASSERT(DVIndex < DV_ARRAY[0].Count); + + DV_ARRAY[VarsCmd.MemMgr.Tail].Link = DVIndex; + VarsCmd.MemMgr.Tail = DVIndex; + DV_ARRAY[DVIndex].Link = NOT_A_DS_ID; + + NXT_ASSERT(cCmdVerifyMemMgr()); + + return NO_ERR; +} + + +UBYTE cCmdVerifyMemMgr() +{ + DV_INDEX i; + UWORD CurrOffset = 0; + UWORD PrevOffset = 0; + UWORD DVCount = 0; + + //Make sure the MemMgr list is properly sorted in ascending offset order + for (i = VarsCmd.MemMgr.Head; i != NOT_A_DS_ID; i = DV_ARRAY[i].Link) + { + CurrOffset = DV_ARRAY[i].Offset; + + if (CurrOffset != 0xFFFF) + { + if (PrevOffset > CurrOffset) + return FALSE; + + PrevOffset = CurrOffset; + } + + if (DV_ARRAY[i].Link == NOT_A_DS_ID && i != VarsCmd.MemMgr.Tail) + return FALSE; + + DVCount++; + } + + for (i = VarsCmd.MemMgr.FreeHead; i != NOT_A_DS_ID; i = DV_ARRAY[i].Link) + { + DVCount++; + } + + //Make sure the # of dope vectors = # used + # free + if (DVCount != DV_ARRAY[0].Count) + return FALSE; + + return TRUE; +} + + +NXT_STATUS cCmdDSCompact(void) +{ + NXT_STATUS Status = NO_ERR; + + DV_INDEX CurrIndex; + UWORD NewOffset; + UWORD CurrOffset; + UWORD Size; + UWORD DeltaDSSize; + UWORD TempOffset, TempSize; + +#if VM_BENCHMARK + ULONG StartTime, TotalTime; + + VarsCmd.CompactionCount++; + VarsCmd.LastCompactionTick = IOMapCmd.Tick - VarsCmd.StartTick; + + StartTime = dTimerRead(); +#endif + + NXT_ASSERT(cCmdVerifyMemMgr()); + + NewOffset = VarsCmd.DSStaticSize; + for (CurrIndex = VarsCmd.MemMgr.Head; CurrIndex != NOT_A_DS_ID; CurrIndex = DV_ARRAY[CurrIndex].Link) + { + //Align NewOffset for array to 4 byte address. + ALIGN_TO_MOD(NewOffset, SIZE_ULONG); + + CurrOffset = DV_ARRAY[CurrIndex].Offset; + if (CurrOffset != NOT_AN_OFFSET) + { + Size = DV_ARRAY[CurrIndex].ElemSize * DV_ARRAY[CurrIndex].Count; + if (CurrOffset != NewOffset) + { + NXT_ASSERT(NewOffset < CurrOffset); + memmove(VarsCmd.pDataspace + NewOffset, VarsCmd.pDataspace + CurrOffset, Size); + + // Clear mem to make stale data references more obvious while debugging. + // Correct for overlapping memory regions (make sure we don't clear what we just moved). + //!!! Clearing step not strictly necessary, so it could be optimized out + if (NewOffset + Size > CurrOffset) + { + TempOffset = NewOffset + Size; + TempSize = Size - (TempOffset - CurrOffset); + } + else + { + TempOffset = CurrOffset; + TempSize = Size; + } + memset(VarsCmd.pDataspace + TempOffset, 0xFF, TempSize); + + //Update pDopeVectorArray if we move the dope vector array + if (CurrIndex == 0) + { + VarsCmd.MemMgr.pDopeVectorArray = (DOPE_VECTOR *)(VarsCmd.pDataspace + NewOffset); + IOMapCmd.OffsetDVA = (UWORD)((ULONG)(VarsCmd.MemMgr.pDopeVectorArray) - (ULONG)&(IOMapCmd)); + } + + //Update offset in DV Array + DV_ARRAY[CurrIndex].Offset = NewOffset; + } + + NewOffset += Size; + } + } + + DeltaDSSize = VarsCmd.DataspaceSize - NewOffset; + + VarsCmd.PoolSize -= DeltaDSSize; + VarsCmd.DataspaceSize -= DeltaDSSize; + + NXT_ASSERT(cCmdVerifyMemMgr()); + +#if VM_BENCHMARK + TotalTime = dTimerRead() - StartTime; + + if (TotalTime > VarsCmd.MaxCompactionTime) + VarsCmd.MaxCompactionTime = TotalTime; +#endif + + return Status; +} + + +// +// Message Queue functions +// + +NXT_STATUS cCmdMessageWrite(UWORD QueueID, UBYTE * pData, UWORD Length) +{ + NXT_STATUS Status = NO_ERR; + + if (pData == NULL) + return ERR_ARG; + + if (QueueID >= MESSAGE_QUEUE_COUNT) + return ERR_INVALID_QUEUE; + + if (VarsCmd.ActiveProgHandle == NOT_A_HANDLE) + return ERR_NO_PROG; + + //Can't accept oversize messages because we treat them as strings (truncation would remove null termination) + if (Length > MAX_MESSAGE_SIZE) + return ERR_INVALID_SIZE; + + if (IS_DV_INDEX_SANE(GET_WRITE_MSG(QueueID))) + { + //A message is already there, the queue is full + NXT_ASSERT(VarsCmd.MessageQueues[QueueID].WriteIndex == VarsCmd.MessageQueues[QueueID].ReadIndex); + + //Bump read index, drop existing message to make room for our new incoming message + VarsCmd.MessageQueues[QueueID].ReadIndex = (VarsCmd.MessageQueues[QueueID].ReadIndex + 1) % MESSAGES_PER_QUEUE; + } + else + { + //Allocate dope vector for message + Status = cCmdAllocDopeVector(&GET_WRITE_MSG(QueueID), 1, NOT_AN_OFFSET); + if (IS_ERR(Status)) + return Status; + } + + //Allocate storage for message + Status = cCmdDVArrayAlloc(GET_WRITE_MSG(QueueID), Length); + if (IS_ERR(Status)) + { + //Clear the dope vector for the message, since we're unable to put a message there. + cCmdFreeDopeVector(GET_WRITE_MSG(QueueID)); + SET_WRITE_MSG(QueueID, NOT_A_DS_ID); + return Status; + } + + //Copy message + memmove(cCmdDVPtr(GET_WRITE_MSG(QueueID)), pData, Length); + + //Advance write index + VarsCmd.MessageQueues[QueueID].WriteIndex = (VarsCmd.MessageQueues[QueueID].WriteIndex + 1) % MESSAGES_PER_QUEUE; + + return Status; +} + + +NXT_STATUS cCmdMessageGetSize(UWORD QueueID, UWORD * Size) +{ + DV_INDEX ReadDVIndex; + + if (Size == NULL) + return (ERR_ARG); + + if (VarsCmd.ActiveProgHandle == NOT_A_HANDLE) + { + *Size = 0; + return (ERR_NO_PROG); + } + + if (QueueID >= MESSAGE_QUEUE_COUNT) + { + *Size = 0; + return (ERR_INVALID_QUEUE); + } + + ReadDVIndex = GET_READ_MSG(QueueID); + + if (IS_DV_INDEX_SANE(ReadDVIndex)) + { + *Size = (DV_ARRAY[ReadDVIndex].Count); + return (NO_ERR); + } + else + { + *Size = 0; + return (STAT_MSG_EMPTY_MAILBOX); + } +} + + +NXT_STATUS cCmdMessageRead(UWORD QueueID, UBYTE * pBuffer, UWORD Length, UBYTE Remove) +{ + NXT_STATUS Status = NO_ERR; + DV_INDEX ReadDVIndex; + + if (pBuffer == NULL) + return (ERR_ARG); + + if (VarsCmd.ActiveProgHandle == NOT_A_HANDLE) + return (ERR_NO_PROG); + + if (QueueID >= MESSAGE_QUEUE_COUNT) + return (ERR_INVALID_QUEUE); + + ReadDVIndex = GET_READ_MSG(QueueID); + + if (IS_DV_INDEX_SANE(ReadDVIndex)) + { + //If Buffer doesn't have room for the entire message, + //don't risk incomplete string floating around + if (Length < DV_ARRAY[ReadDVIndex].Count) + return (ERR_INVALID_SIZE); + + //Copy message + memmove(pBuffer, cCmdDVPtr(ReadDVIndex), DV_ARRAY[ReadDVIndex].Count); + + if (Remove) + { + //Free memory used by message + Status = cCmdFreeDopeVector(ReadDVIndex); + if (IS_ERR(Status)) + return Status; + + SET_READ_MSG(QueueID, NOT_A_DS_ID); + + //Advance read index + VarsCmd.MessageQueues[QueueID].ReadIndex = (VarsCmd.MessageQueues[QueueID].ReadIndex + 1) % MESSAGES_PER_QUEUE; + } + } + else + { + //No message to read, message Queue is empty + NXT_ASSERT(VarsCmd.MessageQueues[QueueID].ReadIndex == VarsCmd.MessageQueues[QueueID].WriteIndex); + + return (STAT_MSG_EMPTY_MAILBOX); + } + + return Status; +} + + +// +// Dataspace Support functions +// + +UBYTE cCmdIsDSElementIDSane(DS_ELEMENT_ID Index) +{ + if (Index < VarsCmd.DataspaceCount) + return TRUE; + else + return FALSE; +} + +TYPE_CODE cCmdDSType(DS_ELEMENT_ID DSElementID) +{ + NXT_ASSERT(cCmdIsDSElementIDSane(DSElementID)); + + return (VarsCmd.pDataspaceTOC[DSElementID].TypeCode); +} + + +void * cCmdResolveDataArg(DATA_ARG DataArg, UWORD Offset, TYPE_CODE * TypeCode) +{ + UBYTE ModuleID; + UWORD FieldID; + void * ret_val = NULL; + + // + //!!! DATA_ARG masking system only for internal c_cmd use! + // All normal bytecode arguments should go through top if() block. + // + + if (DataArg <= (DATA_ARG)(DATA_ARG_ADDR_MASK) ) + { + NXT_ASSERT(cCmdIsDSElementIDSane(DataArg)); + ret_val = cCmdDSPtr(DataArg, Offset); + if (TypeCode) + *TypeCode = VarsCmd.pDataspaceTOC[DataArg].TypeCode; + } + else if (DataArg & ~((DATA_ARG)(DATA_ARG_ADDR_MASK))) + { + //DataArg refers to a field in the IO map + ModuleID = (UBYTE)((DataArg >> 9) & 0x001F); + FieldID = (UWORD)(DataArg & 0x01FF); + + //!!! Preliminary bounds check -- still could allow invalid combos through + if (ModuleID > MOD_OUTPUT || FieldID >= IO_OUT_FIELD_COUNT) + { + NXT_BREAK; + return NULL; + } + + ret_val = IO_PTRS[ModuleID][FieldID]; + if (TypeCode) + *TypeCode = IO_TYPES[ModuleID][FieldID]; + } + + //!!! Caller beware! If DataArg isn't sane, ret_val may be out of range or NULL! + return ret_val; +} + +void cCmdSetVal(void * pVal, TYPE_CODE TypeCode, ULONG NewVal) +{ + + if (pVal) + { + switch (TypeCode) + { + case TC_ULONG: + case TC_SLONG: + { + *(ULONG*)pVal = NewVal; + } + break; + + case TC_UWORD: + case TC_SWORD: + { + *(UWORD*)pVal = (UWORD)NewVal; + } + break; + + case TC_UBYTE: + case TC_SBYTE: + { + *(UBYTE*)pVal = (UBYTE)NewVal; + } + break; + } + } + + return; +} + + +ULONG cCmdGetVal(void * pVal, TYPE_CODE TypeCode) +{ + if (pVal) + { + switch (TypeCode) + { + case TC_ULONG: + { + return (ULONG)(*(ULONG*)pVal); + } + + case TC_SLONG: + { + return (SLONG)(*(SLONG*)pVal); + } + + case TC_UWORD: + { + return (UWORD)(*(UWORD*)pVal); + } + + case TC_SWORD: + { + return (SWORD)(*(SWORD*)pVal); + } + + case TC_UBYTE: + { + return (UBYTE)(*(UBYTE*)pVal); + } + + case TC_SBYTE: + { + return (SBYTE)(*(SBYTE*)pVal); + } + + default: + break; + } + } + + //!!! Default return value places responsibility on caller to use this function wisely + return 0; +} + + +UWORD cCmdSizeOf(TYPE_CODE TypeCode) +{ + //!!! Why not use a lookup table? No particular reason... + switch(TypeCode) + { + case TC_ULONG: + return SIZE_ULONG; + case TC_SLONG: + return SIZE_SLONG; + case TC_UWORD: + return SIZE_UWORD; + case TC_SWORD: + return SIZE_SWORD; + case TC_UBYTE: + return SIZE_UBYTE; + case TC_SBYTE: + return SIZE_SBYTE; + case TC_MUTEX: + return SIZE_MUTEX; + case TC_ARRAY: + //Arrays have a 2-byte structure in the dataspace for the DVIndex + return SIZE_UWORD; + case TC_CLUSTER: + default: + return 0; + } +} + + +void* cCmdDSPtr(DS_ELEMENT_ID DSElementID, UWORD Offset) +{ + void * pDSItem; + DV_INDEX DVIndex; + TYPE_CODE TypeCode; + + NXT_ASSERT(cCmdIsDSElementIDSane(DSElementID)); + + TypeCode = cCmdDSType(DSElementID); + if (TypeCode == TC_ARRAY) + { + //!!! Empty arrays return NULL. + if (cCmdArrayCount(DSElementID, Offset) == 0) + pDSItem = NULL; + else + { + DVIndex = cCmdGetDVIndex(DSElementID, Offset); + pDSItem = (VarsCmd.pDataspace + DV_ARRAY[DVIndex].Offset); + } + } + else if (TypeCode == TC_CLUSTER) + { + NXT_ASSERT(cCmdClusterCount(DSElementID) != 0) + + //Returning pointer to the first element in the cluster + pDSItem = cCmdDSPtr(INC_ID(DSElementID), Offset); + } + else + pDSItem = (VarsCmd.pDataspace + VarsCmd.pDataspaceTOC[DSElementID].DSOffset + Offset); + + NXT_ASSERT((UBYTE*)pDSItem < POOL_SENTINEL); + + return pDSItem; +} + +void* cCmdDVPtr(DV_INDEX DVIndex) +{ + NXT_ASSERT(IS_DV_INDEX_SANE(DVIndex)); + return (VarsCmd.pDataspace + DV_ARRAY[DVIndex].Offset); +} + + +//!!! Recursive function +DS_ELEMENT_ID cCmdNextDSElement(DS_ELEMENT_ID CurrID) +{ + DS_ELEMENT_ID NextID; + TYPE_CODE CurrType; + UWORD ClusterCount, i; + + NXT_ASSERT(cCmdIsDSElementIDSane(CurrID)); + + NextID = CurrID + 1; + + if (!cCmdIsDSElementIDSane(NextID)) + return NOT_A_DS_ID; + + CurrType = cCmdDSType(CurrID); + + if (CurrType == TC_ARRAY) + { + //Arrays contain two elements. Advance past the second one. + NextID = cCmdNextDSElement(NextID); + } + else if (CurrType == TC_CLUSTER) + { + ClusterCount = cCmdClusterCount(CurrID); + for (i = 0; i < ClusterCount; i++) + { + NextID = cCmdNextDSElement(NextID); + } + } + + return NextID; +} + + +//!!! Recursive function +UBYTE cCmdCompareDSType(DS_ELEMENT_ID DSElementID1, DS_ELEMENT_ID DSElementID2) +{ + TYPE_CODE Type1, Type2; + UWORD i, Count1, Count2; + + Type1 = cCmdDSType(DSElementID1); + Type2 = cCmdDSType(DSElementID2); + + if (Type1 != Type2) + return FALSE; + + if (Type1 == TC_CLUSTER) + { + Count1 = cCmdClusterCount(DSElementID1); + Count2 = cCmdClusterCount(DSElementID2); + + if(Count1 != Count2) + return FALSE; + + DSElementID1 = INC_ID(DSElementID1); + DSElementID2 = INC_ID(DSElementID2); + + for (i = 0; i < Count1; i++) + { + if (!cCmdCompareDSType(DSElementID1, DSElementID2)) + return FALSE; + + DSElementID1 = cCmdNextDSElement(DSElementID1); + DSElementID2 = cCmdNextDSElement(DSElementID2); + } + } + else if (Type1 == TC_ARRAY) + { + if (!cCmdCompareDSType(INC_ID(DSElementID1), INC_ID(DSElementID2))) + return FALSE; + } + + return TRUE; +} + + +//!!! Recursive function +UWORD cCmdCalcFlattenedSize(DS_ELEMENT_ID DSElementID, UWORD Offset) +{ + UWORD Size = 0; + TYPE_CODE TypeCode; + DV_INDEX DVIndex; + UWORD i; + UWORD Count; + + TypeCode = cCmdDSType(DSElementID); + + if (TypeCode == TC_ARRAY) + { + DVIndex = cCmdGetDVIndex(DSElementID, Offset); + + DSElementID = INC_ID(DSElementID); + TypeCode = cCmdDSType(DSElementID); + + if (!IS_AGGREGATE_TYPE(TypeCode)) + { + //Short circuit recursive calculation if our array sub-type is a scalar + Size += DV_ARRAY[DVIndex].ElemSize * DV_ARRAY[DVIndex].Count; + } + else + { + //If the sub type is an aggregate type, then it can contain arrays, so we have to recur + for (i = 0; i < DV_ARRAY[DVIndex].Count; i++) + { + Size += cCmdCalcFlattenedSize(DSElementID, ARRAY_ELEM_OFFSET(DVIndex, i)); + } + } + } + else if (TypeCode == TC_CLUSTER) + { + Count = cCmdClusterCount(DSElementID); + + DSElementID = INC_ID(DSElementID); + for (i = 0; i < Count; i++) + { + Size += cCmdCalcFlattenedSize(DSElementID, Offset); + DSElementID = cCmdNextDSElement(DSElementID); + } + } + else //Scalar + { + Size += cCmdSizeOf(TypeCode); + } + return Size; +} + + +//!!! Recursive function +NXT_STATUS cCmdFlattenToByteArray(UBYTE * pByteArray, UWORD * pByteOffset, DS_ELEMENT_ID DSElementID, UWORD Offset) +{ + NXT_STATUS Status = NO_ERR; + TYPE_CODE TypeCode; + DV_INDEX DVIndex; + UWORD i; + UWORD Count; + UBYTE *pVal; + + TypeCode = cCmdDSType(DSElementID); + + if (TypeCode == TC_ARRAY) + { + DVIndex = cCmdGetDVIndex(DSElementID, Offset); + Count = DV_ARRAY[DVIndex].Count; + + DSElementID = INC_ID(DSElementID); + TypeCode = cCmdDSType(DSElementID); + if (!IS_AGGREGATE_TYPE(TypeCode)) + { + //Short circuit recursive calculation if our array sub-type is a scalar + Count = DV_ARRAY[DVIndex].ElemSize * DV_ARRAY[DVIndex].Count; + memmove((pByteArray + *pByteOffset), (VarsCmd.pDataspace + DV_ARRAY[DVIndex].Offset), Count); + *pByteOffset += Count; + } + else + { + //If the sub type is an aggregate type, then it can contain arrays, so we have to recur + for (i = 0; i < Count; i++) + { + cCmdFlattenToByteArray(pByteArray, pByteOffset, DSElementID, ARRAY_ELEM_OFFSET(DVIndex, i)); + } + } + } + else if (TypeCode == TC_CLUSTER) + { + Count = cCmdClusterCount(DSElementID); + + DSElementID = INC_ID(DSElementID); + for (i = 0; i < Count; i++) + { + cCmdFlattenToByteArray(pByteArray, pByteOffset, DSElementID, Offset); + DSElementID = cCmdNextDSElement(DSElementID); + } + } + else //Scalar + { + pVal = cCmdResolveDataArg(DSElementID, Offset, NULL); + Count = cCmdSizeOf(TypeCode); + + memmove((pByteArray + *pByteOffset), pVal, Count); + *pByteOffset += Count; + } + + return Status; +} + +NXT_STATUS cCmdUnflattenFromByteArray(UBYTE * pByteArray, UWORD * pByteOffset, DS_ELEMENT_ID DSElementID, UWORD Offset) +{ + NXT_STATUS Status = NO_ERR; + TYPE_CODE TypeCode; + DV_INDEX DVIndex; + UWORD i; + UWORD Count; + UBYTE *pVal; + + TypeCode = cCmdDSType(DSElementID); + + if (TypeCode == TC_ARRAY) + { + DVIndex = cCmdGetDVIndex(DSElementID, Offset); + Count = DV_ARRAY[DVIndex].Count; + + DSElementID = INC_ID(DSElementID); + TypeCode = cCmdDSType(DSElementID); + if (!IS_AGGREGATE_TYPE(TypeCode)) + { + //Short circuit recursive calculation if our array sub-type is a scalar + Count = DV_ARRAY[DVIndex].ElemSize * DV_ARRAY[DVIndex].Count; + memmove((VarsCmd.pDataspace + DV_ARRAY[DVIndex].Offset), (pByteArray + *pByteOffset), Count); + *pByteOffset += Count; + } + else + { + //If the sub type is an aggregate type, then it can contain arrays, so we have to recur + for (i = 0; i < Count; i++) + { + cCmdUnflattenFromByteArray(pByteArray, pByteOffset, DSElementID, ARRAY_ELEM_OFFSET(DVIndex, i)); + } + } + } + else if (TypeCode == TC_CLUSTER) + { + Count = cCmdClusterCount(DSElementID); + + DSElementID = INC_ID(DSElementID); + for (i = 0; i < Count; i++) + { + cCmdUnflattenFromByteArray(pByteArray, pByteOffset, DSElementID, Offset); + DSElementID = cCmdNextDSElement(DSElementID); + } + } + else //Scalar + { + pVal = cCmdResolveDataArg(DSElementID, Offset, NULL); + Count = cCmdSizeOf(TypeCode); + + memmove(pVal, (pByteArray + *pByteOffset), Count); + *pByteOffset += Count; + } + + return Status; +} + + +UWORD cCmdClusterCount(DS_ELEMENT_ID DSElementID) +{ + UWORD ClusterCount; + + NXT_ASSERT(cCmdIsDSElementIDSane(DSElementID)); + NXT_ASSERT(cCmdDSType(DSElementID) == TC_CLUSTER); + + ClusterCount = VarsCmd.pDataspaceTOC[DSElementID].DSOffset; + + return ClusterCount; +} + + +UWORD cCmdGetDVIndex(DS_ELEMENT_ID DSElementID, UWORD Offset) +{ + UWORD DVIndex; + + NXT_ASSERT(cCmdDSType(DSElementID) == TC_ARRAY); + + DVIndex = *(UWORD *)(VarsCmd.pDataspace + VarsCmd.pDataspaceTOC[DSElementID].DSOffset + Offset); + + //Make sure we're returning a valid DVIndex + NXT_ASSERT(DVIndex != 0 && DVIndex < DV_ARRAY[0].Count); + + return DVIndex; +} + + +UWORD cCmdArrayCount(DS_ELEMENT_ID DSElementID, UWORD Offset) +{ + DV_INDEX DVIndex; + + NXT_ASSERT(cCmdIsDSElementIDSane(DSElementID)); + NXT_ASSERT(cCmdDSType(DSElementID) == TC_ARRAY); + + DVIndex = cCmdGetDVIndex(DSElementID, Offset); + return DV_ARRAY[DVIndex].Count; +} + +TYPE_CODE cCmdArrayType(DS_ELEMENT_ID DSElementID) +{ + TYPE_CODE TypeCode; + + NXT_ASSERT(cCmdIsDSElementIDSane(DSElementID)); + NXT_ASSERT(cCmdIsDSElementIDSane(INC_ID(DSElementID))); + NXT_ASSERT(cCmdDSType(DSElementID) == TC_ARRAY); + + TypeCode = VarsCmd.pDataspaceTOC[DSElementID + 1].TypeCode; + + return TypeCode; +} + + +DS_ELEMENT_ID cCmdGetDataspaceCount(void) +{ + return (VarsCmd.DataspaceCount); +} + + +CODE_INDEX cCmdGetCodespaceCount(CLUMP_ID Clump) +{ + if (Clump == NOT_A_CLUMP) + return (VarsCmd.CodespaceCount); + else + { + NXT_ASSERT(cCmdIsClumpIDSane(Clump)); + return (VarsCmd.pAllClumps[Clump].CodeEnd - VarsCmd.pAllClumps[Clump].CodeStart + 1); + } +} + + +UBYTE cCmdCompare(UBYTE CompCode, ULONG Val1, ULONG Val2, TYPE_CODE TypeCode1, TYPE_CODE TypeCode2) +{ + SLONG SVal1, SVal2; + + if (IS_SIGNED_TYPE(TypeCode1) && IS_SIGNED_TYPE(TypeCode2)) + { + SVal1 = (SLONG)Val1; + SVal2 = (SLONG)Val2; + return ((CompCode == OPCC1_LT && SVal1 < SVal2) + || (CompCode == OPCC1_GT && SVal1 > SVal2) + || (CompCode == OPCC1_LTEQ && SVal1 <= SVal2) + || (CompCode == OPCC1_GTEQ && SVal1 >= SVal2) + || (CompCode == OPCC1_EQ && SVal1 == SVal2) + || (CompCode == OPCC1_NEQ && SVal1 != SVal2)); + } + else + { + return ((CompCode == OPCC1_LT && Val1 < Val2) + || (CompCode == OPCC1_GT && Val1 > Val2) + || (CompCode == OPCC1_LTEQ && Val1 <= Val2) + || (CompCode == OPCC1_GTEQ && Val1 >= Val2) + || (CompCode == OPCC1_EQ && Val1 == Val2) + || (CompCode == OPCC1_NEQ && Val1 != Val2)); + } + +} + + +NXT_STATUS cCmdCompareAggregates(UBYTE CompCode, UBYTE *ReturnBool, DATA_ARG Arg2, UWORD Offset2, DATA_ARG Arg3, UWORD Offset3) +{ + NXT_STATUS Status = NO_ERR; + UBYTE Finished; + + Finished = FALSE; + Status = cCmdRecursiveCompareAggregates(CompCode, ReturnBool, &Finished, Arg2, Offset2, Arg3, Offset3); + if (Finished == FALSE) + { + //If Finished has not been set to TRUE, it means that it was unable to find an inequality, thereby ending the comparison. + //Both elements are equal. Assign the proper value to ReturnBool + *ReturnBool = (CompCode == OPCC1_EQ || CompCode == OPCC1_GTEQ || CompCode == OPCC1_LTEQ); + } + + return Status; +} + + +//!!! Recursive function +NXT_STATUS cCmdRecursiveCompareAggregates(UBYTE CompCode, UBYTE *ReturnBool, UBYTE *Finished, DATA_ARG Arg2, UWORD Offset2, DATA_ARG Arg3, UWORD Offset3) +{ + //The value of Finished must be set to FALSE before calling this function. + //We are able to determine the result of the comparison once we find an inequality. + //Once an inequality is found, Finished is set to TRUE and ReturnBool is set based on the CompCode. + //A call to this function will return with Finished still equal to FALSE if both elements are equal in value and count. + //It is the caller of this function's job to set ReturnBool if this function returns with Finished == FALSE. + + NXT_STATUS Status = NO_ERR; + TYPE_CODE TypeCode2, TypeCode3; + DV_INDEX DVIndex2, DVIndex3; + ULONG ArgVal2, ArgVal3; + UWORD Count2, Count3, MinCount; + UWORD i; + + void *pArg2 = NULL, + *pArg3 = NULL; + + TypeCode2 = cCmdDSType(Arg2); + TypeCode3 = cCmdDSType(Arg3); + + //Make sure the two things we're comparing are the same type + if (IS_AGGREGATE_TYPE(TypeCode2) && (TypeCode2 != TypeCode3)) + { + NXT_BREAK; + return ERR_ARG; + } + + //Simple case, both args are scalars. Solve and return. + if (!IS_AGGREGATE_TYPE(TypeCode2)) + { + pArg2 = cCmdResolveDataArg(Arg2, Offset2, &TypeCode2); + pArg3 = cCmdResolveDataArg(Arg3, Offset3, &TypeCode3); + + ArgVal2 = cCmdGetVal(pArg2, TypeCode2); + ArgVal3 = cCmdGetVal(pArg3, TypeCode3); + + //Once we find an inequality, we can determine the result of the comparison + *Finished = cCmdCompare(OPCC1_NEQ, ArgVal2, ArgVal3, TypeCode2, TypeCode3); + + if (*Finished) + *ReturnBool = cCmdCompare(CompCode, ArgVal2, ArgVal3, TypeCode2, TypeCode3); + + return Status; + } + + // Initialize local variables for each argument + + if (TypeCode2 == TC_ARRAY) + { + Count2 = cCmdArrayCount(Arg2, Offset2); + DVIndex2 = cCmdGetDVIndex(Arg2, Offset2); + Offset2 = DV_ARRAY[DVIndex2].Offset; + + Count3 = cCmdArrayCount(Arg3, Offset3); + DVIndex3 = cCmdGetDVIndex(Arg3, Offset3); + Offset3 = DV_ARRAY[DVIndex3].Offset; + } + else if (TypeCode2 == TC_CLUSTER) + { + Count2 = cCmdClusterCount(Arg2); + Count3 = cCmdClusterCount(Arg3); + } + + //Short circuit evaluation of EQ and NEQ if counts are different + if (Count2 != Count3) + { + if ((CompCode == OPCC1_EQ) || (CompCode == OPCC1_NEQ)) + { + *Finished = TRUE; + *ReturnBool = (CompCode == OPCC1_NEQ); + return Status; + } + } + + MinCount = (Count2 < Count3) ? Count2 : Count3; + + //Advance aggregate args to first sub-element for next call + Arg2 = INC_ID(Arg2); + Arg3 = INC_ID(Arg3); + + // + // Loop through the sub-elements of aggregate arguments. + // Call cCmdRecursiveCompareAggregates recursively with simpler type. + // + + for (i = 0; i < MinCount; i++) + { + Status = cCmdRecursiveCompareAggregates(CompCode, ReturnBool, Finished, Arg2, Offset2, Arg3, Offset3); + if (*Finished || IS_ERR(Status)) + return Status; + + //Advance aggregate args to next sub-element + if (TypeCode2 == TC_ARRAY) + { + Offset2 += DV_ARRAY[DVIndex2].ElemSize; + Offset3 += DV_ARRAY[DVIndex3].ElemSize; + } + else if (TypeCode2 == TC_CLUSTER) + { + Arg2 = cCmdNextDSElement(Arg2); + Arg3 = cCmdNextDSElement(Arg3); + } + } + + //All elements in aggregates type up to MinCount are equal. Count discrepancy determines comparison outcome. + if (Count2 != Count3) + { + *Finished = TRUE; + *ReturnBool = cCmdCompare(CompCode, Count2, Count3, TC_UWORD, TC_UWORD); + } + //Else, no size discrepancy. Elements are equal. Comparison still not resolved, + //so return !Finished and status back up the call chain for further comparison + + return Status; +} + + +// +// Interpreter Functions +// +#define VAR_INSTR_SIZE 0xE + +NXT_STATUS cCmdInterpFromClump(CLUMP_ID Clump) +{ + NXT_STATUS Status = NO_ERR; + CLUMP_REC * pClumpRec; + CODE_WORD * pInstr; + UBYTE InterpFuncIndex, InstrSize; +#if VM_BENCHMARK + ULONG InstrTime = dTimerRead(); +#endif + + if (!cCmdIsClumpIDSane(Clump)) + { + //Caller gave us a bad clump ID -- something is very wrong! Force interpretter to halt. + NXT_BREAK; + return (ERR_ARG); + } + + //Resolve clump record structure and current instruction pointer + pClumpRec = &(VarsCmd.pAllClumps[Clump]); + pInstr = (VarsCmd.pCodespace + pClumpRec->CodeStart + pClumpRec->PC); + + //Get instruction size in bytes. + InstrSize = INSTR_SIZE(pInstr); + + //If instruction is odd-sized or if "real" op code is out of range, give up and return ERR_INSTR + if ((InstrSize & 0x01) || OP_CODE(pInstr) >= OPCODE_COUNT) + return (ERR_INSTR); + + InterpFuncIndex = (InstrSize / 2) - 1; + +#ifdef USE_SHORT_OPS + //If instruction has shortened encoding, add 1 for true interpretter + if (IS_SHORT_OP(pInstr)) + { + InterpFuncIndex++; + } +#endif + + //Peg InterpFuncIndex to 'Other'. Illegal instructions will be caught in cCmdInterpOther(). + if (InterpFuncIndex > 4) + InterpFuncIndex = 4; + + //If instruction is variably-sized; true size is held in the first argument + //!!! This InstrSize wrangling MUST occur after computing InterpFuncIndex + //because variable sized instructions may confuse the code otherwise + if (InstrSize == VAR_INSTR_SIZE) + InstrSize = (UBYTE)(pInstr[1]); + + //Set ScratchPC to clump's current PC so sub-interpreters can apply relative offsets + VarsCmd.ScratchPC = pClumpRec->PC; + + //Set CallerClump to Clump, for use by instructions such as OP_ACQUIRE + VarsCmd.CallerClump = Clump; + + Status = (*InterpFuncs[InterpFuncIndex])(pInstr); + + if (Status == ERR_MEM) + { + //Memory is full. Compact dataspace and try the instruction again. + //!!! Could compact DopeVectorArray here + cCmdDSCompact(); + Status = (*InterpFuncs[InterpFuncIndex])(pInstr); + } + + if (!IS_ERR(Status)) + { + //If clump is finished, reset PC and firecount + if (Status == CLUMP_DONE) + { + pClumpRec->PC = 0; + pClumpRec->CurrFireCount = pClumpRec->InitFireCount; + } + //Else, if instruction has provided override program counter, use it + else if (Status == PC_OVERRIDE) + { + pClumpRec->PC = VarsCmd.ScratchPC; + } + //Else, auto-advance from encoded instruction size (PC is word-based) + else + { + pClumpRec->PC += InstrSize / 2; + } + + //Throw error if we ever advance beyond the clump's codespace + if (pClumpRec->PC > cCmdGetCodespaceCount(Clump)) + { + NXT_BREAK; + Status = ERR_INSTR; + } + } + +#if VM_BENCHMARK + //Increment opcode count + VarsCmd.OpcodeBenchmarks[OP_CODE(pInstr)][0]++; + + InstrTime = dTimerRead() - InstrTime; + if (InstrTime > 1) + { + VarsCmd.OpcodeBenchmarks[OP_CODE(pInstr)][1]++; + if (InstrTime > VarsCmd.OpcodeBenchmarks[OP_CODE(pInstr)][2]) + VarsCmd.OpcodeBenchmarks[OP_CODE(pInstr)][2] = InstrTime; + } +#endif + + return (Status); +} + + +NXT_STATUS cCmdInterpUnop1(CODE_WORD * const pCode) +{ + NXT_STATUS Status = NO_ERR; + UBYTE opCode; + DATA_ARG Arg1; + void *pArg1 = NULL; + TYPE_CODE TypeCode1; + + NXT_ASSERT(pCode != NULL); + +#ifdef USE_SHORT_OPS + if (IS_SHORT_OP(pCode)) + { + //add mapping from quick op to real op + opCode = ShortOpMap[SHORT_OP_CODE(pCode)]; + Arg1 = SHORT_ARG(pCode); + } + else + { + opCode = OP_CODE(pCode); + Arg1 = pCode[1]; + } +#else + opCode = OP_CODE(pCode); + Arg1 = pCode[1]; +#endif //USE_SHORT_OPS + + + switch (opCode) + { + case OP_JMP: + { + VarsCmd.ScratchPC = VarsCmd.ScratchPC + (SWORD)Arg1; + Status = PC_OVERRIDE; + } + break; + + case OP_ACQUIRE: + { + NXT_ASSERT(cCmdIsDSElementIDSane(Arg1)); + NXT_ASSERT(VarsCmd.pDataspaceTOC[Arg1].TypeCode == TC_MUTEX); + + Status = cCmdAcquireMutex((MUTEX_Q *)cCmdDSPtr(Arg1, 0), VarsCmd.CallerClump); + } + break; + + case OP_RELEASE: + { + NXT_ASSERT(cCmdIsDSElementIDSane(Arg1)); + NXT_ASSERT(VarsCmd.pDataspaceTOC[Arg1].TypeCode == TC_MUTEX); + + Status = cCmdReleaseMutex((MUTEX_Q *)cCmdDSPtr(Arg1, 0), VarsCmd.CallerClump); + } + break; + + case OP_SUBRET: + { + NXT_ASSERT(cCmdIsDSElementIDSane(Arg1)); + + //Take Subroutine off RunQ + //Add Subroutine's caller to RunQ + cCmdDeQClump(&(VarsCmd.RunQ), VarsCmd.CallerClump); + cCmdEnQClump(&(VarsCmd.RunQ), *((CLUMP_ID *)cCmdDSPtr(Arg1, 0))); + + Status = CLUMP_DONE; + } + break; + + case OP_FINCLUMPIMMED: + { + cCmdDeQClump(&(VarsCmd.RunQ), VarsCmd.CallerClump); //Dequeue finalized clump + cCmdSchedDependent(VarsCmd.CallerClump, (CLUMP_ID)Arg1); // Use immediate form + + Status = CLUMP_DONE; + } + break; + + case OP_GETTICK: + { + pArg1 = cCmdResolveDataArg(Arg1, 0, &TypeCode1); + + + cCmdSetVal(pArg1, TypeCode1, dTimerRead()); + } + break; + + case OP_STOP: + { + //Unwired Arg1 means always stop + if (Arg1 == NOT_A_DS_ID) + { + Status = STOP_REQ; + } + else + { + pArg1 = cCmdResolveDataArg(Arg1, 0, &TypeCode1); + + if (cCmdGetVal(pArg1, TypeCode1) > 0) + Status = STOP_REQ; + } + } + break; + + default: + { + //Fatal error: Unrecognized instruction + NXT_BREAK; + Status = ERR_INSTR; + } + break; + } + + return (Status); +} + + +NXT_STATUS cCmdInterpUnop2(CODE_WORD * const pCode) +{ + NXT_STATUS Status = NO_ERR; + UBYTE opCode; + DATA_ARG Arg1; + DATA_ARG Arg2; + void *pArg1 = NULL, *pArg2 = NULL; + TYPE_CODE TypeCode1, TypeCode2; + + ULONG i; + UWORD ArgC; + static UBYTE * ArgV[MAX_CALL_ARGS + 1]; + + UWORD Count; + UWORD Offset; + SLONG TmpSLong; + ULONG TmpULong; + ULONG ArgVal2; + + NXT_ASSERT(pCode != NULL); + +#ifdef USE_SHORT_OPS + if (IS_SHORT_OP(pCode)) + { + //add mapping from quick op to real op + opCode = ShortOpMap[SHORT_OP_CODE(pCode)]; + Arg1 = SHORT_ARG(pCode) + pCode[1]; + Arg2 = pCode[1]; + } + else + { + opCode = OP_CODE(pCode); + Arg1 = pCode[1]; + Arg2 = pCode[2]; + } +#else + opCode = OP_CODE(pCode); + Arg1 = pCode[1]; + Arg2 = pCode[2]; +#endif //USE_SHORT_OPS + + if (opCode == OP_NEG || opCode == OP_NOT || opCode == OP_TST) + { + return cCmdInterpPolyUnop2(*pCode, Arg1, 0, Arg2, 0); + } + + switch (opCode) + { + case OP_MOV: + { + //!!! Optimized move for byte arrays (makes File I/O involving CStrs tolerable). Optimize for other cases? + if ((cCmdDSType(Arg1) == TC_ARRAY) && (cCmdDSType(INC_ID(Arg1)) == TC_UBYTE) && + (cCmdDSType(Arg2) == TC_ARRAY) && (cCmdDSType(INC_ID(Arg2)) == TC_UBYTE)) + { + Count = cCmdArrayCount(Arg2, 0); + Status = cCmdDSArrayAlloc(Arg1, 0, Count); + if (IS_ERR(Status)) + return Status; + + pArg1 = cCmdResolveDataArg(Arg1, 0, NULL); + pArg2 = cCmdResolveDataArg(Arg2, 0, NULL); + + memmove(pArg1, pArg2, Count); + } + else + { + Status = cCmdInterpPolyUnop2(OP_MOV, Arg1, 0, Arg2, 0); + } + } + break; + + case OP_SET: + { + //!!! Should throw error if TypeCode1 is non-scalar + // Accepting non-scalar destinations could have unpredictable results! + pArg1 = cCmdResolveDataArg(Arg1, 0, &TypeCode1); + cCmdSetVal(pArg1, TypeCode1, Arg2); + } + break; + + case OP_BRTST: + { + pArg2 = cCmdResolveDataArg(Arg2, 0, &TypeCode2); + if (cCmdCompare(COMP_CODE(pCode), (SLONG)cCmdGetVal(pArg2, TypeCode2), 0, TC_SLONG, TC_SLONG)) + { + VarsCmd.ScratchPC = VarsCmd.ScratchPC + (SWORD)Arg1; + Status = PC_OVERRIDE; + } + } + break; + + case OP_FINCLUMP: + { + cCmdDeQClump(&(VarsCmd.RunQ), VarsCmd.CallerClump); //Dequeue finalized clump + cCmdSchedDependents(VarsCmd.CallerClump, (SWORD)Arg1, (SWORD)Arg2); + + Status = CLUMP_DONE; + } + break; + + case OP_SUBCALL: + { + NXT_ASSERT(cCmdIsClumpIDSane((CLUMP_ID)Arg1)); + NXT_ASSERT(!cCmdIsClumpOnQ(&(VarsCmd.RunQ), (CLUMP_ID)Arg1)); + + NXT_ASSERT(cCmdIsDSElementIDSane(Arg2)); + + *((CLUMP_ID *)(cCmdDSPtr(Arg2, 0))) = VarsCmd.CallerClump; + + cCmdDeQClump(&(VarsCmd.RunQ), VarsCmd.CallerClump); //Take caller off RunQ + cCmdEnQClump(&(VarsCmd.RunQ), (CLUMP_ID)Arg1); //Add callee to RunQ + + Status = CLUMP_SUSPEND; + } + break; + + case OP_ARRSIZE: + { + pArg1 = cCmdResolveDataArg(Arg1, 0, &TypeCode1); + cCmdSetVal(pArg1, TypeCode1, cCmdArrayCount(Arg2, 0)); + } + break; + + case OP_SYSCALL: + { + if (Arg1 >= SYSCALL_COUNT) + { + NXT_BREAK; + Status = ERR_INSTR; + break; + } + + ArgC = cCmdClusterCount(Arg2); + + if (ArgC > MAX_CALL_ARGS) + { + NXT_BREAK; + Status = ERR_INSTR; + break; + } + + if (ArgC > 0) + { + Arg2 = INC_ID(Arg2); + + for (i = 0; i < ArgC; i++) + { + if (cCmdDSType(Arg2) == TC_ARRAY) + { + //Storing pointer to array's DV_INDEX + //!!! This resolve is different than cCmdDSPtr + // since SysCalls may need the DVIndex to re-alloc arrays + ArgV[i] = VarsCmd.pDataspace + VarsCmd.pDataspaceTOC[Arg2].DSOffset; + } + else + { + ArgV[i] = cCmdDSPtr(Arg2, 0); + } + + //If any argument fails to resolve, return a fatal error. + if (ArgV[i] == NULL) + { + Status = ERR_BAD_PTR; + break; + } + + Arg2 = cCmdNextDSElement(Arg2); + } + } + else + { + i = 0; + } + + //ArgV list is null terminated + ArgV[i] = NULL; + + Status = (*SysCallFuncs[Arg1])(ArgV); + } + break; + + case OP_FLATTEN: + { + //Flatten Arg2 to a NULL terminated string + + //Assert that the destination is a string (array of bytes) + NXT_ASSERT(cCmdDSType(Arg1) == TC_ARRAY); + NXT_ASSERT(cCmdDSType(INC_ID(Arg1)) == TC_UBYTE); + + Count = cCmdCalcFlattenedSize(Arg2, 0); + //Add room for NULL terminator + Count++; + Status = cCmdDSArrayAlloc(Arg1, 0, Count); + if (IS_ERR(Status)) + return Status; + + pArg1 = cCmdResolveDataArg(Arg1, 0, NULL); + Offset = 0; + + Status = cCmdFlattenToByteArray(pArg1, &Offset, Arg2, 0); + //Append NULL terminator + *((UBYTE *)pArg1 + Offset) = 0; + Offset++; + NXT_ASSERT(Offset == Count); + } + break; + + case OP_NUMTOSTRING: + { + //Assert that the destination is a string (array of bytes) + NXT_ASSERT(cCmdDSType(Arg1) == TC_ARRAY); + NXT_ASSERT(cCmdDSType(INC_ID(Arg1)) == TC_UBYTE); + + pArg2 = cCmdResolveDataArg(Arg2, 0, &TypeCode2); + //Make sure we're trying to convert a scalar to a string + NXT_ASSERT(!IS_AGGREGATE_TYPE(TypeCode2)); + + ArgVal2 = cCmdGetVal(pArg2, TypeCode2); + + //Calculate size of array + if (ArgVal2 == 0) + Count = 1; + else + Count = 0; + + if (TypeCode2 == TC_SLONG || TypeCode2 == TC_SWORD || TypeCode2 == TC_SBYTE) + { + TmpSLong = (SLONG)ArgVal2; + //Add room for negative sign + if (TmpSLong < 0) + Count++; + + while (TmpSLong) + { + TmpSLong /= 10; + Count++; + } + } + else + { + TmpULong = ArgVal2; + while (TmpULong) + { + TmpULong /= 10; + Count++; + } + } + + //add room for NULL terminator + Count++; + + //Allocate array + Status = cCmdDSArrayAlloc(Arg1, 0, Count); + if (IS_ERR(Status)) + return Status; + + pArg1 = cCmdResolveDataArg(Arg1, 0, &TypeCode1); + + //Populate array + if (TypeCode2 == TC_SLONG || TypeCode2 == TC_SWORD || TypeCode2 == TC_SBYTE) + { + sprintf(pArg1, "%d", (SLONG)ArgVal2); + } + else + { + sprintf(pArg1, "%u", ArgVal2); + } + } + break; + + case OP_STRTOBYTEARR: + { + NXT_ASSERT((cCmdDSType(Arg1) == TC_ARRAY) && (cCmdDSType(INC_ID(Arg1)) == TC_UBYTE)); + NXT_ASSERT((cCmdDSType(Arg2) == TC_ARRAY) && (cCmdDSType(INC_ID(Arg2)) == TC_UBYTE)); + + Count = cCmdArrayCount(Arg2, 0); + + if (Count > 0) + { + Status = cCmdDSArrayAlloc(Arg1, 0, (UWORD)(Count - 1)); + if (IS_ERR(Status)) + return Status; + + pArg1 = cCmdResolveDataArg(Arg1, 0, NULL); + pArg2 = cCmdResolveDataArg(Arg2, 0, NULL); + + memmove(pArg1, pArg2, Count - 1); + } + } + break; + + case OP_BYTEARRTOSTR: + { + NXT_ASSERT((cCmdDSType(Arg1) == TC_ARRAY) && (cCmdDSType(INC_ID(Arg1)) == TC_UBYTE)); + NXT_ASSERT((cCmdDSType(Arg2) == TC_ARRAY) && (cCmdDSType(INC_ID(Arg2)) == TC_UBYTE)); + + Count = cCmdArrayCount(Arg2, 0); + + Status = cCmdDSArrayAlloc(Arg1, 0, (UWORD)(Count + 1)); + if (IS_ERR(Status)) + return Status; + + pArg1 = cCmdResolveDataArg(Arg1, 0, NULL); + pArg2 = cCmdResolveDataArg(Arg2, 0, NULL); + + memmove(pArg1, pArg2, Count); + *((UBYTE *)pArg1 + Count) = '\0'; + } + break; + + default: + { + //Fatal error: Unrecognized instruction + NXT_BREAK; + Status = ERR_INSTR; + } + break; + } + + return (Status); +} + + +NXT_STATUS cCmdInterpPolyUnop2(CODE_WORD const Code, DATA_ARG Arg1, UWORD Offset1, DATA_ARG Arg2, UWORD Offset2) +{ + NXT_STATUS Status = NO_ERR; + TYPE_CODE TypeCode1, TypeCode2; + DV_INDEX DVIndex1, DVIndex2; + ULONG ArgVal1, ArgVal2; + UWORD Count1, Count2; + UWORD MinArrayCount; + UWORD i; + //!!! AdvCluster is intended to catch the case where sources are Cluster and an Array of Clusters. + // In practice, the logic it uses is broken, leading to some source cluster elements being ignored. + UBYTE AdvCluster; + + void * pArg1 = NULL, + *pArg2 = NULL; + + TypeCode1 = cCmdDSType(Arg1); + TypeCode2 = cCmdDSType(Arg2); + + //Simple case, scalar. Solve and return. + if (!IS_AGGREGATE_TYPE(TypeCode2)) + { + NXT_ASSERT(!IS_AGGREGATE_TYPE(TypeCode1)); + + pArg1 = cCmdResolveDataArg(Arg1, Offset1, &TypeCode1); + pArg2 = cCmdResolveDataArg(Arg2, Offset2, &TypeCode2); + + ArgVal2 = cCmdGetVal(pArg2, TypeCode2); + ArgVal1 = cCmdUnop2(Code, ArgVal2, TypeCode2); + cCmdSetVal(pArg1, TypeCode1, ArgVal1); + return Status; + } + + //At least one of the args is an aggregate type + + // + // Initialize Count and ArrayType local variables for each argument + // + + if (TypeCode2 == TC_ARRAY) + { + Count2 = cCmdArrayCount(Arg2, Offset2); + DVIndex2 = cCmdGetDVIndex(Arg2, Offset2); + Offset2 = DV_ARRAY[DVIndex2].Offset; + } + else if (TypeCode2 == TC_CLUSTER) + { + Count2 = cCmdClusterCount(Arg2); + } + + if (TypeCode1 == TC_ARRAY) + { + if (TypeCode2 != TC_ARRAY) + { + //If output is an array, but source is not an array, that's a fatal error! + NXT_BREAK; + return (ERR_ARG); + } + + MinArrayCount = Count2; + + //Make sure the destination array is the proper size to hold the result + Status = cCmdDSArrayAlloc(Arg1, Offset1, MinArrayCount); + if (IS_ERR(Status)) + return Status; + + Count1 = MinArrayCount; + DVIndex1 = cCmdGetDVIndex(Arg1, Offset1); + Offset1 = DV_ARRAY[DVIndex1].Offset; + AdvCluster = FALSE; + } + else if (TypeCode1 == TC_CLUSTER) + { + Count1 = cCmdClusterCount(Arg1); + AdvCluster = TRUE; + } + + //Advance aggregate args to first sub-element for next call + if (IS_AGGREGATE_TYPE(TypeCode1)) + Arg1 = INC_ID(Arg1); + if (IS_AGGREGATE_TYPE(TypeCode2)) + Arg2 = INC_ID(Arg2); + + // + // Loop through the sub-elements of aggregate arguments. + // Call cCmdInterpPolyUnop2 recursively with simpler type. + // + + for (i = 0; i < Count1; i++) + { + Status = cCmdInterpPolyUnop2(Code, Arg1, Offset1, Arg2, Offset2); + if (IS_ERR(Status)) + return Status; + + //Advance aggregate args to next sub-element + if (TypeCode1 == TC_ARRAY) + Offset1 += DV_ARRAY[DVIndex1].ElemSize; + else if ((TypeCode1 == TC_CLUSTER) && AdvCluster) + Arg1 = cCmdNextDSElement(Arg1); + + if (TypeCode2 == TC_ARRAY) + Offset2 += DV_ARRAY[DVIndex2].ElemSize; + else if ((TypeCode2 == TC_CLUSTER) && AdvCluster) + Arg2 = cCmdNextDSElement(Arg2); + } + + return Status; +} + + +ULONG cCmdUnop2(CODE_WORD const Code, ULONG Operand, TYPE_CODE TypeCode) +{ + UBYTE opCode; + + opCode = OP_CODE((&Code)); + + switch (opCode) + { + case OP_MOV: + { + return Operand; + } + + case OP_NEG: + { + return (-((SLONG)Operand)); + } + + case OP_NOT: + { + //!!! OP_NOT is logical, *not* bit-wise. + //This differs from the other logical ops because we don't distinguish booleans from UBYTEs. + return (!Operand); + } + + case OP_TST: + { + return cCmdCompare(COMP_CODE((&Code)), Operand, 0, TypeCode, TypeCode); + } + + default: + { + //Unrecognized instruction, NXT_BREAK for easy debugging (ERR_INSTR handled in caller) + NXT_BREAK; + return 0; + } + } +} + + +NXT_STATUS cCmdInterpBinop(CODE_WORD * const pCode) +{ + NXT_STATUS Status = NO_ERR; + UBYTE opCode; + DATA_ARG Arg1, Arg2, Arg3; + TYPE_CODE TypeCode1, TypeCode2, TypeCode3; + ULONG ArgVal2, ArgVal3; + UBYTE CmpBool; + DV_INDEX DVIndex1, DVIndex2; + UWORD i; + + void * pArg1 = NULL, + *pArg2 = NULL, + *pArg3 = NULL; + + NXT_ASSERT(pCode != NULL); +#ifdef USE_SHORT_OPS + if (IS_SHORT_OP(pCode)) + { + //add mapping from quick op to real op + opCode = ShortOpMap[SHORT_OP_CODE(pCode)]; + Arg1 = SHORT_ARG(pCode) + pCode[1]; + Arg2 = pCode[1]; + Arg3 = pCode[2]; + } + else + { + opCode = OP_CODE(pCode); + Arg1 = pCode[1]; + Arg2 = pCode[2]; + Arg3 = pCode[3]; + } +#else + opCode = OP_CODE(pCode); + Arg1 = pCode[1]; + Arg2 = pCode[2]; + Arg3 = pCode[3]; +#endif //USE_SHORT_OPS + + if (opCode == OP_ADD || opCode == OP_SUB || opCode == OP_MUL || opCode == OP_DIV || opCode == OP_MOD || + opCode == OP_AND || opCode == OP_OR || opCode == OP_XOR) + { + return cCmdInterpPolyBinop(opCode, Arg1, 0, Arg2, 0, Arg3, 0); + } + + //Resolve data arguments, except for opcodes which the arguments are not DataArgs + if (opCode != OP_BRCMP) + { + pArg1 = cCmdResolveDataArg(Arg1, 0, &TypeCode1); + } + + if (opCode != OP_INDEX) + { + pArg2 = cCmdResolveDataArg(Arg2, 0, &TypeCode2); + ArgVal2 = cCmdGetVal(pArg2, TypeCode2); + } + + if ((opCode != OP_GETOUT) && (opCode != OP_SETIN) && (opCode != OP_GETIN) && (opCode != OP_INDEX) && (opCode != OP_ARRINIT)) + { + pArg3 = cCmdResolveDataArg(Arg3, 0, &TypeCode3); + ArgVal3 = cCmdGetVal(pArg3, TypeCode3); + } + + switch (opCode) + { + + case OP_CMP: + { + if (!IS_AGGREGATE_TYPE(cCmdDSType(Arg1)) && IS_AGGREGATE_TYPE(cCmdDSType(Arg2)) && IS_AGGREGATE_TYPE(cCmdDSType(Arg3))) + { + //Compare Aggregates + Status = cCmdCompareAggregates(COMP_CODE(pCode), &CmpBool, Arg2, 0, Arg3, 0); + cCmdSetVal(pArg1, TypeCode1, CmpBool); + } + else + { + //Compare Elements + Status = cCmdInterpPolyBinop(*pCode, Arg1, 0, Arg2, 0, Arg3, 0); + } + } + break; + + case OP_BRCMP: + { + //Compare Aggregates + Status = cCmdCompareAggregates(COMP_CODE(pCode), &CmpBool, Arg2, 0, Arg3, 0); + + if (CmpBool) + { + VarsCmd.ScratchPC = VarsCmd.ScratchPC + (SWORD)Arg1; + Status = PC_OVERRIDE; + } + } + break; + + case OP_GETOUT: + { + Arg2 = (UWORD)(0xC200 | (Arg3 + ArgVal2 * IO_OUT_FPP)); + pArg2 = cCmdResolveDataArg(Arg2, 0, &TypeCode2); + + cCmdSetVal(pArg1, TypeCode1, cCmdGetVal(pArg2, TypeCode2)); + } + break; + + //!!! All IO map access commands should screen illegal port values! + // Right now, cCmdResolveDataArg's implementation allows SETIN/GETIN to access arbitrary RAM! + case OP_SETIN: + { + Arg2 = (UWORD)(0xC000 | (Arg3 + ArgVal2 * IO_IN_FPP)); + pArg2 = cCmdResolveDataArg(Arg2, 0, &TypeCode2); + + cCmdSetVal(pArg2, TypeCode2, cCmdGetVal(pArg1, TypeCode1)); + } + break; + + case OP_GETIN: + { + Arg2 = (UWORD)(0xC000 | (Arg3 + ArgVal2 * IO_IN_FPP)); + pArg2 = cCmdResolveDataArg(Arg2, 0, &TypeCode2); + + cCmdSetVal(pArg1, TypeCode1, cCmdGetVal(pArg2, TypeCode2)); + } + break; + + case OP_INDEX: + { + if (Arg3 != NOT_A_DS_ID) + { + pArg3 = cCmdResolveDataArg(Arg3, 0, &TypeCode3); + ArgVal3 = cCmdGetVal(pArg3, TypeCode3); + } + else //Index input unwired + { + ArgVal3 = 0; + } + + DVIndex2 = cCmdGetDVIndex(Arg2, 0); + if (ArgVal3 >= DV_ARRAY[DVIndex2].Count) + return (ERR_ARG); + + Status = cCmdInterpPolyUnop2(OP_MOV, Arg1, 0, INC_ID(Arg2), ARRAY_ELEM_OFFSET(DVIndex2, ArgVal3)); + } + break; + + case OP_ARRINIT: + { + //Arg1 - Dst, Arg2 - element type/default val, Arg3 - length + + NXT_ASSERT(TypeCode1 == TC_ARRAY); + + if (Arg3 != NOT_A_DS_ID) + { + pArg3 = cCmdResolveDataArg(Arg3, 0, &TypeCode3); + ArgVal3 = cCmdGetVal(pArg3, TypeCode3); + } + else //Length input unwired + { + ArgVal3 = 0; + } + + Status = cCmdDSArrayAlloc(Arg1, 0, (UWORD)ArgVal3); + if (IS_ERR(Status)) + return Status; + + DVIndex1 = cCmdGetDVIndex(Arg1, 0); + for (i = 0; i < ArgVal3; i++) + { + //copy Arg2 into each element of Arg1 + Status = cCmdInterpPolyUnop2(OP_MOV, INC_ID(Arg1), ARRAY_ELEM_OFFSET(DVIndex1, i), Arg2, 0); + } + } + break; + + default: + { + //Fatal error: Unrecognized instruction + NXT_BREAK; + Status = ERR_INSTR; + } + break; + } + + return (Status); +} + + +NXT_STATUS cCmdInterpPolyBinop(CODE_WORD const Code, DATA_ARG Arg1, UWORD Offset1, DATA_ARG Arg2, UWORD Offset2, DATA_ARG Arg3, UWORD Offset3) +{ + NXT_STATUS Status = NO_ERR; + TYPE_CODE TypeCode1, TypeCode2, TypeCode3; + DV_INDEX DVIndex1, DVIndex2, DVIndex3; + ULONG ArgVal1, ArgVal2, ArgVal3; + UWORD Count1, Count2, Count3; + UWORD MinArrayCount; + UWORD i; + //!!! AdvCluster is intended to catch the case where sources are Cluster and an Array of Clusters. + // In practice, the logic it uses is broken, leading to some source cluster elements being ignored. + UBYTE AdvCluster; + + void * pArg1 = NULL, + *pArg2 = NULL, + *pArg3 = NULL; + + TypeCode1 = cCmdDSType(Arg1); + TypeCode2 = cCmdDSType(Arg2); + TypeCode3 = cCmdDSType(Arg3); + + //Simple case, both args are scalars. Solve and return. + if ((!IS_AGGREGATE_TYPE(TypeCode2)) && (!IS_AGGREGATE_TYPE(TypeCode3))) + { + NXT_ASSERT(!IS_AGGREGATE_TYPE(TypeCode1)); + + pArg1 = cCmdResolveDataArg(Arg1, Offset1, &TypeCode1); + pArg2 = cCmdResolveDataArg(Arg2, Offset2, &TypeCode2); + pArg3 = cCmdResolveDataArg(Arg3, Offset3, &TypeCode3); + + ArgVal2 = cCmdGetVal(pArg2, TypeCode2); + ArgVal3 = cCmdGetVal(pArg3, TypeCode3); + ArgVal1 = cCmdBinop(Code, ArgVal2, ArgVal3, TypeCode2, TypeCode3); + cCmdSetVal(pArg1, TypeCode1, ArgVal1); + return Status; + } + + //At least one of the args is an aggregate type + + // + // Initialize Count and ArrayType local variables for each argument + // + + if (TypeCode2 == TC_ARRAY) + { + Count2 = cCmdArrayCount(Arg2, Offset2); + DVIndex2 = cCmdGetDVIndex(Arg2, Offset2); + Offset2 = DV_ARRAY[DVIndex2].Offset; + } + else if (TypeCode2 == TC_CLUSTER) + { + Count2 = cCmdClusterCount(Arg2); + } + + if (TypeCode3 == TC_ARRAY) + { + Count3 = cCmdArrayCount(Arg3, Offset3); + DVIndex3 = cCmdGetDVIndex(Arg3, Offset3); + Offset3 = DV_ARRAY[DVIndex3].Offset; + } + else if (TypeCode3 == TC_CLUSTER) + { + Count3 = cCmdClusterCount(Arg3); + } + + + if (TypeCode1 == TC_ARRAY) + { + //If the destination is an array, make sure it has enough memory to hold the result + if ((TypeCode2 == TC_ARRAY) && (TypeCode3 == TC_ARRAY)) + { + if (Count2 < Count3) + MinArrayCount = Count2; + else + MinArrayCount = Count3; + } + else if (TypeCode2 == TC_ARRAY) + MinArrayCount = Count2; + else if (TypeCode3 == TC_ARRAY) + MinArrayCount = Count3; + else + { + //If output is an array, but no sources are arrays, that's a fatal error! + NXT_BREAK; + return (ERR_ARG); + } + + //Make sure the destination array is the proper size to hold the result + Status = cCmdDSArrayAlloc(Arg1, Offset1, MinArrayCount); + if (IS_ERR(Status)) + return Status; + + Count1 = MinArrayCount; + DVIndex1 = cCmdGetDVIndex(Arg1, Offset1); + Offset1 = DV_ARRAY[DVIndex1].Offset; + AdvCluster = FALSE; + } + else if (TypeCode1 == TC_CLUSTER) + { + Count1 = cCmdClusterCount(Arg1); + AdvCluster = TRUE; + } + + //Advance aggregate args to first sub-element for next call + if (IS_AGGREGATE_TYPE(TypeCode1)) + Arg1 = INC_ID(Arg1); + if (IS_AGGREGATE_TYPE(TypeCode2)) + Arg2 = INC_ID(Arg2); + if (IS_AGGREGATE_TYPE(TypeCode3)) + Arg3 = INC_ID(Arg3); + + // + // Loop through the sub-elements of aggregate arguments. + // Call cCmdInterpPolyBinop recursively with simpler type. + // + + for (i = 0; i < Count1; i++) + { + Status = cCmdInterpPolyBinop(Code, Arg1, Offset1, Arg2, Offset2, Arg3, Offset3); + if (IS_ERR(Status)) + return Status; + + //Advance aggregate args to next sub-element + if (TypeCode1 == TC_ARRAY) + Offset1 += DV_ARRAY[DVIndex1].ElemSize; + else if ((TypeCode1 == TC_CLUSTER) && AdvCluster) + Arg1 = cCmdNextDSElement(Arg1); + + if (TypeCode2 == TC_ARRAY) + Offset2 += DV_ARRAY[DVIndex2].ElemSize; + else if ((TypeCode2 == TC_CLUSTER) && AdvCluster) + Arg2 = cCmdNextDSElement(Arg2); + + if (TypeCode3 == TC_ARRAY) + Offset3 += DV_ARRAY[DVIndex3].ElemSize; + else if ((TypeCode3 == TC_CLUSTER) && AdvCluster) + Arg3 = cCmdNextDSElement(Arg3); + } + + return Status; +} + + +ULONG cCmdBinop(CODE_WORD const Code, ULONG LeftOp, ULONG RightOp, TYPE_CODE LeftType, TYPE_CODE RightType) +{ + UBYTE opCode; + + opCode = OP_CODE((&Code)); + + switch (opCode) + { + case OP_ADD: + { + return LeftOp + RightOp; + } + + case OP_SUB: + { + return LeftOp - RightOp; + } + + case OP_MUL: + { + return LeftOp * RightOp; + } + + case OP_DIV: + { + //Catch divide-by-zero for a portable, well-defined result. + //(x / 0) = 0. Thus Spake LOTHAR!! (It's technical.) + if (RightOp == 0) + return 0; + + if (IS_SIGNED_TYPE(LeftType) && IS_SIGNED_TYPE(RightType)) + return ((SLONG)LeftOp) / ((SLONG)RightOp); + else if (IS_SIGNED_TYPE(LeftType)) + return ((SLONG)LeftOp) / RightOp; + else if (IS_SIGNED_TYPE(RightType)) + return LeftOp / ((SLONG)RightOp); + else + return LeftOp / RightOp; + } + + case OP_MOD: + { + //As with OP_DIV, make sure (x % 0) = x is well-defined + if (RightOp == 0) + return (LeftOp); + + if (IS_SIGNED_TYPE(LeftType) && IS_SIGNED_TYPE(RightType)) + return ((SLONG)LeftOp) % ((SLONG)RightOp); + else if (IS_SIGNED_TYPE(LeftType)) + return ((SLONG)LeftOp) % RightOp; + else if (IS_SIGNED_TYPE(RightType)) + return LeftOp % ((SLONG)RightOp); + else + return LeftOp % RightOp; + } + + case OP_AND: + { + return (LeftOp & RightOp); + } + + case OP_OR: + { + return (LeftOp | RightOp); + } + + case OP_XOR: + { + return ((LeftOp | RightOp) & (~(LeftOp & RightOp))); + } + + case OP_CMP: + { + return cCmdCompare(COMP_CODE((&Code)), LeftOp, RightOp, LeftType, RightType); + } + + default: + { + //Unrecognized instruction, NXT_BREAK for easy debugging (ERR_INSTR handled in caller) + NXT_BREAK; + return 0; + } + } +} + +NXT_STATUS cCmdInterpNoArg(CODE_WORD * const pCode) +{ + //Fatal error: Unrecognized instruction (no current opcodes have zero instructions) + NXT_BREAK; + return (ERR_INSTR); +} + + +//OP_SETOUT gets it's own interpreter function because it is relatively complex +// (called from cCmdInterpOther()) +//This also serves as a convenient breakpoint stop for investigating output module behavior +NXT_STATUS cCmdExecuteSetOut(CODE_WORD * const pCode) +{ + TYPE_CODE TypeCodeField, TypeCodeSrc, TypeCodePortArg; + void *pField = NULL, + *pSrc = NULL, + *pPort = NULL; + DS_ELEMENT_ID PortArg; + UWORD PortCount, InstrSize; + ULONG Port, FieldTableIndex, i, j; + DV_INDEX DVIndex; + + //Arg1 = InstrSize + //Arg2 = port number or list of ports + //Arg3 and beyond = FieldID, src DSID tuples + + //Calculate number of tuples + //!!! Might want to throw ERR_INSTR if instrSize and tuples don't check out + InstrSize = (pCode[1] / 2); + + //Second argument may specify a single port or an array list. + //Figure out which and resolve accordingly. + PortArg = pCode[2]; + TypeCodePortArg = cCmdDSType(PortArg); + + if (TypeCodePortArg == TC_ARRAY) + { + DVIndex = cCmdGetDVIndex(PortArg, 0); + PortCount = cCmdArrayCount(PortArg, 0); + } + else + PortCount = 1; + + //For each port, process all the tuples + for (i = 0; i < PortCount; i++) + { + if (TypeCodePortArg == TC_ARRAY) + { + pPort = (UBYTE*)cCmdResolveDataArg(INC_ID(PortArg), ARRAY_ELEM_OFFSET(DVIndex, i), NULL); + Port = cCmdGetVal(pPort, cCmdDSType(INC_ID(PortArg))); + } + else + { + pPort = (UBYTE*)cCmdResolveDataArg(PortArg, 0, NULL); + Port = cCmdGetVal(pPort, TypeCodePortArg); + } + + //If user specified a valid port, process the tuples. Else, this port is a no-op + if (Port < NO_OF_OUTPUTS) + { + for (j = 3; j < InstrSize; j += 2) + { + FieldTableIndex = (Port * IO_OUT_FPP) + pCode[j]; + pSrc = cCmdResolveDataArg(pCode[j + 1], 0, &TypeCodeSrc); + + //If FieldTableIndex is valid, go ahead and set the value + if (FieldTableIndex < IO_OUT_FIELD_COUNT) + { + pField = IO_PTRS[MOD_OUTPUT][FieldTableIndex]; + TypeCodeField = IO_TYPES[MOD_OUTPUT][FieldTableIndex]; + cCmdSetVal(pField, TypeCodeField, cCmdGetVal(pSrc, TypeCodeSrc)); + } + //Else, compiler is nutso! Return fatal error. + else + return (ERR_INSTR); + } + } + } + + return (NO_ERR); +} + + +NXT_STATUS cCmdInterpOther(CODE_WORD * const pCode) +{ + NXT_STATUS Status = NO_ERR; + UBYTE opCode; + DATA_ARG Arg1, Arg2, Arg3, Arg4, Arg5; + TYPE_CODE TypeCode1, TypeCode2, TypeCode3, TypeCode4, TypeCode5; + ULONG ArgVal1, ArgVal2, ArgVal3, ArgVal4, ArgVal5; + UWORD ArrayCount1, ArrayCount2, ArrayCount3, ArrayCount4; + UWORD MinCount; + UWORD i,j; + DV_INDEX DVIndex1, DVIndex2, DVIndex4,TmpDVIndex; + UWORD SrcCount; + DS_ELEMENT_ID TmpDSID; + UWORD DstIndex; + UWORD Size; + UWORD Offset; + + void *pArg1 = NULL; + void *pArg2 = NULL; + void *pArg3 = NULL; + void *pArg4 = NULL; + void *pArg5 = NULL; + + NXT_ASSERT(pCode != NULL); + + opCode = OP_CODE(pCode); + + switch (opCode) + { + + case OP_REPLACE: + { + //Arg1 - Dst + //Arg2 - Src + //Arg3 - Index + //Arg4 - New val / array of vals + + Arg1 = pCode[1]; + Arg2 = pCode[2]; + Arg3 = pCode[3]; + Arg4 = pCode[4]; + + NXT_ASSERT(cCmdDSType(Arg1) == TC_ARRAY); + NXT_ASSERT(cCmdDSType(Arg2) == TC_ARRAY); + + //Copy Src to Dst + //!!! Could avoid full data copy if we knew which portion to overwrite + if (Arg1 != Arg2) + { + Status = cCmdInterpPolyUnop2(OP_MOV, Arg1, 0, Arg2, 0); + if (IS_ERR(Status)) + return Status; + } + + DVIndex1 = cCmdGetDVIndex(Arg1, 0); + //Copy new val to Dst + if (Arg3 != NOT_A_DS_ID) + { + pArg3 = cCmdResolveDataArg(Arg3, 0, &TypeCode3); + ArgVal3 = cCmdGetVal(pArg3, TypeCode3); + } + else + { + //Index input unwired + ArgVal3 = 0; + } + + ArrayCount1 = cCmdArrayCount(Arg1, 0); + //Bounds check + //If array index (ArgVal3) is out of range, just pass out the copy of Src (effectively no-op) + if (ArgVal3 >= ArrayCount1) + return (NO_ERR); + + if (cCmdDSType(Arg4) != TC_ARRAY) + { + Status = cCmdInterpPolyUnop2(OP_MOV, INC_ID(Arg1), ARRAY_ELEM_OFFSET(DVIndex1, ArgVal3), Arg4, 0); + if (IS_ERR(Status)) + return Status; + } + else + { + DVIndex4 = cCmdGetDVIndex(Arg4, 0); + + ArrayCount4 = cCmdArrayCount(Arg4, 0); + if (ArrayCount1 - ArgVal3 < ArrayCount4) + MinCount = (UWORD)(ArrayCount1 - ArgVal3); + else + MinCount = ArrayCount4; + + for (i = 0; i < MinCount; i++) + { + Status = cCmdInterpPolyUnop2(OP_MOV, INC_ID(Arg1), ARRAY_ELEM_OFFSET(DVIndex1, ArgVal3 + i), INC_ID(Arg4), ARRAY_ELEM_OFFSET(DVIndex4, i)); + if (IS_ERR(Status)) + return Status; + } + } + } + break; + + case OP_ARRSUBSET: + { + //Arg1 - Dst + //Arg2 - Src + //Arg3 - Index + //Arg4 - Length + + Arg1 = pCode[1]; + Arg2 = pCode[2]; + Arg3 = pCode[3]; + Arg4 = pCode[4]; + + NXT_ASSERT(cCmdDSType(Arg1) == TC_ARRAY); + NXT_ASSERT(cCmdDSType(Arg2) == TC_ARRAY); + + ArrayCount2 = cCmdArrayCount(Arg2, 0); + + if (Arg3 != NOT_A_DS_ID) + { + pArg3 = cCmdResolveDataArg(Arg3, 0, &TypeCode3); + ArgVal3 = cCmdGetVal(pArg3, TypeCode3); + } + else //Index input unwired + { + ArgVal3 = 0; + } + + if (Arg4 != NOT_A_DS_ID) + { + pArg4 = cCmdResolveDataArg(Arg4, 0, &TypeCode4); + ArgVal4 = cCmdGetVal(pArg4, TypeCode4); + } + else //Length input unwired, set to "rest" + { + ArgVal4 = (UWORD)(ArrayCount2 - ArgVal3); + } + + //Bounds check + if (ArgVal3 > ArrayCount2) + { + //Illegal range - return empty subset + Status = cCmdDSArrayAlloc(Arg1, 0, 0); + return Status; + } + + //Set MinCount to "rest" + MinCount = (UWORD)(ArrayCount2 - ArgVal3); + + // Copy "Length" if it is less than "rest" + if (ArgVal4 < (ULONG)MinCount) + MinCount = (UWORD)ArgVal4; + + //Allocate Dst array + Status = cCmdDSArrayAlloc(Arg1, 0, MinCount); + if (IS_ERR(Status)) + return Status; + + DVIndex1 = cCmdGetDVIndex(Arg1, 0); + DVIndex2 = cCmdGetDVIndex(Arg2, 0); + + //Move src subset to dst + for (i = 0; i < MinCount; i++) + { + Status = cCmdInterpPolyUnop2(OP_MOV, INC_ID(Arg1), ARRAY_ELEM_OFFSET(DVIndex1, i), INC_ID(Arg2), ARRAY_ELEM_OFFSET(DVIndex2, ArgVal3 + i)); + if (IS_ERR(Status)) + return Status; + } + } + break; + + case OP_STRSUBSET: + { + //Arg1 - Dst + //Arg2 - Src + //Arg3 - Index + //Arg4 - Length + + Arg1 = pCode[1]; + Arg2 = pCode[2]; + Arg3 = pCode[3]; + Arg4 = pCode[4]; + + NXT_ASSERT(cCmdDSType(Arg1) == TC_ARRAY); + NXT_ASSERT(cCmdDSType(INC_ID(Arg1)) == TC_UBYTE); + NXT_ASSERT(cCmdDSType(Arg2) == TC_ARRAY); + NXT_ASSERT(cCmdDSType(INC_ID(Arg2)) == TC_UBYTE); + + ArrayCount2 = cCmdArrayCount(Arg2, 0); + + //Remove NULL from Count + ArrayCount2--; + + if (Arg3 != NOT_A_DS_ID) + { + pArg3 = cCmdResolveDataArg(Arg3, 0, &TypeCode3); + ArgVal3 = cCmdGetVal(pArg3, TypeCode3); + } + else //Index input unwired + { + ArgVal3 = 0; + } + + if (Arg4 != NOT_A_DS_ID) + { + pArg4 = cCmdResolveDataArg(Arg4, 0, &TypeCode4); + ArgVal4 = cCmdGetVal(pArg4, TypeCode4); + } + else //Length input unwired, set to "rest" + { + ArgVal4 = (UWORD)(ArrayCount2 - ArgVal3); + } + + //Bounds check + if (ArgVal3 > ArrayCount2) + { + //Illegal range - return empty string + Status = cCmdDSArrayAlloc(Arg1, 0, 1); + if (!IS_ERR(Status)) + { + pArg1 = cCmdResolveDataArg(Arg1, 0, NULL); + *((UBYTE *)pArg1) = '\0'; + } + return Status; + } + + //Set MinCount to "rest" + MinCount = (UWORD)(ArrayCount2 - ArgVal3); + + // Copy "Length" if it is less than "rest" + if (ArgVal4 < (ArrayCount2 - ArgVal3)) + MinCount = (UWORD)ArgVal4; + + //Allocate Dst array + Status = cCmdDSArrayAlloc(Arg1, 0, (UWORD)(MinCount + 1)); + if (IS_ERR(Status)) + return Status; + + pArg1 = cCmdResolveDataArg(Arg1, 0, NULL); + pArg2 = cCmdResolveDataArg(Arg2, 0, NULL); + + //Move src subset to dst + memmove((UBYTE *)pArg1, (UBYTE *)pArg2 + ArgVal3, MinCount); + + //Append NULL terminator to Dst + *((UBYTE *)pArg1 + MinCount) = '\0'; + + } + break; + + case OP_SETOUT: + { + Status = cCmdExecuteSetOut(pCode); + } + break; + + case OP_ARRBUILD: + { + // Arg1 - Instruction Size in bytes + // Arg2 - Dst + // Arg3-N - Srcs + + Arg2 = pCode[2]; + + NXT_ASSERT(cCmdDSType(Arg2) == TC_ARRAY); + + //Number of Srcs = total code words - 3 (account for opcode word, size, and Dst) + //!!! Argument access like this is potentially unsafe. + //A function/macro which checks proper encoding would be better + SrcCount = (pCode[1] / 2) - 3; + + //Calculate Dst array count + ArrayCount2 = 0; + for (i = 0; i < SrcCount; i++) + { + TmpDSID = pCode[3 + i]; + NXT_ASSERT(cCmdIsDSElementIDSane(TmpDSID)); + + //If the type descriptors are the same, then the input is an array, not a single element + if (cCmdCompareDSType(Arg2, TmpDSID)) + { + NXT_ASSERT(cCmdDSType(TmpDSID) == TC_ARRAY); + ArrayCount2 += cCmdArrayCount(TmpDSID, 0); + } + else + { + //Assert that the output is an array of this input type + NXT_ASSERT(cCmdCompareDSType(INC_ID(Arg2), TmpDSID)); + ArrayCount2++; + } + } + + //Allocate Dst array + Status = cCmdDSArrayAlloc(Arg2, 0, ArrayCount2); + if (IS_ERR(Status)) + return Status; + + DVIndex2 = cCmdGetDVIndex(Arg2, 0); + + //Move Src(s) to Dst + DstIndex = 0; + for (i = 0; i < SrcCount; i++) + { + TmpDSID = pCode[3 + i]; + + //If the type descriptors are the same, then the input is an array, not a single element + if (cCmdCompareDSType(Arg2, TmpDSID)) + { + NXT_ASSERT(cCmdDSType(TmpDSID) == TC_ARRAY); + TmpDVIndex = cCmdGetDVIndex(TmpDSID, 0); + for (j = 0; j < DV_ARRAY[TmpDVIndex].Count; j++) + { + Status = cCmdInterpPolyUnop2(OP_MOV, INC_ID(Arg2), ARRAY_ELEM_OFFSET(DVIndex2, DstIndex), INC_ID(TmpDSID), ARRAY_ELEM_OFFSET(TmpDVIndex, j)); + if (IS_ERR(Status)) + return Status; + DstIndex++; + } + } + else + { + //Assert that the output is an array of this input type + NXT_ASSERT(cCmdCompareDSType(INC_ID(Arg2), TmpDSID)); + Status = cCmdInterpPolyUnop2(OP_MOV, INC_ID(Arg2), ARRAY_ELEM_OFFSET(DVIndex2, DstIndex), TmpDSID, 0); + if (IS_ERR(Status)) + return Status; + DstIndex++; + } + } + + NXT_ASSERT(DstIndex == ArrayCount2); + } + break; + + case OP_STRCAT: + { + // Arg1 - Instruction Size in bytes + // Arg2 - Dst + // Arg3-N - Srcs + + Arg2 = pCode[2]; + + //Make sure Dst arg is a string + NXT_ASSERT(cCmdDSType(Arg2) == TC_ARRAY); + NXT_ASSERT(cCmdDSType(INC_ID(Arg2)) == TC_UBYTE); + + //Number of Srcs = total code words - 3 (account for opcode word, size, and Dst) + //!!! Argument access like this is potentially unsafe. + //A function/macro which checks proper encoding would be better + SrcCount = (pCode[1] / 2) - 3; + + //Calculate Dst array count + ArrayCount2 = 0; + for (i = 0; i < SrcCount; i++) + { + TmpDSID = pCode[3 + i]; + NXT_ASSERT(cCmdIsDSElementIDSane(TmpDSID)); + + //Make sure Src arg is a string + //!!! Type checks here should be richer to allow array of strings as input (match LabVIEW behavior) + NXT_ASSERT(cCmdDSType(TmpDSID) == TC_ARRAY); + + if (cCmdDSType(INC_ID(TmpDSID)) != TC_UBYTE) + { + NXT_BREAK; + return ERR_ARG; + } + + ArrayCount3 = cCmdArrayCount(TmpDSID, 0); + NXT_ASSERT(ArrayCount3 > 0); + //Subtract NULL terminator from Src array count + ArrayCount3--; + + //Increase Dst array count by Src array count + ArrayCount2 += ArrayCount3; + } + + //Add room for NULL terminator + ArrayCount2++; + + //Allocate Dst array + Status = cCmdDSArrayAlloc(Arg2, 0, ArrayCount2); + if (IS_ERR(Status)) + return Status; + + //Move Src(s) to Dst + DstIndex = 0; + pArg2 = cCmdResolveDataArg(Arg2, 0, NULL); + for (i = 0; i < SrcCount; i++) + { + TmpDSID = pCode[3 + i]; + + pArg3 = cCmdResolveDataArg(TmpDSID, 0, NULL); + + ArrayCount3 = cCmdArrayCount(TmpDSID, 0); + NXT_ASSERT(ArrayCount3 > 0); + //Subtract NULL terminator from Src array count + ArrayCount3--; + + memmove((UBYTE *)pArg2 + DstIndex, pArg3, ArrayCount3); + DstIndex += ArrayCount3; + } + + //Append NULL terminator to Dst + *((UBYTE *)pArg2 + DstIndex) = '\0'; + DstIndex++; + + NXT_ASSERT(DstIndex == ArrayCount2); + } + break; + + case OP_UNFLATTEN: + { + //Arg1 - Dst + //Arg2 - Err (output) + //Arg3 - Src (byte stream) + //Arg4 - Type + + //The Type arg is a preallocated structure of the exact size you + //want to unflatten into. This allows us to support unflattening arbitrary types. + + //!!! Currently, both outputs must have valid destinations. + // It would be trivial to handle NOT_A_DS_ID to avoid dummy + // allocations when outputs are unused. + + Arg1 = pCode[1]; + Arg2 = pCode[2]; + Arg3 = pCode[3]; + Arg4 = pCode[4]; + + //Move Type template to Dst + //This provides a default value for Dst and makes sure Dst is properly sized + Status = cCmdInterpPolyUnop2(OP_MOV, Arg1, 0, Arg4, 0); + if (IS_ERR(Status)) + return Status; + + //Resolve error data pointer + pArg2 = cCmdResolveDataArg(Arg2, 0, &TypeCode2); + + //Make sure Arg3 is a String + NXT_ASSERT(cCmdDSType(Arg3) == TC_ARRAY); + NXT_ASSERT(cCmdDSType(INC_ID(Arg3)) == TC_UBYTE); + + ArrayCount3 = cCmdArrayCount(Arg3, 0); + //Take NULL terminator out of count + ArrayCount3--; + + Size = cCmdCalcFlattenedSize(Arg4, 0); + + //Check that we have a proper type template to unflatten into + if (ArrayCount3 == Size) + { + pArg3 = cCmdResolveDataArg(Arg3, 0, NULL); + Offset = 0; + Status = cCmdUnflattenFromByteArray(pArg3, &Offset, Arg1, 0); + + //!!! Status ignored from cCmdUnflattenFromByteArray + // If future revisions of this function provide better error checking, + // Err arg should be conditionally set based on the result. + //Unflatten succeeded; set Err arg to FALSE + cCmdSetVal(pArg2, TypeCode2, FALSE); + + NXT_ASSERT(Offset == Size); + } + else + { + //Unflatten failed; set Err arg to TRUE + cCmdSetVal(pArg2, TypeCode2, TRUE); + } + } + break; + + case OP_STRINGTONUM: + { + + // Arg1 - Dst number (output) + // Arg2 - Offset past match (output) + // Arg3 - Src string + // Arg4 - Offset + // Arg5 - Default (type/value) + + //!!! Currently, both outputs must have valid destinations. + // It would be trivial to handle NOT_A_DS_ID to avoid dummy + // allocations when outputs are unused. + + Arg1 = pCode[1]; + Arg2 = pCode[2]; + Arg3 = pCode[3]; + Arg4 = pCode[4]; + Arg5 = pCode[5]; + + pArg1 = cCmdResolveDataArg(Arg1, 0, &TypeCode1); + pArg2 = cCmdResolveDataArg(Arg2, 0, &TypeCode2); + pArg3 = cCmdResolveDataArg(Arg3, 0, &TypeCode3); + + if (Arg4 != NOT_A_DS_ID) + { + pArg4 = cCmdResolveDataArg(Arg4, 0, &TypeCode4); + ArgVal4 = cCmdGetVal(pArg4, TypeCode4); + } + else //Offset input unwired + { + ArgVal4 = 0; + } + + if (Arg5 != NOT_A_DS_ID) + { + pArg5 = cCmdResolveDataArg(Arg5, 0, &TypeCode5); + ArgVal5 = cCmdGetVal(pArg5, TypeCode5); + } + else //Default input unwired + { + ArgVal5 = 0; + } + + //Read number from string + if (sscanf(((PSZ)pArg3 + ArgVal4), "%d", &ArgVal1) == 1) + { + i = (UWORD)ArgVal4; + //Scan until we see the number + while ((((UBYTE *)pArg3)[i] < '0') || (((UBYTE *)pArg3)[i] > '9')) + i++; + + //Scan until we get past the number + while ((((UBYTE *)pArg3)[i] >= '0') && (((UBYTE *)pArg3)[i] <= '9')) + i++; + + ArgVal2 = i; + } + else + { + //Number wasn't found in string, use defaults + ArgVal1 = ArgVal5; + ArgVal2 = 0; + } + + //Set outputs + cCmdSetVal(pArg1, TypeCode1, ArgVal1); + cCmdSetVal(pArg2, TypeCode2, ArgVal2); + } + break; + + default: + { + //Fatal error: Unrecognized instruction + NXT_BREAK; + Status = ERR_INSTR; + } + break; + } + + return (Status); +} + + +// +//Support functions for lowspeed (I2C devices, i.e. ultrasonic sensor) communications +// + +//Simple lookup table for pMapLowSpeed->ChannelState[Port] values +//This is used to keep VM status code handling consistent +//...and ChannelState gives us too much information, anyway... +static const NXT_STATUS MapLStoVMStat[6] = +{ + NO_ERR, //LOWSPEED_IDLE, + STAT_COMM_PENDING, //LOWSPEED_INIT, + STAT_COMM_PENDING, //LOWSPEED_LOAD_BUFFER, + STAT_COMM_PENDING, //LOWSPEED_COMMUNICATING, + ERR_COMM_BUS_ERR, //LOWSPEED_ERROR, + STAT_COMM_PENDING, //LOWSPEED_DONE (really means c_lowspeed state machine is resetting) +}; + + +//cCmdLSCheckStatus +//Check lowspeed port status, optionally returning bytes available in the buffer for reading +NXT_STATUS cCmdLSCheckStatus(UBYTE Port) +{ + if (Port >= NO_OF_LOWSPEED_COM_CHANNEL) + { + return (ERR_COMM_CHAN_INVALID); + } + + //If port is not configured properly ahead of time, report that error + //!!! This seems like the right policy, but may restrict otherwise valid read operations... + if (!(pMapInput->Inputs[Port].SensorType == LOWSPEED_9V || pMapInput->Inputs[Port].SensorType == LOWSPEED) + || !(pMapInput->Inputs[Port].InvalidData == FALSE)) + { + return (ERR_COMM_CHAN_NOT_READY); + } + + return (MapLStoVMStat[pMapLowSpeed->ChannelState[Port]]); +} + +//cCmdLSCalcBytesReady +//Calculate true number of bytes available in the inbound LS buffer +UBYTE cCmdLSCalcBytesReady(UBYTE Port) +{ + SLONG Tmp; + + //Expect callers to validate Port, but short circuit here to be safe. + if (Port >= NO_OF_LOWSPEED_COM_CHANNEL) + return 0; + + //Normally, bytes available is a simple difference. + Tmp = pMapLowSpeed->InBuf[Port].InPtr - pMapLowSpeed->InBuf[Port].OutPtr; + + //If InPtr is actually behind OutPtr, circular buffer has wrapped. Account for wrappage... + if (Tmp < 0) + Tmp = (pMapLowSpeed->InBuf[Port].InPtr + (SIZE_OF_LSBUF - pMapLowSpeed->InBuf[Port].OutPtr)); + + return (UBYTE)(Tmp); +} + +//cCmdLSWrite +//Write BufLength bytes into specified port's lowspeed buffer and kick off comm process to device +NXT_STATUS cCmdLSWrite(UBYTE Port, UBYTE BufLength, UBYTE *pBuf, UBYTE ResponseLength) +{ + if (Port >= NO_OF_LOWSPEED_COM_CHANNEL) + { + return (ERR_COMM_CHAN_INVALID); + } + + if (BufLength > SIZE_OF_LSBUF || ResponseLength > SIZE_OF_LSBUF) + { + return (ERR_INVALID_SIZE); + } + + //Only start writing process if port is properly configured and c_lowspeed module is ready + if ((pMapInput->Inputs[Port].SensorType == LOWSPEED_9V || pMapInput->Inputs[Port].SensorType == LOWSPEED) + && (pMapInput->Inputs[Port].InvalidData == FALSE) + && (pMapLowSpeed->ChannelState[Port] == LOWSPEED_IDLE) || (pMapLowSpeed->ChannelState[Port] == LOWSPEED_ERROR)) + { + pMapLowSpeed->OutBuf[Port].InPtr = 0; + pMapLowSpeed->OutBuf[Port].OutPtr = 0; + + memcpy(pMapLowSpeed->OutBuf[Port].Buf, pBuf, BufLength); + pMapLowSpeed->OutBuf[Port].InPtr = (UBYTE)BufLength; + + pMapLowSpeed->InBuf[Port].BytesToRx = ResponseLength; + + pMapLowSpeed->ChannelState[Port] = LOWSPEED_INIT; + pMapLowSpeed->State |= (COM_CHANNEL_ONE_ACTIVE << Port); + + return (NO_ERR); + } + else + { + //!!! Would be more consistent to return STAT_COMM_PENDING if c_lowspeed is busy + return (ERR_COMM_CHAN_NOT_READY); + } +} + + +//cCmdLSRead +//Read BufLength bytes from specified port's lowspeed buffer +NXT_STATUS cCmdLSRead(UBYTE Port, UBYTE BufLength, UBYTE * pBuf) +{ + UBYTE BytesReady, BytesToRead; + + if (Port >= NO_OF_LOWSPEED_COM_CHANNEL) + { + return (ERR_COMM_CHAN_INVALID); + } + + if (BufLength > SIZE_OF_LSBUF) + { + return (ERR_INVALID_SIZE); + } + + BytesReady = cCmdLSCalcBytesReady(Port); + + if (BufLength > BytesReady) + { + return (ERR_COMM_CHAN_NOT_READY); + } + + BytesToRead = BufLength; + + //If the bytes we want to read wrap around the end, we must first read the end, then reset back to the beginning + if (pMapLowSpeed->InBuf[Port].OutPtr + BytesToRead >= SIZE_OF_LSBUF) + { + BytesToRead = SIZE_OF_LSBUF - pMapLowSpeed->InBuf[Port].OutPtr; + memcpy(pBuf, pMapLowSpeed->InBuf[Port].Buf + pMapLowSpeed->InBuf[Port].OutPtr, BytesToRead); + pMapLowSpeed->InBuf[Port].OutPtr = 0; + pBuf += BytesToRead; + BytesToRead = BufLength - BytesToRead; + } + + memcpy(pBuf, pMapLowSpeed->InBuf[Port].Buf + pMapLowSpeed->InBuf[Port].OutPtr, BytesToRead); + pMapLowSpeed->InBuf[Port].OutPtr += BytesToRead; + + return (NO_ERR); +} + + +// +//Wrappers for OP_SYSCALL +// + +// +//cCmdWrapFileOpenRead +//ArgV[0]: (Function return) Loader status, U16 return +//ArgV[1]: File Handle, U8 return +//ArgV[2]: Filename, CStr +//ArgV[3]: Length, U32 return +NXT_STATUS cCmdWrapFileOpenRead(UBYTE * ArgV[]) +{ + LOADER_STATUS LStatus; + DV_INDEX DVIndex; + + //Resolve array argument + DVIndex = *(DV_INDEX *)(ArgV[2]); + ArgV[2] = cCmdDVPtr(DVIndex); + + LStatus = pMapLoader->pFunc(OPENREAD, ArgV[2], NULL, (ULONG *)ArgV[3]); + + //Add entry into FileHandleTable + if (LOADER_ERR(LStatus) == SUCCESS) + { + VarsCmd.FileHandleTable[LOADER_HANDLE(LStatus)][0] = 'r'; + strcpy((PSZ)(VarsCmd.FileHandleTable[LOADER_HANDLE(LStatus)] + 1), (PSZ)(ArgV[2])); + } + + //Status code in high byte of LStatus + *((UWORD *)ArgV[0]) = LOADER_ERR(LStatus); + //File handle in low byte of LStatus + *(ArgV[1]) = LOADER_HANDLE(LStatus); + + return NO_ERR; +} + +//cCmdWrapFileOpenWrite +//ArgV[0]: (Function return) Loader status, U16 return +//ArgV[1]: File Handle, U8 return +//ArgV[2]: Filename, CStr +//ArgV[3]: Length, U32 return +NXT_STATUS cCmdWrapFileOpenWrite(UBYTE * ArgV[]) +{ + LOADER_STATUS LStatus; + DV_INDEX DVIndex; + + //Resolve array argument + DVIndex = *(DV_INDEX *)(ArgV[2]); + ArgV[2] = cCmdDVPtr(DVIndex); + + LStatus = pMapLoader->pFunc(OPENWRITEDATA, ArgV[2], NULL, (ULONG *)ArgV[3]); + + //Add entry into FileHandleTable + if (LOADER_ERR(LStatus) == SUCCESS) + { + VarsCmd.FileHandleTable[LOADER_HANDLE(LStatus)][0] = 'w'; + strcpy((PSZ)(VarsCmd.FileHandleTable[LOADER_HANDLE(LStatus)] + 1), (PSZ)(ArgV[2])); + } + + //Status code in high byte of LStatus + *((UWORD *)ArgV[0]) = LOADER_ERR(LStatus); + //File handle in low byte of LStatus + *(ArgV[1]) = LOADER_HANDLE(LStatus); + + return NO_ERR; +} + +//cCmdWrapFileOpenAppend +//ArgV[0]: (Function return) Loader status, U16 return +//ArgV[1]: File Handle, U8 return +//ArgV[2]: Filename, CStr +//ArgV[3]: Length Remaining, U32 return +NXT_STATUS cCmdWrapFileOpenAppend(UBYTE * ArgV[]) +{ + LOADER_STATUS LStatus; + DV_INDEX DVIndex; + + //Resolve array argument + DVIndex = *(DV_INDEX *)(ArgV[2]); + ArgV[2] = cCmdDVPtr(DVIndex); + + LStatus = pMapLoader->pFunc(OPENAPPENDDATA, ArgV[2], NULL, (ULONG *)ArgV[3]); + + //Add entry into FileHandleTable + if (LOADER_ERR(LStatus) == SUCCESS) + { + VarsCmd.FileHandleTable[LOADER_HANDLE(LStatus)][0] = 'w'; + strcpy((PSZ)(VarsCmd.FileHandleTable[LOADER_HANDLE(LStatus)] + 1), (PSZ)(ArgV[2])); + } + + //Status code in high byte of LStatus + *((UWORD *)ArgV[0]) = LOADER_ERR(LStatus); + //File handle in low byte of LStatus + *(ArgV[1]) = LOADER_HANDLE(LStatus); + + return NO_ERR; +} + +//cCmdWrapFileRead +//ArgV[0]: (Function return) Loader status, U16 return +//ArgV[1]: File Handle, U8 in/out +//ArgV[2]: Buffer, CStr out +//ArgV[3]: Length, U32 in/out +NXT_STATUS cCmdWrapFileRead(UBYTE * ArgV[]) +{ + NXT_STATUS Status = NO_ERR; + LOADER_STATUS LStatus; + DV_INDEX DVIndex; + + //Resolve array argument + DVIndex = *(DV_INDEX *)(ArgV[2]); + //Size Buffer to Length + //Add room for null terminator to length + Status = cCmdDVArrayAlloc(DVIndex, (UWORD)(*(ULONG *)ArgV[3] + 1)); + if (IS_ERR(Status)) + return Status; + + ArgV[2] = cCmdDVPtr(DVIndex); + LStatus = pMapLoader->pFunc(READ, ArgV[1], ArgV[2], (ULONG *)ArgV[3]); + + //Tack on NULL terminator + //Note that loader code may have adjusted length (*ArgV[3]) if all requested data was not available + //!!! Better solution would be to resize buffer to new length + 1, + // but then you must also be wary of side effects if resize allocation fails! + *(ArgV[2] + *(ULONG *)ArgV[3]) = '\0'; + + //Status code in high byte of LStatus + *((UWORD *)ArgV[0]) = LOADER_ERR(LStatus); + //File handle in low byte of LStatus + *(ArgV[1]) = LOADER_HANDLE(LStatus); + + return Status; +} + +//cCmdWrapFileWrite +//ArgV[0]: (Function return) Loader status, U16 return +//ArgV[1]: File Handle, U8 in/out +//ArgV[2]: Buffer, CStr +//ArgV[3]: Length, U32 return +NXT_STATUS cCmdWrapFileWrite(UBYTE * ArgV[]) +{ + LOADER_STATUS LStatus; + DV_INDEX DVIndex; + + //Resolve array argument + DVIndex = *(DV_INDEX *)(ArgV[2]); + ArgV[2] = cCmdDVPtr(DVIndex); + + LStatus = pMapLoader->pFunc(WRITE, ArgV[1], ArgV[2], (ULONG *)ArgV[3]); + + //Status code in high byte of LStatus + *((UWORD *)ArgV[0]) = LOADER_ERR(LStatus); + //File handle in low byte of LStatus + *(ArgV[1]) = LOADER_HANDLE(LStatus); + + return NO_ERR; +} + +//cCmdWrapFileClose +//ArgV[0]: (Function return) Loader status, U16 return +//ArgV[1]: File Handle, U8 +NXT_STATUS cCmdWrapFileClose(UBYTE * ArgV[]) +{ + LOADER_STATUS LStatus; + + //!!! This bounds check also exists in dLoaderCloseHandle(), but we provide an explicit error code + if (*(ArgV[1]) >= MAX_HANDLES) + { + *((UWORD *)ArgV[0]) = ILLEGALHANDLE; + return NO_ERR; + } + + LStatus = pMapLoader->pFunc(CLOSE, ArgV[1], NULL, NULL); + + //Clear entry in FileHandleTable + memset(VarsCmd.FileHandleTable[*(ArgV[1])], 0, FILENAME_LENGTH + 2); + + //Status code in high byte of LStatus + *((UWORD *)ArgV[0]) = LOADER_ERR(LStatus); + + return NO_ERR; +} + +//cCmdWrapFileResolveHandle +//ArgV[0]: (Function return) Loader status, U16 return +//ArgV[1]: File Handle, U8 return +//ArgV[2]: Write Handle?, Bool return +//ArgV[3]: Filename, CStr +NXT_STATUS cCmdWrapFileResolveHandle (UBYTE * ArgV[]) +{ + UBYTE i; + DV_INDEX DVIndex; + + //Resolve array argument + DVIndex = *(DV_INDEX *)(ArgV[3]); + ArgV[3] = cCmdDVPtr(DVIndex); + + for (i = 0; i < MAX_HANDLES; i++) + { + if (strcmp((PSZ)(ArgV[3]), (PSZ)(VarsCmd.FileHandleTable[i] + 1)) == 0) + { + *(ArgV[2]) = (VarsCmd.FileHandleTable[i][0] == 'w'); + break; + } + } + + if (i == MAX_HANDLES) + { + i = NOT_A_HANDLE; + *((UWORD *)ArgV[0]) = HANDLEALREADYCLOSED; + } + else + { + *((UWORD *)ArgV[0]) = SUCCESS; + } + + *(ArgV[1]) = i; + + return NO_ERR; +} + + +//cCmdWrapFileRename +//ArgV[0]: (Function return) Loader status, U16 return +//ArgV[1]: Old Filename, CStr +//ArgV[2]: New Filename, CStr +NXT_STATUS cCmdWrapFileRename (UBYTE * ArgV[]) +{ + LOADER_STATUS LStatus; + ULONG Tmp; + DV_INDEX DVIndex; + + //Resolve array arguments + DVIndex = *(DV_INDEX *)(ArgV[1]); + ArgV[1] = cCmdDVPtr(DVIndex); + DVIndex = *(DV_INDEX *)(ArgV[2]); + ArgV[2] = cCmdDVPtr(DVIndex); + + //!!! Tmp placeholder passed into loader code to avoid illegal dereferencing. + LStatus = pMapLoader->pFunc(RENAMEFILE, ArgV[1], ArgV[2], &Tmp); + + //Status code in high byte of LStatus + *((UWORD *)ArgV[0]) = LOADER_ERR(LStatus); + + return NO_ERR; +} + + +//cCmdWrapFileDelete +//ArgV[0]: (Function return) Loader status, U16 return +//ArgV[1]: Filename, CStr +NXT_STATUS cCmdWrapFileDelete (UBYTE * ArgV[]) +{ + LOADER_STATUS LStatus; + DV_INDEX DVIndex; + + //Resolve array arguments + DVIndex = *(DV_INDEX *)(ArgV[1]); + ArgV[1] = cCmdDVPtr(DVIndex); + + LStatus = pMapLoader->pFunc(DELETE, ArgV[1], NULL, NULL); + + //Status code in high byte of LStatus + *((UWORD *)ArgV[0]) = LOADER_ERR(LStatus); + + return NO_ERR; +} + +// +//cCmdWrapSoundPlayFile +//ArgV[0]: (Return value) Status code, SBYTE +//ArgV[1]: Filename, CStr +//ArgV[2]: Loop?, UBYTE (bool) +//ArgV[3]: Volume, UBYTE +// +NXT_STATUS cCmdWrapSoundPlayFile(UBYTE * ArgV[]) +{ + DV_INDEX DVIndex; + + //Resolve array arguments + DVIndex = *(DV_INDEX *)(ArgV[1]); + ArgV[1] = cCmdDVPtr(DVIndex); + + //!!! Should check filename and/or existence and return error before proceeding + strncpy((PSZ)(pMapSound->SoundFilename), (PSZ)(ArgV[1]), FILENAME_LENGTH); + + if (*(ArgV[2]) == TRUE) + pMapSound->Mode = SOUND_LOOP; + else + pMapSound->Mode = SOUND_ONCE; + + pMapSound->Volume = *(ArgV[3]); + //SampleRate of '0' means "let file specify SampleRate" + pMapSound->SampleRate = 0; + pMapSound->Flags |= SOUND_UPDATE; + + *((SBYTE*)(ArgV[0])) = (NO_ERR); + + return (NO_ERR); +} + +// +//cCmdWrapSoundPlayTone +//ArgV[0]: (Return value) Status code, SBYTE +//ArgV[1]: Frequency, UWORD +//ArgV[2]: Duration, UWORD +//ArgV[3]: Loop?, UBYTE (Boolean) +//ArgV[4]: Volume, UBYTE +// +NXT_STATUS cCmdWrapSoundPlayTone(UBYTE * ArgV[]) +{ + pMapSound->Freq = *(UWORD*)(ArgV[1]); + pMapSound->Duration = *(UWORD*)(ArgV[2]); + pMapSound->Volume = *(ArgV[4]); + pMapSound->Flags |= SOUND_UPDATE; + + if (*(ArgV[3]) == TRUE) + pMapSound->Mode = SOUND_TONE | SOUND_LOOP; + else + pMapSound->Mode = SOUND_TONE; + + *((SBYTE*)(ArgV[0])) = (NO_ERR); + + return (NO_ERR); +} + +// +//cCmdWrapSoundGetState +//ArgV[0]: (Return value) sound module state, UBYTE +//ArgV[1]: Flags, UBYTE +// +NXT_STATUS cCmdWrapSoundGetState(UBYTE * ArgV[]) +{ + *(ArgV[0]) = pMapSound->State; + *(ArgV[1]) = pMapSound->Flags; + return (NO_ERR); +} + +// +//cCmdWrapSoundSetState +//ArgV[0]: (Return value) sound module state, UBYTE +//ArgV[1]: State, UBYTE +//ArgV[2]: Flags, UBYTE +// +NXT_STATUS cCmdWrapSoundSetState(UBYTE * ArgV[]) +{ + pMapSound->State = *(ArgV[1]); + //Return same state we just set, mostly for interface consistency + *(ArgV[0]) = pMapSound->State; + + //OR in provided flags (usually 0) + pMapSound->Flags |= *(ArgV[2]); + + return (NO_ERR); +} + +// +//cCmdWrapReadButton +//ArgV[0]: (Function return) Status code, SBYTE +//ArgV[1]: Index (U8) +//ArgV[2]: Pressed (bool) +//ArgV[3]: Count (U8) (count of press-then-release cycles) +//ArgV[4]: ResetCount? (bool in) +// +NXT_STATUS cCmdWrapReadButton(UBYTE * ArgV[]) +{ + UBYTE btnIndex; + + btnIndex = *((UBYTE*)(ArgV[1])); + + if (btnIndex < NO_OF_BTNS) + { + //Set pressed boolean output + if (pMapButton->State[btnIndex] & PRESSED_STATE) + *(ArgV[2]) = TRUE; + else + *(ArgV[2]) = FALSE; + + //Set count output + *(ArgV[3]) = (UBYTE)(pMapButton->BtnCnt[btnIndex].RelCnt); + + //Optionally reset internal count + if (*(ArgV[4]) != 0) + { + pMapButton->BtnCnt[btnIndex].RelCnt = 0; + //Need to clear short and long counts too, because RelCnt depends on them. No known side effects. + pMapButton->BtnCnt[btnIndex].ShortRelCnt = 0; + pMapButton->BtnCnt[btnIndex].LongRelCnt = 0; + } + + // Set status code 'OK' + *((SBYTE*)(ArgV[0])) = NO_ERR; + } + else + { + //Bad button index specified, return error and default outputs + *((SBYTE*)(ArgV[0])) = ERR_INVALID_PORT; + *(ArgV[2]) = FALSE; + *(ArgV[3]) = 0; + } + + return (NO_ERR); +} + +// +//cCmdWrapCommLSWrite +//ArgV[0]: (return) Status code, SBYTE +//ArgV[1]: Port specifier, UBYTE +//ArgV[2]: Buffer to send, UBYTE array, only SIZE_OF_LSBUF bytes will be used +//ArgV[3]: ResponseLength, UBYTE, specifies expected bytes back from slave device +// +NXT_STATUS cCmdWrapCommLSWrite(UBYTE * ArgV[]) +{ + SBYTE * pReturnVal = (SBYTE*)(ArgV[0]); + UBYTE Port = *(ArgV[1]); + UBYTE * pBuf; + UWORD BufLength; + UBYTE ResponseLength = *(ArgV[3]); + DV_INDEX DVIndex; + + //Resolve array arguments + DVIndex = *(DV_INDEX *)(ArgV[2]); + pBuf = cCmdDVPtr(DVIndex); + BufLength = DV_ARRAY[DVIndex].Count; + + *pReturnVal = cCmdLSWrite(Port, (UBYTE)BufLength, pBuf, ResponseLength); + + return (NO_ERR); +} + +// +//cCmdWrapCommLSCheckStatus +//ArgV[0]: (return) Status code, SBYTE +//ArgV[1]: Port specifier, UBYTE +//ArgV[2]: BytesReady, UBYTE +// +NXT_STATUS cCmdWrapCommLSCheckStatus(UBYTE * ArgV[]) +{ + UBYTE Port = *(ArgV[1]); + + *((SBYTE*)(ArgV[0])) = cCmdLSCheckStatus(Port); + *((UBYTE*)(ArgV[2])) = cCmdLSCalcBytesReady(Port); + + return (NO_ERR); +} + +// +//cCmdWrapCommLSRead +//ArgV[0]: (return) Status code, SBYTE +//ArgV[1]: Port specifier, UBYTE +//ArgV[2]: Buffer for data, UBYTE array, max SIZE_OF_LSBUF bytes will be written +//ArgV[3]: BufferLength, UBYTE, specifies size of buffer requested +// +NXT_STATUS cCmdWrapCommLSRead(UBYTE * ArgV[]) +{ + SBYTE * pReturnVal = (SBYTE*)(ArgV[0]); + UBYTE Port = *(ArgV[1]); + UBYTE * pBuf; + UBYTE BufLength = *(ArgV[3]); + UBYTE BytesToRead; + DV_INDEX DVIndex = *(DV_INDEX *)(ArgV[2]); + NXT_STATUS AllocStatus; + + *pReturnVal = cCmdLSCheckStatus(Port); + BytesToRead = cCmdLSCalcBytesReady(Port); + + //If channel is OK and has data ready for us, put the data into outgoing buffer + if (!IS_ERR(*pReturnVal) && BytesToRead > 0) + { + //Limit buffer to available data + if (BufLength > BytesToRead) + BufLength = BytesToRead; + + AllocStatus = cCmdDVArrayAlloc(DVIndex, BufLength); + if (IS_ERR(AllocStatus)) + return (AllocStatus); + + pBuf = cCmdDVPtr(DVIndex); + *pReturnVal = cCmdLSRead(Port, BufLength, pBuf); + } + //Else, the channel has an error and/or there's no data to read; clear the output array + else + { + AllocStatus = cCmdDVArrayAlloc(DVIndex, 0); + if (IS_ERR(AllocStatus)) + return (AllocStatus); + } + + return (NO_ERR); +} + +// +//cCmdWrapRandomNumber +//ArgV[0]: (return) Random number, SWORD +// +NXT_STATUS cCmdWrapRandomNumber(UBYTE * ArgV[]) +{ + static UBYTE count = 0; + SWORD random; + + if (count == 0) + srand(dTimerRead()); + + if (count > 20) + count = 0; + else + count++; + + //!!! IAR's implementation of the rand() library function returns signed values, and we want it that way. + //Some stdlib implementations may return only positive numbers, so be wary if this code is ported. + random = rand(); + + *((SWORD *)ArgV[0]) = random; + + return NO_ERR; +} + +// +//cCmdWrapGetStartTick +//ArgV[0]: (return) Start Tick, ULONG +// +NXT_STATUS cCmdWrapGetStartTick(UBYTE * ArgV[]) +{ + *((ULONG *)ArgV[0]) = VarsCmd.StartTick; + return NO_ERR; +} + +// +//cCmdWrapMessageWrite +//ArgV[0]: (return) Error Code, SBYTE (NXT_STATUS) +//ArgV[1]: QueueID, UBYTE +//ArgV[2]: Message, CStr +// +NXT_STATUS cCmdWrapMessageWrite(UBYTE * ArgV[]) +{ + NXT_STATUS Status = NO_ERR; + DV_INDEX DVIndex; + + //Resolve array arguments + DVIndex = *(DV_INDEX *)(ArgV[2]); + ArgV[2] = cCmdDVPtr(DVIndex); + + Status = cCmdMessageWrite(*(UBYTE *)(ArgV[1]), ArgV[2], DV_ARRAY[DVIndex].Count); + + *(SBYTE *)(ArgV[0]) = Status; + + if (IS_FATAL(Status)) + return Status; + else + return (NO_ERR); +} + +#define UNPACK_STATUS(StatusWord) ((SBYTE)(StatusWord)) + +NXT_STATUS cCmdBTCheckStatus(UBYTE Connection) +{ + //If specified connection is invalid, return error code to the user. + if (Connection >= SIZE_OF_BT_CONNECT_TABLE) + { + return (ERR_INVALID_PORT); + } + + //INPROGRESS means a request is currently pending completion by the comm module + if (VarsCmd.CommStat == INPROGRESS) + { + return (STAT_COMM_PENDING); + } + //Translate BTBUSY to ERR_COMM_CHAN_NOT_READY + //And check if specified connection is indeed configured + else if (VarsCmd.CommStat == (SWORD)BTBUSY + || (pMapComm->BtConnectTable[Connection].Name[0]) == '\0') + { + return (ERR_COMM_CHAN_NOT_READY); + } + else + { + return (UNPACK_STATUS(VarsCmd.CommStat)); + } +} + +//Default packet to send for a remote MESSAGE_READ command. +//3rd byte must be replaced with remote mailbox (QueueID) +//4th byte must be replaced with local mailbox +static UBYTE RemoteMsgReadPacket[5] = {0x00, 0x13, 0xFF, 0xFF, 0x01}; + +// +//cCmdWrapMessageRead +//ArgV[0]: (return) Error Code, SBYTE (NXT_STATUS) +//ArgV[1]: QueueID, UBYTE +//ArgV[2]: Remove, UBYTE +//ArgV[3]: (return) Message, CStr +// +NXT_STATUS cCmdWrapMessageRead(UBYTE * ArgV[]) +{ + NXT_STATUS Status = NO_ERR; + NXT_STATUS AllocStatus = NO_ERR; + UBYTE QueueID = *(UBYTE *)(ArgV[1]); + DV_INDEX DestDVIndex = *(DV_INDEX *)(ArgV[3]); + UWORD MessageSize; + UBYTE i; + + NXT_ASSERT(IS_DV_INDEX_SANE(DestDVIndex)); + + //Check Next Message's size + Status = cCmdMessageGetSize(QueueID, &MessageSize); + + //If there is a valid message in local mailbox, read it + if (!IS_ERR(Status) && MessageSize > 0 ) + { + //!!! Also check for EMPTY_MAILBOX status? + //Size destination string + AllocStatus = cCmdDVArrayAlloc(DestDVIndex, MessageSize); + if (IS_ERR(AllocStatus)) + return AllocStatus; + + //Get Message + //!!! Should more aggressively enforce null termination before blindly copying to dataspace + Status = cCmdMessageRead(QueueID, cCmdDVPtr(DestDVIndex), MessageSize, *(ArgV[2])); + } + else + { + //Clear destination string + AllocStatus = cCmdDVArrayAlloc(DestDVIndex, 1); + if (IS_ERR(AllocStatus)) + return AllocStatus; + + //Successful allocation, make sure first byte is null terminator + *(UBYTE*)(cCmdDVPtr(DestDVIndex)) = '\0'; + } + + //If there were no local messages, see if there are any waiting in our slaves' outboxes + if (Status == STAT_MSG_EMPTY_MAILBOX && QueueID < INCOMING_QUEUE_COUNT) + { + //If there's an old error code hanging around, clear it before proceeding. + //!!! Clearing error here means bytecode status checking loops could get false SUCCESS results? + if (VarsCmd.CommStat < 0) + VarsCmd.CommStat = SUCCESS; + + //Search through possible slaves, looking for valid connection + for (i = 0; i < SIZE_OF_BT_CONNECT_TABLE - 1; i++) + { + //Advance CommCurrConnection and limit to 1, 2, or 3 (only slave connection slots are checked) + VarsCmd.CommCurrConnection++; + if (VarsCmd.CommCurrConnection == SIZE_OF_BT_CONNECT_TABLE) + VarsCmd.CommCurrConnection = 1; + + if (cCmdBTCheckStatus(VarsCmd.CommCurrConnection) == NO_ERR) + break; + } + + //If there is at least one configured slave connection, make a remote read request + if (i < SIZE_OF_BT_CONNECT_TABLE - 1) + { + //Outgoing QueueID on slave device is the local QueueID + INCOMING_QUEUE_COUNT + RemoteMsgReadPacket[2] = QueueID + INCOMING_QUEUE_COUNT; + RemoteMsgReadPacket[3] = QueueID; + + //Request comm module to send assembled packet and not go idle until response comes back (or error) + pMapComm->pFunc(SENDDATA, sizeof(RemoteMsgReadPacket), VarsCmd.CommCurrConnection, TRUE, RemoteMsgReadPacket, (UWORD*)&(VarsCmd.CommStat)); + + //Read status back after SENDDATA call so bytecode gets STAT_COMM_PENDING or error + Status = cCmdBTCheckStatus(VarsCmd.CommCurrConnection); + + //If our request was accepted, set the DirtyComm flag so stream will get cleaned up later + if (Status == STAT_COMM_PENDING) + VarsCmd.DirtyComm = TRUE; + } + } + + *(SBYTE *)(ArgV[0]) = Status; + if (IS_FATAL(Status)) + return Status; + else + return (NO_ERR); +} + + +// +//cCmdWrapCommBTCheckStatus +//ArgV[0]: (return) Status byte, SBYTE +//ArgV[1]: Connection index, 0-3 +// +NXT_STATUS cCmdWrapCommBTCheckStatus(UBYTE * ArgV[]) +{ + *((SBYTE*)(ArgV[0])) = cCmdBTCheckStatus(*(ArgV[1])); + + return (NO_ERR); +} + +// +//cCmdWrapCommBTWrite +//ArgV[0]: (return) Status byte, SBYTE +//ArgV[1]: Connection index, 0-3 +//ArgV[2]: Buffer +// +NXT_STATUS cCmdWrapCommBTWrite(UBYTE * ArgV[]) +{ + SBYTE * pReturnVal = (SBYTE*)(ArgV[0]); + UBYTE Connection = *(ArgV[1]); + UBYTE * pBuf; + UWORD BufLength; + DV_INDEX DVIndex; + + //Resolve array arguments + DVIndex = *(DV_INDEX *)(ArgV[2]); + pBuf = cCmdDVPtr(DVIndex); + + BufLength = DV_ARRAY[DVIndex].Count; + + //If there's an old error code hanging around, clear it before proceeding. + if (VarsCmd.CommStat < 0) + VarsCmd.CommStat = SUCCESS; + + //!!! Only first 256 bytes could possibly make it through! Should return error on longer input? + //!!! Not requesting a wait-for-response because only known use doesn't read responses. + pMapComm->pFunc(SENDDATA, (UBYTE)BufLength, Connection, FALSE, pBuf, (UWORD*)&(VarsCmd.CommStat)); + + //!!! Reasonable to wrap below code in cCmdCommBTCheckStatus? + //INPROGRESS means our request was accepted by His Funkiness of pFunc + if (VarsCmd.CommStat == (SWORD)INPROGRESS) + { + *pReturnVal = STAT_COMM_PENDING; + + //Set DirtyComm flag so stream is reset after program ends + VarsCmd.DirtyComm = TRUE; + } + //Translate BTBUSY to ERR_COMM_CHAN_NOT_READY + else if (VarsCmd.CommStat == (SWORD)BTBUSY) + { + *pReturnVal = ERR_COMM_CHAN_NOT_READY; + } + else + { + *pReturnVal = UNPACK_STATUS(VarsCmd.CommStat); + } + + return (NO_ERR); +} + +// +//cCmdWrapCommBTRead +//ArgV[0]: (return) Status byte, SBYTE +//ArgV[1]: Count to read +//ArgV[2]: Buffer +// +NXT_STATUS cCmdWrapCommBTRead(UBYTE * ArgV[]) +{ + //SBYTE * pReturnVal = (SBYTE*)(ArgV[0]); + //UBYTE * pBuf = (ArgV[2]); + //!!! should provide length and/or connection to read? + + //!!! This syscall is not implemented; return fatal error. + return (ERR_INSTR); +} + +// +//cCmdWrapKeepAlive +//ArgV[0]: (return) Current timer limit in ms, ULONG +// +NXT_STATUS cCmdWrapKeepAlive(UBYTE * ArgV[]) +{ + pMapUi->Flags |= UI_RESET_SLEEP_TIMER; + + //Convert UI's minute-based timeout value to millisecs + //Milliseconds are the "natural" time unit in user-land. + *(ULONG*)(ArgV[0]) = (pMapUi->SleepTimeout * 60 * 1000); + + return (NO_ERR); +} + +#define MAX_IOM_BUFFER_SIZE 64 +// +//cCmdWrapIOMapRead +//ArgV[0]: (return) Status byte, SBYTE +//ArgV[1]: Module name, CStr +//ArgV[2]: Offset, UWORD +//ArgV[3]: Count, UWORD +//ArgV[4]: Buffer, UBYTE array +// +NXT_STATUS cCmdWrapIOMapRead(UBYTE * ArgV[]) +{ + UWORD LStatus; + NXT_STATUS Status; + + SBYTE * pReturnVal = (SBYTE*)(ArgV[0]); + UWORD Offset = *(UWORD*)(ArgV[2]); + //Our copy of 'Count' must be a ULONG to match the loader interface + ULONG Count = *(UWORD*)(ArgV[3]); + + DV_INDEX DVIndex; + + //Buffer for return of FINDFIRSTMODULE call, structure defined in protocol doc + //We need it to transfer the ModuleID to the IOMAPREAD call + UBYTE FindBuffer[FILENAME_LENGTH + 10]; + //Buffer to store data and offset in for IOMAPREAD call + //!!! Constant size means only limited reads and writes + UBYTE DataBuffer[MAX_IOM_BUFFER_SIZE + 2]; + + if (Count > MAX_IOM_BUFFER_SIZE) + { + //Request to read too much data at once; clear buffer, return error. + DVIndex = *(DV_INDEX *)(ArgV[4]); + *pReturnVal = cCmdDVArrayAlloc(DVIndex, 0); + if (IS_ERR(*pReturnVal)) + return (*pReturnVal); + + *pReturnVal = ERR_INVALID_SIZE; + return (NO_ERR); + } + + //Resolve module name + DVIndex = *(DV_INDEX *)(ArgV[1]); + ArgV[1] = cCmdDVPtr(DVIndex); + + //Find module by name. Note that wildcards are accepted, but only first match matters. + LStatus = pMapLoader->pFunc(FINDFIRSTMODULE, ArgV[1], FindBuffer, NULL); + + if (LOADER_ERR(LStatus) == SUCCESS) + { + //Module was found, transfer Offset into first two bytes of DataBuffer and attempt to read + *(UWORD*)(DataBuffer) = Offset; + LStatus = pMapLoader->pFunc(IOMAPREAD, &(FindBuffer[FILENAME_LENGTH + 1]), DataBuffer, &Count); + + if (LOADER_ERR(LStatus) == SUCCESS) + { + //No error from IOMAPREAD, so copy the data into VM's dataspace + //Size destination array + DVIndex = *(DV_INDEX *)(ArgV[4]); + Status = cCmdDVArrayAlloc(DVIndex, (UWORD)Count); + if (IS_ERR(Status)) + { + //Alloc failed, so close handle and return + pMapLoader->pFunc(CLOSEMODHANDLE, NULL, NULL, NULL); + return (Status); + } + + //Alloc succeeded, so resolve and copy away + ArgV[4] = cCmdDVPtr(DVIndex); + memcpy(ArgV[4], &(DataBuffer[2]), Count); + } + } + + *pReturnVal = LOADER_ERR_BYTE(LStatus); + + pMapLoader->pFunc(CLOSEMODHANDLE, NULL, NULL, NULL); + return (NO_ERR); +} + +// +//cCmdWrapIOMapWrite +//ArgV[0]: (return) Status byte, SBYTE +//ArgV[1]: Module name, CStr +//ArgV[2]: Offset, UWORD +//ArgV[3]: Buffer, UBYTE array +// +NXT_STATUS cCmdWrapIOMapWrite(UBYTE * ArgV[]) +{ + UWORD LStatus; + + SBYTE * pReturnVal = (SBYTE*)(ArgV[0]); + UWORD Offset = *(UWORD*)(ArgV[2]); + + //Our copy of 'Count' must be a ULONG to match the loader interface + ULONG Count; + DV_INDEX DVIndex; + + //Buffer for return of FINDFIRSTMODULE call, structure defined in protocol doc + //We need it to transfer the ModuleID to the IOMAPREAD call + UBYTE FindBuffer[FILENAME_LENGTH + 10]; + //Buffer to store data and offset in for IOMAPREAD call + //!!! Constant size means only limited reads and writes + UBYTE DataBuffer[MAX_IOM_BUFFER_SIZE + 2]; + + //Resolve module name and buffer + DVIndex = *(DV_INDEX *)(ArgV[1]); + ArgV[1] = cCmdDVPtr(DVIndex); + + DVIndex = *(DV_INDEX *)(ArgV[3]); + ArgV[3] = cCmdDVPtr(DVIndex); + Count = DV_ARRAY[DVIndex].Count; + + if (Count > MAX_IOM_BUFFER_SIZE) + { + //Request to read too much data at once; return error and give up + *pReturnVal = ERR_INVALID_SIZE; + return (NO_ERR); + } + + LStatus = pMapLoader->pFunc(FINDFIRSTMODULE, ArgV[1], FindBuffer, NULL); + + if (LOADER_ERR(LStatus) == SUCCESS) + { + //Module was found, transfer Offset into first two bytes of DataBuffer, copy data into rest of buffer, then write + *(UWORD*)(DataBuffer) = Offset; + memcpy(&(DataBuffer[2]), ArgV[3], Count); + LStatus = pMapLoader->pFunc(IOMAPWRITE, &(FindBuffer[FILENAME_LENGTH + 1]), DataBuffer, &Count); + } + + *pReturnVal = LOADER_ERR_BYTE(LStatus); + + pMapLoader->pFunc(CLOSEMODHANDLE, NULL, NULL, NULL); + return (NO_ERR); +} + +#if VM_BENCHMARK +void cCmdWriteBenchmarkFile() +{ + LOADER_STATUS LStatus; + UBYTE Handle; + ULONG BenchFileSize; + ULONG i, Length; + UBYTE Buffer[256]; + + //Remove old benchmark file, create a new one + strcpy((char *)Buffer, "benchmark.txt"); + pMapLoader->pFunc(DELETE, Buffer, NULL, NULL); + BenchFileSize = 2048; + LStatus = pMapLoader->pFunc(OPENWRITEDATA, Buffer, NULL, &BenchFileSize); + + if (!LOADER_ERR(LStatus)) + { + //Write Benchmark file + Handle = LOADER_HANDLE(LStatus); + + //Header + sprintf((char *)Buffer, "Program Name: %s\r\n", VarsCmd.ActiveProgName); + Length = strlen((char *)Buffer); + LStatus = pMapLoader->pFunc(WRITE, &Handle, Buffer, &Length); + + sprintf((char *)Buffer, "InstrCount: %d\r\n", VarsCmd.InstrCount); + Length = strlen((char *)Buffer); + LStatus = pMapLoader->pFunc(WRITE, &Handle, Buffer, &Length); + + sprintf((char *)Buffer, "Time: %d\r\n", IOMapCmd.Tick - VarsCmd.StartTick); + Length = strlen((char *)Buffer); + LStatus = pMapLoader->pFunc(WRITE, &Handle, Buffer, &Length); + + sprintf((char *)Buffer, "Instr/Tick: %d\r\n", VarsCmd.Average); + Length = strlen((char *)Buffer); + LStatus = pMapLoader->pFunc(WRITE, &Handle, Buffer, &Length); + + sprintf((char *)Buffer, "CmdCtrl Calls: %d\r\n", VarsCmd.CmdCtrlCount); + Length = strlen((char *)Buffer); + LStatus = pMapLoader->pFunc(WRITE, &Handle, Buffer, &Length); + + sprintf((char *)Buffer, "OverTime Rounds: %d\r\n", VarsCmd.OverTimeCount); + Length = strlen((char *)Buffer); + LStatus = pMapLoader->pFunc(WRITE, &Handle, Buffer, &Length); + + sprintf((char *)Buffer, "Max OverTime Length: %d\r\n", VarsCmd.MaxOverTimeLength); + Length = strlen((char *)Buffer); + LStatus = pMapLoader->pFunc(WRITE, &Handle, Buffer, &Length); + + sprintf((char *)Buffer, "CompactionCount: %d\r\n", VarsCmd.CompactionCount); + Length = strlen((char *)Buffer); + LStatus = pMapLoader->pFunc(WRITE, &Handle, Buffer, &Length); + + sprintf((char *)Buffer, "LastCompactionTick: %d\r\n", VarsCmd.LastCompactionTick); + Length = strlen((char *)Buffer); + LStatus = pMapLoader->pFunc(WRITE, &Handle, Buffer, &Length); + + sprintf((char *)Buffer, "MaxCompactionTime: %d\r\n", VarsCmd.MaxCompactionTime); + Length = strlen((char *)Buffer); + LStatus = pMapLoader->pFunc(WRITE, &Handle, Buffer, &Length); + + //opcode benchmarks + sprintf((char *)Buffer, "Op\tCnt\tOver\tMax\r\n"); + Length = strlen((char *)Buffer); + LStatus = pMapLoader->pFunc(WRITE, &Handle, Buffer, &Length); + for (i = 0; i < OPCODE_COUNT; i++) + { + sprintf((char *)Buffer, "%x\t%d\t%d\t%d\t%d\r\n", i, VarsCmd.OpcodeBenchmarks[i][0], VarsCmd.OpcodeBenchmarks[i][1], VarsCmd.OpcodeBenchmarks[i][2], VarsCmd.OpcodeBenchmarks[i][3]); + Length = strlen((char *)Buffer); + LStatus = pMapLoader->pFunc(WRITE, &Handle, Buffer, &Length); + } + //close file + LStatus = pMapLoader->pFunc(CLOSE, &Handle, NULL, NULL); + } +} +#endif + +#ifdef SIM_NXT +// Accessors for simulator library code +SWORD cCmdGetCodeWord(CLUMP_ID Clump, CODE_INDEX Index) +{ + if (Clump == NOT_A_CLUMP) + { + NXT_ASSERT(Index < VarsCmd.CodespaceCount); + return (VarsCmd.pCodespace[Index]); + } + else + { + NXT_ASSERT(cCmdIsClumpIDSane(Clump)); + return (((SWORD)VarsCmd.pCodespace[VarsCmd.pAllClumps[Clump].CodeStart + Index])); + } +} + + +UBYTE * cCmdGetDataspace(UWORD *DataspaceSize) +{ + if (DataspaceSize) + *DataspaceSize = VarsCmd.DataspaceSize; + return (VarsCmd.pDataspace); +} + + +DOPE_VECTOR * cCmdGetDopeVectorPtr() +{ + return VarsCmd.MemMgr.pDopeVectorArray; +} + + +MEM_MGR cCmdGetMemMgr(void) +{ + return VarsCmd.MemMgr; +} + + +ULONG cCmdGetPoolSize() +{ + return VarsCmd.PoolSize; +} +#endif + +#else //!ENABLE_VM +// +//Implementations of standard interface if VM is disabled. +//Place low-level test code here if VM is causing issues. +//Test code must implement cCmdInit(), cCmdCtrl(), and cCmdExit() at a minimum. +//Recommend using a pattern like #include "c_cmd_alternate.c" +// + +//!!! !ENABLE_VM implementations really should provide a placeholder function for this pointer +//IOMapCmd.pRCHandler = &cCmdHandleRemoteCommands; +//#include "c_cmd_alternate.c" +//#include "c_cmd_FB_LowSpeed_Test.c" +//#include "c_cmd_FB_LowSpeed_JB_Compass.c" +//#include "c_cmd_FB_LowSpeed_Continius.c" +//#include "c_cmd_FB_LowSpeed_JB_Color.c" +#include "c_cmd_FB_LowSpeed_NorthStar_Demo2.c" +//#include "c_cmd_FB_LowSpeed_LEGO_TEST.c" + +#endif //ENABLE_VM diff --git a/AT91SAM7S256/Source/c_cmd.h b/AT91SAM7S256/Source/c_cmd.h new file mode 100644 index 0000000..04f10a3 --- /dev/null +++ b/AT91SAM7S256/Source/c_cmd.h @@ -0,0 +1,804 @@ +// +// Date init 14.12.2004 +// +// Revision date $Date:: 24-07-06 8:52 $ +// +// Filename $Workfile:: c_cmd.h $ +// +// Version $Revision:: 43 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/c_cmd.h $ +// +// Platform C +// + +// +// File Description: +// This file contains definitions and prototypes for the VM which runs bytecode +// programs compatible with LEGO MINDSTORMS NXT Software 1.0. +// + +#ifndef C_CMD +#define C_CMD + +//!!! MAX_HANDLES also defined in m_sched.h +#ifndef MAX_HANDLES +#define MAX_HANDLES 16 +#endif + +#include "c_cmd_bytecodes.h" +#define SYSCALL_COUNT 34 + +extern const HEADER cCmd; + +// +//Standard interface to other modules +// +void cCmdInit(void* pHeader); +void cCmdCtrl(void); +void cCmdExit(void); + +// +//ARM_NXT vs SIM_NXT +//These definitions are set up to allow compiling this code for use in a simulated (non-ARM7) environment. +//If your toolchain doesn't automatically use the __ICCARM__ token, define it to ensure normal compilation. +// +#ifdef __ICCARM__ +#define ARM_NXT +#else +#define SIM_NXT +#endif + +// +//ENABLE_VM toggles compilation the main body of VM code. +//Define it as 0 to compile alternate implementation for testing (see bottom of c_cmd.c) +// +#define ENABLE_VM 1 + +// +//VM_BENCHMARK enables extra instrumentation code to measure VM performance. +//When enabled, a file named "benchmark.txt" is produced every time a program completes. +// +#define VM_BENCHMARK (ENABLE_VM && 0) //<-- Toggle to turn on benchmark calculations + +#if VM_BENCHMARK +//Prototype for benchmark recording function +void cCmdWriteBenchmarkFile(); +#endif + +// +//Run-time assert macros +//Use these to test for unexpected conditions +//If expr evaluates as false while running under a debugger, +// a software breakpoint exception is thrown. +//NXT_BREAK is just a shortcut for unconditional break. +// +//Assert definitions behind WIN_DEBUG only make sense when compiling SIM_NXT +// under an x86 Windows debugger. +// +#if defined WIN_DEBUG +//"int 3" is a break exception on x86 +#define NXT_ASSERT(expr) if (expr) {} else { __asm {int 3} } +#define NXT_BREAK NXT_ASSERT(0) +// +//Assert definitions behind ARM_DEBUG aren't quite as handy as WIN_DEBUG, +// but they do record the code line causing the last assert failure. +// +#elif defined ARM_DEBUG +#define NXT_ASSERT(expr) if (expr) {}\ + else\ + {\ + VarsCmd.AssertFlag = TRUE;\ + VarsCmd.AssertLine = __LINE__;\ + } +#define NXT_BREAK NXT_ASSERT(0); +#else +//Not debugging, so #defined as nothing +//!!! Note that these definitions means all usages of NXT_ASSERT and NXT_BREAK +// get stripped out of an unmodified ARM7 build. +//Unless ARM_DEBUG is enabled, treat them as documentation of expected values. +#define NXT_ASSERT(expr) +#define NXT_BREAK +#endif + +// +//Status byte used to return requests for further action or errors +//Valid codes #defined in c_cmd.iom +//!!!JLOFTUS Replace with NXT_STATUS? Same for ASSERTS? Others? Risk factors? +// +typedef SBYTE NXT_STATUS; + +//dTimerRead() constantly returns latest system MS tick, so empty loop is convenient macro +#define BUSY_WAIT_NEXT_MS while (IOMapCmd.Tick == dTimerRead()) + +#if ENABLE_VM + +//Intial values for clump records are packed into 4 bytes in the file format. +#define VM_FILE_CLUMP_REC_SIZE 4 + +// +// Definitions for dataspace management, IO Map (IOM) access, and bytecode instruction structure +// + +//Type codes for use in the dataspace table-of-contents (DSTOC) +typedef UBYTE TYPE_CODE; + +enum +{ + //VOID type for unused DS elements; never valid to address them from bytecode + TC_VOID, + + //Simple scalar integers, equivalent to matching basic types from stdconst.h + TC_UBYTE, + TC_SBYTE, + TC_UWORD, + TC_SWORD, + TC_ULONG, + TC_SLONG, + + //Aggregate types containing one or more scalar + TC_ARRAY, + TC_CLUSTER, + + //Mutex tracks current holder and any waiting clumps + TC_MUTEX +}; + +//Sizes (in bytes) of each scalar type +#define SIZE_UBYTE 1 +#define SIZE_SBYTE 1 +#define SIZE_UWORD 2 +#define SIZE_SWORD 2 +#define SIZE_ULONG 4 +#define SIZE_SLONG 4 + +//MUTEX record is a struct containing 3 8-bit CLUMP_IDs, packed into 32-bit word +//See MUTEX_Q typedef +#define SIZE_MUTEX 4 + +//Module IDs for IO map addressing +enum +{ + MOD_INPUT, + MOD_OUTPUT +}; + +//Field IDs for input IOM +enum +{ + IO_IN_TYPE, + IO_IN_MODE, + IO_IN_ADRAW, + IO_IN_NORMRAW, + IO_IN_SCALEDVAL, + IO_IN_INVALID_DATA +}; + +//FPP = Fields Per Port +#define IO_IN_FPP 6 +#define IO_IN_FIELD_COUNT (IO_IN_FPP * NO_OF_INPUTS) + +//Field IDs for input IOM +enum +{ + IO_OUT_FLAGS, + IO_OUT_MODE, + IO_OUT_SPEED, //AKA "Power" + IO_OUT_ACTUAL_SPEED, + IO_OUT_TACH_COUNT, + IO_OUT_TACH_LIMIT, + IO_OUT_RUN_STATE, + IO_OUT_TURN_RATIO, + IO_OUT_REG_MODE, + IO_OUT_OVERLOAD, + IO_OUT_REG_P_VAL, + IO_OUT_REG_I_VAL, + IO_OUT_REG_D_VAL, + IO_OUT_BLOCK_TACH_COUNT, + IO_OUT_ROTATION_COUNT +}; + +#define IO_OUT_FPP 15 +#define IO_OUT_FIELD_COUNT (IO_OUT_FPP * NO_OF_OUTPUTS) + +// +//DS_TOC_ENTRY is a record in the dataspace table of contents +//The TypeCode describes the data which is stored at Dataspace[DSOffset] +// +typedef struct +{ + TYPE_CODE TypeCode; + UBYTE Flags; + SWORD DSOffset; +} DS_TOC_ENTRY; + +//DS_TOC_ENTRY Flags +//!!! Yes, there's only one flag defined for an 8-bit field. +//ARM7 alignment rules means those bits would otherwise just be padding, anyway. +#define DS_DEFAULT_DEFAULT 1 //This entry has no default value in file; fill with zero at activation time + +//DS_ELEMENT_ID (AKA "DS item ID") indexes DataspaceTOC +typedef UWORD DS_ELEMENT_ID; + +//Special flag value used for opcode-specific default behavior when real dataspace argument is not provided +#define NOT_A_DS_ID 0xFFFF + +//Macro to bump DS_ELEMENT_IDs +1 with a cast (mostly to quash annoying warnings) +#define INC_ID(X) ((DS_ELEMENT_ID)(X + 1)) + +//DATA_ARG may contain a DS_ELEMENT_ID or encoded IO map address +typedef UWORD DATA_ARG; + +//CODE_WORD is a single indexable element of the codespace +typedef SWORD CODE_WORD; + +//CODE_INDEX indexes codespaces for opcodes and args +//!!! UWORD CODE_INDEX currently limits programs to 128KB code +// Yes, this is "plenty", but noted here to make sure we think about it +// when considering code size changes +typedef UWORD CODE_INDEX; + +//Typedef and define to hold and check for valid file handles +typedef UBYTE FILE_HANDLE; + +#define NOT_A_HANDLE 0xFF + +// +// Dynamic Memory Manager +// + +typedef UWORD DV_INDEX; //Dope Vector Index: Index into the DopeVectorArray + +//DOPE_VECTOR struct: One instance exists in the DopeVectorArray for every array in the dataspace. +//!!! BackPtr is an unused field. Intended to enable compaction of DopeVectorArray. +typedef struct +{ + UWORD Offset; + UWORD ElemSize; + UWORD Count; + UWORD BackPtr; + DV_INDEX Link; +} DOPE_VECTOR; + +// +//MEM_MGR struct +//Head and Tail keep track of the main linked-list of dope vectors, +// which must be maintained in ascending order according to Offset +//FreeHead is the head DV of the list of allocated but unused DVs +//pDopeVectorArray is initialized at activation-time to point to the master DVA +// +typedef struct +{ + DV_INDEX Head; + DV_INDEX Tail; + DV_INDEX FreeHead; + DOPE_VECTOR * pDopeVectorArray; +} MEM_MGR; + +//Macro to shorten common DVA access code +#define DV_ARRAY VarsCmd.MemMgr.pDopeVectorArray +//# of nodes to alloc when the Dope Vector Array is full +#define DV_ARRAY_GROWTH_COUNT 5 +//Flag value for invalid Offset fields in DVs +#define NOT_AN_OFFSET 0xFFFF +//Check for legal index into DVA +#define IS_DV_INDEX_SANE(X) (((X) > 0) && ((X) < DV_ARRAY[0].Count)) + +// +// Message Queuing +// + +// +//There are 10 incoming and 10 outgoing message queues, each 5 messages deep +//A "message" is defined as a null-terminated string under MAX_MESSAGE_SIZE +// +#define MESSAGES_PER_QUEUE 5 +#define MESSAGE_QUEUE_COUNT 20 +#define INCOMING_QUEUE_COUNT ((MESSAGE_QUEUE_COUNT)/2) +#define NOT_A_QUEUE 0xFF + +// +//MAX_MESSAGE_SIZE including null-terminator +//!!! Capped at 59 unless USB protocol assumptions are changed! +// +#define MAX_MESSAGE_SIZE 59 + +//A MESSAGE is a dynamically sized string, so we use a DV_INDEX to get to its information +typedef DV_INDEX MESSAGE; + +// +//MESSAGE_QUEUE keeps track of last messages read and written (acts as a circular buffer) +// +typedef struct +{ + UWORD ReadIndex; + UWORD WriteIndex; + MESSAGE Messages[MESSAGES_PER_QUEUE]; +} MESSAGE_QUEUE; + +//Handy macros for accessing MESSAGE_QUEUEs +#define GET_WRITE_MSG(QueueID) (VarsCmd.MessageQueues[(QueueID)].Messages[VarsCmd.MessageQueues[(QueueID)].WriteIndex]) +#define GET_READ_MSG(QueueID) (VarsCmd.MessageQueues[(QueueID)].Messages[VarsCmd.MessageQueues[(QueueID)].ReadIndex]) +#define SET_WRITE_MSG(QueueID, DVIndex) (VarsCmd.MessageQueues[(QueueID)].Messages[VarsCmd.MessageQueues[(QueueID)].WriteIndex] = (DVIndex)) +#define SET_READ_MSG(QueueID, DVIndex) (VarsCmd.MessageQueues[(QueueID)].Messages[VarsCmd.MessageQueues[(QueueID)].ReadIndex] = (DVIndex)) + + +// +//Definitions related to dataflow scheduling +// + +//CLUMP_IDs are used to index list at pAllClumps +typedef UBYTE CLUMP_ID; + +// +//The last value in CLUMP_ID's range is reserved as NOT_A_CLUMP +//This is useful as a queue terminator and general placeholder +// +#define NOT_A_CLUMP 0xFF +#define MAX_CLUMPS 255 + +//CLUMP_Q struct for tracking head and tail of a queue of clumps +typedef struct +{ + CLUMP_ID Head; + CLUMP_ID Tail; +} CLUMP_Q; + +// +//MUTEX_Q is a struct to be stashed in the dataspace to track state of a mutex +//If mutex is free, Owner field is NOT_A_CLUMP and WaitQ is empty. +//The mutex is acquired by stashing a new owner's ID. +//If others attempt to acquire, they will be put on the WaitQ +// +typedef struct +{ + CLUMP_ID Owner; + CLUMP_Q WaitQ; +} MUTEX_Q; + +// +// Clump Record, run-time book-keeping for each clump +// +// CodeStart: Start of this clump's bytecodes +// CodeEnd: End of this clump's bytecodes +// PC: "program counter" -- current offset into codespace relative to CodeStart +// InitFireCount: Initial count of upstream dependencies +// CurrFireCount: Run-time count of unsatisfied dependencies +// Link: ID of next clump in the queue. NOT_A_CLUMP denotes end or bad link. +// +// Priority: number of instructions to run per pass on this clump +// +// pDependents: pointer to list of downstream dependents' ClumpIDs +// DependentCount: Count of downstream dependents +// +typedef struct +{ + CODE_INDEX CodeStart; + CODE_INDEX CodeEnd; + CODE_INDEX PC; + UBYTE InitFireCount; + UBYTE CurrFireCount; //AKA ShortCount + CLUMP_ID Link; + + UBYTE Priority; + + CLUMP_ID* pDependents; + UBYTE DependentCount; +} CLUMP_REC; + +// +//Definitions for memory pool management +// + +//First valid pointer into the memory pool +#define POOL_START ((UBYTE*)(VarsCmd.Pool)) + +//Sentinel points one byte *past* the pool -- i.e. first bad pool pointer +#define POOL_SENTINEL ((UBYTE*)(VarsCmd.Pool + VarsCmd.PoolSize)) + +//Alignment mod for Pool and all sub-fields of the Pool +#define POOL_ALIGN SIZE_SLONG + +#define ALIGN_TO_MOD(val,mod) if ((val) % (mod) != 0) { (val) += (mod) - ((val) % (mod)); } else {} + +// +//Internal states of the VM +//VM_IDLE: Just sitting around. Request to run program will lead to ONE of the VM_RUN* states. +//VM_RUN_FREE: Attempt to run as many instructions as possible within our timeslice +//VM_RUN_SINGLE: Run exactly one instruction per timeslice +//VM_RUN_PAUSE: Program still "active", but someone has asked us to pause +//VM_RESET2: Final clean up and return to IDLE +//VM_RESET1: Initialize state variables and some I/O devices -- executed when programs end +// +typedef enum +{ + VM_IDLE, + VM_RUN_FREE, + VM_RUN_SINGLE, + VM_RUN_PAUSE, + VM_RESET1, + VM_RESET2, +} VM_STATE; + +// +// VARSCMD: Private state data for active program and VM system +// +//pCodespace: pointer for flat codespace (stored in flash, includes all clumps) +//CodespaceCount: count of code words +// +//pAllClumps: Pointer to list of CLUMP_RECs +//AllClumpsCount: Count of CLUMP_RECs in list +// +//RunQ: Head and tail of run queue (elements in-place in AllClumps list) +//ScratchPC: Temp PC value for control flow instructions +// +//pDataspaceTOC: Pointer to DSTOC entries (stored in flash) +//DataspaceCount: Count of entries in DSTOC +//pDataspace: Base pointer of actual dataspace +//DataspaceSize: Size, in bytes, of dataspace +//DSStaticSize: Size, in bytes, of static portion of the dataspace (used as an offset to the dynamic dataspace) +// +//VMState: Internal state of VM's loader/scheduler (cCmdCtrl()) +// +//MemMgr: Contains data to manage dynamic arrays +// +//PoolSize: Current size of main memory pool, in bytes. +//Pool: Static pool of bytes for stashing all program run-time data +// +//ActiveProgHandle: Handle of the program that is currently running +//ActiveProgName: Stashed name of currently running program, if any +// +//FileHandleTable: Table of file names opened by program while running. +// First byte of each record is 'r' or 'w' (read or write). +// +//MessageQueues: Message buffer tracking data +// +//CommStat, CommStatReset, CommCurrConnection, DirtyComm: Helper data for interfacing to c_comm module +// +//DirtyDisplay: Boolean reminding us to re-initialize the display if program used it +// +//StartTick: MS tick stashed when program started. Used for relative time measurements. +// +//Further notes on the memory pool: +// The main memory pool is used for all clump records, dataspace tracking data, +// and the dataspace itself. In other words, pAllClumps and +// pDataspace must all point to memory within the pool. Watch for NXT_ASSERTs +// to enforce safe indexing into the pool. +// +typedef struct +{ + CODE_WORD* pCodespace; + CLUMP_REC* pAllClumps; + DS_TOC_ENTRY* pDataspaceTOC; + UBYTE* pDataspace; + UBYTE* Pool; + + ULONG PoolSize; + UWORD CodespaceCount; + CLUMP_ID AllClumpsCount; + UWORD DataspaceCount; + UWORD DataspaceSize; + UWORD DSStaticSize; + + VM_STATE VMState; + + MEM_MGR MemMgr; + + CLUMP_Q RunQ; + CODE_INDEX ScratchPC; + CLUMP_ID CallerClump; + + UBYTE ActiveProgHandle; + UBYTE ActiveProgName[FILENAME_LENGTH + 1]; + + UBYTE FileHandleTable[MAX_HANDLES][FILENAME_LENGTH + 2]; + + MESSAGE_QUEUE MessageQueues[MESSAGE_QUEUE_COUNT]; + + SWORD CommStat; + SWORD CommStatReset; + UBYTE CommCurrConnection; + + UBYTE DirtyComm; + UBYTE DirtyDisplay; + + ULONG StartTick; + +#if VM_BENCHMARK + ULONG InstrCount; + ULONG Average; + ULONG OverTimeCount; + ULONG MaxOverTimeLength; + ULONG CmdCtrlCount; + ULONG CompactionCount; + ULONG LastCompactionTick; + ULONG MaxCompactionTime; + ULONG OpcodeBenchmarks[OPCODE_COUNT][4]; + ULONG SyscallBenchmarks[SYSCALL_COUNT][4]; + UBYTE Buffer[256]; +#endif + +#if defined ARM_DEBUG + UBYTE AssertFlag; + ULONG AssertLine; +#endif +} VARSCMD; + +// +//Activation +// + +//Activate new program by filename (open file and inflate run-time data) +NXT_STATUS cCmdActivateProgram(UBYTE * pFileName); + +//Deactivate currently active program (re-init run-time data and close file) +void cCmdDeactivateProgram(); + +//Reset various device state variables +void cCmdResetDevices(void); + +//Parse activation record file header information +typedef struct +{ + UWORD DSTOC; + UWORD DSDefaults; + UWORD DSDefaultsSize; + UWORD DynamicDefaults; + UWORD DynamicDefaultsSize; + UWORD Clumps; + UWORD Codespace; +} PROG_FILE_OFFSETS; + +NXT_STATUS cCmdReadFileHeader(UBYTE* pData, ULONG DataSize, + PROG_FILE_OFFSETS* pFileOffsets); + +NXT_STATUS cCmdInflateDSDefaults(UBYTE* pDSDefaults, UWORD *pDefaultsOffset, DS_ELEMENT_ID DSElementID); + + +// +//Clump management +// + +//Clump queuing +void cCmdEnQClump(CLUMP_Q * Queue, CLUMP_ID NewClump); +void cCmdDeQClump(CLUMP_Q * Queue, CLUMP_ID Clump); +void cCmdRotateQ(CLUMP_Q * Queue); +UBYTE cCmdIsClumpOnQ(CLUMP_Q * Queue, CLUMP_ID Clump); +UBYTE cCmdIsQSane(CLUMP_Q * Queue); + +//Mutex queuing +NXT_STATUS cCmdAcquireMutex(MUTEX_Q * Mutex, CLUMP_ID Clump); +NXT_STATUS cCmdReleaseMutex(MUTEX_Q * Mutex, CLUMP_ID Clump); + +//Conditionally schedule dependents of given clump (Begin and End specify subset of list) +NXT_STATUS cCmdSchedDependents(CLUMP_ID Clump, SWORD Begin, SWORD End); + +//Conditionally schedule TargetClump +NXT_STATUS cCmdSchedDependent(CLUMP_ID Clump, CLUMP_ID TargetClump); + +//Test if ClumpID is sane at run-time (valid for indexing AllClumps) +UBYTE cCmdIsClumpIDSane(CLUMP_ID Clump); + +// +//Code stream management +// + +//Instruction masking macros -- get the interesting bits out of an encoded instruction word +#define COMP_CODE(pInstr) ((UBYTE)((((pInstr)[0]) & 0x0700) >> 8)) +#define INSTR_SIZE(pInstr) ((UBYTE)((((pInstr)[0]) & 0xF000) >> 12)) + +#ifdef USE_SHORT_OPS +//!!! IS_SHORT_OP and SHORT_OP_CODE do not check for insane (out of bounds) data. Accessor function would be safer. +#define IS_SHORT_OP(pInstr) ((UBYTE)((((pInstr)[0]) & 0x0800) >> 8) == 8) +#define SHORT_OP_CODE(pInstr) COMP_CODE(pInstr) +#define SHORT_ARG(pInstr) ((SBYTE) (((pInstr)[0]) & 0x00FF)) +//ShortOpMap defined in c_cmd_bytecodes.h +#define OP_CODE(pInstr) (IS_SHORT_OP(pInstr) ? ShortOpMap[SHORT_OP_CODE(pInstr)] : (UBYTE) (((pInstr)[0]) & 0x00FF)) +#else +#define OP_CODE(pInstr) ((UBYTE) (((pInstr)[0]) & 0x00FF)) +#endif + +//Access count of codewords belonging to Clump. If no clump specified, return count of all codewords in program. +CODE_INDEX cCmdGetCodespaceCount(CLUMP_ID Clump); + +// +//Memory pool management +// + +//Initialize entire memory pool with default value +void cCmdInitPool(void); + +//Resize dataspace array specified by DSElementID and Offset. +NXT_STATUS cCmdDSArrayAlloc(DS_ELEMENT_ID DSElementID, UWORD Offset, UWORD NewCount); +//Resize dataspace array specified by DVIndex. In most cases, call higher-level cCmdDSArrayAlloc instead. +NXT_STATUS cCmdDVArrayAlloc(DV_INDEX DVIndex, UWORD NewCount); + +NXT_STATUS cCmdAllocSubArrayDopeVectors(DS_ELEMENT_ID DSElementID, UWORD Offset); +NXT_STATUS cCmdFreeSubArrayDopeVectors(DS_ELEMENT_ID DSElementID, UWORD Offset); +NXT_STATUS cCmdAllocDopeVector(DV_INDEX *pIndex, UWORD ElemSize, UWORD BackPtr); +NXT_STATUS cCmdFreeDopeVector(DV_INDEX DVIndex); +NXT_STATUS cCmdGrowDopeVectorArray(UWORD NewCount); +NXT_STATUS cCmdCompactDopeVectorArray(void); + +UWORD cCmdCalcArrayElemSize(DS_ELEMENT_ID DSElementID); + +NXT_STATUS cCmdMemMgrMoveToTail(DV_INDEX DVIndex); +NXT_STATUS cCmdMemMgrInsertAtTail(DV_INDEX DVIndex); + +//Utility function to check sanity of MemMgr data structure. Boolean result. +UBYTE cCmdVerifyMemMgr(); + +NXT_STATUS cCmdDSCompact(void); + +// +// Message Queue management +// + +NXT_STATUS cCmdMessageWrite(UWORD QueueID, UBYTE * pData, UWORD Length); +NXT_STATUS cCmdMessageRead(UWORD QueueID, UBYTE * pData, UWORD Length, UBYTE Remove); +NXT_STATUS cCmdMessageGetSize(UWORD QueueID, UWORD * Size); + +// +//Dataspace management +// + +#define IS_AGGREGATE_TYPE(TypeCode) ((TypeCode == TC_ARRAY) || (TypeCode == TC_CLUSTER)) +#define IS_SIGNED_TYPE(TypeCode) (((TypeCode) == TC_SBYTE) || ((TypeCode) == TC_SWORD) || ((TypeCode) == TC_SLONG)) + +//Test if DS_ELEMENT_ID is sane at run-time (valid for indexing DS TOC) +UBYTE cCmdIsDSElementIDSane(DS_ELEMENT_ID Index); + +DS_ELEMENT_ID cCmdGetDataspaceCount(void); +TYPE_CODE cCmdDSType(DS_ELEMENT_ID DSElementID); + +//Pointer accessors to resolve actual data locations in RAM +void* cCmdDSPtr(DS_ELEMENT_ID DSElementID, UWORD Offset); +void* cCmdDVPtr(DV_INDEX DVIndex); + +//Helper to walk the DSTOC to the next entry at the same aggregate nesting level as CurrID +DS_ELEMENT_ID cCmdNextDSElement(DS_ELEMENT_ID CurrID); + +//Recursively compare two complete data type descriptors +UBYTE cCmdCompareDSType(DS_ELEMENT_ID DSElementID1, DS_ELEMENT_ID DSElementID2); + +//Functions for managing data flattened to byte arrays +UWORD cCmdCalcFlattenedSize(DS_ELEMENT_ID DSElementID, UWORD Offset); +NXT_STATUS cCmdFlattenToByteArray(UBYTE * pByteArray, UWORD * pByteOffset, DS_ELEMENT_ID DSElementID, UWORD Offset); +NXT_STATUS cCmdUnflattenFromByteArray(UBYTE * pByteArray, UWORD * pByteOffset, DS_ELEMENT_ID DSElementID, UWORD Offset); + +//Comparison evaluation. Comparison codes defined in c_cmd_bytecodes.h. +//cCmdCompare operates on scalars passed as ULONGs -- type-specific comparisons done inside function. +UBYTE cCmdCompare(UBYTE CompCode, ULONG Val1, ULONG Val2, TYPE_CODE TypeCode1, TYPE_CODE TypeCode2); +//cCmdCompareAggregates does polymorphic comparisons (with recursive helper function). +NXT_STATUS cCmdCompareAggregates(UBYTE CompCode, UBYTE *ReturnBool, DATA_ARG Arg2, UWORD Offset2, DATA_ARG Arg3, UWORD Offset3); +NXT_STATUS cCmdRecursiveCompareAggregates(UBYTE CompCode, UBYTE *ReturnBool, UBYTE *Finished, DATA_ARG Arg2, UWORD Offset2, DATA_ARG Arg3, UWORD Offset3); + +//Cluster functions +UWORD cCmdClusterCount(DS_ELEMENT_ID DSElementID); + +//Array functions +#define ARRAY_ELEM_OFFSET(DVIndex, Index) ((UWORD)(DV_ARRAY[(DVIndex)].Offset + DV_ARRAY[(DVIndex)].ElemSize * (Index))) +UWORD cCmdGetDVIndex(DS_ELEMENT_ID DSElementID, UWORD Offset); +UWORD cCmdArrayCount(DS_ELEMENT_ID DSElementID, UWORD Offset); +TYPE_CODE cCmdArrayType(DS_ELEMENT_ID DSElementID); + +//!!! DATA_ARG masks are for internal use only! (Bytecode programs should never contain them) +// See cCmdResolveDataArg() calls in the interpreter code for OP_GETOUT, OP_SETIN, and OP_GETIN. +#define DATA_ARG_ADDR_MASK 0x3FFF +#define DATA_ARG_IMM_MASK 0x7FFF + +//General data accessors (DS and IO Map) +void * cCmdResolveDataArg(DATA_ARG DataArg, UWORD Offset, TYPE_CODE * TypeCode); +ULONG cCmdGetVal(void * pVal, TYPE_CODE TypeCode); +void cCmdSetVal(void * pVal, TYPE_CODE TypeCode, ULONG NewVal); +UWORD cCmdSizeOf(TYPE_CODE TypeCode); + +// +//Interpreter functions +// + +//Clump-based "master" interpreter +NXT_STATUS cCmdInterpFromClump(CLUMP_ID Clump); + +//Function pointer typedef for sub-interpreters +typedef NXT_STATUS (*pInterp)(CODE_WORD * const); + +//Sub-interpreter dispatch functions +NXT_STATUS cCmdInterpNoArg(CODE_WORD * const pCode); +NXT_STATUS cCmdInterpUnop1(CODE_WORD * const pCode); +NXT_STATUS cCmdInterpUnop2(CODE_WORD * const pCode); +NXT_STATUS cCmdInterpBinop(CODE_WORD * const pCode); +NXT_STATUS cCmdInterpOther(CODE_WORD * const pCode); + +#define INTERP_COUNT 5 + +//Polymorphic interpreter functions +NXT_STATUS cCmdInterpPolyUnop2(CODE_WORD const Code, DATA_ARG Arg1, UWORD Offset1, DATA_ARG Arg2, UWORD Offset2); +ULONG cCmdUnop2(CODE_WORD const Code, ULONG Operand, TYPE_CODE TypeCode); + +NXT_STATUS cCmdInterpPolyBinop(CODE_WORD const Code, DATA_ARG Arg1, UWORD Offset1, DATA_ARG Arg2, UWORD Offset2, DATA_ARG Arg3, UWORD Offset3); +ULONG cCmdBinop(CODE_WORD const Code, ULONG LeftOp, ULONG RightOp, TYPE_CODE LeftType, TYPE_CODE RightType); + +// +//Support functions for lowspeed (I2C devices, i.e. ultrasonic sensor) communications +// + +NXT_STATUS cCmdLSCheckStatus(UBYTE Port); +UBYTE cCmdLSCalcBytesReady(UBYTE Port); +NXT_STATUS cCmdLSWrite(UBYTE Port, UBYTE BufLength, UBYTE *pBuf, UBYTE ResponseLength); +NXT_STATUS cCmdLSRead(UBYTE Port, UBYTE BufLength, UBYTE * pBuf); + +// +//Support for OP_SYSCALL +// + +// +//Each cCmdWrap funtion below implements one system call. +//The OP_SYSCALL interpreter wrangles the argument vector, ArgV, +// then calls the appropriate wrapper function according to the SysCallID. +//Wrapper functions write directly back into the dataspace via ArgV. +// +#define MAX_CALL_ARGS 16 + +typedef NXT_STATUS (*pSysCall)(UBYTE * ArgV[]); + +NXT_STATUS cCmdWrapFileOpenRead(UBYTE * ArgV[]); +NXT_STATUS cCmdWrapFileOpenWrite(UBYTE * ArgV[]); +NXT_STATUS cCmdWrapFileOpenAppend(UBYTE * ArgV[]); +NXT_STATUS cCmdWrapFileRead(UBYTE * ArgV[]); +NXT_STATUS cCmdWrapFileWrite(UBYTE * ArgV[]); +NXT_STATUS cCmdWrapFileClose(UBYTE * ArgV[]); +NXT_STATUS cCmdWrapFileResolveHandle (UBYTE * ArgV[]); +NXT_STATUS cCmdWrapFileRename (UBYTE * ArgV[]); +NXT_STATUS cCmdWrapFileDelete (UBYTE * ArgV[]); +NXT_STATUS cCmdWrapSoundPlayFile(UBYTE * ArgV[]); +NXT_STATUS cCmdWrapSoundPlayTone(UBYTE * ArgV[]); +NXT_STATUS cCmdWrapSoundGetState(UBYTE * ArgV[]); +NXT_STATUS cCmdWrapSoundSetState(UBYTE * ArgV[]); +NXT_STATUS cCmdWrapDrawText(UBYTE * ArgV[]); +NXT_STATUS cCmdWrapDrawPoint(UBYTE * ArgV[]); +NXT_STATUS cCmdWrapDrawLine(UBYTE * ArgV[]); +NXT_STATUS cCmdWrapDrawCircle(UBYTE * ArgV[]); +NXT_STATUS cCmdWrapDrawRect(UBYTE * ArgV[]); +NXT_STATUS cCmdWrapDrawPicture(UBYTE * ArgV[]); +NXT_STATUS cCmdWrapSetScreenMode(UBYTE * ArgV[]); +NXT_STATUS cCmdWrapReadButton(UBYTE * ArgV[]); +NXT_STATUS cCmdWrapCommLSWrite(UBYTE * ArgV[]); +NXT_STATUS cCmdWrapCommLSRead(UBYTE * ArgV[]); +NXT_STATUS cCmdWrapCommLSCheckStatus(UBYTE * ArgV[]); +NXT_STATUS cCmdWrapRandomNumber(UBYTE * ArgV[]); +NXT_STATUS cCmdWrapGetStartTick(UBYTE * ArgV[]); +NXT_STATUS cCmdWrapMessageWrite(UBYTE * ArgV[]); +NXT_STATUS cCmdWrapMessageRead(UBYTE * ArgV[]); +NXT_STATUS cCmdWrapCommBTCheckStatus(UBYTE * ArgV[]); +NXT_STATUS cCmdWrapCommBTWrite(UBYTE * ArgV[]); +NXT_STATUS cCmdWrapCommBTRead(UBYTE * ArgV[]); +NXT_STATUS cCmdWrapKeepAlive(UBYTE * ArgV[]); +NXT_STATUS cCmdWrapIOMapRead(UBYTE * ArgV[]); +NXT_STATUS cCmdWrapIOMapWrite(UBYTE * ArgV[]); + +//Handler for remote control protocol packets -- called from comm module via IO map function pointer +UWORD cCmdHandleRemoteCommands(UBYTE * pInBuf, UBYTE * pOutBuf, UBYTE * pLen); + +#ifdef SIM_NXT +// +// Helper functions to provide simulator library access to VM internals +// +SWORD cCmdGetCodeWord(CLUMP_ID Clump, CODE_INDEX Index); +UBYTE * cCmdGetDataspace(UWORD *DataspaceSize); +DOPE_VECTOR * cCmdGetDopeVectorPtr(void); +ULONG cCmdGetPoolSize(void); +MEM_MGR cCmdGetMemMgr(void); +#endif + +#else //!ENABLE_VM + +//Placeholder VARSCMD for alternate implementation (see bottom of c_cmd.c for usage notes) +typedef struct +{ + UBYTE Tmp; +} VARSCMD; + +#endif //ENABLE_VM + +#endif //C_CMD diff --git a/AT91SAM7S256/Source/c_cmd.iom b/AT91SAM7S256/Source/c_cmd.iom new file mode 100644 index 0000000..2b36743 --- /dev/null +++ b/AT91SAM7S256/Source/c_cmd.iom @@ -0,0 +1,178 @@ +// +// Date init 14.12.2004 +// +// Revision date $Date: 14-06-06 8:09 $ +// +// Filename $Workfile:: c_cmd.iom $ +// +// Version $Revision: 21 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/c_cmd.iom $ +// +// Platform C +// + +#ifndef CCMD_IOM +#define CCMD_IOM + +#include "modules.h" + +#define pMapCmd ((IOMAPCMD*)(pHeaders[ENTRY_CMD]->pIOMap)) + +// +// Status/error codes for the VM internal code and bytecodes, loosely categorized +// Positive values are used for non-error status codes; commonly used by bytecode handlers +// to affect future execution. +// Negative values are run-time errors, and the first group is considered "fatal" in that +// program execution cannot continue when these errors are encountered. +// + +#define STAT_MSG_EMPTY_MAILBOX 64 //0x40 Specified mailbox contains no new messages + +#define STAT_COMM_PENDING 32 //0x20 Pending setup operation in progress + +#define STOP_REQ 5 //0x05 Abort current program +#define BREAKOUT_REQ 4 //0x04 Break multi-instruction interpreter loop; give I/O a chance to run +#define PC_OVERRIDE 3 //0x03 Move program counter according to ScratchPC value +#define CLUMP_SUSPEND 2 //0x02 Place clump in stasis; execute others until this one returns to RunQ +#define CLUMP_DONE 1 //0x01 Finish and reset this clump; execute others until this one is rescheduled + +#define NO_ERR 0 + +//Fatal errors +#define ERR_ARG -1 //0xFF Bad arguments +#define ERR_INSTR -2 //0xFE Illegal bytecode instruction +#define ERR_FILE -3 //0xFD Mal-formed file contents +#define ERR_VER -4 //0xFC Version mismatch between firmware and compiler +#define ERR_MEM -5 //0xFB Insufficient memory available +#define ERR_BAD_PTR -6 //0xFA Someone passed us a bad pointer! + +//General errors +#define ERR_INVALID_PORT -16 //0xF0 Bad input or output port specified +#define ERR_INVALID_FIELD -17 //0xEF Attempted to access invalid field of a structure +#define ERR_INVALID_QUEUE -18 //0xEE Illegal queue ID specified +#define ERR_INVALID_SIZE -19 //0xED Illegal size specified +#define ERR_NO_PROG -20 //0xEC No active program + +//Communications specific errors +#define ERR_COMM_CHAN_NOT_READY -32 //0xE0 Specified channel/connection not configured or busy +#define ERR_COMM_CHAN_INVALID -33 //0xDF Specified channel/connection is not valid +#define ERR_COMM_BUFFER_FULL -34 //0xDE No room in comm buffer +#define ERR_COMM_BUS_ERR -35 //0xDD Something went wrong on the communications bus + +//Remote control ("direct commands") errors +#define ERR_RC_ILLEGAL_VAL -64 //0xC0 Data contains out-of-range values +#define ERR_RC_BAD_PACKET -65 //0xBF Clearly insane packet +#define ERR_RC_UNKNOWN_CMD -66 //0xBE Unknown command opcode +#define ERR_RC_FAILED -67 //0xBD Request failed (i.e. specified file not found) + +//NB: Error codes -96 through -128 (0xA0 through 0x80) reserved for loader (file system) errors +//This whole range isn't actually used by current loader code, but it's a reasonable range to reserve + +#define IS_ERR(Status) ((Status) < NO_ERR) + +//Errors are considered fatal if they are something we'd consider halting the VM for. +#define IS_FATAL(Status) ((Status) < NO_ERR && (Status) >= ERR_BAD_PTR) + +//Direct command protocol opcodes +//!!! These MUST be mutually exclusive with c_comm's protocol opcodes. +// Since all of c_comm's protocol opcodes are above 0x80, we're safe for now. +enum +{ + RC_START_PROGRAM, + RC_STOP_PROGRAM, + RC_PLAY_SOUND_FILE, + RC_PLAY_TONE, + RC_SET_OUT_STATE, + RC_SET_IN_MODE, + RC_GET_OUT_STATE, + RC_GET_IN_VALS, + RC_RESET_IN_VAL, + RC_MESSAGE_WRITE, + RC_RESET_POSITION, + RC_GET_BATT_LVL, + RC_STOP_SOUND, + RC_KEEP_ALIVE, + RC_LS_GET_STATUS, + RC_LS_WRITE, + RC_LS_READ, + RC_GET_CURR_PROGRAM, + RC_GET_BUTTON_STATE, + RC_MESSAGE_READ, + NUM_RC_OPCODES +}; + + +// +//Published status of last program to be activated +//This value is published so outside parties (like the UI) can check if a program is running, +//and if not, how the last program ended. Initial value is "PROG_OK". +//PROG_OK: Last program finished normally. +//PROG_RUNNING: Program currently running +//PROG_ERROR: Last program ended because of an error +//PROG_ABORT: Last program ended because of (user) abort +// +typedef enum +{ + PROG_IDLE, + PROG_OK, + PROG_RUNNING, + PROG_ERROR, + PROG_ABORT, + PROG_RESET +} PROGRAM_STATUS; + +//Maximum size of memory pool, in bytes +//!!! Code assumes this value is evenly divisible by 4! +#define POOL_MAX_SIZE 32768 + +//Versioning information +//Format string must exist verbatim in the header of a valid program file. +//Also included in IOMAPCMD for remote identification of the VM +#define VM_FORMAT_STRING "MindstormsNXT" +//Size of format string above, plus version number packed in the last two bytes. +#define VM_FORMAT_STRING_SIZE 16 +//Current firmware version defined in c_loader.iom as FIRMWAREVERSION +//This is the oldest compatible version in the same system +#define VM_OLDEST_COMPATIBLE_VERSION 0x0004 + +// +//IO Map for Command Module +// pRCHandler: Function pointer to handler for remote control protocol +// Tick: Latest value from 1 ms system timer + +//!!! Two offset values below are useful for external debugging. They are only valid after a program has started! +// OffsetDS: Offset to the dataspace (inside MemoryPool); relative to first byte of IOMapCmd +// OffsetDVA: Offset to the DopeVectorArray (inside MemoryPool); relative to first byte of IOMapCmd + +// ProgStatus: Published status of last program to be activated +// Awake: Boolean is only true after initialization + +// ActivateFlag: Set this flag to notify cCmdCtrl to activate new file +// DeactivateFlag: Set this flag to notify cCmdCtrl to deactivate current program + +// FileName[]: Fill in this buffer when using ActivateFlag +// MemoryPool[]: Main memory pool for program data. +// (Declared as ULONG for portable alignment; used internally via a byte pointer.) +// +typedef struct +{ + UBYTE FormatString[VM_FORMAT_STRING_SIZE]; + UWORD (*pRCHandler)(UBYTE *, UBYTE *, UBYTE *); + ULONG Tick; + + UWORD OffsetDS; + UWORD OffsetDVA; + + PROGRAM_STATUS ProgStatus; + + UBYTE Awake; + + UBYTE ActivateFlag; + UBYTE DeactivateFlag; + UBYTE FileName[FILENAME_LENGTH + 1]; + + ULONG MemoryPool[POOL_MAX_SIZE / 4]; +} IOMAPCMD; + +#endif //CCMD_IOM diff --git a/AT91SAM7S256/Source/c_cmd_alternate.c b/AT91SAM7S256/Source/c_cmd_alternate.c new file mode 100644 index 0000000..9366296 --- /dev/null +++ b/AT91SAM7S256/Source/c_cmd_alternate.c @@ -0,0 +1,163 @@ +// +// File Description: +// This file contains an alternate implementation of c_cmd for testing purposes. +// It implements the minimal standard interface for the module, and serves as +// an example of output module control via C code. +// + +void cCmdInit(void* pHeader) +{ + pHeaders = pHeader; + + IOMapCmd.Awake = TRUE; + + dTimerInit(); + IOMapCmd.Tick = dTimerRead(); + + return; +} + +//Test: Start at speed 100 when enter is pressed; then progressively ramp down every half second until -100. +void cCmdCtrl(void) +{ + static UBYTE State = 0; + static ULONG MyTick = 0; + + if (pMapButton->State[BTN1] & PRESSED_EV) + { + pMapButton->State[BTN1] &= ~PRESSED_EV; + + //Coast both motors + pMapOutPut->Outputs[0].Mode = MOTORON; + pMapOutPut->Outputs[1].Mode = MOTORON; + + pMapOutPut->Outputs[0].Speed = 0; + pMapOutPut->Outputs[0].TachoLimit = 0; + pMapOutPut->Outputs[0].RunState = MOTOR_RUN_STATE_IDLE; + pMapOutPut->Outputs[0].RegMode = REGULATION_MODE_IDLE; + + pMapOutPut->Outputs[1].Speed = 0; + pMapOutPut->Outputs[1].TachoLimit = 0; + pMapOutPut->Outputs[1].RunState = MOTOR_RUN_STATE_IDLE; + pMapOutPut->Outputs[1].RegMode = REGULATION_MODE_IDLE; + + pMapOutPut->Outputs[0].Flags = UPDATE_MODE | UPDATE_SPEED; + pMapOutPut->Outputs[1].Flags = UPDATE_MODE | UPDATE_SPEED; + + //Drop out of ongoing state machine + State = 255; + } + + switch(State) + { + case 0: + { + //Initialize + pMapOutPut->Outputs[0].Flags = UPDATE_RESET_COUNT; + pMapOutPut->Outputs[1].Flags = UPDATE_RESET_COUNT; + pMapOutPut->Outputs[0].RunState = MOTOR_RUN_STATE_IDLE; + pMapOutPut->Outputs[1].RunState = MOTOR_RUN_STATE_IDLE; + + State++; + } + break; + + case 1: + { + //Kick off further states only if Enter button is pressed + if ((pMapButton->State[BTN4] & PRESSED_EV)) + { + //Clear pressed event so UI doesn't re-use it. + pMapButton->State[BTN4] &= ~PRESSED_EV; + + pMapOutPut->Outputs[0].Mode = MOTORON | BRAKE | REGULATED; + pMapOutPut->Outputs[1].Mode = MOTORON | BRAKE | REGULATED; + + pMapOutPut->Outputs[0].Speed = 50; + pMapOutPut->Outputs[0].TachoLimit = 1152; + pMapOutPut->Outputs[0].RunState = MOTOR_RUN_STATE_RUNNING; + pMapOutPut->Outputs[0].SyncTurnParameter = 25; + //pMapOutPut->Outputs[0].RegMode = REGULATION_MODE_MOTOR_SPEED; + pMapOutPut->Outputs[0].RegMode = REGULATION_MODE_MOTOR_SYNC; + + pMapOutPut->Outputs[1].Speed = 50; + pMapOutPut->Outputs[1].TachoLimit = 1152; + pMapOutPut->Outputs[1].RunState = MOTOR_RUN_STATE_RUNNING; + //pMapOutPut->Outputs[1].SyncTurnParameter = -7; + //pMapOutPut->Outputs[1].RegMode = REGULATION_MODE_MOTOR_SPEED; + pMapOutPut->Outputs[1].RegMode = REGULATION_MODE_MOTOR_SYNC; + + pMapOutPut->Outputs[0].Flags = UPDATE_MODE | UPDATE_SPEED | UPDATE_TACHO_LIMIT; + pMapOutPut->Outputs[1].Flags = UPDATE_MODE | UPDATE_SPEED | UPDATE_TACHO_LIMIT; + + State++; + } + } + break; + + case 2: + { + if (pMapOutPut->Outputs[0].RunState == MOTOR_RUN_STATE_IDLE) + { + pMapOutPut->Outputs[0].Mode = MOTORON; + pMapOutPut->Outputs[1].Mode = MOTORON; + + pMapOutPut->Outputs[0].Speed = 0; + pMapOutPut->Outputs[0].TachoLimit = 0; + pMapOutPut->Outputs[0].RunState = MOTOR_RUN_STATE_IDLE; + pMapOutPut->Outputs[0].RegMode = REGULATION_MODE_IDLE; + + pMapOutPut->Outputs[1].Speed = 0; + pMapOutPut->Outputs[1].TachoLimit = 0; + pMapOutPut->Outputs[1].RunState = MOTOR_RUN_STATE_IDLE; + pMapOutPut->Outputs[1].RegMode = REGULATION_MODE_IDLE; + + pMapOutPut->Outputs[0].Flags = UPDATE_MODE | UPDATE_SPEED; + pMapOutPut->Outputs[1].Flags = UPDATE_MODE | UPDATE_SPEED; + State++; + } + } + break; + + case 3: + { + pMapOutPut->Outputs[0].Mode = MOTORON | BRAKE | REGULATED; + pMapOutPut->Outputs[1].Mode = MOTORON | BRAKE | REGULATED; + + pMapOutPut->Outputs[0].Speed = 50; + pMapOutPut->Outputs[0].TachoLimit = 1152; + pMapOutPut->Outputs[0].RunState = MOTOR_RUN_STATE_RUNNING; + //pMapOutPut->Outputs[0].SyncTurnParameter = 5; + //pMapOutPut->Outputs[0].RegMode = REGULATION_MODE_MOTOR_SPEED; + pMapOutPut->Outputs[0].RegMode = REGULATION_MODE_MOTOR_SYNC; + + pMapOutPut->Outputs[1].Speed = 50; + pMapOutPut->Outputs[1].TachoLimit = 1152; + pMapOutPut->Outputs[1].RunState = MOTOR_RUN_STATE_RUNNING; + //pMapOutPut->Outputs[1].RegMode = REGULATION_MODE_MOTOR_SPEED; + pMapOutPut->Outputs[1].RegMode = REGULATION_MODE_MOTOR_SYNC; + + pMapOutPut->Outputs[0].Flags = UPDATE_MODE | UPDATE_SPEED | UPDATE_TACHO_LIMIT; + pMapOutPut->Outputs[1].Flags = UPDATE_MODE | UPDATE_SPEED | UPDATE_TACHO_LIMIT; + + State = 2; + } + break; + + default: + break; + }; + + //Busy loop to ensure return on 1ms boundary + BUSY_WAIT_NEXT_MS; + + IOMapCmd.Tick = dTimerRead(); + MyTick++; + + return; +} + +void cCmdExit(void) +{ + return; +} diff --git a/AT91SAM7S256/Source/c_cmd_bytecodes.h b/AT91SAM7S256/Source/c_cmd_bytecodes.h new file mode 100644 index 0000000..6051aba --- /dev/null +++ b/AT91SAM7S256/Source/c_cmd_bytecodes.h @@ -0,0 +1,115 @@ +#ifndef C_CMD_BYTECODES +#define C_CMD_BYTECODES +// +// opcode definitions +// symbol, bits, arg format +// +#define OPCODE_COUNT 0x36 + +//Family: Math +#define OP_ADD 0x00 // dest, src1, src2 +#define OP_SUB 0x01 // dest, src1, src2 +#define OP_NEG 0x02 // dest, src +#define OP_MUL 0x03 // dest, src1, src2 +#define OP_DIV 0x04 // dest, src1, src2 +#define OP_MOD 0x05 // dest, src1, src2 + +//Family: Logic +#define OP_AND 0x06 // dest, src1, src2 +#define OP_OR 0x07 // dest, src1, src2 +#define OP_XOR 0x08 // dest, src1, src2 +#define OP_NOT 0x09 // dest, src + +//Family: Bit manipulation +#define OP_CMNT 0x0A // dest, src +#define OP_LSL 0x0B // dest, src +#define OP_LSR 0x0C // dest, src +#define OP_ASL 0x0D // dest, src +#define OP_ASR 0x0E // dest, src +#define OP_ROTL 0x0F // dest, src +#define OP_ROTR 0x10 // dest, src + +//Family: Comparison +#define OP_CMP 0x11 // dest, src1, src2 +#define OP_TST 0x12 // dest, src +#define OP_CMPSET 0x13 // dest, src, testsrc, testsrc +#define OP_TSTSET 0x14 // dest, src, testsrc + +//Family: Array ops +#define OP_INDEX 0x15 // dest, src, index +#define OP_REPLACE 0x16 // dest, src, index, val +#define OP_ARRSIZE 0x17 // dest, src +#define OP_ARRBUILD 0x18 // instrsize, dest, src1, src2, … +#define OP_ARRSUBSET 0x19 // dest, src, index, length +#define OP_ARRINIT 0x1A // dest, elem, length + +//Family: Memory ops +#define OP_MOV 0x1B // dest, src +#define OP_SET 0x1C // dest, imm + +//Family: String ops +#define OP_FLATTEN 0x1D // dest, src +#define OP_UNFLATTEN 0x1E // dest, err, src, type +#define OP_NUMTOSTRING 0x1F // dest, src +#define OP_STRINGTONUM 0x20 // dest, offsetpast, src, offset, default +#define OP_STRCAT 0x21 // instrsize, dest, src1, src2, … +#define OP_STRSUBSET 0x22 // dest, src, index, length +#define OP_STRTOBYTEARR 0x23 // dest, src +#define OP_BYTEARRTOSTR 0x24 // dest, src + +//Family: Control flow +#define OP_JMP 0x25 // offset +#define OP_BRCMP 0x26 // offset, src1, src2 +#define OP_BRTST 0x27 // offset, src +#define OP_SYSCALL 0x28 // func, args +#define OP_STOP 0x29 // stop? + +//Family: Clump scheduling +#define OP_FINCLUMP 0x2A // start, end +#define OP_FINCLUMPIMMED 0x2B // clumpID +#define OP_ACQUIRE 0x2C // mutexID +#define OP_RELEASE 0x2D // mutexID +#define OP_SUBCALL 0x2E // subroutine, callerID +#define OP_SUBRET 0x2F // callerID + +//Family: IO ops +#define OP_SETIN 0x30 // src, port, propid +#define OP_SETOUT 0x31 // instrsize, port/portlist, propid1, src1, ... +#define OP_GETIN 0x32 // dest, port, propid +#define OP_GETOUT 0x33 // dest, port, propid + +//Family: Timing +#define OP_WAIT 0x34 // milliseconds +#define OP_GETTICK 0x35 // dest + +// condition code definitions +#define OPCC1_LT 0x00 +#define OPCC1_GT 0x01 +#define OPCC1_LTEQ 0x02 +#define OPCC1_GTEQ 0x03 +#define OPCC1_EQ 0x04 +#define OPCC1_NEQ 0x05 + + + +// +// short op definitions +// +#define USE_SHORT_OPS +#define SHORT_OP_MOV 0 +#define SHORT_OP_ACQUIRE 1 +#define SHORT_OP_RELEASE 2 +#define SHORT_OP_SUBCALL 3 + +// +// short op mapping table +// +static UBYTE ShortOpMap[4] = +{ + OP_MOV, + OP_ACQUIRE, + OP_RELEASE, + OP_SUBCALL +}; + +#endif // C_CMD_BYTECODES diff --git a/AT91SAM7S256/Source/c_cmd_drawing.inc b/AT91SAM7S256/Source/c_cmd_drawing.inc new file mode 100644 index 0000000..0132d44 --- /dev/null +++ b/AT91SAM7S256/Source/c_cmd_drawing.inc @@ -0,0 +1,894 @@ +// +// Date init 14.12.2004 +// +// Revision date $Date:: 8/26/05 4:17p $ +// +// Filename $Workfile:: c_cmd.c $ +// +// Version $Revision:: 35 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/c_cmd_drawing.c $ +// +// Platform C +// + +//absolute value of a +#define ABS(a) (((a)<0) ? -(a) : (a)) + +//take binary sign of a, either -1, or 1 if >= 0 +#define SGN(a) (((a)<0) ? -1 : 1) + +#define DISP_BUFFER_P ((UBYTE*)&(pMapDisplay->Normal)) + +//------------------------------------------------------------------ +// cCmdClearScreenIfNeeded - Clear entire sceen buffer if explicitly requested or implicitly required. +void cCmdClearScreenIfNeeded(ULONG DrawOptions); + +//------------------------------------------------------------------ +// cCmdRestorDefaultScreen - Restore screen to default 'Running' screen +void cCmdRestoreDefaultScreen(void); + +//------------------------------------------------------------------ +// cCmdDrawString - Draw string to display buffer +void cCmdDrawString(UBYTE *pString, ULONG X, ULONG Y); + +// OP codes supported by RIC files +enum { + IMG_DESCRIPTION_ID = 0, // Ignored at this time + IMG_SPRITE_ID = 1, + IMG_VARMAP_ID = 2, + IMG_COPYBITS_ID = 3, + IMG_PIXEL_ID = 4, + IMG_LINE_ID = 5, + IMG_RECTANGLE_ID = 6, + IMG_CIRCLE_ID = 7, + IMG_NUMBOX_ID = 8 +}; + +#define IMG_SYMB_USEARGS(_v) (_v & (SWORD)0xF000) +#define IMG_SYMB_MAP(_v) ((_v & 0x0F00) >> 8) +#define IMG_SYMB_ARG(_v) (_v & 0x000F) + +// DrawingOptions +#define DRAW_OPT_CLEAR_WHOLE_SCREEN (0x0001) +#define DRAW_OPT_CLEAR_EXCEPT_STATUS_SCREEN (0x0002) +#define DRAW_OPT_CLEAR_MODE(_v) ((_v) & 0x0003) + + +// Clear Before Drawing Modes for Draw functions +enum { + DO_NOT_CLEAR = 0, + CLEAR_B4_DRAW = 1 +}; + +// Screen Modes for SetScreenMode function +enum { + RESTORE_NXT_SCREEN = 0 +}; + +#define IMG_COMMON_FIELDS UWORD OpSize; UWORD OpCode; + +#define TRANSLATE_Y(_y) ((DISPLAY_HEIGHT-1) - (_y)) + +typedef struct +{ + SWORD X, Y; +} IMG_PT; + +typedef struct +{ + IMG_PT Pt; + SWORD Width, Height; +} IMG_RECT; + +typedef struct +{ + IMG_COMMON_FIELDS +} IMG_OP_CORE; + +typedef struct +{ + IMG_COMMON_FIELDS + UWORD Options; + UWORD Width; + UWORD Height; +} IMG_OP_DESCRIPTION; + +typedef struct +{ + IMG_COMMON_FIELDS + UWORD DataAddr; //Address sprite handle will be stored in. + UWORD Rows; //Second deminsion of the array below. + UWORD RowBytes; //The actual size of the following array. Must be even. + UBYTE Bytes[2]; //Minimum of two for alignment purposes +} IMG_OP_SPRITE; + +typedef struct +{ + IMG_COMMON_FIELDS + UWORD DataAddr; //Address sprite handle will be stored in. + UWORD MapCount; //The actual size of the following array. Must be even. + struct + { //Minimum of two for alignment purposes + UWORD Domain; + UWORD Range; + } MapElt[1]; +} IMG_OP_VARMAP; + +typedef struct +{ + IMG_COMMON_FIELDS + UWORD CopyOptions; // Copy, CopyNot, Or, BitClear; + UWORD DataAddr; // Address of an already defined sprite + IMG_RECT Src; // Source rectangle + IMG_PT Dst; // Destination left top +} IMG_OP_COPYBITS; + +typedef struct +{ + IMG_COMMON_FIELDS + UWORD CopyOptions; + IMG_PT Pt; + UWORD Value; // typically mapped to an argument +} IMG_OP_PIXEL; + +typedef struct +{ + IMG_COMMON_FIELDS + UWORD CopyOptions; + IMG_PT Pt1; + IMG_PT Pt2; +} IMG_OP_LINE; + +typedef struct +{ + IMG_COMMON_FIELDS + UWORD CopyOptions; + IMG_PT Pt; + SWORD Width, Height; +} IMG_OP_RECT; + +typedef struct +{ + IMG_COMMON_FIELDS + UWORD CopyOptions; + IMG_PT Pt; + UWORD Radius; +} IMG_OP_CIRCLE; + +typedef struct +{ + IMG_COMMON_FIELDS + UWORD CopyOptions; + IMG_PT Pt; + UWORD Value; // typically mapped to an argument +} IMG_OP_NUMBOX; + +typedef union +{ IMG_OP_CORE Core; + IMG_OP_DESCRIPTION Desc; + IMG_OP_SPRITE Sprite; + IMG_OP_VARMAP VarMap; + IMG_OP_COPYBITS CopyBits; + IMG_OP_PIXEL Pixel; + IMG_OP_LINE Line; + IMG_OP_RECT Rect; + IMG_OP_CIRCLE Circle; + IMG_OP_NUMBOX NumBox; +} IMG_OP_UNION; + +// Variables for DrawImage +#define IMG_MAX_DATA 11 +IMG_OP_UNION * gpImgData[IMG_MAX_DATA]; +SLONG * gpPassedImgVars; +SWORD gPassedVarsCount; + +// Private Prototypes +void cCmdDrawLine(SLONG x1, SLONG y1, SLONG x2, SLONG y2); +void cCmdDrawRect(SLONG left, SLONG bottom, SLONG width, SLONG hieght); +void cCmdCopyBitMapBits(SLONG dst_x, SLONG dst_y, + SLONG src_x, SLONG src_y, SLONG src_width, SLONG src_height, + IMG_OP_SPRITE * pSprite); +SLONG cCmdResolveValue(SWORD Value); +void cCmdSetPixel(SLONG X, SLONG Y, ULONG Val); + +//----------------------------------------------------------------- +//cCmdWrapDrawText +//ArgV[0]: (Function return) Status byte, SBYTE +//ArgV[1]: Location (IMG_PT *) +//ArgV[2]: Text (CStr) +//ArgV[3]: Options (ULONG) +// +NXT_STATUS cCmdWrapDrawText(UBYTE * ArgV[]) +{ + IMG_PT * pPt = (IMG_PT*) ArgV[1]; + + ArgV[2] = (UBYTE*)cCmdDVPtr(*(DV_INDEX *)(ArgV[2])); //Resolve array argument + + cCmdClearScreenIfNeeded(*(ULONG*)ArgV[3]); + + // Display the String + cCmdDrawString(ArgV[2], (UBYTE)pPt->X, (UBYTE)(pPt->Y)); + pMapDisplay->UpdateMask |= SCREEN_BIT(SCREEN_BACKGROUND); + + // Set return value + *((SBYTE*)(ArgV[0])) = NO_ERR; + + return NO_ERR; +} + +//----------------------------------------------------------------- +//cCmdWrapDrawPoint +//ArgV[0]: (Function return) Status byte, SBYTE +//ArgV[1]: Location (IMG_PT *) +//ArgV[2]: Options (ULONG) +NXT_STATUS cCmdWrapDrawPoint(UBYTE * ArgV[]) +{ + IMG_PT * pPt = (IMG_PT*) ArgV[1]; + + cCmdClearScreenIfNeeded(*(ULONG*)ArgV[2]); + + // Display the String + cCmdSetPixel(pPt->X, pPt->Y, TRUE); + + pMapDisplay->UpdateMask |= SCREEN_BIT(SCREEN_BACKGROUND); + + // Set return value + *((SBYTE*)(ArgV[0])) = NO_ERR; + + return NO_ERR; +} + +//----------------------------------------------------------------- +//cCmdWrapDrawLine +//ArgV[0]: (Function return) Status byte, SBYTE +//ArgV[1]: Start Location (IMG_PT *) +//ArgV[2]: End Location (IMG_PT *) +//ArgV[3]: Options (ULONG) +NXT_STATUS cCmdWrapDrawLine(UBYTE * ArgV[]) +{ + IMG_PT * pPt1 = (IMG_PT*) ArgV[1]; + IMG_PT * pPt2 = (IMG_PT*) ArgV[2]; + + cCmdClearScreenIfNeeded(*(ULONG*)ArgV[3]); + + cCmdDrawLine(pPt1->X, pPt1->Y, pPt2->X, pPt2->Y); + + pMapDisplay->UpdateMask |= SCREEN_BIT(SCREEN_BACKGROUND); + + // Set return value + *((SBYTE*)(ArgV[0])) = NO_ERR; + + return NO_ERR; +} + +//----------------------------------------------------------------- +//cCmdWrapDrawCircle +//ArgV[0]: (Function return) Status byte, SBYTE +//ArgV[1]: Start Location (IMG_PT *) +//ArgV[2]: Radius (U8) +//ArgV[3]: Options (ULONG) +NXT_STATUS cCmdWrapDrawCircle(UBYTE * ArgV[]) +{ + SLONG x, x1, y1, y, dp, delta; + IMG_PT * pPt = (IMG_PT*) ArgV[1]; + SLONG radius = *(UBYTE*)ArgV[2]; + + cCmdClearScreenIfNeeded(*(ULONG*)ArgV[3]); + + x1 = pPt->X; + y1 = pPt->Y; + x = 0; + y = radius; + dp=2*(1-radius); + while(y >= 0) + { + cCmdSetPixel((x+x1), (y+y1), TRUE); + cCmdSetPixel((-x+x1),(-y+y1), TRUE); + cCmdSetPixel((x+x1), (-y+y1), TRUE); + cCmdSetPixel((-x+x1),(y+y1), TRUE); + if(dp<0) + { + delta = 2*dp + 2*y - 1; + if (delta > 0) + { + x++; + y--; + dp += 2*x - 2*y + 2; + } + else + { + x++; + dp += 2*x + 1; + } + } + else if (dp > 0) + { + delta = 2*dp - 2*x - 1; + if (delta > 0) + { + y--; + dp += 1 - 2*y; + } + else + { + x++; + y--; + dp += 2*x - 2*y + 2; + } + } + else + { + x++; + y--; + dp += 2*x - 2*y +2; + } + } + + pMapDisplay->UpdateMask |= SCREEN_BIT(SCREEN_BACKGROUND); + + // Set return value + *((SBYTE*)(ArgV[0])) = NO_ERR; + + return NO_ERR; +} + +//----------------------------------------------------------------- +//cCmdWrapDrawRect +//ArgV[0]: (Function return) Status byte, SBYTE +//ArgV[1]: TopLeft (IMG_PT *) +//ArgV[2]: BottomRight (IMG_PT *) +//ArgV[3]: Options (ULONG) +NXT_STATUS cCmdWrapDrawRect(UBYTE * ArgV[]) +{ + IMG_PT * pPt1 = (IMG_PT*) ArgV[1]; + IMG_PT * pPt2 = (IMG_PT*) ArgV[2]; // Second point is actually (width, height) + + cCmdClearScreenIfNeeded(*(ULONG*)ArgV[3]); + + cCmdDrawRect(pPt1->X, pPt1->Y, pPt2->X, pPt2->Y); + + pMapDisplay->UpdateMask |= SCREEN_BIT(SCREEN_BACKGROUND); + + // Set return value + *((SBYTE*)(ArgV[0])) = NO_ERR; + + return NO_ERR; +} + +//----------------------------------------------------------------- +IMG_OP_UNION * cCmdGetIMGData(ULONG DataAddr) +{ + if (DataAddr >= IMG_MAX_DATA) + return NULL; + else + return gpImgData[DataAddr]; +} + +//----------------------------------------------------------------- +void cCmdSetIMGData(ULONG DataAddr, IMG_OP_UNION * pSprite) +{ + if ((DataAddr >= 1) && (DataAddr < IMG_MAX_DATA)) + gpImgData[DataAddr] = pSprite; +} + +//----------------------------------------------------------------- +SLONG cCmdResolveValue(SWORD Value) +{ + if (!IMG_SYMB_USEARGS(Value)) + { + return Value; + } + else + { + IMG_OP_VARMAP * pVarMap; + SLONG Arg; + + pVarMap = (IMG_OP_VARMAP *) cCmdGetIMGData((SWORD)IMG_SYMB_MAP(Value)); + Arg = gpPassedImgVars[IMG_SYMB_ARG(Value)]; + + if (!pVarMap) + { + // No map, this implies a 1:1 mapping. + return Arg; + } + else + { + // Scan through the list finding the pair the Arg lies between + // Then linearly interpolate the mapping. + SLONG i, DCur, RCur, DSpread, VSpread, RSpread; + SLONG Count = pVarMap->MapCount; + SLONG DPrev = pVarMap->MapElt[0].Domain; + SLONG RPrev = pVarMap->MapElt[0].Range; + if (Arg <= DPrev) + { + // Too small, map it to the first point + return RPrev; + } + + for (i = 1; i < Count; i++) + { + DCur = pVarMap->MapElt[i].Domain; + RCur = pVarMap->MapElt[i].Range; + if (Arg < DCur) + { + DSpread = DCur - DPrev; + VSpread = Arg - DPrev; + RSpread = RCur - RPrev; + // Found the point and mapped, it return. + return (RPrev+((VSpread*RSpread)/DSpread)); + } + DPrev = DCur; + RPrev = RCur; + } + // If we get this far then it is too large, map it to the last point. + return RCur; + } + } +} + + +//----------------------------------------------------------------- +//cCmdWrapDrawGraphic +//ArgV[0]: (Function return) Status Byte, SBYTE +//ArgV[1]: Left Top (IMG_PT *) +//ArgV[2]: Filename, CStr +//ArgV[3]: Variables, array of I32 +//ArgV[4]: Options (ULONG) +NXT_STATUS cCmdWrapDrawPicture(UBYTE * ArgV[]) +{ + SBYTE * pReturnVal = (SBYTE*)(ArgV[0]); + LOADER_STATUS LStatus; + NXT_STATUS DStatus = NO_ERR; + ULONG DataSize; + SLONG OpSize; + IMG_PT Pt; // Where to draw the picture at (up and to the right) + UBYTE ImageHandle; + IMG_OP_UNION * pImage; + + //Resolve array argument + ArgV[2] = (UBYTE*)cCmdDVPtr(*(DV_INDEX *)(ArgV[2])); + ArgV[3] = (UBYTE*)cCmdDVPtr(*(DV_INDEX *)(ArgV[3])); + + cCmdClearScreenIfNeeded(*(ULONG*)ArgV[4]); + + //Open the file in memory map mode. return if failure. + LStatus = pMapLoader->pFunc(OPENREADLINEAR, ArgV[2], (UBYTE*)(&pImage), &DataSize); + ImageHandle = LOADER_HANDLE(LStatus); + + //If error opening file, give up and write loader status back to user. + if (LOADER_ERR(LStatus) != SUCCESS || pImage == NULL) + { + *pReturnVal = (SBYTE)(LOADER_ERR_BYTE(LStatus)); + return (NO_ERR); + } + //Else, start interpretting the file + else + { + // Read the ArgV params, Clear the data table. + Pt = *(IMG_PT*)ArgV[1]; + //!!! Unsafe assumption that array is non-empty. Should check and avoid using pointer if empty. + gpPassedImgVars = (SLONG*)ArgV[3]; + memset(gpImgData,0,sizeof(gpImgData)); + + // Run through the op codes. + while(!IS_ERR(DStatus)) + { + // Setup to look at an opcode, make sure it looke reasonable. + if (DataSize < sizeof(IMG_OP_CORE)) + { + DStatus = ERR_FILE; + break; // Too small to look at, somethings wrong. + } + OpSize = pImage->Core.OpSize + sizeof(UWORD); + if (OpSize & 0x01) + { + DStatus = ERR_FILE; + break; // Odd sizes not allowed. + } + + switch(pImage->Core.OpCode) + { + case IMG_SPRITE_ID: + { + if (OpSize >= sizeof(IMG_OP_SPRITE)) + cCmdSetIMGData(pImage->Sprite.DataAddr, pImage); + } + break; + + case IMG_VARMAP_ID: + { + if (OpSize >= sizeof(IMG_OP_VARMAP)) + cCmdSetIMGData(pImage->VarMap.DataAddr, pImage); + } + break; + + case IMG_COPYBITS_ID: + { + if (OpSize >= sizeof(IMG_OP_COPYBITS)) + { + IMG_OP_COPYBITS * pCB = &(pImage->CopyBits); + cCmdCopyBitMapBits( + (cCmdResolveValue(pCB->Dst.X) + Pt.X), + (cCmdResolveValue(pCB->Dst.Y) + Pt.Y), + cCmdResolveValue((pCB->Src.Pt.X)), + cCmdResolveValue((pCB->Src.Pt.Y)), + cCmdResolveValue((pCB->Src.Width)), + cCmdResolveValue((pCB->Src.Height)), + (IMG_OP_SPRITE*)cCmdGetIMGData(cCmdResolveValue(pCB->DataAddr))); + } + } + break; + + case IMG_LINE_ID: + { + if (OpSize >= sizeof(IMG_OP_LINE)) + { + IMG_OP_LINE * pL = &(pImage->Line); + cCmdDrawLine( + (cCmdResolveValue(pL->Pt1.X)+Pt.X), + (cCmdResolveValue(pL->Pt1.Y)+Pt.Y), + (cCmdResolveValue(pL->Pt2.X)+Pt.X), + (cCmdResolveValue(pL->Pt2.Y)+Pt.Y) + ); + } + } + break; + + case IMG_RECTANGLE_ID: + { + if (OpSize >= sizeof(IMG_OP_LINE)) + { + IMG_OP_RECT * pL = &(pImage->Rect); + cCmdDrawRect( + (SWORD)(cCmdResolveValue(pL->Pt.X)+Pt.X), + (SWORD)(cCmdResolveValue(pL->Pt.Y)+Pt.Y), + (SWORD)(cCmdResolveValue(pL->Width)), + (SWORD)(cCmdResolveValue(pL->Height)) + ); + } + } + break; + + case IMG_PIXEL_ID: + { + if (OpSize >= sizeof(IMG_OP_PIXEL)) + { + cCmdSetPixel( + (cCmdResolveValue(pImage->Pixel.Pt.X) + Pt.X), + (cCmdResolveValue(pImage->Pixel.Pt.Y) + Pt.Y), + TRUE); + } + } + break; + + case IMG_NUMBOX_ID: + { + if (OpSize >= sizeof(IMG_OP_NUMBOX)) + { + UBYTE NumStr[20]; + IMG_OP_NUMBOX * pNB = &(pImage->NumBox); + sprintf((PSZ)NumStr, "%d", cCmdResolveValue(pNB->Value)); + cCmdDrawString( + NumStr, + (UBYTE) (cCmdResolveValue(pNB->Pt.X) + Pt.X), + (UBYTE) (cCmdResolveValue(pNB->Pt.Y) + Pt.Y)); + } + } + break; + + case IMG_DESCRIPTION_ID: + { + //No-op + } + break; + + default: + { + //Unrecognized opcode, pass an error back to the user. + DStatus = ERR_FILE; + } + break; + } + + DataSize -= OpSize; + pImage = (IMG_OP_UNION*) ((UBYTE*)pImage + OpSize); + } + + pMapDisplay->UpdateMask |= SCREEN_BIT(SCREEN_BACKGROUND); + } + + // Set return value, close file and return + *pReturnVal = DStatus; + pMapLoader->pFunc(CLOSE, &ImageHandle, NULL, NULL); + return (NO_ERR); +} + +//----------------------------------------------------------------- +// cCmdDrawLine - draw a line. All clipping is done by the set pixel function. +void cCmdDrawLine( + SLONG x1, + SLONG y1, + SLONG x2, + SLONG y2) +{ + SLONG d,x,y,ax,ay,sx,sy,dx,dy; + + // Initialize variables + dx = x2-x1; ax = ABS(dx)<<1; sx = SGN(dx); + dy = y2-y1; ay = ABS(dy)<<1; sy = SGN(dy); + x = x1; + y = y1; + if (ax>ay) + { /* x dominant */ + d = ay-(ax>>1); + for (;;) + { + cCmdSetPixel(x, y, TRUE); + if (x==x2) + return; + if (d>=0) + { + y += sy; + d -= ax; + } + x += sx; + d += ay; + } + } + else + { /* y dominant */ + d = ax-(ay>>1); + for (;;) + { + cCmdSetPixel(x, y, TRUE); + if (y==y2) + return; + if (d>=0) + { + x += sx; + d -= ay; + } + y += sy; + d += ax; + } + } +} + + +//----------------------------------------------------------------- +// cCmdDrawRect - draw a rectangle. All clipping is done by the set pixel function. +void cCmdDrawRect( + SLONG left, + SLONG bottom, + SLONG width, + SLONG height) +{ + SLONG right = left + width; + SLONG top = bottom + height; + + // Draw the four line segments + cCmdDrawLine(left, top, right, top); + cCmdDrawLine(right, top, right, bottom); + cCmdDrawLine(right, bottom, left, bottom); + cCmdDrawLine(left, bottom, left, top); +} + + +#ifndef DISPLAY_REALWIDTH + #define DISPLAY_REALWIDTH DISPLAY_WIDTH +#endif +//----------------------------------------------------------------- +//cCmdCopyBitMapBits +void cCmdCopyBitMapBits( + SLONG dst_x, // left pixel on LCD + SLONG dst_y, // bottom pixel on LCD + SLONG src_x, // starting pixel x coordinate from source map + SLONG src_y, // starting pixel y coordinate from source map + SLONG src_width, // width in pixels to the right (negative implies to the left) + SLONG src_height, // height in pixels down (negative implies down) + IMG_OP_SPRITE * pSprite) +{ + SLONG dy; // Location in the destination pixmap , the screen that is + SLONG sx; + SLONG sy; // Location in the source pixmap. + SLONG trim, last_x, last_y, rowbytes; + UBYTE *pSrcByte; + UBYTE *pDstBytes; + UBYTE *pDstByte, *pFirstDstByte; + UBYTE *pLastDstByte; + UBYTE bit_y, not_bit_y; + UBYTE masks[8] = {0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, 0x01}; + + // Data in the image file is row major 8 pixels per byte.top row first. + // src and dst coordinates treat the bottom left most pixel as (0,0) + + if (!pSprite || pSprite->OpCode!=IMG_SPRITE_ID) + return; + + pDstBytes = DISP_BUFFER_P; + + // Clip the edges. Modify the source and width as well. + if (dst_x < 0) { // bounds check start of x + trim = (0 - dst_x); + dst_x = 0; + src_x += trim; + src_width -= trim; + } + + last_x = dst_x + src_width; + if (last_x > DISPLAY_WIDTH) // bound check end of x + last_x = DISPLAY_WIDTH; + + if (dst_y < 0) { // bound check start of y + trim = (0 - dst_y); + dst_y = 0; + src_y += trim; // fix up source as well since we are clipping the start of the loop + src_height -= trim; + } + + last_y = dst_y + src_height; + if (last_y > DISPLAY_HEIGHT) // bound check end of y + last_y = DISPLAY_HEIGHT; + + // Convert the 0,0 bottom left origin to the top left 0,0 used by the actual + // buffer + last_y = TRANSLATE_Y(last_y); + dst_y = TRANSLATE_Y(dst_y); + + // The last row is the top most scan line in the LCD Buffer + // so limit if the copy would copy into memory before the buffer. + // The first row copied will be the one closest to the bottom of the LCD + // If that is off screen then limit as well and adjust the start point on the start + + // Copy bits top to top moving down. + sy = src_y; + rowbytes = pSprite->RowBytes; + + pSrcByte = pSprite->Bytes + ((pSprite->Rows - 1 - sy) * rowbytes); + pFirstDstByte = pDstBytes + ((dst_y >> 3) * DISPLAY_REALWIDTH) + dst_x; + for (dy = dst_y; dy > last_y; dy--) + { + sx = src_x; + bit_y = masks[7 - (dy & 0x07)]; + not_bit_y = ~ bit_y; + pDstByte = pFirstDstByte; + pLastDstByte = pDstByte + (last_x - dst_x); + for (; pDstByte < pLastDstByte; pDstByte++) + { + if ( *(pSrcByte + (sx >> 3)) & masks[sx & 0x07] ){ + *pDstByte |= bit_y; + } else { + *pDstByte &= not_bit_y; + } + sx ++; + } + pSrcByte -= rowbytes; + sy ++; + if ((dy & 0x07) == 0) // bump back the scan line start point at rollover + pFirstDstByte -= DISPLAY_REALWIDTH; + } + +} + +//----------------------------------------------------------------- +// cCmdSetPixel - Set or clear a pixel based on Val +void cCmdSetPixel(SLONG X, SLONG Y, ULONG Val) +{ + Y = TRANSLATE_Y(Y); + + pMapDisplay->pFunc(DISPLAY_PIXEL, (UBYTE)Val, (UBYTE)X, (UBYTE)Y, 0, 0); +} + + +//----------------------------------------------------------------- +//cCmdWrapSetScreenMode +//ArgV[0]: (Function return) Status code, SBYTE +//ArgV[1]: ScreenMode ULONG +NXT_STATUS cCmdWrapSetScreenMode(UBYTE * ArgV[]) +{ + ULONG ScreenMode = (ULONG)(*ArgV[1]); + if (ScreenMode == RESTORE_NXT_SCREEN) { + cCmdRestoreDefaultScreen(); + } + + // Set return value + *(SBYTE*)(ArgV[0]) = NO_ERR; + return NO_ERR; +} + +//------------------------------------------------------------------ +// cCmdClearScreenIfNeeded - Clear entire sceen buffer if explicitly requested or implicitly required. +void cCmdClearScreenIfNeeded(ULONG DrawOptions) +{ + //If we are the first drawing command, clear the screen and record that we've done so + if (VarsCmd.DirtyDisplay == FALSE) + { + VarsCmd.DirtyDisplay = TRUE; + pMapUi->Flags &= ~UI_ENABLE_STATUS_UPDATE; + + //Override DrawOptions because we have to clear anyway + DrawOptions = DRAW_OPT_CLEAR_WHOLE_SCREEN; + } + + if (DRAW_OPT_CLEAR_MODE(DrawOptions)) + { + pMapDisplay->pFunc(DISPLAY_ERASE_ALL, 0, 0, 0, 0, 0); + + //Clear UpdateMask to kill any pending updates + pMapDisplay->UpdateMask = 0; + } + + return; +} + +//------------------------------------------------------------------ +// cCmdDrawString - Draw string to display buffer +// Properly uses 'Normal' display buffer to avoid conflicts with popup buffer +// Clips text at bottom and right hand edges of the screen buffer +//!!! Function copied and modified from cDisplayString +void cCmdDrawString(UBYTE *pString, ULONG X, ULONG Y) +{ + UBYTE *pSource; + UBYTE *pDestination; + FONT *pFont; + ULONG FontWidth; + ULONG Items; + ULONG Item; + ULONG Line; + + //Get current font information + pFont = pMapDisplay->pFont; + Items = pFont->ItemsX * pFont->ItemsY; + + //Invert Y coordinate to match display buffer + Y = TRANSLATE_Y(Y); + Line = (Y & 0xF8) / 8; + + //If text line is out of bounds, do nothing. + if (Line >= TEXTLINES) + return; + + //Calculate pointer to first byte of drawing destination + pDestination = &(DISP_BUFFER_P[Line * DISPLAY_WIDTH + X]); + + while (*pString) + { + FontWidth = pFont->ItemPixelsX; + //Calculate X coordinate of the right edge of this character. + //If it will extend past the right edge, clip the string. + X += FontWidth; + if (X >= DISPLAY_WIDTH) + break; + + //If Item is defined by the font, display it. Else, ignore it. + Item = *pString - ' '; + if (Item < Items) + { + pSource = (UBYTE*)&(pFont->Data[Item * FontWidth]); + while (FontWidth--) + { + *pDestination = *pSource; + pDestination++; + pSource++; + } + } + pString++; + } +} + +//------------------------------------------------------------------ +// cCmdRestoreDefaultScreen - Restore to Default 'Running' screen +void cCmdRestoreDefaultScreen(void) +{ + //If this program has taken over the display, reset it for the UI + if (VarsCmd.DirtyDisplay == TRUE) + { + VarsCmd.DirtyDisplay = FALSE; + + pMapDisplay->pFunc(DISPLAY_ERASE_ALL, 0, 0, 0, 0, 0); + pMapDisplay->UpdateMask = SCREEN_BIT(SCREEN_BACKGROUND); + + pMapUi->Flags |= UI_ENABLE_STATUS_UPDATE | UI_REDRAW_STATUS; + } +} diff --git a/AT91SAM7S256/Source/c_comm.c b/AT91SAM7S256/Source/c_comm.c new file mode 100644 index 0000000..291c96b --- /dev/null +++ b/AT91SAM7S256/Source/c_comm.c @@ -0,0 +1,3658 @@ +// +// Date init 14.12.2004 +// +// Revision date $Date:: 16-05-06 9:42 $ +// +// Filename $Workfile:: c_comm.c $ +// +// Version $Revision:: 172 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/c_comm.c $ +// +// Platform C +// + +#include "stdconst.h" +#include "modules.h" +#include "c_comm.iom" +#include "c_loader.iom" +#include "c_ioctrl.iom" +#include "c_ui.iom" +#include "c_cmd.iom" +#include "c_display.iom" +#include "c_comm.h" +#include "d_usb.h" +#include "d_hispeed.h" +#include "d_bt.h" +#include +#include + +enum +{ + DEVICE_VERIFIED, + DEVICE_UPDATED, + DEVICE_INSERTED +}; + +#define DEFAULTBTADR "\x00\x16\x53\xFF\xFF\xFF" +#define BTSTREAMTOUT 610 + +#define LOOKUPNO 3 + +#define CLEARExtMode {\ + UBYTE Tmp;\ + for(Tmp = 0; Tmp < NO_OF_CHANNELS; Tmp++)\ + {\ + VarsComm.ExtMode[Tmp].Status = FALSE;\ + }\ + } + +#define CHNumber(Bit) (Bit>>1) +#define SETBtStateIdle VarsComm.ActiveUpdate = UPD_IDLE;\ + VarsComm.UpdateState = 0;\ + VarsComm.StreamStateCnt = 0;\ + VarsComm.CmdSwitchCnt = 0;\ + VarsComm.CloseConn0Cnt = 0;\ + VarsComm.DiscAllCnt = 0;\ + VarsComm.ResetBtCnt = 0 + +#define SETBtCmdState VarsComm.BtState = BT_ARM_CMD_MODE;\ + IOMapComm.BtInBuf.InPtr = 0;\ + CLEARExtMode;\ + dBtClearArm7CmdSignal();\ + dBtInitReceive(VarsComm.BtModuleInBuf.Buf, (UBYTE)CMD_MODE); + +#define SETBtDataState IOMapComm.BtInBuf.InPtr = 0;\ + VarsComm.BtState = BT_ARM_DATA_MODE;\ + dBtClearTimeOut(); /* stop cmd timeout because in datamode */\ + dBtSetArm7CmdSignal();\ + dBtInitReceive(VarsComm.BtModuleInBuf.Buf, (UBYTE)STREAM_MODE) + +#define SETBtOff VarsComm.BtState = BT_ARM_OFF;\ + dBtSetBcResetPinLow() + +#define CLEARConnEntry(Index) memset((IOMapComm.BtConnectTable[Index].BdAddr), 0, SIZE_OF_BDADDR);\ + memset(IOMapComm.BtConnectTable[Index].Name, 0, SIZE_OF_BT_NAME);\ + memset((IOMapComm.BtConnectTable[Index].ClassOfDevice), 0, SIZE_OF_CLASS_OF_DEVICE);\ + memset((IOMapComm.BtConnectTable[Index].PinCode), 0, SIZE_OF_BT_PINCODE);\ + IOMapComm.BtConnectTable[Index].HandleNr = BLUETOOTH_HANDLE_UNDEFIEND;\ + IOMapComm.BtConnectTable[Index].StreamStatus = 0;\ + IOMapComm.BtConnectTable[Index].LinkQuality = 0 + +#define FILETXTOUT 30000 + +const UBYTE BootString[] = {"Let's dance: SAMBA"}; +const UBYTE NoName[SIZE_OF_BT_NAME] = {"No Name"}; + +static IOMAPCOMM IOMapComm; +static VARSCOMM VarsComm; +static HEADER **pHeaders; + +const HEADER cComm = +{ + 0x00050001L, + "Comm", + cCommInit, + cCommCtrl, + cCommExit, + (void *)&IOMapComm, + (void *)&VarsComm, + (UWORD)sizeof(IOMapComm), + (UWORD)sizeof(VarsComm), + 0x0000 /* Code size - not used so far */ +}; + +UWORD cCommReceivedBtData(void); +void cCommBtCmdInterpreter(void); +UWORD cCommInterprete(UBYTE *pInBuf, UBYTE *pOutBuf, UBYTE *pLength, UBYTE CmdBit, UWORD MsgLength); +UWORD cCommInterpreteCmd(UBYTE Cmd, UBYTE *pInBuf, UBYTE *pOutBuf, UBYTE *pLength, UBYTE CmdBit, UWORD MsgLength); +void cCommCpyToUpper(UBYTE *pDst, UBYTE *pSrc, UBYTE Length); +void cCommCopyFileName(UBYTE *pDst, UBYTE *pSrc); +void cCommSendHiSpeedData(void); +void cCommReceivedHiSpeedData(void); +UWORD cCommReq(UBYTE Cmd, UBYTE Param1, UBYTE Param2, UBYTE Param3, UBYTE *pName, UWORD *pRetVal); +UBYTE cCommBtValidateCmd(void); + +void cCommClearStreamStatus(void); +void cCommUpdateBt(void); +UWORD cCommCopyBdaddr(UBYTE *pDst, UBYTE *pSrc); +UWORD cCommInsertBtName(UBYTE *pDst, UBYTE *pSrc); +UWORD cCommCheckBdaddr(UBYTE *pAdr, UBYTE *pSrc); +UWORD cCommInsertDevice(UBYTE *pBdaddr, UBYTE *pName, UBYTE *pCod, UBYTE DeviceStatus, UBYTE *pAddInfo); +void cCommsSetCmdMode(UBYTE *pNextState); +void cCommsOpenStream(UBYTE *pNextState); +void cCommsCloseConn0(UBYTE *pNextState); +void cCommsDisconnectAll(UBYTE *pNextState); +void cCommsBtReset(UBYTE *pNextState); +void cCommPinCode(UBYTE *pPinCode); +void cCommClrConnTable(void); + +void cCommInit(void* pHeader) +{ + UBYTE Tmp; + + pHeaders = pHeader; + IOMapComm.pFunc = &cCommReq; + IOMapComm.pFunc2 = &cCommPinCode; + IOMapComm.UsbState = FALSE; + IOMapComm.UsbOutBuf.OutPtr = 0; + + CLEARExtMode; + + dUsbInit(); + dBtInit(); + + SETBtStateIdle; + VarsComm.BtModuleInBuf.InPtr = 0; + VarsComm.BtWaitTimeCnt = 0; + + /* Force a reset sequence on the BC4 */ + VarsComm.pRetVal = &(VarsComm.RetVal); + VarsComm.ActiveUpdate = UPD_RESET; + + VarsComm.BtState = BT_ARM_CMD_MODE; + IOMapComm.BrickData.BtHwStatus = BT_DISABLE; + + for (Tmp = 0; Tmp < SIZE_OF_BT_DEVICE_TABLE; Tmp++) + { + IOMapComm.BtDeviceTable[Tmp].DeviceStatus = BT_DEVICE_EMPTY; + } + IOMapComm.BtDeviceCnt = 0; + IOMapComm.BrickData.BtStateStatus = 0; + + cCommClrConnTable(); + + dBtInitReceive(VarsComm.BtModuleInBuf.Buf, (UBYTE)CMD_MODE); + dBtStartADConverter(); + + dHiSpeedInit(); + VarsComm.HsState = 0; + + IOMapComm.UsbPollBuf.InPtr = 0; + IOMapComm.UsbPollBuf.OutPtr = 0; + + VarsComm.BtAdrStatus = COLDBOOT; +} + +void cCommCtrl(void) +{ + + if (FALSE == cCommReceivedBtData()) + { + + /* there has been a timeout on the BC4 channel */ + SETBtStateIdle; + *(VarsComm.pRetVal) = BTTIMEOUT; + if (COLDBOOT == VarsComm.BtAdrStatus) + { + + /* there is an BT fatal error - set default bt adr and name*/ + strcpy((char*)IOMapComm.BrickData.Name, (char*)UI_NAME_DEFAULT); + dUsbStoreBtAddress((UBYTE*)DEFAULTBTADR); + pMapUi->Flags |= UI_REDRAW_STATUS; + dBtSetBcResetPinLow(); + VarsComm.BtAdrStatus = BTADRERROR; + } + } + cCommUpdateBt(); + VarsComm.BtBcPinLevel = dBtGetBc4CmdSignal(); + + if (UPD_IDLE == VarsComm.ActiveUpdate) + { + switch (VarsComm.BtState) + { + + /* Bluetooth device can either be in CMD, DATA or OFF state at top level */ + case BT_ARM_OFF: + { + } + break; + case BT_ARM_CMD_MODE: + { + if (VarsComm.BtBcPinLevel) + { + SETBtDataState; + } + } + break; + + case BT_ARM_DATA_MODE: + { + if (!(VarsComm.BtBcPinLevel)) + { + SETBtCmdState; + } + } + break; + } + } + IOMapComm.BtInBuf.Buf[BT_CMD_BYTE] = 0; + + + /* Here comes the the HIGHSPEED_PORT implementation */ + if (IOMapComm.HsFlags & HS_UPDATE) + { + IOMapComm.HsFlags &= ~HS_UPDATE; + switch (IOMapComm.HsState) + { + case HS_INITIALISE: + { + dHiSpeedSetupUart(); + IOMapComm.HsState = HS_INIT_RECEIVER; + IOMapComm.HsFlags |= HS_UPDATE; + } + break; + + case HS_INIT_RECEIVER: + { + dHiSpeedInitReceive(VarsComm.HsModuleInBuf.Buf); + VarsComm.HsState = 0x01; + } + break; + + case HS_SEND_DATA: + { + cCommSendHiSpeedData(); + } + break; + + case HS_DISABLE: + { + VarsComm.HsState = 0x00; + dHiSpeedExit(); + } + break; + } + } + + if (VarsComm.HsState != 0) + { + cCommReceivedHiSpeedData(); + } + + /* Here comes the the USB implementation */ + ULONG Length; + UWORD Status; + + if (0 != IOMapComm.UsbOutBuf.OutPtr) + { + dUsbWrite((const UBYTE *)IOMapComm.UsbOutBuf.Buf, (ULONG)IOMapComm.UsbOutBuf.OutPtr); + IOMapComm.UsbOutBuf.OutPtr = 0; + } + + Length = 0; + + if (TRUE == dUsbCheckConnection()) + { + pMapUi->UsbState = 1; + if (TRUE == dUsbIsConfigured()) + { + Length = dUsbRead(IOMapComm.UsbInBuf.Buf, sizeof(IOMapComm.UsbInBuf.Buf)); + IOMapComm.UsbState = TRUE; + pMapUi->UsbState = 2; + } + } + else + { + pMapUi->UsbState = 0; + dUsbResetConfig(); + if (TRUE == IOMapComm.UsbState) + { + IOMapComm.UsbState = FALSE; + Status = dUsbGetFirstHandle(); + while(0 == LOADER_ERR(Status)) + { + IOMapComm.UsbInBuf.Buf[0] = LOADER_HANDLE(Status); + pMapLoader->pFunc(CLOSE, &(IOMapComm.UsbInBuf.Buf[0]), &(IOMapComm.UsbInBuf.Buf[2]), &Length); + dUsbRemoveHandle(IOMapComm.UsbInBuf.Buf[0]); + Status = dUsbGetNextHandle(); + } + } + } + + if (0 != Length) + { + cCommInterprete(IOMapComm.UsbInBuf.Buf, IOMapComm.UsbOutBuf.Buf, (UBYTE*)&Length, USB_CMD_READY, (UWORD)Length); + if (Length) + { + dUsbWrite((const UBYTE *)IOMapComm.UsbOutBuf.Buf, Length); + } + } + dBtStartADConverter(); +} + +void cCommExit(void) +{ + dUsbExit(); + dHiSpeedExit(); + dBtExit(); +} + +UWORD cCommInterprete(UBYTE *pInBuf, UBYTE *pOutBuf, UBYTE *pLength, UBYTE CmdBit, UWORD MsgLength) +{ + UWORD ReturnStatus; + UBYTE Channel; + + Channel = CHNumber(CmdBit); + if (FALSE == VarsComm.ExtMode[Channel].Status) + { + + switch (((pInBuf[0]) & ~NO_REPLY_BIT)) + { + case SYSTEM_CMD: + { + ReturnStatus = cCommInterpreteCmd(pInBuf[1], &(pInBuf[1]), &(pOutBuf[2]), pLength, CmdBit, MsgLength); + + /* Check if reply is requested */ + if ((pInBuf[0]) & NO_REPLY_BIT) + { + + /* Sender has choosen no reply */ + *pLength = 0; + + /* if extended mode then remember the reply bit */ + VarsComm.ExtMode[Channel].Type |= NO_REPLY_BIT; + } + else + { + + /* Check if receiver wants to reply */ + if (*pLength) + { + (*pLength)+= 2; + pOutBuf[0] = REPLY_CMD; + pOutBuf[1] = pInBuf[1]; + } + } + } + break; + + case DIRECT_CMD: + { + + /* Adjust length to account for cmd type byte */ + (*pLength) -= 1; + + /* If no reply requested, pass NULL output buffer pointer and clear *pLength */ + if ((pInBuf[0]) & NO_REPLY_BIT) + { + pMapCmd->pRCHandler(&(pInBuf[0]), NULL, pLength); + } + else + { + pMapCmd->pRCHandler(&(pInBuf[0]), &(pOutBuf[2]), pLength); + if (*pLength) + { + (*pLength) += 2; + pOutBuf[0] = REPLY_CMD; + pOutBuf[1] = pInBuf[1]; + } + } + } + break; + + case REPLY_CMD: + { + + /* If this is a reply to a direct command opcode, pRCHandler will handle it */ + if (pInBuf[1] < NUM_RC_OPCODES) + pMapCmd->pRCHandler(&(pInBuf[0]), NULL, pLength); + + /* No Reply ever required on REPLY_CMD messages */ + *pLength = 0; + } + break; + + default: + { + + /* UNSUPPORTED - don't reply on these messages */ + *pLength = 0; + } + break; + } + + } + else + { + switch (VarsComm.ExtMode[Channel].Type & ~NO_REPLY_BIT) + { + case SYSTEM_CMD: + { + ReturnStatus = cCommInterpreteCmd(VarsComm.ExtMode[Channel].Cmd, &(pInBuf[0]), &(pOutBuf[2]), pLength, CmdBit, MsgLength); + if ((VarsComm.ExtMode[Channel].Type) & NO_REPLY_BIT) + { + + /* Sender has choosen no reply */ + *pLength = 0; + } + else + { + + /* Check if receiver wants to reply */ + if (*pLength) + { + (*pLength) += 2; + pOutBuf[0] = REPLY_CMD; + pOutBuf[1] = VarsComm.ExtMode[Channel].Cmd; + } + } + } + break; + case DIRECT_CMD: + { + } + break; + case REPLY_CMD: + { + } + break; + default: + { + } + break; + } + } + + return(ReturnStatus); +} + + +UWORD cCommInterpreteCmd(UBYTE Cmd, UBYTE *pInBuf, UBYTE *pOutBuf, UBYTE *pLength, UBYTE CmdBit, UWORD MsgLength) +{ + ULONG FileLength; + UWORD Status; + UBYTE Channel; + + Channel = CHNumber(CmdBit); + switch(Cmd) + { + case OPENWRITE: + { + UBYTE TmpFilename[FILENAME_LENGTH + 1]; + + FileLength = pInBuf[21]; + FileLength += (ULONG)pInBuf[22] << 8; + FileLength += (ULONG)pInBuf[23] << 16; + FileLength += (ULONG)pInBuf[24] << 24; + + cCommCpyToUpper(TmpFilename, &pInBuf[1], (UBYTE)(FILENAME_LENGTH + 1)); + + if ((0 != strstr((PSZ)(TmpFilename), ".RXE")) || + (0 != strstr((PSZ)(TmpFilename), ".SYS")) || + (0 != strstr((PSZ)(TmpFilename), ".RTM"))) + { + Status = pMapLoader->pFunc(OPENWRITELINEAR, &pInBuf[1], NULL, &FileLength); + } + else + { + Status = pMapLoader->pFunc(OPENWRITE, &pInBuf[1], NULL, &FileLength); + } + pOutBuf[0] = LOADER_ERR_BYTE(Status); + pOutBuf[1] = LOADER_HANDLE(Status); + *pLength = 2; + if ((SUCCESS == LOADER_ERR(Status)) && (CmdBit & USB_CMD_READY)) + { + dUsbInsertHandle(LOADER_HANDLE(Status)); + } + } + break; + case WRITE: + { + + if (FALSE == VarsComm.ExtMode[Channel].Status) + { + + FileLength = *pLength - 3; + Status = pMapLoader->pFunc(WRITE, &(pInBuf[1]), &(pInBuf[2]), &FileLength); + pOutBuf[2] = (UBYTE)(FileLength); + pOutBuf[3] = (UBYTE)(FileLength >> 8); + if ((*pLength != MsgLength) && (MsgLength != 0)) + { + + /* This is the beginnig of and extended write command*/ + VarsComm.ExtMode[Channel].Cmd = WRITE; + VarsComm.ExtMode[Channel].Type = SYSTEM_CMD; + VarsComm.ExtMode[Channel].Status = TRUE; + VarsComm.ExtMode[Channel].Handle = LOADER_HANDLE(Status); + *pLength = 0; + } + else + { + + /* Normal write */ + pOutBuf[0] = LOADER_ERR_BYTE(Status); + pOutBuf[1] = LOADER_HANDLE(Status); + *pLength = 4; + } + } + else + { + UWORD TmpLen; + FileLength = *pLength; + Status = pMapLoader->pFunc(WRITE, &(VarsComm.ExtMode[Channel].Handle), &(pInBuf[0]), &FileLength); + TmpLen = pOutBuf[3]; + TmpLen <<= 8; + TmpLen |= pOutBuf[2]; + TmpLen += FileLength; + pOutBuf[2] = (UBYTE)(TmpLen); + pOutBuf[3] = (UBYTE)(TmpLen >> 8); + if (MsgLength) + { + + /* Don't answer before complete message has been received */ + *pLength = 0; + } + else + { + + /* Complete msg has been received */ + VarsComm.ExtMode[Channel].Status = FALSE; + pOutBuf[0] = LOADER_ERR_BYTE(Status); + pOutBuf[1] = LOADER_HANDLE(Status); + *pLength = 4; /* Remember the 2 length bytes */ + + } + } + + } + break; + case OPENWRITEDATA: + { + FileLength = pInBuf[21]; + FileLength += (ULONG)pInBuf[22] << 8; + FileLength += (ULONG)pInBuf[23] << 16; + FileLength += (ULONG)pInBuf[24] << 24; + + Status = pMapLoader->pFunc(OPENWRITEDATA, &pInBuf[1], NULL, &FileLength); + + pOutBuf[0] = LOADER_ERR_BYTE(Status); + pOutBuf[1] = LOADER_HANDLE(Status); + *pLength = 2; + if ((SUCCESS == LOADER_ERR(Status)) && (CmdBit & USB_CMD_READY)) + { + dUsbInsertHandle(LOADER_HANDLE(Status)); + } + } + break; + case OPENAPPENDDATA: + { + Status = pMapLoader->pFunc(OPENAPPENDDATA, &pInBuf[1], NULL, &FileLength); + pOutBuf[0] = LOADER_ERR_BYTE(Status); + pOutBuf[1] = LOADER_HANDLE(Status); + + pOutBuf[2] = (UBYTE)FileLength; + pOutBuf[3] = (UBYTE)(FileLength >> 8); + pOutBuf[4] = (UBYTE)(FileLength >> 16); + pOutBuf[5] = (UBYTE)(FileLength >> 24); + *pLength = 6; + if ((SUCCESS == LOADER_ERR(Status)) && (CmdBit & USB_CMD_READY)) + { + dUsbInsertHandle(LOADER_HANDLE(Status)); + } + } + break; + case CLOSE: + { + if (CmdBit & USB_CMD_READY) + { + dUsbRemoveHandle(pInBuf[1]); + } + Status = pMapLoader->pFunc(CLOSE, &(pInBuf[1]), NULL, &FileLength); + pOutBuf[0] = LOADER_ERR_BYTE(Status); + pOutBuf[1] = LOADER_HANDLE(Status); + *pLength = 2; + } + break; + case OPENREAD: + { + Status = pMapLoader->pFunc(OPENREAD, &pInBuf[1], NULL, &FileLength); + pOutBuf[0] = LOADER_ERR_BYTE(Status); + pOutBuf[1] = LOADER_HANDLE(Status); + pOutBuf[2] = (UBYTE)FileLength; + pOutBuf[3] = (UBYTE)(FileLength >> 8); + pOutBuf[4] = (UBYTE)(FileLength >> 16); + pOutBuf[5] = (UBYTE)(FileLength >> 24); + *pLength = 6; + if ((SUCCESS == LOADER_ERR(Status)) && (CmdBit & USB_CMD_READY)) + { + dUsbInsertHandle(LOADER_HANDLE(Status)); + } + } + break; + case READ: + { + ULONG Length; + + FileLength = pInBuf[3]; + FileLength <<= 8; + FileLength |= pInBuf[2]; + Length = FileLength; + + /* Here test for channel - USB can only handle a 64 byte return (- wrapping )*/ + if (CmdBit & USB_CMD_READY) + { + if (FileLength > (SIZE_OF_USBBUF - 6)) + { + + /* Buffer cannot hold the requested data adjust to buffer size */ + FileLength = (SIZE_OF_USBBUF - 6); + } + *pLength = FileLength + 4; + Status = pMapLoader->pFunc(READ, &pInBuf[1], &pOutBuf[4], &FileLength); + pOutBuf[0] = LOADER_ERR_BYTE(Status); + pOutBuf[1] = LOADER_HANDLE(Status); + pOutBuf[2] = (UBYTE)Length; + pOutBuf[3] = (UBYTE)(Length >> 8); + + if (FileLength < Length) + { + + /* End of file is detcted - add up with zeros to the requested msg length */ + Length -= FileLength; + memset(&(pOutBuf[(FileLength + 4)]),0x00,Length); + } + } + else + { + + /* This is a BT request - BT can handle large packets */ + if (FileLength > (SIZE_OF_BTBUF - 6)) + { + + /* Read length exceeds buffer length check for extended read back */ + if (SUCCESS == cCommReq(EXTREAD, 0x00, 0x00, 0x00, NULL, &(VarsComm.RetVal))) + { + + /* More data requested than buffer can hold .... go into extended mode */ + VarsComm.ExtTx.RemMsgSize = FileLength; + VarsComm.ExtTx.SrcHandle = pInBuf[1]; + VarsComm.ExtTx.Cmd = READ; + *pLength = 0; + } + else + { + + /* We were not able to go into extended mode bt was busy */ + /* for now do not try to reply as it is not possible to */ + /* return the requested bytes */ + *pLength = 0; + } + } + else + { + + *pLength = FileLength + 4; + Status = pMapLoader->pFunc(READ, &pInBuf[1], &pOutBuf[4], &FileLength); + pOutBuf[0] = LOADER_ERR_BYTE(Status); + pOutBuf[1] = LOADER_HANDLE(Status); + pOutBuf[2] = (UBYTE)Length; + pOutBuf[3] = (UBYTE)(Length >> 8); + + if (FileLength < Length) + { + + /* End of file is detcted - add up with zeros to the requested msg length */ + Length -= FileLength; + memset(&(pOutBuf[(FileLength + 4)]),0x00,Length); + } + } + } + } + break; + case DELETE: + { + Status = pMapLoader->pFunc(DELETE, &pInBuf[1], NULL, &FileLength); + pOutBuf[0] = LOADER_ERR_BYTE(Status); + cCommCopyFileName(&pOutBuf[1], &pInBuf[1]); + *pLength = FILENAME_LENGTH + 1 + 1; /*Filemname + 0 terminator + error byte */ + } + break; + case FINDFIRST: + { + Status = pMapLoader->pFunc(FINDFIRST, &(pInBuf[1]), &(pOutBuf[2]), &FileLength); + pOutBuf[0] = LOADER_ERR_BYTE(Status); + pOutBuf[1] = LOADER_HANDLE(Status); + if (LOADER_ERR_BYTE(SUCCESS) == pOutBuf[0]) + { + pOutBuf[22] = (UBYTE)FileLength; + pOutBuf[23] = (UBYTE)(FileLength >> 8); + pOutBuf[24] = (UBYTE)(FileLength >> 16); + pOutBuf[25] = (UBYTE)(FileLength >> 24); + if (CmdBit & USB_CMD_READY) + { + dUsbInsertHandle(pOutBuf[1]); + } + } + else + { + + /* ERROR - Fill with zeros */ + memset(&(pOutBuf[2]),0x00,24); + } + + *pLength = 26; + } + break; + case FINDNEXT: + { + Status = pMapLoader->pFunc(FINDNEXT, &(pInBuf[1]), &(pOutBuf[2]), &FileLength); + pOutBuf[0] = LOADER_ERR_BYTE(Status); + pOutBuf[1] = LOADER_HANDLE(Status); + if (LOADER_ERR_BYTE(SUCCESS) == pOutBuf[0]) + { + pOutBuf[22] = (UBYTE)FileLength; + pOutBuf[23] = (UBYTE)(FileLength >> 8); + pOutBuf[24] = (UBYTE)(FileLength >> 16); + pOutBuf[25] = (UBYTE)(FileLength >> 24); + } + else + { + + /* ERROR - Fill with zeros */ + memset(&(pOutBuf[2]),0x00,24); + } + *pLength = 26; + } + break; + case OPENREADLINEAR: + { + + /* For internal use only */ + } + break; + case VERSIONS: + { + pOutBuf[0] = LOADER_ERR_BYTE(SUCCESS); + pOutBuf[1] = (UBYTE)PROTOCOLVERSION; + pOutBuf[2] = (UBYTE)(PROTOCOLVERSION>>8); + pOutBuf[3] = (UBYTE)FIRMWAREVERSION; + pOutBuf[4] = (UBYTE)(FIRMWAREVERSION>>8); + *pLength = 5; + } + break; + case OPENWRITELINEAR: + { + FileLength = pInBuf[21]; + FileLength += (ULONG)pInBuf[22] << 8; + FileLength += (ULONG)pInBuf[23] << 16; + FileLength += (ULONG)pInBuf[24] << 24; + Status = pMapLoader->pFunc(OPENWRITELINEAR, &pInBuf[1], NULL, &FileLength); + pOutBuf[0] = LOADER_ERR_BYTE(Status); + pOutBuf[1] = LOADER_HANDLE(Status); + *pLength = 2; + if ((SUCCESS == LOADER_ERR(Status)) && (CmdBit & USB_CMD_READY)) + { + dUsbInsertHandle(LOADER_HANDLE(Status)); + } + } + break; + case FINDFIRSTMODULE: + { + Status = pMapLoader->pFunc(FINDFIRSTMODULE, &pInBuf[1], &pOutBuf[2], &FileLength); + pOutBuf[0] = LOADER_ERR_BYTE(Status); + pOutBuf[1] = 0; + + if (LOADER_ERR_BYTE(SUCCESS) != pOutBuf[0]) + { + memset(&pOutBuf[2], 0x00, 30); + } + *pLength = 32; + } + break; + + case FINDNEXTMODULE: + { + Status = pMapLoader->pFunc(FINDNEXTMODULE, pInBuf, &pOutBuf[2], &FileLength); + pOutBuf[0] = LOADER_ERR_BYTE(Status); + pOutBuf[1] = 0; + + if (LOADER_ERR_BYTE(SUCCESS) != pOutBuf[0]) + { + memset(&pOutBuf[2], 0x00, 30); + } + *pLength = 32; + } + break; + + case CLOSEMODHANDLE: + { + Status = pMapLoader->pFunc(CLOSEMODHANDLE, NULL, NULL, NULL); + pOutBuf[0] = LOADER_ERR_BYTE(Status); + pOutBuf[1] = 0; + *pLength = 2; + } + break; + + case IOMAPREAD: + { + ULONG ModuleId; + UWORD Length; + + ModuleId = pInBuf[1]; + ModuleId |= (ULONG)pInBuf[2] << 8; + ModuleId |= (ULONG)pInBuf[3] << 16; + ModuleId |= (ULONG)pInBuf[4] << 24; + + /* Transfer the Module id */ + pOutBuf[1] = pInBuf[1]; + pOutBuf[2] = pInBuf[2]; + pOutBuf[3] = pInBuf[3]; + pOutBuf[4] = pInBuf[4]; + + /* Transfer the offset into the iomap (pOutBuf[6] is intended...)*/ + pOutBuf[5] = pInBuf[5]; + pOutBuf[6] = pInBuf[6]; + + /* Get the read *pLength */ + FileLength = pInBuf[8]; + FileLength <<= 8; + FileLength |= pInBuf[7]; + + if (CmdBit & USB_CMD_READY) + { + + /* test for USB buffer overrun */ + if (FileLength > (SIZE_OF_USBBUF - 9)) + { + FileLength = SIZE_OF_USBBUF - 9; + } + } + else + { + + /* test for BT buffer overrun */ + if (FileLength > (SIZE_OF_BTBUF - 9)) + { + FileLength = SIZE_OF_BTBUF - 9; + } + } + + Length = FileLength; + *pLength = Length + 7; + Status = pMapLoader->pFunc(IOMAPREAD, (UBYTE *)&ModuleId, &pOutBuf[5], &FileLength); + + pOutBuf[0] = LOADER_ERR_BYTE(Status); + pOutBuf[5] = (UBYTE)FileLength; + pOutBuf[6] = (UBYTE)(FileLength >> 8); + + if (Length > FileLength) + { + Length -= FileLength; + memset(&(pOutBuf[FileLength + 7]), 0x00, Length); + } + } + break; + + case IOMAPWRITE: + { + ULONG ModuleId; + + pOutBuf[1] = pInBuf[1]; + pOutBuf[2] = pInBuf[2]; + pOutBuf[3] = pInBuf[3]; + pOutBuf[4] = pInBuf[4]; + + ModuleId = pInBuf[1]; + ModuleId |= (ULONG)pInBuf[2] << 8; + ModuleId |= (ULONG)pInBuf[3] << 16; + ModuleId |= (ULONG)pInBuf[4] << 24; + + FileLength = pInBuf[8]; + FileLength <<= 8; + FileLength |= pInBuf[7]; + + /* Place offset right before data */ + pInBuf[8] = pInBuf[6]; + pInBuf[7] = pInBuf[5]; + + Status = pMapLoader->pFunc(IOMAPWRITE, (UBYTE *)&ModuleId, &pInBuf[7], &FileLength); + + pOutBuf[0] = LOADER_ERR_BYTE(Status); + pOutBuf[5] = (UBYTE)FileLength; + pOutBuf[6] = (UBYTE)(FileLength >> 8); + + *pLength = 7; + } + break; + + case BOOTCMD: + { + + UBYTE Tmp; + + /* The boot command is only allowed by USB - as firmware download can ONLY */ + /* be send by USB */ + pOutBuf[0] = LOADER_ERR_BYTE(UNDEFINEDERROR); + memset(&(pOutBuf[1]), 0, 4); + *pLength = 5; + + if (CmdBit & USB_CMD_READY) + { + + Tmp = 0; + while((Tmp < (sizeof(BootString) - 1)) && (BootString[Tmp] == pInBuf[Tmp+1])) + { + Tmp++; + } + if (Tmp == (sizeof(BootString) - 1)) + { + + /* Yes valid boot sequence */ + pMapDisplay->Flags &= ~DISPLAY_ON; + pMapDisplay->Flags |= DISPLAY_REFRESH; + pMapIoCtrl->PowerOn = BOOT; + pOutBuf[0] = LOADER_ERR_BYTE(SUCCESS); + pOutBuf[1] = 'Y'; + pOutBuf[2] = 'e'; + pOutBuf[3] = 's'; + pOutBuf[4] = '\0'; + } + } + } + break; + + case SETBRICKNAME: + { + + UWORD RtnVal; + + *pLength = 1; + + /* Update the name in the BT device - reply for this command is send */ + /* before command is actually executed */ + if (SUCCESS == cCommReq(SETBTNAME, 0, 0, 0, &pInBuf[1], &RtnVal)) + { + pOutBuf[0] = LOADER_ERR_BYTE(SUCCESS); + cCommInsertBtName(IOMapComm.BrickData.Name, &pInBuf[1]); + pMapUi->Flags |= UI_REDRAW_STATUS; + } + else + { + pOutBuf[0] = LOADER_ERR_BYTE(BTBUSY); + } + } + break; + + case BTGETADR: + { + UBYTE Tmp; + UBYTE *pAdr; + + pAdr = (IOMapComm.BrickData.BdAddr); + for (Tmp = 0; Tmp < 7; Tmp++) + { + pOutBuf[Tmp + 1] = pAdr[Tmp]; + } + pOutBuf[0] = LOADER_ERR_BYTE(SUCCESS); + *pLength = 8; + } + break; + + case DEVICEINFO: + { + + pOutBuf[0] = LOADER_ERR_BYTE(SUCCESS); + + /* Brick name */ + memcpy(&(pOutBuf[1]), IOMapComm.BrickData.Name, 15); + + /* BT address */ + cCommCopyBdaddr(&(pOutBuf[16]), (IOMapComm.BrickData.BdAddr)); + + /* Link quality of the 4 possible connected devices */ + pOutBuf[23] = IOMapComm.BtConnectTable[0].LinkQuality; + pOutBuf[24] = IOMapComm.BtConnectTable[1].LinkQuality; + pOutBuf[25] = IOMapComm.BtConnectTable[2].LinkQuality; + pOutBuf[26] = IOMapComm.BtConnectTable[3].LinkQuality; + + /* Free user flash */ + memcpy(&(pOutBuf[27]), &(pMapLoader->FreeUserFlash), sizeof(pMapLoader->FreeUserFlash)); + + /* Set answer length */ + *pLength = 31; + } + break; + + case DELETEUSERFLASH: + { + Status = pMapLoader->pFunc(DELETEUSERFLASH, NULL, NULL, NULL); + pOutBuf[0] = LOADER_ERR_BYTE(SUCCESS); + *pLength = 1; + } + break; + + case POLLCMDLEN: + { + + pOutBuf[0] = LOADER_ERR_BYTE(SUCCESS); + pOutBuf[1] = pInBuf[1]; /* This is the Buf Number */ + if (0 == pInBuf[1]) + { + + /* USB poll buffer */ + pOutBuf[2] = ((IOMapComm.UsbPollBuf.InPtr - IOMapComm.UsbPollBuf.OutPtr) & (SIZE_OF_USBBUF - 1)); + } + else + { + + /* HI speed poll buffer */ + pOutBuf[2] = ((IOMapComm.HsInBuf.InPtr - IOMapComm.HsInBuf.OutPtr) & (SIZE_OF_HSBUF - 1)); + } + *pLength = 3; + } + break; + + case POLLCMD: + { + UBYTE Tmp; + UBYTE MaxBufData; + + pOutBuf[0] = LOADER_ERR_BYTE(SUCCESS); + pOutBuf[1] = pInBuf[1]; + *pLength = pInBuf[2]; + + if (CmdBit & USB_CMD_READY) + { + MaxBufData = (SIZE_OF_USBDATA - 5); /* Substract wrapping */ + } + else + { + MaxBufData = (SIZE_OF_BTBUF - 7); /* Substract wrapping + length bytes for BT*/ + } + + if (0x00 == pInBuf[1]) + { + + /* Data from USB poll buffer are requested */ + if (*pLength <= MaxBufData) + { + for (Tmp = 0; ((Tmp < (*pLength)) && (IOMapComm.UsbPollBuf.InPtr != IOMapComm.UsbPollBuf.OutPtr)); Tmp++) + { + pOutBuf[3 + Tmp] = IOMapComm.UsbPollBuf.Buf[IOMapComm.UsbPollBuf.OutPtr]; + IOMapComm.UsbPollBuf.OutPtr = ((IOMapComm.UsbPollBuf.OutPtr) + 1) % SIZE_OF_USBBUF; + } + pOutBuf[2] = Tmp; + + /* if end of buffer has been reached fill up with zeros */ + memset(&(pOutBuf[Tmp + 3]), 0x00, (*pLength - Tmp)); + } + else + { + + /* if more data requested than possible to return */ + pOutBuf[0] = LOADER_ERR_BYTE(UNDEFINEDERROR); + pOutBuf[1] = pInBuf[1]; /* This is buffer number */ + pOutBuf[2] = 0; /* no of bytes returned */ + *pLength = 0; + } + } + else + { + + /* Data from hi speed buffer are requested */ + if (*pLength <= MaxBufData) + { + for (Tmp = 0; ((Tmp < (*pLength)) && (IOMapComm.HsInBuf.InPtr != IOMapComm.HsInBuf.OutPtr)); Tmp++) + { + pOutBuf[3 + Tmp] = IOMapComm.HsInBuf.Buf[IOMapComm.HsInBuf.OutPtr]; + IOMapComm.HsInBuf.OutPtr = ((IOMapComm.HsInBuf.OutPtr) + 1) % SIZE_OF_USBBUF; + } + pOutBuf[2] = Tmp; + + /* if end of buffer has been reached fill up with zeros */ + memset(&(pOutBuf[Tmp + 3]), 0x00, (*pLength - Tmp)); + } + else + { + + /* if more data requested than possible to return */ + pOutBuf[0] = LOADER_ERR_BYTE(UNDEFINEDERROR); + pOutBuf[1] = pInBuf[1]; /* This is buffer number */ + pOutBuf[2] = 0; /* no of bytes returned */ + *pLength = 0; + } + } + (*pLength) += 3; /* Add 3 bytes for the status byte, length byte and Buf no */ + } + break; + + case BTFACTORYRESET: + { + UWORD RtnVal; + + if (CmdBit & USB_CMD_READY) + { + if (SUCCESS == cCommReq(FACTORYRESET, 0, 0, 0, NULL, &RtnVal)) + { + + /* Request success */ + pOutBuf[0] = LOADER_ERR_BYTE(SUCCESS); + } + else + { + + /* BT request error */ + pOutBuf[0] = LOADER_ERR_BYTE(UNDEFINEDERROR); + } + } + else + { + + /* Factory reset request cannot be done by bluetooth */ + pOutBuf[0] = LOADER_ERR_BYTE(UNDEFINEDERROR); + } + *pLength = 1; + } + break; + + default: + { + } + break; + } + return(Status); +} + + +UWORD cCommReceivedBtData(void) +{ + UWORD NumberOfBytes; + UWORD BytesToGo; + UWORD RtnVal; + + RtnVal = dBtReceivedData(&NumberOfBytes, &BytesToGo); + if (TRUE == RtnVal) + { + + /* Everything is fine go on */ + if (NumberOfBytes != 0) + { + + /* Copy the bytes into the IOMapBuffer */ + memcpy((IOMapComm.BtInBuf.Buf), (VarsComm.BtModuleInBuf.Buf), NumberOfBytes); + + if (VarsComm.BtState == BT_ARM_CMD_MODE) + { + + /* Call the BC4 command interpreter */ + cCommBtCmdInterpreter(); + IOMapComm.BtInBuf.InPtr = 0; + } + else + { + + /* ActiveUpdate has to be idle because BC4 can send stream data even if CMD */ + /* mode has been requested - dont try to interprete the data */ + /* VarsComm.CmdSwitchCnt != 0 if a transition to Cmd mode is in process */ + if ((VarsComm.BtState == BT_ARM_DATA_MODE) && (0 == VarsComm.CmdSwitchCnt)) + { + + /* Move the inptr ahead */ + IOMapComm.BtInBuf.InPtr = NumberOfBytes; + + /* using the outbuf inptr in order to get the number of bytes in the return answer at the right place*/ + IOMapComm.BtOutBuf.InPtr = NumberOfBytes; + + /* call the data stream interpreter */ + cCommInterprete(IOMapComm.BtInBuf.Buf, IOMapComm.BtOutBuf.Buf, &(IOMapComm.BtOutBuf.InPtr), (UBYTE) BT_CMD_READY, BytesToGo); + + /* if there is a reply to be send then send it */ + if (IOMapComm.BtOutBuf.InPtr) + { + dBtSendMsg(IOMapComm.BtOutBuf.Buf, IOMapComm.BtOutBuf.InPtr, IOMapComm.BtOutBuf.InPtr); + IOMapComm.BtOutBuf.InPtr = 0; + } + } + } + } + } + return(RtnVal); +} + +void cCommBtCmdInterpreter(void) +{ + + /* this function handles all bluecode commands that can be */ + /* initiated from the outside, meaning from other devices */ + if(cCommBtValidateCmd()) + { + switch (IOMapComm.BtInBuf.Buf[BT_CMD_BYTE]) + { + case MSG_REQUEST_PIN_CODE: + { + + /* Pass the pin request on to cCommReq it'l handle it */ + cCommReq(PINREQ, 0x00, 0x00, 0x00, NULL, &(VarsComm.RetVal)); + } + break; + + case MSG_REQUEST_CONNECTION: + { + + /* Connect request from the outside */ + cCommReq(CONNECTREQ, 0x00, 0x00, 0x00, NULL, &(VarsComm.RetVal)); + } + break; + + case MSG_LIST_RESULT: + { + switch (IOMapComm.BtInBuf.Buf[2]) + { + case LR_SUCCESS: + { + } + break; + case LR_ENTRY_REMOVED: + { + } + break; +/* + case LR_COULD_NOT_SAVE: + case LR_STORE_IS_FULL: + case LR_UNKOWN_ADDR: +*/ + default: + { + pMapUi->Error = (UBYTE)IOMapComm.BtInBuf.Buf[2]; + pMapUi->BluetoothState |= BT_ERROR_ATTENTION; + } + break; + } + } + break; + + case MSG_CLOSE_CONNECTION_RESULT: + { + UBYTE ConnNo; + + for (ConnNo = 0; ConnNo < SIZE_OF_BT_CONNECT_TABLE; ConnNo++) + { + if (IOMapComm.BtConnectTable[ConnNo].HandleNr == IOMapComm.BtInBuf.Buf[3]) + { + IOMapComm.BrickData.BtStateStatus &= ~(BT_CONNECTION_0_ENABLE<BluetoothState &= ~BT_STATE_CONNECTED; + } + pMapUi->Flags |= UI_REDRAW_STATUS; + } + break; + + case MSG_PORT_OPEN_RESULT: + { + if (IOMapComm.BtInBuf.Buf[2] == 1) + { + IOMapComm.BtConnectTable[0].HandleNr = IOMapComm.BtInBuf.Buf[3]; + IOMapComm.BrickData.BtStateStatus |= BT_BRICK_PORT_OPEN; + } + else + { + + /* There was an error setting up the OpenPort command in BC4 */ + IOMapComm.BtConnectTable[0].HandleNr = BLUETOOTH_HANDLE_UNDEFIEND; + IOMapComm.BrickData.BtStateStatus &= ~BT_BRICK_PORT_OPEN; + } + } + break; + + case MSG_CLOSE_PORT_RESULT: + { + if (IOMapComm.BtInBuf.Buf[2] == 1) + { + IOMapComm.BtConnectTable[0].HandleNr = BLUETOOTH_HANDLE_UNDEFIEND; + IOMapComm.BrickData.BtStateStatus &= ~BT_BRICK_PORT_OPEN; + } + } + break; + + case MSG_PIN_CODE_ACK: + { + pMapUi->BluetoothState &= ~BT_PIN_REQUEST; + } + break; + + case MSG_DISCOVERABLE_ACK: + { + if (VarsComm.BtCmdData.ParamOne == 1) + { + IOMapComm.BrickData.BtStateStatus |= BT_BRICK_VISIBILITY; + pMapUi->BluetoothState |= BT_STATE_VISIBLE; + } + else + { + IOMapComm.BrickData.BtStateStatus &= ~BT_BRICK_VISIBILITY; + pMapUi->BluetoothState &= ~BT_STATE_VISIBLE; + } + } + break; + case MSG_RESET_INDICATION: + { + if ((UPD_RESET != VarsComm.ActiveUpdate) && + (UPD_BRICKNAME != VarsComm.ActiveUpdate) && + (UPD_FACTORYRESET != VarsComm.ActiveUpdate)) + { + + /* Not intended reset indication - restart the bluecore */ + if (VarsComm.ActiveUpdate != UPD_IDLE) + { + + /* Something was ongoing send error message */ + *(VarsComm.pRetVal) = (UWORD)ERR_COMM_BUS_ERR; + *(VarsComm.pRetVal) |= 0x8000; + } + + SETBtStateIdle; + VarsComm.pRetVal = &(VarsComm.RetVal); + VarsComm.ActiveUpdate = UPD_RESET; + } + } + break; + } + } + else + { + /* Receive a message with wrong checkSum ! */ + } +} + +void cCommCpyToUpper(UBYTE *pDst, UBYTE *pSrc, UBYTE Length) +{ + UBYTE Tmp; + + for(Tmp = 0; Tmp < Length; Tmp++) + { + pDst[Tmp] =(UBYTE)toupper((UWORD)pSrc[Tmp]); + } + + /* The requried length has been copied - now fill with zeros */ + for(Tmp = Length; Tmp < (FILENAME_LENGTH + 1); Tmp++) + { + pDst[Tmp] = '\0'; + } +} + +void cCommCopyFileName(UBYTE *pDst, UBYTE *pSrc) +{ + UBYTE Tmp; + + for(Tmp = 0; Tmp < (FILENAME_LENGTH + 1); Tmp++, pDst++) + { + if ('\0' != *pSrc) + { + *pDst = *pSrc; + pSrc++; + } + else + { + *pDst = '\0'; + } + } +} + +void cCommSendHiSpeedData(void) +{ + VarsComm.HsModuleOutBuf.OutPtr = 0; + for (VarsComm.HsModuleOutBuf.InPtr = 0; VarsComm.HsModuleOutBuf.InPtr < IOMapComm.HsOutBuf.InPtr; VarsComm.HsModuleOutBuf.InPtr++) + { + VarsComm.HsModuleOutBuf.Buf[VarsComm.HsModuleOutBuf.InPtr] = IOMapComm.HsOutBuf.Buf[IOMapComm.HsOutBuf.OutPtr]; + IOMapComm.HsOutBuf.OutPtr++; + } + dHiSpeedSendData(VarsComm.HsModuleOutBuf.Buf, (VarsComm.HsModuleOutBuf.InPtr - VarsComm.HsModuleOutBuf.OutPtr)); +} + +void cCommReceivedHiSpeedData(void) +{ + UWORD NumberOfBytes; + UWORD Tmp; + + dHiSpeedReceivedData(&NumberOfBytes); + + if (NumberOfBytes != 0) + { + for (Tmp = 0; Tmp < NumberOfBytes; Tmp++) + { + IOMapComm.HsInBuf.Buf[IOMapComm.HsInBuf.InPtr] = VarsComm.HsModuleInBuf.Buf[Tmp]; + IOMapComm.HsInBuf.InPtr++; + if (IOMapComm.HsInBuf.InPtr > (SIZE_OF_HSBUF - 1)) + { + IOMapComm.HsInBuf.InPtr = 0; + } + VarsComm.HsModuleInBuf.Buf[Tmp] = 0; + } + + /* Now new data is available from the HIGH SPEED port ! */ + } +} + +UBYTE cCommBtValidateCmd(void) +{ + UWORD CheckSumTmp = 0; + UBYTE Tmp, CheckSumHigh, CheckSumLow; + + for (Tmp = 0; Tmp < (IOMapComm.BtInBuf.Buf[0] - 1);Tmp++) + { + CheckSumTmp += IOMapComm.BtInBuf.Buf[Tmp]; + } + CheckSumTmp = (UWORD) (1 + (0xFFFF - CheckSumTmp)); + CheckSumHigh = (UBYTE)((CheckSumTmp & 0xFF00)>>8); + CheckSumLow = (UBYTE)(CheckSumTmp & 0x00FF); + + if ((CheckSumHigh == IOMapComm.BtInBuf.Buf[IOMapComm.BtInBuf.Buf[0] - 1]) && (CheckSumLow == IOMapComm.BtInBuf.Buf[IOMapComm.BtInBuf.Buf[0]])) + { + return(TRUE); + } + else + { + return(FALSE); + } +} + +void cCommClearStreamStatus(void) +{ + IOMapComm.BtConnectTable[0].StreamStatus = 0; + IOMapComm.BtConnectTable[1].StreamStatus = 0; + IOMapComm.BtConnectTable[2].StreamStatus = 0; + IOMapComm.BtConnectTable[3].StreamStatus = 0; +} + +void cCommUpdateBt(void) +{ + UBYTE Tmp, Tmp2, Handle; + + Tmp = 0; + Tmp2 = 0; + + switch(VarsComm.ActiveUpdate) + { + case UPD_RESET: + { + + switch(VarsComm.UpdateState) + { + case 0: + { + /* Setup Reset sequence */ + pMapUi->BluetoothState = BT_STATE_OFF; + VarsComm.UpdateState = 1; + } + break; + + case 1: + { + cCommsBtReset(&(VarsComm.UpdateState)); + } + break; + + case 2: + { + (VarsComm.UpdateState)++; + dBtSendBtCmd((UBYTE)MSG_GET_LOCAL_ADDR, 0, 0, NULL, NULL, NULL, NULL); + } + break; + + case 3: + { + if (MSG_GET_LOCAL_ADDR_RESULT == IOMapComm.BtInBuf.Buf[BT_CMD_BYTE]) + { + cCommCopyBdaddr((IOMapComm.BrickData.BdAddr), &(IOMapComm.BtInBuf.Buf[BT_CMD_BYTE + 1])); + dUsbStoreBtAddress( &(IOMapComm.BtInBuf.Buf[BT_CMD_BYTE + 1])); + dBtSendBtCmd((UBYTE)MSG_GET_FRIENDLY_NAME, 0, 0, NULL, NULL, NULL, NULL); + VarsComm.BtAdrStatus = INITIALIZED; + (VarsComm.UpdateState)++; + } + } + break; + + case 4: + { + if (MSG_GET_FRIENDLY_NAME_RESULT == IOMapComm.BtInBuf.Buf[BT_CMD_BYTE]) + { + memcpy(IOMapComm.BrickData.Name, &(IOMapComm.BtInBuf.Buf[BT_CMD_BYTE + 1]), SIZE_OF_BRICK_NAME); + pMapUi->Flags |= UI_REDRAW_STATUS; + IOMapComm.BtDeviceCnt = 0; + IOMapComm.BtDeviceNameCnt = 0; + dBtSendBtCmd((UBYTE)MSG_DUMP_LIST, 0, 0, NULL, NULL, NULL, NULL); + (VarsComm.UpdateState)++; + } + } + break; + + case 5: + { + if (MSG_LIST_ITEM == IOMapComm.BtInBuf.Buf[BT_CMD_BYTE]) + { + cCommCopyBdaddr((IOMapComm.BtDeviceTable[IOMapComm.BtDeviceCnt].BdAddr), &(IOMapComm.BtInBuf.Buf[2])); + cCommInsertBtName(IOMapComm.BtDeviceTable[IOMapComm.BtDeviceCnt].Name, &(IOMapComm.BtInBuf.Buf[9])); + IOMapComm.BtDeviceTable[IOMapComm.BtDeviceCnt].DeviceStatus = BT_DEVICE_KNOWN; + + memcpy(IOMapComm.BtDeviceTable[IOMapComm.BtDeviceCnt].ClassOfDevice, &(IOMapComm.BtInBuf.Buf[9+SIZE_OF_BT_NAME]), sizeof(IOMapComm.BtDeviceTable[IOMapComm.BtDeviceCnt].ClassOfDevice)); + + IOMapComm.BtDeviceCnt++; + IOMapComm.BtDeviceNameCnt++; + } + + if (MSG_LIST_DUMP_STOPPED == IOMapComm.BtInBuf.Buf[BT_CMD_BYTE]) + { + dBtSendBtCmd((UBYTE)MSG_GET_VERSION, 0, 0, NULL, NULL, NULL, NULL); + (VarsComm.UpdateState)++; + } + IOMapComm.BtInBuf.Buf[BT_CMD_BYTE] = 0; + } + break; + + case 6: + { + if (MSG_GET_VERSION_RESULT == IOMapComm.BtInBuf.Buf[BT_CMD_BYTE]) + { + + IOMapComm.BrickData.BluecoreVersion[0] = IOMapComm.BtInBuf.Buf[3]; + IOMapComm.BrickData.BluecoreVersion[1] = IOMapComm.BtInBuf.Buf[2]; + + /* BtHwStatus indicates cold boot or user interaction */ + if (BT_DISABLE == IOMapComm.BrickData.BtHwStatus) + { + + /* This is from brick turning on */ + dBtSendBtCmd((UBYTE)MSG_GET_BRICK_STATUSBYTE, 0, 0, NULL, NULL, NULL, NULL); + } + else + { + + /* this is user interaction setting the brick on */ + dBtSendBtCmd((UBYTE)MSG_SET_BRICK_STATUSBYTE, BT_ENABLE, 0, NULL, NULL, NULL, NULL); + } + (VarsComm.UpdateState)++; + pMapUi->Flags |= UI_REDRAW_STATUS; + } + } + break; + + case 7: + { + if (MSG_GET_BRICK_STATUSBYTE_RESULT == IOMapComm.BtInBuf.Buf[BT_CMD_BYTE]) + { + IOMapComm.BrickData.TimeOutValue = IOMapComm.BtInBuf.Buf[BT_CMD_BYTE + 2]; + + /* Check for brick to be on or off */ + if (BT_ENABLE == IOMapComm.BtInBuf.Buf[BT_CMD_BYTE + 1]) + { + pMapUi->BluetoothState &= ~BT_STATE_OFF; + IOMapComm.BrickData.BtHwStatus = BT_ENABLE; + dBtSendBtCmd((UBYTE)MSG_GET_DISCOVERABLE, 0, 0, NULL, NULL, NULL, NULL); + (VarsComm.UpdateState)++; + } + else + { + SETBtOff; + IOMapComm.BrickData.BtHwStatus = BT_ENABLE; + SETBtStateIdle; + *(VarsComm.pRetVal) = SUCCESS; + } + } + if (MSG_SET_BRICK_STATUSBYTE_RESULT == IOMapComm.BtInBuf.Buf[BT_CMD_BYTE]) + { + + /* brick to be on*/ + pMapUi->BluetoothState &= ~BT_STATE_OFF; + IOMapComm.BrickData.BtHwStatus = BT_ENABLE; + dBtSendBtCmd((UBYTE)MSG_GET_DISCOVERABLE, 0, 0, NULL, NULL, NULL, NULL); + (VarsComm.UpdateState)++; + } + } + break; + + case 8: + { + if (MSG_GET_DISCOVERABLE_RESULT == IOMapComm.BtInBuf.Buf[BT_CMD_BYTE]) + { + if (IOMapComm.BtInBuf.Buf[2] & 0x01) + { + IOMapComm.BrickData.BtStateStatus |= BT_BRICK_VISIBILITY; + pMapUi->BluetoothState |= BT_STATE_VISIBLE; + } + else + { + IOMapComm.BrickData.BtStateStatus &= ~BT_BRICK_VISIBILITY; + pMapUi->BluetoothState &= ~BT_STATE_VISIBLE; + } + dBtSendBtCmd((UBYTE)MSG_OPEN_PORT, 0, 0, NULL, NULL, NULL, NULL); + (VarsComm.UpdateState)++; + } + } + break; + + case 9: + { + + if (MSG_PORT_OPEN_RESULT == IOMapComm.BtInBuf.Buf[BT_CMD_BYTE]) + { + if (IOMapComm.BtInBuf.Buf[BT_CMD_BYTE + 1] & 0x01) + { + IOMapComm.BrickData.BtStateStatus |= BT_BRICK_PORT_OPEN; + } + else + { + IOMapComm.BrickData.BtStateStatus &= ~BT_BRICK_PORT_OPEN; + } + + SETBtStateIdle; + *(VarsComm.pRetVal) = SUCCESS; + } + } + break; + } + } + break; + + case UPD_FACTORYRESET: + { + switch(VarsComm.UpdateState) + { + + case 0: + { + if (BT_STATE_OFF & (pMapUi->BluetoothState)) + { + + /* Bluetooth is off - now start it up */ + (VarsComm.UpdateState)++; + } + else + { + + /* BT is already on - continue */ + (VarsComm.UpdateState) += 2; + } + } + break; + case 1: + { + cCommsBtReset(&(VarsComm.UpdateState)); + } + break; + case 2: + { + cCommsSetCmdMode(&(VarsComm.UpdateState)); + } + break; + case 3: + { + cCommsDisconnectAll(&(VarsComm.UpdateState)); + } + break; + case 4: + { + + /* Now bc4 is in cmd mode now factory can be sent */ + /* Just leave the BC4 in cmd mode */ + dBtSendBtCmd((UBYTE)MSG_SET_FACTORY_SETTINGS, 0, 0, NULL, NULL, NULL, NULL); + (VarsComm.UpdateState)++; + } + break; + case 5: + { + if (MSG_SET_FACTORY_SETTINGS_ACK == IOMapComm.BtInBuf.Buf[BT_CMD_BYTE]) + { + SETBtStateIdle; + IOMapComm.BrickData.BtHwStatus = BT_DISABLE; /* Boot BT like cold boot*/ + VarsComm.ActiveUpdate = UPD_RESET; + } + } + break; + } + } + break; + + case UPD_BRICKNAME: + { + switch(VarsComm.UpdateState) + { + case 0: + { + + if (BT_STATE_OFF & (pMapUi->BluetoothState)) + { + + /* Bluetooth is off - now start it up */ + (VarsComm.UpdateState)++; + } + else + { + VarsComm.UpdateState = 2; + } + } + break; + + case 1: + { + cCommsBtReset(&(VarsComm.UpdateState)); + } + break; + + case 2: + { + VarsComm.BtUpdateDataConnectNr = 0; + if (BT_ARM_DATA_MODE == VarsComm.BtState) + { + for (Tmp = 0; Tmp < SIZE_OF_BT_CONNECT_TABLE; Tmp++) + { + if (IOMapComm.BtConnectTable[Tmp].StreamStatus) + { + VarsComm.BtUpdateDataConnectNr = Tmp | 0x80; + } + } + (VarsComm.UpdateState)++; + } + else + { + (VarsComm.UpdateState) += 2; + } + } + break; + + case 3: + { + cCommsSetCmdMode(&(VarsComm.UpdateState)); + } + break; + + case 4: + { + + /* Brick name has been updated prior to this */ + dBtSendBtCmd((UBYTE)MSG_SET_FRIENDLY_NAME, 0, 0, NULL, IOMapComm.BrickData.Name, NULL, NULL); + (VarsComm.UpdateState)++; + } + break; + + case 5: + { + if (MSG_SET_FRIENDLY_NAME_ACK == IOMapComm.BtInBuf.Buf[BT_CMD_BYTE]) + { + + /* Set name has been executed */ + if (VarsComm.BtUpdateDataConnectNr & 0x80) + { + dBtSendBtCmd((UBYTE)MSG_OPEN_STREAM, IOMapComm.BtConnectTable[(VarsComm.BtUpdateDataConnectNr & ~0x80)].HandleNr, + 0, NULL, NULL, NULL, NULL); + (VarsComm.UpdateState)++; + } + else + { + if (BT_STATE_OFF & (pMapUi->BluetoothState)) + { + SETBtOff; + } + SETBtStateIdle; + *(VarsComm.pRetVal) = SUCCESS; + } + pMapUi->Flags |= UI_REDRAW_STATUS; + } + } + break; + case 6: + { + if (VarsComm.BtBcPinLevel) + { + IOMapComm.BtConnectTable[(VarsComm.BtUpdateDataConnectNr & ~0x80)].StreamStatus = 1; + *(VarsComm.pRetVal) = SUCCESS; + SETBtDataState; + SETBtStateIdle; + } + } + break; + } + } + break; + + case UPD_REQCMDMODE: + { + switch(VarsComm.UpdateState) + { + case 0: + { + cCommsSetCmdMode(&(VarsComm.UpdateState)); + } + break; + case 1: + { + *(VarsComm.pRetVal) = SUCCESS; + SETBtStateIdle; + } + break; + } + } + break; + + case UPD_OPENSTREAM: + { + switch(VarsComm.UpdateState) + { + case 0: + { + cCommsOpenStream(&(VarsComm.UpdateState)); + } + break; + + case 1: + { + *(VarsComm.pRetVal) = SUCCESS; + SETBtStateIdle; + } + break; + } + } + break; + + case UPD_SENDFILE: + { + switch (VarsComm.UpdateState) + { + case 0: + { + cCommsOpenStream(&(VarsComm.UpdateState)); + } + break; + + case 1: + { + + /* Here we wait for the open stream to succeed*/ + if (IOMapComm.BtConnectTable[VarsComm.ExtTx.SlotNo].StreamStatus) + { + + /* Stream has been opened send the openwrite command */ + VarsComm.BtModuleOutBuf.Buf[0] = SYSTEM_CMD; + VarsComm.BtModuleOutBuf.Buf[1] = OPENWRITE; + memcpy((UBYTE*)&(VarsComm.BtModuleOutBuf.Buf[2]),(UBYTE*)VarsComm.ExtTx.FileName, FILENAME_LENGTH + 1); + memcpy((UBYTE*)&(VarsComm.BtModuleOutBuf.Buf[22]),(UBYTE*)&(VarsComm.ExtTx.RemFileSize), sizeof(VarsComm.ExtTx.RemFileSize)); + dBtSendMsg(VarsComm.BtModuleOutBuf.Buf, 26, 26); + + VarsComm.ExtTx.Timer = 0; + VarsComm.UpdateState = 2; + + } + else + { + if (VarsComm.ExtTx.Timer >= FILETXTOUT) + { + *(VarsComm.pRetVal) = FILETX_STREAMERROR; + VarsComm.UpdateState = 8; + } + else + { + (VarsComm.ExtTx.Timer)++; + } + } + } + break; + + case 2: + { + + if (4 == IOMapComm.BtInBuf.InPtr) + { + + /* Data has been received - examine the answer */ + if ((REPLY_CMD == IOMapComm.BtInBuf.Buf[0]) && (OPENWRITE == IOMapComm.BtInBuf.Buf[1])) + { + + /* OpenWrite answer */ + if (LOADER_ERR_BYTE(SUCCESS) == IOMapComm.BtInBuf.Buf[2]) + { + + /* save the handle from the other brick */ + VarsComm.ExtTx.DstHandle = IOMapComm.BtInBuf.Buf[3]; + VarsComm.UpdateState = 3; + IOMapComm.BtInBuf.InPtr = 0; + } + else + { + + /* Open write failiure - terminate file transfer */ + *(VarsComm.pRetVal) = IOMapComm.BtInBuf.Buf[2]; + VarsComm.UpdateState = 8; + } + } + } + + if (VarsComm.ExtTx.Timer >= FILETXTOUT) + { + *(VarsComm.pRetVal) = FILETX_TIMEOUT; + VarsComm.UpdateState = 8; + } + else + { + (VarsComm.ExtTx.Timer)++; + } + } + break; + + case 3: /*SENDWRITE:*/ + { + ULONG Length; + UWORD MsgSize; + + VarsComm.ExtTx.Timer = 0; + + if (VarsComm.ExtTx.RemFileSize > (MAX_BT_MSG_SIZE - 5)) + { + + /* need to use the maximum size available - approx 64K */ + VarsComm.ExtTx.RemMsgSize = (MAX_BT_MSG_SIZE - 5); + } + else + { + + /* Message can hold the remaining message */ + VarsComm.ExtTx.RemMsgSize = VarsComm.ExtTx.RemFileSize; + } + + if (VarsComm.ExtTx.RemMsgSize > (SIZE_OF_BTBUF - 5)) + { + Length = SIZE_OF_BTBUF - 5; + VarsComm.UpdateState = 4; + } + else + { + Length = VarsComm.ExtTx.RemMsgSize; + VarsComm.UpdateState = 5; + } + + Handle = (UBYTE)(VarsComm.ExtTx.SrcHandle); + pMapLoader->pFunc(READ, &Handle, &(VarsComm.BtModuleOutBuf.Buf[3]), &Length); + MsgSize = VarsComm.ExtTx.RemMsgSize + 3; + VarsComm.BtModuleOutBuf.Buf[0] = SYSTEM_CMD; + VarsComm.BtModuleOutBuf.Buf[1] = WRITE; + VarsComm.BtModuleOutBuf.Buf[2] = VarsComm.ExtTx.DstHandle; + dBtSendMsg(VarsComm.BtModuleOutBuf.Buf, Length + 3, MsgSize); + + VarsComm.ExtTx.RemMsgSize -= Length; + VarsComm.ExtTx.RemFileSize -= Length; + } + break; + + case 4: /* CONTINOUSWRITE:*/ + { + ULONG Length; + UWORD Status; + + if(dBtCheckForTxBuf()) + { + + /* do only send more data if buffer is empty */ + VarsComm.ExtTx.Timer = 0; + if (VarsComm.ExtTx.RemMsgSize >= SIZE_OF_BTBUF) + { + Length = SIZE_OF_BTBUF; + } + else + { + Length = VarsComm.ExtTx.RemMsgSize; + } + + VarsComm.ExtTx.RemMsgSize -= Length; + VarsComm.ExtTx.RemFileSize -= Length; + Handle = (UBYTE)(VarsComm.ExtTx.SrcHandle); + Status = pMapLoader->pFunc(READ, &Handle, &(VarsComm.BtModuleOutBuf.Buf[0]), &Length); + if (Status >= 0x8000) + { + Length = 0; + } + dBtSend(VarsComm.BtModuleOutBuf.Buf, Length); + if (!(VarsComm.ExtTx.RemMsgSize)) + { + + /* at this point due to large write command acknowledge is expected */ + VarsComm.UpdateState = 5; + VarsComm.ExtTx.Timer = 0; + IOMapComm.BtInBuf.InPtr = 0; + } + } + } + break; + + case 5: /* WRITEACK: */ + { + if (6 == IOMapComm.BtInBuf.InPtr) + { + if ((WRITE == IOMapComm.BtInBuf.Buf[1]) && + (REPLY_CMD == IOMapComm.BtInBuf.Buf[0]) && + (VarsComm.ExtTx.DstHandle == IOMapComm.BtInBuf.Buf[3])) + { + + /* Ok the the return reply is for me - was it ok? */ + if (LOADER_ERR_BYTE(SUCCESS) == IOMapComm.BtInBuf.Buf[2]) + { + + /* Ok send next write*/ + if (VarsComm.ExtTx.RemFileSize) + { + VarsComm.UpdateState = 3; + } + else + { + VarsComm.UpdateState = 6; + } + IOMapComm.BtInBuf.InPtr = 0; + } + } + } + + if (VarsComm.ExtTx.Timer >= FILETXTOUT) + { + *(VarsComm.pRetVal) = FILETX_TIMEOUT; + VarsComm.UpdateState = 8; + } + else + { + (VarsComm.ExtTx.Timer)++; + } + } + break; + + case 6: /*TERMINATESEND: */ + { + + /* Stream still open close the receiver handle */ + VarsComm.BtModuleOutBuf.Buf[0] = SYSTEM_CMD; + VarsComm.BtModuleOutBuf.Buf[1] = CLOSE; + VarsComm.BtModuleOutBuf.Buf[2] = VarsComm.ExtTx.DstHandle; + dBtSendMsg(VarsComm.BtModuleOutBuf.Buf, 3, 3); + + VarsComm.ExtTx.Timer = 0; + VarsComm.UpdateState = 7; + } + break; + case 7: /* TERMINATEACK:*/ + { + + if (4 == IOMapComm.BtInBuf.InPtr) + { + + if ((CLOSE == IOMapComm.BtInBuf.Buf[1]) && + (REPLY_CMD == IOMapComm.BtInBuf.Buf[0]) && + (VarsComm.ExtTx.DstHandle == IOMapComm.BtInBuf.Buf[3])) + { + if (LOADER_ERR_BYTE(SUCCESS) == IOMapComm.BtInBuf.Buf[2]) + { + *(VarsComm.pRetVal) = SUCCESS; + VarsComm.UpdateState = 8; + } + else + { + *(VarsComm.pRetVal) = FILETX_CLOSEERROR; + VarsComm.UpdateState = 8; + } + IOMapComm.BtInBuf.InPtr = 0; + } + } + + if (VarsComm.ExtTx.Timer >= FILETXTOUT) + { + *(VarsComm.pRetVal) = FILETX_TIMEOUT; + VarsComm.UpdateState = 8; + } + else + { + (VarsComm.ExtTx.Timer)++; + } + } + break; + case 8: + { + UBYTE Handle; + Handle = (UBYTE)(VarsComm.ExtTx.SrcHandle); + pMapLoader->pFunc(CLOSE, &Handle, NULL, NULL); + (VarsComm.UpdateState)++; + } + break; + case 9: + { + cCommsSetCmdMode(&(VarsComm.UpdateState)); + } + break; + case 10: + { + SETBtStateIdle; + } + break; + } + } + break; + + case UPD_EXTREAD: + { + switch (VarsComm.UpdateState) + { + case 0: + { + ULONG MsgLength; + UWORD Status; + + MsgLength = (SIZE_OF_BTBUF - 8); + Handle =(UBYTE)(VarsComm.ExtTx.SrcHandle); + Status = pMapLoader->pFunc(READ, &Handle, &(VarsComm.BtModuleOutBuf.Buf[6]), &MsgLength); + VarsComm.BtModuleOutBuf.Buf[0] = (UBYTE) (REPLY_CMD); + VarsComm.BtModuleOutBuf.Buf[1] = (UBYTE) (VarsComm.ExtTx.Cmd); + VarsComm.BtModuleOutBuf.Buf[2] = LOADER_ERR_BYTE(Status); + VarsComm.BtModuleOutBuf.Buf[3] = LOADER_HANDLE(Status); + VarsComm.BtModuleOutBuf.Buf[4] = (UBYTE)VarsComm.ExtTx.RemMsgSize; + VarsComm.BtModuleOutBuf.Buf[5] = (UBYTE)(VarsComm.ExtTx.RemMsgSize >> 8); + dBtSendMsg(VarsComm.BtModuleOutBuf.Buf, (UBYTE)(SIZE_OF_BTBUF - 2), (VarsComm.ExtTx.RemMsgSize + 6)); + + VarsComm.ExtTx.RemMsgSize -= (SIZE_OF_BTBUF - 8); + VarsComm.UpdateState = 1; + } + break; + + case 1: + { + + ULONG Length; + + if(dBtCheckForTxBuf()) + { + if (VarsComm.ExtTx.RemMsgSize > (SIZE_OF_BTBUF)) + { + + /* Send max number of bytes */ + VarsComm.ExtTx.RemMsgSize -= SIZE_OF_BTBUF; + Length = SIZE_OF_BTBUF; + } + else + { + + /* Buffer can hold the last part of the requested data */ + Length = VarsComm.ExtTx.RemMsgSize; + VarsComm.ExtTx.RemMsgSize = 0; + *(VarsComm.pRetVal) = SUCCESS; + SETBtStateIdle; + } + Handle =(UBYTE)(VarsComm.ExtTx.SrcHandle); + pMapLoader->pFunc(READ, &Handle, (VarsComm.BtModuleOutBuf.Buf), &Length); + dBtSend(VarsComm.BtModuleOutBuf.Buf, Length); + } + } + break; + } + } + break; + + case UPD_SEARCH: + { + switch (VarsComm.UpdateState) + { + case 0: + { + cCommsSetCmdMode(&(VarsComm.UpdateState)); + } + break; + case 1: + { + cCommsCloseConn0(&(VarsComm.UpdateState)); + } + break; + case 2: + { + + /* Now ready for the actual search */ + for (Tmp = 0; Tmp < SIZE_OF_BT_DEVICE_TABLE; Tmp++) + { + if ((IOMapComm.BtDeviceTable[Tmp].DeviceStatus) & BT_DEVICE_KNOWN) + { + (IOMapComm.BtDeviceTable[Tmp].DeviceStatus) = (BT_DEVICE_AWAY | BT_DEVICE_KNOWN); + } + else + { + IOMapComm.BtDeviceTable[Tmp].DeviceStatus = BT_DEVICE_EMPTY; + } + } + dBtSendBtCmd((UBYTE)MSG_BEGIN_INQUIRY, (UBYTE)BT_DEFAULT_INQUIRY_MAX, + BT_DEFAULT_INQUIRY_TIMEOUT_LO, NULL, NULL, NULL, NULL); + (VarsComm.UpdateState)++; + } + break; + case 3: + { + + /* this is the stop search flag */ + /* - meaning that the search should be stopped */ + if (1 == VarsComm.BtCmdData.ParamOne) + { + dBtSendBtCmd((UBYTE)MSG_CANCEL_INQUIRY, 0, 0, NULL, NULL, NULL, NULL); + (VarsComm.UpdateState) = 7; + } + else + { + + + /* when inquiry is running there is 2 alloable return answers */ + /* either inquiry result or inquiry stopped */ + if (MSG_INQUIRY_RESULT == IOMapComm.BtInBuf.Buf[BT_CMD_BYTE]) + { + + dBtResetTimeOut(); /* reset the cmd timeout */ + Tmp = cCommInsertDevice(&(IOMapComm.BtInBuf.Buf[2]), &(IOMapComm.BtInBuf.Buf[9]), + &(IOMapComm.BtInBuf.Buf[25]), (UBYTE) BT_DEVICE_UNKNOWN, &Tmp2); + if (SIZE_OF_BT_DEVICE_TABLE > Tmp) + { + + /* Remember to check for already existing entry ....*/ + if (DEVICE_VERIFIED != Tmp2) + { + (IOMapComm.BtDeviceTable[Tmp].DeviceStatus) &= ~BT_DEVICE_AWAY; + IOMapComm.BtDeviceCnt++; + } + } + else + { + + /* We will send a stop inquiry cmd as the table is full! */ + dBtSendBtCmd((UBYTE)MSG_CANCEL_INQUIRY, 0, 0, NULL, NULL, NULL, NULL); + } + } + + if (MSG_INQUIRY_STOPPED == IOMapComm.BtInBuf.Buf[BT_CMD_BYTE]) + { + VarsComm.BtDeviceIndex = 0; /* Start looking for found devices at index 0 */ + VarsComm.LookUpCnt = 0; /* how many times should we try to ask for the name */ + (VarsComm.UpdateState)++; + } + } + IOMapComm.BtInBuf.Buf[BT_CMD_BYTE] = 0; + } + break; + + case 4: + { + + /* this is the stop search flag */ + /* - meaning that the search should be stopped */ + if (1 == VarsComm.BtCmdData.ParamOne) + { + (VarsComm.UpdateState) = 8; + } + else + { + + /* Needs to run through the hole list as found devices can be placed anywhere */ + /* in the table */ + for (Tmp = (VarsComm.BtDeviceIndex); Tmp < SIZE_OF_BT_DEVICE_TABLE; Tmp++) + { + if ((BT_DEVICE_UNKNOWN == IOMapComm.BtDeviceTable[Tmp].DeviceStatus) || + (BT_DEVICE_KNOWN == IOMapComm.BtDeviceTable[Tmp].DeviceStatus)) + { + VarsComm.BtDeviceIndex = (Tmp + 1); + (VarsComm.UpdateState)++; + dBtSendBtCmd((UBYTE)MSG_LOOKUP_NAME, 0, 0, (IOMapComm.BtDeviceTable[Tmp].BdAddr), + NULL, NULL, NULL); + break; + } + } + if (SIZE_OF_BT_DEVICE_TABLE == Tmp) + { + (VarsComm.LookUpCnt)++; + if (((VarsComm.LookUpCnt) < LOOKUPNO) && ((IOMapComm.BtDeviceNameCnt) != (IOMapComm.BtDeviceCnt))) + { + VarsComm.BtDeviceIndex = 0; + } + else + { + + // all done + SETBtStateIdle; + *(VarsComm.pRetVal) = SUCCESS; + } + } + } + } + break; + + case 5: + { + + if (MSG_LOOKUP_NAME_RESULT == IOMapComm.BtInBuf.Buf[BT_CMD_BYTE]) + { + Tmp2 = FALSE; /* Tmp2 used to indicate name change */ + (IOMapComm.BtDeviceNameCnt)++; + + /* Try look the most obvious place in the device table */ + Tmp = VarsComm.BtDeviceIndex - 1; + if (TRUE != cCommCheckBdaddr((IOMapComm.BtDeviceTable[Tmp].BdAddr), &(IOMapComm.BtInBuf.Buf[2]))) + { + + /* there was no match - now look the complete table */ + for (Tmp = 0; Tmp < SIZE_OF_BT_DEVICE_TABLE; Tmp++) + { + if (TRUE == cCommCheckBdaddr((IOMapComm.BtDeviceTable[Tmp].BdAddr), &(IOMapComm.BtInBuf.Buf[2]))) + { + break; + } + } + } + + if (Tmp < SIZE_OF_BT_DEVICE_TABLE) + { + + /* Valid index with matching device adress found */ + if (0 == IOMapComm.BtInBuf.Buf[9]) + { + + if (0 == IOMapComm.BtDeviceTable[Tmp].Name[0]) + { + + /* No valid name recvd and no valid name in table -> insert "No Name" */ + cCommInsertBtName(IOMapComm.BtDeviceTable[Tmp].Name, (UBYTE*)NoName); + } + } + else + { + + /* Valid Name - check it against the one allready stored in the device table */ + /* if it differs then update */ + if (0 != strcmp((char const*)IOMapComm.BtDeviceTable[Tmp].Name, (char const*)&(IOMapComm.BtInBuf.Buf[9]))) + { + cCommInsertBtName(IOMapComm.BtDeviceTable[Tmp].Name, &(IOMapComm.BtInBuf.Buf[9])); + Tmp2 = TRUE; + } + } + if ((BT_DEVICE_KNOWN == (IOMapComm.BtDeviceTable[Tmp].DeviceStatus)) && (TRUE == Tmp2)) + { + dBtSendBtCmd((UBYTE)MSG_ADD_DEVICE, 0, 0, (IOMapComm.BtDeviceTable[Tmp].BdAddr), + (IOMapComm.BtDeviceTable[Tmp].Name), (IOMapComm.BtDeviceTable[Tmp].ClassOfDevice), NULL); + (VarsComm.UpdateState)++; + } + else + { + (VarsComm.UpdateState)--; + } + } + + /* Update devicestatus (name found) so it doesn't look up the name anymore */ + IOMapComm.BtDeviceTable[Tmp].DeviceStatus |= BT_DEVICE_NAME; + } + + if (MSG_LOOKUP_NAME_FAILURE == IOMapComm.BtInBuf.Buf[BT_CMD_BYTE]) + { + + if ((LOOKUPNO - 1) == VarsComm.LookUpCnt) + { + + /* This is the last time we ask this device -> we will not get a valid name */ + /* Try look the most obvious place in the device table */ + Tmp = VarsComm.BtDeviceIndex - 1; + if (TRUE != cCommCheckBdaddr((IOMapComm.BtDeviceTable[Tmp].BdAddr), &(IOMapComm.BtInBuf.Buf[2]))) + { + for (Tmp = 0; Tmp < SIZE_OF_BT_DEVICE_TABLE; Tmp++) + { + if (TRUE == cCommCheckBdaddr((IOMapComm.BtDeviceTable[Tmp].BdAddr), &(IOMapComm.BtInBuf.Buf[2]))) + { + break; + } + } + if ((Tmp < SIZE_OF_BT_DEVICE_TABLE) && (BT_DEVICE_UNKNOWN == (IOMapComm.BtDeviceTable[Tmp].DeviceStatus))) + { + cCommInsertBtName(IOMapComm.BtDeviceTable[Tmp].Name, (UBYTE*) NoName); + } + } + (IOMapComm.BtDeviceNameCnt)++; + } + (VarsComm.UpdateState)--; + } + IOMapComm.BtInBuf.Buf[BT_CMD_BYTE] = 0; + } + break; + + case 6: + { + + /* Waiting for reply on add device command - List result */ + if (MSG_LIST_RESULT == IOMapComm.BtInBuf.Buf[BT_CMD_BYTE]) + { + if (LR_SUCCESS == IOMapComm.BtInBuf.Buf[2]) + { + + /* Return and go through the list*/ + (VarsComm.UpdateState) -= 2; + } + else + { + pMapUi->Error = (UBYTE)IOMapComm.BtInBuf.Buf[2]; + pMapUi->BluetoothState |= BT_ERROR_ATTENTION; + } + } + } + break; + case 7: + { + + /* here because search has been stopped by user during inquiry */ + if (MSG_INQUIRY_STOPPED == IOMapComm.BtInBuf.Buf[BT_CMD_BYTE]) + { + + /* table should be cleared as no names hes been inquired */ + for (Tmp = 0; Tmp < SIZE_OF_BT_DEVICE_TABLE; Tmp++) + { + if ((IOMapComm.BtDeviceTable[Tmp].DeviceStatus) & BT_DEVICE_KNOWN) + { + (IOMapComm.BtDeviceTable[Tmp].DeviceStatus) = BT_DEVICE_KNOWN; + } + else + { + (IOMapComm.BtDeviceTable[Tmp].DeviceStatus) = BT_DEVICE_EMPTY; + } + IOMapComm.BtDeviceCnt = 0; + IOMapComm.BtDeviceNameCnt = 0; + } + SETBtStateIdle; + *(VarsComm.pRetVal) = SUCCESS; + } + } + break; + case 8: + { + for (Tmp = (VarsComm.BtDeviceIndex); Tmp < SIZE_OF_BT_DEVICE_TABLE; Tmp++) + { + if (BT_DEVICE_UNKNOWN == IOMapComm.BtDeviceTable[Tmp].DeviceStatus) + { + IOMapComm.BtDeviceTable[Tmp].DeviceStatus = BT_DEVICE_EMPTY; + } + } + SETBtStateIdle; + *(VarsComm.pRetVal) = SUCCESS; + } + break; + } + } + break; + + case UPD_CONNECTREQ: + { + switch (VarsComm.UpdateState) + { + + case 0: + { + dBtSendBtCmd((UBYTE)MSG_ACCEPT_CONNECTION, 1, 0, NULL, NULL, NULL, NULL); + cCommCopyBdaddr((IOMapComm.BtConnectTable[0].BdAddr), &(IOMapComm.BtInBuf.Buf[BT_CMD_BYTE + 1])); + (VarsComm.UpdateState)++; + } + break; + + case 1: + { + if (MSG_CONNECT_RESULT == IOMapComm.BtInBuf.Buf[BT_CMD_BYTE]) + { + + /* Check for successfull connection */ + if (1 == IOMapComm.BtInBuf.Buf[BT_CMD_BYTE + 1]) + { + + /* Save the handle number and look up the name of the master */ + IOMapComm.BtConnectTable[0].HandleNr = IOMapComm.BtInBuf.Buf[BT_CMD_BYTE + 2]; + pMapUi->BluetoothState |= BT_STATE_CONNECTED; + dBtSendBtCmd((UBYTE)MSG_LOOKUP_NAME, 0, 0, (IOMapComm.BtConnectTable[0].BdAddr), NULL, NULL, NULL); + (VarsComm.UpdateState)++; + } + else + { + + /* Unsuccessful connection */ + SETBtStateIdle; + *(VarsComm.pRetVal) = BTCONNECTFAIL; + } + } + } + break; + + case 2: + { + + /* a close connection can happen during connection sequence - if this */ + /* occurs for connection 0 then abort the rest of the sequence - OxFF */ + /* is unused handle */ + if ((MSG_CLOSE_CONNECTION_RESULT == IOMapComm.BtInBuf.Buf[BT_CMD_BYTE]) && + (0xFF == IOMapComm.BtConnectTable[0].HandleNr)) + { + SETBtStateIdle; + *(VarsComm.pRetVal) = BTCONNECTFAIL; + } + else + { + + if (MSG_LOOKUP_NAME_RESULT == IOMapComm.BtInBuf.Buf[BT_CMD_BYTE]) + { + Tmp = cCommInsertDevice(&(IOMapComm.BtInBuf.Buf[2]), &(IOMapComm.BtInBuf.Buf[9]), + &(IOMapComm.BtInBuf.Buf[25]), (UBYTE) BT_DEVICE_KNOWN, &Tmp2); + + if (SIZE_OF_BT_DEVICE_TABLE > Tmp) + { + + /* entry has been added or is allready existing in the devicetable */ + cCommInsertBtName(IOMapComm.BtConnectTable[0].Name, &(IOMapComm.BtInBuf.Buf[9])); + cCommCopyBdaddr((IOMapComm.BtConnectTable[0].BdAddr), &(IOMapComm.BtInBuf.Buf[2])); + memcpy(IOMapComm.BtConnectTable[0].ClassOfDevice, + IOMapComm.BtDeviceTable[Tmp].ClassOfDevice, SIZE_OF_CLASS_OF_DEVICE); + dBtSendBtCmd((UBYTE)MSG_ADD_DEVICE, 0, 0, (IOMapComm.BtDeviceTable[Tmp].BdAddr), + (IOMapComm.BtDeviceTable[Tmp].Name), (IOMapComm.BtDeviceTable[Tmp].ClassOfDevice), NULL); + (VarsComm.UpdateState)++; + } + else + { + + /* no room in the devicetable -> reject the request. Param2 is index in connect table */ + dBtSendBtCmd((UBYTE)MSG_CLOSE_CONNECTION, IOMapComm.BtConnectTable[0].HandleNr, + 0, NULL, NULL, NULL, NULL); + SETBtStateIdle; + *(VarsComm.pRetVal) = BTCONNECTFAIL; + } + } + + if (MSG_LOOKUP_NAME_FAILURE == IOMapComm.BtInBuf.Buf[BT_CMD_BYTE]) + { + + /* not able to get the name - disconnect*/ + dBtSendBtCmd((UBYTE)MSG_CLOSE_CONNECTION, IOMapComm.BtConnectTable[0].HandleNr, + 0, NULL, NULL, NULL, NULL); + *(VarsComm.pRetVal) = BTCONNECTFAIL; + SETBtStateIdle; + } + } + } + break; + + case 3: + { + if (MSG_LIST_RESULT == IOMapComm.BtInBuf.Buf[BT_CMD_BYTE]) + { + if (LR_SUCCESS == IOMapComm.BtInBuf.Buf[2]) + { + + /* All success - open stream (Data mode) */ + dBtSendBtCmd((UBYTE)MSG_OPEN_STREAM, IOMapComm.BtConnectTable[0].HandleNr, 0, NULL, NULL, NULL, NULL); + (VarsComm.UpdateState)++; + } + else + { + + /* no room in the BC4 -> reject the request */ + dBtSendBtCmd((UBYTE)MSG_CLOSE_CONNECTION, IOMapComm.BtConnectTable[0].HandleNr, + 0, NULL, NULL, NULL, NULL); + *(VarsComm.pRetVal) = BTCONNECTFAIL; + SETBtStateIdle; + } + } + } + break; + + case 4: + { + if (VarsComm.BtBcPinLevel) + { + IOMapComm.BtConnectTable[0].StreamStatus = 1; + *(VarsComm.pRetVal) = SUCCESS; + SETBtDataState; + SETBtStateIdle; + } + } + break; + } + } + break; + + case UPD_CONNECT: + { + switch (VarsComm.UpdateState) + { + case 0: + { + cCommsSetCmdMode(&(VarsComm.UpdateState)); + } + break; + case 1: + { + cCommsCloseConn0(&(VarsComm.UpdateState)); + } + break; + case 2: + { + dBtSendBtCmd((UBYTE)MSG_CONNECT, 0, 0, + IOMapComm.BtDeviceTable[VarsComm.BtCmdData.ParamOne].BdAddr, NULL, NULL, NULL); + (VarsComm.UpdateState)++; + } + break; + + case 3: + { + if (MSG_CONNECT_RESULT == IOMapComm.BtInBuf.Buf[BT_CMD_BYTE]) + { + if (IOMapComm.BtInBuf.Buf[2] == 1) + { + + IOMapComm.BtConnectTable[VarsComm.BtCmdData.ParamTwo].HandleNr = IOMapComm.BtInBuf.Buf[3]; + pMapUi->BluetoothState |= BT_STATE_CONNECTED; + + //Now we need to copy the data to the connectiontable + memcpy((IOMapComm.BtConnectTable[VarsComm.BtCmdData.ParamTwo].BdAddr), (IOMapComm.BtDeviceTable[VarsComm.BtCmdData.ParamOne].BdAddr), SIZE_OF_BDADDR); + cCommInsertBtName(IOMapComm.BtConnectTable[VarsComm.BtCmdData.ParamTwo].Name, IOMapComm.BtDeviceTable[VarsComm.BtCmdData.ParamOne].Name); + memcpy((IOMapComm.BtConnectTable[VarsComm.BtCmdData.ParamTwo].ClassOfDevice), + (IOMapComm.BtDeviceTable[VarsComm.BtCmdData.ParamOne].ClassOfDevice), SIZE_OF_CLASS_OF_DEVICE); + IOMapComm.BtDeviceTable[VarsComm.BtCmdData.ParamOne].DeviceStatus = BT_DEVICE_KNOWN; + + if (VarsComm.BtCmdData.ParamTwo == 1) + { + IOMapComm.BrickData.BtStateStatus |= BT_CONNECTION_1_ENABLE; + } + else + { + if (VarsComm.BtCmdData.ParamTwo == 2) + { + IOMapComm.BrickData.BtStateStatus |= BT_CONNECTION_2_ENABLE; + } + else + { + if (VarsComm.BtCmdData.ParamTwo == 3) + { + IOMapComm.BrickData.BtStateStatus |= BT_CONNECTION_3_ENABLE; + } + } + } + dBtSendBtCmd((UBYTE)MSG_ADD_DEVICE, 0, 0, (IOMapComm.BtConnectTable[VarsComm.BtCmdData.ParamTwo].BdAddr), + (IOMapComm.BtConnectTable[VarsComm.BtCmdData.ParamTwo].Name), + (IOMapComm.BtDeviceTable[VarsComm.BtCmdData.ParamOne].ClassOfDevice), NULL); + (VarsComm.UpdateState)+=3; /* skip the pin code part */ + } + else + { + + /* Connect request denied */ + *(VarsComm.pRetVal) = BTCONNECTFAIL; + SETBtStateIdle; + } + } + if (MSG_REQUEST_PIN_CODE == IOMapComm.BtInBuf.Buf[BT_CMD_BYTE]) + { + *(VarsComm.pRetVal) = REQPIN; + VarsComm.pValidPinCode = NULL; + (VarsComm.UpdateState)++; + } + } + break; + + case 4: + { + if (NULL != VarsComm.pValidPinCode) + { + + memcpy((IOMapComm.BtConnectTable[VarsComm.BtCmdData.ParamTwo].PinCode), + VarsComm.pValidPinCode, SIZE_OF_BT_PINCODE); + + dBtSendBtCmd((UBYTE)MSG_PIN_CODE, 0, 0, IOMapComm.BtDeviceTable[VarsComm.BtCmdData.ParamOne].BdAddr, + NULL, NULL, (VarsComm.pValidPinCode)); + (VarsComm.UpdateState)++; + } + if (MSG_CONNECT_RESULT == IOMapComm.BtInBuf.Buf[BT_CMD_BYTE]) + { + + /* if no pin code has been accepted then timeout indicated */ + /* by connect failiure - it can only be failiure here */ + *(VarsComm.pRetVal) = BTCONNECTFAIL; + SETBtStateIdle; + } + } + break; + + case 5: + { + + if (MSG_CONNECT_RESULT == IOMapComm.BtInBuf.Buf[BT_CMD_BYTE]) + { + + /* Connect failiure can happen at any time */ + *(VarsComm.pRetVal) = BTCONNECTFAIL; + SETBtStateIdle; + } + if (MSG_PIN_CODE_ACK == IOMapComm.BtInBuf.Buf[BT_CMD_BYTE]) + { + + /* return back and wait for connect ack */ + (VarsComm.UpdateState) = 3; + } + } + break; + case 6: + { + if (MSG_LIST_RESULT == IOMapComm.BtInBuf.Buf[BT_CMD_BYTE]) + { + *(VarsComm.pRetVal) = SUCCESS; + SETBtStateIdle; + } + } + break; + } + } + break; + + case UPD_DISCONNECT: + { + switch (VarsComm.UpdateState) + { + case 0: + { + cCommsSetCmdMode(&(VarsComm.UpdateState)); + } + break; + + case 1: + { + if (BLUETOOTH_HANDLE_UNDEFIEND != IOMapComm.BtConnectTable[VarsComm.BtCmdData.ParamOne].HandleNr) + { + VarsComm.BtCmdData.ParamOne = IOMapComm.BtConnectTable[VarsComm.BtCmdData.ParamOne].HandleNr; + dBtSendBtCmd((UBYTE)MSG_CLOSE_CONNECTION, VarsComm.BtCmdData.ParamOne, 0, NULL, NULL, NULL, NULL); + (VarsComm.UpdateState)++; + } + else + { + *(VarsComm.pRetVal) = SUCCESS; + SETBtStateIdle; + } + } + break; + + case 2: + { + + /* look for right message and right handle */ + if ((MSG_CLOSE_CONNECTION_RESULT == IOMapComm.BtInBuf.Buf[BT_CMD_BYTE]) && + (VarsComm.BtCmdData.ParamOne == IOMapComm.BtInBuf.Buf[BT_CMD_BYTE + 2])) + { + *(VarsComm.pRetVal) = SUCCESS; + SETBtStateIdle; + } + } + break; + } + } + break; + case UPD_DISCONNECTALL: + { + switch (VarsComm.UpdateState) + { + case 0: + { + cCommsSetCmdMode(&(VarsComm.UpdateState)); + } + break; + case 1: + { + cCommsDisconnectAll(&(VarsComm.UpdateState)); + } + break; + case 2: + { + *(VarsComm.pRetVal) = SUCCESS; + SETBtStateIdle; + } + break; + } + } + break; + case UPD_REMOVEDEVICE: + { + switch (VarsComm.UpdateState) + { + case 0: + { + cCommsSetCmdMode(&(VarsComm.UpdateState)); + } + break; + case 1: + { + cCommsCloseConn0(&(VarsComm.UpdateState)); + } + break; + case 2: + { + dBtSendBtCmd((UBYTE)MSG_REMOVE_DEVICE, 0, 0, + IOMapComm.BtDeviceTable[VarsComm.BtCmdData.ParamOne].BdAddr, NULL, NULL, NULL); + IOMapComm.BtDeviceTable[VarsComm.BtCmdData.ParamOne].DeviceStatus = BT_DEVICE_EMPTY; + (VarsComm.UpdateState)++; + } + break; + case 3: + { + if (MSG_LIST_RESULT == IOMapComm.BtInBuf.Buf[BT_CMD_BYTE]) + { + *(VarsComm.pRetVal) = SUCCESS; + SETBtStateIdle; + } + } + break; + } + } + break; + + case UPD_PINREQ: + { + + /* This is pincode request from the outside - always conn 0*/ + switch (VarsComm.UpdateState) + { + case 0: + { + if (NULL != VarsComm.pValidPinCode) + { + memcpy((IOMapComm.BtConnectTable[0].PinCode), + VarsComm.pValidPinCode, SIZE_OF_BT_PINCODE); + dBtSendBtCmd((UBYTE)MSG_PIN_CODE, 0, 0, (IOMapComm.BtConnectTable[0].BdAddr), + NULL, NULL, (VarsComm.pValidPinCode)); + (VarsComm.UpdateState)++; + } + } + break; + case 1: + { + if (MSG_PIN_CODE_ACK == IOMapComm.BtInBuf.Buf[BT_CMD_BYTE]) + { + SETBtStateIdle; + } + } + break; + } + } + break; + + case UPD_VISIBILITY: + { + switch (VarsComm.UpdateState) + { + case 0: + { + cCommsSetCmdMode(&(VarsComm.UpdateState)); + } + break; + case 1: + { + cCommsCloseConn0(&(VarsComm.UpdateState)); + } + break; + case 2: + { + dBtSendBtCmd((UBYTE)MSG_SET_DISCOVERABLE, VarsComm.BtCmdData.ParamOne, 0, NULL, NULL, NULL, NULL); + (VarsComm.UpdateState)++; + } + break; + case 3: + { + if (MSG_DISCOVERABLE_ACK == IOMapComm.BtInBuf.Buf[BT_CMD_BYTE]) + { + if (VarsComm.BtCmdData.ParamOne == 1) + { + IOMapComm.BrickData.BtStateStatus |= BT_BRICK_VISIBILITY; + pMapUi->BluetoothState |= BT_STATE_VISIBLE; + } + else + { + IOMapComm.BrickData.BtStateStatus &= ~BT_BRICK_VISIBILITY; + pMapUi->BluetoothState &= ~BT_STATE_VISIBLE; + } + *(VarsComm.pRetVal) = SUCCESS; + SETBtStateIdle; + } + } + break; + } + } + break; + + case UPD_OFF: + { + switch (VarsComm.UpdateState) + { + case 0: + { + cCommsSetCmdMode(&(VarsComm.UpdateState)); + } + break; + case 1: + { + cCommsDisconnectAll(&(VarsComm.UpdateState)); + } + break; + case 2: + { + dBtSendBtCmd((UBYTE)MSG_SET_BRICK_STATUSBYTE, BT_DISABLE, 0, NULL, NULL, NULL, NULL); + (VarsComm.UpdateState)++; + } + break; + case 3: + { + if (MSG_SET_BRICK_STATUSBYTE_RESULT == IOMapComm.BtInBuf.Buf[BT_CMD_BYTE]) + { + if (IOMapComm.BtInBuf.Buf[2] == LR_SUCCESS) + { + SETBtOff; + pMapUi->BluetoothState = BT_STATE_OFF; + pMapUi->Flags |= UI_REDRAW_STATUS; + } + *(VarsComm.pRetVal) = SUCCESS; + SETBtStateIdle; + } + } + break; + } + } + break; + case UPD_SENDDATA: + { + switch (VarsComm.UpdateState) + { + case 0: + { + if (1 == IOMapComm.BtConnectTable[VarsComm.BtCmdData.ParamTwo].StreamStatus) + { + + /* Stream is allready open for the requested channel */ + (VarsComm.UpdateState) += 2; + } + else + { + + /* Stream not open - try open it*/ + (VarsComm.UpdateState)++; + } + } + break; + case 1: + { + cCommsOpenStream(&(VarsComm.UpdateState)); + } + break; + case 2: + { + + /* Stream is now opened now send the data */ + IOMapComm.BtInBuf.Buf[0] = 0; + dBtSendMsg((VarsComm.BtModuleOutBuf.Buf), VarsComm.BtCmdData.ParamOne, (UWORD)(VarsComm.BtCmdData.ParamOne)); + (VarsComm.UpdateState)++; + } + break; + case 3: + { + if(dBtCheckForTxBuf()) + { + if (VarsComm.BtCmdData.ParamThree) + { + VarsComm.ExtTx.Timer = 0; + (VarsComm.UpdateState)++; + } + else + { + *(VarsComm.pRetVal) = SUCCESS; + SETBtStateIdle; + } + } + } + break; + case 4: + { + if (0x02 == IOMapComm.BtInBuf.Buf[0]) + { + + /* a reply has been received now release the send sequence */ + *(VarsComm.pRetVal) = SUCCESS; + SETBtStateIdle; + } + else + { + if (++VarsComm.ExtTx.Timer > BTSTREAMTOUT) + { + *(VarsComm.pRetVal) = BTTIMEOUT; + SETBtStateIdle; + } + } + } + break; + } + } + break; + default: + { + + /* This is idle */ + VarsComm.UpdateState = 0; + } + break; + } +} + +UWORD cCommCopyBdaddr(UBYTE *pDst, UBYTE *pSrc) +{ + memcpy(pDst, pSrc, SIZE_OF_BDADDR); + return((UWORD) SIZE_OF_BDADDR); +} + +UWORD cCommCheckBdaddr(UBYTE *pAdr, UBYTE *pSrc) +{ + UWORD RetVal; + + RetVal = FALSE; + if (0 == memcmp((UBYTE*)pAdr, pSrc, SIZE_OF_BDADDR)) + { + RetVal = TRUE; + } + return(RetVal); +} + +UWORD cCommInsertBtName(UBYTE *pDst, UBYTE *pSrc) +{ + UBYTE Cnt; + + Cnt = 0; + + /* Complete brick name */ + while ((pSrc[Cnt]) && (Cnt < (SIZE_OF_BT_NAME - 1))) + { + pDst[Cnt] = pSrc[Cnt]; + Cnt++; + } + + /* Fill remaining up with zeros */ + while (Cnt < SIZE_OF_BT_NAME) + { + pDst[Cnt] = 0; + Cnt++; + } + + return((UWORD)SIZE_OF_BT_NAME); +} + + +UWORD cCommInsertDevice(UBYTE *pBdaddr, UBYTE *pName, UBYTE *pCod, UBYTE DeviceStatus, UBYTE *pAddInfo) +{ + UWORD Tmp; + UWORD RtnVal; + + RtnVal = FALSE; + *pAddInfo = DEVICE_VERIFIED; + for (Tmp = 0; Tmp < SIZE_OF_BT_DEVICE_TABLE; Tmp++) + { + if ((TRUE == cCommCheckBdaddr((IOMapComm.BtDeviceTable[Tmp].BdAddr), pBdaddr)) && + (IOMapComm.BtDeviceTable[Tmp].DeviceStatus != BT_DEVICE_EMPTY)) + { + + if ((IOMapComm.BtDeviceTable[Tmp].DeviceStatus) & BT_DEVICE_AWAY) + { + *pAddInfo = DEVICE_UPDATED; + (IOMapComm.BtDeviceTable[Tmp].DeviceStatus) &= ~BT_DEVICE_AWAY; + } + + if (BT_DEVICE_UNKNOWN == IOMapComm.BtDeviceTable[Tmp].DeviceStatus) + { + + /* Former unknown adresses can be upgraded - downgrading is not possible */ + IOMapComm.BtDeviceTable[Tmp].DeviceStatus = DeviceStatus; + } + if (pCod != NULL) + { + + /* Class of device can also upgraded - never downgraded to 0 */ + memcpy(&(IOMapComm.BtDeviceTable[Tmp].ClassOfDevice), pCod, SIZE_OF_CLASS_OF_DEVICE); + } + if ((*pName) != 0) + { + + /* Only upgrade name if name is received */ + cCommInsertBtName(IOMapComm.BtDeviceTable[Tmp].Name, pName); + } + RtnVal = TRUE; + + /* Break out - entry can only be found once */ + break; + } + } + + if (FALSE == RtnVal) + { + for (Tmp = 0; Tmp < SIZE_OF_BT_DEVICE_TABLE; Tmp++) + { + if (IOMapComm.BtDeviceTable[Tmp].DeviceStatus == BT_DEVICE_EMPTY) + { + *pAddInfo = DEVICE_INSERTED; + IOMapComm.BtDeviceTable[Tmp].DeviceStatus = DeviceStatus; + cCommCopyBdaddr((IOMapComm.BtDeviceTable[Tmp].BdAddr), pBdaddr); + cCommInsertBtName(IOMapComm.BtDeviceTable[Tmp].Name, pName); + if (NULL != pCod) + { + memcpy((IOMapComm.BtDeviceTable[Tmp].ClassOfDevice), pCod, SIZE_OF_CLASS_OF_DEVICE); + } + else + { + memset((IOMapComm.BtDeviceTable[Tmp].ClassOfDevice), 0, SIZE_OF_CLASS_OF_DEVICE); + } + RtnVal = TRUE; + break; + } + } + } + + /* Function returns SIZE_OF_BT_DEVICE_TABLE if device is not in the list */ + return(Tmp); +} + +void cCommsSetCmdMode(UBYTE *pNextState) +{ + switch(VarsComm.CmdSwitchCnt) + { + case 0: + { + if (BT_ARM_CMD_MODE != VarsComm.BtState) + { + cCommClearStreamStatus(); + VarsComm.BtCmdModeWaitCnt = 0; + VarsComm.CmdSwitchCnt++; + } + else + { + + /* allready in CMD mode - Exit */ + VarsComm.CmdSwitchCnt = 0; + (*pNextState)++; + } + } + break; + + case 1: + { + + /* stream status has been cleared now wait until buffers has been emptied */ + if (TRUE == dBtTxEnd()) + { + + /* Wait 100 ms after last byte has been sent to BC4 - else BC4 can crash */ + if (++(VarsComm.BtCmdModeWaitCnt) > 100) + { + dBtClearArm7CmdSignal(); + VarsComm.CmdSwitchCnt++; + } + } + } + break; + + case 2: + { + if (VarsComm.BtBcPinLevel == 0) + { + + /* Bluecore has entered cmd mode */ + SETBtCmdState; + VarsComm.CmdSwitchCnt = 0; + (*pNextState)++; + } + } + break; + + default: + { + VarsComm.CmdSwitchCnt = 0; + } + break; + } +} + +void cCommsOpenStream(UBYTE *pNextState) +{ + switch(VarsComm.StreamStateCnt) + { + case 0: + { + + if (SIZE_OF_BT_CONNECT_TABLE > VarsComm.BtCmdData.ParamTwo) + { + + /* first check if there is a connection on the requested channel */ + if ('\0' != IOMapComm.BtConnectTable[VarsComm.BtCmdData.ParamTwo].Name[0]) + { + + if (1 == IOMapComm.BtConnectTable[VarsComm.BtCmdData.ParamTwo].StreamStatus) + { + + /* Stream is allready open - continue */ + (*pNextState)++; + } + else + { + + /* There is a connection on requested channel proceed */ + VarsComm.StreamStateCnt = 1; + } + } + else + { + + /* Error - no connecteion on requested channel - exit */ + *(VarsComm.pRetVal) = (UWORD)ERR_COMM_CHAN_NOT_READY; + *(VarsComm.pRetVal) |= 0x8000; + SETBtStateIdle; + } + } + else + { + + /* Error - Illegal channel no - exit */ + *(VarsComm.pRetVal) = (UWORD)ERR_COMM_CHAN_INVALID; + *(VarsComm.pRetVal) |= 0x8000; + SETBtStateIdle; + } + } + break; + + case 1: + { + cCommsSetCmdMode(&(VarsComm.StreamStateCnt)); + } + break; + + case 2: + { + cCommsCloseConn0(&(VarsComm.StreamStateCnt)); + } + break; + + case 3: + { + + /* Open stream on the specified channel */ + VarsComm.StreamStateCnt = 4; + dBtSendBtCmd((UBYTE)MSG_OPEN_STREAM, IOMapComm.BtConnectTable[VarsComm.BtCmdData.ParamTwo].HandleNr, + 0, NULL, NULL, NULL, NULL); + } + break; + + case 4: + { + if (VarsComm.BtBcPinLevel) + { + SETBtDataState; + IOMapComm.BtConnectTable[VarsComm.BtCmdData.ParamTwo].StreamStatus = 1; + VarsComm.StreamStateCnt = 0; + (*pNextState)++; + } + } + break; + + default: + { + VarsComm.StreamStateCnt = 0; + } + break; + } +} + +void cCommsCloseConn0(UBYTE *pNextState) +{ + switch(VarsComm.CloseConn0Cnt) + { + case 0: + { + if ('\0' != IOMapComm.BtConnectTable[0].Name[0]) + { + + /* now disconnect channel 0 */ + VarsComm.CloseConn0Cnt = 1; + dBtSendBtCmd((UBYTE)MSG_CLOSE_CONNECTION, IOMapComm.BtConnectTable[0].HandleNr, 0, NULL, NULL, NULL, NULL); + } + else + { + (*pNextState)++; + } + } + break; + case 1: + { + if (MSG_CLOSE_CONNECTION_RESULT == IOMapComm.BtInBuf.Buf[BT_CMD_BYTE]) + { + VarsComm.CloseConn0Cnt = 0; + (*pNextState)++; + } + } + break; + default: + { + VarsComm.CloseConn0Cnt = 0; + } + break; + } +} + +void cCommsDisconnectAll(UBYTE *pNextState) +{ + switch(VarsComm.DiscAllCnt) + { + case 0: + { + VarsComm.BtCmdData.ParamOne = 0; + (VarsComm.DiscAllCnt)++; + } + break; + case 1: + { + while (('\0' == IOMapComm.BtConnectTable[VarsComm.BtCmdData.ParamOne].Name[0]) && + (VarsComm.BtCmdData.ParamOne < 4)) + { + VarsComm.BtCmdData.ParamOne++; + } + if (VarsComm.BtCmdData.ParamOne < 4) + { + + /* now disconnect selected channel */ + dBtSendBtCmd((UBYTE)MSG_CLOSE_CONNECTION, IOMapComm.BtConnectTable[VarsComm.BtCmdData.ParamOne].HandleNr, + 0, NULL, NULL, NULL, NULL); + VarsComm.BtCmdData.ParamOne++; + (VarsComm.DiscAllCnt)++; + } + else + { + + /* no more connections - move on */ + (VarsComm.DiscAllCnt) = 0; + (*pNextState)++; + } + } + break; + case 2: + { + if (MSG_CLOSE_CONNECTION_RESULT == IOMapComm.BtInBuf.Buf[BT_CMD_BYTE]) + { + + /* Go back and check for more connections to close */ + (VarsComm.DiscAllCnt)--; + } + } + break; + } +} + +void cCommsBtReset(UBYTE *pNextState) +{ + switch(VarsComm.ResetBtCnt) + { + case 0: + { + + /* Setup Reset sequence */ + VarsComm.BtResetTimeCnt = 0; + VarsComm.ResetBtCnt = 1; + dBtSetBcResetPinLow(); + } + break; + case 1: + { + + /* Reset should be held low for a certain time "BLUECORE_RESET_TIME" */ + VarsComm.BtResetTimeCnt++; + if (VarsComm.BtResetTimeCnt > BLUECORE_RESET_TIME) + { + dBtSetBcResetPinHigh(); + VarsComm.BtWaitTimeCnt = 0; + VarsComm.ResetBtCnt = 2; + } + } + break; + case 2: + { + + /* Wait after reset is released either wait a minimum time or wait for the reset indication telegram */ + VarsComm.BtWaitTimeCnt++; + if ((VarsComm.BtWaitTimeCnt > BLUECORE_WAIT_BEFORE_INIT) || (MSG_RESET_INDICATION == IOMapComm.BtInBuf.Buf[BT_CMD_BYTE])) + { + memset(&(IOMapComm.BtDeviceTable), 0, sizeof(IOMapComm.BtDeviceTable)); + cCommClrConnTable(); + VarsComm.ResetBtCnt = 3; + } + } + break; + + case 3: + { + SETBtCmdState; + VarsComm.ResetBtCnt = 0; + (*pNextState)++; + } + break; + } +} + + +UWORD cCommReq(UBYTE Cmd, UBYTE Param1, UBYTE Param2, UBYTE Param3, UBYTE *pName, UWORD *pRetVal) +{ + ULONG Length; + UWORD ReturnVal; + + ReturnVal = BTBUSY; + *pRetVal = BTBUSY; + if ((UPD_IDLE == (VarsComm.ActiveUpdate)) || ((UPD_SEARCH == (VarsComm.ActiveUpdate)) && (STOPSEARCH == Cmd))) + { + + ReturnVal = SUCCESS; + *pRetVal = INPROGRESS; + VarsComm.pRetVal = pRetVal; + switch(Cmd) + { + case SENDFILE: + { + ReturnVal = SUCCESS; + + /* No file is currently beeing send - Now open the file */ + VarsComm.ExtTx.SrcHandle = pMapLoader->pFunc(OPENREAD, pName, NULL, &Length); + VarsComm.ExtTx.RemFileSize = Length; + VarsComm.ExtTx.SlotNo = Param1; + VarsComm.BtCmdData.ParamTwo = Param1; /* This is used to open the correct stream */ + + if (0x8000 > VarsComm.ExtTx.SrcHandle) + { + + /* Source file is ok - go ahead */ + VarsComm.ActiveUpdate = UPD_SENDFILE; + VarsComm.ExtTx.Timer = 0; + VarsComm.ExtTx.Cmd = WRITE; + cCommCopyFileName(VarsComm.ExtTx.FileName, pName); + } + else + { + + /* Error in opening source file for read - file do not exist */ + ReturnVal = FILETX_SRCMISSING; + } + } + break; + + case CONNECT: + { + + if (BLUETOOTH_HANDLE_UNDEFIEND == IOMapComm.BtConnectTable[Param2].HandleNr) + { + + /* Connection not occupied */ + VarsComm.ActiveUpdate = UPD_CONNECT; + VarsComm.BtCmdData.ParamOne = Param1; + VarsComm.BtCmdData.ParamTwo = Param2; + } + else + { + + /* Connection occupied */ + ReturnVal = BTCONNECTFAIL; + *pRetVal = BTCONNECTFAIL; + } + } + break; + + case DISCONNECT: + { + VarsComm.ActiveUpdate = UPD_DISCONNECT; + VarsComm.BtCmdData.ParamOne = Param1; + } + break; + + case DISCONNECTALL: + { + VarsComm.ActiveUpdate = UPD_DISCONNECTALL; + } + break; + + case SEARCH: + { + VarsComm.ActiveUpdate = UPD_SEARCH; + IOMapComm.BtDeviceNameCnt = 0; + IOMapComm.BtDeviceCnt = 0; + VarsComm.BtCmdData.ParamOne = 0; + } + break; + case STOPSEARCH: + { + if (UPD_SEARCH == (VarsComm.ActiveUpdate)) + { + VarsComm.BtCmdData.ParamOne = 1; + } + else + { + *pRetVal = SUCCESS; + } + } + break; + case REMOVEDEVICE: + { + VarsComm.ActiveUpdate = UPD_REMOVEDEVICE; + VarsComm.BtCmdData.ParamOne = Param1; + } + break; + case VISIBILITY: + { + VarsComm.ActiveUpdate = UPD_VISIBILITY; + VarsComm.BtCmdData.ParamOne = Param1; + } + break; + case SETCMDMODE: + { + VarsComm.ActiveUpdate = UPD_REQCMDMODE; + } + break; + case FACTORYRESET: + { + VarsComm.ActiveUpdate = UPD_FACTORYRESET; + } + break; + case BTON: + { + if (BT_STATE_OFF & (pMapUi->BluetoothState)) + { + VarsComm.ActiveUpdate = UPD_RESET; + } + else + { + + /* Device is already on*/ + *pRetVal = SUCCESS; + } + } + break; + case BTOFF: + { + VarsComm.ActiveUpdate = UPD_OFF; + } + break; + case SENDDATA: + { + + /* Param2 indicates the port that the data should be */ + /* be sent on - param1 indicates the number of data */ + /* to be sent. pName is the pointer to the data */ + if (Param1 <= sizeof(VarsComm.BtModuleOutBuf.Buf)) + { + if ('\0' != IOMapComm.BtConnectTable[VarsComm.BtCmdData.ParamTwo].Name[0]) + { + VarsComm.BtCmdData.ParamOne = Param1; + VarsComm.BtCmdData.ParamTwo = Param2; + VarsComm.BtCmdData.ParamThree = Param3; + memcpy((VarsComm.BtModuleOutBuf.Buf), pName, Param1); + VarsComm.ActiveUpdate = UPD_SENDDATA; + } + else + { + ReturnVal = (UWORD)ERR_COMM_CHAN_NOT_READY; + ReturnVal |= 0x8000; + } + } + else + { + ReturnVal = (UWORD)ERR_COMM_BUFFER_FULL; + ReturnVal |= 0x8000; + } + } + break; + case OPENSTREAM: + { + VarsComm.BtCmdData.ParamTwo = Param2; + VarsComm.ActiveUpdate = UPD_OPENSTREAM; + } + break; + case SETBTNAME: + { + VarsComm.ActiveUpdate = UPD_BRICKNAME; + } + break; + case EXTREAD: + { + VarsComm.ActiveUpdate = UPD_EXTREAD; + } + break; + case PINREQ: + { + + /* This is an incomming pinrequest for connection on connection 0 because */ + /* ActiveUpdate is idle (if it was incomming it is not idle) */ + cCommCopyBdaddr((IOMapComm.BtConnectTable[0].BdAddr), &(IOMapComm.BtInBuf.Buf[2])); + pMapUi->BluetoothState |= (BT_CONNECT_REQUEST | BT_PIN_REQUEST); + VarsComm.pValidPinCode = NULL; + VarsComm.ActiveUpdate = UPD_PINREQ; + } + break; + case CONNECTREQ: + { + VarsComm.ActiveUpdate = UPD_CONNECTREQ; + } + break; + } + } + return(ReturnVal); +} + +void cCommPinCode(UBYTE *pPinCode) +{ + VarsComm.pValidPinCode = pPinCode; + if (REQPIN == (*(VarsComm.pRetVal))) + { + *(VarsComm.pRetVal) = INPROGRESS; + } +} + +void cCommClrConnTable(void) +{ + UBYTE Tmp; + + for (Tmp = 0; Tmp < SIZE_OF_BT_CONNECT_TABLE; Tmp++) + { + CLEARConnEntry(Tmp); + } + IOMapComm.BrickData.BtStateStatus &= ~(BT_CONNECTION_0_ENABLE | BT_CONNECTION_1_ENABLE | BT_CONNECTION_2_ENABLE | BT_CONNECTION_3_ENABLE); + pMapUi->BluetoothState &= ~BT_STATE_CONNECTED; + pMapUi->Flags |= UI_REDRAW_STATUS; +} diff --git a/AT91SAM7S256/Source/c_comm.h b/AT91SAM7S256/Source/c_comm.h new file mode 100644 index 0000000..8487a82 --- /dev/null +++ b/AT91SAM7S256/Source/c_comm.h @@ -0,0 +1,151 @@ +// +// Date init 14.12.2004 +// +// Revision date $Date:: 16-05-06 9:42 $ +// +// Filename $Workfile:: c_comm.h $ +// +// Version $Revision:: 54 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/c_comm.h $ +// +// Platform C +// + +#ifndef C_COMM +#define C_COMM + + +#define BLUECORE_RESET_TIME 100 // Time in mS +#define BLUECORE_WAIT_BEFORE_INIT 5000 // Time in mS +#define BLUETOOTH_HANDLE_UNDEFIEND 0xFF + +/* Constants related to BtAdrStatus*/ +enum +{ + COLDBOOT, + INITIALIZED, + BTADRERROR +}; + + +enum +{ + USB_CH, + BT_CH, + HISPEED_CH, + NO_OF_CHANNELS +}; + + +/* enum reffering to BT update */ +enum +{ + UPD_BRICKNAME, + UPD_FACTORYRESET, + UPD_OPENSTREAM, + UPD_REQCMDMODE, + UPD_CONNECT, + UPD_CONNECTREQ, + UPD_PINREQ, + UPD_DISCONNECT, + UPD_DISCONNECTALL, + UPD_REMOVEDEVICE, + UPD_SEARCH, + UPD_RESET, + UPD_EXTREAD, + UPD_SENDFILE, + UPD_OFF, + UPD_VISIBILITY, + UPD_SENDDATA, + UPD_IDLE +}; + +/* Constants reffering to Protocol */ +enum +{ + DIRECT_CMD = 0x00, + SYSTEM_CMD = 0x01, + REPLY_CMD = 0x02, + NO_REPLY_BIT = 0x80 +}; + +typedef struct +{ + ULONG RemFileSize; + UWORD RemMsgSize; + UWORD SrcHandle; + UWORD DstHandle; + UWORD Timer; + UBYTE FileName[FILENAME_LENGTH + 1]; + UBYTE Cmd; + UBYTE SlotNo; +}EXTTX; + +typedef struct +{ + UBYTE Buf[256]; + UWORD InPtr; + UWORD OutPtr; +}BTDATA; + +typedef struct +{ + UBYTE Buf[256]; + UWORD InPtr; + UWORD OutPtr; +}HSDATA; + +typedef struct +{ + UBYTE Status; + UBYTE Type; + UBYTE Handle; + UBYTE Cmd; +}EXTMODE; + +typedef struct +{ + UBYTE ParamOne; + UBYTE ParamTwo; + UBYTE ParamThree; +}BTCMD; + +typedef struct +{ + UBYTE BtUpdateDataConnectNr; + UBYTE BtBcPinLevel; + UBYTE BtResetTimeCnt; + UWORD BtWaitTimeCnt; + BTDATA BtModuleInBuf; + BTDATA BtModuleOutBuf; + BTCMD BtCmdData; + UBYTE HsState; + HSDATA HsModuleInBuf; + HSDATA HsModuleOutBuf; + EXTTX ExtTx; + EXTMODE ExtMode[NO_OF_CHANNELS]; + UBYTE ActiveUpdate; + UBYTE UpdateState; + UBYTE BtDeviceIndex; + UBYTE CmdSwitchCnt; + UBYTE StreamStateCnt; + UBYTE CloseConn0Cnt; + UBYTE DiscAllCnt; + UBYTE ResetBtCnt; + UBYTE BtState; + UWORD *pRetVal; + UWORD RetVal; + UBYTE *pValidPinCode; + UBYTE LookUpCnt; + UBYTE BtAdrStatus; + UBYTE BtCmdModeWaitCnt; +}VARSCOMM; + +void cCommInit(void* pHeader); +void cCommCtrl(void); +void cCommExit(void); + +extern const HEADER cComm; + +#endif diff --git a/AT91SAM7S256/Source/c_comm.iom b/AT91SAM7S256/Source/c_comm.iom new file mode 100644 index 0000000..6a43149 --- /dev/null +++ b/AT91SAM7S256/Source/c_comm.iom @@ -0,0 +1,222 @@ +// +// Date init 14.12.2004 +// +// Revision date $Date:: 16-05-06 9:42 $ +// +// Filename $Workfile:: c_comm.iom $ +// +// Version $Revision:: 72 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/c_comm.iom $ +// +// Platform C +// + +#ifndef CCOMM_IOM +#define CCOMM_IOM + +#define pMapComm ((IOMAPCOMM*)(pHeaders[ENTRY_COMM]->pIOMap)) + +#define SIZE_OF_USBBUF 64 +#define USB_PROTOCOL_OVERHEAD 1 + 1 /* Command type byte + Command */ +#define SIZE_OF_USBDATA (SIZE_OF_USBBUF - USB_PROTOCOL_OVERHEAD) +#define SIZE_OF_HSBUF 128 +#define SIZE_OF_BTBUF 128 + +#define BT_CMD_BYTE 1 +#define SIZE_OF_BT_DEVICE_TABLE 30 +#define SIZE_OF_BT_CONNECT_TABLE 4 /* Index 0 is alway incomming connections */ +#define MAX_BT_MSG_SIZE 60000L + +#define BT_DEFAULT_INQUIRY_MAX 0 /* Unlimited no */ +#define BT_DEFAULT_INQUIRY_TIMEOUT_LO 15 /* 15 x 1,28 Sec = 19,2 Sec */ + + +// Constants reffering to BtState +enum +{ + BT_ARM_OFF, + BT_ARM_CMD_MODE, + BT_ARM_DATA_MODE, +}; + +//Constant reffering to BtStateStatus +#define BT_BRICK_VISIBILITY 0x01 +#define BT_BRICK_PORT_OPEN 0x02 +#define BT_CONNECTION_0_ENABLE 0x10 +#define BT_CONNECTION_1_ENABLE 0x20 +#define BT_CONNECTION_2_ENABLE 0x40 +#define BT_CONNECTION_3_ENABLE 0x80 + +//Constant reffering to BtHwStatus +#define BT_ENABLE 0x00 +#define BT_DISABLE 0x01 + +// Constants reffering to HsFlags +enum +{ + HS_UPDATE = 1 +}; + +// Constants reffering to HsState +enum +{ + HS_INITIALISE = 1, + HS_INIT_RECEIVER, + HS_SEND_DATA, + HS_DISABLE +}; + +//Constants refering to DeviceStatus within DeviceTable +enum +{ + BT_DEVICE_EMPTY = 0x00, + BT_DEVICE_UNKNOWN = 0x01, + BT_DEVICE_KNOWN = 0x02, + BT_DEVICE_NAME = 0x40, + BT_DEVICE_AWAY = 0x80 +}; + +/* Interface between command other modules */ +enum +{ + SENDFILE, + SEARCH, + STOPSEARCH, + CONNECT, + DISCONNECT, + DISCONNECTALL, + REMOVEDEVICE, + VISIBILITY, + SETCMDMODE, + OPENSTREAM, + SENDDATA, + FACTORYRESET, + BTON, + BTOFF, + SETBTNAME, + EXTREAD, + PINREQ, + CONNECTREQ +}; + + +enum +{ + LR_SUCCESS = 0x50, + LR_COULD_NOT_SAVE, + LR_STORE_IS_FULL, + LR_ENTRY_REMOVED, + LR_UNKOWN_ADDR +}; + +enum +{ + USB_CMD_READY = 0x01, + BT_CMD_READY = 0x02, + HS_CMD_READY = 0x04 +}; + +typedef struct +{ + UBYTE Buf[SIZE_OF_USBBUF]; + UBYTE InPtr; + UBYTE OutPtr; + UBYTE Spare1; + UBYTE Spare2; +}USBBUF; + +typedef struct +{ + UBYTE Buf[SIZE_OF_HSBUF]; + UBYTE InPtr; + UBYTE OutPtr; + UBYTE Spare1; + UBYTE Spare2; +}HSBUF; + +typedef struct +{ + UBYTE Buf[SIZE_OF_BTBUF]; + UBYTE InPtr; + UBYTE OutPtr; + UBYTE Spare1; + UBYTE Spare2; +}BTBUF; + +typedef struct +{ + UBYTE Name[SIZE_OF_BT_NAME]; + UBYTE ClassOfDevice[SIZE_OF_CLASS_OF_DEVICE]; + UBYTE BdAddr[SIZE_OF_BDADDR]; + UBYTE DeviceStatus; + UBYTE Spare1; + UBYTE Spare2; + UBYTE Spare3; +}BDDEVICETABLE; + +typedef struct +{ + UBYTE Name[SIZE_OF_BT_NAME]; + UBYTE ClassOfDevice[SIZE_OF_CLASS_OF_DEVICE]; + UBYTE PinCode[16]; + UBYTE BdAddr[SIZE_OF_BDADDR]; + UBYTE HandleNr; + UBYTE StreamStatus; + UBYTE LinkQuality; + UBYTE Spare; +}BDCONNECTTABLE; + +typedef struct +{ + UBYTE Name[SIZE_OF_BT_NAME]; + UBYTE BluecoreVersion[2]; + UBYTE BdAddr[SIZE_OF_BDADDR]; + UBYTE BtStateStatus; + UBYTE BtHwStatus; + UBYTE TimeOutValue; + UBYTE Spare1; + UBYTE Spare2; + UBYTE Spare3; +}BRICKDATA; + +typedef struct +{ + UWORD (*pFunc)(UBYTE, UBYTE, UBYTE, UBYTE, UBYTE*, UWORD*); + void (*pFunc2)(UBYTE*); + + // BT related entries + BDDEVICETABLE BtDeviceTable[SIZE_OF_BT_DEVICE_TABLE]; + BDCONNECTTABLE BtConnectTable[SIZE_OF_BT_CONNECT_TABLE]; + + //General brick data + BRICKDATA BrickData; + + BTBUF BtInBuf; + BTBUF BtOutBuf; + + // HI Speed related entries + HSBUF HsInBuf; + HSBUF HsOutBuf; + + // USB related entries + USBBUF UsbInBuf; + USBBUF UsbOutBuf; + USBBUF UsbPollBuf; + + UBYTE BtDeviceCnt; + UBYTE BtDeviceNameCnt; + + UBYTE HsFlags; + UBYTE HsSpeed; + UBYTE HsState; + + UBYTE UsbState; + +}IOMAPCOMM; + + +#endif + + + diff --git a/AT91SAM7S256/Source/c_display.c b/AT91SAM7S256/Source/c_display.c new file mode 100644 index 0000000..36d66e7 --- /dev/null +++ b/AT91SAM7S256/Source/c_display.c @@ -0,0 +1,859 @@ +// +// Programmer +// +// Date init 14.12.2004 +// +// Reviser $Author:: Dktochpe $ +// +// Revision date $Date:: 17-02-06 8:45 $ +// +// Filename $Workfile:: c_display.c $ +// +// Version $Revision:: 36 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/c_display. $ +// +// Platform C +// + +#include +#include "stdconst.h" +#include "modules.h" +#include "c_display.iom" +#include "c_display.h" +#include "d_display.h" + + +static IOMAPDISPLAY IOMapDisplay; +static VARSDISPLAY VarsDisplay; + +const HEADER cDisplay = +{ + 0x000A0001L, + "Display", + cDisplayInit, + cDisplayCtrl, + cDisplayExit, + (void *)&IOMapDisplay, + (void *)&VarsDisplay, + (UWORD)sizeof(IOMapDisplay), + (UWORD)sizeof(VarsDisplay), + 0x0000 //Code size - not used so far +}; + + +const SCREEN_CORDINATE SCREEN_CORDINATES[SCREENS] = +{ + { 0, 0,DISPLAY_WIDTH,DISPLAY_HEIGHT }, // Background + { 0, 8,DISPLAY_WIDTH,DISPLAY_HEIGHT - 8 }, // Large + { 0, 8,DISPLAY_WIDTH,24 } // Small +}; + +const SCREEN_CORDINATE SELECT_FRAME_CORDINATES = +{ + 38,41,24,24 +}; + + +const SCREEN_CORDINATE MENUICON_CORDINATES[MENUICONS] = +{ + { DISPLAY_MENUICONS_X_OFFS,DISPLAY_MENUICONS_Y,24,24 }, // Left + { DISPLAY_MENUICONS_X_OFFS + DISPLAY_MENUICONS_X_DIFF,DISPLAY_MENUICONS_Y,24,24 }, // Center + { DISPLAY_MENUICONS_X_OFFS + DISPLAY_MENUICONS_X_DIFF * 2,DISPLAY_MENUICONS_Y,24,24 },// Right +}; + +const SCREEN_CORDINATE STATUSICON_CORDINATES[STATUSICONS] = +{ + { 0, 0,12, 8 }, // Bluetooth + { 12, 0,12, 8 }, // Usb + { 76, 0,12, 8 }, // Vm + { 88, 0,12, 8 } // Battery +}; + + +const SCREEN_CORDINATE STEPICON_CORDINATES[STEPICONS] = +{ + { 11,16,11,16 }, // Step 1 + { 28,16,11,16 }, // Step 2 + { 45,16,11,16 }, // Step 3 + { 62,16,11,16 }, // Step 4 + { 79,16,11,16 } // Step 5 +}; + + +void cDisplaySetPixel(UBYTE X,UBYTE Y) +{ + if ((X < DISPLAY_WIDTH) && (Y < DISPLAY_HEIGHT)) + { + IOMapDisplay.Display[(Y / 8) * DISPLAY_WIDTH + X] |= (1 << (Y % 8)); + } +} + + +void cDisplayClrPixel(UBYTE X,UBYTE Y) +{ + if ((X < DISPLAY_WIDTH) && (Y < DISPLAY_HEIGHT)) + { + IOMapDisplay.Display[(Y / 8) * DISPLAY_WIDTH + X] &= ~(1 << (Y % 8)); + } +} + + +void cDisplayChar(FONT *pFont,UBYTE On,UBYTE X,UBYTE Y,UBYTE Char) +{ + UBYTE *pSource; + UBYTE FontWidth; + UBYTE FontHeight; + UBYTE Items; + UBYTE Item; + UBYTE TmpY; + + + Items = pFont->ItemsX * pFont->ItemsY; + Item = Char - ' '; + if (Item < Items) + { + FontWidth = pFont->ItemPixelsX; + pSource = (UBYTE*)&pFont->Data[Item * FontWidth]; + while (FontWidth--) + { + TmpY = 0; + FontHeight = pFont->ItemPixelsY; + while (FontHeight--) + { + if (On == TRUE) + { + if (((*pSource) & (1 << TmpY))) + { + cDisplaySetPixel(X,Y + TmpY); + } + else + { + cDisplayClrPixel(X,Y + TmpY); + } + } + else + { + if (((*pSource) & (1 << TmpY))) + { + cDisplayClrPixel(X,Y + TmpY); + } + else + { + cDisplaySetPixel(X,Y + TmpY); + } + } + TmpY++; + } + X++; + pSource++; + } + } +} + + +void cDisplayString(FONT *pFont,UBYTE X,UBYTE Y,UBYTE *pString) +{ + UBYTE *pSource; + UBYTE *pDestination; + UBYTE FontWidth; + UBYTE Line; + UBYTE Items; + UBYTE Item; + + + Line = (Y & 0xF8) / 8; + Items = pFont->ItemsX * pFont->ItemsY; + pDestination = (UBYTE*)&IOMapDisplay.Display[Line * DISPLAY_WIDTH + X]; + + while (*pString) + { + Item = *pString - ' '; + if (Item < Items) + { + FontWidth = pFont->ItemPixelsX; + pSource = (UBYTE*)&pFont->Data[Item * FontWidth]; + while (FontWidth--) + { + *pDestination = *pSource; + pDestination++; + pSource++; + } + } + pString++; + } +} + + +void cDisplayUpdateScreen(SCREEN_CORDINATE *pCord,BMPMAP *pBitmap) +{ + UBYTE *pSource; + UBYTE *pDestination; + UBYTE Line; + UBYTE Lines; + + if (pBitmap) + { + if ((((pBitmap->StartY + pCord->StartY) & 0x07) == 0) && ((pBitmap->PixelsY & 0x07) == 0)) + { + pSource = pBitmap->Data; + Line = (pBitmap->StartY + pCord->StartY) / 8; + Lines = Line + pBitmap->PixelsY / 8; + while (Line < Lines) + { + pDestination = &IOMapDisplay.Display[Line * DISPLAY_WIDTH + pBitmap->StartX + pCord->StartX]; + memcpy(pDestination,pSource,(size_t)pBitmap->PixelsX); + pSource += pBitmap->PixelsX; + Line++; + } + } + } +} + + +void cDisplayCenterString(FONT *pFont,UBYTE *pString,UBYTE Line) +{ + UWORD Chars; + UBYTE Column; + + if (pString) + { + Chars = 0; + while (pString[Chars]) + { + Chars++; + } + Column = (DISPLAY_WIDTH - Chars * pFont->ItemPixelsX) / 2; + cDisplayString(pFont,Column,Line * 8,pString); + } +} + + +void cDisplayUpdateMenuIcon(UBYTE *pIcon,SCREEN_CORDINATE *pCord) +{ + UBYTE *pDestination; + UBYTE Line; + UBYTE Column; + UBYTE Lines; + UBYTE Columns; + + if (((pCord->StartY & 0x07) == 0) && ((pCord->PixelsY & 0x07) == 0)) + { + Line = pCord->StartY / 8; + Lines = Line + pCord->PixelsY / 8; + Columns = pCord->StartX + pCord->PixelsX; + if (pIcon != NULL) + { + while (Line < Lines) + { + Column = pCord->StartX; + pDestination = &IOMapDisplay.Display[Line * DISPLAY_WIDTH + Column]; + + while (Column < Columns) + { + *pDestination |= *pIcon; + pIcon++; + pDestination++; + Column++; + } + Line++; + } + } + else + { + while (Line < Lines) + { + pDestination = &IOMapDisplay.Display[Line * DISPLAY_WIDTH + pCord->StartX]; + memset(pDestination,0,(size_t)pCord->PixelsX); + Line++; + } + } + } +} + + +void cDisplayUpdateIcon(ICON *pIcons,UBYTE Index,SCREEN_CORDINATE *pCord) +{ + UBYTE *pSource; + UBYTE *pDestination; + UBYTE Line; + UBYTE Lines; + + if (pIcons) + { + if ((Index > 0) && (Index <= (pIcons->ItemsX * pIcons->ItemsY))) + { + Index--; + if (((pCord->StartY & 0x07) == 0) && ((pCord->PixelsY & 0x07) == 0)) + { + Line = pCord->StartY / 8; + Lines = Line + pCord->PixelsY / 8; + pSource = &pIcons->Data[((Index / pIcons->ItemsX) * pIcons->ItemsX * pIcons->ItemPixelsX * pIcons->ItemPixelsY / 8) + ((Index % pIcons->ItemsX) * pIcons->ItemPixelsX)]; + while (Line < Lines) + { + pDestination = &IOMapDisplay.Display[Line * DISPLAY_WIDTH + pCord->StartX]; + memcpy(pDestination,pSource,(size_t)pCord->PixelsX); + pSource += (pIcons->ItemPixelsX * pIcons->ItemsX); + Line++; + } + } + } + else + { + if (((pCord->StartY & 0x07) == 0) && ((pCord->PixelsY & 0x07) == 0)) + { + Line = pCord->StartY / 8; + Lines = Line + pCord->PixelsY / 8; + while (Line < Lines) + { + pDestination = &IOMapDisplay.Display[Line * DISPLAY_WIDTH + pCord->StartX]; + memset(pDestination,0,(size_t)pCord->PixelsX); + Line++; + } + } + } + } +} + + +void cDisplayLineX(UBYTE X1,UBYTE X2,UBYTE Y) +{ + UBYTE X; + UBYTE M; + + M = 1 << (Y % 8); + Y >>= 3; + for (X = X1;X < X2;X++) + { + IOMapDisplay.Display[Y * DISPLAY_WIDTH + X] |= M; + } +} + +void cDisplayLineY(UBYTE X,UBYTE Y1,UBYTE Y2) +{ + UBYTE Y; + + for (Y = Y1;Y < Y2;Y++) + { + IOMapDisplay.Display[(Y / 8) * DISPLAY_WIDTH + X] |= (1 << (Y % 8)); + } +} + +void cDisplayFrame(SCREEN_CORDINATE *pCord) +{ + cDisplayLineX(pCord->StartX,pCord->StartX + pCord->PixelsX - 1,pCord->StartY); + cDisplayLineY(pCord->StartX,pCord->StartY,pCord->StartY + pCord->PixelsY - 1); + cDisplayLineY(pCord->StartX + pCord->PixelsX - 1,pCord->StartY,pCord->StartY + pCord->PixelsY - 1); +} + + +void cDisplayEraseLine(UBYTE Line) +{ + UBYTE Tmp; + + for (Tmp = 0;Tmp < DISPLAY_WIDTH;Tmp++) + { + IOMapDisplay.Display[Line * DISPLAY_WIDTH + Tmp] = 0x00; + } +} + + +void cDisplayErase(void) +{ + UBYTE Tmp; + + for (Tmp = 0;Tmp < (DISPLAY_HEIGHT / 8);Tmp++) + { + cDisplayEraseLine(Tmp); + } +} + + +void cDisplayEraseScreen(SCREEN_CORDINATE *pCord) +{ + UBYTE *pDestination; + UBYTE Line; + UBYTE Lines; + + if (((pCord->StartY & 0x07) == 0) && ((pCord->PixelsY & 0x07) == 0)) + { + Line = pCord->StartY / 8; + Lines = Line + pCord->PixelsY / 8; + + while (Line < Lines) + { + pDestination = &IOMapDisplay.Display[Line * DISPLAY_WIDTH + pCord->StartX]; + memset(pDestination,0,(size_t)pCord->PixelsX); + Line++; + } + } +} + + +void cDisplayDraw(UBYTE Cmd,UBYTE On,UBYTE X1,UBYTE Y1,UBYTE X2,UBYTE Y2) +{ + switch (Cmd) + { + case DISPLAY_ERASE_ALL : + { + cDisplayErase(); + } + break; + + case DISPLAY_PIXEL : + { + if (On == TRUE) + { + cDisplaySetPixel(X1,Y1); + } + else + { + cDisplayClrPixel(X1,Y1); + } + } + break; + + case DISPLAY_HORISONTAL_LINE : + { + if (On == TRUE) + { + if (X1 > X2) + { + cDisplayLineX(X2,X1,Y1); + } + else + { + cDisplayLineX(X1,X2,Y1); + } + } + } + break; + + case DISPLAY_VERTICAL_LINE : + { + if (On == TRUE) + { + if (Y1 > Y2) + { + cDisplayLineY(X1,Y2,Y1); + } + else + { + cDisplayLineY(X1,Y1,Y2); + } + } + } + break; + + case DISPLAY_CHAR : + { + cDisplayChar(IOMapDisplay.pFont,On,X1,Y1,X2); + } + break; + + } +} + + +void cDisplayInit(void* pHeader) +{ + dDisplayInit(); + IOMapDisplay.Display = (UBYTE*)IOMapDisplay.Normal; + IOMapDisplay.pFunc = &cDisplayDraw; + IOMapDisplay.EraseMask = 0; + IOMapDisplay.UpdateMask = 0; + IOMapDisplay.TextLinesCenterFlags = 0; + IOMapDisplay.Flags = DISPLAY_REFRESH | DISPLAY_ON; + VarsDisplay.ErasePointer = 0; + VarsDisplay.UpdatePointer = 0; +} + + +void cDisplayCtrl(void) +{ + ULONG TmpMask; + UBYTE Tmp; + SCREEN_CORDINATE Cordinate; + + if (!(IOMapDisplay.Flags & DISPLAY_POPUP)) + { + if (IOMapDisplay.Display == (UBYTE*)IOMapDisplay.Popup) + { + IOMapDisplay.Display = VarsDisplay.DisplaySave; + } + } + else + { + if (IOMapDisplay.Display != (UBYTE*)IOMapDisplay.Popup) + { + VarsDisplay.DisplaySave = IOMapDisplay.Display; + IOMapDisplay.Display = (UBYTE*)IOMapDisplay.Popup; + } + } + + if (IOMapDisplay.EraseMask) + { + + VarsDisplay.ErasePointer = 31; + while ((VarsDisplay.ErasePointer) && (!(IOMapDisplay.EraseMask & (0x00000001 << VarsDisplay.ErasePointer)))) + { + VarsDisplay.ErasePointer--; + } + + TmpMask = IOMapDisplay.EraseMask & (1 << VarsDisplay.ErasePointer); + if ((TmpMask & TEXTLINE_BITS)) + { + Tmp = 0; + while (!(TmpMask & TEXTLINE_BIT(Tmp))) + { + Tmp++; + } + if (Tmp < TEXTLINES) + { + cDisplayEraseLine(Tmp); + } + } + else + { + if ((TmpMask & MENUICON_BITS)) + { + Tmp = 0; + while (!(TmpMask & MENUICON_BIT(Tmp))) + { + Tmp++; + } + if (Tmp < MENUICONS) + { + cDisplayEraseScreen((SCREEN_CORDINATE*)&MENUICON_CORDINATES[Tmp]); + } + } + else + { + if ((TmpMask & STATUSICON_BITS)) + { + Tmp = 0; + while (!(TmpMask & STATUSICON_BIT(Tmp))) + { + Tmp++; + } + if (Tmp < STATUSICONS) + { + cDisplayEraseScreen((SCREEN_CORDINATE*)&STATUSICON_CORDINATES[Tmp]); + } + } + else + { + if ((TmpMask & SCREEN_BITS)) + { + Tmp = 0; + while (!(TmpMask & SCREEN_BIT(Tmp))) + { + Tmp++; + } + if (Tmp < SCREENS) + { + cDisplayEraseScreen((SCREEN_CORDINATE*)&SCREEN_CORDINATES[Tmp]); + } + if ((TmpMask & SCREEN_BIT(SCREEN_LARGE))) + { + if ((IOMapDisplay.UpdateMask & SPECIAL_BIT(TOPLINE))) + { + cDisplayLineX(0,DISPLAY_WIDTH - 1,9); + IOMapDisplay.UpdateMask &= ~SPECIAL_BIT(TOPLINE); + } + } + } + else + { + if ((TmpMask & BITMAP_BITS)) + { + Tmp = 0; + while (!(TmpMask & BITMAP_BIT(Tmp))) + { + Tmp++; + } + if (Tmp < BITMAPS) + { + Cordinate.StartX = VarsDisplay.pOldBitmaps[Tmp]->StartX; + Cordinate.StartY = VarsDisplay.pOldBitmaps[Tmp]->StartY; + Cordinate.PixelsX = VarsDisplay.pOldBitmaps[Tmp]->PixelsX; + Cordinate.PixelsY = VarsDisplay.pOldBitmaps[Tmp]->PixelsY; + cDisplayEraseScreen(&Cordinate); + } + } + else + { + if ((TmpMask & SPECIAL_BITS)) + { + Tmp = 0; + while (!(TmpMask & SPECIAL_BIT(Tmp))) + { + Tmp++; + } + switch (Tmp) + { + case FRAME_SELECT : + { + } + break; + + case MENUTEXT : + { + cDisplayEraseLine(TEXTLINE_5); + } + break; + + case STATUSTEXT : + { + cDisplayEraseLine(TEXTLINE_1); + } + break; + + case STEPLINE : + { + } + break; + + case TOPLINE : + { + } + break; + + } + } + else + { + if ((TmpMask & STEPICON_BITS)) + { + Tmp = 0; + while (!(TmpMask & STEPICON_BIT(Tmp))) + { + Tmp++; + } + if (Tmp < STEPICONS) + { + cDisplayEraseScreen((SCREEN_CORDINATE*)&STEPICON_CORDINATES[Tmp]); + } + } + } + } + } + } + } + } + IOMapDisplay.EraseMask &= ~TmpMask; + + if (++VarsDisplay.ErasePointer >= 32) + { + VarsDisplay.ErasePointer = 0; + } + VarsDisplay.UpdatePointer = 0; + } + else + { + if (IOMapDisplay.UpdateMask) + { + + VarsDisplay.UpdatePointer = 31; + while ((VarsDisplay.UpdatePointer) && (!(IOMapDisplay.UpdateMask & (0x00000001 << VarsDisplay.UpdatePointer)))) + { + VarsDisplay.UpdatePointer--; + } + TmpMask = IOMapDisplay.UpdateMask & (0x00000001 << VarsDisplay.UpdatePointer); + + if ((TmpMask & TEXTLINE_BITS)) + { + Tmp = 0; + while (!(TmpMask & TEXTLINE_BIT(Tmp))) + { + Tmp++; + } + if (Tmp < TEXTLINES) + { + if ((IOMapDisplay.TextLinesCenterFlags & (UBYTE)TmpMask)) + { + cDisplayCenterString(IOMapDisplay.pFont,IOMapDisplay.pTextLines[Tmp],TEXTLINE_1 + Tmp); + } + else + { + cDisplayString(IOMapDisplay.pFont,0,Tmp * 8,IOMapDisplay.pTextLines[Tmp]); + } + } + } + else + { + if ((TmpMask & MENUICON_BITS)) + { + Tmp = 0; + while (!(TmpMask & MENUICON_BIT(Tmp))) + { + Tmp++; + } + if (Tmp < MENUICONS) + { + cDisplayUpdateMenuIcon(IOMapDisplay.pMenuIcons[Tmp],(SCREEN_CORDINATE*)&MENUICON_CORDINATES[Tmp]); + } + } + else + { + if ((TmpMask & STATUSICON_BITS)) + { + Tmp = 0; + while (!(TmpMask & STATUSICON_BIT(Tmp))) + { + Tmp++; + } + if (Tmp < STATUSICONS) + { + cDisplayUpdateIcon(IOMapDisplay.pStatusIcons,IOMapDisplay.StatusIcons[Tmp],(SCREEN_CORDINATE*)&STATUSICON_CORDINATES[Tmp]); + } + } + else + { + if ((TmpMask & SCREEN_BITS)) + { + Tmp = 0; + while (!(TmpMask & SCREEN_BIT(Tmp))) + { + Tmp++; + } + if (Tmp < SCREENS) + { + cDisplayUpdateScreen((SCREEN_CORDINATE*)&SCREEN_CORDINATES[Tmp],IOMapDisplay.pScreens[Tmp]); + } + } + else + { + if ((TmpMask & BITMAP_BITS)) + { + Tmp = 0; + while (!(TmpMask & BITMAP_BIT(Tmp))) + { + Tmp++; + } + if (Tmp < BITMAPS) + { + VarsDisplay.pOldBitmaps[Tmp] = IOMapDisplay.pBitmaps[Tmp]; + cDisplayUpdateScreen((SCREEN_CORDINATE*)&SCREEN_CORDINATES[SCREEN_BACKGROUND],IOMapDisplay.pBitmaps[Tmp]); + } + } + else + { + if ((TmpMask & SPECIAL_BITS)) + { + Tmp = 0; + while (!(TmpMask & SPECIAL_BIT(Tmp))) + { + Tmp++; + } + switch (Tmp) + { + case FRAME_SELECT : + { + cDisplayFrame((SCREEN_CORDINATE*)&SELECT_FRAME_CORDINATES); + } + break; + + case MENUTEXT : + { + cDisplayCenterString(IOMapDisplay.pFont,IOMapDisplay.pMenuText,TEXTLINE_5); + } + break; + + case STATUSTEXT : + { + cDisplayCenterString(IOMapDisplay.pFont,IOMapDisplay.pStatusText,TEXTLINE_1); + } + break; + + case STEPLINE : + { + cDisplayLineX(22,28,20); + cDisplayLineX(39,45,20); + cDisplayLineX(56,62,20); + cDisplayLineX(73,79,20); + } + break; + + case TOPLINE : + { + cDisplayLineX(0,DISPLAY_WIDTH - 1,9); + } + break; + + } + } + else + { + if ((TmpMask & STEPICON_BITS)) + { + Tmp = 0; + while (!(TmpMask & STEPICON_BIT(Tmp))) + { + Tmp++; + } + if (Tmp < STEPICONS) + { + cDisplayUpdateIcon(IOMapDisplay.pStepIcons,IOMapDisplay.StepIcons[Tmp],(SCREEN_CORDINATE*)&STEPICON_CORDINATES[Tmp]); + } + } + } + } + } + } + } + } + IOMapDisplay.TextLinesCenterFlags &= (UBYTE)(~TmpMask); + IOMapDisplay.UpdateMask &= ~TmpMask; + if (++VarsDisplay.UpdatePointer >= 32) + { + VarsDisplay.UpdatePointer = 0; + } + } + VarsDisplay.ErasePointer = 0; + } + if (!(IOMapDisplay.Flags & DISPLAY_POPUP)) + { + if (!(IOMapDisplay.Flags & DISPLAY_REFRESH_DISABLED)) + { + if ((IOMapDisplay.Flags & DISPLAY_ON)) + { + dDisplayOn(TRUE); + } + else + { + dDisplayOn(FALSE); + } + if (!(dDisplayUpdate(DISPLAY_HEIGHT,DISPLAY_WIDTH,(UBYTE*)IOMapDisplay.Normal))) + { + IOMapDisplay.Flags &= ~DISPLAY_BUSY; + if (!(IOMapDisplay.Flags & DISPLAY_REFRESH)) + { + IOMapDisplay.Flags |= DISPLAY_REFRESH_DISABLED; + } + } + else + { + IOMapDisplay.Flags |= DISPLAY_BUSY; + } + } + else + { + if ((IOMapDisplay.Flags & DISPLAY_REFRESH)) + { + IOMapDisplay.Flags &= ~DISPLAY_REFRESH_DISABLED; + } + } + } + else + { + dDisplayUpdate(DISPLAY_HEIGHT,DISPLAY_WIDTH,(UBYTE*)IOMapDisplay.Popup); + } +} + + +void cDisplayExit(void) +{ + dDisplayExit(); +} + diff --git a/AT91SAM7S256/Source/c_display.h b/AT91SAM7S256/Source/c_display.h new file mode 100644 index 0000000..62a89f8 --- /dev/null +++ b/AT91SAM7S256/Source/c_display.h @@ -0,0 +1,43 @@ +// +// Programmer +// +// Date init 14.12.2004 +// +// Reviser $Author:: Dktochpe $ +// +// Revision date $Date:: 17-02-06 8:45 $ +// +// Filename $Workfile:: c_display.h $ +// +// Version $Revision:: 8 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/c_display. $ +// +// Platform C +// + +#ifndef C_DISPLAY +#define C_DISPLAY + +#ifndef INCLUDE_OS + +typedef struct +{ + UBYTE *DisplaySave; + BMPMAP *pOldBitmaps[BITMAPS]; + UBYTE ErasePointer; + UBYTE UpdatePointer; +}VARSDISPLAY; + +#endif + + +void cDisplayInit(void* pHeader); +void cDisplayCtrl(void); +void cDisplayExit(void); + + +extern const HEADER cDisplay; + + +#endif diff --git a/AT91SAM7S256/Source/c_display.iom b/AT91SAM7S256/Source/c_display.iom new file mode 100644 index 0000000..79fd86b --- /dev/null +++ b/AT91SAM7S256/Source/c_display.iom @@ -0,0 +1,177 @@ +// +// Programmer +// +// Date init 14.12.2004 +// +// Reviser $Author:: Dktochpe $ +// +// Revision date $Date:: 17-02-06 8:45 $ +// +// Filename $Workfile:: c_display.iom $ +// +// Version $Revision:: 30 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/c_display. $ +// +// Platform C +// + +#ifndef CDISPLAY_IOM +#define CDISPLAY_IOM + +#define pMapDisplay ((IOMAPDISPLAY*)(pHeaders[ENTRY_DISPLAY]->pIOMap)) + +// Constants related to simple draw entry (x = dont care) +enum +{ + DISPLAY_ERASE_ALL = 0x00, // W - erase entire screen (CMD,x,x,x,x,x) + DISPLAY_PIXEL = 0x01, // W - set pixel (on/off) (CMD,TRUE/FALSE,X,Y,x,x) + DISPLAY_HORISONTAL_LINE = 0x02, // W - draw horisontal line (CMD,TRUE,X1,Y1,X2,x) + DISPLAY_VERTICAL_LINE = 0x03, // W - draw vertical line (CMD,TRUE,X1,Y1,x,Y2) + DISPLAY_CHAR = 0x04 // W - draw char (actual font) (CMD,TRUE,X1,Y1,Char,x) +}; + +// Constants related to Flags +enum +{ + DISPLAY_ON = 0x01, // W - Display on + DISPLAY_REFRESH = 0x02, // W - Enable refresh + DISPLAY_POPUP = 0x08, // W - Use popup display memory + DISPLAY_REFRESH_DISABLED = 0x40, // R - Refresh disabled + DISPLAY_BUSY = 0x80 // R - Refresh in progress +}; + + +#define DISPLAY_HEIGHT 64 // Y pixels +#define DISPLAY_WIDTH 100 // X pixels + +#define DISPLAY_MENUICONS_Y 40 +#define DISPLAY_MENUICONS_X_OFFS 7 +#define DISPLAY_MENUICONS_X_DIFF 31 + +#define DISPLAY_IDLE ((pMapDisplay->EraseMask == 0) && (pMapDisplay->UpdateMask == 0)) + +enum TEXTLINE_NO // Used in macro "TEXTLINE_BIT" +{ + TEXTLINE_1, // Upper most line + TEXTLINE_2, // + TEXTLINE_3, // + TEXTLINE_4, // + TEXTLINE_5, // + TEXTLINE_6, // + TEXTLINE_7, // + TEXTLINE_8, // Buttom line + TEXTLINES +}; + +enum MENUICON_NO // Used in macro "MENUICON_BIT" +{ + MENUICON_LEFT, // Left icon + MENUICON_CENTER, // Center icon + MENUICON_RIGHT, // Right icon + MENUICONS +}; + +enum SPECIAL_NO // Used in macro "SPECIAL_BIT" +{ + FRAME_SELECT, // Center icon select frame + STATUSTEXT, // Status text (BT name) + MENUTEXT, // Center icon text + STEPLINE, // Step collection lines + TOPLINE, // Top status underline + SPECIALS +}; + +enum STATUSICON_NO // Used in macro "STATUSICON_BIT" +{ + STATUSICON_BLUETOOTH, // BlueTooth status icon collection + STATUSICON_USB, // USB status icon collection + STATUSICON_VM, // VM status icon collection + STATUSICON_BATTERY, // Battery status icon collection + STATUSICONS +}; + +enum SCREEN_NO // Used in macro "SCREEN_BIT" +{ + SCREEN_BACKGROUND, // Entire screen + SCREEN_LARGE, // Entire screen except status line + SCREEN_SMALL, // Screen between menu icons and status line + SCREENS +}; + +enum BITMAP_NO // Used in macro "BITMAP_BIT" +{ + BITMAP_1, // Bitmap 1 + BITMAP_2, // Bitmap 2 + BITMAP_3, // Bitmap 3 + BITMAP_4, // Bitmap 4 + BITMAPS +}; + +enum STEP_NO // Used in macro "STEPICON_BIT" +{ + STEPICON_1, // Left most step icon + STEPICON_2, // + STEPICON_3, // + STEPICON_4, // + STEPICON_5, // Right most step icon + STEPICONS +}; + +#define SCREEN_BITS ((ULONG)0xE0000000) // Executed as 1. +#define STEPICON_BITS ((ULONG)0x1F000000) // Executed as 2. +#define BITMAP_BITS ((ULONG)0x00F00000) // Executed as 3. +#define MENUICON_BITS ((ULONG)0x000E0000) // Executed as 4. +#define STATUSICON_BITS ((ULONG)0x0001E000) // Executed as 5. +#define SPECIAL_BITS ((ULONG)0x00001F00) // Executed as 6. +#define TEXTLINE_BITS ((ULONG)0x000000FF) // Executed as 7. + +#define SCREEN_BIT(No) ((ULONG)0x20000000 << (No)) +#define STEPICON_BIT(No) ((ULONG)0x01000000 << (No)) +#define BITMAP_BIT(No) ((ULONG)0x00100000 << (No)) +#define MENUICON_BIT(No) ((ULONG)0x00020000 << (No)) +#define STATUSICON_BIT(No) ((ULONG)0x00002000 << (No)) +#define SPECIAL_BIT(No) ((ULONG)0x00000100 << (No)) +#define TEXTLINE_BIT(No) ((ULONG)0x00000001 << (No)) + + +typedef struct +{ + void (*pFunc)(UBYTE,UBYTE,UBYTE,UBYTE,UBYTE,UBYTE); // Simple draw entry + + ULONG EraseMask; // Section erase mask (executed first) + ULONG UpdateMask; // Section update mask (executed next) + + FONT *pFont; // Pointer to font file + UBYTE *pTextLines[TEXTLINES]; // Pointer to text strings + + UBYTE *pStatusText; // Pointer to status text string + ICON *pStatusIcons; // Pointer to status icon collection file + + BMPMAP *pScreens[SCREENS]; // Pointer to screen bitmap file + BMPMAP *pBitmaps[BITMAPS]; // Pointer to free bitmap files + + UBYTE *pMenuText; // Pointer to menu icon text (NULL == none) + UBYTE *pMenuIcons[MENUICONS]; // Pointer to menu icon images (NULL == none) + + ICON *pStepIcons; // Pointer to step icon collection file + + UBYTE *Display; // Display content copied to physical display every 17 mS + + UBYTE StatusIcons[STATUSICONS]; // Index in status icon collection file (index = 0 -> none) + + UBYTE StepIcons[STEPICONS]; // Index in step icon collection file (index = 0 -> none) + + UBYTE Flags; // Update flags enumerated above + + UBYTE TextLinesCenterFlags; // Mask to center TextLines + + UBYTE Normal[DISPLAY_HEIGHT / 8][DISPLAY_WIDTH]; // Raw display memory for normal screen + UBYTE Popup[DISPLAY_HEIGHT / 8][DISPLAY_WIDTH]; // Raw display memory for popup screen +} +IOMAPDISPLAY; + +#endif + + + diff --git a/AT91SAM7S256/Source/c_input.c b/AT91SAM7S256/Source/c_input.c new file mode 100644 index 0000000..d17c546 --- /dev/null +++ b/AT91SAM7S256/Source/c_input.c @@ -0,0 +1,777 @@ +// +// Date init 14.12.2004 +// +// Revision date $Date:: 16-05-06 10:06 $ +// +// Filename $Workfile:: c_input.c $ +// +// Version $Revision:: 25 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/c_input.c $ +// +// Platform C +// + +#include "stdconst.h" +#include "modules.h" +#include "c_input.h" +#include "d_input.h" +#include "c_output.iom" + +#define INVALID_RELOAD_NORMAL 20 +#define INVALID_RELOAD_SOUND 300 + +#define ROT_SLOW_SPEED 30 +#define ROT_OV_SAMPLING 7 + +#define VCC_SENSOR 5000L +#define VCC_SENSOR_DIODE 4300L +#define AD_MAX 1023L + +#define REFLECTIONSENSORMIN (1906L/(VCC_SENSOR/AD_MAX)) +#define REFLECTIONSENSORMAX ((AD_MAX * 4398L)/VCC_SENSOR) +#define REFLECTIONSENSORPCTDYN (UBYTE)(((REFLECTIONSENSORMAX - REFLECTIONSENSORMIN) * 100L)/AD_MAX) + +#define NEWLIGHTSENSORMIN (800L/(VCC_SENSOR/AD_MAX)) +#define NEWLIGHTSENSORMAX ((AD_MAX * 4400L)/VCC_SENSOR) +#define NEWLIGHTSENSORPCTDYN (UBYTE)(((NEWLIGHTSENSORMAX - NEWLIGHTSENSORMIN) * 100L)/AD_MAX) + +#define NEWSOUNDSENSORMIN (650L/(VCC_SENSOR/AD_MAX)) +#define NEWSOUNDSENSORMAX ((AD_MAX * 4980L)/VCC_SENSOR) +#define NEWSOUNDSENSORPCTDYN (UBYTE)(((NEWSOUNDSENSORMAX - NEWSOUNDSENSORMIN) * 100L)/AD_MAX) + +enum +{ + POWER = 0x00, + NO_POWER = 0x01, + ACTIVE = 0x02, + ALWAYS_ACTIVE = 0x04, + DIGI_0_HIGH = 0x08, + DIGI_1_HIGH = 0x10, + CUSTOM_SETUP = 0x20 +}; + +static const UBYTE ActiveList[NO_OF_SENSOR_TYPES] = +{ + NO_POWER, /* NO_SENSOR */ + NO_POWER, /* SWITCH */ + NO_POWER, /* TEMPERATURE */ + ACTIVE, /* REFLECTION */ + ACTIVE, /* ANGLE */ + DIGI_0_HIGH, /* LIGHT_ACTIVE */ + POWER, /* LIGHT_INACTIVE */ + DIGI_0_HIGH, /* SOUND_DB */ + DIGI_1_HIGH, /* SOUND_DBA */ + CUSTOM_SETUP, /* CUSTOM */ + DIGI_0_HIGH | DIGI_1_HIGH, /* LOWSPEED */ + ALWAYS_ACTIVE | DIGI_0_HIGH | DIGI_1_HIGH /* LOWSPEED_9V on */ + +}; + +static IOMAPINPUT IOMapInput; +static VARSINPUT VarsInput; + +const HEADER cInput = +{ + 0x00030001L, + "Input", + cInputInit, + cInputCtrl, + cInputExit, + (void *)&IOMapInput, + (void *)&VarsInput, + (UWORD)sizeof(IOMapInput), + (UWORD)sizeof(VarsInput), + 0x0000 //Code size - not used so far +}; + +void cInputCalcSensorRaw(UWORD *pRaw, UBYTE Type, UBYTE No); +void cInputCalcFullScale(UWORD *pRawVal, UWORD ZeroPointOffset, UBYTE PctFullScale, UBYTE InvState); +void cInputCalcSensorValue(UWORD *pRaw, UBYTE Slope, UBYTE Mode, UBYTE Tmp); +void cInputCalcSensor(UBYTE Tmp); +void cInputSetupType(UBYTE Port); +void cInputSetupCustomSensor(UBYTE Port); + + +void cInputInit(void* pHeader) +{ + UBYTE Tmp; + + /* Init IO map */ + for (Tmp = 0; Tmp < NO_OF_INPUTS; Tmp++) + { + IOMapInput.Inputs[Tmp].SensorType = NO_SENSOR; + IOMapInput.Inputs[Tmp].SensorMode = RAWMODE; + IOMapInput.Inputs[Tmp].SensorRaw = 0; + IOMapInput.Inputs[Tmp].SensorValue = 0; + IOMapInput.Inputs[Tmp].SensorBoolean = 0; + IOMapInput.Inputs[Tmp].InvalidData = INVALID_DATA; + IOMapInput.Inputs[Tmp].DigiPinsDir = 0; + IOMapInput.Inputs[Tmp].DigiPinsOut = 0; + IOMapInput.Inputs[Tmp].CustomActiveStatus = CUSTOMINACTIVE; + IOMapInput.Inputs[Tmp].CustomZeroOffset = 0; + IOMapInput.Inputs[Tmp].CustomPctFullScale = 0; + dInputRead0(Tmp, &(IOMapInput.Inputs[Tmp].DigiPinsIn)); + dInputRead1(Tmp, &(IOMapInput.Inputs[Tmp].DigiPinsIn)); + + VarsInput.EdgeCnt[Tmp] = 0; + VarsInput.InputDebounce[Tmp] = 0; + VarsInput.LastAngle[Tmp] = 0; + VarsInput.SampleCnt[Tmp] = 0; + VarsInput.InvalidTimer[Tmp] = INVALID_RELOAD_NORMAL; + VarsInput.OldSensorType[Tmp] = NO_SENSOR; + } + dInputInit(); +} + +void cInputCtrl(void) +{ + UBYTE Tmp; + + for (Tmp = 0; Tmp < NO_OF_INPUTS; Tmp++) + { + + if ((IOMapInput.Inputs[Tmp].SensorType) != (VarsInput.OldSensorType[Tmp])) + { + + /* Clear all variables for this sensor */ + VarsInput.EdgeCnt[Tmp] = 0; + VarsInput.InputDebounce[Tmp] = 0; + VarsInput.LastAngle[Tmp] = 0; + VarsInput.SampleCnt[Tmp] = 0; + + /* Has the type change any influence on pin setup? */ + if ((ActiveList[IOMapInput.Inputs[Tmp].SensorType]) != (ActiveList[VarsInput.OldSensorType[Tmp]])) + { + + /* The type change has influence on pin setup - therefore a delay is inserted */ + /* to ensure valid data representation (delay is: time for data to get down into */ + /* the avr + delay before ad conversion + time for data to get up to the ARM */ + /* processor */ + if ((SOUND_DB == IOMapInput.Inputs[Tmp].SensorType) || (SOUND_DBA == IOMapInput.Inputs[Tmp].SensorType)) + { + + /* Sound Sensors have a long hardware stabilizing time */ + VarsInput.InvalidTimer[Tmp] = INVALID_RELOAD_SOUND; + } + else + { + VarsInput.InvalidTimer[Tmp] = INVALID_RELOAD_NORMAL; + } + + /* Setup the pins for the new sensortype */ + cInputSetupType(Tmp); + IOMapInput.Inputs[Tmp].InvalidData = INVALID_DATA; + } + VarsInput.OldSensorType[Tmp] = IOMapInput.Inputs[Tmp].SensorType; + } + else + { + if (VarsInput.InvalidTimer[Tmp]) + { + + /* A type change has bee carried out earlier - waiting for valid data */ + (VarsInput.InvalidTimer[Tmp])--; + if (0 == VarsInput.InvalidTimer[Tmp]) + { + + /* Time elapsed - data are now valid */ + IOMapInput.Inputs[Tmp].InvalidData &= ~INVALID_DATA; + } + } + else + { + + /* The invalid bit could have been set by the VM due to Mode change */ + /* but input module needs to be called once to update the values */ + IOMapInput.Inputs[Tmp].InvalidData &= ~INVALID_DATA; + } + } + + if (!(INVALID_DATA & (IOMapInput.Inputs[Tmp].InvalidData))) + { + cInputCalcSensor(Tmp); + } + } +} + + +void cInputCalcSensor(UBYTE Tmp) +{ + UWORD InputRaw; + + /* Get the RCX hardware compensated AD values put values in */ + /* InputRaw array */ + dInputGetRawAd(&InputRaw, Tmp); + IOMapInput.Inputs[Tmp].ADRaw = InputRaw; + + /* Calculate the sensor hardware compensated AD values and put then */ + /* in IOMapInput.Inputs[Tmp].SensorRaw */ + cInputCalcSensorRaw(&InputRaw, IOMapInput.Inputs[Tmp].SensorType, Tmp); + + /* Calculate the sensor value compensated for sensor mode and put */ + /* them in IOMapInput.Inputs[Tmp].SensorValue */ + cInputCalcSensorValue( &InputRaw, + ((IOMapInput.Inputs[Tmp].SensorMode) & SLOPEMASK), + ((IOMapInput.Inputs[Tmp].SensorMode) & MODEMASK), + Tmp); + +} + + + +void cInputCalcSensorValue(UWORD *pRaw, UBYTE Slope, UBYTE Mode, UBYTE Tmp) +{ + SWORD Delta; + UBYTE PresentBoolean; + UBYTE Sample; + + if (0 == Slope) + { + + /* This is absolute measure method */ + if (*pRaw > THRESHOLD_FALSE) + { + PresentBoolean = FALSE; + } + else + { + if (*pRaw < THRESHOLD_TRUE) + { + PresentBoolean = TRUE; + } + } + } + else + { + + /* This is dynamic measure method */ + if (*pRaw > (ACTUAL_AD_RES - Slope)) + { + PresentBoolean = FALSE; + } + else + { + if (*pRaw < Slope) + { + PresentBoolean = TRUE; + } + else + { + Delta = IOMapInput.Inputs[Tmp].SensorRaw - *pRaw; + if (Delta < 0) + { + if (-Delta > Slope) + { + PresentBoolean = FALSE; + } + } + else + { + if (Delta > Slope) + { + PresentBoolean = TRUE; + } + } + } + } + } + IOMapInput.Inputs[Tmp].SensorRaw = *pRaw; + + switch(Mode) + { + + case RAWMODE: + { + IOMapInput.Inputs[Tmp].SensorValue = *pRaw; + } + break; + + case BOOLEANMODE: + { + IOMapInput.Inputs[Tmp].SensorValue = PresentBoolean; + } + break; + + case TRANSITIONCNTMODE: + { + if (VarsInput.InputDebounce[Tmp] > 0) + { + VarsInput.InputDebounce[Tmp]--; + } + else + { + if (IOMapInput.Inputs[Tmp].SensorBoolean != PresentBoolean) + { + VarsInput.InputDebounce[Tmp] = DEBOUNCERELOAD; + (IOMapInput.Inputs[Tmp].SensorValue)++; + } + } + } + break; + + case PERIODCOUNTERMODE: + { + if (VarsInput.InputDebounce[Tmp] > 0) + { + VarsInput.InputDebounce[Tmp]--; + } + else + { + if (IOMapInput.Inputs[Tmp].SensorBoolean != PresentBoolean) + { + VarsInput.InputDebounce[Tmp] = DEBOUNCERELOAD; + IOMapInput.Inputs[Tmp].SensorBoolean = PresentBoolean; + if (++VarsInput.EdgeCnt[Tmp] > 1) + { + if (PresentBoolean == 0) + { + VarsInput.EdgeCnt[Tmp] = 0; + (IOMapInput.Inputs[Tmp].SensorValue)++; + } + } + } + } + } + break; + + case PCTFULLSCALEMODE: + { + + /* Output is 0-100 pct */ + IOMapInput.Inputs[Tmp].SensorValue = ((*pRaw) * 100)/SENSOR_RESOLUTION; + } + break; + + case FAHRENHEITMODE: + { + + /* Fahrenheit mode goes from -40 to 158 degrees */ + IOMapInput.Inputs[Tmp].SensorValue = (((ULONG)(*pRaw) * 900L)/SENSOR_RESOLUTION) - 200; + IOMapInput.Inputs[Tmp].SensorValue = ((180L * (ULONG)(IOMapInput.Inputs[Tmp].SensorValue))/100L) + 320; + } + break; + + case CELSIUSMODE: + { + + /* Celsius mode goes from -20 to 70 degrees */ + IOMapInput.Inputs[Tmp].SensorValue = (((ULONG)(*pRaw) * 900L)/SENSOR_RESOLUTION) - 200; + } + break; + + case ANGLESTEPSMODE: + { + IOMapInput.Inputs[Tmp].SensorBoolean = PresentBoolean; + + if (*pRaw < ANGLELIMITA) + { + Sample = 0; + } + else + { + if (*pRaw < ANGLELIMITB) + { + Sample = 1; + } + else + { + if (*pRaw < ANGLELIMITC) + { + Sample = 2; + } + else + { + Sample = 3; + } + } + } + + switch (VarsInput.LastAngle[Tmp]) + { + case 0 : + { + if (Sample == 1) + { + if (VarsInput.SampleCnt[Tmp] >= ROT_SLOW_SPEED ) + { + + if (++(VarsInput.SampleCnt[Tmp]) >= (ROT_SLOW_SPEED + ROT_OV_SAMPLING)) + { + (IOMapInput.Inputs[Tmp].SensorValue)++; + VarsInput.LastAngle[Tmp] = Sample; + } + } + else + { + (IOMapInput.Inputs[Tmp].SensorValue)++; + VarsInput.LastAngle[Tmp] = Sample; + } + } + if (Sample == 2) + { + (IOMapInput.Inputs[Tmp].SensorValue)--; + VarsInput.LastAngle[Tmp] = Sample; + } + if (Sample == 0) + { + if (VarsInput.SampleCnt[Tmp] < ROT_SLOW_SPEED) + { + (VarsInput.SampleCnt[Tmp])++; + } + } + } + break; + case 1 : + { + if (Sample == 3) + { + (IOMapInput.Inputs[Tmp].SensorValue)++; + VarsInput.LastAngle[Tmp] = Sample; + } + if (Sample == 0) + { + (IOMapInput.Inputs[Tmp].SensorValue)--; + VarsInput.LastAngle[Tmp] = Sample; + } + VarsInput.SampleCnt[Tmp] = 0; + } + break; + case 2 : + { + if (Sample == 0) + { + (IOMapInput.Inputs[Tmp].SensorValue)++; + VarsInput.LastAngle[Tmp] = Sample; + } + if (Sample == 3) + { + (IOMapInput.Inputs[Tmp].SensorValue)--; + VarsInput.LastAngle[Tmp] = Sample; + } + VarsInput.SampleCnt[Tmp] = 0; + } + break; + case 3 : + { + if (Sample == 2) + { + if (VarsInput.SampleCnt[Tmp] >= ROT_SLOW_SPEED) + { + + if (++(VarsInput.SampleCnt[Tmp]) >= (ROT_SLOW_SPEED + ROT_OV_SAMPLING)) + { + (IOMapInput.Inputs[Tmp].SensorValue)++; + VarsInput.LastAngle[Tmp] = Sample; + } + } + else + { + (IOMapInput.Inputs[Tmp].SensorValue)++; + VarsInput.LastAngle[Tmp] = Sample; + } + } + if (Sample == 1) + { + (IOMapInput.Inputs[Tmp].SensorValue)--; + VarsInput.LastAngle[Tmp] = Sample; + } + if (Sample == 3) + { + if (VarsInput.SampleCnt[Tmp] < ROT_SLOW_SPEED) + { + (VarsInput.SampleCnt[Tmp])++; + } + } + } + break; + } + } + } + + IOMapInput.Inputs[Tmp].SensorBoolean = PresentBoolean; +} + + +const SWORD TempConvTable[] = +{ + 1500, 1460, 1430, 1400, 1380, 1360, 1330, 1310, 1290, 1270, 1250, 1230, 1220, 1200, 1190, 1170, + 1160, 1150, 1140, 1130, 1110, 1100, 1090, 1080, 1070, 1060, 1050, 1040, 1030, 1020, 1010, 1000, + 994, 988, 982, 974, 968, 960, 954, 946, 940, 932, 926, 918, 912, 906, 900, 894, + 890, 884, 878, 874, 868, 864, 858, 854, 848, 844, 838, 832, 828, 822, 816, 812, + 808, 802, 798, 794, 790, 786, 782, 780, 776, 772, 768, 764, 762, 758, 754, 750, + 748, 744, 740, 736, 732, 730, 726, 722, 718, 716, 712, 708, 704, 700, 696, 694, + 690, 688, 684, 682, 678, 674, 672, 668, 666, 662, 660, 656, 654, 650, 648, 644, + 642, 640, 638, 634, 632, 630, 628, 624, 622, 620, 616, 614, 612, 610, 608, 604, + 602, 600, 598, 596, 592, 590, 588, 586, 584, 582, 580, 578, 576, 574, 572, 570, + 568, 564, 562, 560, 558, 556, 554, 552, 550, 548, 546, 544, 542, 540, 538, 536, + 534, 532, 530, 528, 526, 524, 522, 520, 518, 516, 514, 512, 510, 508, 508, 506, + 504, 502, 500, 498, 496, 494, 494, 492, 490, 488, 486, 486, 484, 482, 480, 478, + 476, 476, 474, 472, 470, 468, 468, 466, 464, 462, 460, 458, 458, 456, 454, 452, + 450, 448, 448, 446, 444, 442, 442, 440, 438, 436, 436, 434, 432, 432, 430, 428, + 426, 426, 424, 422, 420, 420, 418, 416, 416, 414, 412, 410, 408, 408, 406, 404, + 404, 402, 400, 398, 398, 396, 394, 394, 392, 390, 390, 388, 386, 386, 384, 382, + 382, 380, 378, 378, 376, 374, 374, 372, 370, 370, 368, 366, 366, 364, 362, 362, + 360, 358, 358, 356, 354, 354, 352, 350, 350, 348, 348, 346, 344, 344, 342, 340, + 340, 338, 338, 336, 334, 334, 332, 332, 330, 328, 328, 326, 326, 324, 322, 322, + 320, 320, 318, 316, 316, 314, 314, 312, 310, 310, 308, 308, 306, 304, 304, 302, + 300, 300, 298, 298, 296, 296, 294, 292, 292, 290, 290, 288, 286, 286, 284, 284, + 282, 282, 280, 280, 278, 278, 276, 274, 274, 272, 272, 270, 270, 268, 268, 266, + 264, 264, 262, 262, 260, 260, 258, 258, 256, 254, 254, 252, 252, 250, 250, 248, + 248, 246, 244, 244, 242, 240, 240, 240, 238, 238, 236, 236, 234, 234, 232, 230, + 230, 228, 228, 226, 226, 224, 224, 222, 220, 220, 218, 218, 216, 216, 214, 214, + 212, 212, 210, 210, 208, 208, 206, 204, 204, 202, 202, 200, 200, 198, 198, 196, + 196, 194, 194, 192, 190, 190, 188, 188, 186, 186, 184, 184, 182, 182, 180, 180, + 178, 178, 176, 176, 174, 174, 172, 172, 170, 170, 168, 168, 166, 166, 164, 164, + 162, 162, 160, 160, 158, 156, 156, 154, 154, 152, 152, 150, 150, 148, 148, 146, + 146, 144, 144, 142, 142, 140, 140, 138, 136, 136, 136, 134, 134, 132, 130, 130, + 128, 128, 126, 126, 124, 124, 122, 122, 120, 120, 118, 118, 116, 116, 114, 114, + 112, 110, 110, 108, 108, 106, 106, 104, 104, 102, 102, 100, 100, 98, 98, 96, + 94, 94, 92, 92, 90, 90, 88, 88, 86, 86, 84, 82, 82, 80, 80, 78, + 78, 76, 76, 74, 74, 72, 72, 70, 70, 68, 68, 66, 66, 64, 62, 62, + 60, 60, 58, 56, 56, 54, 54, 52, 52, 50, 50, 48, 48, 46, 46, 44, + 44, 42, 40, 40, 38, 38, 36, 34, 34, 32, 32, 30, 30, 28, 28, 26, + 24, 24, 22, 22, 20, 20, 18, 16, 16, 14, 14, 12, 12, 10, 10, 8, + 6, 6, 4, 2, 2, 0, 0, -2, -4, -4, -6, -6, -8, -10, -10, -12, + -12, -14, -16, -16, -18, -20, -20, -22, -22, -24, -26, -26, -28, -30, -30, -32, + -34, -34, -36, -36, -38, -40, -40, -42, -42, -44, -46, -46, -48, -50, -50, -52, + -54, -54, -56, -58, -58, -60, -60, -62, -64, -66, -66, -68, -70, -70, -72, -74, + -76, -76, -78, -80, -80, -82, -84, -86, -86, -88, -90, -90, -92, -94, -94, -96, + -98, -98, -100, -102, -104, -106, -106, -108, -110, -112, -114, -114, -116, -118, -120, -120, + -122, -124, -126, -128, -130, -130, -132, -134, -136, -138, -140, -142, -144, -146, -146, -148, + -150, -152, -154, -156, -158, -160, -162, -164, -166, -166, -168, -170, -172, -174, -176, -178, + -180, -182, -184, -186, -188, -190, -192, -194, -196, -196, -198, -200, -202, -204, -206, -208, + -210, -212, -214, -216, -218, -220, -224, -226, -228, -230, -232, -234, -236, -238, -242, -246, + -248, -250, -254, -256, -260, -262, -264, -268, -270, -274, -276, -278, -282, -284, -286, -290, + -292, -296, -298, -300, -306, -308, -312, -316, -320, -324, -326, -330, -334, -338, -342, -344, + -348, -354, -358, -362, -366, -370, -376, -380, -384, -388, -394, -398, -404, -410, -416, -420, + -428, -432, -440, -446, -450, -460, -468, -476, -484, -492, -500, -510, -524, -534, -546, -560, + -572, -588, -600, -630, -656, -684, -720, -770 +}; + + +void cInputCalcSensorRaw(UWORD *pRaw, UBYTE Type, UBYTE No) +{ + + switch (Type) + { + case SWITCH: + { + } + break; + case TEMPERATURE: + { + if (*pRaw < 290) + { + *pRaw = 290; + } + else + { + if (*pRaw > 928) + { + *pRaw = 928; + } + } + *pRaw = TempConvTable[(*pRaw) - 197]; + *pRaw = *pRaw + 200; + *pRaw = (UWORD)(((SLONG)*pRaw * (SLONG)1023)/(SLONG)900); + } + break; + case REFLECTION: + { + + /* Sensor dynanmic is restricted by a double diode connected to ground, */ + /* and it cannot go to the top either, dynamic is approx. 390 - 900 count*/ + cInputCalcFullScale(pRaw, REFLECTIONSENSORMIN, REFLECTIONSENSORPCTDYN, TRUE); + } + break; + case ANGLE: + { + } + break; + case LIGHT_ACTIVE: + { + cInputCalcFullScale(pRaw, NEWLIGHTSENSORMIN, NEWLIGHTSENSORPCTDYN, TRUE); + } + break; + case LIGHT_INACTIVE: + { + cInputCalcFullScale(pRaw, NEWLIGHTSENSORMIN, NEWLIGHTSENSORPCTDYN, TRUE); + } + break; + case SOUND_DB: + { + cInputCalcFullScale(pRaw, NEWSOUNDSENSORMIN, NEWSOUNDSENSORPCTDYN, TRUE); + } + break; + case SOUND_DBA: + { + cInputCalcFullScale(pRaw, NEWSOUNDSENSORMIN, NEWSOUNDSENSORPCTDYN, TRUE); + } + break; + case LOWSPEED: + { + /* Intended empty Low Speed module takes over */ + } + break; + case HIGHSPEED: + { + } + break; + case CUSTOM: + { + + /* Setup and read digital IO */ + cInputSetupCustomSensor(No); + dInputRead0(No, &(IOMapInput.Inputs[No].DigiPinsIn)); + dInputRead1(No, &(IOMapInput.Inputs[No].DigiPinsIn)); + cInputCalcFullScale(pRaw, IOMapInput.Inputs[No].CustomZeroOffset, IOMapInput.Inputs[No].CustomPctFullScale, FALSE); + } + break; + case NO_SENSOR: + { + } + break; + default: + { + } + break; + } +} + +void cInputCalcFullScale(UWORD *pRawVal, UWORD ZeroPointOffset, UBYTE PctFullScale, UBYTE InvStatus) +{ + if (*pRawVal >= ZeroPointOffset) + { + *pRawVal -= ZeroPointOffset; + } + else + { + *pRawVal = 0; + } + + *pRawVal = (*pRawVal * 100)/PctFullScale; + if (*pRawVal > SENSOR_RESOLUTION) + { + *pRawVal = SENSOR_RESOLUTION; + } + if (TRUE == InvStatus) + { + *pRawVal = SENSOR_RESOLUTION - *pRawVal; + } +} + +void cInputSetupType(UBYTE Port) +{ + UBYTE Setup; + + Setup = (ActiveList[IOMapInput.Inputs[Port].SensorType]); + + if (CUSTOM_SETUP & Setup) + { + cInputSetupCustomSensor(Port); + } + else + { + if (NO_POWER & Setup) + { + + /* Setup is not used - set pins in unconfigured state */ + dInputSetInactive(Port); + dInputSetDirInDigi0(Port); + dInputSetDirInDigi1(Port); + } + else + { + if (ACTIVE & Setup) + { + dInputSetActive(Port); + } + else + { + if(ALWAYS_ACTIVE & Setup) + { + dInputSet9v(Port); + } + else + { + dInputSetInactive(Port); + } + } + if (DIGI_0_HIGH & Setup) + { + dInputSetDigi0(Port); + dInputSetDirOutDigi0(Port); + } + else + { + dInputClearDigi0(Port); + dInputSetDirOutDigi0(Port); + } + + if (DIGI_1_HIGH & Setup) + { + dInputSetDigi1(Port); + dInputSetDirOutDigi1(Port); + } + else + { + dInputClearDigi1(Port); + dInputSetDirOutDigi1(Port); + } + } + } +} + +void cInputSetupCustomSensor(UBYTE Port) +{ + if ((IOMapInput.Inputs[Port].DigiPinsDir) & 0x01) + { + if ((IOMapInput.Inputs[Port].DigiPinsOut) & 0x01) + { + dInputSetDigi0(Port); + } + else + { + dInputClearDigi0(Port); + } + dInputSetDirOutDigi0(Port); + } + if ((IOMapInput.Inputs[Port].DigiPinsDir) & 0x02) + { + if ((IOMapInput.Inputs[Port].DigiPinsOut) & 0x02) + { + dInputSetDigi1(Port); + } + else + { + dInputClearDigi1(Port); + } + dInputSetDirOutDigi1(Port); + } + else + { + dInputSetDirInDigi1(Port); + } + + if (CUSTOMACTIVE == (IOMapInput.Inputs[Port].CustomActiveStatus)) + { + dInputSetActive(Port); + } + else + { + if (CUSTOM9V == (IOMapInput.Inputs[Port].CustomActiveStatus)) + { + dInputSet9v(Port); + } + else + { + dInputSetInactive(Port); + } + } +} + +void cInputExit(void) +{ + dInputExit(); +} diff --git a/AT91SAM7S256/Source/c_input.h b/AT91SAM7S256/Source/c_input.h new file mode 100644 index 0000000..dfa981b --- /dev/null +++ b/AT91SAM7S256/Source/c_input.h @@ -0,0 +1,53 @@ +// +// Date init 14.12.2004 +// +// Revision date $Date:: 16-05-06 10:06 $ +// +// Filename $Workfile:: c_input.h $ +// +// Version $Revision:: 9 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/c_input.h $ +// +// Platform C +// + +#ifndef C_INPUT +#define C_INPUT + +#ifdef INCLUDE_OS +extern const HEADER cInput; +#endif + +#include "c_input.iom" + +#define ACTUAL_AD_RES 1023L +#define SENSOR_RESOLUTION 1023L +#define DEBOUNCERELOAD 100 +#define THRESHOLD_FALSE (UWORD)(ACTUAL_AD_RES * 45L / 100L) +#define THRESHOLD_TRUE (UWORD)(ACTUAL_AD_RES * 55L / 100L) + +#define ANGLELIMITA (UWORD)(ACTUAL_AD_RES * 4400L / 10000L) +#define ANGLELIMITB (UWORD)(ACTUAL_AD_RES * 6600L / 10000L) +#define ANGLELIMITC (UWORD)(ACTUAL_AD_RES * 8900L / 10000L) + +#define FWDDIR 1 +#define RWDDIR 2 +#define MAXSAMPLECNT 5 + +typedef struct +{ + UWORD InvalidTimer[NO_OF_INPUTS]; + UBYTE InputDebounce[NO_OF_INPUTS]; + UBYTE EdgeCnt[NO_OF_INPUTS]; + UBYTE LastAngle[NO_OF_INPUTS]; + UBYTE OldSensorType[NO_OF_INPUTS]; + UBYTE SampleCnt[NO_OF_INPUTS]; +}VARSINPUT; + +void cInputInit(void* pHeader); +void cInputCtrl(void); +void cInputExit(void); + + +#endif diff --git a/AT91SAM7S256/Source/c_input.iom b/AT91SAM7S256/Source/c_input.iom new file mode 100644 index 0000000..8d651b8 --- /dev/null +++ b/AT91SAM7S256/Source/c_input.iom @@ -0,0 +1,109 @@ +// +// Date init 14.12.2004 +// +// Revision date $Date:: 16-05-06 10:06 $ +// +// Filename $Workfile:: c_input.iom $ +// +// Version $Revision:: 15 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/c_input.io $ +// +// Platform C +// + +#ifndef CINPUT_IOM +#define CINPUT_IOM + +#define NO_OF_INPUTS 4 +#define pMapInput ((IOMAPINPUT*)(pHeaders[ENTRY_INPUT]->pIOMap)) + + +/* Constants related to sensor type */ +enum +{ + NO_SENSOR = 0, + SWITCH = 1, + TEMPERATURE = 2, + REFLECTION = 3, + ANGLE = 4, + LIGHT_ACTIVE = 5, + LIGHT_INACTIVE = 6, + SOUND_DB = 7, + SOUND_DBA = 8, + CUSTOM = 9, + LOWSPEED = 10, + LOWSPEED_9V = 11, + HIGHSPEED = 12, + NO_OF_SENSOR_TYPES = 13 +}; + +/* Constants related to sensor mode */ +enum +{ + RAWMODE = 0x00, + BOOLEANMODE = 0x20, + TRANSITIONCNTMODE = 0x40, + PERIODCOUNTERMODE = 0x60, + PCTFULLSCALEMODE = 0x80, + CELSIUSMODE = 0xA0, + FAHRENHEITMODE = 0xC0, + ANGLESTEPSMODE = 0xE0, + SLOPEMASK = 0x1F, + MODEMASK = 0xE0 +}; + +/* Constants related to Digital I/O */ +enum +{ + DIGI0 = 1, + DIGI1 = 2 +}; + +enum +{ + CUSTOMINACTIVE = 0x00, + CUSTOM9V = 0x01, + CUSTOMACTIVE = 0x02 +}; + +enum +{ + INVALID_DATA = 0x01 +}; + +typedef struct +{ + UWORD CustomZeroOffset; /* Set the offset of the custom sensor */ + UWORD ADRaw; + UWORD SensorRaw; + SWORD SensorValue; + + UBYTE SensorType; + UBYTE SensorMode; + UBYTE SensorBoolean; + + UBYTE DigiPinsDir; /* Direction of the Digital pins 1 is output 0 is input */ + UBYTE DigiPinsIn; /* Contains the status of the digital pins */ + UBYTE DigiPinsOut; /* Sets the output level of the digital pins */ + UBYTE CustomPctFullScale; /* Sets the Pct full scale of the custom sensor */ + UBYTE CustomActiveStatus; /* Sets the active or inactive state of the custom sensor */ + + UBYTE InvalidData; /* Indicates wether data is invalid (1) or valid (0) */ + + UBYTE Spare1; + UBYTE Spare2; + UBYTE Spare3; + +}INPUT; + + +typedef struct +{ + INPUT Inputs[NO_OF_INPUTS]; +}IOMAPINPUT; + +#endif + + + diff --git a/AT91SAM7S256/Source/c_ioctrl.c b/AT91SAM7S256/Source/c_ioctrl.c new file mode 100644 index 0000000..2964f33 --- /dev/null +++ b/AT91SAM7S256/Source/c_ioctrl.c @@ -0,0 +1,78 @@ +// +// Date init 14.12.2004 +// +// Revision date $Date:: 16-05-06 9:50 $ +// +// Filename $Workfile:: c_ioctrl.c $ +// +// Version $Revision:: 13 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/c_ioctrl.c $ +// +// Platform C +// + + +#include "stdconst.h" +#include "modules.h" +#include "c_ioctrl.iom" +#include "c_ioctrl.h" +#include "d_ioctrl.h" + +static IOMAPIOCTRL IOMapIOCtrl; +static VARSIOCTRL VarsIOCtrl; + +const HEADER cIOCtrl = +{ + 0x00060001L, + "IOCtrl", + cIOCtrlInit, + cIOCtrlCtrl, + cIOCtrlExit, + (void *)&IOMapIOCtrl, + (void *)&VarsIOCtrl, + (UWORD)sizeof(IOMapIOCtrl), + (UWORD)sizeof(VarsIOCtrl), + 0x0000 //Code size - not used so far +}; + + +void cIOCtrlInit(void* pHeader) +{ + dIOCtrlSetPower(0); + dIOCtrlInit(); +} + + +void cIOCtrlCtrl(void) +{ + switch(IOMapIOCtrl.PowerOn) + { + case POWERDOWN: + { + dIOCtrlSetPower((POWERDOWN>>8)); + } + break; + case BOOT: + { + dIOCtrlSetPower((UBYTE)(BOOT>>8)); + dIOCtrlSetPwm((UBYTE)BOOT); + } + break; + default: + { + /* No need to change the default value */ + /* if value is boot or reset it should come */ + /* back from reset - setting the value to 0 */ + } + break; + } + dIOCtrlTransfer(); +} + + +void cIOCtrlExit(void) +{ + dIOCtrlExit(); +} + diff --git a/AT91SAM7S256/Source/c_ioctrl.h b/AT91SAM7S256/Source/c_ioctrl.h new file mode 100644 index 0000000..a2bd892 --- /dev/null +++ b/AT91SAM7S256/Source/c_ioctrl.h @@ -0,0 +1,28 @@ +// +// Date init 14.12.2004 +// +// Revision date $Date:: 16-05-06 9:50 $ +// +// Filename $Workfile:: c_ioctrl.h $ +// +// Version $Revision:: 4 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/c_ioctrl.h $ +// +// Platform C +// + +#ifndef C_IOCTRL +#define C_IOCTRL + +typedef struct +{ + UBYTE Tmp; +}VARSIOCTRL; + +void cIOCtrlInit(void* pHeader); +void cIOCtrlCtrl(void); +void cIOCtrlExit(void); + +extern const HEADER cIOCtrl; +#endif diff --git a/AT91SAM7S256/Source/c_ioctrl.iom b/AT91SAM7S256/Source/c_ioctrl.iom new file mode 100644 index 0000000..3385caa --- /dev/null +++ b/AT91SAM7S256/Source/c_ioctrl.iom @@ -0,0 +1,35 @@ +// +// Date init 14.12.2004 +// +// Revision date $Date:: 16-05-06 9:50 $ +// +// Filename $Workfile:: c_ioctrl.iom $ +// +// Version $Revision:: 8 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/c_ioctrl.i $ +// +// Platform C +// + +#ifndef CIOCTRL_IOM +#define CIOCTRL_IOM + +#define pMapIoCtrl ((IOMAPIOCTRL*)(pHeaders[ENTRY_IOCTRL]->pIOMap)) + +enum +{ + POWERDOWN = 0x5A00, + BOOT = 0xA55A +}; + +typedef struct +{ + UWORD PowerOn; +}IOMAPIOCTRL; + + +#endif + + + diff --git a/AT91SAM7S256/Source/c_loader.c b/AT91SAM7S256/Source/c_loader.c new file mode 100644 index 0000000..8b43bd8 --- /dev/null +++ b/AT91SAM7S256/Source/c_loader.c @@ -0,0 +1,458 @@ +// +// Date init 14.12.2004 +// +// Revision date $Date:: 16-05-06 8:27 $ +// +// Filename $Workfile:: c_loader.c $ +// +// Version $Revision:: 79 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/c_loader.c $ +// +// Platform C +// + +#include "stdconst.h" +#include "modules.h" +#include "c_loader.iom" +#include "c_ioctrl.iom" +#include "d_loader.h" +#include "c_loader.h" + +static IOMAPLOADER IOMapLoader; +static VARSLOADER VarsLoader; +static HEADER **pHeaders; + +const HEADER cLoader = +{ + 0x00090001L, + "Loader", + cLoaderInit, + cLoaderCtrl, + cLoaderExit, + (void *)&IOMapLoader, + (void *)&VarsLoader, + (UWORD)sizeof(IOMapLoader), + (UWORD)sizeof(VarsLoader), + 0x0000 //Code size - not used so far +}; + +UWORD cLoaderFileRq(UBYTE Cmd, UBYTE *pFileName, UBYTE *pBuffer, ULONG *pLength); +UWORD cLoaderGetIoMapInfo(ULONG ModuleId, UBYTE *pIoMap, UWORD *pIoMapSize); +UWORD cLoaderFindModule(UBYTE *pBuffer); +void cLoaderGetModuleName(UBYTE *pDst, UBYTE *pModule); + +void cLoaderInit(void* pHeader) +{ + + IOMapLoader.pFunc = &cLoaderFileRq; + VarsLoader.IoMapHandle = FALSE; + pHeaders = pHeader; + dLoaderInit(); + IOMapLoader.FreeUserFlash = dLoaderReturnFreeUserFlash(); +} + +void cLoaderCtrl(void) +{ +} + + + +UWORD cLoaderFileRq(UBYTE Cmd, UBYTE *pFileName, UBYTE *pBuffer, ULONG *pLength) +{ + UWORD ReturnState; + + ReturnState = SUCCESS; + + switch(Cmd) + { + case OPENREAD: + { + ReturnState = dLoaderOpenRead(pFileName, pLength); + if (0x8000 <= ReturnState) + { + dLoaderCloseHandle(ReturnState); + } + } + break; + case OPENREADLINEAR: + { + ReturnState = dLoaderGetFilePtr(pFileName, pBuffer, pLength); + if (0x8000 <= ReturnState) + { + dLoaderCloseHandle(ReturnState); + } + + } + break; + case OPENWRITE: + { + + /* This is to create a new file */ + ReturnState = dLoaderCreateFileHeader(*pLength, pFileName, (UBYTE) NONLINEAR, SYSTEMFILE); + if (0x8000 <= ReturnState) + { + dLoaderCloseHandle(ReturnState); + } + else + { + IOMapLoader.FreeUserFlash = dLoaderReturnFreeUserFlash(); + } + } + break; + case OPENWRITELINEAR: + { + ReturnState = dLoaderCreateFileHeader(*pLength, pFileName, (UBYTE) LINEAR, SYSTEMFILE); + if (0x8000 <= ReturnState) + { + dLoaderCloseHandle(ReturnState); + } + else + { + IOMapLoader.FreeUserFlash = dLoaderReturnFreeUserFlash(); + } + } + break; + case OPENWRITEDATA: + { + + ReturnState = dLoaderCreateFileHeader(*pLength, pFileName, (UBYTE) LINEAR, DATAFILE); + if (0x8000 <= ReturnState) + { + dLoaderCloseHandle(ReturnState); + } + else + { + IOMapLoader.FreeUserFlash = dLoaderReturnFreeUserFlash(); + } + } + break; + case OPENAPPENDDATA: + { + ReturnState = dLoaderOpenAppend(pFileName, pLength); + if (LOADER_ERR(ReturnState) != SUCCESS) + { + dLoaderCloseHandle(ReturnState); + } + } + break; + case CLOSE: + { + ReturnState = dLoaderCloseHandle(*pFileName); + } + break; + case READ: + { + ReturnState = dLoaderRead(*pFileName, pBuffer, pLength); + } + break; + case WRITE: + { + ReturnState = dLoaderWriteData(*pFileName, pBuffer, (UWORD*)pLength); + } + break; + case FINDFIRST: + { + ULONG DataLength; + + ReturnState = dLoaderFind(pFileName, pBuffer, pLength, &DataLength, (UBYTE) SEARCHING); + if (0x8000 <= ReturnState) + { + dLoaderCloseHandle(ReturnState); + } + } + break; + case FINDNEXT: + { + UWORD Handle; + ULONG DataLength; + + Handle = *pFileName; + ReturnState = dLoaderFindNext(Handle, pBuffer, pLength, &DataLength); + } + break; + case DELETE: + { + ReturnState = dLoaderDelete(pFileName); + IOMapLoader.FreeUserFlash = dLoaderReturnFreeUserFlash(); + + } + break; + case DELETEUSERFLASH: + { + dLoaderDeleteAllFiles(); + IOMapLoader.FreeUserFlash = dLoaderReturnFreeUserFlash(); + + } + break; + + case FINDFIRSTMODULE: + { + if (FALSE == VarsLoader.IoMapHandle) + { + VarsLoader.IoMapHandle = TRUE; + VarsLoader.ModSearchIndex = 0; + dLoaderInsertSearchStr(VarsLoader.ModSearchStr, pFileName, &(VarsLoader.ModSearchType)); + ReturnState = cLoaderFindModule(pBuffer); + } + else + { + ReturnState = NOMOREHANDLES; + } + } + break; + + case FINDNEXTMODULE: + { + ReturnState = cLoaderFindModule(pBuffer); + } + break; + + case CLOSEMODHANDLE: + { + VarsLoader.IoMapHandle = FALSE; + ReturnState = SUCCESS; + } + break; + + case IOMAPREAD: + { + + UBYTE *pIoMap; + ULONG Ptr; + UWORD IoMapSize; + UBYTE Tmp; + + pIoMap = NULL; + ReturnState = cLoaderGetIoMapInfo((*(ULONG*)(pFileName)),(UBYTE*)(&pIoMap), &IoMapSize); + + /* Did we have a valid module ID ?*/ + if (SUCCESS == LOADER_ERR(ReturnState)) + { + + /* This is the offset */ + Ptr = pBuffer[0]; + Ptr |= (UWORD)pBuffer[1] << 8; + + /* is the offset within the limits of the iomap size? */ + if ((Ptr + *pLength) <= IoMapSize) + { + + /* Add the offset to the pointer */ + pIoMap += Ptr; + + for (Tmp = 0; Tmp < *pLength; Tmp++) + { + pBuffer[Tmp + 2] = *pIoMap; + pIoMap++; + } + } + else + { + + /* Error - not within the bounderies */ + ReturnState = OUTOFBOUNDERY; + *pLength = 0; + } + } + else + { + + /* Error - not a valid module id */ + *pLength = 0; + } + } + break; + + case IOMAPWRITE: + { + UBYTE *pIoMap; + ULONG Ptr; + UWORD IoMapSize; + UWORD Tmp; + + + pIoMap = NULL; + ReturnState = cLoaderGetIoMapInfo(*((ULONG*)pFileName), (UBYTE*)&pIoMap, &IoMapSize); + + if (LOADER_ERR(ReturnState) == SUCCESS) + { + + /* This is the offset */ + Ptr = *pBuffer; + pBuffer++; + Tmp = *pBuffer; + Ptr |= Tmp << 8; + pBuffer++; + + if ((Ptr + *pLength) <= IoMapSize) + { + + pIoMap += Ptr; + for (Tmp = 0; Tmp < *pLength; Tmp++) + { + *pIoMap = pBuffer[Tmp]; + pIoMap++; + } + } + else + { + + /* Error - not within the bounderies */ + ReturnState = OUTOFBOUNDERY; + *pLength = 0; + } + } + else + { + + /* Error - not a valid module id */ + *pLength = 0; + } + } + break; + + case RENAMEFILE: + { + UBYTE FoundName[FILENAME_LENGTH + 1]; + + /* Check for file exists*/ + ReturnState = dLoaderFind(pBuffer, FoundName, pLength, pLength, (UBYTE) SEARCHING); + dLoaderCloseHandle(LOADER_HANDLE(ReturnState)); + if (FILENOTFOUND == LOADER_ERR(ReturnState)) + { + ReturnState = dLoaderFind(pFileName, FoundName, pLength, pLength, (UBYTE) SEARCHING); + if (ReturnState < 0x8000) + { + ReturnState = dLoaderCheckFiles((UBYTE) ReturnState); + if (ReturnState < 0x8000) + { + dLoaderRenameFile((UBYTE) ReturnState, pBuffer); + } + } + dLoaderCloseHandle(LOADER_HANDLE(ReturnState)); + } + else + { + if (SUCCESS == LOADER_ERR(ReturnState)) + { + ReturnState |= FILEEXISTS; + } + } + } + break; + + default: + { + } + break; + } + return (ReturnState); +} + +UWORD cLoaderGetIoMapInfo(ULONG ModuleId, UBYTE *pIoMap, UWORD *pIoMapSize) +{ + UBYTE Tmp; + UBYTE Exit; + UWORD RtnVal; + + RtnVal = SUCCESS; + Tmp = 0; + Exit = FALSE; + while((Tmp < 32) && (Exit == FALSE)) + { + if ((*(pHeaders[Tmp])).ModuleID == ModuleId) + { + Exit = TRUE; + } + else + { + Tmp++; + } + } + + /* Did we have a valid module ID ?*/ + if (TRUE == Exit) + { + /* Get the pointer of the module io map */ + *((ULONG *)pIoMap) = (ULONG)((*(pHeaders[Tmp])).pIOMap); + *pIoMapSize = (*(pHeaders[Tmp])).IOMapSize; + } + else + { + RtnVal = MODULENOTFOUND; + } + + /* To avoid a warning - this is optimized away */ + *pIoMap = *pIoMap; + return(RtnVal); +} + +UWORD cLoaderFindModule(UBYTE *pBuffer) +{ + UBYTE Tmp; + UWORD RtnVal; + UBYTE ModuleName[FILENAME_SIZE]; + + RtnVal = MODULENOTFOUND; + + for (Tmp = VarsLoader.ModSearchIndex; Tmp < 32; Tmp++) + { + if (pHeaders[Tmp] != 0) + { + + cLoaderGetModuleName(ModuleName, ((*(pHeaders[Tmp])).ModuleName)); + if (SUCCESS == dLoaderCheckName(ModuleName, VarsLoader.ModSearchStr, VarsLoader.ModSearchType)) + { + + dLoaderCopyFileName(pBuffer, ModuleName); + + pBuffer[FILENAME_SIZE] = (UBYTE) ((*(pHeaders[Tmp])).ModuleID); + pBuffer[FILENAME_SIZE + 1] = (UBYTE)(((*(pHeaders[Tmp])).ModuleID) >> 8); + pBuffer[FILENAME_SIZE + 2] = (UBYTE)(((*(pHeaders[Tmp])).ModuleID) >> 16); + pBuffer[FILENAME_SIZE + 3] = (UBYTE)(((*(pHeaders[Tmp])).ModuleID) >> 24); + + pBuffer[FILENAME_SIZE + 4] = (UBYTE)(((*(pHeaders[Tmp])).ModuleSize)); + pBuffer[FILENAME_SIZE + 5] = (UBYTE)(((*(pHeaders[Tmp])).ModuleSize) >> 8); + pBuffer[FILENAME_SIZE + 6] = (UBYTE)(((*(pHeaders[Tmp])).ModuleSize) >> 16); + pBuffer[FILENAME_SIZE + 7] = (UBYTE)(((*(pHeaders[Tmp])).ModuleSize) >> 24); + + pBuffer[FILENAME_SIZE + 8] = (UBYTE) ((*(pHeaders[Tmp])).IOMapSize); + pBuffer[FILENAME_SIZE + 9] = (UBYTE)(((*(pHeaders[Tmp])).IOMapSize) >> 8); + + RtnVal = SUCCESS; + (VarsLoader.ModSearchIndex) = Tmp + 1; + Tmp = 32; + } + } + } + return(RtnVal); +} + +void cLoaderGetModuleName(UBYTE *pDst, UBYTE *pModule) +{ + UBYTE Tmp; + + for(Tmp = 0; Tmp < FILENAME_SIZE; Tmp++) + { + if (0 != pModule[Tmp]) + { + pDst[Tmp] = pModule[Tmp]; + } + else + { + pDst[Tmp++] = '.'; + pDst[Tmp++] = 'm'; + pDst[Tmp++] = 'o'; + pDst[Tmp++] = 'd'; + pDst[Tmp] = '\0'; + Tmp = FILENAME_SIZE; + } + } +} + +void cLoaderExit(void) +{ +} + + diff --git a/AT91SAM7S256/Source/c_loader.h b/AT91SAM7S256/Source/c_loader.h new file mode 100644 index 0000000..a720c37 --- /dev/null +++ b/AT91SAM7S256/Source/c_loader.h @@ -0,0 +1,44 @@ +// +// Date init 14.12.2004 +// +// Revision date $Date:: 16-05-06 8:27 $ +// +// Filename $Workfile:: c_loader.h $ +// +// Version $Revision:: 8 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/c_loader.h $ +// +// Platform C +// + +#ifndef C_LOADER +#define C_LOADER + +enum +{ + LOADER_BUSY, + TOO_MANY_FILES, + NO_MORE_FLASH, + LOADER_SUCCESS +}; + +typedef struct +{ + UBYTE ModSearchStr[FILENAME_LENGTH + 1]; + UBYTE ModSearchIndex; + UBYTE ModSearchType; + UBYTE UsbStatus; + UBYTE IoMapHandle; +}VARSLOADER; + +void cLoaderInit(void* pHeader); +void cLoaderCtrl(void); +void cLoaderExit(void); + +extern const HEADER cLoader; + +#endif + + + diff --git a/AT91SAM7S256/Source/c_loader.iom b/AT91SAM7S256/Source/c_loader.iom new file mode 100644 index 0000000..8a86e2d --- /dev/null +++ b/AT91SAM7S256/Source/c_loader.iom @@ -0,0 +1,83 @@ +// +// Date init 14.12.2004 +// +// Revision date $Date:: 28-03-07 14:54 $ +// +// Filename $Workfile:: c_loader.iom $ +// +// Version $Revision:: 45 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/c_loader.i $ +// +// Platform C +// + +#ifndef CLOADER_IOM +#define CLOADER_IOM + +#define pMapLoader ((IOMAPLOADER*)(pHeaders[ENTRY_LOADER]->pIOMap)) + +//Version numbers are two bytes, MAJOR.MINOR (big-endian) +//For example, version 1.5 would be 0x0105 +//If these switch to little-endian, be sure to update +//definition and usages of VM_OLDEST_COMPATIBLE_VERSION, too! +#define FIRMWAREVERSION 0x0105 //1.05 +#define PROTOCOLVERSION 0x017C //1.124 + +enum +{ + OPENREAD = 0x80, + OPENWRITE = 0x81, + READ = 0x82, + WRITE = 0x83, + CLOSE = 0x84, + DELETE = 0x85, + FINDFIRST = 0x86, + FINDNEXT = 0x87, + VERSIONS = 0x88, + OPENWRITELINEAR = 0x89, + OPENREADLINEAR = 0x8A, + OPENWRITEDATA = 0x8B, + OPENAPPENDDATA = 0x8C, + FINDFIRSTMODULE = 0x90, + FINDNEXTMODULE = 0x91, + CLOSEMODHANDLE = 0x92, + IOMAPREAD = 0x94, + IOMAPWRITE = 0x95, + BOOTCMD = 0x97, /* external command only */ + SETBRICKNAME = 0x98, + BTGETADR = 0x9A, + DEVICEINFO = 0x9B, + DELETEUSERFLASH = 0xA0, + POLLCMDLEN = 0xA1, + POLLCMD = 0xA2, + RENAMEFILE = 0xA3, + BTFACTORYRESET = 0xA4 + +}; + +typedef UWORD LOADER_STATUS; + +//Mask out handle byte of Loader status word for error code checks +#define LOADER_ERR(StatusWord) ((StatusWord & 0xFF00)) + +//Byte value of error half of Loader status word +#define LOADER_ERR_BYTE(StatusWord) ((UBYTE)((StatusWord & 0xFF00) >> 8)) + +//Value of handle inside Loader status word +#define LOADER_HANDLE(StatusWord) ((UBYTE)(StatusWord)) + +//Pointer to lower byte of Loader status word +#define LOADER_HANDLE_P(StatusWord) ((UBYTE*)(&StatusWord)) + +typedef struct +{ + UWORD (*pFunc)(UBYTE, UBYTE *, UBYTE *, ULONG *); + ULONG FreeUserFlash; +}IOMAPLOADER; + + +#endif + + + diff --git a/AT91SAM7S256/Source/c_lowspeed.c b/AT91SAM7S256/Source/c_lowspeed.c new file mode 100644 index 0000000..a43ba7d --- /dev/null +++ b/AT91SAM7S256/Source/c_lowspeed.c @@ -0,0 +1,236 @@ +// +// Date init 14.12.2004 +// +// Revision date $Date:: 16-05-06 12:13 $ +// +// Filename $Workfile:: c_lowspeed.c $ +// +// Version $Revision:: 23 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/c_lowspeed $ +// +// Platform C +// + +#include "stdconst.h" +#include "modules.h" +#include "c_lowspeed.iom" +#include "c_input.iom" +#include "c_lowspeed.h" +#include "d_lowspeed.h" + +static IOMAPLOWSPEED IOMapLowSpeed; +static VARSLOWSPEED VarsLowSpeed; +static HEADER **pHeaders; + +const UBYTE LOWSPEED_CH_NUMBER[4] = {0x01, 0x02, 0x04, 0x08}; + +const HEADER cLowSpeed = +{ + 0x000B0001L, + "Low Speed", + cLowSpeedInit, + cLowSpeedCtrl, + cLowSpeedExit, + (void *)&IOMapLowSpeed, + (void *)&VarsLowSpeed, + (UWORD)sizeof(IOMapLowSpeed), + (UWORD)sizeof(VarsLowSpeed), + 0x0000 //Code size - not used so far +}; + +void cLowSpeedInit(void* pHeader) +{ + pHeaders = pHeader; + + dLowSpeedInit(); + IOMapLowSpeed.State = COM_CHANNEL_NONE_ACTIVE; + VarsLowSpeed.TimerState = TIMER_STOPPED; +} + +void cLowSpeedCtrl(void) +{ + UBYTE Temp; + UBYTE ChannelNumber = 0; + + if (IOMapLowSpeed.State != 0) + { + for (ChannelNumber = 0; ChannelNumber < NO_OF_LOWSPEED_COM_CHANNEL; ChannelNumber++) + { + //Lowspeed com is activated + switch (IOMapLowSpeed.ChannelState[ChannelNumber]) + { + case LOWSPEED_IDLE: + { + } + break; + + case LOWSPEED_INIT: + { + if ((pMapInput->Inputs[ChannelNumber].SensorType == LOWSPEED) || (pMapInput->Inputs[ChannelNumber].SensorType == LOWSPEED_9V)) + { + if (VarsLowSpeed.TimerState == TIMER_STOPPED) + { + dLowSpeedStartTimer(); + VarsLowSpeed.TimerState = TIMER_RUNNING; + } + IOMapLowSpeed.ChannelState[ChannelNumber] = LOWSPEED_LOAD_BUFFER; + IOMapLowSpeed.ErrorType[ChannelNumber] = LOWSPEED_NO_ERROR; + VarsLowSpeed.ErrorCount[ChannelNumber] = 0; + dLowSpeedInitPins(ChannelNumber); + } + else + { + IOMapLowSpeed.ChannelState[ChannelNumber] = LOWSPEED_ERROR; + IOMapLowSpeed.ErrorType[ChannelNumber] = LOWSPEED_CH_NOT_READY; + } + } + break; + + case LOWSPEED_LOAD_BUFFER: + { + if ((pMapInput->Inputs[ChannelNumber].SensorType == LOWSPEED) || (pMapInput->Inputs[ChannelNumber].SensorType == LOWSPEED_9V)) + { + VarsLowSpeed.OutputBuf[ChannelNumber].OutPtr = 0; + for (VarsLowSpeed.OutputBuf[ChannelNumber].InPtr = 0; VarsLowSpeed.OutputBuf[ChannelNumber].InPtr < IOMapLowSpeed.OutBuf[ChannelNumber].InPtr; VarsLowSpeed.OutputBuf[ChannelNumber].InPtr++) + { + VarsLowSpeed.OutputBuf[ChannelNumber].Buf[VarsLowSpeed.OutputBuf[ChannelNumber].InPtr] = IOMapLowSpeed.OutBuf[ChannelNumber].Buf[IOMapLowSpeed.OutBuf[ChannelNumber].OutPtr]; + IOMapLowSpeed.OutBuf[ChannelNumber].OutPtr++; + } + if (dLowSpeedSendData(ChannelNumber, &VarsLowSpeed.OutputBuf[ChannelNumber].Buf[0], (VarsLowSpeed.OutputBuf[ChannelNumber].InPtr - VarsLowSpeed.OutputBuf[ChannelNumber].OutPtr))) + { + if (IOMapLowSpeed.InBuf[ChannelNumber].BytesToRx != 0) + { + dLowSpeedReceiveData(ChannelNumber, &VarsLowSpeed.InputBuf[ChannelNumber].Buf[0], IOMapLowSpeed.InBuf[ChannelNumber].BytesToRx); + VarsLowSpeed.RxTimeCnt[ChannelNumber] = 0; + } + IOMapLowSpeed.ChannelState[ChannelNumber] = LOWSPEED_COMMUNICATING; + IOMapLowSpeed.Mode[ChannelNumber] = LOWSPEED_TRANSMITTING; + } + else + { + IOMapLowSpeed.ChannelState[ChannelNumber] = LOWSPEED_ERROR; + IOMapLowSpeed.ErrorType[ChannelNumber] = LOWSPEED_CH_NOT_READY; + } + } + else + { + IOMapLowSpeed.ChannelState[ChannelNumber] = LOWSPEED_ERROR; + IOMapLowSpeed.ErrorType[ChannelNumber] = LOWSPEED_CH_NOT_READY; + } + } + break; + + case LOWSPEED_COMMUNICATING: + { + if ((pMapInput->Inputs[ChannelNumber].SensorType == LOWSPEED) || (pMapInput->Inputs[ChannelNumber].SensorType == LOWSPEED_9V)) + { + if (IOMapLowSpeed.Mode[ChannelNumber] == LOWSPEED_TRANSMITTING) + { + Temp = dLowSpeedComTxStatus(ChannelNumber); // Returns 0x00 if not done, 0x01 if success, 0xFF if error + + if (Temp == LOWSPEED_COMMUNICATION_SUCCESS) + { + if (IOMapLowSpeed.InBuf[ChannelNumber].BytesToRx != 0) + { + IOMapLowSpeed.Mode[ChannelNumber] = LOWSPEED_RECEIVING; + } + else + { + IOMapLowSpeed.Mode[ChannelNumber] = LOWSPEED_DATA_RECEIVED; + IOMapLowSpeed.ChannelState[ChannelNumber] = LOWSPEED_DONE; + } + } + if (Temp == LOWSPEED_COMMUNICATION_ERROR) + { + //ERROR in Communication, No ACK received from SLAVE, retry send data 3 times! + VarsLowSpeed.ErrorCount[ChannelNumber]++; + if (VarsLowSpeed.ErrorCount[ChannelNumber] > MAX_RETRY_TX_COUNT) + { + IOMapLowSpeed.ChannelState[ChannelNumber] = LOWSPEED_ERROR; + IOMapLowSpeed.ErrorType[ChannelNumber] = LOWSPEED_TX_ERROR; + } + else + { + IOMapLowSpeed.ChannelState[ChannelNumber] = LOWSPEED_LOAD_BUFFER; + } + } + } + if (IOMapLowSpeed.Mode[ChannelNumber] == LOWSPEED_RECEIVING) + { + VarsLowSpeed.RxTimeCnt[ChannelNumber]++; + if (VarsLowSpeed.RxTimeCnt[ChannelNumber] > LOWSPEED_RX_TIMEOUT) + { + IOMapLowSpeed.ChannelState[ChannelNumber] = LOWSPEED_ERROR; + IOMapLowSpeed.ErrorType[ChannelNumber] = LOWSPEED_RX_ERROR; + } + Temp = dLowSpeedComRxStatus(ChannelNumber); + if (Temp == LOWSPEED_COMMUNICATION_SUCCESS) + { + for (VarsLowSpeed.InputBuf[ChannelNumber].OutPtr = 0; VarsLowSpeed.InputBuf[ChannelNumber].OutPtr < IOMapLowSpeed.InBuf[ChannelNumber].BytesToRx; VarsLowSpeed.InputBuf[ChannelNumber].OutPtr++) + { + IOMapLowSpeed.InBuf[ChannelNumber].Buf[IOMapLowSpeed.InBuf[ChannelNumber].InPtr] = VarsLowSpeed.InputBuf[ChannelNumber].Buf[VarsLowSpeed.InputBuf[ChannelNumber].OutPtr]; + IOMapLowSpeed.InBuf[ChannelNumber].InPtr++; + if (IOMapLowSpeed.InBuf[ChannelNumber].InPtr >= SIZE_OF_LSBUF) + { + IOMapLowSpeed.InBuf[ChannelNumber].InPtr = 0; + } + VarsLowSpeed.InputBuf[ChannelNumber].Buf[VarsLowSpeed.InputBuf[ChannelNumber].OutPtr] = 0; + } + IOMapLowSpeed.Mode[ChannelNumber] = LOWSPEED_DATA_RECEIVED; + IOMapLowSpeed.ChannelState[ChannelNumber] = LOWSPEED_DONE; + } + if (Temp == LOWSPEED_COMMUNICATION_ERROR) + { + //There was and error in receiving data from the device + for (VarsLowSpeed.InputBuf[ChannelNumber].OutPtr = 0; VarsLowSpeed.InputBuf[ChannelNumber].OutPtr < IOMapLowSpeed.InBuf[ChannelNumber].BytesToRx; VarsLowSpeed.InputBuf[ChannelNumber].OutPtr++) + { + VarsLowSpeed.InputBuf[ChannelNumber].Buf[VarsLowSpeed.InputBuf[ChannelNumber].OutPtr] = 0; + } + IOMapLowSpeed.ChannelState[ChannelNumber] = LOWSPEED_ERROR; + IOMapLowSpeed.ErrorType[ChannelNumber] = LOWSPEED_RX_ERROR; + } + } + } + else + { + IOMapLowSpeed.ChannelState[ChannelNumber] = LOWSPEED_ERROR; + IOMapLowSpeed.ErrorType[ChannelNumber] = LOWSPEED_CH_NOT_READY; + } + } + break; + + case LOWSPEED_ERROR: + { + IOMapLowSpeed.State = IOMapLowSpeed.State & ~LOWSPEED_CH_NUMBER[ChannelNumber]; + if (IOMapLowSpeed.State == 0) + { + dLowSpeedStopTimer(); + VarsLowSpeed.TimerState = TIMER_STOPPED; + } + } + break; + + case LOWSPEED_DONE: + { + IOMapLowSpeed.State = IOMapLowSpeed.State & ~LOWSPEED_CH_NUMBER[ChannelNumber]; + IOMapLowSpeed.ChannelState[ChannelNumber] = LOWSPEED_IDLE; + if (IOMapLowSpeed.State == 0) + { + dLowSpeedStopTimer(); + VarsLowSpeed.TimerState = TIMER_STOPPED; + } + } + break; + + default: + break; + } + } + } +} + +void cLowSpeedExit(void) +{ + dLowSpeedExit(); +} diff --git a/AT91SAM7S256/Source/c_lowspeed.h b/AT91SAM7S256/Source/c_lowspeed.h new file mode 100644 index 0000000..7930acc --- /dev/null +++ b/AT91SAM7S256/Source/c_lowspeed.h @@ -0,0 +1,61 @@ +// +// Date init 14.12.2004 +// +// Revision date $Date:: 16-05-06 12:13 $ +// +// Filename $Workfile:: c_lowspeed.h $ +// +// Version $Revision:: 11 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/c_lowspeed $ +// +// Platform C +// + +#ifndef C_LOWSPEED +#define C_LOWSPEED + +#define LOWSPEED_RX_TIMEOUT 100 +#define LOWSPEED_COMMUNICATION_SUCCESS 0x01 +#define LOWSPEED_COMMUNICATION_ERROR 0xFF +#define SIZE_OF_LSBUFDATA 16 +#define NO_OF_LOWSPEED_COM_CH 4 + +enum +{ + LOWSPEED_CHANNEL1, + LOWSPEED_CHANNEL2, + LOWSPEED_CHANNEL3, + LOWSPEED_CHANNEL4 +}; + +enum +{ + TIMER_STOPPED, + TIMER_RUNNING +}; + +typedef struct +{ + UBYTE Buf[SIZE_OF_LSBUFDATA]; + UBYTE InPtr; + UBYTE OutPtr; +}LSDATA; + +typedef struct +{ + LSDATA OutputBuf[NO_OF_LOWSPEED_COM_CH]; + LSDATA InputBuf[NO_OF_LOWSPEED_COM_CH]; + UBYTE RxTimeCnt[NO_OF_LOWSPEED_COM_CH]; + UBYTE ErrorCount[NO_OF_LOWSPEED_COM_CH]; + UBYTE Tmp; + UBYTE TimerState; +}VARSLOWSPEED; + +void cLowSpeedInit(void* pHeader); +void cLowSpeedCtrl(void); +void cLowSpeedExit(void); + +extern const HEADER cLowSpeed; + +#endif diff --git a/AT91SAM7S256/Source/c_lowspeed.iom b/AT91SAM7S256/Source/c_lowspeed.iom new file mode 100644 index 0000000..a8e42a4 --- /dev/null +++ b/AT91SAM7S256/Source/c_lowspeed.iom @@ -0,0 +1,95 @@ +// +// Date init 14.12.2004 +// +// Revision date $Date:: 16-05-06 12:13 $ +// +// Filename $Workfile:: c_lowspeed.iom $ +// +// Version $Revision:: 18 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/c_lowspeed $ +// +// Platform C +// + +#ifndef CLOWSPEED_IOM +#define CLOWSPEED_IOM + +#define pMapLowSpeed ((IOMAPLOWSPEED*)(pHeaders[ENTRY_LOWSPEED]->pIOMap)) + +#define MAX_RETRY_TX_COUNT 3 +#define NO_OF_LOWSPEED_COM_CHANNEL 4 +#define NO_OF_LSBUF NO_OF_LOWSPEED_COM_CHANNEL +#define SIZE_OF_LSBUF 16 + +//Constants referring to LowSpeedDeviceType +enum +{ + ULTRA_SONIC = 2, + CUSTOM_LS_DEVICE +}; + +// Constants reffering to State +enum +{ + COM_CHANNEL_NONE_ACTIVE = 0x00, + COM_CHANNEL_ONE_ACTIVE = 0x01, + COM_CHANNEL_TWO_ACTIVE = 0x02, + COM_CHANNEL_THREE_ACTIVE = 0x04, + COM_CHANNEL_FOUR_ACTIVE = 0x08 +}; + +// Constants reffering to ChannelState +enum +{ + LOWSPEED_IDLE, + LOWSPEED_INIT, + LOWSPEED_LOAD_BUFFER, + LOWSPEED_COMMUNICATING, + LOWSPEED_ERROR, + LOWSPEED_DONE +}; + +// Constants reffering to Mode +enum +{ + LOWSPEED_TRANSMITTING = 1, + LOWSPEED_RECEIVING, + LOWSPEED_DATA_RECEIVED +}; + +// Constants reffering to ErrorType +enum +{ + LOWSPEED_NO_ERROR = 0, + LOWSPEED_CH_NOT_READY, + LOWSPEED_TX_ERROR, + LOWSPEED_RX_ERROR +}; + + +typedef struct +{ + UBYTE Buf[SIZE_OF_LSBUF]; + UBYTE InPtr; + UBYTE OutPtr; + UBYTE BytesToRx; +}LSBUF; + +typedef struct +{ + LSBUF InBuf[NO_OF_LSBUF]; + LSBUF OutBuf[NO_OF_LSBUF]; + UBYTE Mode[NO_OF_LSBUF]; + UBYTE ChannelState[NO_OF_LSBUF]; + UBYTE ErrorType[NO_OF_LSBUF]; + UBYTE State; + UBYTE Speed; + UBYTE Spare1; +}IOMAPLOWSPEED; + + +#endif + + + diff --git a/AT91SAM7S256/Source/c_output.c b/AT91SAM7S256/Source/c_output.c new file mode 100644 index 0000000..c91eb07 --- /dev/null +++ b/AT91SAM7S256/Source/c_output.c @@ -0,0 +1,169 @@ +// +// Date init 14.12.2004 +// +// Revision date $Date:: 16-05-06 12:13 $ +// +// Filename $Workfile:: c_output.c $ +// +// Version $Revision:: 45 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/c_output.c $ +// +// Platform C +// + +#include +#include "stdbool.h" +#include "stdconst.h" +#include "modules.h" +#include "c_output.iom" +#include "c_output.h" +#include "d_output.h" +#include "c_display.iom" + +static IOMAPOUTPUT IOMapOutput; +static VARSOUTPUT VarsOutput; + +const HEADER cOutput = +{ + 0x00020001L, + "Output", + cOutputInit, + cOutputCtrl, + cOutputExit, + (void *)&IOMapOutput, + (void *)&VarsOutput, + (UWORD)sizeof(IOMapOutput), + (UWORD)sizeof(VarsOutput), + 0x0000 //Code size - not used so far +}; + + +void cOutputInit(void* pHeader) +{ + UBYTE Tmp; + + for(Tmp = 0; Tmp < NO_OF_OUTPUTS; Tmp++) + { + IOMapOutput.Outputs[Tmp].Mode = 0x00; + IOMapOutput.Outputs[Tmp].Speed = 0x00; + IOMapOutput.Outputs[Tmp].ActualSpeed = 0x00; + IOMapOutput.Outputs[Tmp].TachoCnt = 0x00; + IOMapOutput.Outputs[Tmp].RunState = 0x00; + IOMapOutput.Outputs[Tmp].TachoLimit = 0x00; + IOMapOutput.Outputs[Tmp].RegPParameter = DEFAULT_P_GAIN_FACTOR; + IOMapOutput.Outputs[Tmp].RegIParameter = DEFAULT_I_GAIN_FACTOR; + IOMapOutput.Outputs[Tmp].RegDParameter = DEFAULT_D_GAIN_FACTOR; + } + VarsOutput.TimeCnt = 0; + dOutputInit(); +} + +void cOutputCtrl(void) +{ + UBYTE Tmp; + + for(Tmp = 0; Tmp < NO_OF_OUTPUTS; Tmp++) + { + if (IOMapOutput.Outputs[Tmp].Flags != 0) + { + if (IOMapOutput.Outputs[Tmp].Flags & UPDATE_RESET_ROTATION_COUNT) + { + IOMapOutput.Outputs[Tmp].Flags &= ~UPDATE_RESET_ROTATION_COUNT; + dOutputResetRotationCaptureCount(Tmp); + } + if (IOMapOutput.Outputs[Tmp].Flags & UPDATE_RESET_COUNT) + { + IOMapOutput.Outputs[Tmp].Flags &= ~UPDATE_RESET_COUNT; + dOutputResetTachoLimit(Tmp); + } + if (IOMapOutput.Outputs[Tmp].Flags & UPDATE_RESET_BLOCK_COUNT) + { + IOMapOutput.Outputs[Tmp].Flags &= ~UPDATE_RESET_BLOCK_COUNT; + dOutputResetBlockTachoLimit(Tmp); + } + if (IOMapOutput.Outputs[Tmp].Flags & UPDATE_SPEED) + { + IOMapOutput.Outputs[Tmp].Flags &= ~UPDATE_SPEED; + if (IOMapOutput.Outputs[Tmp].Mode & MOTORON) + { + dOutputSetSpeed (Tmp, IOMapOutput.Outputs[Tmp].RunState, IOMapOutput.Outputs[Tmp].Speed, IOMapOutput.Outputs[Tmp].SyncTurnParameter); + } + } + if (IOMapOutput.Outputs[Tmp].Flags & UPDATE_TACHO_LIMIT) + { + IOMapOutput.Outputs[Tmp].Flags &= ~UPDATE_TACHO_LIMIT; + dOutputSetTachoLimit(Tmp, IOMapOutput.Outputs[Tmp].TachoLimit); + } + if (IOMapOutput.Outputs[Tmp].Flags & UPDATE_MODE) + { + IOMapOutput.Outputs[Tmp].Flags &= ~UPDATE_MODE; + if (IOMapOutput.Outputs[Tmp].Mode & BRAKE) + { + // Motor is Braked + dOutputSetMode(Tmp, BRAKE); + } + else + { + // Motor is floated + dOutputSetMode(Tmp, 0x00); + } + if (IOMapOutput.Outputs[Tmp].Mode & MOTORON) + { + if (IOMapOutput.Outputs[Tmp].Mode & REGULATED) + { + dOutputEnableRegulation(Tmp, IOMapOutput.Outputs[Tmp].RegMode); + } + else + { + dOutputDisableRegulation(Tmp); + } + } + else + { + dOutputSetSpeed(Tmp, 0x00, 0x00, 0x00); + dOutputDisableRegulation(Tmp); + } + } + if (IOMapOutput.Outputs[Tmp].Flags & UPDATE_PID_VALUES) + { + IOMapOutput.Outputs[Tmp].Flags &= ~UPDATE_PID_VALUES; + dOutputSetPIDParameters(Tmp, IOMapOutput.Outputs[Tmp].RegPParameter, IOMapOutput.Outputs[Tmp].RegIParameter, IOMapOutput.Outputs[Tmp].RegDParameter); + } + } + } + dOutputCtrl(); + cOutputUpdateIomap(); +} + +void cOutputUpdateIomap(void) +{ + UBYTE TempCurrentMotorSpeed[NO_OF_OUTPUTS]; + UBYTE TempRunState[NO_OF_OUTPUTS]; + UBYTE TempMotorOverloaded[NO_OF_OUTPUTS]; + SLONG TempTachoCount[NO_OF_OUTPUTS]; + SLONG TempBlockTachoCount[NO_OF_OUTPUTS]; + SLONG TempRotationCount[NO_OF_OUTPUTS]; + + UBYTE Tmp; + + dOutputGetMotorParameters(TempCurrentMotorSpeed, TempTachoCount, TempBlockTachoCount, TempRunState, TempMotorOverloaded,TempRotationCount); + + for(Tmp = 0; Tmp < NO_OF_OUTPUTS; Tmp++) + { + IOMapOutput.Outputs[Tmp].ActualSpeed = TempCurrentMotorSpeed[Tmp]; + IOMapOutput.Outputs[Tmp].TachoCnt = TempTachoCount[Tmp]; + IOMapOutput.Outputs[Tmp].BlockTachoCount = TempBlockTachoCount[Tmp]; + IOMapOutput.Outputs[Tmp].RotationCount = TempRotationCount[Tmp]; + IOMapOutput.Outputs[Tmp].Overloaded = TempMotorOverloaded[Tmp]; + if (!(IOMapOutput.Outputs[Tmp].Flags & PENDING_UPDATES)) + { + IOMapOutput.Outputs[Tmp].RunState = TempRunState[Tmp]; + } + } +} + +void cOutputExit(void) +{ + dOutputExit(); +} diff --git a/AT91SAM7S256/Source/c_output.h b/AT91SAM7S256/Source/c_output.h new file mode 100644 index 0000000..e3d7c43 --- /dev/null +++ b/AT91SAM7S256/Source/c_output.h @@ -0,0 +1,31 @@ +// +// Date init 14.12.2004 +// +// Revision date $Date:: 16-05-06 12:13 $ +// +// Filename $Workfile:: c_output.h $ +// +// Version $Revision:: 6 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/c_output.h $ +// +// Platform C +// + +#ifndef C_OUTPUT +#define C_OUTPUT + +typedef struct +{ + UBYTE TimeCnt; + UBYTE Tmp; +}VARSOUTPUT; + +void cOutputInit(void* pHeader); +void cOutputCtrl(void); +void cOutputExit(void); +void cOutputUpdateIomap(void); + +extern const HEADER cOutput; + +#endif diff --git a/AT91SAM7S256/Source/c_output.iom b/AT91SAM7S256/Source/c_output.iom new file mode 100644 index 0000000..e13f0f8 --- /dev/null +++ b/AT91SAM7S256/Source/c_output.iom @@ -0,0 +1,92 @@ +// +// Date init 14.12.2004 +// +// Revision date $Date:: 16-05-06 12:13 $ +// +// Filename $Workfile:: c_output.iom $ +// +// Version $Revision:: 25 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/c_output.i $ +// +// Platform C +// + +#ifndef COUTPUT_IOM +#define COUTPUT_IOM + +#define NO_OF_OUTPUTS 3 +#define pMapOutPut ((IOMAPOUTPUT*)(pHeaders[ENTRY_OUTPUT]->pIOMap)) + +// Constants reffering to mode +enum +{ + MOTORON = 0x01, + BRAKE = 0x02, + REGULATED = 0x04, + REG_METHOD = 0xF0 /* Regulation methods - to be designed! */ +}; + +// Constants related to Flags +enum +{ + UPDATE_MODE = 0x01, + UPDATE_SPEED = 0x02, + UPDATE_TACHO_LIMIT = 0x04, + UPDATE_RESET_COUNT = 0x08, + UPDATE_PID_VALUES = 0x10, + UPDATE_RESET_BLOCK_COUNT = 0x20, + UPDATE_RESET_ROTATION_COUNT = 0x40, + PENDING_UPDATES = 0x80 +}; + +// Constant related to RunState +#define MOTOR_RUN_STATE_IDLE 0x00 +#define MOTOR_RUN_STATE_RAMPUP 0x10 +#define MOTOR_RUN_STATE_RUNNING 0x20 +#define MOTOR_RUN_STATE_RAMPDOWN 0x40 + +// Constant related to RegMode +enum +{ + REGULATION_MODE_IDLE, + REGULATION_MODE_MOTOR_SPEED, + REGULATION_MODE_MOTOR_SYNC +}; + +typedef struct +{ + SLONG TachoCnt; /* R - Holds current number of counts, since last reset, updated every 1 mS */ + SLONG BlockTachoCount; /* R - Holds current number of counts for the current output block */ + SLONG RotationCount; /* R - Holds current number of counts for the rotation counter to the output */ + ULONG TachoLimit; /* RW - Holds number of counts to travel, 0 => Run forever */ + SWORD MotorRPM; /* !! Is not updated, will be removed later !! */ + UBYTE Flags; /* RW - Holds flags for which data should be updated */ + UBYTE Mode; /* RW - Holds motor mode: Run, Break, regulated, ... */ + SBYTE Speed; /* RW - Holds the wanted speed */ + SBYTE ActualSpeed; /* R - Holds the current motor speed */ + UBYTE RegPParameter; /* RW - Holds the P-constant use din the regulation, Is set to a default value at init => Setting this value is optional for the user */ + UBYTE RegIParameter; /* RW - Holds the I-constant use din the regulation, Is set to a default value at init => Setting this value is optional for the user */ + UBYTE RegDParameter; /* RW - Holds the D-constant use din the regulation, Is set to a default value at init => Setting this value is optional for the user */ + UBYTE RunState; /* RW - Holds the current RunState in the output module */ + UBYTE RegMode; /* RW - Tells which regulation mode should be used */ + UBYTE Overloaded; /* R - True if the motor has been overloaded within speed control regulation */ + SBYTE SyncTurnParameter; /* RW - Holds the turning parameter need within MoveBlock */ + UBYTE SpareOne; + UBYTE SpareTwo; + UBYTE SpareThree; +}OUTPUT; + + +typedef struct +{ + OUTPUT Outputs[NO_OF_OUTPUTS]; + UBYTE PwnFreq; +}IOMAPOUTPUT; + + + +#endif + + + diff --git a/AT91SAM7S256/Source/c_sound.c b/AT91SAM7S256/Source/c_sound.c new file mode 100644 index 0000000..8e34d32 --- /dev/null +++ b/AT91SAM7S256/Source/c_sound.c @@ -0,0 +1,309 @@ +// +// Programmer +// +// Date init 14.12.2004 +// +// Reviser $Author:: Dkflebun $ +// +// Revision date $Date:: 5-02-07 13:36 $ +// +// Filename $Workfile:: c_sound.c $ +// +// Version $Revision:: 33 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/c_sound.c $ +// +// Platform C +// + +#include +#include +#include "stdconst.h" +#include "modules.h" +#include "c_sound.iom" +#include "c_loader.iom" +#include "c_sound.h" +#include "d_sound.h" + +static IOMAPSOUND IOMapSound; +static VARSSOUND VarsSound; +static HEADER **pHeaders; + +const HEADER cSound = +{ + 0x00080001L, + "Sound", + cSoundInit, + cSoundCtrl, + cSoundExit, + (void *)&IOMapSound, + (void *)&VarsSound, + (UWORD)sizeof(IOMapSound), + (UWORD)sizeof(VarsSound), + 0x0000 //Code size - not used so far +}; + + +UWORD cSoundFile(UBYTE Cmd,UBYTE *pFile,UBYTE *pData,ULONG *pLng) +{ + return (pMapLoader->pFunc(Cmd,pFile,pData,pLng)); +} + + +void cSoundInit(void* pHeader) +{ + pHeaders = pHeader; + IOMapSound.Flags &= ~SOUND_UPDATE; + IOMapSound.Flags &= ~SOUND_RUNNING; + IOMapSound.State = SOUND_IDLE; + IOMapSound.Mode = SOUND_ONCE; + IOMapSound.Volume = SOUNDVOLUMESTEPS; + IOMapSound.SampleRate = 0; + IOMapSound.SoundFilename[0] = 0; + VarsSound.BufferIn = 0; + VarsSound.BufferOut = 0; + dSoundInit(); +} + +void cSoundCtrl(void) +{ + static UWORD FileFormat; + static UBYTE SoundFilename[FILENAME_LENGTH + 1]; + UWORD Handle; + ULONG Length; + UBYTE Header[FILEHEADER_LENGTH]; + UBYTE In,Out,Tmp; + + In = VarsSound.BufferIn; + Out = VarsSound.BufferOut; + + if ((IOMapSound.Flags & SOUND_UPDATE)) + { +// Check if valid update + if (!(SOUND_TONE & IOMapSound.Mode)) + { + Handle = pMapLoader->pFunc(FINDFIRST,IOMapSound.SoundFilename,SoundFilename,&Length); + if (!(Handle & 0x8000)) + { + pMapLoader->pFunc(CLOSE,(UBYTE*)&Handle,NULL,NULL); + } + else + { + IOMapSound.Flags &= ~SOUND_UPDATE; + } + } + if ((IOMapSound.Flags & SOUND_UPDATE)) + { +// Check for open file + if (!(VarsSound.File & 0x8000)) + { + cSoundFile(CLOSE,(UBYTE*)&VarsSound.File,NULL,NULL); + VarsSound.File = 0x8000; + } + + IOMapSound.Flags &= ~SOUND_UPDATE; + + if ((SOUND_TONE & IOMapSound.Mode)) + { + dSoundFreq(IOMapSound.Freq,IOMapSound.Duration,IOMapSound.Volume); + IOMapSound.State = SOUND_FREQ; + } + else + { + if (IOMapSound.Flags & SOUND_RUNNING) + { + dSoundStop(); + IOMapSound.Flags &= ~SOUND_RUNNING; + } + VarsSound.File = pMapLoader->pFunc(OPENREAD,SoundFilename,NULL,&Length); + if (!(VarsSound.File & 0x8000)) + { + Length = FILEHEADER_LENGTH; + pMapLoader->pFunc(READ,(UBYTE*)&VarsSound.File,Header,&Length); + if (Length == FILEHEADER_LENGTH) + { + FileFormat = ((UWORD)Header[0] << 8) + (UWORD)Header[1]; + + if (FILEFORMAT_SOUND == (FileFormat & 0xFF00)) + { + if (IOMapSound.SampleRate) + { + VarsSound.SampleRate = IOMapSound.SampleRate; + IOMapSound.SampleRate = 0; + } + else + { + VarsSound.SampleRate = ((UWORD)Header[4] << 8) + (UWORD)Header[5]; + } + dSoundVolume(IOMapSound.Volume); + Length = SOUNDBUFFERSIZE; + pMapLoader->pFunc(READ,(UBYTE*)&VarsSound.File,VarsSound.Buffer[In],&Length); + VarsSound.Length[In] = (UWORD)Length; + In++; + if (In >= SOUNDBUFFERS) + { + In = 0; + } + IOMapSound.State = SOUND_BUSY; + } + else + { + if (FILEFORMAT_MELODY == FileFormat) + { + Length = SOUNDBUFFERSIZE; + pMapLoader->pFunc(READ,(UBYTE*)&VarsSound.File,VarsSound.Buffer[In],&Length); + VarsSound.Length[In] = (UWORD)Length; + In++; + if (In >= SOUNDBUFFERS) + { + In = 0; + } + IOMapSound.State = SOUND_BUSY; + } + else + { + pMapLoader->pFunc(CLOSE,(UBYTE*)&VarsSound.File,NULL,NULL); + } + } + } + } + } + } + } + + switch (IOMapSound.State) + { + case SOUND_BUSY : + { + IOMapSound.Flags |= SOUND_RUNNING; + if (In != Out) + { + if ((FILEFORMAT_SOUND == FileFormat) || (FILEFORMAT_SOUND_COMPRESSED == FileFormat)) + { + if (dSoundStart(VarsSound.Buffer[Out],VarsSound.Length[Out],VarsSound.SampleRate,(UBYTE)(FileFormat & 0x00FF)) == TRUE) + { + Out++; + if (Out >= SOUNDBUFFERS) + { + Out = 0; + } + } + } + else + { + if (dSoundTone(VarsSound.Buffer[Out],VarsSound.Length[Out],IOMapSound.Volume) == TRUE) + { + Out++; + if (Out >= SOUNDBUFFERS) + { + Out = 0; + } + } + } + } + + Tmp = In; + Tmp++; + if (Tmp >= SOUNDBUFFERS) + { + Tmp = 0; + } + + if (Tmp != Out) + { + Tmp++; + if (Tmp >= SOUNDBUFFERS) + { + Tmp = 0; + } + if (Tmp != Out) + { + Length = SOUNDBUFFERSIZE; + Handle = cSoundFile(READ,(UBYTE*)&VarsSound.File,VarsSound.Buffer[In],&Length); + if ((Handle & 0x8000)) + { + Length = 0L; + } + VarsSound.Length[In] = (UWORD)Length; + if (VarsSound.Length[In] == 0) + { + if (SOUND_LOOP == IOMapSound.Mode) + { + if (!(IOMapSound.Flags & SOUND_UPDATE)) + { + cSoundFile(CLOSE,(UBYTE*)&VarsSound.File,NULL,NULL); + VarsSound.File = cSoundFile(OPENREAD,SoundFilename,NULL,&Length); + Length = FILEHEADER_LENGTH; + cSoundFile(READ,(UBYTE*)&VarsSound.File,Header,&Length); + Length = SOUNDBUFFERSIZE; + cSoundFile(READ,(UBYTE*)&VarsSound.File,VarsSound.Buffer[In],&Length); + VarsSound.Length[In] = (UWORD)Length; + } + } + } + if (VarsSound.Length[In] != 0) + { + In++; + if (In >= SOUNDBUFFERS) + { + In = 0; + } + } + if (VarsSound.Length[Out] == 0) + { + if (!(VarsSound.File & 0x8000)) + { + pMapLoader->pFunc(CLOSE,(UBYTE*)&VarsSound.File,NULL,NULL); + VarsSound.File = 0x8000; + } + IOMapSound.Flags &= ~SOUND_RUNNING; + IOMapSound.State = SOUND_IDLE; + } + } + } + } + break; + + case SOUND_FREQ : + { + IOMapSound.Flags |= SOUND_RUNNING; + if (dSoundReady() == TRUE) + { + if (SOUND_LOOP & IOMapSound.Mode) + { + dSoundFreq(IOMapSound.Freq,IOMapSound.Duration,IOMapSound.Volume); + } + else + { + IOMapSound.Flags &= ~SOUND_RUNNING; + IOMapSound.State = SOUND_IDLE; + } + } + } + break; + + case SOUND_STOP : + { + dSoundStop(); + if (!(VarsSound.File & 0x8000)) + { + pMapLoader->pFunc(CLOSE,(UBYTE*)&VarsSound.File,NULL,NULL); + VarsSound.File = 0x8000; + } + IOMapSound.Flags &= ~SOUND_RUNNING; + IOMapSound.State = SOUND_IDLE; + Out = In; + } + break; + + } + + VarsSound.BufferIn = In; + VarsSound.BufferOut = Out; +} + + +void cSoundExit(void) +{ + dSoundExit(); +} diff --git a/AT91SAM7S256/Source/c_sound.h b/AT91SAM7S256/Source/c_sound.h new file mode 100644 index 0000000..93e3221 --- /dev/null +++ b/AT91SAM7S256/Source/c_sound.h @@ -0,0 +1,44 @@ +// +// Programmer +// +// Date init 14.12.2004 +// +// Reviser $Author:: Dktochpe $ +// +// Revision date $Date:: 26-08-05 8:37 $ +// +// Filename $Workfile:: c_sound.h $ +// +// Version $Revision:: 10 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/c_sound.h $ +// +// Platform C +// + + +#ifndef C_SOUND +#define C_SOUND + +#define SOUNDBUFFERSIZE 64 // Flash Sector size ? +#define SOUNDBUFFERS 3 // Min 3 - max 255 + + +typedef struct +{ + UWORD Length[SOUNDBUFFERS]; + UWORD File; + UWORD SampleRate; + UBYTE Buffer[SOUNDBUFFERS][SOUNDBUFFERSIZE]; + UBYTE BufferIn; + UBYTE BufferOut; + UBYTE BufferTmp; +}VARSSOUND; + +void cSoundInit(void* pHeaders); +void cSoundCtrl(void); +void cSoundExit(void); + +extern const HEADER cSound; + +#endif diff --git a/AT91SAM7S256/Source/c_sound.iom b/AT91SAM7S256/Source/c_sound.iom new file mode 100644 index 0000000..8baeb72 --- /dev/null +++ b/AT91SAM7S256/Source/c_sound.iom @@ -0,0 +1,109 @@ +// +// Programmer +// +// Date init 14.12.2004 +// +// Reviser $Author:: Dktochpe $ +// +// Revision date $Date:: 24-01-06 11:47 $ +// +// Filename $Workfile:: c_sound.iom $ +// +// Version $Revision:: 18 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/c_sound.io $ +// +// Platform C +// + +#ifndef CSOUND_IOM +#define CSOUND_IOM + +#define pMapSound ((IOMAPSOUND*)(pHeaders[ENTRY_SOUND]->pIOMap)) + + +/* HOW TO + +Start a sound file strcpy((char*)pMapSound->SoundFilename,"xxxxxxx.rso"); + pMapSound->Volume = IOMapUi.Volume; + pMapSound->Mode = SOUND_ONCE; + pMapSound->Flags |= SOUND_UPDATE; + + +Start and loop a sound file strcpy((char*)pMapSound->SoundFilename,"xxxxxxx.rso"); + pMapSound->Volume = IOMapUi.Volume; + pMapSound->Mode = SOUND_LOOP; + pMapSound->Flags |= SOUND_UPDATE; + + +Start a tone pMapSound->Freq = 440; + pMapSound->Duration = 1000; + pMapSound->Volume = IOMapUi.Volume; + pMapSound->Mode = SOUND_TONE; + pMapSound->Flags |= SOUND_UPDATE; + + +Start and loop a tone pMapSound->Freq = 440; + pMapSound->Duration = 1000; + pMapSound->Volume = IOMapUi.Volume; + pMapSound->Mode = SOUND_TONE | SOUND_LOOP; + pMapSound->Flags |= SOUND_UPDATE; + + + +Test for sound finished if (!(pMapSound->Flags & (SOUND_RUNNING | SOUND_UPDATE))) + { + // FINISHED + } + + +Abort sound or tone pMapSound->State = SOUND_STOP; + + +**** Start always abort running sound or tone **** + + + +*/ + +// Constants related to Flags +enum +{ + SOUND_UPDATE = 0x01, // W - Make changes take effect + SOUND_RUNNING = 0x02 // R - Processing tone or file +}; + +// Constants related to State +enum +{ + SOUND_IDLE = 0x00, // R - Idle, ready for start sound (SOUND_UPDATE) + SOUND_BUSY = 0x02, // R - Processing file of sound/melody data + SOUND_FREQ = 0x03, // R - Processing play tone request + SOUND_STOP = 0x04 // W - Stop sound imedately and close hardware +}; + +// Constants related to Mode +enum +{ + SOUND_ONCE = 0x00, // W - Only play file once + SOUND_LOOP = 0x01, // W - Play file until writing "SOUND_STOP" into "State" or new "update" + SOUND_TONE = 0x02 // W - Play tone specified in Freq for Duration ms +}; + +typedef struct +{ + UWORD Freq; // RW - Tone frequency [Hz] + UWORD Duration; // RW - Tone duration [mS] + UWORD SampleRate; // RW - Sound file sample rate [2000..16000] + UBYTE SoundFilename[FILENAME_LENGTH + 1]; // RW - Sound/melody filename + UBYTE Flags; // RW - Play flag - descripted above + UBYTE State; // RW - Play state - descriped above + UBYTE Mode; // RW - Play mode - descriped above + UBYTE Volume; // RW - Sound/melody volume [0..4] 0 = off +}IOMAPSOUND; + + +#endif + + + diff --git a/AT91SAM7S256/Source/c_ui.c b/AT91SAM7S256/Source/c_ui.c new file mode 100644 index 0000000..dd7e351 --- /dev/null +++ b/AT91SAM7S256/Source/c_ui.c @@ -0,0 +1,1982 @@ +// +// Programmer +// +// Date init 14.12.2004 +// +// Reviser $Author:: Dktochpe $ +// +// Revision date $Date:: 2-03-06 13:03 $ +// +// Filename $Workfile:: c_ui.c $ +// +// Version $Revision:: 135 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/c_ui.c $ +// +// Platform C +// + +#include "stdio.h" +#include "string.h" +#include "ctype.h" +#include "stdconst.h" +#include "modules.h" +#include "c_ui.iom" +#include "c_ui.h" +#include "m_sched.h" +#include "c_display.iom" +#include "c_loader.iom" +#include "c_button.iom" +#include "c_sound.iom" +#include "c_input.iom" +#include "c_output.iom" +#include "c_ioctrl.iom" +#include "c_cmd.iom" +#include "c_comm.iom" +#include "c_lowspeed.iom" + +static IOMAPUI IOMapUi; +static VARSUI VarsUi; +static HEADER **pHeaders; + +const HEADER cUi = +{ + 0x000C0001L, + "Ui", + cUiInit, + cUiCtrl, + cUiExit, + (void *)&IOMapUi, + (void *)&VarsUi, + (UWORD)sizeof(IOMapUi), + (UWORD)sizeof(VarsUi), + 0x0000 // Code size - not used so far +}; + + +// ****** GENERAL GRAPHIC RESOURCES ****************************************** + +#include "Display.txt" // Bitmap for frame used in view and datalog +#include "LowBattery.txt" // Bitmap showed when low battery occures +#include "Font.txt" // Font used for all text +#include "Step.txt" // Bitmap used in On Brick Programming +#include "Cursor.txt" // Bitmap for cursor +#include "Running.txt" // Icon collection used for "running" symbol +#include "Port.txt" // Font used for naming sensor ports in datalog/bluetooth +#include "Ok.txt" // Bitmap for OK buttom in get user string +#include "Wait.txt" // Bitmap for feedback +#include "Fail.txt" // Bitmap for feedback +#include "Info.txt" // Bitmap for feedback +#include "Icons.txt" // Icon collection used for menues + +// ****** INTRO ANIMATION RESOURCES ****************************************** + +#include "RCXintro_1.txt" // Bitmap for picture 1 in the intro animation +#include "RCXintro_2.txt" // Bitmap for picture 2 in the intro animation +#include "RCXintro_3.txt" // Bitmap for picture 3 in the intro animation +#include "RCXintro_4.txt" // Bitmap for picture 4 in the intro animation +#include "RCXintro_5.txt" // Bitmap for picture 5 in the intro animation +#include "RCXintro_6.txt" // Bitmap for picture 6 in the intro animation +#include "RCXintro_7.txt" // Bitmap for picture 7 in the intro animation +#include "RCXintro_8.txt" // Bitmap for picture 8 in the intro animation +#include "RCXintro_9.txt" // Bitmap for picture 9 in the intro animation +#include "RCXintro_10.txt" // Bitmap for picture 10 in the intro animation +#include "RCXintro_11.txt" // Bitmap for picture 11 in the intro animation +#include "RCXintro_12.txt" // Bitmap for picture 12 in the intro animation +#include "RCXintro_13.txt" // Bitmap for picture 13 in the intro animation +#include "RCXintro_14.txt" // Bitmap for picture 14 in the intro animation +#include "RCXintro_15.txt" // Bitmap for picture 15 in the intro animation +#include "RCXintro_16.txt" // Bitmap for picture 16 in the intro animation + +const BMPMAP *Intro[NO_OF_INTROBITMAPS] = // Picture sequence for the intro animation +{ + (BMPMAP*)RCXintro_1, + (BMPMAP*)RCXintro_2, + (BMPMAP*)RCXintro_3, + (BMPMAP*)RCXintro_4, + (BMPMAP*)RCXintro_5, + (BMPMAP*)RCXintro_6, + (BMPMAP*)RCXintro_7, + (BMPMAP*)RCXintro_8, + (BMPMAP*)RCXintro_9, + (BMPMAP*)RCXintro_10, + (BMPMAP*)RCXintro_11, + (BMPMAP*)RCXintro_12, + (BMPMAP*)RCXintro_13, + (BMPMAP*)RCXintro_14, + (BMPMAP*)RCXintro_15, + (BMPMAP*)RCXintro_16 +}; + +// ****** STATUS LINE GRAPHIC RESOURCES ************************************** + +#include "Status.txt" // Status icon collection file + +enum STATUS_NO // Index in status icon collection file +{ + STATUS_NO_NOT_USED, + STATUS_NO_RUNNING_0, + STATUS_NO_RUNNING_1, + STATUS_NO_RUNNING_2, + STATUS_NO_RUNNING_3, + STATUS_NO_RUNNING_4, + STATUS_NO_RUNNING_5, + STATUS_NO_RUNNING_6, + STATUS_NO_RUNNING_7, + STATUS_NO_RUNNING_8, + STATUS_NO_RUNNING_9, + STATUS_NO_RUNNING_10, + STATUS_NO_RUNNING_11, + STATUS_NO_BATTERY_0, + STATUS_NO_BATTERY_1, + STATUS_NO_BATTERY_2, + STATUS_NO_BATTERY_3, + STATUS_NO_BATTERY_4, + STATUS_NO_BATTERY_5, + STATUS_NO_RECHARGEABLE_0, + STATUS_NO_RECHARGEABLE_1, + STATUS_NO_RECHARGEABLE_2, + STATUS_NO_RECHARGEABLE_3, + STATUS_NO_RECHARGEABLE_4, + STATUS_NO_RECHARGEABLE_5, + STATUS_NO_BLUETOOTH_0, + STATUS_NO_BLUETOOTH_1, + STATUS_NO_BLUETOOTH_2, + STATUS_NO_BLUETOOTH_3, + STATUS_NO_BLUETOOTH_4, + STATUS_NO_BLUETOOTH_5, + STATUS_NO_USB_0, + STATUS_NO_USB_1, + STATUS_NO_USB_2, + STATUS_NO_USB_3, + STATUS_NO_USB_4, + STATUS_NO_USB_5 +}; + +// ****** BT DEVICE GRAPHIC RESOURCES **************************************** + +#include "Devices.txt" // Icon collection used for Blue tooth devices + +enum +{ + DEVICETYPE_UNKNOWN, + DEVICETYPE_NXT, + DEVICETYPE_PHONE, + DEVICETYPE_PC +}; + +// ****** BT CONNECTIONS GRAPHIC RESOURCES *********************************** + +#include "Connections.txt" // Icon collection used for Blue tooth connections + +// ****** FREE TEXT GRAPHIC RESOURCES **************************************** + +#include "Ui.txt" // Text strings that is'nt defined in menu files + +enum // String index in text string file +{ + TXT_GENERAL_EMPTY, + // BlueTooth connect + TXT_FB_BT_CONNECTING_WAIT, // "Connecting" + TXT_FB_BT_CONNECT_BUSY_FAIL, // "Line is busy" + TXT_FB_BT_CONNECTING_FAIL, // "Failed!" + + // BlueTooth send file + TXT_FB_BT_SENDING_NO_CONN_FAIL, // "Connection?" + TXT_FB_BT_SENDING_WAIT, // "Sending file" + TXT_FB_BT_SENDING_FAIL, // "Failed!" + + // BlueTooth on/off + TXT_FB_BT_TURNING_ON_WAIT, // "Turning on" + TXT_FB_BT_TURNING_ON_FAIL, // "Failed!" + TXT_FB_BT_TURNING_OFF_WAIT, // "Turning off" + TXT_FB_BT_TURNING_OFF_FAIL, // "Failed!" + + // BlueTooth seach + TXT_FB_BT_SEARCHING_WAIT, // "Searching" + TXT_FB_BT_SEARCH_ABORTED_INFO, // "Aborted!" + TXT_FB_BT_SEARCHING_FAIL, // "Failed!" + + // BlueTooth device list + TXT_FB_BT_REMOVE_FAIL, // "Failed!" + + // BlueTooth connection list + TXT_FB_BT_DISCONNECT_FAIL, // "Failed!" + + // On Brick Programming + TXT_FB_OBP_MEMORY_FULL_FAIL, // "Memory full!" + TXT_FB_OBP_FILE_SAVED_INFO, // "File saved" + TXT_FB_OBP_FILE_EXIST_FAIL, // "File exist" + TXT_FB_OBP_OVERWRITE_FAIL, // "overwrite!" + + // File delete + TXT_FB_FD_FILE_DELETED_INFO, // "File deleted" + + // Files delete + TXT_FB_FD_FILES_INFO, // "Files" + TXT_FB_FD_DELETED_INFO, // "deleted" + + // File run + TXT_FILERUN_RUNNING, // "Running" + TXT_FILERUN_ABORTED, // "Aborted!" + TXT_FILERUN_ENDED, // "Ended" + TXT_FILERUN_FILE_ERROR, // "File error!" + + // Files delete + TXT_FILESDELETE_DELETING_ALL, // "Deleting all" + TXT_FILESDELETE_S_FILES, // "%s files!" + + // File types + TXT_FILETYPE_SOUND, // "Sound" + TXT_FILETYPE_LMS, // "Software" + TXT_FILETYPE_NXT, // "NXT" + TXT_FILETYPE_TRY_ME, // "Try me" + TXT_FILETYPE_DATA, // "Datalog" + + // Get user string + TXT_GETUSERSTRING_PIN, // "Pin:" + TXT_GETUSERSTRING_FILENAME, // "Filename:" + + // On Brick Programming + TXT_ONBRICKPROGRAMMING_PLEASE_USE_PORT, // "Please use port:" + TXT_ONBRICKPROGRAMMING_1_TOUCH_SENSOR, // "1 - Touch sensor" + TXT_ONBRICKPROGRAMMING_2_SOUND_SENSOR, // "2 - Sound sensor" + TXT_ONBRICKPROGRAMMING_3_LIGHT_SENSOR, // "3 - Light sensor" + TXT_ONBRICKPROGRAMMING_4_ULTRA_SONIC, // "4 - Ultra sonic" + TXT_ONBRICKPROGRAMMING_BC_LR_MOTORS, // "B/C - L/R motors" + + // View + TXT_VIEW_SELECT, // "Select" + + // BlueTooth device list + TXT_BTDEVICELIST_SELECT, // "Select" + + // BlueTooth connection list + TXT_BTCONNECTLIST_SELECT, // "Select" + + // Bluetooth list errors + TXT_FB_BT_ERROR_LR_COULD_NOT_SAVE_1, // BT save data error! + TXT_FB_BT_ERROR_LR_COULD_NOT_SAVE_2, // + TXT_FB_BT_ERROR_LR_STORE_IS_FULL_1, // BT store is full error! + TXT_FB_BT_ERROR_LR_STORE_IS_FULL_2, // + TXT_FB_BT_ERROR_LR_UNKOWN_ADDR_1, // BT unknown addr. error! + TXT_FB_BT_ERROR_LR_UNKOWN_ADDR_2, // + + // Power of time + TXT_POWEROFFTIME_NEVER // "Never" + +}; + +// ****** FILE TYPE GRAPHIC RESOURCES **************************************** + +#define ALLFILES 0x1A // Icon collection offset + +enum // File type id's +{ + FILETYPE_ALL, // 0 = All + FILETYPE_SOUND, // 1 = Sound + FILETYPE_LMS, // 2 = LMS + FILETYPE_NXT, // 3 = NXT + FILETYPE_TRYME, // 4 = Try me + FILETYPE_DATALOG, // 5 = Datalog + FILETYPES +}; + +const UBYTE TXT_FILE_EXT[FILETYPES][4] = +{ + "*", // 0 = All + TXT_SOUND_EXT, // 1 = Sound + TXT_LMS_EXT, // 2 = LMS + TXT_NXT_EXT, // 3 = NXT + TXT_TRYME_EXT, // 4 = Try me + TXT_DATA_EXT // 5 = Datalog +}; + +const UBYTE TXT_FILETYPE[FILETYPES] = +{ + 0, // NA + TXT_FILETYPE_SOUND, // 1 = Sound + TXT_FILETYPE_LMS, // 2 = LM + TXT_FILETYPE_NXT, // 3 = NXT + TXT_FILETYPE_TRY_ME,// 4 = Try me + TXT_FILETYPE_DATA // 5 = Datalog +}; + +// ****** POWER OFF DEFINITIONS ********************************************** + +#define POWER_OFF_TIME_STEPS 6 +#define POWER_OFF_TIME_DEFAULT 3 + +const UBYTE PowerOffTimeSteps[POWER_OFF_TIME_STEPS] = { 0,2,5,10,30,60 }; // [min] + +// ****** BATTERY DEFINITIONS ************************************************ + +#define BATTERYLIMITS 4 // [Cnt] +#define BATTERYLIMITHYST 100 // [mV] +#define RECHARGEABLELIMITHYST 50 // [mV] + +const UWORD BatteryLimits[BATTERYLIMITS] = +{ + 6100,6500,7000,7500 // [mV] +}; + +const UWORD RechargeableLimits[BATTERYLIMITS] = +{ + 7100,7200,7300,7500 // [mV] +}; + +//******* UI MENU FILE HANDLER ************************************************************************* + +#include "Mainmenu.rms" +#include "Submenu01.rms" +#include "Submenu02.rms" +#include "Submenu04.rms" +#include "Submenu05.rms" +#include "Submenu06.rms" +#include "Submenu07.rms" + + +SWORD cUiMenuFile(UBYTE Cmd,UBYTE *pFile,UBYTE *pData,ULONG *pLng) +{ + SWORD Result; + UBYTE *pFilePointer; + + Result = -1; + switch (Cmd) + { + case OPENREADLINEAR : + { + if (strcmp((char*)pFile,"Mainmenu.rms") == 0) + { + pFilePointer = (UBYTE*)MAINMENU; + Result = 0; + } + if (strcmp((char*)pFile,"Submenu01.rms") == 0) + { + pFilePointer = (UBYTE*)SUBMENU01; + Result = 0; + } + if (strcmp((char*)pFile,"Submenu02.rms") == 0) + { + pFilePointer = (UBYTE*)SUBMENU02; + Result = 0; + } + if (strcmp((char*)pFile,"Submenu04.rms") == 0) + { + pFilePointer = (UBYTE*)SUBMENU04; + Result = 0; + } + if (strcmp((char*)pFile,"Submenu05.rms") == 0) + { + pFilePointer = (UBYTE*)SUBMENU05; + Result = 0; + } + if (strcmp((char*)pFile,"Submenu06.rms") == 0) + { + pFilePointer = (UBYTE*)SUBMENU06; + Result = 0; + } + if (strcmp((char*)pFile,"Submenu07.rms") == 0) + { + pFilePointer = (UBYTE*)SUBMENU07; + Result = 0; + } + if (Result == 0) + { + *pLng = ((UWORD)pFilePointer[2] << 8) + (UWORD)pFilePointer[3] + FILEHEADER_LENGTH; + *((ULONG*)pData) = (ULONG)pFilePointer; + } + } + break; + + } + + return (Result); +} + +//****************************************************************************************************** + +UBYTE* cUiGetString(UBYTE No) // Get string in text string file +{ + UBYTE *Result = NULL; + TXT *pUi; + UWORD Tmp; + + pUi = (TXT*)Ui; + if (No) + { + if (No <= pUi->ItemsY) + { + Tmp = No - 1; + Tmp *= pUi->ItemCharsX; + Result = &(pUi->Data[Tmp]); + } + } + + return (Result); +} + + +UBYTE cUiReadButtons(void) // Read buttons +{ + UBYTE Result = BUTTON_NONE; + + if (!(IOMapUi.Flags & UI_DISABLE_LEFT_RIGHT_ENTER)) + { + if ((pMapButton->State[BTN3] & PRESSED_STATE)) + { + Result = BUTTON_LEFT; + } + if ((pMapButton->State[BTN2] & PRESSED_STATE)) + { + Result = BUTTON_RIGHT; + } + if ((pMapButton->State[BTN4] & PRESSED_STATE)) + { + Result = BUTTON_ENTER; + } + } + if (!(IOMapUi.Flags & UI_DISABLE_EXIT)) + { + if ((pMapButton->State[BTN1] & PRESSED_STATE)) + { + Result = BUTTON_EXIT; + } + } + if (Result == BUTTON_NONE) + { + // All buttons released + VarsUi.ButtonOld = BUTTON_NONE; + VarsUi.ButtonTime = BUTTON_DELAY_TIME; + } + else + { + // Some button pressed + if (VarsUi.ButtonOld == BUTTON_NONE) + { + // Just pressed + VarsUi.ButtonOld = Result; + VarsUi.ButtonTimer = 0; + } + else + { + // Still pressed + Result = BUTTON_NONE; + + if (VarsUi.ButtonTimer >= VarsUi.ButtonTime) + { + VarsUi.ButtonTimer = 0; + VarsUi.ButtonTime = BUTTON_REPEAT_TIME; + if ((VarsUi.ButtonOld == BUTTON_LEFT) || (VarsUi.ButtonOld == BUTTON_RIGHT)) + { + // If arrow repeat + Result = VarsUi.ButtonOld; + } + } + } + } + if (VarsUi.ButtonOld == BUTTON_NONE) + { + // If no key - check interface + Result = IOMapUi.Button; + IOMapUi.Button = BUTTON_NONE; + } + if (Result != BUTTON_NONE) + { + // If key - play key sound file + sprintf((char*)pMapSound->SoundFilename,"%s.%s",(char*)UI_KEYCLICK_SOUND,(char*)TXT_SOUND_EXT); + pMapSound->Volume = IOMapUi.Volume; + pMapSound->Mode = SOUND_ONCE; + pMapSound->Flags |= SOUND_UPDATE; + + // Reset power down timer + IOMapUi.Flags |= UI_RESET_SLEEP_TIMER; + } + + return (Result); +} + + +void cUiListLeft(UBYTE Limit,UBYTE *Center) +{ + UBYTE Tmp; + + Tmp = *Center; + if (Tmp > 1) + { + Tmp--; + } + else + { + if (Limit > 2) + { + Tmp = Limit; + } + } + *Center = Tmp; +} + + +void cUiListRight(UBYTE Limit,UBYTE *Center) +{ + UBYTE Tmp; + + Tmp = *Center; + if (Tmp < Limit) + { + Tmp++; + } + else + { + if (Limit > 2) + { + Tmp = 1; + } + } + *Center = Tmp; +} + + +void cUiListCalc(UBYTE Limit,UBYTE *Center,UBYTE *Left,UBYTE *Right) +{ + switch (Limit) + { + case 1 : + { + *Left = 0; + *Right = 0; + } + break; + + case 2 : + { + if ((*Center) == 1) + { + *Left = 0; + *Right = 2; + } + else + { + *Left = 1; + *Right = 0; + } + } + break; + + default : + { + *Left = *Center - 1; + if ((*Left) < 1) + { + *Left = Limit; + } + *Right = *Center + 1; + if ((*Right) > Limit) + { + *Right = 1; + } + } + break; + + } +} + + +UBYTE* cUiGetMenuPointer(UBYTE FileNo) +{ + ULONG Lng; + UWORD Handle; + UBYTE TmpBuffer[FILENAME_LENGTH + 1]; + UBYTE *pPointer; + + if (FileNo) + { + sprintf((char*)TmpBuffer,"Submenu%02X.rms",(UWORD)FileNo); + } + else + { + sprintf((char*)TmpBuffer,"Mainmenu.rms"); + } + Handle = cUiMenuFile(OPENREADLINEAR,TmpBuffer,(UBYTE*)&pPointer,&Lng); + if ((Handle & 0x8000)) + { + pPointer = NULL; + } + else + { + cUiMenuFile(CLOSE,(UBYTE*)&Handle,NULL,NULL); + } + + return (pPointer); +} + + +ULONG cUiMenuGetId(MENUITEM *pMenuItem) +{ + ULONG MenuId; + + MenuId = (ULONG)pMenuItem->ItemId01; + MenuId |= (ULONG)pMenuItem->ItemId23 << 8; + MenuId |= (ULONG)pMenuItem->ItemId45 << 16; + MenuId |= (ULONG)pMenuItem->ItemId67 << 24; + + return (MenuId); +} + + +ULONG cUiMenuGetSpecialMask(MENUITEM *pMenuItem) +{ + ULONG Mask; + + Mask = 0; + if (pMenuItem != NULL) + { + Mask = (ULONG)pMenuItem->SpecialMask0; + Mask |= (ULONG)pMenuItem->SpecialMask1 << 8; + Mask |= (ULONG)pMenuItem->SpecialMask2 << 16; + Mask |= (ULONG)pMenuItem->SpecialMask3 << 24; + } + + return (Mask); +} + + +UBYTE* cUiMenuGetIconImage(UBYTE No) +{ + UBYTE *Image; + + Image = NULL; + if (No < (Icons->ItemsX * Icons->ItemsY)) + { + Image = (UBYTE*)&Icons->Data[No * Icons->ItemPixelsX * (Icons->ItemPixelsY / 8)]; + } + + return (Image); +} + + +ULONG cUiMenuMotherId(ULONG Id,UBYTE Level) +{ + ULONG MotherIdMask; + + MotherIdMask = 0xFFFFFFFFL >> ((8 - Level) * 4); + MotherIdMask |= 0xFFFFFFFFL << ((Level + 1) * 4); + + return (Id & MotherIdMask); +} + + +UBYTE cUiMenuIdValid(MENUFILE *pMenuFile,ULONG Id) +{ + ULONG SpecialMask; + ULONG MotherId; + UBYTE Level; + UBYTE Result; + + Result = FALSE; + Level = pMenuFile->MenuLevel; + + if (Level) + { + SpecialMask = pMenuFile->MenuLevels[Level - 1].SpecialFlags; + MotherId = pMenuFile->MenuLevels[Level - 1].Id; + if ((SpecialMask & MENU_SKIP_THIS_MOTHER_ID)) + { + MotherId &= ~(0x0000000F << ((Level - 1) * 4)); + SpecialMask >>= 28; + MotherId |= (SpecialMask << ((Level - 1) * 4)); + } + if (MotherId == cUiMenuMotherId(Id,Level)) + { + Id >>= (Level * 4); + if ((Id & 0x0000000F) && (!(Id & 0xFFFFFFF0))) + { + Result = TRUE; + } + } + } + else + { + Id >>= (Level * 4); + if ((Id & 0x0000000F) && (!(Id & 0xFFFFFFF0))) + { + Result = TRUE; + } + } + + return (Result); +} + + +UBYTE cUiMenuGetNoOfMenus(MENU *pMenu,MENUFILE *pMenuFile) +{ + ULONG MenuId; + UBYTE NoOfMenus; + UBYTE Index; + + NoOfMenus = 0; + for (Index = 0;Index < pMenu->Items;Index++) + { + MenuId = cUiMenuGetId(&pMenu->Data[Index]); + + if (cUiMenuIdValid(pMenuFile,MenuId) == TRUE) + { + if ((cUiMenuGetSpecialMask(&pMenu->Data[Index]) & MENU_ONLY_BT_ON)) + { + // BT module must be on + if (!(IOMapUi.BluetoothState & BT_STATE_OFF)) + { + // Yes + NoOfMenus++; + } + } + else + { + if ((cUiMenuGetSpecialMask(&pMenu->Data[Index]) & MENU_ONLY_DATALOG_ENABLED)) + { + // Datalog menu must be enabled + if (!(VarsUi.NVData & 0x80)) + { + // Yes + NoOfMenus++; + } + } + else + { + // No restrictions + NoOfMenus++; + } + } + } + } + + return (NoOfMenus); +} + + +UBYTE cUiGetMenuItemIndex(MENU *pMenu,MENUFILE *pMenuFile,UBYTE No) +{ + ULONG MenuId; + UBYTE NoOfMenus; + UBYTE Index; + UBYTE TmpIndex = 0; + + NoOfMenus = 0; + for (Index = 0;(Index < pMenu->Items) && (No != NoOfMenus);Index++) + { + MenuId = cUiMenuGetId(&pMenu->Data[Index]); + + if (cUiMenuIdValid(pMenuFile,MenuId) == TRUE) + { + if ((cUiMenuGetSpecialMask(&pMenu->Data[Index]) & MENU_ONLY_BT_ON)) + { + // BT module must be on + if (!(IOMapUi.BluetoothState & BT_STATE_OFF)) + { + // Yes + TmpIndex = Index; + NoOfMenus++; + } + } + else + { + if ((cUiMenuGetSpecialMask(&pMenu->Data[Index]) & MENU_ONLY_DATALOG_ENABLED)) + { + // Datalog menu must be enabled + if (!(VarsUi.NVData & 0x80)) + { + // Yes + TmpIndex = Index; + NoOfMenus++; + } + } + else + { + // No restrictions + TmpIndex = Index; + NoOfMenus++; + } + } + } + } + if (No != NoOfMenus) + { + Index = TmpIndex + 1; + } + + return (Index); +} + + + +UBYTE cUiMenuGetNo(MENU *pMenu,ULONG Id,UBYTE Level) +{ + ULONG MenuId; + ULONG MotherId; + UBYTE Index; + UBYTE No; + UBYTE NoOfItems; + + No = 0; + NoOfItems = 0; + + MotherId = cUiMenuMotherId(Id,Level); + + for (Index = 0;(Index < pMenu->Items) && (No == 0);Index++) + { + MenuId = cUiMenuGetId(&pMenu->Data[Index]); + + // Scanning all id's until No is found + if (!(MenuId >> ((Level + 1) * 4))) + { + // MenuId is above or on actual level + if (((MenuId >> (Level * 4)) & 0x0000000F)) + { + // MenuId is on actual level + if (MotherId == cUiMenuMotherId(MenuId,Level)) + { + // Same mother id + NoOfItems++; + if (MenuId == Id) + { + No = NoOfItems; + } + } + } + } + } + + return (No); +} + +void cUiUpdateStatus(void) +{ + UWORD Tmp; + UWORD Hyst; + UWORD *pTmp; + UBYTE Pointer; + + if (++VarsUi.UpdateCounter >= RUN_STATUS_CHANGE_TIME) + { + VarsUi.UpdateCounter = 0; + + // Update running status icon pointer + if (++VarsUi.Running >= 12) + { + VarsUi.Running = 0; + } + + // Get battery voltage limits + if ((IoFromAvr.Battery & 0x8000)) + { + IOMapUi.Rechargeable = 1; + pTmp = (UWORD*)RechargeableLimits; + Hyst = RECHARGEABLELIMITHYST; + } + else + { + IOMapUi.Rechargeable = 0; + pTmp = (UWORD*)BatteryLimits; + Hyst = BATTERYLIMITHYST; + } + + // Calculate battery voltage + Tmp = IoFromAvr.Battery & 0x03FF; + Tmp = (UWORD)((float)Tmp * BATTERY_COUNT_TO_MV); + + IOMapUi.BatteryVoltage = Tmp; + + // Find new battery state + Pointer = 0; + while ((Tmp > pTmp[Pointer]) && (Pointer < BATTERYLIMITS)) + { + Pointer++; + } + + // Change battery state + if (Pointer != IOMapUi.BatteryState) + { + if (Pointer > IOMapUi.BatteryState) + { + if (Tmp > (pTmp[IOMapUi.BatteryState] + Hyst)) + { + IOMapUi.BatteryState = Pointer; + } + } + else + { + IOMapUi.BatteryState = Pointer; + } + } + + // Control toggle and bitmap + if (IOMapUi.BatteryState) + { + VarsUi.BatteryToggle = 0; + VarsUi.LowBatt = 0; + } + else + { + if (VarsUi.LowBatt < 255) + { + VarsUi.LowBatt++; + } + + if (VarsUi.BatteryToggle) + { + VarsUi.BatteryToggle = 0; + } + else + { + VarsUi.BatteryToggle = 1; + } + } + + // Ensure frequently status updates + IOMapUi.Flags |= UI_UPDATE; + } + + if ((IOMapUi.Flags & UI_ENABLE_STATUS_UPDATE)) + { + if ((IOMapUi.Flags & UI_UPDATE) || (IOMapUi.Flags & UI_REDRAW_STATUS)) + { + VarsUi.ErrorTimer = 0; + pMapDisplay->pStatusText = (UBYTE*)VarsUi.StatusText; + + // Status line update nessesary + if (IOMapUi.BatteryState < Status->ItemsX) + { + // Update battery status icons + if (IoFromAvr.Battery & 0x8000) + { + VarsUi.NewStatusIcons[STATUSICON_BATTERY] = STATUS_NO_RECHARGEABLE_0 + IOMapUi.BatteryState + VarsUi.BatteryToggle; + } + else + { + VarsUi.NewStatusIcons[STATUSICON_BATTERY] = STATUS_NO_BATTERY_0 + IOMapUi.BatteryState + VarsUi.BatteryToggle; + } + } + + // Update bluetooth status icons + if ((IOMapUi.BluetoothState & (BT_STATE_VISIBLE | BT_STATE_CONNECTED | BT_STATE_OFF)) < Status->ItemsX) + { + VarsUi.NewStatusIcons[STATUSICON_BLUETOOTH] = STATUS_NO_BLUETOOTH_0 + (IOMapUi.BluetoothState & (BT_STATE_VISIBLE | BT_STATE_CONNECTED | BT_STATE_OFF)); + } + + // Update usb status icons + if (IOMapUi.UsbState < 6) + { + VarsUi.NewStatusIcons[STATUSICON_USB] = STATUS_NO_USB_0 + IOMapUi.UsbState; + } + + // Update running status icons + if (IOMapUi.RunState == FALSE) + { + VarsUi.Running = 0; + } + VarsUi.NewStatusIcons[STATUSICON_VM] = STATUS_NO_RUNNING_0 + VarsUi.Running; + + // Update only changed status icons + for (Pointer = 0;Pointer < STATUSICONS;Pointer++) + { + if ((pMapDisplay->StatusIcons[Pointer] != VarsUi.NewStatusIcons[Pointer])) + { + pMapDisplay->StatusIcons[Pointer] = VarsUi.NewStatusIcons[Pointer]; + pMapDisplay->UpdateMask |= STATUSICON_BIT(Pointer); + } + } + + if ((IOMapUi.Flags & UI_REDRAW_STATUS)) + { + // Entire status line needs to be redrawed + if (pMapComm->BrickData.Name[0]) + { + for (Pointer = 0;Pointer < STATUSTEXT_SIZE;Pointer++) + { + VarsUi.StatusText[Pointer] = pMapComm->BrickData.Name[Pointer]; + } + VarsUi.StatusText[Pointer] = 0; + } + pMapDisplay->EraseMask |= SPECIAL_BIT(STATUSTEXT); + pMapDisplay->UpdateMask |= SPECIAL_BIT(STATUSTEXT); + pMapDisplay->UpdateMask |= (SPECIAL_BIT(TOPLINE) | STATUSICON_BITS); + } + + // Clear update flag + IOMapUi.Flags &= ~UI_REDRAW_STATUS; + IOMapUi.Flags &= ~UI_UPDATE; + } + } + else + { + pMapDisplay->UpdateMask &= ~(STATUSICON_BITS | SPECIAL_BIT(TOPLINE) | SPECIAL_BIT(STATUSTEXT)); + } +} + + + + +void cUiMenuCallFunction(UBYTE Function,UBYTE Parameter) +{ + if (Function) + { + VarsUi.Function = Function; + VarsUi.Parameter = Parameter; + } +} + + +void cUiMenuNextFile(void) +{ + MENU *pTmpMenu; + + pTmpMenu = (MENU*)cUiGetMenuPointer(VarsUi.pMenuLevel->NextFileNo); + if (pTmpMenu != NULL) + { + if (VarsUi.MenuFileLevel < (MENUFILELEVELS - 1)) + { + VarsUi.MenuFileLevel++; + VarsUi.MenuFiles[VarsUi.MenuFileLevel].FileId = VarsUi.pMenuLevel->NextFileNo; + VarsUi.MenuFiles[VarsUi.MenuFileLevel].MenuLevel = 0; + VarsUi.MenuFiles[VarsUi.MenuFileLevel].MenuLevels[VarsUi.MenuFiles[VarsUi.MenuFileLevel].MenuLevel].ItemIndex = VarsUi.pMenuLevel->NextMenuNo; + IOMapUi.pMenu = pTmpMenu; + } + } +} + + +void cUiMenuPrevFile(void) +{ + if (VarsUi.MenuFileLevel) + { + VarsUi.MenuFileLevel--; + IOMapUi.pMenu = (MENU*)cUiGetMenuPointer(VarsUi.MenuFiles[VarsUi.MenuFileLevel].FileId); + } +} + + +void cUiMenuNext(void) +{ + if (VarsUi.pMenuFile->MenuLevel < (MENULEVELS - 1)) + { + VarsUi.pMenuFile->MenuLevel++; + VarsUi.pMenuFile->MenuLevels[VarsUi.pMenuFile->MenuLevel].ItemIndex = VarsUi.pMenuLevel->NextMenuNo; + } +} + + +void cUiMenuPrev(void) +{ + if (VarsUi.pMenuFile->MenuLevel) + { + VarsUi.pMenuFile->MenuLevel--; + } +} + + +void cUiMenuEnter(void) +{ + // Call function with parameter (if pressent) + if (!(VarsUi.pMenuLevel->SpecialFlags & MENU_INIT_CALLS)) + { + cUiMenuCallFunction(VarsUi.pMenuLevel->FunctionNo,VarsUi.pMenuLevel->Parameter); + } + + if (VarsUi.EnterOnlyCalls != TRUE) + { + if ((VarsUi.pMenuLevel->SpecialFlags & MENU_ENTER_LEAVES_MENUFILE)) + { + cUiMenuPrevFile(); + } + else + { + // Load new menu file (if pressent) + if (VarsUi.pMenuLevel->NextFileNo) + { + cUiMenuNextFile(); + } + else + { + // Activate next menu level (if pressent) + if (VarsUi.pMenuLevel->NextMenuNo) + { + cUiMenuNext(); + } + } + } + IOMapUi.State = NEXT_MENU; + } + else + { + VarsUi.EnterOnlyCalls = FALSE; + IOMapUi.State = DRAW_MENU; + } +} + + +void cUiMenuExit(void) +{ + + if ((VarsUi.pMenuLevel->SpecialFlags & MENU_EXIT_CALLS)) + { + // Call function with parameter (if pressent) + if (!(VarsUi.pMenuLevel->SpecialFlags & MENU_INIT_CALLS)) + { + cUiMenuCallFunction(VarsUi.pMenuLevel->FunctionNo,VarsUi.pMenuLevel->Parameter); + } + } + + // Call function with 0xFF (if ordered) + if ((VarsUi.pMenuLevel->SpecialFlags & MENU_EXIT_CALLS_WITH_FF)) + { + cUiMenuCallFunction(VarsUi.pMenuLevel->FunctionNo,MENU_EXIT); + } + + if (VarsUi.ExitOnlyCalls != TRUE) + { + if ((VarsUi.pMenuFile->MenuLevel) && (!(VarsUi.pMenuLevel->SpecialFlags & MENU_EXIT_LEAVES_MENUFILE))) + { + if (!(VarsUi.pMenuLevel->SpecialFlags & MENU_EXIT_LOAD_MENU)) + { + cUiMenuPrev(); + if ((VarsUi.pMenuLevel->SpecialFlags & MENU_BACK_TWICE)) + { + if (VarsUi.pMenuFile->MenuLevel) + { + cUiMenuPrev(); + } + VarsUi.SecondTime = FALSE; + } + if ((VarsUi.pMenuLevel->SpecialFlags & MENU_BACK_THREE_TIMES)) + { + if (VarsUi.pMenuFile->MenuLevel) + { + cUiMenuPrev(); + } + if (VarsUi.pMenuFile->MenuLevel) + { + cUiMenuPrev(); + } + VarsUi.SecondTime = FALSE; + } + } + else + { + VarsUi.EnterOnlyCalls = FALSE; + VarsUi.ExitOnlyCalls = FALSE; + if (VarsUi.pMenuLevel->NextFileNo) + { + cUiMenuNextFile(); + } + else + { + // Activate next menu level (if pressent) + if (VarsUi.pMenuLevel->NextMenuNo) + { + cUiMenuNext(); + } + } + } + if ((VarsUi.pMenuLevel->SpecialFlags & MENU_EXIT_LOAD_POINTER)) + { + VarsUi.pMenuFile->MenuLevels[VarsUi.pMenuFile->MenuLevel].ItemIndex = (UBYTE)((VarsUi.pMenuLevel->SpecialFlags) >> 24) & 0x0F; + } + } + else + { + if (!(VarsUi.pMenuLevel->SpecialFlags & MENU_EXIT_LOAD_MENU)) + { + cUiMenuPrevFile(); + } + else + { + VarsUi.EnterOnlyCalls = FALSE; + VarsUi.ExitOnlyCalls = FALSE; + if (VarsUi.pMenuLevel->NextFileNo) + { + cUiMenuNextFile(); + } + else + { + // Activate next menu level (if pressent) + if (VarsUi.pMenuLevel->NextMenuNo) + { + cUiMenuNext(); + } + } + } + } + IOMapUi.State = NEXT_MENU; + } + else + { + VarsUi.ExitOnlyCalls = FALSE; + IOMapUi.State = DRAW_MENU; + } +} + + +void cUiLoadLevel(UBYTE FileLevel,UBYTE MenuLevel,UBYTE MenuIndex) +{ + UBYTE Tmp; + + VarsUi.MenuFileLevel = FileLevel; + VarsUi.MenuFiles[FileLevel].MenuLevel = MenuLevel; + VarsUi.MenuFiles[FileLevel].MenuLevels[MenuLevel].ItemIndex = MenuIndex; + IOMapUi.pMenu = (MENU*)cUiGetMenuPointer(VarsUi.MenuFiles[VarsUi.MenuFileLevel].FileId); + + VarsUi.pMenuFile = &VarsUi.MenuFiles[VarsUi.MenuFileLevel]; + VarsUi.pMenuLevel = &VarsUi.pMenuFile->MenuLevels[VarsUi.pMenuFile->MenuLevel]; + + // Count no of menues on current level + VarsUi.pMenuLevel->Items = cUiMenuGetNoOfMenus(IOMapUi.pMenu,VarsUi.pMenuFile); + + if (VarsUi.pMenuLevel->Items) + { + // if items > 0 -> prepare allways center icon + Tmp = cUiGetMenuItemIndex(IOMapUi.pMenu,VarsUi.pMenuFile,VarsUi.pMenuLevel->ItemIndex); + + if (VarsUi.pMenuItem != &IOMapUi.pMenu->Data[Tmp - 1]) + { + VarsUi.pMenuItem = &IOMapUi.pMenu->Data[Tmp - 1]; + VarsUi.SecondTime = FALSE; + } + + // Save center menu item parameters + VarsUi.pMenuLevel->Id = cUiMenuGetId(VarsUi.pMenuItem); + VarsUi.pMenuLevel->IconImageNo = VarsUi.pMenuItem->IconImageNo; + VarsUi.pMenuLevel->IconText = VarsUi.pMenuItem->IconText; + VarsUi.pMenuLevel->SpecialFlags = cUiMenuGetSpecialMask(VarsUi.pMenuItem); + VarsUi.pMenuLevel->FunctionNo = VarsUi.pMenuItem->FunctionIndex; + VarsUi.pMenuLevel->Parameter = VarsUi.pMenuItem->FunctionParameter; + VarsUi.pMenuLevel->NextFileNo = VarsUi.pMenuItem->FileLoadNo; + VarsUi.pMenuLevel->NextMenuNo = VarsUi.pMenuItem->NextMenu; + } +} + +#include "Functions.inl" + + +void cUiInit(void* pHeader) +{ + pHeaders = pHeader; + VarsUi.Initialized = FALSE; + IOMapUi.BluetoothState = BT_STATE_OFF; + IOMapUi.UsbState = 0; + IOMapUi.State = INIT_DISPLAY; +} + + +void cUiCtrl(void) +{ + UBYTE Tmp; + +// Testcode for low battery voltage +/* + if ((pMapInput->Inputs[0].InvalidData != INVALID_DATA) && (pMapInput->Inputs[0].ADRaw < 500)) + { + if (VarsUi.LowBatt < 255) + { + VarsUi.LowBatt++; + } + } + else + { + VarsUi.LowBatt = 0; + } +*/ +// + +// Testcode for BT connect request +/* + if ((pMapInput->Inputs[0].InvalidData != INVALID_DATA) && (pMapInput->Inputs[0].ADRaw < 500)) + { + IOMapUi.BluetoothState |= BT_CONNECT_REQUEST | BT_PIN_REQUEST; + } +*/ +// + +// Testcode for BT error attention +/* + if ((pMapInput->Inputs[0].InvalidData != INVALID_DATA) && (pMapInput->Inputs[0].ADRaw < 500)) + { + IOMapUi.Error = LR_UNKOWN_ADDR; + IOMapUi.BluetoothState |= BT_ERROR_ATTENTION; + } +*/ +// + +// Testcode for execute program +/* + if ((pMapInput->Inputs[0].InvalidData != INVALID_DATA) && (pMapInput->Inputs[0].ADRaw < 500)) + { + if ((!(IOMapUi.Flags & UI_EXECUTE_LMS_FILE)) && (IOMapUi.State > INIT_MENU)) + { + strcpy((char*)IOMapUi.LMSfilename,"Untitled-1.rxe"); + IOMapUi.Flags |= UI_EXECUTE_LMS_FILE; + } + } +*/ +// + +// Testcode for force off +/* + if ((pMapInput->Inputs[0].InvalidData != INVALID_DATA) && (pMapInput->Inputs[0].ADRaw < 500) && (VarsUi.Initialized == TRUE)) + { + IOMapUi.ForceOff = TRUE; + } +*/ +// + + + VarsUi.CRPasskey++; + VarsUi.ButtonTimer++; + VarsUi.OBPTimer++; + switch (IOMapUi.State) + { + case INIT_DISPLAY : // Load font and icons + { + VarsUi.Initialized = FALSE; + + IOMapUi.Flags = UI_BUSY; + IOMapUi.RunState = 1; + IOMapUi.BatteryState = 0; + IOMapUi.Error = 0; + IOMapUi.ForceOff = FALSE; + VarsUi.LowBatt = 0; + VarsUi.LowBattHasOccured = 0; + + pMapDisplay->pFont = (FONT*)Font; + pMapDisplay->pStatusIcons = (ICON*)Status; + pMapDisplay->pStatusText = (UBYTE*)VarsUi.StatusText; + pMapDisplay->pStepIcons = (ICON*)Step; + + VarsUi.State = 0; + VarsUi.Pointer = 0; + VarsUi.Timer = -INTRO_START_TIME; + + VarsUi.FNOFState = 0; + VarsUi.FBState = 0; + + VarsUi.UpdateCounter = 0; + VarsUi.Running = 0; + VarsUi.BatteryToggle = 0; + + VarsUi.GUSState = 0; + + IOMapUi.pMenu = (MENU*)cUiGetMenuPointer(0); + IOMapUi.State = INIT_INTRO; + + pMapDisplay->EraseMask = SCREEN_BIT(SCREEN_BACKGROUND); + pMapDisplay->pBitmaps[BITMAP_1] = (BMPMAP*)Intro[VarsUi.Pointer]; + pMapDisplay->UpdateMask = BITMAP_BIT(BITMAP_1); + pMapDisplay->Flags |= DISPLAY_ON; + + cUiNVReadByte(); + IOMapUi.Volume = cUiNVReadVolumeCount(); + IOMapUi.SleepTimeout = PowerOffTimeSteps[cUiNVReadPowerOnTimeCount()]; + } + break; + + case INIT_LOW_BATTERY : + { + if (++VarsUi.Timer >= (INTRO_LOWBATT_TIME)) + { + VarsUi.LowBattHasOccured = 2; + pMapDisplay->EraseMask = SCREEN_BIT(SCREEN_BACKGROUND); + pMapDisplay->pBitmaps[BITMAP_1] = (BMPMAP*)Intro[VarsUi.Pointer]; + pMapDisplay->UpdateMask = BITMAP_BIT(BITMAP_1); + IOMapUi.Flags &= ~UI_ENABLE_STATUS_UPDATE; + VarsUi.State = 0; + VarsUi.Pointer = 0; + VarsUi.Timer = -INTRO_START_TIME; + IOMapUi.State = INIT_INTRO; + } + } + break; + + case INIT_INTRO : + { + if (VarsUi.LowBattHasOccured == 1) + { + IOMapUi.Flags |= UI_ENABLE_STATUS_UPDATE; + IOMapUi.Flags |= UI_UPDATE; + IOMapUi.Flags |= UI_REDRAW_STATUS; + VarsUi.Timer = 0; + IOMapUi.State = INIT_LOW_BATTERY; + } + else + { + if (VarsUi.LowBattHasOccured == 0) + { + if (VarsUi.LowBatt) + { + pMapDisplay->pBitmaps[BITMAP_1] = (BMPMAP*)LowBattery; + pMapDisplay->UpdateMask = BITMAP_BIT(BITMAP_1); + VarsUi.LowBattHasOccured = 1; + } + } + if (++VarsUi.Timer >= (INTRO_SHIFT_TIME)) + { + switch (VarsUi.State) + { + case 0 : + { + pMapDisplay->Flags &= ~DISPLAY_REFRESH; + VarsUi.State++; + } + break; + + case 1 : + { + if ((pMapDisplay->Flags & DISPLAY_REFRESH_DISABLED)) + { + if (VarsUi.Pointer < NO_OF_INTROBITMAPS) + { + pMapDisplay->EraseMask |= BITMAP_BIT(BITMAP_1); + pMapDisplay->pBitmaps[BITMAP_1] = (BMPMAP*)Intro[VarsUi.Pointer]; + pMapDisplay->UpdateMask = BITMAP_BIT(BITMAP_1); + if (VarsUi.Pointer == 11) + { + sprintf((char*)pMapSound->SoundFilename,"%s.%s",(char*)UI_STARTUP_SOUND,(char*)TXT_SOUND_EXT); + pMapSound->Volume = IOMapUi.Volume; + pMapSound->Mode = SOUND_ONCE; + pMapSound->Flags |= SOUND_UPDATE; + } + VarsUi.Pointer++; + } + else + { + pMapDisplay->Flags |= DISPLAY_REFRESH; + IOMapUi.State = INIT_WAIT; + } + VarsUi.State++; + } + } + break; + + default : + { + if (!(pMapDisplay->UpdateMask & BITMAP_BIT(BITMAP_1))) + { + pMapDisplay->Flags |= DISPLAY_REFRESH; + VarsUi.Timer = 0; + VarsUi.State = 0; + } + } + break; + + } + } + } + } + break; + + case INIT_WAIT : + { + if (++VarsUi.Timer >= INTRO_STOP_TIME) + { + pMapDisplay->EraseMask |= SCREEN_BIT(SCREEN_BACKGROUND); + IOMapUi.State = INIT_MENU; + } + } + break; + + case INIT_MENU : + { + // Restart menu system + VarsUi.Function = 0; + VarsUi.MenuFileLevel = 0; + + cUiLoadLevel(0,0,1); + cUiLoadLevel(0,1,1); + + VarsUi.EnterOnlyCalls = FALSE; + VarsUi.ExitOnlyCalls = FALSE; + + IOMapUi.State = NEXT_MENU; + } + break; + + case NEXT_MENU : // prepare icons + { + // Init various variables + VarsUi.State = 0; + + // Init icon pointers + pMapDisplay->pMenuIcons[MENUICON_LEFT] = NULL; + pMapDisplay->pMenuIcons[MENUICON_CENTER] = NULL; + pMapDisplay->pMenuIcons[MENUICON_RIGHT] = NULL; + + cUiLoadLevel(VarsUi.MenuFileLevel,VarsUi.MenuFiles[VarsUi.MenuFileLevel].MenuLevel,VarsUi.MenuFiles[VarsUi.MenuFileLevel].MenuLevels[VarsUi.MenuFiles[VarsUi.MenuFileLevel].MenuLevel].ItemIndex); + + // Find menu icons + if (VarsUi.pMenuLevel->Items) + { + // Prepare center icon + pMapDisplay->pMenuIcons[MENUICON_CENTER] = cUiMenuGetIconImage(VarsUi.pMenuLevel->IconImageNo); + pMapDisplay->pMenuText = VarsUi.pMenuLevel->IconText; + + if (VarsUi.pMenuLevel->Items == 2) + { + // if 2 menues -> prepare left or right icon + if (VarsUi.pMenuLevel->ItemIndex == 1) + { + Tmp = cUiGetMenuItemIndex(IOMapUi.pMenu,VarsUi.pMenuFile,2); + if (Tmp) + { + Tmp--; + pMapDisplay->pMenuIcons[MENUICON_RIGHT] = cUiMenuGetIconImage(IOMapUi.pMenu->Data[Tmp].IconImageNo); + } + } + else + { + Tmp = cUiGetMenuItemIndex(IOMapUi.pMenu,VarsUi.pMenuFile,1); + if (Tmp) + { + Tmp--; + pMapDisplay->pMenuIcons[MENUICON_LEFT] = cUiMenuGetIconImage(IOMapUi.pMenu->Data[Tmp].IconImageNo); + } + } + } + + if (VarsUi.pMenuLevel->Items > 2) + { + // if more menues -> prepare left and right icon + if (VarsUi.pMenuLevel->ItemIndex > 1) + { + Tmp = VarsUi.pMenuLevel->ItemIndex -1; + } + else + { + Tmp = VarsUi.pMenuLevel->Items; + } + Tmp = cUiGetMenuItemIndex(IOMapUi.pMenu,VarsUi.pMenuFile,Tmp); + if (Tmp) + { + Tmp--; + pMapDisplay->pMenuIcons[MENUICON_LEFT] = cUiMenuGetIconImage(IOMapUi.pMenu->Data[Tmp].IconImageNo); + + } + if (VarsUi.pMenuLevel->ItemIndex < VarsUi.pMenuLevel->Items) + { + Tmp = VarsUi.pMenuLevel->ItemIndex + 1; + } + else + { + Tmp = 1; + } + Tmp = cUiGetMenuItemIndex(IOMapUi.pMenu,VarsUi.pMenuFile,Tmp); + if (Tmp) + { + Tmp--; + pMapDisplay->pMenuIcons[MENUICON_RIGHT] = cUiMenuGetIconImage(IOMapUi.pMenu->Data[Tmp].IconImageNo); + } + } + } + if ((VarsUi.pMenuLevel->SpecialFlags & MENU_ENTER_ONLY_CALLS)) + { + VarsUi.EnterOnlyCalls = TRUE; + } + if ((VarsUi.pMenuLevel->SpecialFlags & MENU_EXIT_ONLY_CALLS)) + { + VarsUi.ExitOnlyCalls = TRUE; + } + + IOMapUi.State = DRAW_MENU; + } + break; + + case DRAW_MENU : // If no function active -> erase screen, draw statusline and menu icons + { + if (VarsUi.Function) + { + // Function active + if (VarsUi.Function < FUNC_NO_MAX) + { + if (Functions[VarsUi.Function](VarsUi.Parameter) == 0) + { + VarsUi.Function = 0; + } + } + else + { + VarsUi.Function = 0; + } + } + else + { + // function inactive - erase screen + if (!(VarsUi.pMenuLevel->SpecialFlags & MENU_LEAVE_BACKGROUND)) + { + pMapDisplay->EraseMask |= SCREEN_BIT(SCREEN_LARGE); + + // Draw only icons, frame and icon text + pMapDisplay->UpdateMask = (MENUICON_BITS | SPECIAL_BIT(FRAME_SELECT) | SPECIAL_BIT(MENUTEXT)); + pMapDisplay->TextLinesCenterFlags = 0; + } + else + { + pMapDisplay->EraseMask |= (SPECIAL_BIT(MENUTEXT) | MENUICON_BITS); + + // Draw icons, frame and icon text + pMapDisplay->UpdateMask |= (MENUICON_BITS | SPECIAL_BIT(FRAME_SELECT) | SPECIAL_BIT(MENUTEXT)); + } + + // Draw status + IOMapUi.Flags |= (UI_ENABLE_STATUS_UPDATE | UI_UPDATE | UI_REDRAW_STATUS); + + if ((VarsUi.pMenuLevel->SpecialFlags & MENU_INIT_CALLS_WITH_0) && (VarsUi.SecondTime == FALSE)) + { + VarsUi.SecondTime = TRUE; + cUiMenuCallFunction(VarsUi.pMenuLevel->FunctionNo,MENU_INIT); + } + else + { + if ((VarsUi.pMenuLevel->SpecialFlags & MENU_INIT_CALLS_WITH_1) && (VarsUi.SecondTime == FALSE)) + { + VarsUi.SecondTime = TRUE; + cUiMenuCallFunction(VarsUi.pMenuLevel->FunctionNo,MENU_INIT_ALTERNATIVE); + } + else + { + if ((VarsUi.pMenuLevel->SpecialFlags & MENU_INIT_CALLS) && (VarsUi.SecondTime == FALSE)) + { + VarsUi.SecondTime = TRUE; + cUiMenuCallFunction(VarsUi.pMenuLevel->FunctionNo,VarsUi.pMenuLevel->Parameter); + } + else + { + if ((VarsUi.pMenuLevel->SpecialFlags & MENU_AUTO_PRESS_ENTER)) + { + IOMapUi.State = ENTER_PRESSED; + } + else + { + IOMapUi.State = TEST_BUTTONS; + } + } + } + } + } + } + break; + + case TEST_BUTTONS : // Test buttons to execute new functions and new menus + { + if (VarsUi.Initialized == FALSE) + { + VarsUi.Initialized = TRUE; + IOMapUi.Flags &= ~UI_BUSY; + } + + switch (cUiReadButtons()) + { + case BUTTON_LEFT : + { + IOMapUi.State = LEFT_PRESSED; + } + break; + + case BUTTON_RIGHT : + { + IOMapUi.State = RIGHT_PRESSED; + } + break; + + case BUTTON_ENTER : + { + IOMapUi.State = ENTER_PRESSED; + } + break; + + case BUTTON_EXIT : + { + if (!(VarsUi.pMenuLevel->SpecialFlags & MENU_EXIT_DISABLE)) + { + IOMapUi.State = EXIT_PRESSED; + } + } + break; + + } + + } + break; + + case LEFT_PRESSED : + { + if ((VarsUi.pMenuLevel->SpecialFlags & MENU_LEFT_RIGHT_AS_CALL)) + { + cUiMenuCallFunction(VarsUi.pMenuLevel->FunctionNo,MENU_LEFT); + } + else + { + VarsUi.SecondTime = FALSE; + VarsUi.EnterOnlyCalls = FALSE; + VarsUi.ExitOnlyCalls = FALSE; + + if (VarsUi.pMenuLevel->ItemIndex > 1) + { + VarsUi.pMenuLevel->ItemIndex--; + } + else + { + if (VarsUi.pMenuLevel->Items > 2) + { + VarsUi.pMenuLevel->ItemIndex = VarsUi.pMenuLevel->Items; + } + } + } + IOMapUi.State = NEXT_MENU; + } + break; + + case RIGHT_PRESSED : + { + if ((VarsUi.pMenuLevel->SpecialFlags & MENU_LEFT_RIGHT_AS_CALL)) + { + cUiMenuCallFunction(VarsUi.pMenuLevel->FunctionNo,MENU_RIGHT); + } + else + { + VarsUi.SecondTime = FALSE; + VarsUi.EnterOnlyCalls = FALSE; + VarsUi.ExitOnlyCalls = FALSE; + + if (VarsUi.pMenuLevel->ItemIndex < VarsUi.pMenuLevel->Items) + { + VarsUi.pMenuLevel->ItemIndex++; + } + else + { + if (VarsUi.pMenuLevel->Items > 2) + { + VarsUi.pMenuLevel->ItemIndex = 1; + } + } + } + IOMapUi.State = NEXT_MENU; + } + break; + + case ENTER_PRESSED : + { + if ((VarsUi.pMenuLevel->SpecialFlags & MENU_ENTER_ACT_AS_EXIT)) + { + cUiMenuExit(); + } + else + { + cUiMenuEnter(); + } + } + break; + + case EXIT_PRESSED : + { + if ((VarsUi.pMenuLevel->SpecialFlags & MENU_EXIT_ACT_AS_ENTER)) + { + cUiMenuEnter(); + } + else + { + cUiMenuExit(); + } + } + break; + + case CONNECT_REQUEST : + { + if (cUiBTConnectRequest(MENU_INIT) == 0) + { + IOMapUi.BluetoothState &= ~BT_CONNECT_REQUEST; + cUiLoadLevel(0,1,1); + IOMapUi.State = NEXT_MENU; + IOMapUi.Flags &= ~UI_BUSY; + } + } + break; + + case EXECUTE_FILE : + { + cUiLoadLevel(0,1,1); + cUiMenuEnter(); + cUiLoadLevel(VarsUi.MenuFileLevel,VarsUi.MenuFiles[VarsUi.MenuFileLevel].MenuLevel,VarsUi.MenuFiles[VarsUi.MenuFileLevel].MenuLevels[VarsUi.MenuFiles[VarsUi.MenuFileLevel].MenuLevel].ItemIndex); + cUiMenuEnter(); + cUiLoadLevel(VarsUi.MenuFileLevel,VarsUi.MenuFiles[VarsUi.MenuFileLevel].MenuLevel,VarsUi.MenuFiles[VarsUi.MenuFileLevel].MenuLevels[VarsUi.MenuFiles[VarsUi.MenuFileLevel].MenuLevel].ItemIndex); + cUiMenuEnter(); + cUiLoadLevel(VarsUi.MenuFileLevel,VarsUi.MenuFiles[VarsUi.MenuFileLevel].MenuLevel,VarsUi.MenuFiles[VarsUi.MenuFileLevel].MenuLevels[VarsUi.MenuFiles[VarsUi.MenuFileLevel].MenuLevel].ItemIndex); + + VarsUi.Function = 0; + VarsUi.State = 0; + VarsUi.Pointer = 0; + VarsUi.FNOFState = 0; + VarsUi.FBState = 0; + VarsUi.GUSState = 0; + + strcpy((char*)VarsUi.SelectedFilename,(char*)IOMapUi.LMSfilename); + IOMapUi.State = EXECUTING_FILE; + VarsUi.FileType = FILETYPE_LMS; + cUiFileRun(MENU_INIT); + } + break; + + case EXECUTING_FILE : + { + if (cUiFileRun(MENU_RUN) == 0) + { + IOMapUi.Flags &= ~UI_EXECUTE_LMS_FILE; + IOMapUi.State = NEXT_MENU; + } + } + break; + + case LOW_BATTERY : + { + if (DISPLAY_IDLE) + { + if (cUiReadButtons() != BUTTON_NONE) + { + pMapDisplay->Flags &= ~DISPLAY_POPUP; + pMapDisplay->pBitmaps[BITMAP_1] = (BMPMAP*)VarsUi.LowBattSavedBitmap; + IOMapUi.State = VarsUi.LowBattSavedState; + IOMapUi.Flags &= ~UI_BUSY; + } + } + } + break; + + case BT_ERROR : + { + switch (IOMapUi.Error) + { + case LR_COULD_NOT_SAVE : + { + Tmp = TXT_FB_BT_ERROR_LR_COULD_NOT_SAVE_1; + } + break; + + case LR_STORE_IS_FULL : + { + Tmp = TXT_FB_BT_ERROR_LR_STORE_IS_FULL_1; + } + break; + + default : + { + Tmp = TXT_FB_BT_ERROR_LR_UNKOWN_ADDR_1; + } + break; + + } + + if (!cUiFeedback((BMPMAP*)Fail,Tmp,Tmp + 1,DISPLAY_SHOW_ERROR_TIME)) + { + IOMapUi.BluetoothState &= ~BT_ERROR_ATTENTION; + cUiLoadLevel(0,1,1); + IOMapUi.State = NEXT_MENU; + IOMapUi.Flags &= ~UI_BUSY; + } + } + break; + + } + + // Check for low battery voltage + if (VarsUi.LowBatt >= LOW_BATT_THRESHOLD) + { + if (!VarsUi.LowBattHasOccured) + { + if (DISPLAY_IDLE) + { + if (!(IOMapUi.Flags & UI_BUSY)) + { + pMapDisplay->Flags |= DISPLAY_POPUP; + VarsUi.LowBattHasOccured = 1; + VarsUi.LowBattSavedState = IOMapUi.State; + VarsUi.LowBattSavedBitmap = (UBYTE*)pMapDisplay->pBitmaps[BITMAP_1]; + pMapDisplay->pBitmaps[BITMAP_1] = (BMPMAP*)LowBattery; + pMapDisplay->UpdateMask = BITMAP_BIT(BITMAP_1); + IOMapUi.Flags |= UI_REDRAW_STATUS; + IOMapUi.Flags |= UI_BUSY; + IOMapUi.State = LOW_BATTERY; + } + } + } + } + + // Check for incomming BT connection requests + if ((IOMapUi.BluetoothState & BT_CONNECT_REQUEST) && (!(IOMapUi.Flags & UI_BUSY))) + { + IOMapUi.Flags |= UI_BUSY; + IOMapUi.State = CONNECT_REQUEST; + } + + // Check for BT errors + if ((IOMapUi.BluetoothState & BT_ERROR_ATTENTION) && (!(IOMapUi.Flags & UI_BUSY))) + { + IOMapUi.Flags |= UI_BUSY; + IOMapUi.State = BT_ERROR; + } + + // Check for incomming execute program + if ((IOMapUi.Flags & UI_EXECUTE_LMS_FILE) && (!(IOMapUi.Flags & UI_BUSY))) + { + // Reset power down timer + IOMapUi.Flags |= UI_RESET_SLEEP_TIMER; + + // Set state and busy + IOMapUi.Flags |= UI_BUSY; + IOMapUi.State = EXECUTE_FILE; + } + + // Check for power timeout + if ((IOMapUi.Flags & UI_RESET_SLEEP_TIMER)) + { + IOMapUi.Flags &= ~UI_RESET_SLEEP_TIMER; + IOMapUi.SleepTimer = 0; + VarsUi.SleepTimer = 0; + } + if (IOMapUi.SleepTimeout) + { + if (++VarsUi.SleepTimer >= 60000) + { + VarsUi.SleepTimer = 0; + if (++IOMapUi.SleepTimer >= IOMapUi.SleepTimeout) + { + IOMapUi.ForceOff = TRUE; + } + } + } + else + { + IOMapUi.Flags |= UI_RESET_SLEEP_TIMER; + } + + // Check for "long prees on exit" power off + if ((pMapButton->State[BTN1] & LONG_PRESSED_EV) && (pMapCmd->ProgStatus != PROG_RUNNING) && (VarsUi.Initialized == TRUE) && (VarsUi.State == 0)) + { + IOMapUi.ForceOff = TRUE; + } + + // Check for "force" off + if (IOMapUi.ForceOff != FALSE) + { + IOMapUi.ForceOff = FALSE; + VarsUi.Function = FUNC_NO_OFF; + VarsUi.Parameter = MENU_INIT; + VarsUi.State = 0; + IOMapUi.State = DRAW_MENU; + } + + // Update status line + cUiUpdateStatus(); +} + + +void cUiExit(void) +{ + VarsUi.Initialized = FALSE; + IOMapUi.State = INIT_DISPLAY; +} diff --git a/AT91SAM7S256/Source/c_ui.h b/AT91SAM7S256/Source/c_ui.h new file mode 100644 index 0000000..07a4237 --- /dev/null +++ b/AT91SAM7S256/Source/c_ui.h @@ -0,0 +1,352 @@ +// +// Programmer +// +// Date init 14.12.2004 +// +// Reviser $Author:: Dktochpe $ +// +// Revision date $Date:: 3-02-06 12:50 $ +// +// Filename $Workfile:: c_ui.h $ +// +// Version $Revision:: 75 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/c_ui.h $ +// +// Platform C +// + +#ifndef C_UI +#define C_UI + +#define NO_OF_FEEDBACK_CHARS 12 // Chars left when bitmap also showed +#define SIZE_OF_CURSOR 16 // Bitmap size of cursor (header + 8x8 pixels) +#define SIZE_OF_PORTBITMAP 11 // Bitmap size of port no (header + 3x8 pixels) +#define NO_OF_STATUSICONS 4 // Status icons + +#define NO_OF_INTROBITMAPS 16 // Intro bitmaps +#define INTRO_START_TIME 1000 // Intro startup time [mS] +#define INTRO_SHIFT_TIME 100 // Intro inter bitmap time [mS] +#define INTRO_STOP_TIME 1000 // Intro stop time [mS] +#define INTRO_LOWBATT_TIME 2000 // Low battery show time at power up [mS] + +#define MAX_VOLUME 4 // Max volume in UI [cnt] + +#define BATTERY_COUNT_TO_MV 13.848 // Battery count to mV factor [mV/cnt] +#define LOW_BATT_THRESHOLD 6 // Low batt conunts before warning + +#define BUTTON_DELAY_TIME 800 // Delay before first repeat [mS] +#define BUTTON_REPEAT_TIME 200 // Repeat time [mS] + +#define RUN_BITMAP_CHANGE_TIME 125 // Running bimap update time [mS] +#define RUN_STATUS_CHANGE_TIME 167 // Running status update time [mS] + +#define DISPLAY_SHOW_ERROR_TIME 2500 // Error string show time [mS] +#define DISPLAY_SHOW_TIME 1500 // Min. response display time [mS] +#define DISPLAY_VIEW_UPDATE 250 // Display update time [mS] +#define MIN_DISPLAY_UPDATE_TIME 50 // OBP min graphics update time [mS] +#define MIN_SENSOR_READ_TIME 25 // Time between sensor reads [mS] + +#define ARM_WAIT_FOR_POWER_OFF 250 // Time for off command to execute [mS] + +// Menu special flags + +#define MENU_SKIP_THIS_MOTHER_ID 0x00000001L // Used to seek next common menu (i0000000) + // Free +#define MENU_ENTER_ACT_AS_EXIT 0x00000004L // Enter button acts as exit button +#define MENU_BACK_TWICE 0x00000008L // Exit twice on exit button +#define MENU_EXIT_ACT_AS_ENTER 0x00000010L // Exit button acts as enter button +#define MENU_LEAVE_BACKGROUND 0x00000020L // Don't erase background at next menu +#define MENU_EXIT_CALLS_WITH_FF 0x00000040L // Exit button calls function with MENU_EXIT +#define MENU_EXIT_LEAVES_MENUFILE 0x00000080L // Exit leaves menu file +#define MENU_INIT_CALLS_WITH_0 0x00000100L // Menu init calls with MENU_INIT +#define MENU_LEFT_RIGHT_AS_CALL 0x00000200L // Left calls with MENU_LEFT and right with MENU_RIGHT +#define MENU_ENTER_ONLY_CALLS 0x00000400L // Enter calls only it does not change menues +#define MENU_EXIT_ONLY_CALLS 0x00000800L // Exit calls only it does not change menues +#define MENU_AUTO_PRESS_ENTER 0x00001000L // Enter button is pressed automaticly +#define MENU_ENTER_LEAVES_MENUFILE 0x00002000L // Enter leaves menufile +#define MENU_INIT_CALLS 0x00004000L // Init calls instead of enter +#define MENU_ACCEPT_INCOMMING_REQUEST 0x00008000L // Accept incomming BT connection request +#define MENU_BACK_THREE_TIMES 0x00010000L // Exit three times on exit button +#define MENU_EXIT_DISABLE 0x00020000L // Disable exit button +#define MENU_EXIT_LOAD_POINTER 0x00040000L // Load item index on exit (0i000000) +#define MENU_EXIT_CALLS 0x00080000L // Exit calls as enter +#define MENU_INIT_CALLS_WITH_1 0x00100000L // Menu init calls with MENU_INIT +#define MENU_EXIT_LOAD_MENU 0x00200000L // Exit loads next menu +#define MENU_ONLY_BT_ON 0x00400000L // Only valid when bluecore is on +#define MENU_ONLY_DATALOG_ENABLED 0x00800000L // Only valid when datalog is enabled + +// Menu function call parameter + +#define MENU_SENSOR_EMPTY 0x01 // Empty +#define MENU_SENSOR_SOUND_DB 0x02 // Sound sensor dB +#define MENU_SENSOR_SOUND_DBA 0x03 // Sound sensor dBA +#define MENU_SENSOR_LIGHT 0x04 // Light sensor with flood light +#define MENU_SENSOR_LIGHT_AMB 0x05 // Light sensor without flood light +#define MENU_SENSOR_LIGHT_OLD 0x06 // Light sensor old with flood light +#define MENU_SENSOR_TOUCH 0x07 // Touch sensor +#define MENU_SENSOR_MOTOR_DEG 0x08 // Motor sensor degrees +#define MENU_SENSOR_MOTOR_ROT 0x09 // Motor sensor rotations +#define MENU_SENSOR_ROTATION 0x0A // Rotation sensor ticks +#define MENU_SENSOR_ULTRASONIC_IN 0x0B // Ultrasonic sensor inch +#define MENU_SENSOR_ULTRASONIC_CM 0x0C // Ultrasonic sensor cm +#define MENU_SENSOR_TEMP_C 0x0D // Temp sensor celcius +#define MENU_SENSOR_TEMP_F 0x0E // Temp sensor fahrenheit +#define MENU_SENSOR_INVALID 0x0F // Invalid + +#define MENU_PORT_EMPTY 0x11 // NA +#define MENU_PORT_1 0x12 // Port 1 +#define MENU_PORT_2 0x13 // Port 2 +#define MENU_PORT_3 0x14 // Port 3 +#define MENU_PORT_4 0x15 // Port 4 +#define MENU_PORT_A 0x16 // Port A +#define MENU_PORT_B 0x17 // Port B +#define MENU_PORT_C 0x18 // Port C +#define MENU_PORT_INVALID 0x19 // Invalid + +#define MENU_ACTION_EMPTY 0x21 // Empty +#define MENU_ACTION_FORWARD_1 0x22 // Forward until +#define MENU_ACTION_FORWARD_2 0x23 // Forward 5 +#define MENU_ACTION_BACK_LEFT_2 0x24 // Back left 2 +#define MENU_ACTION_TURN_LEFT_1 0x25 // Turn left until +#define MENU_ACTION_TURN_LEFT_2 0x26 // Turn left 2 +#define MENU_ACTION_BACK_RIGHT_1 0x27 // Back right until +#define MENU_ACTION_TURN_RIGHT_1 0x28 // Turn right until +#define MENU_ACTION_TURN_RIGHT_2 0x29 // Turn right 2 +#define MENU_ACTION_BACK_LEFT_1 0x2A // Back left until +#define MENU_ACTION_TONE_1 0x2B // Tone 1 +#define MENU_ACTION_TONE_2 0x2C // Tone 2 +#define MENU_ACTION_BACKWARD_1 0x2D // Backward until +#define MENU_ACTION_BACKWARD_2 0x2E // Backward 5 +#define MENU_ACTION_BACK_RIGHT_2 0x2F // Back right 2 +#define MENU_ACTION_INVALID 0x30 // Invalid + +#define MENU_WAIT_EMPTY 0x41 // Empty +#define MENU_WAIT_LIGHT 0x42 // Light +#define MENU_WAIT_SEEK_OBJ 0x43 // Seek obj. +#define MENU_WAIT_SOUND 0x44 // Sound +#define MENU_WAIT_TOUCH 0x45 // Touch +#define MENU_WAIT_1 0x46 // Wait 2 +#define MENU_WAIT_2 0x47 // Wait 5 +#define MENU_WAIT_3 0x48 // Wait 10 +#define MENU_WAIT_DARK 0x49 // Dark +#define MENU_WAIT_INVALID 0x4A // Invalid + +#define MENU_INIT 0x00 // Init +#define MENU_INIT_ALTERNATIVE 0x01 // Init alternative +#define MENU_DRAW 0xE9 // Draw +#define MENU_OFF 0xEA // Off +#define MENU_ON 0xEB // On +#define MENU_OPEN_STREAM 0xEC // Open stream +#define MENU_OVERWRITE 0xED // Overwrite file +#define MENU_CALCULATE 0xEE // Calculate +#define MENU_ENTER 0xEF // Enter +#define MENU_DISCONNECT 0xF0 // Disconnect BT +#define MENU_DELETE 0xF1 // Delete +#define MENU_SELECT 0xF2 // Select +#define MENU_RUN_SILENT 0xF3 // Run without graphics +#define MENU_TOGGLE 0xF4 // Toggle +#define MENU_CONNECT 0xF5 // Connect BT +#define MENU_UPDATE 0xF6 // Update +#define MENU_TEXT 0xF7 // Text +#define MENU_RUN 0xF8 // Run +#define MENU_SEND 0xF9 // Send +#define MENU_SAVE 0xFA // Save +#define MENU_STOP 0xFB // Stop +#define MENU_LOOP 0xFC // Loop +#define MENU_LEFT 0xFD // Left +#define MENU_RIGHT 0xFE // Right +#define MENU_EXIT 0xFF // Exit + +#define MENULEVELS 10 // Max no of levels in one file (8 + 2 virtual) +#define MENUFILELEVELS 3 // Max deept in menu file pool + +typedef struct // VarsUi.MenuFiles[VarsUi.MenuFileLevel].MenuLevels[VarsUi.MenuLevel]. +{ + ULONG Id; // Menu item id + UBYTE *IconText; // Menu item icon text pointer + ULONG SpecialFlags; // Menu item special behaivor + UBYTE IconImageNo; // Menu item icon image no + UBYTE FunctionNo; // Menu item function call no (0 = none) + UBYTE Parameter; // Menu item function call parameter + UBYTE NextFileNo; // Menu item next menu file no (0 = none) + UBYTE NextMenuNo; // Menu item next menu no (0 = none) + + UBYTE ItemIndex; // Menu item index on level + UBYTE Items; // Menu items on level +} +MENULEVEL; + +typedef struct +{ + MENULEVEL MenuLevels[MENULEVELS]; // See above + UBYTE FileId; // VarsUi.MenuFiles[VarsUi.MenuFileLevel].FileId + UBYTE MenuLevel; // VarsUi.MenuFiles[VarsUi.MenuFileLevel].MenuLevel +} +MENUFILE; + +typedef struct +{ + UBYTE StatusText[STATUSTEXT_SIZE + 1]; // RCX name + UBYTE Initialized; // Ui init done + UWORD SleepTimer; // Sleep timer + + // Menu system + MENUFILE MenuFiles[MENUFILELEVELS]; // Menu file array + MENUFILE *pMenuFile; // Actual menu file pointer + MENULEVEL *pMenuLevel; // Actual menu item on level, pointer + MENUITEM *pMenuItem; // Actual menu item in menu flash file + UBYTE MenuFileLevel; // Actual menu file level + UBYTE Function; // Running function (0 = none) + UBYTE Parameter; // Parameter for running function + UBYTE SecondTime; // Second time flag + UBYTE EnterOnlyCalls; // Enter button only calls + UBYTE ExitOnlyCalls; // Exit button only calls + UWORD ButtonTimer; // Button repeat timer + UWORD ButtonTime; // Button repeat time + UBYTE ButtonOld; // Button old state + + // Update status + UWORD UpdateCounter; // Update counter + UBYTE Running; // Running pointer + UBYTE BatteryToggle; // Battery flash toggle flag + UBYTE NewStatusIcons[NO_OF_STATUSICONS]; // New status icons (used to detect changes) + + // Low battery voltage + UBYTE *LowBattSavedBitmap; // Low battery overwritten bitmap placeholder + UBYTE LowBatt; // Low battery volatge flag + UBYTE LowBattHasOccured; // Low battery voltage has occured + UBYTE LowBattSavedState; // Low battery current state placeholder + + // General used variables + UBYTE *MenuIconTextSave; // Menu icon text save + + UBYTE *pTmp; // General UBYTE pointer + ULONG TmpLength; // General filelength (used in filelist) + SWORD TmpHandle; // General filehandle (used in filelist) + + SWORD Timer; // General tmp purpose timer + SWORD ReadoutTimer; // General read out timer + UBYTE Tmp; // General UBYTE + UBYTE FileType; // General file type + UBYTE State; // General tmp purpose state + UBYTE Pointer; // General tmp purpose pointer + UBYTE Counter; // General tmp purpose counter + UBYTE Cursor; // General cursor + UBYTE SelectedSensor; // General used for selected sensor + UBYTE SelectedPort; // General used for selected port + UBYTE NextState; + + UBYTE SelectedFilename[FILENAME_LENGTH + 1]; // Selected file name + UBYTE FilenameBuffer[FILENAME_LENGTH + 1]; // General filename buffer + UBYTE SearchFilenameBuffer[FILENAME_LENGTH + 1];// General filename buffer + UBYTE DisplayBuffer[DISPLAYLINE_LENGTH + 1]; // General purpose display buffer + + UBYTE PortBitmapLeft[SIZE_OF_PORTBITMAP]; // Port no bitmap for left icon + UBYTE PortBitmapCenter[SIZE_OF_PORTBITMAP]; // Port no bitmap for center icon + UBYTE PortBitmapRight[SIZE_OF_PORTBITMAP]; // Port no bitmap for right icon + + // Find no of files and find name for file no + ULONG FNOFLength; // Length + SWORD FNOFHandle; // Handle + UBYTE FNOFState; // State + UBYTE FNOFSearchBuffer[FILENAME_LENGTH + 1]; // Search buffer + UBYTE FNOFNameBuffer[FILENAME_LENGTH + 1]; // File name buffer + UBYTE FNOFFileNo; // File no + + // File list + UBYTE FileCenter; // File center + UBYTE FileLeft; // File left + UBYTE FileRight; // File right + UBYTE NoOfFiles; // No of files + + // On brick programming menu + UBYTE ProgramSteps[ON_BRICK_PROGRAMSTEPS]; // On brick programming steps + UBYTE ProgramStepPointer; // On brick programming step pointer + UBYTE CursorTmp[SIZE_OF_CURSOR]; // On brick programming cursor + UBYTE FileHeader[FILEHEADER_LENGTH]; // File header for programs + UBYTE *FeedBackText; // Program end text + UWORD OBPTimer; // Graphic update timer + + // BT search menu + UBYTE NoOfDevices; // BT search no of devices found + UBYTE NoOfNames; // BT search no of names found + UBYTE SelectedDevice; // BT selected device + UBYTE SelectedSlot; // BT selected slot + + // BT device list menu + UBYTE DevicesKnown; // BT device known flag + UBYTE Devices; // BT devices + UBYTE DeviceLeft; // BT device left + UBYTE DeviceCenter; // BT device center + UBYTE DeviceRight; // BT device right + UBYTE DeviceType; // BT device type + + // BT connect Menu + UBYTE Slots; // BT connect no of slots + UBYTE SlotLeft; // BT connect + UBYTE SlotCenter; // BT connect + UBYTE SlotRight; // BT connect + + // Get user string + UBYTE GUSTmp; // Seperat tmp for "Get user string" + UBYTE GUSState; // Seperat state for "Get user string" + UBYTE GUSNoname; // No user entry + UBYTE UserString[DISPLAYLINE_LENGTH + 1]; // User string + UBYTE DisplayText[DISPLAYLINE_LENGTH + 1]; // Display buffer + SBYTE FigurePointer; // Figure cursor + UBYTE GUSCursor; // User string cursor + + // Connect request + ULONG CRPasskey; // Passkey to fake wrong pin code + UBYTE CRState; // Seperate state for "Connect request" + UBYTE CRTmp; // Seperate tmp for "Connect request" + + // Run files + UBYTE *RunIconSave; // Menu center icon save + UWORD RunTimer; // Bitmap change timer + UBYTE RunBitmapPointer; // Bitmap pointer + + // Delete files + UBYTE SelectedType; // Type of selected files for delete + + // View + SLONG ViewSampleValue; // Latch for sensor values + UBYTE ViewSampleValid; // Latch for sensor valid + + // NV storage + ULONG NVTmpLength; // Non volatile filelength + SWORD NVTmpHandle; // Non volatile filehandle + UBYTE NVFilename[FILENAME_LENGTH + 1]; // Non volatile file name + UBYTE NVData; // Non volatile data + + // Feedback + UBYTE *FBText; // Seperate text pointer for feedback + UWORD FBTimer; // Seperate timer for feedback + UBYTE FBState; // Seperate state for feedback + UBYTE FBPointer; // Seperate pointer for feedback + + // BT command + UBYTE BTIndex; // List index + UBYTE BTTmpIndex; // Tmp list index + UBYTE BTCommand; // Last lached BT command + UBYTE BTPar1; // Last lached BT command parameter 1 + UBYTE BTPar2; // Last lached BT command parameter 2 + UWORD BTResult; // Last lached BT command result + + // Error display + UBYTE ErrorTimer; // Error show timer + UBYTE ErrorFunction; // Error latched function + UBYTE ErrorParameter; // Error latched parameter + UBYTE ErrorState; // Error latched state + UBYTE ErrorString[DISPLAYLINE_LENGTH + 1]; // Error string +}VARSUI; + + +void cUiInit(void* pHeader); // Init controller +void cUiCtrl(void); // Run controller +void cUiExit(void); // Exit controller + +extern const HEADER cUi; + +#endif diff --git a/AT91SAM7S256/Source/c_ui.iom b/AT91SAM7S256/Source/c_ui.iom new file mode 100644 index 0000000..6159a4f --- /dev/null +++ b/AT91SAM7S256/Source/c_ui.iom @@ -0,0 +1,116 @@ +// +// Programmer +// +// Date init 14.12.2004 +// +// Reviser $Author:: Dktochpe $ +// +// Revision date $Date:: 28-02-06 14:07 $ +// +// Filename $Workfile:: c_ui.iom $ +// +// Version $Revision:: 45 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/c_ui.iom $ +// +// Platform C +// + +#ifndef CUI_IOM +#define CUI_IOM + +#define pMapUi ((IOMAPUI*)(pHeaders[ENTRY_UI]->pIOMap)) + +// Various filenames without extension +#define UI_NONVOLATILE "NVConfig" // Ui non volatile config filename +#define UI_PROGRAM_DEFAULT "Untitled" // On brick programming default filename +#define UI_PROGRAM_TEMP "Program" // On brick programming tmp filename +#define UI_PROGRAM_READER "RPGReader" // On brick programming script reader filename +#define UI_STARTUP_SOUND "! Startup" // Sound file activated when the menu system starts up +#define UI_KEYCLICK_SOUND "! Click" // Sound file activated when key pressed in the menu system +#define UI_ATTENTION_SOUND "! Attention" // Sound file activated when incomming BT requests attention + +// Various text strings +#define UI_NAME_DEFAULT "NXT" // Default blue tooth name +#define UI_PINCODE_DEFAULT "1234" // Default blue tooth pin code +#define UI_PINCODE_NONE_OUT "????" // Fake pin code to deney outgoing request +#define UI_PINCODE_NONE_IN "????" // Fake pin code to deney incomming request + +// Constants related to Flags +enum +{ + UI_UPDATE = 0x01, // W - Make changes take effect + UI_DISABLE_LEFT_RIGHT_ENTER = 0x02, // RW - Disable left, right and enter button + UI_DISABLE_EXIT = 0x04, // RW - Disable exit button + UI_REDRAW_STATUS = 0x08, // W - Redraw entire status line + UI_RESET_SLEEP_TIMER = 0x10, // W - Reset sleep timeout timer + UI_EXECUTE_LMS_FILE = 0x20, // W - Execute LMS file in "LMSfilename" (Try It) + UI_BUSY = 0x40, // R - UI busy running or datalogging (popup disabled) + UI_ENABLE_STATUS_UPDATE = 0x80 // W - Enable status line to be updated +}; + +// Constants related to State +enum +{ + INIT_DISPLAY, // RW - Init display and load font, menu etc. + INIT_LOW_BATTERY, // R - Low battery voltage at power on + INIT_INTRO, // R - Display intro + INIT_WAIT, // RW - Wait for initialization end + INIT_MENU, // RW - Init menu system + NEXT_MENU, // RW - Next menu icons ready for drawing + DRAW_MENU, // RW - Execute function and draw menu icons + TEST_BUTTONS, // RW - Wait for buttons to be pressed + LEFT_PRESSED, // RW - Load selected function and next menu id + RIGHT_PRESSED, // RW - Load selected function and next menu id + ENTER_PRESSED, // RW - Load selected function and next menu id + EXIT_PRESSED, // RW - Load selected function and next menu id + CONNECT_REQUEST, // RW - Request for connection accept + EXECUTE_FILE, // RW - Execute file in "LMSfilename" + EXECUTING_FILE, // R - Executing file in "LMSfilename" + LOW_BATTERY, // R - Low battery at runtime + BT_ERROR // R - BT error +}; + +// Constants related to Button +enum +{ + BUTTON_NONE, // R - Button inserted are executed + BUTTON_LEFT, // W - Insert left arrow button + BUTTON_ENTER, // W - Insert enter button + BUTTON_RIGHT, // W - Insert right arrow button + BUTTON_EXIT // W - Insert exit button +}; + +// Constants related to BlueToothState +enum +{ + BT_STATE_VISIBLE = 0x01, // RW - BT visible + BT_STATE_CONNECTED = 0x02, // RW - BT connected to something + BT_STATE_OFF = 0x04, // RW - BT power off + BT_ERROR_ATTENTION = 0x08, // W - BT error attention + BT_CONNECT_REQUEST = 0x40, // RW - BT get connect accept in progress + BT_PIN_REQUEST = 0x80 // RW - BT get pin code +}; + +typedef struct +{ + MENU *pMenu; // W - Pointer to menu file + UWORD BatteryVoltage; // R - Battery voltage in millivolts + UBYTE LMSfilename[FILENAME_LENGTH + 1]; // W - LMS filename to execute (Try It) + UBYTE Flags; // RW - Update command flags (flags enumerated above) + UBYTE State; // RW - UI state (states enumerated above) + UBYTE Button; // RW - Insert button (buttons enumerated above) + UBYTE RunState; // W - VM Run state (0 = stopped, 1 = running) + UBYTE BatteryState; // W - Battery state (0..4 capacity) + UBYTE BluetoothState; // W - Bluetooth state (0=on, 1=visible, 2=conn, 3=conn.visible, 4=off, 5=dfu) + UBYTE UsbState; // W - Usb state (0=disconnected, 1=connected, 2=working) + UBYTE SleepTimeout; // RW - Sleep timeout time (min) + UBYTE SleepTimer; // RW - Sleep timer (min) + UBYTE Rechargeable; // R - Rechargeable battery (0 = no, 1 = yes) + UBYTE Volume; // RW - Volume used in UI (0 - 4) + UBYTE Error; // W - Error code + UBYTE OBPPointer; // W - Actual OBP step (0 - 4) + UBYTE ForceOff; // W - Force off (> 0 = off) +}IOMAPUI; + +#endif diff --git a/AT91SAM7S256/Source/d_bt.c b/AT91SAM7S256/Source/d_bt.c new file mode 100644 index 0000000..55b81f7 --- /dev/null +++ b/AT91SAM7S256/Source/d_bt.c @@ -0,0 +1,453 @@ +// +// Date init 14.12.2004 +// +// Revision date $Date:: 16-05-06 9:42 $ +// +// Filename $Workfile:: d_bt.c $ +// +// Version $Revision:: 21 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/d_bt.c $ +// +// Platform C +// + + +#include "stdconst.h" +#include "modules.h" +#include "m_sched.h" +#include "d_bt.h" +#include "d_bt.r" +#include + +enum +{ + BT_FAST_TIMEOUT = 500, + BT_CMD_TIMEOUT_2S = 2000, + BT_TIMEOUT_30S = 30000 +}; + +#define SETTimeout(TOut) CmdTOut = 0;\ + CmdTOutLimit = TOut +#define RESETTimeout CmdTOut = 0 + +static UWORD CmdTOut; +static UWORD CmdTOutLimit; + +void dBtInit(void) +{ + SETTimeout(0); + BTInit; + BTInitPIOPins; + BTInitADC; +} + +void dBtSetBcResetPinLow(void) +{ + BTSetResetLow; /* Set Reset pin to Bluecore chip low */ +} + +void dBtSetBcResetPinHigh(void) +{ + BTSetResetHigh; /* Set Reset pin to Bluecore chip high */ +} + +void dBtStartADConverter(void) +{ + BTStartADConverter; +} + +void dBtInitReceive(UBYTE *InputBuffer, UBYTE Mode) +{ + BTInitReceiver(InputBuffer, Mode); +} + +void dBtSetArm7CmdSignal(void) +{ + BT_SetArm7CmdPin; +} + +void dBtClearArm7CmdSignal(void) +{ + BT_ClearArm7CmdPin; +} + +UBYTE dBtGetBc4CmdSignal(void) +{ + UWORD ADValue; + + BTReadADCValue(ADValue); + + if (ADValue > 0x200) + { + ADValue = 1; + } + else + { + ADValue = 0; + } + return(ADValue); +} + + +UWORD dBtTxEnd(void) +{ + UWORD TxEnd; + + REQTxEnd(TxEnd); + + return(TxEnd); + +} + +UWORD dBtCheckForTxBuf(void) +{ + UWORD AvailBytes; + + AVAILOutBuf(AvailBytes); + + return(AvailBytes); +} + +void dBtSendMsg(UBYTE *OutputBuffer, UBYTE BytesToSend, UWORD MsgSize) +{ + + /* Used for sending a complete message that can be placed in the buffer - */ + /* or to send the first part of a message that cannot be placed in the buffer */ + /* once (bigger than the buffer) */ + BTSendMsg(OutputBuffer,BytesToSend, MsgSize); +} + +void dBtSend(UBYTE *OutputBuffer, UBYTE BytesToSend) +{ + + /* Used for continous stream of data to be send */ + BTSend(OutputBuffer, BytesToSend); +} + +UWORD dBtReceivedData(UWORD *pLength, UWORD *pBytesToGo) +{ + UWORD RtnVal; + + RtnVal = TRUE; + BTReceivedData(pLength, pBytesToGo); + if (*pLength) + { + SETTimeout(0); + } + else + { + if (CmdTOut < CmdTOutLimit) + { + CmdTOut++; + if (CmdTOut >= CmdTOutLimit) + { + SETTimeout(0); + RtnVal = FALSE; + } + } + } + return(RtnVal); +} + +void dBtResetTimeOut(void) +{ + RESETTimeout; +} + +void dBtClearTimeOut(void) +{ + SETTimeout(0); +} + +void dBtSendBtCmd(UBYTE Cmd, UBYTE Param1, UBYTE Param2, UBYTE *pBdAddr, UBYTE *pName, UBYTE *pCod, UBYTE *pPin) +{ + UBYTE Tmp; + UBYTE SendData; + UWORD CheckSumTmp; + UBYTE BtOutBuf[128]; + UBYTE BtOutCnt; + + SendData = 0; + BtOutCnt = 0; + switch (Cmd) + { + case MSG_BEGIN_INQUIRY: + { + BtOutBuf[BtOutCnt++] = MSG_BEGIN_INQUIRY; + BtOutBuf[BtOutCnt++] = Param1; + BtOutBuf[BtOutCnt++] = 0x00; + BtOutBuf[BtOutCnt++] = Param2; + BtOutBuf[BtOutCnt++] = 0x00; + BtOutBuf[BtOutCnt++] = 0x00; + BtOutBuf[BtOutCnt++] = 0x00; + BtOutBuf[BtOutCnt++] = 0x00; + + SendData = 1; + SETTimeout(BT_TIMEOUT_30S); + } + break; + + case MSG_CANCEL_INQUIRY: + { + BtOutBuf[BtOutCnt++] = MSG_CANCEL_INQUIRY; + + SendData = 1; + SETTimeout(BT_FAST_TIMEOUT); + } + break; + + case MSG_CONNECT: + { + BtOutBuf[BtOutCnt++] = MSG_CONNECT; + memcpy(&(BtOutBuf[BtOutCnt]), pBdAddr, SIZE_OF_BDADDR); + BtOutCnt += SIZE_OF_BDADDR; + + SendData = 1; + SETTimeout(BT_TIMEOUT_30S); + } + break; + + case MSG_OPEN_PORT: + { + BtOutBuf[BtOutCnt++] = MSG_OPEN_PORT; + + SendData = 1; + SETTimeout(BT_FAST_TIMEOUT); + } + break; + + case MSG_LOOKUP_NAME: + { + BtOutBuf[BtOutCnt++] = MSG_LOOKUP_NAME; + memcpy(&(BtOutBuf[BtOutCnt]), pBdAddr, SIZE_OF_BDADDR); + BtOutCnt += SIZE_OF_BDADDR; + + SendData = 1; + SETTimeout(BT_TIMEOUT_30S); + } + break; + + case MSG_ADD_DEVICE: + { + BtOutBuf[BtOutCnt++] = MSG_ADD_DEVICE; + memcpy(&(BtOutBuf[BtOutCnt]), pBdAddr, SIZE_OF_BDADDR); + BtOutCnt += SIZE_OF_BDADDR; + memcpy(&(BtOutBuf[BtOutCnt]), pName, SIZE_OF_BT_NAME); + BtOutCnt += SIZE_OF_BT_NAME; + memcpy(&(BtOutBuf[BtOutCnt]), pCod, SIZE_OF_CLASS_OF_DEVICE); + BtOutCnt += SIZE_OF_CLASS_OF_DEVICE; + + SendData = 1; + SETTimeout(BT_TIMEOUT_30S); + } + break; + + case MSG_REMOVE_DEVICE: + { + BtOutBuf[BtOutCnt++] = MSG_REMOVE_DEVICE; + memcpy(&(BtOutBuf[BtOutCnt]), pBdAddr, SIZE_OF_BDADDR); + BtOutCnt += SIZE_OF_BDADDR; + + SendData = 1; + SETTimeout(BT_FAST_TIMEOUT); + } + break; + + case MSG_DUMP_LIST: + { + BtOutBuf[BtOutCnt++] = MSG_DUMP_LIST; + + SendData = 1; + SETTimeout(BT_TIMEOUT_30S); + } + break; + + case MSG_CLOSE_CONNECTION: + { + BtOutBuf[BtOutCnt++] = MSG_CLOSE_CONNECTION; + BtOutBuf[BtOutCnt++] = Param1; + + SendData = 1; + SETTimeout(BT_TIMEOUT_30S); + } + break; + + case MSG_ACCEPT_CONNECTION: + { + BtOutBuf[BtOutCnt++] = MSG_ACCEPT_CONNECTION; + BtOutBuf[BtOutCnt++] = Param1; + + SendData = 1; + SETTimeout(BT_TIMEOUT_30S); + } + break; + + case MSG_PIN_CODE: + { + BtOutBuf[BtOutCnt++] = MSG_PIN_CODE; + memcpy(&(BtOutBuf[BtOutCnt]), pBdAddr, SIZE_OF_BDADDR); + BtOutCnt += SIZE_OF_BDADDR; + memcpy(&(BtOutBuf[BtOutCnt]), pPin, SIZE_OF_BT_PINCODE); + BtOutCnt += SIZE_OF_BT_PINCODE; + + SendData = 1; + SETTimeout(BT_TIMEOUT_30S); + } + break; + + case MSG_OPEN_STREAM: + { + BtOutBuf[BtOutCnt++] = MSG_OPEN_STREAM; + BtOutBuf[BtOutCnt++] = Param1; + + SendData = 1; + SETTimeout(BT_TIMEOUT_30S); + } + break; + + case MSG_START_HEART: + { + BtOutBuf[BtOutCnt++] = MSG_START_HEART; + + SendData = 1; + SETTimeout(BT_FAST_TIMEOUT); + } + break; + + case MSG_SET_DISCOVERABLE: + { + BtOutBuf[BtOutCnt++] = MSG_SET_DISCOVERABLE; + BtOutBuf[BtOutCnt++] = Param1; + + SendData = 1; + SETTimeout(BT_FAST_TIMEOUT); + } + break; + + case MSG_CLOSE_PORT: + { + BtOutBuf[BtOutCnt++] = MSG_CLOSE_PORT; + BtOutBuf[BtOutCnt++] = 0x03; + + SendData = 1; + SETTimeout(BT_FAST_TIMEOUT); + } + break; + + case MSG_SET_FRIENDLY_NAME: + { + BtOutBuf[BtOutCnt++] = MSG_SET_FRIENDLY_NAME; + memcpy(&(BtOutBuf[BtOutCnt]), pName, SIZE_OF_BT_NAME); + BtOutCnt += SIZE_OF_BT_NAME; + + SendData = 1; + SETTimeout(BT_FAST_TIMEOUT); + } + break; + + case MSG_GET_LINK_QUALITY: + { + BtOutBuf[BtOutCnt++] = MSG_GET_LINK_QUALITY; + BtOutBuf[BtOutCnt++] = Param1; + + SendData = 1; + SETTimeout(BT_FAST_TIMEOUT); + } + break; + + case MSG_SET_FACTORY_SETTINGS: + { + BtOutBuf[BtOutCnt++] = MSG_SET_FACTORY_SETTINGS; + + SendData = 1; + SETTimeout(BT_FAST_TIMEOUT); + } + break; + + case MSG_GET_LOCAL_ADDR: + { + BtOutBuf[BtOutCnt++] = MSG_GET_LOCAL_ADDR; + + SendData = 1; + SETTimeout(BT_FAST_TIMEOUT); + } + break; + + case MSG_GET_FRIENDLY_NAME: + { + BtOutBuf[BtOutCnt++] = MSG_GET_FRIENDLY_NAME; + + SendData = 1; + SETTimeout(BT_FAST_TIMEOUT); + } + break; + + case MSG_GET_DISCOVERABLE: + { + BtOutBuf[BtOutCnt++] = MSG_GET_DISCOVERABLE; + + SendData = 1; + SETTimeout(BT_FAST_TIMEOUT); + } + break; + + case MSG_GET_PORT_OPEN: + { + BtOutBuf[BtOutCnt++] = MSG_GET_PORT_OPEN; + + SendData = 1; + SETTimeout(BT_FAST_TIMEOUT); + } + break; + + case MSG_GET_VERSION: + { + BtOutBuf[BtOutCnt++] = MSG_GET_VERSION; + + SendData = 1; + SETTimeout(BT_FAST_TIMEOUT); + } + break; + + case MSG_GET_BRICK_STATUSBYTE: + { + BtOutBuf[BtOutCnt++] = MSG_GET_BRICK_STATUSBYTE; + + SendData = 1; + SETTimeout(BT_FAST_TIMEOUT); + } + break; + + case MSG_SET_BRICK_STATUSBYTE: + { + BtOutBuf[BtOutCnt++] = MSG_SET_BRICK_STATUSBYTE; + BtOutBuf[BtOutCnt++] = Param1; + BtOutBuf[BtOutCnt++] = Param2; + + SendData = 1; + SETTimeout(BT_FAST_TIMEOUT); + } + break; + } + + if (SendData == 1) + { + CheckSumTmp = 0; + for(Tmp = 0; Tmp < BtOutCnt; Tmp++) + { + CheckSumTmp += BtOutBuf[Tmp]; + } + CheckSumTmp = (UWORD) (1 + (0xFFFF - CheckSumTmp)); + BtOutBuf[BtOutCnt++] = (UBYTE)((CheckSumTmp & 0xFF00)>>8); + BtOutBuf[BtOutCnt++] = (UBYTE)(CheckSumTmp & 0x00FF); + BTSendMsg(BtOutBuf, BtOutCnt, (UWORD)BtOutCnt); + } +} + + + +void dBtExit(void) +{ + BTExit; +} diff --git a/AT91SAM7S256/Source/d_bt.h b/AT91SAM7S256/Source/d_bt.h new file mode 100644 index 0000000..2e41ded --- /dev/null +++ b/AT91SAM7S256/Source/d_bt.h @@ -0,0 +1,39 @@ +// +// Date init 14.12.2004 +// +// Revision date $Date:: 16-05-06 9:41 $ +// +// Filename $Workfile:: d_bt.h $ +// +// Version $Revision:: 16 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/d_bt.h $ +// +// Platform C +// + +#ifndef D_BT +#define D_BT + +#define STREAM_MODE 1 +#define CMD_MODE 2 + +void dBtInit(void); +void dBtExit(void); +void dBtStartADConverter(void); +void dBtSetArm7CmdSignal(void); +void dBtClearArm7CmdSignal(void); +void dBtInitReceive(UBYTE *InputBuffer, UBYTE Mode); +void dBtSetBcResetPinLow(void); +void dBtSetBcResetPinHigh(void); +void dBtSendBtCmd(UBYTE Cmd, UBYTE Param1, UBYTE Param2, UBYTE *pBdAddr, UBYTE *pName, UBYTE *pCod, UBYTE *pPin); +void dBtSendMsg(UBYTE *pData, UBYTE Length, UWORD MsgSize); +void dBtSend(UBYTE *pData, UBYTE Length); +void dBtResetTimeOut(void); +void dBtClearTimeOut(void); +UBYTE dBtGetBc4CmdSignal(void); +UWORD dBtTxEnd(void); +UWORD dBtReceivedData(UWORD *pLength, UWORD *pBytesToGo); +UWORD dBtCheckForTxBuf(void); + +#endif diff --git a/AT91SAM7S256/Source/d_bt.r b/AT91SAM7S256/Source/d_bt.r new file mode 100644 index 0000000..f5c6a7d --- /dev/null +++ b/AT91SAM7S256/Source/d_bt.r @@ -0,0 +1,350 @@ +// +// Date init 14.12.2004 +// +// Revision date $Date:: 16-05-06 9:42 $ +// +// Filename $Workfile:: d_bt.r $ +// +// Version $Revision:: 28 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/d_bt.r $ +// +// Platform C +// + +#ifdef SAM7S256 + +#if defined (PROTOTYPE_PCB_3) || (PROTOTYPE_PCB_4) + +#define BT_RX_PIN AT91C_PIO_PA21 +#define BT_TX_PIN AT91C_PIO_PA22 +#define BT_SCK_PIN AT91C_PIO_PA23 +#define BT_RTS_PIN AT91C_PIO_PA24 +#define BT_CTS_PIN AT91C_PIO_PA25 + +#define BT_CS_PIN AT91C_PIO_PA31 +#define BT_RST_PIN AT91C_PIO_PA11 + +#define BT_ARM7_CMD_PIN AT91C_PIO_PA27 + +#else + +#endif + +#define BAUD_RATE 460800L + +#define SIZE_OF_INBUF 128 +#define NO_OF_INBUFFERS 2 +#define NO_OF_DMA_OUTBUFFERS 2 +#define SIZE_OF_OUTBUF 256 + +#define PER_ID7_UART_1 0x80 +#define UART1_INQ 0x80 +#define EXT_LEN_MSG_BIT 0x80 + +static UBYTE InBuf[NO_OF_INBUFFERS][SIZE_OF_INBUF]; +static ULONG InBufPtrs[NO_OF_INBUFFERS]; +static UBYTE InBufInPtr; +static UBYTE LengthSize; + +static UBYTE OutDma[NO_OF_DMA_OUTBUFFERS][SIZE_OF_OUTBUF]; +static UBYTE DmaBufPtr; +static UBYTE *pBuffer; + +static UBYTE MsgIn; +static UBYTE InBufOutCnt; +static UWORD FullRxLength; +static UWORD RemainingLength; + + +#define ENABLEDebugOutput {\ + *AT91C_PIOA_PER = 0x20000000; /* Enable PIO on PA029 */\ + *AT91C_PIOA_OER = 0x20000000; /* PA029 set to Output */\ + } + +#define SETDebugOutputHigh *AT91C_PIOA_SODR = 0x20000000 + +#define SETDebugOutputLow *AT91C_PIOA_CODR = 0x20000000 + +#define BTInit {\ + UBYTE Tmp;\ + LengthSize = 1;\ + InBufInPtr = 0;\ + for(Tmp = 0; Tmp < NO_OF_INBUFFERS; Tmp++)\ + {\ + InBufPtrs[Tmp] = (ULONG)&(InBuf[Tmp][0]);\ + }\ + *AT91C_PMC_PCER = PER_ID7_UART_1; /* Enable PMC clock for UART 1 */\ + *AT91C_PIOA_PDR = BT_RX_PIN | BT_TX_PIN | BT_SCK_PIN | BT_RTS_PIN | BT_CTS_PIN; /* Disable Per. A on PA21, PA22, PA23, PA24 & PA25 */\ + *AT91C_PIOA_ASR = BT_RX_PIN | BT_TX_PIN | BT_SCK_PIN | BT_RTS_PIN | BT_CTS_PIN; /* Enable Per. A on PA21, PA22, PA23, PA24 & PA25 */\ + *AT91C_US1_CR = AT91C_US_RSTSTA; /* Resets pins on UART1 */\ + *AT91C_US1_CR = AT91C_US_STTTO; /* Start timeout functionality after 1 byte */\ + *AT91C_US1_RTOR = 10000; /* Approxitely 20 mS,x times bit time with 115200 bit pr s */\ + *AT91C_US1_IDR = AT91C_US_TIMEOUT; /* Disable interrupt on timeout */\ + *AT91C_AIC_IDCR = UART1_INQ; /* Disable UART1 interrupt */\ + *AT91C_AIC_ICCR = UART1_INQ; /* Clear interrupt register */\ + *AT91C_US1_MR = AT91C_US_USMODE_HWHSH; /* Set UART with HW handshake */\ + *AT91C_US1_MR &= ~AT91C_US_SYNC; /* Set UART in asynchronous mode */\ + *AT91C_US1_MR |= AT91C_US_CLKS_CLOCK; /* Clock setup MCK*/\ + *AT91C_US1_MR |= AT91C_US_CHRL_8_BITS; /* UART using 8-bit */\ + *AT91C_US1_MR |= AT91C_US_PAR_NONE; /* UART using none parity bit */\ + *AT91C_US1_MR |= AT91C_US_NBSTOP_1_BIT; /* UART using 1 stop bit */\ + *AT91C_US1_MR |= AT91C_US_OVER; /* UART is using 8-bit sampling */\ + *AT91C_US1_BRGR = ((OSC/8/BAUD_RATE) | (((OSC/8) - ((OSC/8/BAUD_RATE) * BAUD_RATE)) / ((BAUD_RATE + 4)/8)) << 16);\ + *AT91C_US1_PTCR = (AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS); /* Disable of TX & RX with DMA */\ + *AT91C_US1_RCR = 0; /* Receive Counter Register */\ + *AT91C_US1_TCR = 0; /* Transmit Counter Register */\ + *AT91C_US1_RNPR = 0;\ + *AT91C_US1_TNPR = 0;\ + Tmp = *AT91C_US1_RHR;\ + Tmp = *AT91C_US1_CSR;\ + *AT91C_US1_RPR = (unsigned int)&(InBuf[InBufInPtr][0]); /* Initialise receiver buffer using DMA */\ + *AT91C_US1_RCR = SIZE_OF_INBUF;\ + *AT91C_US1_RNPR = (unsigned int)&(InBuf[(InBufInPtr + 1)%NO_OF_INBUFFERS][0]);\ + *AT91C_US1_RNCR = SIZE_OF_INBUF;\ + MsgIn = 0;\ + InBufOutCnt = 0;\ + FullRxLength = 0;\ + RemainingLength = 0;\ + *AT91C_US1_CR = AT91C_US_RXEN | AT91C_US_TXEN; /* Enable Tx & Rx on UART 1*/\ + *AT91C_US1_PTCR = (AT91C_PDC_RXTEN | AT91C_PDC_TXTEN); /* Enable of TX & RX with DMA */\ + } + + +#define BTInitPIOPins {\ + *AT91C_PIOA_PER = BT_CS_PIN | BT_RST_PIN; /* Enable PIO on PA11 & PA31 */\ + *AT91C_PIOA_OER = BT_CS_PIN | BT_RST_PIN; /* PA11 & PA31 set to output */\ + *AT91C_PIOA_SODR = BT_CS_PIN | BT_RST_PIN; /* PA31 & PA11 set output high */\ + *AT91C_PIOA_PPUDR = BT_ARM7_CMD_PIN; /* Disable PULL-UP resistor on PA27 */\ + *AT91C_PIOA_PER = BT_ARM7_CMD_PIN; /* Enable PIO on PA27 */\ + *AT91C_PIOA_CODR = BT_ARM7_CMD_PIN; /* PA27 set output low */\ + *AT91C_PIOA_OER = BT_ARM7_CMD_PIN; /* PA27 set to output */\ + } + +#define BTInitADC {\ + *AT91C_ADC_MR = 0; /* Reset register plus setting only software trigger */\ + *AT91C_ADC_MR |= 0x00003F00; /* ADC-clock set to approximatly 375 kHz */\ + *AT91C_ADC_MR |= 0x00020000; /* Startup set to approximatly 84uS */\ + *AT91C_ADC_MR |= 0x09000000; /* Sample & Hold set to approximatly 20uS */\ + *AT91C_ADC_CHER = AT91C_ADC_CH6 | AT91C_ADC_CH4; /* Enable channel 6 and 4*/\ + } + +#define BTStartADConverter *AT91C_ADC_CR = AT91C_ADC_START; /* Start the ADC converter */\ + +#define BTReadADCValue(ADValue) ADValue = *AT91C_ADC_CDR6; + +#define BTSetResetHigh {\ + *AT91C_PIOA_SODR = BT_RST_PIN; /* PA11 set output high */\ + } + +#define BTSetResetLow {\ + *AT91C_PIOA_CODR = BT_RST_PIN; /* PA11 set output low */\ + } + +#define BTInitReceiver(InputBuffer, Mode)\ + {\ + pBuffer = InputBuffer;\ + MsgIn = 0;\ + FullRxLength = 0;\ + if (STREAM_MODE == Mode)\ + {\ + LengthSize = 2;\ + }\ + else\ + {\ + LengthSize = 1;\ + }\ + } + +#define BT_SetArm7CmdPin *AT91C_PIOA_SODR = BT_ARM7_CMD_PIN + +#define BT_ClearArm7CmdPin *AT91C_PIOA_CODR = BT_ARM7_CMD_PIN + +#define BT_GetBc4CmdPin *AT91C_PIOA_PDSR & BT_BC4_CMD_PIN + +#define REQTxEnd(TxEnd) TxEnd = FALSE;\ + if ((!(*AT91C_US1_TNCR)) && (!(*AT91C_US1_TCR)))\ + {\ + TxEnd = TRUE;\ + } + +#define AVAILOutBuf(Avail) if (!(*AT91C_US1_TNCR))\ + {\ + Avail = SIZE_OF_OUTBUF;\ + }\ + else\ + {\ + Avail = 0;\ + } + + +#define BTSend(OutputBuffer, BytesToSend)\ + {\ + UWORD Avail;\ + AVAILOutBuf(Avail);\ + if (BytesToSend < (Avail - 1))\ + {\ + memcpy(&(OutDma[DmaBufPtr][0]), OutputBuffer, BytesToSend);\ + *AT91C_US1_TNPR = (unsigned int)&(OutDma[DmaBufPtr][0]);\ + *AT91C_US1_TNCR = BytesToSend;\ + DmaBufPtr = (DmaBufPtr + 1) % NO_OF_DMA_OUTBUFFERS;\ + }\ + } + + +#define BTSendMsg(OutputBuffer, BytesToSend, MsgSize)\ + {\ + UWORD Avail;\ + AVAILOutBuf(Avail);\ + if (BytesToSend < (Avail - 1))\ + {\ + if (2 == LengthSize)\ + {\ + OutDma[DmaBufPtr][0] = (UBYTE)MsgSize;\ + OutDma[DmaBufPtr][1] = (UBYTE)(MsgSize>>8);\ + }\ + else\ + {\ + OutDma[DmaBufPtr][0] = (UBYTE)MsgSize;\ + }\ + memcpy(&(OutDma[DmaBufPtr][LengthSize]), OutputBuffer, BytesToSend);\ + *AT91C_US1_TNPR = (unsigned int)&(OutDma[DmaBufPtr][0]);\ + *AT91C_US1_TNCR = BytesToSend + LengthSize;\ + DmaBufPtr = (DmaBufPtr + 1) % NO_OF_DMA_OUTBUFFERS;\ + }\ + } + + +#define BTReceivedData(pByteCnt, pToGo)\ + {\ + UWORD InCnt, Cnt;\ + *pByteCnt = 0;\ + *pToGo = 0;\ + InCnt = (SIZE_OF_INBUF - *AT91C_US1_RCR);\ + if (*AT91C_US1_RNCR == 0)\ + {\ + InCnt = SIZE_OF_INBUF;\ + }\ + InCnt -= InBufOutCnt; /* Remove already read bytes */\ + if (InCnt)\ + {\ + if (0 == FullRxLength) /* FullRxLength still to be calculated */\ + {\ + while((MsgIn < LengthSize) && (InCnt > 0))\ + {\ + pBuffer[MsgIn] = InBuf[InBufInPtr][InBufOutCnt];\ + MsgIn++;\ + InBufOutCnt++;\ + InCnt--;\ + }\ + if (LengthSize == MsgIn)\ + {\ + if (2 == LengthSize)\ + {\ + FullRxLength = pBuffer[1];\ + FullRxLength <<= 8;\ + FullRxLength |= pBuffer[0];\ + /* Remove Length when in strean mode */\ + MsgIn = 0;\ + }\ + else\ + {\ + FullRxLength = pBuffer[0];\ + }\ + RemainingLength = FullRxLength;\ + }\ + else\ + {\ + /* Length still not received */\ + FullRxLength = 0;\ + }\ + }\ + if (FullRxLength)\ + {\ + /* Incomming msg in progress */\ + /* room for bytes? */\ + if (InCnt >= RemainingLength)\ + {\ + /* Remaining msg bytes are in the buffer */\ + /* Can remaining byte be stored in buffer? */\ + if ((MsgIn + RemainingLength) <= SIZE_OF_INBUF)\ + {\ + /* All bytes can be stored */\ + for (Cnt = 0; Cnt < RemainingLength; Cnt++)\ + {\ + pBuffer[MsgIn] = InBuf[InBufInPtr][InBufOutCnt];\ + MsgIn++;\ + InBufOutCnt++;\ + }\ + *pByteCnt = MsgIn;\ + *pToGo = 0;\ + FullRxLength = 0;\ + RemainingLength = 0;\ + MsgIn = 0;\ + }\ + else\ + {\ + for (Cnt = 0; MsgIn < SIZE_OF_INBUF; Cnt++)\ + {\ + pBuffer[MsgIn] = InBuf[InBufInPtr][InBufOutCnt];\ + MsgIn++;\ + InBufOutCnt++;\ + }\ + *pByteCnt = SIZE_OF_INBUF;\ + RemainingLength -= Cnt;\ + *pToGo = RemainingLength;\ + MsgIn = 0;\ + }\ + }\ + else\ + {\ + if ((InCnt + MsgIn) < SIZE_OF_INBUF)\ + {\ + /* Received bytes do not fill up the buffer */\ + for (Cnt = 0; Cnt < InCnt; Cnt++)\ + {\ + pBuffer[MsgIn] = InBuf[InBufInPtr][InBufOutCnt];\ + MsgIn++;\ + InBufOutCnt++;\ + }\ + RemainingLength -= InCnt;\ + }\ + else\ + {\ + /* Received bytes fill up the buffer */\ + for (Cnt = 0; MsgIn < SIZE_OF_INBUF; Cnt++)\ + {\ + pBuffer[MsgIn] = InBuf[InBufInPtr][InBufOutCnt];\ + MsgIn++;\ + InBufOutCnt++;\ + }\ + *pByteCnt = SIZE_OF_INBUF;\ + RemainingLength -= Cnt; /* Only substract no removed */\ + *pToGo = RemainingLength;\ + MsgIn = 0;\ + }\ + }\ + }\ + }\ + if ((*AT91C_US1_RNCR == 0) && (SIZE_OF_INBUF == InBufOutCnt))\ + {\ + InBufOutCnt = 0;\ + *AT91C_US1_RNPR = (unsigned int)InBufPtrs[InBufInPtr];\ + *AT91C_US1_RNCR = SIZE_OF_INBUF;\ + InBufInPtr = (InBufInPtr + 1) % NO_OF_INBUFFERS;\ + }\ + } + +#define BTExit {\ + *AT91C_PMC_PCDR = PER_ID7_UART_1; /* Disable PMC clock for UART 1*/\ + *AT91C_US1_IDR = AT91C_US_TIMEOUT; /* Disable interrupt on timeout */\ + *AT91C_AIC_IDCR = UART1_INQ; /* Disable PIO interrupt */\ + *AT91C_AIC_ICCR = UART1_INQ; /* Clear interrupt register */\ + } + + +#endif + +#ifdef PCWIN + +#endif diff --git a/AT91SAM7S256/Source/d_button.c b/AT91SAM7S256/Source/d_button.c new file mode 100644 index 0000000..a74c166 --- /dev/null +++ b/AT91SAM7S256/Source/d_button.c @@ -0,0 +1,36 @@ +// +// Date init 14.12.2004 +// +// Revision date $Date:: 16-05-06 9:58 $ +// +// Filename $Workfile:: d_button.c $ +// +// Version $Revision:: 4 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/d_button.c $ +// +// Platform C +// + +#include "stdconst.h" +#include "m_sched.h" +#include "d_button.h" +#include "d_button.r" + +static UBYTE TimeTick; + +void dButtonInit(UBYTE Prescaler) +{ + TimeTick = Prescaler; + BUTTONInit; +} + +void dButtonRead(UBYTE *pButton) +{ + BUTTONRead(pButton); +} + +void dButtonExit(void) +{ + BUTTONExit; +} diff --git a/AT91SAM7S256/Source/d_button.h b/AT91SAM7S256/Source/d_button.h new file mode 100644 index 0000000..2826c3f --- /dev/null +++ b/AT91SAM7S256/Source/d_button.h @@ -0,0 +1,24 @@ +// +// Date init 14.12.2004 +// +// Revision date $Date:: 16-05-06 9:58 $ +// +// Filename $Workfile:: d_button.h $ +// +// Version $Revision:: 4 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/d_button.h $ +// +// Platform C +// + +#ifndef D_BUTTON +#define D_BUTTON + +void dButtonInit(UBYTE Prescaler); +void dButtonExit(void); + +void dButtonRead(UBYTE *pButton); + + +#endif diff --git a/AT91SAM7S256/Source/d_button.r b/AT91SAM7S256/Source/d_button.r new file mode 100644 index 0000000..3e5e359 --- /dev/null +++ b/AT91SAM7S256/Source/d_button.r @@ -0,0 +1,189 @@ +// +// Date init 14.12.2004 +// +// Revision date $Date:: 16-05-06 9:58 $ +// +// Filename $Workfile:: d_button.r $ +// +// Version $Revision:: 14 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/d_button.r $ +// +// Platform C +// + +#ifdef SAM7S256 + +static UBYTE PrellCnt[NOS_OF_AVR_BTNS]; +static UWORD OldVal; +static UBYTE OldState; +static UBYTE RisingTime; + +#define PRELL_TIME (60/TimeTick) +#define RISING_THRESHOLD (10/TimeTick) + +#define BUTTONInit {\ + UBYTE Tmp;\ + for (Tmp = 0; Tmp < NOS_OF_AVR_BTNS; Tmp++)\ + {\ + PrellCnt[Tmp] = 0;\ + }\ + IoFromAvr.Buttons = 0;\ + OldVal = 0;\ + OldState = 0;\ + RisingTime = 0;\ + } + +#if defined (PROTOTYPE_PCB_3) || (PROTOTYPE_PCB_4) + +/* Buttons read here are free of prell or jitter */ +/* And because it's an AD value returned from the AVR */ +/* then a peak detector is needed */ +#define BUTTONRead(pB) {\ + UBYTE Tmp, BtnPtr;\ + UWORD TmpBtn;\ + *pB = OldState;\ + BtnPtr = 0x01;\ + if (OldVal < IoFromAvr.Buttons)\ + {\ + OldVal = IoFromAvr.Buttons;\ + RisingTime = 0;\ + }\ + else\ + {\ + if (OldVal > (IoFromAvr.Buttons + 20))\ + {\ + OldVal = IoFromAvr.Buttons;\ + RisingTime = 0;\ + }\ + else\ + {\ + if (RisingTime > RISING_THRESHOLD)\ + {\ + TmpBtn = IoFromAvr.Buttons;\ + if (0x40 > TmpBtn)\ + {\ + TmpBtn = 0x00;\ + }\ + else if (0x100 > TmpBtn)\ + {\ + TmpBtn = 0x04;\ + }\ + else if (0x1FF > TmpBtn)\ + {\ + TmpBtn = 0x02;\ + }\ + else if (0x5FF > TmpBtn)\ + {\ + TmpBtn = 0x01;\ + }\ + else\ + {\ + TmpBtn = 0x08;\ + }\ + for (Tmp = 0; Tmp < NOS_OF_AVR_BTNS; Tmp++)\ + {\ + if ((TmpBtn) & BtnPtr)\ + {\ + *pB |= BtnPtr;\ + PrellCnt[Tmp] = PRELL_TIME;\ + }\ + else\ + {\ + /* btn not pressed */\ + if (0 != PrellCnt[Tmp])\ + {\ + PrellCnt[Tmp]--;\ + }\ + else\ + {\ + *pB &= ~BtnPtr;\ + }\ + }\ + BtnPtr <<= 1;\ + }\ + OldState = *pB;\ + }\ + else\ + {\ + RisingTime++;\ + }\ + }\ + }\ + } + +#else + +// Buttons read here are free of prell or jitter +#define BUTTONRead(pB) {\ + UBYTE Tmp, BtnPtr;\ + UWORD TmpBtn;\ + *pB = OldState;\ + BtnPtr = 0x01;\ + if ((OldVal) < IoFromAvr.Buttons)\ + {\ + OldVal = IoFromAvr.Buttons;\ + }\ + else\ + {\ + if ((OldVal) > IoFromAvr.Buttons)\ + {\ + OldVal = IoFromAvr.Buttons;\ + }\ + else\ + {\ + TmpBtn = IoFromAvr.Buttons;\ + if (100 > TmpBtn)\ + {\ + TmpBtn = 0x00;\ + }\ + else if (170 > TmpBtn)\ + {\ + TmpBtn = 0x01;\ + }\ + else if (255 > TmpBtn)\ + {\ + TmpBtn = 0x02;\ + }\ + else if (1000 > TmpBtn)\ + {\ + TmpBtn = 0x04;\ + }\ + else if (1024 > TmpBtn)\ + {\ + TmpBtn = 0x08;\ + }\ + for (Tmp = 0; Tmp < NOS_OF_AVR_BTNS; Tmp++)\ + {\ + if ((TmpBtn) & BtnPtr)\ + {\ + *pB |= BtnPtr;\ + PrellCnt[Tmp] = PRELL_TIME;\ + }\ + else\ + {\ + /* btn not pressed */\ + if (0 != PrellCnt[Tmp])\ + {\ + PrellCnt[Tmp]--;\ + }\ + else\ + {\ + *pB &= ~BtnPtr;\ + }\ + }\ + BtnPtr <<= 1;\ + }\ + OldState = *pB;\ + }\ + }\ + } +#endif + +#define BUTTONExit + +#endif + +#ifdef PCWIN + +#endif diff --git a/AT91SAM7S256/Source/d_display.c b/AT91SAM7S256/Source/d_display.c new file mode 100644 index 0000000..7181913 --- /dev/null +++ b/AT91SAM7S256/Source/d_display.c @@ -0,0 +1,53 @@ +// +// Programmer +// +// Date init 14.12.2004 +// +// Reviser $Author:: Dktochpe $ +// +// Revision date $Date:: 29-08-05 11:26 $ +// +// Filename $Workfile:: d_display.c $ +// +// Version $Revision:: 4 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/d_display. $ +// +// Platform C +// + +#include "stdconst.h" +#include "m_sched.h" +#include "d_display.h" +#include "d_display.r" + + +void dDisplayInit(void) +{ + DISPLAYInit; +} + + +void dDisplayOn(UBYTE On) +{ + if (On) + { + DISPLAYOn; + } + else + { + DISPLAYOff; + } +} + + +UBYTE dDisplayUpdate(UWORD Height,UWORD Width,UBYTE *pImage) +{ + return (DISPLAYUpdate(Height,Width,pImage)); +} + + +void dDisplayExit(void) +{ + DISPLAYExit; +} diff --git a/AT91SAM7S256/Source/d_display.h b/AT91SAM7S256/Source/d_display.h new file mode 100644 index 0000000..c205619 --- /dev/null +++ b/AT91SAM7S256/Source/d_display.h @@ -0,0 +1,39 @@ +// +// Programmer +// +// Date init 14.12.2004 +// +// Reviser $Author:: Dktochpe $ +// +// Revision date $Date:: 29-08-05 11:26 $ +// +// Filename $Workfile:: d_display.h $ +// +// Version $Revision:: 5 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/d_display. $ +// +// Platform C +// + +#ifndef D_DISPLAY +#define D_DISPLAY + +void dDisplayInit(void); +void dDisplayOn(UBYTE On); +UBYTE dDisplayUpdate(UWORD Height,UWORD Width,UBYTE *pImage); +void dDisplayExit(void); + + + +typedef struct +{ + UBYTE StartX; + UBYTE StartY; + UBYTE PixelsX; + UBYTE PixelsY; +} +SCREEN_CORDINATE; + + +#endif diff --git a/AT91SAM7S256/Source/d_display.r b/AT91SAM7S256/Source/d_display.r new file mode 100644 index 0000000..d4328b7 --- /dev/null +++ b/AT91SAM7S256/Source/d_display.r @@ -0,0 +1,374 @@ +// +// Programmer +// +// Date init 14.12.2004 +// +// Reviser $Author:: Dktochpe $ +// +// Revision date $Date:: 20-12-05 12:28 $ +// +// Filename $Workfile:: d_display.r $ +// +// Version $Revision:: 18 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/d_display. $ +// +// Platform C +// + +#ifdef SAM7S256 + +// Display 128 x 64 +// 1/65 duty, 1/9 bias +// VLCD 12.0V + +// SPI interface +// +// PCB LCD ARM PIO +// ------ ----- ---- ----- +// CS_DIS -CS1 PA10 NPCS2 (PB) +// DIS_A0 A0 PA12 PA12 +// DIS_SCL SCL PA14 SPCK (PA) +// DIS_SDA SI PA13 MOSI (PA) + + +// CPOL = 0, NCPHA=0, + +#define BT_RESET_OUT AT91C_PIO_PA11 +#define BT_RESET_IN AT91C_PIO_PA29 +#define BT_MOSI_OUT AT91C_PIO_PA13 +#define BT_MOSI_IN AT91C_PIO_PA20 +#define BT_CLK_OUT AT91C_PIO_PA14 +#define BT_CLK_IN AT91C_PIO_PA28 +#define BT_CE_OUT AT91C_PIO_PA31 +#define BT_CE_IN AT91C_PIO_PA19 +#define BT_REA_OUT AT91C_PIO_PA7 +#define BT_MISO_OUT AT91C_PIO_PA6 +#define BT_MISO_IN AT91C_PIO_PA12 + +#pragma optimize=s 9 + +__ramfunc void SpiBtIo(void) +{ + register ULONG Port; + + *AT91C_AIC_IDCR = 0xFFFFFFFF; /* Disable all interrupts */ + + *AT91C_PIOA_PER = BT_RESET_OUT; /* Enable pin RESET out */ + *AT91C_PIOA_OER = BT_RESET_OUT; /* Set output */ + *AT91C_PIOA_SODR = BT_RESET_OUT; /* Set high */ + + *AT91C_PIOA_PER = BT_MOSI_OUT; /* Enable pin MOSI out */ + *AT91C_PIOA_OER = BT_MOSI_OUT; /* Set output */ + + *AT91C_PIOA_PER = BT_CLK_OUT; /* Enable pin CLK out */ + *AT91C_PIOA_OER = BT_CLK_OUT; /* Set output */ + + *AT91C_PIOA_PER = BT_CE_OUT; /* Enable pin CE out */ + *AT91C_PIOA_OER = BT_CE_OUT; /* Set output */ + + *AT91C_PIOA_PER = BT_REA_OUT; /* Enable pin REA out */ + *AT91C_PIOA_OER = BT_REA_OUT; /* Set output */ + *AT91C_PIOA_SODR = BT_REA_OUT; /* Set high */ + + *AT91C_PIOA_PER = BT_MISO_OUT; /* Enable pin MISO out */ + *AT91C_PIOA_OER = BT_MISO_OUT; /* Set output */ + + *AT91C_PIOA_PER = BT_RESET_IN; /* Enable pin RESET in */ + *AT91C_PIOA_ODR = BT_RESET_IN; /* Set input */ + *AT91C_PIOA_IFDR = BT_RESET_IN; /* Disable filter */ + *AT91C_PIOA_IDR = BT_RESET_IN; /* Disable interrupt */ + *AT91C_PIOA_MDDR = BT_RESET_IN; /* Disable multidriver */ + *AT91C_PIOA_PPUDR = BT_RESET_IN; /* Disable pullup */ + + *AT91C_PIOA_PER = BT_MOSI_IN; /* Enable pin MOSI in */ + *AT91C_PIOA_ODR = BT_MOSI_IN; /* Set input */ + *AT91C_PIOA_IFDR = BT_MOSI_IN; /* Disable filter */ + *AT91C_PIOA_IDR = BT_MOSI_IN; /* Disable interrupt */ + *AT91C_PIOA_MDDR = BT_MOSI_IN; /* Disable multidriver */ + *AT91C_PIOA_PPUDR = BT_MOSI_IN; /* Disable pullup */ + + *AT91C_PIOA_PER = BT_CLK_IN; /* Enable pin CLK in */ + *AT91C_PIOA_ODR = BT_CLK_IN; /* Set input */ + *AT91C_PIOA_IFDR = BT_CLK_IN; /* Disable filter */ + *AT91C_PIOA_IDR = BT_CLK_IN; /* Disable interrupt */ + *AT91C_PIOA_MDDR = BT_CLK_IN; /* Disable multidriver */ + *AT91C_PIOA_PPUDR = BT_CLK_IN; /* Disable pullup */ + + *AT91C_PIOA_PER = BT_CE_IN; /* Enable pin CE in */ + *AT91C_PIOA_ODR = BT_CE_IN; /* Set input */ + *AT91C_PIOA_IFDR = BT_CE_IN; /* Disable filter */ + *AT91C_PIOA_IDR = BT_CE_IN; /* Disable interrupt */ + *AT91C_PIOA_MDDR = BT_CE_IN; /* Disable multidriver */ + *AT91C_PIOA_PPUDR = BT_CE_IN; /* Disable pullup */ + + *AT91C_PIOA_PER = BT_MISO_IN; /* Enable pin MISO in */ + *AT91C_PIOA_ODR = BT_MISO_IN; /* Set input */ + *AT91C_PIOA_IFDR = BT_MISO_IN; /* Disable filter */ + *AT91C_PIOA_IDR = BT_MISO_IN; /* Disable interrupt */ + *AT91C_PIOA_MDDR = BT_MISO_IN; /* Disable multidriver */ + *AT91C_PIOA_PPUDR = BT_MISO_IN; /* Disable pullup */ + + while (1) + { + Port = *AT91C_PIOA_PDSR; + if ((Port & BT_MISO_IN)) + { + *AT91C_PIOA_SODR = BT_MISO_OUT; + } + else + { + *AT91C_PIOA_CODR = BT_MISO_OUT; + } + if ((Port & BT_MOSI_IN)) + { + *AT91C_PIOA_SODR = BT_MOSI_OUT; + } + else + { + *AT91C_PIOA_CODR = BT_MOSI_OUT; + } + if ((Port & BT_CLK_IN)) + { + *AT91C_PIOA_SODR = BT_CLK_OUT; + } + else + { + *AT91C_PIOA_CODR = BT_CLK_OUT; + } + if ((Port & BT_CE_IN)) + { + *AT91C_PIOA_SODR = BT_CE_OUT; + } + else + { + *AT91C_PIOA_CODR = BT_CE_OUT; + } + } + +} + + +void BtIo(void) +{ + SpiBtIo(); +} + + + +#define SPI_BITRATE 2000000 + +#define SPIA0High {\ + *AT91C_PIOA_SODR = AT91C_PIO_PA12;\ + } + + +#define SPIA0Low {\ + *AT91C_PIOA_CODR = AT91C_PIO_PA12;\ + } + + +#define SPIInit {\ + *AT91C_PMC_PCER = (1L << AT91C_ID_SPI); /* Enable MCK clock */\ + *AT91C_PIOA_PER = AT91C_PIO_PA12; /* Enable A0 on PA12 */\ + *AT91C_PIOA_OER = AT91C_PIO_PA12;\ + *AT91C_PIOA_CODR = AT91C_PIO_PA12;\ + *AT91C_PIOA_PDR = AT91C_PA14_SPCK; /* Enable SPCK on PA14 */\ + *AT91C_PIOA_ASR = AT91C_PA14_SPCK;\ + *AT91C_PIOA_ODR = AT91C_PA14_SPCK;\ + *AT91C_PIOA_OWER = AT91C_PA14_SPCK;\ + *AT91C_PIOA_MDDR = AT91C_PA14_SPCK;\ + *AT91C_PIOA_PPUDR = AT91C_PA14_SPCK;\ + *AT91C_PIOA_IFDR = AT91C_PA14_SPCK;\ + *AT91C_PIOA_CODR = AT91C_PA14_SPCK;\ + *AT91C_PIOA_IDR = AT91C_PA14_SPCK;\ + *AT91C_PIOA_PDR = AT91C_PA13_MOSI; /* Enable mosi on PA13 */\ + *AT91C_PIOA_ASR = AT91C_PA13_MOSI;\ + *AT91C_PIOA_ODR = AT91C_PA13_MOSI;\ + *AT91C_PIOA_OWER = AT91C_PA13_MOSI;\ + *AT91C_PIOA_MDDR = AT91C_PA13_MOSI;\ + *AT91C_PIOA_PPUDR = AT91C_PA13_MOSI;\ + *AT91C_PIOA_IFDR = AT91C_PA13_MOSI;\ + *AT91C_PIOA_CODR = AT91C_PA13_MOSI;\ + *AT91C_PIOA_IDR = AT91C_PA13_MOSI;\ + *AT91C_PIOA_PDR = AT91C_PA10_NPCS2; /* Enable npcs0 on PA11 */\ + *AT91C_PIOA_BSR = AT91C_PA10_NPCS2;\ + *AT91C_PIOA_ODR = AT91C_PA10_NPCS2;\ + *AT91C_PIOA_OWER = AT91C_PA10_NPCS2;\ + *AT91C_PIOA_MDDR = AT91C_PA10_NPCS2;\ + *AT91C_PIOA_PPUDR = AT91C_PA10_NPCS2;\ + *AT91C_PIOA_IFDR = AT91C_PA10_NPCS2;\ + *AT91C_PIOA_CODR = AT91C_PA10_NPCS2;\ + *AT91C_PIOA_IDR = AT91C_PA10_NPCS2;\ + *AT91C_SPI_CR = AT91C_SPI_SWRST; /* Soft reset */\ + *AT91C_SPI_CR = AT91C_SPI_SPIEN; /* Enable spi */\ + *AT91C_SPI_MR = AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | (0xB << 16);\ + AT91C_SPI_CSR[2] = ((OSC / SPI_BITRATE) << 8) | AT91C_SPI_CPOL;\ + } + + +#define SPIWrite(pString,Length) {\ + *AT91C_SPI_TPR = (unsigned int)pString;\ + *AT91C_SPI_TCR = (unsigned int)Length;\ + *AT91C_SPI_PTCR = AT91C_PDC_TXTEN;\ + } + + + +#define CMD 0 +#define DAT 1 +#define DISP_LINES 8 + +#if defined (PROTOTYPE_PCB_3) || (PROTOTYPE_PCB_4) + +#define ACTUAL_WIDTH 100 + +UBYTE DisplayInitString[] = +{ + 0xEB, // LCD bias setting = 1/9 0xEB + 0x2F, // Power control = internal 0x2F + 0xA4, // All points not on 0xA4 + 0xA6, // Not inverse 0xA6 + 0x40, // Start line = 0 0x40 + 0x81, // Electronic volume 0x81 + 0x5A, // -"- 0x5F + 0xC4, // LCD mapping 0xC4 + 0x27, // Set temp comp. 0x27- + 0x29, // Panel loading 0x28 0-1 + 0xA0, // Framerate 0xA0- + 0x88, // CA++ 0x88- + 0x23, // Multiplex 1:65 0x23 + 0xAF // Display on 0xAF +}; + +#else + +#define ACTUAL_WIDTH 128 + +UBYTE DisplayInitString[] = +{ + 0xA2, // LCD bias setting = 1/9 + 0x2F, // Power control = internal + 0xA4, // All points not on + 0xA6, // Not inverse + 0x40, // Start line = 0 + 0x81, // Electronic volume + 0x3F, // -"- + 0xA0, // LCD mapping + 0x27, // Resistor ratio + 0xC8, // Common output state selection + 0xF8, // Booster ratio + 0x00, // -"- + 0xE3, // nop + 0xAF // Display on +}; + +#endif + +UBYTE DisplayLineString[DISP_LINES][3] = +{ + { 0xB0,0x10,0x00 }, + { 0xB1,0x10,0x00 }, + { 0xB2,0x10,0x00 }, + { 0xB3,0x10,0x00 }, + { 0xB4,0x10,0x00 }, + { 0xB5,0x10,0x00 }, + { 0xB6,0x10,0x00 }, + { 0xB7,0x10,0x00 } +}; + +UBYTE DisplayWrite(UBYTE Type,UBYTE *pData,UWORD Length) +{ + UBYTE Result = FALSE; + + if ((*AT91C_SPI_SR & AT91C_SPI_TXEMPTY)) + { + if (Type) + { + SPIA0High; + } + else + { + SPIA0Low; + } + SPIWrite(pData,Length); + Result = TRUE; + } + + return (Result); +} + +UBYTE DisplayUpdate(UWORD Height,UWORD Width,UBYTE *pImage) +{ + static UWORD State = 0; + static UWORD Line; + + if (State == 0) + { + if (DisplayWrite(CMD,(UBYTE*)DisplayInitString,sizeof(DisplayInitString)) == TRUE) + { + Line = 0; + State++; + } + } + else + { + if ((State & 1)) + { + if (DisplayWrite(CMD,(UBYTE*)DisplayLineString[Line],3) == TRUE) + { + State++; + } + } + else + { + if (DisplayWrite(DAT,(UBYTE*)&pImage[Line * Width],ACTUAL_WIDTH) == TRUE) + { + State++; + if (++Line >= (Height / 8)) + { + State = 0; + } + } + } + } + + return (State); +} + + +#if defined (PROTOTYPE_PCB_3) + +#define DISPLAYInit {\ + TSTInit;\ + TSTOn;\ + SPIInit;\ + } + +#else + +#define DISPLAYInit {\ + SPIInit;\ + } + +#endif + +#define DISPLAYOn {\ + DisplayInitString[6] = 0x5A;\ + DisplayInitString[13] = 0xAF;\ + } + +#define DISPLAYOff {\ + DisplayInitString[6] = 0x00;\ + DisplayInitString[13] = 0xAE;\ + } + +#define DISPLAYUpdate(H,W,I) DisplayUpdate(H,W,I) + +#define DISPLAYExit + +#endif + +#ifdef PCWIN + +#endif diff --git a/AT91SAM7S256/Source/d_hispeed.c b/AT91SAM7S256/Source/d_hispeed.c new file mode 100644 index 0000000..cdb79b7 --- /dev/null +++ b/AT91SAM7S256/Source/d_hispeed.c @@ -0,0 +1,48 @@ +// +// Date init 14.12.2004 +// +// Revision date $Date:: 16-05-06 12:13 $ +// +// Filename $Workfile:: d_hispeed.c $ +// +// Version $Revision:: 8 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/d_hispeed. $ +// +// Platform C +// + +#include "stdconst.h" +#include "m_sched.h" +#include "d_hispeed.h" +#include "d_hispeed.r" + +void dHiSpeedInit(void) +{ + HIGHSPEEDInit; +} + +void dHiSpeedSendData(UBYTE *OutputBuffer, UBYTE BytesToSend) +{ + HIGHSPEEDSendDmaData(OutputBuffer,BytesToSend); +} + +void dHiSpeedSetupUart(void) +{ + HIGHSPEEDSetupUart; +} + +void dHiSpeedInitReceive(UBYTE *InputBuffer) +{ + HIGHSPEEDInitReceiver(InputBuffer); +} + +void dHiSpeedReceivedData(UWORD *ByteCnt) +{ + HIGHSPEEDReceivedData(ByteCnt); +} + +void dHiSpeedExit(void) +{ + HIGHSPEEDExit; +} diff --git a/AT91SAM7S256/Source/d_hispeed.h b/AT91SAM7S256/Source/d_hispeed.h new file mode 100644 index 0000000..2ebda66 --- /dev/null +++ b/AT91SAM7S256/Source/d_hispeed.h @@ -0,0 +1,25 @@ +// +// Date init 14.12.2004 +// +// Revision date $Date:: 16-05-06 12:13 $ +// +// Filename $Workfile:: d_hispeed.h $ +// +// Version $Revision:: 5 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/d_hispeed. $ +// +// Platform C +// + +#ifndef D_HISPEED +#define D_HISPEED + +void dHiSpeedInit(void); +void dHiSpeedSendData(UBYTE *OutputBuffer, UBYTE BytesToSend); +void dHiSpeedSetupUart(void); +void dHiSpeedInitReceive(UBYTE *InputBuffer); +void dHiSpeedReceivedData(UWORD *ByteCnt); +void dHiSpeedExit(void); + +#endif diff --git a/AT91SAM7S256/Source/d_hispeed.r b/AT91SAM7S256/Source/d_hispeed.r new file mode 100644 index 0000000..0f4a455 --- /dev/null +++ b/AT91SAM7S256/Source/d_hispeed.r @@ -0,0 +1,190 @@ +// +// Date init 14.12.2004 +// +// Revision date $Date:: 16-05-06 12:13 $ +// +// Filename $Workfile:: d_hispeed.r $ +// +// Version $Revision:: 11 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/d_hispeed. $ +// +// Platform C +// + +#ifdef SAM7S256 + +#if defined (PROTOTYPE_PCB_3) || (PROTOTYPE_PCB_4) + +#define HIGHSPEED_RX_PIN AT91C_PIO_PA5 +#define HIGHSPEED_TX_PIN AT91C_PIO_PA6 +#define HIGHSPEED_RTS_PIN AT91C_PIO_PA7 + +#else + + +#endif + +#define PER_ID6_UART_0 0x40 +#define UART0_INQ 0x40 +#define BAUD_RATE 921600L + +#define SIZE_OF_INBUF 128 +#define NO_OF_INBUFFERS 2 +#define SIZE_OF_OUTBUF 128 +#define NO_OF_DMA_OUTBUFFERS 1 + +static UBYTE InBuf[NO_OF_INBUFFERS][SIZE_OF_INBUF]; +static ULONG InBufPtrs[NO_OF_INBUFFERS]; +static UBYTE InBufInPtr; + +static UBYTE OutDma[NO_OF_DMA_OUTBUFFERS][SIZE_OF_OUTBUF]; +static UBYTE DmaBufPtr; +static UBYTE *pBuffer; + +static UBYTE MsgIn; +static UBYTE InBufOutCnt; + +#define HIGHSPEEDInit {\ + *AT91C_PIOA_PER = HIGHSPEED_TX_PIN | HIGHSPEED_RTS_PIN | HIGHSPEED_RX_PIN; /* Enable PIO on PA07, PA06 & PA05 */\ + *AT91C_PIOA_PPUDR = HIGHSPEED_RX_PIN | HIGHSPEED_TX_PIN | HIGHSPEED_RTS_PIN; /* Disable Pull-up resistor */\ + *AT91C_PIOA_OER = HIGHSPEED_TX_PIN | HIGHSPEED_RTS_PIN | HIGHSPEED_RX_PIN; /* PA07 & PA06 set to Output */\ + *AT91C_PIOA_CODR = HIGHSPEED_TX_PIN | HIGHSPEED_RTS_PIN | HIGHSPEED_RX_PIN; /* Set output low */\ + } + + +#define HIGHSPEEDSetupUart {\ + UBYTE Tmp;\ + InBufInPtr = 0;\ + for(Tmp = 0; Tmp < NO_OF_INBUFFERS; Tmp++)\ + {\ + InBufPtrs[Tmp] = (ULONG)&(InBuf[Tmp][0]);\ + }\ + *AT91C_PMC_PCER = PER_ID6_UART_0; /* Enable PMC clock for UART 0 */\ + *AT91C_PIOA_PPUDR = HIGHSPEED_RX_PIN | HIGHSPEED_TX_PIN | HIGHSPEED_RTS_PIN; /* Disable Pull-up resistor */\ + *AT91C_PIOA_PDR = HIGHSPEED_TX_PIN | HIGHSPEED_RTS_PIN | HIGHSPEED_RX_PIN; /* Disable Per. A on PA5, PA6 & PA7 */\ + *AT91C_PIOA_ASR = HIGHSPEED_TX_PIN | HIGHSPEED_RTS_PIN | HIGHSPEED_RX_PIN;; /* Enable Per. A on PA5, PA6 & PA7 */\ + *AT91C_US0_CR = AT91C_US_RSTSTA; /* Resets pins on UART0 */\ + *AT91C_US0_CR = AT91C_US_STTTO; /* Start timeout functionality after 1 byte */\ + *AT91C_US0_RTOR = 2400; /* Approxitely 20 mS,x times bit time with 115200 bit pr s */\ + *AT91C_US0_IDR = AT91C_US_TIMEOUT; /* Disable interrupt on timeout */\ + *AT91C_AIC_IDCR = UART0_INQ; /* Disable UART0 interrupt */\ + *AT91C_AIC_ICCR = UART0_INQ; /* Clear interrupt register */\ + *AT91C_US0_MR = AT91C_US_USMODE_RS485; /* Set UART to RUN RS485 Mode*/\ + *AT91C_US0_MR &= ~AT91C_US_SYNC; /* Set UART in asynchronous mode */\ + *AT91C_US0_MR |= AT91C_US_CLKS_CLOCK; /* Clock setup MCK*/\ + *AT91C_US0_MR |= AT91C_US_CHRL_8_BITS; /* UART using 8-bit */\ + *AT91C_US0_MR |= AT91C_US_PAR_NONE; /* UART using none parity bit */\ + *AT91C_US0_MR |= AT91C_US_NBSTOP_1_BIT; /* UART using 1 stop bit */\ + *AT91C_US0_MR |= AT91C_US_OVER; /* UART is using 8-bit sampling */\ + *AT91C_US0_BRGR = ((OSC/8/BAUD_RATE) | (((OSC/8) - ((OSC/8/BAUD_RATE) * BAUD_RATE)) / ((BAUD_RATE + 4)/8)) << 16);\ + *AT91C_US0_PTCR = (AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS); /* Disable of TX & RX with DMA */\ + *AT91C_US0_RCR = 0; /* Receive Counter Register */\ + *AT91C_US0_TCR = 0; /* Transmit Counter Register */\ + *AT91C_US0_RNPR = 0;\ + *AT91C_US0_TNPR = 0;\ + Tmp = *AT91C_US0_RHR;\ + Tmp = *AT91C_US0_CSR;\ + *AT91C_US0_RPR = (unsigned int)&(InBuf[InBufInPtr][0]); /* Initialise receiver buffer using DMA */\ + *AT91C_US0_RCR = SIZE_OF_INBUF;\ + *AT91C_US0_RNPR = (unsigned int)&(InBuf[(InBufInPtr + 1)%NO_OF_INBUFFERS][0]);\ + *AT91C_US0_RNCR = SIZE_OF_INBUF;\ + MsgIn = 0;\ + InBufOutCnt = 0;\ + *AT91C_US0_CR = AT91C_US_RXEN | AT91C_US_TXEN; /* Enable Tx & Rx on UART 0*/\ + *AT91C_US0_PTCR = (AT91C_PDC_RXTEN | AT91C_PDC_TXTEN); /* Enable of TX & RX with DMA */\ + } + +#define HIGHSPEEDInitReceiver(InputBuffer)\ + {\ + UBYTE Tmp;\ + pBuffer = InputBuffer;\ + *AT91C_US0_PTCR = (AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS); /* Disable of TX & RX with DMA */\ + *AT91C_US0_RCR = 0; /* Receive Counter Register */\ + *AT91C_US0_TCR = 0; /* Transmit Counter Register */\ + *AT91C_US0_RNPR = 0;\ + *AT91C_US0_TNPR = 0;\ + Tmp = *AT91C_US0_RHR;\ + Tmp = *AT91C_US0_CSR;\ + Tmp = Tmp;\ + *AT91C_US0_RPR = (unsigned int)&(InBuf[InBufInPtr][0]); /* Initialise receiver buffer using DMA */\ + *AT91C_US0_RCR = SIZE_OF_INBUF;\ + *AT91C_US0_RNPR = (unsigned int)&(InBuf[(InBufInPtr + 1)%NO_OF_INBUFFERS][0]);\ + *AT91C_US0_RNCR = SIZE_OF_INBUF;\ + MsgIn = 0;\ + InBufOutCnt = 0;\ + *AT91C_US0_CR = AT91C_US_RXEN | AT91C_US_TXEN; /* Enable Tx & Rx on UART 0*/\ + *AT91C_US0_PTCR = (AT91C_PDC_RXTEN | AT91C_PDC_TXTEN); /* Enable of TX & RX with DMA */\ + } + + +#define HIGHSPEEDReceivedData(pByteCnt)\ + {\ + UWORD InCnt;\ + *pByteCnt = 0;\ + InCnt = (SIZE_OF_INBUF - *AT91C_US0_RCR);\ + if (*AT91C_US0_RNCR == 0)\ + {\ + InCnt = SIZE_OF_INBUF;\ + }\ + InCnt -= InBufOutCnt; /* Remove already read bytes */\ + if(InCnt)\ + {\ + while(InCnt > 0)\ + {\ + pBuffer[MsgIn] = InBuf[InBufInPtr][InBufOutCnt];\ + MsgIn++;\ + InBufOutCnt++;\ + InCnt--;\ + }\ + *pByteCnt = MsgIn;\ + MsgIn = 0;\ + }\ + if ((*AT91C_US0_RNCR == 0) && (SIZE_OF_INBUF == InBufOutCnt))\ + {\ + InBufOutCnt = 0;\ + *AT91C_US0_RNPR = (unsigned int)InBufPtrs[InBufInPtr];\ + *AT91C_US0_RNCR = SIZE_OF_INBUF;\ + InBufInPtr = (InBufInPtr + 1) % NO_OF_INBUFFERS;\ + }\ + } + +#define AVAILOutBuf(Avail) if (!(*AT91C_US0_TNCR))\ + {\ + Avail = SIZE_OF_OUTBUF;\ + }\ + else\ + {\ + Avail = 0;\ + } + +#define HIGHSPEEDSendDmaData(OutputBuffer, BytesToSend)\ + {\ + UWORD Avail, Cnt;\ + AVAILOutBuf(Avail);\ + if (BytesToSend < (Avail - 1))\ + {\ + for (Cnt = 0; Cnt < BytesToSend; Cnt++)\ + {\ + OutDma[DmaBufPtr][Cnt] = OutputBuffer[Cnt];\ + }\ + *AT91C_US0_TNPR = (unsigned int)&(OutDma[DmaBufPtr][0]);\ + *AT91C_US0_TNCR = BytesToSend;\ + DmaBufPtr = (DmaBufPtr + 1) % NO_OF_DMA_OUTBUFFERS;\ + }\ + } + +#define HIGHSPEEDExit {\ + *AT91C_PMC_PCDR = PER_ID6_UART_0; /* Disable PMC clock for UART 0*/\ + *AT91C_PIOA_PER = HIGHSPEED_TX_PIN | HIGHSPEED_RTS_PIN | HIGHSPEED_RX_PIN; /* Enable PIO on PA07, PA06 & PA05 */\ + *AT91C_PIOA_PPUDR = HIGHSPEED_RX_PIN | HIGHSPEED_TX_PIN | HIGHSPEED_RTS_PIN; /* Disable Pull-up resistor */\ + *AT91C_PIOA_OER = HIGHSPEED_TX_PIN | HIGHSPEED_RTS_PIN | HIGHSPEED_RX_PIN; /* PA07 & PA06 set to Output */\ + *AT91C_PIOA_CODR = HIGHSPEED_TX_PIN | HIGHSPEED_RTS_PIN | HIGHSPEED_RX_PIN; /* Set output low */\ + } + + +#endif + +#ifdef PCWIN + +#endif diff --git a/AT91SAM7S256/Source/d_input.c b/AT91SAM7S256/Source/d_input.c new file mode 100644 index 0000000..272f35e --- /dev/null +++ b/AT91SAM7S256/Source/d_input.c @@ -0,0 +1,104 @@ +// +// Date init 14.12.2004 +// +// Revision date $Date:: 16-05-06 10:06 $ +// +// Filename $Workfile:: d_input.c $ +// +// Version $Revision:: 14 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/d_input.c $ +// +// Platform C +// + +#include "stdconst.h" +#include "m_sched.h" +#include "c_input.h" +#include "d_input.h" +#include "d_input.r" + + +void dInputInit(void) +{ + INPUTInit; +} + + +void dInputGetRawAd(UWORD *pValues, UBYTE No) +{ + INPUTGetVal(pValues, No); +} + + +void dInputSetDirOutDigi0(UBYTE Port) +{ + INPUTSetOutDigi0(Port); +} + +void dInputSetDirOutDigi1(UBYTE Port) +{ + INPUTSetOutDigi1(Port); +} + +void dInputSetDirInDigi0(UBYTE Port) +{ + INPUTSetInDigi0(Port); +} + +void dInputSetDirInDigi1(UBYTE Port) +{ + INPUTSetInDigi1(Port); +} + +void dInputClearDigi0(UBYTE Port) +{ + INPUTClearDigi0(Port); +} + +void dInputClearDigi1(UBYTE Port) +{ + INPUTClearDigi1(Port); +} + +void dInputSetDigi0(UBYTE Port) +{ + INPUTSetDigi0(Port); +} + +void dInputSetDigi1(UBYTE Port) +{ + INPUTSetDigi1(Port); +} + +void dInputRead0(UBYTE Port, UBYTE *pData) +{ + INPUTReadDigi0(Port, pData); +} + +void dInputRead1(UBYTE Port, UBYTE * pData) +{ + INPUTReadDigi1(Port, pData); +} + +void dInputSetActive(UBYTE Port) +{ + INPUTSetActive(Port); +} + +void dInputSet9v(UBYTE Port) +{ + INPUTSet9v(Port); +} + +void dInputSetInactive(UBYTE Port) +{ + INPUTSetInactive(Port); +} + + +void dInputExit(void) +{ + INPUTExit; +} + diff --git a/AT91SAM7S256/Source/d_input.h b/AT91SAM7S256/Source/d_input.h new file mode 100644 index 0000000..8a7d4ef --- /dev/null +++ b/AT91SAM7S256/Source/d_input.h @@ -0,0 +1,37 @@ +// +// Date init 14.12.2004 +// +// Revision date $Date:: 16-05-06 10:06 $ +// +// Filename $Workfile:: d_input.h $ +// +// Version $Revision:: 6 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/d_input.h $ +// +// Platform C +// + +#ifndef D_INPUT +#define D_INPUT + +void dInputInit(void); +void dInputExit(void); + +void dInputGetRawAd(UWORD *pValues, UBYTE No); +void dInputSetActive(UBYTE Port); +void dInputSet9v(UBYTE Port); +void dInputSetInactive(UBYTE Port); + +void dInputSetDirOutDigi0(UBYTE Port); +void dInputSetDirOutDigi1(UBYTE Port); +void dInputSetDirInDigi0(UBYTE Port); +void dInputSetDirInDigi1(UBYTE Port); +void dInputClearDigi0(UBYTE Port); +void dInputClearDigi1(UBYTE Port); +void dInputSetDigi0(UBYTE Port); +void dInputSetDigi1(UBYTE Port); +void dInputRead0(UBYTE Port, UBYTE *pData); +void dInputRead1(UBYTE Port, UBYTE *pData); + +#endif diff --git a/AT91SAM7S256/Source/d_input.r b/AT91SAM7S256/Source/d_input.r new file mode 100644 index 0000000..6e3d989 --- /dev/null +++ b/AT91SAM7S256/Source/d_input.r @@ -0,0 +1,99 @@ +// +// Date init 14.12.2004 +// +// Revision date $Date:: 16-05-06 10:06 $ +// +// Filename $Workfile:: d_input.r $ +// +// Version $Revision:: 10 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/d_input.r $ +// +// Platform C +// + +#ifdef SAM7S256 + +#define MAX_AD_VALUE 0x3FF + +#define INPUTInit {\ + UBYTE Tmp;\ + for (Tmp = 0; Tmp < NOS_OF_AVR_INPUTS; Tmp++)\ + {\ + IoFromAvr.AdValue[Tmp] = MAX_AD_VALUE;\ + }\ + IoToAvr.InputPower = 0;\ + for (Tmp = 0; Tmp < NO_OF_INPUTS; Tmp++)\ + {\ + *AT91C_PIOA_PPUDR = Digi0Alloc[Tmp];\ + *AT91C_PIOA_PPUDR = Digi1Alloc[Tmp];\ + INPUTSetInDigi0(Tmp);\ + INPUTSetInDigi1(Tmp);\ + }\ + } + +#define INPUTGetVal(pValues, No) *pValues = (UWORD)IoFromAvr.AdValue[No];\ + *pValues &= 0x03FF + +#define INPUTSetActive(Input) IoToAvr.InputPower |= (0x01 << Input);\ + IoToAvr.InputPower &= ~(0x10 << Input) +#define INPUTSet9v(Input) IoToAvr.InputPower |= (0x10 << Input);\ + IoToAvr.InputPower &= ~(0x01 << Input) +#define INPUTSetInactive(Input) IoToAvr.InputPower &= ~(0x11 << Input) + +const ULONG Digi0Alloc[] = {AT91C_PIO_PA23, AT91C_PIO_PA28, AT91C_PIO_PA29, AT91C_PIO_PA30}; +const ULONG Digi1Alloc[] = {AT91C_PIO_PA18, AT91C_PIO_PA19, AT91C_PIO_PA20, AT91C_PIO_PA2}; + +#define INPUTSetOutDigi0(Input) *AT91C_PIOA_PER = Digi0Alloc[Input];\ + *AT91C_PIOA_OER = Digi0Alloc[Input] + +#define INPUTSetOutDigi1(Input) *AT91C_PIOA_PER = Digi1Alloc[Input];\ + *AT91C_PIOA_OER = Digi1Alloc[Input] + + +#define INPUTSetInDigi0(Input) *AT91C_PIOA_PER = Digi0Alloc[Input];\ + *AT91C_PIOA_ODR = Digi0Alloc[Input] + +#define INPUTSetInDigi1(Input) *AT91C_PIOA_PER = Digi1Alloc[Input];\ + *AT91C_PIOA_ODR = Digi1Alloc[Input] + +#define INPUTSetDigi0(Input) *AT91C_PIOA_SODR = Digi0Alloc[Input] + +#define INPUTSetDigi1(Input) *AT91C_PIOA_SODR = Digi1Alloc[Input] + +#define INPUTClearDigi0(Input) *AT91C_PIOA_CODR = Digi0Alloc[Input] + +#define INPUTClearDigi1(Input) *AT91C_PIOA_CODR = Digi1Alloc[Input] + +#define INPUTReadDigi0(Input, Data) if ((*AT91C_PIOA_PDSR) & Digi0Alloc[Input])\ + {\ + *Data |= 0x00000001;\ + }\ + else\ + {\ + *Data &= ~0x00000001;\ + } +#define INPUTReadDigi1(Input, Data) if ((*AT91C_PIOA_PDSR) & Digi1Alloc[Input])\ + {\ + *Data |= 0x00000002;\ + }\ + else\ + {\ + *Data &= ~0x00000002;\ + } + +#define INPUTExit {\ + UBYTE Tmp;\ + for (Tmp = 0; Tmp < NO_OF_INPUTS; Tmp++)\ + {\ + INPUTSetInDigi0(Tmp);\ + INPUTSetInDigi1(Tmp);\ + }\ + } + + +#endif + +#ifdef PCWIN + +#endif diff --git a/AT91SAM7S256/Source/d_ioctrl.c b/AT91SAM7S256/Source/d_ioctrl.c new file mode 100644 index 0000000..7c414f6 --- /dev/null +++ b/AT91SAM7S256/Source/d_ioctrl.c @@ -0,0 +1,102 @@ +// +// Date init 14.12.2004 +// +// Revision date $Date:: 16-05-06 9:50 $ +// +// Filename $Workfile:: d_ioctrl.c $ +// +// Version $Revision:: 11 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/d_ioctrl.c $ +// +// Platform C +// + + +#include +#include "stdconst.h" +#include "m_sched.h" +#include "d_ioctrl.h" +#include "d_ioctrl.r" + +/* Enum related to State */ +enum +{ + RX_I2C = 1, + TX_I2C = 2, + UNLOCK_I2C = 3, + WAIT_I2C = 4 +}; + + +static UBYTE volatile State; + +void dIOCtrlInit(void) +{ + IOCTRLInit; + State = UNLOCK_I2C; +} + +void dIOCtrlSetPower(UBYTE Power) +{ + INSERTPower(Power); +} + +void dIOCtrlSetPwm(UBYTE Pwm) +{ + INSERTPwm(Pwm); +} + +void dIOCtrlTransfer(void) +{ + UBYTE B; + + CHECKTime(B); + if (B) + { + switch(State) + { + case TX_I2C: + { + FULLDataTx; + State = RX_I2C; + } + break; + case RX_I2C: + { + FULLDataRx; + State = TX_I2C; + } + break; + case UNLOCK_I2C: + { + UNLOCKTx; + State = WAIT_I2C; + } + break; + case WAIT_I2C: + { + + /* Intermediate state as unlock string is 47 */ + /* characters which is a little more than 1mS */ + State = TX_I2C; + } + break; + default: + { + UNLOCKTx; + State = WAIT_I2C; + } + break; + } + SETTime; + } +} + + + +void dIOCtrlExit(void) +{ + IOCTRLExit; +} + diff --git a/AT91SAM7S256/Source/d_ioctrl.h b/AT91SAM7S256/Source/d_ioctrl.h new file mode 100644 index 0000000..4ebedd3 --- /dev/null +++ b/AT91SAM7S256/Source/d_ioctrl.h @@ -0,0 +1,25 @@ +// +// Date init 14.12.2004 +// +// Revision date $Date:: 16-05-06 9:50 $ +// +// Filename $Workfile:: d_ioctrl.h $ +// +// Version $Revision:: 7 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/d_ioctrl.h $ +// +// Platform C +// + +#ifndef D_AVRCOMM +#define D_AVRCOMM + +void dIOCtrlInit(void); +void dIOCtrlExit(void); + +void dIOCtrlSetPower(UBYTE Power); +void dIOCtrlSetPwm(UBYTE Pwm); +void dIOCtrlTransfer(void); + +#endif diff --git a/AT91SAM7S256/Source/d_ioctrl.r b/AT91SAM7S256/Source/d_ioctrl.r new file mode 100644 index 0000000..71bf0f4 --- /dev/null +++ b/AT91SAM7S256/Source/d_ioctrl.r @@ -0,0 +1,310 @@ +// +// Date init 14.12.2004 +// +// Revision date $Date:: 16-05-06 9:50 $ +// +// Filename $Workfile:: d_ioctrl.r $ +// +// Version $Revision:: 21 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/d_ioctrl.r $ +// +// Platform C +// + + +#ifdef SAM7S256 + +#define NO_TO_TX BYTES_TO_TX + 1 +#define NO_TO_RX BYTES_TO_RX + 1 +#define TIMEOUT 2100 + + + +extern void I2cHandler(void); + +static UBYTE *pIrq; +static UBYTE Cnt; +static UBYTE NoToTx; +static UBYTE I2cStatus; +static UBYTE I2cInBuffer[NO_TO_RX]; +static UBYTE I2cOutBuffer[NO_TO_TX]; +static UBYTE RxSum; + +#define I2C_IDLE 1 +#define I2C_ERROR 2 +#define I2C_TX 3 +#define I2C_RX 4 + +#define I2CClk 400000L +#define TIME400KHz (((OSC/16L)/(I2CClk * 2)) + 1) +#define CLDIV (((OSC/I2CClk)/2)-3) + +#define DEVICE_ADR 0x01 +#define DISABLEI2cIrqs *AT91C_TWI_IDR = 0x000001C7 +#define ISSUEStopCond *AT91C_TWI_CR = AT91C_TWI_STOP + + +#define WAITClk {\ + ULONG PitTmr;\ + PitTmr = (*AT91C_PITC_PIIR & AT91C_PITC_CPIV) + TIME400KHz;\ + if (PitTmr >= (*AT91C_PITC_PIMR & AT91C_PITC_CPIV))\ + {\ + PitTmr -= (*AT91C_PITC_PIMR & AT91C_PITC_CPIV);\ + }\ + while ((*AT91C_PITC_PIIR & AT91C_PITC_CPIV) < PitTmr);\ + } + + + +#define RESETI2c {\ + UBYTE Tmp;\ + *AT91C_PMC_PCER = (1L< +#include + +#define FILEVERSION (0x00000106L) + +#define MAX_FILES ((SECTORSIZE/4) - 1) /* Last file entry is used for file version*/ +#define MAX_WRITE_BUFFERS 4 +#define FLASHOFFSET (0x100000L) + +#define IS_LOADER_ERR(LStatus) (((LStatus) & 0xFF00) != SUCCESS) +#define SECTORINDEXUSERFLASH ((STARTOFUSERFLASH & ~FLASHOFFSET)/256/32) +#define SECTORPOINTERUSERFLASH (((STARTOFUSERFLASH & ~FLASHOFFSET) - ((SECTORINDEXUSERFLASH * 32) * 256))/256) + +typedef struct +{ + const UBYTE *pFlash; + const UWORD *pSectorNo; + ULONG ReadLength; + ULONG DataLength; + ULONG FileDlPtr; + UBYTE SearchStr[FILENAME_SIZE]; + UWORD FileIndex; + UWORD CheckSum; + UBYTE SearchType; + UBYTE Status; + UBYTE FileType; + UBYTE WriteBufNo; +}HANDLE; + +typedef struct +{ + ULONG Buf[SECTORSIZE/4]; + UBYTE BufIndex; + UBYTE Status; +}WRITEBUF; + +static HANDLE HandleTable[MAX_HANDLES]; +static WRITEBUF WriteBuffer[MAX_WRITE_BUFFERS]; +static ULONG SectorTable[NOOFSECTORS>>5]; +static const ULONG *Files; +static FILEHEADER Header; +static ULONG FreeUserFlash; +static UWORD FreeSectors; + +void dLoaderUpdateSectorTable(void); +UWORD dLoaderGetFreeHandle(void); +const UBYTE * dLoaderGetNextSectorPtr(UBYTE Handle); +ULONG dLoaderReturnFreeFlash(void); +UWORD dLoaderAllocateHeader(UWORD Handle, ULONG *FileStartAdr, FILEHEADER *pHeader, UWORD HeaderByteSize, UWORD CompleteFileSectorSize); +UWORD dLoaderFlashFileHeader(UWORD Handle, ULONG FileStartAdr, FILEHEADER *pHeader, UWORD HeaderByteSize); +UWORD dLoaderFindFirstSector(UBYTE Type, UWORD SectorCount, UWORD *pSector); +UWORD dLoaderAllocateWriteBuffer(UWORD Handle); +UWORD dLoaderSetFilePointer(UWORD Handle, ULONG BytePtr, const UBYTE **pData); +UWORD dLoaderGetSectorNumber(ULONG Adr); +void dLoaderCheckVersion(void); +UWORD dLoaderCheckHandle(UWORD Handle, UBYTE Operation); +ULONG dLoaderCalcFreeFileSpace(UWORD NosOfFreeSectors); +UWORD dLoaderCheckDownload(UBYTE *pName); +UWORD dLoaderAvailFileNo(void); + + +void dLoaderInit(void) +{ + UWORD Tmp; + + LOADERInit; + + Files = (const ULONG*)STARTOFFILETABLE; + + /* Clear handle table */ + for (Tmp = 0; Tmp < MAX_HANDLES; Tmp++) + { + HandleTable[Tmp].Status = FREE; + HandleTable[Tmp].WriteBufNo = FREEBUFNO; + } + + /* Clear write buffers */ + for (Tmp = 0; Tmp < MAX_WRITE_BUFFERS; Tmp++) + { + WriteBuffer[Tmp].Status = FREE; + } + + dLoaderCheckVersion(); + dLoaderUpdateSectorTable(); + FreeUserFlash = dLoaderReturnFreeFlash(); +} + +UWORD dLoaderAvailFileNo(void) +{ + UBYTE Tmp, Tmp2; + UWORD ReturnVal; + const ULONG* FlashPtr; + + ReturnVal = NOMOREFILES; + Tmp2 = 0; + FlashPtr = Files; + for(Tmp = 0; Tmp < MAX_HANDLES; Tmp++) + { + + /* Check for files allready downloading except datafiles as the have entered their */ + /* filepointer in the filepointer table at begin of download */ + if ((DOWNLOADING == HandleTable[Tmp].Status) && (DATAFILE != HandleTable[Tmp].FileType)) + { + Tmp2++; + } + } + if ((0xFFFFFFFF == FlashPtr[(MAX_FILES - 1) - Tmp2]) || (0 == FlashPtr[(MAX_FILES - 1) - Tmp2])) + { + ReturnVal = SUCCESS; + } + return(ReturnVal); +} + + +UWORD dLoaderInsertPtrTable(const UBYTE *pAdr, UWORD Handle) +{ + UWORD TmpCnt; + UWORD Status; + ULONG SectorCopy[(SECTORSIZE/4)]; + const ULONG* FlashPtr; + + /* It is possible to add the file as checking for number of files */ + /* is done when initiating the file download */ + FlashPtr = Files; + memset(SectorCopy, 0, sizeof(SectorCopy)); + + TmpCnt = MAX_FILES - 1; + while(TmpCnt) + { + + /* TmpCnt-- first because you want to copy from index 0 */ + TmpCnt--; + SectorCopy[TmpCnt + 1] = FlashPtr[TmpCnt]; + } + + /* Copy the new file in position 0 */ + SectorCopy[0] = (ULONG)pAdr; + + /* Add the File version to the top of the file list */ + SectorCopy[MAX_FILES] = FlashPtr[MAX_FILES]; + dLoaderWritePage((ULONG)Files, SECTORSIZE, SectorCopy); + + /* FileIndex in HandleTable should be incremented by one - new file index is 0 */ + for (TmpCnt = 0; TmpCnt < MAX_HANDLES; TmpCnt++) + { + if (HandleTable[TmpCnt].Status != FREE) + { + (HandleTable[TmpCnt].FileIndex)++; + } + } + HandleTable[Handle].FileIndex = 0; + + Status = SUCCESS | Handle; + + return(Status); +} + + +UWORD dLoaderDeleteFilePtr(UWORD Handle) +{ + + UWORD ErrorCode; + UWORD LongCnt; + ULONG SectorCopy[(SECTORSIZE>>2)]; + const ULONG *pFlash; + + ErrorCode = SUCCESS; + if (0xFFFFFFFF != Files[HandleTable[Handle].FileIndex]) + { + ErrorCode = dLoaderCheckFiles(Handle); + if (0x8000 > ErrorCode) + { + pFlash = Files; + for (LongCnt = 0; LongCnt < (HandleTable[Handle].FileIndex); LongCnt++, pFlash++) + { + SectorCopy[LongCnt] = *pFlash; + } + + /* Skip the file that has to be deleted */ + pFlash++; + for ( ; LongCnt < (MAX_FILES - 1); LongCnt++, pFlash++) + { + SectorCopy[LongCnt] = *pFlash; + } + + /* The top file entry is now free */ + SectorCopy[MAX_FILES - 1] = 0xFFFFFFFF; + + /* Insert the file version */ + SectorCopy[MAX_FILES] = *pFlash; + + + /* Write the sectortable back into flash */ + dLoaderWritePage((ULONG)Files, SECTORSIZE,(ULONG*) &SectorCopy); + dLoaderUpdateSectorTable(); + FreeUserFlash = dLoaderReturnFreeFlash(); + + /* Update the HandleTable[].FileIndex */ + for (LongCnt = 0; LongCnt < MAX_HANDLES; LongCnt++) + { + if ((HandleTable[Handle].FileIndex <= HandleTable[LongCnt].FileIndex) && (FREE != HandleTable[LongCnt].Status)) + { + (HandleTable[LongCnt].FileIndex)--; + } + } + } + } + else + { + ErrorCode = FILENOTFOUND; + } + return(ErrorCode | Handle); +} + + +void dLoaderDeleteAllFiles(void) +{ + ULONG Tmp; + ULONG SectorBuf[SECTORSIZE/4]; + + /* Close all handles - all files is to be wiped out */ + for (Tmp = 0; Tmp < MAX_HANDLES; Tmp++) + { + dLoaderCloseHandle(Tmp); + } + + for (Tmp = ((STARTOFUSERFLASH-FLASHOFFSET)/SECTORSIZE); Tmp < (SIZEOFFLASH/SECTORSIZE); Tmp++) + { + dLoaderErasePage(Tmp<>5] |= (0x1 << (SectorNo - ((SectorNo>>5)<<5))); + Tmp += (SECTORSIZE >> 2); + } + + for (Tmp = 0; Tmp < MAX_FILES; Tmp++) + { + if ((0xFFFFFFFF != Files[Tmp]) && (0x00000000 != Files[Tmp])) + { + pFile = (const FILEHEADER *) Files[Tmp]; + FileStart = pFile->FileStartAdr; + + /* This is necessary if the start address is at the first address in an sector */ + SectorNo = dLoaderGetSectorNumber((ULONG)pFile->FileStartAdr); + SectorTable[SectorNo>>5] |= (0x1 << (SectorNo - ((SectorNo>>5)<<5))); + + /* This is necessary as the first sector (where the fileheader is) is not */ + /* included in the sector table */ + SectorNo = dLoaderGetSectorNumber((ULONG)Files[Tmp]); + SectorTable[SectorNo>>5] |= (0x1 << (SectorNo - ((SectorNo>>5)<<5))); + + SectorNo = 0; + while(FileStart > ((ULONG)(&(pFile->FileSectorTable[SectorNo]))) && (NOOFSECTORS > pFile->FileSectorTable[SectorNo])) + { + SectorTable[(pFile->FileSectorTable[SectorNo])>>5] |= (0x1 << ((pFile->FileSectorTable[SectorNo]) - (((pFile->FileSectorTable[SectorNo])>>5)<<5))); + if (0 == ((ULONG)(&(pFile->FileSectorTable[SectorNo+1])) & (SECTORSIZE-1))) + { + SectorNo += (((pFile->FileSectorTable[SectorNo]) << SECTORSIZESHIFT) - ((ULONG)&(pFile->FileSectorTable[SectorNo]) & ~FLASHOFFSET)>>1); + } + else + { + SectorNo++; + } + } + } + } +} + + +UWORD dLoaderCreateFileHeader(ULONG FileSize, UBYTE *pName, UBYTE LinearState, UBYTE FileType) +{ + UWORD HeaderByteSize; + ULONG FileStartAdr; + ULONG CompleteFileByteSize; + UWORD Handle; + UBYTE Name[FILENAME_SIZE]; + ULONG FileLength; + ULONG DataLength; + UWORD ErrorCode; + UWORD CompleteSectorNo; + UWORD Tmp; + + memset(&(Header.FileName), 0, sizeof(Header.FileName)); + memset(&(Header.FileSectorTable), 0xFF, sizeof(Header.FileSectorTable)); + + ErrorCode = dLoaderFind(pName, Name, &FileLength, &DataLength, (UBYTE)BUSY); + Handle = ErrorCode & 0x00FF; + if (SUCCESS == (ErrorCode & 0xFF00)) + { + ErrorCode |= FILEEXISTS; + } + if (FILENOTFOUND == (ErrorCode & 0xFF00)) + { + /* Here check for the download buffers for a matching download */ + /* in progress */ + ErrorCode &= 0x00FF; + ErrorCode = dLoaderCheckDownload(pName); + + if (0x8000 > ErrorCode) + { + + /* Check for file overflow */ + ErrorCode = dLoaderAvailFileNo(); + if (0x8000 > ErrorCode) + { + + ErrorCode = dLoaderAllocateWriteBuffer(Handle); + if (0x8000 > ErrorCode) + { + + dLoaderCopyFileName((Header.FileName), pName); + HandleTable[Handle].pSectorNo = 0; + HandleTable[Handle].DataLength = FileSize; /* used for end of file detection */ + Header.FileSize = FileSize; /* used to program into flash */ + if (DATAFILE == FileType) + { + Header.DataSize = 0; + } + else + { + Header.DataSize = FileSize; + } + HandleTable[Handle].FileType = FileType | LinearState; /* if it is a datafile it can be stopped */ + Header.FileType = FileType | LinearState; /* FileType included for future appending */ + + /* File body size calculation*/ + CompleteFileByteSize = FileSize; + + /* Add the the fixed header to the fixed size */ + CompleteFileByteSize += HEADERFIXEDSIZE; + + /* Find the number of sectors used by the fixed file size */ + CompleteSectorNo = (CompleteFileByteSize - 1) >> SECTORSIZESHIFT; + + /* Add the size taken by the sectortable */ + CompleteFileByteSize += (CompleteSectorNo << 1); + + /* Recalc the number of sectors - to see wether the sectortable has caused */ + /* the sectornumber to encrease */ + Tmp = ((CompleteFileByteSize - 1) >> SECTORSIZESHIFT); + + /* Substract from the original sectors used - Tmp holds the encreased number*/ + Tmp -= CompleteSectorNo; + if (Tmp) + { + /* The sectortable takes up more than one sector */ + CompleteFileByteSize += Tmp << 1; + CompleteSectorNo += Tmp; + } + + HeaderByteSize = CompleteFileByteSize - FileSize; + + if (HeaderByteSize & 0x0003) + { + /* Header size is not a multiplum of 4 - now make it a mul 4 */ + HeaderByteSize += (0x0004 - (HeaderByteSize & 0x0003)); + } + + if (FileSize <= FreeUserFlash) + { + + + /* Allocate file header */ + Tmp = (((CompleteFileByteSize - 1) >> SECTORSIZESHIFT) + 1); + Handle = dLoaderAllocateHeader(Handle, &FileStartAdr, &Header, HeaderByteSize, Tmp); + if (Handle < 0x8000) + { + dLoaderFlashFileHeader(Handle, FileStartAdr, &Header, HeaderByteSize); + + /* If this is a datafile then add the filepointer to the filepointer table */ + /* now as the datafile do not need to have a special size to be valid */ + if (DATAFILE & HandleTable[Handle].FileType) + { + ErrorCode = dLoaderInsertPtrTable((const UBYTE *)HandleTable[Handle].FileDlPtr, Handle); + } + FreeSectors -= Tmp; + FreeUserFlash = dLoaderCalcFreeFileSpace(FreeSectors); + HandleTable[Handle].Status = DOWNLOADING; + } + } + else + { + ErrorCode = NOSPACE; + } + } + } + } + } + + return(ErrorCode | Handle); +} + + +UWORD dLoaderWriteData(UWORD Handle, UBYTE *pBuf, UWORD *pLen) +{ + UWORD Tmp; + UBYTE *pSectorBuf; + + Handle = dLoaderCheckHandle(Handle, DOWNLOADING); + if (0x8000 > Handle) + { + + if (*pLen > HandleTable[Handle].DataLength) + { + + /* Write request exceeds filesize - only flash up to filesize*/ + *pLen = HandleTable[Handle].DataLength; + WriteBuffer[HandleTable[Handle].WriteBufNo].Status = DLERROR; /* save error untill close handle */ + } + + pSectorBuf = (UBYTE *)WriteBuffer[HandleTable[Handle].WriteBufNo].Buf; + for(Tmp = 0; Tmp < *pLen; Tmp++) + { + pSectorBuf[WriteBuffer[HandleTable[Handle].WriteBufNo].BufIndex] = pBuf[Tmp]; + if ((WriteBuffer[HandleTable[Handle].WriteBufNo].BufIndex) >= (SECTORSIZE-1)) + { + dLoaderWritePage(((ULONG)HandleTable[Handle].pFlash & ~(SECTORSIZE - 1)), SECTORSIZE, WriteBuffer[HandleTable[Handle].WriteBufNo].Buf); + WriteBuffer[HandleTable[Handle].WriteBufNo].BufIndex = 0; + HandleTable[Handle].pFlash = dLoaderGetNextSectorPtr(Handle); + memset(WriteBuffer[HandleTable[Handle].WriteBufNo].Buf, 0xFF, sizeof(WriteBuffer[0].Buf)); + } + else + { + (WriteBuffer[HandleTable[Handle].WriteBufNo].BufIndex)++; + } + } + HandleTable[Handle].DataLength -= *pLen; + + /* Check for correct end of file */ + if (0 == HandleTable[Handle].DataLength) + { + if ((WriteBuffer[HandleTable[Handle].WriteBufNo].BufIndex) != 0) + { + + /* write the last data into the file */ + dLoaderWritePage(((ULONG)HandleTable[Handle].pFlash & ~(SECTORSIZE - 1)), WriteBuffer[HandleTable[Handle].WriteBufNo].BufIndex, WriteBuffer[HandleTable[Handle].WriteBufNo].Buf); + WriteBuffer[HandleTable[Handle].WriteBufNo].BufIndex = 0; + } + } + } + else + { + *pLen = 0; + } + + if (DLERROR == WriteBuffer[HandleTable[Handle].WriteBufNo].Status) + { + + /* DLERROR set due to over flow a file - EOFEXSPECTED should be set */ + /* for repeated overflow requests */ + Handle |= EOFEXSPECTED; + } + return(Handle); +} + + +UWORD dLoaderGetFreeHandle(void) +{ + UBYTE Tmp; + UWORD Handle; + + Handle = NOMOREHANDLES; + for(Tmp = 0; Tmp < MAX_HANDLES; Tmp++) + { + if (FREE == HandleTable[Tmp].Status) + { + HandleTable[Tmp].Status = BUSY; + Handle = 0; /* Clear NOMOREHANDLES */ + Handle = Tmp; + Tmp = MAX_HANDLES; + } + } + return(Handle); +} + +const UBYTE * dLoaderGetNextSectorPtr(UBYTE Handle) +{ + const UBYTE *pAdr; + + /* Check for the last entry in a sector - if so, */ + /* then this is the sector number on the next sector table */ + if (!((ULONG)(HandleTable[Handle].pSectorNo + 1) & (SECTORSIZE-1))) + { + HandleTable[Handle].pSectorNo = (const UWORD *)(((ULONG)(*(HandleTable[Handle].pSectorNo)) << SECTORSIZESHIFT) | FLASHOFFSET); + } + + /* If pointing at an illegal adr then set it to NULL */ + if (SIZEOFFLASH < (ULONG)((ULONG)(HandleTable[Handle].pSectorNo) & ~FLASHOFFSET)) + { + pAdr = NULL; + } + else + { + pAdr = (const UBYTE *)(((ULONG)(*(HandleTable[Handle].pSectorNo)) << SECTORSIZESHIFT) | FLASHOFFSET); + } + + (HandleTable[Handle].pSectorNo)++; + return(pAdr); +} + +UWORD dLoaderCloseHandle(UWORD Handle) +{ + UWORD RtnStatus; + FILEHEADER *TmpFileHeader; + + + RtnStatus = Handle; + + /* if it is a normal handle or handle closed due to an error then error must be different */ + /* from the no more handles available error (else you would delete a used handle) */ + if (((0x8000 > Handle) || (NOMOREHANDLES != (Handle & 0xFF00))) && ((UBYTE)Handle < MAX_HANDLES)) + { + Handle &= 0x00FF; + if (FREE == HandleTable[Handle].Status) + { + RtnStatus |= HANDLEALREADYCLOSED; + } + else + { + + /* Handle was NOT free - now close it */ + if (DOWNLOADING == HandleTable[Handle].Status) + { + if (DATAFILE & HandleTable[Handle].FileType) + { + + /* This is a Datafile that should be closed and this is a legal action */ + /* 1. Write the data from the writebuffer into flash */ + /* 2. Update the Datalength in the file header */ + /* This takes minimum 8 mS (2 page writes into flash) */ + + if (WriteBuffer[HandleTable[Handle].WriteBufNo].BufIndex) + { + + /* There are databytes in the writebuffer write them into flash */ + dLoaderWritePage(((ULONG)HandleTable[Handle].pFlash & ~(SECTORSIZE - 1)), WriteBuffer[HandleTable[Handle].WriteBufNo].BufIndex, WriteBuffer[HandleTable[Handle].WriteBufNo].Buf); + } + + /* Now the databuffer is free now use if for a buffer for the fileheader*/ + memcpy(WriteBuffer[HandleTable[Handle].WriteBufNo].Buf, (void const*)HandleTable[Handle].FileDlPtr, SECTORSIZE); + TmpFileHeader = (FILEHEADER *) WriteBuffer[HandleTable[Handle].WriteBufNo].Buf; + TmpFileHeader->DataSize = TmpFileHeader->FileSize - HandleTable[Handle].DataLength; + dLoaderWritePage(((ULONG)HandleTable[Handle].FileDlPtr & ~(SECTORSIZE - 1)), SECTORSIZE, WriteBuffer[HandleTable[Handle].WriteBufNo].Buf); + } + else + { + + /* This is a system file being closed now update the file pointer table if no error and complete file written */ + if ((DLERROR != WriteBuffer[HandleTable[Handle].WriteBufNo].Status) && (0 == HandleTable[Handle].DataLength)) + { + + /* no error durig download - add the file pointer to the file pointer table */ + Handle = dLoaderInsertPtrTable((const UBYTE *) HandleTable[Handle].FileDlPtr, Handle); + } + else + { + + /* an error has occured during download - now clean up the mess... */ + dLoaderUpdateSectorTable(); + FreeUserFlash = dLoaderReturnFreeFlash(); + } + } + } + if (HandleTable[Handle].WriteBufNo != FREEBUFNO) + { + WriteBuffer[HandleTable[Handle].WriteBufNo].Status = FREE; + HandleTable[Handle].WriteBufNo = FREEBUFNO; + } + HandleTable[Handle].Status = FREE; + } + } + return(RtnStatus); +} + + +UWORD dLoaderOpenRead(UBYTE *pFileName, ULONG *pLength) +{ + UWORD Handle; + UBYTE Name[16]; + const FILEHEADER *TmpHeader; + ULONG FileLength; + ULONG DataLength; + + Handle = dLoaderFind(pFileName, Name, &FileLength, &DataLength, (UBYTE)BUSY); + if (0x8000 > Handle) + { + if (FileLength) + { + TmpHeader = (FILEHEADER const *)(Files[HandleTable[Handle].FileIndex]); + HandleTable[Handle].pFlash = (const UBYTE *)TmpHeader->FileStartAdr; + HandleTable[Handle].pSectorNo = TmpHeader->FileSectorTable; + HandleTable[Handle].DataLength = TmpHeader->DataSize; + HandleTable[Handle].ReadLength = 0; + *pLength = TmpHeader->DataSize; + } + else + { + Handle = FILENOTFOUND; + } + } + return(Handle); +} + +UWORD dLoaderRead(UBYTE Handle, UBYTE *pBuffer, ULONG *pLength) +{ + UWORD ByteCnt, Status; + + Status = dLoaderCheckHandle(Handle, BUSY); + if (0x8000 > Status) + { + Status = Handle; + ByteCnt = 0; + while (ByteCnt < *pLength) + { + if (HandleTable[Handle].DataLength <= HandleTable[Handle].ReadLength) + { + *pLength = ByteCnt; + Status |= ENDOFFILE; + } + else + { + *pBuffer = *(HandleTable[Handle].pFlash); + pBuffer++; + ByteCnt++; + HandleTable[Handle].pFlash++; + HandleTable[Handle].ReadLength++; + if (!((ULONG)(HandleTable[Handle].pFlash) & (SECTORSIZE-1))) + { + HandleTable[Handle].pFlash = dLoaderGetNextSectorPtr(Handle); + } + } + } + } + return(Status); +} + +UWORD dLoaderDelete(UBYTE *pFile) +{ + UWORD LStatus; + ULONG FileLength; + ULONG DataLength; + UBYTE Name[FILENAME_LENGTH + 1]; + + LStatus = dLoaderFind(pFile, Name, &FileLength, &DataLength, (UBYTE)BUSY); + + if (!IS_LOADER_ERR(LStatus)) + { + LStatus = dLoaderDeleteFilePtr((UBYTE)LStatus); + } + + dLoaderCloseHandle(LStatus); + + return(LStatus); +} + +UWORD dLoaderFind(UBYTE *pFind, UBYTE *pFound, ULONG *pFileLength, ULONG *pDataLength, UBYTE Session) +{ + UWORD Handle; + + Handle = dLoaderGetFreeHandle(); + if (Handle < 0x8000) + { + if (FILENAME_LENGTH < strlen((const char*)pFind)) + { + Handle |= ILLEGALFILENAME; + } + else + { + HandleTable[Handle].FileIndex = 0xFFFF; + HandleTable[Handle].Status = Session; + dLoaderInsertSearchStr((HandleTable[Handle].SearchStr), pFind, &(HandleTable[Handle].SearchType)); + Handle = dLoaderFindNext(Handle, pFound, pFileLength, pDataLength); + } + } + + return(Handle); +} + +UWORD dLoaderFindNext(UWORD Handle, UBYTE *pFound, ULONG *pFileLength, ULONG *pDataLength) +{ + UBYTE Tmp; + UWORD ReturnVal; + FILEHEADER *pHeader; + + *pFileLength = 0; + ReturnVal = Handle | FILENOTFOUND; + + + for (Tmp = ((HandleTable[Handle].FileIndex) + 1); Tmp < MAX_FILES; Tmp++) + { + if (0xFFFFFFFF != Files[Tmp]) + { + if (SUCCESS == dLoaderCheckName((UBYTE*)Files[Tmp], HandleTable[Handle].SearchStr, HandleTable[Handle].SearchType)) + { + HandleTable[Handle].FileIndex = Tmp; + Tmp = MAX_FILES; + ReturnVal = Handle; + } + } + } + if (0x8000 > ReturnVal) + { + pHeader = (FILEHEADER *)Files[HandleTable[Handle].FileIndex]; + if (NULL != pFileLength) + { + *pFileLength = pHeader->FileSize; + } + if (NULL != pDataLength) + { + *pDataLength = pHeader->DataSize; + } + if (NULL != pFound) + { + dLoaderCopyFileName(pFound, (UBYTE *)pHeader->FileName); + } + } + return(ReturnVal); +} + + +ULONG dLoaderReturnFreeFlash(void) +{ + ULONG SectorCnt, IndexPtr; + UWORD Sectors; + + + Sectors = 0; + IndexPtr = (ULONG)0x01 << SECTORPOINTERUSERFLASH; /* Offset in first index can be different from 0 */ + for(SectorCnt = SECTORINDEXUSERFLASH; SectorCnt <= ((NOOFSECTORS>>5)-1); SectorCnt++) + { + for( ; IndexPtr > 0; IndexPtr<<=1) + { + if (!(SectorTable[SectorCnt] & IndexPtr)) + { + Sectors++; + } + } + IndexPtr = 0x00000001; + } + + FreeSectors = Sectors; + return(dLoaderCalcFreeFileSpace(Sectors)); +} + +ULONG dLoaderCalcFreeFileSpace(UWORD NosOfFreeSectors) +{ + UWORD SectorCnt; + ULONG Space; + ULONG HeaderSpace; + + /* Calculate only if any sectors available */ + if (NosOfFreeSectors) + { + + Space = (ULONG)NosOfFreeSectors << SECTORSIZESHIFT; + + /* (FreeSectors - 1) is beacuse the the first sector of a file do not */ + /* require an entry in the sector table - it is pointed to by the filepointer */ + /* in the file pointer table*/ + SectorCnt = NosOfFreeSectors - 1; + + /* If more that one sector is used for the header the first filebody sector do not */ + /* require an entry in the sectortable - it is pointed to by the file startpointer */ + /* in the file header */ + if ((((SectorCnt<<1) + HEADERFIXEDSIZE) & (SECTORSIZE - 1)) < 4) + { + SectorCnt--; + } + + HeaderSpace = (HEADERFIXEDSIZE + (SectorCnt << 1)); + if (HeaderSpace & 0x0003) + { + /* Header size is not a multiplum of 4 - now make it a mul 4 */ + HeaderSpace += (0x0004 - (HeaderSpace & 0x0003)); + } + Space -= HeaderSpace; + } + return(Space); +} + + +UWORD dLoaderGetFilePtr(UBYTE *pFileName, UBYTE *pPtrToFile, ULONG *pFileLength) +{ + UWORD RtnVal; + UBYTE FoundFile[16]; + FILEHEADER *File; + ULONG DataLength; + + + RtnVal = dLoaderFind(pFileName, FoundFile, pFileLength, &DataLength, (UBYTE)BUSY); + if (0x8000 > RtnVal) + { + + File = (FILEHEADER*) Files[HandleTable[RtnVal].FileIndex]; + if (LINEAR & File->FileType) + { + *((ULONG*)pPtrToFile) = File->FileStartAdr; + } + else + { + RtnVal |= NOTLINEARFILE; + } + } + return(RtnVal); +} + +UWORD dLoaderAllocateHeader(UWORD Handle, ULONG *FileStartAdr, FILEHEADER *pHeader, UWORD HeaderByteSize, UWORD CompleteFileSectorSize) +{ + UWORD Tmp; + UWORD SectorTableIndex; + ULONG SectorIndex; + UWORD HeaderSectorSize; + UBYTE EvenHeader; + UWORD FileBodySectorSize; + UWORD ErrorCode; + + HeaderSectorSize = ((HeaderByteSize - 1) >> SECTORSIZESHIFT) + 1; + FileBodySectorSize = (((pHeader->FileSize - (SECTORSIZE - (HeaderByteSize & (SECTORSIZE - 1)))) - 1) >> SECTORSIZESHIFT) + 1; + + /* First allocate the file file header - this means the file name, */ + /* the file start adress, and the sector table */ + + /* SectorTableIndex indicates in the last word of a sector in which */ + /* sector the sectortable continues */ + SectorTableIndex = ((SECTORSIZE - HEADERFIXEDSIZE)>>1) - 1; + + /* Find first free sector - here there is a differende between linear or not*/ + ErrorCode = dLoaderFindFirstSector(pHeader->FileType, CompleteFileSectorSize, &Tmp); + + if (SUCCESS == ErrorCode) + { + *FileStartAdr = (ULONG)((ULONG)Tmp << SECTORSIZESHIFT) | FLASHOFFSET; + HandleTable[Handle].FileDlPtr = *FileStartAdr; + + SectorIndex = (Tmp >> 5); + Tmp &= 0x1F; + + SectorTable[SectorIndex]|= (0x01<FileStartAdr = (ULONG)(*FileStartAdr) + HeaderByteSize; + + /* if there is a sectortable it always starts right after the fixed header (Name + start + size)*/ + HandleTable[Handle].pSectorNo = (const UWORD *)(*FileStartAdr + HEADERFIXEDSIZE); + + /* First header has been allocated by find first function */ + HeaderSectorSize--; + UWORD TmpHSS = HeaderSectorSize; + + /* Next part is only executed when more than one sector is used */ + if (HeaderSectorSize) + { + UBYTE ExitCode = FALSE; + + while ((FALSE == ExitCode) && (SectorIndex < (NOOFSECTORS/32))) + { + for(; ((Tmp < 32) && (ExitCode == FALSE)); Tmp++) + { + if (!(SectorTable[SectorIndex] & (0x01<FileSectorTable[SectorTableIndex] = (SectorIndex << 5) + Tmp; + SectorTableIndex += (SECTORSIZE/2); + HeaderSectorSize--; + if (0 == HeaderSectorSize) + { + pHeader->FileStartAdr = (((SectorIndex << 5) + Tmp) << SECTORSIZESHIFT) + (HeaderByteSize - (TmpHSS<= (SECTORSIZE - 2)) || (0 == (HeaderByteSize & (SECTORSIZE - 1)))) + { + + /* The header uses exact one or several sectors */ + /* meaning that the next sector do not go into */ + /* the sectortable as it is pointed to by the */ + /* FileStart pointer */ + EvenHeader = TRUE; + } + + /* Now allocated the file body */ + SectorTableIndex = 0; + while ((FileBodySectorSize > 0) && (SectorIndex < (NOOFSECTORS/32))) + { + for(; Tmp < 32; Tmp++) + { + if (!(SectorTable[SectorIndex] & (0x01<FileStartAdr = (((SectorIndex << 5) + Tmp) << SECTORSIZESHIFT) | FLASHOFFSET; + EvenHeader = FALSE; + } + else + { + + /* Sector is free you can have this one */ + SectorTable[SectorIndex] |= (0x01<>1)-1) == SectorTableIndex) || (((SectorTableIndex - ((SECTORSIZE - HEADERFIXEDSIZE)>>1)) & 0x7F) == 127)) + { + SectorTableIndex++; + } + pHeader->FileSectorTable[SectorTableIndex] = (SectorIndex << 5) + Tmp; + SectorTableIndex++; + FileBodySectorSize--; + if (0 == FileBodySectorSize) + { + Tmp = 32; + SectorIndex = (NOOFSECTORS/32); + } + } + } + } + SectorIndex++; + Tmp = 0; + } + } + else + { + Handle |= ErrorCode; + } + return(Handle); +} + + +UWORD dLoaderFindFirstSector(UBYTE Type, UWORD SectorCount, UWORD *pSector) +{ + UWORD CompleteSectorSize; + UWORD SectorIndex; + UBYTE Tmp; + UWORD SectorCnt; + UWORD ErrorCode; + + + ErrorCode = SUCCESS; + + SectorIndex = SECTORINDEXUSERFLASH; + Tmp = SECTORPOINTERUSERFLASH; + + + + if (LINEAR & Type) + { + CompleteSectorSize = SectorCount; + ErrorCode = NOLINEARSPACE; + + /* find linear adress space */ + SectorCnt = CompleteSectorSize; + + while ((SectorCnt > 0) && (SectorIndex < (NOOFSECTORS>>5))) + { + if ((SectorTable[SectorIndex]) & ((ULONG)0x01<>5); + ErrorCode = SUCCESS; + } + } + + if (0x1F == Tmp) + { + SectorIndex++; + } + Tmp = (Tmp + 1) & 0x1F; + } + } + else + { + ErrorCode = UNDEFINEDERROR; + while(SectorIndex < (NOOFSECTORS>>5)) + { + if (!((SectorTable[SectorIndex]) & ((ULONG)0x01<>5); + ErrorCode = SUCCESS; + } + if (0x1F == Tmp) + { + SectorIndex++; + } + Tmp = (Tmp + 1) & 0x1F; + } + } + return(ErrorCode); +} + + +UWORD dLoaderFlashFileHeader(UWORD Handle, ULONG FileStartAdr, FILEHEADER *pHeader, UWORD HeaderByteSize) +{ + ULONG *pBufPtr; + ULONG FlashPtr; + UWORD HeaderSectorSize; + + pBufPtr = (ULONG*)pHeader; + FlashPtr = FileStartAdr; + HeaderSectorSize = (HeaderByteSize - 1) >> SECTORSIZESHIFT; + + dLoaderWritePage(FlashPtr, SECTORSIZE, pBufPtr); + + while(HeaderSectorSize) + { + pBufPtr += (SECTORSIZE>>2); + FlashPtr = (((*(pBufPtr - 1) & 0xFFFF0000) >> 16) << SECTORSIZESHIFT) | FLASHOFFSET; + dLoaderWritePage(FlashPtr, SECTORSIZE, pBufPtr); + HeaderSectorSize--; + } + + /* Prepare for actual data download */ + memcpy(WriteBuffer[HandleTable[Handle].WriteBufNo].Buf, pBufPtr, SECTORSIZE); + WriteBuffer[HandleTable[Handle].WriteBufNo].BufIndex = (UWORD)(pHeader->FileStartAdr) & (SECTORSIZE-1); + HandleTable[Handle].pFlash = (UBYTE *)pHeader->FileStartAdr; + + return(Handle); +} + +UWORD dLoaderGetSectorNumber(ULONG Adr) +{ + UWORD SectorNo; + + SectorNo = (Adr & ~FLASHOFFSET)>>SECTORSIZESHIFT; + + return(SectorNo); +} + + +UWORD dLoaderAllocateWriteBuffer(UWORD Handle) +{ + UBYTE Tmp; + UWORD ErrorCode; + + ErrorCode = NOWRITEBUFFERS; + for (Tmp = 0; Tmp < MAX_WRITE_BUFFERS; Tmp++) + { + if (FREE == WriteBuffer[Tmp].Status) + { + WriteBuffer[Tmp].Status = BUSY; + memset(WriteBuffer[Tmp].Buf, 0xFF, sizeof(WriteBuffer[Tmp].Buf)); + WriteBuffer[Tmp].BufIndex = 0; + HandleTable[Handle].WriteBufNo = Tmp; + ErrorCode = SUCCESS; + Tmp = MAX_WRITE_BUFFERS; + } + } + Handle |= ErrorCode; + return(Handle); +} + +UWORD dLoaderCheckFiles(UBYTE Handle) +{ + UBYTE Tmp; + UBYTE Index; + UWORD ErrorCode; + + ErrorCode = SUCCESS; + Index = HandleTable[Handle].FileIndex; + for (Tmp = 0; Tmp < MAX_HANDLES; Tmp++) + { + if ((BUSY == HandleTable[Tmp].Status) && (Index == HandleTable[Tmp].FileIndex) && (Tmp != Handle)) + { + ErrorCode = FILEISBUSY; + } + } + return(Handle | ErrorCode); +} + +void dLoaderCopyFileName(UBYTE *pDst, UBYTE *pSrc) +{ + UBYTE Tmp; + + for(Tmp = 0; Tmp < FILENAME_SIZE; Tmp++, pDst++) + { + if ('\0' != *pSrc) + { + *pDst = *pSrc; + pSrc++; + } + else + { + *pDst = '\0'; + } + } +} + +void dLoaderCheckVersion(void) +{ + ULONG Version; + + Version = *(const ULONG*)(STARTOFFILETABLE + (MAX_FILES * 4)); + if (Version != FILEVERSION) + { + dLoaderDeleteAllFiles(); + } +} + +UWORD dLoaderOpenAppend(UBYTE *pFileName, ULONG *pAvailSize) +{ + UWORD Handle; + ULONG FileSize, DataSize; + UBYTE Name[FILENAME_SIZE]; + FILEHEADER *pHeader; + + *pAvailSize = 0; + + Handle = dLoaderFind(pFileName, Name, &FileSize, &DataSize, (UBYTE)BUSY); + if (0x8000 > Handle) + { + + /* Check for an append in progress for this file */ + if (0x8000 > dLoaderCheckDownload(pFileName)) + { + + /* File has bee found - check for then correct filetype (Datafile) */ + pHeader = (FILEHEADER *)Files[HandleTable[Handle].FileIndex]; + if (DATAFILE & pHeader->FileType) + { + if (FileSize > DataSize) + { + /* Append is possible */ + Handle = dLoaderAllocateWriteBuffer(Handle); + if (Handle < 0x8000) + { + dLoaderSetFilePointer(Handle, DataSize, &(HandleTable[Handle].pFlash)); + WriteBuffer[HandleTable[Handle].WriteBufNo].BufIndex = (ULONG)(HandleTable[Handle].pFlash) & (SECTORSIZE - 1); + memcpy(WriteBuffer[HandleTable[Handle].WriteBufNo].Buf, (const UBYTE *)((ULONG)(HandleTable[Handle].pFlash) & ~(SECTORSIZE - 1)), WriteBuffer[HandleTable[Handle].WriteBufNo].BufIndex ); + HandleTable[Handle].FileDlPtr = Files[HandleTable[Handle].FileIndex]; + HandleTable[Handle].Status = (UBYTE)DOWNLOADING; + *pAvailSize = FileSize - DataSize; + HandleTable[Handle].DataLength = *pAvailSize; + HandleTable[Handle].FileType = pHeader->FileType; + } + } + else + { + Handle |= FILEISFULL; + } + } + else + { + Handle |= APPENDNOTPOSSIBLE; + } + } + else + { + Handle |= FILEISBUSY; + } + } + + return(Handle); +} + + +UWORD dLoaderSetFilePointer(UWORD Handle, ULONG BytePtr, const UBYTE **pData) +{ + ULONG AdrOffset; + const UBYTE *Adr; + UWORD SectorNo; + UWORD Tmp; + FILEHEADER *pHeader; + + + pData = pData; + pHeader = (FILEHEADER*)Files[HandleTable[Handle].FileIndex]; + HandleTable[Handle].pSectorNo = pHeader->FileSectorTable; + + /* Get the sector offset */ + AdrOffset = SECTORSIZE - ((pHeader->FileStartAdr) & (SECTORSIZE - 1)); + + if (BytePtr > AdrOffset) + { + BytePtr = BytePtr - AdrOffset; + SectorNo = ((BytePtr >> SECTORSIZESHIFT) + 1); + + for (Tmp = 0; Tmp < SectorNo; Tmp++) + { + Adr = dLoaderGetNextSectorPtr(Handle); + if (BytePtr > SECTORSIZE) + { + BytePtr -= SECTORSIZE; + } + } + *pData = (const UBYTE *)((ULONG)Adr + BytePtr); + } + else + { + + /* Pointer reside in the first sector of the file body */ + *pData = (const UBYTE *)((ULONG)(pHeader->FileStartAdr) + BytePtr); + } + return(Handle); +} + +void dLoaderCpyToLower(UBYTE *pDst, UBYTE *pSrc, UBYTE Length) +{ + UBYTE Tmp; + + for(Tmp = 0; Tmp < Length; Tmp++) + { + pDst[Tmp] =(UBYTE)toupper((UWORD)pSrc[Tmp]); + } + + /* The requried length has been copied - now fill with zeros */ + for(Tmp = Length; Tmp < FILENAME_SIZE; Tmp++) + { + pDst[Tmp] = '\0'; + } +} + +UWORD dLoaderCheckName(UBYTE *pName, UBYTE *pSearchStr, UBYTE SearchType) +{ + UBYTE TmpName[FILENAME_SIZE]; + UWORD RtnVal; + + RtnVal = UNDEFINEDERROR; + + dLoaderCpyToLower(TmpName, pName, (UBYTE)FILENAME_SIZE); + + RtnVal = SUCCESS; + switch (SearchType) + { + case FULLNAME: + { + if (0 != strcmp((const char*)TmpName, (const char *)pSearchStr)) + { + RtnVal = UNDEFINEDERROR; + } + } + break; + case NAME: + { + if (0 != memcmp(TmpName, pSearchStr, strlen((const char *)pSearchStr))) + { + RtnVal = UNDEFINEDERROR; + } + } + break; + case EXTENTION: + { + if (0 == strstr((const char *)TmpName, (const char*)pSearchStr)) + { + RtnVal = UNDEFINEDERROR; + } + } + break; + case WILDCARD: + { + RtnVal = SUCCESS; + } + break; + default: + { + } + break; + } + return(RtnVal); +} + +void dLoaderInsertSearchStr(UBYTE *pDst, UBYTE *pSrc, UBYTE *pSearchType) +{ + UBYTE Tmp; + + *pSearchType = WILDCARD; + if (0 != strstr((char const *)pSrc, "*.*")) + { + + /* find all */ + strcpy ((PSZ)pDst, (PSZ)pSrc); + *pSearchType = WILDCARD; + } + else + { + + /* Using other wild cards? */ + Tmp = strlen((char const *)pSrc); + if (0 != strstr((PSZ)(pSrc), ".*")) + { + + /* Extention wildcard */ + dLoaderCpyToLower(pDst, pSrc, (Tmp-1)); + *pSearchType = NAME; + } + else + { + if (0 != strstr((PSZ)(pSrc), "*.")) + { + + /* Filename wildcard */ + dLoaderCpyToLower(pDst, &pSrc[1], (UBYTE)4); + *pSearchType = EXTENTION; + } + else + { + + /* no wildcards used */ + dLoaderCpyToLower(pDst, pSrc, Tmp); + *pSearchType = FULLNAME; + } + } + } +} + +UWORD dLoaderCheckHandle(UWORD Handle, UBYTE Operation) +{ + + if (MAX_HANDLES > Handle) + { + if (Operation != HandleTable[(UBYTE)Handle].Status) + { + Handle |= ILLEGALHANDLE; + } + } + else + { + Handle |= ILLEGALHANDLE; + } + return(Handle); +} + +ULONG dLoaderReturnFreeUserFlash(void) +{ + return(FreeUserFlash); +} + +UWORD dLoaderRenameFile(UBYTE Handle, UBYTE *pNewName) +{ + ULONG SectorBuf[SECTORSIZE/4]; + ULONG *pFile; + UBYTE Tmp; + FILEHEADER *pHeader; + + pFile = (ULONG *)Files[HandleTable[Handle].FileIndex]; + for (Tmp = 0; Tmp < (SECTORSIZE/4); Tmp++) + { + SectorBuf[Tmp] = pFile[Tmp]; + } + + pHeader = (FILEHEADER *) SectorBuf; + + dLoaderCopyFileName((pHeader->FileName), pNewName); + dLoaderWritePage((ULONG)pFile, SECTORSIZE, SectorBuf); + return(SUCCESS); +} + + +UWORD dLoaderCheckDownload(UBYTE *pName) +{ + UBYTE Tmp; + UWORD ErrorCode; + + ErrorCode = SUCCESS; + for(Tmp = 0; Tmp < MAX_HANDLES; Tmp ++) + { + if (DOWNLOADING == HandleTable[Tmp].Status) + { + if (SUCCESS == dLoaderCheckName(pName, HandleTable[Tmp].SearchStr, FULLNAME)) + { + Tmp = MAX_HANDLES; + ErrorCode = FILEEXISTS; + } + } + } + return(ErrorCode); +} + + +void dLoaderExit(void) +{ +} diff --git a/AT91SAM7S256/Source/d_loader.h b/AT91SAM7S256/Source/d_loader.h new file mode 100644 index 0000000..0279631 --- /dev/null +++ b/AT91SAM7S256/Source/d_loader.h @@ -0,0 +1,99 @@ +// +// Date init 14.12.2004 +// +// Revision date $Date:: 28-03-07 14:54 $ +// +// Filename $Workfile:: d_loader.h $ +// +// Version $Revision:: 40 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/d_loader.h $ +// +// Platform C +// + +#ifndef D_LOADER +#define D_LOADER + +#define STARTOFFILETABLE (0x13FF00L) +#define STARTOFUSERFLASH (0x121400L)//(0x11F000L) +#define SIZEOFUSERFLASH (STARTOFFILETABLE - STARTOFUSERFLASH) + +#define SIZEOFFLASH 262144L +#define SECTORSIZE 256L +#define SECTORSIZESHIFT 8 +#define NOOFSECTORS (SIZEOFFLASH/SECTORSIZE) +#define HEADERFIXEDSIZE (FILENAME_SIZE + 4 + 4 + 4 + 2 + 2) +#define FILENAME_SIZE (FILENAME_LENGTH + 1) + +#define FULLNAME 1 +#define NAME 2 +#define EXTENTION 3 +#define WILDCARD 4 + +/* Enum related to HandleTable Status */ +enum +{ + FREE, + BUSY, + DOWNLOADING, + SEARCHING, + DLERROR +}; + +/* Enum related to HandleTable WriteBufNo */ +enum +{ + FREEBUFNO = 0xFF +}; + + +/* Constants related to filetype */ +enum +{ + SYSTEMFILE = 0x01, + DATAFILE = 0x02, + LINEAR = 0x04, + NONLINEAR = 0x08 +}; + +typedef struct +{ + UBYTE FileName[FILENAME_SIZE]; + ULONG FileStartAdr; + ULONG FileSize; + ULONG DataSize; + UWORD CheckSum; + UWORD FileType; + UWORD FileSectorTable[SIZEOFUSERFLASH/SECTORSIZE]; +}FILEHEADER; + +void dLoaderInit(void); +__ramfunc UWORD dLoaderWritePage(ULONG Flash_Address, UWORD Size, ULONG *pBuf); +UWORD dLoaderInsertPtrTable(const UBYTE *pAdr, UWORD Handle); +UWORD dLoaderCreateFileHeader(ULONG FileSize, UBYTE *pName, UBYTE LinearState, UBYTE FileType); +UWORD dLoaderWriteData(UWORD Handle, UBYTE *pBuf, UWORD *pLen); +UWORD dLoaderCloseHandle(UWORD Handle); +UWORD dLoaderOpenRead(UBYTE *pFileName, ULONG *pLength); +UWORD dLoaderRead(UBYTE Handle, UBYTE *pBuf, ULONG *pLength); +UWORD dLoaderDelete(UBYTE *pFile); +UWORD dLoaderFind(UBYTE *pFind, UBYTE *pFound, ULONG *pFileLength, ULONG *pDataLength, UBYTE Session); +UWORD dLoaderFindNext(UWORD Handle, UBYTE *pFound, ULONG *pFileLength, ULONG *pDataLength); +UWORD dLoaderDeleteFilePtr(UWORD Handle); +void dLoaderDeleteAllFiles(void); +UWORD dLoaderGetFilePtr(UBYTE *pFileName, UBYTE *pPtrToFile, ULONG *pFileLength); +void dLoaderCopyFileName(UBYTE *pDst, UBYTE *pSrc); +UWORD dLoaderOpenAppend(UBYTE *pFileName, ULONG *pAvailSize); +void dLoaderCpyToLower(UBYTE *pDst, UBYTE *pSrc, UBYTE Length); +UWORD dLoaderCheckName(UBYTE *pName, UBYTE *pSearchStr, UBYTE SearchType); +void dLoaderInsertSearchStr(UBYTE *pDst, UBYTE *pSrc, UBYTE *pSearchType); +ULONG dLoaderReturnFreeUserFlash(void); +UWORD dLoaderRenameFile(UBYTE Handle, UBYTE *pNewName); +UWORD dLoaderCheckFiles(UBYTE Handle); + + + + +void dLoaderExit(void); + +#endif diff --git a/AT91SAM7S256/Source/d_loader.r b/AT91SAM7S256/Source/d_loader.r new file mode 100644 index 0000000..bec0c90 --- /dev/null +++ b/AT91SAM7S256/Source/d_loader.r @@ -0,0 +1,117 @@ +// +// Date init 14.12.2004 +// +// Revision date $Date:: 16-05-06 8:27 $ +// +// Filename $Workfile:: d_loader.r $ +// +// Version $Revision:: 8 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/d_loader.r $ +// +// Platform C +// + +#ifdef SAM7S256 + +#define AT91C_MC_CORRECT_KEY 0x5A000000L + +static ULONG SectorImage[SECTORSIZE>>2]; + +#define LOADERInit + + +__ramfunc UWORD AT91F_Flash_Ready (void) +{ + UWORD status; + status = 0; + + //* Wait the end of command + while ((status & AT91C_MC_FRDY) != AT91C_MC_FRDY ) + { + status = AT91C_BASE_MC->MC_FSR; + } + return status; +} + +__ramfunc UWORD dLoaderWritePage(ULONG Flash_Address, UWORD Size, ULONG *pBuf) +{ + //* set the Flash controller base address + AT91PS_MC ptMC = AT91C_BASE_MC; + unsigned int i, page, status; + unsigned int * Flash; + + //* init flash pointer + Flash = (unsigned int *) (Flash_Address | (unsigned int)AT91C_IFLASH); + + //* Get the Flash page number + page = ((Flash_Address & ~(unsigned int)AT91C_IFLASH) >> SECTORSIZESHIFT); + + //* copy the new value + if (Size & 0x0003) + { + Size = Size + (0x0004 - (Size & 0x0003)); + } + for (i=0; (i < SECTORSIZE) & (Size > 0) ;i++, Flash++,pBuf++,Size-=4 ) + { + //* copy the flash to the write buffer ensuring code generation + *Flash=*pBuf; + } + + //* Write the write page command + ptMC->MC_FCR = AT91C_MC_CORRECT_KEY | AT91C_MC_FCMD_START_PROG | (AT91C_MC_PAGEN & (page <<8)); + + //* Wait the end of command + status = AT91F_Flash_Ready(); + + //* Check the result + if ( (status & ( AT91C_MC_PROGE | AT91C_MC_LOCKE ))!=0) + { + return FALSE; + } + return TRUE; + +} + +__ramfunc UWORD dLoaderErasePage(ULONG Flash_Address) +{ + //* set the Flash controller base address + AT91PS_MC ptMC = AT91C_BASE_MC; + unsigned int i, page, status, Size; + unsigned int * Flash; + + Size = SECTORSIZE; + + //* init flash pointer + Flash = (unsigned int *) (Flash_Address | (unsigned int)AT91C_IFLASH); + + //* Get the Flash page number + page = ((Flash_Address & ~(unsigned int)AT91C_IFLASH) >> SECTORSIZESHIFT); + + //* copy the new value + for (i=0; (i < SECTORSIZE) & (Size > 0) ;i++, Flash++,Size-=4 ) + { + //* copy the flash to the write buffer ensuring code generation + *Flash=0xFFFFFFFF; + } + + //* Write the write page command + ptMC->MC_FCR = AT91C_MC_CORRECT_KEY | AT91C_MC_FCMD_START_PROG | (AT91C_MC_PAGEN & (page <<8)); + + //* Wait the end of command + status = AT91F_Flash_Ready(); + + //* Check the result + if ( (status & ( AT91C_MC_PROGE | AT91C_MC_LOCKE ))!=0) + { + return FALSE; + } + return TRUE; + +} + + + + + +#endif diff --git a/AT91SAM7S256/Source/d_lowspeed.c b/AT91SAM7S256/Source/d_lowspeed.c new file mode 100644 index 0000000..e3b5ba8 --- /dev/null +++ b/AT91SAM7S256/Source/d_lowspeed.c @@ -0,0 +1,77 @@ +// +// Date init 14.12.2004 +// +// Revision date $Date:: 16-05-06 12:13 $ +// +// Filename $Workfile:: d_lowspeed.c $ +// +// Version $Revision:: 14 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/d_lowspeed $ +// +// Platform C +// + +#include "stdconst.h" +#include "m_sched.h" +#include "d_lowspeed.h" +#include "d_lowspeed.r" + + +void dLowSpeedInit(void) +{ + LOWSpeedTxInit; + LOWSpeedTimerInit; + //ENABLEDebugOutput; +} + +void dLowSpeedStartTimer(void) +{ + ENABLEPWMTimerForLowCom; +} + +void dLowSpeedStopTimer(void) +{ + DISABLEPWMTimerForLowCom; +} + +void dLowSpeedInitPins(UBYTE ChannelNumber) +{ + ENABLETxPins(ChannelNumber); +} + +UBYTE dLowSpeedSendData(UBYTE ChannelNumber, UBYTE *DataOutBuffer, UBYTE NumberOfTxByte) +{ + UBYTE Status; + + TxData(ChannelNumber, Status, DataOutBuffer, NumberOfTxByte); + return(Status); +} + +void dLowSpeedReceiveData(UBYTE ChannelNumber, UBYTE *DataInBuffer, UBYTE ByteToRx) +{ + RxData(ChannelNumber, DataInBuffer, ByteToRx); +} + +UBYTE dLowSpeedComTxStatus(UBYTE ChannelNumber) +{ + UBYTE Status; + + STATUSTxCom(ChannelNumber, Status) + + return(Status); +} + +UBYTE dLowSpeedComRxStatus(UBYTE ChannelNumber) +{ + UBYTE Status; + + STATUSRxCom(ChannelNumber, Status) + + return(Status); +} + +void dLowSpeedExit(void) +{ + LOWSpeedExit; +} diff --git a/AT91SAM7S256/Source/d_lowspeed.h b/AT91SAM7S256/Source/d_lowspeed.h new file mode 100644 index 0000000..9a680f0 --- /dev/null +++ b/AT91SAM7S256/Source/d_lowspeed.h @@ -0,0 +1,28 @@ +// +// Date init 14.12.2004 +// +// Revision date $Date:: 16-05-06 12:13 $ +// +// Filename $Workfile:: d_lowspeed.h $ +// +// Version $Revision:: 7 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/d_lowspeed $ +// +// Platform C +// + +#ifndef D_LOWSPEED +#define D_LOWSPEED + +void dLowSpeedInit(void); +void dLowSpeedStartTimer(void); +void dLowSpeedStopTimer(void); +void dLowSpeedInitPins(UBYTE ChannelNumber); +UBYTE dLowSpeedSendData(UBYTE ChannelNumber, UBYTE *DataOutBuffer, UBYTE NumberOfTxByte); +void dLowSpeedReceiveData(UBYTE ChannelNumber, UBYTE *DataInBuffer, UBYTE ByteToRx); +UBYTE dLowSpeedComTxStatus(UBYTE ChannelNumber); +UBYTE dLowSpeedComRxStatus(UBYTE ChannelNumber); +void dLowSpeedExit(void); + +#endif diff --git a/AT91SAM7S256/Source/d_lowspeed.r b/AT91SAM7S256/Source/d_lowspeed.r new file mode 100644 index 0000000..f811193 --- /dev/null +++ b/AT91SAM7S256/Source/d_lowspeed.r @@ -0,0 +1,932 @@ +// +// Date init 14.12.2004 +// +// Revision date $Date:: 19-09-06 15:05 $ +// +// Filename $Workfile:: d_lowspeed.r $ +// +// Version $Revision:: 24 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/d_lowspeed $ +// +// Platform C +// + +#ifdef SAM7S256 + +#if defined (PROTOTYPE_PCB_3) || (PROTOTYPE_PCB_4) + +#define CHANNEL_ONE_CLK AT91C_PIO_PA23 /* PA23 is Clk */ +#define CHANNEL_ONE_DATA AT91C_PIO_PA18 /* PA18 is Data */ + +#define CHANNEL_TWO_CLK AT91C_PIO_PA28 /* PA28 is Clk */ +#define CHANNEL_TWO_DATA AT91C_PIO_PA19 /* PA19 is Data */ + +#define CHANNEL_THREE_CLK AT91C_PIO_PA29 /* PA29 is Clk */ +#define CHANNEL_THREE_DATA AT91C_PIO_PA20 /* PA20 is Data */ + +#define CHANNEL_FOUR_CLK AT91C_PIO_PA30 /* PA30 is Clk */ +#define CHANNEL_FOUR_DATA AT91C_PIO_PA2 /* PA2 is Data */ + +#else + +#define CHANNEL_ONE_CLK AT91C_PIO_PA28 /* PA28 is Clk */ +#define CHANNEL_ONE_DATA AT91C_PIO_PA20 /* PA20 is Data */ + +#endif + +typedef struct +{ + UWORD MaskBit; + UBYTE ChannelState; + UBYTE TxState; + UBYTE RxState; + UBYTE ReStartState; + UBYTE TxByteCnt; + UBYTE RxByteCnt; + UBYTE *pComOutBuffer; + UBYTE *pComInBuffer; + UBYTE AckStatus; + UBYTE RxBitCnt; + UBYTE ReStartBit; + UBYTE ComDeviceAddress; + UBYTE RxWaitCnt; +}LOWSPEEDPARAMETERS; + +static LOWSPEEDPARAMETERS LowSpeedData[4]; + +ULONG DATA_PINS[4] = {CHANNEL_ONE_DATA, CHANNEL_TWO_DATA, CHANNEL_THREE_DATA, CHANNEL_FOUR_DATA}; +ULONG CLK_PINS[4] = {CHANNEL_ONE_CLK, CHANNEL_TWO_CLK, CHANNEL_THREE_CLK, CHANNEL_FOUR_CLK}; + +#define LOWSPEED_CHANNEL1 0 +#define LOWSPEED_CHANNEL2 1 +#define LOWSPEED_CHANNEL3 2 +#define LOWSPEED_CHANNEL4 3 +#define NO_OF_LOWSPEED_COM_CHANNEL 4 + +#define MASK_BIT_8 0x80 + +#define PIO_INQ 0x04 + +//Used for variable ChannelState +#define LOWSPEED_IDLE 0x00 +#define LOWSPEED_TX_STOP_BIT 0x01 +#define LOWSPEED_TRANSMITTING 0x02 +#define LOWSPEED_RECEIVING 0x04 +#define LOWSPEED_TEST_WAIT_STATE 0x08 +#define LOWSPEED_RESTART_CONDITION 0x10 +#define LOWSPEED_WAIT_BEFORE_RX 0x20 + +//Used for variable TxState +#define TX_IDLE 0x00 +#define TX_DATA_MORE_DATA 0x01 +#define TX_DATA_CLK_HIGH 0x02 +#define TX_EVALUATE_ACK_CLK_HIGH 0x03 +#define TX_DATA_READ_ACK_CLK_LOW 0x04 +#define TX_DATA_CLK_LOW 0x05 +#define TX_ACK_EVALUATED_CLK_LOW 0x06 + +//Used for variable RxState +#define RX_IDLE 0x00 +#define RX_START_BIT_CLK_HIGH 0x01 +#define RX_DATA_CLK_HIGH 0x02 +#define RX_ACK_TX_CLK_HIGH 0x03 +#define RX_DATA_CLK_LOW 0x04 +#define RX_DONE_OR_NOT_CLK_LOW 0x05 + +//Used for variable ReStart +#define RESTART_STATE_IDLE 0x00 +#define RESTART_STATE_ONE 0x01 +#define RESTART_STATE_TWO 0x02 +#define RESTART_STATE_THREE 0x03 +#define RESTART_STATE_FOUR 0x04 +#define RESTART_STATE_FIVE 0x05 +#define RESTART_STATE_SIX 0x06 +#define RESTART_STATE_SEVEN 0x07 + +#define LOWSpeedTxInit {\ + LowSpeedData[LOWSPEED_CHANNEL1].ChannelState = 0;\ + LowSpeedData[LOWSPEED_CHANNEL2].ChannelState = 0;\ + LowSpeedData[LOWSPEED_CHANNEL3].ChannelState = 0;\ + LowSpeedData[LOWSPEED_CHANNEL4].ChannelState = 0;\ + } + +#define LOWSpeedTimerInit {\ + *AT91C_PMC_PCER = 0x400; /* Enable clock for PWM, PID10*/\ + *AT91C_PWMC_MR = 0x01; /* CLKA is output from prescaler */\ + *AT91C_PWMC_MR |= 0x600; /* Prescaler MCK divided with 64 */\ + *AT91C_PWMC_CH0_CMR = 0x06; /* Channel 0 uses MCK divided by 64 */\ + *AT91C_PWMC_CH0_CMR &= 0xFFFFFEFF; /* Left alignment on periode */\ + *AT91C_PWMC_CH0_CPRDR = 0x20; /* Set to 39 => 52uSecondes interrupt */\ + *AT91C_PWMC_IDR = AT91C_PWMC_CHID0; /* Disable interrupt for PWM output channel 0 */\ + *AT91C_AIC_IDCR = 0x400; /* Disable AIC intterupt on ID10 PWM */\ + AT91C_AIC_SVR[10] = (unsigned int)LowSpeedPwmIrqHandler;\ + AT91C_AIC_SMR[10] = 0x01; /* Enable trigger on level */\ + *AT91C_AIC_ICCR = 0x400; /* Clear interrupt register PID10*/\ + *AT91C_PWMC_IER = AT91C_PWMC_CHID0; /* Enable interrupt for PWM output channel 0 */\ + *AT91C_AIC_IECR = 0x400; /* Enable interrupt from PWM */\ + } + +#define LOWSpeedExit + +#define ENABLEDebugOutput {\ + *AT91C_PIOA_PER = AT91C_PIO_PA29; /* Enable PIO on PA029 */\ + *AT91C_PIOA_OER = AT91C_PIO_PA29; /* PA029 set to Output */\ + *AT91C_PIOA_CODR = 0x20000000;\ + } + +#define SETDebugOutputHigh *AT91C_PIOA_SODR = 0x20000000 + +#define SETDebugOutputLow *AT91C_PIOA_CODR = 0x20000000 + + +#define SETClkComOneHigh *AT91C_PIOA_SODR = CHANNEL_ONE_CLK + +#define SETClkComOneLow *AT91C_PIOA_CODR = CHANNEL_ONE_CLK + +#define GetClkComOnePinLevel *AT91C_PIOA_PDSR & CHANNEL_ONE_CLK + +#define SETClkComTwoHigh *AT91C_PIOA_SODR = CHANNEL_TWO_CLK + +#define SETClkComTwoLow *AT91C_PIOA_CODR = CHANNEL_TWO_CLK + +#define GetClkComTwoPinLevel *AT91C_PIOA_PDSR & CHANNEL_TWO_CLK + +#define SETClkComThreeHigh *AT91C_PIOA_SODR = CHANNEL_THREE_CLK + +#define SETClkComThreeLow *AT91C_PIOA_CODR = CHANNEL_THREE_CLK + +#define GetClkComThreePinLevel *AT91C_PIOA_PDSR & CHANNEL_THREE_CLK + +#define SETClkComFourHigh *AT91C_PIOA_SODR = CHANNEL_FOUR_CLK + +#define SETClkComFourLow *AT91C_PIOA_CODR = CHANNEL_FOUR_CLK + +#define GetClkComFourPinLevel *AT91C_PIOA_PDSR & CHANNEL_FOUR_CLK + + +#define SETDataComOneHigh *AT91C_PIOA_SODR = CHANNEL_ONE_DATA + +#define SETDataComOneLow *AT91C_PIOA_CODR = CHANNEL_ONE_DATA + +#define GetDataComOnePinLevel *AT91C_PIOA_PDSR & CHANNEL_ONE_DATA + +#define GETDataComOnePinDirection *AT91C_PIOA_OSR & CHANNEL_ONE_DATA + +#define SETDataComTwoHigh *AT91C_PIOA_SODR = CHANNEL_TWO_DATA + +#define SETDataComTwoLow *AT91C_PIOA_CODR = CHANNEL_TWO_DATA + +#define GetDataComTwoPinLevel *AT91C_PIOA_PDSR & CHANNEL_TWO_DATA + +#define GETDataComTwoPinDirection *AT91C_PIOA_OSR & CHANNEL_TWO_DATA + +#define SETDataComThreeHigh *AT91C_PIOA_SODR = CHANNEL_THREE_DATA + +#define SETDataComThreeLow *AT91C_PIOA_CODR = CHANNEL_THREE_DATA + +#define GetDataComThreePinLevel *AT91C_PIOA_PDSR & CHANNEL_THREE_DATA + +#define GETDataComThreePinDirection *AT91C_PIOA_OSR & CHANNEL_THREE_DATA + +#define SETDataComFourHigh *AT91C_PIOA_SODR = CHANNEL_FOUR_DATA + +#define SETDataComFourLow *AT91C_PIOA_CODR = CHANNEL_FOUR_DATA + +#define GetDataComFourPinLevel *AT91C_PIOA_PDSR & CHANNEL_FOUR_DATA + +#define GETDataComFourPinDirection *AT91C_PIOA_OSR & CHANNEL_FOUR_DATA + +#define SETDataComOneToInput *AT91C_PIOA_ODR = CHANNEL_ONE_DATA; + +#define SETDataComOneToOutput *AT91C_PIOA_OER = CHANNEL_ONE_DATA; + +#define SETDataComTwoToInput *AT91C_PIOA_ODR = CHANNEL_TWO_DATA; + +#define SETDataComTwoToOutput *AT91C_PIOA_OER = CHANNEL_TWO_DATA; + +#define SETDataComThreeToInput *AT91C_PIOA_ODR = CHANNEL_THREE_DATA; + +#define SETDataComThreeToOutput *AT91C_PIOA_OER = CHANNEL_THREE_DATA; + +#define SETDataComFourToInput *AT91C_PIOA_ODR = CHANNEL_FOUR_DATA; + +#define SETDataComFourToOutput *AT91C_PIOA_OER = CHANNEL_FOUR_DATA; + +#define DISABLEPullupDataComOne *AT91C_PIOA_PPUDR = CHANNEL_ONE_DATA; + +#define DISABLEPullupClkComOne *AT91C_PIOA_PPUDR = CHANNEL_ONE_CLK; + +#define DISABLEPullupDataComTwo *AT91C_PIOA_PPUDR = CHANNEL_TWO_DATA; + +#define DISABLEPullupClkComTwo *AT91C_PIOA_PPUDR = CHANNEL_TWO_CLK; + +#define DISABLEPullupDataComThree *AT91C_PIOA_PPUDR = CHANNEL_THREE_DATA; + +#define DISABLEPullupClkComThree *AT91C_PIOA_PPUDR = CHANNEL_THREE_CLK; + +#define DISABLEPullupDataComFour *AT91C_PIOA_PPUDR = CHANNEL_FOUR_DATA; + +#define DISABLEPullupClkComFour *AT91C_PIOA_PPUDR = CHANNEL_FOUR_CLK; + +#define ENABLEPullupDataComOne *AT91C_PIOA_PPUER = CHANNEL_ONE_DATA; + +#define ENABLEPullupClkComOne *AT91C_PIOA_PPUER = CHANNEL_ONE_CLK; + +#define ENABLEPullupDataComTwo *AT91C_PIOA_PPUER = CHANNEL_TWO_DATA; + +#define ENABLEPullupClkComTwo *AT91C_PIOA_PPUER = CHANNEL_TWO_CLK; + +#define ENABLEPullupDataComThree *AT91C_PIOA_PPUER = CHANNEL_THREE_DATA; + +#define ENABLEPullupClkComThree *AT91C_PIOA_PPUER = CHANNEL_THREE_CLK; + +#define ENABLEPullupDataComFour *AT91C_PIOA_PPUER = CHANNEL_FOUR_DATA; + +#define ENABLEPullupClkComFour *AT91C_PIOA_PPUER = CHANNEL_FOUR_CLK; + +#define SETClkLow(ChannelNr) {\ + if (ChannelNr == 0)\ + {\ + SETClkComOneLow;\ + }\ + else\ + {\ + if (ChannelNr == 1)\ + {\ + SETClkComTwoLow;\ + }\ + else\ + {\ + if (ChannelNr == 2)\ + {\ + SETClkComThreeLow;\ + }\ + else\ + {\ + if (ChannelNr == 3)\ + {\ + SETClkComFourLow;\ + }\ + }\ + }\ + }\ + } + + +#define SETClkHigh(ChannelNr) {\ + if (ChannelNr == 0)\ + {\ + SETClkComOneHigh;\ + }\ + else\ + {\ + if (ChannelNr == 1)\ + {\ + SETClkComTwoHigh;\ + }\ + else\ + {\ + if (ChannelNr == 2)\ + {\ + SETClkComThreeHigh;\ + }\ + else\ + {\ + if (ChannelNr == 3)\ + {\ + SETClkComFourHigh;\ + }\ + }\ + }\ + }\ + } + +#define SETDataLow(ChannelNr) {\ + if (ChannelNr == 0)\ + {\ + SETDataComOneLow;\ + }\ + else\ + {\ + if (ChannelNr == 1)\ + {\ + SETDataComTwoLow;\ + }\ + else\ + {\ + if (ChannelNr == 2)\ + {\ + SETDataComThreeLow;\ + }\ + else\ + {\ + if (ChannelNr == 3)\ + {\ + SETDataComFourLow;\ + }\ + }\ + }\ + }\ + } + +#define SETDataHigh(ChannelNr) {\ + if (ChannelNr == 0)\ + {\ + SETDataComOneHigh;\ + }\ + else\ + {\ + if (ChannelNr == 1)\ + {\ + SETDataComTwoHigh;\ + }\ + else\ + {\ + if (ChannelNr == 2)\ + {\ + SETDataComThreeHigh;\ + }\ + else\ + {\ + if (ChannelNr == 3)\ + {\ + SETDataComFourHigh;\ + }\ + }\ + }\ + }\ + } + +#define SETDataToInput(ChannelNr) {\ + if (ChannelNr == 0)\ + {\ + SETDataComOneToInput;\ + }\ + else\ + {\ + if (ChannelNr == 1)\ + {\ + SETDataComTwoToInput;\ + }\ + else\ + {\ + if (ChannelNr == 2)\ + {\ + SETDataComThreeToInput;\ + }\ + else\ + {\ + if (ChannelNr == 3)\ + {\ + SETDataComFourToInput;\ + }\ + }\ + }\ + }\ + } + + +#define SETDataToOutput(ChannelNr) {\ + if (ChannelNr == 0)\ + {\ + SETDataComOneToOutput;\ + }\ + else\ + {\ + if (ChannelNr == 1)\ + {\ + SETDataComTwoToOutput;\ + }\ + else\ + {\ + if (ChannelNr == 2)\ + {\ + SETDataComThreeToOutput;\ + }\ + else\ + {\ + if (ChannelNr == 3)\ + {\ + SETDataComFourToOutput;\ + }\ + }\ + }\ + }\ + } + + +#define ENABLEPWMTimerForLowCom {\ + *AT91C_PWMC_ENA = AT91C_PWMC_CHID0; /* Enable PWM output channel 0 */\ + } + +#define DISABLEPWMTimerForLowCom {\ + *AT91C_PWMC_DIS = AT91C_PWMC_CHID0; /* Disable PWM output channel 0 */\ + } + +#define OLD_DISABLEPWMTimerForLowCom {\ + *AT91C_PWMC_DIS = AT91C_PWMC_CHID0; /* Disable PWM output channel 0 */\ + *AT91C_PWMC_IDR = AT91C_PWMC_CHID0; /* Disable interrupt from PWM output channel 0 */\ + *AT91C_AIC_IDCR = 0x400; /* Disable Irq from PID10 */\ + *AT91C_AIC_ICCR = 0x400; /* Clear interrupt register PID10*/\ + *AT91C_PMC_PCDR = 0x400; /* Disable clock for PWM, PID10*/\ + } + +__ramfunc void LowSpeedPwmIrqHandler(void) +{ + ULONG TestVar; + ULONG PinStatus; + UBYTE ChannelNr; + + TestVar = *AT91C_PWMC_ISR; + TestVar = TestVar; + PinStatus = *AT91C_PIOA_PDSR; + + for (ChannelNr = 0; ChannelNr < NO_OF_LOWSPEED_COM_CHANNEL; ChannelNr++) + { + switch(LowSpeedData[ChannelNr].ChannelState) + { + case LOWSPEED_IDLE: + { + } + break; + + case LOWSPEED_TX_STOP_BIT: + { + SETDataHigh(ChannelNr); + LowSpeedData[ChannelNr].ChannelState = LOWSPEED_IDLE; //Now we have send a STOP sequence, disable this channel + } + break; + + case LOWSPEED_TRANSMITTING: + { + switch(LowSpeedData[ChannelNr].TxState) + { + case TX_DATA_MORE_DATA: + { + PinStatus |= CLK_PINS[ChannelNr]; + LowSpeedData[ChannelNr].TxState = TX_DATA_CLK_HIGH; + } + break; + + case TX_DATA_CLK_HIGH: + { + SETClkLow(ChannelNr); + if (LowSpeedData[ChannelNr].MaskBit == 0) //Is Byte Done, then we need a ack from receiver + { + SETDataToInput(ChannelNr); //Set datapin to input + LowSpeedData[ChannelNr].TxState = TX_DATA_READ_ACK_CLK_LOW; + } + else + { + if (*LowSpeedData[ChannelNr].pComOutBuffer & LowSpeedData[ChannelNr].MaskBit) //Setup data pin in relation to the data + { + SETDataHigh(ChannelNr); //Set data output high + } + else + { + SETDataLow(ChannelNr); //Set data output low + } + LowSpeedData[ChannelNr].TxState = TX_DATA_CLK_LOW; + } + } + break; + + case TX_EVALUATE_ACK_CLK_HIGH: + { + SETClkLow(ChannelNr); + if (LowSpeedData[ChannelNr].AckStatus == 1) + { + LowSpeedData[ChannelNr].TxByteCnt--; + if (LowSpeedData[ChannelNr].TxByteCnt > 0) //Here initialise to send next byte + { + LowSpeedData[ChannelNr].MaskBit = MASK_BIT_8; + LowSpeedData[ChannelNr].pComOutBuffer++; + } + LowSpeedData[ChannelNr].TxState = TX_ACK_EVALUATED_CLK_LOW; //Received ack, now make a stop sequence or send next byte + } + else + { //Data communication error ! + LowSpeedData[ChannelNr].TxByteCnt = 0; + SETClkHigh(ChannelNr); + LowSpeedData[ChannelNr].ChannelState = LOWSPEED_TX_STOP_BIT; //Received ack, now make a stop sequence or send next byte. + } + } + break; + + case TX_DATA_READ_ACK_CLK_LOW: + { + if (!(PinStatus & DATA_PINS[ChannelNr])) + { + LowSpeedData[ChannelNr].AckStatus = 1; //Read ack signal from receiver + } + SETDataToOutput(ChannelNr); + SETDataLow(ChannelNr); + LowSpeedData[ChannelNr].TxState = TX_EVALUATE_ACK_CLK_HIGH; + SETClkHigh(ChannelNr); + } + break; + + case TX_DATA_CLK_LOW: + { + LowSpeedData[ChannelNr].MaskBit = LowSpeedData[ChannelNr].MaskBit >> 1; //Get ready for the next bit which should be clk out next time + SETClkHigh(ChannelNr); //Clk goes high = The reciever reads the data + LowSpeedData[ChannelNr].TxState = TX_DATA_CLK_HIGH; + } + break; + + case TX_ACK_EVALUATED_CLK_LOW: + { + if (LowSpeedData[ChannelNr].MaskBit != 0) + { + LowSpeedData[ChannelNr].TxState = TX_DATA_MORE_DATA; + } + else + { + if (LowSpeedData[ChannelNr].ReStartBit != 0) + { + LowSpeedData[ChannelNr].ChannelState = LOWSPEED_RESTART_CONDITION; + LowSpeedData[ChannelNr].ReStartState = RESTART_STATE_ONE; + SETDataLow(ChannelNr); + SETClkHigh(ChannelNr); //Clk goes high = The reciever reads the data + } + else + { + if (LowSpeedData[ChannelNr].RxByteCnt != 0) + { + LowSpeedData[ChannelNr].ChannelState = LOWSPEED_WAIT_BEFORE_RX; + } + else + { + LowSpeedData[ChannelNr].ChannelState = LOWSPEED_TX_STOP_BIT; + SETClkHigh(ChannelNr); //Clk goes high = The reciever reads the data + } + } + LowSpeedData[ChannelNr].TxState = TX_IDLE; + } + } + break; + } + } + break; + + case LOWSPEED_RESTART_CONDITION: + { + switch(LowSpeedData[ChannelNr].ReStartState) + { + case RESTART_STATE_ONE: + { + LowSpeedData[ChannelNr].ReStartState = RESTART_STATE_TWO; + } + break; + + case RESTART_STATE_TWO: + { + SETDataHigh(ChannelNr); + LowSpeedData[ChannelNr].ReStartState = RESTART_STATE_THREE; + } + break; + + case RESTART_STATE_THREE: + { + SETClkLow(ChannelNr); + LowSpeedData[ChannelNr].ReStartState = RESTART_STATE_FOUR; + } + break; + + case RESTART_STATE_FOUR: + { + SETClkHigh(ChannelNr); + LowSpeedData[ChannelNr].ReStartState = RESTART_STATE_FIVE; + } + break; + + case RESTART_STATE_FIVE: + { + SETDataLow(ChannelNr); + LowSpeedData[ChannelNr].ReStartState = RESTART_STATE_SIX; + } + break; + + case RESTART_STATE_SIX: + { + LowSpeedData[ChannelNr].ReStartState = RESTART_STATE_SEVEN; + } + break; + + case RESTART_STATE_SEVEN: + { + SETClkLow(ChannelNr); + LowSpeedData[ChannelNr].ReStartState = RESTART_STATE_IDLE; + LowSpeedData[ChannelNr].ReStartBit = 0; + LowSpeedData[ChannelNr].pComOutBuffer = &LowSpeedData[ChannelNr].ComDeviceAddress; + *LowSpeedData[ChannelNr].pComOutBuffer += 0x01; + LowSpeedData[ChannelNr].ChannelState = LOWSPEED_TRANSMITTING; + LowSpeedData[ChannelNr].MaskBit = MASK_BIT_8; + LowSpeedData[ChannelNr].TxByteCnt = 0x01; + LowSpeedData[ChannelNr].TxState = TX_DATA_CLK_HIGH; + LowSpeedData[ChannelNr].AckStatus = 0; + } + break; + } + } + break; + + case LOWSPEED_WAIT_BEFORE_RX: + { + LowSpeedData[ChannelNr].RxWaitCnt++; + if (LowSpeedData[ChannelNr].RxWaitCnt > 5) + { + LowSpeedData[ChannelNr].ChannelState = LOWSPEED_RECEIVING; + SETDataToInput(ChannelNr); + } + } + break; + + case LOWSPEED_RECEIVING: + { + switch(LowSpeedData[ChannelNr].RxState) + { + case RX_START_BIT_CLK_HIGH: + { + SETClkLow(ChannelNr); + LowSpeedData[ChannelNr].RxState = RX_DATA_CLK_LOW; + } + break; + + case RX_DATA_CLK_HIGH: + { + LowSpeedData[ChannelNr].RxBitCnt++; + if(PinStatus & DATA_PINS[ChannelNr]) + { + *LowSpeedData[ChannelNr].pComInBuffer |= 0x01; + } + SETClkLow(ChannelNr); + if (LowSpeedData[ChannelNr].RxBitCnt < 8) + { + *LowSpeedData[ChannelNr].pComInBuffer = *LowSpeedData[ChannelNr].pComInBuffer << 1; + } + else + { + if (LowSpeedData[ChannelNr].RxByteCnt > 1) + { + SETDataToOutput(ChannelNr); + SETDataLow(ChannelNr); + } + } + LowSpeedData[ChannelNr].RxState = RX_DATA_CLK_LOW; + } + break; + + case RX_ACK_TX_CLK_HIGH: + { + SETClkLow(ChannelNr); + SETDataToInput(ChannelNr); + LowSpeedData[ChannelNr].pComInBuffer++; + LowSpeedData[ChannelNr].RxByteCnt--; + LowSpeedData[ChannelNr].RxBitCnt = 0; + LowSpeedData[ChannelNr].RxState = RX_DONE_OR_NOT_CLK_LOW; + } + break; + + case RX_DATA_CLK_LOW: + { + SETClkHigh(ChannelNr); + if (LowSpeedData[ChannelNr].RxBitCnt == 8) + { + LowSpeedData[ChannelNr].RxState = RX_ACK_TX_CLK_HIGH; + } + else + { + LowSpeedData[ChannelNr].RxState = RX_DATA_CLK_HIGH; + } + } + break; + + case RX_DONE_OR_NOT_CLK_LOW: + { + if (LowSpeedData[ChannelNr].RxByteCnt == 0) + { + LowSpeedData[ChannelNr].ChannelState = LOWSPEED_IDLE; + LowSpeedData[ChannelNr].RxState = RX_IDLE; + SETClkHigh(ChannelNr); + } + else + { + LowSpeedData[ChannelNr].RxState = RX_START_BIT_CLK_HIGH; + } + } + break; + } + } + break; + + default: + break; + } + } +} + + +#define ENABLETxPins(ChannelNumber) {\ + if (ChannelNumber == LOWSPEED_CHANNEL1)\ + {\ + *AT91C_PIOA_PER = CHANNEL_ONE_CLK | CHANNEL_ONE_DATA; /* Enable PIO on PA20 & PA28 */\ + *AT91C_PIOA_PPUDR = CHANNEL_ONE_CLK | CHANNEL_ONE_DATA; /* Disable Pull-up resistor */\ + *AT91C_PIOA_ODR = CHANNEL_ONE_CLK | CHANNEL_ONE_DATA; /* PA20 & PA28 set to Input */\ + }\ + if (ChannelNumber == LOWSPEED_CHANNEL2)\ + {\ + *AT91C_PIOA_PER = CHANNEL_TWO_CLK | CHANNEL_TWO_DATA; /* Enable PIO on PA20 & PA28 */\ + *AT91C_PIOA_PPUDR = CHANNEL_TWO_CLK | CHANNEL_TWO_DATA; /* Disable Pull-up resistor */\ + *AT91C_PIOA_ODR = CHANNEL_TWO_CLK | CHANNEL_TWO_DATA; /* PA20 & PA28 set to Input */\ + }\ + if (ChannelNumber == LOWSPEED_CHANNEL3)\ + {\ + *AT91C_PIOA_PER = CHANNEL_THREE_CLK | CHANNEL_THREE_DATA; /* */\ + *AT91C_PIOA_PPUDR = CHANNEL_THREE_CLK | CHANNEL_THREE_DATA; /* */\ + *AT91C_PIOA_ODR = CHANNEL_THREE_CLK | CHANNEL_THREE_DATA; /* */\ + }\ + if (ChannelNumber == LOWSPEED_CHANNEL4)\ + {\ + *AT91C_PIOA_PER = CHANNEL_FOUR_CLK | CHANNEL_FOUR_DATA; /* */\ + *AT91C_PIOA_PPUDR = CHANNEL_FOUR_CLK | CHANNEL_FOUR_DATA; /* */\ + *AT91C_PIOA_ODR = CHANNEL_FOUR_CLK | CHANNEL_FOUR_DATA; /* */\ + }\ + } + +#define TxData(ChannelNumber, Status, DataOutBuffer, NumberOfByte) {\ + if (ChannelNumber == LOWSPEED_CHANNEL1)\ + {\ + if (GetDataComOnePinLevel && GetClkComOnePinLevel)\ + {\ + *AT91C_PIOA_PER = CHANNEL_ONE_CLK | CHANNEL_ONE_DATA; /* Enable PIO on PA20 & PA28 */\ + *AT91C_PIOA_OER = CHANNEL_ONE_CLK | CHANNEL_ONE_DATA; /* PA20 & PA28 set to Output */\ + *AT91C_PIOA_PPUDR = CHANNEL_ONE_CLK | CHANNEL_ONE_DATA; /* Disable Pull-up resistor */\ + SETClkComOneHigh;\ + LowSpeedData[LOWSPEED_CHANNEL1].pComOutBuffer = DataOutBuffer;\ + LowSpeedData[LOWSPEED_CHANNEL1].ComDeviceAddress = *LowSpeedData[LOWSPEED_CHANNEL1].pComOutBuffer;\ + LowSpeedData[LOWSPEED_CHANNEL1].MaskBit = MASK_BIT_8;\ + LowSpeedData[LOWSPEED_CHANNEL1].TxByteCnt = NumberOfByte;\ + LowSpeedData[LOWSPEED_CHANNEL1].ChannelState = LOWSPEED_TRANSMITTING;\ + LowSpeedData[LOWSPEED_CHANNEL1].TxState = TX_DATA_CLK_HIGH;\ + SETDataComOneLow;\ + LowSpeedData[LOWSPEED_CHANNEL1].AckStatus = 0;\ + Status = 1;\ + }\ + else\ + {\ + Status = 0;\ + }\ + }\ + if (ChannelNumber == LOWSPEED_CHANNEL2)\ + {\ + if (GetDataComTwoPinLevel && GetClkComTwoPinLevel)\ + {\ + *AT91C_PIOA_PER = CHANNEL_TWO_CLK | CHANNEL_TWO_DATA; /* Enable PIO on PA20 & PA28 */\ + *AT91C_PIOA_OER = CHANNEL_TWO_CLK | CHANNEL_TWO_DATA; /* PA20 & PA28 set to Output */\ + *AT91C_PIOA_PPUDR = CHANNEL_TWO_CLK | CHANNEL_TWO_DATA; /* Disable Pull-up resistor */\ + SETClkComTwoHigh;\ + LowSpeedData[LOWSPEED_CHANNEL2].pComOutBuffer = DataOutBuffer;\ + LowSpeedData[LOWSPEED_CHANNEL2].ComDeviceAddress = *LowSpeedData[LOWSPEED_CHANNEL2].pComOutBuffer;\ + LowSpeedData[LOWSPEED_CHANNEL2].MaskBit = MASK_BIT_8;\ + LowSpeedData[LOWSPEED_CHANNEL2].TxByteCnt = NumberOfByte;\ + LowSpeedData[LOWSPEED_CHANNEL2].ChannelState = LOWSPEED_TRANSMITTING;\ + LowSpeedData[LOWSPEED_CHANNEL2].TxState = TX_DATA_CLK_HIGH;\ + SETDataComTwoLow;\ + LowSpeedData[LOWSPEED_CHANNEL2].AckStatus = 0;\ + Status = 1;\ + }\ + else\ + {\ + Status = 0;\ + }\ + }\ + if (ChannelNumber == LOWSPEED_CHANNEL3)\ + {\ + if (GetDataComThreePinLevel && GetClkComThreePinLevel)\ + {\ + *AT91C_PIOA_PER = CHANNEL_THREE_CLK | CHANNEL_THREE_DATA; /* */\ + *AT91C_PIOA_OER = CHANNEL_THREE_CLK | CHANNEL_THREE_DATA; /* */\ + *AT91C_PIOA_PPUDR = CHANNEL_THREE_CLK | CHANNEL_THREE_DATA; /* */\ + SETClkComThreeHigh;\ + LowSpeedData[LOWSPEED_CHANNEL3].pComOutBuffer = DataOutBuffer;\ + LowSpeedData[LOWSPEED_CHANNEL3].ComDeviceAddress = *LowSpeedData[LOWSPEED_CHANNEL3].pComOutBuffer;\ + LowSpeedData[LOWSPEED_CHANNEL3].MaskBit = MASK_BIT_8;\ + LowSpeedData[LOWSPEED_CHANNEL3].TxByteCnt = NumberOfByte;\ + LowSpeedData[LOWSPEED_CHANNEL3].ChannelState = LOWSPEED_TRANSMITTING;\ + LowSpeedData[LOWSPEED_CHANNEL3].TxState = TX_DATA_CLK_HIGH;\ + SETDataComThreeLow;\ + LowSpeedData[LOWSPEED_CHANNEL3].AckStatus = 0;\ + Status = 1;\ + }\ + else\ + {\ + Status = 0;\ + }\ + }\ + if (ChannelNumber == LOWSPEED_CHANNEL4)\ + {\ + if (GetDataComFourPinLevel && GetClkComFourPinLevel)\ + {\ + *AT91C_PIOA_PER = CHANNEL_FOUR_CLK | CHANNEL_FOUR_DATA; /* */\ + *AT91C_PIOA_OER = CHANNEL_FOUR_CLK | CHANNEL_FOUR_DATA; /* */\ + *AT91C_PIOA_PPUDR = CHANNEL_FOUR_CLK | CHANNEL_FOUR_DATA; /* */\ + SETClkComFourHigh;\ + LowSpeedData[LOWSPEED_CHANNEL4].pComOutBuffer = DataOutBuffer;\ + LowSpeedData[LOWSPEED_CHANNEL4].ComDeviceAddress = *LowSpeedData[LOWSPEED_CHANNEL4].pComOutBuffer;\ + LowSpeedData[LOWSPEED_CHANNEL4].MaskBit = MASK_BIT_8;\ + LowSpeedData[LOWSPEED_CHANNEL4].TxByteCnt = NumberOfByte;\ + LowSpeedData[LOWSPEED_CHANNEL4].ChannelState = LOWSPEED_TRANSMITTING;\ + LowSpeedData[LOWSPEED_CHANNEL4].TxState = TX_DATA_CLK_HIGH;\ + SETDataComFourLow;\ + LowSpeedData[LOWSPEED_CHANNEL4].AckStatus = 0;\ + Status = 1;\ + }\ + else\ + {\ + Status = 0;\ + }\ + }\ + } + +#define RxData(ChannelNumber, DataInBuffer, RxBytes) {\ + LowSpeedData[ChannelNumber].pComInBuffer = DataInBuffer;\ + LowSpeedData[ChannelNumber].RxBitCnt = 0;\ + LowSpeedData[ChannelNumber].RxByteCnt = RxBytes;\ + LowSpeedData[ChannelNumber].RxState = RX_DATA_CLK_LOW;\ + LowSpeedData[ChannelNumber].ReStartBit = 1;\ + LowSpeedData[ChannelNumber].RxWaitCnt = 0;\ + } + + +#define STATUSTxCom(ChannelNumber, Status) {\ + if (LowSpeedData[ChannelNumber].ChannelState != 0)\ + {\ + if (LowSpeedData[ChannelNumber].TxByteCnt == 0)\ + {\ + if (LowSpeedData[ChannelNumber].MaskBit == 0)\ + {\ + if (LowSpeedData[ChannelNumber].AckStatus == 1)\ + {\ + Status = 0x01; /* TX SUCCESS */\ + }\ + else\ + {\ + Status = 0xFF; /* TX ERROR */\ + }\ + }\ + else\ + {\ + Status = 0;\ + }\ + }\ + else\ + {\ + Status = 0;\ + }\ + }\ + else\ + {\ + if (LowSpeedData[ChannelNumber].RxByteCnt == 0)\ + {\ + if (LowSpeedData[ChannelNumber].AckStatus == 1)\ + {\ + Status = 0x01; /* TX SUCCESS */\ + }\ + else\ + {\ + Status = 0xFF; /* TX ERROR */\ + }\ + }\ + else\ + {\ + Status = 0xFF; /* TX ERROR */\ + }\ + }\ + } + +#define STATUSRxCom(ChannelNumber, Status) {\ + if (LowSpeedData[ChannelNumber].ChannelState == LOWSPEED_IDLE)\ + {\ + if (LowSpeedData[ChannelNumber].RxByteCnt == 0)\ + {\ + Status = 0x01; /* RX SUCCESS */\ + }\ + else\ + {\ + Status = 0xFF; /* RX ERROR */\ + }\ + }\ + else\ + {\ + Status = 0;\ + }\ + } + + +#endif + +#ifdef PCWIN + +#endif diff --git a/AT91SAM7S256/Source/d_output.c b/AT91SAM7S256/Source/d_output.c new file mode 100644 index 0000000..e542cf6 --- /dev/null +++ b/AT91SAM7S256/Source/d_output.c @@ -0,0 +1,1605 @@ +// +// Date init 14.12.2004 +// +// Revision date $Date:: 5-02-07 13:48 $ +// +// Filename $Workfile:: d_output.c $ +// +// Version $Revision:: 118 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/d_output.c $ +// +// Platform C +// + +#include "stdconst.h" +#include "m_sched.h" +#include "d_output.h" +#include "d_output.r" + +#define MAXIMUM_SPEED_FW 100 +#define MAXIMUM_SPEED_RW -100 + +#define INPUT_SCALE_FACTOR 100 + +#define MAX_COUNT_TO_RUN 10000000 + +#define REG_MAX_VALUE 100 +#define REG_MIN_VALUE -100 + +#define RAMP_TIME_INTERVAL 25 // Measured in 1 mS => 25 mS interval +#define REGULATION_TIME 100 // Measured in 1 mS => 100 mS regulation interval + +#define RAMPDOWN_STATE_RAMPDOWN 0 +#define RAMPDOWN_STATE_CONTINIUE 1 + +#define COAST_MOTOR_MODE 0 + +void dOutputRampDownSynch(UBYTE MotorNr); + +typedef struct +{ + SBYTE MotorSetSpeed; // Motor setpoint in speed + SBYTE MotorTargetSpeed; // Speed order for the movement + SBYTE MotorActualSpeed; // Actual speed for motor (Calculated within the PID regulation) + SBYTE TurnParameter; // Tell the turning parameter used + UBYTE RegPParameter; // Current P parameter used within the regulation + UBYTE RegIParameter; // Current I parameter used within the regulation + UBYTE RegDParameter; // Current D parameter used within the regulation + UBYTE RegulationTimeCount; // Time counter used to evaluate when the regulation should run again (100 mS) + UBYTE MotorRunState; // Hold current motor state (Ramp-up, Running, Ramp-Down, Idle) + UBYTE RegulationMode; // Hold current regulation mode (Position control, Synchronization mode) + UBYTE MotorOverloaded; // Set if the motor speed in regulation is calculated to be above maximum + UBYTE MotorRunForever; // Tell that the motor is set to run forever + UWORD MotorRampDownCount; // Counter to tell if the ramp-down can reach it gaol and therefor need some additional help + SWORD MotorRampDownIncrement; // Tell the number of count between each speed adjustment during Ramp-Down + UWORD MotorRampUpCount; // Used to speedup Ramp-Up if position regulation is not enabled + SWORD MotorRampUpIncrement; // Tell the number of count between each speed adjustment during Ramp-up + SWORD AccError; // Accumulated Error, used within the integrator of the PID regulation + SWORD OldPositionError; // Used within position regulation + SLONG DeltaCaptureCount; // Counts within last regulation time-periode + SLONG CurrentCaptureCount; // Total counts since motor counts has been reset + SLONG MotorTachoCountToRun; // Holds number of counts to run. 0 = Run forever + SLONG MotorBlockTachoCount; // Hold CaptureCount for current movement + SLONG MotorRampTachoCountOld; // Used to hold old position during Ramp-Up + SLONG MotorRampTachoCountStart; // Used to hold position when Ramp-up started + SLONG RotationCaptureCount; // Counter for additional rotation counter +}MOTORDATA; + +typedef struct +{ + SLONG SyncTachoDif; + SLONG SyncTurnParameter; + SWORD SyncOldError; + SWORD SyncAccError; +}SYNCMOTORDATA; + +static MOTORDATA MotorData[3]; +static SYNCMOTORDATA SyncData; + +void dOutputInit(void) +{ + UBYTE Temp; + + OUTPUTInit; + ENABLECaptureMotorA; + ENABLECaptureMotorB; + ENABLECaptureMotorC; + + for (Temp = 0; Temp < 3; Temp++) + { + MotorData[Temp].MotorSetSpeed = 0; + MotorData[Temp].MotorTargetSpeed = 0; + MotorData[Temp].MotorActualSpeed = 0; + MotorData[Temp].MotorRampUpCount = 0; + MotorData[Temp].MotorRampDownCount = 0; + MotorData[Temp].MotorRunState = 0; + MotorData[Temp].MotorTachoCountToRun = 0; + MotorData[Temp].MotorRunForever = 1; + MotorData[Temp].AccError = 0; + MotorData[Temp].RegulationTimeCount = 0; + MotorData[Temp].RegPParameter = DEFAULT_P_GAIN_FACTOR; + MotorData[Temp].RegIParameter = DEFAULT_I_GAIN_FACTOR; + MotorData[Temp].RegDParameter = DEFAULT_D_GAIN_FACTOR; + MotorData[Temp].RegulationMode = 0; + MotorData[Temp].MotorOverloaded = 0; + INSERTMode(Temp, COAST_MOTOR_MODE); + INSERTSpeed(Temp, MotorData[Temp].MotorSetSpeed); + } +} + +/* This function is called every 1 mS and will go through all the motors and there dependencies */ +/* Actual motor speed is only passed (updated) to the AVR controller form this function */ +/* DeltacaptureCount used to count number of Tachocount within last 100 mS. Used with position control regulation */ +/* CurrentCaptureCount used to tell total current position. Used to tell when movement has been obtained */ +/* MotorBlockTachoCount tell current position within current movement. Reset when a new block is started from the VM */ +/* RotationCaptureCount is additional counter for the rotationsensor. Uses it own value so it does conflict with other CaptureCount */ +void dOutputCtrl(void) +{ + UBYTE MotorNr; + SLONG NewTachoCount[3]; + + TACHOCaptureReadResetAll(NewTachoCount[MOTOR_A], NewTachoCount[MOTOR_B], NewTachoCount[MOTOR_C]); + + for (MotorNr = 0; MotorNr < 3; MotorNr++) + { + MotorData[MotorNr].DeltaCaptureCount += NewTachoCount[MotorNr]; + MotorData[MotorNr].CurrentCaptureCount += NewTachoCount[MotorNr]; + MotorData[MotorNr].MotorBlockTachoCount += NewTachoCount[MotorNr]; + MotorData[MotorNr].RotationCaptureCount += NewTachoCount[MotorNr]; + MotorData[MotorNr].RegulationTimeCount++; + + if (MotorData[MotorNr].MotorRunState == MOTOR_RUN_STATE_RAMPUP) + { + dOutputRampUpFunction(MotorNr); + } + if (MotorData[MotorNr].MotorRunState == MOTOR_RUN_STATE_RAMPDOWN) + { + dOutputRampDownFunction(MotorNr); + } + if (MotorData[MotorNr].MotorRunState == MOTOR_RUN_STATE_RUNNING) + { + dOutputTachoLimitControl(MotorNr); + } + if (MotorData[MotorNr].MotorRunState == MOTOR_RUN_STATE_IDLE) + { + dOutputMotorIdleControl(MotorNr); + } + if (MotorData[MotorNr].MotorRunState == MOTOR_RUN_STATE_HOLD) + { + MotorData[MotorNr].MotorSetSpeed = 0; + MotorData[MotorNr].MotorActualSpeed = 0; + MotorData[MotorNr].MotorTargetSpeed = 0; + MotorData[MotorNr].RegulationTimeCount = 0; + MotorData[MotorNr].DeltaCaptureCount = 0; + MotorData[MotorNr].MotorRunState = MOTOR_RUN_STATE_RUNNING; + + } + if (MotorData[MotorNr].RegulationTimeCount > REGULATION_TIME) + { + MotorData[MotorNr].RegulationTimeCount = 0; + dOutputRegulateMotor(MotorNr); + MotorData[MotorNr].DeltaCaptureCount = 0; + } + } + INSERTSpeed(MOTOR_A, MotorData[MOTOR_A].MotorActualSpeed); + INSERTSpeed(MOTOR_B, MotorData[MOTOR_B].MotorActualSpeed); + INSERTSpeed(MOTOR_C, MotorData[MOTOR_C].MotorActualSpeed); +} + +void dOutputExit(void) +{ + OUTPUTExit; +} + +/* Called eveyr 1 mS */ +/* Data mapping for controller (IO-Map is updated with these values) */ +void dOutputGetMotorParameters(UBYTE *CurrentMotorSpeed, SLONG *TachoCount, SLONG *BlockTachoCount, UBYTE *RunState, UBYTE *MotorOverloaded, SLONG *RotationCount) +{ + UBYTE Tmp; + + for (Tmp = 0; Tmp < 3; Tmp++) + { + CurrentMotorSpeed[Tmp] = MotorData[Tmp].MotorActualSpeed; + TachoCount[Tmp] = MotorData[Tmp].CurrentCaptureCount; + BlockTachoCount[Tmp] = MotorData[Tmp].MotorBlockTachoCount; + RotationCount[Tmp] = MotorData[Tmp].RotationCaptureCount; + RunState[Tmp] = MotorData[Tmp].MotorRunState; + MotorOverloaded[Tmp] = MotorData[Tmp].MotorOverloaded; + } +} + +void dOutputSetMode(UBYTE Motor, UBYTE Mode) //Set motor mode (break, Float) +{ + INSERTMode(Motor, Mode); +} + +/* Update the regulation state for the motor */ +/* Need to reset regulation parameter depending on current status of the motor */ +/* AccError & OldPositionError used for position regulation and Sync Parameter are used for synchronization regulation */ +void dOutputEnableRegulation(UBYTE MotorNr, UBYTE RegulationMode) +{ + MotorData[MotorNr].RegulationMode = RegulationMode; + + if ((MotorData[MotorNr].RegulationMode & REGSTATE_REGULATED) && (MotorData[MotorNr].MotorSetSpeed == 0) && (MotorData[MotorNr].MotorRunState != MOTOR_RUN_STATE_RAMPDOWN)) + { + MotorData[MotorNr].AccError = 0; + MotorData[MotorNr].OldPositionError = 0; + } + + if (MotorData[MotorNr].RegulationMode & REGSTATE_SYNCHRONE) + { + if (((MotorData[MotorNr].MotorActualSpeed == 0) || (MotorData[MotorNr].TurnParameter != 0) || (MotorData[MotorNr].TurnParameter == 0)) && (MotorData[MotorNr].MotorRunState != MOTOR_RUN_STATE_RAMPDOWN)) + { + SyncData.SyncTachoDif = 0; + + SyncData.SyncAccError = 0; + SyncData.SyncOldError = 0; + SyncData.SyncTurnParameter = 0; + } + } +} + +/* Disable current regulation if enabled */ +void dOutputDisableRegulation(UBYTE MotorNr) +{ + MotorData[MotorNr].RegulationMode = REGSTATE_IDLE; +} + +/* Calling this function with reset count which tell current position and which is used to tell if the wanted position is obtained */ +/* Calling this function will reset current movement of the motor if it is running */ +void dOutputResetTachoLimit(UBYTE MotorNr) +{ + MotorData[MotorNr].CurrentCaptureCount = 0; + MotorData[MotorNr].MotorTachoCountToRun = 0; + + if (MotorData[MotorNr].RegulationMode & REGSTATE_SYNCHRONE) + { + dOutputResetSyncMotors(MotorNr); + } + + if (MotorData[MotorNr].MotorRunForever == 1) + { + MotorData[MotorNr].MotorRunForever = 0; // To ensure that we get the same functionality for all combination on motor durations + } +} + +/* MotorBlockTachoCount tells current position in current movement. */ +/* Used within the synchronization to compare current motor position. Reset on every new movement from the VM */ +void dOutputResetBlockTachoLimit(UBYTE MotorNr) +{ + MotorData[MotorNr].MotorBlockTachoCount = 0; +} + +/* Additional counter add to help the VM application keep track of number of rotation for the rotation sensor */ +/* This values can be reset independtly from the other tacho count values used with regulation and position control */ +void dOutputResetRotationCaptureCount(UBYTE MotorNr) +{ + MotorData[MotorNr].RotationCaptureCount = 0; +} + +/* Can be used to set new PID values */ +void dOutputSetPIDParameters(UBYTE Motor, UBYTE NewRegPParameter, UBYTE NewRegIParameter, UBYTE NewRegDParameter) +{ + MotorData[Motor].RegPParameter = NewRegPParameter; + MotorData[Motor].RegIParameter = NewRegIParameter; + MotorData[Motor].RegDParameter = NewRegDParameter; +} + +/* Called to set TachoCountToRun which is used for position control for the model */ +/* Must be called before motor start */ +/* TachoCountToRun is calculated as a signed value */ +void dOutputSetTachoLimit(UBYTE MotorNr, ULONG BlockTachoCntToTravel) +{ + if (BlockTachoCntToTravel == 0) + { + MotorData[MotorNr].MotorRunForever = 1; + } + else + { + MotorData[MotorNr].MotorRunForever = 0; + + if (MotorData[MotorNr].MotorSetSpeed == 0) + { + if (MotorData[MotorNr].MotorTargetSpeed > 0) + { + MotorData[MotorNr].MotorTachoCountToRun += BlockTachoCntToTravel; + } + else + { + MotorData[MotorNr].MotorTachoCountToRun -= BlockTachoCntToTravel; + } + } + else + { + if (MotorData[MotorNr].MotorSetSpeed > 0) + { + MotorData[MotorNr].MotorTachoCountToRun += BlockTachoCntToTravel; + } + else + { + MotorData[MotorNr].MotorTachoCountToRun -= BlockTachoCntToTravel; + } + } + } +} + +/* This function is used for setting up the motor mode and motor speed */ +void dOutputSetSpeed (UBYTE MotorNr, UBYTE NewMotorRunState, SBYTE Speed, SBYTE NewTurnParameter) +{ + if ((MotorData[MotorNr].MotorSetSpeed != Speed) || (MotorData[MotorNr].MotorRunState != NewMotorRunState) || (NewMotorRunState == MOTOR_RUN_STATE_IDLE) || (MotorData[MotorNr].TurnParameter != NewTurnParameter)) + { + if (MotorData[MotorNr].MotorTargetSpeed == 0) + { + MotorData[MotorNr].AccError = 0; + MotorData[MotorNr].OldPositionError = 0; + MotorData[MotorNr].RegulationTimeCount = 0; + MotorData[MotorNr].DeltaCaptureCount = 0; + TACHOCountReset(MotorNr); + } + switch (NewMotorRunState) + { + case MOTOR_RUN_STATE_IDLE: + { + //MotorData[MotorNr].MotorSetSpeed = 0; + //MotorData[MotorNr].MotorTargetSpeed = 0; + //MotorData[MotorNr].TurnParameter = 0; + MotorData[MotorNr].RegulationMode = REGSTATE_IDLE; + } + break; + + case MOTOR_RUN_STATE_RAMPUP: + { + if (MotorData[MotorNr].MotorSetSpeed == 0) + { + MotorData[MotorNr].MotorSetSpeed = Speed; + MotorData[MotorNr].TurnParameter = NewTurnParameter; + MotorData[MotorNr].MotorRampUpIncrement = 0; + MotorData[MotorNr].MotorRampTachoCountStart = MotorData[MotorNr].CurrentCaptureCount; + MotorData[MotorNr].MotorRampUpCount = 0; + } + else + { + if (Speed > 0) + { + if (MotorData[MotorNr].MotorSetSpeed >= Speed) + { + NewMotorRunState = MOTOR_RUN_STATE_RUNNING; + } + else + { + MotorData[MotorNr].MotorSetSpeed = Speed; + MotorData[MotorNr].TurnParameter = NewTurnParameter; + MotorData[MotorNr].MotorRampUpIncrement = 0; + MotorData[MotorNr].MotorRampTachoCountStart = MotorData[MotorNr].CurrentCaptureCount; + MotorData[MotorNr].MotorRampUpCount = 0; + } + } + else + { + if (MotorData[MotorNr].MotorSetSpeed <= Speed) + { + NewMotorRunState = MOTOR_RUN_STATE_RUNNING; + } + else + { + MotorData[MotorNr].MotorSetSpeed = Speed; + MotorData[MotorNr].TurnParameter = NewTurnParameter; + MotorData[MotorNr].MotorRampUpIncrement = 0; + MotorData[MotorNr].MotorRampTachoCountStart = MotorData[MotorNr].CurrentCaptureCount; + MotorData[MotorNr].MotorRampUpCount = 0; + } + } + } + } + break; + + case MOTOR_RUN_STATE_RUNNING: + { + MotorData[MotorNr].MotorSetSpeed = Speed; + MotorData[MotorNr].MotorTargetSpeed = Speed; + MotorData[MotorNr].TurnParameter = NewTurnParameter; + + if (MotorData[MotorNr].MotorSetSpeed == 0) + { + NewMotorRunState = MOTOR_RUN_STATE_HOLD; + } + } + break; + + case MOTOR_RUN_STATE_RAMPDOWN: + { + if (MotorData[MotorNr].MotorTargetSpeed >= 0) + { + if (MotorData[MotorNr].MotorSetSpeed <= Speed) + { + NewMotorRunState = MOTOR_RUN_STATE_RUNNING; + } + else + { + MotorData[MotorNr].MotorSetSpeed = Speed; + MotorData[MotorNr].TurnParameter = NewTurnParameter; + MotorData[MotorNr].MotorRampDownIncrement = 0; + MotorData[MotorNr].MotorRampTachoCountStart = MotorData[MotorNr].CurrentCaptureCount; + MotorData[MotorNr].MotorRampDownCount = 0; + } + } + else + { + if (MotorData[MotorNr].MotorSetSpeed >= Speed) + { + NewMotorRunState = MOTOR_RUN_STATE_RUNNING; + } + else + { + MotorData[MotorNr].MotorSetSpeed = Speed; + MotorData[MotorNr].TurnParameter = NewTurnParameter; + MotorData[MotorNr].MotorRampDownIncrement = 0; + MotorData[MotorNr].MotorRampTachoCountStart = MotorData[MotorNr].CurrentCaptureCount; + MotorData[MotorNr].MotorRampDownCount = 0; + } + } + } + break; + } + MotorData[MotorNr].MotorRunState = NewMotorRunState; + MotorData[MotorNr].MotorOverloaded = 0; + } +} + +/* Function used for controlling the Ramp-up periode */ +/* Ramp-up is done with 1 increment in speed every X number of TachoCount, where X depend on duration of the periode and the wanted speed */ +void dOutputRampUpFunction(UBYTE MotorNr) +{ + if (MotorData[MotorNr].MotorTargetSpeed == 0) + { + if (MotorData[MotorNr].MotorSetSpeed > 0) + { + MotorData[MotorNr].MotorTargetSpeed = MIN_MOVEMENT_POWER; + } + else + { + MotorData[MotorNr].MotorTargetSpeed = -MIN_MOVEMENT_POWER; + } + } + else + { + if (MotorData[MotorNr].MotorRampUpIncrement == 0) + { + if (MotorData[MotorNr].MotorSetSpeed > 0) + { + MotorData[MotorNr].MotorRampUpIncrement = (SWORD)((MotorData[MotorNr].MotorTachoCountToRun - MotorData[MotorNr].MotorRampTachoCountStart) / (MotorData[MotorNr].MotorSetSpeed - MotorData[MotorNr].MotorTargetSpeed)); + } + else + { + MotorData[MotorNr].MotorRampUpIncrement = (SWORD)(-((MotorData[MotorNr].MotorTachoCountToRun - MotorData[MotorNr].MotorRampTachoCountStart) / (MotorData[MotorNr].MotorSetSpeed - MotorData[MotorNr].MotorTargetSpeed))); + } + MotorData[MotorNr].MotorRampTachoCountOld = MotorData[MotorNr].CurrentCaptureCount; + } + if (MotorData[MotorNr].MotorSetSpeed > 0) + { + if (MotorData[MotorNr].CurrentCaptureCount > (MotorData[MotorNr].MotorRampTachoCountOld + MotorData[MotorNr].MotorRampUpIncrement)) + { + MotorData[MotorNr].MotorTargetSpeed += 1; + MotorData[MotorNr].MotorRampTachoCountOld = MotorData[MotorNr].CurrentCaptureCount; + MotorData[MotorNr].MotorRampUpCount = 0; + } + else + { + if (!(MotorData[MotorNr].RegulationMode & REGSTATE_REGULATED)) + { + MotorData[MotorNr].MotorRampUpCount++; + if (MotorData[MotorNr].MotorRampUpCount > 100) + { + MotorData[MotorNr].MotorRampUpCount = 0; + MotorData[MotorNr].MotorTargetSpeed++; + } + } + } + } + else + { + if (MotorData[MotorNr].CurrentCaptureCount < (MotorData[MotorNr].MotorRampTachoCountOld + MotorData[MotorNr].MotorRampUpIncrement)) + { + MotorData[MotorNr].MotorTargetSpeed -= 1; + MotorData[MotorNr].MotorRampTachoCountOld = MotorData[MotorNr].CurrentCaptureCount; + MotorData[MotorNr].MotorRampUpCount = 0; + } + else + { + if (!(MotorData[MotorNr].RegulationMode & REGSTATE_REGULATED)) + { + MotorData[MotorNr].MotorRampUpCount++; + if (MotorData[MotorNr].MotorRampUpCount > 100) + { + MotorData[MotorNr].MotorRampUpCount = 0; + MotorData[MotorNr].MotorTargetSpeed--; + } + } + } + } + } + if (MotorData[MotorNr].MotorSetSpeed > 0) + { + if ((MotorData[MotorNr].CurrentCaptureCount - MotorData[MotorNr].MotorRampTachoCountStart) >= (MotorData[MotorNr].MotorTachoCountToRun - MotorData[MotorNr].MotorRampTachoCountStart)) + { + MotorData[MotorNr].MotorTargetSpeed = MotorData[MotorNr].MotorSetSpeed; + MotorData[MotorNr].MotorRunState = MOTOR_RUN_STATE_IDLE; + } + } + else + { + if ((MotorData[MotorNr].CurrentCaptureCount + MotorData[MotorNr].MotorRampTachoCountStart) <= (MotorData[MotorNr].MotorTachoCountToRun + MotorData[MotorNr].MotorRampTachoCountStart)) + { + MotorData[MotorNr].MotorTargetSpeed = MotorData[MotorNr].MotorSetSpeed; + MotorData[MotorNr].MotorRunState = MOTOR_RUN_STATE_IDLE; + } + } + if (MotorData[MotorNr].MotorSetSpeed > 0) + { + if (MotorData[MotorNr].MotorTargetSpeed > MotorData[MotorNr].MotorSetSpeed) + { + MotorData[MotorNr].MotorTargetSpeed = MotorData[MotorNr].MotorSetSpeed; + } + } + else + { + if (MotorData[MotorNr].MotorTargetSpeed < MotorData[MotorNr].MotorSetSpeed) + { + MotorData[MotorNr].MotorTargetSpeed = MotorData[MotorNr].MotorSetSpeed; + } + } + if (MotorData[MotorNr].RegulationMode == REGSTATE_IDLE) + { + MotorData[MotorNr].MotorActualSpeed = MotorData[MotorNr].MotorTargetSpeed; + } +} + +/* Function used for controlling the Ramp-down periode */ +/* Ramp-down is done with 1 decrement in speed every X number of TachoCount, where X depend on duration of the periode and the wanted speed */ +void dOutputRampDownFunction(UBYTE MotorNr) +{ + if (MotorData[MotorNr].MotorRampDownIncrement == 0) + { + if (MotorData[MotorNr].MotorTargetSpeed > 0) + { + if ((MotorData[MotorNr].MotorTargetSpeed > MIN_MOVEMENT_POWER) && (MotorData[MotorNr].MotorSetSpeed == 0)) + { + MotorData[MotorNr].MotorRampDownIncrement = ((MotorData[MotorNr].MotorTachoCountToRun - MotorData[MotorNr].CurrentCaptureCount) / ((MotorData[MotorNr].MotorTargetSpeed - MotorData[MotorNr].MotorSetSpeed) - MIN_MOVEMENT_POWER)); + } + else + { + MotorData[MotorNr].MotorRampDownIncrement = ((MotorData[MotorNr].MotorTachoCountToRun - MotorData[MotorNr].CurrentCaptureCount) / (MotorData[MotorNr].MotorTargetSpeed - MotorData[MotorNr].MotorSetSpeed)); + } + } + else + { + if ((MotorData[MotorNr].MotorTargetSpeed < -MIN_MOVEMENT_POWER) && (MotorData[MotorNr].MotorSetSpeed == 0)) + { + MotorData[MotorNr].MotorRampDownIncrement = (-((MotorData[MotorNr].MotorTachoCountToRun - MotorData[MotorNr].CurrentCaptureCount) / ((MotorData[MotorNr].MotorTargetSpeed - MotorData[MotorNr].MotorSetSpeed) + MIN_MOVEMENT_POWER))); + } + else + { + MotorData[MotorNr].MotorRampDownIncrement = (-((MotorData[MotorNr].MotorTachoCountToRun - MotorData[MotorNr].CurrentCaptureCount) / (MotorData[MotorNr].MotorTargetSpeed - MotorData[MotorNr].MotorSetSpeed))); + } + } + MotorData[MotorNr].MotorRampTachoCountOld = MotorData[MotorNr].CurrentCaptureCount; + } + if (MotorData[MotorNr].MotorTargetSpeed > 0) + { + if (MotorData[MotorNr].CurrentCaptureCount > (MotorData[MotorNr].MotorRampTachoCountOld + (SLONG)MotorData[MotorNr].MotorRampDownIncrement)) + { + MotorData[MotorNr].MotorTargetSpeed--; + if (MotorData[MotorNr].MotorTargetSpeed < MIN_MOVEMENT_POWER) + { + MotorData[MotorNr].MotorTargetSpeed = MIN_MOVEMENT_POWER; + } + MotorData[MotorNr].MotorRampTachoCountOld = MotorData[MotorNr].CurrentCaptureCount; + MotorData[MotorNr].MotorRampDownCount = 0; + dOutputRampDownSynch(MotorNr); + } + else + { + if (!(MotorData[MotorNr].RegulationMode & REGSTATE_REGULATED)) + { + MotorData[MotorNr].MotorRampDownCount++; + if (MotorData[MotorNr].MotorRampDownCount > (UWORD)(30 * MotorData[MotorNr].MotorRampDownIncrement)) + { + MotorData[MotorNr].MotorRampDownCount = (UWORD)(20 * MotorData[MotorNr].MotorRampDownIncrement); + MotorData[MotorNr].MotorTargetSpeed++; + } + } + } + } + else + { + if (MotorData[MotorNr].CurrentCaptureCount < (MotorData[MotorNr].MotorRampTachoCountOld + (SLONG)MotorData[MotorNr].MotorRampDownIncrement)) + { + MotorData[MotorNr].MotorTargetSpeed++; + if (MotorData[MotorNr].MotorTargetSpeed > -MIN_MOVEMENT_POWER) + { + MotorData[MotorNr].MotorTargetSpeed = -MIN_MOVEMENT_POWER; + } + MotorData[MotorNr].MotorRampTachoCountOld = MotorData[MotorNr].CurrentCaptureCount; + MotorData[MotorNr].MotorRampDownCount = 0; + dOutputRampDownSynch(MotorNr); + } + else + { + if (!(MotorData[MotorNr].RegulationMode & REGSTATE_REGULATED)) + { + MotorData[MotorNr].MotorRampDownCount++; + if (MotorData[MotorNr].MotorRampDownCount > (UWORD)(30 * (-MotorData[MotorNr].MotorRampDownIncrement))) + { + MotorData[MotorNr].MotorRampDownCount = (UWORD)(20 * (-MotorData[MotorNr].MotorRampDownIncrement)); + MotorData[MotorNr].MotorTargetSpeed--; + } + } + } + } + if ((MotorData[MotorNr].RegulationMode & REGSTATE_SYNCHRONE) && (MotorData[MotorNr].TurnParameter != 0)) + { + dOutputSyncTachoLimitControl(MotorNr); + if (MotorData[MotorNr].MotorRunState == MOTOR_RUN_STATE_IDLE) + { + dOutputMotorReachedTachoLimit(MotorNr); + } + } + else + { + if (MotorData[MotorNr].MotorTargetSpeed > 0) + { + if (MotorData[MotorNr].CurrentCaptureCount >= MotorData[MotorNr].MotorTachoCountToRun) + { + dOutputMotorReachedTachoLimit(MotorNr); + } + } + else + { + if (MotorData[MotorNr].CurrentCaptureCount <= MotorData[MotorNr].MotorTachoCountToRun) + { + dOutputMotorReachedTachoLimit(MotorNr); + } + } + } + if (MotorData[MotorNr].RegulationMode == REGSTATE_IDLE) + { + MotorData[MotorNr].MotorActualSpeed = MotorData[MotorNr].MotorTargetSpeed; + } +} + +/* Function used to tell whether the wanted position is obtained */ +void dOutputTachoLimitControl(UBYTE MotorNr) +{ + if (MotorData[MotorNr].MotorRunForever == 0) + { + if (MotorData[MotorNr].RegulationMode & REGSTATE_SYNCHRONE) + { + dOutputSyncTachoLimitControl(MotorNr); + } + else + { + if (MotorData[MotorNr].MotorSetSpeed > 0) + { + if ((MotorData[MotorNr].CurrentCaptureCount >= MotorData[MotorNr].MotorTachoCountToRun)) + { + MotorData[MotorNr].MotorRunState = MOTOR_RUN_STATE_IDLE; + MotorData[MotorNr].RegulationMode = REGSTATE_IDLE; + } + } + else + { + if (MotorData[MotorNr].MotorSetSpeed < 0) + { + if (MotorData[MotorNr].CurrentCaptureCount <= MotorData[MotorNr].MotorTachoCountToRun) + { + MotorData[MotorNr].MotorRunState = MOTOR_RUN_STATE_IDLE; + MotorData[MotorNr].RegulationMode = REGSTATE_IDLE; + } + } + } + } + } + else + { + if (MotorData[MotorNr].CurrentCaptureCount > MAX_COUNT_TO_RUN) + { + MotorData[MotorNr].CurrentCaptureCount = 0; + } + if (MotorData[MotorNr].MotorTargetSpeed != 0) + { + MotorData[MotorNr].MotorTachoCountToRun = MotorData[MotorNr].CurrentCaptureCount; + } + } + if (MotorData[MotorNr].RegulationMode == REGSTATE_IDLE) + { + MotorData[MotorNr].MotorActualSpeed = MotorData[MotorNr].MotorTargetSpeed; + } +} + +/* Function used to decrease speed slowly when the motor is set to idle */ +void dOutputMotorIdleControl(UBYTE MotorNr) +{ + INSERTMode(MotorNr, COAST_MOTOR_MODE); + + if (MotorData[MotorNr].MotorActualSpeed != 0) + { + if (MotorData[MotorNr].MotorActualSpeed > 0) + { + MotorData[MotorNr].MotorActualSpeed--; + } + else + { + MotorData[MotorNr].MotorActualSpeed++; + } + } + + if (MotorData[MotorNr].MotorTargetSpeed != 0) + { + if (MotorData[MotorNr].MotorTargetSpeed > 0) + { + MotorData[MotorNr].MotorTargetSpeed--; + } + else + { + MotorData[MotorNr].MotorTargetSpeed++; + } + } + + if (MotorData[MotorNr].MotorSetSpeed != 0) + { + if (MotorData[MotorNr].MotorSetSpeed > 0) + { + MotorData[MotorNr].MotorSetSpeed--; + } + else + { + MotorData[MotorNr].MotorSetSpeed++; + } + } +} + +/* Function called to evaluate which regulation princip that need to run and which MotorNr to use (I.E.: Which motors are synched together)*/ +void dOutputRegulateMotor(UBYTE MotorNr) +{ + UBYTE SyncMotorOne; + UBYTE SyncMotorTwo; + + if (MotorData[MotorNr].RegulationMode & REGSTATE_REGULATED) + { + dOutputCalculateMotorPosition(MotorNr); + } + else + { + if (MotorData[MotorNr].RegulationMode & REGSTATE_SYNCHRONE) + { + dOutputMotorSyncStatus(MotorNr, &SyncMotorOne, &SyncMotorTwo); + + if ((SyncMotorOne != 0xFF) &&(SyncMotorTwo != 0xFF)) + { + dOutputSyncMotorPosition(SyncMotorOne, SyncMotorTwo); + } + } + } +} + +/* Regulation function used when Position regulation is enabled */ +/* The regulation form only control one motor at a time */ +void dOutputCalculateMotorPosition(UBYTE MotorNr) +{ + SWORD PositionError; + SWORD PValue; + SWORD IValue; + SWORD DValue; + SWORD TotalRegValue; + SWORD NewSpeedCount = 0; + + NewSpeedCount = (SWORD)((MotorData[MotorNr].MotorTargetSpeed * MAX_CAPTURE_COUNT)/INPUT_SCALE_FACTOR); + + PositionError = (SWORD)(MotorData[MotorNr].OldPositionError - MotorData[MotorNr].DeltaCaptureCount) + NewSpeedCount; + + //Overflow control on PositionError + if (MotorData[MotorNr].RegPParameter != 0) + { + if (PositionError > (SWORD)(32000 / MotorData[MotorNr].RegPParameter)) + { + PositionError = (SWORD)(32000 / MotorData[MotorNr].RegPParameter); + } + if (PositionError < (SWORD)(-(32000 / MotorData[MotorNr].RegPParameter))) + { + PositionError = (SWORD)(-(32000 / MotorData[MotorNr].RegPParameter)); + } + } + else + { + if (PositionError > (SWORD)32000) + { + PositionError = (SWORD)32000; + } + if (PositionError < (SWORD)-32000) + { + PositionError = (SWORD)-32000; + } + } + + PValue = PositionError * (SWORD)(MotorData[MotorNr].RegPParameter/REG_CONST_DIV); + if (PValue > (SWORD)REG_MAX_VALUE) + { + PValue = REG_MAX_VALUE; + } + if (PValue <= (SWORD)REG_MIN_VALUE) + { + PValue = REG_MIN_VALUE; + } + + DValue = (PositionError - MotorData[MotorNr].OldPositionError) * (SWORD)(MotorData[MotorNr].RegDParameter/REG_CONST_DIV); + MotorData[MotorNr].OldPositionError = PositionError; + + MotorData[MotorNr].AccError = (MotorData[MotorNr].AccError * 3) + PositionError; + MotorData[MotorNr].AccError = MotorData[MotorNr].AccError / 4; + + if (MotorData[MotorNr].AccError > (SWORD)800) + { + MotorData[MotorNr].AccError = 800; + } + if (MotorData[MotorNr].AccError <= (SWORD)-800) + { + MotorData[MotorNr].AccError = -800; + } + IValue = MotorData[MotorNr].AccError * (SWORD)(MotorData[MotorNr].RegIParameter/REG_CONST_DIV); + + if (IValue > (SWORD)REG_MAX_VALUE) + { + IValue = REG_MAX_VALUE; + } + if (IValue <= (SWORD)REG_MIN_VALUE) + { + IValue = REG_MIN_VALUE; + } + TotalRegValue = (SWORD)((PValue + IValue + DValue)/2); + + if (TotalRegValue > MAXIMUM_SPEED_FW) + { + TotalRegValue = MAXIMUM_SPEED_FW; + MotorData[MotorNr].MotorOverloaded = 1; + } + if (TotalRegValue < MAXIMUM_SPEED_RW) + { + TotalRegValue = MAXIMUM_SPEED_RW; + MotorData[MotorNr].MotorOverloaded = 1; + } + MotorData[MotorNr].MotorActualSpeed = (SBYTE)TotalRegValue; +} + +/* Regulation function used when syncrhonization regulation is enabled */ +/* The regulation form controls two motors at a time */ +void dOutputSyncMotorPosition(UBYTE MotorOne, UBYTE MotorTwo) +{ + SLONG TempTurnParameter; + SWORD PValue; + SWORD IValue; + SWORD DValue; + SWORD CorrectionValue; + SWORD MotorSpeed; + + SyncData.SyncTachoDif = (SLONG)((MotorData[MotorOne].MotorBlockTachoCount) - (MotorData[MotorTwo].MotorBlockTachoCount)); + + if (MotorData[MotorOne].TurnParameter != 0) + { + if ((MotorData[MotorOne].MotorBlockTachoCount != 0) || (MotorData[MotorTwo].MotorBlockTachoCount)) + { + if (MotorData[MotorOne].MotorTargetSpeed >= 0) + { + if (MotorData[MotorOne].TurnParameter > 0) + { + TempTurnParameter = (SLONG)(((SLONG)MotorData[MotorTwo].TurnParameter * (SLONG)MotorData[MotorTwo].MotorTargetSpeed)/100); + } + else + { + TempTurnParameter = (SLONG)(((SLONG)MotorData[MotorOne].TurnParameter * (SLONG)MotorData[MotorOne].MotorTargetSpeed)/100); + } + } + else + { + if (MotorData[MotorOne].TurnParameter > 0) + { + TempTurnParameter = (SLONG)(((SLONG)MotorData[MotorOne].TurnParameter * (-(SLONG)MotorData[MotorOne].MotorTargetSpeed))/100); + } + else + { + TempTurnParameter = (SLONG)(((SLONG)MotorData[MotorTwo].TurnParameter * (-(SLONG)MotorData[MotorTwo].MotorTargetSpeed))/100); + } + } + } + else + { + TempTurnParameter = MotorData[MotorOne].TurnParameter; + } + } + else + { + TempTurnParameter = 0; + } + + SyncData.SyncTurnParameter += (SLONG)(((TempTurnParameter * (MAX_CAPTURE_COUNT))/INPUT_SCALE_FACTOR)*2); + //SyncTurnParameter should ophold difference between the two motors. + + SyncData.SyncTachoDif += SyncData.SyncTurnParameter; + + if ((SWORD)SyncData.SyncTachoDif > 500) + { + SyncData.SyncTachoDif = 500; + } + if ((SWORD)SyncData.SyncTachoDif < -500) + { + SyncData.SyncTachoDif = -500; + } + + PValue = (SWORD)SyncData.SyncTachoDif * (SWORD)(MotorData[MotorOne].RegPParameter/REG_CONST_DIV); + + DValue = ((SWORD)SyncData.SyncTachoDif - SyncData.SyncOldError) * (SWORD)(MotorData[MotorOne].RegDParameter/REG_CONST_DIV); + SyncData.SyncOldError = (SWORD)SyncData.SyncTachoDif; + + SyncData.SyncAccError += (SWORD)SyncData.SyncTachoDif; + + if (SyncData.SyncAccError > (SWORD)900) + { + SyncData.SyncAccError = 900; + } + if (SyncData.SyncAccError < (SWORD)-900) + { + SyncData.SyncAccError = -900; + } + IValue = SyncData.SyncAccError * (SWORD)(MotorData[MotorOne].RegIParameter/REG_CONST_DIV); + + CorrectionValue = (SWORD)((PValue + IValue + DValue)/4); + + MotorSpeed = (SWORD)MotorData[MotorOne].MotorTargetSpeed - CorrectionValue; + + if (MotorSpeed > (SWORD)MAXIMUM_SPEED_FW) + { + MotorSpeed = MAXIMUM_SPEED_FW; + } + else + { + if (MotorSpeed < (SWORD)MAXIMUM_SPEED_RW) + { + MotorSpeed = MAXIMUM_SPEED_RW; + } + } + + if (MotorData[MotorOne].TurnParameter != 0) + { + if (MotorData[MotorOne].MotorTargetSpeed > 0) + { + if (MotorSpeed > (SWORD)MotorData[MotorOne].MotorTargetSpeed) + { + MotorSpeed = (SWORD)MotorData[MotorOne].MotorTargetSpeed; + } + else + { + if (MotorSpeed < (SWORD)-MotorData[MotorOne].MotorTargetSpeed) + { + MotorSpeed = -MotorData[MotorOne].MotorTargetSpeed; + } + } + } + else + { + if (MotorSpeed < (SWORD)MotorData[MotorOne].MotorTargetSpeed) + { + MotorSpeed = (SWORD)MotorData[MotorOne].MotorTargetSpeed; + } + else + { + if (MotorSpeed > (SWORD)-MotorData[MotorOne].MotorTargetSpeed) + { + MotorSpeed = -MotorData[MotorOne].MotorTargetSpeed; + } + } + } + } + MotorData[MotorOne].MotorActualSpeed = (SBYTE)MotorSpeed; + + MotorSpeed = (SWORD)MotorData[MotorTwo].MotorTargetSpeed + CorrectionValue; + + if (MotorSpeed > (SWORD)MAXIMUM_SPEED_FW) + { + MotorSpeed = MAXIMUM_SPEED_FW; + } + else + { + if (MotorSpeed < (SWORD)MAXIMUM_SPEED_RW) + { + MotorSpeed = MAXIMUM_SPEED_RW; + } + } + + if (MotorData[MotorOne].TurnParameter != 0) + { + if (MotorData[MotorTwo].MotorTargetSpeed > 0) + { + if (MotorSpeed > (SWORD)MotorData[MotorTwo].MotorTargetSpeed) + { + MotorSpeed = (SWORD)MotorData[MotorTwo].MotorTargetSpeed; + } + else + { + if (MotorSpeed < (SWORD)-MotorData[MotorTwo].MotorTargetSpeed) + { + MotorSpeed = -MotorData[MotorTwo].MotorTargetSpeed; + } + } + } + else + { + if (MotorSpeed < (SWORD)MotorData[MotorTwo].MotorTargetSpeed) + { + MotorSpeed = (SWORD)MotorData[MotorTwo].MotorTargetSpeed; + } + else + { + if (MotorSpeed > (SWORD)-MotorData[MotorTwo].MotorTargetSpeed) + { + MotorSpeed = -MotorData[MotorTwo].MotorTargetSpeed; + } + } + } + } + MotorData[MotorTwo].MotorActualSpeed = (SBYTE)MotorSpeed; +} + +//Called when the motor is ramping down +void dOutputMotorReachedTachoLimit(UBYTE MotorNr) +{ + UBYTE MotorOne, MotorTwo; + + if (MotorData[MotorNr].RegulationMode & REGSTATE_SYNCHRONE) + { + if (MotorNr == MOTOR_A) + { + MotorOne = MotorNr; + MotorTwo = MotorOne + 1; + if (MotorData[MotorTwo].RegulationMode & REGSTATE_SYNCHRONE) + { + //Synchronise motor A & B + MotorData[MotorOne].MotorSetSpeed = 0; + MotorData[MotorOne].MotorTargetSpeed = 0; + MotorData[MotorOne].MotorActualSpeed = 0; + MotorData[MotorOne].MotorRunState = MOTOR_RUN_STATE_IDLE; + MotorData[MotorOne].RegulationMode = REGSTATE_IDLE; + MotorData[MotorTwo].MotorSetSpeed = 0; + MotorData[MotorTwo].MotorTargetSpeed = 0; + MotorData[MotorTwo].MotorActualSpeed = 0; + MotorData[MotorTwo].MotorRunState = MOTOR_RUN_STATE_IDLE; + MotorData[MotorTwo].RegulationMode = REGSTATE_IDLE; + } + else + { + MotorTwo = MotorOne + 2; + if (MotorData[MotorTwo].RegulationMode & REGSTATE_SYNCHRONE) + { + //Synchronise motor A & C + MotorData[MotorOne].MotorSetSpeed = 0; + MotorData[MotorOne].MotorTargetSpeed = 0; + MotorData[MotorOne].MotorActualSpeed = 0; + MotorData[MotorOne].MotorRunState = MOTOR_RUN_STATE_IDLE; + MotorData[MotorOne].RegulationMode = REGSTATE_IDLE; + MotorData[MotorTwo].MotorSetSpeed = 0; + MotorData[MotorTwo].MotorTargetSpeed = 0; + MotorData[MotorTwo].MotorActualSpeed = 0; + MotorData[MotorTwo].MotorRunState = MOTOR_RUN_STATE_IDLE; + MotorData[MotorTwo].RegulationMode = REGSTATE_IDLE; + } + else + { + //Only Motor A has Sync setting => Stop normal + MotorData[MotorNr].MotorSetSpeed = 0; + MotorData[MotorNr].MotorTargetSpeed = 0; + MotorData[MotorNr].MotorActualSpeed = 0; + MotorData[MotorNr].MotorRunState = MOTOR_RUN_STATE_IDLE; + MotorData[MotorNr].RegulationMode = REGSTATE_IDLE; + } + } + } + if (MotorNr == MOTOR_B) + { + MotorOne = MotorNr; + MotorTwo = MotorOne - 1; + if (MotorData[MotorTwo].RegulationMode & REGSTATE_SYNCHRONE) + { + //Synchronise motor A & B + MotorData[MotorOne].MotorSetSpeed = 0; + MotorData[MotorOne].MotorTargetSpeed = 0; + MotorData[MotorOne].MotorActualSpeed = 0; + MotorData[MotorOne].MotorRunState = MOTOR_RUN_STATE_IDLE; + MotorData[MotorOne].RegulationMode = REGSTATE_IDLE; + MotorData[MotorTwo].MotorSetSpeed = 0; + MotorData[MotorTwo].MotorTargetSpeed = 0; + MotorData[MotorTwo].MotorActualSpeed = 0; + MotorData[MotorTwo].MotorRunState = MOTOR_RUN_STATE_IDLE; + MotorData[MotorTwo].RegulationMode = REGSTATE_IDLE; + } + MotorTwo = MotorOne + 1; + if (MotorData[MotorTwo].RegulationMode & REGSTATE_SYNCHRONE) + { + //Synchronise motor B & C + MotorData[MotorOne].MotorSetSpeed = 0; + MotorData[MotorOne].MotorTargetSpeed = 0; + MotorData[MotorOne].MotorActualSpeed = 0; + MotorData[MotorOne].MotorRunState = MOTOR_RUN_STATE_IDLE; + MotorData[MotorOne].RegulationMode = REGSTATE_IDLE; + MotorData[MotorTwo].MotorSetSpeed = 0; + MotorData[MotorTwo].MotorTargetSpeed = 0; + MotorData[MotorTwo].MotorActualSpeed = 0; + MotorData[MotorTwo].MotorRunState = MOTOR_RUN_STATE_IDLE; + MotorData[MotorTwo].RegulationMode = REGSTATE_IDLE; + } + else + { + //Only Motor B has Sync settings => Stop normal + MotorData[MotorNr].MotorSetSpeed = 0; + MotorData[MotorNr].MotorTargetSpeed = 0; + MotorData[MotorNr].MotorActualSpeed = 0; + MotorData[MotorNr].MotorRunState = MOTOR_RUN_STATE_IDLE; + MotorData[MotorNr].RegulationMode = REGSTATE_IDLE; + } + } + if (MotorNr == MOTOR_C) + { + MotorOne = MotorNr; + MotorTwo = MotorOne - 2; + if (MotorData[MotorTwo].RegulationMode & REGSTATE_SYNCHRONE) + { + //Synchronise motor A & C + MotorData[MotorOne].MotorSetSpeed = 0; + MotorData[MotorOne].MotorTargetSpeed = 0; + MotorData[MotorOne].MotorActualSpeed = 0; + MotorData[MotorOne].MotorRunState = MOTOR_RUN_STATE_IDLE; + MotorData[MotorOne].RegulationMode = REGSTATE_IDLE; + MotorData[MotorTwo].MotorSetSpeed = 0; + MotorData[MotorTwo].MotorTargetSpeed = 0; + MotorData[MotorTwo].MotorActualSpeed = 0; + MotorData[MotorTwo].MotorRunState = MOTOR_RUN_STATE_IDLE; + MotorData[MotorTwo].RegulationMode = REGSTATE_IDLE; + } + MotorTwo = MotorOne - 1; + if (MotorData[MotorTwo].RegulationMode & REGSTATE_SYNCHRONE) + { + //Synchronise motor B & C + MotorData[MotorOne].MotorSetSpeed = 0; + MotorData[MotorOne].MotorTargetSpeed = 0; + MotorData[MotorOne].MotorActualSpeed = 0; + MotorData[MotorOne].MotorRunState = MOTOR_RUN_STATE_IDLE; + MotorData[MotorOne].RegulationMode = REGSTATE_IDLE; + MotorData[MotorTwo].MotorSetSpeed = 0; + MotorData[MotorTwo].MotorTargetSpeed = 0; + MotorData[MotorTwo].MotorActualSpeed = 0; + MotorData[MotorTwo].MotorRunState = MOTOR_RUN_STATE_IDLE; + MotorData[MotorTwo].RegulationMode = REGSTATE_IDLE; + } + else + { + //Only Motor C has Sync settings => Stop normal + MotorData[MotorNr].MotorSetSpeed = 0; + MotorData[MotorNr].MotorTargetSpeed = 0; + MotorData[MotorNr].MotorActualSpeed = 0; + MotorData[MotorNr].MotorRunState = MOTOR_RUN_STATE_IDLE; + MotorData[MotorNr].RegulationMode = REGSTATE_IDLE; + } + } + } + else + { + if (MotorData[MotorNr].MotorSetSpeed == 0) + { + MotorData[MotorNr].MotorSetSpeed = 0; + MotorData[MotorNr].MotorTargetSpeed = 0; + MotorData[MotorNr].MotorActualSpeed = 0; + } + MotorData[MotorNr].MotorRunState = MOTOR_RUN_STATE_IDLE; + MotorData[MotorNr].RegulationMode = REGSTATE_IDLE; + } +} + +/* Function used for control tacho limit when motors are synchronised */ +/* Special control is needed when the motor are turning */ +void dOutputSyncTachoLimitControl(UBYTE MotorNr) +{ + UBYTE MotorOne, MotorTwo; + + if (MotorNr == MOTOR_A) + { + MotorOne = MotorNr; + MotorTwo = MotorOne + 1; + if (MotorData[MotorTwo].RegulationMode & REGSTATE_SYNCHRONE) + { + //Synchronise motor A & B + } + else + { + MotorTwo = MotorOne + 2; + if (MotorData[MotorTwo].RegulationMode & REGSTATE_SYNCHRONE) + { + //Synchronise motor A & C + } + else + { + //Only Motor A has Sync setting => Stop normal + MotorOne = 0xFF; + MotorTwo = 0xFF; + } + } + } + if (MotorNr == MOTOR_B) + { + MotorOne = MotorNr; + MotorTwo = MotorOne - 1; + if (MotorData[MotorTwo].RegulationMode & REGSTATE_SYNCHRONE) + { + //Synchronise motor A & B, which has already been called when running throught motor A + //MotorOne = 0xFF; + //MotorTwo = 0xFF; + } + else + { + MotorTwo = MotorOne + 1; + if (MotorData[MotorTwo].RegulationMode & REGSTATE_SYNCHRONE) + { + //Synchronise motor B & C + } + else + { + //Only Motor B has Sync settings => Stop normal + MotorOne = 0xFF; + MotorTwo = 0xFF; + } + } + } + if (MotorNr == MOTOR_C) + { + MotorOne = MotorNr; + MotorTwo = MotorOne - 2; + if (MotorData[MotorTwo].RegulationMode & REGSTATE_SYNCHRONE) + { + //Synchronise motor A & C, which has already been called when running throught motor A + //MotorOne = 0xFF; + //MotorTwo = 0xFF; + } + else + { + MotorTwo = MotorOne - 1; + if (MotorData[MotorTwo].RegulationMode & REGSTATE_SYNCHRONE) + { + //Synchronise motor B & C, which has already been called when running throught motor B + //MotorOne = 0xFF; + //MotorTwo = 0xFF; + } + else + { + //Only Motor C has Sync settings => Stop normal + MotorOne = 0xFF; + MotorTwo = 0xFF; + } + } + } + + if ((MotorOne != 0xFF) && (MotorTwo != 0xFF)) + { + if (MotorData[MotorOne].TurnParameter != 0) + { + if (MotorData[MotorOne].TurnParameter > 0) + { + if (MotorData[MotorTwo].MotorTargetSpeed >= 0) + { + if ((SLONG)(MotorData[MotorTwo].CurrentCaptureCount >= MotorData[MotorTwo].MotorTachoCountToRun)) + { + MotorData[MotorOne].MotorRunState = MOTOR_RUN_STATE_IDLE; + MotorData[MotorTwo].MotorRunState = MOTOR_RUN_STATE_IDLE; + + MotorData[MotorOne].CurrentCaptureCount = MotorData[MotorTwo].CurrentCaptureCount; + MotorData[MotorOne].MotorTachoCountToRun = MotorData[MotorTwo].MotorTachoCountToRun; + } + } + else + { + if ((SLONG)(MotorData[MotorOne].CurrentCaptureCount <= MotorData[MotorOne].MotorTachoCountToRun)) + { + MotorData[MotorOne].MotorRunState = MOTOR_RUN_STATE_IDLE; + MotorData[MotorTwo].MotorRunState = MOTOR_RUN_STATE_IDLE; + + MotorData[MotorTwo].CurrentCaptureCount = MotorData[MotorOne].CurrentCaptureCount; + MotorData[MotorTwo].MotorTachoCountToRun = MotorData[MotorOne].MotorTachoCountToRun; + } + } + } + else + { + if (MotorData[MotorOne].MotorTargetSpeed >= 0) + { + if ((SLONG)(MotorData[MotorOne].CurrentCaptureCount >= MotorData[MotorOne].MotorTachoCountToRun)) + { + MotorData[MotorOne].MotorRunState = MOTOR_RUN_STATE_IDLE; + MotorData[MotorTwo].MotorRunState = MOTOR_RUN_STATE_IDLE; + + MotorData[MotorTwo].CurrentCaptureCount = MotorData[MotorOne].CurrentCaptureCount; + MotorData[MotorTwo].MotorTachoCountToRun = MotorData[MotorOne].MotorTachoCountToRun; + } + } + else + { + if ((SLONG)(MotorData[MotorTwo].CurrentCaptureCount <= MotorData[MotorTwo].MotorTachoCountToRun)) + { + MotorData[MotorOne].MotorRunState = MOTOR_RUN_STATE_IDLE; + MotorData[MotorTwo].MotorRunState = MOTOR_RUN_STATE_IDLE; + + MotorData[MotorOne].CurrentCaptureCount = MotorData[MotorTwo].CurrentCaptureCount; + MotorData[MotorOne].MotorTachoCountToRun = MotorData[MotorTwo].MotorTachoCountToRun; + } + } + } + } + else + { + if (MotorData[MotorOne].MotorSetSpeed > 0) + { + if ((MotorData[MotorOne].CurrentCaptureCount >= MotorData[MotorOne].MotorTachoCountToRun) || (MotorData[MotorTwo].CurrentCaptureCount >= MotorData[MotorTwo].MotorTachoCountToRun)) + { + MotorData[MotorOne].MotorRunState = MOTOR_RUN_STATE_IDLE; + MotorData[MotorTwo].MotorRunState = MOTOR_RUN_STATE_IDLE; + } + } + else + { + if (MotorData[MotorOne].MotorSetSpeed < 0) + { + if ((MotorData[MotorOne].CurrentCaptureCount <= MotorData[MotorOne].MotorTachoCountToRun) || (MotorData[MotorTwo].CurrentCaptureCount <= MotorData[MotorTwo].MotorTachoCountToRun)) + { + MotorData[MotorOne].MotorRunState = MOTOR_RUN_STATE_IDLE; + MotorData[MotorTwo].MotorRunState = MOTOR_RUN_STATE_IDLE; + } + } + } + } + } +} + +/* Function which can evaluate which motor are synched */ +void dOutputMotorSyncStatus(UBYTE MotorNr, UBYTE *SyncMotorOne, UBYTE *SyncMotorTwo) +{ + if (MotorNr < MOTOR_C) + { + if (MotorNr == MOTOR_A) + { + *SyncMotorOne = MotorNr; + *SyncMotorTwo = *SyncMotorOne + 1; + if (MotorData[*SyncMotorTwo].RegulationMode & REGSTATE_SYNCHRONE) + { + //Synchronise motor A & B + } + else + { + *SyncMotorTwo = *SyncMotorOne + 2; + if (MotorData[*SyncMotorTwo].RegulationMode & REGSTATE_SYNCHRONE) + { + //Synchronise motor A & C + } + else + { + //Only Motor A has Sync setting => Do nothing, treat motor as motor without regulation + *SyncMotorTwo = 0xFF; + } + } + } + if (MotorNr == MOTOR_B) + { + *SyncMotorOne = MotorNr; + *SyncMotorTwo = *SyncMotorOne + 1; + if (MotorData[*SyncMotorTwo].RegulationMode & REGSTATE_SYNCHRONE) + { + if (!(MotorData[MOTOR_A].RegulationMode & REGSTATE_SYNCHRONE)) + { + //Synchronise motor B & C + } + } + else + { + //Only Motor B has Sync settings or Motor is sync. with Motor A and has therefore already been called + *SyncMotorTwo = 0xFF; + } + } + } + else + { + *SyncMotorOne = 0xFF; + *SyncMotorTwo = 0xFF; + } +} +/* Function which is called when motors are synchronized and the motor position is reset */ +void dOutputResetSyncMotors(UBYTE MotorNr) +{ + UBYTE MotorOne, MotorTwo; + + if (MotorNr == MOTOR_A) + { + MotorOne = MotorNr; + MotorTwo = MotorOne + 1; + if (MotorData[MotorTwo].RegulationMode & REGSTATE_SYNCHRONE) + { + //Synchronise motor A & B + } + else + { + MotorTwo = MotorOne + 2; + if (MotorData[MotorTwo].RegulationMode & REGSTATE_SYNCHRONE) + { + //Synchronise motor A & C + } + else + { + //Only Motor A has Sync setting => Stop normal + MotorOne = 0xFF; + MotorTwo = 0xFF; + } + } + } + if (MotorNr == MOTOR_B) + { + MotorOne = MotorNr; + MotorTwo = MotorOne - 1; + if (MotorData[MotorTwo].RegulationMode & REGSTATE_SYNCHRONE) + { + //Synchronise motor A & B + } + else + { + MotorTwo = MotorOne + 1; + if (MotorData[MotorTwo].RegulationMode & REGSTATE_SYNCHRONE) + { + //Synchronise motor B & C + } + else + { + //Only Motor B has Sync settings => Stop normal + MotorOne = 0xFF; + MotorTwo = 0xFF; + } + } + } + if (MotorNr == MOTOR_C) + { + MotorOne = MotorNr; + MotorTwo = MotorOne - 2; + if (MotorData[MotorTwo].RegulationMode & REGSTATE_SYNCHRONE) + { + //Synchronise motor A & C + } + else + { + MotorTwo = MotorOne - 1; + if (MotorData[MotorTwo].RegulationMode & REGSTATE_SYNCHRONE) + { + //Synchronise motor B & C + } + else + { + //Only Motor C has Sync settings => Stop normal + MotorOne = 0xFF; + MotorTwo = 0xFF; + } + } + } + + if ((MotorOne != 0xFF) && (MotorTwo != 0xFF)) + { + MotorData[MotorOne].CurrentCaptureCount = 0; + MotorData[MotorOne].MotorTachoCountToRun = 0; + MotorData[MotorTwo].CurrentCaptureCount = 0; + MotorData[MotorTwo].MotorTachoCountToRun = 0; + } + else + { + MotorData[MotorNr].CurrentCaptureCount = 0; + MotorData[MotorNr].MotorTachoCountToRun = 0; + } +} + +/* Function which is called when motors are synchronized and motor is ramping down */ +void dOutputRampDownSynch(UBYTE MotorNr) +{ + UBYTE MotorOne, MotorTwo; + + if (MotorNr == MOTOR_A) + { + MotorOne = MotorNr; + MotorTwo = MotorOne + 1; + if (MotorData[MotorTwo].RegulationMode & REGSTATE_SYNCHRONE) + { + //Synchronise motor A & B + } + else + { + MotorTwo = MotorOne + 2; + if (MotorData[MotorTwo].RegulationMode & REGSTATE_SYNCHRONE) + { + //Synchronise motor A & C + } + else + { + //Only Motor A has Sync setting => Stop normal + MotorOne = 0xFF; + MotorTwo = 0xFF; + } + } + } + if (MotorNr == MOTOR_B) + { + MotorOne = MotorNr; + MotorTwo = MotorOne - 1; + if (MotorData[MotorTwo].RegulationMode & REGSTATE_SYNCHRONE) + { + //Synchronise motor A & B, which has already been called when running throught motor A + //MotorOne = 0xFF; + //MotorTwo = 0xFF; + } + else + { + MotorTwo = MotorOne + 1; + if (MotorData[MotorTwo].RegulationMode & REGSTATE_SYNCHRONE) + { + //Synchronise motor B & C + } + else + { + //Only Motor B has Sync settings => Stop normal + MotorOne = 0xFF; + MotorTwo = 0xFF; + } + } + } + if (MotorNr == MOTOR_C) + { + MotorOne = MotorNr; + MotorTwo = MotorOne - 2; + if (MotorData[MotorTwo].RegulationMode & REGSTATE_SYNCHRONE) + { + //Synchronise motor A & C, which has already been called when running throught motor A + } + else + { + MotorTwo = MotorOne - 1; + if (MotorData[MotorTwo].RegulationMode & REGSTATE_SYNCHRONE) + { + //Synchronise motor B & C,, which has already been called when running throught motor B + } + else + { + //Only Motor C has Sync settings => Stop normal + MotorOne = 0xFF; + MotorTwo = 0xFF; + } + } + } + + if ((MotorOne != 0xFF) && (MotorTwo != 0xFF)) + { + if (MotorData[MotorOne].TurnParameter != 0) + { + if (MotorData[MotorOne].TurnParameter > 0) + { + if (MotorData[MotorOne].MotorTargetSpeed >= 0) + { + if (MotorData[MotorTwo].MotorActualSpeed < 0) + { + MotorData[MotorTwo].MotorTargetSpeed--; + } + } + else + { + if (MotorData[MotorTwo].MotorActualSpeed > 0) + { + MotorData[MotorTwo].MotorTargetSpeed++; + } + } + } + else + { + if (MotorData[MotorOne].MotorTargetSpeed >= 0) + { + if (MotorData[MotorTwo].MotorActualSpeed < 0) + { + MotorData[MotorTwo].MotorTargetSpeed--; + } + } + else + { + if (MotorData[MotorTwo].MotorActualSpeed > 0) + { + MotorData[MotorTwo].MotorTargetSpeed++; + } + } + } + } + } +} + diff --git a/AT91SAM7S256/Source/d_output.h b/AT91SAM7S256/Source/d_output.h new file mode 100644 index 0000000..cb0de5e --- /dev/null +++ b/AT91SAM7S256/Source/d_output.h @@ -0,0 +1,90 @@ +// +// Date init 14.12.2004 +// +// Revision date $Date:: 16-05-06 12:13 $ +// +// Filename $Workfile:: d_output.h $ +// +// Version $Revision:: 48 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/d_output.h $ +// +// Platform C +// + +#ifndef D_OUTPUT +#define D_OUTPUT + +#define NEW_MOTOR + +#ifdef NEW_MOTOR + +//Constant reffering to new motor +#define REG_CONST_DIV 32 // Constant which the PID constants value will be divided with +#define DEFAULT_P_GAIN_FACTOR 96//3 +#define DEFAULT_I_GAIN_FACTOR 32//1 +#define DEFAULT_D_GAIN_FACTOR 32//1 +#define MIN_MOVEMENT_POWER 10 +#define MAX_CAPTURE_COUNT 100 + +#else + +//Constant reffering to Old motor +#define REG_CONST_DIV 1 // Constant which the PID constants value will be divided with +#define DEFAULT_P_GAIN_FACTOR 3 +#define DEFAULT_I_GAIN_FACTOR 1 +#define DEFAULT_D_GAIN_FACTOR 1 +#define MIN_MOVEMENT_POWER 30 +#define MAX_CAPTURE_COUNT 80 + +#endif + +//Constant reffering to RegMode parameter +#define REGSTATE_IDLE 0x00 +#define REGSTATE_REGULATED 0x01 +#define REGSTATE_SYNCHRONE 0x02 + +//Constant reffering to RunState parameter +#define MOTOR_RUN_STATE_IDLE 0x00 +#define MOTOR_RUN_STATE_RAMPUP 0x10 +#define MOTOR_RUN_STATE_RUNNING 0x20 +#define MOTOR_RUN_STATE_RAMPDOWN 0x40 +#define MOTOR_RUN_STATE_HOLD 0x60 + + +enum +{ + MOTOR_A, + MOTOR_B, + MOTOR_C +}; + +void dOutputInit(void); +void dOutputExit(void); + +void dOutputCtrl(void); +void dOutputGetMotorParameters(UBYTE *CurrentMotorSpeed, SLONG *TachoCount, SLONG *BlockTachoCount, UBYTE *RunState, UBYTE *MotorOverloaded, SLONG *RotationCount); +void dOutputSetMode(UBYTE Motor, UBYTE Mode); +void dOutputSetSpeed (UBYTE MotorNr, UBYTE NewMotorRunState, SBYTE Speed, SBYTE TurnParameter); +void dOutputEnableRegulation(UBYTE Motor, UBYTE RegulationMode); +void dOutputDisableRegulation(UBYTE Motor); +void dOutputSetTachoLimit(UBYTE Motor, ULONG TachoCntToTravel); +void dOutputResetTachoLimit(UBYTE Motor); +void dOutputResetBlockTachoLimit(UBYTE Motor); +void dOutputResetRotationCaptureCount(UBYTE MotorNr); +void dOutputSetPIDParameters(UBYTE Motor, UBYTE NewRegPParameter, UBYTE NewRegIParameter, UBYTE NewRegDParameter); + +void dOutputRegulateMotor(UBYTE MotorNr); +void dOutputCalculateRampUpParameter(UBYTE MotorNr, ULONG NewTachoLimit); +void dOutputRampDownFunction(UBYTE MotorNr); +void dOutputRampUpFunction(UBYTE MotorNr); +void dOutputTachoLimitControl(UBYTE MotorNr); +void dOutputCalculateMotorPosition(UBYTE MotorNr); +void dOutputSyncMotorPosition(UBYTE MotorOne, UBYTE MotorTwo); +void dOutputMotorReachedTachoLimit(UBYTE MotorNr); +void dOutputMotorIdleControl(UBYTE MotorNr); +void dOutputSyncTachoLimitControl(UBYTE MotorNr); +void dOutputMotorSyncStatus(UBYTE MotorNr, UBYTE *SyncMotorOne, UBYTE *SyncMotorTwo); +void dOutputResetSyncMotors(UBYTE MotorNr); + +#endif diff --git a/AT91SAM7S256/Source/d_output.r b/AT91SAM7S256/Source/d_output.r new file mode 100644 index 0000000..0ed35ff --- /dev/null +++ b/AT91SAM7S256/Source/d_output.r @@ -0,0 +1,306 @@ +// +// Date init 14.12.2004 +// +// Revision date $Date:: 16-05-06 12:13 $ +// +// Filename $Workfile:: d_output.r $ +// +// Version $Revision:: 36 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/d_output.r $ +// +// Platform C +// + +#ifdef SAM7S256 + +#if defined (PROTOTYPE_PCB_3) || (PROTOTYPE_PCB_4) + +#define MOTOR_A_DIR AT91C_PIO_PA1 +#define MOTOR_A_INT AT91C_PIO_PA15 + +#define MOTOR_B_DIR AT91C_PIO_PA9 +#define MOTOR_B_INT AT91C_PIO_PA26 + +#define MOTOR_C_DIR AT91C_PIO_PA8 +#define MOTOR_C_INT AT91C_PIO_PA0 + +#else + +#define MOTOR_A_DIR AT91C_PIO_PA1 +#define MOTOR_A_INT AT91C_PIO_PA15 + +#define MOTOR_B_DIR AT91C_PIO_PA9 +#define MOTOR_B_INT AT91C_PIO_PA26 + +#define MOTOR_C_DIR AT91C_PIO_PA8 +#define MOTOR_C_INT AT91C_PIO_PA27 + +#endif + +#define FORWARD 0x01 +#define REVERSE -0x01 + +#define TIMER_0_ID12 (1L << AT91C_ID_TC0) +#define TIMER_1_ID13 (1L << AT91C_ID_TC1) +#define TIMER_2_ID14 (1L << AT91C_ID_TC2) + +typedef struct +{ + SLONG TachoCountTable; + SLONG TachoCountTableOld; + SBYTE MotorDirection; +}TACHOPARAMETERS; + +static TACHOPARAMETERS MotorTachoValue[3]; + +#define OUTPUTInit {\ + UBYTE Tmp;\ + for (Tmp = 0; Tmp < NOS_OF_AVR_OUTPUTS; Tmp++)\ + {\ + IoToAvr.PwmValue[Tmp] = 0;\ + }\ + IoToAvr.OutputMode = 0x00;\ + IoToAvr.PwmFreq = 8;\ + } + +#define INSERTSpeed(Motor, Speed) IoToAvr.PwmValue[Motor] = Speed + +#define INSERTMode(Motor, Mode) if (Mode & 0x02)\ + {\ + IoToAvr.OutputMode |= (0x01 << Motor);\ + }\ + else\ + {\ + IoToAvr.OutputMode &= ~(0x01 << Motor);\ + } + +#define ENABLEDebugOutput {\ + *AT91C_PIOA_PER = 0x20000000; /* Enable PIO on PA029 */\ + *AT91C_PIOA_OER = 0x20000000; /* PA029 set to Output */\ + } + +#define SETDebugOutputHigh *AT91C_PIOA_SODR = 0x20000000 + +#define SETDebugOutputLow *AT91C_PIOA_CODR = 0x20000000 + +#define ENABLECaptureMotorA {\ + *AT91C_PIOA_PDR = MOTOR_A_INT; /* Disable PIO on PA15 */\ + *AT91C_PIOA_BSR = MOTOR_A_INT; /* Enable Peripheral B on PA15 */\ + *AT91C_PIOA_PPUDR = MOTOR_A_INT | MOTOR_A_DIR; /* Disable Pull Up resistor on PA15 & PA1 */\ + *AT91C_PIOA_PER = MOTOR_A_DIR; /* Enable PIO on PA1 */\ + *AT91C_PIOA_ODR = MOTOR_A_DIR; /* PA1 set to input */\ + *AT91C_PIOA_IFER = MOTOR_A_INT | MOTOR_A_DIR; /* Enable filter on PA15 & PA1 */\ + *AT91C_PMC_PCER = TIMER_1_ID13; /* Enable clock for TC1*/\ + *AT91C_TCB_BMR = AT91C_TCB_TC1XC1S_NONE; /* No external clock signal XC2 */\ + *AT91C_TCB_BCR = 0x0; /* Clear SYNC */\ + *AT91C_TC1_CMR = *AT91C_TC1_CMR & 0X00000000; /* Clear all bits in TC1_CMR */\ + *AT91C_TC1_CMR = *AT91C_TC1_CMR & 0xFFFF7FFF; /* Enable capture mode */\ + *AT91C_TC1_CMR = *AT91C_TC1_CMR | AT91C_TC_CLKS_TIMER_DIV5_CLOCK; /* Set clock for timer to Clock5 = div 1024*/\ + *AT91C_TC1_CMR = *AT91C_TC1_CMR | AT91C_TC_ABETRG; /* Use external trigger for TIO1*/\ + *AT91C_TC1_CMR = *AT91C_TC1_CMR | AT91C_TC_EEVTEDG_BOTH; /* Trigger on both edges */\ + *AT91C_TC1_CMR = *AT91C_TC1_CMR | AT91C_TC_LDRA_RISING; /* RA loading register set */\ + *AT91C_AIC_IDCR = TIMER_1_ID13; /* Irq controller setup */\ + AT91C_AIC_SVR[13] = (unsigned int)CaptureAInt; \ + AT91C_AIC_SMR[13] = 0x05; /* Enable trigger on level */\ + *AT91C_AIC_ICCR = TIMER_1_ID13; /* Clear interrupt register PID13*/\ + *AT91C_TC1_IDR = 0xFF; /* Disable all interrupt from TC1 */\ + *AT91C_TC1_IER = 0x80; /* Enable interrupt from external trigger */\ + *AT91C_AIC_IECR = TIMER_1_ID13; /* Enable interrupt from TC1 */\ + *AT91C_TC1_CCR = 0x00; /* Clear registers before setting */\ + *AT91C_TC1_CCR = AT91C_TC_CLKEN; /* Enable clock */\ + } + +#define ENABLECaptureMotorB {\ + *AT91C_PIOA_PDR = MOTOR_B_INT; /* Disable PIO on PA26 */\ + *AT91C_PIOA_BSR = MOTOR_B_INT; /* Enable Peripheral B on PA26 */\ + *AT91C_PIOA_PER = MOTOR_B_DIR; /* Enable PIO on PA09 */\ + *AT91C_PIOA_PPUDR = MOTOR_B_INT | MOTOR_B_DIR; /* Disable Pull Up resistor on PA26 & PA09 */\ + *AT91C_PIOA_ODR = MOTOR_B_DIR; /* PA09 set to input */\ + *AT91C_PIOA_IFER = MOTOR_B_INT | MOTOR_B_DIR; /* Enable filter on PA26 & PA09 */\ + *AT91C_PMC_PCER = TIMER_2_ID14; /* Enable clock for TC2*/\ + *AT91C_TCB_BMR = AT91C_TCB_TC2XC2S_NONE; /* No external clock signal */\ + *AT91C_TCB_BCR = 0x0; /* Clear SYNC */\ + *AT91C_TC2_CMR = *AT91C_TC2_CMR & 0X00000000; /* Clear all bits in TC1_CMR */\ + *AT91C_TC2_CMR = *AT91C_TC2_CMR & 0xFFFF7FFF; /* Enable capture mode */\ + *AT91C_TC2_CMR = *AT91C_TC2_CMR | AT91C_TC_CLKS_TIMER_DIV5_CLOCK; /* Set clock for timer to Clock5 = div 1024*/\ + *AT91C_TC2_CMR = *AT91C_TC2_CMR | AT91C_TC_ABETRG; /* Use external trigger for TIO2*/\ + *AT91C_TC2_CMR = *AT91C_TC2_CMR | AT91C_TC_EEVTEDG_BOTH; /* Trigger on both edges */\ + *AT91C_TC2_CMR = *AT91C_TC2_CMR | AT91C_TC_LDRA_RISING; /* RA loading register set */\ + *AT91C_AIC_IDCR = TIMER_2_ID14; /* Irq controller setup */\ + AT91C_AIC_SVR[14] = (unsigned int)CaptureBInt; \ + AT91C_AIC_SMR[14] = 0x05; /* Enable trigger on level */\ + *AT91C_AIC_ICCR = TIMER_2_ID14; /* Clear interrupt register PID14*/\ + *AT91C_TC2_IDR = 0xFF; /* Disable all interrupt from TC2 */\ + *AT91C_TC2_IER = 0x80; /* Enable interrupts from external trigger */\ + *AT91C_AIC_IECR = TIMER_2_ID14; /* Enable interrupt from TC2 */\ + *AT91C_TC2_CCR = 0x00; /* Clear registers before setting */\ + *AT91C_TC2_CCR = AT91C_TC_CLKEN; /* Enable clock */\ + } + + #define ENABLECaptureMotorC {\ + *AT91C_PIOA_PDR = MOTOR_C_INT; /* Disable PIO on PA0 */\ + *AT91C_PIOA_BSR = MOTOR_C_INT; /* Enable Peripheral B on PA0 */\ + *AT91C_PIOA_PER = MOTOR_C_DIR; /* Enable PIO on PA08 */\ + *AT91C_PIOA_PPUDR = MOTOR_C_INT | MOTOR_C_DIR; /* Disable Pull Up resistor on PA0 & PA08 */\ + *AT91C_PIOA_ODR = MOTOR_C_DIR; /* PA08 set to input */\ + *AT91C_PIOA_IFER = MOTOR_C_INT | MOTOR_C_DIR; /* Enable filter on PA26 & PA09 */\ + *AT91C_PMC_PCER = TIMER_0_ID12; /* Enable clock for TC0*/\ + *AT91C_TCB_BMR = AT91C_TCB_TC0XC0S_NONE; /* No external clock signal */\ + *AT91C_TC0_CMR = *AT91C_TC0_CMR & 0X00000000; /* Clear all bits in TC0_CMR */\ + *AT91C_TC0_CMR = *AT91C_TC0_CMR & 0xFFFF7FFF; /* Enable capture mode */\ + *AT91C_TC0_CMR = *AT91C_TC0_CMR | AT91C_TC_CLKS_TIMER_DIV5_CLOCK; /* Set clock for timer to Clock5 = div 1024*/\ + *AT91C_TC0_CMR = *AT91C_TC0_CMR | AT91C_TC_ABETRG; /* Use external trigger for TI0*/\ + *AT91C_TC0_CMR = *AT91C_TC0_CMR | AT91C_TC_EEVTEDG_BOTH; /* Trigger on both edges */\ + *AT91C_TC0_CMR = *AT91C_TC0_CMR | AT91C_TC_LDRA_RISING; /* RA loading register set */\ + *AT91C_AIC_IDCR = TIMER_0_ID12; /* Disable interrupt */\ + AT91C_AIC_SVR[12] = (unsigned int)CaptureCInt; \ + AT91C_AIC_SMR[12] = 0x05; /* Enable trigger on level */\ + *AT91C_AIC_ICCR = TIMER_0_ID12; /* Clear interrupt register PID12*/\ + *AT91C_TC0_IDR = 0xFF; /* Disable all interrupt from TC0 */\ + *AT91C_TC0_IER = 0x80; /* Enable interrupts from external trigger */\ + *AT91C_AIC_IECR = TIMER_0_ID12; /* Enable interrupt from TC0 */\ + *AT91C_TC0_CCR = 0x00; /* Clear registers before setting */\ + *AT91C_TC0_CCR = AT91C_TC_CLKEN; /* Enable clock */\ + } + +__ramfunc void CaptureAInt(void) +{ + if (*AT91C_TC1_SR & AT91C_TC_MTIOA) + { + if (*AT91C_PIOA_PDSR & MOTOR_A_DIR) + { + MotorTachoValue[0].MotorDirection = REVERSE; //Motor is running reverse + MotorTachoValue[0].TachoCountTable--; + } + else + { + MotorTachoValue[0].MotorDirection = FORWARD; //Motor is running forward + MotorTachoValue[0].TachoCountTable++; + } + } + else + { + if (*AT91C_PIOA_PDSR & MOTOR_A_DIR) + { + MotorTachoValue[0].MotorDirection = FORWARD; + MotorTachoValue[0].TachoCountTable++; + } + else + { + MotorTachoValue[0].MotorDirection = REVERSE; + MotorTachoValue[0].TachoCountTable--; + } + } +} + +__ramfunc void CaptureBInt(void) +{ + if (*AT91C_TC2_SR & AT91C_TC_MTIOA) + { + if (*AT91C_PIOA_PDSR & MOTOR_B_DIR) + { + MotorTachoValue[1].MotorDirection = REVERSE; //Motor is running reverse + MotorTachoValue[1].TachoCountTable--; + } + else + { + MotorTachoValue[1].MotorDirection = FORWARD; //Motor is running forward + MotorTachoValue[1].TachoCountTable++; + } + } + else + { + if (*AT91C_PIOA_PDSR & MOTOR_B_DIR) + { + MotorTachoValue[1].MotorDirection = FORWARD; + MotorTachoValue[1].TachoCountTable++; + } + else + { + MotorTachoValue[1].MotorDirection = REVERSE; + MotorTachoValue[1].TachoCountTable--; + } + } +} + + +//__ramfunc void CaptureBInt(void) +//{ +// if (((bool)(*AT91C_TC2_SR & AT91C_TC_MTIOA))==((bool)(*AT91C_PIOA_PDSR & MOTOR_B_DIR))) +// { +// MotorTachoValue[1].MotorDirection = REVERSE; //Motor is running reverse +// MotorTachoValue[1].TachoCountTable--; +// } +// else +// { +// MotorTachoValue[1].MotorDirection = FORWARD; //Motor is running reverse +// MotorTachoValue[1].TachoCountTable++; +// } +//} + + +__ramfunc void CaptureCInt(void) +{ + if (*AT91C_TC0_SR & AT91C_TC_MTIOA) + { + if (*AT91C_PIOA_PDSR & MOTOR_C_DIR) + { + MotorTachoValue[2].MotorDirection = REVERSE; //Motor is running reverse + MotorTachoValue[2].TachoCountTable--; + } + else + { + MotorTachoValue[2].MotorDirection = FORWARD; //Motor is running forward + MotorTachoValue[2].TachoCountTable++; + } + } + else + { + if (*AT91C_PIOA_PDSR & MOTOR_C_DIR) + { + MotorTachoValue[2].MotorDirection = FORWARD; + MotorTachoValue[2].TachoCountTable++; + } + else + { + MotorTachoValue[2].MotorDirection = REVERSE; + MotorTachoValue[2].TachoCountTable--; + } + } +} + +#define OUTPUTExit {\ + *AT91C_AIC_IDCR = TIMER_0_ID12 | TIMER_1_ID13 | TIMER_2_ID14; /* Disable interrupts for the timers */\ + *AT91C_AIC_ICCR = TIMER_0_ID12 | TIMER_1_ID13 | TIMER_2_ID14; /* Clear penting interrupt register for timers*/\ + *AT91C_PMC_PCDR = TIMER_0_ID12 | TIMER_1_ID13 | TIMER_2_ID14; /* Disable the clock for each of the timers*/\ + *AT91C_PIOA_PER = MOTOR_A_DIR | MOTOR_A_INT | MOTOR_B_DIR | MOTOR_B_INT | MOTOR_C_DIR | MOTOR_C_INT; /* Enable PIO on PA15, PA11, PA26, PA09, PA27 & PA08 */\ + *AT91C_PIOA_ODR = MOTOR_A_DIR | MOTOR_A_INT | MOTOR_B_DIR | MOTOR_B_INT | MOTOR_C_DIR | MOTOR_C_INT; /* Set to input PA15, PA11, PA26, PA09, PA27 & PA08 */\ + *AT91C_PIOA_PPUDR = MOTOR_A_DIR | MOTOR_A_INT | MOTOR_B_DIR | MOTOR_B_INT | MOTOR_C_DIR | MOTOR_C_INT; /* Enable Pullup on PA15, PA11, PA26, PA09, PA27 & PA08 */\ + } + + +#define TACHOCountReset(MotorNr) {\ + MotorTachoValue[MotorNr].TachoCountTable = 0;\ + MotorTachoValue[MotorNr].TachoCountTableOld = 0;\ + } + +#define TACHOCaptureReadResetAll(MotorDataA,MotorDataB,MotorDataC){\ + MotorDataA = (MotorTachoValue[MOTOR_A].TachoCountTable - MotorTachoValue[MOTOR_A].TachoCountTableOld);\ + MotorTachoValue[MOTOR_A].TachoCountTableOld = MotorTachoValue[MOTOR_A].TachoCountTable;\ + MotorDataB = (MotorTachoValue[MOTOR_B].TachoCountTable - MotorTachoValue[MOTOR_B].TachoCountTableOld);\ + MotorTachoValue[MOTOR_B].TachoCountTableOld = MotorTachoValue[MOTOR_B].TachoCountTable;\ + MotorDataC = (MotorTachoValue[MOTOR_C].TachoCountTable - MotorTachoValue[MOTOR_C].TachoCountTableOld);\ + MotorTachoValue[MOTOR_C].TachoCountTableOld = MotorTachoValue[MOTOR_C].TachoCountTable;\ + } + + + + +#define GetMotorDirection(MotorNr) MotorTachoValue[MotorNr].MotorDirection + +#endif + +#ifdef PCWIN + +#endif diff --git a/AT91SAM7S256/Source/d_sound.c b/AT91SAM7S256/Source/d_sound.c new file mode 100644 index 0000000..66745d3 --- /dev/null +++ b/AT91SAM7S256/Source/d_sound.c @@ -0,0 +1,70 @@ +// +// Programmer +// +// Date init 14.12.2004 +// +// Reviser $Author:: Dkflebun $ +// +// Revision date $Date:: 5-02-07 13:36 $ +// +// Filename $Workfile:: d_sound.c $ +// +// Version $Revision:: 11 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/d_sound.c $ +// +// Platform C +// + +#include "stdconst.h" +#include "m_sched.h" +#include "d_sound.h" +#include "d_sound.r" + + +void dSoundInit(void) +{ + SOUNDInit; +} + + +void dSoundVolume(UBYTE Step) +{ + SOUNDVolume(Step); +} + + +UBYTE dSoundReady(void) +{ + return (SOUNDReady); +} + + +UBYTE dSoundStart(UBYTE *pSound,UWORD Length,UWORD SampleRate, UBYTE FileType) +{ + return (SOUNDStart(pSound,Length,SampleRate,FileType)); +} + + +UBYTE dSoundStop(void) +{ + return (SOUNDStop); +} + + +UBYTE dSoundTone(UBYTE *pMelody,UWORD Length,UBYTE Volume) +{ + return (SOUNDTone(pMelody,Length,Volume)); +} + + +void dSoundFreq(UWORD Hz,UWORD mS,UBYTE Volume) +{ + SOUNDFreq(Hz,mS,Volume); +} + + +void dSoundExit(void) +{ + SOUNDExit; +} diff --git a/AT91SAM7S256/Source/d_sound.h b/AT91SAM7S256/Source/d_sound.h new file mode 100644 index 0000000..8cef028 --- /dev/null +++ b/AT91SAM7S256/Source/d_sound.h @@ -0,0 +1,42 @@ +// +// Programmer +// +// Date init 14.12.2004 +// +// Reviser $Author:: Dkflebun $ +// +// Revision date $Date:: 5-02-07 13:36 $ +// +// Filename $Workfile:: d_sound.h $ +// +// Version $Revision:: 10 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/d_sound.h $ +// +// Platform C +// + + +#ifndef D_SOUND +#define D_SOUND + +void dSoundInit(void); +void dSoundVolume(UBYTE Step); +UBYTE dSoundReady(void); +UBYTE dSoundStart(UBYTE *pSound,UWORD Length,UWORD SampleRate, UBYTE FileFormat); +UBYTE dSoundStop(void); +UBYTE dSoundTone(UBYTE *pMelody,UWORD Length,UBYTE Volume); +void dSoundFreq(UWORD Hz,UWORD mS,UBYTE Volume); +void dSoundExit(void); + +#define SOUNDVOLUMESTEPS 4 + +#define DURATION_MIN 10 // [mS] +#define FREQUENCY_MIN 220 // [Hz] +#define FREQUENCY_MAX 14080 // [Hz] + +#define SAMPLERATE_MIN 2000 // Min sample rate [sps] +#define SAMPLERATE_DEFAULT 8000 // Default sample rate [sps] +#define SAMPLERATE_MAX 16000 // Max sample rate [sps] + +#endif diff --git a/AT91SAM7S256/Source/d_sound.r b/AT91SAM7S256/Source/d_sound.r new file mode 100644 index 0000000..00c7511 --- /dev/null +++ b/AT91SAM7S256/Source/d_sound.r @@ -0,0 +1,514 @@ +// +// Programmer +// +// Date init 14.12.2004 +// +// Reviser $Author:: Dkflebun $ +// +// Revision date $Date:: 5-02-07 13:36 $ +// +// Filename $Workfile:: d_sound.r $ +// +// Version $Revision:: 34 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/d_sound.r $ +// +// Platform C +// + +#include "d_sound_adpcm.r" + +#ifdef SAM7S256 + +#define SAMPLEMIN 0 // Must be zero (no pwm/interrupt) +#define SAMPLEMAX 256 // Must be 256 (8 bit wave format) +#define SAMPLECENTER (((SAMPLEMAX - SAMPLEMIN) / 2) + SAMPLEMIN) + +#define SAMPLEWORD ULONG +#define SAMPLEWORDS 8 +#define SAMPLEWORDBITS (sizeof(SAMPLEWORD) * 8) +#define SAMPLEBITS (SAMPLEWORDS * SAMPLEWORDBITS) +#define SAMPLECONSTANT 3 // >> == (SAMPLEMAX / SAMPLEWORDBITS) + +#define SAMPLETONENO 16 // No of tone samples + +#define SAMPLEBUFFERS 2 + +#define INIT_PREV_VAL_ADPCM 0x7F +#define INIT_INDEX_ADPCM 20 + +SAMPLEWORD SampleBuffer[SAMPLEBUFFERS][SAMPLEWORDS]; +SAMPLEWORD ToneBuffer[SAMPLETONENO]; + +const SAMPLEWORD TonePattern[SOUNDVOLUMESTEPS + 1][SAMPLETONENO] = +{ + { + 0xF0F0F0F0,0xF0F0F0F0, // Step 0 = silence + 0xF0F0F0F0,0xF0F0F0F0, + 0xF0F0F0F0,0xF0F0F0F0, + 0xF0F0F0F0,0xF0F0F0F0, + 0xF0F0F0F0,0xF0F0F0F0, + 0xF0F0F0F0,0xF0F0F0F0, + 0xF0F0F0F0,0xF0F0F0F0, + 0xF0F0F0F0,0xF0F0F0F0 + }, + { + 0xF0F0F0F0,0xF0F0F0F0, // Step 1 = 1/512 + 0xF0F0F0F0,0xF0F0F0F0, + 0xF0F0F0F0,0xF0F0F0F8, + 0xF0F0F0F0,0xF0F0F0F0, + 0xF0F0F0F0,0xF0F0F0F0, + 0xF0F0F0F0,0xF0F0F0F0, + 0xF0F0F0F0,0xF0F0F0F0, + 0xF0F0F0F0,0xF0F0F0F0 + }, + { + 0xF0F0F0F0,0xF0F0F0F0, // Step 2 = 0,+3,+4,+3,0,-3,-4,-3 + 0xF0F0F0F0,0xF0F8F8F8, + 0xF0F0F8F8,0xF8F8F0F0, + 0xF8F8F8F0,0xF0F0F0F0, + 0xF0F0F0F0,0xF0F0F0F0, + 0xF0F0F0F0,0xF0E0E0E0, + 0xF0F0E0E0,0xE0E0F0F0, + 0xE0E0E0F0,0xF0F0F0F0 + }, + { + 0xF0F0F0F0,0xF0F0F0F0, // Step 3 = 0,+10,+14,+10,0,-10,-14,-10 + 0xF8F8F8F8,0xF8F8FCFC, + 0xF8F8FCFC,0xFCFCFCFC, + 0xFCFCF8F8,0xF8F8F8F8, + 0xF0F0F0F0,0xF0F0F0F0, + 0xE0E0E0E0,0xE0E0C0C0, + 0xE0E0C0C0,0xC0C0C0C0, + 0xC0C0E0E0,0xE0E0E0E0 + }, + { + 0xF0F0F0F0,0xF0F0F0F0, // Step 4 = 0,+22,+32,+22,0,-22,-32,-22 + 0xFCFCFCFC,0xFCFCFDFD, + 0xFFFFFFFF,0xFFFFFFFF, + 0xFDFDFCFC,0xFCFCFCFC, + 0xF0F0F0F0,0xF0F0F0F0, + 0xC0C0C0C0,0xC0C08080, + 0x00000000,0x00000000, + 0x8080C0C0,0xC0C0C0C0 + } +}; + +UBYTE FractionPattern[SAMPLEWORDS] = +{ + 0x00, // 0 -> 00000000 + 0x10, // 1 -> 00010000 + 0x22, // 2 -> 00100010 + 0x4A, // 3 -> 01001010 + 0x55, // 4 -> 01010101 + 0x6D, // 5 -> 01101101 + 0x77, // 6 -> 01110111 + 0x7F, // 7 -> 01111111 +}; + +typedef struct +{ + SWORD Valprev; // Previous output value + SWORD Index; // Index into stepsize table +}ADPCM_State; + +ULONG ToneCycles; // No of tone cycles +ULONG ToneCyclesReady; // No of tone cycles for ready +ULONG ClockNext; // Serial clock for next buffer + +UBYTE *pSoundPointer; // Pointer to sample in actual sound buffer +UBYTE *pSoundPointerNext; // Pointer to sample in next sound buffer + +UWORD SoundSamplesLeft; // Number of samples left on actual sound buffer +UWORD SoundSamplesLeftNext; // Number of samples left on next sound buffer + +UBYTE SampleBufferNo; // Sample buffer no in use + +UBYTE SoundReady; // Sound channel ready (idle) +UBYTE SoundDivider; // Volume + +UWORD MelodyPointer; +UBYTE CurrentFileFormat; // Hold current playing file type + +UBYTE Outdata[2]; // Output buffer used within the ADPCM algorithm +ADPCM_State State; // Struct holding ADPCM state + +#define SOUNDIntEnable {\ + *AT91C_SSC_IER = AT91C_SSC_ENDTX;\ + } + +#define SOUNDIntDisable {\ + *AT91C_SSC_IDR = AT91C_SSC_ENDTX;\ + } + +#define SOUNDEnable {\ + *AT91C_PIOA_PDR = AT91C_PA17_TD; /* Enable TD on PA17 */\ + } + +#define SOUNDDisable {\ + *AT91C_PIOA_PER = AT91C_PA17_TD; /* Disable TD on PA17 */\ + } + +ULONG SoundSampleRate(UWORD Rate) +{ + ULONG Result; + + if (Rate > SAMPLERATE_MAX) + { + Rate = SAMPLERATE_MAX; + } + if (Rate < SAMPLERATE_MIN) + { + Rate = SAMPLERATE_MIN; + } + Result = ((OSC / (2 * SAMPLEBITS)) / Rate) + 1; + + return (Result); +} + +__ramfunc void CalculateBitstream(SAMPLEWORD *pSampleBuffer,UBYTE Sample) +{ + ULONG IntegerMask; + ULONG FractionMask; + UBYTE Integer; + UBYTE Fraction; + UBYTE Mask; + UBYTE Tmp; + SWORD STmp; + + if (SoundDivider) + { + STmp = Sample; + STmp &= 0xFF; + STmp -= SAMPLECENTER; + STmp >>= (SOUNDVOLUMESTEPS - SoundDivider); + STmp += SAMPLECENTER; + Sample = (UBYTE)STmp; + SOUNDEnable; + } + else + { + SOUNDDisable; + } + + Tmp = 0; + IntegerMask = 0xFFFF0000; + Integer = Sample >> SAMPLECONSTANT; + Fraction = Sample - (Integer << SAMPLECONSTANT); + IntegerMask = 0xFFFFFFFF << (SAMPLEWORDBITS - Integer); + FractionMask = (IntegerMask >> 1) | IntegerMask; + Mask = FractionPattern[Fraction]; + while (Tmp < SAMPLEWORDS) + { + if ((Mask & (0x01 << Tmp))) + { + *pSampleBuffer = FractionMask; + } + else + { + *pSampleBuffer = IntegerMask; + } + pSampleBuffer++; + Tmp++; + } +} + +__ramfunc void SscHandler(void) +{ + static UBYTE ByteCnt = 0; + + if (SoundSamplesLeft) + { + if (0 == CurrentFileFormat) + { + CalculateBitstream(SampleBuffer[SampleBufferNo],*pSoundPointer); + *AT91C_SSC_TNPR = (unsigned int)SampleBuffer[SampleBufferNo]; + *AT91C_SSC_TNCR = SAMPLEWORDS; + + pSoundPointer++; + SoundSamplesLeft--; + if (!SoundSamplesLeft) + { + pSoundPointer = pSoundPointerNext; + SoundSamplesLeft = SoundSamplesLeftNext; + *AT91C_SSC_CMR = ClockNext; + SoundSamplesLeftNext = 0; + } + + if (++SampleBufferNo >= SAMPLEBUFFERS) + { + SampleBufferNo = 0; + } + } + else + { + if (0 == ByteCnt) + { + SoundADPCMDecoder(*pSoundPointer, Outdata, &State.Valprev, &State.Index); + CalculateBitstream(SampleBuffer[SampleBufferNo],Outdata[0]); + *AT91C_SSC_TNPR = (unsigned int)SampleBuffer[SampleBufferNo]; + *AT91C_SSC_TNCR = SAMPLEWORDS; + + if (++SampleBufferNo >= SAMPLEBUFFERS) + { + SampleBufferNo = 0; + } + + ByteCnt++; + } + else + { + CalculateBitstream(SampleBuffer[SampleBufferNo],Outdata[1]); + *AT91C_SSC_TNPR = (unsigned int)SampleBuffer[SampleBufferNo]; + *AT91C_SSC_TNCR = SAMPLEWORDS; + + pSoundPointer++; + SoundSamplesLeft--; + if (!SoundSamplesLeft) + { + pSoundPointer = pSoundPointerNext; + SoundSamplesLeft = SoundSamplesLeftNext; + *AT91C_SSC_CMR = ClockNext; + SoundSamplesLeftNext = 0; + } + + if (++SampleBufferNo >= SAMPLEBUFFERS) + { + SampleBufferNo = 0; + } + ByteCnt = 0; + } + } + } + else + { + if (ToneCycles) + { + ToneCycles--; + if (ToneCycles < ToneCyclesReady) + { + SoundReady = TRUE; + } + *AT91C_SSC_TNPR = (unsigned int)ToneBuffer; + *AT91C_SSC_TNCR = SAMPLETONENO; + if (SoundDivider) + { + SOUNDEnable; + } + else + { + SOUNDDisable; + } + } + else + { + SoundReady = TRUE; + SOUNDDisable; + SOUNDIntDisable; + } + } +} + +UBYTE SoundStart(UBYTE *Sound,UWORD Length,UWORD SampleRate, UBYTE NewFileFormat) +{ + UBYTE Result = FALSE; + + if (SoundReady == TRUE) + { + if (Length > 1) + { + CurrentFileFormat = NewFileFormat; + *AT91C_SSC_CMR = SoundSampleRate(SampleRate); + pSoundPointer = Sound; + SoundSamplesLeft = Length; + + if (0 == CurrentFileFormat) + { + CalculateBitstream(SampleBuffer[0],*pSoundPointer); + *AT91C_SSC_TPR = (unsigned int)SampleBuffer[0]; + *AT91C_SSC_TCR = SAMPLEWORDS; + pSoundPointer++; + SoundSamplesLeft--; + CalculateBitstream(SampleBuffer[1],*pSoundPointer); + *AT91C_SSC_TNPR = (unsigned int)SampleBuffer[1]; + *AT91C_SSC_TNCR = SAMPLEWORDS; + pSoundPointer++; + SoundSamplesLeft--; + } + else + { + State.Valprev = INIT_PREV_VAL_ADPCM; + State.Index = INIT_INDEX_ADPCM; + SoundADPCMDecoder(*pSoundPointer, Outdata, &State.Valprev, &State.Index); + CalculateBitstream(SampleBuffer[0],Outdata[0]); + *AT91C_SSC_TPR = (unsigned int)SampleBuffer[0]; + *AT91C_SSC_TCR = SAMPLEWORDS; + pSoundPointer++; + SoundSamplesLeft--; + CalculateBitstream(SampleBuffer[1],Outdata[1]); + *AT91C_SSC_TNPR = (unsigned int)SampleBuffer[1]; + *AT91C_SSC_TNCR = SAMPLEWORDS; + } + SampleBufferNo = 0; + SoundReady = FALSE; + SOUNDIntEnable; + *AT91C_SSC_PTCR = AT91C_PDC_TXTEN; + } + Result = TRUE; + } + else + { + if (!ToneCycles) + { + if (!SoundSamplesLeftNext) + { + CurrentFileFormat = NewFileFormat; + ClockNext = SoundSampleRate(SampleRate); + pSoundPointerNext = Sound; + SoundSamplesLeftNext = Length; + Result = TRUE; + } + } + } + + return (Result); +} + +UBYTE SoundStop(void) +{ + ToneCycles = 0; + SOUNDIntDisable; + SOUNDDisable; + SoundReady = TRUE; + SoundSamplesLeft = 0; + SoundSamplesLeftNext = 0; + MelodyPointer = 0; + + return (TRUE); +} + +void SoundVolume(UBYTE Step) +{ + if (Step > SOUNDVOLUMESTEPS) + { + Step = SOUNDVOLUMESTEPS; + } + SoundDivider = Step; +} + +void SoundFreq(UWORD Freq,UWORD mS,UBYTE Step) +{ + UBYTE Tmp; + + if (mS < DURATION_MIN) + { + mS = DURATION_MIN; + } + if (Freq) + { + if (Freq < FREQUENCY_MIN) + { + Freq = FREQUENCY_MIN; + } + if (Freq > FREQUENCY_MAX) + { + Freq = FREQUENCY_MAX; + } + if (Step > SOUNDVOLUMESTEPS) + { + Step = SOUNDVOLUMESTEPS; + } + } + else + { + Step = 0; + Freq = 1000; + } + SoundDivider = Step; + SoundSamplesLeft = 0; + SoundSamplesLeftNext = 0; + for (Tmp = 0;Tmp < SAMPLETONENO;Tmp++) + { + ToneBuffer[Tmp] = TonePattern[Step][Tmp]; + } + + *AT91C_SSC_CMR = (((ULONG)OSC / (2L * 512L)) / ((ULONG)Freq)) + 1L; + ToneCycles = ((ULONG)Freq * (ULONG)mS) / 1000L - 1L; + ToneCyclesReady = ((ULONG)Freq * (ULONG)2L) / 1000L + 1L; + + *AT91C_SSC_TNPR = (unsigned int)ToneBuffer; + *AT91C_SSC_TNCR = SAMPLETONENO; + *AT91C_SSC_PTCR = AT91C_PDC_TXTEN; + SoundReady = FALSE; + SOUNDIntEnable; +} + +UBYTE SoundTone(UBYTE *pMel,UWORD Length,UBYTE Step) +{ + UBYTE Result = FALSE; + UWORD Freq; + UWORD mS; + + if ((SoundReady == TRUE)) + { + if (MelodyPointer <= (Length - 4)) + { + Freq = (UWORD)pMel[MelodyPointer++] << 8; + Freq += (UWORD)pMel[MelodyPointer++]; + mS = (UWORD)pMel[MelodyPointer++] << 8; + mS += (UWORD)pMel[MelodyPointer++]; + SoundFreq(Freq,mS,Step); + } + else + { + MelodyPointer = 0; + Result = TRUE; + } + } + + return (Result); +} + +#define SOUNDInit {\ + SOUNDIntDisable;\ + SoundReady = TRUE;\ + MelodyPointer = 0;\ + *AT91C_PMC_PCER = (1L << AT91C_ID_SSC); /* Enable MCK clock */\ + *AT91C_PIOA_PER = AT91C_PA17_TD; /* Disable TD on PA17 */\ + *AT91C_PIOA_ODR = AT91C_PA17_TD;\ + *AT91C_PIOA_OWDR = AT91C_PA17_TD;\ + *AT91C_PIOA_MDDR = AT91C_PA17_TD;\ + *AT91C_PIOA_PPUDR = AT91C_PA17_TD;\ + *AT91C_PIOA_IFDR = AT91C_PA17_TD;\ + *AT91C_PIOA_CODR = AT91C_PA17_TD;\ + *AT91C_PIOA_IDR = AT91C_PA17_TD;\ + *AT91C_SSC_CR = AT91C_SSC_SWRST;\ + AT91C_AIC_SVR[AT91C_ID_SSC] = (unsigned int)SscHandler;\ + AT91C_AIC_SMR[AT91C_ID_SSC] = AT91C_AIC_PRIOR_LOWEST | AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED; /* Set priority */\ + *AT91C_SSC_TCMR = AT91C_SSC_CKS_DIV + AT91C_SSC_CKO_CONTINOUS + AT91C_SSC_START_CONTINOUS;\ + *AT91C_SSC_TFMR = (SAMPLEWORDBITS - 1) + ((SAMPLEWORDS & 0xF) << 8) + AT91C_SSC_MSBF;\ + *AT91C_SSC_CR = AT91C_SSC_TXEN; /* TX enable */\ + *AT91C_AIC_ICCR = (1L << AT91C_ID_SSC); /* Clear interrupt */\ + *AT91C_AIC_IECR = (1L << AT91C_ID_SSC); /* Enable int. controller */\ + } + +#define SOUNDVolume(V) SoundVolume((UBYTE)V) + +#define SOUNDReady SoundReady + +#define SOUNDStart(pSnd,Lng,SR,FT) SoundStart(pSnd,Lng,SR,FT) + +#define SOUNDStop SoundStop() + +#define SOUNDTone(pMel,Lng,Vol) SoundTone(pMel,Lng,Vol) + +#define SOUNDFreq(Freq,Duration,Vol) SoundFreq(Freq,Duration,Vol) + +#define SOUNDExit {\ + SOUNDIntDisable;\ + SOUNDDisable;\ + *AT91C_AIC_IDCR = (1L << AT91C_ID_SSC);\ + } + + +#endif diff --git a/AT91SAM7S256/Source/d_sound_adpcm.r b/AT91SAM7S256/Source/d_sound_adpcm.r new file mode 100644 index 0000000..03e16b7 --- /dev/null +++ b/AT91SAM7S256/Source/d_sound_adpcm.r @@ -0,0 +1,156 @@ +//Playback of compressed sound files. This additional feature is being brought to you under the following license. +//Please adhere to its terms. +//The original code includes minor changes to function correctly within the LEGO MINDSTORMS NXT embedded system, +//but the main architecture are implemented as within the original code. + +//*********************************************************** +//Copyright 1992 by Stichting Mathematisch Centrum, Amsterdam, The +//Netherlands. +// +// All Rights Reserved +// +//Permission to use, copy, modify, and distribute this software and its +//documentation for any purpose and without fee is hereby granted, +//provided that the above copyright notice appear in all copies and that +//both that copyright notice and this permission notice appear in +//supporting documentation, and that the names of Stichting Mathematisch +//Centrum or CWI not be used in advertising or publicity pertaining to +//distribution of the software without specific, written prior permission. +// +//STICHTING MATHEMATISCH CENTRUM DISCLAIMS ALL WARRANTIES WITH REGARD TO +//THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND +//FITNESS, IN NO EVENT SHALL STICHTING MATHEMATISCH CENTRUM BE LIABLE +//FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +//WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +//ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT +//OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// +//******************************************************************/ + +// +// Programmer +// +// Date init 14.12.2004 +// +// Reviser $Author:: Dkflebun $ +// +// Revision date $Date:: 5-02-07 13:36 $ +// +// Filename $Workfile:: d_sound_adpcm.r $ +// +// Version $Revision:: 1 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/d_sound_adpcm.r $ +// +// Platform C +// + +#ifdef SAM7S256 + +static SWORD IndexTable[16] = +{ + -1, -1, -1, -1, 2, 4, 6, 8, + -1, -1, -1, -1, 2, 4, 6, 8, +}; + +static SWORD StepsizeTable[89] = +{ + 7, 8, 9, 10, 11, 12, 13, 14, 16, 17, + 19, 21, 23, 25, 28, 31, 34, 37, 41, 45, + 50, 55, 60, 66, 73, 80, 88, 97, 107, 118, + 130, 143, 157, 173, 190, 209, 230, 253, 279, 307, + 337, 371, 408, 449, 494, 544, 598, 658, 724, 796, + 876, 963, 1060, 1166, 1282, 1411, 1552, 1707, 1878, 2066, + 2272, 2499, 2749, 3024, 3327, 3660, 4026, 4428, 4871, 5358, + 5894, 6484, 7132, 7845, 8630, 9493, 10442, 11487, 12635, 13899, + 15289, 16818, 18500, 20350, 22385, 24623, 27086, 29794, 32767 +}; + +__ramfunc void SoundADPCMDecoder(UBYTE Indata, UBYTE *Outdata, SWORD *pStateValprev, SWORD *pStateIndex) +{ + SWORD Step; // Stepsize + SWORD Valprev; // Virtual previous output value + SWORD Vpdiff; // Current change to valprev + SWORD Index; // Current step change index + UBYTE *pOut; // Output buffer pointer + UBYTE Sign; // Current adpcm sign bit + UBYTE Delta; // Current adpcm output value + UBYTE Bufferstep; // Toggle between High og Low nibble + UBYTE Len; // Nibble Counter + + pOut = Outdata; + + Valprev = *pStateValprev; + Index = *pStateIndex; + Step = StepsizeTable[Index]; + + Bufferstep = 0; + Len = 2; + + for (; Len > 0 ; Len--) //Step 1 - get the delta value and compute next index + { + if(Bufferstep) + { + Delta = Indata & 0x0F; + } + else + { + Delta = (Indata >> 4) & 0x0F; + } + Bufferstep = !Bufferstep; + + Index += IndexTable[Delta]; //Step 2 - Find new index value (for later) + if (Index < 0) + { + Index = 0; + } + else + { + if (Index > 88) + { + Index = 88; + } + } + + Sign = Delta & 8; //Step 3 - Separate sign and magnitude + Delta = Delta & 7; + + Vpdiff = Step >> 3; //Step 4 - Compute difference and new predicted value + + if (Delta & 4) + { + Vpdiff += Step; + } + if (Delta & 2) + { + Vpdiff += Step>>1; + } + if (Delta & 1) + { + Vpdiff += Step>>2; + } + + if (Sign) + Valprev -= Vpdiff; + else + Valprev += Vpdiff; + + if (Valprev > 255) //Step 5 - clamp output value + { + Valprev = 255; + } + else + { + if (Valprev < 0) + { + Valprev = 0; + } + } + Step = StepsizeTable[Index]; //Step 6 - Update step value + *pOut++ = (UBYTE)Valprev; //Step 7 - Output value + } + *pStateValprev = Valprev; //State.Valprev = Valprev; + *pStateIndex = Index; //State.Index = Index; +} + +#endif diff --git a/AT91SAM7S256/Source/d_timer.c b/AT91SAM7S256/Source/d_timer.c new file mode 100644 index 0000000..7c38aed --- /dev/null +++ b/AT91SAM7S256/Source/d_timer.c @@ -0,0 +1,42 @@ +// +// Date init 14.12.2004 +// +// Revision date $Date:: 16-05-06 10:18 $ +// +// Filename $Workfile:: d_timer.c $ +// +// Version $Revision:: 3 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/d_timer.c $ +// +// Platform C +// + + +#include "stdconst.h" +#include "m_sched.h" +#include "d_timer.h" +#include "d_timer.r" + + +void dTimerInit(void) +{ + TIMERInit; +} + + +ULONG dTimerRead(void) +{ + ULONG Tmp; + + TIMERRead(Tmp); + + return (Tmp); +} + + +void dTimerExit(void) +{ + TIMERExit; +} + diff --git a/AT91SAM7S256/Source/d_timer.h b/AT91SAM7S256/Source/d_timer.h new file mode 100644 index 0000000..bf01b25 --- /dev/null +++ b/AT91SAM7S256/Source/d_timer.h @@ -0,0 +1,26 @@ +// +// Date init 14.12.2004 +// +// Revision date $Date:: 16-05-06 10:18 $ +// +// Filename $Workfile:: d_timer.h $ +// +// Version $Revision:: 2 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/d_timer.h $ +// +// Platform C +// + + +#ifndef D_TIMER +#define D_TIMER + +void dTimerInit(void); +ULONG dTimerRead(void); +void dTimerExit(void); + +#endif + + + diff --git a/AT91SAM7S256/Source/d_timer.r b/AT91SAM7S256/Source/d_timer.r new file mode 100644 index 0000000..91e9f7b --- /dev/null +++ b/AT91SAM7S256/Source/d_timer.r @@ -0,0 +1,56 @@ +// +// Date init 14.12.2004 +// +// Revision date $Date:: 16-05-06 10:18 $ +// +// Filename $Workfile:: d_timer.r $ +// +// Version $Revision:: 11 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/d_timer.r $ +// +// Platform C +// + + +#ifdef SAM7S256 + + +#define MS_1_TIME ((OSC/16)/1000) + +static ULONG TimerValue; +static ULONG Timer1mS; + +/* PIT timer is used as main timer - timer interval is 1mS */ + +#define TIMERInit TimerValue = ((*AT91C_PITC_PIIR) & AT91C_PITC_CPIV);\ + Timer1mS = 0 + +#define TIMERRead(V) if (MS_1_TIME < ((((*AT91C_PITC_PIIR) & AT91C_PITC_CPIV) - TimerValue) & AT91C_PITC_CPIV))\ + {\ + TimerValue += MS_1_TIME;\ + TimerValue &= AT91C_PITC_CPIV;\ + Timer1mS++;\ + }\ + V = Timer1mS + +#define TIMERExit + + + +#endif //SAM7S256 + + + +#ifdef _WINDOWS + +#include +#include + +#define TIMERInit timeBeginPeriod(1); + +#define TIMERRead(V) (V) = timeGetTime(); + +#define TIMERExit timeEndPeriod(1); + +#endif //_WINDOWS diff --git a/AT91SAM7S256/Source/d_usb.c b/AT91SAM7S256/Source/d_usb.c new file mode 100644 index 0000000..b4b92f4 --- /dev/null +++ b/AT91SAM7S256/Source/d_usb.c @@ -0,0 +1,946 @@ +// +// Programmer +// +// Date init 14.12.2004 +// +// Reviser $Author:: Dkpechri $ +// +// Revision date $Date:: 19-07-06 10:02 $ +// +// Filename $Workfile:: d_usb.c $ +// +// Version $Revision:: 32 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/d_usb.c $ +// +// Platform C +// + +#include "stdconst.h" +#include "m_sched.h" +#include "d_usb.h" +#include "d_usb.r" + +#define ENDPOINT_OUT 1 // HOST write +#define ENDPOINT_OUT_SIZE 64 +#define ENDPOINT_IN 2 // HOST read +#define ENDPOINT_IN_SIZE 64 + +#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register +#define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable + + // Endpoint Control and Status Registers +#define AT91C_UDP_CSR0 ((AT91_REG *) 0xFFFB0030) // Endpoint 0 Control and Status Register +#define AT91C_UDP_CSR1 ((AT91_REG *) 0xFFFB0034) // Endpoint 1 Control and Status Register +#define AT91C_UDP_CSR2 ((AT91_REG *) 0xFFFB0038) // Endpoint 2 Control and Status Register +#define AT91C_UDP_CSR3 ((AT91_REG *) 0xFFFB003C) // Endpoint 3 Control and Status Register + + // Endpoint FIFO Data Registers +#define AT91C_UDP_FDR0 ((AT91_REG *) 0xFFFB0050) // Endpoint 0 FIFO Data Register +#define AT91C_UDP_FDR1 ((AT91_REG *) 0xFFFB0054) // Endpoint 1 FIFO Data Register +#define AT91C_UDP_FDR2 ((AT91_REG *) 0xFFFB0058) // Endpoint 2 FIFO Data Register +#define AT91C_UDP_FDR3 ((AT91_REG *) 0xFFFB005C) // Endpoint 3 FIFO Data Register + +const UBYTE DeviceDescriptor[] = { + /* Device descriptor */ + 0x12, // bLength, size of this descriptor = 18 entries + 0x01, // bDescriptorType = 1 = DEVICE + 0x00, // bcdUSBL, USB spec. vers. 2.0 + 0x02, // bcdUSBH, - + 0x00, // bDeviceClass + 0x00, // bDeviceSubclass + 0x00, // bDeviceProtocol + 0x08, // bMaxPacketSize0, EndPointZero packet size = 8 + 0x94, // idVendorL, LEGO Group + 0x06, // idVendorH, - + 0x02, // idProductL, LEGO USB IR Tower = 0x01 + 0x00, // idProductH, - + 0x00, // bcdDeviceL, device is version (zero) + 0x00, // bcdDeviceH, - + 0x00, // iManufacturer, index of string descriptor describing manufacturer + 0x00, // iProduct, index of string descriptor describing product + 0x01, // iSerialNumber, index of string descriptor describing the device's + // serial no. + 0x01 // bNumConfigs, number of possible configurations (only one) +}; + +/* USB standard request codes */ + +#define STD_GET_STATUS_ZERO 0x0080 +#define STD_GET_STATUS_INTERFACE 0x0081 +#define STD_GET_STATUS_ENDPOINT 0x0082 + +#define STD_CLEAR_FEATURE_ZERO 0x0100 +#define STD_CLEAR_FEATURE_INTERFACE 0x0101 +#define STD_CLEAR_FEATURE_ENDPOINT 0x0102 + +#define STD_SET_FEATURE_ZERO 0x0300 +#define STD_SET_FEATURE_INTERFACE 0x0301 +#define STD_SET_FEATURE_ENDPOINT 0x0302 + +#define STD_SET_ADDRESS 0x0500 +#define STD_GET_DESCRIPTOR 0x0680 +#define STD_SET_DESCRIPTOR 0x0700 +#define STD_GET_CONFIGURATION 0x0880 +#define STD_SET_CONFIGURATION 0x0900 +#define STD_GET_INTERFACE 0x0A81 +#define STD_SET_INTERFACE 0x0B01 +#define STD_SYNCH_FRAME 0x0C82 + +/* USB constants, masks etc. */ + +#define END_OF_BUS_RESET ((unsigned int) 0x1 << 12) +#define SUSPEND_INT ((unsigned int) 0x1 << 8) +#define SUSPEND_RESUME ((unsigned int) 0x1 << 9) +#define WAKEUP ((unsigned int) 0x1 << 13) + +//USB spec allows 500ms for control transfers +#define USB_MAX_TIMEOUT 500 + +static UBYTE UsbHandleList[MAX_HANDLES]; +static UBYTE UsbHandleCnt; +static UWORD RequestedData; +static UBYTE BrickNameKnown; +enum +{ + USB_NOT_CONFIGURED, + USB_CONFIGURED, + USB_CONFIGURED_BUT_SUSPENDED +}; +static UBYTE UsbConnectionStates; + + +const UBYTE ConfigurationDescriptor[] = { + /* ============== CONFIGURATION 1 =========== */ + /* Configuration 1 descriptor */ + 0x09, // bLength, descriptor size in bytes + 0x02, // bDescriptorType, The constant Configuration + 0x20, // wTotalLengthL for 2 EP + Control + 0x00, // wTotalLengthH - + 0x01, // bNumInterfaces, Number of interfaces in the configuration + 0x01, // bConfigurationValue, Identifier for + // Set_Configuration and Get_Configuration requests + 0x00, // iConfiguration, Index of string descriptor for the configuration + 0xC0, // bmAttributes, Bit 7 shall always be set. See e.g. page 108 in the book: + // "USB Complete" by Jan Axelson. June 2001 + // Self powered only bit 6 = 1 (zero = buspowered USB 1.1 and up) + 0x00, // MaxPower, power required (mA./2) We're SELF-POWERED, so ZERO + + /* Interface Descriptor */ + 0x09, // bLength, descriptor size in bytes + 0x04, // bDescriptorType, the constant 0x04 = "INTERFACE" + 0x00, // bInterfaceNumber, No. identifying this interface + 0x00, // bAlternateSetting, value used to get an alternative interface + 0x02, // bNumEndpoints, No. of supported endpoints in addition to endpoint 0 + 0xFF, // bInterfaceClass, Specifies the class code = VENDOR Specific + 0xFF, // bInterfaceSubclass, Specifies the subclass code = VENDOR Specific + 0xFF, // bInterfaceProtocol, protocol code = VENDOR Specific + 0x00, // iInterface, index of string descriptor for the interface + + /* Endpoint 1 descriptor */ + 0x07, // bLength, descriptor length incl. this = 7 + 0x05, // bDescriptorType + 0x01, // bEndpointAddress, Endpoint 01 - OUT + 0x02, // bmAttributes BULK + ENDPOINT_OUT_SIZE, // wMaxPacketSize + 0x00, // - + 0x00, // bInterval + + /* Endpoint 2 descriptor */ + 0x07, // bLength, descriptor length incl. this = 7 + 0x05, // bDescriptorType + 0x82, // bEndpointAddress, Endpoint 02 - IN + 0x02, // bmAttributes BULK + ENDPOINT_IN_SIZE, // wMaxPacketSize + 0x00, // - + 0x00 // bInterval +}; + +UBYTE SerialNumberDescriptor[] = +{ + 0x1A, // bLength, descriptor length incl. this = 16 bytes + 0x03, // bDescriptorType + + 0x31, 0x00, // MSD of Lap (Lap[2,3]) in UNICode + 0x32, 0x00, // Lap[4,5] + 0x33, 0x00, // Lap[6,7] + 0x34, 0x00, // Lap[8,9] + 0x35, 0x00, // Lap[10,11] + 0x36, 0x00, // Lap[12,13] + 0x37, 0x00, // Lap[14,15] + 0x38, 0x00, // LSD of Lap (Lap[16,17]) in UNICode + + 0x30, 0x00, // MSD of Nap (Nap[18,19]) in UNICode + 0x30, 0x00, // LSD of Nap (Nap[20,21]) in UNICode + + 0x39, 0x00, // MSD of Uap in UNICode + 0x30, 0x00 // LSD of Uap in UNICode +}; + +const UBYTE LangIdDescriptor[] = +{ + 0x04, // Length + 0x03, // Type, 3 = CONSTANT String + 0x09, // English + 0x04 // subcode = U.S. English +}; + +static UCHAR CurrentConfiguration; // Configured or not. We've only 1 conf. so... Boolean +static ULONG CurrentReceiveBank; // Used for keep track of the PING-PONG buffers + +ULONG g_UsbTimeoutCounter; + +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) + +void dUsbDisconnect(void) +{ + USBDisconnect; +} + +void dUsbConnect(void) +{ + USBConnect; +} + +void dUsbStartTimeoutTimer(void) +{ + g_UsbTimeoutCounter = 0; + + USBGetActualTime; +} + +// A longer version of the USB timer. +// Table 7-14 of the USB 2.0 spec allows up to 500ms for standard request completion. +UBYTE dUsbTimedOut(void) +{ + if(USBTimedOut) + { + g_UsbTimeoutCounter++; + + USBGetActualTime; + } + + return (g_UsbTimeoutCounter >= USB_MAX_TIMEOUT) ? TRUE : FALSE; +} + + +UBYTE ConvertHighToHex(UBYTE TempChar) +{ + TempChar = (TempChar >> 4) & 0x0F; + if (TempChar > 0x09) + TempChar += 0x37; + else + TempChar += 0x30; + return TempChar; +} + +UBYTE ConvertLowToHex(UBYTE TempChar) +{ + TempChar &= 0x0F; + if (TempChar > 0x09) + TempChar += 0x37; + else + TempChar += 0x30; + return TempChar; +} + +void dUsbStoreBtAddress(UBYTE *pBtAddress) +{ + UBYTE NoToConvert; + + // make the Lap human readable (hmmm Hexadecimal) + NoToConvert = *pBtAddress++; + SerialNumberDescriptor[2] = ConvertHighToHex(NoToConvert); + SerialNumberDescriptor[4] = ConvertLowToHex(NoToConvert); + + NoToConvert = *pBtAddress++; + SerialNumberDescriptor[6] = ConvertHighToHex(NoToConvert); + SerialNumberDescriptor[8] = ConvertLowToHex(NoToConvert); + + NoToConvert = *pBtAddress++; + SerialNumberDescriptor[10] = ConvertHighToHex(NoToConvert); + SerialNumberDescriptor[12] = ConvertLowToHex(NoToConvert); + + NoToConvert = *pBtAddress++; + SerialNumberDescriptor[14] = ConvertHighToHex(NoToConvert); + SerialNumberDescriptor[16] = ConvertLowToHex(NoToConvert); + + // make the Uap human readable (hmmm Hexadecimal) + NoToConvert = *pBtAddress++; + SerialNumberDescriptor[18] = ConvertHighToHex(NoToConvert); + SerialNumberDescriptor[20] = ConvertLowToHex(NoToConvert); + + // make the Nap human readable (hmmm Hexadecimal) + NoToConvert = *pBtAddress++; + SerialNumberDescriptor[22] = ConvertHighToHex(NoToConvert); + SerialNumberDescriptor[24] = ConvertLowToHex(NoToConvert); + + USBConnect; // We're ready to participate in the real world + BrickNameKnown = TRUE; // OK for referencing :-) +} + + +ULONG dUsbRead(UBYTE *pData, ULONG Length) +{ + ULONG PacketSize, NumberOfBytesReceived; + + NumberOfBytesReceived = 0; + + while (Length) // Wished read size from user (Max length) + { + if ( !(BrickNameKnown)) // Right Brick??? + break; + + if ( !(dUsbIsConfigured()) ) + break; // Not configured - no time to waste + + if ( (*AT91C_UDP_CSR1) & CurrentReceiveBank ) // Data packet rx'ed in Current bank? + { + + PacketSize = MIN((*AT91C_UDP_CSR1) >> 16, Length); // Normalize number of bytes available in FIFO + Length -= PacketSize; // Rest of data to receive + + if (PacketSize < ENDPOINT_OUT_SIZE) // If data less, we only have one loop + Length = 0; + + while(PacketSize--) // While more data in this very packet... + pData[NumberOfBytesReceived++] = *AT91C_UDP_FDR1; // Fill in buffer + + *AT91C_UDP_CSR1 &= ~(CurrentReceiveBank); // Reset current bank pointer + + if (CurrentReceiveBank == AT91C_UDP_RX_DATA_BK0) // Current Receive Bank 0? + CurrentReceiveBank = AT91C_UDP_RX_DATA_BK1; // We better use Bank 1 + else + CurrentReceiveBank = AT91C_UDP_RX_DATA_BK0; // Okay, go for Bank 0 :-) + + } + + else Length = 0; // Leave and let's use the CPU cycles in a better way + + } + + return NumberOfBytesReceived; // Size of actually received stuff + +} + +ULONG dUsbWrite( const UBYTE *pData, ULONG Length) +{ + ULONG CharsEachTx = 0; + + // Send the very first (or only) packet + CharsEachTx = MIN(Length, ENDPOINT_IN_SIZE); // First transmission size + Length -= CharsEachTx; // Adjust the rest of transmission size + + while (CharsEachTx--) // While more chars in this chunk + *AT91C_UDP_FDR2 = *pData++; // Get rid off it one by one + // Pushing the data into the UDP TX-fifo + *AT91C_UDP_CSR2 |= AT91C_UDP_TXPKTRDY; // Signal "DO THE TX" the stuff is delivered... + + while (Length) // While more bytes (I.e. packets) ín total transmission + { // Start filling the second bank + + CharsEachTx = MIN(Length, ENDPOINT_IN_SIZE); + Length -= CharsEachTx; // Adjust total length + + while (CharsEachTx--) // While more chars in this chunk + *AT91C_UDP_FDR2 = *pData++; + + dUsbStartTimeoutTimer(); + while ( !((*AT91C_UDP_CSR2) & AT91C_UDP_TXCOMP) ) // Wait for the the first bank to be sent + if (dUsbTimedOut() || !(dUsbIsConfigured()) ) // Communication down..... Bail out + return Length; // Invalid function - return job length not done + + (*AT91C_UDP_CSR2) &= ~(AT91C_UDP_TXCOMP); // Reset transmit interrupt flag + + while ((*AT91C_UDP_CSR2) & AT91C_UDP_TXCOMP); // Wait until flag (H/W) is reset + + (*AT91C_UDP_CSR2) |= AT91C_UDP_TXPKTRDY; // We're ready to send next bank + + } // Loop while bytes to tx + + dUsbStartTimeoutTimer(); // Arm the timeout timing + while ( !((*AT91C_UDP_CSR2) & AT91C_UDP_TXCOMP) ) // Wait for transmission to complete + if ( !(dUsbIsConfigured()) || dUsbTimedOut()) // Communication down..... Bail out + return Length; // Invalid function - return job length not done + + (*AT91C_UDP_CSR2) &= ~(AT91C_UDP_TXCOMP); // Reset Interrupt flag + + while ((*AT91C_UDP_CSR2) & AT91C_UDP_TXCOMP); // Wait for H/W to settle..... + + return Length; // Return byte count NOT x-ferred + +} + +static void dUsbSendStall(void) +{ + (*AT91C_UDP_CSR0) |= AT91C_UDP_FORCESTALL; // Set STALL condition + while ( !((*AT91C_UDP_CSR0) & AT91C_UDP_ISOERROR) ); // Wait until stall ack'ed + + (*AT91C_UDP_CSR0) &= ~(AT91C_UDP_FORCESTALL | AT91C_UDP_ISOERROR); // Reset again + while ((*AT91C_UDP_CSR0) & (AT91C_UDP_FORCESTALL | AT91C_UDP_ISOERROR)); // Wait until H/W really reset +} + +static void dUsbSendZeroLengthPackage(void) +{ + // Signal that buffer is ready to send + (*AT91C_UDP_CSR0) |= AT91C_UDP_TXPKTRDY; + + dUsbStartTimeoutTimer(); + + // Wait for ACK handshake from host + while ( !((*AT91C_UDP_CSR0) & AT91C_UDP_TXCOMP) && !dUsbTimedOut()); + // Clear handshake flag + (*AT91C_UDP_CSR0) &= ~(AT91C_UDP_TXCOMP); + while ((*AT91C_UDP_CSR0) & AT91C_UDP_TXCOMP); +} + +static void dUsbSendViaControl(const UBYTE *pData, ULONG Length) +{ + ULONG BytesToTx = 0; + AT91_REG Temp_Csr; + UBYTE HaveToTxZeroLength = FALSE; + UBYTE ZeroCouldBeNeeded = FALSE; + + // If the amount of data requested is more than what can be sent, a 0-length + // packet may be required + if (RequestedData > Length) + { + ZeroCouldBeNeeded = TRUE; // Exact same size would be interpreted as EOP @ host + } + + do + { + // The endpoint size is 8 bytes. Limit each data phase to 8 bytes. + + BytesToTx = MIN(Length, 8); + Length -= BytesToTx; + + // If this is the last data phase containing data, but the host requested + // more, a 0-byte packet will be needed to terminate the data phase. + if(ZeroCouldBeNeeded && (Length == 0) && (BytesToTx == 8)) + { + HaveToTxZeroLength = TRUE; + } + + // Copy data to endpoint buffer + while (BytesToTx--) + { + (*AT91C_UDP_FDR0) = *pData++; + } + + // Signal that buffer is ready to send + (*AT91C_UDP_CSR0) |= AT91C_UDP_TXPKTRDY; + + dUsbStartTimeoutTimer(); + + // Wait for ACK handshake from host + do + { + Temp_Csr = (*AT91C_UDP_CSR0); + + // Return if the status phase occurs before the packet is accepted + if (Temp_Csr & AT91C_UDP_RX_DATA_BK0) + { + // Clear the PKTRDY flag + (*AT91C_UDP_CSR0) &= ~(AT91C_UDP_TXPKTRDY); + // Clear the status phase flag + (*AT91C_UDP_CSR0) &= ~(AT91C_UDP_RX_DATA_BK0); + return; + } + } + while (!(Temp_Csr & AT91C_UDP_TXCOMP) && !dUsbTimedOut()); + + // Clear handshake flag + (*AT91C_UDP_CSR0) &= ~(AT91C_UDP_TXCOMP); + + while ((*AT91C_UDP_CSR0) & AT91C_UDP_TXCOMP); + + } while (Length); + + if(HaveToTxZeroLength) + { + dUsbSendZeroLengthPackage(); + } + + dUsbStartTimeoutTimer(); + + // Wait for Status Phase + while(!((*AT91C_UDP_CSR0) & AT91C_UDP_RX_DATA_BK0) && !dUsbTimedOut()); + // Clear flag + (*AT91C_UDP_CSR0) &= ~(AT91C_UDP_RX_DATA_BK0); +} + +static void dUsbEnumerate(void) +{ + UBYTE bmRequestType, bRequest; + UWORD wValue, wIndex, wLength, wStatus; + + if ( !((*AT91C_UDP_CSR0) & AT91C_UDP_RXSETUP) ) // No setup package available + return; + // Bytes are popped from the FIFO one by one + + bmRequestType = *AT91C_UDP_FDR0; + bRequest = *AT91C_UDP_FDR0; + wValue = ((*AT91C_UDP_FDR0) & 0xFF); + wValue |= ((*AT91C_UDP_FDR0) << 8); + wIndex = ((*AT91C_UDP_FDR0) & 0xFF); + wIndex |= ((*AT91C_UDP_FDR0) << 8); + wLength = ((*AT91C_UDP_FDR0) & 0xFF); + wLength |= ((*AT91C_UDP_FDR0) << 8); + + if (bmRequestType & 0x80) // If a DEVICE-TO-HOST request + { + *AT91C_UDP_CSR0 |= AT91C_UDP_DIR; // Enables data IN transaction in the control data stage + while ( !((*AT91C_UDP_CSR0) & AT91C_UDP_DIR) ); // Repeat until the DIR bit is set + } + + *AT91C_UDP_CSR0 &= ~AT91C_UDP_RXSETUP; // Device firmware has read the setup data in FIFO + while ( ((*AT91C_UDP_CSR0) & AT91C_UDP_RXSETUP) ); // Wait until bit cleared + + // Handle supported standard device request from Table 9-3 in USB specification Rev 2.0 + + switch ((bRequest << 8) | bmRequestType) + { + case STD_GET_DESCRIPTOR: + + RequestedData = wLength; + + if (wValue == 0x100) // Return Device Descriptor + { + if (sizeof(DeviceDescriptor) > wLength) + { + dUsbSendViaControl(DeviceDescriptor, wLength); + } + else + { + dUsbSendViaControl(DeviceDescriptor, sizeof(DeviceDescriptor)); + } + } + else if (wValue == 0x200) // Return Configuration Descriptor + { + if (sizeof(ConfigurationDescriptor) > wLength) + { + dUsbSendViaControl(ConfigurationDescriptor, wLength); + } + else + { + dUsbSendViaControl(ConfigurationDescriptor, sizeof(ConfigurationDescriptor)); + } + } + else if ((wValue & 0xF00) == 0x300) + { + switch(wValue & 0xFF) + { + case 0x00: + if ((sizeof(LangIdDescriptor)) > wLength) + { + dUsbSendViaControl(LangIdDescriptor, wLength); + } + else + { + dUsbSendViaControl(LangIdDescriptor, sizeof(LangIdDescriptor)); + } + break; + + case 0x01: + if ((sizeof(SerialNumberDescriptor)) > wLength) + { + dUsbSendViaControl(SerialNumberDescriptor, wLength); + } + else + { + dUsbSendViaControl(SerialNumberDescriptor, sizeof(SerialNumberDescriptor)); + } + break; + + default: + dUsbSendStall(); // Illegal request :-( + break; + } + } + else + dUsbSendStall(); // Illegal request :-( + + break; + + case STD_SET_ADDRESS: + + // Status IN transfer + (*AT91C_UDP_CSR0) |= AT91C_UDP_TXPKTRDY; + + dUsbStartTimeoutTimer(); + + while((*AT91C_UDP_CSR0) & AT91C_UDP_TXPKTRDY && !dUsbTimedOut()); + + *AT91C_UDP_FADDR = (AT91C_UDP_FEN | wValue); // Set device address. No check for invalid address. + // Function endpoint enabled. + *AT91C_UDP_GLBSTATE = (wValue) ? AT91C_UDP_FADDEN : 0; // If Device address != 0 then flag device + // in ADDRESS STATE + break; + + case STD_SET_CONFIGURATION: + + CurrentConfiguration = wValue; // Low byte of wValue = wanted configuration + UsbConnectionStates = USB_CONFIGURED; + dUsbSendZeroLengthPackage(); // Signal request processed OK + + *AT91C_UDP_GLBSTATE = (wValue) ? AT91C_UDP_CONFG : AT91C_UDP_FADDEN; // If wanted configuration != 0 + + *AT91C_UDP_CSR1 = (wValue) ? (AT91C_UDP_EPEDS | AT91C_UDP_EPTYPE_BULK_OUT) : 0; // Endpoint 1 enabled and set as BULK OUT + *AT91C_UDP_CSR2 = (wValue) ? (AT91C_UDP_EPEDS | AT91C_UDP_EPTYPE_BULK_IN) : 0; // Endpoint 2 enabled and set as BULK IN + *AT91C_UDP_CSR3 = (wValue) ? (AT91C_UDP_EPTYPE_INT_IN) : 0; // Endpoint 3 disabled and set as INTERRUPT IN + + break; + + case STD_GET_CONFIGURATION: // The actual configuration value is sent to HOST + + RequestedData = sizeof(CurrentConfiguration); + + dUsbSendViaControl((UBYTE *) &(CurrentConfiguration), sizeof(CurrentConfiguration)); + + break; + + case STD_GET_STATUS_ZERO: + + wStatus = 0x01; // Atmel has a 0x00, but we're not BUS-powered + RequestedData = sizeof(wStatus); + + dUsbSendViaControl((UBYTE *) &wStatus, sizeof(wStatus)); + + break; + + case STD_GET_STATUS_INTERFACE: // Everything reset to zero (reserved) + + wStatus = 0; + RequestedData = sizeof(wStatus); + + dUsbSendViaControl((UBYTE *) &wStatus, sizeof(wStatus)); + + break; + + case STD_GET_STATUS_ENDPOINT: + + wStatus = 0; + RequestedData = sizeof(wStatus); + wIndex &= 0x0F; // Mask the endpoint # + + if (((*AT91C_UDP_GLBSTATE) & AT91C_UDP_CONFG) && (wIndex <= 3)) // If device in CONFIGURED state + { // and ENDPOINT selected in valid range + + switch (wIndex) + { + + case 1: wStatus = ((*AT91C_UDP_CSR1) & AT91C_UDP_EPEDS) ? 0 : 1; // If an endpoint is halted, the HALT + // feature is set to 1, else reset + break; + + case 2: wStatus = ((*AT91C_UDP_CSR2) & AT91C_UDP_EPEDS) ? 0 : 1; + + break; + + case 3: wStatus = ((*AT91C_UDP_CSR3) & AT91C_UDP_EPEDS) ? 0 : 1; + + break; + default: + // We'll never come here, but we'll never say never....... + break; + } + + dUsbSendViaControl((UBYTE *) &wStatus, sizeof(wStatus)); + + } + + else if (((*AT91C_UDP_GLBSTATE) & AT91C_UDP_FADDEN) && (wIndex == 0)) + { + wStatus = ((*AT91C_UDP_CSR0) & AT91C_UDP_EPEDS) ? 0 : 1; // Return 1 if device in ADRESSED state + + dUsbSendViaControl((UBYTE *) &wStatus, sizeof(wStatus)); + } + else + + dUsbSendStall(); // Illegal request :-( + + break; + + case STD_SET_FEATURE_ZERO: + + dUsbSendStall(); // Illegal request :-( + + break; + + case STD_SET_FEATURE_INTERFACE: + + dUsbSendZeroLengthPackage(); // TextBook + + break; + + case STD_SET_FEATURE_ENDPOINT: + + wIndex &= 0x0F; + + if ((wValue == 0) && wIndex && (wIndex <= 3)) // Feature Selector = 0 ENDPOINT HALT and + { // endpoint isolated and validated + + switch (wIndex) + { + + case 1: (*AT91C_UDP_CSR1) = 0; + + break; + + case 2: (*AT91C_UDP_CSR2) = 0; + + break; + + case 3: (*AT91C_UDP_CSR3) = 0; + + break; + + default: + // We'll never come here, but we'll never say never....... + break; + + } + + dUsbSendZeroLengthPackage(); + + } + else + + dUsbSendStall(); // Illegal request :-( + + break; + + case STD_CLEAR_FEATURE_ZERO: + + dUsbSendStall(); // Illegal request :-( + + break; + + case STD_CLEAR_FEATURE_INTERFACE: + + dUsbSendZeroLengthPackage(); // No special + + break; + + case STD_CLEAR_FEATURE_ENDPOINT: + + wIndex &= 0x0F; + + if ((wValue == 0) && wIndex && (wIndex <= 3)) // Feature Selector = 0 => ENABLE A HALTED endpoint + { // and endpoint isolated and validated + + if (wIndex == 1) + (*AT91C_UDP_CSR1) = (AT91C_UDP_EPEDS | AT91C_UDP_EPTYPE_BULK_OUT); // On duty again + else if (wIndex == 2) + (*AT91C_UDP_CSR2) = (AT91C_UDP_EPEDS | AT91C_UDP_EPTYPE_BULK_IN); // - + else if (wIndex == 3) + (*AT91C_UDP_CSR3) = (AT91C_UDP_EPEDS | AT91C_UDP_EPTYPE_INT_IN); // - + + dUsbSendZeroLengthPackage(); + + } + else + + dUsbSendStall(); // Illegal request :-( + + break; + + default: + + dUsbSendStall(); // Illegal request :-( + + break; + } +} + +UBYTE dUsbIsConfigured(void) +{ + + if (*AT91C_UDP_ISR & END_OF_BUS_RESET) // If "End Of Bus Reset Interrupt" + { // Somebody fallen in the wire? ;-) + + + *AT91C_UDP_ICR = END_OF_BUS_RESET; // Reset "End Of Bus Reset Interrupt" + *AT91C_UDP_ICR = SUSPEND_RESUME; // State unknown after reset, so we better clear + *AT91C_UDP_ICR = WAKEUP; // As above + + CurrentConfiguration = 0; // We're new and ready + UsbConnectionStates = USB_NOT_CONFIGURED; + + *AT91C_UDP_RSTEP = 0xFFFFFFFF; // Reset all implemented endpoints "and a few more" + *AT91C_UDP_RSTEP = 0x0; // Restored as zeroes + // Below our main crash thing, if it is missing ;-) + CurrentReceiveBank = AT91C_UDP_RX_DATA_BK0; // Start the PING-PONG buffers at a known state and order + + *AT91C_UDP_FADDR = AT91C_UDP_FEN; // Set FEN in the Function Address Register + // USB device is able to receive and transfer data + + *AT91C_UDP_CSR0 = (AT91C_UDP_EPEDS | AT91C_UDP_EPTYPE_CTRL); // Configure endpoint 0 + // AT91C_UDP_EPEDS = Endpoint enable + // AT91C_UDP_EPTYPE_CTRL = Endpoint type CONTROL + } + + else if (*AT91C_UDP_ISR & SUSPEND_INT) + { + if (UsbConnectionStates == USB_CONFIGURED) + { + UsbConnectionStates = USB_CONFIGURED_BUT_SUSPENDED; + } + else + { + UsbConnectionStates = USB_NOT_CONFIGURED; + } + + *AT91C_UDP_ICR = SUSPEND_INT; + CurrentReceiveBank = AT91C_UDP_RX_DATA_BK0; // Start the PING-PONG buffers at a known state and order + } + + else if (*AT91C_UDP_ISR & SUSPEND_RESUME) + { + if (UsbConnectionStates == USB_CONFIGURED_BUT_SUSPENDED) + { + UsbConnectionStates = USB_CONFIGURED; + } + else + { + UsbConnectionStates = USB_NOT_CONFIGURED; + } + + *AT91C_UDP_ICR = WAKEUP; + *AT91C_UDP_ICR = SUSPEND_RESUME; + } + + else if (*AT91C_UDP_ISR & AT91C_UDP_EPINT0) // If "Endpoint 0 Interrupt" + { + *AT91C_UDP_ICR = AT91C_UDP_EPINT0; // Reset "Endpoint 0 Interrupt" + if (BrickNameKnown) + dUsbEnumerate(); // Let's date & exchange "personal data" + } + + if (UsbConnectionStates == USB_CONFIGURED) + { + return TRUE; + } + else + { + return FALSE; + } + +} + + +void dUsbInsertHandle(UBYTE Handle) +{ + UBYTE Tmp; + + Tmp = 0; + while((UsbHandleList[Tmp] != MAX_HANDLES) && (Tmp < MAX_HANDLES)) + { + Tmp++; + } + UsbHandleList[Tmp] = Handle; +} + +void dUsbRemoveHandle(UBYTE Handle) +{ + UBYTE Tmp; + + Tmp = 0; + while (Tmp < MAX_HANDLES) + { + if (Handle == UsbHandleList[Tmp]) + { + UsbHandleList[Tmp] = MAX_HANDLES; + } + Tmp++; + } +} + +UWORD dUsbGetFirstHandle(void) +{ + UWORD RtnVal; + + UsbHandleCnt = 0; + RtnVal = dUsbGetNextHandle(); + + return(RtnVal); +} + +UWORD dUsbGetNextHandle(void) +{ + UBYTE Tmp; + UWORD RtnVal; + + RtnVal = 0; + Tmp = UsbHandleCnt; + while((Tmp < MAX_HANDLES) && (MAX_HANDLES == UsbHandleList[Tmp])) + { + Tmp++; + } + UsbHandleCnt = Tmp + 1; + + if (Tmp < MAX_HANDLES) + { + RtnVal |= UsbHandleList[Tmp]; + } + else + { + RtnVal = 0x8100; + } + + return(RtnVal); +} + +UWORD dUsbCheckConnection(void) +{ + UWORD ADValue; + UWORD Return; + + Return = FALSE; + USBReadADCValue(&ADValue); + + if (ADValue > 512) + { + Return = TRUE; + } + return(Return); +} + +void dUsbInit(void) +{ + UBYTE Tmp; + + // We could come from a SAMBA session and then we need + // to "introduce ourself in a polite way for the PNP manager + // We will pull the carpet and start a new session by removing + // the pull up of the D+ wire + + BrickNameKnown = FALSE; + dUsbStartTimeoutTimer(); // Let H/W settle + dUsbDisconnect(); // Pull the carpet + while(!USBTimedOut); // wait 1 mS. + + USBHwInit; // New session + + CurrentConfiguration = 0; // We're new born + UsbConnectionStates = USB_NOT_CONFIGURED; + CurrentReceiveBank = AT91C_UDP_RX_DATA_BK0; // Always start from Bank 0 + RequestedData = 0; + + for(Tmp = 0; Tmp < MAX_HANDLES; Tmp++) + { + UsbHandleList[Tmp] = MAX_HANDLES; + } +} + +void dUsbResetConfig(void) +{ + CurrentConfiguration = 0; // We've lost the connection + UsbConnectionStates = USB_NOT_CONFIGURED; +} + +void dUsbExit(void) +{ +// USBExit; +} diff --git a/AT91SAM7S256/Source/d_usb.h b/AT91SAM7S256/Source/d_usb.h new file mode 100644 index 0000000..3a176b3 --- /dev/null +++ b/AT91SAM7S256/Source/d_usb.h @@ -0,0 +1,51 @@ +// +// Programmer +// +// Date init 14.12.2004 +// +// Reviser $Author:: Dkpechri $ +// +// Revision date $Date:: 19-07-06 10:02 $ +// +// Filename $Workfile:: d_usb.h $ +// +// Version $Revision:: 10 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/d_usb.h $ +// +// Platform C +// + +#ifndef D_USB +#define D_USB + +//* public constants + +// LOW level commands + +#define OPENFILEWRITE 0x01 +#define OPENFILEREAD 0x02 +#define WRITEFILE 0x03 +#define CLOSEFILE 0x04 + +// Low level direct command escape + +#define DIRECTCOMMAND 0x80 // Escape sent to the Loader +#define USB_TIMEOUT 0x0BB8 // Equals approx. 1 mS. Used for recover a "broken" cable situation + +//* external function description + +void dUsbInit(void); +void dUsbExit(void); +ULONG dUsbRead(UBYTE *pData, ULONG Length); +ULONG dUsbWrite( const UBYTE *pData, ULONG Length); +UBYTE dUsbIsConfigured(void); + +void dUsbInsertHandle(UBYTE Handle); +void dUsbRemoveHandle(UBYTE Handle); +UWORD dUsbGetFirstHandle(void); +UWORD dUsbGetNextHandle(void); +UWORD dUsbCheckConnection(void); +void dUsbResetConfig(void); +void dUsbStoreBtAddress(UBYTE *pBtAddress); +#endif diff --git a/AT91SAM7S256/Source/d_usb.r b/AT91SAM7S256/Source/d_usb.r new file mode 100644 index 0000000..a3c3284 --- /dev/null +++ b/AT91SAM7S256/Source/d_usb.r @@ -0,0 +1,65 @@ +// +// Programmer +// +// Date init 14.12.2004 +// +// Reviser $Author:: Dkpechri $ +// +// Revision date $Date:: 19-07-06 10:02 $ +// +// Filename $Workfile:: d_usb.r $ +// +// Version $Revision:: 9 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/d_usb.r $ +// +// Platform C +// + +#ifdef SAM7S256 + +#ifdef PROTOTYPE_PCB_3 +#define ENABLEUsbPU *AT91C_PIOA_PER = AT91C_PIO_PA16; /* PIO allowed to control bit 16 */\ + *AT91C_PIOA_OER = AT91C_PIO_PA16; /* Output pin 16 enabled */\ + *AT91C_PIOA_SODR = AT91C_PIO_PA16 /* Pin 16 set = enable USB pull-up */ +#endif + +#ifdef PROTOTYPE_PCB_4 +#define ENABLEUsbPU *AT91C_PIOA_PER = AT91C_PIO_PA16; /* PIO allowed to control bit 16 */\ + *AT91C_PIOA_OER = AT91C_PIO_PA16; /* Output pin 16 enabled */\ + *AT91C_PIOA_CODR = AT91C_PIO_PA16 /* Pin 16 clear = enable USB pull-up */ + +#define DISABLEUsbPU *AT91C_PIOA_PER = AT91C_PIO_PA16; /* PIO allowed to control bit 16 */\ + *AT91C_PIOA_OER = AT91C_PIO_PA16; /* Output pin 16 enabled */\ + *AT91C_PIOA_SODR = AT91C_PIO_PA16 /* Pin 16 set = disable USB pull-up */ +#endif + + +#define USBHwInit *AT91C_CKGR_PLLR |= AT91C_CKGR_USBDIV_1; /* Set the PLL USB Divider (96MHz/2) */\ + *AT91C_PMC_SCER = AT91C_PMC_UDP; /* WRITE-ONLY REG! Enables the 48MHz USB clock UDPCK (SysClk) */\ + *AT91C_PMC_PCER = (1 << AT91C_ID_UDP); /* WRITE-ONLY REG! Enable USB clock (Peripheral Clock) */\ + \ + /* Enable UDP PullUp (USB_DP_PUP) : enable & Clear of the corresponding PIO */ \ + \ + /* Removed 22022006 14:20 pc ENABLEUsbPU BlueCore delay , No pull up before OK serial-no rec. from B.C.*/ + + +static ULONG USBTimeOut; + +#define USBTimedOut (USB_TIMEOUT < ((((*AT91C_PITC_PIIR) & AT91C_PITC_CPIV) - USBTimeOut) & AT91C_PITC_CPIV)) + +#define USBGetActualTime USBTimeOut = ((*AT91C_PITC_PIIR) & AT91C_PITC_CPIV) + +#define USBReadADCValue(ADValue) *ADValue = *AT91C_ADC_CDR4 + +#define USBExit + +#define USBDisconnect DISABLEUsbPU + +#define USBConnect ENABLEUsbPU + +#endif + +#ifdef PCWIN + +#endif diff --git a/AT91SAM7S256/Source/m_sched.c b/AT91SAM7S256/Source/m_sched.c new file mode 100644 index 0000000..bc394a5 --- /dev/null +++ b/AT91SAM7S256/Source/m_sched.c @@ -0,0 +1,94 @@ +// +// Date init 14.12.2004 +// +// Revision date $Date:: 16-05-06 10:15 $ +// +// Filename $Workfile:: m_sched.c $ +// +// Version $Revision:: 14 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/m_sched.c $ +// +// Platform C +// + + +#define INCLUDE_OS + +#define MODULEHEADERS 32 + +#include "stdconst.h" +#include "modules.h" +#include "m_sched.h" + +#include "c_comm.h" +#include "c_input.h" +#include "c_button.h" +#include "c_loader.h" +#include "c_sound.h" +#include "c_display.h" +#include "c_lowspeed.h" +#include "c_output.h" +#include "c_cmd.h" +#include "c_cmd.iom" +#include "c_ioctrl.h" +#include "c_ui.h" + + +static const HEADER* pModuleHeaders[MODULEHEADERS] = +{ + &cComm, + &cInput, + &cButton, + &cDisplay, + &cLoader, + &cLowSpeed, + &cOutput, + &cSound, + &cIOCtrl, + &cCmd, + &cUi, + 0 +}; + + +void mSchedInit(void) +{ + UWORD Tmp; + + Tmp = 0; + while(pModuleHeaders[Tmp]) + { + (*pModuleHeaders[Tmp]).cInit((void*) pModuleHeaders); + Tmp++; + } +} + + +UBYTE mSchedCtrl(void) +{ + UWORD Tmp; + + Tmp = 0; + while(pModuleHeaders[Tmp]) + { + (*pModuleHeaders[Tmp]).cCtrl(); + Tmp++; + } + + return(((IOMAPCMD*)(pModuleHeaders[ENTRY_CMD]->pIOMap))->Awake); +} + + +void mSchedExit(void) +{ + UWORD Tmp; + + Tmp = 0; + while(pModuleHeaders[Tmp]) + { + (*pModuleHeaders[Tmp]).cExit(); + Tmp++; + } +} + diff --git a/AT91SAM7S256/Source/m_sched.h b/AT91SAM7S256/Source/m_sched.h new file mode 100644 index 0000000..6bf5a07 --- /dev/null +++ b/AT91SAM7S256/Source/m_sched.h @@ -0,0 +1,135 @@ +// +// Date init 14.12.2004 +// +// Revision date $Date:: 16-05-06 10:15 $ +// +// Filename $Workfile:: m_sched.h $ +// +// Version $Revision:: 20 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/m_sched.h $ +// +// Platform C +// + + + +#define APPNAME "LMS01" + +#define COPYRIGHTSTRING "Let's samba nxt arm in arm, (c)LEGO System A/S" + +#define COPYRIGHTSTRINGLENGTH 46 /* Number of bytes checked in COPYRIGHTSTRING */ + + +#ifndef _WINDOWS + +#define SAM7SXX + +#ifdef SAM7SXX + + // + // Platform ATMEL ARM7 + // + // + +#define OSC 48054850L +#define SYSFREQ 1000 + + +#include "..\SAM7S256\include\sam7s256.h" + +#if defined (PROTOTYPE_PCB_3) || (PROTOTYPE_PCB_4) + +#define TSTPin AT91C_PIO_PA27 + +#else + +#define TSTPin AT91C_PIO_PA31 + +#endif + +#define TSTInit {\ + *AT91C_PIOA_PER = TSTPin;\ + *AT91C_PIOA_OER = TSTPin;\ + } + +#define TSTOn {\ + *AT91C_PIOA_SODR = TSTPin;\ + } + +#define TSTOff {\ + *AT91C_PIOA_CODR = TSTPin;\ + } + +#define TSTExit {\ + *AT91C_PIOA_ODR = TSTPin;\ + *AT91C_PIOA_CODR = TSTPin;\ + } + +/* Defines related to loader */ +#define MAX_HANDLES 16 + + +/* Defines related to I2c */ +#define BYTES_TO_TX 8 +#define BYTES_TO_RX 12 + +enum +{ + NOS_OF_AVR_OUTPUTS = 4, + NOS_OF_AVR_BTNS = 4, + NOS_OF_AVR_INPUTS = 4 +}; + +typedef struct +{ + UWORD AdValue[NOS_OF_AVR_INPUTS]; + UWORD Buttons; + UWORD Battery; +}IOFROMAVR; + +typedef struct +{ + UBYTE Power; + UBYTE PwmFreq; + SBYTE PwmValue[NOS_OF_AVR_OUTPUTS]; + UBYTE OutputMode; + UBYTE InputPower; +}IOTOAVR; + +extern IOTOAVR IoToAvr; +extern IOFROMAVR IoFromAvr; + +#ifdef INCLUDE_OS + +#include "..\SAM7S256\include\sam7s256.c" + +IOTOAVR IoToAvr; +IOFROMAVR IoFromAvr; + +#endif + +#endif + +#else + + // + // Platform PCWIN + // + // + +#define OSC 1192000L +#define SYSFREQ 1000 + +#include "Pcwin.h" + +#ifdef INCLUDE_OS + +#include "Pcwin.c" + +#endif + +#endif + + + diff --git a/AT91SAM7S256/Source/modules.h b/AT91SAM7S256/Source/modules.h new file mode 100644 index 0000000..6060800 --- /dev/null +++ b/AT91SAM7S256/Source/modules.h @@ -0,0 +1,343 @@ +// +// Programmer +// +// Date init 14.12.2004 +// +// Reviser $Author:: Dkflebun $ +// +// Revision date $Date:: 5-02-07 13:36 $ +// +// Filename $Workfile:: modules.h $ +// +// Version $Revision:: 49 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/modules.h $ +// +// Platform C +// + +#ifndef MODULE_HEADER +#define MODULE_HEADER + +#define FILENAME_LENGTH 19 // zero termination not included +#define FILEHEADER_LENGTH 8 // all simple file headers +#define DISPLAYLINE_LENGTH 16 // zero termination not included +#define ON_BRICK_PROGRAMSTEPS 5 // no of on brick program steps +#define STATUSTEXT_SIZE 8 // zero termination not included + +#define TXT_SOUND_EXT "rso" // Sound filename extension +#define TXT_LMS_EXT "rxe" // Mindstorms program filename extension +#define TXT_NXT_EXT "rpg" // Program filename extension +#define TXT_TRYME_EXT "rtm" // Try me program filename extension +#define TXT_DATA_EXT "rdt" // Datalog filename extension +#define TXT_MENU_EXT "rms" // Menu system filename extension (hidden) +#define TXT_SYS_EXT "sys" // System filename extension (hidden) +#define TXT_TMP_EXT "tmp" // Temporary filename extension (hidden) + + +/* Error codes from then Loader */ +enum +{ + SUCCESS = 0x0000, + INPROGRESS = 0x0001, + REQPIN = 0x0002, + NOMOREHANDLES = 0x8100, + NOSPACE = 0x8200, + NOMOREFILES = 0x8300, + EOFEXSPECTED = 0x8400, + ENDOFFILE = 0x8500, + NOTLINEARFILE = 0x8600, + FILENOTFOUND = 0x8700, + HANDLEALREADYCLOSED = 0x8800, + NOLINEARSPACE = 0x8900, + UNDEFINEDERROR = 0x8A00, + FILEISBUSY = 0x8B00, + NOWRITEBUFFERS = 0x8C00, + APPENDNOTPOSSIBLE = 0x8D00, + FILEISFULL = 0x8E00, + FILEEXISTS = 0x8F00, + MODULENOTFOUND = 0x9000, + OUTOFBOUNDERY = 0x9100, + ILLEGALFILENAME = 0x9200, + ILLEGALHANDLE = 0x9300, + BTBUSY = 0x9400, + BTCONNECTFAIL = 0x9500, + BTTIMEOUT = 0x9600, + FILETX_TIMEOUT = 0x9700, + FILETX_DSTEXISTS = 0x9800, + FILETX_SRCMISSING = 0x9900, + FILETX_STREAMERROR = 0x9A00, + FILETX_CLOSEERROR = 0x9B00 +}; + + +/* interface between comm and BC4 */ +enum +{ + MSG_BEGIN_INQUIRY, + MSG_CANCEL_INQUIRY, + MSG_CONNECT, + MSG_OPEN_PORT, + MSG_LOOKUP_NAME, + MSG_ADD_DEVICE, + MSG_REMOVE_DEVICE, + MSG_DUMP_LIST, + MSG_CLOSE_CONNECTION, + MSG_ACCEPT_CONNECTION, + MSG_PIN_CODE, + MSG_OPEN_STREAM, + MSG_START_HEART, + MSG_HEARTBEAT, + MSG_INQUIRY_RUNNING, + MSG_INQUIRY_RESULT, + MSG_INQUIRY_STOPPED, + MSG_LOOKUP_NAME_RESULT, + MSG_LOOKUP_NAME_FAILURE, + MSG_CONNECT_RESULT, + MSG_RESET_INDICATION, + MSG_REQUEST_PIN_CODE, + MSG_REQUEST_CONNECTION, + MSG_LIST_RESULT, + MSG_LIST_ITEM, + MSG_LIST_DUMP_STOPPED, + MSG_CLOSE_CONNECTION_RESULT, + MSG_PORT_OPEN_RESULT, + MSG_SET_DISCOVERABLE, + MSG_CLOSE_PORT, + MSG_CLOSE_PORT_RESULT, + MSG_PIN_CODE_ACK, + MSG_DISCOVERABLE_ACK, + MSG_SET_FRIENDLY_NAME, + MSG_SET_FRIENDLY_NAME_ACK, + MSG_GET_LINK_QUALITY, + MSG_LINK_QUALITY_RESULT, + MSG_SET_FACTORY_SETTINGS, + MSG_SET_FACTORY_SETTINGS_ACK, + MSG_GET_LOCAL_ADDR, + MSG_GET_LOCAL_ADDR_RESULT, + MSG_GET_FRIENDLY_NAME, + MSG_GET_DISCOVERABLE, + MSG_GET_PORT_OPEN, + MSG_GET_FRIENDLY_NAME_RESULT, + MSG_GET_DISCOVERABLE_RESULT, + MSG_GET_PORT_OPEN_RESULT, + MSG_GET_VERSION, + MSG_GET_VERSION_RESULT, + MSG_GET_BRICK_STATUSBYTE_RESULT, + MSG_SET_BRICK_STATUSBYTE_RESULT, + MSG_GET_BRICK_STATUSBYTE, + MSG_SET_BRICK_STATUSBYTE +}; + +#define SIZE_OF_BT_NAME 16 +#define SIZE_OF_BRICK_NAME 8 +#define SIZE_OF_CLASS_OF_DEVICE 4 +#define SIZE_OF_BT_PINCODE 16 +#define SIZE_OF_BDADDR 7 + + +enum +{ + ENTRY_COMM, + ENTRY_INPUT, + ENTRY_BUTTON, + ENTRY_DISPLAY, + ENTRY_LOADER, + ENTRY_LOWSPEED, + ENTRY_OUTPUT, + ENTRY_SOUND, + ENTRY_IOCTRL, + ENTRY_CMD, + ENTRY_UI, + ENTRY_FREE2, + ENTRY_FREE3, + ENTRY_FREE4, + ENTRY_FREE5 +}; + +typedef struct +{ + ULONG ModuleID; + UBYTE ModuleName[FILENAME_LENGTH + 1]; + void (*cInit)(void* pHeader); + void (*cCtrl)(void); + void (*cExit)(void); + void *pIOMap; + void *pVars; + UWORD IOMapSize; + UWORD VarsSize; + UWORD ModuleSize; +}HEADER; + +enum +{ + FILEFORMAT_SOUND = 0x0100, // rso + FILEFORMAT_SOUND_COMPRESSED = 0x0101, // rso + FILEFORMAT_BITMAP = 0x0200, + FILEFORMAT_FONT = 0x0300, + FILEFORMAT_ICON = 0x0400, + FILEFORMAT_TEXT = 0x0500, + FILEFORMAT_MELODY = 0x0600, + FILEFORMAT_MENU = 0x0700, // rms + FILEFORMAT_PROGRAM = 0x0800, // rpg + FILEFORMAT_DATALOG = 0x0900 // rdt +}; + +typedef struct +{ + UBYTE FormatMsb; + UBYTE FormatLsb; + UBYTE DateBytesMsb; + UBYTE DataBytesLsb; + UBYTE SampleRateMsb; + UBYTE SampleRateLsb; + UBYTE PlayModeMsb; + UBYTE PlayModeLsb; + UBYTE Data[]; +} +SOUND; + +typedef struct +{ + UBYTE FormatMsb; + UBYTE FormatLsb; + UBYTE DateBytesMsb; + UBYTE DataBytesLsb; + UBYTE StartX; + UBYTE StartY; + UBYTE PixelsX; + UBYTE PixelsY; + UBYTE Data[]; +} +BMPMAP; + +typedef struct +{ + UBYTE FormatMsb; + UBYTE FormatLsb; + UBYTE DataBytesMsb; + UBYTE DataBytesLsb; + UBYTE ItemsX; + UBYTE ItemsY; + UBYTE ItemPixelsX; + UBYTE ItemPixelsY; + UBYTE Data[]; +} +FONT; + +typedef struct +{ + UBYTE FormatMsb; + UBYTE FormatLsb; + UBYTE DataBytesMsb; + UBYTE DataBytesLsb; + UBYTE ItemsX; + UBYTE ItemsY; + UBYTE ItemPixelsX; + UBYTE ItemPixelsY; + UBYTE Data[]; +} +ICON; + +typedef struct +{ + UBYTE FormatMsb; + UBYTE FormatLsb; + UBYTE DataBytesMsb; + UBYTE DataBytesLsb; + UBYTE ItemsX; + UBYTE ItemsY; + UBYTE ItemCharsX; + UBYTE ItemCharsY; + UBYTE Data[]; +} +TXT; + +typedef struct +{ + UBYTE FormatMsb; + UBYTE FormatLsb; + UBYTE DateBytesMsb; + UBYTE DataBytesLsb; + UBYTE TonesMsb; + UBYTE TonesLsb; + UBYTE PlayModeMsb; + UBYTE PlayModeLsb; + UBYTE Data[]; // Data[0] = FreqMsb, Data[1] = FreqLsb, Data[2] = DurationMsb, Data[3] = DurationLsb .... +} +MELODY; + +typedef struct +{ + UBYTE FormatMsb; + UBYTE FormatLsb; + UBYTE DataBytesMsb; + UBYTE DataBytesLsb; + UBYTE Steps; + UBYTE NotUsed1; + UBYTE NotUsed2; + UBYTE NotUsed3; + UBYTE Data[]; +} +PROGRAM; + +typedef struct +{ + UBYTE FormatMsb; + UBYTE FormatLsb; + UBYTE DataBytesMsb; + UBYTE DataBytesLsb; + UBYTE TotalTime3; + UBYTE TotalTime2; + UBYTE TotalTime1; + UBYTE TotalTime0; + UBYTE Data[]; +} +DATALOG; + +#define DATALOG_FILE_LENGTH 64000L// Max datalog file size +#define DATALOG_HEADER_LENGTH 9 // Datalog sensor header length [Bytes] +#define DATALOG_DATA_LENGTH 5 // Datalog sensor data length [Bytes] + +#define ICON_TEXTLNG 15 // 15 characters +#define ICON_IMAGESIZE 72 // 24 x 24 pixels +#define MAX_MENUITEMS 256 + +typedef struct +{ + UBYTE ItemId67; // Menu item id + UBYTE ItemId45; // Menu item id + UBYTE ItemId23; // Menu item id + UBYTE ItemId01; // Menu item id + UBYTE SpecialMask3; // Menu item special mask (TBD) + UBYTE SpecialMask2; // Menu item special mask (TBD) + UBYTE SpecialMask1; // Menu item special mask (TBD) + UBYTE SpecialMask0; // Menu item special mask (TBD) + UBYTE FunctionIndex; // Menu item enter function call index + UBYTE FunctionParameter; // Menu item enter function parameter + UBYTE FileLoadNo; // Menu item enter menu file load no + UBYTE NextMenu; // Menu item enter next level menu no + UBYTE IconText[ICON_TEXTLNG + 1]; // Menu item icon text string + UBYTE IconImageNo; // Menu item icon image number +}MENUITEM; + +typedef struct +{ + UBYTE FormatMsb; + UBYTE FormatLsb; + UBYTE DataBytesMsb; + UBYTE DataBytesLsb; + UBYTE ItemSize; + UBYTE Items; + UBYTE ItemPixelsX; + UBYTE ItemPixelsY; + MENUITEM Data[MAX_MENUITEMS]; +} +MENU; + +typedef UBYTE (*FUNCTION)(UBYTE); // Menu function type + +#endif + + + diff --git a/AT91SAM7S256/Source/stdconst.h b/AT91SAM7S256/Source/stdconst.h new file mode 100644 index 0000000..81bf972 --- /dev/null +++ b/AT91SAM7S256/Source/stdconst.h @@ -0,0 +1,48 @@ +// +// Programmer +// +// Date init 14.12.2004 +// +// Reviser $Author:: Us8jamlo $ +// +// Revision date $Date:: 3/04/05 2:59p $ +// +// Filename $Workfile:: stdconst.h $ +// +// Version $Revision:: 3 $ +// +// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/stdconst.h $ +// +// Platform C +// + + +#ifndef STDCONST +#define STDCONST + +#ifndef NULL +#define NULL ((void *)0) +#endif + +#define TRUE 1 +#define FALSE 0 + +typedef unsigned char UCHAR; +typedef unsigned short USHORT; + +typedef unsigned char UBYTE; +typedef signed char SBYTE; +typedef unsigned short int UWORD; +typedef signed short int SWORD; +typedef unsigned long ULONG; +typedef signed long SLONG; + +typedef ULONG* PULONG; +typedef USHORT* PUSHORT; +typedef UCHAR* PUCHAR; +typedef char* PSZ; + +#define BASETYPES + + +#endif diff --git a/ATmega48/MEGA48/Include/atmega48.c b/ATmega48/MEGA48/Include/atmega48.c new file mode 100644 index 0000000..9583438 --- /dev/null +++ b/ATmega48/MEGA48/Include/atmega48.c @@ -0,0 +1,31 @@ +// +// Programmer +// +// Date init 14.12.2004 +// +// Reviser $Author:: Dktochpe $ +// +// Revision date $Date:: 17-02-05 11:26 $ +// +// Filename $Workfile:: atmega48.c $ +// +// Version $Revision:: 2 $ +// +// Archive $Archive:: /LMS2006/Sys01/Ioctrl/Firmware/Mega48/Include/ $ +// +// Platform C +// + + +void main(void) +{ + HARDWAREInit; + mSchedInit(); + while(TRUE == mSchedCtrl()) + { + OSWatchdogWrite; + } + mSchedExit(); + HARDWAREExit; +} + diff --git a/ATmega48/MEGA48/Include/atmega48.h b/ATmega48/MEGA48/Include/atmega48.h new file mode 100644 index 0000000..d6b75b4 --- /dev/null +++ b/ATmega48/MEGA48/Include/atmega48.h @@ -0,0 +1,66 @@ +// +// Programmer +// +// Date init 14.12.2004 +// +// Reviser $Author:: Dktochpe $ +// +// Revision date $Date:: 2-09-05 14:37 $ +// +// Filename $Workfile:: atmega48.h $ +// +// Version $Revision:: 7 $ +// +// Archive $Archive:: /LMS2006/Sys01/Ioctrl/Firmware/Mega48/Include/ $ +// +// Platform C +// + + +#ifndef ATMEGA88_H +#define ATMEGA88_H + +#include "iom48.h" +#include "inavr.h" + + +#define ATMEGAX8 + + +#define HARDWAREReset {\ + void (*Reset)(void);\ + Reset = (void*)0x0000;\ + Reset();\ + } + +#define HARDWAREInit {\ + SMCR = 0x00;\ + CLKPR = 0x80;\ + CLKPR = 0x00;\ + __enable_interrupt();\ + } + + +#define HARDWAREExit {\ + ADCSRA = 0x00;\ + SMCR = 0x05;\ + __sleep();\ + HARDWAREReset;\ + } + +#define OSIntEnable() {\ + __enable_interrupt();\ + } + +#define OSIntDisable() {\ + __disable_interrupt();\ + } + +#define OSWatchdogWrite + +void mSchedInit(void); +UBYTE mSchedCtrl(void); +void mSchedExit(void); + + +#endif diff --git a/ATmega48/MEGA48/Include/inavr.h b/ATmega48/MEGA48/Include/inavr.h new file mode 100644 index 0000000..bf1ecfc --- /dev/null +++ b/ATmega48/MEGA48/Include/inavr.h @@ -0,0 +1,213 @@ +/************************************************************** + ** - INAVR.H - + ** + ** Intrinsics for iccAVR + ** + ** Used with iccAVR. + ** + ** Copyright IAR Systems 1999. All rights reserved. + ** + ** File version: $Revision: 1 $ + ** + **************************************************************/ + +#ifndef __INAVR_H +#define __INAVR_H + +#ifndef __ICCAVR__ +#error This file should only be compiled with iccAVR +#endif /* __ICCAVR__ */ + +__intrinsic void __no_operation(void); +__intrinsic void __enable_interrupt(void); +__intrinsic void __disable_interrupt(void); +__intrinsic void __sleep(void); +__intrinsic void __watchdog_reset(void); +#define __clear_watchdog_timer() __watchdog_reset() +#pragma language=extended +__intrinsic unsigned char __load_program_memory(const unsigned char __flash *); +#ifdef __HAS_ELPM__ +__intrinsic unsigned char __extended_load_program_memory( + const unsigned char __farflash *); +#endif +#pragma language=default + +__intrinsic void __insert_opcode(unsigned short op); + +#if __MEMORY_MODEL__ == 4 +#if __CPU__ < 2 +#define __STR_MATTR__ __flash +#else +#define __STR_MATTR__ __hugeflash +#endif +#else +#define __STR_MATTR__ +#endif + + +__intrinsic void __require(void *); + +__intrinsic void __delay_cycles(unsigned long); + +__intrinsic unsigned char __save_interrupt(void); +#define __get_interrupt_state() __save_interrupt() + +__intrinsic void __restore_interrupt(unsigned char); +#define __set_interrupt_state(STATE) __restore_interrupt(STATE) + +__intrinsic unsigned char __swap_nibbles(unsigned char); + +__intrinsic void __indirect_jump_to(unsigned long); + +#ifdef __HAS_ENHANCED_CORE__ + +#ifdef __HAS_MUL__ +__intrinsic unsigned int __multiply_unsigned(unsigned char, unsigned char); +__intrinsic signed int __multiply_signed(signed char, signed char); +__intrinsic signed int __multiply_signed_with_unsigned(signed char, unsigned char); + +__intrinsic unsigned int __fractional_multiply_unsigned(unsigned char, unsigned char); +__intrinsic signed int __fractional_multiply_signed(signed char, signed char); +__intrinsic signed int __fractional_multiply_signed_with_unsigned(signed char, signed char); +#endif + +#pragma language=extended + +/* SPM */ +__intrinsic void __DataToR0ByteToSPMCR_SPM(unsigned char data, + unsigned char byte); +__intrinsic void __AddrToZByteToSPMCR_SPM(void __flash* addr, + unsigned char byte); +__intrinsic void __AddrToZWordToR1R0ByteToSPMCR_SPM(void __flash* addr, + unsigned short word, + unsigned char byte); + +#define _SPM_LOCKBITS(Data) \ + __DataToR0ByteToSPMCR_SPM((Data), 0x09) + +#define _SPM_ERASE(Addr) \ + __AddrToZByteToSPMCR_SPM((void __flash*)(Addr), 0x03) + +#define _SPM_FILLTEMP(Addr,Data) \ + __AddrToZWordToR1R0ByteToSPMCR_SPM((void __flash*)(Addr), (Data), 0x01) + +#define _SPM_PAGEWRITE(Addr) \ + __AddrToZByteToSPMCR_SPM((void __flash*)(Addr), (0x05)) + + +__intrinsic unsigned char __AddrToZByteToSPMCR_LPM(void __flash* addr, + unsigned char byte); + +#define _SPM_GET_LOCKBITS() \ + __AddrToZByteToSPMCR_LPM((void __flash*)0x0001, 0x09) + +#define _SPM_GET_FUSEBITS() \ + __AddrToZByteToSPMCR_LPM((void __flash*)0x0000, 0x09) + + +#ifdef __HAS_ELPM__ +__intrinsic void __AddrToZ24ByteToSPMCR_SPM(void __farflash* addr, + unsigned char byte); +__intrinsic void __AddrToZ24WordToR1R0ByteToSPMCR_SPM(void __farflash* addr, + unsigned short word, + unsigned char byte); +#define _SPM_24_ERASE(Addr) \ + __AddrToZ24ByteToSPMCR_SPM((void __farflash*)(Addr), 0x03) + +#define _SPM_24_FILLTEMP(Addr,Data) \ + __AddrToZ24WordToR1R0ByteToSPMCR_SPM((void __farflash*)(Addr), (Data), 0x01) + +#define _SPM_24_PAGEWRITE(Addr) \ + __AddrToZ24ByteToSPMCR_SPM((void __farflash*)(Addr), (0x05)) + +__intrinsic unsigned char __AddrToZ24ByteToSPMCR_ELPM(void __farflash* addr, + unsigned char byte); +#endif +#pragma language=default + +#endif //__HAS_ENHANCED_CORE__ + +/* Include a file appropriate for the processor used, + * that defines EECR, EEAR and EEDR (e.g. io2312.h). */ +#ifdef __HAS_EEPROM__ +#define __EEPUT(ADR,VAL) (*((unsigned char __eeprom *)ADR) = VAL) +#define __EEGET(VAR, ADR) (VAR = *((unsigned char __eeprom *)ADR)) +#else /* !__HAS_EEPROM__ */ +#define __EEPUT(ADR,VAL) {while (EECR & 0x02); \ + EEAR = (ADR); EEDR = (VAL); EECR = 0x04; EECR = 0x02;} + +#define __EEGET(VAR, ADR) {while (EECR & 0x02); \ + EEAR = (ADR); EECR = 0x01; (VAR) = EEDR;} +#endif /* __HAS_EEPROM__ */ + +/* PORT is a sfrb defined variable */ +#define input(PORT) (PORT) +#define output(PORT,VAL) ((PORT)=(VAL)) + +#define input_block_dec(PORT,ADDRESS,COUNT)\ +{ \ + unsigned char i;\ + unsigned char *addr=(ADDRESS);\ + for(i=0;i<(COUNT);i++)\ + *addr--=(PORT);\ +} + +#define input_block_inc(PORT,ADDRESS,COUNT)\ +{ \ + unsigned char i;\ + unsigned char *addr=(ADDRESS);\ + for(i=0;i<(COUNT);i++)\ + *addr++=(PORT);\ +} + +#define output_block_dec(PORT,ADDRESS,COUNT)\ +{ \ + unsigned char i;\ + unsigned char *addr=(ADDRESS);\ + for(i=0;i<(COUNT);i++)\ + (PORT)=*addr--;\ +} + +#define output_block_inc(PORT,ADDRESS,COUNT)\ +{ \ + unsigned char i;\ + unsigned char *addr=(ADDRESS);\ + for(i=0;i<(COUNT);i++)\ + (PORT)=*addr++;\ +} + + +//Nice to have macros + +#define __out_word(BaseName, value)\ +{\ + unsigned char _tH=(value) >> 8;\ + unsigned char _tL=(value) & 0xFF;\ + BaseName ## H = _tH;\ + BaseName ## L = _tL;\ +} + + +#define __out_word_atomic(BaseName, value)\ +{\ + unsigned char _t=__save_interrupt();\ + __disable_interrupt();\ + __out_word(BaseName,value);\ + __restore_interrupt(_t);\ +} + +#define __in_word(BaseName, value)\ +{\ + (value) = (BaseName ## L);\ + (value) |= (unsigned short)BaseName ## H << 8;\ +} + + +#define __in_word_atomic(BaseName, value)\ +{\ + unsigned char _t=__save_interrupt();\ + __disable_interrupt();\ + __in_word(BaseName, value);\ + __restore_interrupt(_t);\ +} +#endif /* __INAVR_H */ diff --git a/ATmega48/MEGA48/Include/iom48.h b/ATmega48/MEGA48/Include/iom48.h new file mode 100644 index 0000000..ab268c1 --- /dev/null +++ b/ATmega48/MEGA48/Include/iom48.h @@ -0,0 +1,741 @@ +/**************************************************************************** + ** - iom48.h - + ** + ** This file declares the internal register addresses for ATmega48. + ** + ** Used with iccAVR and aAVR. + ** + ** Copyright IAR Systems 2003. All rights reserved. + ** + ** File version: $Revision: 1 $ + ** + ***************************************************************************/ + +#include "iomacro.h" + +#if TID_GUARD(1) +#error This file should only be compiled with iccavr or aavr whith processor option -v1 +#endif /* TID_GUARD(1) */ + +/* Include the SFR part if this file has not been included before, + * OR this file is included by the assembler (SFRs must be defined in + * each assembler module). */ +#if !defined(__IOM48_H) || defined(__IAR_SYSTEMS_ASM__) + +#pragma language=extended + +/*==========================*/ +/* Predefined SFR Addresses */ +/*==========================*/ + +/**************************************************************************** + * An example showing the SFR_B() macro call, + * the expanded result and usage of this result: + * + * SFR_B(AVR, 0x1F) Expands to: + * __io union { + * unsigned char AVR; // The sfrb as 1 byte + * struct { // The sfrb as 8 bits + * unsigned char AVR_Bit0:1, + * AVR_Bit1:1, + * AVR_Bit2:1, + * AVR_Bit3:1, + * AVR_Bit4:1, + * AVR_Bit5:1, + * AVR_Bit6:1, + * AVR_Bit7:1; + * }; + * } @ 0x1F; + * Examples of how to use the expanded result: + * AVR |= (1<<5); + * or like this: + * AVR_Bit5 = 1; + ***************************************************************************/ + + +/* Extended I/O space */ +SFR_B(UDR0, 0xC6) /* USART0 I/O Data Register */ +SFR_W(UBRR0, 0xC4) /* USART0 Baud Rate Register */ + +SFR_B(UCSR0C, 0xC2) /* USART0 Control and Status Register C */ +SFR_B(UCSR0B, 0xC1) /* USART0 Control and Status Register B */ +SFR_B(UCSR0A, 0xC0) /* USART0 Control and Status Register A */ + +SFR_B(TWAMR, 0xBD) /* 2-wire Serial Interface */ +SFR_B(TWCR, 0xBC) /* 2-wire Serial Interface Control Register */ +SFR_B(TWDR, 0xBB) /* 2-wire Serial Interface Data Register */ +SFR_B(TWAR, 0xBA) /* 2-wire Serial Interface Address Register */ +SFR_B(TWSR, 0xB9) /* 2-wire Serial Interface Status Register */ +SFR_B(TWBR, 0xB8) /* 2-wire Serial Interface Bit Rate Register */ + +SFR_B(ASSR, 0xB6) /* Asynchronous mode Status Register */ + +SFR_B(OCR2B, 0xB4) /* Timer/Counter 2 Output Compare Register B */ +SFR_B(OCR2A, 0xB3) /* Timer/Counter 2 Output Compare Register A */ +SFR_B(TCNT2, 0xB2) /* Timer/Counter 2 */ +SFR_B(TCCR2B, 0xB1) /* Timer/Counter 2 Control Register B */ +SFR_B(TCCR2A, 0xB0) /* Timer/Counter 2 Control Register A */ + +SFR_W(OCR1B, 0x8A) /* Timer/Counter 1 - Output Compare Register B */ +SFR_W(OCR1A, 0x88) /* Timer/Counter 1 - Output Compare Register A */ +SFR_W(ICR1, 0x86) /* Timer/Counter 1 - Input Capture Register */ +SFR_W(TCNT1, 0x84) /* Timer/Counter 1 - Counter Register */ + +SFR_B(TCCR1C, 0x82) /* Timer/Counter 1 Control Register C */ +SFR_B(TCCR1B, 0x81) /* Timer/Counter 1 Control Register B */ +SFR_B(TCCR1A, 0x80) /* Timer/Counter 1 Control Register A */ +SFR_B(DIDR1, 0x7F) /* Digital Input Disable Register 1 */ +SFR_B(DIDR0, 0x7E) /* Digital Input Disable Register 0 */ + +SFR_B(ADMUX, 0x7C) /* ADC Multiplexer Selection Register */ +SFR_B(ADCSRB, 0x7B) /* ADC Control and Status Register B */ +SFR_B(ADCSRA, 0x7A) /* ADC Control and Status Register A */ +SFR_W(ADC, 0x78) /* ADC Data Register */ + +SFR_B(TIMSK2, 0x70) /* Timer/Counter 2 Interrupt Mask Register */ +SFR_B(TIMSK1, 0x6F) /* Timer/Counter 1 Interrupt Mask Register */ +SFR_B(TIMSK0, 0x6E) /* Timer/Counter 0 Interrupt Mask Register */ +SFR_B(PCMSK2, 0x6D) /* Pin Change Mask Register 2 */ +SFR_B(PCMSK1, 0x6C) /* Pin Change Mask Register 1 */ +SFR_B(PCMSK0, 0x6B) /* Pin Change Mask Register 0 */ + +SFR_B(EICRA, 0x69) /* External Interrupt Control Register A */ +SFR_B(PCICR, 0x68) /* Pin Change Interrupt Control Register */ + +SFR_B(OSCCAL, 0x66) /* Oscillator Calibration Register */ + +SFR_B(PRR, 0x64) /* */ + +SFR_B(CLKPR, 0x61) /* System Clock Prescaler */ +SFR_B(WDTCSR, 0x60) /* Watchdog Timer Control and Status Register */ + +/* Ordinary I/O space */ +SFR_B(SREG, 0x3F) /* Status Register */ +SFR_W(SP, 0x3D) /* Stack Pointer */ + +SFR_B(SPMCSR, 0x37) /* Store Program Memory Control Register */ + +SFR_B(MCUCR, 0x35) /* MCU Control Register */ +SFR_B(MCUSR, 0x34) /* MCU Status Register */ +SFR_B(SMCR, 0x33) /* Sleep Mode Control Register */ + +SFR_B(MONDR, 0x31) /* Monitor Data Register */ +SFR_B(ACSR, 0x30) /* Analog Comparator Control and Status Register */ + +SFR_B(SPDR, 0x2E) /* SPI Data Register */ +SFR_B(SPSR, 0x2D) /* SPI Status Register */ +SFR_B(SPCR, 0x2C) /* SPI Control Register */ +SFR_B(GPIOR2, 0x2B) /* General Purpose I/O Register 2 */ +SFR_B(GPIOR1, 0x2A) /* General Purpose I/O Register 1 */ + +SFR_B(OCR0B, 0x28) /* Timer/Counter 0 Output Compare Register B */ +SFR_B(OCR0A, 0x27) /* Timer/Counter 0 Output Compare Register A */ +SFR_B(TCNT0, 0x26) /* Timer/Counter 0 (8-bit) */ +SFR_B(TCCR0B, 0x25) /* Timer/Counter 0 Control Register B */ +SFR_B(TCCR0A, 0x24) /* Timer/Counter 0 Control Register A */ +SFR_B(GTCCR, 0x23) /* General Timer/Counter Control Register */ +SFR_B(EEAR, 0x21) /* EEPROM Address Register */ +SFR_B(EEDR, 0x20) /* EEPROM Data Register */ +SFR_B(EECR, 0x1F) /* EEPROM Control Register */ +SFR_B(GPIOR0, 0x1E) /* General Purpose I/O Register 0 */ +SFR_B(EIMSK, 0x1D) /* External Interrupt Mask Register */ +SFR_B(EIFR, 0x1C) /* External Interrupt Flag Register */ +SFR_B(PCIFR, 0x1B) /* Pin Change Interrupt Flag Register */ + +SFR_B(TIFR2, 0x17) /* Timer/Counter 2 Interrupt Flag Register */ +SFR_B(TIFR1, 0x16) /* Timer/Counter 1 Interrupt Flag Register */ +SFR_B(TIFR0, 0x15) /* Timer/Counter 0 Interrupt Flag Register */ + +SFR_B(PORTD, 0x0B) /* Data Register, Port D */ +SFR_B(DDRD, 0x0A) /* Data Direction Register, Port D */ +SFR_B(PIND, 0x09) /* Input Pins, Port D */ +SFR_B(PORTC, 0x08) /* Data Register, Port C */ +SFR_B(DDRC, 0x07) /* Data Direction Register, Port C */ +SFR_B(PINC, 0x06) /* Input Pins, Port C */ +SFR_B(PORTB, 0x05) /* Data Register, Port B */ +SFR_B(DDRB, 0x04) /* Data Direction Register, Port B */ +SFR_B(PINB, 0x03) /* Input Pins, Port B */ + + +#ifndef __IOM48_H +#define __IOM48_H + + +/* SFRs are local in assembler modules (so this file may need to be */ +/* included in more than one module in the same source file), */ +/* but #defines must only be made once per source file. */ + +/*==============================*/ +/* Interrupt Vector Definitions */ +/*==============================*/ + +/* NB! vectors are specified as byte addresses */ + +#define RESET_vect (0x00) /* External Pin, Power-on Reset, Brownout + Reset and Watchdog Reset */ +#define INT0_vect (0x02) /* External Interrupt Request 0 */ +#define INT1_vect (0x04) /* External Interrupt Request 1 */ +#define PCINT0_vect (0x06) /* Pin Change Interrupt Request 0 */ +#define PCINT1_vect (0x08) /* Pin Change Interrupt Request 1 */ +#define PCINT2_vect (0x0A) /* Pin Change Interrupt Request 2 */ +#define WDT_vect (0x0C) /* Watchdog Time-out Interrupt */ +#define TIMER2_COMPA_vect (0x0E) /* Timer/Counter2 Compare Match A */ +#define TIMER2_COMPB_vect (0x10) /* Timer/Counter2 Compare Match B */ +#define TIMER2_OVF_vect (0x12) /* Timer/Counter2 Overflow */ +#define TIMER1_CAPT_vect (0x14) /* Timer/Counter1 Capture Event */ +#define TIMER1_COMPA_vect (0x16) /* Timer/Counter1 Compare Match A */ +#define TIMER1_COMPB_vect (0x18) /* Timer/Coutner1 Compare Match B */ +#define TIMER1_OVF_vect (0x1A) /* Timer/Counter1 Overflow */ +#define TIMER0_COMPA_vect (0x1C) /* Timer/Counter0 Compare Match A */ +#define TIMER0_COMPB_vect (0x1E) /* Timer/Counter0 Compare Match B */ +#define TIMER0_OVF_vect (0x20) /* Timer/Counter0 Overflow */ +#define SPI_STC_vect (0x22) /* SPI Serial Transfer Complete */ +#define USART_RX_vect (0x24) /* USART Rx Complete */ +#define USART_UDRE_vect (0x26) /* USART, Data Register Empty */ +#define USART_TX_vect (0x28) /* USART, Tx Complete */ +#define ADC_vect (0x2A) /* ADC Conversion Complete */ +#define EE_RDY_vect (0x2C) /* EEPROM Ready */ +#define ANA_COMP_vect (0x2E) /* Analog Comparator */ +#define TWI_vect (0x30) /* 2-wire Serial Interface */ +#define SPM_READY_vect (0x32) /* Store Program Memory Ready */ + +#ifdef __IAR_SYSTEMS_ASM__ +#ifndef ENABLE_BIT_DEFINITIONS +#define ENABLE_BIT_DEFINITIONS +#endif /* ENABLE_BIT_DEFINITIONS */ +#endif /* __IAR_SYSTEMS_ASM__ */ + +#ifdef ENABLE_BIT_DEFINITIONS + + +/* Bit definitions for use with the IAR Assembler + The Register Bit names are represented by their bit number (0-7). +*/ + +/*UCSR0C*/ +#define UMSEL01 7 +#define UMSEL00 6 +#define UPM01 5 +#define UPM00 4 +#define USBS0 3 +#define UDORD0 2 +#define UCPHA0 1 +#define UCPOL0 0 + +#define UCSZ01 UDORD0 +#define UCSZ00 UCPHA0 + +/*UCSR0B*/ +#define RXCIE0 7 +#define TXCIE0 6 +#define UDRIE0 5 +#define RXEN0 4 +#define TXEN0 3 +#define UCSZ02 2 +#define RXB80 1 +#define TXB80 0 + +/*UCSR0A*/ +#define RXC0 7 +#define TXC0 6 +#define UDRE0 5 +#define FE0 4 +#define DOR0 3 +#define UPE0 2 +#define U2X0 1 +#define MPCM0 0 + + +/*TWAMR*/ +#define TWAM6 7 +#define TWAM5 6 +#define TWAM4 5 +#define TWAM3 4 +#define TWAM2 3 +#define TWAM1 2 +#define TWAM0 1 + +/*TWCR*/ +#define TWINT 7 +#define TWEA 6 +#define TWSTA 5 +#define TWSTO 4 +#define TWWC 3 +#define TWEN 2 +#define TWIE 0 + +/*TWAR*/ +#define TWA6 7 +#define TWA5 6 +#define TWA4 5 +#define TWA3 4 +#define TWA2 3 +#define TWA1 2 +#define TWA0 1 +#define TWGCE 0 + +/*TWSR*/ +#define TWS7 7 +#define TWS6 6 +#define TWS5 5 +#define TWS4 4 +#define TWS3 3 +#define TWPS1 1 +#define TWPS0 0 + + +/*ASSR*/ +#define EXCLK 6 +#define AS2 5 +#define TCN2UB 4 +#define OCR2AUB 3 +#define OCR2BUB 2 +#define TCR2AUB 1 +#define TCR2BUB 0 + + +/*TCCR2B*/ +#define FOC2A 7 +#define FOC2B 6 +#define WGM22 3 +#define CS22 2 +#define CS21 1 +#define CS20 0 + +/*TCCR2A*/ +#define COM2A1 7 +#define COM2A0 6 +#define COM2B1 5 +#define COM2B0 4 +#define WGM21 1 +#define WGM20 0 + + +/*TCCR1C*/ +#define FOC1A 7 +#define FOC1B 6 + +/*TCCR1B*/ +#define ICNC1 7 +#define ICES1 6 +#define WGM13 4 +#define WGM12 3 +#define CS12 2 +#define CS11 1 +#define CS10 0 + +/*TCCR1A*/ +#define COM1A1 7 +#define COM1A0 6 +#define COM1B1 5 +#define COM1B0 4 +#define WGM11 1 +#define WGM10 0 + +/*DIDR1*/ +#define AIN1D 1 +#define AIN0D 0 + +/*DIDR0*/ +#define ADC5D 5 +#define ADC4D 4 +#define ADC3D 3 +#define ADC2D 2 +#define ADC1D 1 +#define ADC0D 0 + + +/*ADMUX*/ +#define REFS1 7 +#define REFS0 6 +#define ADLAR 5 +#define MUX3 3 +#define MUX2 2 +#define MUX1 1 +#define MUX0 0 + +/*ADCSRB*/ +#define ACME 6 +#define ADTS2 2 +#define ADTS1 1 +#define ADTS0 0 + +/*ADCSRA*/ +#define ADEN 7 +#define ADSC 6 +#define ADATE 5 +#define ADIF 4 +#define ADIE 3 +#define ADPS2 2 +#define ADPS1 1 +#define ADPS0 0 + + +/*TIMSK2*/ +#define OCIE2B 2 +#define OCIE2A 1 +#define TOIE2 0 + +/*TIMSK1*/ +#define ICIE1 5 +#define OCIE1B 2 +#define OCIE1A 1 +#define TOIE1 0 + +/*TIMSK0*/ +#define OCIE0B 2 +#define OCIE0A 1 +#define TOIE0 0 + +/*PCMSK2*/ +#define PCINT23 7 +#define PCINT22 6 +#define PCINT21 5 +#define PCINT20 4 +#define PCINT19 3 +#define PCINT18 2 +#define PCINT17 1 +#define PCINT16 0 + +/*PCMSK1*/ +#define PCINT14 6 +#define PCINT13 5 +#define PCINT12 4 +#define PCINT11 3 +#define PCINT10 2 +#define PCINT9 1 +#define PCINT8 0 + +/*PCMSK0*/ +#define PCINT7 7 +#define PCINT6 6 +#define PCINT5 5 +#define PCINT4 4 +#define PCINT3 3 +#define PCINT2 2 +#define PCINT1 1 +#define PCINT0 0 + + +/*EICRA*/ +#define ISC11 3 +#define ISC10 2 +#define ISC01 1 +#define ISC00 0 + +/*PCICR*/ +#define PCIE2 2 +#define PCIE1 1 +#define PCIE0 0 + + +/*PRR*/ +#define PRTW1 7 +#define PRTIM2 6 +#define PRTIM0 5 +#define PRTIM1 3 +#define PRSPI 2 +#define PRUSART0 1 +#define PRADC 0 + + +/*CLKPR*/ +#define CLKPCE 7 +#define CLKPS3 3 +#define CLKPS2 2 +#define CLKPS1 1 +#define CLKPS0 0 + +/*WDTCSR*/ +#define WDIF 7 +#define WDIE 6 +#define WDP3 5 +#define WDCE 4 +#define WDE 3 +#define WDP2 2 +#define WDP1 1 +#define WDP0 0 + +/* Ordinary I/O space */ + +/*SPH*/ +#define SP9 1 +#define SP8 0 + +/*SPL*/ +#define SP7 7 +#define SP6 6 +#define SP5 5 +#define SP4 4 +#define SP3 3 +#define SP2 2 +#define SP1 1 +#define SP0 0 + + +/*SPMCSR*/ +#define SPMIE 7 +#define BLBSET 3 +#define PGWRT 2 +#define PGERS 1 +#define SPMEN 0 + + +/*MCUCR*/ +#define PUD 4 +#define IVSEL 1 +#define IVCE 0 + +/*MCUSR*/ +#define WDRF 3 +#define BORF 2 +#define EXTRF 1 +#define PORF 0 + +/*SMCR*/ +#define SM2 3 +#define SM1 2 +#define SM0 1 +#define SE 0 + + +/*ACSR*/ +#define ACD 7 +#define ACBG 6 +#define ACO 5 +#define ACI 4 +#define ACIE 3 +#define ACIC 2 +#define ACIS1 1 +#define ACIS0 0 + + +/*SPSR*/ +#define SPIF 7 +#define WCOL 6 +#define SPI2X 0 + +/*SPCR*/ +#define SPIE 7 +#define SPE 6 +#define DORD 5 +#define MSTR 4 +#define CPOL 3 +#define CPHA 2 +#define SPR1 1 +#define SPR0 0 + + +/*TCCR0B*/ +#define FOC0A 7 +#define FOC0B 6 +#define WGM02 3 +#define CS02 2 +#define CS01 1 +#define CS00 0 + +/*TCCR0A*/ +#define COM0A1 7 +#define COM0A0 6 +#define COM0B1 5 +#define COM0B0 4 +#define WGM01 1 +#define WGM00 0 + +/*GTCCR*/ +#define TSM 7 +#define PSR2 1 +#define PSR10 0 + + +/*EECR*/ +#define EERIE 3 +#define EEMPE 2 +#define EEPE 1 +#define EERE 0 + +/*EIMSK*/ +#define INT1 1 +#define INT0 0 + +/*EIFR*/ +#define INTF1 1 +#define INTF0 0 + +/*PCIFR*/ +#define PCIF2 2 +#define PCIF1 1 +#define PCIF0 0 + + +/*TIFR2*/ +#define OCF2B 2 +#define OCF2A 1 +#define TOV2 0 + +/*TIFR1*/ +#define ICF1 5 +#define OCF1B 2 +#define OCF1A 1 +#define TOV1 0 + +/*TIFR0*/ +#define OCF0B 2 +#define OCF0A 1 +#define TOV0 0 + + +/*PORTD*/ +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +#define PD7 7 +#define PD6 6 +#define PD5 5 +#define PD4 4 +#define PD3 3 +#define PD2 2 +#define PD1 1 +#define PD0 0 + +/*DDRD*/ +#define DDD7 7 +#define DDD6 6 +#define DDD5 5 +#define DDD4 4 +#define DDD3 3 +#define DDD2 2 +#define DDD1 1 +#define DDD0 0 + +/*PIND*/ +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +/*PORTC*/ +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PC6 6 +#define PC5 5 +#define PC4 4 +#define PC3 3 +#define PC2 2 +#define PC1 1 +#define PC0 0 + +/*DDRC*/ +#define DDC6 6 +#define DDC5 5 +#define DDC4 4 +#define DDC3 3 +#define DDC2 2 +#define DDC1 1 +#define DDC0 0 + +/*PINC*/ +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +/*PORTB*/ +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PB7 7 +#define PB6 6 +#define PB5 5 +#define PB4 4 +#define PB3 3 +#define PB2 2 +#define PB1 1 +#define PB0 0 + +/*DDRB*/ +#define DDB7 7 +#define DDB6 6 +#define DDB5 5 +#define DDB4 4 +#define DDB3 3 +#define DDB2 2 +#define DDB1 1 +#define DDB0 0 + +/*PINB*/ +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + + +/* Extended Fuse Byte */ +#define SELFPRGEN 0 + +/* High Fuse Byte */ +#define RSTDISBL 7 +#define DWEN 6 +#define SPIEN 5 +#define WDTON 4 +#define EESAVE 3 +#define BODLEVEL2 2 +#define BODLEVEL1 1 +#define BODLEVEL0 0 + +/* Low Fuse Byte */ +#define CKDIV8 7 +#define CKOUT 6 +#define SUT1 5 +#define SUT0 4 +#define CKSEL3 3 +#define CKSEL2 2 +#define CKSEL1 1 +#define CKSEL0 0 + +/* Pointer definition */ +#define XL r26 +#define XH r27 +#define YL r28 +#define YH r29 +#define ZL r30 +#define ZH r31 + +/* Contants */ +#define RAMEND 0x02FF /*Last On-Chip SRAM location*/ +#define XRAMEND 0x02FF +#define E2END 0x00FF +#define FLASHEND 0x0FFF + +#endif /* ENABLE_BIT_DEFINITIONS */ +#endif /* __IOM48_H (define part) */ +#endif /* __IOM48_H (SFR part) */ diff --git a/ATmega48/MEGA48/Include/iomacro.h b/ATmega48/MEGA48/Include/iomacro.h new file mode 100644 index 0000000..ff3a71f --- /dev/null +++ b/ATmega48/MEGA48/Include/iomacro.h @@ -0,0 +1,380 @@ +/************************************************************** + ** - iomacro.h - + ** + ** This file defines the Special Function Register Macros + ** for Atmel AT90S. + ** + ** Used with iccAVR and aAVR. + ** + ** Copyright IAR Systems 1999. All rights reserved. + ** + ** File version: $Revision: 1 $ + ** + **************************************************************/ + +#ifndef __IOMACRO_H +#define __IOMACRO_H + +#define TID_GUARD(proc) ((__TID__ & 0x7FF0) != ((90 << 8) | ((proc) << 4))) + +#if !(__IAR_SYSTEMS_ICC__) && !defined(__IAR_SYSTEMS_ASM__) +#error This file should only be compiled with iccavr,icca90 or aavr. +#endif /* !(__IAR_SYSTEMS_ICC__ > 2) && !defined __IAR_SYSTEMS_ASM__ */ + +/* The assembler uses a special set of macros... */ +#ifdef __IAR_SYSTEMS_ASM__ + +/* Byte sized SFRs */ +#define SFR_B_BITS(_NAME,_ADDR,_A,_B,_C,_D,_E,_F,_G,_H)\ + sfrb _NAME = _ADDR +#define SFR_B_BITS_EXT(_NAME,_ADDR,_A,_B,_C,_D,_E,_F,_G,_H)\ + sfrb _NAME = _ADDR +#define SFR_B_BITS_EXT_IO(_NAME,_ADDR,_A,_B,_C,_D,_E,_F,_G,_H)\ + sfrb _NAME = _ADDR +#define SFR_B2_BITS(_NAME1,_NAME2,_ADDR,_A,_B,_C,_D,_E,_F,_G,_H)\ + ASMSFRB2 _NAME1, _NAME2, _ADDR + +#define SFR_B_BITS_N(_NAME,_ADDR,_A,_B,_C,_D,_E,_F,_G,_H, \ + _A2,_B2,_C2,_D2,_E2,_F2,_G2,_H2)\ + sfrb _NAME = _ADDR +#define SFR_B_BITS_EXT_N(_NAME,_ADDR,_A,_B,_C,_D,_E,_F,_G,_H, \ + _A2,_B2,_C2,_D2,_E2,_F2,_G2,_H2)\ + sfrb _NAME = _ADDR +#define SFR_B_BITS_EXT_IO_N(_NAME,_ADDR,_A,_B,_C,_D,_E,_F,_G,_H, \ + _A2,_B2,_C2,_D2,_E2,_F2,_G2,_H2)\ + sfrb _NAME = _ADDR +#define SFR_B2_BITS_N(_NAME1,_NAME2,_ADDR,_A,_B,_C,_D,_E,_F,_G,_H, \ + _A2,_B2,_C2,_D2,_E2,_F2,_G2,_H2)\ + ASMSFRB2 _NAME1, _NAME2, _ADDR + +ASMSFRB2 MACRO + sfrb \1 = \3 + sfrb \2 = \3 + ENDM + + +/* Word sized SFRs, needs to be expanded into an assembler macro first. */ +#define SFR_W_BITS(_NAME, _ADDR, _A,_B,_C,_D,_E,_F,_G,_H, _I,_J,_K,_L,_M,_N,_O,_P)\ + ASMSFRW _NAME, _ADDR +#define SFR_W_BITS_EXT_IO(_ADDR, _NAME, _A,_B,_C,_D,_E,_F,_G,_H, _I,_J,_K,_L,_M,_N,_O,_P)\ + ASMSFRW _NAME, _ADDR +#define SFR_W_BITS_N(_NAME, _ADDR, _A,_B,_C,_D,_E,_F,_G,_H, _I,_J,_K,_L,_M,_N,_O,_P, \ + _A2,_B2,_C2,_D2,_E2,_F2,_G2,_H2, \ + _I2,_J2,_K2,_L2,_M2,_N2,_O2,_P2)\ + ASMSFRW _NAME, _ADDR + +ASMSFRW MACRO + sfrw \1 = \2 + sfrb \1L = (\2+0) + sfrb \1H = (\2+1) + ENDM + +#endif /* __IAR_SYSTEMS_ASM__ */ + +#ifdef __ICCAVR__ + +#define __BYTEBITS(_NAME,_A,_B,_C,_D,_E,_F,_G,_H) \ +unsigned char _NAME ## _ ## _A:1, \ + _NAME ## _ ## _B:1, \ + _NAME ## _ ## _C:1, \ + _NAME ## _ ## _D:1, \ + _NAME ## _ ## _E:1, \ + _NAME ## _ ## _F:1, \ + _NAME ## _ ## _G:1, \ + _NAME ## _ ## _H:1; + +#define SFR_B_BITS(_NAME, _ADDR, _A,_B,_C,_D,_E,_F,_G,_H) \ + __io union { \ + unsigned char _NAME; /* The sfrb as 1 byte */ \ + struct { /* The sfrb as 8 bits */ \ + __BYTEBITS(_NAME, _A,_B,_C,_D,_E,_F,_G,_H) \ + }; \ + } @ _ADDR; + +#define SFR_B_BITS_N(_NAME, _ADDR, _A,_B,_C,_D,_E,_F,_G,_H, \ + _A2,_B2,_C2,_D2,_E2,_F2,_G2,_H2) \ + __io union { \ + unsigned char _NAME; /* The sfrb as 1 byte */ \ + struct { /* The sfrb as 8 bits */ \ + __BYTEBITS(_NAME, _A,_B,_C,_D,_E,_F,_G,_H) \ + }; \ + struct { /* The sfrb as 8 bits */ \ + __BYTEBITS(_NAME, _A2,_B2,_C2,_D2,_E2,_F2,_G2,_H2) \ + }; \ + } @ _ADDR; + +#define SFR_B2_BITS(_NAME1, _NAME2, _ADDR, _A,_B,_C,_D,_E,_F,_G,_H) \ + __io union { \ + unsigned char _NAME1; /* The sfrb as 1 byte */ \ + unsigned char _NAME2; /* The sfrb as 1 byte */ \ + struct { /* The sfrb as 8 bits */ \ + __BYTEBITS(_NAME1, _A,_B,_C,_D,_E,_F,_G,_H) \ + }; \ + struct { /* The sfrb as 8 bits */ \ + __BYTEBITS(_NAME2, _A,_B,_C,_D,_E,_F,_G,_H) \ + }; \ + } @ _ADDR; + +#define SFR_B2_BITS_N(_NAME1, _NAME2, _ADDR, _A,_B,_C,_D,_E,_F,_G,_H, \ + _A2,_B2,_C2,_D2,_E2,_F2,_G2,_H2) \ + __io union { \ + unsigned char _NAME1; /* The sfrb as 1 byte */ \ + unsigned char _NAME2; /* The sfrb as 1 byte */ \ + struct { /* The sfrb as 8 bits */ \ + __BYTEBITS(_NAME1, _A,_B,_C,_D,_E,_F,_G,_H) \ + }; \ + struct { /* The sfrb as 8 bits */ \ + __BYTEBITS(_NAME2, _A,_B,_C,_D,_E,_F,_G,_H) \ + }; \ + struct { /* The sfrb as 8 bits */ \ + __BYTEBITS(_NAME1, _A2,_B2,_C2,_D2,_E2,_F2,_G2,_H2) \ + }; \ + struct { /* The sfrb as 8 bits */ \ + __BYTEBITS(_NAME2, _A2,_B2,_C2,_D2,_E2,_F2,_G2,_H2) \ + }; \ + } @ _ADDR; + +#define SFR_B_BITS_EXT(_NAME, _ADDR, _A,_B,_C,_D,_E,_F,_G,_H) \ + __near __no_init volatile union { \ + unsigned char _NAME; /* The sfrb as 1 byte */ \ + struct { /* The sfrb as 8 bits */ \ + __BYTEBITS(_NAME, _A,_B,_C,_D,_E,_F,_G,_H) \ + }; \ + } @ _ADDR; + +#define SFR_B_BITS_EXT_IO(_NAME, _ADDR, _A,_B,_C,_D,_E,_F,_G,_H) \ + __ext_io union { \ + unsigned char _NAME; /* The sfrb as 1 byte */ \ + struct { /* The sfrb as 8 bits */ \ + __BYTEBITS(_NAME, _A,_B,_C,_D,_E,_F,_G,_H) \ + }; \ + } @ _ADDR; + + +#define SFR_B_BITS_EXT_N(_NAME, _ADDR, _A,_B,_C,_D,_E,_F,_G,_H, \ + _A2,_B2,_C2,_D2,_E2,_F2,_G2,_H2) \ + __near __no_init volatile union { \ + unsigned char _NAME; /* The sfrb as 1 byte */ \ + struct { /* The sfrb as 8 bits */ \ + __BYTEBITS(_NAME, _A,_B,_C,_D,_E,_F,_G,_H) \ + }; \ + struct { /* The sfrb as 8 bits */ \ + __BYTEBITS(_NAME, _A2,_B2,_C2,_D2,_E2,_F2,_G2,_H2) \ + }; \ + } @ _ADDR; + +#define SFR_B_BITS_EXT_IO_N(_NAME, _ADDR, _A,_B,_C,_D,_E,_F,_G,_H, \ + _A2,_B2,_C2,_D2,_E2,_F2,_G2,_H2) \ + __ext_io union { \ + unsigned char _NAME; /* The sfrb as 1 byte */ \ + struct { /* The sfrb as 8 bits */ \ + __BYTEBITS(_NAME, _A,_B,_C,_D,_E,_F,_G,_H) \ + }; \ + struct { /* The sfrb as 8 bits */ \ + __BYTEBITS(_NAME, _A2,_B2,_C2,_D2,_E2,_F2,_G2,_H2) \ + }; \ + } @ _ADDR; + +#define SFR_W_BITS(_NAME, _ADDR, _A,_B,_C,_D,_E,_F,_G,_H, _I,_J,_K,_L,_M,_N,_O,_P) \ + __io union { \ + unsigned short _NAME; /* The sfrw as 1 short */ \ + struct { /* The sfrw as 16 bits */ \ + __BYTEBITS(_NAME, _A,_B,_C,_D,_E,_F,_G,_H) /* Bit names defined by user */ \ + __BYTEBITS(_NAME, _I,_J,_K,_L,_M,_N,_O,_P) /* Bit names defined by user */ \ + }; \ + struct { /* The sfrw as 2 bytes */ \ + unsigned char _NAME ## L; \ + unsigned char _NAME ## H; \ + }; \ + struct { /* The sfrw as 2 x 8 bits */ \ + __BYTEBITS(_NAME ## L, Bit0,Bit1,Bit2,Bit3,Bit4,Bit5,Bit6,Bit7) /* Bit names hard coded to 0-7 */ \ + __BYTEBITS(_NAME ## H, Bit0,Bit1,Bit2,Bit3,Bit4,Bit5,Bit6,Bit7) /* Bit names hard coded to 0-7 */ \ + }; \ + } @ _ADDR; + +#define SFR_W_BITS_EXT_IO(_ADDR, _NAME, _A,_B,_C,_D,_E,_F,_G,_H, _I,_J,_K,_L,_M,_N,_O,_P) \ + __ext_io union { \ + unsigned short _NAME; /* The sfrw as 1 short */ \ + struct { /* The sfrw as 16 bits */ \ + __BYTEBITS(_NAME, _A,_B,_C,_D,_E,_F,_G,_H) /* Bit names defined by user */ \ + __BYTEBITS(_NAME, _I,_J,_K,_L,_M,_N,_O,_P) /* Bit names defined by user */ \ + }; \ + struct { /* The sfrw as 2 bytes */ \ + unsigned char _NAME ## L; \ + unsigned char _NAME ## H; \ + }; \ + struct { /* The sfrw as 2 x 8 bits */ \ + __BYTEBITS(_NAME ## L, Bit0,Bit1,Bit2,Bit3,Bit4,Bit5,Bit6,Bit7) /* Bit names hard coded to 0-7 */ \ + __BYTEBITS(_NAME ## H, Bit0,Bit1,Bit2,Bit3,Bit4,Bit5,Bit6,Bit7) /* Bit names hard coded to 0-7 */ \ + }; \ + } @ _ADDR; + +#define SFR_W_BITS_N(_NAME, _ADDR, _A,_B,_C,_D,_E,_F,_G,_H, _I,_J,_K,_L,_M,_N,_O,_P, \ + _A2,_B2,_C2,_D2,_E2,_F2,_G2,_H2, \ + _I2,_J2,_K2,_L2,_M2,_N2,_O2,_P2) \ + __io union { \ + unsigned short _NAME; /* The sfrw as 1 short */ \ + struct { /* The sfrw as 16 bits */ \ + __BYTEBITS(_NAME, _A,_B,_C,_D,_E,_F,_G,_H) /* Bit names defined by user */ \ + __BYTEBITS(_NAME, _I,_J,_K,_L,_M,_N,_O,_P) /* Bit names defined by user */ \ + }; \ + struct { /* The sfrw as 16 bits */ \ + __BYTEBITS(_NAME, _A2,_B2,_C2,_D2,_E2,_F2,_G2,_H2) /* Bit names defined by user */ \ + __BYTEBITS(_NAME, _I2,_J2,_K2,_L2,_M2,_N2,_O2,_P2) /* Bit names defined by user */ \ + }; \ + struct { /* The sfrw as 2 bytes */ \ + unsigned char _NAME ## L; \ + unsigned char _NAME ## H; \ + }; \ + struct { /* The sfrw as 2 x 8 bits */ \ + __BYTEBITS(_NAME ## L, Bit0,Bit1,Bit2,Bit3,Bit4,Bit5,Bit6,Bit7) /* Bit names hard coded to 0-7 */ \ + __BYTEBITS(_NAME ## H, Bit0,Bit1,Bit2,Bit3,Bit4,Bit5,Bit6,Bit7) /* Bit names hard coded to 0-7 */ \ + }; \ + struct { /* The sfrw as 2 x 8 bits */ \ + __BYTEBITS(_NAME ## L, _A2,_B2,_C2,_D2,_E2,_F2,_G2,_H2) /* Bit names defined by user */ \ + __BYTEBITS(_NAME ## H, _I2,_J2,_K2,_L2,_M2,_N2,_O2,_P2) /* Bit names defined by user */ \ + }; \ + } @ _ADDR; +#else +#ifndef __IAR_SYSTEMS_ASM__ + /* Special for the icca90 */ + +/* Byte sized SFRs */ +#define SFR_B_BITS(_NAME,_ADDR,_A,_B,_C,_D,_E,_F,_G,_H)\ + sfrb _NAME = _ADDR; +#define SFR_B_BITS_EXT(_NAME,_ADDR,_A,_B,_C,_D,_E,_F,_G,_H)\ + sfrb _NAME = _ADDR; +#define SFR_B2_BITS(_NAME1,_NAME2,_ADDR,_A,_B,_C,_D,_E,_F,_G,_H)\ + sfrb _NAME1 = _ADDR; sfrb _NAME2 = _ADDR; + +#define SFR_B_BITS_N(_NAME,_ADDR,_A,_B,_C,_D,_E,_F,_G,_H, \ + _A2,_B2,_C2,_D2,_E2,_F2,_G2,_H2)\ + sfrb _NAME = _ADDR; +#define SFR_B_BITS_EXT_N(_NAME,_ADDR,_A,_B,_C,_D,_E,_F,_G,_H, \ + _A2,_B2,_C2,_D2,_E2,_F2,_G2,_H2)\ + sfrb _NAME = _ADDR; +#define SFR_B2_BITS_N(_NAME1,_NAME2,_ADDR,_A,_B,_C,_D,_E,_F,_G,_H, \ + _A2,_B2,_C2,_D2,_E2,_F2,_G2,_H2)\ + sfrb _NAME1 = _ADDR; sfrb _NAME2 = _ADDR; + +/* Word sized SFRs */ +#define SFR_W_BITS(_NAME, _ADDR, _A,_B,_C,_D,_E,_F,_G,_H, _I,_J,_K,_L,_M,_N,_O,_P)\ + sfrw _NAME = _ADDR; sfrb _NAME##L = _ADDR; sfrb _NAME##H = (_ADDR+1); +#define SFR_W_BITS_N(_NAME, _ADDR, _A,_B,_C,_D,_E,_F,_G,_H, _I,_J,_K,_L,_M,_N,_O,_P, \ + _A2,_B2,_C2,_D2,_E2,_F2,_G2,_H2, \ + _I2,_J2,_K2,_L2,_M2,_N2,_O2,_P2)\ + sfrw _NAME = _ADDR; sfrb _NAME##L = _ADDR; sfrb _NAME##H = (_ADDR+1); + +#endif +#endif /* !__ICCAVR__ */ + +#define SFR_B(_NAME, _ADDR) SFR_B_BITS(_NAME, _ADDR, \ + Bit0,Bit1,Bit2,Bit3,Bit4,Bit5,Bit6,Bit7) +/* + SFR_B(SREG, 0x3F) Expands to: + __io union { + unsigned char SREG; // The sfrb as 1 byte + struct { // The sfrb as 8 bits + unsigned char SREG_Bit0:1, + SREG_Bit1:1, + SREG_Bit2:1, + SREG_Bit3:1, + SREG_Bit4:1, + SREG_Bit5:1, + SREG_Bit6:1, + SREG_Bit7:1; + }; + } @ 0x3F; +*/ +#define SFR_B2(_NAME1, _NAME2, _ADDR) SFR_B2_BITS(_NAME1, _NAME2, _ADDR, \ + Bit0,Bit1,Bit2,Bit3,Bit4,Bit5,Bit6,Bit7) +#define SFR_B_EXT(_NAME, _ADDR) SFR_B_BITS_EXT(_NAME, _ADDR, \ + Bit0,Bit1,Bit2,Bit3,Bit4,Bit5,Bit6,Bit7) + +#define SFR_W(_NAME, _ADDR) SFR_W_BITS(_NAME, _ADDR, \ + Bit0,Bit1,Bit2,Bit3,Bit4,Bit5,Bit6,Bit7, \ + Bit8,Bit9,Bit10,Bit11,Bit12,Bit13,Bit14,Bit15) + +#define SFR_B_R(_ADDR, _NAME) SFR_B_BITS(_NAME, _ADDR, \ + Bit0,Bit1,Bit2,Bit3,Bit4,Bit5,Bit6,Bit7) +#define SFR_B_EXT_IO_R(_ADDR, _NAME) SFR_B_BITS_EXT_IO(_NAME, _ADDR, \ + Bit0,Bit1,Bit2,Bit3,Bit4,Bit5,Bit6,Bit7) +#define SFR_W_EXT_IO_R(_NAME, _ADDR) SFR_W_BITS_EXT_IO(_NAME, _ADDR, \ + Bit0,Bit1,Bit2,Bit3,Bit4,Bit5,Bit6,Bit7, \ + Bit8,Bit9,Bit10,Bit11,Bit12,Bit13,Bit14,Bit15) +/* + SFR_B(0x3F, SREG) Expands to: + __io union { + unsigned char SREG; // The sfrb as 1 byte + struct { // The sfrb as 8 bits + unsigned char SREG_Bit0:1, + SREG_Bit1:1, + SREG_Bit2:1, + SREG_Bit3:1, + SREG_Bit4:1, + SREG_Bit5:1, + SREG_Bit6:1, + SREG_Bit7:1; + }; + } @ 0x3F; +*/ +#define SFR_B2_R(_ADDR, _NAME1, _NAME2) SFR_B2_BITS(_NAME1, _NAME2, _ADDR, \ + Bit0,Bit1,Bit2,Bit3,Bit4,Bit5,Bit6,Bit7) +#define SFR_W_R(_ADDR, _NAME) SFR_W_BITS(_NAME, _ADDR, \ + Bit0,Bit1,Bit2,Bit3,Bit4,Bit5,Bit6,Bit7, \ + Bit8,Bit9,Bit10,Bit11,Bit12,Bit13,Bit14,Bit15) + +#define SFR_B_N(_ADDR, _NAME, _B7, _B6, _B5, _B4, _B3, _B2, _B1, _B0) \ + SFR_B_BITS_N(_NAME, _ADDR, \ + Bit0,Bit1,Bit2,Bit3,Bit4,Bit5,Bit6,Bit7, \ + _B0,_B1,_B2,_B3,_B4,_B5,_B6,_B7) +/* + SFR_B_N(0x3F,SREG,I,T,H,S,V,N,Z,C) Expands to: + __io union { + unsigned char SREG; // The sfrb as 1 byte + struct { // The sfrb as 8 bits + unsigned char SREG_Bit0:1, + SREG_Bit1:1, + SREG_Bit2:1, + SREG_Bit3:1, + SREG_Bit4:1, + SREG_Bit5:1, + SREG_Bit6:1, + SREG_Bit7:1; + }; + struct { // The sfrb as 8 bits + unsigned char SREG_C:1, + SREG_Z:1, + SREG_N:1, + SREG_V:1, + SREG_S:1, + SREG_H:1, + SREG_T:1, + SREG_I:1; + }; + } @ 0x3F; +*/ +#define SFR_B2_N(_ADDR, _NAME1, _NAME2, _B7, _B6, _B5, _B4, _B3, _B2, _B1, _B0) \ + SFR_B2_BITS_N(_NAME1, _NAME2, _ADDR, \ + Bit0,Bit1,Bit2,Bit3,Bit4,Bit5,Bit6,Bit7, \ + _B0,_B1,_B2,_B3,_B4,_B5,_B6,_B7) + +#define SFR_B_EXT_N(_ADDR, _NAME, _B7, _B6, _B5, _B4, _B3, _B2, _B1, _B0) \ + SFR_B_BITS_EXT_N(_NAME, _ADDR, \ + Bit0,Bit1,Bit2,Bit3,Bit4,Bit5,Bit6,Bit7, \ + _B0,_B1,_B2,_B3,_B4,_B5,_B6,_B7) + +#define SFR_B_EXT_IO_N(_ADDR, _NAME, _B7, _B6, _B5, _B4, _B3, _B2, _B1, _B0) \ + SFR_B_BITS_EXT_IO_N(_NAME, _ADDR, \ + Bit0,Bit1,Bit2,Bit3,Bit4,Bit5,Bit6,Bit7, \ + _B0,_B1,_B2,_B3,_B4,_B5,_B6,_B7) + +#define SFR_W_N(_ADDR, _NAME, _B15, _B14, _B13, _B12, _B11, _B10, _B9, _B8, \ + _B7, _B6, _B5, _B4, _B3, _B2, _B1, _B0) \ + SFR_W_BITS_N(_NAME, _ADDR, \ + Bit0,Bit1,Bit2,Bit3,Bit4,Bit5,Bit6,Bit7, \ + Bit8,Bit9,Bit10,Bit11,Bit12,Bit13,Bit14,Bit15, \ + _B0,_B1,_B2,_B3,_B4,_B5,_B6,_B7, \ + _B8,_B9,_B10,_B11,_B12,_B13,_B14,_B15) + +#endif /* __IOMACRO_H */ diff --git a/ATmega48/MEGA48/Lib/cl1s-ec.r90 b/ATmega48/MEGA48/Lib/cl1s-ec.r90 new file mode 100644 index 0000000..cb214e0 Binary files /dev/null and b/ATmega48/MEGA48/Lib/cl1s-ec.r90 differ diff --git a/ATmega48/Source/c_armcomm.c b/ATmega48/Source/c_armcomm.c new file mode 100644 index 0000000..6d5853d --- /dev/null +++ b/ATmega48/Source/c_armcomm.c @@ -0,0 +1,601 @@ +// +// Programmer +// +// Date init 14.12.2004 +// +// Reviser $Author:: Dktochpe $ +// +// Revision date $Date:: 10-11-05 15:35 $ +// +// Filename $Workfile:: c_armcomm.c $ +// +// Version $Revision:: 17 $ +// +// Archive $Archive:: /LMS2006/Sys01/Ioctrl/Firmware/Source/c_armcom $ +// +// Platform C +// + +/* Event Function State +--------------------------------------- ------------------------------------- ----------------------------------- + +Voltage > 4,3V, wakeup or reset button Brake motor drivers RESET + POWERUP + Batt measument off POWERUP_CHECK_FOR_RECHARGEABLE + Wait 10 mS + Rechargeable if switch > 0,5V + Batt measurement on POWERUP_CHECK_VOLTAGE_FOR_ARM_ON + Wait 10 mS + Check voltage for ARM on <= 11,8V + Batt measument off POWERUP_DISABLE_AMP + Wait 10 mS + Turn ARM on POWERUP_TURN_ARM_ON + Brake off + Wait 500 mS POWERUP_ENABLE_AMP + Batt measurement on + Check voltage for ARM on >= 6,5V (rechg) POWERUP_CHECK_RECHARGEABLE_VOLTAGE +Samba active Reset copyright timer ON + Read all inputs and update buttons ON_RUNNING + Check ARM communicating + Check for high voltage/samba button + Control led (Batt measurement on/off) + Check for ARM samba request + Check for ARM powerdown request + Check for ARM copyright invalid + + +High voltage (batt > 12,2V or samba button) Turn of input current drive ON_HIGH_VOLTAGE + Turn off ARM + Brake output drivers + Batt measurement off ON_CHECK_BUTTON + Check samba button + + +Power down request or copyright invalid POWERDOWN + Batt measurement off POWERDOWN_DISABLE_AMP + Wait 10 mS + Turn ARM off POWERDOWN_TURN_ARM_OFF + Wait 1 sec +Rechargeable < 6,5V OFF + SLEEP + + +Samba button (long press) or samba request SAMBA + Wait 100 mS SAMBA_ACTIVATE + Batt measurement forced high SAMBA_TURN_ARM_OFF_AND_WAIT + Batt measurement off + Turn ARM off + Wait 1 sec + Turn ARM on SAMBA_TURN_ARM_ON_AND_WAIT + Wait 10 sec + Turn ARM off SAMBA_TURN_ARM_OFF_FOR_RESET + Remove batt measurement force + Wait 1 sec + Turn ARM on SAMBA_TURN_ARM_ON + ON + + +*/ + +#include "stdconst.h" +#include "c_armcomm.h" +#include "d_power.h" +#include "d_output.h" +#include "d_input.h" +#include "d_button.h" +#include "d_armcomm.h" +#include "d_timer.h" + + +#define INPUTPOWER_ONTIME 3000 // [uS] time between input A/D samples +#define COPYRIGHT_TIME 300000L // [mS] time to power down if no copy right string found + +#define POWERUP_ENABLE_MEASURE_TIME 10 // [mS] time to enable voltage divider for measurement +#define POWERUP_DISABLE_MEASURE_TIME 10 // [mS] time to disable voltage divider for measurement +#define POWERUP_DISABLE_AMP_TIME 10 // [mS] time after amp is disenabled +#define POWERUP_ENABLE_AMP_TIME 100 // [mS] time before amp is enabled +#define POWERUP_RECHARGE_TEST_TIME 1000 // [mS] time testing voltage if rechargeable (to show low batt on display) +#define ON_ARM_TIMEOUT_TIME 2000 // [mS] time between ARM communication (max) +#define LED_TOGGLE_TIME 500 // [mS] time between led toggles on and off +#define CHECK_TEST_BUTTON_TIME 2000 // [mS] time for stable button reading (samba activate) +#define BUTTON_ACCEPT_TIME 200 // [mS] time from samba accept to actual active +#define SAMBA_POWEROFF_TIME 1000 // [mS] time for ARM power to drop +#define SAMBA_BOOT_TIME 10000 // [mS] time for copying samba boot loader +#define POWEROFF_TIME 1000 // [mS] time from ARM off to sleep + +#define RECHARGEABLE_SWITCH_VOLTAGE 500L // [mV] trigger point for rechageable battery detect switch +#define ARM_POWERUP_MAX_VOLTAGE 11800L // [mV] maximum allowable voltage when turning on ARM +#define ARM_ON_MAX_VOLTAGE 12200L // [mV] maximum allowable voltage when running ARM +#define ARM_ON_OK_VOLTAGE 10000L // [mV] maximum allowable voltage when turning on ARM (after high voltage) +#define ARM_ON_MIN_VOLTAGE 6500L // [mV] minimum allowable voltage when turning on ARM (rechargeable) + + + + + +// Use compiler to calculate ticks from time +#define INPUTPOWER_ONTICK (UBYTE)(((ULONG)TIMER_RESOLUTION / (1000000L / (ULONG)INPUTPOWER_ONTIME))) +#define COPYRIGHT_TICK (ULONG)(((ULONG)COPYRIGHT_TIME * 1000L) / (ULONG)INPUTPOWER_ONTIME) +#define POWERUP_ENABLE_MEASURE_TICK (UWORD)(((ULONG)POWERUP_ENABLE_MEASURE_TIME * 1000L) / (ULONG)INPUTPOWER_ONTIME) +#define POWERUP_DISABLE_MEASURE_TICK (UWORD)(((ULONG)POWERUP_DISABLE_MEASURE_TIME * 1000L) / (ULONG)INPUTPOWER_ONTIME) +#define POWERUP_DISABLE_AMP_TICK (UWORD)(((ULONG)POWERUP_DISABLE_AMP_TIME * 1000L) / (ULONG)INPUTPOWER_ONTIME) +#define POWERUP_ENABLE_AMP_TICK (UWORD)(((ULONG)POWERUP_ENABLE_AMP_TIME * 1000L) / (ULONG)INPUTPOWER_ONTIME) +#define POWERUP_RECHARGE_TEST_TICK (UWORD)(((ULONG)POWERUP_RECHARGE_TEST_TIME * 1000L) / (ULONG)INPUTPOWER_ONTIME) +#define ON_ARM_TIMEOUT_TICK (UWORD)(((ULONG)ON_ARM_TIMEOUT_TIME * 1000L) / (ULONG)INPUTPOWER_ONTIME) +#define LED_TOGGLE_TICK (UWORD)(((ULONG)LED_TOGGLE_TIME * 1000L) / (ULONG)INPUTPOWER_ONTIME) +#define CHECK_TEST_BUTTON_TICK (UWORD)(((ULONG)CHECK_TEST_BUTTON_TIME * 1000L) / (ULONG)INPUTPOWER_ONTIME) +#define SAMBA_POWEROFF_TICK (UWORD)(((ULONG)SAMBA_POWEROFF_TIME * 1000L) / (ULONG)INPUTPOWER_ONTIME) +#define SAMBA_BOOT_TICK (UWORD)(((ULONG)SAMBA_BOOT_TIME * 1000L) / (ULONG)INPUTPOWER_ONTIME) +#define BUTTON_ACCEPT_TICK (UWORD)(((ULONG)BUTTON_ACCEPT_TIME * 1000L) / (ULONG)INPUTPOWER_ONTIME) +#define POWEROFF_TICK (UWORD)(((ULONG)POWEROFF_TIME * 1000L) / (ULONG)INPUTPOWER_ONTIME) + + +// Use compiler to calculate counts from voltage +#define ADC_REFERENCE 5000L // [mv] +#define ADC_RESOLUTION 1023L // [Count] +#define RESISTOR_HIGH 22000L // [ohm] +#define RESISTOR_LOW 12000L // [ohm] +#define RECHARGEABLE_SWITCH_COUNT (UWORD)(((((RECHARGEABLE_SWITCH_VOLTAGE * RESISTOR_LOW) / (RESISTOR_LOW + RESISTOR_HIGH)) * ADC_RESOLUTION) / ADC_REFERENCE)) +#define ARM_POWERUP_MAX_COUNT (UWORD)(((((ARM_POWERUP_MAX_VOLTAGE * RESISTOR_LOW) / (RESISTOR_LOW + RESISTOR_HIGH)) * ADC_RESOLUTION) / ADC_REFERENCE)) +#define ARM_ON_MAX_COUNT (UWORD)(((((ARM_ON_MAX_VOLTAGE * RESISTOR_LOW) / (RESISTOR_LOW + RESISTOR_HIGH)) * ADC_RESOLUTION) / ADC_REFERENCE)) +#define ARM_ON_OK_COUNT (UWORD)(((((ARM_ON_OK_VOLTAGE * RESISTOR_LOW) / (RESISTOR_LOW + RESISTOR_HIGH)) * ADC_RESOLUTION) / ADC_REFERENCE)) +#define ARM_ON_MIN_COUNT (UWORD)(((((ARM_ON_MIN_VOLTAGE * RESISTOR_LOW) / (RESISTOR_LOW + RESISTOR_HIGH)) * ADC_RESOLUTION) / ADC_REFERENCE)) + +#define TEST_BUTTON_VALUE (ADC_RESOLUTION - 10) + +// State machine states +enum +{ + RESET, + POWERUP, + POWERUP_CHECK_FOR_RECHARGEABLE, + POWERUP_CHECK_VOLTAGE_FOR_ARM_ON, + POWERUP_DISABLE_AMP, + POWERUP_TURN_ARM_ON, + POWERUP_ENABLE_AMP, + POWERUP_CHECK_RECHARGEABLE_VOLTAGE, + ON, + ON_RUNNING, + ON_HIGH_VOLTAGE, + ON_CHECK_BUTTON, + SAMBA, + SAMBA_ACTIVATE, + SAMBA_TURN_ARM_OFF_AND_WAIT, + SAMBA_TURN_ARM_ON_AND_WAIT, + SAMBA_TURN_ARM_OFF_FOR_RESET, + SAMBA_TURN_ARM_ON, + POWERDOWN, + POWERDOWN_DISABLE_AMP, + POWERDOWN_TURN_ARM_OFF, + OFF, + SLEEP +}; + + +UBYTE State; +UBYTE OldState; +UBYTE OverwriteFloat; +UWORD StateTimer; +UBYTE Rechargeable; +UWORD ArmTimer; +UBYTE ArmFucked; +UBYTE LedState; +UWORD ButtonTimer; +ULONG CopyRightTimer; + + +void cArmCommInit(void) +{ + dPowerInit(); + dOutputInit(); + dInputInit(); + dButtonInit(); + dArmCommInit(); + dTimerInit(); + + State = RESET; + OldState = ~State; +} + + +UBYTE cArmCommCtrl(void) +{ + UBYTE Result = TRUE; + + // Update state machine if timeout (or RESET) + if ((dTimerRead() >= INPUTPOWER_ONTICK) || (State == RESET)) + { + dTimerClear(); + + // Maintain StateTimer (clear if state changes else increament) + if (State != OldState) + { + OldState = State; + StateTimer = 0; + } + else + { + StateTimer++; + } + + // STATE MACHINE + switch (State) + { + + case RESET : + { + if (!StateTimer) + { + OverwriteFloat = TRUE; + State = POWERUP; + } + } + break; + + case POWERUP : + { + State = POWERUP_CHECK_FOR_RECHARGEABLE; + } + break; + + case POWERUP_CHECK_FOR_RECHARGEABLE : + { + if (!StateTimer) + { + dPowerDeselect(); + } + if (StateTimer >= POWERUP_DISABLE_MEASURE_TICK) + { + if (dPowerConvert() > RECHARGEABLE_SWITCH_COUNT) + { + Rechargeable = TRUE; + } + dPowerRechargeable(Rechargeable); + State = POWERUP_CHECK_VOLTAGE_FOR_ARM_ON; + } + } + break; + + case POWERUP_CHECK_VOLTAGE_FOR_ARM_ON : + { + if (!StateTimer) + { + dPowerSelect(); + } + if (StateTimer >= POWERUP_ENABLE_MEASURE_TICK) + { + if (dPowerConvert() <= ARM_POWERUP_MAX_COUNT) + { + State = POWERUP_DISABLE_AMP; + } + } + } + break; + + case POWERUP_DISABLE_AMP : + { + if (!StateTimer) + { + dPowerDeselect(); + } + if (StateTimer >= POWERUP_DISABLE_AMP_TICK) + { + State = POWERUP_TURN_ARM_ON; + } + } + break; + + case POWERUP_TURN_ARM_ON : + { + dPowerWriteOn(TRUE); + OverwriteFloat = FALSE; + State = POWERUP_ENABLE_AMP; + } + break; + + case POWERUP_ENABLE_AMP : + { + if (StateTimer >= POWERUP_ENABLE_AMP_TICK) + { + dPowerSelect(); + State = POWERUP_CHECK_RECHARGEABLE_VOLTAGE; + } + } + break; + + case POWERUP_CHECK_RECHARGEABLE_VOLTAGE : + { + if (Rechargeable == TRUE) + { + if (dPowerConvert() < ARM_ON_MIN_COUNT) + { + if (StateTimer >= POWERUP_RECHARGE_TEST_TICK) + { + State = OFF; + } + } + else + { + State = ON; + } + } + else + { + State = ON; + } + } + break; + + case ON : + { + CopyRightTimer = 0L; + State = ON_RUNNING; + } + break; + + case ON_RUNNING : + { + + // Read all inputs + dInputSelect(0); + dInputConvert(0); + dInputConvert(0); + dInputDeselect(0); + + dInputSelect(1); + dInputConvert(1); + dInputConvert(1); + dInputDeselect(1); + + dInputSelect(2); + dInputConvert(2); + dInputConvert(2); + dInputDeselect(2); + + dInputSelect(3); + dInputConvert(3); + dInputConvert(3); + dInputDeselect(3); + + // Update buttons + dButtonUpdate(); + + // Check for ARM communication + if (dArmCommCheck() == TRUE) + { + ArmTimer = 0; + ArmFucked = FALSE; + } + + if (ArmTimer >= ON_ARM_TIMEOUT_TICK) + { + ArmFucked = TRUE; + } + else + { + ArmTimer++; + } + + // Check for high voltage + dPowerSelect(); + if (dPowerConvert() > ARM_ON_MAX_COUNT) + { + State = ON_HIGH_VOLTAGE; + } + + // Control led + if (ArmFucked == TRUE) + { + if (StateTimer >= LED_TOGGLE_TICK) + { + StateTimer = 0; + if (LedState == TRUE) + { + LedState = FALSE; + } + else + { + LedState = TRUE; + } + } + } + else + { + LedState = TRUE; + } + + if (LedState == FALSE) + { + dPowerDeselect(); + } + + // Check for SAMBA request + if (dPowerReadBoot() == TRUE) + { + State = SAMBA; + } + + // Check for POWERDOWN request + if (dPowerReadOn() == FALSE) + { + State = POWERDOWN; + } + + // Check for CopyRight valid + if (dArmCommCopyRight() != TRUE) + { + if (++CopyRightTimer >= COPYRIGHT_TICK) + { + State = POWERDOWN; + } + } + } + break; + + case ON_HIGH_VOLTAGE : + { + dInputInit(); + dPowerWriteOn(FALSE); + OverwriteFloat = TRUE; + ButtonTimer = CHECK_TEST_BUTTON_TICK; + State = ON_CHECK_BUTTON; + } + break; + + case ON_CHECK_BUTTON : + { + dPowerSelect(); + if (ButtonTimer) + { + dPowerDeselect(); + if (dPowerConvert() >= TEST_BUTTON_VALUE) + { + ButtonTimer++; + if (ButtonTimer > (CHECK_TEST_BUTTON_TICK * 2)) + { + dPowerSelect(); + State = SAMBA; + } + } + else + { + ButtonTimer--; + } + } + else + { + if (dPowerConvert() <= ARM_ON_OK_COUNT) + { + State = RESET; + } + } + } + break; + + case POWERDOWN : + { + State = POWERDOWN_DISABLE_AMP; + } + break; + + case POWERDOWN_DISABLE_AMP : + { + if (!StateTimer) + { + dPowerDeselect(); + } + if (StateTimer >= POWERUP_DISABLE_AMP_TICK) + { + State = POWERDOWN_TURN_ARM_OFF; + } + } + break; + + case POWERDOWN_TURN_ARM_OFF : + { + if (!StateTimer) + { + dPowerWriteOn(FALSE); + } + if (StateTimer >= POWEROFF_TICK) + { + State = OFF; + } + } + break; + + case OFF : + { + State = SLEEP; + } + break; + + case SAMBA : + { + State = SAMBA_ACTIVATE; + } + break; + + case SAMBA_ACTIVATE : + { + if (++StateTimer >= BUTTON_ACCEPT_TICK) + { + State = SAMBA_TURN_ARM_OFF_AND_WAIT; + } + } + break; + + case SAMBA_TURN_ARM_OFF_AND_WAIT : + { + if (!StateTimer) + { + dPowerHigh(); + dPowerDeselect(); + dPowerWriteOn(FALSE); + } + if (++StateTimer >= SAMBA_POWEROFF_TICK) + { + State = SAMBA_TURN_ARM_ON_AND_WAIT; + } + } + break; + + case SAMBA_TURN_ARM_ON_AND_WAIT : + { + if (!StateTimer) + { + dPowerWriteOn(TRUE); + } + if (++StateTimer >= SAMBA_BOOT_TICK) + { + State = SAMBA_TURN_ARM_OFF_FOR_RESET; + } + } + break; + + case SAMBA_TURN_ARM_OFF_FOR_RESET : + { + if (!StateTimer) + { + dPowerWriteOn(FALSE); + dPowerFloat(); + } + if (++StateTimer >= SAMBA_POWEROFF_TICK) + { + State = SAMBA_TURN_ARM_ON; + } + } + break; + + case SAMBA_TURN_ARM_ON : + { + dPowerWriteOn(TRUE); + State = ON; + } + break; + + case SLEEP : + { + Result = FALSE; + } + break; + + } + } + + // Update allways output + dOutputUpdate(OverwriteFloat); + + return(Result); +} + + +void cArmCommExit(void) +{ + dTimerExit(); + dArmCommExit(); + dButtonExit(); + dInputExit(); + dOutputExit(); + dPowerExit(); +} diff --git a/ATmega48/Source/c_armcomm.h b/ATmega48/Source/c_armcomm.h new file mode 100644 index 0000000..239ab73 --- /dev/null +++ b/ATmega48/Source/c_armcomm.h @@ -0,0 +1,44 @@ +// +// Programmer +// +// Date init 14.12.2004 +// +// Reviser $Author:: Dkandlun $ +// +// Revision date $Date:: 28-12-04 14:19 $ +// +// Filename $Workfile:: c_armcomm.h $ +// +// Version $Revision:: 1 $ +// +// Archive $Archive:: /LMS2006/Sys01/Peripheral/Firmware/Source/c_ar $ +// +// Platform C +// + + +#ifndef C_ARMCOMM +#define C_ARMCOMM + +#define NOS_OF_MOTORS 4 +#define NOS_OF_SENSORS 4 +#define NOS_OF_BTNS 5 + +typedef struct +{ + UBYTE TimerTik; + UBYTE MotorStatus[NOS_OF_MOTORS]; + UBYTE MotorSpeed[NOS_OF_MOTORS]; +}InputMap; + +typedef struct +{ + SWORD SensorValue[NOS_OF_SENSORS]; + UBYTE ButtonState[NOS_OF_BTNS]; +}OutputMap; + +void cArmCommInit(void); +UBYTE cArmCommCtrl(void); +void cArmCommExit(void); + +#endif diff --git a/ATmega48/Source/d_armcomm.c b/ATmega48/Source/d_armcomm.c new file mode 100644 index 0000000..bdcce63 --- /dev/null +++ b/ATmega48/Source/d_armcomm.c @@ -0,0 +1,48 @@ +// +// Programmer +// +// Date init 14.12.2004 +// +// Reviser $Author:: Dktochpe $ +// +// Revision date $Date:: 28-10-05 13:46 $ +// +// Filename $Workfile:: d_armcomm.c $ +// +// Version $Revision:: 5 $ +// +// Archive $Archive:: /LMS2006/Sys01/Ioctrl/Firmware/Source/d_armcom $ +// +// Platform C +// + + + +#include "stdconst.h" +#include "m_sched.h" +#include "c_armcomm.h" +#include "d_armcomm.r" + + +void dArmCommInit(void) +{ + ARMCOMMInit; +} + + +UBYTE dArmCommCheck(void) +{ + return (ARMCOMMCheck); +} + + +UBYTE dArmCommCopyRight(void) +{ + return (ARMCOMMCopyRight); +} + + +void dArmCommExit(void) +{ + ARMCOMMExit; +} diff --git a/ATmega48/Source/d_armcomm.h b/ATmega48/Source/d_armcomm.h new file mode 100644 index 0000000..416753e --- /dev/null +++ b/ATmega48/Source/d_armcomm.h @@ -0,0 +1,28 @@ +// +// Programmer +// +// Date init 14.12.2004 +// +// Reviser $Author:: Dktochpe $ +// +// Revision date $Date:: 28-10-05 13:46 $ +// +// Filename $Workfile:: d_armcomm.h $ +// +// Version $Revision:: 4 $ +// +// Archive $Archive:: /LMS2006/Sys01/Ioctrl/Firmware/Source/d_armcom $ +// +// Platform C +// + + +#ifndef D_ARMCOMM +#define D_ARMCOMM + +void dArmCommInit(void); +UBYTE dArmCommCheck(void); +UBYTE dArmCommCopyRight(void); +void dArmCommExit(void); + +#endif diff --git a/ATmega48/Source/d_armcomm.r b/ATmega48/Source/d_armcomm.r new file mode 100644 index 0000000..42712aa --- /dev/null +++ b/ATmega48/Source/d_armcomm.r @@ -0,0 +1,253 @@ +// +// Programmer +// +// Date init 14.12.2004 +// +// Reviser $Author:: Dktochpe $ +// +// Revision date $Date:: 28-10-05 13:46 $ +// +// Filename $Workfile:: d_armcomm.r $ +// +// Version $Revision:: 15 $ +// +// Archive $Archive:: /LMS2006/Sys01/Ioctrl/Firmware/Source/d_armcom $ +// +// Platform C +// + +#ifdef ATMEGAX8 + +/**************************************************************************** + TWI State codes +****************************************************************************/ + +#define TWI_START 0x08 // START has been transmitted +#define TWI_REP_START 0x10 // Repeated START has been transmitted +#define TWI_ARB_LOST 0x38 // Arbitration lost + +// TWI Master Transmitter staus codes +#define TWI_MTX_ADR_ACK 0x18 // SLA+W has been tramsmitted and ACK received +#define TWI_MTX_ADR_NACK 0x20 // SLA+W has been tramsmitted and NACK received +#define TWI_MTX_DATA_ACK 0x28 // Data byte has been tramsmitted and ACK received +#define TWI_MTX_DATA_NACK 0x30 // Data byte has been tramsmitted and NACK received + +// TWI Master Receiver staus codes +#define TWI_MRX_ADR_ACK 0x40 // SLA+R has been tramsmitted and ACK received +#define TWI_MRX_ADR_NACK 0x48 // SLA+R has been tramsmitted and NACK received +#define TWI_MRX_DATA_ACK 0x50 // Data byte has been received and ACK tramsmitted +#define TWI_MRX_DATA_NACK 0x58 // Data byte has been received and NACK tramsmitted + +// TWI Slave Transmitter staus codes +#define TWI_STX_ADR_ACK 0xA8 // Own SLA+R has been received; ACK has been returned +#define TWI_STX_ADR_ACK_M_ARB_LOST 0xB0 // Arbitration lost in SLA+R/W as Master; own SLA+R has been received; ACK has been returned +#define TWI_STX_DATA_ACK 0xB8 // Data byte in TWDR has been transmitted; ACK has been received +#define TWI_STX_DATA_NACK 0xC0 // Data byte in TWDR has been transmitted; NOT ACK has been received +#define TWI_STX_DATA_ACK_LAST_BYTE 0xC8 // Last data byte in TWDR has been transmitted (TWEA = “0”); ACK has been received + +// TWI Slave Receiver staus codes +#define TWI_SRX_ADR_ACK 0x60 // Own SLA+W has been received ACK has been returned +#define TWI_SRX_ADR_ACK_M_ARB_LOST 0x68 // Arbitration lost in SLA+R/W as Master; own SLA+W has been received; ACK has been returned +#define TWI_SRX_GEN_ACK 0x70 // General call address has been received; ACK has been returned +#define TWI_SRX_GEN_ACK_M_ARB_LOST 0x78 // Arbitration lost in SLA+R/W as Master; General call address has been received; ACK has been returned +#define TWI_SRX_ADR_DATA_ACK 0x80 // Previously addressed with own SLA+W; data has been received; ACK has been returned +#define TWI_SRX_ADR_DATA_NACK 0x88 // Previously addressed with own SLA+W; data has been received; NOT ACK has been returned +#define TWI_SRX_GEN_DATA_ACK 0x90 // Previously addressed with general call; data has been received; ACK has been returned +#define TWI_SRX_GEN_DATA_NACK 0x98 // Previously addressed with general call; data has been received; NOT ACK has been returned +#define TWI_SRX_STOP_RESTART 0xA0 // A STOP condition or repeated START condition has been received while still addressed as Slave + +// TWI Miscellaneous status codes +#define TWI_NO_STATE 0xF8 // No relevant state information available; TWINT = “0” +#define TWI_BUS_ERROR 0x00 // Bus error due to an illegal START or STOP condition + + + +/***********************************************************************************/ +/*********************** Declaration of variables *******************************/ +/***********************************************************************************/ + +#define ADDRESS 1 +#define INBYTES BYTES_TO_TX // (sizeof(IoToAvr)) +#define OUTBYTES BYTES_TO_RX // (sizeof(IoFromAvr)) + +__flash UBYTE CopyRightString[COPYRIGHTSTRINGLENGTH + 1] = COPYRIGHTSTRING; + +static UBYTE I2CInByte; +static UBYTE I2CInBuffer[INBYTES + 1]; +static UBYTE *pI2CInBuffer; +static UBYTE I2CInPointer; +static UBYTE I2COutBuffer[OUTBYTES + 1]; +static UBYTE *pI2COutBuffer; +static UBYTE I2COutPointer; +static UBYTE Chksum; +static UBYTE I2CInState; +static UBYTE ArmCommFlag; +static UBYTE ArmCopyRightValid; + +#define ARMCOMMInit TWAR = (UBYTE)(ADDRESS << 1);\ + TWCR = 0xC5;\ + ArmCommFlag = FALSE;\ + ArmCopyRightValid = FALSE + + +#pragma vector=TWI_vect +__interrupt void I2CInterrupt(void) +{ + switch ((TWSR & 0xF8)) + { + + // Write command + + case TWI_SRX_ADR_ACK : + { + I2CInPointer = 0; + I2CInState = 0; + } + break; + + case TWI_SRX_ADR_DATA_ACK : + { + I2CInByte = TWDR; + + switch (I2CInState) + { + case 0 : + { + if (I2CInByte != 0xCC) + { + I2CInBuffer[I2CInPointer++] = I2CInByte; + I2CInState++; + } + else + { + I2CInState = 2; + } + } + break; + + case 1 : + { + I2CInBuffer[I2CInPointer++] = I2CInByte; + if (I2CInPointer >= (INBYTES + 1)) + { + Chksum = 0; + for (I2CInPointer = 0;I2CInPointer < (INBYTES + 1);I2CInPointer++) + { + Chksum += I2CInBuffer[I2CInPointer]; + } + + if (Chksum == 0xFF) + { + pI2CInBuffer = (UBYTE*)&IoToAvr; + for (I2CInPointer = 0;I2CInPointer < INBYTES;I2CInPointer++) + { + *pI2CInBuffer = I2CInBuffer[I2CInPointer]; + pI2CInBuffer++; + } + ArmCommFlag = TRUE; + } + I2CInState = 99; + } + } + break; + + case 2 : + { + if (I2CInByte == CopyRightString[I2CInPointer++]) + { + if (I2CInPointer >= COPYRIGHTSTRINGLENGTH) + { + ArmCopyRightValid = TRUE; + } + } + else + { + I2CInState = 99; + } + } + break; + + default : + { + } + break; + + } + } + break; + + // Read command + + case TWI_STX_ADR_ACK : + { + Chksum = 0; + pI2COutBuffer = (UBYTE*)&IoFromAvr; + for (I2COutPointer = 0;I2COutPointer < OUTBYTES;I2COutPointer++) + { + I2COutBuffer[I2COutPointer] = *pI2COutBuffer; + Chksum += *pI2COutBuffer; + pI2COutBuffer++; + } + I2COutBuffer[I2COutPointer] = ~Chksum; + I2COutPointer = 0; + TWDR = I2COutBuffer[I2COutPointer++]; + } + break; + + case TWI_STX_DATA_ACK : + { + if (I2COutPointer >= (OUTBYTES + 1)) + { + + } + else + { + TWDR = I2COutBuffer[I2COutPointer++]; + } + } + break; + case TWI_NO_STATE: + { + TWCR |= 0x90; + } + break; + case TWI_BUS_ERROR: + { + UBYTE volatile Tmp; + Tmp = 1; + TWCR &= ~0x20; + Tmp = 0; + TWCR |= 0x90; + Tmp = 2; + } + break; + + default: + { + } + break; + + } + TWCR |= 0x80; +} + +UBYTE ArmCommCheck(void) +{ + UBYTE Result; + + Result = ArmCommFlag; + ArmCommFlag = FALSE; + + return (Result); +} + + +#define ARMCOMMCheck ArmCommCheck() + +#define ARMCOMMCopyRight ArmCopyRightValid + +#define ARMCOMMExit PORTC &= ~0x30;\ + DDRC |= 0x30;\ + TWCR = 0x80 + +#endif diff --git a/ATmega48/Source/d_button.c b/ATmega48/Source/d_button.c new file mode 100644 index 0000000..5fd3ebf --- /dev/null +++ b/ATmega48/Source/d_button.c @@ -0,0 +1,40 @@ +// +// Programmer +// +// Date init 14.12.2004 +// +// Reviser $Author:: Dktochpe $ +// +// Revision date $Date:: 28-10-05 13:46 $ +// +// Filename $Workfile:: d_button.c $ +// +// Version $Revision:: 7 $ +// +// Archive $Archive:: /LMS2006/Sys01/Ioctrl/Firmware/Source/d_button $ +// +// Platform C +// + +#include "stdconst.h" +#include "m_sched.h" +#include "d_button.h" +#include "d_button.r" + + +void dButtonInit(void) +{ + BUTTONInit; +} + + +void dButtonUpdate(void) +{ + IoFromAvr.Buttons = BUTTONRead; +} + + +void dButtonExit(void) +{ + BUTTONExit; +} diff --git a/ATmega48/Source/d_button.h b/ATmega48/Source/d_button.h new file mode 100644 index 0000000..3fc62c8 --- /dev/null +++ b/ATmega48/Source/d_button.h @@ -0,0 +1,27 @@ +// +// Programmer +// +// Date init 14.12.2004 +// +// Reviser $Author:: Dktochpe $ +// +// Revision date $Date:: 28-10-05 13:46 $ +// +// Filename $Workfile:: d_button.h $ +// +// Version $Revision:: 3 $ +// +// Archive $Archive:: /LMS2006/Sys01/Ioctrl/Firmware/Source/d_button $ +// +// Platform C +// + + +#ifndef D_BUTTON +#define D_BUTTON + +void dButtonInit(void); +void dButtonUpdate(void); +void dButtonExit(void); + +#endif diff --git a/ATmega48/Source/d_button.r b/ATmega48/Source/d_button.r new file mode 100644 index 0000000..a1ab5c5 --- /dev/null +++ b/ATmega48/Source/d_button.r @@ -0,0 +1,68 @@ +// +// Programmer +// +// Date init 14.12.2004 +// +// Reviser $Author:: Dktochpe $ +// +// Revision date $Date:: 2-09-05 14:37 $ +// +// Filename $Workfile:: d_button.r $ +// +// Version $Revision:: 10 $ +// +// Archive $Archive:: /LMS2006/Sys01/Ioctrl/Firmware/Source/d_button $ +// +// Platform C +// + +#ifdef ATMEGAX8 + +#pragma language=extended +#pragma vector = INT1_vect +__interrupt void OnInterrupt(void) +{ + EIMSK &= ~0x02; + HARDWAREReset; +} + +#define BUTTONInit {\ + EIMSK &= ~0x02;\ + PORTD |= 0x08;\ + DDRD &= ~0x08;\ + PORTC &= ~0x08;\ + DDRC &= ~0x08;\ + DIDR0 |= 0x08;\ + } + + +UWORD ButtonRead(void) +{ + UWORD Result; + + ADMUX = 0x43; + ADCSRA &= ~0x07; + ADCSRA |= 0x05; + ADCSRA |= 0x40; + while ((ADCSRA & 0x40)); + ADCSRA |= 0x40; + while ((ADCSRA & 0x40)); + Result = ADC; + if (!(PIND & 0x08)) + { + Result += 0x7FF; + } + return (Result); +} + + +#define BUTTONRead ButtonRead() + +#define BUTTONExit {\ + PORTD |= 0x08;\ + DDRD &= ~0x08;\ + EICRA &= ~0x0C;\ + EIFR |= 0x02;\ + EIMSK |= 0x02;\ + } +#endif diff --git a/ATmega48/Source/d_input.c b/ATmega48/Source/d_input.c new file mode 100644 index 0000000..e7d2c42 --- /dev/null +++ b/ATmega48/Source/d_input.c @@ -0,0 +1,52 @@ +// +// Programmer +// +// Date init 14.12.2004 +// +// Reviser $Author:: Dktochpe $ +// +// Revision date $Date:: 16-06-05 14:32 $ +// +// Filename $Workfile:: d_input.c $ +// +// Version $Revision:: 3 $ +// +// Archive $Archive:: /LMS2006/Sys01/Ioctrl/Firmware/Source/d_input. $ +// +// Platform C +// + +#include "stdconst.h" +#include "m_sched.h" +#include "d_input.h" +#include "d_input.r" + + +void dInputInit(void) +{ + INPUTInit; +} + + +void dInputSelect(UBYTE No) +{ + INPUTSelect(No); +} + + +void dInputConvert(UBYTE No) +{ + INPUTConvert(No); +} + + +void dInputDeselect(UBYTE No) +{ + INPUTDeselect(No); +} + + +void dInputExit(void) +{ + INPUTExit; +} diff --git a/ATmega48/Source/d_input.h b/ATmega48/Source/d_input.h new file mode 100644 index 0000000..15ef795 --- /dev/null +++ b/ATmega48/Source/d_input.h @@ -0,0 +1,29 @@ +// +// Programmer +// +// Date init 14.12.2004 +// +// Reviser $Author:: Dktochpe $ +// +// Revision date $Date:: 16-06-05 14:32 $ +// +// Filename $Workfile:: d_input.h $ +// +// Version $Revision:: 3 $ +// +// Archive $Archive:: /LMS2006/Sys01/Ioctrl/Firmware/Source/d_input. $ +// +// Platform C +// + + +#ifndef D_INPUT +#define D_INPUT + +void dInputInit(void); +void dInputSelect(UBYTE No); +void dInputConvert(UBYTE No); +void dInputDeselect(UBYTE No); +void dInputExit(void); + +#endif diff --git a/ATmega48/Source/d_input.r b/ATmega48/Source/d_input.r new file mode 100644 index 0000000..88f1eae --- /dev/null +++ b/ATmega48/Source/d_input.r @@ -0,0 +1,209 @@ +// +// Programmer +// +// Date init 14.12.2004 +// +// Reviser $Author:: Dktochpe $ +// +// Revision date $Date:: 2-09-05 14:37 $ +// +// Filename $Workfile:: d_input.r $ +// +// Version $Revision:: 13 $ +// +// Archive $Archive:: /LMS2006/Sys01/Ioctrl/Firmware/Source/d_input. $ +// +// Platform C +// + +#ifdef ATMEGAX8 + +// ADC input used for sensors : + +__flash UBYTE AdcInputNo[NOS_OF_AVR_INPUTS] = +{ + 7,0,1,6 +}; + +#define ONInputPower0 {\ + PORTD |= 0x02;\ + DDRD |= 0x02;\ + } + +#define OFFInputPower0 {\ + PORTD &= ~0x02;\ + DDRD |= 0x02;\ + } + +#define ONInputPower1 {\ + PORTD |= 0x01;\ + DDRD |= 0x01;\ + } + +#define OFFInputPower1 {\ + PORTD &= ~0x01;\ + DDRD |= 0x01;\ + } + +#define ONInputPower2 {\ + PORTB |= 0x10;\ + DDRB |= 0x10;\ + } + +#define OFFInputPower2 {\ + PORTB &= ~0x10;\ + DDRB |= 0x10;\ + } + +#define ONInputPower3 {\ + PORTB |= 0x20;\ + DDRB |= 0x20;\ + } + +#define OFFInputPower3 {\ + PORTB &= ~0x20;\ + DDRB |= 0x20;\ + } + +void OnInputPower(UBYTE No) +{ + switch (No) + { + case 0 : + { + ONInputPower0; + } + break; + + case 1 : + { + ONInputPower1; + } + break; + + case 2 : + { + ONInputPower2; + } + break; + + case 3 : + { + ONInputPower3; + } + break; + + } +} + +void OffInputPower(UBYTE No) +{ + switch (No) + { + case 0 : + { + OFFInputPower0; + } + break; + + case 1 : + { + OFFInputPower1; + } + break; + + case 2 : + { + OFFInputPower2; + } + break; + + case 3 : + { + OFFInputPower3; + } + break; + + } +} + + +#define STARTInput {\ + ADCSRA &= ~0x07;\ + ADCSRA |= 0x05;\ + ADCSRA |= 0x40;\ + } + +#define SELECTInput(No) {\ + UBYTE Mask;\ + Mask = 1 << AdcInputNo[No];\ + PORTC &= ~Mask;\ + DDRC &= ~Mask;\ + DIDR0 |= Mask;\ + ADMUX = 0x40 + (AdcInputNo[No]);\ + ADCSRA &= ~0x07;\ + ADCSRA |= 0x04;\ + ADCSRA |= 0x40;\ + } + +#define BUSYInput ((ADCSRA & 0x40)) + +#define READInput ADC + +#define EXITInput(No) {\ + UBYTE Mask;\ + Mask = 1 << AdcInputNo[No];\ + PORTC &= ~Mask;\ + DDRC |= Mask;\ + } + +#define INPUTInit {\ + UBYTE AdcTmp;\ + for (AdcTmp = 0;AdcTmp < NOS_OF_AVR_INPUTS;AdcTmp++)\ + {\ + OffInputPower(AdcTmp);\ + }\ + ADCSRA = 0x94;\ + ADCSRB = 0x00;\ + } + + +#define INPUTSelect(Inp) {\ + SELECTInput(Inp);\ + if ((IoToAvr.InputPower & (0x10 << Inp)))\ + {\ + OnInputPower(Inp);\ + }\ + else\ + {\ + OffInputPower(Inp);\ + }\ + } + + +#define INPUTConvert(Inp) {\ + STARTInput;\ + while (BUSYInput);\ + IoFromAvr.AdValue[Inp] = ADC;\ + } + + +#define INPUTDeselect(Inp) {\ + if ((IoToAvr.InputPower & (0x01 << Inp)))\ + {\ + OnInputPower(Inp);\ + }\ + } + + +#define INPUTExit {\ + UBYTE AdcTmp;\ + for (AdcTmp = 0;AdcTmp < NOS_OF_AVR_INPUTS;AdcTmp++)\ + {\ + OffInputPower(AdcTmp);\ + EXITInput(AdcTmp);\ + }\ + ADCSRA = 0x10;\ + } + +#endif diff --git a/ATmega48/Source/d_output.c b/ATmega48/Source/d_output.c new file mode 100644 index 0000000..7141ef9 --- /dev/null +++ b/ATmega48/Source/d_output.c @@ -0,0 +1,86 @@ +// +// Programmer +// +// Date init 14.12.2004 +// +// Reviser $Author:: Dktochpe $ +// +// Revision date $Date:: 17-08-05 8:20 $ +// +// Filename $Workfile:: d_output.c $ +// +// Version $Revision:: 13 $ +// +// Archive $Archive:: /LMS2006/Sys01/Ioctrl/Firmware/Source/d_output $ +// +// Platform C +// + +#include "stdconst.h" +#include "m_sched.h" +#include "d_output.h" +#include "d_output.r" + +static SBYTE Dutycycle[NOS_OF_AVR_OUTPUTS]; +static UBYTE Frequency; +static UBYTE LastOutputMode; + + +void dOutputInit(void) +{ + UBYTE Tmp; + + OUTPUTInit; + for (Tmp = 0;Tmp < NOS_OF_AVR_OUTPUTS;Tmp++) + { + Dutycycle[Tmp] = 0; + OUTPUTWrite(Tmp,Dutycycle[Tmp]); + } + LastOutputMode = 0x00; +} + + +void dOutputUpdate(UBYTE Brake) +{ + UBYTE Tmp; + UBYTE TmpMask; + + Tmp = IoToAvr.PwmFreq; + if (Frequency != Tmp) + { + if ((Tmp >= 1) && (Tmp <= 32)) + { + Frequency = Tmp; + OUTPUTFreq(Frequency); + for (Tmp = 0;Tmp < NOS_OF_AVR_OUTPUTS;Tmp++) + { + Dutycycle[Tmp] = 0; + } + } + } + + TmpMask = IoToAvr.OutputMode; + + for (Tmp = 0;Tmp < NOS_OF_AVR_OUTPUTS;Tmp++) + { + if (Brake == TRUE) + { + TmpMask |= (0x01 << Tmp); + IoToAvr.PwmValue[Tmp] = 0; + } + if ((Dutycycle[Tmp] != IoToAvr.PwmValue[Tmp]) || ((LastOutputMode ^ TmpMask) & (0x01 << Tmp))) + { + OUTPUTWriteBrakeMask(TmpMask); + Dutycycle[Tmp] = IoToAvr.PwmValue[Tmp]; + OUTPUTWrite(Tmp,Dutycycle[Tmp]); + } + } + LastOutputMode = TmpMask; + OUTPUTUpdate; +} + + +void dOutputExit(void) +{ + OUTPUTExit; +} diff --git a/ATmega48/Source/d_output.h b/ATmega48/Source/d_output.h new file mode 100644 index 0000000..d130ba9 --- /dev/null +++ b/ATmega48/Source/d_output.h @@ -0,0 +1,27 @@ +// +// Programmer +// +// Date init 14.12.2004 +// +// Reviser $Author:: Dktochpe $ +// +// Revision date $Date:: 16-06-05 14:32 $ +// +// Filename $Workfile:: d_output.h $ +// +// Version $Revision:: 4 $ +// +// Archive $Archive:: /LMS2006/Sys01/Ioctrl/Firmware/Source/d_output $ +// +// Platform C +// + + +#ifndef D_OUTPUT +#define D_OUTPUT + +void dOutputInit(void); +void dOutputUpdate(UBYTE Brake); +void dOutputExit(void); + +#endif diff --git a/ATmega48/Source/d_output.r b/ATmega48/Source/d_output.r new file mode 100644 index 0000000..f883bde --- /dev/null +++ b/ATmega48/Source/d_output.r @@ -0,0 +1,425 @@ +// +// Programmer +// +// Date init 14.12.2004 +// +// Reviser $Author:: Dktochpe $ +// +// Revision date $Date:: 2-09-05 14:37 $ +// +// Filename $Workfile:: d_output.r $ +// +// Version $Revision:: 17 $ +// +// Archive $Archive:: /LMS2006/Sys01/Ioctrl/Firmware/Source/d_output $ +// +// Platform C +// + +#ifdef ATMEGAX8 + +// Schematics Function PORT +// ---------- -------- ---- +// MAIN0 PB0 (PD6) +// MAPWM OC1B PB2 (PD5) +// MAIN1 PB3 (PD7) + +#define OUTPUTAFloat PORTB &= ~0x0B;\ + DDRB |= 0x0B;\ + TCCR1A &= ~0x30 + +#define OUTPUTABrake PORTB |= 0x0B;\ + DDRB |= 0x0B;\ + TCCR1A &= ~0x30 + +#define OUTPUTAInit OUTPUTABrake;\ + TCCR1A = 0x01;\ + TCCR1B = 0x09;\ + TCNT1 = 0;\ + OCR1B = 0;\ + TIMSK1 = 0x00 + +#define OUTPUTAFwdFloat(D) OUTPUTAFloat;\ + DDRB &= ~0x01;\ + TCCR1A |= 0x20;\ + OCR1B = D + +#define OUTPUTAFwdBrake(D) OUTPUTABrake;\ + PORTB &= ~0x08;\ + DDRB &= ~0x08;\ + TCCR1A |= 0x30;\ + OCR1B = D + +#define OUTPUTABwdFloat(D) OUTPUTAFloat;\ + DDRB &= ~0x08;\ + TCCR1A |= 0x20;\ + OCR1B = D + +#define OUTPUTABwdBrake(D) OUTPUTABrake;\ + PORTB &= ~0x01;\ + DDRB &= ~0x01;\ + TCCR1A |= 0x30;\ + OCR1B = D + +#define OUTPUTAExit OUTPUTAFloat + + + + + +// Schematics Function PORT +// ---------- -------- ---- +// MBIN0 PD6 (PB0) +// MBPWM OC1A PB1 (PB1) +// MBIN1 PD7 (PB3) + +#define OUTPUTBFloat PORTD &= ~0xE0;\ + DDRD |= 0xE0;\ + TCCR1A &= ~0xC0 + +#define OUTPUTBBrake PORTD |= 0xE0;\ + DDRD |= 0xE0;\ + TCCR1A &= ~0xC0 + +#define OUTPUTBInit OUTPUTBBrake;\ + TCCR1A = 0x01;\ + TCCR1B = 0x09;\ + TCNT1 = 0;\ + OCR1A = 0;\ + TIMSK1 = 0x00 + +#define OUTPUTBFwdFloat(D) OUTPUTBFloat;\ + DDRD &= ~0x40;\ + TCCR1A |= 0x80;\ + OCR1A = D + +#define OUTPUTBFwdBrake(D) OUTPUTBBrake;\ + PORTD &= ~0x80;\ + DDRD &= ~0x80;\ + TCCR1A |= 0xC0;\ + OCR1A = D + +#define OUTPUTBBwdFloat(D) OUTPUTBFloat;\ + DDRD &= ~0x80;\ + TCCR1A |= 0x80;\ + OCR1A = D + +#define OUTPUTBBwdBrake(D) OUTPUTBBrake;\ + PORTD &= ~0x40;\ + DDRD &= ~0x40;\ + TCCR1A |= 0xC0;\ + OCR1A = D + +#define OUTPUTBExit OUTPUTBFloat + + + +// Schematics Function PORT +// ---------- -------- ---- +// MCIN0 PB7 (PB7) +// MCPWM OC0B PD5 (PB2) +// MCIN1 PB6 (PB6) + +#define OUTPUTCFloat PORTB &= ~0xC4;\ + DDRB |= 0xC4;\ + TCCR0A &= ~0x30 + +#define OUTPUTCBrake PORTB |= 0xC4;\ + DDRB |= 0xC4;\ + TCCR0A &= ~0x30 + +#define OUTPUTCInit OUTPUTCBrake;\ + TCCR0A = 0x03;\ + TCCR0B = 0x01;\ + TCNT0 = 0;\ + OCR0B = 0;\ + TIMSK0 = 0x00 + +#define OUTPUTCFwdFloat(D) OUTPUTCFloat;\ + DDRB &= ~0x80;\ + TCCR0A |= 0x20;\ + OCR0B = D + +#define OUTPUTCFwdBrake(D) OUTPUTCBrake;\ + PORTB &= ~0x40;\ + DDRB &= ~0x40;\ + TCCR0A |= 0x30;\ + OCR0B = D + +#define OUTPUTCBwdFloat(D) OUTPUTCFloat;\ + DDRB &= ~0x40;\ + TCCR0A |= 0x20;\ + OCR0B = D + +#define OUTPUTCBwdBrake(D) OUTPUTCBrake;\ + PORTB &= ~0x80;\ + DDRB &= ~0x80;\ + TCCR0A |= 0x30;\ + OCR0B = D + +#define OUTPUTCExit OUTPUTCFloat + + + +UBYTE TopValue = 255; +UBYTE BrakeMask; + +void WriteFreq(UBYTE Freq) +{ + if (Freq >= 4) + { + TopValue = (UBYTE)(((ULONG)OSC / 8000L) / (ULONG)Freq); + TCCR0B &= ~0x0F; + TCCR0B |= 0x0A; + + TCCR1A &= ~0x03; + TCCR1A |= 0x02; + TCCR1B &= ~0x1F; + TCCR1B |= 0x1A; + } + else + { + TopValue = (UBYTE)(((ULONG)OSC / 64000L) / (ULONG)Freq); + TCCR0B &= ~0x0F; + TCCR0B |= 0x0B; + + TCCR1A &= ~0x03; + TCCR1A |= 0x02; + TCCR1B &= ~0x1F; + TCCR1B |= 0x1B; + } + OCR0B = 0; + OCR0A = TopValue; + OCR1A = 0; + OCR1B = 0; + ICR1L = TopValue; + ICR1H = 0; +} + + +void OutputBrake(UBYTE No) +{ + switch (No) + { + case 0 : + { + OUTPUTABrake; + } + break; + + case 1 : + { + OUTPUTBBrake; + } + break; + + case 2 : + { + OUTPUTCBrake; + } + break; + + } +} + +void OutputFloat(UBYTE No) +{ + switch (No) + { + case 0 : + { + OUTPUTAFloat; + } + break; + + case 1 : + { + OUTPUTBFloat; + } + break; + + case 2 : + { + OUTPUTCFloat; + } + break; + + } +} + +void OutputFwdBrake(UBYTE No,UBYTE Pwm) +{ + switch (No) + { + case 0 : + { + OUTPUTAFwdBrake(Pwm); + } + break; + + case 1 : + { + OUTPUTBFwdBrake(Pwm); + } + break; + + case 2 : + { + OUTPUTCFwdBrake(Pwm); + } + break; + + } +} + +void OutputBwdBrake(UBYTE No,UBYTE Pwm) +{ + switch (No) + { + case 0 : + { + OUTPUTABwdBrake(Pwm); + } + break; + + case 1 : + { + OUTPUTBBwdBrake(Pwm); + } + break; + + case 2 : + { + OUTPUTCBwdBrake(Pwm); + } + break; + + } +} + +void OutputFwdFloat(UBYTE No,UBYTE Pwm) +{ + switch (No) + { + case 0 : + { + OUTPUTAFwdFloat(Pwm); + } + break; + + case 1 : + { + OUTPUTBFwdFloat(Pwm); + } + break; + + case 2 : + { + OUTPUTCFwdFloat(Pwm); + } + break; + + } +} + +void OutputBwdFloat(UBYTE No,UBYTE Pwm) +{ + switch (No) + { + case 0 : + { + OUTPUTABwdFloat(Pwm); + } + break; + + case 1 : + { + OUTPUTBBwdFloat(Pwm); + } + break; + + case 2 : + { + OUTPUTCBwdFloat(Pwm); + } + break; + + } +} + +void OutputWrite(UBYTE No,SBYTE Duty) +{ + UBYTE Pwm; + + if (No < NOS_OF_AVR_OUTPUTS) + { + if (Duty < 0) + { + Pwm = (UBYTE)(0 - Duty); + } + else + { + Pwm = (UBYTE)Duty; + } + Pwm = (UBYTE)(((UWORD)Pwm * (UWORD)TopValue) / 100); + + + if ((BrakeMask & (0x01 << No))) + { + if (Duty) + { + if (Duty > 0) + { + OutputFwdBrake(No,Pwm); + } + else + { + OutputBwdBrake(No,Pwm); + } + } + else + { + OutputBrake(No); + } + } + else + { + if (Duty) + { + if (Duty > 0) + { + OutputFwdFloat(No,Pwm); + } + else + { + OutputBwdFloat(No,Pwm); + } + } + else + { + OutputFloat(No); + } + } + } +} + + + +#define OUTPUTInit OUTPUTAInit;\ + OUTPUTBInit;\ + OUTPUTCInit;\ + BrakeMask = 0xFF + +#define OUTPUTWriteBrakeMask(M) BrakeMask = M + +#define OUTPUTWrite(No,Duty) OutputWrite(No,Duty) + +#define OUTPUTFreq(Freq) WriteFreq(Freq) + +#define OUTPUTUpdate + +#define OUTPUTExit OUTPUTAExit;\ + OUTPUTBExit;\ + OUTPUTCExit + +#endif diff --git a/ATmega48/Source/d_pccomm.c b/ATmega48/Source/d_pccomm.c new file mode 100644 index 0000000..b2e3c6c --- /dev/null +++ b/ATmega48/Source/d_pccomm.c @@ -0,0 +1,33 @@ +// +// Programmer +// +// Date init 14.12.2004 +// +// Reviser $Author:: Dktochpe $ +// +// Revision date $Date:: 8-04-05 9:51 $ +// +// Filename $Workfile:: d_pccomm.c $ +// +// Version $Revision:: 3 $ +// +// Archive $Archive:: /LMS2006/Sys01/Ioctrl/Firmware/Source/d_pccomm $ +// +// Platform C +// + +#include "stdconst.h" +#include "m_sched.h" +#include "d_pccomm.h" +#include "d_pccomm.r" + + +void dPcCommInit(void) +{ + //INITPcComm; +} + +void dPcCommExit(void) +{ + //EXITPcComm; +} diff --git a/ATmega48/Source/d_pccomm.h b/ATmega48/Source/d_pccomm.h new file mode 100644 index 0000000..29ca916 --- /dev/null +++ b/ATmega48/Source/d_pccomm.h @@ -0,0 +1,26 @@ +// +// Programmer +// +// Date init 14.12.2004 +// +// Reviser $Author:: Dkandlun $ +// +// Revision date $Date:: 28-12-04 14:19 $ +// +// Filename $Workfile:: d_pccomm.h $ +// +// Version $Revision:: 1 $ +// +// Archive $Archive:: /LMS2006/Sys01/Peripheral/Firmware/Source/d_pc $ +// +// Platform C +// + + +#ifndef D_PCCOMM +#define D_PCCOMM + +void dPcCommInit(void); +void dPcCommExit(void); + +#endif diff --git a/ATmega48/Source/d_pccomm.r b/ATmega48/Source/d_pccomm.r new file mode 100644 index 0000000..0660ac7 --- /dev/null +++ b/ATmega48/Source/d_pccomm.r @@ -0,0 +1,93 @@ +// +// Programmer +// +// Date init 14.12.2004 +// +// Reviser $Author:: Dktochpe $ +// +// Revision date $Date:: 22-02-05 11:10 $ +// +// Filename $Workfile:: d_pccomm.r $ +// +// Version $Revision:: 6 $ +// +// Archive $Archive:: /LMS2006/Sys01/Ioctrl/Firmware/Source/d_pccomm $ +// +// Platform C +// + +#ifdef ATMEGAX8 + +#define BAUD_RATE 4800L + +#define RX_BUFFERSIZE (BYTES_TO_TX) +#define TX_BUFFERSIZE (BYTES_TO_RX) + +UBYTE RxBuffer[RX_BUFFERSIZE]; +UBYTE RxPointer; + +UBYTE TxBuffer[TX_BUFFERSIZE]; +UBYTE TxPointer; + +#pragma language=extended +#pragma vector = USART_RX_vect +__interrupt void RxInterrupt(void) +{ + UBYTE *pBuffer; + + RxBuffer[RxPointer] = UDR0; + RxPointer++; + if (RxPointer >= RX_BUFFERSIZE) + { + pBuffer = (UBYTE*)&IoToAvr; + for (RxPointer = 0;RxPointer < RX_BUFFERSIZE;RxPointer++) + { + *pBuffer = RxBuffer[RxPointer]; + pBuffer++; + } + RxPointer = 0; + pBuffer = (UBYTE*)&IoFromAvr; + for (TxPointer = 0;TxPointer < TX_BUFFERSIZE;TxPointer++) + { + TxBuffer[TxPointer] = *pBuffer; + pBuffer++; + } + TxPointer = 0; + UDR0 = TxBuffer[TxPointer]; + TxPointer++; + UCSR0B |= 0x40; + } +} + +#pragma language=extended +#pragma vector = USART_TX_vect +__interrupt void TxInterrupt(void) +{ + UDR0 = TxBuffer[TxPointer]; + TxPointer++; + if (TxPointer >= TX_BUFFERSIZE) + { + UCSR0B &= ~0x40; + TxPointer = 0; + RxPointer = 0; + } +} + +#define INITPcComm {\ + DDRD |= 0x02;\ + DDRD &= ~0x01;\ + UBRR0 = (UWORD)((OSC/(16 * BAUD_RATE)) - 1);\ + UCSR0A = 0x40;\ + UCSR0B = 0x98;\ + UCSR0C = 0x36;\ + RxPointer = 0;\ + } + +#define EXITPcComm {\ + UCSR0B = 0x00;\ + PORTD &= ~0x01;\ + DDRD |= 0x01;\ + } + + +#endif diff --git a/ATmega48/Source/d_power.c b/ATmega48/Source/d_power.c new file mode 100644 index 0000000..f28179a --- /dev/null +++ b/ATmega48/Source/d_power.c @@ -0,0 +1,122 @@ +// +// Programmer +// +// Date init 14.12.2004 +// +// Reviser $Author:: Dktochpe $ +// +// Revision date $Date:: 2-09-05 14:37 $ +// +// Filename $Workfile:: d_power.c $ +// +// Version $Revision:: 7 $ +// +// Archive $Archive:: /LMS2006/Sys01/Ioctrl/Firmware/Source/d_power. $ +// +// Platform C +// + +#include "stdconst.h" +#include "m_sched.h" +#include "d_power.h" +#include "d_power.r" + + +void dPowerInit(void) +{ + POWERInit; +} + + +void dPowerRechargeable(UBYTE Mounted) +{ + if (Mounted) + { + IoFromAvr.Battery |= 0x8000; + } + else + { + IoFromAvr.Battery &= ~0x8000; + } +} + + +UBYTE dPowerReadOn(void) +{ + UBYTE Result = TRUE; + + if (IoToAvr.Power == 0x5A) + { + Result = FALSE; + } + + return (Result); +} + + +UBYTE dPowerReadBoot(void) +{ + UBYTE Result = FALSE; + + if ((IoToAvr.Power == 0xA5) && (IoToAvr.PwmFreq == 0x5A)) + { + IoToAvr.Power = 0x00; + IoToAvr.PwmFreq = 0x00; + Result = TRUE; + } + + return (Result); +} + + +void dPowerSelect(void) +{ + POWERSelect; +} + + +UWORD dPowerConvert(void) +{ + UWORD Result; + + POWERConvert(Result); + + return (Result); +} + + +void dPowerDeselect(void) +{ + POWERDeselect; +} + + +void dPowerWriteOn(UBYTE On) +{ + if (On == TRUE) + { + POWEROn; + } + else + { + POWEROff; + } +} + + +void dPowerHigh(void) +{ + POWERHigh; +} + + +void dPowerFloat(void) +{ + POWERFloat; +} + + +void dPowerExit(void) +{ + POWERExit; +} diff --git a/ATmega48/Source/d_power.h b/ATmega48/Source/d_power.h new file mode 100644 index 0000000..f1b5c2f --- /dev/null +++ b/ATmega48/Source/d_power.h @@ -0,0 +1,35 @@ +// +// Programmer +// +// Date init 14.12.2004 +// +// Reviser $Author:: Dktochpe $ +// +// Revision date $Date:: 2-09-05 14:37 $ +// +// Filename $Workfile:: d_power.h $ +// +// Version $Revision:: 4 $ +// +// Archive $Archive:: /LMS2006/Sys01/Ioctrl/Firmware/Source/d_power. $ +// +// Platform C +// + + +#ifndef D_POWER +#define D_POWER + +void dPowerInit(void); +void dPowerRechargeable(UBYTE Mounted); +UBYTE dPowerReadOn(void); +UBYTE dPowerReadBoot(void); +void dPowerWriteOn(UBYTE On); +void dPowerSelect(void); +UWORD dPowerConvert(void); +void dPowerDeselect(void); +void dPowerHigh(void); +void dPowerFloat(void); +void dPowerExit(void); + +#endif diff --git a/ATmega48/Source/d_power.r b/ATmega48/Source/d_power.r new file mode 100644 index 0000000..de229a3 --- /dev/null +++ b/ATmega48/Source/d_power.r @@ -0,0 +1,79 @@ +// +// Programmer +// +// Date init 14.12.2004 +// +// Reviser $Author:: Dktochpe $ +// +// Revision date $Date:: 2-09-05 14:37 $ +// +// Filename $Workfile:: d_power.r $ +// +// Version $Revision:: 8 $ +// +// Archive $Archive:: /LMS2006/Sys01/Ioctrl/Firmware/Source/d_power. $ +// +// Platform C +// + +#ifdef ATMEGAX8 + +#define POWERInit {\ + PORTC &= ~0x04;\ + DDRC &= ~0x04;\ + DIDR0 |= 0x04;\ + } + +#define POWEROff {\ + PORTD &= ~0x10;\ + DDRD |= 0x10;\ + } + +#define POWEROn {\ + PORTD |= 0x10;\ + DDRD |= 0x10;\ + } + +#define POWERSelect {\ + PORTD |= 0x04;\ + DDRD |= 0x04;\ + } + +#define POWERConvert(V) {\ + ADMUX = 0x42;\ + ADCSRA &= ~0x07;\ + ADCSRA |= 0x05;\ + ADCSRA |= 0x40;\ + while ((ADCSRA & 0x40));\ + ADCSRA |= 0x40;\ + while ((ADCSRA & 0x40));\ + V = ADC;\ + V &= 0x7FFF;\ + IoFromAvr.Battery &= 0x8000;\ + IoFromAvr.Battery |= V;\ + } + +#define POWERDeselect {\ + PORTD &= ~0x04;\ + DDRD |= 0x04;\ + } + +#define POWERHigh {\ + PORTC |= 0x04;\ + DDRC |= 0x04;\ + } + +#define POWERFloat {\ + PORTC &= ~0x04;\ + DDRC &= ~0x04;\ + } + + + +#define POWERExit {\ + POWEROff;\ + POWERDeselect;\ + POWERConvert(ADC);\ + } + +#endif diff --git a/ATmega48/Source/d_timer.c b/ATmega48/Source/d_timer.c new file mode 100644 index 0000000..94758c9 --- /dev/null +++ b/ATmega48/Source/d_timer.c @@ -0,0 +1,48 @@ +// +// Programmer +// +// Date init 14.12.2004 +// +// Reviser $Author:: Dktochpe $ +// +// Revision date $Date:: 16-06-05 14:32 $ +// +// Filename $Workfile:: d_timer.c $ +// +// Version $Revision:: 2 $ +// +// Archive $Archive:: /LMS2006/Sys01/Ioctrl/Firmware/Source/d_timer. $ +// +// Platform C +// + +#include "stdconst.h" +#include "m_sched.h" +#include "d_timer.h" +#include "d_timer.r" + +UBYTE Timer; + + +void dTimerInit(void) +{ + TIMERInit; +} + + +void dTimerClear(void) +{ + Timer = TIMERRead; +} + + +UBYTE dTimerRead(void) +{ + return ((UBYTE)(TIMERRead - Timer)); +} + + +void dTimerExit(void) +{ + TIMERExit; +} diff --git a/ATmega48/Source/d_timer.h b/ATmega48/Source/d_timer.h new file mode 100644 index 0000000..862f4f4 --- /dev/null +++ b/ATmega48/Source/d_timer.h @@ -0,0 +1,30 @@ +// +// Programmer +// +// Date init 14.12.2004 +// +// Reviser $Author:: Dktochpe $ +// +// Revision date $Date:: 16-06-05 14:32 $ +// +// Filename $Workfile:: d_timer.h $ +// +// Version $Revision:: 2 $ +// +// Archive $Archive:: /LMS2006/Sys01/Ioctrl/Firmware/Source/d_timer. $ +// +// Platform C +// + + +#ifndef D_TIMER +#define D_TIMER + +void dTimerInit(void); +void dTimerClear(void); +UBYTE dTimerRead(void); +void dTimerExit(void); + +#define TIMER_RESOLUTION (8000000L / 256L) + +#endif diff --git a/ATmega48/Source/d_timer.r b/ATmega48/Source/d_timer.r new file mode 100644 index 0000000..9798be9 --- /dev/null +++ b/ATmega48/Source/d_timer.r @@ -0,0 +1,34 @@ +// +// Programmer +// +// Date init 14.12.2004 +// +// Reviser $Author:: Dktochpe $ +// +// Revision date $Date:: 2-09-05 14:37 $ +// +// Filename $Workfile:: d_timer.r $ +// +// Version $Revision:: 4 $ +// +// Archive $Archive:: /LMS2006/Sys01/Ioctrl/Firmware/Source/d_timer. $ +// +// Platform C +// + +#ifdef ATMEGAX8 + +#define TIMERInit {\ + TCCR2A = 0x00;\ + TCCR2B = 0x06;\ + TCNT2 = 0x00;\ + } + +#define TIMERRead TCNT2 + + +#define TIMERExit {\ + } + + +#endif diff --git a/ATmega48/Source/m_sched.c b/ATmega48/Source/m_sched.c new file mode 100644 index 0000000..d208469 --- /dev/null +++ b/ATmega48/Source/m_sched.c @@ -0,0 +1,54 @@ +// +// Programmer +// +// Date init 14.12.2004 +// +// Reviser $Author:: Dktochpe $ +// +// Revision date $Date:: 2-09-05 14:37 $ +// +// Filename $Workfile:: m_sched.c $ +// +// Version $Revision:: 2 $ +// +// Archive $Archive:: /LMS2006/Sys01/Ioctrl/Firmware/Source/m_sched. $ +// +// Platform C +// + + +#define INCLUDE_OS + + +#include "stdconst.h" +#include "m_sched.h" +#include "c_armcomm.h" + + +UBYTE Run; + + +void mSchedInit(void) +{ + Run = FALSE; + + cArmCommInit(); + Run = TRUE; +} + + +UBYTE mSchedCtrl(void) +{ + Run = cArmCommCtrl(); + + return (Run); +} + + +void mSchedExit(void) +{ + Run = FALSE; + + cArmCommExit(); +} + diff --git a/ATmega48/Source/m_sched.h b/ATmega48/Source/m_sched.h new file mode 100644 index 0000000..1dd7a09 --- /dev/null +++ b/ATmega48/Source/m_sched.h @@ -0,0 +1,87 @@ +// +// Programmer +// +// Date init 14.12.2004 +// +// Reviser $Author:: Dktochpe $ +// +// Revision date $Date:: 28-10-05 13:46 $ +// +// Filename $Workfile:: m_sched.h $ +// +// Version $Revision:: 15 $ +// +// Archive $Archive:: /LMS2006/Sys01/Ioctrl/Firmware/Source/m_sched. $ +// +// Platform C +// + + +#define COPYRIGHTSTRING "Let's samba nxt arm in arm, (c)LEGO System A/S" + +#define COPYRIGHTSTRINGLENGTH 46 // Number of bytes checked in COPYRIGHTSTRING + +#define OSC 8000000L // Main oscillator frequency + +#include "..\mega48\include\atmega48.h" + +#define BYTES_TO_TX 8 // Number of bytes received from ARM = sizeof(IOTOAVR) +#define BYTES_TO_RX 12 // Number of bytes transmitted to ARM = sizeof(IOFROMAVR) +#define NOS_OF_AVR_OUTPUTS 4 // Number of motor outputs +#define NOS_OF_AVR_INPUTS 4 // Number of a/d inputs + + +typedef struct // From AVR to ARM +{ + UWORD AdValue[NOS_OF_AVR_INPUTS]; // Raw a/d converter values [0..1023] + UWORD Buttons; // Raw a/d converter value [0..1023] (Enter -> +0x07FF) + UWORD Battery; // Raw a/d converter value [0..1023] (rechargeable -> +0x8000) +}IOFROMAVR; + + +typedef struct // From ARM to AVR +{ + UBYTE Power; // Command descriped below + UBYTE PwmFreq; // Common pwm freq [Khz] [1..32] + SBYTE PwmValue[NOS_OF_AVR_OUTPUTS]; // Pwm value [%] [-100..100] + UBYTE OutputMode; // Bitwise Bit 0 = Motor A [0 = float, 1 = brake] + UBYTE InputPower; // Bitwise Bit 0 and 4 = input 1 [00 = inactive,01 = pulsed, 11 = constant] +}IOTOAVR; + +/* + Powerdown request: Power = 0x5A + Samba boot request: Power = 0xA5 and PwmFreq = 0x5A + Copyright string: Power = 0xCC +*/ + + +#ifdef INCLUDE_OS + +#include "..\mega48\include\atmega48.c" + +IOFROMAVR IoFromAvr = +{ + { 0,0,0,0 }, + 0, + 0 +}; + +IOTOAVR IoToAvr = +{ + 0, + 4, + { 0,0,0,0 }, + 0x0F,0x0F +}; + +#endif + +extern IOTOAVR IoToAvr; +extern IOFROMAVR IoFromAvr; +extern UBYTE Run; + + + + + + diff --git a/ATmega48/Source/stdconst.h b/ATmega48/Source/stdconst.h new file mode 100644 index 0000000..392633e --- /dev/null +++ b/ATmega48/Source/stdconst.h @@ -0,0 +1,44 @@ +// +// Programmer +// +// Date init 14.12.2004 +// +// Reviser $Author:: Dkandlun $ +// +// Revision date $Date:: 28-12-04 14:19 $ +// +// Filename $Workfile:: stdconst.h $ +// +// Version $Revision:: 1 $ +// +// Archive $Archive:: /LMS2006/Sys01/Peripheral/Firmware/Source/stdc $ +// +// Platform C +// + + +#ifndef STDCONST +#define STDCONST + + +#define TRUE 1 +#define FALSE 0 + +typedef unsigned char UCHAR; +typedef unsigned short USHORT; +typedef unsigned char UBYTE; +typedef signed char SBYTE; +typedef unsigned int UWORD; +typedef signed int SWORD; +typedef unsigned long ULONG; +typedef signed long SLONG; + +typedef ULONG* PULONG; +typedef USHORT* PUSHORT; +typedef UCHAR* PUCHAR; +typedef char* PSZ; + +#define BASETYPES + + +#endif diff --git a/LEGO MINDSTORMS NXT Firmware Open Source.doc b/LEGO MINDSTORMS NXT Firmware Open Source.doc new file mode 100644 index 0000000..7cf37dd Binary files /dev/null and b/LEGO MINDSTORMS NXT Firmware Open Source.doc differ diff --git a/LEGO Open Source License.doc b/LEGO Open Source License.doc new file mode 100644 index 0000000..94b65e6 Binary files /dev/null and b/LEGO Open Source License.doc differ -- cgit v1.2.3