From 35a62b404da36bf239aa8954c286efa6c2bb925d Mon Sep 17 00:00:00 2001 From: galmes Date: Mon, 23 Feb 2004 13:56:11 +0000 Subject: Ajout du code fait pendant les vacances + modifications sur le modèle --- 2004/n/fpga/src/gpio/bch_reg_io.vhd | 67 +++++++++++++++++++++++++++++++++++ 2004/n/fpga/src/gpio/bch_reg_rw.vhd | 64 +++++++++++++++++++++++++++++++++ 2004/n/fpga/src/gpio/reg_io.vhd | 57 +++++++++++++++++++++++++++++ 2004/n/fpga/src/gpio/reg_rw.vhd | 52 +++++++++++++++++++++++++++ 2004/n/fpga/src/modele/isa_const.vhd | 27 ++++++++++++++ 2004/n/fpga/src/modele/modele.vhd | 6 ++-- 2004/n/fpga/src/modele/nono_const.vhd | 9 +++-- 7 files changed, 276 insertions(+), 6 deletions(-) create mode 100644 2004/n/fpga/src/gpio/bch_reg_io.vhd create mode 100644 2004/n/fpga/src/gpio/bch_reg_rw.vhd create mode 100644 2004/n/fpga/src/gpio/reg_io.vhd create mode 100644 2004/n/fpga/src/gpio/reg_rw.vhd create mode 100644 2004/n/fpga/src/modele/isa_const.vhd diff --git a/2004/n/fpga/src/gpio/bch_reg_io.vhd b/2004/n/fpga/src/gpio/bch_reg_io.vhd new file mode 100644 index 0000000..f9fd5c9 --- /dev/null +++ b/2004/n/fpga/src/gpio/bch_reg_io.vhd @@ -0,0 +1,67 @@ +-- bch_reg_io.vhd +-- Eurobot 2004 : APB Team +-- Auteur : Pierre-André Galmes +-- Test de reg_rw. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +use work.isa_const.all; +use work.nono_const.all; + + +entity bch_reg_io is +end bch_reg_io; + +architecture sim1 of bch_reg_io is + + component reg_io + port ( + rst : in std_logic; + rw : in std_logic; + enable : in std_logic; + data_in : inout T_DATA; + data_out : inout T_DATA + ); + end component; + + -- définiton des signaux + signal rst : std_logic; + signal rw : std_logic; -- read / write + signal enable : std_logic; + signal data_in : T_DATA; + signal data_out : T_DATA; + +begin + U1 : reg_io port map ( + rst => rst, + rw => rw, + enable => enable, + data_in => data_in, + data_out => data_out + ); + + rst <= '1', '0' after CK_PERIOD; + enable <= '0', + '1' after 2*CK_PERIOD, + '0' after 3*CK_PERIOD, + '1' after 5*CK_PERIOD, + '0' after 6*CK_PERIOD; + rw <= '1', '0' after 3*CK_PERIOD; + data_in <= x"01", + x"02" after 3*CK_PERIOD, + "ZZZZZZZZ" after 5*CK_PERIOD; + --x"03" after 5*CK_PERIOD; + data_out <= "ZZZZZZZZ", + x"07" after 5*CK_PERIOD, + "ZZZZZZZZ" after 6*CK_PERIOD; +end sim1; + +configuration cf1_bch_reg_io of bch_reg_io is + for sim1 + for all : reg_io use entity work.reg_io(BEHAV); end for; + end for; +end cf1_bch_reg_io; + diff --git a/2004/n/fpga/src/gpio/bch_reg_rw.vhd b/2004/n/fpga/src/gpio/bch_reg_rw.vhd new file mode 100644 index 0000000..7d4a41a --- /dev/null +++ b/2004/n/fpga/src/gpio/bch_reg_rw.vhd @@ -0,0 +1,64 @@ +-- bch_reg_rw.vhd +-- Eurobot 2004 : APB Team +-- Auteur : Pierre-André Galmes +-- Test de reg_rw. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +use work.isa_const.all; +use work.nono_const.all; + + +entity bch_reg_rw is +end bch_reg_rw; + +architecture sim1 of bch_reg_rw is + + component reg_rw + port ( + rst : in std_logic; + rw : in std_logic; + enable : in std_logic; + data_in : inout T_DATA; + data_out : out T_DATA + ); + end component; + + -- définiton des signaux + signal rst : std_logic; + signal rw : std_logic; -- read / write + signal enable : std_logic; + signal data_in : T_DATA; + signal data_out : T_DATA; + +begin + U1 : reg_rw port map ( + rst => rst, + rw => rw, + enable => enable, + data_in => data_in, + data_out => data_out + ); + + rst <= '1', '0' after CK_PERIOD; + enable <= '0', + '1' after 2*CK_PERIOD, + '0' after 3*CK_PERIOD, + '1' after 5*CK_PERIOD, + '0' after 6*CK_PERIOD; + rw <= '1', '0' after 3*CK_PERIOD; + data_in <= x"01", + x"02" after 3*CK_PERIOD, + "ZZZZZZZZ" after 5*CK_PERIOD; + --x"03" after 5*CK_PERIOD; +end sim1; + +configuration cf1_bch_reg_rw of bch_reg_rw is + for sim1 + for all : reg_rw use entity work.reg_rw(BEHAV); end for; + end for; +end cf1_bch_reg_rw; + diff --git a/2004/n/fpga/src/gpio/reg_io.vhd b/2004/n/fpga/src/gpio/reg_io.vhd new file mode 100644 index 0000000..951c56d --- /dev/null +++ b/2004/n/fpga/src/gpio/reg_io.vhd @@ -0,0 +1,57 @@ +-- reg_io.vhd +-- Eurobot 2004 : APB Team +-- Auteur : Pierre-André Galmes +-- Registre dont on peut lire les valeurs sur data_out. +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + + +use work.isa_const.all; +use work.nono_const.all; + + +entity reg_io is + port ( + rst : in std_logic; + + -- XXX : savoir si read = 0 ou 1 !! + rw : in std_logic; -- read (0) / write (1) + enable : in std_logic; + data_in : inout T_DATA; + data_out : inout T_DATA + --data_direction : in T_DATA + ); +end entity; + +architecture BEHAV of reg_io is + -- signal interne + signal REG : T_DATA; +begin + -- process + process (rst, rw, enable, data_in) + begin + if (rst = '1') then + REG <= x"00"; + -- data_in <= "ZZZZZZZZ"; + else + if (enable = '1') then + if (rw = ISA_WRITE) then + REG <= data_in; + -- data_out <= REG; + elsif (rw = ISA_READ) then + data_in <= data_out; + -- data_in <= REG; + end if; + else + data_in <= "ZZZZZZZZ"; + -- data_out <= REG; + end if; + end if; + end process; + + data_out <= "ZZZZZZZZ" when (rw = ISA_READ and enable = '1') else REG; +end BEHAV; diff --git a/2004/n/fpga/src/gpio/reg_rw.vhd b/2004/n/fpga/src/gpio/reg_rw.vhd new file mode 100644 index 0000000..7350e76 --- /dev/null +++ b/2004/n/fpga/src/gpio/reg_rw.vhd @@ -0,0 +1,52 @@ +-- reg_rw.vhd +-- Eurobot 2004 : APB Team +-- Auteur : Pierre-André Galmes +-- Registre dont la valeur est accessible en lecture. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + + +use work.isa_const.all; +use work.nono_const.all; + + +entity reg_rw is + port ( + rst : in std_logic; + + -- XXX : savoir si read = 0 ou 1 !! + rw : in std_logic; -- read (0) / write (1) + enable : in std_logic; + data_in : inout T_DATA; + data_out : out T_DATA + ); +end entity; + +architecture BEHAV of reg_rw is + -- signal interne + signal REG : T_DATA; +begin + -- process d'écriture. + process (rst, rw, enable, data_in) + begin + if (rst = '1') then + REG <= x"00"; + else + if (enable = '1') then + if (rw = ISA_WRITE) then + REG <= data_in; + elsif (rw = ISA_READ) then + data_in <= REG; + end if; + else + data_in <= "ZZZZZZZZ"; + end if; + end if; + end process; + + -- + data_out <= REG; +end BEHAV; diff --git a/2004/n/fpga/src/modele/isa_const.vhd b/2004/n/fpga/src/modele/isa_const.vhd new file mode 100644 index 0000000..12ab384 --- /dev/null +++ b/2004/n/fpga/src/modele/isa_const.vhd @@ -0,0 +1,27 @@ +-- isa_const.vhd +-- Eurobot 2004 : APB Team +-- Auteur : Pierre-André Galmes +-- Fichier de déclaration de constantes. + +-- RQ : pour une indentation bien sous vim : +-- 1 - ":set shiftwidth=4" +-- 2 - se placer sous "package nono_const is" +-- 3 - tapez : = puis shift+G + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + + +-- Constantes relatives au bus ISA +package isa_const is + + -- Temps d'une période d'horloge sur le bus ISA + constant ISA_CK_PERIOD : time := 50 ns; + + -- Ligne RW : lecture et écriture + constant ISA_READ : std_logic := '0'; + constant ISA_WRITE : std_logic := '1'; +end isa_const; + diff --git a/2004/n/fpga/src/modele/modele.vhd b/2004/n/fpga/src/modele/modele.vhd index 366759d..c877df9 100644 --- a/2004/n/fpga/src/modele/modele.vhd +++ b/2004/n/fpga/src/modele/modele.vhd @@ -13,9 +13,9 @@ use work.nono_const.all; entity modele is generic ( -- adresses des différents registres du module. - A_REG1 : T_ADDRESS := A_REG_IO_DIRECTION; - A_REG2 : T_ADDRESS := A_REG_IO_DATA; - A_REG3 : T_ADDRESS := A_REG_IO_INTERRUPT_MASK + A_REG1 : T_ADDRESS; + A_REG2 : T_ADDRESS; + A_REG3 : T_ADDRESS -- si autre choses à déclarer... ); port ( diff --git a/2004/n/fpga/src/modele/nono_const.vhd b/2004/n/fpga/src/modele/nono_const.vhd index 5c2e04a..fc260e1 100644 --- a/2004/n/fpga/src/modele/nono_const.vhd +++ b/2004/n/fpga/src/modele/nono_const.vhd @@ -13,9 +13,11 @@ use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; + +-- Constantes relatives package nono_const is - -- Temps d'une période d'horloge + -- Temps d'une période d'horloge sur la carte constant CK_PERIOD : time := 10 ns; -- Taille d'une addresse sur la carte @@ -26,8 +28,9 @@ package nono_const is -- Taille des données sur la carte constant NB_BIT_DATA : integer := 8; - -- Définition d'un nouveau type : ADDRESS + -- Définition de nouveaux types : T_ADDRESS et T_DATA subtype T_ADDRESS is unsigned ((NB_BIT_ADDRESS - 1) downto 0); + subtype T_DATA is unsigned ((NB_BIT_DATA - 1) downto 0); -- Les différentes banques d'adresses (4 x 256) -- Rq pour Pierre : ça va influer sur le bloc de gestion du bus @@ -40,7 +43,7 @@ package nono_const is -- gestion des interruptions constant A_INTERRUPT_MANAGER : T_ADDRESS := START_ADDR_B0 + x"00"; - -- Bloc d'IO + -- Bloc d'IO1 constant A_REG_IO_DIRECTION : T_ADDRESS := START_ADDR_B0 + x"01"; constant A_REG_IO_DATA : T_ADDRESS := START_ADDR_B0 + x"02"; constant A_REG_IO_INTERRUPT_MASK : T_ADDRESS := START_ADDR_B0 + x"03"; -- cgit v1.2.3