From 2a8c2d3c2521de1599f6dc0d5a6b116d9c28bea3 Mon Sep 17 00:00:00 2001 From: prot Date: Sat, 3 Apr 2004 18:18:36 +0000 Subject: Modif aprs cration du top fpga.vhd --- 2004/n/fpga/src/decodisa/bch_decodisa.vhd | 59 + 2004/n/fpga/src/decodisa/decodadr.xco | 42 + 2004/n/fpga/src/decodisa/decodisa_timesim.vhd | 20384 +++++++++++++++++++ 2004/n/fpga/src/decodisa/decodisa_translate.vhd | 14082 +++++++++++++ 2004/n/fpga/src/fpga/decodadr.xco | 41 + 2004/n/fpga/src/fpga/decodisa.vhd | 61 + 2004/n/fpga/src/fpga/fpga-test.vhd | 142 + 2004/n/fpga/src/fpga/fpga.npl | 39 + 2004/n/fpga/src/fpga/fpga.vhd | 104 + 2004/n/fpga/src/fpga/fpga_translate.vhd | 13444 ++++++++++++ 2004/n/fpga/src/fpga/isa_const.vhd | 34 + 2004/n/fpga/src/fpga/nono_const.vhd | 72 + 2004/n/fpga/src/fpga/rxserie.vhd | 254 + 2004/n/fpga/src/fpga/sfifo.xco | 41 + 2004/n/fpga/src/modele/nono_const.vhd | 8 +- 2004/n/fpga/src/portserie/clockgene/clockgene.vhd | 16 +- 2004/n/fpga/src/portserie/fifo/bch_fifodriver.vhd | 12 +- 2004/n/fpga/src/portserie/fifo/bch_sfifo.vhd | 6 +- 2004/n/fpga/src/portserie/fifo/fifo.npl | 9 +- 2004/n/fpga/src/portserie/fifo/fifodriver.vhd | 2 +- 2004/n/fpga/src/portserie/fifo/sfifo.xco | 20 +- .../n/fpga/src/portserie/portserie/bch_txserie.vhd | 12 +- 2004/n/fpga/src/portserie/portserie/portserie.npl | 2 + 2004/n/fpga/src/portserie/portserie/sfifo.xco | 5 +- 2004/n/fpga/src/portserie/portserie/txserie.vhd | 21 +- 2004/n/fpga/src/portserie/rxserie/bch_rxserie.vhd | 24 +- 2004/n/fpga/src/portserie/rxserie/rxserie.npl | 14 +- 2004/n/fpga/src/portserie/rxserie/rxserie.vhd | 13 +- 2004/n/fpga/src/portserie/rxserie/sfifo.xco | 9 +- 2004/n/fpga/src/portserie/uart/txmit.vhd | 14 +- 30 files changed, 48909 insertions(+), 77 deletions(-) create mode 100644 2004/n/fpga/src/decodisa/bch_decodisa.vhd create mode 100644 2004/n/fpga/src/decodisa/decodadr.xco create mode 100644 2004/n/fpga/src/decodisa/decodisa_timesim.vhd create mode 100644 2004/n/fpga/src/decodisa/decodisa_translate.vhd create mode 100644 2004/n/fpga/src/fpga/decodadr.xco create mode 100644 2004/n/fpga/src/fpga/decodisa.vhd create mode 100644 2004/n/fpga/src/fpga/fpga-test.vhd create mode 100644 2004/n/fpga/src/fpga/fpga.npl create mode 100644 2004/n/fpga/src/fpga/fpga.vhd create mode 100644 2004/n/fpga/src/fpga/fpga_translate.vhd create mode 100644 2004/n/fpga/src/fpga/isa_const.vhd create mode 100644 2004/n/fpga/src/fpga/nono_const.vhd create mode 100644 2004/n/fpga/src/fpga/rxserie.vhd create mode 100644 2004/n/fpga/src/fpga/sfifo.xco diff --git a/2004/n/fpga/src/decodisa/bch_decodisa.vhd b/2004/n/fpga/src/decodisa/bch_decodisa.vhd new file mode 100644 index 0000000..5457481 --- /dev/null +++ b/2004/n/fpga/src/decodisa/bch_decodisa.vhd @@ -0,0 +1,59 @@ + +-- VHDL Test Bench Created from source file decodisa.vhd -- 02:25:56 03/17/2004 +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-- +LIBRARY ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +ENTITY decodisa_bch IS +END decodisa_bch; + +ARCHITECTURE behavior OF decodisa_bch IS + + COMPONENT decodisa + PORT( + adr_bus : IN std_logic_vector(23 downto 0); + AEN : IN std_logic; + IOR : IN std_logic; + IOW : IN std_logic; + cs : OUT std_logic_vector(255 downto 0); + rw : OUT std_logic; + clk : OUT std_logic + ); + END COMPONENT; + + SIGNAL adr_bus : std_logic_vector(23 downto 0):=(others => '0'); + SIGNAL AEN : std_logic:='0'; + SIGNAL IOR : std_logic:='0'; + SIGNAL IOW : std_logic:='0'; + SIGNAL cs : std_logic_vector(255 downto 0); + SIGNAL rw : std_logic; + SIGNAL clk : std_logic; + +BEGIN + + uut: decodisa PORT MAP( + adr_bus => adr_bus, + AEN => AEN, + IOR => IOR, + IOW => IOW, + cs => cs, + rw => rw, + clk => clk + ); + +adr_bus <= conv_std_logic_vector(unsigned(adr_bus) + 1 , 24) after 120 ns; +aen<= not aen after 1500 ns; +ior<= not ior after 70 ns; +iow<= not iow after 50 ns; + + +END; diff --git a/2004/n/fpga/src/decodisa/decodadr.xco b/2004/n/fpga/src/decodisa/decodadr.xco new file mode 100644 index 0000000..498e91e --- /dev/null +++ b/2004/n/fpga/src/decodisa/decodadr.xco @@ -0,0 +1,42 @@ +# Xilinx CORE Generator 6.1.03i +# Username = Administrateur +# COREGenPath = D:\xilinx\coregen +# ProjectPath = D:\vhdl\robot\carte_fpga\src\decodisa +# ExpandedProjectPath = D:\vhdl\robot\carte_fpga\src\decodisa +# OverwriteFiles = true +# Core name: decodadr +# Number of Primitives in design: 768 +# Number of CLBs used in design: 264 +# Number of Slices used in design: 512 +# Number of LUT sites used in design: 768 +# Number of LUTs used in design: 768 +# Number of REG used in design: 0 +# Number of SRL16s used in design: 0 +# Number of Distributed RAM primitives used in design: 0 +# Number of Block Memories used in design: 0 +# Number of Dedicated Multipliers used in design: 0 +# Number of HU_SETs used: 1 +# Huset "default" = (0, 0) to (17, 16) in CLBs +# +SET BusFormat = BusFormatAngleBracketNotRipped +SET XilinxFamily = Spartan2 +SET OutputOption = OutputProducts +SET FlowVendor = Foundation_iSE +SET FormalVerification = None +SET OutputProducts = ImpNetlist ASYSymbol VHDLSim VerilogSim +SELECT Binary_Decoder Spartan2 Xilinx,_Inc. 6.0 +CSET output_sense = active_high +CSET async_init_value = 0 +CSET set_clear_priority = clear_overrides_set +CSET ce_overrides = sync_controls_override_ce +CSET number_of_outputs = 256 +CSET output_options = non_registered +CSET sync_init_value = 0 +CSET clock_enable = false +CSET create_rpm = true +CSET decoder_enable = true +CSET asynchronous_settings = none +CSET synchronous_settings = none +CSET component_name = decodadr +GENERATE + diff --git a/2004/n/fpga/src/decodisa/decodisa_timesim.vhd b/2004/n/fpga/src/decodisa/decodisa_timesim.vhd new file mode 100644 index 0000000..2b13dcd --- /dev/null +++ b/2004/n/fpga/src/decodisa/decodisa_timesim.vhd @@ -0,0 +1,20384 @@ +-- Xilinx Vhdl netlist produced by netgen application (version G.26) +-- Command : -intstyle ise -s 6 -pcf decodisa.pcf -ngm decodisa.ngm -rpw 100 -tpw 0 -ar Structure -xon true -w -ofmt vhdl -sim decodisa.ncd decodisa_timesim.vhd +-- Input file : decodisa.ncd +-- Output file : decodisa_timesim.vhd +-- Design name : decodisa +-- # of Entities : 1 +-- Xilinx : D:/xilinx +-- Device : 2s200fg456-6 (PRODUCTION 1.27 2003-11-04) + +-- This vhdl netlist is a simulation model and uses simulation +-- primitives which may not represent the true implementation of the +-- device, however the netlist is functionally correct and should not +-- be modified. This file cannot be synthesized and should only be used +-- with supported simulation tools. + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library SIMPRIM; +use SIMPRIM.VCOMPONENTS.ALL; +use SIMPRIM.VPACKAGE.ALL; + +entity decodisa is + port ( + rw : out STD_LOGIC; + clk : out STD_LOGIC; + IOW : in STD_LOGIC := 'X'; + IOR : in STD_LOGIC := 'X'; + AEN : in STD_LOGIC := 'X'; + cs : out STD_LOGIC_VECTOR ( 255 downto 0 ); + adr_bus : in STD_LOGIC_VECTOR ( 23 downto 0 ) + ); +end decodisa; + +architecture Structure of decodisa is + signal adr_bus_3_IBUF : STD_LOGIC; + signal adr_bus_2_IBUF : STD_LOGIC; + signal adr_bus_1_IBUF : STD_LOGIC; + signal adr_bus_0_IBUF : STD_LOGIC; + signal adr_bus_7_IBUF : STD_LOGIC; + signal adr_bus_6_IBUF : STD_LOGIC; + signal adr_bus_5_IBUF : STD_LOGIC; + signal adr_bus_4_IBUF : STD_LOGIC; + signal dadrL_N18117 : STD_LOGIC; + signal dadrL_N18116 : STD_LOGIC; + signal dadrL_N14638 : STD_LOGIC; + signal dadrL_N14637 : STD_LOGIC; + signal dadrL_N16129 : STD_LOGIC; + signal dadrL_N16128 : STD_LOGIC; + signal dadrL_N16058 : STD_LOGIC; + signal dadrL_N16057 : STD_LOGIC; + signal dadrL_N1361 : STD_LOGIC; + signal dadrL_N1360 : STD_LOGIC; + signal dadrL_N1290 : STD_LOGIC; + signal dadrL_N1289 : STD_LOGIC; + signal dadrL_N8816 : STD_LOGIC; + signal dadrL_N8815 : STD_LOGIC; + signal dadrL_N11442 : STD_LOGIC; + signal dadrL_N11443 : STD_LOGIC; + signal dadrL_N8745 : STD_LOGIC; + signal dadrL_N8744 : STD_LOGIC; + signal dadrL_N11371 : STD_LOGIC; + signal dadrL_N11372 : STD_LOGIC; + signal dadrL_N18330 : STD_LOGIC; + signal dadrL_N18329 : STD_LOGIC; + signal dadrL_N14851 : STD_LOGIC; + signal dadrL_N14850 : STD_LOGIC; + signal dadrL_N18259 : STD_LOGIC; + signal dadrL_N18258 : STD_LOGIC; + signal dadrL_N16271 : STD_LOGIC; + signal dadrL_N16270 : STD_LOGIC; + signal dadrL_N14780 : STD_LOGIC; + signal dadrL_N14779 : STD_LOGIC; + signal dadrL_N16200 : STD_LOGIC; + signal dadrL_N16199 : STD_LOGIC; + signal dadrL_N1502 : STD_LOGIC; + signal dadrL_N1503 : STD_LOGIC; + signal dadrL_N1431 : STD_LOGIC; + signal dadrL_N1432 : STD_LOGIC; + signal dadrL_N8958 : STD_LOGIC; + signal dadrL_N8957 : STD_LOGIC; + signal dadrL_N11585 : STD_LOGIC; + signal dadrL_N11584 : STD_LOGIC; + signal dadrL_N8887 : STD_LOGIC; + signal dadrL_N8886 : STD_LOGIC; + signal dadrL_N11513 : STD_LOGIC; + signal dadrL_N11514 : STD_LOGIC; + signal dadrL_N14992 : STD_LOGIC; + signal dadrL_N14993 : STD_LOGIC; + signal dadrL_N16412 : STD_LOGIC; + signal dadrL_N16413 : STD_LOGIC; + signal dadrL_N14921 : STD_LOGIC; + signal dadrL_N14922 : STD_LOGIC; + signal dadrL_N16341 : STD_LOGIC; + signal dadrL_N16342 : STD_LOGIC; + signal dadrL_N1645 : STD_LOGIC; + signal dadrL_N1644 : STD_LOGIC; + signal dadrL_N1573 : STD_LOGIC; + signal dadrL_N1574 : STD_LOGIC; + signal dadrL_N11727 : STD_LOGIC; + signal dadrL_N11726 : STD_LOGIC; + signal dadrL_N11656 : STD_LOGIC; + signal dadrL_N11655 : STD_LOGIC; + signal dadrL_N15135 : STD_LOGIC; + signal dadrL_N15134 : STD_LOGIC; + signal dadrL_N16555 : STD_LOGIC; + signal dadrL_N16554 : STD_LOGIC; + signal dadrL_N15063 : STD_LOGIC; + signal dadrL_N15064 : STD_LOGIC; + signal dadrL_N16483 : STD_LOGIC; + signal dadrL_N16484 : STD_LOGIC; + signal dadrL_N1787 : STD_LOGIC; + signal dadrL_N1786 : STD_LOGIC; + signal dadrL_N1716 : STD_LOGIC; + signal dadrL_N1715 : STD_LOGIC; + signal dadrL_N11869 : STD_LOGIC; + signal dadrL_N11868 : STD_LOGIC; + signal dadrL_N11798 : STD_LOGIC; + signal dadrL_N11797 : STD_LOGIC; + signal dadrL_N15277 : STD_LOGIC; + signal dadrL_N15276 : STD_LOGIC; + signal dadrL_N15206 : STD_LOGIC; + signal dadrL_N15205 : STD_LOGIC; + signal dadrL_N16697 : STD_LOGIC; + signal dadrL_N16696 : STD_LOGIC; + signal dadrL_N16626 : STD_LOGIC; + signal dadrL_N16625 : STD_LOGIC; + signal dadrL_N1929 : STD_LOGIC; + signal dadrL_N1928 : STD_LOGIC; + signal dadrL_N1858 : STD_LOGIC; + signal dadrL_N1857 : STD_LOGIC; + signal dadrL_N12011 : STD_LOGIC; + signal dadrL_N12010 : STD_LOGIC; + signal dadrL_N11940 : STD_LOGIC; + signal dadrL_N11939 : STD_LOGIC; + signal dadrL_N15419 : STD_LOGIC; + signal dadrL_N15418 : STD_LOGIC; + signal dadrL_N16839 : STD_LOGIC; + signal dadrL_N16838 : STD_LOGIC; + signal dadrL_N15348 : STD_LOGIC; + signal dadrL_N15347 : STD_LOGIC; + signal dadrL_N16768 : STD_LOGIC; + signal dadrL_N16767 : STD_LOGIC; + signal dadrL_N12152 : STD_LOGIC; + signal dadrL_N12153 : STD_LOGIC; + signal dadrL_N12081 : STD_LOGIC; + signal dadrL_N12082 : STD_LOGIC; + signal dadrL_N15561 : STD_LOGIC; + signal dadrL_N15560 : STD_LOGIC; + signal dadrL_N15490 : STD_LOGIC; + signal dadrL_N15489 : STD_LOGIC; + signal dadrL_N16910 : STD_LOGIC; + signal dadrL_N16909 : STD_LOGIC; + signal dadrL_N4413 : STD_LOGIC; + signal dadrL_N4414 : STD_LOGIC; + signal dadrL_N4342 : STD_LOGIC; + signal dadrL_N4343 : STD_LOGIC; + signal dadrL_N12223 : STD_LOGIC; + signal dadrL_N12224 : STD_LOGIC; + signal dadrL_N15702 : STD_LOGIC; + signal dadrL_N15703 : STD_LOGIC; + signal dadrL_N15631 : STD_LOGIC; + signal dadrL_N15632 : STD_LOGIC; + signal dadrL_N4556 : STD_LOGIC; + signal dadrL_N4555 : STD_LOGIC; + signal dadrL_N4485 : STD_LOGIC; + signal dadrL_N4484 : STD_LOGIC; + signal dadrL_N12366 : STD_LOGIC; + signal dadrL_N12365 : STD_LOGIC; + signal dadrL_N15845 : STD_LOGIC; + signal dadrL_N15844 : STD_LOGIC; + signal dadrL_N12295 : STD_LOGIC; + signal dadrL_N12294 : STD_LOGIC; + signal dadrL_N15773 : STD_LOGIC; + signal dadrL_N15774 : STD_LOGIC; + signal dadrL_N4698 : STD_LOGIC; + signal dadrL_N4697 : STD_LOGIC; + signal dadrL_N4627 : STD_LOGIC; + signal dadrL_N4626 : STD_LOGIC; + signal dadrL_N12508 : STD_LOGIC; + signal dadrL_N12507 : STD_LOGIC; + signal dadrL_N15987 : STD_LOGIC; + signal dadrL_N15986 : STD_LOGIC; + signal dadrL_N12437 : STD_LOGIC; + signal dadrL_N12436 : STD_LOGIC; + signal dadrL_N15916 : STD_LOGIC; + signal dadrL_N15915 : STD_LOGIC; + signal dadrL_N4840 : STD_LOGIC; + signal dadrL_N4839 : STD_LOGIC; + signal dadrL_N4769 : STD_LOGIC; + signal dadrL_N4768 : STD_LOGIC; + signal dadrL_N12650 : STD_LOGIC; + signal dadrL_N12649 : STD_LOGIC; + signal dadrL_N12579 : STD_LOGIC; + signal dadrL_N12578 : STD_LOGIC; + signal dadrL_N4981 : STD_LOGIC; + signal dadrL_N4982 : STD_LOGIC; + signal dadrL_N4911 : STD_LOGIC; + signal dadrL_N4910 : STD_LOGIC; + signal dadrL_N5337 : STD_LOGIC; + signal dadrL_N5336 : STD_LOGIC; + signal dadrL_N5266 : STD_LOGIC; + signal dadrL_N5265 : STD_LOGIC; + signal dadrL_N12791 : STD_LOGIC; + signal dadrL_N12792 : STD_LOGIC; + signal dadrL_N12721 : STD_LOGIC; + signal dadrL_N12720 : STD_LOGIC; + signal dadrL_N5123 : STD_LOGIC; + signal dadrL_N5124 : STD_LOGIC; + signal dadrL_N5052 : STD_LOGIC; + signal dadrL_N5053 : STD_LOGIC; + signal dadrL_N5479 : STD_LOGIC; + signal dadrL_N5478 : STD_LOGIC; + signal dadrL_N5408 : STD_LOGIC; + signal dadrL_N5407 : STD_LOGIC; + signal dadrL_N12933 : STD_LOGIC; + signal dadrL_N12934 : STD_LOGIC; + signal dadrL_N12862 : STD_LOGIC; + signal dadrL_N12863 : STD_LOGIC; + signal dadrL_N5195 : STD_LOGIC; + signal dadrL_N5194 : STD_LOGIC; + signal dadrL_N5621 : STD_LOGIC; + signal dadrL_N5620 : STD_LOGIC; + signal dadrL_N5550 : STD_LOGIC; + signal dadrL_N5549 : STD_LOGIC; + signal dadrL_N13076 : STD_LOGIC; + signal dadrL_N13075 : STD_LOGIC; + signal dadrL_N13005 : STD_LOGIC; + signal dadrL_N13004 : STD_LOGIC; + signal dadrL_N5762 : STD_LOGIC; + signal dadrL_N5763 : STD_LOGIC; + signal dadrL_N5691 : STD_LOGIC; + signal dadrL_N5692 : STD_LOGIC; + signal dadrL_N13218 : STD_LOGIC; + signal dadrL_N13217 : STD_LOGIC; + signal dadrL_N13147 : STD_LOGIC; + signal dadrL_N13146 : STD_LOGIC; + signal dadrL_N5905 : STD_LOGIC; + signal dadrL_N5904 : STD_LOGIC; + signal dadrL_N5833 : STD_LOGIC; + signal dadrL_N5834 : STD_LOGIC; + signal dadrL_N13360 : STD_LOGIC; + signal dadrL_N13359 : STD_LOGIC; + signal dadrL_N13289 : STD_LOGIC; + signal dadrL_N13288 : STD_LOGIC; + signal dadrL_N18471 : STD_LOGIC; + signal dadrL_N18472 : STD_LOGIC; + signal dadrL_N18401 : STD_LOGIC; + signal dadrL_N18400 : STD_LOGIC; + signal dadrL_N6047 : STD_LOGIC; + signal dadrL_N6046 : STD_LOGIC; + signal dadrL_N5976 : STD_LOGIC; + signal dadrL_N5975 : STD_LOGIC; + signal dadrL_N10022 : STD_LOGIC; + signal dadrL_N10023 : STD_LOGIC; + signal dadrL_N13501 : STD_LOGIC; + signal dadrL_N13502 : STD_LOGIC; + signal dadrL_N9951 : STD_LOGIC; + signal dadrL_N9952 : STD_LOGIC; + signal dadrL_N13786 : STD_LOGIC; + signal dadrL_N13785 : STD_LOGIC; + signal dadrL_N13431 : STD_LOGIC; + signal dadrL_N13430 : STD_LOGIC; + signal dadrL_N13715 : STD_LOGIC; + signal dadrL_N13714 : STD_LOGIC; + signal dadrL_N18613 : STD_LOGIC; + signal dadrL_N18614 : STD_LOGIC; + signal dadrL_N18542 : STD_LOGIC; + signal dadrL_N18543 : STD_LOGIC; + signal dadrL_N9100 : STD_LOGIC; + signal dadrL_N9099 : STD_LOGIC; + signal dadrL_N6189 : STD_LOGIC; + signal dadrL_N6188 : STD_LOGIC; + signal dadrL_N9029 : STD_LOGIC; + signal dadrL_N9028 : STD_LOGIC; + signal dadrL_N6118 : STD_LOGIC; + signal dadrL_N6117 : STD_LOGIC; + signal dadrL_N10165 : STD_LOGIC; + signal dadrL_N10164 : STD_LOGIC; + signal dadrL_N13643 : STD_LOGIC; + signal dadrL_N13644 : STD_LOGIC; + signal dadrL_N10093 : STD_LOGIC; + signal dadrL_N10094 : STD_LOGIC; + signal dadrL_N13928 : STD_LOGIC; + signal dadrL_N13927 : STD_LOGIC; + signal dadrL_N13572 : STD_LOGIC; + signal dadrL_N13573 : STD_LOGIC; + signal dadrL_N13857 : STD_LOGIC; + signal dadrL_N13856 : STD_LOGIC; + signal dadrL_N18685 : STD_LOGIC; + signal dadrL_N18684 : STD_LOGIC; + signal dadrL_N9241 : STD_LOGIC; + signal dadrL_N9242 : STD_LOGIC; + signal dadrL_N6331 : STD_LOGIC; + signal dadrL_N6330 : STD_LOGIC; + signal dadrL_N9171 : STD_LOGIC; + signal dadrL_N9170 : STD_LOGIC; + signal dadrL_N6260 : STD_LOGIC; + signal dadrL_N6259 : STD_LOGIC; + signal dadrL_N10307 : STD_LOGIC; + signal dadrL_N10306 : STD_LOGIC; + signal dadrL_N10236 : STD_LOGIC; + signal dadrL_N10235 : STD_LOGIC; + signal dadrL_N14070 : STD_LOGIC; + signal dadrL_N14069 : STD_LOGIC; + signal dadrL_N13999 : STD_LOGIC; + signal dadrL_N13998 : STD_LOGIC; + signal dadrL_N9383 : STD_LOGIC; + signal dadrL_N9384 : STD_LOGIC; + signal dadrL_N6472 : STD_LOGIC; + signal dadrL_N6473 : STD_LOGIC; + signal dadrL_N2993 : STD_LOGIC; + signal dadrL_N2994 : STD_LOGIC; + signal dadrL_N9312 : STD_LOGIC; + signal dadrL_N9313 : STD_LOGIC; + signal dadrL_N6401 : STD_LOGIC; + signal dadrL_N6402 : STD_LOGIC; + signal dadrL_N2922 : STD_LOGIC; + signal dadrL_N2923 : STD_LOGIC; + signal dadrL_N10449 : STD_LOGIC; + signal dadrL_N10448 : STD_LOGIC; + signal dadrL_N10378 : STD_LOGIC; + signal dadrL_N10377 : STD_LOGIC; + signal dadrL_N14211 : STD_LOGIC; + signal dadrL_N14212 : STD_LOGIC; + signal dadrL_N14141 : STD_LOGIC; + signal dadrL_N14140 : STD_LOGIC; + signal dadrL_N9526 : STD_LOGIC; + signal dadrL_N9525 : STD_LOGIC; + signal dadrL_N6615 : STD_LOGIC; + signal dadrL_N6614 : STD_LOGIC; + signal dadrL_N3136 : STD_LOGIC; + signal dadrL_N3135 : STD_LOGIC; + signal dadrL_N9455 : STD_LOGIC; + signal dadrL_N9454 : STD_LOGIC; + signal dadrL_N6543 : STD_LOGIC; + signal dadrL_N6544 : STD_LOGIC; + signal dadrL_N3065 : STD_LOGIC; + signal dadrL_N3064 : STD_LOGIC; + signal dadrL_N10591 : STD_LOGIC; + signal dadrL_N10590 : STD_LOGIC; + signal dadrL_N10520 : STD_LOGIC; + signal dadrL_N10519 : STD_LOGIC; + signal dadrL_N14353 : STD_LOGIC; + signal dadrL_N14354 : STD_LOGIC; + signal dadrL_N14282 : STD_LOGIC; + signal dadrL_N14283 : STD_LOGIC; + signal dadrL_N9668 : STD_LOGIC; + signal dadrL_N9667 : STD_LOGIC; + signal dadrL_N3278 : STD_LOGIC; + signal dadrL_N3277 : STD_LOGIC; + signal dadrL_N9597 : STD_LOGIC; + signal dadrL_N9596 : STD_LOGIC; + signal dadrL_N3207 : STD_LOGIC; + signal dadrL_N3206 : STD_LOGIC; + signal dadrL_N10732 : STD_LOGIC; + signal dadrL_N10733 : STD_LOGIC; + signal dadrL_N10661 : STD_LOGIC; + signal dadrL_N10662 : STD_LOGIC; + signal dadrL_N14496 : STD_LOGIC; + signal dadrL_N14495 : STD_LOGIC; + signal dadrL_N14425 : STD_LOGIC; + signal dadrL_N14424 : STD_LOGIC; + signal dadrL_N9810 : STD_LOGIC; + signal dadrL_N9809 : STD_LOGIC; + signal dadrL_N6757 : STD_LOGIC; + signal dadrL_N6756 : STD_LOGIC; + signal dadrL_N3420 : STD_LOGIC; + signal dadrL_N3419 : STD_LOGIC; + signal dadrL_N9739 : STD_LOGIC; + signal dadrL_N9738 : STD_LOGIC; + signal dadrL_N6686 : STD_LOGIC; + signal dadrL_N6685 : STD_LOGIC; + signal dadrL_N3349 : STD_LOGIC; + signal dadrL_N3348 : STD_LOGIC; + signal dadrL_N10875 : STD_LOGIC; + signal dadrL_N10874 : STD_LOGIC; + signal dadrL_N10803 : STD_LOGIC; + signal dadrL_N10804 : STD_LOGIC; + signal dadrL_N14567 : STD_LOGIC; + signal dadrL_N14566 : STD_LOGIC; + signal dadrL_N2071 : STD_LOGIC; + signal dadrL_N2070 : STD_LOGIC; + signal dadrL_N2000 : STD_LOGIC; + signal dadrL_N1999 : STD_LOGIC; + signal dadrL_N6899 : STD_LOGIC; + signal dadrL_N6898 : STD_LOGIC; + signal dadrL_N3561 : STD_LOGIC; + signal dadrL_N3562 : STD_LOGIC; + signal dadrL_N9881 : STD_LOGIC; + signal dadrL_N9880 : STD_LOGIC; + signal dadrL_N6828 : STD_LOGIC; + signal dadrL_N6827 : STD_LOGIC; + signal dadrL_N3491 : STD_LOGIC; + signal dadrL_N3490 : STD_LOGIC; + signal dadrL_N11017 : STD_LOGIC; + signal dadrL_N11016 : STD_LOGIC; + signal dadrL_N10946 : STD_LOGIC; + signal dadrL_N10945 : STD_LOGIC; + signal dadrL_N17051 : STD_LOGIC; + signal dadrL_N17052 : STD_LOGIC; + signal dadrL_N2212 : STD_LOGIC; + signal dadrL_N2213 : STD_LOGIC; + signal dadrL_N16981 : STD_LOGIC; + signal dadrL_N16980 : STD_LOGIC; + signal dadrL_N2141 : STD_LOGIC; + signal dadrL_N2142 : STD_LOGIC; + signal dadrL_N3703 : STD_LOGIC; + signal dadrL_N3704 : STD_LOGIC; + signal dadrL_N7041 : STD_LOGIC; + signal dadrL_N7040 : STD_LOGIC; + signal dadrL_N3632 : STD_LOGIC; + signal dadrL_N3633 : STD_LOGIC; + signal dadrL_N11159 : STD_LOGIC; + signal dadrL_N11158 : STD_LOGIC; + signal dadrL_N7680 : STD_LOGIC; + signal dadrL_N7679 : STD_LOGIC; + signal dadrL_N6970 : STD_LOGIC; + signal dadrL_N6969 : STD_LOGIC; + signal dadrL_N11088 : STD_LOGIC; + signal dadrL_N11087 : STD_LOGIC; + signal dadrL_N7609 : STD_LOGIC; + signal dadrL_N7608 : STD_LOGIC; + signal dadrL_N17193 : STD_LOGIC; + signal dadrL_N17194 : STD_LOGIC; + signal dadrL_N2355 : STD_LOGIC; + signal dadrL_N2354 : STD_LOGIC; + signal dadrL_N17122 : STD_LOGIC; + signal dadrL_N17123 : STD_LOGIC; + signal dadrL_N2283 : STD_LOGIC; + signal dadrL_N2284 : STD_LOGIC; + signal dadrL_N3846 : STD_LOGIC; + signal dadrL_N3845 : STD_LOGIC; + signal dadrL_N7182 : STD_LOGIC; + signal dadrL_N7183 : STD_LOGIC; + signal dadrL_N3775 : STD_LOGIC; + signal dadrL_N3774 : STD_LOGIC; + signal dadrL_N11301 : STD_LOGIC; + signal dadrL_N11300 : STD_LOGIC; + signal dadrL_N7821 : STD_LOGIC; + signal dadrL_N7822 : STD_LOGIC; + signal dadrL_N7111 : STD_LOGIC; + signal dadrL_N7112 : STD_LOGIC; + signal dadrL_N11230 : STD_LOGIC; + signal dadrL_N11229 : STD_LOGIC; + signal dadrL_N7751 : STD_LOGIC; + signal dadrL_N7750 : STD_LOGIC; + signal dadrL_N17336 : STD_LOGIC; + signal dadrL_N17335 : STD_LOGIC; + signal dadrL_N2497 : STD_LOGIC; + signal dadrL_N2496 : STD_LOGIC; + signal dadrL_N17265 : STD_LOGIC; + signal dadrL_N17264 : STD_LOGIC; + signal dadrL_N2426 : STD_LOGIC; + signal dadrL_N2425 : STD_LOGIC; + signal dadrL_N3988 : STD_LOGIC; + signal dadrL_N3987 : STD_LOGIC; + signal dadrL_N7325 : STD_LOGIC; + signal dadrL_N7324 : STD_LOGIC; + signal dadrL_N3917 : STD_LOGIC; + signal dadrL_N3916 : STD_LOGIC; + signal dadrL_N7963 : STD_LOGIC; + signal dadrL_N7964 : STD_LOGIC; + signal dadrL_N7253 : STD_LOGIC; + signal dadrL_N7254 : STD_LOGIC; + signal dadrL_N7892 : STD_LOGIC; + signal dadrL_N7893 : STD_LOGIC; + signal dadrL_N17478 : STD_LOGIC; + signal dadrL_N17477 : STD_LOGIC; + signal dadrL_N2639 : STD_LOGIC; + signal dadrL_N2638 : STD_LOGIC; + signal dadrL_N17407 : STD_LOGIC; + signal dadrL_N17406 : STD_LOGIC; + signal dadrL_N2568 : STD_LOGIC; + signal dadrL_N2567 : STD_LOGIC; + signal dadrL_N4130 : STD_LOGIC; + signal dadrL_N4129 : STD_LOGIC; + signal dadrL_N7467 : STD_LOGIC; + signal dadrL_N7466 : STD_LOGIC; + signal dadrL_N651 : STD_LOGIC; + signal dadrL_N650 : STD_LOGIC; + signal dadrL_N4059 : STD_LOGIC; + signal dadrL_N4058 : STD_LOGIC; + signal dadrL_N8106 : STD_LOGIC; + signal dadrL_N8105 : STD_LOGIC; + signal dadrL_N7396 : STD_LOGIC; + signal dadrL_N7395 : STD_LOGIC; + signal dadrL_N580 : STD_LOGIC; + signal dadrL_N579 : STD_LOGIC; + signal dadrL_N8035 : STD_LOGIC; + signal dadrL_N8034 : STD_LOGIC; + signal dadrL_N17620 : STD_LOGIC; + signal dadrL_N17619 : STD_LOGIC; + signal dadrL_N2781 : STD_LOGIC; + signal dadrL_N2780 : STD_LOGIC; + signal dadrL_N17549 : STD_LOGIC; + signal dadrL_N17548 : STD_LOGIC; + signal dadrL_N2710 : STD_LOGIC; + signal dadrL_N2709 : STD_LOGIC; + signal dadrL_N4271 : STD_LOGIC; + signal dadrL_N4272 : STD_LOGIC; + signal dadrL_N792 : STD_LOGIC; + signal dadrL_N793 : STD_LOGIC; + signal dadrL_N4201 : STD_LOGIC; + signal dadrL_N4200 : STD_LOGIC; + signal dadrL_N7538 : STD_LOGIC; + signal dadrL_N7537 : STD_LOGIC; + signal dadrL_N8248 : STD_LOGIC; + signal dadrL_N8247 : STD_LOGIC; + signal dadrL_N721 : STD_LOGIC; + signal dadrL_N722 : STD_LOGIC; + signal dadrL_N8177 : STD_LOGIC; + signal dadrL_N8176 : STD_LOGIC; + signal dadrL_N17761 : STD_LOGIC; + signal dadrL_N17762 : STD_LOGIC; + signal dadrL_N17691 : STD_LOGIC; + signal dadrL_N17690 : STD_LOGIC; + signal dadrL_N2851 : STD_LOGIC; + signal dadrL_N2852 : STD_LOGIC; + signal dadrL_N935 : STD_LOGIC; + signal dadrL_N934 : STD_LOGIC; + signal dadrL_N8390 : STD_LOGIC; + signal dadrL_N8389 : STD_LOGIC; + signal dadrL_N863 : STD_LOGIC; + signal dadrL_N864 : STD_LOGIC; + signal dadrL_N8319 : STD_LOGIC; + signal dadrL_N8318 : STD_LOGIC; + signal dadrL_N17903 : STD_LOGIC; + signal dadrL_N17904 : STD_LOGIC; + signal dadrL_N17832 : STD_LOGIC; + signal dadrL_N17833 : STD_LOGIC; + signal dadrL_N1077 : STD_LOGIC; + signal dadrL_N1076 : STD_LOGIC; + signal dadrL_N8531 : STD_LOGIC; + signal dadrL_N8532 : STD_LOGIC; + signal dadrL_N1006 : STD_LOGIC; + signal dadrL_N1005 : STD_LOGIC; + signal dadrL_N8461 : STD_LOGIC; + signal dadrL_N8460 : STD_LOGIC; + signal dadrL_N18046 : STD_LOGIC; + signal dadrL_N18045 : STD_LOGIC; + signal dadrL_N17975 : STD_LOGIC; + signal dadrL_N17974 : STD_LOGIC; + signal dadrL_N1219 : STD_LOGIC; + signal dadrL_N1218 : STD_LOGIC; + signal dadrL_N1148 : STD_LOGIC; + signal dadrL_N1147 : STD_LOGIC; + signal dadrL_N8673 : STD_LOGIC; + signal dadrL_N8674 : STD_LOGIC; + signal dadrL_N8602 : STD_LOGIC; + signal dadrL_N8603 : STD_LOGIC; + signal dadrL_N18188 : STD_LOGIC; + signal dadrL_N18187 : STD_LOGIC; + signal dadrL_N14709 : STD_LOGIC; + signal dadrL_N14708 : STD_LOGIC; + signal reg_select : STD_LOGIC; + signal cs_1_OBUF : STD_LOGIC; + signal cs_2_OBUF : STD_LOGIC; + signal cs_3_OBUF : STD_LOGIC; + signal cs_4_OBUF : STD_LOGIC; + signal cs_5_OBUF : STD_LOGIC; + signal cs_6_OBUF : STD_LOGIC; + signal cs_7_OBUF : STD_LOGIC; + signal adr_bus_9_IBUF : STD_LOGIC; + signal adr_bus_10_IBUF : STD_LOGIC; + signal adr_bus_11_IBUF : STD_LOGIC; + signal N5267 : STD_LOGIC; + signal cs_0_OBUF : STD_LOGIC; + signal cs_89_OBUF : STD_LOGIC; + signal cs_90_OBUF : STD_LOGIC; + signal cs_99_OBUF : STD_LOGIC; + signal cs_91_OBUF : STD_LOGIC; + signal cs_180_OBUF : STD_LOGIC; + signal cs_100_OBUF : STD_LOGIC; + signal cs_92_OBUF : STD_LOGIC; + signal cs_189_OBUF : STD_LOGIC; + signal cs_181_OBUF : STD_LOGIC; + signal cs_109_OBUF : STD_LOGIC; + signal cs_101_OBUF : STD_LOGIC; + signal cs_93_OBUF : STD_LOGIC; + signal cs_190_OBUF : STD_LOGIC; + signal cs_182_OBUF : STD_LOGIC; + signal cs_110_OBUF : STD_LOGIC; + signal cs_102_OBUF : STD_LOGIC; + signal cs_94_OBUF : STD_LOGIC; + signal cs_108_OBUF : STD_LOGIC; + signal cs_199_OBUF : STD_LOGIC; + signal cs_191_OBUF : STD_LOGIC; + signal cs_183_OBUF : STD_LOGIC; + signal cs_119_OBUF : STD_LOGIC; + signal cs_111_OBUF : STD_LOGIC; + signal cs_103_OBUF : STD_LOGIC; + signal cs_95_OBUF : STD_LOGIC; + signal cs_117_OBUF : STD_LOGIC; + signal cs_200_OBUF : STD_LOGIC; + signal cs_192_OBUF : STD_LOGIC; + signal cs_184_OBUF : STD_LOGIC; + signal cs_120_OBUF : STD_LOGIC; + signal cs_112_OBUF : STD_LOGIC; + signal cs_104_OBUF : STD_LOGIC; + signal cs_96_OBUF : STD_LOGIC; + signal cs_126_OBUF : STD_LOGIC; + signal cs_118_OBUF : STD_LOGIC; + signal cs_209_OBUF : STD_LOGIC; + signal cs_201_OBUF : STD_LOGIC; + signal cs_193_OBUF : STD_LOGIC; + signal cs_185_OBUF : STD_LOGIC; + signal cs_129_OBUF : STD_LOGIC; + signal cs_121_OBUF : STD_LOGIC; + signal cs_113_OBUF : STD_LOGIC; + signal cs_105_OBUF : STD_LOGIC; + signal cs_97_OBUF : STD_LOGIC; + signal cs_135_OBUF : STD_LOGIC; + signal cs_127_OBUF : STD_LOGIC; + signal cs_210_OBUF : STD_LOGIC; + signal cs_202_OBUF : STD_LOGIC; + signal cs_194_OBUF : STD_LOGIC; + signal cs_186_OBUF : STD_LOGIC; + signal cs_130_OBUF : STD_LOGIC; + signal cs_122_OBUF : STD_LOGIC; + signal cs_114_OBUF : STD_LOGIC; + signal cs_106_OBUF : STD_LOGIC; + signal cs_98_OBUF : STD_LOGIC; + signal cs_208_OBUF : STD_LOGIC; + signal cs_144_OBUF : STD_LOGIC; + signal cs_136_OBUF : STD_LOGIC; + signal cs_128_OBUF : STD_LOGIC; + signal cs_219_OBUF : STD_LOGIC; + signal cs_211_OBUF : STD_LOGIC; + signal cs_203_OBUF : STD_LOGIC; + signal cs_195_OBUF : STD_LOGIC; + signal cs_187_OBUF : STD_LOGIC; + signal cs_139_OBUF : STD_LOGIC; + signal cs_131_OBUF : STD_LOGIC; + signal cs_123_OBUF : STD_LOGIC; + signal cs_115_OBUF : STD_LOGIC; + signal cs_107_OBUF : STD_LOGIC; + signal cs_217_OBUF : STD_LOGIC; + signal cs_153_OBUF : STD_LOGIC; + signal cs_145_OBUF : STD_LOGIC; + signal cs_137_OBUF : STD_LOGIC; + signal cs_220_OBUF : STD_LOGIC; + signal cs_212_OBUF : STD_LOGIC; + signal cs_204_OBUF : STD_LOGIC; + signal cs_196_OBUF : STD_LOGIC; + signal cs_188_OBUF : STD_LOGIC; + signal cs_140_OBUF : STD_LOGIC; + signal cs_132_OBUF : STD_LOGIC; + signal cs_124_OBUF : STD_LOGIC; + signal cs_116_OBUF : STD_LOGIC; + signal cs_226_OBUF : STD_LOGIC; + signal cs_218_OBUF : STD_LOGIC; + signal cs_162_OBUF : STD_LOGIC; + signal cs_154_OBUF : STD_LOGIC; + signal cs_146_OBUF : STD_LOGIC; + signal cs_138_OBUF : STD_LOGIC; + signal cs_229_OBUF : STD_LOGIC; + signal cs_221_OBUF : STD_LOGIC; + signal cs_213_OBUF : STD_LOGIC; + signal cs_205_OBUF : STD_LOGIC; + signal cs_197_OBUF : STD_LOGIC; + signal cs_149_OBUF : STD_LOGIC; + signal cs_141_OBUF : STD_LOGIC; + signal cs_133_OBUF : STD_LOGIC; + signal cs_125_OBUF : STD_LOGIC; + signal cs_235_OBUF : STD_LOGIC; + signal cs_227_OBUF : STD_LOGIC; + signal cs_171_OBUF : STD_LOGIC; + signal cs_163_OBUF : STD_LOGIC; + signal cs_155_OBUF : STD_LOGIC; + signal cs_147_OBUF : STD_LOGIC; + signal cs_230_OBUF : STD_LOGIC; + signal cs_222_OBUF : STD_LOGIC; + signal cs_214_OBUF : STD_LOGIC; + signal cs_206_OBUF : STD_LOGIC; + signal cs_198_OBUF : STD_LOGIC; + signal cs_150_OBUF : STD_LOGIC; + signal cs_142_OBUF : STD_LOGIC; + signal cs_134_OBUF : STD_LOGIC; + signal cs_244_OBUF : STD_LOGIC; + signal cs_236_OBUF : STD_LOGIC; + signal cs_228_OBUF : STD_LOGIC; + signal cs_172_OBUF : STD_LOGIC; + signal cs_164_OBUF : STD_LOGIC; + signal cs_156_OBUF : STD_LOGIC; + signal cs_148_OBUF : STD_LOGIC; + signal cs_239_OBUF : STD_LOGIC; + signal cs_231_OBUF : STD_LOGIC; + signal cs_223_OBUF : STD_LOGIC; + signal cs_215_OBUF : STD_LOGIC; + signal cs_207_OBUF : STD_LOGIC; + signal cs_159_OBUF : STD_LOGIC; + signal cs_151_OBUF : STD_LOGIC; + signal cs_143_OBUF : STD_LOGIC; + signal cs_253_OBUF : STD_LOGIC; + signal cs_245_OBUF : STD_LOGIC; + signal cs_237_OBUF : STD_LOGIC; + signal cs_173_OBUF : STD_LOGIC; + signal cs_165_OBUF : STD_LOGIC; + signal cs_157_OBUF : STD_LOGIC; + signal cs_240_OBUF : STD_LOGIC; + signal cs_232_OBUF : STD_LOGIC; + signal cs_224_OBUF : STD_LOGIC; + signal cs_216_OBUF : STD_LOGIC; + signal cs_160_OBUF : STD_LOGIC; + signal cs_152_OBUF : STD_LOGIC; + signal cs_254_OBUF : STD_LOGIC; + signal cs_246_OBUF : STD_LOGIC; + signal cs_238_OBUF : STD_LOGIC; + signal cs_174_OBUF : STD_LOGIC; + signal cs_166_OBUF : STD_LOGIC; + signal cs_158_OBUF : STD_LOGIC; + signal cs_9_OBUF : STD_LOGIC; + signal cs_249_OBUF : STD_LOGIC; + signal cs_241_OBUF : STD_LOGIC; + signal cs_233_OBUF : STD_LOGIC; + signal cs_225_OBUF : STD_LOGIC; + signal cs_169_OBUF : STD_LOGIC; + signal cs_161_OBUF : STD_LOGIC; + signal cs_255_OBUF : STD_LOGIC; + signal cs_247_OBUF : STD_LOGIC; + signal cs_175_OBUF : STD_LOGIC; + signal cs_167_OBUF : STD_LOGIC; + signal cs_10_OBUF : STD_LOGIC; + signal cs_250_OBUF : STD_LOGIC; + signal cs_242_OBUF : STD_LOGIC; + signal cs_234_OBUF : STD_LOGIC; + signal cs_170_OBUF : STD_LOGIC; + signal cs_8_OBUF : STD_LOGIC; + signal cs_248_OBUF : STD_LOGIC; + signal cs_176_OBUF : STD_LOGIC; + signal cs_168_OBUF : STD_LOGIC; + signal cs_19_OBUF : STD_LOGIC; + signal cs_11_OBUF : STD_LOGIC; + signal cs_251_OBUF : STD_LOGIC; + signal cs_243_OBUF : STD_LOGIC; + signal cs_179_OBUF : STD_LOGIC; + signal cs_17_OBUF : STD_LOGIC; + signal cs_177_OBUF : STD_LOGIC; + signal cs_20_OBUF : STD_LOGIC; + signal cs_12_OBUF : STD_LOGIC; + signal cs_252_OBUF : STD_LOGIC; + signal cs_26_OBUF : STD_LOGIC; + signal cs_18_OBUF : STD_LOGIC; + signal cs_178_OBUF : STD_LOGIC; + signal cs_29_OBUF : STD_LOGIC; + signal cs_21_OBUF : STD_LOGIC; + signal cs_13_OBUF : STD_LOGIC; + signal cs_35_OBUF : STD_LOGIC; + signal cs_27_OBUF : STD_LOGIC; + signal cs_30_OBUF : STD_LOGIC; + signal cs_22_OBUF : STD_LOGIC; + signal cs_14_OBUF : STD_LOGIC; + signal cs_44_OBUF : STD_LOGIC; + signal cs_36_OBUF : STD_LOGIC; + signal cs_28_OBUF : STD_LOGIC; + signal cs_39_OBUF : STD_LOGIC; + signal cs_31_OBUF : STD_LOGIC; + signal cs_23_OBUF : STD_LOGIC; + signal cs_15_OBUF : STD_LOGIC; + signal cs_53_OBUF : STD_LOGIC; + signal cs_45_OBUF : STD_LOGIC; + signal cs_37_OBUF : STD_LOGIC; + signal cs_40_OBUF : STD_LOGIC; + signal cs_32_OBUF : STD_LOGIC; + signal cs_24_OBUF : STD_LOGIC; + signal cs_16_OBUF : STD_LOGIC; + signal cs_62_OBUF : STD_LOGIC; + signal cs_54_OBUF : STD_LOGIC; + signal cs_46_OBUF : STD_LOGIC; + signal cs_38_OBUF : STD_LOGIC; + signal cs_49_OBUF : STD_LOGIC; + signal cs_41_OBUF : STD_LOGIC; + signal cs_33_OBUF : STD_LOGIC; + signal cs_25_OBUF : STD_LOGIC; + signal cs_71_OBUF : STD_LOGIC; + signal cs_63_OBUF : STD_LOGIC; + signal cs_55_OBUF : STD_LOGIC; + signal cs_47_OBUF : STD_LOGIC; + signal cs_50_OBUF : STD_LOGIC; + signal cs_42_OBUF : STD_LOGIC; + signal cs_34_OBUF : STD_LOGIC; + signal cs_80_OBUF : STD_LOGIC; + signal cs_72_OBUF : STD_LOGIC; + signal cs_64_OBUF : STD_LOGIC; + signal cs_56_OBUF : STD_LOGIC; + signal cs_48_OBUF : STD_LOGIC; + signal cs_59_OBUF : STD_LOGIC; + signal cs_51_OBUF : STD_LOGIC; + signal cs_43_OBUF : STD_LOGIC; + signal cs_81_OBUF : STD_LOGIC; + signal cs_73_OBUF : STD_LOGIC; + signal cs_65_OBUF : STD_LOGIC; + signal cs_57_OBUF : STD_LOGIC; + signal cs_60_OBUF : STD_LOGIC; + signal cs_52_OBUF : STD_LOGIC; + signal cs_82_OBUF : STD_LOGIC; + signal cs_74_OBUF : STD_LOGIC; + signal cs_66_OBUF : STD_LOGIC; + signal cs_58_OBUF : STD_LOGIC; + signal cs_69_OBUF : STD_LOGIC; + signal cs_61_OBUF : STD_LOGIC; + signal cs_83_OBUF : STD_LOGIC; + signal cs_75_OBUF : STD_LOGIC; + signal cs_67_OBUF : STD_LOGIC; + signal cs_70_OBUF : STD_LOGIC; + signal cs_84_OBUF : STD_LOGIC; + signal cs_76_OBUF : STD_LOGIC; + signal cs_68_OBUF : STD_LOGIC; + signal cs_79_OBUF : STD_LOGIC; + signal cs_85_OBUF : STD_LOGIC; + signal cs_77_OBUF : STD_LOGIC; + signal cs_86_OBUF : STD_LOGIC; + signal cs_78_OBUF : STD_LOGIC; + signal cs_87_OBUF : STD_LOGIC; + signal cs_88_OBUF : STD_LOGIC; + signal rw_OBUF : STD_LOGIC; + signal adr_bus_8_IBUF : STD_LOGIC; + signal AEN_IBUF : STD_LOGIC; + signal IOR_IBUF : STD_LOGIC; + signal IOW_IBUF : STD_LOGIC; + signal clk_OBUF : STD_LOGIC; + signal adr_bus_12_IBUF : STD_LOGIC; + signal adr_bus_13_IBUF : STD_LOGIC; + signal adr_bus_14_IBUF : STD_LOGIC; + signal adr_bus_15_IBUF : STD_LOGIC; + signal CHOICE45 : STD_LOGIC; + signal GSR : STD_LOGIC; + signal GTS : STD_LOGIC; + signal dadrL_N18117_FROM : STD_LOGIC; + signal dadrL_N18117_GROM : STD_LOGIC; + signal dadrL_N14638_FROM : STD_LOGIC; + signal dadrL_N14638_GROM : STD_LOGIC; + signal dadrL_N16129_FROM : STD_LOGIC; + signal dadrL_N16129_GROM : STD_LOGIC; + signal dadrL_N16058_FROM : STD_LOGIC; + signal dadrL_N16058_GROM : STD_LOGIC; + signal dadrL_N1361_FROM : STD_LOGIC; + signal dadrL_N1361_GROM : STD_LOGIC; + signal dadrL_N1290_FROM : STD_LOGIC; + signal dadrL_N1290_GROM : STD_LOGIC; + signal dadrL_N8816_FROM : STD_LOGIC; + signal dadrL_N8816_GROM : STD_LOGIC; + signal dadrL_N11442_FROM : STD_LOGIC; + signal dadrL_N11442_GROM : STD_LOGIC; + signal dadrL_N8745_FROM : STD_LOGIC; + signal dadrL_N8745_GROM : STD_LOGIC; + signal dadrL_N11371_FROM : STD_LOGIC; + signal dadrL_N11371_GROM : STD_LOGIC; + signal dadrL_N18330_FROM : STD_LOGIC; + signal dadrL_N18330_GROM : STD_LOGIC; + signal dadrL_N14851_FROM : STD_LOGIC; + signal dadrL_N14851_GROM : STD_LOGIC; + signal dadrL_N18259_FROM : STD_LOGIC; + signal dadrL_N18259_GROM : STD_LOGIC; + signal dadrL_N16271_FROM : STD_LOGIC; + signal dadrL_N16271_GROM : STD_LOGIC; + signal dadrL_N14780_FROM : STD_LOGIC; + signal dadrL_N14780_GROM : STD_LOGIC; + signal dadrL_N16200_FROM : STD_LOGIC; + signal dadrL_N16200_GROM : STD_LOGIC; + signal dadrL_N1502_FROM : STD_LOGIC; + signal dadrL_N1502_GROM : STD_LOGIC; + signal dadrL_N1431_FROM : STD_LOGIC; + signal dadrL_N1431_GROM : STD_LOGIC; + signal dadrL_N8958_FROM : STD_LOGIC; + signal dadrL_N8958_GROM : STD_LOGIC; + signal dadrL_N11585_FROM : STD_LOGIC; + signal dadrL_N11585_GROM : STD_LOGIC; + signal dadrL_N8887_FROM : STD_LOGIC; + signal dadrL_N8887_GROM : STD_LOGIC; + signal dadrL_N11513_FROM : STD_LOGIC; + signal dadrL_N11513_GROM : STD_LOGIC; + signal dadrL_N14992_FROM : STD_LOGIC; + signal dadrL_N14992_GROM : STD_LOGIC; + signal dadrL_N16412_FROM : STD_LOGIC; + signal dadrL_N16412_GROM : STD_LOGIC; + signal dadrL_N14921_FROM : STD_LOGIC; + signal dadrL_N14921_GROM : STD_LOGIC; + signal dadrL_N16341_FROM : STD_LOGIC; + signal dadrL_N16341_GROM : STD_LOGIC; + signal dadrL_N1645_FROM : STD_LOGIC; + signal dadrL_N1645_GROM : STD_LOGIC; + signal dadrL_N1573_FROM : STD_LOGIC; + signal dadrL_N1573_GROM : STD_LOGIC; + signal dadrL_N11727_FROM : STD_LOGIC; + signal dadrL_N11727_GROM : STD_LOGIC; + signal dadrL_N11656_FROM : STD_LOGIC; + signal dadrL_N11656_GROM : STD_LOGIC; + signal dadrL_N15135_FROM : STD_LOGIC; + signal dadrL_N15135_GROM : STD_LOGIC; + signal dadrL_N16555_FROM : STD_LOGIC; + signal dadrL_N16555_GROM : STD_LOGIC; + signal dadrL_N15063_FROM : STD_LOGIC; + signal dadrL_N15063_GROM : STD_LOGIC; + signal dadrL_N16483_FROM : STD_LOGIC; + signal dadrL_N16483_GROM : STD_LOGIC; + signal dadrL_N1787_FROM : STD_LOGIC; + signal dadrL_N1787_GROM : STD_LOGIC; + signal dadrL_N1716_FROM : STD_LOGIC; + signal dadrL_N1716_GROM : STD_LOGIC; + signal dadrL_N11869_FROM : STD_LOGIC; + signal dadrL_N11869_GROM : STD_LOGIC; + signal dadrL_N11798_FROM : STD_LOGIC; + signal dadrL_N11798_GROM : STD_LOGIC; + signal dadrL_N15277_FROM : STD_LOGIC; + signal dadrL_N15277_GROM : STD_LOGIC; + signal dadrL_N15206_FROM : STD_LOGIC; + signal dadrL_N15206_GROM : STD_LOGIC; + signal dadrL_N16697_FROM : STD_LOGIC; + signal dadrL_N16697_GROM : STD_LOGIC; + signal dadrL_N16626_FROM : STD_LOGIC; + signal dadrL_N16626_GROM : STD_LOGIC; + signal dadrL_N1929_FROM : STD_LOGIC; + signal dadrL_N1929_GROM : STD_LOGIC; + signal dadrL_N1858_FROM : STD_LOGIC; + signal dadrL_N1858_GROM : STD_LOGIC; + signal dadrL_N12011_FROM : STD_LOGIC; + signal dadrL_N12011_GROM : STD_LOGIC; + signal dadrL_N11940_FROM : STD_LOGIC; + signal dadrL_N11940_GROM : STD_LOGIC; + signal dadrL_N15419_FROM : STD_LOGIC; + signal dadrL_N15419_GROM : STD_LOGIC; + signal dadrL_N16839_FROM : STD_LOGIC; + signal dadrL_N16839_GROM : STD_LOGIC; + signal dadrL_N15348_FROM : STD_LOGIC; + signal dadrL_N15348_GROM : STD_LOGIC; + signal dadrL_N16768_FROM : STD_LOGIC; + signal dadrL_N16768_GROM : STD_LOGIC; + signal dadrL_N12152_FROM : STD_LOGIC; + signal dadrL_N12152_GROM : STD_LOGIC; + signal dadrL_N12081_FROM : STD_LOGIC; + signal dadrL_N12081_GROM : STD_LOGIC; + signal dadrL_N15561_FROM : STD_LOGIC; + signal dadrL_N15561_GROM : STD_LOGIC; + signal dadrL_N15490_FROM : STD_LOGIC; + signal dadrL_N15490_GROM : STD_LOGIC; + signal dadrL_N16910_FROM : STD_LOGIC; + signal dadrL_N16910_GROM : STD_LOGIC; + signal dadrL_N4413_FROM : STD_LOGIC; + signal dadrL_N4413_GROM : STD_LOGIC; + signal dadrL_N4342_FROM : STD_LOGIC; + signal dadrL_N4342_GROM : STD_LOGIC; + signal dadrL_N12223_FROM : STD_LOGIC; + signal dadrL_N12223_GROM : STD_LOGIC; + signal dadrL_N15702_FROM : STD_LOGIC; + signal dadrL_N15702_GROM : STD_LOGIC; + signal dadrL_N15631_FROM : STD_LOGIC; + signal dadrL_N15631_GROM : STD_LOGIC; + signal dadrL_N4556_FROM : STD_LOGIC; + signal dadrL_N4556_GROM : STD_LOGIC; + signal dadrL_N4485_FROM : STD_LOGIC; + signal dadrL_N4485_GROM : STD_LOGIC; + signal dadrL_N12366_FROM : STD_LOGIC; + signal dadrL_N12366_GROM : STD_LOGIC; + signal dadrL_N15845_FROM : STD_LOGIC; + signal dadrL_N15845_GROM : STD_LOGIC; + signal dadrL_N12295_FROM : STD_LOGIC; + signal dadrL_N12295_GROM : STD_LOGIC; + signal dadrL_N15773_FROM : STD_LOGIC; + signal dadrL_N15773_GROM : STD_LOGIC; + signal dadrL_N4698_FROM : STD_LOGIC; + signal dadrL_N4698_GROM : STD_LOGIC; + signal dadrL_N4627_FROM : STD_LOGIC; + signal dadrL_N4627_GROM : STD_LOGIC; + signal dadrL_N12508_FROM : STD_LOGIC; + signal dadrL_N12508_GROM : STD_LOGIC; + signal dadrL_N15987_FROM : STD_LOGIC; + signal dadrL_N15987_GROM : STD_LOGIC; + signal dadrL_N12437_FROM : STD_LOGIC; + signal dadrL_N12437_GROM : STD_LOGIC; + signal dadrL_N15916_FROM : STD_LOGIC; + signal dadrL_N15916_GROM : STD_LOGIC; + signal dadrL_N4840_FROM : STD_LOGIC; + signal dadrL_N4840_GROM : STD_LOGIC; + signal dadrL_N4769_FROM : STD_LOGIC; + signal dadrL_N4769_GROM : STD_LOGIC; + signal dadrL_N12650_FROM : STD_LOGIC; + signal dadrL_N12650_GROM : STD_LOGIC; + signal dadrL_N12579_FROM : STD_LOGIC; + signal dadrL_N12579_GROM : STD_LOGIC; + signal dadrL_N4981_FROM : STD_LOGIC; + signal dadrL_N4981_GROM : STD_LOGIC; + signal dadrL_N4911_FROM : STD_LOGIC; + signal dadrL_N4911_GROM : STD_LOGIC; + signal dadrL_N5337_FROM : STD_LOGIC; + signal dadrL_N5337_GROM : STD_LOGIC; + signal dadrL_N5266_FROM : STD_LOGIC; + signal dadrL_N5266_GROM : STD_LOGIC; + signal dadrL_N12791_FROM : STD_LOGIC; + signal dadrL_N12791_GROM : STD_LOGIC; + signal dadrL_N12721_FROM : STD_LOGIC; + signal dadrL_N12721_GROM : STD_LOGIC; + signal dadrL_N5123_FROM : STD_LOGIC; + signal dadrL_N5123_GROM : STD_LOGIC; + signal dadrL_N5052_FROM : STD_LOGIC; + signal dadrL_N5052_GROM : STD_LOGIC; + signal dadrL_N5479_FROM : STD_LOGIC; + signal dadrL_N5479_GROM : STD_LOGIC; + signal dadrL_N5408_FROM : STD_LOGIC; + signal dadrL_N5408_GROM : STD_LOGIC; + signal dadrL_N12933_FROM : STD_LOGIC; + signal dadrL_N12933_GROM : STD_LOGIC; + signal dadrL_N12862_FROM : STD_LOGIC; + signal dadrL_N12862_GROM : STD_LOGIC; + signal dadrL_N5195_FROM : STD_LOGIC; + signal dadrL_N5195_GROM : STD_LOGIC; + signal dadrL_N5621_FROM : STD_LOGIC; + signal dadrL_N5621_GROM : STD_LOGIC; + signal dadrL_N5550_FROM : STD_LOGIC; + signal dadrL_N5550_GROM : STD_LOGIC; + signal dadrL_N13076_FROM : STD_LOGIC; + signal dadrL_N13076_GROM : STD_LOGIC; + signal dadrL_N13005_FROM : STD_LOGIC; + signal dadrL_N13005_GROM : STD_LOGIC; + signal dadrL_N5762_FROM : STD_LOGIC; + signal dadrL_N5762_GROM : STD_LOGIC; + signal dadrL_N5691_FROM : STD_LOGIC; + signal dadrL_N5691_GROM : STD_LOGIC; + signal dadrL_N13218_FROM : STD_LOGIC; + signal dadrL_N13218_GROM : STD_LOGIC; + signal dadrL_N13147_FROM : STD_LOGIC; + signal dadrL_N13147_GROM : STD_LOGIC; + signal dadrL_N5905_FROM : STD_LOGIC; + signal dadrL_N5905_GROM : STD_LOGIC; + signal dadrL_N5833_FROM : STD_LOGIC; + signal dadrL_N5833_GROM : STD_LOGIC; + signal dadrL_N13360_FROM : STD_LOGIC; + signal dadrL_N13360_GROM : STD_LOGIC; + signal dadrL_N13289_FROM : STD_LOGIC; + signal dadrL_N13289_GROM : STD_LOGIC; + signal dadrL_N18471_FROM : STD_LOGIC; + signal dadrL_N18471_GROM : STD_LOGIC; + signal dadrL_N18401_FROM : STD_LOGIC; + signal dadrL_N18401_GROM : STD_LOGIC; + signal dadrL_N6047_FROM : STD_LOGIC; + signal dadrL_N6047_GROM : STD_LOGIC; + signal dadrL_N5976_FROM : STD_LOGIC; + signal dadrL_N5976_GROM : STD_LOGIC; + signal dadrL_N10022_FROM : STD_LOGIC; + signal dadrL_N10022_GROM : STD_LOGIC; + signal dadrL_N13501_FROM : STD_LOGIC; + signal dadrL_N13501_GROM : STD_LOGIC; + signal dadrL_N9951_FROM : STD_LOGIC; + signal dadrL_N9951_GROM : STD_LOGIC; + signal dadrL_N13786_FROM : STD_LOGIC; + signal dadrL_N13786_GROM : STD_LOGIC; + signal dadrL_N13431_FROM : STD_LOGIC; + signal dadrL_N13431_GROM : STD_LOGIC; + signal dadrL_N13715_FROM : STD_LOGIC; + signal dadrL_N13715_GROM : STD_LOGIC; + signal dadrL_N18613_FROM : STD_LOGIC; + signal dadrL_N18613_GROM : STD_LOGIC; + signal dadrL_N18542_FROM : STD_LOGIC; + signal dadrL_N18542_GROM : STD_LOGIC; + signal dadrL_N9100_FROM : STD_LOGIC; + signal dadrL_N9100_GROM : STD_LOGIC; + signal dadrL_N6189_FROM : STD_LOGIC; + signal dadrL_N6189_GROM : STD_LOGIC; + signal dadrL_N9029_FROM : STD_LOGIC; + signal dadrL_N9029_GROM : STD_LOGIC; + signal dadrL_N6118_FROM : STD_LOGIC; + signal dadrL_N6118_GROM : STD_LOGIC; + signal dadrL_N10165_FROM : STD_LOGIC; + signal dadrL_N10165_GROM : STD_LOGIC; + signal dadrL_N13643_FROM : STD_LOGIC; + signal dadrL_N13643_GROM : STD_LOGIC; + signal dadrL_N10093_FROM : STD_LOGIC; + signal dadrL_N10093_GROM : STD_LOGIC; + signal dadrL_N13928_FROM : STD_LOGIC; + signal dadrL_N13928_GROM : STD_LOGIC; + signal dadrL_N13572_FROM : STD_LOGIC; + signal dadrL_N13572_GROM : STD_LOGIC; + signal dadrL_N13857_FROM : STD_LOGIC; + signal dadrL_N13857_GROM : STD_LOGIC; + signal dadrL_N18685_FROM : STD_LOGIC; + signal dadrL_N18685_GROM : STD_LOGIC; + signal dadrL_N9241_FROM : STD_LOGIC; + signal dadrL_N9241_GROM : STD_LOGIC; + signal dadrL_N6331_FROM : STD_LOGIC; + signal dadrL_N6331_GROM : STD_LOGIC; + signal dadrL_N9171_FROM : STD_LOGIC; + signal dadrL_N9171_GROM : STD_LOGIC; + signal dadrL_N6260_FROM : STD_LOGIC; + signal dadrL_N6260_GROM : STD_LOGIC; + signal dadrL_N10307_FROM : STD_LOGIC; + signal dadrL_N10307_GROM : STD_LOGIC; + signal dadrL_N10236_FROM : STD_LOGIC; + signal dadrL_N10236_GROM : STD_LOGIC; + signal dadrL_N14070_FROM : STD_LOGIC; + signal dadrL_N14070_GROM : STD_LOGIC; + signal dadrL_N13999_FROM : STD_LOGIC; + signal dadrL_N13999_GROM : STD_LOGIC; + signal dadrL_N9383_FROM : STD_LOGIC; + signal dadrL_N9383_GROM : STD_LOGIC; + signal dadrL_N6472_FROM : STD_LOGIC; + signal dadrL_N6472_GROM : STD_LOGIC; + signal dadrL_N2993_FROM : STD_LOGIC; + signal dadrL_N2993_GROM : STD_LOGIC; + signal dadrL_N9312_FROM : STD_LOGIC; + signal dadrL_N9312_GROM : STD_LOGIC; + signal dadrL_N6401_FROM : STD_LOGIC; + signal dadrL_N6401_GROM : STD_LOGIC; + signal dadrL_N2922_FROM : STD_LOGIC; + signal dadrL_N2922_GROM : STD_LOGIC; + signal dadrL_N10449_FROM : STD_LOGIC; + signal dadrL_N10449_GROM : STD_LOGIC; + signal dadrL_N10378_FROM : STD_LOGIC; + signal dadrL_N10378_GROM : STD_LOGIC; + signal dadrL_N14211_FROM : STD_LOGIC; + signal dadrL_N14211_GROM : STD_LOGIC; + signal dadrL_N14141_FROM : STD_LOGIC; + signal dadrL_N14141_GROM : STD_LOGIC; + signal dadrL_N9526_FROM : STD_LOGIC; + signal dadrL_N9526_GROM : STD_LOGIC; + signal dadrL_N6615_FROM : STD_LOGIC; + signal dadrL_N6615_GROM : STD_LOGIC; + signal dadrL_N3136_FROM : STD_LOGIC; + signal dadrL_N3136_GROM : STD_LOGIC; + signal dadrL_N9455_FROM : STD_LOGIC; + signal dadrL_N9455_GROM : STD_LOGIC; + signal dadrL_N6543_FROM : STD_LOGIC; + signal dadrL_N6543_GROM : STD_LOGIC; + signal dadrL_N3065_FROM : STD_LOGIC; + signal dadrL_N3065_GROM : STD_LOGIC; + signal dadrL_N10591_FROM : STD_LOGIC; + signal dadrL_N10591_GROM : STD_LOGIC; + signal dadrL_N10520_FROM : STD_LOGIC; + signal dadrL_N10520_GROM : STD_LOGIC; + signal dadrL_N14353_FROM : STD_LOGIC; + signal dadrL_N14353_GROM : STD_LOGIC; + signal dadrL_N14282_FROM : STD_LOGIC; + signal dadrL_N14282_GROM : STD_LOGIC; + signal dadrL_N9668_FROM : STD_LOGIC; + signal dadrL_N9668_GROM : STD_LOGIC; + signal dadrL_N3278_FROM : STD_LOGIC; + signal dadrL_N3278_GROM : STD_LOGIC; + signal dadrL_N9597_FROM : STD_LOGIC; + signal dadrL_N9597_GROM : STD_LOGIC; + signal dadrL_N3207_FROM : STD_LOGIC; + signal dadrL_N3207_GROM : STD_LOGIC; + signal dadrL_N10732_FROM : STD_LOGIC; + signal dadrL_N10732_GROM : STD_LOGIC; + signal dadrL_N10661_FROM : STD_LOGIC; + signal dadrL_N10661_GROM : STD_LOGIC; + signal dadrL_N14496_FROM : STD_LOGIC; + signal dadrL_N14496_GROM : STD_LOGIC; + signal dadrL_N14425_FROM : STD_LOGIC; + signal dadrL_N14425_GROM : STD_LOGIC; + signal dadrL_N9810_FROM : STD_LOGIC; + signal dadrL_N9810_GROM : STD_LOGIC; + signal dadrL_N6757_FROM : STD_LOGIC; + signal dadrL_N6757_GROM : STD_LOGIC; + signal dadrL_N3420_FROM : STD_LOGIC; + signal dadrL_N3420_GROM : STD_LOGIC; + signal dadrL_N9739_FROM : STD_LOGIC; + signal dadrL_N9739_GROM : STD_LOGIC; + signal dadrL_N6686_FROM : STD_LOGIC; + signal dadrL_N6686_GROM : STD_LOGIC; + signal dadrL_N3349_FROM : STD_LOGIC; + signal dadrL_N3349_GROM : STD_LOGIC; + signal dadrL_N10875_FROM : STD_LOGIC; + signal dadrL_N10875_GROM : STD_LOGIC; + signal dadrL_N10803_FROM : STD_LOGIC; + signal dadrL_N10803_GROM : STD_LOGIC; + signal dadrL_N14567_FROM : STD_LOGIC; + signal dadrL_N14567_GROM : STD_LOGIC; + signal dadrL_N2071_FROM : STD_LOGIC; + signal dadrL_N2071_GROM : STD_LOGIC; + signal dadrL_N2000_FROM : STD_LOGIC; + signal dadrL_N2000_GROM : STD_LOGIC; + signal dadrL_N6899_FROM : STD_LOGIC; + signal dadrL_N6899_GROM : STD_LOGIC; + signal dadrL_N3561_FROM : STD_LOGIC; + signal dadrL_N3561_GROM : STD_LOGIC; + signal dadrL_N9881_FROM : STD_LOGIC; + signal dadrL_N9881_GROM : STD_LOGIC; + signal dadrL_N6828_FROM : STD_LOGIC; + signal dadrL_N6828_GROM : STD_LOGIC; + signal dadrL_N3491_FROM : STD_LOGIC; + signal dadrL_N3491_GROM : STD_LOGIC; + signal dadrL_N11017_FROM : STD_LOGIC; + signal dadrL_N11017_GROM : STD_LOGIC; + signal dadrL_N10946_FROM : STD_LOGIC; + signal dadrL_N10946_GROM : STD_LOGIC; + signal dadrL_N17051_FROM : STD_LOGIC; + signal dadrL_N17051_GROM : STD_LOGIC; + signal dadrL_N2212_FROM : STD_LOGIC; + signal dadrL_N2212_GROM : STD_LOGIC; + signal dadrL_N16981_FROM : STD_LOGIC; + signal dadrL_N16981_GROM : STD_LOGIC; + signal dadrL_N2141_FROM : STD_LOGIC; + signal dadrL_N2141_GROM : STD_LOGIC; + signal dadrL_N3703_FROM : STD_LOGIC; + signal dadrL_N3703_GROM : STD_LOGIC; + signal dadrL_N7041_FROM : STD_LOGIC; + signal dadrL_N7041_GROM : STD_LOGIC; + signal dadrL_N3632_FROM : STD_LOGIC; + signal dadrL_N3632_GROM : STD_LOGIC; + signal dadrL_N11159_FROM : STD_LOGIC; + signal dadrL_N11159_GROM : STD_LOGIC; + signal dadrL_N7680_FROM : STD_LOGIC; + signal dadrL_N7680_GROM : STD_LOGIC; + signal dadrL_N6970_FROM : STD_LOGIC; + signal dadrL_N6970_GROM : STD_LOGIC; + signal dadrL_N11088_FROM : STD_LOGIC; + signal dadrL_N11088_GROM : STD_LOGIC; + signal dadrL_N7609_FROM : STD_LOGIC; + signal dadrL_N7609_GROM : STD_LOGIC; + signal dadrL_N17193_FROM : STD_LOGIC; + signal dadrL_N17193_GROM : STD_LOGIC; + signal dadrL_N2355_FROM : STD_LOGIC; + signal dadrL_N2355_GROM : STD_LOGIC; + signal dadrL_N17122_FROM : STD_LOGIC; + signal dadrL_N17122_GROM : STD_LOGIC; + signal dadrL_N2283_FROM : STD_LOGIC; + signal dadrL_N2283_GROM : STD_LOGIC; + signal dadrL_N3846_FROM : STD_LOGIC; + signal dadrL_N3846_GROM : STD_LOGIC; + signal dadrL_N7182_FROM : STD_LOGIC; + signal dadrL_N7182_GROM : STD_LOGIC; + signal dadrL_N3775_FROM : STD_LOGIC; + signal dadrL_N3775_GROM : STD_LOGIC; + signal dadrL_N11301_FROM : STD_LOGIC; + signal dadrL_N11301_GROM : STD_LOGIC; + signal dadrL_N7821_FROM : STD_LOGIC; + signal dadrL_N7821_GROM : STD_LOGIC; + signal dadrL_N7111_FROM : STD_LOGIC; + signal dadrL_N7111_GROM : STD_LOGIC; + signal dadrL_N11230_FROM : STD_LOGIC; + signal dadrL_N11230_GROM : STD_LOGIC; + signal dadrL_N7751_FROM : STD_LOGIC; + signal dadrL_N7751_GROM : STD_LOGIC; + signal dadrL_N17336_FROM : STD_LOGIC; + signal dadrL_N17336_GROM : STD_LOGIC; + signal dadrL_N2497_FROM : STD_LOGIC; + signal dadrL_N2497_GROM : STD_LOGIC; + signal dadrL_N17265_FROM : STD_LOGIC; + signal dadrL_N17265_GROM : STD_LOGIC; + signal dadrL_N2426_FROM : STD_LOGIC; + signal dadrL_N2426_GROM : STD_LOGIC; + signal dadrL_N3988_FROM : STD_LOGIC; + signal dadrL_N3988_GROM : STD_LOGIC; + signal dadrL_N7325_FROM : STD_LOGIC; + signal dadrL_N7325_GROM : STD_LOGIC; + signal dadrL_N3917_FROM : STD_LOGIC; + signal dadrL_N3917_GROM : STD_LOGIC; + signal dadrL_N7963_FROM : STD_LOGIC; + signal dadrL_N7963_GROM : STD_LOGIC; + signal dadrL_N7253_FROM : STD_LOGIC; + signal dadrL_N7253_GROM : STD_LOGIC; + signal dadrL_N7892_FROM : STD_LOGIC; + signal dadrL_N7892_GROM : STD_LOGIC; + signal dadrL_N17478_FROM : STD_LOGIC; + signal dadrL_N17478_GROM : STD_LOGIC; + signal dadrL_N2639_FROM : STD_LOGIC; + signal dadrL_N2639_GROM : STD_LOGIC; + signal dadrL_N17407_FROM : STD_LOGIC; + signal dadrL_N17407_GROM : STD_LOGIC; + signal dadrL_N2568_FROM : STD_LOGIC; + signal dadrL_N2568_GROM : STD_LOGIC; + signal dadrL_N4130_FROM : STD_LOGIC; + signal dadrL_N4130_GROM : STD_LOGIC; + signal dadrL_N7467_FROM : STD_LOGIC; + signal dadrL_N7467_GROM : STD_LOGIC; + signal dadrL_N651_FROM : STD_LOGIC; + signal dadrL_N651_GROM : STD_LOGIC; + signal dadrL_N4059_FROM : STD_LOGIC; + signal dadrL_N4059_GROM : STD_LOGIC; + signal dadrL_N8106_FROM : STD_LOGIC; + signal dadrL_N8106_GROM : STD_LOGIC; + signal dadrL_N7396_FROM : STD_LOGIC; + signal dadrL_N7396_GROM : STD_LOGIC; + signal dadrL_N580_FROM : STD_LOGIC; + signal dadrL_N580_GROM : STD_LOGIC; + signal dadrL_N8035_FROM : STD_LOGIC; + signal dadrL_N8035_GROM : STD_LOGIC; + signal dadrL_N17620_FROM : STD_LOGIC; + signal dadrL_N17620_GROM : STD_LOGIC; + signal dadrL_N2781_FROM : STD_LOGIC; + signal dadrL_N2781_GROM : STD_LOGIC; + signal dadrL_N17549_FROM : STD_LOGIC; + signal dadrL_N17549_GROM : STD_LOGIC; + signal dadrL_N2710_FROM : STD_LOGIC; + signal dadrL_N2710_GROM : STD_LOGIC; + signal dadrL_N4271_FROM : STD_LOGIC; + signal dadrL_N4271_GROM : STD_LOGIC; + signal dadrL_N792_FROM : STD_LOGIC; + signal dadrL_N792_GROM : STD_LOGIC; + signal dadrL_N4201_FROM : STD_LOGIC; + signal dadrL_N4201_GROM : STD_LOGIC; + signal dadrL_N7538_FROM : STD_LOGIC; + signal dadrL_N7538_GROM : STD_LOGIC; + signal dadrL_N8248_FROM : STD_LOGIC; + signal dadrL_N8248_GROM : STD_LOGIC; + signal dadrL_N721_FROM : STD_LOGIC; + signal dadrL_N721_GROM : STD_LOGIC; + signal dadrL_N8177_FROM : STD_LOGIC; + signal dadrL_N8177_GROM : STD_LOGIC; + signal dadrL_N17761_FROM : STD_LOGIC; + signal dadrL_N17761_GROM : STD_LOGIC; + signal dadrL_N17691_FROM : STD_LOGIC; + signal dadrL_N17691_GROM : STD_LOGIC; + signal dadrL_N2851_FROM : STD_LOGIC; + signal dadrL_N2851_GROM : STD_LOGIC; + signal dadrL_N935_FROM : STD_LOGIC; + signal dadrL_N935_GROM : STD_LOGIC; + signal dadrL_N8390_FROM : STD_LOGIC; + signal dadrL_N8390_GROM : STD_LOGIC; + signal dadrL_N863_FROM : STD_LOGIC; + signal dadrL_N863_GROM : STD_LOGIC; + signal dadrL_N8319_FROM : STD_LOGIC; + signal dadrL_N8319_GROM : STD_LOGIC; + signal dadrL_N17903_FROM : STD_LOGIC; + signal dadrL_N17903_GROM : STD_LOGIC; + signal dadrL_N17832_FROM : STD_LOGIC; + signal dadrL_N17832_GROM : STD_LOGIC; + signal dadrL_N1077_FROM : STD_LOGIC; + signal dadrL_N1077_GROM : STD_LOGIC; + signal dadrL_N8531_FROM : STD_LOGIC; + signal dadrL_N8531_GROM : STD_LOGIC; + signal dadrL_N1006_FROM : STD_LOGIC; + signal dadrL_N1006_GROM : STD_LOGIC; + signal dadrL_N8461_FROM : STD_LOGIC; + signal dadrL_N8461_GROM : STD_LOGIC; + signal dadrL_N18046_FROM : STD_LOGIC; + signal dadrL_N18046_GROM : STD_LOGIC; + signal dadrL_N17975_FROM : STD_LOGIC; + signal dadrL_N17975_GROM : STD_LOGIC; + signal dadrL_N1219_FROM : STD_LOGIC; + signal dadrL_N1219_GROM : STD_LOGIC; + signal dadrL_N1148_FROM : STD_LOGIC; + signal dadrL_N1148_GROM : STD_LOGIC; + signal dadrL_N8673_FROM : STD_LOGIC; + signal dadrL_N8673_GROM : STD_LOGIC; + signal dadrL_N8602_FROM : STD_LOGIC; + signal dadrL_N8602_GROM : STD_LOGIC; + signal dadrL_N18188_FROM : STD_LOGIC; + signal dadrL_N18188_GROM : STD_LOGIC; + signal dadrL_N14709_FROM : STD_LOGIC; + signal dadrL_N14709_GROM : STD_LOGIC; + signal cs_1_OBUF_GROM : STD_LOGIC; + signal cs_2_OBUF_GROM : STD_LOGIC; + signal cs_3_OBUF_GROM : STD_LOGIC; + signal cs_4_OBUF_GROM : STD_LOGIC; + signal cs_5_OBUF_GROM : STD_LOGIC; + signal cs_6_OBUF_GROM : STD_LOGIC; + signal cs_7_OBUF_GROM : STD_LOGIC; + signal reg_select_FROM : STD_LOGIC; + signal reg_select_GROM : STD_LOGIC; + signal cs_89_OBUF_GROM : STD_LOGIC; + signal cs_90_OBUF_GROM : STD_LOGIC; + signal cs_99_OBUF_GROM : STD_LOGIC; + signal cs_91_OBUF_GROM : STD_LOGIC; + signal cs_180_OBUF_GROM : STD_LOGIC; + signal cs_100_OBUF_GROM : STD_LOGIC; + signal cs_92_OBUF_GROM : STD_LOGIC; + signal cs_189_OBUF_GROM : STD_LOGIC; + signal cs_181_OBUF_GROM : STD_LOGIC; + signal cs_109_OBUF_GROM : STD_LOGIC; + signal cs_101_OBUF_GROM : STD_LOGIC; + signal cs_93_OBUF_GROM : STD_LOGIC; + signal cs_190_OBUF_GROM : STD_LOGIC; + signal cs_182_OBUF_GROM : STD_LOGIC; + signal cs_110_OBUF_GROM : STD_LOGIC; + signal cs_102_OBUF_GROM : STD_LOGIC; + signal cs_94_OBUF_GROM : STD_LOGIC; + signal cs_108_OBUF_GROM : STD_LOGIC; + signal cs_199_OBUF_GROM : STD_LOGIC; + signal cs_191_OBUF_GROM : STD_LOGIC; + signal cs_183_OBUF_GROM : STD_LOGIC; + signal cs_119_OBUF_GROM : STD_LOGIC; + signal cs_111_OBUF_GROM : STD_LOGIC; + signal cs_103_OBUF_GROM : STD_LOGIC; + signal cs_95_OBUF_GROM : STD_LOGIC; + signal cs_117_OBUF_GROM : STD_LOGIC; + signal cs_200_OBUF_GROM : STD_LOGIC; + signal cs_192_OBUF_GROM : STD_LOGIC; + signal cs_184_OBUF_GROM : STD_LOGIC; + signal cs_120_OBUF_GROM : STD_LOGIC; + signal cs_112_OBUF_GROM : STD_LOGIC; + signal cs_104_OBUF_GROM : STD_LOGIC; + signal cs_96_OBUF_GROM : STD_LOGIC; + signal cs_126_OBUF_GROM : STD_LOGIC; + signal cs_118_OBUF_GROM : STD_LOGIC; + signal cs_209_OBUF_GROM : STD_LOGIC; + signal cs_201_OBUF_GROM : STD_LOGIC; + signal cs_193_OBUF_GROM : STD_LOGIC; + signal cs_185_OBUF_GROM : STD_LOGIC; + signal cs_129_OBUF_GROM : STD_LOGIC; + signal cs_121_OBUF_GROM : STD_LOGIC; + signal cs_113_OBUF_GROM : STD_LOGIC; + signal cs_105_OBUF_GROM : STD_LOGIC; + signal cs_97_OBUF_GROM : STD_LOGIC; + signal cs_135_OBUF_GROM : STD_LOGIC; + signal cs_127_OBUF_GROM : STD_LOGIC; + signal cs_210_OBUF_GROM : STD_LOGIC; + signal cs_202_OBUF_GROM : STD_LOGIC; + signal cs_194_OBUF_GROM : STD_LOGIC; + signal cs_186_OBUF_GROM : STD_LOGIC; + signal cs_130_OBUF_GROM : STD_LOGIC; + signal cs_77_ENABLE : STD_LOGIC; + signal cs_77_TORGTS : STD_LOGIC; + signal cs_77_OUTMUX : STD_LOGIC; + signal cs_85_ENABLE : STD_LOGIC; + signal cs_85_TORGTS : STD_LOGIC; + signal cs_85_OUTMUX : STD_LOGIC; + signal cs_93_ENABLE : STD_LOGIC; + signal cs_93_TORGTS : STD_LOGIC; + signal cs_93_OUTMUX : STD_LOGIC; + signal cs_78_ENABLE : STD_LOGIC; + signal cs_78_TORGTS : STD_LOGIC; + signal cs_78_OUTMUX : STD_LOGIC; + signal cs_86_ENABLE : STD_LOGIC; + signal cs_86_TORGTS : STD_LOGIC; + signal cs_86_OUTMUX : STD_LOGIC; + signal cs_94_ENABLE : STD_LOGIC; + signal cs_94_TORGTS : STD_LOGIC; + signal cs_94_OUTMUX : STD_LOGIC; + signal cs_79_ENABLE : STD_LOGIC; + signal cs_79_TORGTS : STD_LOGIC; + signal cs_79_OUTMUX : STD_LOGIC; + signal cs_87_ENABLE : STD_LOGIC; + signal cs_87_TORGTS : STD_LOGIC; + signal cs_87_OUTMUX : STD_LOGIC; + signal cs_95_ENABLE : STD_LOGIC; + signal cs_95_TORGTS : STD_LOGIC; + signal cs_95_OUTMUX : STD_LOGIC; + signal cs_88_ENABLE : STD_LOGIC; + signal cs_88_TORGTS : STD_LOGIC; + signal cs_88_OUTMUX : STD_LOGIC; + signal cs_96_ENABLE : STD_LOGIC; + signal cs_96_TORGTS : STD_LOGIC; + signal cs_96_OUTMUX : STD_LOGIC; + signal cs_89_ENABLE : STD_LOGIC; + signal cs_89_TORGTS : STD_LOGIC; + signal cs_89_OUTMUX : STD_LOGIC; + signal cs_97_ENABLE : STD_LOGIC; + signal cs_97_TORGTS : STD_LOGIC; + signal cs_97_OUTMUX : STD_LOGIC; + signal cs_98_ENABLE : STD_LOGIC; + signal cs_98_TORGTS : STD_LOGIC; + signal cs_98_OUTMUX : STD_LOGIC; + signal cs_99_ENABLE : STD_LOGIC; + signal cs_99_TORGTS : STD_LOGIC; + signal cs_99_OUTMUX : STD_LOGIC; + signal cs_0_ENABLE : STD_LOGIC; + signal cs_0_TORGTS : STD_LOGIC; + signal cs_0_OUTMUX : STD_LOGIC; + signal cs_1_ENABLE : STD_LOGIC; + signal cs_1_TORGTS : STD_LOGIC; + signal cs_1_OUTMUX : STD_LOGIC; + signal cs_2_ENABLE : STD_LOGIC; + signal cs_2_TORGTS : STD_LOGIC; + signal cs_2_OUTMUX : STD_LOGIC; + signal cs_3_ENABLE : STD_LOGIC; + signal cs_3_TORGTS : STD_LOGIC; + signal cs_3_OUTMUX : STD_LOGIC; + signal cs_4_ENABLE : STD_LOGIC; + signal cs_4_TORGTS : STD_LOGIC; + signal cs_4_OUTMUX : STD_LOGIC; + signal cs_5_ENABLE : STD_LOGIC; + signal cs_5_TORGTS : STD_LOGIC; + signal cs_5_OUTMUX : STD_LOGIC; + signal cs_6_ENABLE : STD_LOGIC; + signal cs_6_TORGTS : STD_LOGIC; + signal cs_6_OUTMUX : STD_LOGIC; + signal cs_7_ENABLE : STD_LOGIC; + signal cs_7_TORGTS : STD_LOGIC; + signal cs_7_OUTMUX : STD_LOGIC; + signal cs_8_ENABLE : STD_LOGIC; + signal cs_8_TORGTS : STD_LOGIC; + signal cs_8_OUTMUX : STD_LOGIC; + signal cs_9_ENABLE : STD_LOGIC; + signal cs_9_TORGTS : STD_LOGIC; + signal cs_9_OUTMUX : STD_LOGIC; + signal CHOICE45_FROM : STD_LOGIC; + signal CHOICE45_GROM : STD_LOGIC; + signal rw_OBUF_FROM : STD_LOGIC; + signal rw_OBUF_GROM : STD_LOGIC; + signal cs_122_OBUF_GROM : STD_LOGIC; + signal cs_114_OBUF_GROM : STD_LOGIC; + signal cs_106_OBUF_GROM : STD_LOGIC; + signal cs_98_OBUF_GROM : STD_LOGIC; + signal cs_208_OBUF_GROM : STD_LOGIC; + signal cs_144_OBUF_GROM : STD_LOGIC; + signal cs_136_OBUF_GROM : STD_LOGIC; + signal cs_128_OBUF_GROM : STD_LOGIC; + signal cs_219_OBUF_GROM : STD_LOGIC; + signal cs_211_OBUF_GROM : STD_LOGIC; + signal cs_203_OBUF_GROM : STD_LOGIC; + signal cs_195_OBUF_GROM : STD_LOGIC; + signal cs_187_OBUF_GROM : STD_LOGIC; + signal cs_139_OBUF_GROM : STD_LOGIC; + signal cs_131_OBUF_GROM : STD_LOGIC; + signal cs_123_OBUF_GROM : STD_LOGIC; + signal cs_115_OBUF_GROM : STD_LOGIC; + signal cs_107_OBUF_GROM : STD_LOGIC; + signal cs_217_OBUF_GROM : STD_LOGIC; + signal cs_153_OBUF_GROM : STD_LOGIC; + signal cs_145_OBUF_GROM : STD_LOGIC; + signal cs_137_OBUF_GROM : STD_LOGIC; + signal cs_220_OBUF_GROM : STD_LOGIC; + signal cs_212_OBUF_GROM : STD_LOGIC; + signal cs_204_OBUF_GROM : STD_LOGIC; + signal cs_196_OBUF_GROM : STD_LOGIC; + signal cs_188_OBUF_GROM : STD_LOGIC; + signal cs_140_OBUF_GROM : STD_LOGIC; + signal cs_132_OBUF_GROM : STD_LOGIC; + signal cs_124_OBUF_GROM : STD_LOGIC; + signal cs_116_OBUF_GROM : STD_LOGIC; + signal cs_226_OBUF_GROM : STD_LOGIC; + signal cs_218_OBUF_GROM : STD_LOGIC; + signal cs_162_OBUF_GROM : STD_LOGIC; + signal cs_154_OBUF_GROM : STD_LOGIC; + signal cs_146_OBUF_GROM : STD_LOGIC; + signal cs_138_OBUF_GROM : STD_LOGIC; + signal cs_229_OBUF_GROM : STD_LOGIC; + signal cs_221_OBUF_GROM : STD_LOGIC; + signal cs_213_OBUF_GROM : STD_LOGIC; + signal cs_205_OBUF_GROM : STD_LOGIC; + signal cs_197_OBUF_GROM : STD_LOGIC; + signal cs_149_OBUF_GROM : STD_LOGIC; + signal cs_141_OBUF_GROM : STD_LOGIC; + signal cs_133_OBUF_GROM : STD_LOGIC; + signal cs_125_OBUF_GROM : STD_LOGIC; + signal cs_235_OBUF_GROM : STD_LOGIC; + signal cs_227_OBUF_GROM : STD_LOGIC; + signal cs_171_OBUF_GROM : STD_LOGIC; + signal cs_163_OBUF_GROM : STD_LOGIC; + signal cs_155_OBUF_GROM : STD_LOGIC; + signal cs_147_OBUF_GROM : STD_LOGIC; + signal cs_230_OBUF_GROM : STD_LOGIC; + signal cs_222_OBUF_GROM : STD_LOGIC; + signal cs_214_OBUF_GROM : STD_LOGIC; + signal cs_206_OBUF_GROM : STD_LOGIC; + signal cs_198_OBUF_GROM : STD_LOGIC; + signal cs_150_OBUF_GROM : STD_LOGIC; + signal cs_142_OBUF_GROM : STD_LOGIC; + signal cs_134_OBUF_GROM : STD_LOGIC; + signal cs_244_OBUF_GROM : STD_LOGIC; + signal cs_236_OBUF_GROM : STD_LOGIC; + signal cs_228_OBUF_GROM : STD_LOGIC; + signal cs_172_OBUF_GROM : STD_LOGIC; + signal cs_164_OBUF_GROM : STD_LOGIC; + signal cs_156_OBUF_GROM : STD_LOGIC; + signal cs_148_OBUF_GROM : STD_LOGIC; + signal cs_239_OBUF_GROM : STD_LOGIC; + signal cs_231_OBUF_GROM : STD_LOGIC; + signal cs_223_OBUF_GROM : STD_LOGIC; + signal cs_215_OBUF_GROM : STD_LOGIC; + signal cs_207_OBUF_GROM : STD_LOGIC; + signal cs_159_OBUF_GROM : STD_LOGIC; + signal cs_151_OBUF_GROM : STD_LOGIC; + signal cs_143_OBUF_GROM : STD_LOGIC; + signal cs_253_OBUF_GROM : STD_LOGIC; + signal cs_245_OBUF_GROM : STD_LOGIC; + signal cs_237_OBUF_GROM : STD_LOGIC; + signal cs_173_OBUF_GROM : STD_LOGIC; + signal cs_165_OBUF_GROM : STD_LOGIC; + signal cs_157_OBUF_GROM : STD_LOGIC; + signal cs_240_OBUF_GROM : STD_LOGIC; + signal cs_232_OBUF_GROM : STD_LOGIC; + signal cs_224_OBUF_GROM : STD_LOGIC; + signal cs_216_OBUF_GROM : STD_LOGIC; + signal cs_160_OBUF_GROM : STD_LOGIC; + signal cs_152_OBUF_GROM : STD_LOGIC; + signal cs_254_OBUF_GROM : STD_LOGIC; + signal cs_246_OBUF_GROM : STD_LOGIC; + signal cs_238_OBUF_GROM : STD_LOGIC; + signal cs_174_OBUF_GROM : STD_LOGIC; + signal cs_166_OBUF_GROM : STD_LOGIC; + signal cs_158_OBUF_GROM : STD_LOGIC; + signal cs_9_OBUF_GROM : STD_LOGIC; + signal cs_249_OBUF_GROM : STD_LOGIC; + signal cs_241_OBUF_GROM : STD_LOGIC; + signal cs_233_OBUF_GROM : STD_LOGIC; + signal cs_225_OBUF_GROM : STD_LOGIC; + signal cs_169_OBUF_GROM : STD_LOGIC; + signal cs_161_OBUF_GROM : STD_LOGIC; + signal cs_255_OBUF_GROM : STD_LOGIC; + signal cs_247_OBUF_GROM : STD_LOGIC; + signal cs_175_OBUF_GROM : STD_LOGIC; + signal cs_167_OBUF_GROM : STD_LOGIC; + signal cs_10_OBUF_GROM : STD_LOGIC; + signal cs_250_OBUF_GROM : STD_LOGIC; + signal cs_242_OBUF_GROM : STD_LOGIC; + signal cs_234_OBUF_GROM : STD_LOGIC; + signal cs_170_OBUF_GROM : STD_LOGIC; + signal cs_8_OBUF_GROM : STD_LOGIC; + signal cs_248_OBUF_GROM : STD_LOGIC; + signal cs_176_OBUF_GROM : STD_LOGIC; + signal cs_168_OBUF_GROM : STD_LOGIC; + signal cs_19_OBUF_GROM : STD_LOGIC; + signal cs_11_OBUF_GROM : STD_LOGIC; + signal cs_251_OBUF_GROM : STD_LOGIC; + signal cs_243_OBUF_GROM : STD_LOGIC; + signal cs_179_OBUF_GROM : STD_LOGIC; + signal cs_17_OBUF_GROM : STD_LOGIC; + signal cs_177_OBUF_GROM : STD_LOGIC; + signal cs_20_OBUF_GROM : STD_LOGIC; + signal cs_12_OBUF_GROM : STD_LOGIC; + signal cs_252_OBUF_GROM : STD_LOGIC; + signal cs_26_OBUF_GROM : STD_LOGIC; + signal cs_18_OBUF_GROM : STD_LOGIC; + signal cs_178_OBUF_GROM : STD_LOGIC; + signal cs_29_OBUF_GROM : STD_LOGIC; + signal cs_21_OBUF_GROM : STD_LOGIC; + signal cs_13_OBUF_GROM : STD_LOGIC; + signal cs_35_OBUF_GROM : STD_LOGIC; + signal cs_27_OBUF_GROM : STD_LOGIC; + signal cs_30_OBUF_GROM : STD_LOGIC; + signal cs_22_OBUF_GROM : STD_LOGIC; + signal cs_14_OBUF_GROM : STD_LOGIC; + signal cs_44_OBUF_GROM : STD_LOGIC; + signal cs_36_OBUF_GROM : STD_LOGIC; + signal cs_28_OBUF_GROM : STD_LOGIC; + signal cs_39_OBUF_GROM : STD_LOGIC; + signal cs_31_OBUF_GROM : STD_LOGIC; + signal cs_23_OBUF_GROM : STD_LOGIC; + signal cs_15_OBUF_GROM : STD_LOGIC; + signal cs_53_OBUF_GROM : STD_LOGIC; + signal cs_45_OBUF_GROM : STD_LOGIC; + signal cs_37_OBUF_GROM : STD_LOGIC; + signal cs_40_OBUF_GROM : STD_LOGIC; + signal cs_32_OBUF_GROM : STD_LOGIC; + signal cs_24_OBUF_GROM : STD_LOGIC; + signal cs_16_OBUF_GROM : STD_LOGIC; + signal cs_62_OBUF_GROM : STD_LOGIC; + signal cs_54_OBUF_GROM : STD_LOGIC; + signal cs_46_OBUF_GROM : STD_LOGIC; + signal cs_38_OBUF_GROM : STD_LOGIC; + signal cs_49_OBUF_GROM : STD_LOGIC; + signal cs_41_OBUF_GROM : STD_LOGIC; + signal cs_33_OBUF_GROM : STD_LOGIC; + signal cs_25_OBUF_GROM : STD_LOGIC; + signal cs_71_OBUF_GROM : STD_LOGIC; + signal cs_63_OBUF_GROM : STD_LOGIC; + signal cs_55_OBUF_GROM : STD_LOGIC; + signal cs_47_OBUF_GROM : STD_LOGIC; + signal cs_50_OBUF_GROM : STD_LOGIC; + signal cs_42_OBUF_GROM : STD_LOGIC; + signal cs_34_OBUF_GROM : STD_LOGIC; + signal cs_80_OBUF_GROM : STD_LOGIC; + signal cs_72_OBUF_GROM : STD_LOGIC; + signal cs_64_OBUF_GROM : STD_LOGIC; + signal cs_56_OBUF_GROM : STD_LOGIC; + signal cs_48_OBUF_GROM : STD_LOGIC; + signal cs_59_OBUF_GROM : STD_LOGIC; + signal cs_51_OBUF_GROM : STD_LOGIC; + signal cs_43_OBUF_GROM : STD_LOGIC; + signal cs_81_OBUF_GROM : STD_LOGIC; + signal cs_73_OBUF_GROM : STD_LOGIC; + signal cs_65_OBUF_GROM : STD_LOGIC; + signal cs_57_OBUF_GROM : STD_LOGIC; + signal cs_60_OBUF_GROM : STD_LOGIC; + signal cs_52_OBUF_GROM : STD_LOGIC; + signal cs_82_OBUF_GROM : STD_LOGIC; + signal cs_74_OBUF_GROM : STD_LOGIC; + signal cs_66_OBUF_GROM : STD_LOGIC; + signal cs_58_OBUF_GROM : STD_LOGIC; + signal cs_69_OBUF_GROM : STD_LOGIC; + signal cs_61_OBUF_GROM : STD_LOGIC; + signal cs_83_OBUF_GROM : STD_LOGIC; + signal cs_75_OBUF_GROM : STD_LOGIC; + signal cs_67_OBUF_GROM : STD_LOGIC; + signal cs_70_OBUF_GROM : STD_LOGIC; + signal cs_84_OBUF_GROM : STD_LOGIC; + signal cs_76_OBUF_GROM : STD_LOGIC; + signal cs_68_OBUF_GROM : STD_LOGIC; + signal cs_79_OBUF_GROM : STD_LOGIC; + signal cs_85_OBUF_GROM : STD_LOGIC; + signal cs_77_OBUF_GROM : STD_LOGIC; + signal cs_86_OBUF_GROM : STD_LOGIC; + signal cs_78_OBUF_GROM : STD_LOGIC; + signal cs_87_OBUF_GROM : STD_LOGIC; + signal cs_88_OBUF_GROM : STD_LOGIC; + signal rw_ENABLE : STD_LOGIC; + signal rw_TORGTS : STD_LOGIC; + signal rw_OUTMUX : STD_LOGIC; + signal adr_bus_0_IBUF_0 : STD_LOGIC; + signal adr_bus_1_IBUF_1 : STD_LOGIC; + signal adr_bus_2_IBUF_2 : STD_LOGIC; + signal adr_bus_3_IBUF_3 : STD_LOGIC; + signal adr_bus_4_IBUF_4 : STD_LOGIC; + signal adr_bus_5_IBUF_5 : STD_LOGIC; + signal adr_bus_6_IBUF_6 : STD_LOGIC; + signal adr_bus_7_IBUF_7 : STD_LOGIC; + signal adr_bus_8_IBUF_8 : STD_LOGIC; + signal adr_bus_9_IBUF_9 : STD_LOGIC; + signal AEN_IBUF_10 : STD_LOGIC; + signal IOR_IBUF_11 : STD_LOGIC; + signal IOW_IBUF_12 : STD_LOGIC; + signal cs_100_ENABLE : STD_LOGIC; + signal cs_100_TORGTS : STD_LOGIC; + signal cs_100_OUTMUX : STD_LOGIC; + signal cs_101_ENABLE : STD_LOGIC; + signal cs_101_TORGTS : STD_LOGIC; + signal cs_101_OUTMUX : STD_LOGIC; + signal cs_102_ENABLE : STD_LOGIC; + signal cs_102_TORGTS : STD_LOGIC; + signal cs_102_OUTMUX : STD_LOGIC; + signal cs_110_ENABLE : STD_LOGIC; + signal cs_110_TORGTS : STD_LOGIC; + signal cs_110_OUTMUX : STD_LOGIC; + signal cs_103_ENABLE : STD_LOGIC; + signal cs_103_TORGTS : STD_LOGIC; + signal cs_103_OUTMUX : STD_LOGIC; + signal cs_111_ENABLE : STD_LOGIC; + signal cs_111_TORGTS : STD_LOGIC; + signal cs_111_OUTMUX : STD_LOGIC; + signal cs_104_ENABLE : STD_LOGIC; + signal cs_104_TORGTS : STD_LOGIC; + signal cs_104_OUTMUX : STD_LOGIC; + signal cs_112_ENABLE : STD_LOGIC; + signal cs_112_TORGTS : STD_LOGIC; + signal cs_112_OUTMUX : STD_LOGIC; + signal cs_120_ENABLE : STD_LOGIC; + signal cs_120_TORGTS : STD_LOGIC; + signal cs_120_OUTMUX : STD_LOGIC; + signal cs_200_ENABLE : STD_LOGIC; + signal cs_200_TORGTS : STD_LOGIC; + signal cs_200_OUTMUX : STD_LOGIC; + signal cs_105_ENABLE : STD_LOGIC; + signal cs_105_TORGTS : STD_LOGIC; + signal cs_105_OUTMUX : STD_LOGIC; + signal cs_113_ENABLE : STD_LOGIC; + signal cs_113_TORGTS : STD_LOGIC; + signal cs_113_OUTMUX : STD_LOGIC; + signal cs_121_ENABLE : STD_LOGIC; + signal cs_121_TORGTS : STD_LOGIC; + signal cs_121_OUTMUX : STD_LOGIC; + signal cs_201_ENABLE : STD_LOGIC; + signal cs_201_TORGTS : STD_LOGIC; + signal cs_201_OUTMUX : STD_LOGIC; + signal cs_106_ENABLE : STD_LOGIC; + signal cs_106_TORGTS : STD_LOGIC; + signal cs_106_OUTMUX : STD_LOGIC; + signal cs_114_ENABLE : STD_LOGIC; + signal cs_114_TORGTS : STD_LOGIC; + signal cs_114_OUTMUX : STD_LOGIC; + signal cs_122_ENABLE : STD_LOGIC; + signal cs_122_TORGTS : STD_LOGIC; + signal cs_122_OUTMUX : STD_LOGIC; + signal cs_130_ENABLE : STD_LOGIC; + signal cs_130_TORGTS : STD_LOGIC; + signal cs_130_OUTMUX : STD_LOGIC; + signal cs_202_ENABLE : STD_LOGIC; + signal cs_202_TORGTS : STD_LOGIC; + signal cs_202_OUTMUX : STD_LOGIC; + signal cs_210_ENABLE : STD_LOGIC; + signal cs_210_TORGTS : STD_LOGIC; + signal cs_210_OUTMUX : STD_LOGIC; + signal cs_107_ENABLE : STD_LOGIC; + signal cs_107_TORGTS : STD_LOGIC; + signal cs_107_OUTMUX : STD_LOGIC; + signal cs_115_ENABLE : STD_LOGIC; + signal cs_115_TORGTS : STD_LOGIC; + signal cs_115_OUTMUX : STD_LOGIC; + signal cs_123_ENABLE : STD_LOGIC; + signal cs_123_TORGTS : STD_LOGIC; + signal cs_123_OUTMUX : STD_LOGIC; + signal cs_131_ENABLE : STD_LOGIC; + signal cs_131_TORGTS : STD_LOGIC; + signal cs_131_OUTMUX : STD_LOGIC; + signal cs_203_ENABLE : STD_LOGIC; + signal cs_203_TORGTS : STD_LOGIC; + signal cs_203_OUTMUX : STD_LOGIC; + signal cs_211_ENABLE : STD_LOGIC; + signal cs_211_TORGTS : STD_LOGIC; + signal cs_211_OUTMUX : STD_LOGIC; + signal cs_108_ENABLE : STD_LOGIC; + signal cs_108_TORGTS : STD_LOGIC; + signal cs_108_OUTMUX : STD_LOGIC; + signal cs_116_ENABLE : STD_LOGIC; + signal cs_116_TORGTS : STD_LOGIC; + signal cs_116_OUTMUX : STD_LOGIC; + signal cs_124_ENABLE : STD_LOGIC; + signal cs_124_TORGTS : STD_LOGIC; + signal cs_124_OUTMUX : STD_LOGIC; + signal cs_132_ENABLE : STD_LOGIC; + signal cs_132_TORGTS : STD_LOGIC; + signal cs_132_OUTMUX : STD_LOGIC; + signal cs_140_ENABLE : STD_LOGIC; + signal cs_140_TORGTS : STD_LOGIC; + signal cs_140_OUTMUX : STD_LOGIC; + signal cs_204_ENABLE : STD_LOGIC; + signal cs_204_TORGTS : STD_LOGIC; + signal cs_204_OUTMUX : STD_LOGIC; + signal cs_212_ENABLE : STD_LOGIC; + signal cs_212_TORGTS : STD_LOGIC; + signal cs_212_OUTMUX : STD_LOGIC; + signal cs_220_ENABLE : STD_LOGIC; + signal cs_220_TORGTS : STD_LOGIC; + signal cs_220_OUTMUX : STD_LOGIC; + signal cs_109_ENABLE : STD_LOGIC; + signal cs_109_TORGTS : STD_LOGIC; + signal cs_109_OUTMUX : STD_LOGIC; + signal cs_117_ENABLE : STD_LOGIC; + signal cs_117_TORGTS : STD_LOGIC; + signal cs_117_OUTMUX : STD_LOGIC; + signal cs_125_ENABLE : STD_LOGIC; + signal cs_125_TORGTS : STD_LOGIC; + signal cs_125_OUTMUX : STD_LOGIC; + signal cs_133_ENABLE : STD_LOGIC; + signal cs_133_TORGTS : STD_LOGIC; + signal cs_133_OUTMUX : STD_LOGIC; + signal cs_141_ENABLE : STD_LOGIC; + signal cs_141_TORGTS : STD_LOGIC; + signal cs_141_OUTMUX : STD_LOGIC; + signal cs_205_ENABLE : STD_LOGIC; + signal cs_205_TORGTS : STD_LOGIC; + signal cs_205_OUTMUX : STD_LOGIC; + signal cs_213_ENABLE : STD_LOGIC; + signal cs_213_TORGTS : STD_LOGIC; + signal cs_213_OUTMUX : STD_LOGIC; + signal cs_221_ENABLE : STD_LOGIC; + signal cs_221_TORGTS : STD_LOGIC; + signal cs_221_OUTMUX : STD_LOGIC; + signal cs_118_ENABLE : STD_LOGIC; + signal cs_118_TORGTS : STD_LOGIC; + signal cs_118_OUTMUX : STD_LOGIC; + signal cs_126_ENABLE : STD_LOGIC; + signal cs_126_TORGTS : STD_LOGIC; + signal cs_126_OUTMUX : STD_LOGIC; + signal cs_134_ENABLE : STD_LOGIC; + signal cs_134_TORGTS : STD_LOGIC; + signal cs_134_OUTMUX : STD_LOGIC; + signal cs_142_ENABLE : STD_LOGIC; + signal cs_142_TORGTS : STD_LOGIC; + signal cs_142_OUTMUX : STD_LOGIC; + signal cs_150_ENABLE : STD_LOGIC; + signal cs_150_TORGTS : STD_LOGIC; + signal cs_150_OUTMUX : STD_LOGIC; + signal cs_206_ENABLE : STD_LOGIC; + signal cs_206_TORGTS : STD_LOGIC; + signal cs_206_OUTMUX : STD_LOGIC; + signal cs_214_ENABLE : STD_LOGIC; + signal cs_214_TORGTS : STD_LOGIC; + signal cs_214_OUTMUX : STD_LOGIC; + signal cs_222_ENABLE : STD_LOGIC; + signal cs_222_TORGTS : STD_LOGIC; + signal cs_222_OUTMUX : STD_LOGIC; + signal cs_230_ENABLE : STD_LOGIC; + signal cs_230_TORGTS : STD_LOGIC; + signal cs_230_OUTMUX : STD_LOGIC; + signal cs_119_ENABLE : STD_LOGIC; + signal cs_119_TORGTS : STD_LOGIC; + signal cs_119_OUTMUX : STD_LOGIC; + signal cs_127_ENABLE : STD_LOGIC; + signal cs_127_TORGTS : STD_LOGIC; + signal cs_127_OUTMUX : STD_LOGIC; + signal cs_135_ENABLE : STD_LOGIC; + signal cs_135_TORGTS : STD_LOGIC; + signal cs_135_OUTMUX : STD_LOGIC; + signal cs_143_ENABLE : STD_LOGIC; + signal cs_143_TORGTS : STD_LOGIC; + signal cs_143_OUTMUX : STD_LOGIC; + signal cs_151_ENABLE : STD_LOGIC; + signal cs_151_TORGTS : STD_LOGIC; + signal cs_151_OUTMUX : STD_LOGIC; + signal cs_207_ENABLE : STD_LOGIC; + signal cs_207_TORGTS : STD_LOGIC; + signal cs_207_OUTMUX : STD_LOGIC; + signal cs_215_ENABLE : STD_LOGIC; + signal cs_215_TORGTS : STD_LOGIC; + signal cs_215_OUTMUX : STD_LOGIC; + signal cs_223_ENABLE : STD_LOGIC; + signal cs_223_TORGTS : STD_LOGIC; + signal cs_223_OUTMUX : STD_LOGIC; + signal cs_231_ENABLE : STD_LOGIC; + signal cs_231_TORGTS : STD_LOGIC; + signal cs_231_OUTMUX : STD_LOGIC; + signal cs_128_ENABLE : STD_LOGIC; + signal cs_128_TORGTS : STD_LOGIC; + signal cs_128_OUTMUX : STD_LOGIC; + signal cs_136_ENABLE : STD_LOGIC; + signal cs_136_TORGTS : STD_LOGIC; + signal cs_136_OUTMUX : STD_LOGIC; + signal cs_144_ENABLE : STD_LOGIC; + signal cs_144_TORGTS : STD_LOGIC; + signal cs_144_OUTMUX : STD_LOGIC; + signal cs_152_ENABLE : STD_LOGIC; + signal cs_152_TORGTS : STD_LOGIC; + signal cs_152_OUTMUX : STD_LOGIC; + signal cs_160_ENABLE : STD_LOGIC; + signal cs_160_TORGTS : STD_LOGIC; + signal cs_160_OUTMUX : STD_LOGIC; + signal cs_208_ENABLE : STD_LOGIC; + signal cs_208_TORGTS : STD_LOGIC; + signal cs_208_OUTMUX : STD_LOGIC; + signal cs_216_ENABLE : STD_LOGIC; + signal cs_216_TORGTS : STD_LOGIC; + signal cs_216_OUTMUX : STD_LOGIC; + signal cs_224_ENABLE : STD_LOGIC; + signal cs_224_TORGTS : STD_LOGIC; + signal cs_224_OUTMUX : STD_LOGIC; + signal cs_232_ENABLE : STD_LOGIC; + signal cs_232_TORGTS : STD_LOGIC; + signal cs_232_OUTMUX : STD_LOGIC; + signal cs_240_ENABLE : STD_LOGIC; + signal cs_240_TORGTS : STD_LOGIC; + signal cs_240_OUTMUX : STD_LOGIC; + signal cs_129_ENABLE : STD_LOGIC; + signal cs_129_TORGTS : STD_LOGIC; + signal cs_129_OUTMUX : STD_LOGIC; + signal cs_137_ENABLE : STD_LOGIC; + signal cs_137_TORGTS : STD_LOGIC; + signal cs_137_OUTMUX : STD_LOGIC; + signal cs_145_ENABLE : STD_LOGIC; + signal cs_145_TORGTS : STD_LOGIC; + signal cs_145_OUTMUX : STD_LOGIC; + signal cs_153_ENABLE : STD_LOGIC; + signal cs_153_TORGTS : STD_LOGIC; + signal cs_153_OUTMUX : STD_LOGIC; + signal cs_161_ENABLE : STD_LOGIC; + signal cs_161_TORGTS : STD_LOGIC; + signal cs_161_OUTMUX : STD_LOGIC; + signal cs_209_ENABLE : STD_LOGIC; + signal cs_209_TORGTS : STD_LOGIC; + signal cs_209_OUTMUX : STD_LOGIC; + signal cs_217_ENABLE : STD_LOGIC; + signal cs_217_TORGTS : STD_LOGIC; + signal cs_217_OUTMUX : STD_LOGIC; + signal cs_225_ENABLE : STD_LOGIC; + signal cs_225_TORGTS : STD_LOGIC; + signal cs_225_OUTMUX : STD_LOGIC; + signal cs_233_ENABLE : STD_LOGIC; + signal cs_233_TORGTS : STD_LOGIC; + signal cs_233_OUTMUX : STD_LOGIC; + signal cs_241_ENABLE : STD_LOGIC; + signal cs_241_TORGTS : STD_LOGIC; + signal cs_241_OUTMUX : STD_LOGIC; + signal cs_138_ENABLE : STD_LOGIC; + signal cs_138_TORGTS : STD_LOGIC; + signal cs_138_OUTMUX : STD_LOGIC; + signal cs_146_ENABLE : STD_LOGIC; + signal cs_146_TORGTS : STD_LOGIC; + signal cs_146_OUTMUX : STD_LOGIC; + signal cs_154_ENABLE : STD_LOGIC; + signal cs_154_TORGTS : STD_LOGIC; + signal cs_154_OUTMUX : STD_LOGIC; + signal cs_162_ENABLE : STD_LOGIC; + signal cs_162_TORGTS : STD_LOGIC; + signal cs_162_OUTMUX : STD_LOGIC; + signal cs_170_ENABLE : STD_LOGIC; + signal cs_170_TORGTS : STD_LOGIC; + signal cs_170_OUTMUX : STD_LOGIC; + signal cs_218_ENABLE : STD_LOGIC; + signal cs_218_TORGTS : STD_LOGIC; + signal cs_218_OUTMUX : STD_LOGIC; + signal cs_226_ENABLE : STD_LOGIC; + signal cs_226_TORGTS : STD_LOGIC; + signal cs_226_OUTMUX : STD_LOGIC; + signal cs_234_ENABLE : STD_LOGIC; + signal cs_234_TORGTS : STD_LOGIC; + signal cs_234_OUTMUX : STD_LOGIC; + signal cs_242_ENABLE : STD_LOGIC; + signal cs_242_TORGTS : STD_LOGIC; + signal cs_242_OUTMUX : STD_LOGIC; + signal cs_250_ENABLE : STD_LOGIC; + signal cs_250_TORGTS : STD_LOGIC; + signal cs_250_OUTMUX : STD_LOGIC; + signal cs_139_ENABLE : STD_LOGIC; + signal cs_139_TORGTS : STD_LOGIC; + signal cs_139_OUTMUX : STD_LOGIC; + signal cs_147_ENABLE : STD_LOGIC; + signal cs_147_TORGTS : STD_LOGIC; + signal cs_147_OUTMUX : STD_LOGIC; + signal cs_155_ENABLE : STD_LOGIC; + signal cs_155_TORGTS : STD_LOGIC; + signal cs_155_OUTMUX : STD_LOGIC; + signal cs_163_ENABLE : STD_LOGIC; + signal cs_163_TORGTS : STD_LOGIC; + signal cs_163_OUTMUX : STD_LOGIC; + signal cs_171_ENABLE : STD_LOGIC; + signal cs_171_TORGTS : STD_LOGIC; + signal cs_171_OUTMUX : STD_LOGIC; + signal cs_219_ENABLE : STD_LOGIC; + signal cs_219_TORGTS : STD_LOGIC; + signal cs_219_OUTMUX : STD_LOGIC; + signal cs_227_ENABLE : STD_LOGIC; + signal cs_227_TORGTS : STD_LOGIC; + signal cs_227_OUTMUX : STD_LOGIC; + signal cs_235_ENABLE : STD_LOGIC; + signal cs_235_TORGTS : STD_LOGIC; + signal cs_235_OUTMUX : STD_LOGIC; + signal cs_243_ENABLE : STD_LOGIC; + signal cs_243_TORGTS : STD_LOGIC; + signal cs_243_OUTMUX : STD_LOGIC; + signal cs_251_ENABLE : STD_LOGIC; + signal cs_251_TORGTS : STD_LOGIC; + signal cs_251_OUTMUX : STD_LOGIC; + signal cs_148_ENABLE : STD_LOGIC; + signal cs_148_TORGTS : STD_LOGIC; + signal cs_148_OUTMUX : STD_LOGIC; + signal cs_156_ENABLE : STD_LOGIC; + signal cs_156_TORGTS : STD_LOGIC; + signal cs_156_OUTMUX : STD_LOGIC; + signal cs_164_ENABLE : STD_LOGIC; + signal cs_164_TORGTS : STD_LOGIC; + signal cs_164_OUTMUX : STD_LOGIC; + signal cs_172_ENABLE : STD_LOGIC; + signal cs_172_TORGTS : STD_LOGIC; + signal cs_172_OUTMUX : STD_LOGIC; + signal cs_180_ENABLE : STD_LOGIC; + signal cs_180_TORGTS : STD_LOGIC; + signal cs_180_OUTMUX : STD_LOGIC; + signal cs_228_ENABLE : STD_LOGIC; + signal cs_228_TORGTS : STD_LOGIC; + signal cs_228_OUTMUX : STD_LOGIC; + signal cs_236_ENABLE : STD_LOGIC; + signal cs_236_TORGTS : STD_LOGIC; + signal cs_236_OUTMUX : STD_LOGIC; + signal cs_244_ENABLE : STD_LOGIC; + signal cs_244_TORGTS : STD_LOGIC; + signal cs_244_OUTMUX : STD_LOGIC; + signal cs_252_ENABLE : STD_LOGIC; + signal cs_252_TORGTS : STD_LOGIC; + signal cs_252_OUTMUX : STD_LOGIC; + signal cs_149_ENABLE : STD_LOGIC; + signal cs_149_TORGTS : STD_LOGIC; + signal cs_149_OUTMUX : STD_LOGIC; + signal cs_157_ENABLE : STD_LOGIC; + signal cs_157_TORGTS : STD_LOGIC; + signal cs_157_OUTMUX : STD_LOGIC; + signal cs_165_ENABLE : STD_LOGIC; + signal cs_165_TORGTS : STD_LOGIC; + signal cs_165_OUTMUX : STD_LOGIC; + signal cs_173_ENABLE : STD_LOGIC; + signal cs_173_TORGTS : STD_LOGIC; + signal cs_173_OUTMUX : STD_LOGIC; + signal cs_181_ENABLE : STD_LOGIC; + signal cs_181_TORGTS : STD_LOGIC; + signal cs_181_OUTMUX : STD_LOGIC; + signal cs_229_ENABLE : STD_LOGIC; + signal cs_229_TORGTS : STD_LOGIC; + signal cs_229_OUTMUX : STD_LOGIC; + signal cs_237_ENABLE : STD_LOGIC; + signal cs_237_TORGTS : STD_LOGIC; + signal cs_237_OUTMUX : STD_LOGIC; + signal cs_245_ENABLE : STD_LOGIC; + signal cs_245_TORGTS : STD_LOGIC; + signal cs_245_OUTMUX : STD_LOGIC; + signal cs_253_ENABLE : STD_LOGIC; + signal cs_253_TORGTS : STD_LOGIC; + signal cs_253_OUTMUX : STD_LOGIC; + signal cs_158_ENABLE : STD_LOGIC; + signal cs_158_TORGTS : STD_LOGIC; + signal cs_158_OUTMUX : STD_LOGIC; + signal cs_166_ENABLE : STD_LOGIC; + signal cs_166_TORGTS : STD_LOGIC; + signal cs_166_OUTMUX : STD_LOGIC; + signal cs_174_ENABLE : STD_LOGIC; + signal cs_174_TORGTS : STD_LOGIC; + signal cs_174_OUTMUX : STD_LOGIC; + signal cs_182_ENABLE : STD_LOGIC; + signal cs_182_TORGTS : STD_LOGIC; + signal cs_182_OUTMUX : STD_LOGIC; + signal cs_190_ENABLE : STD_LOGIC; + signal cs_190_TORGTS : STD_LOGIC; + signal cs_190_OUTMUX : STD_LOGIC; + signal cs_238_ENABLE : STD_LOGIC; + signal cs_238_TORGTS : STD_LOGIC; + signal cs_238_OUTMUX : STD_LOGIC; + signal cs_246_ENABLE : STD_LOGIC; + signal cs_246_TORGTS : STD_LOGIC; + signal cs_246_OUTMUX : STD_LOGIC; + signal cs_254_ENABLE : STD_LOGIC; + signal cs_254_TORGTS : STD_LOGIC; + signal cs_254_OUTMUX : STD_LOGIC; + signal cs_159_ENABLE : STD_LOGIC; + signal cs_159_TORGTS : STD_LOGIC; + signal cs_159_OUTMUX : STD_LOGIC; + signal cs_167_ENABLE : STD_LOGIC; + signal cs_167_TORGTS : STD_LOGIC; + signal cs_167_OUTMUX : STD_LOGIC; + signal cs_175_ENABLE : STD_LOGIC; + signal cs_175_TORGTS : STD_LOGIC; + signal cs_175_OUTMUX : STD_LOGIC; + signal cs_183_ENABLE : STD_LOGIC; + signal cs_183_TORGTS : STD_LOGIC; + signal cs_183_OUTMUX : STD_LOGIC; + signal cs_191_ENABLE : STD_LOGIC; + signal cs_191_TORGTS : STD_LOGIC; + signal cs_191_OUTMUX : STD_LOGIC; + signal cs_239_ENABLE : STD_LOGIC; + signal cs_239_TORGTS : STD_LOGIC; + signal cs_239_OUTMUX : STD_LOGIC; + signal cs_247_ENABLE : STD_LOGIC; + signal cs_247_TORGTS : STD_LOGIC; + signal cs_247_OUTMUX : STD_LOGIC; + signal cs_255_ENABLE : STD_LOGIC; + signal cs_255_TORGTS : STD_LOGIC; + signal cs_255_OUTMUX : STD_LOGIC; + signal cs_168_ENABLE : STD_LOGIC; + signal cs_168_TORGTS : STD_LOGIC; + signal cs_168_OUTMUX : STD_LOGIC; + signal cs_176_ENABLE : STD_LOGIC; + signal cs_176_TORGTS : STD_LOGIC; + signal cs_176_OUTMUX : STD_LOGIC; + signal cs_184_ENABLE : STD_LOGIC; + signal cs_184_TORGTS : STD_LOGIC; + signal cs_184_OUTMUX : STD_LOGIC; + signal cs_192_ENABLE : STD_LOGIC; + signal cs_192_TORGTS : STD_LOGIC; + signal cs_192_OUTMUX : STD_LOGIC; + signal cs_248_ENABLE : STD_LOGIC; + signal cs_248_TORGTS : STD_LOGIC; + signal cs_248_OUTMUX : STD_LOGIC; + signal cs_169_ENABLE : STD_LOGIC; + signal cs_169_TORGTS : STD_LOGIC; + signal cs_169_OUTMUX : STD_LOGIC; + signal cs_177_ENABLE : STD_LOGIC; + signal cs_177_TORGTS : STD_LOGIC; + signal cs_177_OUTMUX : STD_LOGIC; + signal cs_185_ENABLE : STD_LOGIC; + signal cs_185_TORGTS : STD_LOGIC; + signal cs_185_OUTMUX : STD_LOGIC; + signal cs_193_ENABLE : STD_LOGIC; + signal cs_193_TORGTS : STD_LOGIC; + signal cs_193_OUTMUX : STD_LOGIC; + signal cs_249_ENABLE : STD_LOGIC; + signal cs_249_TORGTS : STD_LOGIC; + signal cs_249_OUTMUX : STD_LOGIC; + signal cs_178_ENABLE : STD_LOGIC; + signal cs_178_TORGTS : STD_LOGIC; + signal cs_178_OUTMUX : STD_LOGIC; + signal cs_186_ENABLE : STD_LOGIC; + signal cs_186_TORGTS : STD_LOGIC; + signal cs_186_OUTMUX : STD_LOGIC; + signal cs_194_ENABLE : STD_LOGIC; + signal cs_194_TORGTS : STD_LOGIC; + signal cs_194_OUTMUX : STD_LOGIC; + signal cs_179_ENABLE : STD_LOGIC; + signal cs_179_TORGTS : STD_LOGIC; + signal cs_179_OUTMUX : STD_LOGIC; + signal cs_187_ENABLE : STD_LOGIC; + signal cs_187_TORGTS : STD_LOGIC; + signal cs_187_OUTMUX : STD_LOGIC; + signal cs_195_ENABLE : STD_LOGIC; + signal cs_195_TORGTS : STD_LOGIC; + signal cs_195_OUTMUX : STD_LOGIC; + signal cs_188_ENABLE : STD_LOGIC; + signal cs_188_TORGTS : STD_LOGIC; + signal cs_188_OUTMUX : STD_LOGIC; + signal cs_196_ENABLE : STD_LOGIC; + signal cs_196_TORGTS : STD_LOGIC; + signal cs_196_OUTMUX : STD_LOGIC; + signal cs_189_ENABLE : STD_LOGIC; + signal cs_189_TORGTS : STD_LOGIC; + signal cs_189_OUTMUX : STD_LOGIC; + signal cs_197_ENABLE : STD_LOGIC; + signal cs_197_TORGTS : STD_LOGIC; + signal cs_197_OUTMUX : STD_LOGIC; + signal cs_198_ENABLE : STD_LOGIC; + signal cs_198_TORGTS : STD_LOGIC; + signal cs_198_OUTMUX : STD_LOGIC; + signal cs_199_ENABLE : STD_LOGIC; + signal cs_199_TORGTS : STD_LOGIC; + signal cs_199_OUTMUX : STD_LOGIC; + signal clk_ENABLE : STD_LOGIC; + signal clk_TORGTS : STD_LOGIC; + signal clk_OUTMUX : STD_LOGIC; + signal adr_bus_10_IBUF_13 : STD_LOGIC; + signal adr_bus_11_IBUF_14 : STD_LOGIC; + signal adr_bus_12_IBUF_15 : STD_LOGIC; + signal adr_bus_13_IBUF_16 : STD_LOGIC; + signal adr_bus_14_IBUF_17 : STD_LOGIC; + signal adr_bus_15_IBUF_18 : STD_LOGIC; + signal cs_10_ENABLE : STD_LOGIC; + signal cs_10_TORGTS : STD_LOGIC; + signal cs_10_OUTMUX : STD_LOGIC; + signal cs_11_ENABLE : STD_LOGIC; + signal cs_11_TORGTS : STD_LOGIC; + signal cs_11_OUTMUX : STD_LOGIC; + signal cs_12_ENABLE : STD_LOGIC; + signal cs_12_TORGTS : STD_LOGIC; + signal cs_12_OUTMUX : STD_LOGIC; + signal cs_20_ENABLE : STD_LOGIC; + signal cs_20_TORGTS : STD_LOGIC; + signal cs_20_OUTMUX : STD_LOGIC; + signal cs_13_ENABLE : STD_LOGIC; + signal cs_13_TORGTS : STD_LOGIC; + signal cs_13_OUTMUX : STD_LOGIC; + signal cs_21_ENABLE : STD_LOGIC; + signal cs_21_TORGTS : STD_LOGIC; + signal cs_21_OUTMUX : STD_LOGIC; + signal cs_14_ENABLE : STD_LOGIC; + signal cs_14_TORGTS : STD_LOGIC; + signal cs_14_OUTMUX : STD_LOGIC; + signal cs_22_ENABLE : STD_LOGIC; + signal cs_22_TORGTS : STD_LOGIC; + signal cs_22_OUTMUX : STD_LOGIC; + signal cs_30_ENABLE : STD_LOGIC; + signal cs_30_TORGTS : STD_LOGIC; + signal cs_30_OUTMUX : STD_LOGIC; + signal cs_15_ENABLE : STD_LOGIC; + signal cs_15_TORGTS : STD_LOGIC; + signal cs_15_OUTMUX : STD_LOGIC; + signal cs_23_ENABLE : STD_LOGIC; + signal cs_23_TORGTS : STD_LOGIC; + signal cs_23_OUTMUX : STD_LOGIC; + signal cs_31_ENABLE : STD_LOGIC; + signal cs_31_TORGTS : STD_LOGIC; + signal cs_31_OUTMUX : STD_LOGIC; + signal cs_16_ENABLE : STD_LOGIC; + signal cs_16_TORGTS : STD_LOGIC; + signal cs_16_OUTMUX : STD_LOGIC; + signal cs_24_ENABLE : STD_LOGIC; + signal cs_24_TORGTS : STD_LOGIC; + signal cs_24_OUTMUX : STD_LOGIC; + signal cs_32_ENABLE : STD_LOGIC; + signal cs_32_TORGTS : STD_LOGIC; + signal cs_32_OUTMUX : STD_LOGIC; + signal cs_40_ENABLE : STD_LOGIC; + signal cs_40_TORGTS : STD_LOGIC; + signal cs_40_OUTMUX : STD_LOGIC; + signal cs_17_ENABLE : STD_LOGIC; + signal cs_17_TORGTS : STD_LOGIC; + signal cs_17_OUTMUX : STD_LOGIC; + signal cs_25_ENABLE : STD_LOGIC; + signal cs_25_TORGTS : STD_LOGIC; + signal cs_25_OUTMUX : STD_LOGIC; + signal cs_33_ENABLE : STD_LOGIC; + signal cs_33_TORGTS : STD_LOGIC; + signal cs_33_OUTMUX : STD_LOGIC; + signal cs_41_ENABLE : STD_LOGIC; + signal cs_41_TORGTS : STD_LOGIC; + signal cs_41_OUTMUX : STD_LOGIC; + signal cs_18_ENABLE : STD_LOGIC; + signal cs_18_TORGTS : STD_LOGIC; + signal cs_18_OUTMUX : STD_LOGIC; + signal cs_26_ENABLE : STD_LOGIC; + signal cs_26_TORGTS : STD_LOGIC; + signal cs_26_OUTMUX : STD_LOGIC; + signal cs_34_ENABLE : STD_LOGIC; + signal cs_34_TORGTS : STD_LOGIC; + signal cs_34_OUTMUX : STD_LOGIC; + signal cs_42_ENABLE : STD_LOGIC; + signal cs_42_TORGTS : STD_LOGIC; + signal cs_42_OUTMUX : STD_LOGIC; + signal cs_50_ENABLE : STD_LOGIC; + signal cs_50_TORGTS : STD_LOGIC; + signal cs_50_OUTMUX : STD_LOGIC; + signal cs_19_ENABLE : STD_LOGIC; + signal cs_19_TORGTS : STD_LOGIC; + signal cs_19_OUTMUX : STD_LOGIC; + signal cs_27_ENABLE : STD_LOGIC; + signal cs_27_TORGTS : STD_LOGIC; + signal cs_27_OUTMUX : STD_LOGIC; + signal cs_35_ENABLE : STD_LOGIC; + signal cs_35_TORGTS : STD_LOGIC; + signal cs_35_OUTMUX : STD_LOGIC; + signal cs_43_ENABLE : STD_LOGIC; + signal cs_43_TORGTS : STD_LOGIC; + signal cs_43_OUTMUX : STD_LOGIC; + signal cs_51_ENABLE : STD_LOGIC; + signal cs_51_TORGTS : STD_LOGIC; + signal cs_51_OUTMUX : STD_LOGIC; + signal cs_28_ENABLE : STD_LOGIC; + signal cs_28_TORGTS : STD_LOGIC; + signal cs_28_OUTMUX : STD_LOGIC; + signal cs_36_ENABLE : STD_LOGIC; + signal cs_36_TORGTS : STD_LOGIC; + signal cs_36_OUTMUX : STD_LOGIC; + signal cs_44_ENABLE : STD_LOGIC; + signal cs_44_TORGTS : STD_LOGIC; + signal cs_44_OUTMUX : STD_LOGIC; + signal cs_52_ENABLE : STD_LOGIC; + signal cs_52_TORGTS : STD_LOGIC; + signal cs_52_OUTMUX : STD_LOGIC; + signal cs_60_ENABLE : STD_LOGIC; + signal cs_60_TORGTS : STD_LOGIC; + signal cs_60_OUTMUX : STD_LOGIC; + signal cs_29_ENABLE : STD_LOGIC; + signal cs_29_TORGTS : STD_LOGIC; + signal cs_29_OUTMUX : STD_LOGIC; + signal cs_37_ENABLE : STD_LOGIC; + signal cs_37_TORGTS : STD_LOGIC; + signal cs_37_OUTMUX : STD_LOGIC; + signal cs_45_ENABLE : STD_LOGIC; + signal cs_45_TORGTS : STD_LOGIC; + signal cs_45_OUTMUX : STD_LOGIC; + signal cs_53_ENABLE : STD_LOGIC; + signal cs_53_TORGTS : STD_LOGIC; + signal cs_53_OUTMUX : STD_LOGIC; + signal cs_61_ENABLE : STD_LOGIC; + signal cs_61_TORGTS : STD_LOGIC; + signal cs_61_OUTMUX : STD_LOGIC; + signal cs_38_ENABLE : STD_LOGIC; + signal cs_38_TORGTS : STD_LOGIC; + signal cs_38_OUTMUX : STD_LOGIC; + signal cs_46_ENABLE : STD_LOGIC; + signal cs_46_TORGTS : STD_LOGIC; + signal cs_46_OUTMUX : STD_LOGIC; + signal cs_54_ENABLE : STD_LOGIC; + signal cs_54_TORGTS : STD_LOGIC; + signal cs_54_OUTMUX : STD_LOGIC; + signal cs_62_ENABLE : STD_LOGIC; + signal cs_62_TORGTS : STD_LOGIC; + signal cs_62_OUTMUX : STD_LOGIC; + signal cs_70_ENABLE : STD_LOGIC; + signal cs_70_TORGTS : STD_LOGIC; + signal cs_70_OUTMUX : STD_LOGIC; + signal cs_39_ENABLE : STD_LOGIC; + signal cs_39_TORGTS : STD_LOGIC; + signal cs_39_OUTMUX : STD_LOGIC; + signal cs_47_ENABLE : STD_LOGIC; + signal cs_47_TORGTS : STD_LOGIC; + signal cs_47_OUTMUX : STD_LOGIC; + signal cs_55_ENABLE : STD_LOGIC; + signal cs_55_TORGTS : STD_LOGIC; + signal cs_55_OUTMUX : STD_LOGIC; + signal cs_63_ENABLE : STD_LOGIC; + signal cs_63_TORGTS : STD_LOGIC; + signal cs_63_OUTMUX : STD_LOGIC; + signal cs_71_ENABLE : STD_LOGIC; + signal cs_71_TORGTS : STD_LOGIC; + signal cs_71_OUTMUX : STD_LOGIC; + signal cs_48_ENABLE : STD_LOGIC; + signal cs_48_TORGTS : STD_LOGIC; + signal cs_48_OUTMUX : STD_LOGIC; + signal cs_56_ENABLE : STD_LOGIC; + signal cs_56_TORGTS : STD_LOGIC; + signal cs_56_OUTMUX : STD_LOGIC; + signal cs_64_ENABLE : STD_LOGIC; + signal cs_64_TORGTS : STD_LOGIC; + signal cs_64_OUTMUX : STD_LOGIC; + signal cs_72_ENABLE : STD_LOGIC; + signal cs_72_TORGTS : STD_LOGIC; + signal cs_72_OUTMUX : STD_LOGIC; + signal cs_80_ENABLE : STD_LOGIC; + signal cs_80_TORGTS : STD_LOGIC; + signal cs_80_OUTMUX : STD_LOGIC; + signal cs_49_ENABLE : STD_LOGIC; + signal cs_49_TORGTS : STD_LOGIC; + signal cs_49_OUTMUX : STD_LOGIC; + signal cs_57_ENABLE : STD_LOGIC; + signal cs_57_TORGTS : STD_LOGIC; + signal cs_57_OUTMUX : STD_LOGIC; + signal cs_65_ENABLE : STD_LOGIC; + signal cs_65_TORGTS : STD_LOGIC; + signal cs_65_OUTMUX : STD_LOGIC; + signal cs_73_ENABLE : STD_LOGIC; + signal cs_73_TORGTS : STD_LOGIC; + signal cs_73_OUTMUX : STD_LOGIC; + signal cs_81_ENABLE : STD_LOGIC; + signal cs_81_TORGTS : STD_LOGIC; + signal cs_81_OUTMUX : STD_LOGIC; + signal cs_58_ENABLE : STD_LOGIC; + signal cs_58_TORGTS : STD_LOGIC; + signal cs_58_OUTMUX : STD_LOGIC; + signal cs_66_ENABLE : STD_LOGIC; + signal cs_66_TORGTS : STD_LOGIC; + signal cs_66_OUTMUX : STD_LOGIC; + signal cs_74_ENABLE : STD_LOGIC; + signal cs_74_TORGTS : STD_LOGIC; + signal cs_74_OUTMUX : STD_LOGIC; + signal cs_82_ENABLE : STD_LOGIC; + signal cs_82_TORGTS : STD_LOGIC; + signal cs_82_OUTMUX : STD_LOGIC; + signal cs_90_ENABLE : STD_LOGIC; + signal cs_90_TORGTS : STD_LOGIC; + signal cs_90_OUTMUX : STD_LOGIC; + signal cs_59_ENABLE : STD_LOGIC; + signal cs_59_TORGTS : STD_LOGIC; + signal cs_59_OUTMUX : STD_LOGIC; + signal cs_67_ENABLE : STD_LOGIC; + signal cs_67_TORGTS : STD_LOGIC; + signal cs_67_OUTMUX : STD_LOGIC; + signal cs_75_ENABLE : STD_LOGIC; + signal cs_75_TORGTS : STD_LOGIC; + signal cs_75_OUTMUX : STD_LOGIC; + signal cs_83_ENABLE : STD_LOGIC; + signal cs_83_TORGTS : STD_LOGIC; + signal cs_83_OUTMUX : STD_LOGIC; + signal cs_91_ENABLE : STD_LOGIC; + signal cs_91_TORGTS : STD_LOGIC; + signal cs_91_OUTMUX : STD_LOGIC; + signal cs_68_ENABLE : STD_LOGIC; + signal cs_68_TORGTS : STD_LOGIC; + signal cs_68_OUTMUX : STD_LOGIC; + signal cs_76_ENABLE : STD_LOGIC; + signal cs_76_TORGTS : STD_LOGIC; + signal cs_76_OUTMUX : STD_LOGIC; + signal cs_84_ENABLE : STD_LOGIC; + signal cs_84_TORGTS : STD_LOGIC; + signal cs_84_OUTMUX : STD_LOGIC; + signal cs_92_ENABLE : STD_LOGIC; + signal cs_92_TORGTS : STD_LOGIC; + signal cs_92_OUTMUX : STD_LOGIC; + signal cs_69_ENABLE : STD_LOGIC; + signal cs_69_TORGTS : STD_LOGIC; + signal cs_69_OUTMUX : STD_LOGIC; + signal VCC : STD_LOGIC; +begin + dadrL_BU2735 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N18117_FROM + ); + dadrL_BU2732 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_5_IBUF, + ADR1 => adr_bus_7_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N18117_GROM + ); + dadrL_N18117_XUSED : X_BUF + port map ( + I => dadrL_N18117_FROM, + O => dadrL_N18117 + ); + dadrL_N18117_YUSED : X_BUF + port map ( + I => dadrL_N18117_GROM, + O => dadrL_N18116 + ); + dadrL_BU2196 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N14638_FROM + ); + dadrL_BU2193 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N14638_GROM + ); + dadrL_N14638_XUSED : X_BUF + port map ( + I => dadrL_N14638_FROM, + O => dadrL_N14638 + ); + dadrL_N14638_YUSED : X_BUF + port map ( + I => dadrL_N14638_GROM, + O => dadrL_N14637 + ); + dadrL_BU2427 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N16129_FROM + ); + dadrL_BU2424 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N16129_GROM + ); + dadrL_N16129_XUSED : X_BUF + port map ( + I => dadrL_N16129_FROM, + O => dadrL_N16129 + ); + dadrL_N16129_YUSED : X_BUF + port map ( + I => dadrL_N16129_GROM, + O => dadrL_N16128 + ); + dadrL_BU2416 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N16058_FROM + ); + dadrL_BU2413 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N16058_GROM + ); + dadrL_N16058_XUSED : X_BUF + port map ( + I => dadrL_N16058_FROM, + O => dadrL_N16058 + ); + dadrL_N16058_YUSED : X_BUF + port map ( + I => dadrL_N16058_GROM, + O => dadrL_N16057 + ); + dadrL_BU139 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N1361_FROM + ); + dadrL_BU136 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_4_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_6_IBUF, + O => dadrL_N1361_GROM + ); + dadrL_N1361_XUSED : X_BUF + port map ( + I => dadrL_N1361_FROM, + O => dadrL_N1361 + ); + dadrL_N1361_YUSED : X_BUF + port map ( + I => dadrL_N1361_GROM, + O => dadrL_N1360 + ); + dadrL_BU128 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_0_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N1290_FROM + ); + dadrL_BU125 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N1290_GROM + ); + dadrL_N1290_XUSED : X_BUF + port map ( + I => dadrL_N1290_FROM, + O => dadrL_N1290 + ); + dadrL_N1290_YUSED : X_BUF + port map ( + I => dadrL_N1290_GROM, + O => dadrL_N1289 + ); + dadrL_BU1294 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_0_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N8816_FROM + ); + dadrL_BU1291 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N8816_GROM + ); + dadrL_N8816_XUSED : X_BUF + port map ( + I => dadrL_N8816_FROM, + O => dadrL_N8816 + ); + dadrL_N8816_YUSED : X_BUF + port map ( + I => dadrL_N8816_GROM, + O => dadrL_N8815 + ); + dadrL_BU1698 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N11442_FROM + ); + dadrL_BU1701 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N11442_GROM + ); + dadrL_N11442_XUSED : X_BUF + port map ( + I => dadrL_N11442_FROM, + O => dadrL_N11442 + ); + dadrL_N11442_YUSED : X_BUF + port map ( + I => dadrL_N11442_GROM, + O => dadrL_N11443 + ); + dadrL_BU1283 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N8745_FROM + ); + dadrL_BU1280 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_5_IBUF, + ADR1 => adr_bus_7_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N8745_GROM + ); + dadrL_N8745_XUSED : X_BUF + port map ( + I => dadrL_N8745_FROM, + O => dadrL_N8745 + ); + dadrL_N8745_YUSED : X_BUF + port map ( + I => dadrL_N8745_GROM, + O => dadrL_N8744 + ); + dadrL_BU1687 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_5_IBUF, + ADR1 => adr_bus_7_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_6_IBUF, + O => dadrL_N11371_FROM + ); + dadrL_BU1690 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N11371_GROM + ); + dadrL_N11371_XUSED : X_BUF + port map ( + I => dadrL_N11371_FROM, + O => dadrL_N11371 + ); + dadrL_N11371_YUSED : X_BUF + port map ( + I => dadrL_N11371_GROM, + O => dadrL_N11372 + ); + dadrL_BU2768 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_0_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N18330_FROM + ); + dadrL_BU2765 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_6_IBUF, + O => dadrL_N18330_GROM + ); + dadrL_N18330_XUSED : X_BUF + port map ( + I => dadrL_N18330_FROM, + O => dadrL_N18330 + ); + dadrL_N18330_YUSED : X_BUF + port map ( + I => dadrL_N18330_GROM, + O => dadrL_N18329 + ); + dadrL_BU2229 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N14851_FROM + ); + dadrL_BU2226 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_7_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N14851_GROM + ); + dadrL_N14851_XUSED : X_BUF + port map ( + I => dadrL_N14851_FROM, + O => dadrL_N14851 + ); + dadrL_N14851_YUSED : X_BUF + port map ( + I => dadrL_N14851_GROM, + O => dadrL_N14850 + ); + dadrL_BU2757 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N18259_FROM + ); + dadrL_BU2754 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_5_IBUF, + ADR1 => adr_bus_7_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N18259_GROM + ); + dadrL_N18259_XUSED : X_BUF + port map ( + I => dadrL_N18259_FROM, + O => dadrL_N18259 + ); + dadrL_N18259_YUSED : X_BUF + port map ( + I => dadrL_N18259_GROM, + O => dadrL_N18258 + ); + dadrL_BU2449 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N16271_FROM + ); + dadrL_BU2446 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_7_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N16271_GROM + ); + dadrL_N16271_XUSED : X_BUF + port map ( + I => dadrL_N16271_FROM, + O => dadrL_N16271 + ); + dadrL_N16271_YUSED : X_BUF + port map ( + I => dadrL_N16271_GROM, + O => dadrL_N16270 + ); + dadrL_BU2218 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N14780_FROM + ); + dadrL_BU2215 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_6_IBUF, + O => dadrL_N14780_GROM + ); + dadrL_N14780_XUSED : X_BUF + port map ( + I => dadrL_N14780_FROM, + O => dadrL_N14780 + ); + dadrL_N14780_YUSED : X_BUF + port map ( + I => dadrL_N14780_GROM, + O => dadrL_N14779 + ); + dadrL_BU2438 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N16200_FROM + ); + dadrL_BU2435 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_7_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N16200_GROM + ); + dadrL_N16200_XUSED : X_BUF + port map ( + I => dadrL_N16200_FROM, + O => dadrL_N16200 + ); + dadrL_N16200_YUSED : X_BUF + port map ( + I => dadrL_N16200_GROM, + O => dadrL_N16199 + ); + dadrL_BU158 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N1502_FROM + ); + dadrL_BU161 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N1502_GROM + ); + dadrL_N1502_XUSED : X_BUF + port map ( + I => dadrL_N1502_FROM, + O => dadrL_N1502 + ); + dadrL_N1502_YUSED : X_BUF + port map ( + I => dadrL_N1502_GROM, + O => dadrL_N1503 + ); + dadrL_BU147 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_4_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N1431_FROM + ); + dadrL_BU150 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_0_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N1431_GROM + ); + dadrL_N1431_XUSED : X_BUF + port map ( + I => dadrL_N1431_FROM, + O => dadrL_N1431 + ); + dadrL_N1431_YUSED : X_BUF + port map ( + I => dadrL_N1431_GROM, + O => dadrL_N1432 + ); + dadrL_BU1316 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N8958_FROM + ); + dadrL_BU1313 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_7_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N8958_GROM + ); + dadrL_N8958_XUSED : X_BUF + port map ( + I => dadrL_N8958_FROM, + O => dadrL_N8958 + ); + dadrL_N8958_YUSED : X_BUF + port map ( + I => dadrL_N8958_GROM, + O => dadrL_N8957 + ); + dadrL_BU1723 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N11585_FROM + ); + dadrL_BU1720 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => adr_bus_5_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N11585_GROM + ); + dadrL_N11585_XUSED : X_BUF + port map ( + I => dadrL_N11585_FROM, + O => dadrL_N11585 + ); + dadrL_N11585_YUSED : X_BUF + port map ( + I => dadrL_N11585_GROM, + O => dadrL_N11584 + ); + dadrL_BU1305 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N8887_FROM + ); + dadrL_BU1302 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_5_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N8887_GROM + ); + dadrL_N8887_XUSED : X_BUF + port map ( + I => dadrL_N8887_FROM, + O => dadrL_N8887 + ); + dadrL_N8887_YUSED : X_BUF + port map ( + I => dadrL_N8887_GROM, + O => dadrL_N8886 + ); + dadrL_BU1709 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_7_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N11513_FROM + ); + dadrL_BU1712 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N11513_GROM + ); + dadrL_N11513_XUSED : X_BUF + port map ( + I => dadrL_N11513_FROM, + O => dadrL_N11513 + ); + dadrL_N11513_YUSED : X_BUF + port map ( + I => dadrL_N11513_GROM, + O => dadrL_N11514 + ); + dadrL_BU2248 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N14992_FROM + ); + dadrL_BU2251 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N14992_GROM + ); + dadrL_N14992_XUSED : X_BUF + port map ( + I => dadrL_N14992_FROM, + O => dadrL_N14992 + ); + dadrL_N14992_YUSED : X_BUF + port map ( + I => dadrL_N14992_GROM, + O => dadrL_N14993 + ); + dadrL_BU2468 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N16412_FROM + ); + dadrL_BU2471 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_0_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N16412_GROM + ); + dadrL_N16412_XUSED : X_BUF + port map ( + I => dadrL_N16412_FROM, + O => dadrL_N16412 + ); + dadrL_N16412_YUSED : X_BUF + port map ( + I => dadrL_N16412_GROM, + O => dadrL_N16413 + ); + dadrL_BU2237 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_6_IBUF, + O => dadrL_N14921_FROM + ); + dadrL_BU2240 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N14921_GROM + ); + dadrL_N14921_XUSED : X_BUF + port map ( + I => dadrL_N14921_FROM, + O => dadrL_N14921 + ); + dadrL_N14921_YUSED : X_BUF + port map ( + I => dadrL_N14921_GROM, + O => dadrL_N14922 + ); + dadrL_BU2457 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N16341_FROM + ); + dadrL_BU2460 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N16341_GROM + ); + dadrL_N16341_XUSED : X_BUF + port map ( + I => dadrL_N16341_FROM, + O => dadrL_N16341 + ); + dadrL_N16341_YUSED : X_BUF + port map ( + I => dadrL_N16341_GROM, + O => dadrL_N16342 + ); + dadrL_BU183 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_0_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N1645_FROM + ); + dadrL_BU180 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N1645_GROM + ); + dadrL_N1645_XUSED : X_BUF + port map ( + I => dadrL_N1645_FROM, + O => dadrL_N1645 + ); + dadrL_N1645_YUSED : X_BUF + port map ( + I => dadrL_N1645_GROM, + O => dadrL_N1644 + ); + dadrL_BU169 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N1573_FROM + ); + dadrL_BU172 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N1573_GROM + ); + dadrL_N1573_XUSED : X_BUF + port map ( + I => dadrL_N1573_FROM, + O => dadrL_N1573 + ); + dadrL_N1573_YUSED : X_BUF + port map ( + I => dadrL_N1573_GROM, + O => dadrL_N1574 + ); + dadrL_BU1745 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N11727_FROM + ); + dadrL_BU1742 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N11727_GROM + ); + dadrL_N11727_XUSED : X_BUF + port map ( + I => dadrL_N11727_FROM, + O => dadrL_N11727 + ); + dadrL_N11727_YUSED : X_BUF + port map ( + I => dadrL_N11727_GROM, + O => dadrL_N11726 + ); + dadrL_BU1734 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_0_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N11656_FROM + ); + dadrL_BU1731 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N11656_GROM + ); + dadrL_N11656_XUSED : X_BUF + port map ( + I => dadrL_N11656_FROM, + O => dadrL_N11656 + ); + dadrL_N11656_YUSED : X_BUF + port map ( + I => dadrL_N11656_GROM, + O => dadrL_N11655 + ); + dadrL_BU2273 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N15135_FROM + ); + dadrL_BU2270 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N15135_GROM + ); + dadrL_N15135_XUSED : X_BUF + port map ( + I => dadrL_N15135_FROM, + O => dadrL_N15135 + ); + dadrL_N15135_YUSED : X_BUF + port map ( + I => dadrL_N15135_GROM, + O => dadrL_N15134 + ); + dadrL_BU2493 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N16555_FROM + ); + dadrL_BU2490 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_5_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N16555_GROM + ); + dadrL_N16555_XUSED : X_BUF + port map ( + I => dadrL_N16555_FROM, + O => dadrL_N16555 + ); + dadrL_N16555_YUSED : X_BUF + port map ( + I => dadrL_N16555_GROM, + O => dadrL_N16554 + ); + dadrL_BU2259 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N15063_FROM + ); + dadrL_BU2262 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_0_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N15063_GROM + ); + dadrL_N15063_XUSED : X_BUF + port map ( + I => dadrL_N15063_FROM, + O => dadrL_N15063 + ); + dadrL_N15063_YUSED : X_BUF + port map ( + I => dadrL_N15063_GROM, + O => dadrL_N15064 + ); + dadrL_BU2479 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N16483_FROM + ); + dadrL_BU2482 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N16483_GROM + ); + dadrL_N16483_XUSED : X_BUF + port map ( + I => dadrL_N16483_FROM, + O => dadrL_N16483 + ); + dadrL_N16483_YUSED : X_BUF + port map ( + I => dadrL_N16483_GROM, + O => dadrL_N16484 + ); + dadrL_BU205 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_0_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N1787_FROM + ); + dadrL_BU202 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_4_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N1787_GROM + ); + dadrL_N1787_XUSED : X_BUF + port map ( + I => dadrL_N1787_FROM, + O => dadrL_N1787 + ); + dadrL_N1787_YUSED : X_BUF + port map ( + I => dadrL_N1787_GROM, + O => dadrL_N1786 + ); + dadrL_BU194 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_0_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N1716_FROM + ); + dadrL_BU191 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N1716_GROM + ); + dadrL_N1716_XUSED : X_BUF + port map ( + I => dadrL_N1716_FROM, + O => dadrL_N1716 + ); + dadrL_N1716_YUSED : X_BUF + port map ( + I => dadrL_N1716_GROM, + O => dadrL_N1715 + ); + dadrL_BU1767 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N11869_FROM + ); + dadrL_BU1764 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_7_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_6_IBUF, + O => dadrL_N11869_GROM + ); + dadrL_N11869_XUSED : X_BUF + port map ( + I => dadrL_N11869_FROM, + O => dadrL_N11869 + ); + dadrL_N11869_YUSED : X_BUF + port map ( + I => dadrL_N11869_GROM, + O => dadrL_N11868 + ); + dadrL_BU1756 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N11798_FROM + ); + dadrL_BU1753 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_5_IBUF, + ADR1 => adr_bus_4_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_6_IBUF, + O => dadrL_N11798_GROM + ); + dadrL_N11798_XUSED : X_BUF + port map ( + I => dadrL_N11798_FROM, + O => dadrL_N11798 + ); + dadrL_N11798_YUSED : X_BUF + port map ( + I => dadrL_N11798_GROM, + O => dadrL_N11797 + ); + dadrL_BU2295 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N15277_FROM + ); + dadrL_BU2292 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N15277_GROM + ); + dadrL_N15277_XUSED : X_BUF + port map ( + I => dadrL_N15277_FROM, + O => dadrL_N15277 + ); + dadrL_N15277_YUSED : X_BUF + port map ( + I => dadrL_N15277_GROM, + O => dadrL_N15276 + ); + dadrL_BU2284 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N15206_FROM + ); + dadrL_BU2281 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N15206_GROM + ); + dadrL_N15206_XUSED : X_BUF + port map ( + I => dadrL_N15206_FROM, + O => dadrL_N15206 + ); + dadrL_N15206_YUSED : X_BUF + port map ( + I => dadrL_N15206_GROM, + O => dadrL_N15205 + ); + dadrL_BU2515 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N16697_FROM + ); + dadrL_BU2512 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_6_IBUF, + O => dadrL_N16697_GROM + ); + dadrL_N16697_XUSED : X_BUF + port map ( + I => dadrL_N16697_FROM, + O => dadrL_N16697 + ); + dadrL_N16697_YUSED : X_BUF + port map ( + I => dadrL_N16697_GROM, + O => dadrL_N16696 + ); + dadrL_BU2504 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N16626_FROM + ); + dadrL_BU2501 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_4_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N16626_GROM + ); + dadrL_N16626_XUSED : X_BUF + port map ( + I => dadrL_N16626_FROM, + O => dadrL_N16626 + ); + dadrL_N16626_YUSED : X_BUF + port map ( + I => dadrL_N16626_GROM, + O => dadrL_N16625 + ); + dadrL_BU227 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N1929_FROM + ); + dadrL_BU224 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_7_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N1929_GROM + ); + dadrL_N1929_XUSED : X_BUF + port map ( + I => dadrL_N1929_FROM, + O => dadrL_N1929 + ); + dadrL_N1929_YUSED : X_BUF + port map ( + I => dadrL_N1929_GROM, + O => dadrL_N1928 + ); + dadrL_BU216 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N1858_FROM + ); + dadrL_BU213 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N1858_GROM + ); + dadrL_N1858_XUSED : X_BUF + port map ( + I => dadrL_N1858_FROM, + O => dadrL_N1858 + ); + dadrL_N1858_YUSED : X_BUF + port map ( + I => dadrL_N1858_GROM, + O => dadrL_N1857 + ); + dadrL_BU1789 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N12011_FROM + ); + dadrL_BU1786 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_7_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N12011_GROM + ); + dadrL_N12011_XUSED : X_BUF + port map ( + I => dadrL_N12011_FROM, + O => dadrL_N12011 + ); + dadrL_N12011_YUSED : X_BUF + port map ( + I => dadrL_N12011_GROM, + O => dadrL_N12010 + ); + dadrL_BU1778 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N11940_FROM + ); + dadrL_BU1775 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_5_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N11940_GROM + ); + dadrL_N11940_XUSED : X_BUF + port map ( + I => dadrL_N11940_FROM, + O => dadrL_N11940 + ); + dadrL_N11940_YUSED : X_BUF + port map ( + I => dadrL_N11940_GROM, + O => dadrL_N11939 + ); + dadrL_BU2317 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_0_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N15419_FROM + ); + dadrL_BU2314 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => adr_bus_5_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N15419_GROM + ); + dadrL_N15419_XUSED : X_BUF + port map ( + I => dadrL_N15419_FROM, + O => dadrL_N15419 + ); + dadrL_N15419_YUSED : X_BUF + port map ( + I => dadrL_N15419_GROM, + O => dadrL_N15418 + ); + dadrL_BU2537 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N16839_FROM + ); + dadrL_BU2534 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_4_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N16839_GROM + ); + dadrL_N16839_XUSED : X_BUF + port map ( + I => dadrL_N16839_FROM, + O => dadrL_N16839 + ); + dadrL_N16839_YUSED : X_BUF + port map ( + I => dadrL_N16839_GROM, + O => dadrL_N16838 + ); + dadrL_BU2306 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N15348_FROM + ); + dadrL_BU2303 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N15348_GROM + ); + dadrL_N15348_XUSED : X_BUF + port map ( + I => dadrL_N15348_FROM, + O => dadrL_N15348 + ); + dadrL_N15348_YUSED : X_BUF + port map ( + I => dadrL_N15348_GROM, + O => dadrL_N15347 + ); + dadrL_BU2526 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N16768_FROM + ); + dadrL_BU2523 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_6_IBUF, + O => dadrL_N16768_GROM + ); + dadrL_N16768_XUSED : X_BUF + port map ( + I => dadrL_N16768_FROM, + O => dadrL_N16768 + ); + dadrL_N16768_YUSED : X_BUF + port map ( + I => dadrL_N16768_GROM, + O => dadrL_N16767 + ); + dadrL_BU1808 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_4_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N12152_FROM + ); + dadrL_BU1811 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N12152_GROM + ); + dadrL_N12152_XUSED : X_BUF + port map ( + I => dadrL_N12152_FROM, + O => dadrL_N12152 + ); + dadrL_N12152_YUSED : X_BUF + port map ( + I => dadrL_N12152_GROM, + O => dadrL_N12153 + ); + dadrL_BU1797 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N12081_FROM + ); + dadrL_BU1800 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N12081_GROM + ); + dadrL_N12081_XUSED : X_BUF + port map ( + I => dadrL_N12081_FROM, + O => dadrL_N12081 + ); + dadrL_N12081_YUSED : X_BUF + port map ( + I => dadrL_N12081_GROM, + O => dadrL_N12082 + ); + dadrL_BU2339 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N15561_FROM + ); + dadrL_BU2336 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_6_IBUF, + O => dadrL_N15561_GROM + ); + dadrL_N15561_XUSED : X_BUF + port map ( + I => dadrL_N15561_FROM, + O => dadrL_N15561 + ); + dadrL_N15561_YUSED : X_BUF + port map ( + I => dadrL_N15561_GROM, + O => dadrL_N15560 + ); + dadrL_BU2328 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N15490_FROM + ); + dadrL_BU2325 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_4_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N15490_GROM + ); + dadrL_N15490_XUSED : X_BUF + port map ( + I => dadrL_N15490_FROM, + O => dadrL_N15490 + ); + dadrL_N15490_YUSED : X_BUF + port map ( + I => dadrL_N15490_GROM, + O => dadrL_N15489 + ); + dadrL_BU2548 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N16910_FROM + ); + dadrL_BU2545 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_6_IBUF, + O => dadrL_N16910_GROM + ); + dadrL_N16910_XUSED : X_BUF + port map ( + I => dadrL_N16910_FROM, + O => dadrL_N16910 + ); + dadrL_N16910_YUSED : X_BUF + port map ( + I => dadrL_N16910_GROM, + O => dadrL_N16909 + ); + dadrL_BU609 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_7_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N4413_FROM + ); + dadrL_BU612 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_0_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N4413_GROM + ); + dadrL_N4413_XUSED : X_BUF + port map ( + I => dadrL_N4413_FROM, + O => dadrL_N4413 + ); + dadrL_N4413_YUSED : X_BUF + port map ( + I => dadrL_N4413_GROM, + O => dadrL_N4414 + ); + dadrL_BU598 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_5_IBUF, + ADR1 => adr_bus_4_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_6_IBUF, + O => dadrL_N4342_FROM + ); + dadrL_BU601 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_0_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N4342_GROM + ); + dadrL_N4342_XUSED : X_BUF + port map ( + I => dadrL_N4342_FROM, + O => dadrL_N4342 + ); + dadrL_N4342_YUSED : X_BUF + port map ( + I => dadrL_N4342_GROM, + O => dadrL_N4343 + ); + dadrL_BU1819 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N12223_FROM + ); + dadrL_BU1822 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_0_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N12223_GROM + ); + dadrL_N12223_XUSED : X_BUF + port map ( + I => dadrL_N12223_FROM, + O => dadrL_N12223 + ); + dadrL_N12223_YUSED : X_BUF + port map ( + I => dadrL_N12223_GROM, + O => dadrL_N12224 + ); + dadrL_BU2358 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_6_IBUF, + O => dadrL_N15702_FROM + ); + dadrL_BU2361 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N15702_GROM + ); + dadrL_N15702_XUSED : X_BUF + port map ( + I => dadrL_N15702_FROM, + O => dadrL_N15702 + ); + dadrL_N15702_YUSED : X_BUF + port map ( + I => dadrL_N15702_GROM, + O => dadrL_N15703 + ); + dadrL_BU2347 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => adr_bus_5_IBUF, + ADR1 => adr_bus_4_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_6_IBUF, + O => dadrL_N15631_FROM + ); + dadrL_BU2350 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N15631_GROM + ); + dadrL_N15631_XUSED : X_BUF + port map ( + I => dadrL_N15631_FROM, + O => dadrL_N15631 + ); + dadrL_N15631_YUSED : X_BUF + port map ( + I => dadrL_N15631_GROM, + O => dadrL_N15632 + ); + dadrL_BU634 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N4556_FROM + ); + dadrL_BU631 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_5_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N4556_GROM + ); + dadrL_N4556_XUSED : X_BUF + port map ( + I => dadrL_N4556_FROM, + O => dadrL_N4556 + ); + dadrL_N4556_YUSED : X_BUF + port map ( + I => dadrL_N4556_GROM, + O => dadrL_N4555 + ); + dadrL_BU623 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N4485_FROM + ); + dadrL_BU620 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_7_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N4485_GROM + ); + dadrL_N4485_XUSED : X_BUF + port map ( + I => dadrL_N4485_FROM, + O => dadrL_N4485 + ); + dadrL_N4485_YUSED : X_BUF + port map ( + I => dadrL_N4485_GROM, + O => dadrL_N4484 + ); + dadrL_BU1844 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N12366_FROM + ); + dadrL_BU1841 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N12366_GROM + ); + dadrL_N12366_XUSED : X_BUF + port map ( + I => dadrL_N12366_FROM, + O => dadrL_N12366 + ); + dadrL_N12366_YUSED : X_BUF + port map ( + I => dadrL_N12366_GROM, + O => dadrL_N12365 + ); + dadrL_BU2383 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_0_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N15845_FROM + ); + dadrL_BU2380 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_6_IBUF, + O => dadrL_N15845_GROM + ); + dadrL_N15845_XUSED : X_BUF + port map ( + I => dadrL_N15845_FROM, + O => dadrL_N15845 + ); + dadrL_N15845_YUSED : X_BUF + port map ( + I => dadrL_N15845_GROM, + O => dadrL_N15844 + ); + dadrL_BU1833 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N12295_FROM + ); + dadrL_BU1830 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_5_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N12295_GROM + ); + dadrL_N12295_XUSED : X_BUF + port map ( + I => dadrL_N12295_FROM, + O => dadrL_N12295 + ); + dadrL_N12295_YUSED : X_BUF + port map ( + I => dadrL_N12295_GROM, + O => dadrL_N12294 + ); + dadrL_BU2369 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_7_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N15773_FROM + ); + dadrL_BU2372 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N15773_GROM + ); + dadrL_N15773_XUSED : X_BUF + port map ( + I => dadrL_N15773_FROM, + O => dadrL_N15773 + ); + dadrL_N15773_YUSED : X_BUF + port map ( + I => dadrL_N15773_GROM, + O => dadrL_N15774 + ); + dadrL_BU656 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N4698_FROM + ); + dadrL_BU653 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N4698_GROM + ); + dadrL_N4698_XUSED : X_BUF + port map ( + I => dadrL_N4698_FROM, + O => dadrL_N4698 + ); + dadrL_N4698_YUSED : X_BUF + port map ( + I => dadrL_N4698_GROM, + O => dadrL_N4697 + ); + dadrL_BU645 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N4627_FROM + ); + dadrL_BU642 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_7_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N4627_GROM + ); + dadrL_N4627_XUSED : X_BUF + port map ( + I => dadrL_N4627_FROM, + O => dadrL_N4627 + ); + dadrL_N4627_YUSED : X_BUF + port map ( + I => dadrL_N4627_GROM, + O => dadrL_N4626 + ); + dadrL_BU1866 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N12508_FROM + ); + dadrL_BU1863 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_7_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N12508_GROM + ); + dadrL_N12508_XUSED : X_BUF + port map ( + I => dadrL_N12508_FROM, + O => dadrL_N12508 + ); + dadrL_N12508_YUSED : X_BUF + port map ( + I => dadrL_N12508_GROM, + O => dadrL_N12507 + ); + dadrL_BU2405 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N15987_FROM + ); + dadrL_BU2402 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_4_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_6_IBUF, + O => dadrL_N15987_GROM + ); + dadrL_N15987_XUSED : X_BUF + port map ( + I => dadrL_N15987_FROM, + O => dadrL_N15987 + ); + dadrL_N15987_YUSED : X_BUF + port map ( + I => dadrL_N15987_GROM, + O => dadrL_N15986 + ); + dadrL_BU1855 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_0_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N12437_FROM + ); + dadrL_BU1852 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_5_IBUF, + ADR1 => adr_bus_4_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N12437_GROM + ); + dadrL_N12437_XUSED : X_BUF + port map ( + I => dadrL_N12437_FROM, + O => dadrL_N12437 + ); + dadrL_N12437_YUSED : X_BUF + port map ( + I => dadrL_N12437_GROM, + O => dadrL_N12436 + ); + dadrL_BU2394 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N15916_FROM + ); + dadrL_BU2391 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => adr_bus_5_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N15916_GROM + ); + dadrL_N15916_XUSED : X_BUF + port map ( + I => dadrL_N15916_FROM, + O => dadrL_N15916 + ); + dadrL_N15916_YUSED : X_BUF + port map ( + I => dadrL_N15916_GROM, + O => dadrL_N15915 + ); + dadrL_BU678 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_0_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N4840_FROM + ); + dadrL_BU675 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_6_IBUF, + O => dadrL_N4840_GROM + ); + dadrL_N4840_XUSED : X_BUF + port map ( + I => dadrL_N4840_FROM, + O => dadrL_N4840 + ); + dadrL_N4840_YUSED : X_BUF + port map ( + I => dadrL_N4840_GROM, + O => dadrL_N4839 + ); + dadrL_BU667 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N4769_FROM + ); + dadrL_BU664 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_5_IBUF, + ADR1 => adr_bus_4_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_6_IBUF, + O => dadrL_N4769_GROM + ); + dadrL_N4769_XUSED : X_BUF + port map ( + I => dadrL_N4769_FROM, + O => dadrL_N4769 + ); + dadrL_N4769_YUSED : X_BUF + port map ( + I => dadrL_N4769_GROM, + O => dadrL_N4768 + ); + dadrL_BU1888 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N12650_FROM + ); + dadrL_BU1885 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_7_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N12650_GROM + ); + dadrL_N12650_XUSED : X_BUF + port map ( + I => dadrL_N12650_FROM, + O => dadrL_N12650 + ); + dadrL_N12650_YUSED : X_BUF + port map ( + I => dadrL_N12650_GROM, + O => dadrL_N12649 + ); + dadrL_BU1877 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N12579_FROM + ); + dadrL_BU1874 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N12579_GROM + ); + dadrL_N12579_XUSED : X_BUF + port map ( + I => dadrL_N12579_FROM, + O => dadrL_N12579 + ); + dadrL_N12579_YUSED : X_BUF + port map ( + I => dadrL_N12579_GROM, + O => dadrL_N12578 + ); + dadrL_BU697 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_4_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N4981_FROM + ); + dadrL_BU700 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N4981_GROM + ); + dadrL_N4981_XUSED : X_BUF + port map ( + I => dadrL_N4981_FROM, + O => dadrL_N4981 + ); + dadrL_N4981_YUSED : X_BUF + port map ( + I => dadrL_N4981_GROM, + O => dadrL_N4982 + ); + dadrL_BU689 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_0_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N4911_FROM + ); + dadrL_BU686 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_5_IBUF, + ADR1 => adr_bus_7_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N4911_GROM + ); + dadrL_N4911_XUSED : X_BUF + port map ( + I => dadrL_N4911_FROM, + O => dadrL_N4911 + ); + dadrL_N4911_YUSED : X_BUF + port map ( + I => dadrL_N4911_GROM, + O => dadrL_N4910 + ); + dadrL_BU755 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N5337_FROM + ); + dadrL_BU752 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N5337_GROM + ); + dadrL_N5337_XUSED : X_BUF + port map ( + I => dadrL_N5337_FROM, + O => dadrL_N5337 + ); + dadrL_N5337_YUSED : X_BUF + port map ( + I => dadrL_N5337_GROM, + O => dadrL_N5336 + ); + dadrL_BU744 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N5266_FROM + ); + dadrL_BU741 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_7_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N5266_GROM + ); + dadrL_N5266_XUSED : X_BUF + port map ( + I => dadrL_N5266_FROM, + O => dadrL_N5266 + ); + dadrL_N5266_YUSED : X_BUF + port map ( + I => dadrL_N5266_GROM, + O => dadrL_N5265 + ); + dadrL_BU1907 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N12791_FROM + ); + dadrL_BU1910 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N12791_GROM + ); + dadrL_N12791_XUSED : X_BUF + port map ( + I => dadrL_N12791_FROM, + O => dadrL_N12791 + ); + dadrL_N12791_YUSED : X_BUF + port map ( + I => dadrL_N12791_GROM, + O => dadrL_N12792 + ); + dadrL_BU1899 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N12721_FROM + ); + dadrL_BU1896 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_4_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N12721_GROM + ); + dadrL_N12721_XUSED : X_BUF + port map ( + I => dadrL_N12721_FROM, + O => dadrL_N12721 + ); + dadrL_N12721_YUSED : X_BUF + port map ( + I => dadrL_N12721_GROM, + O => dadrL_N12720 + ); + dadrL_BU719 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_5_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N5123_FROM + ); + dadrL_BU722 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N5123_GROM + ); + dadrL_N5123_XUSED : X_BUF + port map ( + I => dadrL_N5123_FROM, + O => dadrL_N5123 + ); + dadrL_N5123_YUSED : X_BUF + port map ( + I => dadrL_N5123_GROM, + O => dadrL_N5124 + ); + dadrL_BU708 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N5052_FROM + ); + dadrL_BU711 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N5052_GROM + ); + dadrL_N5052_XUSED : X_BUF + port map ( + I => dadrL_N5052_FROM, + O => dadrL_N5052 + ); + dadrL_N5052_YUSED : X_BUF + port map ( + I => dadrL_N5052_GROM, + O => dadrL_N5053 + ); + dadrL_BU777 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N5479_FROM + ); + dadrL_BU774 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N5479_GROM + ); + dadrL_N5479_XUSED : X_BUF + port map ( + I => dadrL_N5479_FROM, + O => dadrL_N5479 + ); + dadrL_N5479_YUSED : X_BUF + port map ( + I => dadrL_N5479_GROM, + O => dadrL_N5478 + ); + dadrL_BU766 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_0_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N5408_FROM + ); + dadrL_BU763 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_4_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N5408_GROM + ); + dadrL_N5408_XUSED : X_BUF + port map ( + I => dadrL_N5408_FROM, + O => dadrL_N5408 + ); + dadrL_N5408_YUSED : X_BUF + port map ( + I => dadrL_N5408_GROM, + O => dadrL_N5407 + ); + dadrL_BU1929 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_4_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N12933_FROM + ); + dadrL_BU1932 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N12933_GROM + ); + dadrL_N12933_XUSED : X_BUF + port map ( + I => dadrL_N12933_FROM, + O => dadrL_N12933 + ); + dadrL_N12933_YUSED : X_BUF + port map ( + I => dadrL_N12933_GROM, + O => dadrL_N12934 + ); + dadrL_BU1918 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_7_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N12862_FROM + ); + dadrL_BU1921 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_0_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N12862_GROM + ); + dadrL_N12862_XUSED : X_BUF + port map ( + I => dadrL_N12862_FROM, + O => dadrL_N12862 + ); + dadrL_N12862_YUSED : X_BUF + port map ( + I => dadrL_N12862_GROM, + O => dadrL_N12863 + ); + dadrL_BU733 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N5195_FROM + ); + dadrL_BU730 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_5_IBUF, + ADR1 => adr_bus_4_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N5195_GROM + ); + dadrL_N5195_XUSED : X_BUF + port map ( + I => dadrL_N5195_FROM, + O => dadrL_N5195 + ); + dadrL_N5195_YUSED : X_BUF + port map ( + I => dadrL_N5195_GROM, + O => dadrL_N5194 + ); + dadrL_BU799 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N5621_FROM + ); + dadrL_BU796 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N5621_GROM + ); + dadrL_N5621_XUSED : X_BUF + port map ( + I => dadrL_N5621_FROM, + O => dadrL_N5621 + ); + dadrL_N5621_YUSED : X_BUF + port map ( + I => dadrL_N5621_GROM, + O => dadrL_N5620 + ); + dadrL_BU788 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_0_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N5550_FROM + ); + dadrL_BU785 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N5550_GROM + ); + dadrL_N5550_XUSED : X_BUF + port map ( + I => dadrL_N5550_FROM, + O => dadrL_N5550 + ); + dadrL_N5550_YUSED : X_BUF + port map ( + I => dadrL_N5550_GROM, + O => dadrL_N5549 + ); + dadrL_BU1954 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N13076_FROM + ); + dadrL_BU1951 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_4_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N13076_GROM + ); + dadrL_N13076_XUSED : X_BUF + port map ( + I => dadrL_N13076_FROM, + O => dadrL_N13076 + ); + dadrL_N13076_YUSED : X_BUF + port map ( + I => dadrL_N13076_GROM, + O => dadrL_N13075 + ); + dadrL_BU1943 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_0_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N13005_FROM + ); + dadrL_BU1940 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N13005_GROM + ); + dadrL_N13005_XUSED : X_BUF + port map ( + I => dadrL_N13005_FROM, + O => dadrL_N13005 + ); + dadrL_N13005_YUSED : X_BUF + port map ( + I => dadrL_N13005_GROM, + O => dadrL_N13004 + ); + dadrL_BU818 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_5_IBUF, + ADR1 => adr_bus_4_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N5762_FROM + ); + dadrL_BU821 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N5762_GROM + ); + dadrL_N5762_XUSED : X_BUF + port map ( + I => dadrL_N5762_FROM, + O => dadrL_N5762 + ); + dadrL_N5762_YUSED : X_BUF + port map ( + I => dadrL_N5762_GROM, + O => dadrL_N5763 + ); + dadrL_BU807 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N5691_FROM + ); + dadrL_BU810 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N5691_GROM + ); + dadrL_N5691_XUSED : X_BUF + port map ( + I => dadrL_N5691_FROM, + O => dadrL_N5691 + ); + dadrL_N5691_YUSED : X_BUF + port map ( + I => dadrL_N5691_GROM, + O => dadrL_N5692 + ); + dadrL_BU1976 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_0_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N13218_FROM + ); + dadrL_BU1973 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_7_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_6_IBUF, + O => dadrL_N13218_GROM + ); + dadrL_N13218_XUSED : X_BUF + port map ( + I => dadrL_N13218_FROM, + O => dadrL_N13218 + ); + dadrL_N13218_YUSED : X_BUF + port map ( + I => dadrL_N13218_GROM, + O => dadrL_N13217 + ); + dadrL_BU1965 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N13147_FROM + ); + dadrL_BU1962 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_6_IBUF, + O => dadrL_N13147_GROM + ); + dadrL_N13147_XUSED : X_BUF + port map ( + I => dadrL_N13147_FROM, + O => dadrL_N13147 + ); + dadrL_N13147_YUSED : X_BUF + port map ( + I => dadrL_N13147_GROM, + O => dadrL_N13146 + ); + dadrL_BU843 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N5905_FROM + ); + dadrL_BU840 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N5905_GROM + ); + dadrL_N5905_XUSED : X_BUF + port map ( + I => dadrL_N5905_FROM, + O => dadrL_N5905 + ); + dadrL_N5905_YUSED : X_BUF + port map ( + I => dadrL_N5905_GROM, + O => dadrL_N5904 + ); + dadrL_BU829 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N5833_FROM + ); + dadrL_BU832 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N5833_GROM + ); + dadrL_N5833_XUSED : X_BUF + port map ( + I => dadrL_N5833_FROM, + O => dadrL_N5833 + ); + dadrL_N5833_YUSED : X_BUF + port map ( + I => dadrL_N5833_GROM, + O => dadrL_N5834 + ); + dadrL_BU1998 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N13360_FROM + ); + dadrL_BU1995 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N13360_GROM + ); + dadrL_N13360_XUSED : X_BUF + port map ( + I => dadrL_N13360_FROM, + O => dadrL_N13360 + ); + dadrL_N13360_YUSED : X_BUF + port map ( + I => dadrL_N13360_GROM, + O => dadrL_N13359 + ); + dadrL_BU1987 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_0_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N13289_FROM + ); + dadrL_BU1984 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_4_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N13289_GROM + ); + dadrL_N13289_XUSED : X_BUF + port map ( + I => dadrL_N13289_FROM, + O => dadrL_N13289 + ); + dadrL_N13289_YUSED : X_BUF + port map ( + I => dadrL_N13289_GROM, + O => dadrL_N13288 + ); + dadrL_BU2787 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_4_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N18471_FROM + ); + dadrL_BU2790 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_0_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N18471_GROM + ); + dadrL_N18471_XUSED : X_BUF + port map ( + I => dadrL_N18471_FROM, + O => dadrL_N18471 + ); + dadrL_N18471_YUSED : X_BUF + port map ( + I => dadrL_N18471_GROM, + O => dadrL_N18472 + ); + dadrL_BU2779 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N18401_FROM + ); + dadrL_BU2776 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_5_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N18401_GROM + ); + dadrL_N18401_XUSED : X_BUF + port map ( + I => dadrL_N18401_FROM, + O => dadrL_N18401 + ); + dadrL_N18401_YUSED : X_BUF + port map ( + I => dadrL_N18401_GROM, + O => dadrL_N18400 + ); + dadrL_BU865 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N6047_FROM + ); + dadrL_BU862 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_5_IBUF, + ADR1 => adr_bus_4_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_6_IBUF, + O => dadrL_N6047_GROM + ); + dadrL_N6047_XUSED : X_BUF + port map ( + I => dadrL_N6047_FROM, + O => dadrL_N6047 + ); + dadrL_N6047_YUSED : X_BUF + port map ( + I => dadrL_N6047_GROM, + O => dadrL_N6046 + ); + dadrL_BU854 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N5976_FROM + ); + dadrL_BU851 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_5_IBUF, + ADR1 => adr_bus_4_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_6_IBUF, + O => dadrL_N5976_GROM + ); + dadrL_N5976_XUSED : X_BUF + port map ( + I => dadrL_N5976_FROM, + O => dadrL_N5976 + ); + dadrL_N5976_YUSED : X_BUF + port map ( + I => dadrL_N5976_GROM, + O => dadrL_N5975 + ); + dadrL_BU1478 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_6_IBUF, + O => dadrL_N10022_FROM + ); + dadrL_BU1481 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N10022_GROM + ); + dadrL_N10022_XUSED : X_BUF + port map ( + I => dadrL_N10022_FROM, + O => dadrL_N10022 + ); + dadrL_N10022_YUSED : X_BUF + port map ( + I => dadrL_N10022_GROM, + O => dadrL_N10023 + ); + dadrL_BU2017 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_4_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N13501_FROM + ); + dadrL_BU2020 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N13501_GROM + ); + dadrL_N13501_XUSED : X_BUF + port map ( + I => dadrL_N13501_FROM, + O => dadrL_N13501 + ); + dadrL_N13501_YUSED : X_BUF + port map ( + I => dadrL_N13501_GROM, + O => dadrL_N13502 + ); + dadrL_BU1467 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_5_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N9951_FROM + ); + dadrL_BU1470 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N9951_GROM + ); + dadrL_N9951_XUSED : X_BUF + port map ( + I => dadrL_N9951_FROM, + O => dadrL_N9951 + ); + dadrL_N9951_YUSED : X_BUF + port map ( + I => dadrL_N9951_GROM, + O => dadrL_N9952 + ); + dadrL_BU2064 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N13786_FROM + ); + dadrL_BU2061 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_7_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N13786_GROM + ); + dadrL_N13786_XUSED : X_BUF + port map ( + I => dadrL_N13786_FROM, + O => dadrL_N13786 + ); + dadrL_N13786_YUSED : X_BUF + port map ( + I => dadrL_N13786_GROM, + O => dadrL_N13785 + ); + dadrL_BU2009 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N13431_FROM + ); + dadrL_BU2006 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_5_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N13431_GROM + ); + dadrL_N13431_XUSED : X_BUF + port map ( + I => dadrL_N13431_FROM, + O => dadrL_N13431 + ); + dadrL_N13431_YUSED : X_BUF + port map ( + I => dadrL_N13431_GROM, + O => dadrL_N13430 + ); + dadrL_BU2053 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N13715_FROM + ); + dadrL_BU2050 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N13715_GROM + ); + dadrL_N13715_XUSED : X_BUF + port map ( + I => dadrL_N13715_FROM, + O => dadrL_N13715 + ); + dadrL_N13715_YUSED : X_BUF + port map ( + I => dadrL_N13715_GROM, + O => dadrL_N13714 + ); + dadrL_BU2809 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N18613_FROM + ); + dadrL_BU2812 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N18613_GROM + ); + dadrL_N18613_XUSED : X_BUF + port map ( + I => dadrL_N18613_FROM, + O => dadrL_N18613 + ); + dadrL_N18613_YUSED : X_BUF + port map ( + I => dadrL_N18613_GROM, + O => dadrL_N18614 + ); + dadrL_BU2798 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_7_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N18542_FROM + ); + dadrL_BU2801 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N18542_GROM + ); + dadrL_N18542_XUSED : X_BUF + port map ( + I => dadrL_N18542_FROM, + O => dadrL_N18542 + ); + dadrL_N18542_YUSED : X_BUF + port map ( + I => dadrL_N18542_GROM, + O => dadrL_N18543 + ); + dadrL_BU1338 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N9100_FROM + ); + dadrL_BU1335 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_7_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N9100_GROM + ); + dadrL_N9100_XUSED : X_BUF + port map ( + I => dadrL_N9100_FROM, + O => dadrL_N9100 + ); + dadrL_N9100_YUSED : X_BUF + port map ( + I => dadrL_N9100_GROM, + O => dadrL_N9099 + ); + dadrL_BU887 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N6189_FROM + ); + dadrL_BU884 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_6_IBUF, + O => dadrL_N6189_GROM + ); + dadrL_N6189_XUSED : X_BUF + port map ( + I => dadrL_N6189_FROM, + O => dadrL_N6189 + ); + dadrL_N6189_YUSED : X_BUF + port map ( + I => dadrL_N6189_GROM, + O => dadrL_N6188 + ); + dadrL_BU1327 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_0_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N9029_FROM + ); + dadrL_BU1324 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_5_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N9029_GROM + ); + dadrL_N9029_XUSED : X_BUF + port map ( + I => dadrL_N9029_FROM, + O => dadrL_N9029 + ); + dadrL_N9029_YUSED : X_BUF + port map ( + I => dadrL_N9029_GROM, + O => dadrL_N9028 + ); + dadrL_BU876 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N6118_FROM + ); + dadrL_BU873 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_7_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N6118_GROM + ); + dadrL_N6118_XUSED : X_BUF + port map ( + I => dadrL_N6118_FROM, + O => dadrL_N6118 + ); + dadrL_N6118_YUSED : X_BUF + port map ( + I => dadrL_N6118_GROM, + O => dadrL_N6117 + ); + dadrL_BU1503 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N10165_FROM + ); + dadrL_BU1500 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N10165_GROM + ); + dadrL_N10165_XUSED : X_BUF + port map ( + I => dadrL_N10165_FROM, + O => dadrL_N10165 + ); + dadrL_N10165_YUSED : X_BUF + port map ( + I => dadrL_N10165_GROM, + O => dadrL_N10164 + ); + dadrL_BU2039 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_7_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N13643_FROM + ); + dadrL_BU2042 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N13643_GROM + ); + dadrL_N13643_XUSED : X_BUF + port map ( + I => dadrL_N13643_FROM, + O => dadrL_N13643 + ); + dadrL_N13643_YUSED : X_BUF + port map ( + I => dadrL_N13643_GROM, + O => dadrL_N13644 + ); + dadrL_BU1489 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_4_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N10093_FROM + ); + dadrL_BU1492 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N10093_GROM + ); + dadrL_N10093_XUSED : X_BUF + port map ( + I => dadrL_N10093_FROM, + O => dadrL_N10093 + ); + dadrL_N10093_YUSED : X_BUF + port map ( + I => dadrL_N10093_GROM, + O => dadrL_N10094 + ); + dadrL_BU2086 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_0_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N13928_FROM + ); + dadrL_BU2083 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_5_IBUF, + ADR1 => adr_bus_7_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_6_IBUF, + O => dadrL_N13928_GROM + ); + dadrL_N13928_XUSED : X_BUF + port map ( + I => dadrL_N13928_FROM, + O => dadrL_N13928 + ); + dadrL_N13928_YUSED : X_BUF + port map ( + I => dadrL_N13928_GROM, + O => dadrL_N13927 + ); + dadrL_BU2028 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N13572_FROM + ); + dadrL_BU2031 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_0_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N13572_GROM + ); + dadrL_N13572_XUSED : X_BUF + port map ( + I => dadrL_N13572_FROM, + O => dadrL_N13572 + ); + dadrL_N13572_YUSED : X_BUF + port map ( + I => dadrL_N13572_GROM, + O => dadrL_N13573 + ); + dadrL_BU2075 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N13857_FROM + ); + dadrL_BU2072 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_7_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_6_IBUF, + O => dadrL_N13857_GROM + ); + dadrL_N13857_XUSED : X_BUF + port map ( + I => dadrL_N13857_FROM, + O => dadrL_N13857 + ); + dadrL_N13857_YUSED : X_BUF + port map ( + I => dadrL_N13857_GROM, + O => dadrL_N13856 + ); + dadrL_BU2823 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N18685_FROM + ); + dadrL_BU2820 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N18685_GROM + ); + dadrL_N18685_XUSED : X_BUF + port map ( + I => dadrL_N18685_FROM, + O => dadrL_N18685 + ); + dadrL_N18685_YUSED : X_BUF + port map ( + I => dadrL_N18685_GROM, + O => dadrL_N18684 + ); + dadrL_BU1357 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N9241_FROM + ); + dadrL_BU1360 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N9241_GROM + ); + dadrL_N9241_XUSED : X_BUF + port map ( + I => dadrL_N9241_FROM, + O => dadrL_N9241 + ); + dadrL_N9241_YUSED : X_BUF + port map ( + I => dadrL_N9241_GROM, + O => dadrL_N9242 + ); + dadrL_BU909 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N6331_FROM + ); + dadrL_BU906 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N6331_GROM + ); + dadrL_N6331_XUSED : X_BUF + port map ( + I => dadrL_N6331_FROM, + O => dadrL_N6331 + ); + dadrL_N6331_YUSED : X_BUF + port map ( + I => dadrL_N6331_GROM, + O => dadrL_N6330 + ); + dadrL_BU1349 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N9171_FROM + ); + dadrL_BU1346 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N9171_GROM + ); + dadrL_N9171_XUSED : X_BUF + port map ( + I => dadrL_N9171_FROM, + O => dadrL_N9171 + ); + dadrL_N9171_YUSED : X_BUF + port map ( + I => dadrL_N9171_GROM, + O => dadrL_N9170 + ); + dadrL_BU898 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_0_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N6260_FROM + ); + dadrL_BU895 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_4_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N6260_GROM + ); + dadrL_N6260_XUSED : X_BUF + port map ( + I => dadrL_N6260_FROM, + O => dadrL_N6260 + ); + dadrL_N6260_YUSED : X_BUF + port map ( + I => dadrL_N6260_GROM, + O => dadrL_N6259 + ); + dadrL_BU1525 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_0_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N10307_FROM + ); + dadrL_BU1522 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_7_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N10307_GROM + ); + dadrL_N10307_XUSED : X_BUF + port map ( + I => dadrL_N10307_FROM, + O => dadrL_N10307 + ); + dadrL_N10307_YUSED : X_BUF + port map ( + I => dadrL_N10307_GROM, + O => dadrL_N10306 + ); + dadrL_BU1514 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_0_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N10236_FROM + ); + dadrL_BU1511 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N10236_GROM + ); + dadrL_N10236_XUSED : X_BUF + port map ( + I => dadrL_N10236_FROM, + O => dadrL_N10236 + ); + dadrL_N10236_YUSED : X_BUF + port map ( + I => dadrL_N10236_GROM, + O => dadrL_N10235 + ); + dadrL_BU2108 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N14070_FROM + ); + dadrL_BU2105 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N14070_GROM + ); + dadrL_N14070_XUSED : X_BUF + port map ( + I => dadrL_N14070_FROM, + O => dadrL_N14070 + ); + dadrL_N14070_YUSED : X_BUF + port map ( + I => dadrL_N14070_GROM, + O => dadrL_N14069 + ); + dadrL_BU2097 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N13999_FROM + ); + dadrL_BU2094 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_6_IBUF, + O => dadrL_N13999_GROM + ); + dadrL_N13999_XUSED : X_BUF + port map ( + I => dadrL_N13999_FROM, + O => dadrL_N13999 + ); + dadrL_N13999_YUSED : X_BUF + port map ( + I => dadrL_N13999_GROM, + O => dadrL_N13998 + ); + dadrL_BU1379 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_6_IBUF, + O => dadrL_N9383_FROM + ); + dadrL_BU1382 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N9383_GROM + ); + dadrL_N9383_XUSED : X_BUF + port map ( + I => dadrL_N9383_FROM, + O => dadrL_N9383 + ); + dadrL_N9383_YUSED : X_BUF + port map ( + I => dadrL_N9383_GROM, + O => dadrL_N9384 + ); + dadrL_BU928 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_4_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N6472_FROM + ); + dadrL_BU931 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N6472_GROM + ); + dadrL_N6472_XUSED : X_BUF + port map ( + I => dadrL_N6472_FROM, + O => dadrL_N6472 + ); + dadrL_N6472_YUSED : X_BUF + port map ( + I => dadrL_N6472_GROM, + O => dadrL_N6473 + ); + dadrL_BU389 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_7_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N2993_FROM + ); + dadrL_BU392 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_0_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N2993_GROM + ); + dadrL_N2993_XUSED : X_BUF + port map ( + I => dadrL_N2993_FROM, + O => dadrL_N2993 + ); + dadrL_N2993_YUSED : X_BUF + port map ( + I => dadrL_N2993_GROM, + O => dadrL_N2994 + ); + dadrL_BU1368 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_5_IBUF, + ADR1 => adr_bus_7_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_6_IBUF, + O => dadrL_N9312_FROM + ); + dadrL_BU1371 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N9312_GROM + ); + dadrL_N9312_XUSED : X_BUF + port map ( + I => dadrL_N9312_FROM, + O => dadrL_N9312 + ); + dadrL_N9312_YUSED : X_BUF + port map ( + I => dadrL_N9312_GROM, + O => dadrL_N9313 + ); + dadrL_BU917 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N6401_FROM + ); + dadrL_BU920 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N6401_GROM + ); + dadrL_N6401_XUSED : X_BUF + port map ( + I => dadrL_N6401_FROM, + O => dadrL_N6401 + ); + dadrL_N6401_YUSED : X_BUF + port map ( + I => dadrL_N6401_GROM, + O => dadrL_N6402 + ); + dadrL_BU378 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_5_IBUF, + ADR1 => adr_bus_4_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_6_IBUF, + O => dadrL_N2922_FROM + ); + dadrL_BU381 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N2922_GROM + ); + dadrL_N2922_XUSED : X_BUF + port map ( + I => dadrL_N2922_FROM, + O => dadrL_N2922 + ); + dadrL_N2922_YUSED : X_BUF + port map ( + I => dadrL_N2922_GROM, + O => dadrL_N2923 + ); + dadrL_BU1547 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N10449_FROM + ); + dadrL_BU1544 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N10449_GROM + ); + dadrL_N10449_XUSED : X_BUF + port map ( + I => dadrL_N10449_FROM, + O => dadrL_N10449 + ); + dadrL_N10449_YUSED : X_BUF + port map ( + I => dadrL_N10449_GROM, + O => dadrL_N10448 + ); + dadrL_BU1536 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N10378_FROM + ); + dadrL_BU1533 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_4_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_6_IBUF, + O => dadrL_N10378_GROM + ); + dadrL_N10378_XUSED : X_BUF + port map ( + I => dadrL_N10378_FROM, + O => dadrL_N10378 + ); + dadrL_N10378_YUSED : X_BUF + port map ( + I => dadrL_N10378_GROM, + O => dadrL_N10377 + ); + dadrL_BU2127 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => adr_bus_5_IBUF, + ADR1 => adr_bus_4_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N14211_FROM + ); + dadrL_BU2130 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N14211_GROM + ); + dadrL_N14211_XUSED : X_BUF + port map ( + I => dadrL_N14211_FROM, + O => dadrL_N14211 + ); + dadrL_N14211_YUSED : X_BUF + port map ( + I => dadrL_N14211_GROM, + O => dadrL_N14212 + ); + dadrL_BU2119 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N14141_FROM + ); + dadrL_BU2116 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_5_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N14141_GROM + ); + dadrL_N14141_XUSED : X_BUF + port map ( + I => dadrL_N14141_FROM, + O => dadrL_N14141 + ); + dadrL_N14141_YUSED : X_BUF + port map ( + I => dadrL_N14141_GROM, + O => dadrL_N14140 + ); + dadrL_BU1404 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N9526_FROM + ); + dadrL_BU1401 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_5_IBUF, + ADR1 => adr_bus_7_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N9526_GROM + ); + dadrL_N9526_XUSED : X_BUF + port map ( + I => dadrL_N9526_FROM, + O => dadrL_N9526 + ); + dadrL_N9526_YUSED : X_BUF + port map ( + I => dadrL_N9526_GROM, + O => dadrL_N9525 + ); + dadrL_BU953 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N6615_FROM + ); + dadrL_BU950 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_7_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N6615_GROM + ); + dadrL_N6615_XUSED : X_BUF + port map ( + I => dadrL_N6615_FROM, + O => dadrL_N6615 + ); + dadrL_N6615_YUSED : X_BUF + port map ( + I => dadrL_N6615_GROM, + O => dadrL_N6614 + ); + dadrL_BU414 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N3136_FROM + ); + dadrL_BU411 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N3136_GROM + ); + dadrL_N3136_XUSED : X_BUF + port map ( + I => dadrL_N3136_FROM, + O => dadrL_N3136 + ); + dadrL_N3136_YUSED : X_BUF + port map ( + I => dadrL_N3136_GROM, + O => dadrL_N3135 + ); + dadrL_BU1393 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N9455_FROM + ); + dadrL_BU1390 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_7_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_6_IBUF, + O => dadrL_N9455_GROM + ); + dadrL_N9455_XUSED : X_BUF + port map ( + I => dadrL_N9455_FROM, + O => dadrL_N9455 + ); + dadrL_N9455_YUSED : X_BUF + port map ( + I => dadrL_N9455_GROM, + O => dadrL_N9454 + ); + dadrL_BU939 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N6543_FROM + ); + dadrL_BU942 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N6543_GROM + ); + dadrL_N6543_XUSED : X_BUF + port map ( + I => dadrL_N6543_FROM, + O => dadrL_N6543 + ); + dadrL_N6543_YUSED : X_BUF + port map ( + I => dadrL_N6543_GROM, + O => dadrL_N6544 + ); + dadrL_BU403 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_0_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N3065_FROM + ); + dadrL_BU400 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_4_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_6_IBUF, + O => dadrL_N3065_GROM + ); + dadrL_N3065_XUSED : X_BUF + port map ( + I => dadrL_N3065_FROM, + O => dadrL_N3065 + ); + dadrL_N3065_YUSED : X_BUF + port map ( + I => dadrL_N3065_GROM, + O => dadrL_N3064 + ); + dadrL_BU1569 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N10591_FROM + ); + dadrL_BU1566 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N10591_GROM + ); + dadrL_N10591_XUSED : X_BUF + port map ( + I => dadrL_N10591_FROM, + O => dadrL_N10591 + ); + dadrL_N10591_YUSED : X_BUF + port map ( + I => dadrL_N10591_GROM, + O => dadrL_N10590 + ); + dadrL_BU1558 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N10520_FROM + ); + dadrL_BU1555 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_5_IBUF, + ADR1 => adr_bus_7_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N10520_GROM + ); + dadrL_N10520_XUSED : X_BUF + port map ( + I => dadrL_N10520_FROM, + O => dadrL_N10520 + ); + dadrL_N10520_YUSED : X_BUF + port map ( + I => dadrL_N10520_GROM, + O => dadrL_N10519 + ); + dadrL_BU2149 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_4_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N14353_FROM + ); + dadrL_BU2152 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N14353_GROM + ); + dadrL_N14353_XUSED : X_BUF + port map ( + I => dadrL_N14353_FROM, + O => dadrL_N14353 + ); + dadrL_N14353_YUSED : X_BUF + port map ( + I => dadrL_N14353_GROM, + O => dadrL_N14354 + ); + dadrL_BU2138 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => adr_bus_5_IBUF, + ADR1 => adr_bus_7_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_6_IBUF, + O => dadrL_N14282_FROM + ); + dadrL_BU2141 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N14282_GROM + ); + dadrL_N14282_XUSED : X_BUF + port map ( + I => dadrL_N14282_FROM, + O => dadrL_N14282 + ); + dadrL_N14282_YUSED : X_BUF + port map ( + I => dadrL_N14282_GROM, + O => dadrL_N14283 + ); + dadrL_BU1426 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N9668_FROM + ); + dadrL_BU1423 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_4_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N9668_GROM + ); + dadrL_N9668_XUSED : X_BUF + port map ( + I => dadrL_N9668_FROM, + O => dadrL_N9668 + ); + dadrL_N9668_YUSED : X_BUF + port map ( + I => dadrL_N9668_GROM, + O => dadrL_N9667 + ); + dadrL_BU436 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N3278_FROM + ); + dadrL_BU433 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_4_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_6_IBUF, + O => dadrL_N3278_GROM + ); + dadrL_N3278_XUSED : X_BUF + port map ( + I => dadrL_N3278_FROM, + O => dadrL_N3278 + ); + dadrL_N3278_YUSED : X_BUF + port map ( + I => dadrL_N3278_GROM, + O => dadrL_N3277 + ); + dadrL_BU1415 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N9597_FROM + ); + dadrL_BU1412 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N9597_GROM + ); + dadrL_N9597_XUSED : X_BUF + port map ( + I => dadrL_N9597_FROM, + O => dadrL_N9597 + ); + dadrL_N9597_YUSED : X_BUF + port map ( + I => dadrL_N9597_GROM, + O => dadrL_N9596 + ); + dadrL_BU425 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_0_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N3207_FROM + ); + dadrL_BU422 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N3207_GROM + ); + dadrL_N3207_XUSED : X_BUF + port map ( + I => dadrL_N3207_FROM, + O => dadrL_N3207 + ); + dadrL_N3207_YUSED : X_BUF + port map ( + I => dadrL_N3207_GROM, + O => dadrL_N3206 + ); + dadrL_BU1588 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N10732_FROM + ); + dadrL_BU1591 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N10732_GROM + ); + dadrL_N10732_XUSED : X_BUF + port map ( + I => dadrL_N10732_FROM, + O => dadrL_N10732 + ); + dadrL_N10732_YUSED : X_BUF + port map ( + I => dadrL_N10732_GROM, + O => dadrL_N10733 + ); + dadrL_BU1577 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N10661_FROM + ); + dadrL_BU1580 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N10661_GROM + ); + dadrL_N10661_XUSED : X_BUF + port map ( + I => dadrL_N10661_FROM, + O => dadrL_N10661 + ); + dadrL_N10661_YUSED : X_BUF + port map ( + I => dadrL_N10661_GROM, + O => dadrL_N10662 + ); + dadrL_BU2174 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_0_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N14496_FROM + ); + dadrL_BU2171 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_5_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N14496_GROM + ); + dadrL_N14496_XUSED : X_BUF + port map ( + I => dadrL_N14496_FROM, + O => dadrL_N14496 + ); + dadrL_N14496_YUSED : X_BUF + port map ( + I => dadrL_N14496_GROM, + O => dadrL_N14495 + ); + dadrL_BU2163 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_0_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N14425_FROM + ); + dadrL_BU2160 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_7_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N14425_GROM + ); + dadrL_N14425_XUSED : X_BUF + port map ( + I => dadrL_N14425_FROM, + O => dadrL_N14425 + ); + dadrL_N14425_YUSED : X_BUF + port map ( + I => dadrL_N14425_GROM, + O => dadrL_N14424 + ); + dadrL_BU1448 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N9810_FROM + ); + dadrL_BU1445 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_5_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N9810_GROM + ); + dadrL_N9810_XUSED : X_BUF + port map ( + I => dadrL_N9810_FROM, + O => dadrL_N9810 + ); + dadrL_N9810_YUSED : X_BUF + port map ( + I => dadrL_N9810_GROM, + O => dadrL_N9809 + ); + dadrL_BU975 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N6757_FROM + ); + dadrL_BU972 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N6757_GROM + ); + dadrL_N6757_XUSED : X_BUF + port map ( + I => dadrL_N6757_FROM, + O => dadrL_N6757 + ); + dadrL_N6757_YUSED : X_BUF + port map ( + I => dadrL_N6757_GROM, + O => dadrL_N6756 + ); + dadrL_BU458 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N3420_FROM + ); + dadrL_BU455 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N3420_GROM + ); + dadrL_N3420_XUSED : X_BUF + port map ( + I => dadrL_N3420_FROM, + O => dadrL_N3420 + ); + dadrL_N3420_YUSED : X_BUF + port map ( + I => dadrL_N3420_GROM, + O => dadrL_N3419 + ); + dadrL_BU1437 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N9739_FROM + ); + dadrL_BU1434 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N9739_GROM + ); + dadrL_N9739_XUSED : X_BUF + port map ( + I => dadrL_N9739_FROM, + O => dadrL_N9739 + ); + dadrL_N9739_YUSED : X_BUF + port map ( + I => dadrL_N9739_GROM, + O => dadrL_N9738 + ); + dadrL_BU964 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N6686_FROM + ); + dadrL_BU961 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N6686_GROM + ); + dadrL_N6686_XUSED : X_BUF + port map ( + I => dadrL_N6686_FROM, + O => dadrL_N6686 + ); + dadrL_N6686_YUSED : X_BUF + port map ( + I => dadrL_N6686_GROM, + O => dadrL_N6685 + ); + dadrL_BU447 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N3349_FROM + ); + dadrL_BU444 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N3349_GROM + ); + dadrL_N3349_XUSED : X_BUF + port map ( + I => dadrL_N3349_FROM, + O => dadrL_N3349 + ); + dadrL_N3349_YUSED : X_BUF + port map ( + I => dadrL_N3349_GROM, + O => dadrL_N3348 + ); + dadrL_BU1613 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N10875_FROM + ); + dadrL_BU1610 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N10875_GROM + ); + dadrL_N10875_XUSED : X_BUF + port map ( + I => dadrL_N10875_FROM, + O => dadrL_N10875 + ); + dadrL_N10875_YUSED : X_BUF + port map ( + I => dadrL_N10875_GROM, + O => dadrL_N10874 + ); + dadrL_BU1599 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_7_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_6_IBUF, + O => dadrL_N10803_FROM + ); + dadrL_BU1602 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N10803_GROM + ); + dadrL_N10803_XUSED : X_BUF + port map ( + I => dadrL_N10803_FROM, + O => dadrL_N10803 + ); + dadrL_N10803_YUSED : X_BUF + port map ( + I => dadrL_N10803_GROM, + O => dadrL_N10804 + ); + dadrL_BU2185 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N14567_FROM + ); + dadrL_BU2182 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_4_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N14567_GROM + ); + dadrL_N14567_XUSED : X_BUF + port map ( + I => dadrL_N14567_FROM, + O => dadrL_N14567 + ); + dadrL_N14567_YUSED : X_BUF + port map ( + I => dadrL_N14567_GROM, + O => dadrL_N14566 + ); + dadrL_BU249 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N2071_FROM + ); + dadrL_BU246 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_6_IBUF, + O => dadrL_N2071_GROM + ); + dadrL_N2071_XUSED : X_BUF + port map ( + I => dadrL_N2071_FROM, + O => dadrL_N2071 + ); + dadrL_N2071_YUSED : X_BUF + port map ( + I => dadrL_N2071_GROM, + O => dadrL_N2070 + ); + dadrL_BU238 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_0_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N2000_FROM + ); + dadrL_BU235 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_5_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N2000_GROM + ); + dadrL_N2000_XUSED : X_BUF + port map ( + I => dadrL_N2000_FROM, + O => dadrL_N2000 + ); + dadrL_N2000_YUSED : X_BUF + port map ( + I => dadrL_N2000_GROM, + O => dadrL_N1999 + ); + dadrL_BU997 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N6899_FROM + ); + dadrL_BU994 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_6_IBUF, + O => dadrL_N6899_GROM + ); + dadrL_N6899_XUSED : X_BUF + port map ( + I => dadrL_N6899_FROM, + O => dadrL_N6899 + ); + dadrL_N6899_YUSED : X_BUF + port map ( + I => dadrL_N6899_GROM, + O => dadrL_N6898 + ); + dadrL_BU477 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_7_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N3561_FROM + ); + dadrL_BU480 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N3561_GROM + ); + dadrL_N3561_XUSED : X_BUF + port map ( + I => dadrL_N3561_FROM, + O => dadrL_N3561 + ); + dadrL_N3561_YUSED : X_BUF + port map ( + I => dadrL_N3561_GROM, + O => dadrL_N3562 + ); + dadrL_BU1459 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N9881_FROM + ); + dadrL_BU1456 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N9881_GROM + ); + dadrL_N9881_XUSED : X_BUF + port map ( + I => dadrL_N9881_FROM, + O => dadrL_N9881 + ); + dadrL_N9881_YUSED : X_BUF + port map ( + I => dadrL_N9881_GROM, + O => dadrL_N9880 + ); + dadrL_BU986 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N6828_FROM + ); + dadrL_BU983 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_6_IBUF, + O => dadrL_N6828_GROM + ); + dadrL_N6828_XUSED : X_BUF + port map ( + I => dadrL_N6828_FROM, + O => dadrL_N6828 + ); + dadrL_N6828_YUSED : X_BUF + port map ( + I => dadrL_N6828_GROM, + O => dadrL_N6827 + ); + dadrL_BU469 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N3491_FROM + ); + dadrL_BU466 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_4_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N3491_GROM + ); + dadrL_N3491_XUSED : X_BUF + port map ( + I => dadrL_N3491_FROM, + O => dadrL_N3491 + ); + dadrL_N3491_YUSED : X_BUF + port map ( + I => dadrL_N3491_GROM, + O => dadrL_N3490 + ); + dadrL_BU1635 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N11017_FROM + ); + dadrL_BU1632 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_7_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_6_IBUF, + O => dadrL_N11017_GROM + ); + dadrL_N11017_XUSED : X_BUF + port map ( + I => dadrL_N11017_FROM, + O => dadrL_N11017 + ); + dadrL_N11017_YUSED : X_BUF + port map ( + I => dadrL_N11017_GROM, + O => dadrL_N11016 + ); + dadrL_BU1624 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N10946_FROM + ); + dadrL_BU1621 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N10946_GROM + ); + dadrL_N10946_XUSED : X_BUF + port map ( + I => dadrL_N10946_FROM, + O => dadrL_N10946 + ); + dadrL_N10946_YUSED : X_BUF + port map ( + I => dadrL_N10946_GROM, + O => dadrL_N10945 + ); + dadrL_BU2567 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_7_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_6_IBUF, + O => dadrL_N17051_FROM + ); + dadrL_BU2570 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N17051_GROM + ); + dadrL_N17051_XUSED : X_BUF + port map ( + I => dadrL_N17051_FROM, + O => dadrL_N17051 + ); + dadrL_N17051_YUSED : X_BUF + port map ( + I => dadrL_N17051_GROM, + O => dadrL_N17052 + ); + dadrL_BU268 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N2212_FROM + ); + dadrL_BU271 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N2212_GROM + ); + dadrL_N2212_XUSED : X_BUF + port map ( + I => dadrL_N2212_FROM, + O => dadrL_N2212 + ); + dadrL_N2212_YUSED : X_BUF + port map ( + I => dadrL_N2212_GROM, + O => dadrL_N2213 + ); + dadrL_BU2559 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N16981_FROM + ); + dadrL_BU2556 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_5_IBUF, + ADR1 => adr_bus_4_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N16981_GROM + ); + dadrL_N16981_XUSED : X_BUF + port map ( + I => dadrL_N16981_FROM, + O => dadrL_N16981 + ); + dadrL_N16981_YUSED : X_BUF + port map ( + I => dadrL_N16981_GROM, + O => dadrL_N16980 + ); + dadrL_BU257 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N2141_FROM + ); + dadrL_BU260 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_0_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N2141_GROM + ); + dadrL_N2141_XUSED : X_BUF + port map ( + I => dadrL_N2141_FROM, + O => dadrL_N2141 + ); + dadrL_N2141_YUSED : X_BUF + port map ( + I => dadrL_N2141_GROM, + O => dadrL_N2142 + ); + dadrL_BU499 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_7_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N3703_FROM + ); + dadrL_BU502 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N3703_GROM + ); + dadrL_N3703_XUSED : X_BUF + port map ( + I => dadrL_N3703_FROM, + O => dadrL_N3703 + ); + dadrL_N3703_YUSED : X_BUF + port map ( + I => dadrL_N3703_GROM, + O => dadrL_N3704 + ); + dadrL_BU1019 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N7041_FROM + ); + dadrL_BU1016 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_5_IBUF, + ADR1 => adr_bus_4_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N7041_GROM + ); + dadrL_N7041_XUSED : X_BUF + port map ( + I => dadrL_N7041_FROM, + O => dadrL_N7041 + ); + dadrL_N7041_YUSED : X_BUF + port map ( + I => dadrL_N7041_GROM, + O => dadrL_N7040 + ); + dadrL_BU488 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_5_IBUF, + ADR1 => adr_bus_7_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_6_IBUF, + O => dadrL_N3632_FROM + ); + dadrL_BU491 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_0_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N3632_GROM + ); + dadrL_N3632_XUSED : X_BUF + port map ( + I => dadrL_N3632_FROM, + O => dadrL_N3632 + ); + dadrL_N3632_YUSED : X_BUF + port map ( + I => dadrL_N3632_GROM, + O => dadrL_N3633 + ); + dadrL_BU1657 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_0_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N11159_FROM + ); + dadrL_BU1654 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N11159_GROM + ); + dadrL_N11159_XUSED : X_BUF + port map ( + I => dadrL_N11159_FROM, + O => dadrL_N11159 + ); + dadrL_N11159_YUSED : X_BUF + port map ( + I => dadrL_N11159_GROM, + O => dadrL_N11158 + ); + dadrL_BU1118 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_0_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N7680_FROM + ); + dadrL_BU1115 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N7680_GROM + ); + dadrL_N7680_XUSED : X_BUF + port map ( + I => dadrL_N7680_FROM, + O => dadrL_N7680 + ); + dadrL_N7680_YUSED : X_BUF + port map ( + I => dadrL_N7680_GROM, + O => dadrL_N7679 + ); + dadrL_BU1008 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N6970_FROM + ); + dadrL_BU1005 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_7_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N6970_GROM + ); + dadrL_N6970_XUSED : X_BUF + port map ( + I => dadrL_N6970_FROM, + O => dadrL_N6970 + ); + dadrL_N6970_YUSED : X_BUF + port map ( + I => dadrL_N6970_GROM, + O => dadrL_N6969 + ); + dadrL_BU1646 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N11088_FROM + ); + dadrL_BU1643 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N11088_GROM + ); + dadrL_N11088_XUSED : X_BUF + port map ( + I => dadrL_N11088_FROM, + O => dadrL_N11088 + ); + dadrL_N11088_YUSED : X_BUF + port map ( + I => dadrL_N11088_GROM, + O => dadrL_N11087 + ); + dadrL_BU1107 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N7609_FROM + ); + dadrL_BU1104 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_5_IBUF, + ADR1 => adr_bus_4_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_6_IBUF, + O => dadrL_N7609_GROM + ); + dadrL_N7609_XUSED : X_BUF + port map ( + I => dadrL_N7609_FROM, + O => dadrL_N7609 + ); + dadrL_N7609_YUSED : X_BUF + port map ( + I => dadrL_N7609_GROM, + O => dadrL_N7608 + ); + dadrL_BU2589 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_6_IBUF, + O => dadrL_N17193_FROM + ); + dadrL_BU2592 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N17193_GROM + ); + dadrL_N17193_XUSED : X_BUF + port map ( + I => dadrL_N17193_FROM, + O => dadrL_N17193 + ); + dadrL_N17193_YUSED : X_BUF + port map ( + I => dadrL_N17193_GROM, + O => dadrL_N17194 + ); + dadrL_BU293 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N2355_FROM + ); + dadrL_BU290 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_5_IBUF, + ADR1 => adr_bus_4_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N2355_GROM + ); + dadrL_N2355_XUSED : X_BUF + port map ( + I => dadrL_N2355_FROM, + O => dadrL_N2355 + ); + dadrL_N2355_YUSED : X_BUF + port map ( + I => dadrL_N2355_GROM, + O => dadrL_N2354 + ); + dadrL_BU2578 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_5_IBUF, + ADR1 => adr_bus_4_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_6_IBUF, + O => dadrL_N17122_FROM + ); + dadrL_BU2581 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N17122_GROM + ); + dadrL_N17122_XUSED : X_BUF + port map ( + I => dadrL_N17122_FROM, + O => dadrL_N17122 + ); + dadrL_N17122_YUSED : X_BUF + port map ( + I => dadrL_N17122_GROM, + O => dadrL_N17123 + ); + dadrL_BU279 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_5_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N2283_FROM + ); + dadrL_BU282 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_0_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N2283_GROM + ); + dadrL_N2283_XUSED : X_BUF + port map ( + I => dadrL_N2283_FROM, + O => dadrL_N2283 + ); + dadrL_N2283_YUSED : X_BUF + port map ( + I => dadrL_N2283_GROM, + O => dadrL_N2284 + ); + dadrL_BU524 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_0_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N3846_FROM + ); + dadrL_BU521 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_5_IBUF, + ADR1 => adr_bus_7_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_6_IBUF, + O => dadrL_N3846_GROM + ); + dadrL_N3846_XUSED : X_BUF + port map ( + I => dadrL_N3846_FROM, + O => dadrL_N3846 + ); + dadrL_N3846_YUSED : X_BUF + port map ( + I => dadrL_N3846_GROM, + O => dadrL_N3845 + ); + dadrL_BU1038 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_7_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N7182_FROM + ); + dadrL_BU1041 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N7182_GROM + ); + dadrL_N7182_XUSED : X_BUF + port map ( + I => dadrL_N7182_FROM, + O => dadrL_N7182 + ); + dadrL_N7182_YUSED : X_BUF + port map ( + I => dadrL_N7182_GROM, + O => dadrL_N7183 + ); + dadrL_BU513 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N3775_FROM + ); + dadrL_BU510 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_4_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N3775_GROM + ); + dadrL_N3775_XUSED : X_BUF + port map ( + I => dadrL_N3775_FROM, + O => dadrL_N3775 + ); + dadrL_N3775_YUSED : X_BUF + port map ( + I => dadrL_N3775_GROM, + O => dadrL_N3774 + ); + dadrL_BU1679 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_0_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N11301_FROM + ); + dadrL_BU1676 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_4_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N11301_GROM + ); + dadrL_N11301_XUSED : X_BUF + port map ( + I => dadrL_N11301_FROM, + O => dadrL_N11301 + ); + dadrL_N11301_YUSED : X_BUF + port map ( + I => dadrL_N11301_GROM, + O => dadrL_N11300 + ); + dadrL_BU1137 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N7821_FROM + ); + dadrL_BU1140 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N7821_GROM + ); + dadrL_N7821_XUSED : X_BUF + port map ( + I => dadrL_N7821_FROM, + O => dadrL_N7821 + ); + dadrL_N7821_YUSED : X_BUF + port map ( + I => dadrL_N7821_GROM, + O => dadrL_N7822 + ); + dadrL_BU1027 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N7111_FROM + ); + dadrL_BU1030 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N7111_GROM + ); + dadrL_N7111_XUSED : X_BUF + port map ( + I => dadrL_N7111_FROM, + O => dadrL_N7111 + ); + dadrL_N7111_YUSED : X_BUF + port map ( + I => dadrL_N7111_GROM, + O => dadrL_N7112 + ); + dadrL_BU1668 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N11230_FROM + ); + dadrL_BU1665 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N11230_GROM + ); + dadrL_N11230_XUSED : X_BUF + port map ( + I => dadrL_N11230_FROM, + O => dadrL_N11230 + ); + dadrL_N11230_YUSED : X_BUF + port map ( + I => dadrL_N11230_GROM, + O => dadrL_N11229 + ); + dadrL_BU1129 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N7751_FROM + ); + dadrL_BU1126 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_4_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N7751_GROM + ); + dadrL_N7751_XUSED : X_BUF + port map ( + I => dadrL_N7751_FROM, + O => dadrL_N7751 + ); + dadrL_N7751_YUSED : X_BUF + port map ( + I => dadrL_N7751_GROM, + O => dadrL_N7750 + ); + dadrL_BU2614 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N17336_FROM + ); + dadrL_BU2611 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N17336_GROM + ); + dadrL_N17336_XUSED : X_BUF + port map ( + I => dadrL_N17336_FROM, + O => dadrL_N17336 + ); + dadrL_N17336_YUSED : X_BUF + port map ( + I => dadrL_N17336_GROM, + O => dadrL_N17335 + ); + dadrL_BU315 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_0_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N2497_FROM + ); + dadrL_BU312 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N2497_GROM + ); + dadrL_N2497_XUSED : X_BUF + port map ( + I => dadrL_N2497_FROM, + O => dadrL_N2497 + ); + dadrL_N2497_YUSED : X_BUF + port map ( + I => dadrL_N2497_GROM, + O => dadrL_N2496 + ); + dadrL_BU2603 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_0_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N17265_FROM + ); + dadrL_BU2600 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N17265_GROM + ); + dadrL_N17265_XUSED : X_BUF + port map ( + I => dadrL_N17265_FROM, + O => dadrL_N17265 + ); + dadrL_N17265_YUSED : X_BUF + port map ( + I => dadrL_N17265_GROM, + O => dadrL_N17264 + ); + dadrL_BU304 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N2426_FROM + ); + dadrL_BU301 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_4_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N2426_GROM + ); + dadrL_N2426_XUSED : X_BUF + port map ( + I => dadrL_N2426_FROM, + O => dadrL_N2426 + ); + dadrL_N2426_YUSED : X_BUF + port map ( + I => dadrL_N2426_GROM, + O => dadrL_N2425 + ); + dadrL_BU546 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N3988_FROM + ); + dadrL_BU543 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N3988_GROM + ); + dadrL_N3988_XUSED : X_BUF + port map ( + I => dadrL_N3988_FROM, + O => dadrL_N3988 + ); + dadrL_N3988_YUSED : X_BUF + port map ( + I => dadrL_N3988_GROM, + O => dadrL_N3987 + ); + dadrL_BU1063 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N7325_FROM + ); + dadrL_BU1060 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_4_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N7325_GROM + ); + dadrL_N7325_XUSED : X_BUF + port map ( + I => dadrL_N7325_FROM, + O => dadrL_N7325 + ); + dadrL_N7325_YUSED : X_BUF + port map ( + I => dadrL_N7325_GROM, + O => dadrL_N7324 + ); + dadrL_BU535 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N3917_FROM + ); + dadrL_BU532 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N3917_GROM + ); + dadrL_N3917_XUSED : X_BUF + port map ( + I => dadrL_N3917_FROM, + O => dadrL_N3917 + ); + dadrL_N3917_YUSED : X_BUF + port map ( + I => dadrL_N3917_GROM, + O => dadrL_N3916 + ); + dadrL_BU1159 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_6_IBUF, + O => dadrL_N7963_FROM + ); + dadrL_BU1162 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N7963_GROM + ); + dadrL_N7963_XUSED : X_BUF + port map ( + I => dadrL_N7963_FROM, + O => dadrL_N7963 + ); + dadrL_N7963_YUSED : X_BUF + port map ( + I => dadrL_N7963_GROM, + O => dadrL_N7964 + ); + dadrL_BU1049 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_6_IBUF, + O => dadrL_N7253_FROM + ); + dadrL_BU1052 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N7253_GROM + ); + dadrL_N7253_XUSED : X_BUF + port map ( + I => dadrL_N7253_FROM, + O => dadrL_N7253 + ); + dadrL_N7253_YUSED : X_BUF + port map ( + I => dadrL_N7253_GROM, + O => dadrL_N7254 + ); + dadrL_BU1148 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N7892_FROM + ); + dadrL_BU1151 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N7892_GROM + ); + dadrL_N7892_XUSED : X_BUF + port map ( + I => dadrL_N7892_FROM, + O => dadrL_N7892 + ); + dadrL_N7892_YUSED : X_BUF + port map ( + I => dadrL_N7892_GROM, + O => dadrL_N7893 + ); + dadrL_BU2636 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N17478_FROM + ); + dadrL_BU2633 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N17478_GROM + ); + dadrL_N17478_XUSED : X_BUF + port map ( + I => dadrL_N17478_FROM, + O => dadrL_N17478 + ); + dadrL_N17478_YUSED : X_BUF + port map ( + I => dadrL_N17478_GROM, + O => dadrL_N17477 + ); + dadrL_BU337 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N2639_FROM + ); + dadrL_BU334 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N2639_GROM + ); + dadrL_N2639_XUSED : X_BUF + port map ( + I => dadrL_N2639_FROM, + O => dadrL_N2639 + ); + dadrL_N2639_YUSED : X_BUF + port map ( + I => dadrL_N2639_GROM, + O => dadrL_N2638 + ); + dadrL_BU2625 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N17407_FROM + ); + dadrL_BU2622 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_4_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N17407_GROM + ); + dadrL_N17407_XUSED : X_BUF + port map ( + I => dadrL_N17407_FROM, + O => dadrL_N17407 + ); + dadrL_N17407_YUSED : X_BUF + port map ( + I => dadrL_N17407_GROM, + O => dadrL_N17406 + ); + dadrL_BU326 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N2568_FROM + ); + dadrL_BU323 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N2568_GROM + ); + dadrL_N2568_XUSED : X_BUF + port map ( + I => dadrL_N2568_FROM, + O => dadrL_N2568 + ); + dadrL_N2568_YUSED : X_BUF + port map ( + I => dadrL_N2568_GROM, + O => dadrL_N2567 + ); + dadrL_BU568 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N4130_FROM + ); + dadrL_BU565 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_7_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N4130_GROM + ); + dadrL_N4130_XUSED : X_BUF + port map ( + I => dadrL_N4130_FROM, + O => dadrL_N4130 + ); + dadrL_N4130_YUSED : X_BUF + port map ( + I => dadrL_N4130_GROM, + O => dadrL_N4129 + ); + dadrL_BU1085 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_0_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N7467_FROM + ); + dadrL_BU1082 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_5_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N7467_GROM + ); + dadrL_N7467_XUSED : X_BUF + port map ( + I => dadrL_N7467_FROM, + O => dadrL_N7467 + ); + dadrL_N7467_YUSED : X_BUF + port map ( + I => dadrL_N7467_GROM, + O => dadrL_N7466 + ); + dadrL_BU29 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_0_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N651_FROM + ); + dadrL_BU26 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N651_GROM + ); + dadrL_N651_XUSED : X_BUF + port map ( + I => dadrL_N651_FROM, + O => dadrL_N651 + ); + dadrL_N651_YUSED : X_BUF + port map ( + I => dadrL_N651_GROM, + O => dadrL_N650 + ); + dadrL_BU557 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_0_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N4059_FROM + ); + dadrL_BU554 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N4059_GROM + ); + dadrL_N4059_XUSED : X_BUF + port map ( + I => dadrL_N4059_FROM, + O => dadrL_N4059 + ); + dadrL_N4059_YUSED : X_BUF + port map ( + I => dadrL_N4059_GROM, + O => dadrL_N4058 + ); + dadrL_BU1184 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N8106_FROM + ); + dadrL_BU1181 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_4_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N8106_GROM + ); + dadrL_N8106_XUSED : X_BUF + port map ( + I => dadrL_N8106_FROM, + O => dadrL_N8106 + ); + dadrL_N8106_YUSED : X_BUF + port map ( + I => dadrL_N8106_GROM, + O => dadrL_N8105 + ); + dadrL_BU1074 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N7396_FROM + ); + dadrL_BU1071 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N7396_GROM + ); + dadrL_N7396_XUSED : X_BUF + port map ( + I => dadrL_N7396_FROM, + O => dadrL_N7396 + ); + dadrL_N7396_YUSED : X_BUF + port map ( + I => dadrL_N7396_GROM, + O => dadrL_N7395 + ); + dadrL_BU18 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N580_FROM + ); + dadrL_BU15 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_7_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_6_IBUF, + O => dadrL_N580_GROM + ); + dadrL_N580_XUSED : X_BUF + port map ( + I => dadrL_N580_FROM, + O => dadrL_N580 + ); + dadrL_N580_YUSED : X_BUF + port map ( + I => dadrL_N580_GROM, + O => dadrL_N579 + ); + dadrL_BU1173 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N8035_FROM + ); + dadrL_BU1170 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_7_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N8035_GROM + ); + dadrL_N8035_XUSED : X_BUF + port map ( + I => dadrL_N8035_FROM, + O => dadrL_N8035 + ); + dadrL_N8035_YUSED : X_BUF + port map ( + I => dadrL_N8035_GROM, + O => dadrL_N8034 + ); + dadrL_BU2658 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N17620_FROM + ); + dadrL_BU2655 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N17620_GROM + ); + dadrL_N17620_XUSED : X_BUF + port map ( + I => dadrL_N17620_FROM, + O => dadrL_N17620 + ); + dadrL_N17620_YUSED : X_BUF + port map ( + I => dadrL_N17620_GROM, + O => dadrL_N17619 + ); + dadrL_BU359 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N2781_FROM + ); + dadrL_BU356 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N2781_GROM + ); + dadrL_N2781_XUSED : X_BUF + port map ( + I => dadrL_N2781_FROM, + O => dadrL_N2781 + ); + dadrL_N2781_YUSED : X_BUF + port map ( + I => dadrL_N2781_GROM, + O => dadrL_N2780 + ); + dadrL_BU2647 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_0_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N17549_FROM + ); + dadrL_BU2644 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_7_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N17549_GROM + ); + dadrL_N17549_XUSED : X_BUF + port map ( + I => dadrL_N17549_FROM, + O => dadrL_N17549 + ); + dadrL_N17549_YUSED : X_BUF + port map ( + I => dadrL_N17549_GROM, + O => dadrL_N17548 + ); + dadrL_BU348 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N2710_FROM + ); + dadrL_BU345 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N2710_GROM + ); + dadrL_N2710_XUSED : X_BUF + port map ( + I => dadrL_N2710_FROM, + O => dadrL_N2710 + ); + dadrL_N2710_YUSED : X_BUF + port map ( + I => dadrL_N2710_GROM, + O => dadrL_N2709 + ); + dadrL_BU587 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_4_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N4271_FROM + ); + dadrL_BU590 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_0_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N4271_GROM + ); + dadrL_N4271_XUSED : X_BUF + port map ( + I => dadrL_N4271_FROM, + O => dadrL_N4271 + ); + dadrL_N4271_YUSED : X_BUF + port map ( + I => dadrL_N4271_GROM, + O => dadrL_N4272 + ); + dadrL_BU48 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_5_IBUF, + ADR1 => adr_bus_7_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N792_FROM + ); + dadrL_BU51 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_0_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N792_GROM + ); + dadrL_N792_XUSED : X_BUF + port map ( + I => dadrL_N792_FROM, + O => dadrL_N792 + ); + dadrL_N792_YUSED : X_BUF + port map ( + I => dadrL_N792_GROM, + O => dadrL_N793 + ); + dadrL_BU579 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N4201_FROM + ); + dadrL_BU576 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_5_IBUF, + ADR1 => adr_bus_7_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N4201_GROM + ); + dadrL_N4201_XUSED : X_BUF + port map ( + I => dadrL_N4201_FROM, + O => dadrL_N4201 + ); + dadrL_N4201_YUSED : X_BUF + port map ( + I => dadrL_N4201_GROM, + O => dadrL_N4200 + ); + dadrL_BU1096 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N7538_FROM + ); + dadrL_BU1093 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_7_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N7538_GROM + ); + dadrL_N7538_XUSED : X_BUF + port map ( + I => dadrL_N7538_FROM, + O => dadrL_N7538 + ); + dadrL_N7538_YUSED : X_BUF + port map ( + I => dadrL_N7538_GROM, + O => dadrL_N7537 + ); + dadrL_BU1206 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N8248_FROM + ); + dadrL_BU1203 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_6_IBUF, + O => dadrL_N8248_GROM + ); + dadrL_N8248_XUSED : X_BUF + port map ( + I => dadrL_N8248_FROM, + O => dadrL_N8248 + ); + dadrL_N8248_YUSED : X_BUF + port map ( + I => dadrL_N8248_GROM, + O => dadrL_N8247 + ); + dadrL_BU37 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_5_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N721_FROM + ); + dadrL_BU40 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N721_GROM + ); + dadrL_N721_XUSED : X_BUF + port map ( + I => dadrL_N721_FROM, + O => dadrL_N721 + ); + dadrL_N721_YUSED : X_BUF + port map ( + I => dadrL_N721_GROM, + O => dadrL_N722 + ); + dadrL_BU1195 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N8177_FROM + ); + dadrL_BU1192 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N8177_GROM + ); + dadrL_N8177_XUSED : X_BUF + port map ( + I => dadrL_N8177_FROM, + O => dadrL_N8177 + ); + dadrL_N8177_YUSED : X_BUF + port map ( + I => dadrL_N8177_GROM, + O => dadrL_N8176 + ); + dadrL_BU2677 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_7_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N17761_FROM + ); + dadrL_BU2680 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N17761_GROM + ); + dadrL_N17761_XUSED : X_BUF + port map ( + I => dadrL_N17761_FROM, + O => dadrL_N17761 + ); + dadrL_N17761_YUSED : X_BUF + port map ( + I => dadrL_N17761_GROM, + O => dadrL_N17762 + ); + dadrL_BU2669 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N17691_FROM + ); + dadrL_BU2666 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N17691_GROM + ); + dadrL_N17691_XUSED : X_BUF + port map ( + I => dadrL_N17691_FROM, + O => dadrL_N17691 + ); + dadrL_N17691_YUSED : X_BUF + port map ( + I => dadrL_N17691_GROM, + O => dadrL_N17690 + ); + dadrL_BU367 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N2851_FROM + ); + dadrL_BU370 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N2851_GROM + ); + dadrL_N2851_XUSED : X_BUF + port map ( + I => dadrL_N2851_FROM, + O => dadrL_N2851 + ); + dadrL_N2851_YUSED : X_BUF + port map ( + I => dadrL_N2851_GROM, + O => dadrL_N2852 + ); + dadrL_BU73 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N935_FROM + ); + dadrL_BU70 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N935_GROM + ); + dadrL_N935_XUSED : X_BUF + port map ( + I => dadrL_N935_FROM, + O => dadrL_N935 + ); + dadrL_N935_YUSED : X_BUF + port map ( + I => dadrL_N935_GROM, + O => dadrL_N934 + ); + dadrL_BU1228 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N8390_FROM + ); + dadrL_BU1225 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_5_IBUF, + ADR1 => adr_bus_4_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_6_IBUF, + O => dadrL_N8390_GROM + ); + dadrL_N8390_XUSED : X_BUF + port map ( + I => dadrL_N8390_FROM, + O => dadrL_N8390 + ); + dadrL_N8390_YUSED : X_BUF + port map ( + I => dadrL_N8390_GROM, + O => dadrL_N8389 + ); + dadrL_BU59 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N863_FROM + ); + dadrL_BU62 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N863_GROM + ); + dadrL_N863_XUSED : X_BUF + port map ( + I => dadrL_N863_FROM, + O => dadrL_N863 + ); + dadrL_N863_YUSED : X_BUF + port map ( + I => dadrL_N863_GROM, + O => dadrL_N864 + ); + dadrL_BU1217 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N8319_FROM + ); + dadrL_BU1214 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N8319_GROM + ); + dadrL_N8319_XUSED : X_BUF + port map ( + I => dadrL_N8319_FROM, + O => dadrL_N8319 + ); + dadrL_N8319_YUSED : X_BUF + port map ( + I => dadrL_N8319_GROM, + O => dadrL_N8318 + ); + dadrL_BU2699 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N17903_FROM + ); + dadrL_BU2702 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_0_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N17903_GROM + ); + dadrL_N17903_XUSED : X_BUF + port map ( + I => dadrL_N17903_FROM, + O => dadrL_N17903 + ); + dadrL_N17903_YUSED : X_BUF + port map ( + I => dadrL_N17903_GROM, + O => dadrL_N17904 + ); + dadrL_BU2688 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_4_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N17832_FROM + ); + dadrL_BU2691 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N17832_GROM + ); + dadrL_N17832_XUSED : X_BUF + port map ( + I => dadrL_N17832_FROM, + O => dadrL_N17832 + ); + dadrL_N17832_YUSED : X_BUF + port map ( + I => dadrL_N17832_GROM, + O => dadrL_N17833 + ); + dadrL_BU95 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N1077_FROM + ); + dadrL_BU92 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_6_IBUF, + O => dadrL_N1077_GROM + ); + dadrL_N1077_XUSED : X_BUF + port map ( + I => dadrL_N1077_FROM, + O => dadrL_N1077 + ); + dadrL_N1077_YUSED : X_BUF + port map ( + I => dadrL_N1077_GROM, + O => dadrL_N1076 + ); + dadrL_BU1247 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_4_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N8531_FROM + ); + dadrL_BU1250 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N8531_GROM + ); + dadrL_N8531_XUSED : X_BUF + port map ( + I => dadrL_N8531_FROM, + O => dadrL_N8531 + ); + dadrL_N8531_YUSED : X_BUF + port map ( + I => dadrL_N8531_GROM, + O => dadrL_N8532 + ); + dadrL_BU84 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N1006_FROM + ); + dadrL_BU81 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N1006_GROM + ); + dadrL_N1006_XUSED : X_BUF + port map ( + I => dadrL_N1006_FROM, + O => dadrL_N1006 + ); + dadrL_N1006_YUSED : X_BUF + port map ( + I => dadrL_N1006_GROM, + O => dadrL_N1005 + ); + dadrL_BU1239 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N8461_FROM + ); + dadrL_BU1236 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_5_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N8461_GROM + ); + dadrL_N8461_XUSED : X_BUF + port map ( + I => dadrL_N8461_FROM, + O => dadrL_N8461 + ); + dadrL_N8461_YUSED : X_BUF + port map ( + I => dadrL_N8461_GROM, + O => dadrL_N8460 + ); + dadrL_BU2724 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_0_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N18046_FROM + ); + dadrL_BU2721 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N18046_GROM + ); + dadrL_N18046_XUSED : X_BUF + port map ( + I => dadrL_N18046_FROM, + O => dadrL_N18046 + ); + dadrL_N18046_YUSED : X_BUF + port map ( + I => dadrL_N18046_GROM, + O => dadrL_N18045 + ); + dadrL_BU2713 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N17975_FROM + ); + dadrL_BU2710 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_5_IBUF, + ADR1 => adr_bus_7_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N17975_GROM + ); + dadrL_N17975_XUSED : X_BUF + port map ( + I => dadrL_N17975_FROM, + O => dadrL_N17975 + ); + dadrL_N17975_YUSED : X_BUF + port map ( + I => dadrL_N17975_GROM, + O => dadrL_N17974 + ); + dadrL_BU117 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_2_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N1219_FROM + ); + dadrL_BU114 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_4_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N1219_GROM + ); + dadrL_N1219_XUSED : X_BUF + port map ( + I => dadrL_N1219_FROM, + O => dadrL_N1219 + ); + dadrL_N1219_YUSED : X_BUF + port map ( + I => dadrL_N1219_GROM, + O => dadrL_N1218 + ); + dadrL_BU106 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_0_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N1148_FROM + ); + dadrL_BU103 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_5_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_6_IBUF, + O => dadrL_N1148_GROM + ); + dadrL_N1148_XUSED : X_BUF + port map ( + I => dadrL_N1148_FROM, + O => dadrL_N1148 + ); + dadrL_N1148_YUSED : X_BUF + port map ( + I => dadrL_N1148_GROM, + O => dadrL_N1147 + ); + dadrL_BU1269 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_5_IBUF, + ADR1 => adr_bus_7_IBUF, + ADR2 => adr_bus_6_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N8673_FROM + ); + dadrL_BU1272 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_3_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_1_IBUF, + O => dadrL_N8673_GROM + ); + dadrL_N8673_XUSED : X_BUF + port map ( + I => dadrL_N8673_FROM, + O => dadrL_N8673 + ); + dadrL_N8673_YUSED : X_BUF + port map ( + I => dadrL_N8673_GROM, + O => dadrL_N8674 + ); + dadrL_BU1258 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_4_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_7_IBUF, + ADR3 => adr_bus_5_IBUF, + O => dadrL_N8602_FROM + ); + dadrL_BU1261 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_1_IBUF, + ADR1 => adr_bus_0_IBUF, + ADR2 => adr_bus_3_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N8602_GROM + ); + dadrL_N8602_XUSED : X_BUF + port map ( + I => dadrL_N8602_FROM, + O => dadrL_N8602 + ); + dadrL_N8602_YUSED : X_BUF + port map ( + I => dadrL_N8602_GROM, + O => dadrL_N8603 + ); + dadrL_BU2746 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_2_IBUF, + ADR1 => adr_bus_1_IBUF, + ADR2 => adr_bus_0_IBUF, + ADR3 => adr_bus_3_IBUF, + O => dadrL_N18188_FROM + ); + dadrL_BU2743 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_4_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_7_IBUF, + O => dadrL_N18188_GROM + ); + dadrL_N18188_XUSED : X_BUF + port map ( + I => dadrL_N18188_FROM, + O => dadrL_N18188 + ); + dadrL_N18188_YUSED : X_BUF + port map ( + I => dadrL_N18188_GROM, + O => dadrL_N18187 + ); + dadrL_BU2207 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_0_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_2_IBUF, + O => dadrL_N14709_FROM + ); + dadrL_BU2204 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_6_IBUF, + ADR1 => adr_bus_7_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N14709_GROM + ); + dadrL_N14709_XUSED : X_BUF + port map ( + I => dadrL_N14709_FROM, + O => dadrL_N14709 + ); + dadrL_N14709_YUSED : X_BUF + port map ( + I => dadrL_N14709_GROM, + O => dadrL_N14708 + ); + dadrL_BU32 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => reg_select, + ADR1 => VCC, + ADR2 => dadrL_N650, + ADR3 => dadrL_N651, + O => cs_1_OBUF_GROM + ); + cs_1_OBUF_YUSED : X_BUF + port map ( + I => cs_1_OBUF_GROM, + O => cs_1_OBUF + ); + dadrL_BU43 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => dadrL_N722, + ADR1 => dadrL_N721, + ADR2 => reg_select, + ADR3 => VCC, + O => cs_2_OBUF_GROM + ); + cs_2_OBUF_YUSED : X_BUF + port map ( + I => cs_2_OBUF_GROM, + O => cs_2_OBUF + ); + dadrL_BU54 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => dadrL_N792, + ADR1 => reg_select, + ADR2 => dadrL_N793, + ADR3 => VCC, + O => cs_3_OBUF_GROM + ); + cs_3_OBUF_YUSED : X_BUF + port map ( + I => cs_3_OBUF_GROM, + O => cs_3_OBUF + ); + dadrL_BU65 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => dadrL_N864, + ADR1 => dadrL_N863, + ADR2 => reg_select, + ADR3 => VCC, + O => cs_4_OBUF_GROM + ); + cs_4_OBUF_YUSED : X_BUF + port map ( + I => cs_4_OBUF_GROM, + O => cs_4_OBUF + ); + dadrL_BU76 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N935, + ADR1 => VCC, + ADR2 => dadrL_N934, + ADR3 => reg_select, + O => cs_5_OBUF_GROM + ); + cs_5_OBUF_YUSED : X_BUF + port map ( + I => cs_5_OBUF_GROM, + O => cs_5_OBUF + ); + dadrL_BU87 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N1005, + ADR1 => dadrL_N1006, + ADR2 => VCC, + ADR3 => reg_select, + O => cs_6_OBUF_GROM + ); + cs_6_OBUF_YUSED : X_BUF + port map ( + I => cs_6_OBUF_GROM, + O => cs_6_OBUF + ); + dadrL_BU98 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N1076, + ADR1 => VCC, + ADR2 => reg_select, + ADR3 => dadrL_N1077, + O => cs_7_OBUF_GROM + ); + cs_7_OBUF_YUSED : X_BUF + port map ( + I => cs_7_OBUF_GROM, + O => cs_7_OBUF + ); + reg_select32 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_9_IBUF, + ADR1 => adr_bus_11_IBUF, + ADR2 => N5267, + ADR3 => adr_bus_10_IBUF, + O => reg_select_FROM + ); + dadrL_BU21 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N579, + ADR1 => dadrL_N580, + ADR2 => VCC, + ADR3 => reg_select, + O => reg_select_GROM + ); + reg_select_XUSED : X_BUF + port map ( + I => reg_select_FROM, + O => reg_select + ); + reg_select_YUSED : X_BUF + port map ( + I => reg_select_GROM, + O => cs_0_OBUF + ); + dadrL_BU1000 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => reg_select, + ADR1 => VCC, + ADR2 => dadrL_N6898, + ADR3 => dadrL_N6899, + O => cs_89_OBUF_GROM + ); + cs_89_OBUF_YUSED : X_BUF + port map ( + I => cs_89_OBUF_GROM, + O => cs_89_OBUF + ); + dadrL_BU1011 : X_LUT4 + generic map( + INIT => X"C000" + ) + port map ( + ADR0 => VCC, + ADR1 => dadrL_N6970, + ADR2 => reg_select, + ADR3 => dadrL_N6969, + O => cs_90_OBUF_GROM + ); + cs_90_OBUF_YUSED : X_BUF + port map ( + I => cs_90_OBUF_GROM, + O => cs_90_OBUF + ); + dadrL_BU1110 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N7608, + ADR1 => VCC, + ADR2 => reg_select, + ADR3 => dadrL_N7609, + O => cs_99_OBUF_GROM + ); + cs_99_OBUF_YUSED : X_BUF + port map ( + I => cs_99_OBUF_GROM, + O => cs_99_OBUF + ); + dadrL_BU1022 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => dadrL_N7041, + ADR1 => reg_select, + ADR2 => dadrL_N7040, + ADR3 => VCC, + O => cs_91_OBUF_GROM + ); + cs_91_OBUF_YUSED : X_BUF + port map ( + I => cs_91_OBUF_GROM, + O => cs_91_OBUF + ); + dadrL_BU2001 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => reg_select, + ADR1 => VCC, + ADR2 => dadrL_N13359, + ADR3 => dadrL_N13360, + O => cs_180_OBUF_GROM + ); + cs_180_OBUF_YUSED : X_BUF + port map ( + I => cs_180_OBUF_GROM, + O => cs_180_OBUF + ); + dadrL_BU1121 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => reg_select, + ADR1 => VCC, + ADR2 => dadrL_N7679, + ADR3 => dadrL_N7680, + O => cs_100_OBUF_GROM + ); + cs_100_OBUF_YUSED : X_BUF + port map ( + I => cs_100_OBUF_GROM, + O => cs_100_OBUF + ); + dadrL_BU1033 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N7111, + ADR2 => VCC, + ADR3 => dadrL_N7112, + O => cs_92_OBUF_GROM + ); + cs_92_OBUF_YUSED : X_BUF + port map ( + I => cs_92_OBUF_GROM, + O => cs_92_OBUF + ); + dadrL_BU2100 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => dadrL_N13998, + ADR1 => dadrL_N13999, + ADR2 => reg_select, + ADR3 => VCC, + O => cs_189_OBUF_GROM + ); + cs_189_OBUF_YUSED : X_BUF + port map ( + I => cs_189_OBUF_GROM, + O => cs_189_OBUF + ); + dadrL_BU2012 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => dadrL_N13430, + ADR1 => dadrL_N13431, + ADR2 => reg_select, + ADR3 => VCC, + O => cs_181_OBUF_GROM + ); + cs_181_OBUF_YUSED : X_BUF + port map ( + I => cs_181_OBUF_GROM, + O => cs_181_OBUF + ); + dadrL_BU1220 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N8318, + ADR1 => reg_select, + ADR2 => VCC, + ADR3 => dadrL_N8319, + O => cs_109_OBUF_GROM + ); + cs_109_OBUF_YUSED : X_BUF + port map ( + I => cs_109_OBUF_GROM, + O => cs_109_OBUF + ); + dadrL_BU1132 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => dadrL_N7750, + ADR1 => dadrL_N7751, + ADR2 => reg_select, + ADR3 => VCC, + O => cs_101_OBUF_GROM + ); + cs_101_OBUF_YUSED : X_BUF + port map ( + I => cs_101_OBUF_GROM, + O => cs_101_OBUF + ); + dadrL_BU1044 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N7182, + ADR1 => VCC, + ADR2 => dadrL_N7183, + ADR3 => reg_select, + O => cs_93_OBUF_GROM + ); + cs_93_OBUF_YUSED : X_BUF + port map ( + I => cs_93_OBUF_GROM, + O => cs_93_OBUF + ); + dadrL_BU2111 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => dadrL_N14070, + ADR1 => reg_select, + ADR2 => dadrL_N14069, + ADR3 => VCC, + O => cs_190_OBUF_GROM + ); + cs_190_OBUF_YUSED : X_BUF + port map ( + I => cs_190_OBUF_GROM, + O => cs_190_OBUF + ); + dadrL_BU2023 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N13502, + ADR1 => VCC, + ADR2 => reg_select, + ADR3 => dadrL_N13501, + O => cs_182_OBUF_GROM + ); + cs_182_OBUF_YUSED : X_BUF + port map ( + I => cs_182_OBUF_GROM, + O => cs_182_OBUF + ); + dadrL_BU1231 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N8390, + ADR1 => VCC, + ADR2 => dadrL_N8389, + ADR3 => reg_select, + O => cs_110_OBUF_GROM + ); + cs_110_OBUF_YUSED : X_BUF + port map ( + I => cs_110_OBUF_GROM, + O => cs_110_OBUF + ); + dadrL_BU1143 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => dadrL_N7821, + ADR1 => reg_select, + ADR2 => dadrL_N7822, + ADR3 => VCC, + O => cs_102_OBUF_GROM + ); + cs_102_OBUF_YUSED : X_BUF + port map ( + I => cs_102_OBUF_GROM, + O => cs_102_OBUF + ); + dadrL_BU1055 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N7253, + ADR2 => VCC, + ADR3 => dadrL_N7254, + O => cs_94_OBUF_GROM + ); + cs_94_OBUF_YUSED : X_BUF + port map ( + I => cs_94_OBUF_GROM, + O => cs_94_OBUF + ); + dadrL_BU1209 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => dadrL_N8248, + ADR1 => reg_select, + ADR2 => dadrL_N8247, + ADR3 => VCC, + O => cs_108_OBUF_GROM + ); + cs_108_OBUF_YUSED : X_BUF + port map ( + I => cs_108_OBUF_GROM, + O => cs_108_OBUF + ); + dadrL_BU2210 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => reg_select, + ADR1 => VCC, + ADR2 => dadrL_N14709, + ADR3 => dadrL_N14708, + O => cs_199_OBUF_GROM + ); + cs_199_OBUF_YUSED : X_BUF + port map ( + I => cs_199_OBUF_GROM, + O => cs_199_OBUF + ); + dadrL_BU2122 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N14140, + ADR2 => VCC, + ADR3 => dadrL_N14141, + O => cs_191_OBUF_GROM + ); + cs_191_OBUF_YUSED : X_BUF + port map ( + I => cs_191_OBUF_GROM, + O => cs_191_OBUF + ); + dadrL_BU2034 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N13573, + ADR1 => VCC, + ADR2 => dadrL_N13572, + ADR3 => reg_select, + O => cs_183_OBUF_GROM + ); + cs_183_OBUF_YUSED : X_BUF + port map ( + I => cs_183_OBUF_GROM, + O => cs_183_OBUF + ); + dadrL_BU1330 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N9028, + ADR1 => VCC, + ADR2 => reg_select, + ADR3 => dadrL_N9029, + O => cs_119_OBUF_GROM + ); + cs_119_OBUF_YUSED : X_BUF + port map ( + I => cs_119_OBUF_GROM, + O => cs_119_OBUF + ); + dadrL_BU1242 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => dadrL_N8460, + ADR1 => dadrL_N8461, + ADR2 => reg_select, + ADR3 => VCC, + O => cs_111_OBUF_GROM + ); + cs_111_OBUF_YUSED : X_BUF + port map ( + I => cs_111_OBUF_GROM, + O => cs_111_OBUF + ); + dadrL_BU1154 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N7893, + ADR1 => reg_select, + ADR2 => VCC, + ADR3 => dadrL_N7892, + O => cs_103_OBUF_GROM + ); + cs_103_OBUF_YUSED : X_BUF + port map ( + I => cs_103_OBUF_GROM, + O => cs_103_OBUF + ); + dadrL_BU1066 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N7325, + ADR1 => VCC, + ADR2 => dadrL_N7324, + ADR3 => reg_select, + O => cs_95_OBUF_GROM + ); + cs_95_OBUF_YUSED : X_BUF + port map ( + I => cs_95_OBUF_GROM, + O => cs_95_OBUF + ); + dadrL_BU1308 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N8887, + ADR1 => dadrL_N8886, + ADR2 => VCC, + ADR3 => reg_select, + O => cs_117_OBUF_GROM + ); + cs_117_OBUF_YUSED : X_BUF + port map ( + I => cs_117_OBUF_GROM, + O => cs_117_OBUF + ); + dadrL_BU2221 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => dadrL_N14779, + ADR1 => dadrL_N14780, + ADR2 => reg_select, + ADR3 => VCC, + O => cs_200_OBUF_GROM + ); + cs_200_OBUF_YUSED : X_BUF + port map ( + I => cs_200_OBUF_GROM, + O => cs_200_OBUF + ); + dadrL_BU2133 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => reg_select, + ADR1 => VCC, + ADR2 => dadrL_N14212, + ADR3 => dadrL_N14211, + O => cs_192_OBUF_GROM + ); + cs_192_OBUF_YUSED : X_BUF + port map ( + I => cs_192_OBUF_GROM, + O => cs_192_OBUF + ); + dadrL_BU2045 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N13643, + ADR1 => VCC, + ADR2 => reg_select, + ADR3 => dadrL_N13644, + O => cs_184_OBUF_GROM + ); + cs_184_OBUF_YUSED : X_BUF + port map ( + I => cs_184_OBUF_GROM, + O => cs_184_OBUF + ); + dadrL_BU1341 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => reg_select, + ADR1 => VCC, + ADR2 => dadrL_N9100, + ADR3 => dadrL_N9099, + O => cs_120_OBUF_GROM + ); + cs_120_OBUF_YUSED : X_BUF + port map ( + I => cs_120_OBUF_GROM, + O => cs_120_OBUF + ); + dadrL_BU1253 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N8532, + ADR1 => VCC, + ADR2 => reg_select, + ADR3 => dadrL_N8531, + O => cs_112_OBUF_GROM + ); + cs_112_OBUF_YUSED : X_BUF + port map ( + I => cs_112_OBUF_GROM, + O => cs_112_OBUF + ); + dadrL_BU1165 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => dadrL_N7963, + ADR1 => reg_select, + ADR2 => dadrL_N7964, + ADR3 => VCC, + O => cs_104_OBUF_GROM + ); + cs_104_OBUF_YUSED : X_BUF + port map ( + I => cs_104_OBUF_GROM, + O => cs_104_OBUF + ); + dadrL_BU1077 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N7395, + ADR1 => reg_select, + ADR2 => VCC, + ADR3 => dadrL_N7396, + O => cs_96_OBUF_GROM + ); + cs_96_OBUF_YUSED : X_BUF + port map ( + I => cs_96_OBUF_GROM, + O => cs_96_OBUF + ); + dadrL_BU1407 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => reg_select, + ADR1 => VCC, + ADR2 => dadrL_N9525, + ADR3 => dadrL_N9526, + O => cs_126_OBUF_GROM + ); + cs_126_OBUF_YUSED : X_BUF + port map ( + I => cs_126_OBUF_GROM, + O => cs_126_OBUF + ); + dadrL_BU1319 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N8958, + ADR1 => reg_select, + ADR2 => VCC, + ADR3 => dadrL_N8957, + O => cs_118_OBUF_GROM + ); + cs_118_OBUF_YUSED : X_BUF + port map ( + I => cs_118_OBUF_GROM, + O => cs_118_OBUF + ); + dadrL_BU2320 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => reg_select, + ADR1 => VCC, + ADR2 => dadrL_N15418, + ADR3 => dadrL_N15419, + O => cs_209_OBUF_GROM + ); + cs_209_OBUF_YUSED : X_BUF + port map ( + I => cs_209_OBUF_GROM, + O => cs_209_OBUF + ); + dadrL_BU2232 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => dadrL_N14851, + ADR1 => reg_select, + ADR2 => dadrL_N14850, + ADR3 => VCC, + O => cs_201_OBUF_GROM + ); + cs_201_OBUF_YUSED : X_BUF + port map ( + I => cs_201_OBUF_GROM, + O => cs_201_OBUF + ); + dadrL_BU2144 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => reg_select, + ADR1 => VCC, + ADR2 => dadrL_N14282, + ADR3 => dadrL_N14283, + O => cs_193_OBUF_GROM + ); + cs_193_OBUF_YUSED : X_BUF + port map ( + I => cs_193_OBUF_GROM, + O => cs_193_OBUF + ); + dadrL_BU2056 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N13715, + ADR2 => VCC, + ADR3 => dadrL_N13714, + O => cs_185_OBUF_GROM + ); + cs_185_OBUF_YUSED : X_BUF + port map ( + I => cs_185_OBUF_GROM, + O => cs_185_OBUF + ); + dadrL_BU1440 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N9738, + ADR1 => dadrL_N9739, + ADR2 => VCC, + ADR3 => reg_select, + O => cs_129_OBUF_GROM + ); + cs_129_OBUF_YUSED : X_BUF + port map ( + I => cs_129_OBUF_GROM, + O => cs_129_OBUF + ); + dadrL_BU1352 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N9171, + ADR1 => dadrL_N9170, + ADR2 => VCC, + ADR3 => reg_select, + O => cs_121_OBUF_GROM + ); + cs_121_OBUF_YUSED : X_BUF + port map ( + I => cs_121_OBUF_GROM, + O => cs_121_OBUF + ); + dadrL_BU1264 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => dadrL_N8603, + ADR1 => dadrL_N8602, + ADR2 => reg_select, + ADR3 => VCC, + O => cs_113_OBUF_GROM + ); + cs_113_OBUF_YUSED : X_BUF + port map ( + I => cs_113_OBUF_GROM, + O => cs_113_OBUF + ); + dadrL_BU1176 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => dadrL_N8034, + ADR1 => dadrL_N8035, + ADR2 => reg_select, + ADR3 => VCC, + O => cs_105_OBUF_GROM + ); + cs_105_OBUF_YUSED : X_BUF + port map ( + I => cs_105_OBUF_GROM, + O => cs_105_OBUF + ); + dadrL_BU1088 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => reg_select, + ADR1 => VCC, + ADR2 => dadrL_N7467, + ADR3 => dadrL_N7466, + O => cs_97_OBUF_GROM + ); + cs_97_OBUF_YUSED : X_BUF + port map ( + I => cs_97_OBUF_GROM, + O => cs_97_OBUF + ); + dadrL_BU1506 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N10164, + ADR1 => VCC, + ADR2 => reg_select, + ADR3 => dadrL_N10165, + O => cs_135_OBUF_GROM + ); + cs_135_OBUF_YUSED : X_BUF + port map ( + I => cs_135_OBUF_GROM, + O => cs_135_OBUF + ); + dadrL_BU1418 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N9596, + ADR1 => dadrL_N9597, + ADR2 => VCC, + ADR3 => reg_select, + O => cs_127_OBUF_GROM + ); + cs_127_OBUF_YUSED : X_BUF + port map ( + I => cs_127_OBUF_GROM, + O => cs_127_OBUF + ); + dadrL_BU2331 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N15489, + ADR1 => reg_select, + ADR2 => VCC, + ADR3 => dadrL_N15490, + O => cs_210_OBUF_GROM + ); + cs_210_OBUF_YUSED : X_BUF + port map ( + I => cs_210_OBUF_GROM, + O => cs_210_OBUF + ); + dadrL_BU2243 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N14922, + ADR1 => VCC, + ADR2 => reg_select, + ADR3 => dadrL_N14921, + O => cs_202_OBUF_GROM + ); + cs_202_OBUF_YUSED : X_BUF + port map ( + I => cs_202_OBUF_GROM, + O => cs_202_OBUF + ); + dadrL_BU2155 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N14353, + ADR1 => VCC, + ADR2 => dadrL_N14354, + ADR3 => reg_select, + O => cs_194_OBUF_GROM + ); + cs_194_OBUF_YUSED : X_BUF + port map ( + I => cs_194_OBUF_GROM, + O => cs_194_OBUF + ); + dadrL_BU2067 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N13785, + ADR1 => VCC, + ADR2 => reg_select, + ADR3 => dadrL_N13786, + O => cs_186_OBUF_GROM + ); + cs_186_OBUF_YUSED : X_BUF + port map ( + I => cs_186_OBUF_GROM, + O => cs_186_OBUF + ); + dadrL_BU1451 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N9809, + ADR1 => VCC, + ADR2 => reg_select, + ADR3 => dadrL_N9810, + O => cs_130_OBUF_GROM + ); + cs_130_OBUF_YUSED : X_BUF + port map ( + I => cs_130_OBUF_GROM, + O => cs_130_OBUF + ); + cs_77_OBUF_19 : X_TRI + port map ( + I => cs_77_OUTMUX, + CTL => cs_77_ENABLE, + O => cs(77) + ); + cs_77_ENABLEINV : X_INV + port map ( + I => cs_77_TORGTS, + O => cs_77_ENABLE + ); + cs_77_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_77_TORGTS + ); + cs_77_OUTMUX_20 : X_BUF + port map ( + I => cs_77_OBUF, + O => cs_77_OUTMUX + ); + cs_85_OBUF_21 : X_TRI + port map ( + I => cs_85_OUTMUX, + CTL => cs_85_ENABLE, + O => cs(85) + ); + cs_85_ENABLEINV : X_INV + port map ( + I => cs_85_TORGTS, + O => cs_85_ENABLE + ); + cs_85_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_85_TORGTS + ); + cs_85_OUTMUX_22 : X_BUF + port map ( + I => cs_85_OBUF, + O => cs_85_OUTMUX + ); + cs_93_OBUF_23 : X_TRI + port map ( + I => cs_93_OUTMUX, + CTL => cs_93_ENABLE, + O => cs(93) + ); + cs_93_ENABLEINV : X_INV + port map ( + I => cs_93_TORGTS, + O => cs_93_ENABLE + ); + cs_93_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_93_TORGTS + ); + cs_93_OUTMUX_24 : X_BUF + port map ( + I => cs_93_OBUF, + O => cs_93_OUTMUX + ); + cs_78_OBUF_25 : X_TRI + port map ( + I => cs_78_OUTMUX, + CTL => cs_78_ENABLE, + O => cs(78) + ); + cs_78_ENABLEINV : X_INV + port map ( + I => cs_78_TORGTS, + O => cs_78_ENABLE + ); + cs_78_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_78_TORGTS + ); + cs_78_OUTMUX_26 : X_BUF + port map ( + I => cs_78_OBUF, + O => cs_78_OUTMUX + ); + cs_86_OBUF_27 : X_TRI + port map ( + I => cs_86_OUTMUX, + CTL => cs_86_ENABLE, + O => cs(86) + ); + cs_86_ENABLEINV : X_INV + port map ( + I => cs_86_TORGTS, + O => cs_86_ENABLE + ); + cs_86_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_86_TORGTS + ); + cs_86_OUTMUX_28 : X_BUF + port map ( + I => cs_86_OBUF, + O => cs_86_OUTMUX + ); + cs_94_OBUF_29 : X_TRI + port map ( + I => cs_94_OUTMUX, + CTL => cs_94_ENABLE, + O => cs(94) + ); + cs_94_ENABLEINV : X_INV + port map ( + I => cs_94_TORGTS, + O => cs_94_ENABLE + ); + cs_94_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_94_TORGTS + ); + cs_94_OUTMUX_30 : X_BUF + port map ( + I => cs_94_OBUF, + O => cs_94_OUTMUX + ); + cs_79_OBUF_31 : X_TRI + port map ( + I => cs_79_OUTMUX, + CTL => cs_79_ENABLE, + O => cs(79) + ); + cs_79_ENABLEINV : X_INV + port map ( + I => cs_79_TORGTS, + O => cs_79_ENABLE + ); + cs_79_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_79_TORGTS + ); + cs_79_OUTMUX_32 : X_BUF + port map ( + I => cs_79_OBUF, + O => cs_79_OUTMUX + ); + cs_87_OBUF_33 : X_TRI + port map ( + I => cs_87_OUTMUX, + CTL => cs_87_ENABLE, + O => cs(87) + ); + cs_87_ENABLEINV : X_INV + port map ( + I => cs_87_TORGTS, + O => cs_87_ENABLE + ); + cs_87_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_87_TORGTS + ); + cs_87_OUTMUX_34 : X_BUF + port map ( + I => cs_87_OBUF, + O => cs_87_OUTMUX + ); + cs_95_OBUF_35 : X_TRI + port map ( + I => cs_95_OUTMUX, + CTL => cs_95_ENABLE, + O => cs(95) + ); + cs_95_ENABLEINV : X_INV + port map ( + I => cs_95_TORGTS, + O => cs_95_ENABLE + ); + cs_95_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_95_TORGTS + ); + cs_95_OUTMUX_36 : X_BUF + port map ( + I => cs_95_OBUF, + O => cs_95_OUTMUX + ); + cs_88_OBUF_37 : X_TRI + port map ( + I => cs_88_OUTMUX, + CTL => cs_88_ENABLE, + O => cs(88) + ); + cs_88_ENABLEINV : X_INV + port map ( + I => cs_88_TORGTS, + O => cs_88_ENABLE + ); + cs_88_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_88_TORGTS + ); + cs_88_OUTMUX_38 : X_BUF + port map ( + I => cs_88_OBUF, + O => cs_88_OUTMUX + ); + cs_96_OBUF_39 : X_TRI + port map ( + I => cs_96_OUTMUX, + CTL => cs_96_ENABLE, + O => cs(96) + ); + cs_96_ENABLEINV : X_INV + port map ( + I => cs_96_TORGTS, + O => cs_96_ENABLE + ); + cs_96_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_96_TORGTS + ); + cs_96_OUTMUX_40 : X_BUF + port map ( + I => cs_96_OBUF, + O => cs_96_OUTMUX + ); + cs_89_OBUF_41 : X_TRI + port map ( + I => cs_89_OUTMUX, + CTL => cs_89_ENABLE, + O => cs(89) + ); + cs_89_ENABLEINV : X_INV + port map ( + I => cs_89_TORGTS, + O => cs_89_ENABLE + ); + cs_89_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_89_TORGTS + ); + cs_89_OUTMUX_42 : X_BUF + port map ( + I => cs_89_OBUF, + O => cs_89_OUTMUX + ); + cs_97_OBUF_43 : X_TRI + port map ( + I => cs_97_OUTMUX, + CTL => cs_97_ENABLE, + O => cs(97) + ); + cs_97_ENABLEINV : X_INV + port map ( + I => cs_97_TORGTS, + O => cs_97_ENABLE + ); + cs_97_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_97_TORGTS + ); + cs_97_OUTMUX_44 : X_BUF + port map ( + I => cs_97_OBUF, + O => cs_97_OUTMUX + ); + cs_98_OBUF_45 : X_TRI + port map ( + I => cs_98_OUTMUX, + CTL => cs_98_ENABLE, + O => cs(98) + ); + cs_98_ENABLEINV : X_INV + port map ( + I => cs_98_TORGTS, + O => cs_98_ENABLE + ); + cs_98_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_98_TORGTS + ); + cs_98_OUTMUX_46 : X_BUF + port map ( + I => cs_98_OBUF, + O => cs_98_OUTMUX + ); + cs_99_OBUF_47 : X_TRI + port map ( + I => cs_99_OUTMUX, + CTL => cs_99_ENABLE, + O => cs(99) + ); + cs_99_ENABLEINV : X_INV + port map ( + I => cs_99_TORGTS, + O => cs_99_ENABLE + ); + cs_99_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_99_TORGTS + ); + cs_99_OUTMUX_48 : X_BUF + port map ( + I => cs_99_OBUF, + O => cs_99_OUTMUX + ); + cs_0_OBUF_49 : X_TRI + port map ( + I => cs_0_OUTMUX, + CTL => cs_0_ENABLE, + O => cs(0) + ); + cs_0_ENABLEINV : X_INV + port map ( + I => cs_0_TORGTS, + O => cs_0_ENABLE + ); + cs_0_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_0_TORGTS + ); + cs_0_OUTMUX_50 : X_BUF + port map ( + I => cs_0_OBUF, + O => cs_0_OUTMUX + ); + cs_1_OBUF_51 : X_TRI + port map ( + I => cs_1_OUTMUX, + CTL => cs_1_ENABLE, + O => cs(1) + ); + cs_1_ENABLEINV : X_INV + port map ( + I => cs_1_TORGTS, + O => cs_1_ENABLE + ); + cs_1_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_1_TORGTS + ); + cs_1_OUTMUX_52 : X_BUF + port map ( + I => cs_1_OBUF, + O => cs_1_OUTMUX + ); + cs_2_OBUF_53 : X_TRI + port map ( + I => cs_2_OUTMUX, + CTL => cs_2_ENABLE, + O => cs(2) + ); + cs_2_ENABLEINV : X_INV + port map ( + I => cs_2_TORGTS, + O => cs_2_ENABLE + ); + cs_2_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_2_TORGTS + ); + cs_2_OUTMUX_54 : X_BUF + port map ( + I => cs_2_OBUF, + O => cs_2_OUTMUX + ); + cs_3_OBUF_55 : X_TRI + port map ( + I => cs_3_OUTMUX, + CTL => cs_3_ENABLE, + O => cs(3) + ); + cs_3_ENABLEINV : X_INV + port map ( + I => cs_3_TORGTS, + O => cs_3_ENABLE + ); + cs_3_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_3_TORGTS + ); + cs_3_OUTMUX_56 : X_BUF + port map ( + I => cs_3_OBUF, + O => cs_3_OUTMUX + ); + cs_4_OBUF_57 : X_TRI + port map ( + I => cs_4_OUTMUX, + CTL => cs_4_ENABLE, + O => cs(4) + ); + cs_4_ENABLEINV : X_INV + port map ( + I => cs_4_TORGTS, + O => cs_4_ENABLE + ); + cs_4_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_4_TORGTS + ); + cs_4_OUTMUX_58 : X_BUF + port map ( + I => cs_4_OBUF, + O => cs_4_OUTMUX + ); + cs_5_OBUF_59 : X_TRI + port map ( + I => cs_5_OUTMUX, + CTL => cs_5_ENABLE, + O => cs(5) + ); + cs_5_ENABLEINV : X_INV + port map ( + I => cs_5_TORGTS, + O => cs_5_ENABLE + ); + cs_5_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_5_TORGTS + ); + cs_5_OUTMUX_60 : X_BUF + port map ( + I => cs_5_OBUF, + O => cs_5_OUTMUX + ); + cs_6_OBUF_61 : X_TRI + port map ( + I => cs_6_OUTMUX, + CTL => cs_6_ENABLE, + O => cs(6) + ); + cs_6_ENABLEINV : X_INV + port map ( + I => cs_6_TORGTS, + O => cs_6_ENABLE + ); + cs_6_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_6_TORGTS + ); + cs_6_OUTMUX_62 : X_BUF + port map ( + I => cs_6_OBUF, + O => cs_6_OUTMUX + ); + cs_7_OBUF_63 : X_TRI + port map ( + I => cs_7_OUTMUX, + CTL => cs_7_ENABLE, + O => cs(7) + ); + cs_7_ENABLEINV : X_INV + port map ( + I => cs_7_TORGTS, + O => cs_7_ENABLE + ); + cs_7_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_7_TORGTS + ); + cs_7_OUTMUX_64 : X_BUF + port map ( + I => cs_7_OBUF, + O => cs_7_OUTMUX + ); + cs_8_OBUF_65 : X_TRI + port map ( + I => cs_8_OUTMUX, + CTL => cs_8_ENABLE, + O => cs(8) + ); + cs_8_ENABLEINV : X_INV + port map ( + I => cs_8_TORGTS, + O => cs_8_ENABLE + ); + cs_8_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_8_TORGTS + ); + cs_8_OUTMUX_66 : X_BUF + port map ( + I => cs_8_OBUF, + O => cs_8_OUTMUX + ); + cs_9_OBUF_67 : X_TRI + port map ( + I => cs_9_OUTMUX, + CTL => cs_9_ENABLE, + O => cs(9) + ); + cs_9_ENABLEINV : X_INV + port map ( + I => cs_9_TORGTS, + O => cs_9_ENABLE + ); + cs_9_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_9_TORGTS + ); + cs_9_OUTMUX_68 : X_BUF + port map ( + I => cs_9_OBUF, + O => cs_9_OUTMUX + ); + reg_select24 : X_LUT4 + generic map( + INIT => X"0404" + ) + port map ( + ADR0 => adr_bus_15_IBUF, + ADR1 => adr_bus_8_IBUF, + ADR2 => AEN_IBUF, + ADR3 => VCC, + O => CHOICE45_FROM + ); + reg_select32_SW0 : X_LUT4 + generic map( + INIT => X"FEFF" + ) + port map ( + ADR0 => adr_bus_14_IBUF, + ADR1 => adr_bus_12_IBUF, + ADR2 => adr_bus_13_IBUF, + ADR3 => CHOICE45, + O => CHOICE45_GROM + ); + CHOICE45_XUSED : X_BUF + port map ( + I => CHOICE45_FROM, + O => CHOICE45 + ); + CHOICE45_YUSED : X_BUF + port map ( + I => CHOICE45_GROM, + O => N5267 + ); + Q_n00031 : X_LUT4 + generic map( + INIT => X"000C" + ) + port map ( + ADR0 => VCC, + ADR1 => IOW_IBUF, + ADR2 => IOR_IBUF, + ADR3 => AEN_IBUF, + O => rw_OBUF_FROM + ); + Q_n00021 : X_LUT4 + generic map( + INIT => X"FF88" + ) + port map ( + ADR0 => IOW_IBUF, + ADR1 => IOR_IBUF, + ADR2 => VCC, + ADR3 => AEN_IBUF, + O => rw_OBUF_GROM + ); + rw_OBUF_XUSED : X_BUF + port map ( + I => rw_OBUF_FROM, + O => rw_OBUF + ); + rw_OBUF_YUSED : X_BUF + port map ( + I => rw_OBUF_GROM, + O => clk_OBUF + ); + dadrL_BU1363 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N9241, + ADR1 => VCC, + ADR2 => reg_select, + ADR3 => dadrL_N9242, + O => cs_122_OBUF_GROM + ); + cs_122_OBUF_YUSED : X_BUF + port map ( + I => cs_122_OBUF_GROM, + O => cs_122_OBUF + ); + dadrL_BU1275 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => dadrL_N8673, + ADR1 => reg_select, + ADR2 => dadrL_N8674, + ADR3 => VCC, + O => cs_114_OBUF_GROM + ); + cs_114_OBUF_YUSED : X_BUF + port map ( + I => cs_114_OBUF_GROM, + O => cs_114_OBUF + ); + dadrL_BU1187 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N8105, + ADR1 => reg_select, + ADR2 => VCC, + ADR3 => dadrL_N8106, + O => cs_106_OBUF_GROM + ); + cs_106_OBUF_YUSED : X_BUF + port map ( + I => cs_106_OBUF_GROM, + O => cs_106_OBUF + ); + dadrL_BU1099 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N7537, + ADR1 => VCC, + ADR2 => reg_select, + ADR3 => dadrL_N7538, + O => cs_98_OBUF_GROM + ); + cs_98_OBUF_YUSED : X_BUF + port map ( + I => cs_98_OBUF_GROM, + O => cs_98_OBUF + ); + dadrL_BU2309 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N15347, + ADR1 => dadrL_N15348, + ADR2 => VCC, + ADR3 => reg_select, + O => cs_208_OBUF_GROM + ); + cs_208_OBUF_YUSED : X_BUF + port map ( + I => cs_208_OBUF_GROM, + O => cs_208_OBUF + ); + dadrL_BU1605 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N10804, + ADR1 => VCC, + ADR2 => dadrL_N10803, + ADR3 => reg_select, + O => cs_144_OBUF_GROM + ); + cs_144_OBUF_YUSED : X_BUF + port map ( + I => cs_144_OBUF_GROM, + O => cs_144_OBUF + ); + dadrL_BU1517 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N10235, + ADR1 => reg_select, + ADR2 => VCC, + ADR3 => dadrL_N10236, + O => cs_136_OBUF_GROM + ); + cs_136_OBUF_YUSED : X_BUF + port map ( + I => cs_136_OBUF_GROM, + O => cs_136_OBUF + ); + dadrL_BU1429 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => reg_select, + ADR1 => VCC, + ADR2 => dadrL_N9667, + ADR3 => dadrL_N9668, + O => cs_128_OBUF_GROM + ); + cs_128_OBUF_YUSED : X_BUF + port map ( + I => cs_128_OBUF_GROM, + O => cs_128_OBUF + ); + dadrL_BU2430 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N16129, + ADR2 => VCC, + ADR3 => dadrL_N16128, + O => cs_219_OBUF_GROM + ); + cs_219_OBUF_YUSED : X_BUF + port map ( + I => cs_219_OBUF_GROM, + O => cs_219_OBUF + ); + dadrL_BU2342 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => reg_select, + ADR1 => VCC, + ADR2 => dadrL_N15560, + ADR3 => dadrL_N15561, + O => cs_211_OBUF_GROM + ); + cs_211_OBUF_YUSED : X_BUF + port map ( + I => cs_211_OBUF_GROM, + O => cs_211_OBUF + ); + dadrL_BU2254 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => reg_select, + ADR1 => VCC, + ADR2 => dadrL_N14993, + ADR3 => dadrL_N14992, + O => cs_203_OBUF_GROM + ); + cs_203_OBUF_YUSED : X_BUF + port map ( + I => cs_203_OBUF_GROM, + O => cs_203_OBUF + ); + dadrL_BU2166 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N14424, + ADR1 => dadrL_N14425, + ADR2 => VCC, + ADR3 => reg_select, + O => cs_195_OBUF_GROM + ); + cs_195_OBUF_YUSED : X_BUF + port map ( + I => cs_195_OBUF_GROM, + O => cs_195_OBUF + ); + dadrL_BU2078 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N13856, + ADR1 => dadrL_N13857, + ADR2 => VCC, + ADR3 => reg_select, + O => cs_187_OBUF_GROM + ); + cs_187_OBUF_YUSED : X_BUF + port map ( + I => cs_187_OBUF_GROM, + O => cs_187_OBUF + ); + dadrL_BU1550 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N10448, + ADR1 => dadrL_N10449, + ADR2 => VCC, + ADR3 => reg_select, + O => cs_139_OBUF_GROM + ); + cs_139_OBUF_YUSED : X_BUF + port map ( + I => cs_139_OBUF_GROM, + O => cs_139_OBUF + ); + dadrL_BU1462 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N9880, + ADR1 => VCC, + ADR2 => reg_select, + ADR3 => dadrL_N9881, + O => cs_131_OBUF_GROM + ); + cs_131_OBUF_YUSED : X_BUF + port map ( + I => cs_131_OBUF_GROM, + O => cs_131_OBUF + ); + dadrL_BU1374 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => dadrL_N9313, + ADR1 => dadrL_N9312, + ADR2 => reg_select, + ADR3 => VCC, + O => cs_123_OBUF_GROM + ); + cs_123_OBUF_YUSED : X_BUF + port map ( + I => cs_123_OBUF_GROM, + O => cs_123_OBUF + ); + dadrL_BU1286 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N8745, + ADR2 => VCC, + ADR3 => dadrL_N8744, + O => cs_115_OBUF_GROM + ); + cs_115_OBUF_YUSED : X_BUF + port map ( + I => cs_115_OBUF_GROM, + O => cs_115_OBUF + ); + dadrL_BU1198 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => dadrL_N8176, + ADR1 => dadrL_N8177, + ADR2 => reg_select, + ADR3 => VCC, + O => cs_107_OBUF_GROM + ); + cs_107_OBUF_YUSED : X_BUF + port map ( + I => cs_107_OBUF_GROM, + O => cs_107_OBUF + ); + dadrL_BU2408 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N15987, + ADR1 => reg_select, + ADR2 => VCC, + ADR3 => dadrL_N15986, + O => cs_217_OBUF_GROM + ); + cs_217_OBUF_YUSED : X_BUF + port map ( + I => cs_217_OBUF_GROM, + O => cs_217_OBUF + ); + dadrL_BU1704 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => dadrL_N11442, + ADR1 => reg_select, + ADR2 => dadrL_N11443, + ADR3 => VCC, + O => cs_153_OBUF_GROM + ); + cs_153_OBUF_YUSED : X_BUF + port map ( + I => cs_153_OBUF_GROM, + O => cs_153_OBUF + ); + dadrL_BU1616 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => reg_select, + ADR1 => VCC, + ADR2 => dadrL_N10874, + ADR3 => dadrL_N10875, + O => cs_145_OBUF_GROM + ); + cs_145_OBUF_YUSED : X_BUF + port map ( + I => cs_145_OBUF_GROM, + O => cs_145_OBUF + ); + dadrL_BU1528 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => reg_select, + ADR1 => VCC, + ADR2 => dadrL_N10306, + ADR3 => dadrL_N10307, + O => cs_137_OBUF_GROM + ); + cs_137_OBUF_YUSED : X_BUF + port map ( + I => cs_137_OBUF_GROM, + O => cs_137_OBUF + ); + dadrL_BU2441 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N16199, + ADR1 => dadrL_N16200, + ADR2 => VCC, + ADR3 => reg_select, + O => cs_220_OBUF_GROM + ); + cs_220_OBUF_YUSED : X_BUF + port map ( + I => cs_220_OBUF_GROM, + O => cs_220_OBUF + ); + dadrL_BU2353 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => dadrL_N15632, + ADR1 => dadrL_N15631, + ADR2 => reg_select, + ADR3 => VCC, + O => cs_212_OBUF_GROM + ); + cs_212_OBUF_YUSED : X_BUF + port map ( + I => cs_212_OBUF_GROM, + O => cs_212_OBUF + ); + dadrL_BU2265 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N15064, + ADR1 => dadrL_N15063, + ADR2 => VCC, + ADR3 => reg_select, + O => cs_204_OBUF_GROM + ); + cs_204_OBUF_YUSED : X_BUF + port map ( + I => cs_204_OBUF_GROM, + O => cs_204_OBUF + ); + dadrL_BU2177 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N14495, + ADR1 => VCC, + ADR2 => reg_select, + ADR3 => dadrL_N14496, + O => cs_196_OBUF_GROM + ); + cs_196_OBUF_YUSED : X_BUF + port map ( + I => cs_196_OBUF_GROM, + O => cs_196_OBUF + ); + dadrL_BU2089 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N13927, + ADR1 => VCC, + ADR2 => reg_select, + ADR3 => dadrL_N13928, + O => cs_188_OBUF_GROM + ); + cs_188_OBUF_YUSED : X_BUF + port map ( + I => cs_188_OBUF_GROM, + O => cs_188_OBUF + ); + dadrL_BU1561 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N10520, + ADR2 => dadrL_N10519, + ADR3 => VCC, + O => cs_140_OBUF_GROM + ); + cs_140_OBUF_YUSED : X_BUF + port map ( + I => cs_140_OBUF_GROM, + O => cs_140_OBUF + ); + dadrL_BU1473 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N9952, + ADR1 => VCC, + ADR2 => reg_select, + ADR3 => dadrL_N9951, + O => cs_132_OBUF_GROM + ); + cs_132_OBUF_YUSED : X_BUF + port map ( + I => cs_132_OBUF_GROM, + O => cs_132_OBUF + ); + dadrL_BU1385 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N9383, + ADR1 => VCC, + ADR2 => dadrL_N9384, + ADR3 => reg_select, + O => cs_124_OBUF_GROM + ); + cs_124_OBUF_YUSED : X_BUF + port map ( + I => cs_124_OBUF_GROM, + O => cs_124_OBUF + ); + dadrL_BU1297 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => dadrL_N8816, + ADR1 => reg_select, + ADR2 => dadrL_N8815, + ADR3 => VCC, + O => cs_116_OBUF_GROM + ); + cs_116_OBUF_YUSED : X_BUF + port map ( + I => cs_116_OBUF_GROM, + O => cs_116_OBUF + ); + dadrL_BU2507 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N16626, + ADR1 => dadrL_N16625, + ADR2 => VCC, + ADR3 => reg_select, + O => cs_226_OBUF_GROM + ); + cs_226_OBUF_YUSED : X_BUF + port map ( + I => cs_226_OBUF_GROM, + O => cs_226_OBUF + ); + dadrL_BU2419 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N16057, + ADR1 => VCC, + ADR2 => reg_select, + ADR3 => dadrL_N16058, + O => cs_218_OBUF_GROM + ); + cs_218_OBUF_YUSED : X_BUF + port map ( + I => cs_218_OBUF_GROM, + O => cs_218_OBUF + ); + dadrL_BU1803 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N12082, + ADR1 => VCC, + ADR2 => reg_select, + ADR3 => dadrL_N12081, + O => cs_162_OBUF_GROM + ); + cs_162_OBUF_YUSED : X_BUF + port map ( + I => cs_162_OBUF_GROM, + O => cs_162_OBUF + ); + dadrL_BU1715 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => dadrL_N11514, + ADR1 => dadrL_N11513, + ADR2 => reg_select, + ADR3 => VCC, + O => cs_154_OBUF_GROM + ); + cs_154_OBUF_YUSED : X_BUF + port map ( + I => cs_154_OBUF_GROM, + O => cs_154_OBUF + ); + dadrL_BU1627 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => dadrL_N10945, + ADR1 => dadrL_N10946, + ADR2 => reg_select, + ADR3 => VCC, + O => cs_146_OBUF_GROM + ); + cs_146_OBUF_YUSED : X_BUF + port map ( + I => cs_146_OBUF_GROM, + O => cs_146_OBUF + ); + dadrL_BU1539 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => dadrL_N10377, + ADR1 => dadrL_N10378, + ADR2 => reg_select, + ADR3 => VCC, + O => cs_138_OBUF_GROM + ); + cs_138_OBUF_YUSED : X_BUF + port map ( + I => cs_138_OBUF_GROM, + O => cs_138_OBUF + ); + dadrL_BU2540 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => dadrL_N16839, + ADR1 => reg_select, + ADR2 => dadrL_N16838, + ADR3 => VCC, + O => cs_229_OBUF_GROM + ); + cs_229_OBUF_YUSED : X_BUF + port map ( + I => cs_229_OBUF_GROM, + O => cs_229_OBUF + ); + dadrL_BU2452 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N16271, + ADR1 => VCC, + ADR2 => dadrL_N16270, + ADR3 => reg_select, + O => cs_221_OBUF_GROM + ); + cs_221_OBUF_YUSED : X_BUF + port map ( + I => cs_221_OBUF_GROM, + O => cs_221_OBUF + ); + dadrL_BU2364 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => dadrL_N15702, + ADR1 => reg_select, + ADR2 => dadrL_N15703, + ADR3 => VCC, + O => cs_213_OBUF_GROM + ); + cs_213_OBUF_YUSED : X_BUF + port map ( + I => cs_213_OBUF_GROM, + O => cs_213_OBUF + ); + dadrL_BU2276 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N15134, + ADR1 => reg_select, + ADR2 => VCC, + ADR3 => dadrL_N15135, + O => cs_205_OBUF_GROM + ); + cs_205_OBUF_YUSED : X_BUF + port map ( + I => cs_205_OBUF_GROM, + O => cs_205_OBUF + ); + dadrL_BU2188 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N14566, + ADR1 => dadrL_N14567, + ADR2 => VCC, + ADR3 => reg_select, + O => cs_197_OBUF_GROM + ); + cs_197_OBUF_YUSED : X_BUF + port map ( + I => cs_197_OBUF_GROM, + O => cs_197_OBUF + ); + dadrL_BU1660 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N11159, + ADR1 => VCC, + ADR2 => dadrL_N11158, + ADR3 => reg_select, + O => cs_149_OBUF_GROM + ); + cs_149_OBUF_YUSED : X_BUF + port map ( + I => cs_149_OBUF_GROM, + O => cs_149_OBUF + ); + dadrL_BU1572 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => reg_select, + ADR1 => VCC, + ADR2 => dadrL_N10590, + ADR3 => dadrL_N10591, + O => cs_141_OBUF_GROM + ); + cs_141_OBUF_YUSED : X_BUF + port map ( + I => cs_141_OBUF_GROM, + O => cs_141_OBUF + ); + dadrL_BU1484 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => dadrL_N10022, + ADR1 => reg_select, + ADR2 => dadrL_N10023, + ADR3 => VCC, + O => cs_133_OBUF_GROM + ); + cs_133_OBUF_YUSED : X_BUF + port map ( + I => cs_133_OBUF_GROM, + O => cs_133_OBUF + ); + dadrL_BU1396 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N9454, + ADR1 => dadrL_N9455, + ADR2 => VCC, + ADR3 => reg_select, + O => cs_125_OBUF_GROM + ); + cs_125_OBUF_YUSED : X_BUF + port map ( + I => cs_125_OBUF_GROM, + O => cs_125_OBUF + ); + dadrL_BU2606 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N17264, + ADR1 => VCC, + ADR2 => reg_select, + ADR3 => dadrL_N17265, + O => cs_235_OBUF_GROM + ); + cs_235_OBUF_YUSED : X_BUF + port map ( + I => cs_235_OBUF_GROM, + O => cs_235_OBUF + ); + dadrL_BU2518 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N16696, + ADR1 => VCC, + ADR2 => reg_select, + ADR3 => dadrL_N16697, + O => cs_227_OBUF_GROM + ); + cs_227_OBUF_YUSED : X_BUF + port map ( + I => cs_227_OBUF_GROM, + O => cs_227_OBUF + ); + dadrL_BU1902 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N12720, + ADR1 => dadrL_N12721, + ADR2 => VCC, + ADR3 => reg_select, + O => cs_171_OBUF_GROM + ); + cs_171_OBUF_YUSED : X_BUF + port map ( + I => cs_171_OBUF_GROM, + O => cs_171_OBUF + ); + dadrL_BU1814 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => reg_select, + ADR1 => VCC, + ADR2 => dadrL_N12152, + ADR3 => dadrL_N12153, + O => cs_163_OBUF_GROM + ); + cs_163_OBUF_YUSED : X_BUF + port map ( + I => cs_163_OBUF_GROM, + O => cs_163_OBUF + ); + dadrL_BU1726 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => dadrL_N11585, + ADR1 => reg_select, + ADR2 => dadrL_N11584, + ADR3 => VCC, + O => cs_155_OBUF_GROM + ); + cs_155_OBUF_YUSED : X_BUF + port map ( + I => cs_155_OBUF_GROM, + O => cs_155_OBUF + ); + dadrL_BU1638 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => dadrL_N11017, + ADR1 => reg_select, + ADR2 => dadrL_N11016, + ADR3 => VCC, + O => cs_147_OBUF_GROM + ); + cs_147_OBUF_YUSED : X_BUF + port map ( + I => cs_147_OBUF_GROM, + O => cs_147_OBUF + ); + dadrL_BU2551 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N16909, + ADR1 => VCC, + ADR2 => reg_select, + ADR3 => dadrL_N16910, + O => cs_230_OBUF_GROM + ); + cs_230_OBUF_YUSED : X_BUF + port map ( + I => cs_230_OBUF_GROM, + O => cs_230_OBUF + ); + dadrL_BU2463 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N16342, + ADR1 => dadrL_N16341, + ADR2 => VCC, + ADR3 => reg_select, + O => cs_222_OBUF_GROM + ); + cs_222_OBUF_YUSED : X_BUF + port map ( + I => cs_222_OBUF_GROM, + O => cs_222_OBUF + ); + dadrL_BU2375 : X_LUT4 + generic map( + INIT => X"C000" + ) + port map ( + ADR0 => VCC, + ADR1 => dadrL_N15773, + ADR2 => reg_select, + ADR3 => dadrL_N15774, + O => cs_214_OBUF_GROM + ); + cs_214_OBUF_YUSED : X_BUF + port map ( + I => cs_214_OBUF_GROM, + O => cs_214_OBUF + ); + dadrL_BU2287 : X_LUT4 + generic map( + INIT => X"C000" + ) + port map ( + ADR0 => VCC, + ADR1 => dadrL_N15206, + ADR2 => reg_select, + ADR3 => dadrL_N15205, + O => cs_206_OBUF_GROM + ); + cs_206_OBUF_YUSED : X_BUF + port map ( + I => cs_206_OBUF_GROM, + O => cs_206_OBUF + ); + dadrL_BU2199 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N14638, + ADR1 => dadrL_N14637, + ADR2 => VCC, + ADR3 => reg_select, + O => cs_198_OBUF_GROM + ); + cs_198_OBUF_YUSED : X_BUF + port map ( + I => cs_198_OBUF_GROM, + O => cs_198_OBUF + ); + dadrL_BU1671 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N11229, + ADR1 => VCC, + ADR2 => reg_select, + ADR3 => dadrL_N11230, + O => cs_150_OBUF_GROM + ); + cs_150_OBUF_YUSED : X_BUF + port map ( + I => cs_150_OBUF_GROM, + O => cs_150_OBUF + ); + dadrL_BU1583 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N10661, + ADR1 => dadrL_N10662, + ADR2 => VCC, + ADR3 => reg_select, + O => cs_142_OBUF_GROM + ); + cs_142_OBUF_YUSED : X_BUF + port map ( + I => cs_142_OBUF_GROM, + O => cs_142_OBUF + ); + dadrL_BU1495 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N10094, + ADR1 => dadrL_N10093, + ADR2 => VCC, + ADR3 => reg_select, + O => cs_134_OBUF_GROM + ); + cs_134_OBUF_YUSED : X_BUF + port map ( + I => cs_134_OBUF_GROM, + O => cs_134_OBUF + ); + dadrL_BU2705 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => reg_select, + ADR1 => VCC, + ADR2 => dadrL_N17904, + ADR3 => dadrL_N17903, + O => cs_244_OBUF_GROM + ); + cs_244_OBUF_YUSED : X_BUF + port map ( + I => cs_244_OBUF_GROM, + O => cs_244_OBUF + ); + dadrL_BU2617 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => reg_select, + ADR1 => VCC, + ADR2 => dadrL_N17335, + ADR3 => dadrL_N17336, + O => cs_236_OBUF_GROM + ); + cs_236_OBUF_YUSED : X_BUF + port map ( + I => cs_236_OBUF_GROM, + O => cs_236_OBUF + ); + dadrL_BU2529 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N16767, + ADR1 => dadrL_N16768, + ADR2 => VCC, + ADR3 => reg_select, + O => cs_228_OBUF_GROM + ); + cs_228_OBUF_YUSED : X_BUF + port map ( + I => cs_228_OBUF_GROM, + O => cs_228_OBUF + ); + dadrL_BU1913 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N12792, + ADR1 => VCC, + ADR2 => reg_select, + ADR3 => dadrL_N12791, + O => cs_172_OBUF_GROM + ); + cs_172_OBUF_YUSED : X_BUF + port map ( + I => cs_172_OBUF_GROM, + O => cs_172_OBUF + ); + dadrL_BU1825 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N12224, + ADR1 => dadrL_N12223, + ADR2 => VCC, + ADR3 => reg_select, + O => cs_164_OBUF_GROM + ); + cs_164_OBUF_YUSED : X_BUF + port map ( + I => cs_164_OBUF_GROM, + O => cs_164_OBUF + ); + dadrL_BU1737 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N11656, + ADR2 => VCC, + ADR3 => dadrL_N11655, + O => cs_156_OBUF_GROM + ); + cs_156_OBUF_YUSED : X_BUF + port map ( + I => cs_156_OBUF_GROM, + O => cs_156_OBUF + ); + dadrL_BU1649 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N11087, + ADR1 => dadrL_N11088, + ADR2 => VCC, + ADR3 => reg_select, + O => cs_148_OBUF_GROM + ); + cs_148_OBUF_YUSED : X_BUF + port map ( + I => cs_148_OBUF_GROM, + O => cs_148_OBUF + ); + dadrL_BU2650 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N17548, + ADR1 => dadrL_N17549, + ADR2 => VCC, + ADR3 => reg_select, + O => cs_239_OBUF_GROM + ); + cs_239_OBUF_YUSED : X_BUF + port map ( + I => cs_239_OBUF_GROM, + O => cs_239_OBUF + ); + dadrL_BU2562 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => dadrL_N16980, + ADR1 => dadrL_N16981, + ADR2 => reg_select, + ADR3 => VCC, + O => cs_231_OBUF_GROM + ); + cs_231_OBUF_YUSED : X_BUF + port map ( + I => cs_231_OBUF_GROM, + O => cs_231_OBUF + ); + dadrL_BU2474 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N16413, + ADR1 => VCC, + ADR2 => reg_select, + ADR3 => dadrL_N16412, + O => cs_223_OBUF_GROM + ); + cs_223_OBUF_YUSED : X_BUF + port map ( + I => cs_223_OBUF_GROM, + O => cs_223_OBUF + ); + dadrL_BU2386 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => dadrL_N15845, + ADR1 => reg_select, + ADR2 => dadrL_N15844, + ADR3 => VCC, + O => cs_215_OBUF_GROM + ); + cs_215_OBUF_YUSED : X_BUF + port map ( + I => cs_215_OBUF_GROM, + O => cs_215_OBUF + ); + dadrL_BU2298 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => dadrL_N15277, + ADR1 => reg_select, + ADR2 => dadrL_N15276, + ADR3 => VCC, + O => cs_207_OBUF_GROM + ); + cs_207_OBUF_YUSED : X_BUF + port map ( + I => cs_207_OBUF_GROM, + O => cs_207_OBUF + ); + dadrL_BU1770 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N11869, + ADR1 => VCC, + ADR2 => dadrL_N11868, + ADR3 => reg_select, + O => cs_159_OBUF_GROM + ); + cs_159_OBUF_YUSED : X_BUF + port map ( + I => cs_159_OBUF_GROM, + O => cs_159_OBUF + ); + dadrL_BU1682 : X_LUT4 + generic map( + INIT => X"C000" + ) + port map ( + ADR0 => VCC, + ADR1 => reg_select, + ADR2 => dadrL_N11301, + ADR3 => dadrL_N11300, + O => cs_151_OBUF_GROM + ); + cs_151_OBUF_YUSED : X_BUF + port map ( + I => cs_151_OBUF_GROM, + O => cs_151_OBUF + ); + dadrL_BU1594 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N10733, + ADR1 => VCC, + ADR2 => reg_select, + ADR3 => dadrL_N10732, + O => cs_143_OBUF_GROM + ); + cs_143_OBUF_YUSED : X_BUF + port map ( + I => cs_143_OBUF_GROM, + O => cs_143_OBUF + ); + dadrL_BU2804 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N18543, + ADR1 => dadrL_N18542, + ADR2 => VCC, + ADR3 => reg_select, + O => cs_253_OBUF_GROM + ); + cs_253_OBUF_YUSED : X_BUF + port map ( + I => cs_253_OBUF_GROM, + O => cs_253_OBUF + ); + dadrL_BU2716 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N17974, + ADR1 => reg_select, + ADR2 => VCC, + ADR3 => dadrL_N17975, + O => cs_245_OBUF_GROM + ); + cs_245_OBUF_YUSED : X_BUF + port map ( + I => cs_245_OBUF_GROM, + O => cs_245_OBUF + ); + dadrL_BU2628 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N17406, + ADR1 => reg_select, + ADR2 => VCC, + ADR3 => dadrL_N17407, + O => cs_237_OBUF_GROM + ); + cs_237_OBUF_YUSED : X_BUF + port map ( + I => cs_237_OBUF_GROM, + O => cs_237_OBUF + ); + dadrL_BU1924 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => dadrL_N12863, + ADR1 => dadrL_N12862, + ADR2 => reg_select, + ADR3 => VCC, + O => cs_173_OBUF_GROM + ); + cs_173_OBUF_YUSED : X_BUF + port map ( + I => cs_173_OBUF_GROM, + O => cs_173_OBUF + ); + dadrL_BU1836 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N12294, + ADR1 => VCC, + ADR2 => reg_select, + ADR3 => dadrL_N12295, + O => cs_165_OBUF_GROM + ); + cs_165_OBUF_YUSED : X_BUF + port map ( + I => cs_165_OBUF_GROM, + O => cs_165_OBUF + ); + dadrL_BU1748 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N11727, + ADR1 => reg_select, + ADR2 => VCC, + ADR3 => dadrL_N11726, + O => cs_157_OBUF_GROM + ); + cs_157_OBUF_YUSED : X_BUF + port map ( + I => cs_157_OBUF_GROM, + O => cs_157_OBUF + ); + dadrL_BU2661 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => dadrL_N17620, + ADR1 => reg_select, + ADR2 => dadrL_N17619, + ADR3 => VCC, + O => cs_240_OBUF_GROM + ); + cs_240_OBUF_YUSED : X_BUF + port map ( + I => cs_240_OBUF_GROM, + O => cs_240_OBUF + ); + dadrL_BU2573 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => dadrL_N17051, + ADR1 => reg_select, + ADR2 => dadrL_N17052, + ADR3 => VCC, + O => cs_232_OBUF_GROM + ); + cs_232_OBUF_YUSED : X_BUF + port map ( + I => cs_232_OBUF_GROM, + O => cs_232_OBUF + ); + dadrL_BU2485 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N16484, + ADR1 => reg_select, + ADR2 => VCC, + ADR3 => dadrL_N16483, + O => cs_224_OBUF_GROM + ); + cs_224_OBUF_YUSED : X_BUF + port map ( + I => cs_224_OBUF_GROM, + O => cs_224_OBUF + ); + dadrL_BU2397 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N15916, + ADR1 => dadrL_N15915, + ADR2 => VCC, + ADR3 => reg_select, + O => cs_216_OBUF_GROM + ); + cs_216_OBUF_YUSED : X_BUF + port map ( + I => cs_216_OBUF_GROM, + O => cs_216_OBUF + ); + dadrL_BU1781 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N11940, + ADR2 => VCC, + ADR3 => dadrL_N11939, + O => cs_160_OBUF_GROM + ); + cs_160_OBUF_YUSED : X_BUF + port map ( + I => cs_160_OBUF_GROM, + O => cs_160_OBUF + ); + dadrL_BU1693 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N11371, + ADR2 => VCC, + ADR3 => dadrL_N11372, + O => cs_152_OBUF_GROM + ); + cs_152_OBUF_YUSED : X_BUF + port map ( + I => cs_152_OBUF_GROM, + O => cs_152_OBUF + ); + dadrL_BU2815 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => dadrL_N18613, + ADR1 => reg_select, + ADR2 => dadrL_N18614, + ADR3 => VCC, + O => cs_254_OBUF_GROM + ); + cs_254_OBUF_YUSED : X_BUF + port map ( + I => cs_254_OBUF_GROM, + O => cs_254_OBUF + ); + dadrL_BU2727 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N18046, + ADR1 => VCC, + ADR2 => dadrL_N18045, + ADR3 => reg_select, + O => cs_246_OBUF_GROM + ); + cs_246_OBUF_YUSED : X_BUF + port map ( + I => cs_246_OBUF_GROM, + O => cs_246_OBUF + ); + dadrL_BU2639 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => reg_select, + ADR1 => VCC, + ADR2 => dadrL_N17477, + ADR3 => dadrL_N17478, + O => cs_238_OBUF_GROM + ); + cs_238_OBUF_YUSED : X_BUF + port map ( + I => cs_238_OBUF_GROM, + O => cs_238_OBUF + ); + dadrL_BU1935 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => dadrL_N12933, + ADR1 => reg_select, + ADR2 => dadrL_N12934, + ADR3 => VCC, + O => cs_174_OBUF_GROM + ); + cs_174_OBUF_YUSED : X_BUF + port map ( + I => cs_174_OBUF_GROM, + O => cs_174_OBUF + ); + dadrL_BU1847 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => dadrL_N12366, + ADR1 => reg_select, + ADR2 => dadrL_N12365, + ADR3 => VCC, + O => cs_166_OBUF_GROM + ); + cs_166_OBUF_YUSED : X_BUF + port map ( + I => cs_166_OBUF_GROM, + O => cs_166_OBUF + ); + dadrL_BU1759 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N11797, + ADR1 => reg_select, + ADR2 => VCC, + ADR3 => dadrL_N11798, + O => cs_158_OBUF_GROM + ); + cs_158_OBUF_YUSED : X_BUF + port map ( + I => cs_158_OBUF_GROM, + O => cs_158_OBUF + ); + dadrL_BU120 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N1218, + ADR1 => VCC, + ADR2 => reg_select, + ADR3 => dadrL_N1219, + O => cs_9_OBUF_GROM + ); + cs_9_OBUF_YUSED : X_BUF + port map ( + I => cs_9_OBUF_GROM, + O => cs_9_OBUF + ); + dadrL_BU2760 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N18258, + ADR1 => VCC, + ADR2 => reg_select, + ADR3 => dadrL_N18259, + O => cs_249_OBUF_GROM + ); + cs_249_OBUF_YUSED : X_BUF + port map ( + I => cs_249_OBUF_GROM, + O => cs_249_OBUF + ); + dadrL_BU2672 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N17691, + ADR2 => VCC, + ADR3 => dadrL_N17690, + O => cs_241_OBUF_GROM + ); + cs_241_OBUF_YUSED : X_BUF + port map ( + I => cs_241_OBUF_GROM, + O => cs_241_OBUF + ); + dadrL_BU2584 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N17123, + ADR1 => dadrL_N17122, + ADR2 => VCC, + ADR3 => reg_select, + O => cs_233_OBUF_GROM + ); + cs_233_OBUF_YUSED : X_BUF + port map ( + I => cs_233_OBUF_GROM, + O => cs_233_OBUF + ); + dadrL_BU2496 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => reg_select, + ADR1 => VCC, + ADR2 => dadrL_N16554, + ADR3 => dadrL_N16555, + O => cs_225_OBUF_GROM + ); + cs_225_OBUF_YUSED : X_BUF + port map ( + I => cs_225_OBUF_GROM, + O => cs_225_OBUF + ); + dadrL_BU1880 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N12578, + ADR1 => VCC, + ADR2 => reg_select, + ADR3 => dadrL_N12579, + O => cs_169_OBUF_GROM + ); + cs_169_OBUF_YUSED : X_BUF + port map ( + I => cs_169_OBUF_GROM, + O => cs_169_OBUF + ); + dadrL_BU1792 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N12010, + ADR1 => VCC, + ADR2 => reg_select, + ADR3 => dadrL_N12011, + O => cs_161_OBUF_GROM + ); + cs_161_OBUF_YUSED : X_BUF + port map ( + I => cs_161_OBUF_GROM, + O => cs_161_OBUF + ); + dadrL_BU2826 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N18684, + ADR1 => VCC, + ADR2 => reg_select, + ADR3 => dadrL_N18685, + O => cs_255_OBUF_GROM + ); + cs_255_OBUF_YUSED : X_BUF + port map ( + I => cs_255_OBUF_GROM, + O => cs_255_OBUF + ); + dadrL_BU2738 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N18116, + ADR2 => VCC, + ADR3 => dadrL_N18117, + O => cs_247_OBUF_GROM + ); + cs_247_OBUF_YUSED : X_BUF + port map ( + I => cs_247_OBUF_GROM, + O => cs_247_OBUF + ); + dadrL_BU1946 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => dadrL_N13004, + ADR1 => dadrL_N13005, + ADR2 => reg_select, + ADR3 => VCC, + O => cs_175_OBUF_GROM + ); + cs_175_OBUF_YUSED : X_BUF + port map ( + I => cs_175_OBUF_GROM, + O => cs_175_OBUF + ); + dadrL_BU1858 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N12436, + ADR1 => VCC, + ADR2 => reg_select, + ADR3 => dadrL_N12437, + O => cs_167_OBUF_GROM + ); + cs_167_OBUF_YUSED : X_BUF + port map ( + I => cs_167_OBUF_GROM, + O => cs_167_OBUF + ); + dadrL_BU131 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => dadrL_N1289, + ADR1 => dadrL_N1290, + ADR2 => reg_select, + ADR3 => VCC, + O => cs_10_OBUF_GROM + ); + cs_10_OBUF_YUSED : X_BUF + port map ( + I => cs_10_OBUF_GROM, + O => cs_10_OBUF + ); + dadrL_BU2771 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N18330, + ADR1 => VCC, + ADR2 => reg_select, + ADR3 => dadrL_N18329, + O => cs_250_OBUF_GROM + ); + cs_250_OBUF_YUSED : X_BUF + port map ( + I => cs_250_OBUF_GROM, + O => cs_250_OBUF + ); + dadrL_BU2683 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N17761, + ADR1 => VCC, + ADR2 => dadrL_N17762, + ADR3 => reg_select, + O => cs_242_OBUF_GROM + ); + cs_242_OBUF_YUSED : X_BUF + port map ( + I => cs_242_OBUF_GROM, + O => cs_242_OBUF + ); + dadrL_BU2595 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => reg_select, + ADR1 => VCC, + ADR2 => dadrL_N17194, + ADR3 => dadrL_N17193, + O => cs_234_OBUF_GROM + ); + cs_234_OBUF_YUSED : X_BUF + port map ( + I => cs_234_OBUF_GROM, + O => cs_234_OBUF + ); + dadrL_BU1891 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => reg_select, + ADR1 => VCC, + ADR2 => dadrL_N12649, + ADR3 => dadrL_N12650, + O => cs_170_OBUF_GROM + ); + cs_170_OBUF_YUSED : X_BUF + port map ( + I => cs_170_OBUF_GROM, + O => cs_170_OBUF + ); + dadrL_BU109 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N1147, + ADR1 => dadrL_N1148, + ADR2 => VCC, + ADR3 => reg_select, + O => cs_8_OBUF_GROM + ); + cs_8_OBUF_YUSED : X_BUF + port map ( + I => cs_8_OBUF_GROM, + O => cs_8_OBUF + ); + dadrL_BU2749 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N18187, + ADR1 => VCC, + ADR2 => dadrL_N18188, + ADR3 => reg_select, + O => cs_248_OBUF_GROM + ); + cs_248_OBUF_YUSED : X_BUF + port map ( + I => cs_248_OBUF_GROM, + O => cs_248_OBUF + ); + dadrL_BU1957 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N13076, + ADR1 => VCC, + ADR2 => dadrL_N13075, + ADR3 => reg_select, + O => cs_176_OBUF_GROM + ); + cs_176_OBUF_YUSED : X_BUF + port map ( + I => cs_176_OBUF_GROM, + O => cs_176_OBUF + ); + dadrL_BU1869 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => dadrL_N12508, + ADR1 => reg_select, + ADR2 => dadrL_N12507, + ADR3 => VCC, + O => cs_168_OBUF_GROM + ); + cs_168_OBUF_YUSED : X_BUF + port map ( + I => cs_168_OBUF_GROM, + O => cs_168_OBUF + ); + dadrL_BU230 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => reg_select, + ADR1 => VCC, + ADR2 => dadrL_N1929, + ADR3 => dadrL_N1928, + O => cs_19_OBUF_GROM + ); + cs_19_OBUF_YUSED : X_BUF + port map ( + I => cs_19_OBUF_GROM, + O => cs_19_OBUF + ); + dadrL_BU142 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N1360, + ADR1 => VCC, + ADR2 => reg_select, + ADR3 => dadrL_N1361, + O => cs_11_OBUF_GROM + ); + cs_11_OBUF_YUSED : X_BUF + port map ( + I => cs_11_OBUF_GROM, + O => cs_11_OBUF + ); + dadrL_BU2782 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N18400, + ADR1 => reg_select, + ADR2 => VCC, + ADR3 => dadrL_N18401, + O => cs_251_OBUF_GROM + ); + cs_251_OBUF_YUSED : X_BUF + port map ( + I => cs_251_OBUF_GROM, + O => cs_251_OBUF + ); + dadrL_BU2694 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N17833, + ADR1 => reg_select, + ADR2 => VCC, + ADR3 => dadrL_N17832, + O => cs_243_OBUF_GROM + ); + cs_243_OBUF_YUSED : X_BUF + port map ( + I => cs_243_OBUF_GROM, + O => cs_243_OBUF + ); + dadrL_BU1990 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => reg_select, + ADR1 => VCC, + ADR2 => dadrL_N13288, + ADR3 => dadrL_N13289, + O => cs_179_OBUF_GROM + ); + cs_179_OBUF_YUSED : X_BUF + port map ( + I => cs_179_OBUF_GROM, + O => cs_179_OBUF + ); + dadrL_BU208 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => reg_select, + ADR1 => VCC, + ADR2 => dadrL_N1786, + ADR3 => dadrL_N1787, + O => cs_17_OBUF_GROM + ); + cs_17_OBUF_YUSED : X_BUF + port map ( + I => cs_17_OBUF_GROM, + O => cs_17_OBUF + ); + dadrL_BU1968 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N13146, + ADR1 => dadrL_N13147, + ADR2 => VCC, + ADR3 => reg_select, + O => cs_177_OBUF_GROM + ); + cs_177_OBUF_YUSED : X_BUF + port map ( + I => cs_177_OBUF_GROM, + O => cs_177_OBUF + ); + dadrL_BU241 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N1999, + ADR1 => reg_select, + ADR2 => VCC, + ADR3 => dadrL_N2000, + O => cs_20_OBUF_GROM + ); + cs_20_OBUF_YUSED : X_BUF + port map ( + I => cs_20_OBUF_GROM, + O => cs_20_OBUF + ); + dadrL_BU153 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => dadrL_N1432, + ADR1 => dadrL_N1431, + ADR2 => reg_select, + ADR3 => VCC, + O => cs_12_OBUF_GROM + ); + cs_12_OBUF_YUSED : X_BUF + port map ( + I => cs_12_OBUF_GROM, + O => cs_12_OBUF + ); + dadrL_BU2793 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => reg_select, + ADR1 => VCC, + ADR2 => dadrL_N18472, + ADR3 => dadrL_N18471, + O => cs_252_OBUF_GROM + ); + cs_252_OBUF_YUSED : X_BUF + port map ( + I => cs_252_OBUF_GROM, + O => cs_252_OBUF + ); + dadrL_BU307 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N2425, + ADR1 => VCC, + ADR2 => reg_select, + ADR3 => dadrL_N2426, + O => cs_26_OBUF_GROM + ); + cs_26_OBUF_YUSED : X_BUF + port map ( + I => cs_26_OBUF_GROM, + O => cs_26_OBUF + ); + dadrL_BU219 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N1857, + ADR1 => reg_select, + ADR2 => VCC, + ADR3 => dadrL_N1858, + O => cs_18_OBUF_GROM + ); + cs_18_OBUF_YUSED : X_BUF + port map ( + I => cs_18_OBUF_GROM, + O => cs_18_OBUF + ); + dadrL_BU1979 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N13217, + ADR1 => VCC, + ADR2 => reg_select, + ADR3 => dadrL_N13218, + O => cs_178_OBUF_GROM + ); + cs_178_OBUF_YUSED : X_BUF + port map ( + I => cs_178_OBUF_GROM, + O => cs_178_OBUF + ); + dadrL_BU340 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => reg_select, + ADR1 => VCC, + ADR2 => dadrL_N2638, + ADR3 => dadrL_N2639, + O => cs_29_OBUF_GROM + ); + cs_29_OBUF_YUSED : X_BUF + port map ( + I => cs_29_OBUF_GROM, + O => cs_29_OBUF + ); + dadrL_BU252 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => reg_select, + ADR1 => VCC, + ADR2 => dadrL_N2071, + ADR3 => dadrL_N2070, + O => cs_21_OBUF_GROM + ); + cs_21_OBUF_YUSED : X_BUF + port map ( + I => cs_21_OBUF_GROM, + O => cs_21_OBUF + ); + dadrL_BU164 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N1502, + ADR1 => VCC, + ADR2 => dadrL_N1503, + ADR3 => reg_select, + O => cs_13_OBUF_GROM + ); + cs_13_OBUF_YUSED : X_BUF + port map ( + I => cs_13_OBUF_GROM, + O => cs_13_OBUF + ); + dadrL_BU406 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N3064, + ADR1 => dadrL_N3065, + ADR2 => VCC, + ADR3 => reg_select, + O => cs_35_OBUF_GROM + ); + cs_35_OBUF_YUSED : X_BUF + port map ( + I => cs_35_OBUF_GROM, + O => cs_35_OBUF + ); + dadrL_BU318 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => reg_select, + ADR1 => VCC, + ADR2 => dadrL_N2497, + ADR3 => dadrL_N2496, + O => cs_27_OBUF_GROM + ); + cs_27_OBUF_YUSED : X_BUF + port map ( + I => cs_27_OBUF_GROM, + O => cs_27_OBUF + ); + dadrL_BU351 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N2709, + ADR1 => VCC, + ADR2 => reg_select, + ADR3 => dadrL_N2710, + O => cs_30_OBUF_GROM + ); + cs_30_OBUF_YUSED : X_BUF + port map ( + I => cs_30_OBUF_GROM, + O => cs_30_OBUF + ); + dadrL_BU263 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => dadrL_N2142, + ADR1 => dadrL_N2141, + ADR2 => reg_select, + ADR3 => VCC, + O => cs_22_OBUF_GROM + ); + cs_22_OBUF_YUSED : X_BUF + port map ( + I => cs_22_OBUF_GROM, + O => cs_22_OBUF + ); + dadrL_BU175 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N1574, + ADR1 => dadrL_N1573, + ADR2 => VCC, + ADR3 => reg_select, + O => cs_14_OBUF_GROM + ); + cs_14_OBUF_YUSED : X_BUF + port map ( + I => cs_14_OBUF_GROM, + O => cs_14_OBUF + ); + dadrL_BU505 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N3703, + ADR1 => VCC, + ADR2 => dadrL_N3704, + ADR3 => reg_select, + O => cs_44_OBUF_GROM + ); + cs_44_OBUF_YUSED : X_BUF + port map ( + I => cs_44_OBUF_GROM, + O => cs_44_OBUF + ); + dadrL_BU417 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N3135, + ADR1 => VCC, + ADR2 => reg_select, + ADR3 => dadrL_N3136, + O => cs_36_OBUF_GROM + ); + cs_36_OBUF_YUSED : X_BUF + port map ( + I => cs_36_OBUF_GROM, + O => cs_36_OBUF + ); + dadrL_BU329 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N2567, + ADR1 => VCC, + ADR2 => reg_select, + ADR3 => dadrL_N2568, + O => cs_28_OBUF_GROM + ); + cs_28_OBUF_YUSED : X_BUF + port map ( + I => cs_28_OBUF_GROM, + O => cs_28_OBUF + ); + dadrL_BU450 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => dadrL_N3348, + ADR1 => dadrL_N3349, + ADR2 => reg_select, + ADR3 => VCC, + O => cs_39_OBUF_GROM + ); + cs_39_OBUF_YUSED : X_BUF + port map ( + I => cs_39_OBUF_GROM, + O => cs_39_OBUF + ); + dadrL_BU362 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => reg_select, + ADR1 => VCC, + ADR2 => dadrL_N2780, + ADR3 => dadrL_N2781, + O => cs_31_OBUF_GROM + ); + cs_31_OBUF_YUSED : X_BUF + port map ( + I => cs_31_OBUF_GROM, + O => cs_31_OBUF + ); + dadrL_BU274 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => dadrL_N2212, + ADR1 => reg_select, + ADR2 => dadrL_N2213, + ADR3 => VCC, + O => cs_23_OBUF_GROM + ); + cs_23_OBUF_YUSED : X_BUF + port map ( + I => cs_23_OBUF_GROM, + O => cs_23_OBUF + ); + dadrL_BU186 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => reg_select, + ADR1 => VCC, + ADR2 => dadrL_N1645, + ADR3 => dadrL_N1644, + O => cs_15_OBUF_GROM + ); + cs_15_OBUF_YUSED : X_BUF + port map ( + I => cs_15_OBUF_GROM, + O => cs_15_OBUF + ); + dadrL_BU604 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N4343, + ADR1 => VCC, + ADR2 => reg_select, + ADR3 => dadrL_N4342, + O => cs_53_OBUF_GROM + ); + cs_53_OBUF_YUSED : X_BUF + port map ( + I => cs_53_OBUF_GROM, + O => cs_53_OBUF + ); + dadrL_BU516 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N3774, + ADR1 => dadrL_N3775, + ADR2 => VCC, + ADR3 => reg_select, + O => cs_45_OBUF_GROM + ); + cs_45_OBUF_YUSED : X_BUF + port map ( + I => cs_45_OBUF_GROM, + O => cs_45_OBUF + ); + dadrL_BU428 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N3206, + ADR1 => dadrL_N3207, + ADR2 => VCC, + ADR3 => reg_select, + O => cs_37_OBUF_GROM + ); + cs_37_OBUF_YUSED : X_BUF + port map ( + I => cs_37_OBUF_GROM, + O => cs_37_OBUF + ); + dadrL_BU461 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => dadrL_N3420, + ADR1 => reg_select, + ADR2 => dadrL_N3419, + ADR3 => VCC, + O => cs_40_OBUF_GROM + ); + cs_40_OBUF_YUSED : X_BUF + port map ( + I => cs_40_OBUF_GROM, + O => cs_40_OBUF + ); + dadrL_BU373 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N2851, + ADR1 => dadrL_N2852, + ADR2 => VCC, + ADR3 => reg_select, + O => cs_32_OBUF_GROM + ); + cs_32_OBUF_YUSED : X_BUF + port map ( + I => cs_32_OBUF_GROM, + O => cs_32_OBUF + ); + dadrL_BU285 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N2284, + ADR1 => dadrL_N2283, + ADR2 => VCC, + ADR3 => reg_select, + O => cs_24_OBUF_GROM + ); + cs_24_OBUF_YUSED : X_BUF + port map ( + I => cs_24_OBUF_GROM, + O => cs_24_OBUF + ); + dadrL_BU197 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N1715, + ADR1 => VCC, + ADR2 => reg_select, + ADR3 => dadrL_N1716, + O => cs_16_OBUF_GROM + ); + cs_16_OBUF_YUSED : X_BUF + port map ( + I => cs_16_OBUF_GROM, + O => cs_16_OBUF + ); + dadrL_BU703 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N4982, + ADR1 => VCC, + ADR2 => reg_select, + ADR3 => dadrL_N4981, + O => cs_62_OBUF_GROM + ); + cs_62_OBUF_YUSED : X_BUF + port map ( + I => cs_62_OBUF_GROM, + O => cs_62_OBUF + ); + dadrL_BU615 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => reg_select, + ADR1 => VCC, + ADR2 => dadrL_N4414, + ADR3 => dadrL_N4413, + O => cs_54_OBUF_GROM + ); + cs_54_OBUF_YUSED : X_BUF + port map ( + I => cs_54_OBUF_GROM, + O => cs_54_OBUF + ); + dadrL_BU527 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N3845, + ADR1 => VCC, + ADR2 => reg_select, + ADR3 => dadrL_N3846, + O => cs_46_OBUF_GROM + ); + cs_46_OBUF_YUSED : X_BUF + port map ( + I => cs_46_OBUF_GROM, + O => cs_46_OBUF + ); + dadrL_BU439 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N3278, + ADR1 => VCC, + ADR2 => dadrL_N3277, + ADR3 => reg_select, + O => cs_38_OBUF_GROM + ); + cs_38_OBUF_YUSED : X_BUF + port map ( + I => cs_38_OBUF_GROM, + O => cs_38_OBUF + ); + dadrL_BU560 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N4058, + ADR1 => VCC, + ADR2 => reg_select, + ADR3 => dadrL_N4059, + O => cs_49_OBUF_GROM + ); + cs_49_OBUF_YUSED : X_BUF + port map ( + I => cs_49_OBUF_GROM, + O => cs_49_OBUF + ); + dadrL_BU472 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N3490, + ADR1 => reg_select, + ADR2 => VCC, + ADR3 => dadrL_N3491, + O => cs_41_OBUF_GROM + ); + cs_41_OBUF_YUSED : X_BUF + port map ( + I => cs_41_OBUF_GROM, + O => cs_41_OBUF + ); + dadrL_BU384 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N2923, + ADR1 => reg_select, + ADR2 => VCC, + ADR3 => dadrL_N2922, + O => cs_33_OBUF_GROM + ); + cs_33_OBUF_YUSED : X_BUF + port map ( + I => cs_33_OBUF_GROM, + O => cs_33_OBUF + ); + dadrL_BU296 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => dadrL_N2355, + ADR1 => reg_select, + ADR2 => dadrL_N2354, + ADR3 => VCC, + O => cs_25_OBUF_GROM + ); + cs_25_OBUF_YUSED : X_BUF + port map ( + I => cs_25_OBUF_GROM, + O => cs_25_OBUF + ); + dadrL_BU802 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N5620, + ADR1 => VCC, + ADR2 => reg_select, + ADR3 => dadrL_N5621, + O => cs_71_OBUF_GROM + ); + cs_71_OBUF_YUSED : X_BUF + port map ( + I => cs_71_OBUF_GROM, + O => cs_71_OBUF + ); + dadrL_BU714 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => dadrL_N5053, + ADR1 => dadrL_N5052, + ADR2 => reg_select, + ADR3 => VCC, + O => cs_63_OBUF_GROM + ); + cs_63_OBUF_YUSED : X_BUF + port map ( + I => cs_63_OBUF_GROM, + O => cs_63_OBUF + ); + dadrL_BU626 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N4485, + ADR2 => VCC, + ADR3 => dadrL_N4484, + O => cs_55_OBUF_GROM + ); + cs_55_OBUF_YUSED : X_BUF + port map ( + I => cs_55_OBUF_GROM, + O => cs_55_OBUF + ); + dadrL_BU538 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N3916, + ADR1 => VCC, + ADR2 => reg_select, + ADR3 => dadrL_N3917, + O => cs_47_OBUF_GROM + ); + cs_47_OBUF_YUSED : X_BUF + port map ( + I => cs_47_OBUF_GROM, + O => cs_47_OBUF + ); + dadrL_BU571 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => reg_select, + ADR1 => VCC, + ADR2 => dadrL_N4129, + ADR3 => dadrL_N4130, + O => cs_50_OBUF_GROM + ); + cs_50_OBUF_YUSED : X_BUF + port map ( + I => cs_50_OBUF_GROM, + O => cs_50_OBUF + ); + dadrL_BU483 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => reg_select, + ADR1 => VCC, + ADR2 => dadrL_N3562, + ADR3 => dadrL_N3561, + O => cs_42_OBUF_GROM + ); + cs_42_OBUF_YUSED : X_BUF + port map ( + I => cs_42_OBUF_GROM, + O => cs_42_OBUF + ); + dadrL_BU395 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => reg_select, + ADR1 => VCC, + ADR2 => dadrL_N2993, + ADR3 => dadrL_N2994, + O => cs_34_OBUF_GROM + ); + cs_34_OBUF_YUSED : X_BUF + port map ( + I => cs_34_OBUF_GROM, + O => cs_34_OBUF + ); + dadrL_BU901 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N6259, + ADR1 => reg_select, + ADR2 => VCC, + ADR3 => dadrL_N6260, + O => cs_80_OBUF_GROM + ); + cs_80_OBUF_YUSED : X_BUF + port map ( + I => cs_80_OBUF_GROM, + O => cs_80_OBUF + ); + dadrL_BU813 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N5692, + ADR1 => dadrL_N5691, + ADR2 => VCC, + ADR3 => reg_select, + O => cs_72_OBUF_GROM + ); + cs_72_OBUF_YUSED : X_BUF + port map ( + I => cs_72_OBUF_GROM, + O => cs_72_OBUF + ); + dadrL_BU725 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => dadrL_N5123, + ADR1 => reg_select, + ADR2 => dadrL_N5124, + ADR3 => VCC, + O => cs_64_OBUF_GROM + ); + cs_64_OBUF_YUSED : X_BUF + port map ( + I => cs_64_OBUF_GROM, + O => cs_64_OBUF + ); + dadrL_BU637 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N4556, + ADR1 => VCC, + ADR2 => dadrL_N4555, + ADR3 => reg_select, + O => cs_56_OBUF_GROM + ); + cs_56_OBUF_YUSED : X_BUF + port map ( + I => cs_56_OBUF_GROM, + O => cs_56_OBUF + ); + dadrL_BU549 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => reg_select, + ADR1 => VCC, + ADR2 => dadrL_N3987, + ADR3 => dadrL_N3988, + O => cs_48_OBUF_GROM + ); + cs_48_OBUF_YUSED : X_BUF + port map ( + I => cs_48_OBUF_GROM, + O => cs_48_OBUF + ); + dadrL_BU670 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N4768, + ADR1 => dadrL_N4769, + ADR2 => VCC, + ADR3 => reg_select, + O => cs_59_OBUF_GROM + ); + cs_59_OBUF_YUSED : X_BUF + port map ( + I => cs_59_OBUF_GROM, + O => cs_59_OBUF + ); + dadrL_BU582 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N4200, + ADR1 => VCC, + ADR2 => reg_select, + ADR3 => dadrL_N4201, + O => cs_51_OBUF_GROM + ); + cs_51_OBUF_YUSED : X_BUF + port map ( + I => cs_51_OBUF_GROM, + O => cs_51_OBUF + ); + dadrL_BU494 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N3632, + ADR1 => reg_select, + ADR2 => VCC, + ADR3 => dadrL_N3633, + O => cs_43_OBUF_GROM + ); + cs_43_OBUF_YUSED : X_BUF + port map ( + I => cs_43_OBUF_GROM, + O => cs_43_OBUF + ); + dadrL_BU912 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => reg_select, + ADR1 => VCC, + ADR2 => dadrL_N6330, + ADR3 => dadrL_N6331, + O => cs_81_OBUF_GROM + ); + cs_81_OBUF_YUSED : X_BUF + port map ( + I => cs_81_OBUF_GROM, + O => cs_81_OBUF + ); + dadrL_BU824 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N5763, + ADR1 => VCC, + ADR2 => reg_select, + ADR3 => dadrL_N5762, + O => cs_73_OBUF_GROM + ); + cs_73_OBUF_YUSED : X_BUF + port map ( + I => cs_73_OBUF_GROM, + O => cs_73_OBUF + ); + dadrL_BU736 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N5194, + ADR1 => VCC, + ADR2 => reg_select, + ADR3 => dadrL_N5195, + O => cs_65_OBUF_GROM + ); + cs_65_OBUF_YUSED : X_BUF + port map ( + I => cs_65_OBUF_GROM, + O => cs_65_OBUF + ); + dadrL_BU648 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N4626, + ADR1 => reg_select, + ADR2 => VCC, + ADR3 => dadrL_N4627, + O => cs_57_OBUF_GROM + ); + cs_57_OBUF_YUSED : X_BUF + port map ( + I => cs_57_OBUF_GROM, + O => cs_57_OBUF + ); + dadrL_BU681 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => reg_select, + ADR1 => VCC, + ADR2 => dadrL_N4839, + ADR3 => dadrL_N4840, + O => cs_60_OBUF_GROM + ); + cs_60_OBUF_YUSED : X_BUF + port map ( + I => cs_60_OBUF_GROM, + O => cs_60_OBUF + ); + dadrL_BU593 : X_LUT4 + generic map( + INIT => X"C000" + ) + port map ( + ADR0 => VCC, + ADR1 => reg_select, + ADR2 => dadrL_N4271, + ADR3 => dadrL_N4272, + O => cs_52_OBUF_GROM + ); + cs_52_OBUF_YUSED : X_BUF + port map ( + I => cs_52_OBUF_GROM, + O => cs_52_OBUF + ); + dadrL_BU923 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N6402, + ADR1 => dadrL_N6401, + ADR2 => VCC, + ADR3 => reg_select, + O => cs_82_OBUF_GROM + ); + cs_82_OBUF_YUSED : X_BUF + port map ( + I => cs_82_OBUF_GROM, + O => cs_82_OBUF + ); + dadrL_BU835 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => dadrL_N5834, + ADR1 => dadrL_N5833, + ADR2 => reg_select, + ADR3 => VCC, + O => cs_74_OBUF_GROM + ); + cs_74_OBUF_YUSED : X_BUF + port map ( + I => cs_74_OBUF_GROM, + O => cs_74_OBUF + ); + dadrL_BU747 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => dadrL_N5265, + ADR1 => dadrL_N5266, + ADR2 => reg_select, + ADR3 => VCC, + O => cs_66_OBUF_GROM + ); + cs_66_OBUF_YUSED : X_BUF + port map ( + I => cs_66_OBUF_GROM, + O => cs_66_OBUF + ); + dadrL_BU659 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N4697, + ADR1 => VCC, + ADR2 => reg_select, + ADR3 => dadrL_N4698, + O => cs_58_OBUF_GROM + ); + cs_58_OBUF_YUSED : X_BUF + port map ( + I => cs_58_OBUF_GROM, + O => cs_58_OBUF + ); + dadrL_BU780 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N5478, + ADR1 => VCC, + ADR2 => reg_select, + ADR3 => dadrL_N5479, + O => cs_69_OBUF_GROM + ); + cs_69_OBUF_YUSED : X_BUF + port map ( + I => cs_69_OBUF_GROM, + O => cs_69_OBUF + ); + dadrL_BU692 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N4910, + ADR1 => dadrL_N4911, + ADR2 => VCC, + ADR3 => reg_select, + O => cs_61_OBUF_GROM + ); + cs_61_OBUF_YUSED : X_BUF + port map ( + I => cs_61_OBUF_GROM, + O => cs_61_OBUF + ); + dadrL_BU934 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N6473, + ADR1 => VCC, + ADR2 => reg_select, + ADR3 => dadrL_N6472, + O => cs_83_OBUF_GROM + ); + cs_83_OBUF_YUSED : X_BUF + port map ( + I => cs_83_OBUF_GROM, + O => cs_83_OBUF + ); + dadrL_BU846 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => dadrL_N5905, + ADR1 => reg_select, + ADR2 => dadrL_N5904, + ADR3 => VCC, + O => cs_75_OBUF_GROM + ); + cs_75_OBUF_YUSED : X_BUF + port map ( + I => cs_75_OBUF_GROM, + O => cs_75_OBUF + ); + dadrL_BU758 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N5336, + ADR1 => reg_select, + ADR2 => VCC, + ADR3 => dadrL_N5337, + O => cs_67_OBUF_GROM + ); + cs_67_OBUF_YUSED : X_BUF + port map ( + I => cs_67_OBUF_GROM, + O => cs_67_OBUF + ); + dadrL_BU791 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N5549, + ADR1 => dadrL_N5550, + ADR2 => VCC, + ADR3 => reg_select, + O => cs_70_OBUF_GROM + ); + cs_70_OBUF_YUSED : X_BUF + port map ( + I => cs_70_OBUF_GROM, + O => cs_70_OBUF + ); + dadrL_BU945 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N6543, + ADR1 => VCC, + ADR2 => dadrL_N6544, + ADR3 => reg_select, + O => cs_84_OBUF_GROM + ); + cs_84_OBUF_YUSED : X_BUF + port map ( + I => cs_84_OBUF_GROM, + O => cs_84_OBUF + ); + dadrL_BU857 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N5975, + ADR1 => VCC, + ADR2 => reg_select, + ADR3 => dadrL_N5976, + O => cs_76_OBUF_GROM + ); + cs_76_OBUF_YUSED : X_BUF + port map ( + I => cs_76_OBUF_GROM, + O => cs_76_OBUF + ); + dadrL_BU769 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N5407, + ADR1 => dadrL_N5408, + ADR2 => VCC, + ADR3 => reg_select, + O => cs_68_OBUF_GROM + ); + cs_68_OBUF_YUSED : X_BUF + port map ( + I => cs_68_OBUF_GROM, + O => cs_68_OBUF + ); + dadrL_BU890 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N6188, + ADR1 => VCC, + ADR2 => reg_select, + ADR3 => dadrL_N6189, + O => cs_79_OBUF_GROM + ); + cs_79_OBUF_YUSED : X_BUF + port map ( + I => cs_79_OBUF_GROM, + O => cs_79_OBUF + ); + dadrL_BU956 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N6615, + ADR1 => VCC, + ADR2 => reg_select, + ADR3 => dadrL_N6614, + O => cs_85_OBUF_GROM + ); + cs_85_OBUF_YUSED : X_BUF + port map ( + I => cs_85_OBUF_GROM, + O => cs_85_OBUF + ); + dadrL_BU868 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N6047, + ADR1 => VCC, + ADR2 => dadrL_N6046, + ADR3 => reg_select, + O => cs_77_OBUF_GROM + ); + cs_77_OBUF_YUSED : X_BUF + port map ( + I => cs_77_OBUF_GROM, + O => cs_77_OBUF + ); + dadrL_BU967 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N6685, + ADR1 => dadrL_N6686, + ADR2 => VCC, + ADR3 => reg_select, + O => cs_86_OBUF_GROM + ); + cs_86_OBUF_YUSED : X_BUF + port map ( + I => cs_86_OBUF_GROM, + O => cs_86_OBUF + ); + dadrL_BU879 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => dadrL_N6117, + ADR1 => dadrL_N6118, + ADR2 => reg_select, + ADR3 => VCC, + O => cs_78_OBUF_GROM + ); + cs_78_OBUF_YUSED : X_BUF + port map ( + I => cs_78_OBUF_GROM, + O => cs_78_OBUF + ); + dadrL_BU978 : X_LUT4 + generic map( + INIT => X"A000" + ) + port map ( + ADR0 => dadrL_N6756, + ADR1 => VCC, + ADR2 => reg_select, + ADR3 => dadrL_N6757, + O => cs_87_OBUF_GROM + ); + cs_87_OBUF_YUSED : X_BUF + port map ( + I => cs_87_OBUF_GROM, + O => cs_87_OBUF + ); + dadrL_BU989 : X_LUT4 + generic map( + INIT => X"8800" + ) + port map ( + ADR0 => dadrL_N6827, + ADR1 => dadrL_N6828, + ADR2 => VCC, + ADR3 => reg_select, + O => cs_88_OBUF_GROM + ); + cs_88_OBUF_YUSED : X_BUF + port map ( + I => cs_88_OBUF_GROM, + O => cs_88_OBUF + ); + rw_OBUF_69 : X_TRI + port map ( + I => rw_OUTMUX, + CTL => rw_ENABLE, + O => rw + ); + rw_ENABLEINV : X_INV + port map ( + I => rw_TORGTS, + O => rw_ENABLE + ); + rw_GTS_OR : X_BUF + port map ( + I => GTS, + O => rw_TORGTS + ); + rw_OUTMUX_70 : X_BUF + port map ( + I => rw_OBUF, + O => rw_OUTMUX + ); + adr_bus_0_IMUX : X_BUF + port map ( + I => adr_bus_0_IBUF_0, + O => adr_bus_0_IBUF + ); + adr_bus_0_IBUF_71 : X_BUF + port map ( + I => adr_bus(0), + O => adr_bus_0_IBUF_0 + ); + adr_bus_1_IMUX : X_BUF + port map ( + I => adr_bus_1_IBUF_1, + O => adr_bus_1_IBUF + ); + adr_bus_1_IBUF_72 : X_BUF + port map ( + I => adr_bus(1), + O => adr_bus_1_IBUF_1 + ); + adr_bus_2_IMUX : X_BUF + port map ( + I => adr_bus_2_IBUF_2, + O => adr_bus_2_IBUF + ); + adr_bus_2_IBUF_73 : X_BUF + port map ( + I => adr_bus(2), + O => adr_bus_2_IBUF_2 + ); + adr_bus_3_IMUX : X_BUF + port map ( + I => adr_bus_3_IBUF_3, + O => adr_bus_3_IBUF + ); + adr_bus_3_IBUF_74 : X_BUF + port map ( + I => adr_bus(3), + O => adr_bus_3_IBUF_3 + ); + adr_bus_4_IMUX : X_BUF + port map ( + I => adr_bus_4_IBUF_4, + O => adr_bus_4_IBUF + ); + adr_bus_4_IBUF_75 : X_BUF + port map ( + I => adr_bus(4), + O => adr_bus_4_IBUF_4 + ); + adr_bus_5_IMUX : X_BUF + port map ( + I => adr_bus_5_IBUF_5, + O => adr_bus_5_IBUF + ); + adr_bus_5_IBUF_76 : X_BUF + port map ( + I => adr_bus(5), + O => adr_bus_5_IBUF_5 + ); + adr_bus_6_IMUX : X_BUF + port map ( + I => adr_bus_6_IBUF_6, + O => adr_bus_6_IBUF + ); + adr_bus_6_IBUF_77 : X_BUF + port map ( + I => adr_bus(6), + O => adr_bus_6_IBUF_6 + ); + adr_bus_7_IMUX : X_BUF + port map ( + I => adr_bus_7_IBUF_7, + O => adr_bus_7_IBUF + ); + adr_bus_7_IBUF_78 : X_BUF + port map ( + I => adr_bus(7), + O => adr_bus_7_IBUF_7 + ); + adr_bus_8_IMUX : X_BUF + port map ( + I => adr_bus_8_IBUF_8, + O => adr_bus_8_IBUF + ); + adr_bus_8_IBUF_79 : X_BUF + port map ( + I => adr_bus(8), + O => adr_bus_8_IBUF_8 + ); + adr_bus_9_IMUX : X_BUF + port map ( + I => adr_bus_9_IBUF_9, + O => adr_bus_9_IBUF + ); + adr_bus_9_IBUF_80 : X_BUF + port map ( + I => adr_bus(9), + O => adr_bus_9_IBUF_9 + ); + AEN_IMUX : X_BUF + port map ( + I => AEN_IBUF_10, + O => AEN_IBUF + ); + AEN_IBUF_81 : X_BUF + port map ( + I => AEN, + O => AEN_IBUF_10 + ); + IOR_IMUX : X_BUF + port map ( + I => IOR_IBUF_11, + O => IOR_IBUF + ); + IOR_IBUF_82 : X_BUF + port map ( + I => IOR, + O => IOR_IBUF_11 + ); + IOW_IMUX : X_BUF + port map ( + I => IOW_IBUF_12, + O => IOW_IBUF + ); + IOW_IBUF_83 : X_BUF + port map ( + I => IOW, + O => IOW_IBUF_12 + ); + cs_100_OBUF_84 : X_TRI + port map ( + I => cs_100_OUTMUX, + CTL => cs_100_ENABLE, + O => cs(100) + ); + cs_100_ENABLEINV : X_INV + port map ( + I => cs_100_TORGTS, + O => cs_100_ENABLE + ); + cs_100_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_100_TORGTS + ); + cs_100_OUTMUX_85 : X_BUF + port map ( + I => cs_100_OBUF, + O => cs_100_OUTMUX + ); + cs_101_OBUF_86 : X_TRI + port map ( + I => cs_101_OUTMUX, + CTL => cs_101_ENABLE, + O => cs(101) + ); + cs_101_ENABLEINV : X_INV + port map ( + I => cs_101_TORGTS, + O => cs_101_ENABLE + ); + cs_101_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_101_TORGTS + ); + cs_101_OUTMUX_87 : X_BUF + port map ( + I => cs_101_OBUF, + O => cs_101_OUTMUX + ); + cs_102_OBUF_88 : X_TRI + port map ( + I => cs_102_OUTMUX, + CTL => cs_102_ENABLE, + O => cs(102) + ); + cs_102_ENABLEINV : X_INV + port map ( + I => cs_102_TORGTS, + O => cs_102_ENABLE + ); + cs_102_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_102_TORGTS + ); + cs_102_OUTMUX_89 : X_BUF + port map ( + I => cs_102_OBUF, + O => cs_102_OUTMUX + ); + cs_110_OBUF_90 : X_TRI + port map ( + I => cs_110_OUTMUX, + CTL => cs_110_ENABLE, + O => cs(110) + ); + cs_110_ENABLEINV : X_INV + port map ( + I => cs_110_TORGTS, + O => cs_110_ENABLE + ); + cs_110_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_110_TORGTS + ); + cs_110_OUTMUX_91 : X_BUF + port map ( + I => cs_110_OBUF, + O => cs_110_OUTMUX + ); + cs_103_OBUF_92 : X_TRI + port map ( + I => cs_103_OUTMUX, + CTL => cs_103_ENABLE, + O => cs(103) + ); + cs_103_ENABLEINV : X_INV + port map ( + I => cs_103_TORGTS, + O => cs_103_ENABLE + ); + cs_103_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_103_TORGTS + ); + cs_103_OUTMUX_93 : X_BUF + port map ( + I => cs_103_OBUF, + O => cs_103_OUTMUX + ); + cs_111_OBUF_94 : X_TRI + port map ( + I => cs_111_OUTMUX, + CTL => cs_111_ENABLE, + O => cs(111) + ); + cs_111_ENABLEINV : X_INV + port map ( + I => cs_111_TORGTS, + O => cs_111_ENABLE + ); + cs_111_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_111_TORGTS + ); + cs_111_OUTMUX_95 : X_BUF + port map ( + I => cs_111_OBUF, + O => cs_111_OUTMUX + ); + cs_104_OBUF_96 : X_TRI + port map ( + I => cs_104_OUTMUX, + CTL => cs_104_ENABLE, + O => cs(104) + ); + cs_104_ENABLEINV : X_INV + port map ( + I => cs_104_TORGTS, + O => cs_104_ENABLE + ); + cs_104_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_104_TORGTS + ); + cs_104_OUTMUX_97 : X_BUF + port map ( + I => cs_104_OBUF, + O => cs_104_OUTMUX + ); + cs_112_OBUF_98 : X_TRI + port map ( + I => cs_112_OUTMUX, + CTL => cs_112_ENABLE, + O => cs(112) + ); + cs_112_ENABLEINV : X_INV + port map ( + I => cs_112_TORGTS, + O => cs_112_ENABLE + ); + cs_112_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_112_TORGTS + ); + cs_112_OUTMUX_99 : X_BUF + port map ( + I => cs_112_OBUF, + O => cs_112_OUTMUX + ); + cs_120_OBUF_100 : X_TRI + port map ( + I => cs_120_OUTMUX, + CTL => cs_120_ENABLE, + O => cs(120) + ); + cs_120_ENABLEINV : X_INV + port map ( + I => cs_120_TORGTS, + O => cs_120_ENABLE + ); + cs_120_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_120_TORGTS + ); + cs_120_OUTMUX_101 : X_BUF + port map ( + I => cs_120_OBUF, + O => cs_120_OUTMUX + ); + cs_200_OBUF_102 : X_TRI + port map ( + I => cs_200_OUTMUX, + CTL => cs_200_ENABLE, + O => cs(200) + ); + cs_200_ENABLEINV : X_INV + port map ( + I => cs_200_TORGTS, + O => cs_200_ENABLE + ); + cs_200_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_200_TORGTS + ); + cs_200_OUTMUX_103 : X_BUF + port map ( + I => cs_200_OBUF, + O => cs_200_OUTMUX + ); + cs_105_OBUF_104 : X_TRI + port map ( + I => cs_105_OUTMUX, + CTL => cs_105_ENABLE, + O => cs(105) + ); + cs_105_ENABLEINV : X_INV + port map ( + I => cs_105_TORGTS, + O => cs_105_ENABLE + ); + cs_105_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_105_TORGTS + ); + cs_105_OUTMUX_105 : X_BUF + port map ( + I => cs_105_OBUF, + O => cs_105_OUTMUX + ); + cs_113_OBUF_106 : X_TRI + port map ( + I => cs_113_OUTMUX, + CTL => cs_113_ENABLE, + O => cs(113) + ); + cs_113_ENABLEINV : X_INV + port map ( + I => cs_113_TORGTS, + O => cs_113_ENABLE + ); + cs_113_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_113_TORGTS + ); + cs_113_OUTMUX_107 : X_BUF + port map ( + I => cs_113_OBUF, + O => cs_113_OUTMUX + ); + cs_121_OBUF_108 : X_TRI + port map ( + I => cs_121_OUTMUX, + CTL => cs_121_ENABLE, + O => cs(121) + ); + cs_121_ENABLEINV : X_INV + port map ( + I => cs_121_TORGTS, + O => cs_121_ENABLE + ); + cs_121_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_121_TORGTS + ); + cs_121_OUTMUX_109 : X_BUF + port map ( + I => cs_121_OBUF, + O => cs_121_OUTMUX + ); + cs_201_OBUF_110 : X_TRI + port map ( + I => cs_201_OUTMUX, + CTL => cs_201_ENABLE, + O => cs(201) + ); + cs_201_ENABLEINV : X_INV + port map ( + I => cs_201_TORGTS, + O => cs_201_ENABLE + ); + cs_201_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_201_TORGTS + ); + cs_201_OUTMUX_111 : X_BUF + port map ( + I => cs_201_OBUF, + O => cs_201_OUTMUX + ); + cs_106_OBUF_112 : X_TRI + port map ( + I => cs_106_OUTMUX, + CTL => cs_106_ENABLE, + O => cs(106) + ); + cs_106_ENABLEINV : X_INV + port map ( + I => cs_106_TORGTS, + O => cs_106_ENABLE + ); + cs_106_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_106_TORGTS + ); + cs_106_OUTMUX_113 : X_BUF + port map ( + I => cs_106_OBUF, + O => cs_106_OUTMUX + ); + cs_114_OBUF_114 : X_TRI + port map ( + I => cs_114_OUTMUX, + CTL => cs_114_ENABLE, + O => cs(114) + ); + cs_114_ENABLEINV : X_INV + port map ( + I => cs_114_TORGTS, + O => cs_114_ENABLE + ); + cs_114_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_114_TORGTS + ); + cs_114_OUTMUX_115 : X_BUF + port map ( + I => cs_114_OBUF, + O => cs_114_OUTMUX + ); + cs_122_OBUF_116 : X_TRI + port map ( + I => cs_122_OUTMUX, + CTL => cs_122_ENABLE, + O => cs(122) + ); + cs_122_ENABLEINV : X_INV + port map ( + I => cs_122_TORGTS, + O => cs_122_ENABLE + ); + cs_122_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_122_TORGTS + ); + cs_122_OUTMUX_117 : X_BUF + port map ( + I => cs_122_OBUF, + O => cs_122_OUTMUX + ); + cs_130_OBUF_118 : X_TRI + port map ( + I => cs_130_OUTMUX, + CTL => cs_130_ENABLE, + O => cs(130) + ); + cs_130_ENABLEINV : X_INV + port map ( + I => cs_130_TORGTS, + O => cs_130_ENABLE + ); + cs_130_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_130_TORGTS + ); + cs_130_OUTMUX_119 : X_BUF + port map ( + I => cs_130_OBUF, + O => cs_130_OUTMUX + ); + cs_202_OBUF_120 : X_TRI + port map ( + I => cs_202_OUTMUX, + CTL => cs_202_ENABLE, + O => cs(202) + ); + cs_202_ENABLEINV : X_INV + port map ( + I => cs_202_TORGTS, + O => cs_202_ENABLE + ); + cs_202_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_202_TORGTS + ); + cs_202_OUTMUX_121 : X_BUF + port map ( + I => cs_202_OBUF, + O => cs_202_OUTMUX + ); + cs_210_OBUF_122 : X_TRI + port map ( + I => cs_210_OUTMUX, + CTL => cs_210_ENABLE, + O => cs(210) + ); + cs_210_ENABLEINV : X_INV + port map ( + I => cs_210_TORGTS, + O => cs_210_ENABLE + ); + cs_210_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_210_TORGTS + ); + cs_210_OUTMUX_123 : X_BUF + port map ( + I => cs_210_OBUF, + O => cs_210_OUTMUX + ); + cs_107_OBUF_124 : X_TRI + port map ( + I => cs_107_OUTMUX, + CTL => cs_107_ENABLE, + O => cs(107) + ); + cs_107_ENABLEINV : X_INV + port map ( + I => cs_107_TORGTS, + O => cs_107_ENABLE + ); + cs_107_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_107_TORGTS + ); + cs_107_OUTMUX_125 : X_BUF + port map ( + I => cs_107_OBUF, + O => cs_107_OUTMUX + ); + cs_115_OBUF_126 : X_TRI + port map ( + I => cs_115_OUTMUX, + CTL => cs_115_ENABLE, + O => cs(115) + ); + cs_115_ENABLEINV : X_INV + port map ( + I => cs_115_TORGTS, + O => cs_115_ENABLE + ); + cs_115_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_115_TORGTS + ); + cs_115_OUTMUX_127 : X_BUF + port map ( + I => cs_115_OBUF, + O => cs_115_OUTMUX + ); + cs_123_OBUF_128 : X_TRI + port map ( + I => cs_123_OUTMUX, + CTL => cs_123_ENABLE, + O => cs(123) + ); + cs_123_ENABLEINV : X_INV + port map ( + I => cs_123_TORGTS, + O => cs_123_ENABLE + ); + cs_123_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_123_TORGTS + ); + cs_123_OUTMUX_129 : X_BUF + port map ( + I => cs_123_OBUF, + O => cs_123_OUTMUX + ); + cs_131_OBUF_130 : X_TRI + port map ( + I => cs_131_OUTMUX, + CTL => cs_131_ENABLE, + O => cs(131) + ); + cs_131_ENABLEINV : X_INV + port map ( + I => cs_131_TORGTS, + O => cs_131_ENABLE + ); + cs_131_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_131_TORGTS + ); + cs_131_OUTMUX_131 : X_BUF + port map ( + I => cs_131_OBUF, + O => cs_131_OUTMUX + ); + cs_203_OBUF_132 : X_TRI + port map ( + I => cs_203_OUTMUX, + CTL => cs_203_ENABLE, + O => cs(203) + ); + cs_203_ENABLEINV : X_INV + port map ( + I => cs_203_TORGTS, + O => cs_203_ENABLE + ); + cs_203_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_203_TORGTS + ); + cs_203_OUTMUX_133 : X_BUF + port map ( + I => cs_203_OBUF, + O => cs_203_OUTMUX + ); + cs_211_OBUF_134 : X_TRI + port map ( + I => cs_211_OUTMUX, + CTL => cs_211_ENABLE, + O => cs(211) + ); + cs_211_ENABLEINV : X_INV + port map ( + I => cs_211_TORGTS, + O => cs_211_ENABLE + ); + cs_211_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_211_TORGTS + ); + cs_211_OUTMUX_135 : X_BUF + port map ( + I => cs_211_OBUF, + O => cs_211_OUTMUX + ); + cs_108_OBUF_136 : X_TRI + port map ( + I => cs_108_OUTMUX, + CTL => cs_108_ENABLE, + O => cs(108) + ); + cs_108_ENABLEINV : X_INV + port map ( + I => cs_108_TORGTS, + O => cs_108_ENABLE + ); + cs_108_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_108_TORGTS + ); + cs_108_OUTMUX_137 : X_BUF + port map ( + I => cs_108_OBUF, + O => cs_108_OUTMUX + ); + cs_116_OBUF_138 : X_TRI + port map ( + I => cs_116_OUTMUX, + CTL => cs_116_ENABLE, + O => cs(116) + ); + cs_116_ENABLEINV : X_INV + port map ( + I => cs_116_TORGTS, + O => cs_116_ENABLE + ); + cs_116_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_116_TORGTS + ); + cs_116_OUTMUX_139 : X_BUF + port map ( + I => cs_116_OBUF, + O => cs_116_OUTMUX + ); + cs_124_OBUF_140 : X_TRI + port map ( + I => cs_124_OUTMUX, + CTL => cs_124_ENABLE, + O => cs(124) + ); + cs_124_ENABLEINV : X_INV + port map ( + I => cs_124_TORGTS, + O => cs_124_ENABLE + ); + cs_124_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_124_TORGTS + ); + cs_124_OUTMUX_141 : X_BUF + port map ( + I => cs_124_OBUF, + O => cs_124_OUTMUX + ); + cs_132_OBUF_142 : X_TRI + port map ( + I => cs_132_OUTMUX, + CTL => cs_132_ENABLE, + O => cs(132) + ); + cs_132_ENABLEINV : X_INV + port map ( + I => cs_132_TORGTS, + O => cs_132_ENABLE + ); + cs_132_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_132_TORGTS + ); + cs_132_OUTMUX_143 : X_BUF + port map ( + I => cs_132_OBUF, + O => cs_132_OUTMUX + ); + cs_140_OBUF_144 : X_TRI + port map ( + I => cs_140_OUTMUX, + CTL => cs_140_ENABLE, + O => cs(140) + ); + cs_140_ENABLEINV : X_INV + port map ( + I => cs_140_TORGTS, + O => cs_140_ENABLE + ); + cs_140_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_140_TORGTS + ); + cs_140_OUTMUX_145 : X_BUF + port map ( + I => cs_140_OBUF, + O => cs_140_OUTMUX + ); + cs_204_OBUF_146 : X_TRI + port map ( + I => cs_204_OUTMUX, + CTL => cs_204_ENABLE, + O => cs(204) + ); + cs_204_ENABLEINV : X_INV + port map ( + I => cs_204_TORGTS, + O => cs_204_ENABLE + ); + cs_204_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_204_TORGTS + ); + cs_204_OUTMUX_147 : X_BUF + port map ( + I => cs_204_OBUF, + O => cs_204_OUTMUX + ); + cs_212_OBUF_148 : X_TRI + port map ( + I => cs_212_OUTMUX, + CTL => cs_212_ENABLE, + O => cs(212) + ); + cs_212_ENABLEINV : X_INV + port map ( + I => cs_212_TORGTS, + O => cs_212_ENABLE + ); + cs_212_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_212_TORGTS + ); + cs_212_OUTMUX_149 : X_BUF + port map ( + I => cs_212_OBUF, + O => cs_212_OUTMUX + ); + cs_220_OBUF_150 : X_TRI + port map ( + I => cs_220_OUTMUX, + CTL => cs_220_ENABLE, + O => cs(220) + ); + cs_220_ENABLEINV : X_INV + port map ( + I => cs_220_TORGTS, + O => cs_220_ENABLE + ); + cs_220_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_220_TORGTS + ); + cs_220_OUTMUX_151 : X_BUF + port map ( + I => cs_220_OBUF, + O => cs_220_OUTMUX + ); + cs_109_OBUF_152 : X_TRI + port map ( + I => cs_109_OUTMUX, + CTL => cs_109_ENABLE, + O => cs(109) + ); + cs_109_ENABLEINV : X_INV + port map ( + I => cs_109_TORGTS, + O => cs_109_ENABLE + ); + cs_109_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_109_TORGTS + ); + cs_109_OUTMUX_153 : X_BUF + port map ( + I => cs_109_OBUF, + O => cs_109_OUTMUX + ); + cs_117_OBUF_154 : X_TRI + port map ( + I => cs_117_OUTMUX, + CTL => cs_117_ENABLE, + O => cs(117) + ); + cs_117_ENABLEINV : X_INV + port map ( + I => cs_117_TORGTS, + O => cs_117_ENABLE + ); + cs_117_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_117_TORGTS + ); + cs_117_OUTMUX_155 : X_BUF + port map ( + I => cs_117_OBUF, + O => cs_117_OUTMUX + ); + cs_125_OBUF_156 : X_TRI + port map ( + I => cs_125_OUTMUX, + CTL => cs_125_ENABLE, + O => cs(125) + ); + cs_125_ENABLEINV : X_INV + port map ( + I => cs_125_TORGTS, + O => cs_125_ENABLE + ); + cs_125_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_125_TORGTS + ); + cs_125_OUTMUX_157 : X_BUF + port map ( + I => cs_125_OBUF, + O => cs_125_OUTMUX + ); + cs_133_OBUF_158 : X_TRI + port map ( + I => cs_133_OUTMUX, + CTL => cs_133_ENABLE, + O => cs(133) + ); + cs_133_ENABLEINV : X_INV + port map ( + I => cs_133_TORGTS, + O => cs_133_ENABLE + ); + cs_133_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_133_TORGTS + ); + cs_133_OUTMUX_159 : X_BUF + port map ( + I => cs_133_OBUF, + O => cs_133_OUTMUX + ); + cs_141_OBUF_160 : X_TRI + port map ( + I => cs_141_OUTMUX, + CTL => cs_141_ENABLE, + O => cs(141) + ); + cs_141_ENABLEINV : X_INV + port map ( + I => cs_141_TORGTS, + O => cs_141_ENABLE + ); + cs_141_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_141_TORGTS + ); + cs_141_OUTMUX_161 : X_BUF + port map ( + I => cs_141_OBUF, + O => cs_141_OUTMUX + ); + cs_205_OBUF_162 : X_TRI + port map ( + I => cs_205_OUTMUX, + CTL => cs_205_ENABLE, + O => cs(205) + ); + cs_205_ENABLEINV : X_INV + port map ( + I => cs_205_TORGTS, + O => cs_205_ENABLE + ); + cs_205_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_205_TORGTS + ); + cs_205_OUTMUX_163 : X_BUF + port map ( + I => cs_205_OBUF, + O => cs_205_OUTMUX + ); + cs_213_OBUF_164 : X_TRI + port map ( + I => cs_213_OUTMUX, + CTL => cs_213_ENABLE, + O => cs(213) + ); + cs_213_ENABLEINV : X_INV + port map ( + I => cs_213_TORGTS, + O => cs_213_ENABLE + ); + cs_213_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_213_TORGTS + ); + cs_213_OUTMUX_165 : X_BUF + port map ( + I => cs_213_OBUF, + O => cs_213_OUTMUX + ); + cs_221_OBUF_166 : X_TRI + port map ( + I => cs_221_OUTMUX, + CTL => cs_221_ENABLE, + O => cs(221) + ); + cs_221_ENABLEINV : X_INV + port map ( + I => cs_221_TORGTS, + O => cs_221_ENABLE + ); + cs_221_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_221_TORGTS + ); + cs_221_OUTMUX_167 : X_BUF + port map ( + I => cs_221_OBUF, + O => cs_221_OUTMUX + ); + cs_118_OBUF_168 : X_TRI + port map ( + I => cs_118_OUTMUX, + CTL => cs_118_ENABLE, + O => cs(118) + ); + cs_118_ENABLEINV : X_INV + port map ( + I => cs_118_TORGTS, + O => cs_118_ENABLE + ); + cs_118_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_118_TORGTS + ); + cs_118_OUTMUX_169 : X_BUF + port map ( + I => cs_118_OBUF, + O => cs_118_OUTMUX + ); + cs_126_OBUF_170 : X_TRI + port map ( + I => cs_126_OUTMUX, + CTL => cs_126_ENABLE, + O => cs(126) + ); + cs_126_ENABLEINV : X_INV + port map ( + I => cs_126_TORGTS, + O => cs_126_ENABLE + ); + cs_126_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_126_TORGTS + ); + cs_126_OUTMUX_171 : X_BUF + port map ( + I => cs_126_OBUF, + O => cs_126_OUTMUX + ); + cs_134_OBUF_172 : X_TRI + port map ( + I => cs_134_OUTMUX, + CTL => cs_134_ENABLE, + O => cs(134) + ); + cs_134_ENABLEINV : X_INV + port map ( + I => cs_134_TORGTS, + O => cs_134_ENABLE + ); + cs_134_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_134_TORGTS + ); + cs_134_OUTMUX_173 : X_BUF + port map ( + I => cs_134_OBUF, + O => cs_134_OUTMUX + ); + cs_142_OBUF_174 : X_TRI + port map ( + I => cs_142_OUTMUX, + CTL => cs_142_ENABLE, + O => cs(142) + ); + cs_142_ENABLEINV : X_INV + port map ( + I => cs_142_TORGTS, + O => cs_142_ENABLE + ); + cs_142_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_142_TORGTS + ); + cs_142_OUTMUX_175 : X_BUF + port map ( + I => cs_142_OBUF, + O => cs_142_OUTMUX + ); + cs_150_OBUF_176 : X_TRI + port map ( + I => cs_150_OUTMUX, + CTL => cs_150_ENABLE, + O => cs(150) + ); + cs_150_ENABLEINV : X_INV + port map ( + I => cs_150_TORGTS, + O => cs_150_ENABLE + ); + cs_150_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_150_TORGTS + ); + cs_150_OUTMUX_177 : X_BUF + port map ( + I => cs_150_OBUF, + O => cs_150_OUTMUX + ); + cs_206_OBUF_178 : X_TRI + port map ( + I => cs_206_OUTMUX, + CTL => cs_206_ENABLE, + O => cs(206) + ); + cs_206_ENABLEINV : X_INV + port map ( + I => cs_206_TORGTS, + O => cs_206_ENABLE + ); + cs_206_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_206_TORGTS + ); + cs_206_OUTMUX_179 : X_BUF + port map ( + I => cs_206_OBUF, + O => cs_206_OUTMUX + ); + cs_214_OBUF_180 : X_TRI + port map ( + I => cs_214_OUTMUX, + CTL => cs_214_ENABLE, + O => cs(214) + ); + cs_214_ENABLEINV : X_INV + port map ( + I => cs_214_TORGTS, + O => cs_214_ENABLE + ); + cs_214_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_214_TORGTS + ); + cs_214_OUTMUX_181 : X_BUF + port map ( + I => cs_214_OBUF, + O => cs_214_OUTMUX + ); + cs_222_OBUF_182 : X_TRI + port map ( + I => cs_222_OUTMUX, + CTL => cs_222_ENABLE, + O => cs(222) + ); + cs_222_ENABLEINV : X_INV + port map ( + I => cs_222_TORGTS, + O => cs_222_ENABLE + ); + cs_222_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_222_TORGTS + ); + cs_222_OUTMUX_183 : X_BUF + port map ( + I => cs_222_OBUF, + O => cs_222_OUTMUX + ); + cs_230_OBUF_184 : X_TRI + port map ( + I => cs_230_OUTMUX, + CTL => cs_230_ENABLE, + O => cs(230) + ); + cs_230_ENABLEINV : X_INV + port map ( + I => cs_230_TORGTS, + O => cs_230_ENABLE + ); + cs_230_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_230_TORGTS + ); + cs_230_OUTMUX_185 : X_BUF + port map ( + I => cs_230_OBUF, + O => cs_230_OUTMUX + ); + cs_119_OBUF_186 : X_TRI + port map ( + I => cs_119_OUTMUX, + CTL => cs_119_ENABLE, + O => cs(119) + ); + cs_119_ENABLEINV : X_INV + port map ( + I => cs_119_TORGTS, + O => cs_119_ENABLE + ); + cs_119_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_119_TORGTS + ); + cs_119_OUTMUX_187 : X_BUF + port map ( + I => cs_119_OBUF, + O => cs_119_OUTMUX + ); + cs_127_OBUF_188 : X_TRI + port map ( + I => cs_127_OUTMUX, + CTL => cs_127_ENABLE, + O => cs(127) + ); + cs_127_ENABLEINV : X_INV + port map ( + I => cs_127_TORGTS, + O => cs_127_ENABLE + ); + cs_127_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_127_TORGTS + ); + cs_127_OUTMUX_189 : X_BUF + port map ( + I => cs_127_OBUF, + O => cs_127_OUTMUX + ); + cs_135_OBUF_190 : X_TRI + port map ( + I => cs_135_OUTMUX, + CTL => cs_135_ENABLE, + O => cs(135) + ); + cs_135_ENABLEINV : X_INV + port map ( + I => cs_135_TORGTS, + O => cs_135_ENABLE + ); + cs_135_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_135_TORGTS + ); + cs_135_OUTMUX_191 : X_BUF + port map ( + I => cs_135_OBUF, + O => cs_135_OUTMUX + ); + cs_143_OBUF_192 : X_TRI + port map ( + I => cs_143_OUTMUX, + CTL => cs_143_ENABLE, + O => cs(143) + ); + cs_143_ENABLEINV : X_INV + port map ( + I => cs_143_TORGTS, + O => cs_143_ENABLE + ); + cs_143_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_143_TORGTS + ); + cs_143_OUTMUX_193 : X_BUF + port map ( + I => cs_143_OBUF, + O => cs_143_OUTMUX + ); + cs_151_OBUF_194 : X_TRI + port map ( + I => cs_151_OUTMUX, + CTL => cs_151_ENABLE, + O => cs(151) + ); + cs_151_ENABLEINV : X_INV + port map ( + I => cs_151_TORGTS, + O => cs_151_ENABLE + ); + cs_151_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_151_TORGTS + ); + cs_151_OUTMUX_195 : X_BUF + port map ( + I => cs_151_OBUF, + O => cs_151_OUTMUX + ); + cs_207_OBUF_196 : X_TRI + port map ( + I => cs_207_OUTMUX, + CTL => cs_207_ENABLE, + O => cs(207) + ); + cs_207_ENABLEINV : X_INV + port map ( + I => cs_207_TORGTS, + O => cs_207_ENABLE + ); + cs_207_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_207_TORGTS + ); + cs_207_OUTMUX_197 : X_BUF + port map ( + I => cs_207_OBUF, + O => cs_207_OUTMUX + ); + cs_215_OBUF_198 : X_TRI + port map ( + I => cs_215_OUTMUX, + CTL => cs_215_ENABLE, + O => cs(215) + ); + cs_215_ENABLEINV : X_INV + port map ( + I => cs_215_TORGTS, + O => cs_215_ENABLE + ); + cs_215_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_215_TORGTS + ); + cs_215_OUTMUX_199 : X_BUF + port map ( + I => cs_215_OBUF, + O => cs_215_OUTMUX + ); + cs_223_OBUF_200 : X_TRI + port map ( + I => cs_223_OUTMUX, + CTL => cs_223_ENABLE, + O => cs(223) + ); + cs_223_ENABLEINV : X_INV + port map ( + I => cs_223_TORGTS, + O => cs_223_ENABLE + ); + cs_223_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_223_TORGTS + ); + cs_223_OUTMUX_201 : X_BUF + port map ( + I => cs_223_OBUF, + O => cs_223_OUTMUX + ); + cs_231_OBUF_202 : X_TRI + port map ( + I => cs_231_OUTMUX, + CTL => cs_231_ENABLE, + O => cs(231) + ); + cs_231_ENABLEINV : X_INV + port map ( + I => cs_231_TORGTS, + O => cs_231_ENABLE + ); + cs_231_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_231_TORGTS + ); + cs_231_OUTMUX_203 : X_BUF + port map ( + I => cs_231_OBUF, + O => cs_231_OUTMUX + ); + cs_128_OBUF_204 : X_TRI + port map ( + I => cs_128_OUTMUX, + CTL => cs_128_ENABLE, + O => cs(128) + ); + cs_128_ENABLEINV : X_INV + port map ( + I => cs_128_TORGTS, + O => cs_128_ENABLE + ); + cs_128_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_128_TORGTS + ); + cs_128_OUTMUX_205 : X_BUF + port map ( + I => cs_128_OBUF, + O => cs_128_OUTMUX + ); + cs_136_OBUF_206 : X_TRI + port map ( + I => cs_136_OUTMUX, + CTL => cs_136_ENABLE, + O => cs(136) + ); + cs_136_ENABLEINV : X_INV + port map ( + I => cs_136_TORGTS, + O => cs_136_ENABLE + ); + cs_136_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_136_TORGTS + ); + cs_136_OUTMUX_207 : X_BUF + port map ( + I => cs_136_OBUF, + O => cs_136_OUTMUX + ); + cs_144_OBUF_208 : X_TRI + port map ( + I => cs_144_OUTMUX, + CTL => cs_144_ENABLE, + O => cs(144) + ); + cs_144_ENABLEINV : X_INV + port map ( + I => cs_144_TORGTS, + O => cs_144_ENABLE + ); + cs_144_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_144_TORGTS + ); + cs_144_OUTMUX_209 : X_BUF + port map ( + I => cs_144_OBUF, + O => cs_144_OUTMUX + ); + cs_152_OBUF_210 : X_TRI + port map ( + I => cs_152_OUTMUX, + CTL => cs_152_ENABLE, + O => cs(152) + ); + cs_152_ENABLEINV : X_INV + port map ( + I => cs_152_TORGTS, + O => cs_152_ENABLE + ); + cs_152_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_152_TORGTS + ); + cs_152_OUTMUX_211 : X_BUF + port map ( + I => cs_152_OBUF, + O => cs_152_OUTMUX + ); + cs_160_OBUF_212 : X_TRI + port map ( + I => cs_160_OUTMUX, + CTL => cs_160_ENABLE, + O => cs(160) + ); + cs_160_ENABLEINV : X_INV + port map ( + I => cs_160_TORGTS, + O => cs_160_ENABLE + ); + cs_160_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_160_TORGTS + ); + cs_160_OUTMUX_213 : X_BUF + port map ( + I => cs_160_OBUF, + O => cs_160_OUTMUX + ); + cs_208_OBUF_214 : X_TRI + port map ( + I => cs_208_OUTMUX, + CTL => cs_208_ENABLE, + O => cs(208) + ); + cs_208_ENABLEINV : X_INV + port map ( + I => cs_208_TORGTS, + O => cs_208_ENABLE + ); + cs_208_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_208_TORGTS + ); + cs_208_OUTMUX_215 : X_BUF + port map ( + I => cs_208_OBUF, + O => cs_208_OUTMUX + ); + cs_216_OBUF_216 : X_TRI + port map ( + I => cs_216_OUTMUX, + CTL => cs_216_ENABLE, + O => cs(216) + ); + cs_216_ENABLEINV : X_INV + port map ( + I => cs_216_TORGTS, + O => cs_216_ENABLE + ); + cs_216_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_216_TORGTS + ); + cs_216_OUTMUX_217 : X_BUF + port map ( + I => cs_216_OBUF, + O => cs_216_OUTMUX + ); + cs_224_OBUF_218 : X_TRI + port map ( + I => cs_224_OUTMUX, + CTL => cs_224_ENABLE, + O => cs(224) + ); + cs_224_ENABLEINV : X_INV + port map ( + I => cs_224_TORGTS, + O => cs_224_ENABLE + ); + cs_224_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_224_TORGTS + ); + cs_224_OUTMUX_219 : X_BUF + port map ( + I => cs_224_OBUF, + O => cs_224_OUTMUX + ); + cs_232_OBUF_220 : X_TRI + port map ( + I => cs_232_OUTMUX, + CTL => cs_232_ENABLE, + O => cs(232) + ); + cs_232_ENABLEINV : X_INV + port map ( + I => cs_232_TORGTS, + O => cs_232_ENABLE + ); + cs_232_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_232_TORGTS + ); + cs_232_OUTMUX_221 : X_BUF + port map ( + I => cs_232_OBUF, + O => cs_232_OUTMUX + ); + cs_240_OBUF_222 : X_TRI + port map ( + I => cs_240_OUTMUX, + CTL => cs_240_ENABLE, + O => cs(240) + ); + cs_240_ENABLEINV : X_INV + port map ( + I => cs_240_TORGTS, + O => cs_240_ENABLE + ); + cs_240_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_240_TORGTS + ); + cs_240_OUTMUX_223 : X_BUF + port map ( + I => cs_240_OBUF, + O => cs_240_OUTMUX + ); + cs_129_OBUF_224 : X_TRI + port map ( + I => cs_129_OUTMUX, + CTL => cs_129_ENABLE, + O => cs(129) + ); + cs_129_ENABLEINV : X_INV + port map ( + I => cs_129_TORGTS, + O => cs_129_ENABLE + ); + cs_129_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_129_TORGTS + ); + cs_129_OUTMUX_225 : X_BUF + port map ( + I => cs_129_OBUF, + O => cs_129_OUTMUX + ); + cs_137_OBUF_226 : X_TRI + port map ( + I => cs_137_OUTMUX, + CTL => cs_137_ENABLE, + O => cs(137) + ); + cs_137_ENABLEINV : X_INV + port map ( + I => cs_137_TORGTS, + O => cs_137_ENABLE + ); + cs_137_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_137_TORGTS + ); + cs_137_OUTMUX_227 : X_BUF + port map ( + I => cs_137_OBUF, + O => cs_137_OUTMUX + ); + cs_145_OBUF_228 : X_TRI + port map ( + I => cs_145_OUTMUX, + CTL => cs_145_ENABLE, + O => cs(145) + ); + cs_145_ENABLEINV : X_INV + port map ( + I => cs_145_TORGTS, + O => cs_145_ENABLE + ); + cs_145_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_145_TORGTS + ); + cs_145_OUTMUX_229 : X_BUF + port map ( + I => cs_145_OBUF, + O => cs_145_OUTMUX + ); + cs_153_OBUF_230 : X_TRI + port map ( + I => cs_153_OUTMUX, + CTL => cs_153_ENABLE, + O => cs(153) + ); + cs_153_ENABLEINV : X_INV + port map ( + I => cs_153_TORGTS, + O => cs_153_ENABLE + ); + cs_153_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_153_TORGTS + ); + cs_153_OUTMUX_231 : X_BUF + port map ( + I => cs_153_OBUF, + O => cs_153_OUTMUX + ); + cs_161_OBUF_232 : X_TRI + port map ( + I => cs_161_OUTMUX, + CTL => cs_161_ENABLE, + O => cs(161) + ); + cs_161_ENABLEINV : X_INV + port map ( + I => cs_161_TORGTS, + O => cs_161_ENABLE + ); + cs_161_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_161_TORGTS + ); + cs_161_OUTMUX_233 : X_BUF + port map ( + I => cs_161_OBUF, + O => cs_161_OUTMUX + ); + cs_209_OBUF_234 : X_TRI + port map ( + I => cs_209_OUTMUX, + CTL => cs_209_ENABLE, + O => cs(209) + ); + cs_209_ENABLEINV : X_INV + port map ( + I => cs_209_TORGTS, + O => cs_209_ENABLE + ); + cs_209_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_209_TORGTS + ); + cs_209_OUTMUX_235 : X_BUF + port map ( + I => cs_209_OBUF, + O => cs_209_OUTMUX + ); + cs_217_OBUF_236 : X_TRI + port map ( + I => cs_217_OUTMUX, + CTL => cs_217_ENABLE, + O => cs(217) + ); + cs_217_ENABLEINV : X_INV + port map ( + I => cs_217_TORGTS, + O => cs_217_ENABLE + ); + cs_217_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_217_TORGTS + ); + cs_217_OUTMUX_237 : X_BUF + port map ( + I => cs_217_OBUF, + O => cs_217_OUTMUX + ); + cs_225_OBUF_238 : X_TRI + port map ( + I => cs_225_OUTMUX, + CTL => cs_225_ENABLE, + O => cs(225) + ); + cs_225_ENABLEINV : X_INV + port map ( + I => cs_225_TORGTS, + O => cs_225_ENABLE + ); + cs_225_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_225_TORGTS + ); + cs_225_OUTMUX_239 : X_BUF + port map ( + I => cs_225_OBUF, + O => cs_225_OUTMUX + ); + cs_233_OBUF_240 : X_TRI + port map ( + I => cs_233_OUTMUX, + CTL => cs_233_ENABLE, + O => cs(233) + ); + cs_233_ENABLEINV : X_INV + port map ( + I => cs_233_TORGTS, + O => cs_233_ENABLE + ); + cs_233_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_233_TORGTS + ); + cs_233_OUTMUX_241 : X_BUF + port map ( + I => cs_233_OBUF, + O => cs_233_OUTMUX + ); + cs_241_OBUF_242 : X_TRI + port map ( + I => cs_241_OUTMUX, + CTL => cs_241_ENABLE, + O => cs(241) + ); + cs_241_ENABLEINV : X_INV + port map ( + I => cs_241_TORGTS, + O => cs_241_ENABLE + ); + cs_241_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_241_TORGTS + ); + cs_241_OUTMUX_243 : X_BUF + port map ( + I => cs_241_OBUF, + O => cs_241_OUTMUX + ); + cs_138_OBUF_244 : X_TRI + port map ( + I => cs_138_OUTMUX, + CTL => cs_138_ENABLE, + O => cs(138) + ); + cs_138_ENABLEINV : X_INV + port map ( + I => cs_138_TORGTS, + O => cs_138_ENABLE + ); + cs_138_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_138_TORGTS + ); + cs_138_OUTMUX_245 : X_BUF + port map ( + I => cs_138_OBUF, + O => cs_138_OUTMUX + ); + cs_146_OBUF_246 : X_TRI + port map ( + I => cs_146_OUTMUX, + CTL => cs_146_ENABLE, + O => cs(146) + ); + cs_146_ENABLEINV : X_INV + port map ( + I => cs_146_TORGTS, + O => cs_146_ENABLE + ); + cs_146_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_146_TORGTS + ); + cs_146_OUTMUX_247 : X_BUF + port map ( + I => cs_146_OBUF, + O => cs_146_OUTMUX + ); + cs_154_OBUF_248 : X_TRI + port map ( + I => cs_154_OUTMUX, + CTL => cs_154_ENABLE, + O => cs(154) + ); + cs_154_ENABLEINV : X_INV + port map ( + I => cs_154_TORGTS, + O => cs_154_ENABLE + ); + cs_154_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_154_TORGTS + ); + cs_154_OUTMUX_249 : X_BUF + port map ( + I => cs_154_OBUF, + O => cs_154_OUTMUX + ); + cs_162_OBUF_250 : X_TRI + port map ( + I => cs_162_OUTMUX, + CTL => cs_162_ENABLE, + O => cs(162) + ); + cs_162_ENABLEINV : X_INV + port map ( + I => cs_162_TORGTS, + O => cs_162_ENABLE + ); + cs_162_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_162_TORGTS + ); + cs_162_OUTMUX_251 : X_BUF + port map ( + I => cs_162_OBUF, + O => cs_162_OUTMUX + ); + cs_170_OBUF_252 : X_TRI + port map ( + I => cs_170_OUTMUX, + CTL => cs_170_ENABLE, + O => cs(170) + ); + cs_170_ENABLEINV : X_INV + port map ( + I => cs_170_TORGTS, + O => cs_170_ENABLE + ); + cs_170_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_170_TORGTS + ); + cs_170_OUTMUX_253 : X_BUF + port map ( + I => cs_170_OBUF, + O => cs_170_OUTMUX + ); + cs_218_OBUF_254 : X_TRI + port map ( + I => cs_218_OUTMUX, + CTL => cs_218_ENABLE, + O => cs(218) + ); + cs_218_ENABLEINV : X_INV + port map ( + I => cs_218_TORGTS, + O => cs_218_ENABLE + ); + cs_218_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_218_TORGTS + ); + cs_218_OUTMUX_255 : X_BUF + port map ( + I => cs_218_OBUF, + O => cs_218_OUTMUX + ); + cs_226_OBUF_256 : X_TRI + port map ( + I => cs_226_OUTMUX, + CTL => cs_226_ENABLE, + O => cs(226) + ); + cs_226_ENABLEINV : X_INV + port map ( + I => cs_226_TORGTS, + O => cs_226_ENABLE + ); + cs_226_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_226_TORGTS + ); + cs_226_OUTMUX_257 : X_BUF + port map ( + I => cs_226_OBUF, + O => cs_226_OUTMUX + ); + cs_234_OBUF_258 : X_TRI + port map ( + I => cs_234_OUTMUX, + CTL => cs_234_ENABLE, + O => cs(234) + ); + cs_234_ENABLEINV : X_INV + port map ( + I => cs_234_TORGTS, + O => cs_234_ENABLE + ); + cs_234_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_234_TORGTS + ); + cs_234_OUTMUX_259 : X_BUF + port map ( + I => cs_234_OBUF, + O => cs_234_OUTMUX + ); + cs_242_OBUF_260 : X_TRI + port map ( + I => cs_242_OUTMUX, + CTL => cs_242_ENABLE, + O => cs(242) + ); + cs_242_ENABLEINV : X_INV + port map ( + I => cs_242_TORGTS, + O => cs_242_ENABLE + ); + cs_242_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_242_TORGTS + ); + cs_242_OUTMUX_261 : X_BUF + port map ( + I => cs_242_OBUF, + O => cs_242_OUTMUX + ); + cs_250_OBUF_262 : X_TRI + port map ( + I => cs_250_OUTMUX, + CTL => cs_250_ENABLE, + O => cs(250) + ); + cs_250_ENABLEINV : X_INV + port map ( + I => cs_250_TORGTS, + O => cs_250_ENABLE + ); + cs_250_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_250_TORGTS + ); + cs_250_OUTMUX_263 : X_BUF + port map ( + I => cs_250_OBUF, + O => cs_250_OUTMUX + ); + cs_139_OBUF_264 : X_TRI + port map ( + I => cs_139_OUTMUX, + CTL => cs_139_ENABLE, + O => cs(139) + ); + cs_139_ENABLEINV : X_INV + port map ( + I => cs_139_TORGTS, + O => cs_139_ENABLE + ); + cs_139_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_139_TORGTS + ); + cs_139_OUTMUX_265 : X_BUF + port map ( + I => cs_139_OBUF, + O => cs_139_OUTMUX + ); + cs_147_OBUF_266 : X_TRI + port map ( + I => cs_147_OUTMUX, + CTL => cs_147_ENABLE, + O => cs(147) + ); + cs_147_ENABLEINV : X_INV + port map ( + I => cs_147_TORGTS, + O => cs_147_ENABLE + ); + cs_147_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_147_TORGTS + ); + cs_147_OUTMUX_267 : X_BUF + port map ( + I => cs_147_OBUF, + O => cs_147_OUTMUX + ); + cs_155_OBUF_268 : X_TRI + port map ( + I => cs_155_OUTMUX, + CTL => cs_155_ENABLE, + O => cs(155) + ); + cs_155_ENABLEINV : X_INV + port map ( + I => cs_155_TORGTS, + O => cs_155_ENABLE + ); + cs_155_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_155_TORGTS + ); + cs_155_OUTMUX_269 : X_BUF + port map ( + I => cs_155_OBUF, + O => cs_155_OUTMUX + ); + cs_163_OBUF_270 : X_TRI + port map ( + I => cs_163_OUTMUX, + CTL => cs_163_ENABLE, + O => cs(163) + ); + cs_163_ENABLEINV : X_INV + port map ( + I => cs_163_TORGTS, + O => cs_163_ENABLE + ); + cs_163_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_163_TORGTS + ); + cs_163_OUTMUX_271 : X_BUF + port map ( + I => cs_163_OBUF, + O => cs_163_OUTMUX + ); + cs_171_OBUF_272 : X_TRI + port map ( + I => cs_171_OUTMUX, + CTL => cs_171_ENABLE, + O => cs(171) + ); + cs_171_ENABLEINV : X_INV + port map ( + I => cs_171_TORGTS, + O => cs_171_ENABLE + ); + cs_171_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_171_TORGTS + ); + cs_171_OUTMUX_273 : X_BUF + port map ( + I => cs_171_OBUF, + O => cs_171_OUTMUX + ); + cs_219_OBUF_274 : X_TRI + port map ( + I => cs_219_OUTMUX, + CTL => cs_219_ENABLE, + O => cs(219) + ); + cs_219_ENABLEINV : X_INV + port map ( + I => cs_219_TORGTS, + O => cs_219_ENABLE + ); + cs_219_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_219_TORGTS + ); + cs_219_OUTMUX_275 : X_BUF + port map ( + I => cs_219_OBUF, + O => cs_219_OUTMUX + ); + cs_227_OBUF_276 : X_TRI + port map ( + I => cs_227_OUTMUX, + CTL => cs_227_ENABLE, + O => cs(227) + ); + cs_227_ENABLEINV : X_INV + port map ( + I => cs_227_TORGTS, + O => cs_227_ENABLE + ); + cs_227_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_227_TORGTS + ); + cs_227_OUTMUX_277 : X_BUF + port map ( + I => cs_227_OBUF, + O => cs_227_OUTMUX + ); + cs_235_OBUF_278 : X_TRI + port map ( + I => cs_235_OUTMUX, + CTL => cs_235_ENABLE, + O => cs(235) + ); + cs_235_ENABLEINV : X_INV + port map ( + I => cs_235_TORGTS, + O => cs_235_ENABLE + ); + cs_235_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_235_TORGTS + ); + cs_235_OUTMUX_279 : X_BUF + port map ( + I => cs_235_OBUF, + O => cs_235_OUTMUX + ); + cs_243_OBUF_280 : X_TRI + port map ( + I => cs_243_OUTMUX, + CTL => cs_243_ENABLE, + O => cs(243) + ); + cs_243_ENABLEINV : X_INV + port map ( + I => cs_243_TORGTS, + O => cs_243_ENABLE + ); + cs_243_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_243_TORGTS + ); + cs_243_OUTMUX_281 : X_BUF + port map ( + I => cs_243_OBUF, + O => cs_243_OUTMUX + ); + cs_251_OBUF_282 : X_TRI + port map ( + I => cs_251_OUTMUX, + CTL => cs_251_ENABLE, + O => cs(251) + ); + cs_251_ENABLEINV : X_INV + port map ( + I => cs_251_TORGTS, + O => cs_251_ENABLE + ); + cs_251_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_251_TORGTS + ); + cs_251_OUTMUX_283 : X_BUF + port map ( + I => cs_251_OBUF, + O => cs_251_OUTMUX + ); + cs_148_OBUF_284 : X_TRI + port map ( + I => cs_148_OUTMUX, + CTL => cs_148_ENABLE, + O => cs(148) + ); + cs_148_ENABLEINV : X_INV + port map ( + I => cs_148_TORGTS, + O => cs_148_ENABLE + ); + cs_148_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_148_TORGTS + ); + cs_148_OUTMUX_285 : X_BUF + port map ( + I => cs_148_OBUF, + O => cs_148_OUTMUX + ); + cs_156_OBUF_286 : X_TRI + port map ( + I => cs_156_OUTMUX, + CTL => cs_156_ENABLE, + O => cs(156) + ); + cs_156_ENABLEINV : X_INV + port map ( + I => cs_156_TORGTS, + O => cs_156_ENABLE + ); + cs_156_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_156_TORGTS + ); + cs_156_OUTMUX_287 : X_BUF + port map ( + I => cs_156_OBUF, + O => cs_156_OUTMUX + ); + cs_164_OBUF_288 : X_TRI + port map ( + I => cs_164_OUTMUX, + CTL => cs_164_ENABLE, + O => cs(164) + ); + cs_164_ENABLEINV : X_INV + port map ( + I => cs_164_TORGTS, + O => cs_164_ENABLE + ); + cs_164_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_164_TORGTS + ); + cs_164_OUTMUX_289 : X_BUF + port map ( + I => cs_164_OBUF, + O => cs_164_OUTMUX + ); + cs_172_OBUF_290 : X_TRI + port map ( + I => cs_172_OUTMUX, + CTL => cs_172_ENABLE, + O => cs(172) + ); + cs_172_ENABLEINV : X_INV + port map ( + I => cs_172_TORGTS, + O => cs_172_ENABLE + ); + cs_172_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_172_TORGTS + ); + cs_172_OUTMUX_291 : X_BUF + port map ( + I => cs_172_OBUF, + O => cs_172_OUTMUX + ); + cs_180_OBUF_292 : X_TRI + port map ( + I => cs_180_OUTMUX, + CTL => cs_180_ENABLE, + O => cs(180) + ); + cs_180_ENABLEINV : X_INV + port map ( + I => cs_180_TORGTS, + O => cs_180_ENABLE + ); + cs_180_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_180_TORGTS + ); + cs_180_OUTMUX_293 : X_BUF + port map ( + I => cs_180_OBUF, + O => cs_180_OUTMUX + ); + cs_228_OBUF_294 : X_TRI + port map ( + I => cs_228_OUTMUX, + CTL => cs_228_ENABLE, + O => cs(228) + ); + cs_228_ENABLEINV : X_INV + port map ( + I => cs_228_TORGTS, + O => cs_228_ENABLE + ); + cs_228_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_228_TORGTS + ); + cs_228_OUTMUX_295 : X_BUF + port map ( + I => cs_228_OBUF, + O => cs_228_OUTMUX + ); + cs_236_OBUF_296 : X_TRI + port map ( + I => cs_236_OUTMUX, + CTL => cs_236_ENABLE, + O => cs(236) + ); + cs_236_ENABLEINV : X_INV + port map ( + I => cs_236_TORGTS, + O => cs_236_ENABLE + ); + cs_236_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_236_TORGTS + ); + cs_236_OUTMUX_297 : X_BUF + port map ( + I => cs_236_OBUF, + O => cs_236_OUTMUX + ); + cs_244_OBUF_298 : X_TRI + port map ( + I => cs_244_OUTMUX, + CTL => cs_244_ENABLE, + O => cs(244) + ); + cs_244_ENABLEINV : X_INV + port map ( + I => cs_244_TORGTS, + O => cs_244_ENABLE + ); + cs_244_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_244_TORGTS + ); + cs_244_OUTMUX_299 : X_BUF + port map ( + I => cs_244_OBUF, + O => cs_244_OUTMUX + ); + cs_252_OBUF_300 : X_TRI + port map ( + I => cs_252_OUTMUX, + CTL => cs_252_ENABLE, + O => cs(252) + ); + cs_252_ENABLEINV : X_INV + port map ( + I => cs_252_TORGTS, + O => cs_252_ENABLE + ); + cs_252_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_252_TORGTS + ); + cs_252_OUTMUX_301 : X_BUF + port map ( + I => cs_252_OBUF, + O => cs_252_OUTMUX + ); + cs_149_OBUF_302 : X_TRI + port map ( + I => cs_149_OUTMUX, + CTL => cs_149_ENABLE, + O => cs(149) + ); + cs_149_ENABLEINV : X_INV + port map ( + I => cs_149_TORGTS, + O => cs_149_ENABLE + ); + cs_149_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_149_TORGTS + ); + cs_149_OUTMUX_303 : X_BUF + port map ( + I => cs_149_OBUF, + O => cs_149_OUTMUX + ); + cs_157_OBUF_304 : X_TRI + port map ( + I => cs_157_OUTMUX, + CTL => cs_157_ENABLE, + O => cs(157) + ); + cs_157_ENABLEINV : X_INV + port map ( + I => cs_157_TORGTS, + O => cs_157_ENABLE + ); + cs_157_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_157_TORGTS + ); + cs_157_OUTMUX_305 : X_BUF + port map ( + I => cs_157_OBUF, + O => cs_157_OUTMUX + ); + cs_165_OBUF_306 : X_TRI + port map ( + I => cs_165_OUTMUX, + CTL => cs_165_ENABLE, + O => cs(165) + ); + cs_165_ENABLEINV : X_INV + port map ( + I => cs_165_TORGTS, + O => cs_165_ENABLE + ); + cs_165_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_165_TORGTS + ); + cs_165_OUTMUX_307 : X_BUF + port map ( + I => cs_165_OBUF, + O => cs_165_OUTMUX + ); + cs_173_OBUF_308 : X_TRI + port map ( + I => cs_173_OUTMUX, + CTL => cs_173_ENABLE, + O => cs(173) + ); + cs_173_ENABLEINV : X_INV + port map ( + I => cs_173_TORGTS, + O => cs_173_ENABLE + ); + cs_173_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_173_TORGTS + ); + cs_173_OUTMUX_309 : X_BUF + port map ( + I => cs_173_OBUF, + O => cs_173_OUTMUX + ); + cs_181_OBUF_310 : X_TRI + port map ( + I => cs_181_OUTMUX, + CTL => cs_181_ENABLE, + O => cs(181) + ); + cs_181_ENABLEINV : X_INV + port map ( + I => cs_181_TORGTS, + O => cs_181_ENABLE + ); + cs_181_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_181_TORGTS + ); + cs_181_OUTMUX_311 : X_BUF + port map ( + I => cs_181_OBUF, + O => cs_181_OUTMUX + ); + cs_229_OBUF_312 : X_TRI + port map ( + I => cs_229_OUTMUX, + CTL => cs_229_ENABLE, + O => cs(229) + ); + cs_229_ENABLEINV : X_INV + port map ( + I => cs_229_TORGTS, + O => cs_229_ENABLE + ); + cs_229_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_229_TORGTS + ); + cs_229_OUTMUX_313 : X_BUF + port map ( + I => cs_229_OBUF, + O => cs_229_OUTMUX + ); + cs_237_OBUF_314 : X_TRI + port map ( + I => cs_237_OUTMUX, + CTL => cs_237_ENABLE, + O => cs(237) + ); + cs_237_ENABLEINV : X_INV + port map ( + I => cs_237_TORGTS, + O => cs_237_ENABLE + ); + cs_237_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_237_TORGTS + ); + cs_237_OUTMUX_315 : X_BUF + port map ( + I => cs_237_OBUF, + O => cs_237_OUTMUX + ); + cs_245_OBUF_316 : X_TRI + port map ( + I => cs_245_OUTMUX, + CTL => cs_245_ENABLE, + O => cs(245) + ); + cs_245_ENABLEINV : X_INV + port map ( + I => cs_245_TORGTS, + O => cs_245_ENABLE + ); + cs_245_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_245_TORGTS + ); + cs_245_OUTMUX_317 : X_BUF + port map ( + I => cs_245_OBUF, + O => cs_245_OUTMUX + ); + cs_253_OBUF_318 : X_TRI + port map ( + I => cs_253_OUTMUX, + CTL => cs_253_ENABLE, + O => cs(253) + ); + cs_253_ENABLEINV : X_INV + port map ( + I => cs_253_TORGTS, + O => cs_253_ENABLE + ); + cs_253_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_253_TORGTS + ); + cs_253_OUTMUX_319 : X_BUF + port map ( + I => cs_253_OBUF, + O => cs_253_OUTMUX + ); + cs_158_OBUF_320 : X_TRI + port map ( + I => cs_158_OUTMUX, + CTL => cs_158_ENABLE, + O => cs(158) + ); + cs_158_ENABLEINV : X_INV + port map ( + I => cs_158_TORGTS, + O => cs_158_ENABLE + ); + cs_158_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_158_TORGTS + ); + cs_158_OUTMUX_321 : X_BUF + port map ( + I => cs_158_OBUF, + O => cs_158_OUTMUX + ); + cs_166_OBUF_322 : X_TRI + port map ( + I => cs_166_OUTMUX, + CTL => cs_166_ENABLE, + O => cs(166) + ); + cs_166_ENABLEINV : X_INV + port map ( + I => cs_166_TORGTS, + O => cs_166_ENABLE + ); + cs_166_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_166_TORGTS + ); + cs_166_OUTMUX_323 : X_BUF + port map ( + I => cs_166_OBUF, + O => cs_166_OUTMUX + ); + cs_174_OBUF_324 : X_TRI + port map ( + I => cs_174_OUTMUX, + CTL => cs_174_ENABLE, + O => cs(174) + ); + cs_174_ENABLEINV : X_INV + port map ( + I => cs_174_TORGTS, + O => cs_174_ENABLE + ); + cs_174_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_174_TORGTS + ); + cs_174_OUTMUX_325 : X_BUF + port map ( + I => cs_174_OBUF, + O => cs_174_OUTMUX + ); + cs_182_OBUF_326 : X_TRI + port map ( + I => cs_182_OUTMUX, + CTL => cs_182_ENABLE, + O => cs(182) + ); + cs_182_ENABLEINV : X_INV + port map ( + I => cs_182_TORGTS, + O => cs_182_ENABLE + ); + cs_182_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_182_TORGTS + ); + cs_182_OUTMUX_327 : X_BUF + port map ( + I => cs_182_OBUF, + O => cs_182_OUTMUX + ); + cs_190_OBUF_328 : X_TRI + port map ( + I => cs_190_OUTMUX, + CTL => cs_190_ENABLE, + O => cs(190) + ); + cs_190_ENABLEINV : X_INV + port map ( + I => cs_190_TORGTS, + O => cs_190_ENABLE + ); + cs_190_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_190_TORGTS + ); + cs_190_OUTMUX_329 : X_BUF + port map ( + I => cs_190_OBUF, + O => cs_190_OUTMUX + ); + cs_238_OBUF_330 : X_TRI + port map ( + I => cs_238_OUTMUX, + CTL => cs_238_ENABLE, + O => cs(238) + ); + cs_238_ENABLEINV : X_INV + port map ( + I => cs_238_TORGTS, + O => cs_238_ENABLE + ); + cs_238_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_238_TORGTS + ); + cs_238_OUTMUX_331 : X_BUF + port map ( + I => cs_238_OBUF, + O => cs_238_OUTMUX + ); + cs_246_OBUF_332 : X_TRI + port map ( + I => cs_246_OUTMUX, + CTL => cs_246_ENABLE, + O => cs(246) + ); + cs_246_ENABLEINV : X_INV + port map ( + I => cs_246_TORGTS, + O => cs_246_ENABLE + ); + cs_246_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_246_TORGTS + ); + cs_246_OUTMUX_333 : X_BUF + port map ( + I => cs_246_OBUF, + O => cs_246_OUTMUX + ); + cs_254_OBUF_334 : X_TRI + port map ( + I => cs_254_OUTMUX, + CTL => cs_254_ENABLE, + O => cs(254) + ); + cs_254_ENABLEINV : X_INV + port map ( + I => cs_254_TORGTS, + O => cs_254_ENABLE + ); + cs_254_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_254_TORGTS + ); + cs_254_OUTMUX_335 : X_BUF + port map ( + I => cs_254_OBUF, + O => cs_254_OUTMUX + ); + cs_159_OBUF_336 : X_TRI + port map ( + I => cs_159_OUTMUX, + CTL => cs_159_ENABLE, + O => cs(159) + ); + cs_159_ENABLEINV : X_INV + port map ( + I => cs_159_TORGTS, + O => cs_159_ENABLE + ); + cs_159_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_159_TORGTS + ); + cs_159_OUTMUX_337 : X_BUF + port map ( + I => cs_159_OBUF, + O => cs_159_OUTMUX + ); + cs_167_OBUF_338 : X_TRI + port map ( + I => cs_167_OUTMUX, + CTL => cs_167_ENABLE, + O => cs(167) + ); + cs_167_ENABLEINV : X_INV + port map ( + I => cs_167_TORGTS, + O => cs_167_ENABLE + ); + cs_167_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_167_TORGTS + ); + cs_167_OUTMUX_339 : X_BUF + port map ( + I => cs_167_OBUF, + O => cs_167_OUTMUX + ); + cs_175_OBUF_340 : X_TRI + port map ( + I => cs_175_OUTMUX, + CTL => cs_175_ENABLE, + O => cs(175) + ); + cs_175_ENABLEINV : X_INV + port map ( + I => cs_175_TORGTS, + O => cs_175_ENABLE + ); + cs_175_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_175_TORGTS + ); + cs_175_OUTMUX_341 : X_BUF + port map ( + I => cs_175_OBUF, + O => cs_175_OUTMUX + ); + cs_183_OBUF_342 : X_TRI + port map ( + I => cs_183_OUTMUX, + CTL => cs_183_ENABLE, + O => cs(183) + ); + cs_183_ENABLEINV : X_INV + port map ( + I => cs_183_TORGTS, + O => cs_183_ENABLE + ); + cs_183_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_183_TORGTS + ); + cs_183_OUTMUX_343 : X_BUF + port map ( + I => cs_183_OBUF, + O => cs_183_OUTMUX + ); + cs_191_OBUF_344 : X_TRI + port map ( + I => cs_191_OUTMUX, + CTL => cs_191_ENABLE, + O => cs(191) + ); + cs_191_ENABLEINV : X_INV + port map ( + I => cs_191_TORGTS, + O => cs_191_ENABLE + ); + cs_191_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_191_TORGTS + ); + cs_191_OUTMUX_345 : X_BUF + port map ( + I => cs_191_OBUF, + O => cs_191_OUTMUX + ); + cs_239_OBUF_346 : X_TRI + port map ( + I => cs_239_OUTMUX, + CTL => cs_239_ENABLE, + O => cs(239) + ); + cs_239_ENABLEINV : X_INV + port map ( + I => cs_239_TORGTS, + O => cs_239_ENABLE + ); + cs_239_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_239_TORGTS + ); + cs_239_OUTMUX_347 : X_BUF + port map ( + I => cs_239_OBUF, + O => cs_239_OUTMUX + ); + cs_247_OBUF_348 : X_TRI + port map ( + I => cs_247_OUTMUX, + CTL => cs_247_ENABLE, + O => cs(247) + ); + cs_247_ENABLEINV : X_INV + port map ( + I => cs_247_TORGTS, + O => cs_247_ENABLE + ); + cs_247_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_247_TORGTS + ); + cs_247_OUTMUX_349 : X_BUF + port map ( + I => cs_247_OBUF, + O => cs_247_OUTMUX + ); + cs_255_OBUF_350 : X_TRI + port map ( + I => cs_255_OUTMUX, + CTL => cs_255_ENABLE, + O => cs(255) + ); + cs_255_ENABLEINV : X_INV + port map ( + I => cs_255_TORGTS, + O => cs_255_ENABLE + ); + cs_255_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_255_TORGTS + ); + cs_255_OUTMUX_351 : X_BUF + port map ( + I => cs_255_OBUF, + O => cs_255_OUTMUX + ); + cs_168_OBUF_352 : X_TRI + port map ( + I => cs_168_OUTMUX, + CTL => cs_168_ENABLE, + O => cs(168) + ); + cs_168_ENABLEINV : X_INV + port map ( + I => cs_168_TORGTS, + O => cs_168_ENABLE + ); + cs_168_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_168_TORGTS + ); + cs_168_OUTMUX_353 : X_BUF + port map ( + I => cs_168_OBUF, + O => cs_168_OUTMUX + ); + cs_176_OBUF_354 : X_TRI + port map ( + I => cs_176_OUTMUX, + CTL => cs_176_ENABLE, + O => cs(176) + ); + cs_176_ENABLEINV : X_INV + port map ( + I => cs_176_TORGTS, + O => cs_176_ENABLE + ); + cs_176_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_176_TORGTS + ); + cs_176_OUTMUX_355 : X_BUF + port map ( + I => cs_176_OBUF, + O => cs_176_OUTMUX + ); + cs_184_OBUF_356 : X_TRI + port map ( + I => cs_184_OUTMUX, + CTL => cs_184_ENABLE, + O => cs(184) + ); + cs_184_ENABLEINV : X_INV + port map ( + I => cs_184_TORGTS, + O => cs_184_ENABLE + ); + cs_184_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_184_TORGTS + ); + cs_184_OUTMUX_357 : X_BUF + port map ( + I => cs_184_OBUF, + O => cs_184_OUTMUX + ); + cs_192_OBUF_358 : X_TRI + port map ( + I => cs_192_OUTMUX, + CTL => cs_192_ENABLE, + O => cs(192) + ); + cs_192_ENABLEINV : X_INV + port map ( + I => cs_192_TORGTS, + O => cs_192_ENABLE + ); + cs_192_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_192_TORGTS + ); + cs_192_OUTMUX_359 : X_BUF + port map ( + I => cs_192_OBUF, + O => cs_192_OUTMUX + ); + cs_248_OBUF_360 : X_TRI + port map ( + I => cs_248_OUTMUX, + CTL => cs_248_ENABLE, + O => cs(248) + ); + cs_248_ENABLEINV : X_INV + port map ( + I => cs_248_TORGTS, + O => cs_248_ENABLE + ); + cs_248_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_248_TORGTS + ); + cs_248_OUTMUX_361 : X_BUF + port map ( + I => cs_248_OBUF, + O => cs_248_OUTMUX + ); + cs_169_OBUF_362 : X_TRI + port map ( + I => cs_169_OUTMUX, + CTL => cs_169_ENABLE, + O => cs(169) + ); + cs_169_ENABLEINV : X_INV + port map ( + I => cs_169_TORGTS, + O => cs_169_ENABLE + ); + cs_169_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_169_TORGTS + ); + cs_169_OUTMUX_363 : X_BUF + port map ( + I => cs_169_OBUF, + O => cs_169_OUTMUX + ); + cs_177_OBUF_364 : X_TRI + port map ( + I => cs_177_OUTMUX, + CTL => cs_177_ENABLE, + O => cs(177) + ); + cs_177_ENABLEINV : X_INV + port map ( + I => cs_177_TORGTS, + O => cs_177_ENABLE + ); + cs_177_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_177_TORGTS + ); + cs_177_OUTMUX_365 : X_BUF + port map ( + I => cs_177_OBUF, + O => cs_177_OUTMUX + ); + cs_185_OBUF_366 : X_TRI + port map ( + I => cs_185_OUTMUX, + CTL => cs_185_ENABLE, + O => cs(185) + ); + cs_185_ENABLEINV : X_INV + port map ( + I => cs_185_TORGTS, + O => cs_185_ENABLE + ); + cs_185_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_185_TORGTS + ); + cs_185_OUTMUX_367 : X_BUF + port map ( + I => cs_185_OBUF, + O => cs_185_OUTMUX + ); + cs_193_OBUF_368 : X_TRI + port map ( + I => cs_193_OUTMUX, + CTL => cs_193_ENABLE, + O => cs(193) + ); + cs_193_ENABLEINV : X_INV + port map ( + I => cs_193_TORGTS, + O => cs_193_ENABLE + ); + cs_193_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_193_TORGTS + ); + cs_193_OUTMUX_369 : X_BUF + port map ( + I => cs_193_OBUF, + O => cs_193_OUTMUX + ); + cs_249_OBUF_370 : X_TRI + port map ( + I => cs_249_OUTMUX, + CTL => cs_249_ENABLE, + O => cs(249) + ); + cs_249_ENABLEINV : X_INV + port map ( + I => cs_249_TORGTS, + O => cs_249_ENABLE + ); + cs_249_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_249_TORGTS + ); + cs_249_OUTMUX_371 : X_BUF + port map ( + I => cs_249_OBUF, + O => cs_249_OUTMUX + ); + cs_178_OBUF_372 : X_TRI + port map ( + I => cs_178_OUTMUX, + CTL => cs_178_ENABLE, + O => cs(178) + ); + cs_178_ENABLEINV : X_INV + port map ( + I => cs_178_TORGTS, + O => cs_178_ENABLE + ); + cs_178_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_178_TORGTS + ); + cs_178_OUTMUX_373 : X_BUF + port map ( + I => cs_178_OBUF, + O => cs_178_OUTMUX + ); + cs_186_OBUF_374 : X_TRI + port map ( + I => cs_186_OUTMUX, + CTL => cs_186_ENABLE, + O => cs(186) + ); + cs_186_ENABLEINV : X_INV + port map ( + I => cs_186_TORGTS, + O => cs_186_ENABLE + ); + cs_186_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_186_TORGTS + ); + cs_186_OUTMUX_375 : X_BUF + port map ( + I => cs_186_OBUF, + O => cs_186_OUTMUX + ); + cs_194_OBUF_376 : X_TRI + port map ( + I => cs_194_OUTMUX, + CTL => cs_194_ENABLE, + O => cs(194) + ); + cs_194_ENABLEINV : X_INV + port map ( + I => cs_194_TORGTS, + O => cs_194_ENABLE + ); + cs_194_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_194_TORGTS + ); + cs_194_OUTMUX_377 : X_BUF + port map ( + I => cs_194_OBUF, + O => cs_194_OUTMUX + ); + cs_179_OBUF_378 : X_TRI + port map ( + I => cs_179_OUTMUX, + CTL => cs_179_ENABLE, + O => cs(179) + ); + cs_179_ENABLEINV : X_INV + port map ( + I => cs_179_TORGTS, + O => cs_179_ENABLE + ); + cs_179_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_179_TORGTS + ); + cs_179_OUTMUX_379 : X_BUF + port map ( + I => cs_179_OBUF, + O => cs_179_OUTMUX + ); + cs_187_OBUF_380 : X_TRI + port map ( + I => cs_187_OUTMUX, + CTL => cs_187_ENABLE, + O => cs(187) + ); + cs_187_ENABLEINV : X_INV + port map ( + I => cs_187_TORGTS, + O => cs_187_ENABLE + ); + cs_187_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_187_TORGTS + ); + cs_187_OUTMUX_381 : X_BUF + port map ( + I => cs_187_OBUF, + O => cs_187_OUTMUX + ); + cs_195_OBUF_382 : X_TRI + port map ( + I => cs_195_OUTMUX, + CTL => cs_195_ENABLE, + O => cs(195) + ); + cs_195_ENABLEINV : X_INV + port map ( + I => cs_195_TORGTS, + O => cs_195_ENABLE + ); + cs_195_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_195_TORGTS + ); + cs_195_OUTMUX_383 : X_BUF + port map ( + I => cs_195_OBUF, + O => cs_195_OUTMUX + ); + cs_188_OBUF_384 : X_TRI + port map ( + I => cs_188_OUTMUX, + CTL => cs_188_ENABLE, + O => cs(188) + ); + cs_188_ENABLEINV : X_INV + port map ( + I => cs_188_TORGTS, + O => cs_188_ENABLE + ); + cs_188_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_188_TORGTS + ); + cs_188_OUTMUX_385 : X_BUF + port map ( + I => cs_188_OBUF, + O => cs_188_OUTMUX + ); + cs_196_OBUF_386 : X_TRI + port map ( + I => cs_196_OUTMUX, + CTL => cs_196_ENABLE, + O => cs(196) + ); + cs_196_ENABLEINV : X_INV + port map ( + I => cs_196_TORGTS, + O => cs_196_ENABLE + ); + cs_196_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_196_TORGTS + ); + cs_196_OUTMUX_387 : X_BUF + port map ( + I => cs_196_OBUF, + O => cs_196_OUTMUX + ); + cs_189_OBUF_388 : X_TRI + port map ( + I => cs_189_OUTMUX, + CTL => cs_189_ENABLE, + O => cs(189) + ); + cs_189_ENABLEINV : X_INV + port map ( + I => cs_189_TORGTS, + O => cs_189_ENABLE + ); + cs_189_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_189_TORGTS + ); + cs_189_OUTMUX_389 : X_BUF + port map ( + I => cs_189_OBUF, + O => cs_189_OUTMUX + ); + cs_197_OBUF_390 : X_TRI + port map ( + I => cs_197_OUTMUX, + CTL => cs_197_ENABLE, + O => cs(197) + ); + cs_197_ENABLEINV : X_INV + port map ( + I => cs_197_TORGTS, + O => cs_197_ENABLE + ); + cs_197_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_197_TORGTS + ); + cs_197_OUTMUX_391 : X_BUF + port map ( + I => cs_197_OBUF, + O => cs_197_OUTMUX + ); + cs_198_OBUF_392 : X_TRI + port map ( + I => cs_198_OUTMUX, + CTL => cs_198_ENABLE, + O => cs(198) + ); + cs_198_ENABLEINV : X_INV + port map ( + I => cs_198_TORGTS, + O => cs_198_ENABLE + ); + cs_198_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_198_TORGTS + ); + cs_198_OUTMUX_393 : X_BUF + port map ( + I => cs_198_OBUF, + O => cs_198_OUTMUX + ); + cs_199_OBUF_394 : X_TRI + port map ( + I => cs_199_OUTMUX, + CTL => cs_199_ENABLE, + O => cs(199) + ); + cs_199_ENABLEINV : X_INV + port map ( + I => cs_199_TORGTS, + O => cs_199_ENABLE + ); + cs_199_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_199_TORGTS + ); + cs_199_OUTMUX_395 : X_BUF + port map ( + I => cs_199_OBUF, + O => cs_199_OUTMUX + ); + clk_OBUF_396 : X_TRI + port map ( + I => clk_OUTMUX, + CTL => clk_ENABLE, + O => clk + ); + clk_ENABLEINV : X_INV + port map ( + I => clk_TORGTS, + O => clk_ENABLE + ); + clk_GTS_OR : X_BUF + port map ( + I => GTS, + O => clk_TORGTS + ); + clk_OUTMUX_397 : X_BUF + port map ( + I => clk_OBUF, + O => clk_OUTMUX + ); + adr_bus_10_IMUX : X_BUF + port map ( + I => adr_bus_10_IBUF_13, + O => adr_bus_10_IBUF + ); + adr_bus_10_IBUF_398 : X_BUF + port map ( + I => adr_bus(10), + O => adr_bus_10_IBUF_13 + ); + adr_bus_11_IMUX : X_BUF + port map ( + I => adr_bus_11_IBUF_14, + O => adr_bus_11_IBUF + ); + adr_bus_11_IBUF_399 : X_BUF + port map ( + I => adr_bus(11), + O => adr_bus_11_IBUF_14 + ); + adr_bus_12_IMUX : X_BUF + port map ( + I => adr_bus_12_IBUF_15, + O => adr_bus_12_IBUF + ); + adr_bus_12_IBUF_400 : X_BUF + port map ( + I => adr_bus(12), + O => adr_bus_12_IBUF_15 + ); + adr_bus_13_IMUX : X_BUF + port map ( + I => adr_bus_13_IBUF_16, + O => adr_bus_13_IBUF + ); + adr_bus_13_IBUF_401 : X_BUF + port map ( + I => adr_bus(13), + O => adr_bus_13_IBUF_16 + ); + adr_bus_14_IMUX : X_BUF + port map ( + I => adr_bus_14_IBUF_17, + O => adr_bus_14_IBUF + ); + adr_bus_14_IBUF_402 : X_BUF + port map ( + I => adr_bus(14), + O => adr_bus_14_IBUF_17 + ); + adr_bus_15_IMUX : X_BUF + port map ( + I => adr_bus_15_IBUF_18, + O => adr_bus_15_IBUF + ); + adr_bus_15_IBUF_403 : X_BUF + port map ( + I => adr_bus(15), + O => adr_bus_15_IBUF_18 + ); + cs_10_OBUF_404 : X_TRI + port map ( + I => cs_10_OUTMUX, + CTL => cs_10_ENABLE, + O => cs(10) + ); + cs_10_ENABLEINV : X_INV + port map ( + I => cs_10_TORGTS, + O => cs_10_ENABLE + ); + cs_10_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_10_TORGTS + ); + cs_10_OUTMUX_405 : X_BUF + port map ( + I => cs_10_OBUF, + O => cs_10_OUTMUX + ); + cs_11_OBUF_406 : X_TRI + port map ( + I => cs_11_OUTMUX, + CTL => cs_11_ENABLE, + O => cs(11) + ); + cs_11_ENABLEINV : X_INV + port map ( + I => cs_11_TORGTS, + O => cs_11_ENABLE + ); + cs_11_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_11_TORGTS + ); + cs_11_OUTMUX_407 : X_BUF + port map ( + I => cs_11_OBUF, + O => cs_11_OUTMUX + ); + cs_12_OBUF_408 : X_TRI + port map ( + I => cs_12_OUTMUX, + CTL => cs_12_ENABLE, + O => cs(12) + ); + cs_12_ENABLEINV : X_INV + port map ( + I => cs_12_TORGTS, + O => cs_12_ENABLE + ); + cs_12_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_12_TORGTS + ); + cs_12_OUTMUX_409 : X_BUF + port map ( + I => cs_12_OBUF, + O => cs_12_OUTMUX + ); + cs_20_OBUF_410 : X_TRI + port map ( + I => cs_20_OUTMUX, + CTL => cs_20_ENABLE, + O => cs(20) + ); + cs_20_ENABLEINV : X_INV + port map ( + I => cs_20_TORGTS, + O => cs_20_ENABLE + ); + cs_20_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_20_TORGTS + ); + cs_20_OUTMUX_411 : X_BUF + port map ( + I => cs_20_OBUF, + O => cs_20_OUTMUX + ); + cs_13_OBUF_412 : X_TRI + port map ( + I => cs_13_OUTMUX, + CTL => cs_13_ENABLE, + O => cs(13) + ); + cs_13_ENABLEINV : X_INV + port map ( + I => cs_13_TORGTS, + O => cs_13_ENABLE + ); + cs_13_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_13_TORGTS + ); + cs_13_OUTMUX_413 : X_BUF + port map ( + I => cs_13_OBUF, + O => cs_13_OUTMUX + ); + cs_21_OBUF_414 : X_TRI + port map ( + I => cs_21_OUTMUX, + CTL => cs_21_ENABLE, + O => cs(21) + ); + cs_21_ENABLEINV : X_INV + port map ( + I => cs_21_TORGTS, + O => cs_21_ENABLE + ); + cs_21_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_21_TORGTS + ); + cs_21_OUTMUX_415 : X_BUF + port map ( + I => cs_21_OBUF, + O => cs_21_OUTMUX + ); + cs_14_OBUF_416 : X_TRI + port map ( + I => cs_14_OUTMUX, + CTL => cs_14_ENABLE, + O => cs(14) + ); + cs_14_ENABLEINV : X_INV + port map ( + I => cs_14_TORGTS, + O => cs_14_ENABLE + ); + cs_14_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_14_TORGTS + ); + cs_14_OUTMUX_417 : X_BUF + port map ( + I => cs_14_OBUF, + O => cs_14_OUTMUX + ); + cs_22_OBUF_418 : X_TRI + port map ( + I => cs_22_OUTMUX, + CTL => cs_22_ENABLE, + O => cs(22) + ); + cs_22_ENABLEINV : X_INV + port map ( + I => cs_22_TORGTS, + O => cs_22_ENABLE + ); + cs_22_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_22_TORGTS + ); + cs_22_OUTMUX_419 : X_BUF + port map ( + I => cs_22_OBUF, + O => cs_22_OUTMUX + ); + cs_30_OBUF_420 : X_TRI + port map ( + I => cs_30_OUTMUX, + CTL => cs_30_ENABLE, + O => cs(30) + ); + cs_30_ENABLEINV : X_INV + port map ( + I => cs_30_TORGTS, + O => cs_30_ENABLE + ); + cs_30_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_30_TORGTS + ); + cs_30_OUTMUX_421 : X_BUF + port map ( + I => cs_30_OBUF, + O => cs_30_OUTMUX + ); + cs_15_OBUF_422 : X_TRI + port map ( + I => cs_15_OUTMUX, + CTL => cs_15_ENABLE, + O => cs(15) + ); + cs_15_ENABLEINV : X_INV + port map ( + I => cs_15_TORGTS, + O => cs_15_ENABLE + ); + cs_15_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_15_TORGTS + ); + cs_15_OUTMUX_423 : X_BUF + port map ( + I => cs_15_OBUF, + O => cs_15_OUTMUX + ); + cs_23_OBUF_424 : X_TRI + port map ( + I => cs_23_OUTMUX, + CTL => cs_23_ENABLE, + O => cs(23) + ); + cs_23_ENABLEINV : X_INV + port map ( + I => cs_23_TORGTS, + O => cs_23_ENABLE + ); + cs_23_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_23_TORGTS + ); + cs_23_OUTMUX_425 : X_BUF + port map ( + I => cs_23_OBUF, + O => cs_23_OUTMUX + ); + cs_31_OBUF_426 : X_TRI + port map ( + I => cs_31_OUTMUX, + CTL => cs_31_ENABLE, + O => cs(31) + ); + cs_31_ENABLEINV : X_INV + port map ( + I => cs_31_TORGTS, + O => cs_31_ENABLE + ); + cs_31_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_31_TORGTS + ); + cs_31_OUTMUX_427 : X_BUF + port map ( + I => cs_31_OBUF, + O => cs_31_OUTMUX + ); + cs_16_OBUF_428 : X_TRI + port map ( + I => cs_16_OUTMUX, + CTL => cs_16_ENABLE, + O => cs(16) + ); + cs_16_ENABLEINV : X_INV + port map ( + I => cs_16_TORGTS, + O => cs_16_ENABLE + ); + cs_16_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_16_TORGTS + ); + cs_16_OUTMUX_429 : X_BUF + port map ( + I => cs_16_OBUF, + O => cs_16_OUTMUX + ); + cs_24_OBUF_430 : X_TRI + port map ( + I => cs_24_OUTMUX, + CTL => cs_24_ENABLE, + O => cs(24) + ); + cs_24_ENABLEINV : X_INV + port map ( + I => cs_24_TORGTS, + O => cs_24_ENABLE + ); + cs_24_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_24_TORGTS + ); + cs_24_OUTMUX_431 : X_BUF + port map ( + I => cs_24_OBUF, + O => cs_24_OUTMUX + ); + cs_32_OBUF_432 : X_TRI + port map ( + I => cs_32_OUTMUX, + CTL => cs_32_ENABLE, + O => cs(32) + ); + cs_32_ENABLEINV : X_INV + port map ( + I => cs_32_TORGTS, + O => cs_32_ENABLE + ); + cs_32_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_32_TORGTS + ); + cs_32_OUTMUX_433 : X_BUF + port map ( + I => cs_32_OBUF, + O => cs_32_OUTMUX + ); + cs_40_OBUF_434 : X_TRI + port map ( + I => cs_40_OUTMUX, + CTL => cs_40_ENABLE, + O => cs(40) + ); + cs_40_ENABLEINV : X_INV + port map ( + I => cs_40_TORGTS, + O => cs_40_ENABLE + ); + cs_40_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_40_TORGTS + ); + cs_40_OUTMUX_435 : X_BUF + port map ( + I => cs_40_OBUF, + O => cs_40_OUTMUX + ); + cs_17_OBUF_436 : X_TRI + port map ( + I => cs_17_OUTMUX, + CTL => cs_17_ENABLE, + O => cs(17) + ); + cs_17_ENABLEINV : X_INV + port map ( + I => cs_17_TORGTS, + O => cs_17_ENABLE + ); + cs_17_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_17_TORGTS + ); + cs_17_OUTMUX_437 : X_BUF + port map ( + I => cs_17_OBUF, + O => cs_17_OUTMUX + ); + cs_25_OBUF_438 : X_TRI + port map ( + I => cs_25_OUTMUX, + CTL => cs_25_ENABLE, + O => cs(25) + ); + cs_25_ENABLEINV : X_INV + port map ( + I => cs_25_TORGTS, + O => cs_25_ENABLE + ); + cs_25_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_25_TORGTS + ); + cs_25_OUTMUX_439 : X_BUF + port map ( + I => cs_25_OBUF, + O => cs_25_OUTMUX + ); + cs_33_OBUF_440 : X_TRI + port map ( + I => cs_33_OUTMUX, + CTL => cs_33_ENABLE, + O => cs(33) + ); + cs_33_ENABLEINV : X_INV + port map ( + I => cs_33_TORGTS, + O => cs_33_ENABLE + ); + cs_33_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_33_TORGTS + ); + cs_33_OUTMUX_441 : X_BUF + port map ( + I => cs_33_OBUF, + O => cs_33_OUTMUX + ); + cs_41_OBUF_442 : X_TRI + port map ( + I => cs_41_OUTMUX, + CTL => cs_41_ENABLE, + O => cs(41) + ); + cs_41_ENABLEINV : X_INV + port map ( + I => cs_41_TORGTS, + O => cs_41_ENABLE + ); + cs_41_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_41_TORGTS + ); + cs_41_OUTMUX_443 : X_BUF + port map ( + I => cs_41_OBUF, + O => cs_41_OUTMUX + ); + cs_18_OBUF_444 : X_TRI + port map ( + I => cs_18_OUTMUX, + CTL => cs_18_ENABLE, + O => cs(18) + ); + cs_18_ENABLEINV : X_INV + port map ( + I => cs_18_TORGTS, + O => cs_18_ENABLE + ); + cs_18_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_18_TORGTS + ); + cs_18_OUTMUX_445 : X_BUF + port map ( + I => cs_18_OBUF, + O => cs_18_OUTMUX + ); + cs_26_OBUF_446 : X_TRI + port map ( + I => cs_26_OUTMUX, + CTL => cs_26_ENABLE, + O => cs(26) + ); + cs_26_ENABLEINV : X_INV + port map ( + I => cs_26_TORGTS, + O => cs_26_ENABLE + ); + cs_26_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_26_TORGTS + ); + cs_26_OUTMUX_447 : X_BUF + port map ( + I => cs_26_OBUF, + O => cs_26_OUTMUX + ); + cs_34_OBUF_448 : X_TRI + port map ( + I => cs_34_OUTMUX, + CTL => cs_34_ENABLE, + O => cs(34) + ); + cs_34_ENABLEINV : X_INV + port map ( + I => cs_34_TORGTS, + O => cs_34_ENABLE + ); + cs_34_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_34_TORGTS + ); + cs_34_OUTMUX_449 : X_BUF + port map ( + I => cs_34_OBUF, + O => cs_34_OUTMUX + ); + cs_42_OBUF_450 : X_TRI + port map ( + I => cs_42_OUTMUX, + CTL => cs_42_ENABLE, + O => cs(42) + ); + cs_42_ENABLEINV : X_INV + port map ( + I => cs_42_TORGTS, + O => cs_42_ENABLE + ); + cs_42_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_42_TORGTS + ); + cs_42_OUTMUX_451 : X_BUF + port map ( + I => cs_42_OBUF, + O => cs_42_OUTMUX + ); + cs_50_OBUF_452 : X_TRI + port map ( + I => cs_50_OUTMUX, + CTL => cs_50_ENABLE, + O => cs(50) + ); + cs_50_ENABLEINV : X_INV + port map ( + I => cs_50_TORGTS, + O => cs_50_ENABLE + ); + cs_50_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_50_TORGTS + ); + cs_50_OUTMUX_453 : X_BUF + port map ( + I => cs_50_OBUF, + O => cs_50_OUTMUX + ); + cs_19_OBUF_454 : X_TRI + port map ( + I => cs_19_OUTMUX, + CTL => cs_19_ENABLE, + O => cs(19) + ); + cs_19_ENABLEINV : X_INV + port map ( + I => cs_19_TORGTS, + O => cs_19_ENABLE + ); + cs_19_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_19_TORGTS + ); + cs_19_OUTMUX_455 : X_BUF + port map ( + I => cs_19_OBUF, + O => cs_19_OUTMUX + ); + cs_27_OBUF_456 : X_TRI + port map ( + I => cs_27_OUTMUX, + CTL => cs_27_ENABLE, + O => cs(27) + ); + cs_27_ENABLEINV : X_INV + port map ( + I => cs_27_TORGTS, + O => cs_27_ENABLE + ); + cs_27_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_27_TORGTS + ); + cs_27_OUTMUX_457 : X_BUF + port map ( + I => cs_27_OBUF, + O => cs_27_OUTMUX + ); + cs_35_OBUF_458 : X_TRI + port map ( + I => cs_35_OUTMUX, + CTL => cs_35_ENABLE, + O => cs(35) + ); + cs_35_ENABLEINV : X_INV + port map ( + I => cs_35_TORGTS, + O => cs_35_ENABLE + ); + cs_35_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_35_TORGTS + ); + cs_35_OUTMUX_459 : X_BUF + port map ( + I => cs_35_OBUF, + O => cs_35_OUTMUX + ); + cs_43_OBUF_460 : X_TRI + port map ( + I => cs_43_OUTMUX, + CTL => cs_43_ENABLE, + O => cs(43) + ); + cs_43_ENABLEINV : X_INV + port map ( + I => cs_43_TORGTS, + O => cs_43_ENABLE + ); + cs_43_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_43_TORGTS + ); + cs_43_OUTMUX_461 : X_BUF + port map ( + I => cs_43_OBUF, + O => cs_43_OUTMUX + ); + cs_51_OBUF_462 : X_TRI + port map ( + I => cs_51_OUTMUX, + CTL => cs_51_ENABLE, + O => cs(51) + ); + cs_51_ENABLEINV : X_INV + port map ( + I => cs_51_TORGTS, + O => cs_51_ENABLE + ); + cs_51_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_51_TORGTS + ); + cs_51_OUTMUX_463 : X_BUF + port map ( + I => cs_51_OBUF, + O => cs_51_OUTMUX + ); + cs_28_OBUF_464 : X_TRI + port map ( + I => cs_28_OUTMUX, + CTL => cs_28_ENABLE, + O => cs(28) + ); + cs_28_ENABLEINV : X_INV + port map ( + I => cs_28_TORGTS, + O => cs_28_ENABLE + ); + cs_28_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_28_TORGTS + ); + cs_28_OUTMUX_465 : X_BUF + port map ( + I => cs_28_OBUF, + O => cs_28_OUTMUX + ); + cs_36_OBUF_466 : X_TRI + port map ( + I => cs_36_OUTMUX, + CTL => cs_36_ENABLE, + O => cs(36) + ); + cs_36_ENABLEINV : X_INV + port map ( + I => cs_36_TORGTS, + O => cs_36_ENABLE + ); + cs_36_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_36_TORGTS + ); + cs_36_OUTMUX_467 : X_BUF + port map ( + I => cs_36_OBUF, + O => cs_36_OUTMUX + ); + cs_44_OBUF_468 : X_TRI + port map ( + I => cs_44_OUTMUX, + CTL => cs_44_ENABLE, + O => cs(44) + ); + cs_44_ENABLEINV : X_INV + port map ( + I => cs_44_TORGTS, + O => cs_44_ENABLE + ); + cs_44_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_44_TORGTS + ); + cs_44_OUTMUX_469 : X_BUF + port map ( + I => cs_44_OBUF, + O => cs_44_OUTMUX + ); + cs_52_OBUF_470 : X_TRI + port map ( + I => cs_52_OUTMUX, + CTL => cs_52_ENABLE, + O => cs(52) + ); + cs_52_ENABLEINV : X_INV + port map ( + I => cs_52_TORGTS, + O => cs_52_ENABLE + ); + cs_52_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_52_TORGTS + ); + cs_52_OUTMUX_471 : X_BUF + port map ( + I => cs_52_OBUF, + O => cs_52_OUTMUX + ); + cs_60_OBUF_472 : X_TRI + port map ( + I => cs_60_OUTMUX, + CTL => cs_60_ENABLE, + O => cs(60) + ); + cs_60_ENABLEINV : X_INV + port map ( + I => cs_60_TORGTS, + O => cs_60_ENABLE + ); + cs_60_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_60_TORGTS + ); + cs_60_OUTMUX_473 : X_BUF + port map ( + I => cs_60_OBUF, + O => cs_60_OUTMUX + ); + cs_29_OBUF_474 : X_TRI + port map ( + I => cs_29_OUTMUX, + CTL => cs_29_ENABLE, + O => cs(29) + ); + cs_29_ENABLEINV : X_INV + port map ( + I => cs_29_TORGTS, + O => cs_29_ENABLE + ); + cs_29_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_29_TORGTS + ); + cs_29_OUTMUX_475 : X_BUF + port map ( + I => cs_29_OBUF, + O => cs_29_OUTMUX + ); + cs_37_OBUF_476 : X_TRI + port map ( + I => cs_37_OUTMUX, + CTL => cs_37_ENABLE, + O => cs(37) + ); + cs_37_ENABLEINV : X_INV + port map ( + I => cs_37_TORGTS, + O => cs_37_ENABLE + ); + cs_37_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_37_TORGTS + ); + cs_37_OUTMUX_477 : X_BUF + port map ( + I => cs_37_OBUF, + O => cs_37_OUTMUX + ); + cs_45_OBUF_478 : X_TRI + port map ( + I => cs_45_OUTMUX, + CTL => cs_45_ENABLE, + O => cs(45) + ); + cs_45_ENABLEINV : X_INV + port map ( + I => cs_45_TORGTS, + O => cs_45_ENABLE + ); + cs_45_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_45_TORGTS + ); + cs_45_OUTMUX_479 : X_BUF + port map ( + I => cs_45_OBUF, + O => cs_45_OUTMUX + ); + cs_53_OBUF_480 : X_TRI + port map ( + I => cs_53_OUTMUX, + CTL => cs_53_ENABLE, + O => cs(53) + ); + cs_53_ENABLEINV : X_INV + port map ( + I => cs_53_TORGTS, + O => cs_53_ENABLE + ); + cs_53_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_53_TORGTS + ); + cs_53_OUTMUX_481 : X_BUF + port map ( + I => cs_53_OBUF, + O => cs_53_OUTMUX + ); + cs_61_OBUF_482 : X_TRI + port map ( + I => cs_61_OUTMUX, + CTL => cs_61_ENABLE, + O => cs(61) + ); + cs_61_ENABLEINV : X_INV + port map ( + I => cs_61_TORGTS, + O => cs_61_ENABLE + ); + cs_61_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_61_TORGTS + ); + cs_61_OUTMUX_483 : X_BUF + port map ( + I => cs_61_OBUF, + O => cs_61_OUTMUX + ); + cs_38_OBUF_484 : X_TRI + port map ( + I => cs_38_OUTMUX, + CTL => cs_38_ENABLE, + O => cs(38) + ); + cs_38_ENABLEINV : X_INV + port map ( + I => cs_38_TORGTS, + O => cs_38_ENABLE + ); + cs_38_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_38_TORGTS + ); + cs_38_OUTMUX_485 : X_BUF + port map ( + I => cs_38_OBUF, + O => cs_38_OUTMUX + ); + cs_46_OBUF_486 : X_TRI + port map ( + I => cs_46_OUTMUX, + CTL => cs_46_ENABLE, + O => cs(46) + ); + cs_46_ENABLEINV : X_INV + port map ( + I => cs_46_TORGTS, + O => cs_46_ENABLE + ); + cs_46_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_46_TORGTS + ); + cs_46_OUTMUX_487 : X_BUF + port map ( + I => cs_46_OBUF, + O => cs_46_OUTMUX + ); + cs_54_OBUF_488 : X_TRI + port map ( + I => cs_54_OUTMUX, + CTL => cs_54_ENABLE, + O => cs(54) + ); + cs_54_ENABLEINV : X_INV + port map ( + I => cs_54_TORGTS, + O => cs_54_ENABLE + ); + cs_54_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_54_TORGTS + ); + cs_54_OUTMUX_489 : X_BUF + port map ( + I => cs_54_OBUF, + O => cs_54_OUTMUX + ); + cs_62_OBUF_490 : X_TRI + port map ( + I => cs_62_OUTMUX, + CTL => cs_62_ENABLE, + O => cs(62) + ); + cs_62_ENABLEINV : X_INV + port map ( + I => cs_62_TORGTS, + O => cs_62_ENABLE + ); + cs_62_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_62_TORGTS + ); + cs_62_OUTMUX_491 : X_BUF + port map ( + I => cs_62_OBUF, + O => cs_62_OUTMUX + ); + cs_70_OBUF_492 : X_TRI + port map ( + I => cs_70_OUTMUX, + CTL => cs_70_ENABLE, + O => cs(70) + ); + cs_70_ENABLEINV : X_INV + port map ( + I => cs_70_TORGTS, + O => cs_70_ENABLE + ); + cs_70_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_70_TORGTS + ); + cs_70_OUTMUX_493 : X_BUF + port map ( + I => cs_70_OBUF, + O => cs_70_OUTMUX + ); + cs_39_OBUF_494 : X_TRI + port map ( + I => cs_39_OUTMUX, + CTL => cs_39_ENABLE, + O => cs(39) + ); + cs_39_ENABLEINV : X_INV + port map ( + I => cs_39_TORGTS, + O => cs_39_ENABLE + ); + cs_39_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_39_TORGTS + ); + cs_39_OUTMUX_495 : X_BUF + port map ( + I => cs_39_OBUF, + O => cs_39_OUTMUX + ); + cs_47_OBUF_496 : X_TRI + port map ( + I => cs_47_OUTMUX, + CTL => cs_47_ENABLE, + O => cs(47) + ); + cs_47_ENABLEINV : X_INV + port map ( + I => cs_47_TORGTS, + O => cs_47_ENABLE + ); + cs_47_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_47_TORGTS + ); + cs_47_OUTMUX_497 : X_BUF + port map ( + I => cs_47_OBUF, + O => cs_47_OUTMUX + ); + cs_55_OBUF_498 : X_TRI + port map ( + I => cs_55_OUTMUX, + CTL => cs_55_ENABLE, + O => cs(55) + ); + cs_55_ENABLEINV : X_INV + port map ( + I => cs_55_TORGTS, + O => cs_55_ENABLE + ); + cs_55_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_55_TORGTS + ); + cs_55_OUTMUX_499 : X_BUF + port map ( + I => cs_55_OBUF, + O => cs_55_OUTMUX + ); + cs_63_OBUF_500 : X_TRI + port map ( + I => cs_63_OUTMUX, + CTL => cs_63_ENABLE, + O => cs(63) + ); + cs_63_ENABLEINV : X_INV + port map ( + I => cs_63_TORGTS, + O => cs_63_ENABLE + ); + cs_63_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_63_TORGTS + ); + cs_63_OUTMUX_501 : X_BUF + port map ( + I => cs_63_OBUF, + O => cs_63_OUTMUX + ); + cs_71_OBUF_502 : X_TRI + port map ( + I => cs_71_OUTMUX, + CTL => cs_71_ENABLE, + O => cs(71) + ); + cs_71_ENABLEINV : X_INV + port map ( + I => cs_71_TORGTS, + O => cs_71_ENABLE + ); + cs_71_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_71_TORGTS + ); + cs_71_OUTMUX_503 : X_BUF + port map ( + I => cs_71_OBUF, + O => cs_71_OUTMUX + ); + cs_48_OBUF_504 : X_TRI + port map ( + I => cs_48_OUTMUX, + CTL => cs_48_ENABLE, + O => cs(48) + ); + cs_48_ENABLEINV : X_INV + port map ( + I => cs_48_TORGTS, + O => cs_48_ENABLE + ); + cs_48_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_48_TORGTS + ); + cs_48_OUTMUX_505 : X_BUF + port map ( + I => cs_48_OBUF, + O => cs_48_OUTMUX + ); + cs_56_OBUF_506 : X_TRI + port map ( + I => cs_56_OUTMUX, + CTL => cs_56_ENABLE, + O => cs(56) + ); + cs_56_ENABLEINV : X_INV + port map ( + I => cs_56_TORGTS, + O => cs_56_ENABLE + ); + cs_56_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_56_TORGTS + ); + cs_56_OUTMUX_507 : X_BUF + port map ( + I => cs_56_OBUF, + O => cs_56_OUTMUX + ); + cs_64_OBUF_508 : X_TRI + port map ( + I => cs_64_OUTMUX, + CTL => cs_64_ENABLE, + O => cs(64) + ); + cs_64_ENABLEINV : X_INV + port map ( + I => cs_64_TORGTS, + O => cs_64_ENABLE + ); + cs_64_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_64_TORGTS + ); + cs_64_OUTMUX_509 : X_BUF + port map ( + I => cs_64_OBUF, + O => cs_64_OUTMUX + ); + cs_72_OBUF_510 : X_TRI + port map ( + I => cs_72_OUTMUX, + CTL => cs_72_ENABLE, + O => cs(72) + ); + cs_72_ENABLEINV : X_INV + port map ( + I => cs_72_TORGTS, + O => cs_72_ENABLE + ); + cs_72_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_72_TORGTS + ); + cs_72_OUTMUX_511 : X_BUF + port map ( + I => cs_72_OBUF, + O => cs_72_OUTMUX + ); + cs_80_OBUF_512 : X_TRI + port map ( + I => cs_80_OUTMUX, + CTL => cs_80_ENABLE, + O => cs(80) + ); + cs_80_ENABLEINV : X_INV + port map ( + I => cs_80_TORGTS, + O => cs_80_ENABLE + ); + cs_80_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_80_TORGTS + ); + cs_80_OUTMUX_513 : X_BUF + port map ( + I => cs_80_OBUF, + O => cs_80_OUTMUX + ); + cs_49_OBUF_514 : X_TRI + port map ( + I => cs_49_OUTMUX, + CTL => cs_49_ENABLE, + O => cs(49) + ); + cs_49_ENABLEINV : X_INV + port map ( + I => cs_49_TORGTS, + O => cs_49_ENABLE + ); + cs_49_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_49_TORGTS + ); + cs_49_OUTMUX_515 : X_BUF + port map ( + I => cs_49_OBUF, + O => cs_49_OUTMUX + ); + cs_57_OBUF_516 : X_TRI + port map ( + I => cs_57_OUTMUX, + CTL => cs_57_ENABLE, + O => cs(57) + ); + cs_57_ENABLEINV : X_INV + port map ( + I => cs_57_TORGTS, + O => cs_57_ENABLE + ); + cs_57_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_57_TORGTS + ); + cs_57_OUTMUX_517 : X_BUF + port map ( + I => cs_57_OBUF, + O => cs_57_OUTMUX + ); + cs_65_OBUF_518 : X_TRI + port map ( + I => cs_65_OUTMUX, + CTL => cs_65_ENABLE, + O => cs(65) + ); + cs_65_ENABLEINV : X_INV + port map ( + I => cs_65_TORGTS, + O => cs_65_ENABLE + ); + cs_65_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_65_TORGTS + ); + cs_65_OUTMUX_519 : X_BUF + port map ( + I => cs_65_OBUF, + O => cs_65_OUTMUX + ); + cs_73_OBUF_520 : X_TRI + port map ( + I => cs_73_OUTMUX, + CTL => cs_73_ENABLE, + O => cs(73) + ); + cs_73_ENABLEINV : X_INV + port map ( + I => cs_73_TORGTS, + O => cs_73_ENABLE + ); + cs_73_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_73_TORGTS + ); + cs_73_OUTMUX_521 : X_BUF + port map ( + I => cs_73_OBUF, + O => cs_73_OUTMUX + ); + cs_81_OBUF_522 : X_TRI + port map ( + I => cs_81_OUTMUX, + CTL => cs_81_ENABLE, + O => cs(81) + ); + cs_81_ENABLEINV : X_INV + port map ( + I => cs_81_TORGTS, + O => cs_81_ENABLE + ); + cs_81_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_81_TORGTS + ); + cs_81_OUTMUX_523 : X_BUF + port map ( + I => cs_81_OBUF, + O => cs_81_OUTMUX + ); + cs_58_OBUF_524 : X_TRI + port map ( + I => cs_58_OUTMUX, + CTL => cs_58_ENABLE, + O => cs(58) + ); + cs_58_ENABLEINV : X_INV + port map ( + I => cs_58_TORGTS, + O => cs_58_ENABLE + ); + cs_58_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_58_TORGTS + ); + cs_58_OUTMUX_525 : X_BUF + port map ( + I => cs_58_OBUF, + O => cs_58_OUTMUX + ); + cs_66_OBUF_526 : X_TRI + port map ( + I => cs_66_OUTMUX, + CTL => cs_66_ENABLE, + O => cs(66) + ); + cs_66_ENABLEINV : X_INV + port map ( + I => cs_66_TORGTS, + O => cs_66_ENABLE + ); + cs_66_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_66_TORGTS + ); + cs_66_OUTMUX_527 : X_BUF + port map ( + I => cs_66_OBUF, + O => cs_66_OUTMUX + ); + cs_74_OBUF_528 : X_TRI + port map ( + I => cs_74_OUTMUX, + CTL => cs_74_ENABLE, + O => cs(74) + ); + cs_74_ENABLEINV : X_INV + port map ( + I => cs_74_TORGTS, + O => cs_74_ENABLE + ); + cs_74_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_74_TORGTS + ); + cs_74_OUTMUX_529 : X_BUF + port map ( + I => cs_74_OBUF, + O => cs_74_OUTMUX + ); + cs_82_OBUF_530 : X_TRI + port map ( + I => cs_82_OUTMUX, + CTL => cs_82_ENABLE, + O => cs(82) + ); + cs_82_ENABLEINV : X_INV + port map ( + I => cs_82_TORGTS, + O => cs_82_ENABLE + ); + cs_82_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_82_TORGTS + ); + cs_82_OUTMUX_531 : X_BUF + port map ( + I => cs_82_OBUF, + O => cs_82_OUTMUX + ); + cs_90_OBUF_532 : X_TRI + port map ( + I => cs_90_OUTMUX, + CTL => cs_90_ENABLE, + O => cs(90) + ); + cs_90_ENABLEINV : X_INV + port map ( + I => cs_90_TORGTS, + O => cs_90_ENABLE + ); + cs_90_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_90_TORGTS + ); + cs_90_OUTMUX_533 : X_BUF + port map ( + I => cs_90_OBUF, + O => cs_90_OUTMUX + ); + cs_59_OBUF_534 : X_TRI + port map ( + I => cs_59_OUTMUX, + CTL => cs_59_ENABLE, + O => cs(59) + ); + cs_59_ENABLEINV : X_INV + port map ( + I => cs_59_TORGTS, + O => cs_59_ENABLE + ); + cs_59_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_59_TORGTS + ); + cs_59_OUTMUX_535 : X_BUF + port map ( + I => cs_59_OBUF, + O => cs_59_OUTMUX + ); + cs_67_OBUF_536 : X_TRI + port map ( + I => cs_67_OUTMUX, + CTL => cs_67_ENABLE, + O => cs(67) + ); + cs_67_ENABLEINV : X_INV + port map ( + I => cs_67_TORGTS, + O => cs_67_ENABLE + ); + cs_67_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_67_TORGTS + ); + cs_67_OUTMUX_537 : X_BUF + port map ( + I => cs_67_OBUF, + O => cs_67_OUTMUX + ); + cs_75_OBUF_538 : X_TRI + port map ( + I => cs_75_OUTMUX, + CTL => cs_75_ENABLE, + O => cs(75) + ); + cs_75_ENABLEINV : X_INV + port map ( + I => cs_75_TORGTS, + O => cs_75_ENABLE + ); + cs_75_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_75_TORGTS + ); + cs_75_OUTMUX_539 : X_BUF + port map ( + I => cs_75_OBUF, + O => cs_75_OUTMUX + ); + cs_83_OBUF_540 : X_TRI + port map ( + I => cs_83_OUTMUX, + CTL => cs_83_ENABLE, + O => cs(83) + ); + cs_83_ENABLEINV : X_INV + port map ( + I => cs_83_TORGTS, + O => cs_83_ENABLE + ); + cs_83_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_83_TORGTS + ); + cs_83_OUTMUX_541 : X_BUF + port map ( + I => cs_83_OBUF, + O => cs_83_OUTMUX + ); + cs_91_OBUF_542 : X_TRI + port map ( + I => cs_91_OUTMUX, + CTL => cs_91_ENABLE, + O => cs(91) + ); + cs_91_ENABLEINV : X_INV + port map ( + I => cs_91_TORGTS, + O => cs_91_ENABLE + ); + cs_91_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_91_TORGTS + ); + cs_91_OUTMUX_543 : X_BUF + port map ( + I => cs_91_OBUF, + O => cs_91_OUTMUX + ); + cs_68_OBUF_544 : X_TRI + port map ( + I => cs_68_OUTMUX, + CTL => cs_68_ENABLE, + O => cs(68) + ); + cs_68_ENABLEINV : X_INV + port map ( + I => cs_68_TORGTS, + O => cs_68_ENABLE + ); + cs_68_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_68_TORGTS + ); + cs_68_OUTMUX_545 : X_BUF + port map ( + I => cs_68_OBUF, + O => cs_68_OUTMUX + ); + cs_76_OBUF_546 : X_TRI + port map ( + I => cs_76_OUTMUX, + CTL => cs_76_ENABLE, + O => cs(76) + ); + cs_76_ENABLEINV : X_INV + port map ( + I => cs_76_TORGTS, + O => cs_76_ENABLE + ); + cs_76_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_76_TORGTS + ); + cs_76_OUTMUX_547 : X_BUF + port map ( + I => cs_76_OBUF, + O => cs_76_OUTMUX + ); + cs_84_OBUF_548 : X_TRI + port map ( + I => cs_84_OUTMUX, + CTL => cs_84_ENABLE, + O => cs(84) + ); + cs_84_ENABLEINV : X_INV + port map ( + I => cs_84_TORGTS, + O => cs_84_ENABLE + ); + cs_84_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_84_TORGTS + ); + cs_84_OUTMUX_549 : X_BUF + port map ( + I => cs_84_OBUF, + O => cs_84_OUTMUX + ); + cs_92_OBUF_550 : X_TRI + port map ( + I => cs_92_OUTMUX, + CTL => cs_92_ENABLE, + O => cs(92) + ); + cs_92_ENABLEINV : X_INV + port map ( + I => cs_92_TORGTS, + O => cs_92_ENABLE + ); + cs_92_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_92_TORGTS + ); + cs_92_OUTMUX_551 : X_BUF + port map ( + I => cs_92_OBUF, + O => cs_92_OUTMUX + ); + cs_69_OBUF_552 : X_TRI + port map ( + I => cs_69_OUTMUX, + CTL => cs_69_ENABLE, + O => cs(69) + ); + cs_69_ENABLEINV : X_INV + port map ( + I => cs_69_TORGTS, + O => cs_69_ENABLE + ); + cs_69_GTS_OR : X_BUF + port map ( + I => GTS, + O => cs_69_TORGTS + ); + cs_69_OUTMUX_553 : X_BUF + port map ( + I => cs_69_OBUF, + O => cs_69_OUTMUX + ); + NlwBlock_decodisa_VCC : X_ONE + port map ( + O => VCC + ); + NlwBlockROC : X_ROC + generic map (ROC_WIDTH => 100 ns) + port map (O => GSR); + NlwBlockTOC : X_TOC + port map (O => GTS); + +end Structure; + diff --git a/2004/n/fpga/src/decodisa/decodisa_translate.vhd b/2004/n/fpga/src/decodisa/decodisa_translate.vhd new file mode 100644 index 0000000..095f62b --- /dev/null +++ b/2004/n/fpga/src/decodisa/decodisa_translate.vhd @@ -0,0 +1,14082 @@ +-- Xilinx Vhdl netlist produced by netgen application (version G.26) +-- Command : -intstyle ise -rpw 100 -tpw 0 -ar Structure -xon true -w -ofmt vhdl -sim decodisa.ngd decodisa_translate.vhd +-- Input file : decodisa.ngd +-- Output file : decodisa_translate.vhd +-- Design name : decodisa +-- # of Entities : 1 +-- Xilinx : D:/xilinx +-- Device : 2s200fg456-6 + +-- This vhdl netlist is a simulation model and uses simulation +-- primitives which may not represent the true implementation of the +-- device, however the netlist is functionally correct and should not +-- be modified. This file cannot be synthesized and should only be used +-- with supported simulation tools. + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library SIMPRIM; +use SIMPRIM.VCOMPONENTS.ALL; +use SIMPRIM.VPACKAGE.ALL; + +entity decodisa is + port ( + AEN : in STD_LOGIC := 'X'; + IOR : in STD_LOGIC := 'X'; + IOW : in STD_LOGIC := 'X'; + clk : out STD_LOGIC; + rw : out STD_LOGIC; + adr_bus : in STD_LOGIC_VECTOR ( 23 downto 0 ); + cs : out STD_LOGIC_VECTOR ( 255 downto 0 ) + ); +end decodisa; + +architecture Structure of decodisa is + signal clk_OBUF : STD_LOGIC; + signal adr_bus_11_IBUF : STD_LOGIC; + signal rw_OBUF : STD_LOGIC; + signal adr_bus_10_IBUF : STD_LOGIC; + signal AEN_IBUF : STD_LOGIC; + signal IOR_IBUF : STD_LOGIC; + signal IOW_IBUF : STD_LOGIC; + signal adr_bus_9_IBUF : STD_LOGIC; + signal cs_0_OBUF : STD_LOGIC; + signal adr_bus_14_IBUF : STD_LOGIC; + signal adr_bus_15_IBUF : STD_LOGIC; + signal adr_bus_6_IBUF : STD_LOGIC; + signal adr_bus_0_IBUF : STD_LOGIC; + signal adr_bus_8_IBUF : STD_LOGIC; + signal cs_2_OBUF : STD_LOGIC; + signal adr_bus_7_IBUF : STD_LOGIC; + signal cs_1_OBUF : STD_LOGIC; + signal adr_bus_3_IBUF : STD_LOGIC; + signal adr_bus_4_IBUF : STD_LOGIC; + signal adr_bus_2_IBUF : STD_LOGIC; + signal adr_bus_5_IBUF : STD_LOGIC; + signal adr_bus_1_IBUF : STD_LOGIC; + signal adr_bus_13_IBUF : STD_LOGIC; + signal adr_bus_12_IBUF : STD_LOGIC; + signal reg_select : STD_LOGIC; + signal cs_3_OBUF : STD_LOGIC; + signal cs_255_OBUF : STD_LOGIC; + signal cs_254_OBUF : STD_LOGIC; + signal cs_253_OBUF : STD_LOGIC; + signal cs_252_OBUF : STD_LOGIC; + signal cs_251_OBUF : STD_LOGIC; + signal cs_250_OBUF : STD_LOGIC; + signal cs_249_OBUF : STD_LOGIC; + signal cs_248_OBUF : STD_LOGIC; + signal cs_247_OBUF : STD_LOGIC; + signal cs_246_OBUF : STD_LOGIC; + signal cs_245_OBUF : STD_LOGIC; + signal cs_244_OBUF : STD_LOGIC; + signal cs_243_OBUF : STD_LOGIC; + signal cs_242_OBUF : STD_LOGIC; + signal cs_241_OBUF : STD_LOGIC; + signal cs_240_OBUF : STD_LOGIC; + signal cs_239_OBUF : STD_LOGIC; + signal cs_238_OBUF : STD_LOGIC; + signal cs_237_OBUF : STD_LOGIC; + signal cs_236_OBUF : STD_LOGIC; + signal cs_235_OBUF : STD_LOGIC; + signal cs_234_OBUF : STD_LOGIC; + signal cs_233_OBUF : STD_LOGIC; + signal cs_232_OBUF : STD_LOGIC; + signal cs_231_OBUF : STD_LOGIC; + signal cs_230_OBUF : STD_LOGIC; + signal cs_229_OBUF : STD_LOGIC; + signal cs_228_OBUF : STD_LOGIC; + signal cs_227_OBUF : STD_LOGIC; + signal cs_226_OBUF : STD_LOGIC; + signal cs_225_OBUF : STD_LOGIC; + signal cs_224_OBUF : STD_LOGIC; + signal cs_223_OBUF : STD_LOGIC; + signal cs_222_OBUF : STD_LOGIC; + signal cs_221_OBUF : STD_LOGIC; + signal cs_220_OBUF : STD_LOGIC; + signal cs_219_OBUF : STD_LOGIC; + signal cs_218_OBUF : STD_LOGIC; + signal cs_217_OBUF : STD_LOGIC; + signal cs_216_OBUF : STD_LOGIC; + signal cs_215_OBUF : STD_LOGIC; + signal cs_214_OBUF : STD_LOGIC; + signal cs_213_OBUF : STD_LOGIC; + signal cs_212_OBUF : STD_LOGIC; + signal cs_211_OBUF : STD_LOGIC; + signal cs_210_OBUF : STD_LOGIC; + signal cs_209_OBUF : STD_LOGIC; + signal cs_208_OBUF : STD_LOGIC; + signal cs_207_OBUF : STD_LOGIC; + signal cs_206_OBUF : STD_LOGIC; + signal cs_205_OBUF : STD_LOGIC; + signal cs_204_OBUF : STD_LOGIC; + signal cs_203_OBUF : STD_LOGIC; + signal cs_202_OBUF : STD_LOGIC; + signal cs_201_OBUF : STD_LOGIC; + signal cs_200_OBUF : STD_LOGIC; + signal cs_199_OBUF : STD_LOGIC; + signal cs_198_OBUF : STD_LOGIC; + signal cs_197_OBUF : STD_LOGIC; + signal cs_196_OBUF : STD_LOGIC; + signal cs_195_OBUF : STD_LOGIC; + signal cs_194_OBUF : STD_LOGIC; + signal cs_193_OBUF : STD_LOGIC; + signal cs_192_OBUF : STD_LOGIC; + signal cs_191_OBUF : STD_LOGIC; + signal cs_190_OBUF : STD_LOGIC; + signal cs_189_OBUF : STD_LOGIC; + signal cs_188_OBUF : STD_LOGIC; + signal cs_187_OBUF : STD_LOGIC; + signal cs_186_OBUF : STD_LOGIC; + signal cs_185_OBUF : STD_LOGIC; + signal cs_184_OBUF : STD_LOGIC; + signal cs_183_OBUF : STD_LOGIC; + signal cs_182_OBUF : STD_LOGIC; + signal cs_181_OBUF : STD_LOGIC; + signal cs_180_OBUF : STD_LOGIC; + signal cs_179_OBUF : STD_LOGIC; + signal cs_178_OBUF : STD_LOGIC; + signal cs_177_OBUF : STD_LOGIC; + signal cs_176_OBUF : STD_LOGIC; + signal cs_175_OBUF : STD_LOGIC; + signal cs_174_OBUF : STD_LOGIC; + signal cs_173_OBUF : STD_LOGIC; + signal cs_172_OBUF : STD_LOGIC; + signal cs_171_OBUF : STD_LOGIC; + signal cs_170_OBUF : STD_LOGIC; + signal cs_169_OBUF : STD_LOGIC; + signal cs_168_OBUF : STD_LOGIC; + signal cs_167_OBUF : STD_LOGIC; + signal cs_166_OBUF : STD_LOGIC; + signal cs_165_OBUF : STD_LOGIC; + signal cs_164_OBUF : STD_LOGIC; + signal cs_163_OBUF : STD_LOGIC; + signal cs_162_OBUF : STD_LOGIC; + signal cs_161_OBUF : STD_LOGIC; + signal cs_160_OBUF : STD_LOGIC; + signal cs_159_OBUF : STD_LOGIC; + signal cs_158_OBUF : STD_LOGIC; + signal cs_157_OBUF : STD_LOGIC; + signal cs_156_OBUF : STD_LOGIC; + signal cs_155_OBUF : STD_LOGIC; + signal cs_154_OBUF : STD_LOGIC; + signal cs_153_OBUF : STD_LOGIC; + signal cs_152_OBUF : STD_LOGIC; + signal cs_151_OBUF : STD_LOGIC; + signal cs_150_OBUF : STD_LOGIC; + signal cs_149_OBUF : STD_LOGIC; + signal cs_148_OBUF : STD_LOGIC; + signal cs_147_OBUF : STD_LOGIC; + signal cs_146_OBUF : STD_LOGIC; + signal cs_145_OBUF : STD_LOGIC; + signal cs_144_OBUF : STD_LOGIC; + signal cs_143_OBUF : STD_LOGIC; + signal cs_142_OBUF : STD_LOGIC; + signal cs_141_OBUF : STD_LOGIC; + signal cs_140_OBUF : STD_LOGIC; + signal cs_139_OBUF : STD_LOGIC; + signal cs_138_OBUF : STD_LOGIC; + signal cs_137_OBUF : STD_LOGIC; + signal cs_136_OBUF : STD_LOGIC; + signal cs_135_OBUF : STD_LOGIC; + signal cs_134_OBUF : STD_LOGIC; + signal cs_133_OBUF : STD_LOGIC; + signal cs_132_OBUF : STD_LOGIC; + signal cs_131_OBUF : STD_LOGIC; + signal cs_130_OBUF : STD_LOGIC; + signal cs_129_OBUF : STD_LOGIC; + signal cs_128_OBUF : STD_LOGIC; + signal cs_127_OBUF : STD_LOGIC; + signal cs_126_OBUF : STD_LOGIC; + signal cs_125_OBUF : STD_LOGIC; + signal cs_124_OBUF : STD_LOGIC; + signal cs_123_OBUF : STD_LOGIC; + signal cs_122_OBUF : STD_LOGIC; + signal cs_121_OBUF : STD_LOGIC; + signal cs_120_OBUF : STD_LOGIC; + signal cs_119_OBUF : STD_LOGIC; + signal cs_118_OBUF : STD_LOGIC; + signal cs_117_OBUF : STD_LOGIC; + signal cs_116_OBUF : STD_LOGIC; + signal cs_115_OBUF : STD_LOGIC; + signal cs_114_OBUF : STD_LOGIC; + signal cs_113_OBUF : STD_LOGIC; + signal cs_112_OBUF : STD_LOGIC; + signal cs_111_OBUF : STD_LOGIC; + signal cs_110_OBUF : STD_LOGIC; + signal cs_109_OBUF : STD_LOGIC; + signal cs_108_OBUF : STD_LOGIC; + signal cs_107_OBUF : STD_LOGIC; + signal cs_106_OBUF : STD_LOGIC; + signal cs_105_OBUF : STD_LOGIC; + signal cs_104_OBUF : STD_LOGIC; + signal cs_103_OBUF : STD_LOGIC; + signal cs_102_OBUF : STD_LOGIC; + signal cs_101_OBUF : STD_LOGIC; + signal cs_100_OBUF : STD_LOGIC; + signal cs_99_OBUF : STD_LOGIC; + signal cs_98_OBUF : STD_LOGIC; + signal cs_97_OBUF : STD_LOGIC; + signal cs_96_OBUF : STD_LOGIC; + signal cs_95_OBUF : STD_LOGIC; + signal cs_94_OBUF : STD_LOGIC; + signal cs_93_OBUF : STD_LOGIC; + signal cs_92_OBUF : STD_LOGIC; + signal cs_91_OBUF : STD_LOGIC; + signal cs_90_OBUF : STD_LOGIC; + signal cs_89_OBUF : STD_LOGIC; + signal cs_88_OBUF : STD_LOGIC; + signal cs_87_OBUF : STD_LOGIC; + signal cs_86_OBUF : STD_LOGIC; + signal cs_85_OBUF : STD_LOGIC; + signal cs_84_OBUF : STD_LOGIC; + signal cs_83_OBUF : STD_LOGIC; + signal cs_82_OBUF : STD_LOGIC; + signal cs_81_OBUF : STD_LOGIC; + signal cs_80_OBUF : STD_LOGIC; + signal cs_79_OBUF : STD_LOGIC; + signal cs_78_OBUF : STD_LOGIC; + signal cs_77_OBUF : STD_LOGIC; + signal cs_76_OBUF : STD_LOGIC; + signal cs_75_OBUF : STD_LOGIC; + signal cs_74_OBUF : STD_LOGIC; + signal cs_73_OBUF : STD_LOGIC; + signal cs_72_OBUF : STD_LOGIC; + signal cs_71_OBUF : STD_LOGIC; + signal cs_70_OBUF : STD_LOGIC; + signal cs_69_OBUF : STD_LOGIC; + signal cs_68_OBUF : STD_LOGIC; + signal cs_67_OBUF : STD_LOGIC; + signal cs_66_OBUF : STD_LOGIC; + signal cs_65_OBUF : STD_LOGIC; + signal cs_64_OBUF : STD_LOGIC; + signal cs_63_OBUF : STD_LOGIC; + signal cs_62_OBUF : STD_LOGIC; + signal cs_61_OBUF : STD_LOGIC; + signal cs_60_OBUF : STD_LOGIC; + signal cs_59_OBUF : STD_LOGIC; + signal cs_58_OBUF : STD_LOGIC; + signal cs_57_OBUF : STD_LOGIC; + signal cs_56_OBUF : STD_LOGIC; + signal cs_55_OBUF : STD_LOGIC; + signal cs_54_OBUF : STD_LOGIC; + signal cs_53_OBUF : STD_LOGIC; + signal cs_52_OBUF : STD_LOGIC; + signal cs_51_OBUF : STD_LOGIC; + signal cs_50_OBUF : STD_LOGIC; + signal cs_49_OBUF : STD_LOGIC; + signal cs_48_OBUF : STD_LOGIC; + signal cs_47_OBUF : STD_LOGIC; + signal cs_46_OBUF : STD_LOGIC; + signal cs_45_OBUF : STD_LOGIC; + signal cs_44_OBUF : STD_LOGIC; + signal cs_43_OBUF : STD_LOGIC; + signal cs_42_OBUF : STD_LOGIC; + signal cs_41_OBUF : STD_LOGIC; + signal cs_40_OBUF : STD_LOGIC; + signal cs_39_OBUF : STD_LOGIC; + signal cs_38_OBUF : STD_LOGIC; + signal cs_37_OBUF : STD_LOGIC; + signal cs_36_OBUF : STD_LOGIC; + signal cs_35_OBUF : STD_LOGIC; + signal cs_34_OBUF : STD_LOGIC; + signal cs_33_OBUF : STD_LOGIC; + signal cs_32_OBUF : STD_LOGIC; + signal cs_31_OBUF : STD_LOGIC; + signal cs_30_OBUF : STD_LOGIC; + signal cs_29_OBUF : STD_LOGIC; + signal cs_28_OBUF : STD_LOGIC; + signal cs_27_OBUF : STD_LOGIC; + signal cs_26_OBUF : STD_LOGIC; + signal cs_25_OBUF : STD_LOGIC; + signal cs_24_OBUF : STD_LOGIC; + signal cs_23_OBUF : STD_LOGIC; + signal cs_22_OBUF : STD_LOGIC; + signal cs_21_OBUF : STD_LOGIC; + signal cs_20_OBUF : STD_LOGIC; + signal cs_19_OBUF : STD_LOGIC; + signal cs_18_OBUF : STD_LOGIC; + signal cs_17_OBUF : STD_LOGIC; + signal cs_16_OBUF : STD_LOGIC; + signal cs_15_OBUF : STD_LOGIC; + signal cs_14_OBUF : STD_LOGIC; + signal cs_13_OBUF : STD_LOGIC; + signal cs_12_OBUF : STD_LOGIC; + signal cs_11_OBUF : STD_LOGIC; + signal cs_10_OBUF : STD_LOGIC; + signal cs_9_OBUF : STD_LOGIC; + signal cs_8_OBUF : STD_LOGIC; + signal cs_7_OBUF : STD_LOGIC; + signal cs_6_OBUF : STD_LOGIC; + signal cs_5_OBUF : STD_LOGIC; + signal cs_4_OBUF : STD_LOGIC; + signal N5267 : STD_LOGIC; + signal CHOICE45 : STD_LOGIC; + signal dadrL_N18685 : STD_LOGIC; + signal dadrL_N18684 : STD_LOGIC; + signal dadrL_N18614 : STD_LOGIC; + signal dadrL_N18613 : STD_LOGIC; + signal dadrL_N18543 : STD_LOGIC; + signal dadrL_N18542 : STD_LOGIC; + signal dadrL_N18472 : STD_LOGIC; + signal dadrL_N18471 : STD_LOGIC; + signal dadrL_N18401 : STD_LOGIC; + signal dadrL_N18400 : STD_LOGIC; + signal dadrL_N18330 : STD_LOGIC; + signal dadrL_N18329 : STD_LOGIC; + signal dadrL_N18259 : STD_LOGIC; + signal dadrL_N18258 : STD_LOGIC; + signal dadrL_N18188 : STD_LOGIC; + signal dadrL_N18187 : STD_LOGIC; + signal dadrL_N18117 : STD_LOGIC; + signal dadrL_N18116 : STD_LOGIC; + signal dadrL_N18046 : STD_LOGIC; + signal dadrL_N18045 : STD_LOGIC; + signal dadrL_N17975 : STD_LOGIC; + signal dadrL_N17974 : STD_LOGIC; + signal dadrL_N17904 : STD_LOGIC; + signal dadrL_N17903 : STD_LOGIC; + signal dadrL_N17833 : STD_LOGIC; + signal dadrL_N17832 : STD_LOGIC; + signal dadrL_N17762 : STD_LOGIC; + signal dadrL_N17761 : STD_LOGIC; + signal dadrL_N17691 : STD_LOGIC; + signal dadrL_N17690 : STD_LOGIC; + signal dadrL_N17620 : STD_LOGIC; + signal dadrL_N17619 : STD_LOGIC; + signal dadrL_N17549 : STD_LOGIC; + signal dadrL_N17548 : STD_LOGIC; + signal dadrL_N17478 : STD_LOGIC; + signal dadrL_N17477 : STD_LOGIC; + signal dadrL_N17407 : STD_LOGIC; + signal dadrL_N17406 : STD_LOGIC; + signal dadrL_N17336 : STD_LOGIC; + signal dadrL_N17335 : STD_LOGIC; + signal dadrL_N17265 : STD_LOGIC; + signal dadrL_N17264 : STD_LOGIC; + signal dadrL_N17194 : STD_LOGIC; + signal dadrL_N17193 : STD_LOGIC; + signal dadrL_N17123 : STD_LOGIC; + signal dadrL_N17122 : STD_LOGIC; + signal dadrL_N17052 : STD_LOGIC; + signal dadrL_N17051 : STD_LOGIC; + signal dadrL_N16981 : STD_LOGIC; + signal dadrL_N16980 : STD_LOGIC; + signal dadrL_N16910 : STD_LOGIC; + signal dadrL_N16909 : STD_LOGIC; + signal dadrL_N16839 : STD_LOGIC; + signal dadrL_N16838 : STD_LOGIC; + signal dadrL_N16768 : STD_LOGIC; + signal dadrL_N16767 : STD_LOGIC; + signal dadrL_N16697 : STD_LOGIC; + signal dadrL_N16696 : STD_LOGIC; + signal dadrL_N16626 : STD_LOGIC; + signal dadrL_N16625 : STD_LOGIC; + signal dadrL_N16555 : STD_LOGIC; + signal dadrL_N16554 : STD_LOGIC; + signal dadrL_N16484 : STD_LOGIC; + signal dadrL_N16483 : STD_LOGIC; + signal dadrL_N16413 : STD_LOGIC; + signal dadrL_N16412 : STD_LOGIC; + signal dadrL_N16342 : STD_LOGIC; + signal dadrL_N16341 : STD_LOGIC; + signal dadrL_N16271 : STD_LOGIC; + signal dadrL_N16270 : STD_LOGIC; + signal dadrL_N16200 : STD_LOGIC; + signal dadrL_N16199 : STD_LOGIC; + signal dadrL_N16129 : STD_LOGIC; + signal dadrL_N16128 : STD_LOGIC; + signal dadrL_N16058 : STD_LOGIC; + signal dadrL_N16057 : STD_LOGIC; + signal dadrL_N15987 : STD_LOGIC; + signal dadrL_N15986 : STD_LOGIC; + signal dadrL_N15916 : STD_LOGIC; + signal dadrL_N15915 : STD_LOGIC; + signal dadrL_N15845 : STD_LOGIC; + signal dadrL_N15844 : STD_LOGIC; + signal dadrL_N15774 : STD_LOGIC; + signal dadrL_N15773 : STD_LOGIC; + signal dadrL_N15703 : STD_LOGIC; + signal dadrL_N15702 : STD_LOGIC; + signal dadrL_N15632 : STD_LOGIC; + signal dadrL_N15631 : STD_LOGIC; + signal dadrL_N15561 : STD_LOGIC; + signal dadrL_N15560 : STD_LOGIC; + signal dadrL_N15490 : STD_LOGIC; + signal dadrL_N15489 : STD_LOGIC; + signal dadrL_N15419 : STD_LOGIC; + signal dadrL_N15418 : STD_LOGIC; + signal dadrL_N15348 : STD_LOGIC; + signal dadrL_N15347 : STD_LOGIC; + signal dadrL_N15277 : STD_LOGIC; + signal dadrL_N15276 : STD_LOGIC; + signal dadrL_N15206 : STD_LOGIC; + signal dadrL_N15205 : STD_LOGIC; + signal dadrL_N15135 : STD_LOGIC; + signal dadrL_N15134 : STD_LOGIC; + signal dadrL_N15064 : STD_LOGIC; + signal dadrL_N15063 : STD_LOGIC; + signal dadrL_N14993 : STD_LOGIC; + signal dadrL_N14992 : STD_LOGIC; + signal dadrL_N14922 : STD_LOGIC; + signal dadrL_N14921 : STD_LOGIC; + signal dadrL_N14851 : STD_LOGIC; + signal dadrL_N14850 : STD_LOGIC; + signal dadrL_N14780 : STD_LOGIC; + signal dadrL_N14779 : STD_LOGIC; + signal dadrL_N14709 : STD_LOGIC; + signal dadrL_N14708 : STD_LOGIC; + signal dadrL_N14638 : STD_LOGIC; + signal dadrL_N14637 : STD_LOGIC; + signal dadrL_N14567 : STD_LOGIC; + signal dadrL_N14566 : STD_LOGIC; + signal dadrL_N14496 : STD_LOGIC; + signal dadrL_N14495 : STD_LOGIC; + signal dadrL_N14425 : STD_LOGIC; + signal dadrL_N14424 : STD_LOGIC; + signal dadrL_N14354 : STD_LOGIC; + signal dadrL_N14353 : STD_LOGIC; + signal dadrL_N14283 : STD_LOGIC; + signal dadrL_N14282 : STD_LOGIC; + signal dadrL_N14212 : STD_LOGIC; + signal dadrL_N14211 : STD_LOGIC; + signal dadrL_N14141 : STD_LOGIC; + signal dadrL_N14140 : STD_LOGIC; + signal dadrL_N14070 : STD_LOGIC; + signal dadrL_N14069 : STD_LOGIC; + signal dadrL_N13999 : STD_LOGIC; + signal dadrL_N13998 : STD_LOGIC; + signal dadrL_N13928 : STD_LOGIC; + signal dadrL_N13927 : STD_LOGIC; + signal dadrL_N13857 : STD_LOGIC; + signal dadrL_N13856 : STD_LOGIC; + signal dadrL_N13786 : STD_LOGIC; + signal dadrL_N13785 : STD_LOGIC; + signal dadrL_N13715 : STD_LOGIC; + signal dadrL_N13714 : STD_LOGIC; + signal dadrL_N13644 : STD_LOGIC; + signal dadrL_N13643 : STD_LOGIC; + signal dadrL_N13573 : STD_LOGIC; + signal dadrL_N13572 : STD_LOGIC; + signal dadrL_N13502 : STD_LOGIC; + signal dadrL_N13501 : STD_LOGIC; + signal dadrL_N13431 : STD_LOGIC; + signal dadrL_N13430 : STD_LOGIC; + signal dadrL_N13360 : STD_LOGIC; + signal dadrL_N13359 : STD_LOGIC; + signal dadrL_N13289 : STD_LOGIC; + signal dadrL_N13288 : STD_LOGIC; + signal dadrL_N13218 : STD_LOGIC; + signal dadrL_N13217 : STD_LOGIC; + signal dadrL_N13147 : STD_LOGIC; + signal dadrL_N13146 : STD_LOGIC; + signal dadrL_N13076 : STD_LOGIC; + signal dadrL_N13075 : STD_LOGIC; + signal dadrL_N13005 : STD_LOGIC; + signal dadrL_N13004 : STD_LOGIC; + signal dadrL_N12934 : STD_LOGIC; + signal dadrL_N12933 : STD_LOGIC; + signal dadrL_N12863 : STD_LOGIC; + signal dadrL_N12862 : STD_LOGIC; + signal dadrL_N12792 : STD_LOGIC; + signal dadrL_N12791 : STD_LOGIC; + signal dadrL_N12721 : STD_LOGIC; + signal dadrL_N12720 : STD_LOGIC; + signal dadrL_N12650 : STD_LOGIC; + signal dadrL_N12649 : STD_LOGIC; + signal dadrL_N12579 : STD_LOGIC; + signal dadrL_N12578 : STD_LOGIC; + signal dadrL_N12508 : STD_LOGIC; + signal dadrL_N12507 : STD_LOGIC; + signal dadrL_N12437 : STD_LOGIC; + signal dadrL_N12436 : STD_LOGIC; + signal dadrL_N12366 : STD_LOGIC; + signal dadrL_N12365 : STD_LOGIC; + signal dadrL_N12295 : STD_LOGIC; + signal dadrL_N12294 : STD_LOGIC; + signal dadrL_N12224 : STD_LOGIC; + signal dadrL_N12223 : STD_LOGIC; + signal dadrL_N12153 : STD_LOGIC; + signal dadrL_N12152 : STD_LOGIC; + signal dadrL_N12082 : STD_LOGIC; + signal dadrL_N12081 : STD_LOGIC; + signal dadrL_N12011 : STD_LOGIC; + signal dadrL_N12010 : STD_LOGIC; + signal dadrL_N11940 : STD_LOGIC; + signal dadrL_N11939 : STD_LOGIC; + signal dadrL_N11869 : STD_LOGIC; + signal dadrL_N11868 : STD_LOGIC; + signal dadrL_N11798 : STD_LOGIC; + signal dadrL_N11797 : STD_LOGIC; + signal dadrL_N11727 : STD_LOGIC; + signal dadrL_N11726 : STD_LOGIC; + signal dadrL_N11656 : STD_LOGIC; + signal dadrL_N11655 : STD_LOGIC; + signal dadrL_N11585 : STD_LOGIC; + signal dadrL_N11584 : STD_LOGIC; + signal dadrL_N11514 : STD_LOGIC; + signal dadrL_N11513 : STD_LOGIC; + signal dadrL_N11443 : STD_LOGIC; + signal dadrL_N11442 : STD_LOGIC; + signal dadrL_N11372 : STD_LOGIC; + signal dadrL_N11371 : STD_LOGIC; + signal dadrL_N11301 : STD_LOGIC; + signal dadrL_N11300 : STD_LOGIC; + signal dadrL_N11230 : STD_LOGIC; + signal dadrL_N11229 : STD_LOGIC; + signal dadrL_N11159 : STD_LOGIC; + signal dadrL_N11158 : STD_LOGIC; + signal dadrL_N11088 : STD_LOGIC; + signal dadrL_N11087 : STD_LOGIC; + signal dadrL_N11017 : STD_LOGIC; + signal dadrL_N11016 : STD_LOGIC; + signal dadrL_N10946 : STD_LOGIC; + signal dadrL_N10945 : STD_LOGIC; + signal dadrL_N10875 : STD_LOGIC; + signal dadrL_N10874 : STD_LOGIC; + signal dadrL_N10804 : STD_LOGIC; + signal dadrL_N10803 : STD_LOGIC; + signal dadrL_N10733 : STD_LOGIC; + signal dadrL_N10732 : STD_LOGIC; + signal dadrL_N10662 : STD_LOGIC; + signal dadrL_N10661 : STD_LOGIC; + signal dadrL_N10591 : STD_LOGIC; + signal dadrL_N10590 : STD_LOGIC; + signal dadrL_N10520 : STD_LOGIC; + signal dadrL_N10519 : STD_LOGIC; + signal dadrL_N10449 : STD_LOGIC; + signal dadrL_N10448 : STD_LOGIC; + signal dadrL_N10378 : STD_LOGIC; + signal dadrL_N10377 : STD_LOGIC; + signal dadrL_N10307 : STD_LOGIC; + signal dadrL_N10306 : STD_LOGIC; + signal dadrL_N10236 : STD_LOGIC; + signal dadrL_N10235 : STD_LOGIC; + signal dadrL_N10165 : STD_LOGIC; + signal dadrL_N10164 : STD_LOGIC; + signal dadrL_N10094 : STD_LOGIC; + signal dadrL_N10093 : STD_LOGIC; + signal dadrL_N10023 : STD_LOGIC; + signal dadrL_N10022 : STD_LOGIC; + signal dadrL_N9952 : STD_LOGIC; + signal dadrL_N9951 : STD_LOGIC; + signal dadrL_N9881 : STD_LOGIC; + signal dadrL_N9880 : STD_LOGIC; + signal dadrL_N9810 : STD_LOGIC; + signal dadrL_N9809 : STD_LOGIC; + signal dadrL_N9739 : STD_LOGIC; + signal dadrL_N9738 : STD_LOGIC; + signal dadrL_N9668 : STD_LOGIC; + signal dadrL_N9667 : STD_LOGIC; + signal dadrL_N9597 : STD_LOGIC; + signal dadrL_N9596 : STD_LOGIC; + signal dadrL_N9526 : STD_LOGIC; + signal dadrL_N9525 : STD_LOGIC; + signal dadrL_N9455 : STD_LOGIC; + signal dadrL_N9454 : STD_LOGIC; + signal dadrL_N9384 : STD_LOGIC; + signal dadrL_N9383 : STD_LOGIC; + signal dadrL_N9313 : STD_LOGIC; + signal dadrL_N9312 : STD_LOGIC; + signal dadrL_N9242 : STD_LOGIC; + signal dadrL_N9241 : STD_LOGIC; + signal dadrL_N9171 : STD_LOGIC; + signal dadrL_N9170 : STD_LOGIC; + signal dadrL_N9100 : STD_LOGIC; + signal dadrL_N9099 : STD_LOGIC; + signal dadrL_N9029 : STD_LOGIC; + signal dadrL_N9028 : STD_LOGIC; + signal dadrL_N8958 : STD_LOGIC; + signal dadrL_N8957 : STD_LOGIC; + signal dadrL_N8887 : STD_LOGIC; + signal dadrL_N8886 : STD_LOGIC; + signal dadrL_N8816 : STD_LOGIC; + signal dadrL_N8815 : STD_LOGIC; + signal dadrL_N8745 : STD_LOGIC; + signal dadrL_N8744 : STD_LOGIC; + signal dadrL_N8674 : STD_LOGIC; + signal dadrL_N8673 : STD_LOGIC; + signal dadrL_N8603 : STD_LOGIC; + signal dadrL_N8602 : STD_LOGIC; + signal dadrL_N8532 : STD_LOGIC; + signal dadrL_N8531 : STD_LOGIC; + signal dadrL_N8461 : STD_LOGIC; + signal dadrL_N8460 : STD_LOGIC; + signal dadrL_N8390 : STD_LOGIC; + signal dadrL_N8389 : STD_LOGIC; + signal dadrL_N8319 : STD_LOGIC; + signal dadrL_N8318 : STD_LOGIC; + signal dadrL_N8248 : STD_LOGIC; + signal dadrL_N8247 : STD_LOGIC; + signal dadrL_N8177 : STD_LOGIC; + signal dadrL_N8176 : STD_LOGIC; + signal dadrL_N8106 : STD_LOGIC; + signal dadrL_N8105 : STD_LOGIC; + signal dadrL_N8035 : STD_LOGIC; + signal dadrL_N8034 : STD_LOGIC; + signal dadrL_N7964 : STD_LOGIC; + signal dadrL_N7963 : STD_LOGIC; + signal dadrL_N7893 : STD_LOGIC; + signal dadrL_N7892 : STD_LOGIC; + signal dadrL_N7822 : STD_LOGIC; + signal dadrL_N7821 : STD_LOGIC; + signal dadrL_N7751 : STD_LOGIC; + signal dadrL_N7750 : STD_LOGIC; + signal dadrL_N7680 : STD_LOGIC; + signal dadrL_N7679 : STD_LOGIC; + signal dadrL_N7609 : STD_LOGIC; + signal dadrL_N7608 : STD_LOGIC; + signal dadrL_N7538 : STD_LOGIC; + signal dadrL_N7537 : STD_LOGIC; + signal dadrL_N7467 : STD_LOGIC; + signal dadrL_N7466 : STD_LOGIC; + signal dadrL_N7396 : STD_LOGIC; + signal dadrL_N7395 : STD_LOGIC; + signal dadrL_N7325 : STD_LOGIC; + signal dadrL_N7324 : STD_LOGIC; + signal dadrL_N7254 : STD_LOGIC; + signal dadrL_N7253 : STD_LOGIC; + signal dadrL_N7183 : STD_LOGIC; + signal dadrL_N7182 : STD_LOGIC; + signal dadrL_N7112 : STD_LOGIC; + signal dadrL_N7111 : STD_LOGIC; + signal dadrL_N7041 : STD_LOGIC; + signal dadrL_N7040 : STD_LOGIC; + signal dadrL_N6970 : STD_LOGIC; + signal dadrL_N6969 : STD_LOGIC; + signal dadrL_N6899 : STD_LOGIC; + signal dadrL_N6898 : STD_LOGIC; + signal dadrL_N6828 : STD_LOGIC; + signal dadrL_N6827 : STD_LOGIC; + signal dadrL_N6757 : STD_LOGIC; + signal dadrL_N6756 : STD_LOGIC; + signal dadrL_N6686 : STD_LOGIC; + signal dadrL_N6685 : STD_LOGIC; + signal dadrL_N6615 : STD_LOGIC; + signal dadrL_N6614 : STD_LOGIC; + signal dadrL_N6544 : STD_LOGIC; + signal dadrL_N6543 : STD_LOGIC; + signal dadrL_N6473 : STD_LOGIC; + signal dadrL_N6472 : STD_LOGIC; + signal dadrL_N6402 : STD_LOGIC; + signal dadrL_N6401 : STD_LOGIC; + signal dadrL_N6331 : STD_LOGIC; + signal dadrL_N6330 : STD_LOGIC; + signal dadrL_N6260 : STD_LOGIC; + signal dadrL_N6259 : STD_LOGIC; + signal dadrL_N6189 : STD_LOGIC; + signal dadrL_N6188 : STD_LOGIC; + signal dadrL_N6118 : STD_LOGIC; + signal dadrL_N6117 : STD_LOGIC; + signal dadrL_N6047 : STD_LOGIC; + signal dadrL_N6046 : STD_LOGIC; + signal dadrL_N5976 : STD_LOGIC; + signal dadrL_N5975 : STD_LOGIC; + signal dadrL_N5905 : STD_LOGIC; + signal dadrL_N5904 : STD_LOGIC; + signal dadrL_N5834 : STD_LOGIC; + signal dadrL_N5833 : STD_LOGIC; + signal dadrL_N5763 : STD_LOGIC; + signal dadrL_N5762 : STD_LOGIC; + signal dadrL_N5692 : STD_LOGIC; + signal dadrL_N5691 : STD_LOGIC; + signal dadrL_N5621 : STD_LOGIC; + signal dadrL_N5620 : STD_LOGIC; + signal dadrL_N5550 : STD_LOGIC; + signal dadrL_N5549 : STD_LOGIC; + signal dadrL_N5479 : STD_LOGIC; + signal dadrL_N5478 : STD_LOGIC; + signal dadrL_N5408 : STD_LOGIC; + signal dadrL_N5407 : STD_LOGIC; + signal dadrL_N5337 : STD_LOGIC; + signal dadrL_N5336 : STD_LOGIC; + signal dadrL_N5266 : STD_LOGIC; + signal dadrL_N5265 : STD_LOGIC; + signal dadrL_N5195 : STD_LOGIC; + signal dadrL_N5194 : STD_LOGIC; + signal dadrL_N5124 : STD_LOGIC; + signal dadrL_N5123 : STD_LOGIC; + signal dadrL_N5053 : STD_LOGIC; + signal dadrL_N5052 : STD_LOGIC; + signal dadrL_N4982 : STD_LOGIC; + signal dadrL_N4981 : STD_LOGIC; + signal dadrL_N4911 : STD_LOGIC; + signal dadrL_N4910 : STD_LOGIC; + signal dadrL_N4840 : STD_LOGIC; + signal dadrL_N4839 : STD_LOGIC; + signal dadrL_N4769 : STD_LOGIC; + signal dadrL_N4768 : STD_LOGIC; + signal dadrL_N4698 : STD_LOGIC; + signal dadrL_N4697 : STD_LOGIC; + signal dadrL_N4627 : STD_LOGIC; + signal dadrL_N4626 : STD_LOGIC; + signal dadrL_N4556 : STD_LOGIC; + signal dadrL_N4555 : STD_LOGIC; + signal dadrL_N4485 : STD_LOGIC; + signal dadrL_N4484 : STD_LOGIC; + signal dadrL_N4414 : STD_LOGIC; + signal dadrL_N4413 : STD_LOGIC; + signal dadrL_N4343 : STD_LOGIC; + signal dadrL_N4342 : STD_LOGIC; + signal dadrL_N4272 : STD_LOGIC; + signal dadrL_N4271 : STD_LOGIC; + signal dadrL_N4201 : STD_LOGIC; + signal dadrL_N4200 : STD_LOGIC; + signal dadrL_N4130 : STD_LOGIC; + signal dadrL_N4129 : STD_LOGIC; + signal dadrL_N4059 : STD_LOGIC; + signal dadrL_N4058 : STD_LOGIC; + signal dadrL_N3988 : STD_LOGIC; + signal dadrL_N3987 : STD_LOGIC; + signal dadrL_N3917 : STD_LOGIC; + signal dadrL_N3916 : STD_LOGIC; + signal dadrL_N3846 : STD_LOGIC; + signal dadrL_N3845 : STD_LOGIC; + signal dadrL_N3775 : STD_LOGIC; + signal dadrL_N3774 : STD_LOGIC; + signal dadrL_N3704 : STD_LOGIC; + signal dadrL_N3703 : STD_LOGIC; + signal dadrL_N3633 : STD_LOGIC; + signal dadrL_N3632 : STD_LOGIC; + signal dadrL_N3562 : STD_LOGIC; + signal dadrL_N3561 : STD_LOGIC; + signal dadrL_N3491 : STD_LOGIC; + signal dadrL_N3490 : STD_LOGIC; + signal dadrL_N3420 : STD_LOGIC; + signal dadrL_N3419 : STD_LOGIC; + signal dadrL_N3349 : STD_LOGIC; + signal dadrL_N3348 : STD_LOGIC; + signal dadrL_N3278 : STD_LOGIC; + signal dadrL_N3277 : STD_LOGIC; + signal dadrL_N3207 : STD_LOGIC; + signal dadrL_N3206 : STD_LOGIC; + signal dadrL_N3136 : STD_LOGIC; + signal dadrL_N3135 : STD_LOGIC; + signal dadrL_N3065 : STD_LOGIC; + signal dadrL_N3064 : STD_LOGIC; + signal dadrL_N2994 : STD_LOGIC; + signal dadrL_N2993 : STD_LOGIC; + signal dadrL_N2923 : STD_LOGIC; + signal dadrL_N2922 : STD_LOGIC; + signal dadrL_N2852 : STD_LOGIC; + signal dadrL_N2851 : STD_LOGIC; + signal dadrL_N2781 : STD_LOGIC; + signal dadrL_N2780 : STD_LOGIC; + signal dadrL_N2710 : STD_LOGIC; + signal dadrL_N2709 : STD_LOGIC; + signal dadrL_N2639 : STD_LOGIC; + signal dadrL_N2638 : STD_LOGIC; + signal dadrL_N2568 : STD_LOGIC; + signal dadrL_N2567 : STD_LOGIC; + signal dadrL_N2497 : STD_LOGIC; + signal dadrL_N2496 : STD_LOGIC; + signal dadrL_N2426 : STD_LOGIC; + signal dadrL_N2425 : STD_LOGIC; + signal dadrL_N2355 : STD_LOGIC; + signal dadrL_N2354 : STD_LOGIC; + signal dadrL_N2284 : STD_LOGIC; + signal dadrL_N2283 : STD_LOGIC; + signal dadrL_N2213 : STD_LOGIC; + signal dadrL_N2212 : STD_LOGIC; + signal dadrL_N2142 : STD_LOGIC; + signal dadrL_N2141 : STD_LOGIC; + signal dadrL_N2071 : STD_LOGIC; + signal dadrL_N2070 : STD_LOGIC; + signal dadrL_N2000 : STD_LOGIC; + signal dadrL_N1999 : STD_LOGIC; + signal dadrL_N1929 : STD_LOGIC; + signal dadrL_N1928 : STD_LOGIC; + signal dadrL_N1858 : STD_LOGIC; + signal dadrL_N1857 : STD_LOGIC; + signal dadrL_N1787 : STD_LOGIC; + signal dadrL_N1786 : STD_LOGIC; + signal dadrL_N1716 : STD_LOGIC; + signal dadrL_N1715 : STD_LOGIC; + signal dadrL_N1645 : STD_LOGIC; + signal dadrL_N1644 : STD_LOGIC; + signal dadrL_N1574 : STD_LOGIC; + signal dadrL_N1573 : STD_LOGIC; + signal dadrL_N1503 : STD_LOGIC; + signal dadrL_N1502 : STD_LOGIC; + signal dadrL_N1432 : STD_LOGIC; + signal dadrL_N1431 : STD_LOGIC; + signal dadrL_N1361 : STD_LOGIC; + signal dadrL_N1360 : STD_LOGIC; + signal dadrL_N1290 : STD_LOGIC; + signal dadrL_N1289 : STD_LOGIC; + signal dadrL_N1219 : STD_LOGIC; + signal dadrL_N1218 : STD_LOGIC; + signal dadrL_N1148 : STD_LOGIC; + signal dadrL_N1147 : STD_LOGIC; + signal dadrL_N1077 : STD_LOGIC; + signal dadrL_N1076 : STD_LOGIC; + signal dadrL_N1006 : STD_LOGIC; + signal dadrL_N1005 : STD_LOGIC; + signal dadrL_N935 : STD_LOGIC; + signal dadrL_N934 : STD_LOGIC; + signal dadrL_N864 : STD_LOGIC; + signal dadrL_N863 : STD_LOGIC; + signal dadrL_N793 : STD_LOGIC; + signal dadrL_N792 : STD_LOGIC; + signal dadrL_N722 : STD_LOGIC; + signal dadrL_N721 : STD_LOGIC; + signal dadrL_N651 : STD_LOGIC; + signal dadrL_N650 : STD_LOGIC; + signal dadrL_N580 : STD_LOGIC; + signal dadrL_N579 : STD_LOGIC; + signal dadrL_N0 : STD_LOGIC; + signal cs_0_OBUF_GTS_TRI : STD_LOGIC; + signal GTS : STD_LOGIC; + signal clk_OBUF_GTS_TRI : STD_LOGIC; + signal rw_OBUF_GTS_TRI : STD_LOGIC; + signal cs_255_OBUF_GTS_TRI : STD_LOGIC; + signal cs_254_OBUF_GTS_TRI : STD_LOGIC; + signal cs_253_OBUF_GTS_TRI : STD_LOGIC; + signal cs_252_OBUF_GTS_TRI : STD_LOGIC; + signal cs_251_OBUF_GTS_TRI : STD_LOGIC; + signal cs_250_OBUF_GTS_TRI : STD_LOGIC; + signal cs_249_OBUF_GTS_TRI : STD_LOGIC; + signal cs_248_OBUF_GTS_TRI : STD_LOGIC; + signal cs_247_OBUF_GTS_TRI : STD_LOGIC; + signal cs_246_OBUF_GTS_TRI : STD_LOGIC; + signal cs_245_OBUF_GTS_TRI : STD_LOGIC; + signal cs_244_OBUF_GTS_TRI : STD_LOGIC; + signal cs_243_OBUF_GTS_TRI : STD_LOGIC; + signal cs_242_OBUF_GTS_TRI : STD_LOGIC; + signal cs_241_OBUF_GTS_TRI : STD_LOGIC; + signal cs_240_OBUF_GTS_TRI : STD_LOGIC; + signal cs_239_OBUF_GTS_TRI : STD_LOGIC; + signal cs_238_OBUF_GTS_TRI : STD_LOGIC; + signal cs_237_OBUF_GTS_TRI : STD_LOGIC; + signal cs_236_OBUF_GTS_TRI : STD_LOGIC; + signal cs_235_OBUF_GTS_TRI : STD_LOGIC; + signal cs_234_OBUF_GTS_TRI : STD_LOGIC; + signal cs_233_OBUF_GTS_TRI : STD_LOGIC; + signal cs_232_OBUF_GTS_TRI : STD_LOGIC; + signal cs_231_OBUF_GTS_TRI : STD_LOGIC; + signal cs_230_OBUF_GTS_TRI : STD_LOGIC; + signal cs_229_OBUF_GTS_TRI : STD_LOGIC; + signal cs_228_OBUF_GTS_TRI : STD_LOGIC; + signal cs_227_OBUF_GTS_TRI : STD_LOGIC; + signal cs_226_OBUF_GTS_TRI : STD_LOGIC; + signal cs_225_OBUF_GTS_TRI : STD_LOGIC; + signal cs_224_OBUF_GTS_TRI : STD_LOGIC; + signal cs_223_OBUF_GTS_TRI : STD_LOGIC; + signal cs_222_OBUF_GTS_TRI : STD_LOGIC; + signal cs_221_OBUF_GTS_TRI : STD_LOGIC; + signal cs_220_OBUF_GTS_TRI : STD_LOGIC; + signal cs_219_OBUF_GTS_TRI : STD_LOGIC; + signal cs_218_OBUF_GTS_TRI : STD_LOGIC; + signal cs_217_OBUF_GTS_TRI : STD_LOGIC; + signal cs_216_OBUF_GTS_TRI : STD_LOGIC; + signal cs_215_OBUF_GTS_TRI : STD_LOGIC; + signal cs_214_OBUF_GTS_TRI : STD_LOGIC; + signal cs_213_OBUF_GTS_TRI : STD_LOGIC; + signal cs_212_OBUF_GTS_TRI : STD_LOGIC; + signal cs_211_OBUF_GTS_TRI : STD_LOGIC; + signal cs_210_OBUF_GTS_TRI : STD_LOGIC; + signal cs_209_OBUF_GTS_TRI : STD_LOGIC; + signal cs_208_OBUF_GTS_TRI : STD_LOGIC; + signal cs_207_OBUF_GTS_TRI : STD_LOGIC; + signal cs_206_OBUF_GTS_TRI : STD_LOGIC; + signal cs_205_OBUF_GTS_TRI : STD_LOGIC; + signal cs_204_OBUF_GTS_TRI : STD_LOGIC; + signal cs_203_OBUF_GTS_TRI : STD_LOGIC; + signal cs_202_OBUF_GTS_TRI : STD_LOGIC; + signal cs_201_OBUF_GTS_TRI : STD_LOGIC; + signal cs_200_OBUF_GTS_TRI : STD_LOGIC; + signal cs_199_OBUF_GTS_TRI : STD_LOGIC; + signal cs_198_OBUF_GTS_TRI : STD_LOGIC; + signal cs_197_OBUF_GTS_TRI : STD_LOGIC; + signal cs_196_OBUF_GTS_TRI : STD_LOGIC; + signal cs_195_OBUF_GTS_TRI : STD_LOGIC; + signal cs_194_OBUF_GTS_TRI : STD_LOGIC; + signal cs_193_OBUF_GTS_TRI : STD_LOGIC; + signal cs_192_OBUF_GTS_TRI : STD_LOGIC; + signal cs_191_OBUF_GTS_TRI : STD_LOGIC; + signal cs_190_OBUF_GTS_TRI : STD_LOGIC; + signal cs_189_OBUF_GTS_TRI : STD_LOGIC; + signal cs_188_OBUF_GTS_TRI : STD_LOGIC; + signal cs_187_OBUF_GTS_TRI : STD_LOGIC; + signal cs_186_OBUF_GTS_TRI : STD_LOGIC; + signal cs_185_OBUF_GTS_TRI : STD_LOGIC; + signal cs_184_OBUF_GTS_TRI : STD_LOGIC; + signal cs_183_OBUF_GTS_TRI : STD_LOGIC; + signal cs_182_OBUF_GTS_TRI : STD_LOGIC; + signal cs_181_OBUF_GTS_TRI : STD_LOGIC; + signal cs_180_OBUF_GTS_TRI : STD_LOGIC; + signal cs_179_OBUF_GTS_TRI : STD_LOGIC; + signal cs_178_OBUF_GTS_TRI : STD_LOGIC; + signal cs_177_OBUF_GTS_TRI : STD_LOGIC; + signal cs_176_OBUF_GTS_TRI : STD_LOGIC; + signal cs_175_OBUF_GTS_TRI : STD_LOGIC; + signal cs_174_OBUF_GTS_TRI : STD_LOGIC; + signal cs_173_OBUF_GTS_TRI : STD_LOGIC; + signal cs_172_OBUF_GTS_TRI : STD_LOGIC; + signal cs_171_OBUF_GTS_TRI : STD_LOGIC; + signal cs_170_OBUF_GTS_TRI : STD_LOGIC; + signal cs_169_OBUF_GTS_TRI : STD_LOGIC; + signal cs_168_OBUF_GTS_TRI : STD_LOGIC; + signal cs_167_OBUF_GTS_TRI : STD_LOGIC; + signal cs_166_OBUF_GTS_TRI : STD_LOGIC; + signal cs_165_OBUF_GTS_TRI : STD_LOGIC; + signal cs_164_OBUF_GTS_TRI : STD_LOGIC; + signal cs_163_OBUF_GTS_TRI : STD_LOGIC; + signal cs_162_OBUF_GTS_TRI : STD_LOGIC; + signal cs_161_OBUF_GTS_TRI : STD_LOGIC; + signal cs_160_OBUF_GTS_TRI : STD_LOGIC; + signal cs_159_OBUF_GTS_TRI : STD_LOGIC; + signal cs_158_OBUF_GTS_TRI : STD_LOGIC; + signal cs_157_OBUF_GTS_TRI : STD_LOGIC; + signal cs_156_OBUF_GTS_TRI : STD_LOGIC; + signal cs_155_OBUF_GTS_TRI : STD_LOGIC; + signal cs_154_OBUF_GTS_TRI : STD_LOGIC; + signal cs_153_OBUF_GTS_TRI : STD_LOGIC; + signal cs_152_OBUF_GTS_TRI : STD_LOGIC; + signal cs_151_OBUF_GTS_TRI : STD_LOGIC; + signal cs_150_OBUF_GTS_TRI : STD_LOGIC; + signal cs_149_OBUF_GTS_TRI : STD_LOGIC; + signal cs_148_OBUF_GTS_TRI : STD_LOGIC; + signal cs_147_OBUF_GTS_TRI : STD_LOGIC; + signal cs_146_OBUF_GTS_TRI : STD_LOGIC; + signal cs_145_OBUF_GTS_TRI : STD_LOGIC; + signal cs_144_OBUF_GTS_TRI : STD_LOGIC; + signal cs_143_OBUF_GTS_TRI : STD_LOGIC; + signal cs_142_OBUF_GTS_TRI : STD_LOGIC; + signal cs_141_OBUF_GTS_TRI : STD_LOGIC; + signal cs_140_OBUF_GTS_TRI : STD_LOGIC; + signal cs_139_OBUF_GTS_TRI : STD_LOGIC; + signal cs_138_OBUF_GTS_TRI : STD_LOGIC; + signal cs_137_OBUF_GTS_TRI : STD_LOGIC; + signal cs_136_OBUF_GTS_TRI : STD_LOGIC; + signal cs_135_OBUF_GTS_TRI : STD_LOGIC; + signal cs_134_OBUF_GTS_TRI : STD_LOGIC; + signal cs_133_OBUF_GTS_TRI : STD_LOGIC; + signal cs_132_OBUF_GTS_TRI : STD_LOGIC; + signal cs_131_OBUF_GTS_TRI : STD_LOGIC; + signal cs_130_OBUF_GTS_TRI : STD_LOGIC; + signal cs_129_OBUF_GTS_TRI : STD_LOGIC; + signal cs_128_OBUF_GTS_TRI : STD_LOGIC; + signal cs_127_OBUF_GTS_TRI : STD_LOGIC; + signal cs_126_OBUF_GTS_TRI : STD_LOGIC; + signal cs_125_OBUF_GTS_TRI : STD_LOGIC; + signal cs_124_OBUF_GTS_TRI : STD_LOGIC; + signal cs_123_OBUF_GTS_TRI : STD_LOGIC; + signal cs_122_OBUF_GTS_TRI : STD_LOGIC; + signal cs_121_OBUF_GTS_TRI : STD_LOGIC; + signal cs_120_OBUF_GTS_TRI : STD_LOGIC; + signal cs_119_OBUF_GTS_TRI : STD_LOGIC; + signal cs_118_OBUF_GTS_TRI : STD_LOGIC; + signal cs_117_OBUF_GTS_TRI : STD_LOGIC; + signal cs_116_OBUF_GTS_TRI : STD_LOGIC; + signal cs_115_OBUF_GTS_TRI : STD_LOGIC; + signal cs_114_OBUF_GTS_TRI : STD_LOGIC; + signal cs_113_OBUF_GTS_TRI : STD_LOGIC; + signal cs_112_OBUF_GTS_TRI : STD_LOGIC; + signal cs_111_OBUF_GTS_TRI : STD_LOGIC; + signal cs_110_OBUF_GTS_TRI : STD_LOGIC; + signal cs_109_OBUF_GTS_TRI : STD_LOGIC; + signal cs_108_OBUF_GTS_TRI : STD_LOGIC; + signal cs_107_OBUF_GTS_TRI : STD_LOGIC; + signal cs_106_OBUF_GTS_TRI : STD_LOGIC; + signal cs_105_OBUF_GTS_TRI : STD_LOGIC; + signal cs_104_OBUF_GTS_TRI : STD_LOGIC; + signal cs_103_OBUF_GTS_TRI : STD_LOGIC; + signal cs_102_OBUF_GTS_TRI : STD_LOGIC; + signal cs_101_OBUF_GTS_TRI : STD_LOGIC; + signal cs_100_OBUF_GTS_TRI : STD_LOGIC; + signal cs_99_OBUF_GTS_TRI : STD_LOGIC; + signal cs_98_OBUF_GTS_TRI : STD_LOGIC; + signal cs_97_OBUF_GTS_TRI : STD_LOGIC; + signal cs_96_OBUF_GTS_TRI : STD_LOGIC; + signal cs_95_OBUF_GTS_TRI : STD_LOGIC; + signal cs_94_OBUF_GTS_TRI : STD_LOGIC; + signal cs_93_OBUF_GTS_TRI : STD_LOGIC; + signal cs_92_OBUF_GTS_TRI : STD_LOGIC; + signal cs_91_OBUF_GTS_TRI : STD_LOGIC; + signal cs_90_OBUF_GTS_TRI : STD_LOGIC; + signal cs_89_OBUF_GTS_TRI : STD_LOGIC; + signal cs_88_OBUF_GTS_TRI : STD_LOGIC; + signal cs_87_OBUF_GTS_TRI : STD_LOGIC; + signal cs_86_OBUF_GTS_TRI : STD_LOGIC; + signal cs_85_OBUF_GTS_TRI : STD_LOGIC; + signal cs_84_OBUF_GTS_TRI : STD_LOGIC; + signal cs_83_OBUF_GTS_TRI : STD_LOGIC; + signal cs_82_OBUF_GTS_TRI : STD_LOGIC; + signal cs_81_OBUF_GTS_TRI : STD_LOGIC; + signal cs_80_OBUF_GTS_TRI : STD_LOGIC; + signal cs_79_OBUF_GTS_TRI : STD_LOGIC; + signal cs_78_OBUF_GTS_TRI : STD_LOGIC; + signal cs_77_OBUF_GTS_TRI : STD_LOGIC; + signal cs_76_OBUF_GTS_TRI : STD_LOGIC; + signal cs_75_OBUF_GTS_TRI : STD_LOGIC; + signal cs_74_OBUF_GTS_TRI : STD_LOGIC; + signal cs_73_OBUF_GTS_TRI : STD_LOGIC; + signal cs_72_OBUF_GTS_TRI : STD_LOGIC; + signal cs_71_OBUF_GTS_TRI : STD_LOGIC; + signal cs_70_OBUF_GTS_TRI : STD_LOGIC; + signal cs_69_OBUF_GTS_TRI : STD_LOGIC; + signal cs_68_OBUF_GTS_TRI : STD_LOGIC; + signal cs_67_OBUF_GTS_TRI : STD_LOGIC; + signal cs_66_OBUF_GTS_TRI : STD_LOGIC; + signal cs_65_OBUF_GTS_TRI : STD_LOGIC; + signal cs_64_OBUF_GTS_TRI : STD_LOGIC; + signal cs_63_OBUF_GTS_TRI : STD_LOGIC; + signal cs_62_OBUF_GTS_TRI : STD_LOGIC; + signal cs_61_OBUF_GTS_TRI : STD_LOGIC; + signal cs_60_OBUF_GTS_TRI : STD_LOGIC; + signal cs_59_OBUF_GTS_TRI : STD_LOGIC; + signal cs_58_OBUF_GTS_TRI : STD_LOGIC; + signal cs_57_OBUF_GTS_TRI : STD_LOGIC; + signal cs_56_OBUF_GTS_TRI : STD_LOGIC; + signal cs_55_OBUF_GTS_TRI : STD_LOGIC; + signal cs_54_OBUF_GTS_TRI : STD_LOGIC; + signal cs_53_OBUF_GTS_TRI : STD_LOGIC; + signal cs_52_OBUF_GTS_TRI : STD_LOGIC; + signal cs_51_OBUF_GTS_TRI : STD_LOGIC; + signal cs_50_OBUF_GTS_TRI : STD_LOGIC; + signal cs_49_OBUF_GTS_TRI : STD_LOGIC; + signal cs_48_OBUF_GTS_TRI : STD_LOGIC; + signal cs_47_OBUF_GTS_TRI : STD_LOGIC; + signal cs_46_OBUF_GTS_TRI : STD_LOGIC; + signal cs_45_OBUF_GTS_TRI : STD_LOGIC; + signal cs_44_OBUF_GTS_TRI : STD_LOGIC; + signal cs_43_OBUF_GTS_TRI : STD_LOGIC; + signal cs_42_OBUF_GTS_TRI : STD_LOGIC; + signal cs_41_OBUF_GTS_TRI : STD_LOGIC; + signal cs_40_OBUF_GTS_TRI : STD_LOGIC; + signal cs_39_OBUF_GTS_TRI : STD_LOGIC; + signal cs_38_OBUF_GTS_TRI : STD_LOGIC; + signal cs_37_OBUF_GTS_TRI : STD_LOGIC; + signal cs_36_OBUF_GTS_TRI : STD_LOGIC; + signal cs_35_OBUF_GTS_TRI : STD_LOGIC; + signal cs_34_OBUF_GTS_TRI : STD_LOGIC; + signal cs_33_OBUF_GTS_TRI : STD_LOGIC; + signal cs_32_OBUF_GTS_TRI : STD_LOGIC; + signal cs_31_OBUF_GTS_TRI : STD_LOGIC; + signal cs_30_OBUF_GTS_TRI : STD_LOGIC; + signal cs_29_OBUF_GTS_TRI : STD_LOGIC; + signal cs_28_OBUF_GTS_TRI : STD_LOGIC; + signal cs_27_OBUF_GTS_TRI : STD_LOGIC; + signal cs_26_OBUF_GTS_TRI : STD_LOGIC; + signal cs_25_OBUF_GTS_TRI : STD_LOGIC; + signal cs_24_OBUF_GTS_TRI : STD_LOGIC; + signal cs_23_OBUF_GTS_TRI : STD_LOGIC; + signal cs_22_OBUF_GTS_TRI : STD_LOGIC; + signal cs_21_OBUF_GTS_TRI : STD_LOGIC; + signal cs_20_OBUF_GTS_TRI : STD_LOGIC; + signal cs_19_OBUF_GTS_TRI : STD_LOGIC; + signal cs_18_OBUF_GTS_TRI : STD_LOGIC; + signal cs_17_OBUF_GTS_TRI : STD_LOGIC; + signal cs_16_OBUF_GTS_TRI : STD_LOGIC; + signal cs_15_OBUF_GTS_TRI : STD_LOGIC; + signal cs_14_OBUF_GTS_TRI : STD_LOGIC; + signal cs_13_OBUF_GTS_TRI : STD_LOGIC; + signal cs_12_OBUF_GTS_TRI : STD_LOGIC; + signal cs_11_OBUF_GTS_TRI : STD_LOGIC; + signal cs_10_OBUF_GTS_TRI : STD_LOGIC; + signal cs_9_OBUF_GTS_TRI : STD_LOGIC; + signal cs_8_OBUF_GTS_TRI : STD_LOGIC; + signal cs_7_OBUF_GTS_TRI : STD_LOGIC; + signal cs_6_OBUF_GTS_TRI : STD_LOGIC; + signal cs_5_OBUF_GTS_TRI : STD_LOGIC; + signal cs_4_OBUF_GTS_TRI : STD_LOGIC; + signal cs_3_OBUF_GTS_TRI : STD_LOGIC; + signal cs_2_OBUF_GTS_TRI : STD_LOGIC; + signal cs_1_OBUF_GTS_TRI : STD_LOGIC; + signal NLW_dadrL_VCC_O_UNCONNECTED : STD_LOGIC; + signal NlwInverterSignal_cs_0_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_clk_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_rw_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_255_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_254_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_253_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_252_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_251_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_250_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_249_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_248_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_247_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_246_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_245_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_244_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_243_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_242_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_241_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_240_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_239_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_238_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_237_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_236_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_235_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_234_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_233_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_232_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_231_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_230_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_229_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_228_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_227_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_226_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_225_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_224_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_223_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_222_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_221_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_220_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_219_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_218_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_217_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_216_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_215_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_214_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_213_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_212_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_211_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_210_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_209_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_208_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_207_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_206_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_205_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_204_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_203_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_202_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_201_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_200_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_199_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_198_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_197_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_196_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_195_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_194_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_193_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_192_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_191_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_190_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_189_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_188_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_187_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_186_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_185_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_184_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_183_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_182_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_181_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_180_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_179_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_178_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_177_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_176_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_175_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_174_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_173_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_172_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_171_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_170_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_169_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_168_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_167_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_166_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_165_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_164_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_163_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_162_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_161_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_160_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_159_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_158_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_157_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_156_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_155_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_154_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_153_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_152_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_151_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_150_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_149_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_148_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_147_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_146_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_145_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_144_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_143_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_142_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_141_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_140_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_139_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_138_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_137_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_136_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_135_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_134_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_133_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_132_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_131_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_130_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_129_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_128_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_127_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_126_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_125_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_124_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_123_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_122_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_121_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_120_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_119_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_118_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_117_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_116_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_115_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_114_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_113_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_112_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_111_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_110_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_109_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_108_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_107_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_106_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_105_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_104_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_103_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_102_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_101_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_100_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_99_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_98_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_97_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_96_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_95_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_94_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_93_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_92_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_91_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_90_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_89_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_88_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_87_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_86_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_85_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_84_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_83_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_82_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_81_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_80_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_79_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_78_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_77_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_76_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_75_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_74_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_73_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_72_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_71_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_70_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_69_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_68_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_67_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_66_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_65_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_64_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_63_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_62_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_61_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_60_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_59_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_58_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_57_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_56_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_55_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_54_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_53_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_52_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_51_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_50_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_49_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_48_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_47_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_46_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_45_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_44_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_43_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_42_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_41_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_40_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_39_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_38_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_37_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_36_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_35_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_34_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_33_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_32_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_31_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_30_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_29_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_28_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_27_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_26_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_25_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_24_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_23_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_22_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_21_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_20_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_19_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_18_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_17_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_16_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_15_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_14_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_13_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_12_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_11_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_10_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_9_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_8_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_7_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_6_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_5_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_4_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_3_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_2_OBUF_GTS_TRI_CTL : STD_LOGIC; + signal NlwInverterSignal_cs_1_OBUF_GTS_TRI_CTL : STD_LOGIC; +begin + cs_0_OBUF_0 : X_BUF + port map ( + I => cs_0_OBUF, + O => cs_0_OBUF_GTS_TRI + ); + Q_n00031 : X_LUT3 + generic map( + INIT => X"04" + ) + port map ( + ADR0 => IOR_IBUF, + ADR1 => IOW_IBUF, + ADR2 => AEN_IBUF, + O => rw_OBUF + ); + Q_n00021 : X_LUT3 + generic map( + INIT => X"F8" + ) + port map ( + ADR0 => IOW_IBUF, + ADR1 => IOR_IBUF, + ADR2 => AEN_IBUF, + O => clk_OBUF + ); + reg_select24 : X_LUT3 + generic map( + INIT => X"04" + ) + port map ( + ADR0 => adr_bus_15_IBUF, + ADR1 => adr_bus_8_IBUF, + ADR2 => AEN_IBUF, + O => CHOICE45 + ); + reg_select32 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_9_IBUF, + ADR1 => adr_bus_10_IBUF, + ADR2 => adr_bus_11_IBUF, + ADR3 => N5267, + O => reg_select + ); + reg_select32_SW0 : X_LUT4 + generic map( + INIT => X"FFEF" + ) + port map ( + ADR0 => adr_bus_12_IBUF, + ADR1 => adr_bus_13_IBUF, + ADR2 => CHOICE45, + ADR3 => adr_bus_14_IBUF, + O => N5267 + ); + AEN_IBUF_1 : X_BUF + port map ( + I => AEN, + O => AEN_IBUF + ); + IOR_IBUF_2 : X_BUF + port map ( + I => IOR, + O => IOR_IBUF + ); + IOW_IBUF_3 : X_BUF + port map ( + I => IOW, + O => IOW_IBUF + ); + adr_bus_15_IBUF_4 : X_BUF + port map ( + I => adr_bus(15), + O => adr_bus_15_IBUF + ); + adr_bus_14_IBUF_5 : X_BUF + port map ( + I => adr_bus(14), + O => adr_bus_14_IBUF + ); + adr_bus_13_IBUF_6 : X_BUF + port map ( + I => adr_bus(13), + O => adr_bus_13_IBUF + ); + adr_bus_12_IBUF_7 : X_BUF + port map ( + I => adr_bus(12), + O => adr_bus_12_IBUF + ); + adr_bus_11_IBUF_8 : X_BUF + port map ( + I => adr_bus(11), + O => adr_bus_11_IBUF + ); + adr_bus_10_IBUF_9 : X_BUF + port map ( + I => adr_bus(10), + O => adr_bus_10_IBUF + ); + adr_bus_9_IBUF_10 : X_BUF + port map ( + I => adr_bus(9), + O => adr_bus_9_IBUF + ); + adr_bus_8_IBUF_11 : X_BUF + port map ( + I => adr_bus(8), + O => adr_bus_8_IBUF + ); + adr_bus_7_IBUF_12 : X_BUF + port map ( + I => adr_bus(7), + O => adr_bus_7_IBUF + ); + adr_bus_6_IBUF_13 : X_BUF + port map ( + I => adr_bus(6), + O => adr_bus_6_IBUF + ); + adr_bus_5_IBUF_14 : X_BUF + port map ( + I => adr_bus(5), + O => adr_bus_5_IBUF + ); + adr_bus_4_IBUF_15 : X_BUF + port map ( + I => adr_bus(4), + O => adr_bus_4_IBUF + ); + adr_bus_3_IBUF_16 : X_BUF + port map ( + I => adr_bus(3), + O => adr_bus_3_IBUF + ); + adr_bus_2_IBUF_17 : X_BUF + port map ( + I => adr_bus(2), + O => adr_bus_2_IBUF + ); + adr_bus_1_IBUF_18 : X_BUF + port map ( + I => adr_bus(1), + O => adr_bus_1_IBUF + ); + adr_bus_0_IBUF_19 : X_BUF + port map ( + I => adr_bus(0), + O => adr_bus_0_IBUF + ); + clk_OBUF_20 : X_BUF + port map ( + I => clk_OBUF, + O => clk_OBUF_GTS_TRI + ); + rw_OBUF_21 : X_BUF + port map ( + I => rw_OBUF, + O => rw_OBUF_GTS_TRI + ); + cs_255_OBUF_22 : X_BUF + port map ( + I => cs_255_OBUF, + O => cs_255_OBUF_GTS_TRI + ); + cs_254_OBUF_23 : X_BUF + port map ( + I => cs_254_OBUF, + O => cs_254_OBUF_GTS_TRI + ); + cs_253_OBUF_24 : X_BUF + port map ( + I => cs_253_OBUF, + O => cs_253_OBUF_GTS_TRI + ); + cs_252_OBUF_25 : X_BUF + port map ( + I => cs_252_OBUF, + O => cs_252_OBUF_GTS_TRI + ); + cs_251_OBUF_26 : X_BUF + port map ( + I => cs_251_OBUF, + O => cs_251_OBUF_GTS_TRI + ); + cs_250_OBUF_27 : X_BUF + port map ( + I => cs_250_OBUF, + O => cs_250_OBUF_GTS_TRI + ); + cs_249_OBUF_28 : X_BUF + port map ( + I => cs_249_OBUF, + O => cs_249_OBUF_GTS_TRI + ); + cs_248_OBUF_29 : X_BUF + port map ( + I => cs_248_OBUF, + O => cs_248_OBUF_GTS_TRI + ); + cs_247_OBUF_30 : X_BUF + port map ( + I => cs_247_OBUF, + O => cs_247_OBUF_GTS_TRI + ); + cs_246_OBUF_31 : X_BUF + port map ( + I => cs_246_OBUF, + O => cs_246_OBUF_GTS_TRI + ); + cs_245_OBUF_32 : X_BUF + port map ( + I => cs_245_OBUF, + O => cs_245_OBUF_GTS_TRI + ); + cs_244_OBUF_33 : X_BUF + port map ( + I => cs_244_OBUF, + O => cs_244_OBUF_GTS_TRI + ); + cs_243_OBUF_34 : X_BUF + port map ( + I => cs_243_OBUF, + O => cs_243_OBUF_GTS_TRI + ); + cs_242_OBUF_35 : X_BUF + port map ( + I => cs_242_OBUF, + O => cs_242_OBUF_GTS_TRI + ); + cs_241_OBUF_36 : X_BUF + port map ( + I => cs_241_OBUF, + O => cs_241_OBUF_GTS_TRI + ); + cs_240_OBUF_37 : X_BUF + port map ( + I => cs_240_OBUF, + O => cs_240_OBUF_GTS_TRI + ); + cs_239_OBUF_38 : X_BUF + port map ( + I => cs_239_OBUF, + O => cs_239_OBUF_GTS_TRI + ); + cs_238_OBUF_39 : X_BUF + port map ( + I => cs_238_OBUF, + O => cs_238_OBUF_GTS_TRI + ); + cs_237_OBUF_40 : X_BUF + port map ( + I => cs_237_OBUF, + O => cs_237_OBUF_GTS_TRI + ); + cs_236_OBUF_41 : X_BUF + port map ( + I => cs_236_OBUF, + O => cs_236_OBUF_GTS_TRI + ); + cs_235_OBUF_42 : X_BUF + port map ( + I => cs_235_OBUF, + O => cs_235_OBUF_GTS_TRI + ); + cs_234_OBUF_43 : X_BUF + port map ( + I => cs_234_OBUF, + O => cs_234_OBUF_GTS_TRI + ); + cs_233_OBUF_44 : X_BUF + port map ( + I => cs_233_OBUF, + O => cs_233_OBUF_GTS_TRI + ); + cs_232_OBUF_45 : X_BUF + port map ( + I => cs_232_OBUF, + O => cs_232_OBUF_GTS_TRI + ); + cs_231_OBUF_46 : X_BUF + port map ( + I => cs_231_OBUF, + O => cs_231_OBUF_GTS_TRI + ); + cs_230_OBUF_47 : X_BUF + port map ( + I => cs_230_OBUF, + O => cs_230_OBUF_GTS_TRI + ); + cs_229_OBUF_48 : X_BUF + port map ( + I => cs_229_OBUF, + O => cs_229_OBUF_GTS_TRI + ); + cs_228_OBUF_49 : X_BUF + port map ( + I => cs_228_OBUF, + O => cs_228_OBUF_GTS_TRI + ); + cs_227_OBUF_50 : X_BUF + port map ( + I => cs_227_OBUF, + O => cs_227_OBUF_GTS_TRI + ); + cs_226_OBUF_51 : X_BUF + port map ( + I => cs_226_OBUF, + O => cs_226_OBUF_GTS_TRI + ); + cs_225_OBUF_52 : X_BUF + port map ( + I => cs_225_OBUF, + O => cs_225_OBUF_GTS_TRI + ); + cs_224_OBUF_53 : X_BUF + port map ( + I => cs_224_OBUF, + O => cs_224_OBUF_GTS_TRI + ); + cs_223_OBUF_54 : X_BUF + port map ( + I => cs_223_OBUF, + O => cs_223_OBUF_GTS_TRI + ); + cs_222_OBUF_55 : X_BUF + port map ( + I => cs_222_OBUF, + O => cs_222_OBUF_GTS_TRI + ); + cs_221_OBUF_56 : X_BUF + port map ( + I => cs_221_OBUF, + O => cs_221_OBUF_GTS_TRI + ); + cs_220_OBUF_57 : X_BUF + port map ( + I => cs_220_OBUF, + O => cs_220_OBUF_GTS_TRI + ); + cs_219_OBUF_58 : X_BUF + port map ( + I => cs_219_OBUF, + O => cs_219_OBUF_GTS_TRI + ); + cs_218_OBUF_59 : X_BUF + port map ( + I => cs_218_OBUF, + O => cs_218_OBUF_GTS_TRI + ); + cs_217_OBUF_60 : X_BUF + port map ( + I => cs_217_OBUF, + O => cs_217_OBUF_GTS_TRI + ); + cs_216_OBUF_61 : X_BUF + port map ( + I => cs_216_OBUF, + O => cs_216_OBUF_GTS_TRI + ); + cs_215_OBUF_62 : X_BUF + port map ( + I => cs_215_OBUF, + O => cs_215_OBUF_GTS_TRI + ); + cs_214_OBUF_63 : X_BUF + port map ( + I => cs_214_OBUF, + O => cs_214_OBUF_GTS_TRI + ); + cs_213_OBUF_64 : X_BUF + port map ( + I => cs_213_OBUF, + O => cs_213_OBUF_GTS_TRI + ); + cs_212_OBUF_65 : X_BUF + port map ( + I => cs_212_OBUF, + O => cs_212_OBUF_GTS_TRI + ); + cs_211_OBUF_66 : X_BUF + port map ( + I => cs_211_OBUF, + O => cs_211_OBUF_GTS_TRI + ); + cs_210_OBUF_67 : X_BUF + port map ( + I => cs_210_OBUF, + O => cs_210_OBUF_GTS_TRI + ); + cs_209_OBUF_68 : X_BUF + port map ( + I => cs_209_OBUF, + O => cs_209_OBUF_GTS_TRI + ); + cs_208_OBUF_69 : X_BUF + port map ( + I => cs_208_OBUF, + O => cs_208_OBUF_GTS_TRI + ); + cs_207_OBUF_70 : X_BUF + port map ( + I => cs_207_OBUF, + O => cs_207_OBUF_GTS_TRI + ); + cs_206_OBUF_71 : X_BUF + port map ( + I => cs_206_OBUF, + O => cs_206_OBUF_GTS_TRI + ); + cs_205_OBUF_72 : X_BUF + port map ( + I => cs_205_OBUF, + O => cs_205_OBUF_GTS_TRI + ); + cs_204_OBUF_73 : X_BUF + port map ( + I => cs_204_OBUF, + O => cs_204_OBUF_GTS_TRI + ); + cs_203_OBUF_74 : X_BUF + port map ( + I => cs_203_OBUF, + O => cs_203_OBUF_GTS_TRI + ); + cs_202_OBUF_75 : X_BUF + port map ( + I => cs_202_OBUF, + O => cs_202_OBUF_GTS_TRI + ); + cs_201_OBUF_76 : X_BUF + port map ( + I => cs_201_OBUF, + O => cs_201_OBUF_GTS_TRI + ); + cs_200_OBUF_77 : X_BUF + port map ( + I => cs_200_OBUF, + O => cs_200_OBUF_GTS_TRI + ); + cs_199_OBUF_78 : X_BUF + port map ( + I => cs_199_OBUF, + O => cs_199_OBUF_GTS_TRI + ); + cs_198_OBUF_79 : X_BUF + port map ( + I => cs_198_OBUF, + O => cs_198_OBUF_GTS_TRI + ); + cs_197_OBUF_80 : X_BUF + port map ( + I => cs_197_OBUF, + O => cs_197_OBUF_GTS_TRI + ); + cs_196_OBUF_81 : X_BUF + port map ( + I => cs_196_OBUF, + O => cs_196_OBUF_GTS_TRI + ); + cs_195_OBUF_82 : X_BUF + port map ( + I => cs_195_OBUF, + O => cs_195_OBUF_GTS_TRI + ); + cs_194_OBUF_83 : X_BUF + port map ( + I => cs_194_OBUF, + O => cs_194_OBUF_GTS_TRI + ); + cs_193_OBUF_84 : X_BUF + port map ( + I => cs_193_OBUF, + O => cs_193_OBUF_GTS_TRI + ); + cs_192_OBUF_85 : X_BUF + port map ( + I => cs_192_OBUF, + O => cs_192_OBUF_GTS_TRI + ); + cs_191_OBUF_86 : X_BUF + port map ( + I => cs_191_OBUF, + O => cs_191_OBUF_GTS_TRI + ); + cs_190_OBUF_87 : X_BUF + port map ( + I => cs_190_OBUF, + O => cs_190_OBUF_GTS_TRI + ); + cs_189_OBUF_88 : X_BUF + port map ( + I => cs_189_OBUF, + O => cs_189_OBUF_GTS_TRI + ); + cs_188_OBUF_89 : X_BUF + port map ( + I => cs_188_OBUF, + O => cs_188_OBUF_GTS_TRI + ); + cs_187_OBUF_90 : X_BUF + port map ( + I => cs_187_OBUF, + O => cs_187_OBUF_GTS_TRI + ); + cs_186_OBUF_91 : X_BUF + port map ( + I => cs_186_OBUF, + O => cs_186_OBUF_GTS_TRI + ); + cs_185_OBUF_92 : X_BUF + port map ( + I => cs_185_OBUF, + O => cs_185_OBUF_GTS_TRI + ); + cs_184_OBUF_93 : X_BUF + port map ( + I => cs_184_OBUF, + O => cs_184_OBUF_GTS_TRI + ); + cs_183_OBUF_94 : X_BUF + port map ( + I => cs_183_OBUF, + O => cs_183_OBUF_GTS_TRI + ); + cs_182_OBUF_95 : X_BUF + port map ( + I => cs_182_OBUF, + O => cs_182_OBUF_GTS_TRI + ); + cs_181_OBUF_96 : X_BUF + port map ( + I => cs_181_OBUF, + O => cs_181_OBUF_GTS_TRI + ); + cs_180_OBUF_97 : X_BUF + port map ( + I => cs_180_OBUF, + O => cs_180_OBUF_GTS_TRI + ); + cs_179_OBUF_98 : X_BUF + port map ( + I => cs_179_OBUF, + O => cs_179_OBUF_GTS_TRI + ); + cs_178_OBUF_99 : X_BUF + port map ( + I => cs_178_OBUF, + O => cs_178_OBUF_GTS_TRI + ); + cs_177_OBUF_100 : X_BUF + port map ( + I => cs_177_OBUF, + O => cs_177_OBUF_GTS_TRI + ); + cs_176_OBUF_101 : X_BUF + port map ( + I => cs_176_OBUF, + O => cs_176_OBUF_GTS_TRI + ); + cs_175_OBUF_102 : X_BUF + port map ( + I => cs_175_OBUF, + O => cs_175_OBUF_GTS_TRI + ); + cs_174_OBUF_103 : X_BUF + port map ( + I => cs_174_OBUF, + O => cs_174_OBUF_GTS_TRI + ); + cs_173_OBUF_104 : X_BUF + port map ( + I => cs_173_OBUF, + O => cs_173_OBUF_GTS_TRI + ); + cs_172_OBUF_105 : X_BUF + port map ( + I => cs_172_OBUF, + O => cs_172_OBUF_GTS_TRI + ); + cs_171_OBUF_106 : X_BUF + port map ( + I => cs_171_OBUF, + O => cs_171_OBUF_GTS_TRI + ); + cs_170_OBUF_107 : X_BUF + port map ( + I => cs_170_OBUF, + O => cs_170_OBUF_GTS_TRI + ); + cs_169_OBUF_108 : X_BUF + port map ( + I => cs_169_OBUF, + O => cs_169_OBUF_GTS_TRI + ); + cs_168_OBUF_109 : X_BUF + port map ( + I => cs_168_OBUF, + O => cs_168_OBUF_GTS_TRI + ); + cs_167_OBUF_110 : X_BUF + port map ( + I => cs_167_OBUF, + O => cs_167_OBUF_GTS_TRI + ); + cs_166_OBUF_111 : X_BUF + port map ( + I => cs_166_OBUF, + O => cs_166_OBUF_GTS_TRI + ); + cs_165_OBUF_112 : X_BUF + port map ( + I => cs_165_OBUF, + O => cs_165_OBUF_GTS_TRI + ); + cs_164_OBUF_113 : X_BUF + port map ( + I => cs_164_OBUF, + O => cs_164_OBUF_GTS_TRI + ); + cs_163_OBUF_114 : X_BUF + port map ( + I => cs_163_OBUF, + O => cs_163_OBUF_GTS_TRI + ); + cs_162_OBUF_115 : X_BUF + port map ( + I => cs_162_OBUF, + O => cs_162_OBUF_GTS_TRI + ); + cs_161_OBUF_116 : X_BUF + port map ( + I => cs_161_OBUF, + O => cs_161_OBUF_GTS_TRI + ); + cs_160_OBUF_117 : X_BUF + port map ( + I => cs_160_OBUF, + O => cs_160_OBUF_GTS_TRI + ); + cs_159_OBUF_118 : X_BUF + port map ( + I => cs_159_OBUF, + O => cs_159_OBUF_GTS_TRI + ); + cs_158_OBUF_119 : X_BUF + port map ( + I => cs_158_OBUF, + O => cs_158_OBUF_GTS_TRI + ); + cs_157_OBUF_120 : X_BUF + port map ( + I => cs_157_OBUF, + O => cs_157_OBUF_GTS_TRI + ); + cs_156_OBUF_121 : X_BUF + port map ( + I => cs_156_OBUF, + O => cs_156_OBUF_GTS_TRI + ); + cs_155_OBUF_122 : X_BUF + port map ( + I => cs_155_OBUF, + O => cs_155_OBUF_GTS_TRI + ); + cs_154_OBUF_123 : X_BUF + port map ( + I => cs_154_OBUF, + O => cs_154_OBUF_GTS_TRI + ); + cs_153_OBUF_124 : X_BUF + port map ( + I => cs_153_OBUF, + O => cs_153_OBUF_GTS_TRI + ); + cs_152_OBUF_125 : X_BUF + port map ( + I => cs_152_OBUF, + O => cs_152_OBUF_GTS_TRI + ); + cs_151_OBUF_126 : X_BUF + port map ( + I => cs_151_OBUF, + O => cs_151_OBUF_GTS_TRI + ); + cs_150_OBUF_127 : X_BUF + port map ( + I => cs_150_OBUF, + O => cs_150_OBUF_GTS_TRI + ); + cs_149_OBUF_128 : X_BUF + port map ( + I => cs_149_OBUF, + O => cs_149_OBUF_GTS_TRI + ); + cs_148_OBUF_129 : X_BUF + port map ( + I => cs_148_OBUF, + O => cs_148_OBUF_GTS_TRI + ); + cs_147_OBUF_130 : X_BUF + port map ( + I => cs_147_OBUF, + O => cs_147_OBUF_GTS_TRI + ); + cs_146_OBUF_131 : X_BUF + port map ( + I => cs_146_OBUF, + O => cs_146_OBUF_GTS_TRI + ); + cs_145_OBUF_132 : X_BUF + port map ( + I => cs_145_OBUF, + O => cs_145_OBUF_GTS_TRI + ); + cs_144_OBUF_133 : X_BUF + port map ( + I => cs_144_OBUF, + O => cs_144_OBUF_GTS_TRI + ); + cs_143_OBUF_134 : X_BUF + port map ( + I => cs_143_OBUF, + O => cs_143_OBUF_GTS_TRI + ); + cs_142_OBUF_135 : X_BUF + port map ( + I => cs_142_OBUF, + O => cs_142_OBUF_GTS_TRI + ); + cs_141_OBUF_136 : X_BUF + port map ( + I => cs_141_OBUF, + O => cs_141_OBUF_GTS_TRI + ); + cs_140_OBUF_137 : X_BUF + port map ( + I => cs_140_OBUF, + O => cs_140_OBUF_GTS_TRI + ); + cs_139_OBUF_138 : X_BUF + port map ( + I => cs_139_OBUF, + O => cs_139_OBUF_GTS_TRI + ); + cs_138_OBUF_139 : X_BUF + port map ( + I => cs_138_OBUF, + O => cs_138_OBUF_GTS_TRI + ); + cs_137_OBUF_140 : X_BUF + port map ( + I => cs_137_OBUF, + O => cs_137_OBUF_GTS_TRI + ); + cs_136_OBUF_141 : X_BUF + port map ( + I => cs_136_OBUF, + O => cs_136_OBUF_GTS_TRI + ); + cs_135_OBUF_142 : X_BUF + port map ( + I => cs_135_OBUF, + O => cs_135_OBUF_GTS_TRI + ); + cs_134_OBUF_143 : X_BUF + port map ( + I => cs_134_OBUF, + O => cs_134_OBUF_GTS_TRI + ); + cs_133_OBUF_144 : X_BUF + port map ( + I => cs_133_OBUF, + O => cs_133_OBUF_GTS_TRI + ); + cs_132_OBUF_145 : X_BUF + port map ( + I => cs_132_OBUF, + O => cs_132_OBUF_GTS_TRI + ); + cs_131_OBUF_146 : X_BUF + port map ( + I => cs_131_OBUF, + O => cs_131_OBUF_GTS_TRI + ); + cs_130_OBUF_147 : X_BUF + port map ( + I => cs_130_OBUF, + O => cs_130_OBUF_GTS_TRI + ); + cs_129_OBUF_148 : X_BUF + port map ( + I => cs_129_OBUF, + O => cs_129_OBUF_GTS_TRI + ); + cs_128_OBUF_149 : X_BUF + port map ( + I => cs_128_OBUF, + O => cs_128_OBUF_GTS_TRI + ); + cs_127_OBUF_150 : X_BUF + port map ( + I => cs_127_OBUF, + O => cs_127_OBUF_GTS_TRI + ); + cs_126_OBUF_151 : X_BUF + port map ( + I => cs_126_OBUF, + O => cs_126_OBUF_GTS_TRI + ); + cs_125_OBUF_152 : X_BUF + port map ( + I => cs_125_OBUF, + O => cs_125_OBUF_GTS_TRI + ); + cs_124_OBUF_153 : X_BUF + port map ( + I => cs_124_OBUF, + O => cs_124_OBUF_GTS_TRI + ); + cs_123_OBUF_154 : X_BUF + port map ( + I => cs_123_OBUF, + O => cs_123_OBUF_GTS_TRI + ); + cs_122_OBUF_155 : X_BUF + port map ( + I => cs_122_OBUF, + O => cs_122_OBUF_GTS_TRI + ); + cs_121_OBUF_156 : X_BUF + port map ( + I => cs_121_OBUF, + O => cs_121_OBUF_GTS_TRI + ); + cs_120_OBUF_157 : X_BUF + port map ( + I => cs_120_OBUF, + O => cs_120_OBUF_GTS_TRI + ); + cs_119_OBUF_158 : X_BUF + port map ( + I => cs_119_OBUF, + O => cs_119_OBUF_GTS_TRI + ); + cs_118_OBUF_159 : X_BUF + port map ( + I => cs_118_OBUF, + O => cs_118_OBUF_GTS_TRI + ); + cs_117_OBUF_160 : X_BUF + port map ( + I => cs_117_OBUF, + O => cs_117_OBUF_GTS_TRI + ); + cs_116_OBUF_161 : X_BUF + port map ( + I => cs_116_OBUF, + O => cs_116_OBUF_GTS_TRI + ); + cs_115_OBUF_162 : X_BUF + port map ( + I => cs_115_OBUF, + O => cs_115_OBUF_GTS_TRI + ); + cs_114_OBUF_163 : X_BUF + port map ( + I => cs_114_OBUF, + O => cs_114_OBUF_GTS_TRI + ); + cs_113_OBUF_164 : X_BUF + port map ( + I => cs_113_OBUF, + O => cs_113_OBUF_GTS_TRI + ); + cs_112_OBUF_165 : X_BUF + port map ( + I => cs_112_OBUF, + O => cs_112_OBUF_GTS_TRI + ); + cs_111_OBUF_166 : X_BUF + port map ( + I => cs_111_OBUF, + O => cs_111_OBUF_GTS_TRI + ); + cs_110_OBUF_167 : X_BUF + port map ( + I => cs_110_OBUF, + O => cs_110_OBUF_GTS_TRI + ); + cs_109_OBUF_168 : X_BUF + port map ( + I => cs_109_OBUF, + O => cs_109_OBUF_GTS_TRI + ); + cs_108_OBUF_169 : X_BUF + port map ( + I => cs_108_OBUF, + O => cs_108_OBUF_GTS_TRI + ); + cs_107_OBUF_170 : X_BUF + port map ( + I => cs_107_OBUF, + O => cs_107_OBUF_GTS_TRI + ); + cs_106_OBUF_171 : X_BUF + port map ( + I => cs_106_OBUF, + O => cs_106_OBUF_GTS_TRI + ); + cs_105_OBUF_172 : X_BUF + port map ( + I => cs_105_OBUF, + O => cs_105_OBUF_GTS_TRI + ); + cs_104_OBUF_173 : X_BUF + port map ( + I => cs_104_OBUF, + O => cs_104_OBUF_GTS_TRI + ); + cs_103_OBUF_174 : X_BUF + port map ( + I => cs_103_OBUF, + O => cs_103_OBUF_GTS_TRI + ); + cs_102_OBUF_175 : X_BUF + port map ( + I => cs_102_OBUF, + O => cs_102_OBUF_GTS_TRI + ); + cs_101_OBUF_176 : X_BUF + port map ( + I => cs_101_OBUF, + O => cs_101_OBUF_GTS_TRI + ); + cs_100_OBUF_177 : X_BUF + port map ( + I => cs_100_OBUF, + O => cs_100_OBUF_GTS_TRI + ); + cs_99_OBUF_178 : X_BUF + port map ( + I => cs_99_OBUF, + O => cs_99_OBUF_GTS_TRI + ); + cs_98_OBUF_179 : X_BUF + port map ( + I => cs_98_OBUF, + O => cs_98_OBUF_GTS_TRI + ); + cs_97_OBUF_180 : X_BUF + port map ( + I => cs_97_OBUF, + O => cs_97_OBUF_GTS_TRI + ); + cs_96_OBUF_181 : X_BUF + port map ( + I => cs_96_OBUF, + O => cs_96_OBUF_GTS_TRI + ); + cs_95_OBUF_182 : X_BUF + port map ( + I => cs_95_OBUF, + O => cs_95_OBUF_GTS_TRI + ); + cs_94_OBUF_183 : X_BUF + port map ( + I => cs_94_OBUF, + O => cs_94_OBUF_GTS_TRI + ); + cs_93_OBUF_184 : X_BUF + port map ( + I => cs_93_OBUF, + O => cs_93_OBUF_GTS_TRI + ); + cs_92_OBUF_185 : X_BUF + port map ( + I => cs_92_OBUF, + O => cs_92_OBUF_GTS_TRI + ); + cs_91_OBUF_186 : X_BUF + port map ( + I => cs_91_OBUF, + O => cs_91_OBUF_GTS_TRI + ); + cs_90_OBUF_187 : X_BUF + port map ( + I => cs_90_OBUF, + O => cs_90_OBUF_GTS_TRI + ); + cs_89_OBUF_188 : X_BUF + port map ( + I => cs_89_OBUF, + O => cs_89_OBUF_GTS_TRI + ); + cs_88_OBUF_189 : X_BUF + port map ( + I => cs_88_OBUF, + O => cs_88_OBUF_GTS_TRI + ); + cs_87_OBUF_190 : X_BUF + port map ( + I => cs_87_OBUF, + O => cs_87_OBUF_GTS_TRI + ); + cs_86_OBUF_191 : X_BUF + port map ( + I => cs_86_OBUF, + O => cs_86_OBUF_GTS_TRI + ); + cs_85_OBUF_192 : X_BUF + port map ( + I => cs_85_OBUF, + O => cs_85_OBUF_GTS_TRI + ); + cs_84_OBUF_193 : X_BUF + port map ( + I => cs_84_OBUF, + O => cs_84_OBUF_GTS_TRI + ); + cs_83_OBUF_194 : X_BUF + port map ( + I => cs_83_OBUF, + O => cs_83_OBUF_GTS_TRI + ); + cs_82_OBUF_195 : X_BUF + port map ( + I => cs_82_OBUF, + O => cs_82_OBUF_GTS_TRI + ); + cs_81_OBUF_196 : X_BUF + port map ( + I => cs_81_OBUF, + O => cs_81_OBUF_GTS_TRI + ); + cs_80_OBUF_197 : X_BUF + port map ( + I => cs_80_OBUF, + O => cs_80_OBUF_GTS_TRI + ); + cs_79_OBUF_198 : X_BUF + port map ( + I => cs_79_OBUF, + O => cs_79_OBUF_GTS_TRI + ); + cs_78_OBUF_199 : X_BUF + port map ( + I => cs_78_OBUF, + O => cs_78_OBUF_GTS_TRI + ); + cs_77_OBUF_200 : X_BUF + port map ( + I => cs_77_OBUF, + O => cs_77_OBUF_GTS_TRI + ); + cs_76_OBUF_201 : X_BUF + port map ( + I => cs_76_OBUF, + O => cs_76_OBUF_GTS_TRI + ); + cs_75_OBUF_202 : X_BUF + port map ( + I => cs_75_OBUF, + O => cs_75_OBUF_GTS_TRI + ); + cs_74_OBUF_203 : X_BUF + port map ( + I => cs_74_OBUF, + O => cs_74_OBUF_GTS_TRI + ); + cs_73_OBUF_204 : X_BUF + port map ( + I => cs_73_OBUF, + O => cs_73_OBUF_GTS_TRI + ); + cs_72_OBUF_205 : X_BUF + port map ( + I => cs_72_OBUF, + O => cs_72_OBUF_GTS_TRI + ); + cs_71_OBUF_206 : X_BUF + port map ( + I => cs_71_OBUF, + O => cs_71_OBUF_GTS_TRI + ); + cs_70_OBUF_207 : X_BUF + port map ( + I => cs_70_OBUF, + O => cs_70_OBUF_GTS_TRI + ); + cs_69_OBUF_208 : X_BUF + port map ( + I => cs_69_OBUF, + O => cs_69_OBUF_GTS_TRI + ); + cs_68_OBUF_209 : X_BUF + port map ( + I => cs_68_OBUF, + O => cs_68_OBUF_GTS_TRI + ); + cs_67_OBUF_210 : X_BUF + port map ( + I => cs_67_OBUF, + O => cs_67_OBUF_GTS_TRI + ); + cs_66_OBUF_211 : X_BUF + port map ( + I => cs_66_OBUF, + O => cs_66_OBUF_GTS_TRI + ); + cs_65_OBUF_212 : X_BUF + port map ( + I => cs_65_OBUF, + O => cs_65_OBUF_GTS_TRI + ); + cs_64_OBUF_213 : X_BUF + port map ( + I => cs_64_OBUF, + O => cs_64_OBUF_GTS_TRI + ); + cs_63_OBUF_214 : X_BUF + port map ( + I => cs_63_OBUF, + O => cs_63_OBUF_GTS_TRI + ); + cs_62_OBUF_215 : X_BUF + port map ( + I => cs_62_OBUF, + O => cs_62_OBUF_GTS_TRI + ); + cs_61_OBUF_216 : X_BUF + port map ( + I => cs_61_OBUF, + O => cs_61_OBUF_GTS_TRI + ); + cs_60_OBUF_217 : X_BUF + port map ( + I => cs_60_OBUF, + O => cs_60_OBUF_GTS_TRI + ); + cs_59_OBUF_218 : X_BUF + port map ( + I => cs_59_OBUF, + O => cs_59_OBUF_GTS_TRI + ); + cs_58_OBUF_219 : X_BUF + port map ( + I => cs_58_OBUF, + O => cs_58_OBUF_GTS_TRI + ); + cs_57_OBUF_220 : X_BUF + port map ( + I => cs_57_OBUF, + O => cs_57_OBUF_GTS_TRI + ); + cs_56_OBUF_221 : X_BUF + port map ( + I => cs_56_OBUF, + O => cs_56_OBUF_GTS_TRI + ); + cs_55_OBUF_222 : X_BUF + port map ( + I => cs_55_OBUF, + O => cs_55_OBUF_GTS_TRI + ); + cs_54_OBUF_223 : X_BUF + port map ( + I => cs_54_OBUF, + O => cs_54_OBUF_GTS_TRI + ); + cs_53_OBUF_224 : X_BUF + port map ( + I => cs_53_OBUF, + O => cs_53_OBUF_GTS_TRI + ); + cs_52_OBUF_225 : X_BUF + port map ( + I => cs_52_OBUF, + O => cs_52_OBUF_GTS_TRI + ); + cs_51_OBUF_226 : X_BUF + port map ( + I => cs_51_OBUF, + O => cs_51_OBUF_GTS_TRI + ); + cs_50_OBUF_227 : X_BUF + port map ( + I => cs_50_OBUF, + O => cs_50_OBUF_GTS_TRI + ); + cs_49_OBUF_228 : X_BUF + port map ( + I => cs_49_OBUF, + O => cs_49_OBUF_GTS_TRI + ); + cs_48_OBUF_229 : X_BUF + port map ( + I => cs_48_OBUF, + O => cs_48_OBUF_GTS_TRI + ); + cs_47_OBUF_230 : X_BUF + port map ( + I => cs_47_OBUF, + O => cs_47_OBUF_GTS_TRI + ); + cs_46_OBUF_231 : X_BUF + port map ( + I => cs_46_OBUF, + O => cs_46_OBUF_GTS_TRI + ); + cs_45_OBUF_232 : X_BUF + port map ( + I => cs_45_OBUF, + O => cs_45_OBUF_GTS_TRI + ); + cs_44_OBUF_233 : X_BUF + port map ( + I => cs_44_OBUF, + O => cs_44_OBUF_GTS_TRI + ); + cs_43_OBUF_234 : X_BUF + port map ( + I => cs_43_OBUF, + O => cs_43_OBUF_GTS_TRI + ); + cs_42_OBUF_235 : X_BUF + port map ( + I => cs_42_OBUF, + O => cs_42_OBUF_GTS_TRI + ); + cs_41_OBUF_236 : X_BUF + port map ( + I => cs_41_OBUF, + O => cs_41_OBUF_GTS_TRI + ); + cs_40_OBUF_237 : X_BUF + port map ( + I => cs_40_OBUF, + O => cs_40_OBUF_GTS_TRI + ); + cs_39_OBUF_238 : X_BUF + port map ( + I => cs_39_OBUF, + O => cs_39_OBUF_GTS_TRI + ); + cs_38_OBUF_239 : X_BUF + port map ( + I => cs_38_OBUF, + O => cs_38_OBUF_GTS_TRI + ); + cs_37_OBUF_240 : X_BUF + port map ( + I => cs_37_OBUF, + O => cs_37_OBUF_GTS_TRI + ); + cs_36_OBUF_241 : X_BUF + port map ( + I => cs_36_OBUF, + O => cs_36_OBUF_GTS_TRI + ); + cs_35_OBUF_242 : X_BUF + port map ( + I => cs_35_OBUF, + O => cs_35_OBUF_GTS_TRI + ); + cs_34_OBUF_243 : X_BUF + port map ( + I => cs_34_OBUF, + O => cs_34_OBUF_GTS_TRI + ); + cs_33_OBUF_244 : X_BUF + port map ( + I => cs_33_OBUF, + O => cs_33_OBUF_GTS_TRI + ); + cs_32_OBUF_245 : X_BUF + port map ( + I => cs_32_OBUF, + O => cs_32_OBUF_GTS_TRI + ); + cs_31_OBUF_246 : X_BUF + port map ( + I => cs_31_OBUF, + O => cs_31_OBUF_GTS_TRI + ); + cs_30_OBUF_247 : X_BUF + port map ( + I => cs_30_OBUF, + O => cs_30_OBUF_GTS_TRI + ); + cs_29_OBUF_248 : X_BUF + port map ( + I => cs_29_OBUF, + O => cs_29_OBUF_GTS_TRI + ); + cs_28_OBUF_249 : X_BUF + port map ( + I => cs_28_OBUF, + O => cs_28_OBUF_GTS_TRI + ); + cs_27_OBUF_250 : X_BUF + port map ( + I => cs_27_OBUF, + O => cs_27_OBUF_GTS_TRI + ); + cs_26_OBUF_251 : X_BUF + port map ( + I => cs_26_OBUF, + O => cs_26_OBUF_GTS_TRI + ); + cs_25_OBUF_252 : X_BUF + port map ( + I => cs_25_OBUF, + O => cs_25_OBUF_GTS_TRI + ); + cs_24_OBUF_253 : X_BUF + port map ( + I => cs_24_OBUF, + O => cs_24_OBUF_GTS_TRI + ); + cs_23_OBUF_254 : X_BUF + port map ( + I => cs_23_OBUF, + O => cs_23_OBUF_GTS_TRI + ); + cs_22_OBUF_255 : X_BUF + port map ( + I => cs_22_OBUF, + O => cs_22_OBUF_GTS_TRI + ); + cs_21_OBUF_256 : X_BUF + port map ( + I => cs_21_OBUF, + O => cs_21_OBUF_GTS_TRI + ); + cs_20_OBUF_257 : X_BUF + port map ( + I => cs_20_OBUF, + O => cs_20_OBUF_GTS_TRI + ); + cs_19_OBUF_258 : X_BUF + port map ( + I => cs_19_OBUF, + O => cs_19_OBUF_GTS_TRI + ); + cs_18_OBUF_259 : X_BUF + port map ( + I => cs_18_OBUF, + O => cs_18_OBUF_GTS_TRI + ); + cs_17_OBUF_260 : X_BUF + port map ( + I => cs_17_OBUF, + O => cs_17_OBUF_GTS_TRI + ); + cs_16_OBUF_261 : X_BUF + port map ( + I => cs_16_OBUF, + O => cs_16_OBUF_GTS_TRI + ); + cs_15_OBUF_262 : X_BUF + port map ( + I => cs_15_OBUF, + O => cs_15_OBUF_GTS_TRI + ); + cs_14_OBUF_263 : X_BUF + port map ( + I => cs_14_OBUF, + O => cs_14_OBUF_GTS_TRI + ); + cs_13_OBUF_264 : X_BUF + port map ( + I => cs_13_OBUF, + O => cs_13_OBUF_GTS_TRI + ); + cs_12_OBUF_265 : X_BUF + port map ( + I => cs_12_OBUF, + O => cs_12_OBUF_GTS_TRI + ); + cs_11_OBUF_266 : X_BUF + port map ( + I => cs_11_OBUF, + O => cs_11_OBUF_GTS_TRI + ); + cs_10_OBUF_267 : X_BUF + port map ( + I => cs_10_OBUF, + O => cs_10_OBUF_GTS_TRI + ); + cs_9_OBUF_268 : X_BUF + port map ( + I => cs_9_OBUF, + O => cs_9_OBUF_GTS_TRI + ); + cs_8_OBUF_269 : X_BUF + port map ( + I => cs_8_OBUF, + O => cs_8_OBUF_GTS_TRI + ); + cs_7_OBUF_270 : X_BUF + port map ( + I => cs_7_OBUF, + O => cs_7_OBUF_GTS_TRI + ); + cs_6_OBUF_271 : X_BUF + port map ( + I => cs_6_OBUF, + O => cs_6_OBUF_GTS_TRI + ); + cs_5_OBUF_272 : X_BUF + port map ( + I => cs_5_OBUF, + O => cs_5_OBUF_GTS_TRI + ); + cs_4_OBUF_273 : X_BUF + port map ( + I => cs_4_OBUF, + O => cs_4_OBUF_GTS_TRI + ); + cs_3_OBUF_274 : X_BUF + port map ( + I => cs_3_OBUF, + O => cs_3_OBUF_GTS_TRI + ); + cs_2_OBUF_275 : X_BUF + port map ( + I => cs_2_OBUF, + O => cs_2_OBUF_GTS_TRI + ); + cs_1_OBUF_276 : X_BUF + port map ( + I => cs_1_OBUF, + O => cs_1_OBUF_GTS_TRI + ); + dadrL_BU2826 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N18684, + ADR2 => dadrL_N18685, + ADR3 => dadrL_N0, + O => cs_255_OBUF + ); + dadrL_BU2823 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N18685 + ); + dadrL_BU2820 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N18684 + ); + dadrL_BU2815 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N18613, + ADR2 => dadrL_N18614, + ADR3 => dadrL_N0, + O => cs_254_OBUF + ); + dadrL_BU2812 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N18614 + ); + dadrL_BU2809 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N18613 + ); + dadrL_BU2804 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N18542, + ADR2 => dadrL_N18543, + ADR3 => dadrL_N0, + O => cs_253_OBUF + ); + dadrL_BU2801 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N18543 + ); + dadrL_BU2798 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N18542 + ); + dadrL_BU2793 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N18471, + ADR2 => dadrL_N18472, + ADR3 => dadrL_N0, + O => cs_252_OBUF + ); + dadrL_BU2790 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N18472 + ); + dadrL_BU2787 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N18471 + ); + dadrL_BU2782 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N18400, + ADR2 => dadrL_N18401, + ADR3 => dadrL_N0, + O => cs_251_OBUF + ); + dadrL_BU2779 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N18401 + ); + dadrL_BU2776 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N18400 + ); + dadrL_BU2771 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N18329, + ADR2 => dadrL_N18330, + ADR3 => dadrL_N0, + O => cs_250_OBUF + ); + dadrL_BU2768 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N18330 + ); + dadrL_BU2765 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N18329 + ); + dadrL_BU2760 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N18258, + ADR2 => dadrL_N18259, + ADR3 => dadrL_N0, + O => cs_249_OBUF + ); + dadrL_BU2757 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N18259 + ); + dadrL_BU2754 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N18258 + ); + dadrL_BU2749 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N18187, + ADR2 => dadrL_N18188, + ADR3 => dadrL_N0, + O => cs_248_OBUF + ); + dadrL_BU2746 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N18188 + ); + dadrL_BU2743 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N18187 + ); + dadrL_BU2738 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N18116, + ADR2 => dadrL_N18117, + ADR3 => dadrL_N0, + O => cs_247_OBUF + ); + dadrL_BU2735 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N18117 + ); + dadrL_BU2732 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N18116 + ); + dadrL_BU2727 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N18045, + ADR2 => dadrL_N18046, + ADR3 => dadrL_N0, + O => cs_246_OBUF + ); + dadrL_BU2724 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N18046 + ); + dadrL_BU2721 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N18045 + ); + dadrL_BU2716 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N17974, + ADR2 => dadrL_N17975, + ADR3 => dadrL_N0, + O => cs_245_OBUF + ); + dadrL_BU2713 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N17975 + ); + dadrL_BU2710 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N17974 + ); + dadrL_BU2705 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N17903, + ADR2 => dadrL_N17904, + ADR3 => dadrL_N0, + O => cs_244_OBUF + ); + dadrL_BU2702 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N17904 + ); + dadrL_BU2699 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N17903 + ); + dadrL_BU2694 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N17832, + ADR2 => dadrL_N17833, + ADR3 => dadrL_N0, + O => cs_243_OBUF + ); + dadrL_BU2691 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N17833 + ); + dadrL_BU2688 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N17832 + ); + dadrL_BU2683 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N17761, + ADR2 => dadrL_N17762, + ADR3 => dadrL_N0, + O => cs_242_OBUF + ); + dadrL_BU2680 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N17762 + ); + dadrL_BU2677 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N17761 + ); + dadrL_BU2672 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N17690, + ADR2 => dadrL_N17691, + ADR3 => dadrL_N0, + O => cs_241_OBUF + ); + dadrL_BU2669 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N17691 + ); + dadrL_BU2666 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N17690 + ); + dadrL_BU2661 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N17619, + ADR2 => dadrL_N17620, + ADR3 => dadrL_N0, + O => cs_240_OBUF + ); + dadrL_BU2658 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N17620 + ); + dadrL_BU2655 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N17619 + ); + dadrL_BU2650 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N17548, + ADR2 => dadrL_N17549, + ADR3 => dadrL_N0, + O => cs_239_OBUF + ); + dadrL_BU2647 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N17549 + ); + dadrL_BU2644 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N17548 + ); + dadrL_BU2639 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N17477, + ADR2 => dadrL_N17478, + ADR3 => dadrL_N0, + O => cs_238_OBUF + ); + dadrL_BU2636 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N17478 + ); + dadrL_BU2633 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N17477 + ); + dadrL_BU2628 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N17406, + ADR2 => dadrL_N17407, + ADR3 => dadrL_N0, + O => cs_237_OBUF + ); + dadrL_BU2625 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N17407 + ); + dadrL_BU2622 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N17406 + ); + dadrL_BU2617 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N17335, + ADR2 => dadrL_N17336, + ADR3 => dadrL_N0, + O => cs_236_OBUF + ); + dadrL_BU2614 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N17336 + ); + dadrL_BU2611 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N17335 + ); + dadrL_BU2606 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N17264, + ADR2 => dadrL_N17265, + ADR3 => dadrL_N0, + O => cs_235_OBUF + ); + dadrL_BU2603 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N17265 + ); + dadrL_BU2600 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N17264 + ); + dadrL_BU2595 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N17193, + ADR2 => dadrL_N17194, + ADR3 => dadrL_N0, + O => cs_234_OBUF + ); + dadrL_BU2592 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N17194 + ); + dadrL_BU2589 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N17193 + ); + dadrL_BU2584 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N17122, + ADR2 => dadrL_N17123, + ADR3 => dadrL_N0, + O => cs_233_OBUF + ); + dadrL_BU2581 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N17123 + ); + dadrL_BU2578 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N17122 + ); + dadrL_BU2573 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N17051, + ADR2 => dadrL_N17052, + ADR3 => dadrL_N0, + O => cs_232_OBUF + ); + dadrL_BU2570 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N17052 + ); + dadrL_BU2567 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N17051 + ); + dadrL_BU2562 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N16980, + ADR2 => dadrL_N16981, + ADR3 => dadrL_N0, + O => cs_231_OBUF + ); + dadrL_BU2559 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N16981 + ); + dadrL_BU2556 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N16980 + ); + dadrL_BU2551 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N16909, + ADR2 => dadrL_N16910, + ADR3 => dadrL_N0, + O => cs_230_OBUF + ); + dadrL_BU2548 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N16910 + ); + dadrL_BU2545 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N16909 + ); + dadrL_BU2540 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N16838, + ADR2 => dadrL_N16839, + ADR3 => dadrL_N0, + O => cs_229_OBUF + ); + dadrL_BU2537 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N16839 + ); + dadrL_BU2534 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N16838 + ); + dadrL_BU2529 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N16767, + ADR2 => dadrL_N16768, + ADR3 => dadrL_N0, + O => cs_228_OBUF + ); + dadrL_BU2526 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N16768 + ); + dadrL_BU2523 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N16767 + ); + dadrL_BU2518 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N16696, + ADR2 => dadrL_N16697, + ADR3 => dadrL_N0, + O => cs_227_OBUF + ); + dadrL_BU2515 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N16697 + ); + dadrL_BU2512 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N16696 + ); + dadrL_BU2507 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N16625, + ADR2 => dadrL_N16626, + ADR3 => dadrL_N0, + O => cs_226_OBUF + ); + dadrL_BU2504 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N16626 + ); + dadrL_BU2501 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N16625 + ); + dadrL_BU2496 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N16554, + ADR2 => dadrL_N16555, + ADR3 => dadrL_N0, + O => cs_225_OBUF + ); + dadrL_BU2493 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N16555 + ); + dadrL_BU2490 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N16554 + ); + dadrL_BU2485 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N16483, + ADR2 => dadrL_N16484, + ADR3 => dadrL_N0, + O => cs_224_OBUF + ); + dadrL_BU2482 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N16484 + ); + dadrL_BU2479 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N16483 + ); + dadrL_BU2474 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N16412, + ADR2 => dadrL_N16413, + ADR3 => dadrL_N0, + O => cs_223_OBUF + ); + dadrL_BU2471 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N16413 + ); + dadrL_BU2468 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N16412 + ); + dadrL_BU2463 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N16341, + ADR2 => dadrL_N16342, + ADR3 => dadrL_N0, + O => cs_222_OBUF + ); + dadrL_BU2460 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N16342 + ); + dadrL_BU2457 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N16341 + ); + dadrL_BU2452 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N16270, + ADR2 => dadrL_N16271, + ADR3 => dadrL_N0, + O => cs_221_OBUF + ); + dadrL_BU2449 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N16271 + ); + dadrL_BU2446 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N16270 + ); + dadrL_BU2441 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N16199, + ADR2 => dadrL_N16200, + ADR3 => dadrL_N0, + O => cs_220_OBUF + ); + dadrL_BU2438 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N16200 + ); + dadrL_BU2435 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N16199 + ); + dadrL_BU2430 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N16128, + ADR2 => dadrL_N16129, + ADR3 => dadrL_N0, + O => cs_219_OBUF + ); + dadrL_BU2427 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N16129 + ); + dadrL_BU2424 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N16128 + ); + dadrL_BU2419 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N16057, + ADR2 => dadrL_N16058, + ADR3 => dadrL_N0, + O => cs_218_OBUF + ); + dadrL_BU2416 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N16058 + ); + dadrL_BU2413 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N16057 + ); + dadrL_BU2408 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N15986, + ADR2 => dadrL_N15987, + ADR3 => dadrL_N0, + O => cs_217_OBUF + ); + dadrL_BU2405 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N15987 + ); + dadrL_BU2402 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N15986 + ); + dadrL_BU2397 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N15915, + ADR2 => dadrL_N15916, + ADR3 => dadrL_N0, + O => cs_216_OBUF + ); + dadrL_BU2394 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N15916 + ); + dadrL_BU2391 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N15915 + ); + dadrL_BU2386 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N15844, + ADR2 => dadrL_N15845, + ADR3 => dadrL_N0, + O => cs_215_OBUF + ); + dadrL_BU2383 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N15845 + ); + dadrL_BU2380 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N15844 + ); + dadrL_BU2375 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N15773, + ADR2 => dadrL_N15774, + ADR3 => dadrL_N0, + O => cs_214_OBUF + ); + dadrL_BU2372 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N15774 + ); + dadrL_BU2369 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N15773 + ); + dadrL_BU2364 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N15702, + ADR2 => dadrL_N15703, + ADR3 => dadrL_N0, + O => cs_213_OBUF + ); + dadrL_BU2361 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N15703 + ); + dadrL_BU2358 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N15702 + ); + dadrL_BU2353 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N15631, + ADR2 => dadrL_N15632, + ADR3 => dadrL_N0, + O => cs_212_OBUF + ); + dadrL_BU2350 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N15632 + ); + dadrL_BU2347 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N15631 + ); + dadrL_BU2342 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N15560, + ADR2 => dadrL_N15561, + ADR3 => dadrL_N0, + O => cs_211_OBUF + ); + dadrL_BU2339 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N15561 + ); + dadrL_BU2336 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N15560 + ); + dadrL_BU2331 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N15489, + ADR2 => dadrL_N15490, + ADR3 => dadrL_N0, + O => cs_210_OBUF + ); + dadrL_BU2328 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N15490 + ); + dadrL_BU2325 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N15489 + ); + dadrL_BU2320 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N15418, + ADR2 => dadrL_N15419, + ADR3 => dadrL_N0, + O => cs_209_OBUF + ); + dadrL_BU2317 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N15419 + ); + dadrL_BU2314 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N15418 + ); + dadrL_BU2309 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N15347, + ADR2 => dadrL_N15348, + ADR3 => dadrL_N0, + O => cs_208_OBUF + ); + dadrL_BU2306 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N15348 + ); + dadrL_BU2303 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N15347 + ); + dadrL_BU2298 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N15276, + ADR2 => dadrL_N15277, + ADR3 => dadrL_N0, + O => cs_207_OBUF + ); + dadrL_BU2295 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N15277 + ); + dadrL_BU2292 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N15276 + ); + dadrL_BU2287 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N15205, + ADR2 => dadrL_N15206, + ADR3 => dadrL_N0, + O => cs_206_OBUF + ); + dadrL_BU2284 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N15206 + ); + dadrL_BU2281 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N15205 + ); + dadrL_BU2276 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N15134, + ADR2 => dadrL_N15135, + ADR3 => dadrL_N0, + O => cs_205_OBUF + ); + dadrL_BU2273 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N15135 + ); + dadrL_BU2270 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N15134 + ); + dadrL_BU2265 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N15063, + ADR2 => dadrL_N15064, + ADR3 => dadrL_N0, + O => cs_204_OBUF + ); + dadrL_BU2262 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N15064 + ); + dadrL_BU2259 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N15063 + ); + dadrL_BU2254 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N14992, + ADR2 => dadrL_N14993, + ADR3 => dadrL_N0, + O => cs_203_OBUF + ); + dadrL_BU2251 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N14993 + ); + dadrL_BU2248 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N14992 + ); + dadrL_BU2243 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N14921, + ADR2 => dadrL_N14922, + ADR3 => dadrL_N0, + O => cs_202_OBUF + ); + dadrL_BU2240 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N14922 + ); + dadrL_BU2237 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N14921 + ); + dadrL_BU2232 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N14850, + ADR2 => dadrL_N14851, + ADR3 => dadrL_N0, + O => cs_201_OBUF + ); + dadrL_BU2229 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N14851 + ); + dadrL_BU2226 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N14850 + ); + dadrL_BU2221 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N14779, + ADR2 => dadrL_N14780, + ADR3 => dadrL_N0, + O => cs_200_OBUF + ); + dadrL_BU2218 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N14780 + ); + dadrL_BU2215 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N14779 + ); + dadrL_BU2210 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N14708, + ADR2 => dadrL_N14709, + ADR3 => dadrL_N0, + O => cs_199_OBUF + ); + dadrL_BU2207 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N14709 + ); + dadrL_BU2204 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N14708 + ); + dadrL_BU2199 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N14637, + ADR2 => dadrL_N14638, + ADR3 => dadrL_N0, + O => cs_198_OBUF + ); + dadrL_BU2196 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N14638 + ); + dadrL_BU2193 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N14637 + ); + dadrL_BU2188 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N14566, + ADR2 => dadrL_N14567, + ADR3 => dadrL_N0, + O => cs_197_OBUF + ); + dadrL_BU2185 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N14567 + ); + dadrL_BU2182 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N14566 + ); + dadrL_BU2177 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N14495, + ADR2 => dadrL_N14496, + ADR3 => dadrL_N0, + O => cs_196_OBUF + ); + dadrL_BU2174 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N14496 + ); + dadrL_BU2171 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N14495 + ); + dadrL_BU2166 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N14424, + ADR2 => dadrL_N14425, + ADR3 => dadrL_N0, + O => cs_195_OBUF + ); + dadrL_BU2163 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N14425 + ); + dadrL_BU2160 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N14424 + ); + dadrL_BU2155 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N14353, + ADR2 => dadrL_N14354, + ADR3 => dadrL_N0, + O => cs_194_OBUF + ); + dadrL_BU2152 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N14354 + ); + dadrL_BU2149 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N14353 + ); + dadrL_BU2144 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N14282, + ADR2 => dadrL_N14283, + ADR3 => dadrL_N0, + O => cs_193_OBUF + ); + dadrL_BU2141 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N14283 + ); + dadrL_BU2138 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N14282 + ); + dadrL_BU2133 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N14211, + ADR2 => dadrL_N14212, + ADR3 => dadrL_N0, + O => cs_192_OBUF + ); + dadrL_BU2130 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N14212 + ); + dadrL_BU2127 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N14211 + ); + dadrL_BU2122 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N14140, + ADR2 => dadrL_N14141, + ADR3 => dadrL_N0, + O => cs_191_OBUF + ); + dadrL_BU2119 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N14141 + ); + dadrL_BU2116 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N14140 + ); + dadrL_BU2111 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N14069, + ADR2 => dadrL_N14070, + ADR3 => dadrL_N0, + O => cs_190_OBUF + ); + dadrL_BU2108 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N14070 + ); + dadrL_BU2105 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N14069 + ); + dadrL_BU2100 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N13998, + ADR2 => dadrL_N13999, + ADR3 => dadrL_N0, + O => cs_189_OBUF + ); + dadrL_BU2097 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N13999 + ); + dadrL_BU2094 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N13998 + ); + dadrL_BU2089 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N13927, + ADR2 => dadrL_N13928, + ADR3 => dadrL_N0, + O => cs_188_OBUF + ); + dadrL_BU2086 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N13928 + ); + dadrL_BU2083 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N13927 + ); + dadrL_BU2078 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N13856, + ADR2 => dadrL_N13857, + ADR3 => dadrL_N0, + O => cs_187_OBUF + ); + dadrL_BU2075 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N13857 + ); + dadrL_BU2072 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N13856 + ); + dadrL_BU2067 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N13785, + ADR2 => dadrL_N13786, + ADR3 => dadrL_N0, + O => cs_186_OBUF + ); + dadrL_BU2064 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N13786 + ); + dadrL_BU2061 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N13785 + ); + dadrL_BU2056 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N13714, + ADR2 => dadrL_N13715, + ADR3 => dadrL_N0, + O => cs_185_OBUF + ); + dadrL_BU2053 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N13715 + ); + dadrL_BU2050 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N13714 + ); + dadrL_BU2045 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N13643, + ADR2 => dadrL_N13644, + ADR3 => dadrL_N0, + O => cs_184_OBUF + ); + dadrL_BU2042 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N13644 + ); + dadrL_BU2039 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N13643 + ); + dadrL_BU2034 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N13572, + ADR2 => dadrL_N13573, + ADR3 => dadrL_N0, + O => cs_183_OBUF + ); + dadrL_BU2031 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N13573 + ); + dadrL_BU2028 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N13572 + ); + dadrL_BU2023 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N13501, + ADR2 => dadrL_N13502, + ADR3 => dadrL_N0, + O => cs_182_OBUF + ); + dadrL_BU2020 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N13502 + ); + dadrL_BU2017 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N13501 + ); + dadrL_BU2012 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N13430, + ADR2 => dadrL_N13431, + ADR3 => dadrL_N0, + O => cs_181_OBUF + ); + dadrL_BU2009 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N13431 + ); + dadrL_BU2006 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N13430 + ); + dadrL_BU2001 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N13359, + ADR2 => dadrL_N13360, + ADR3 => dadrL_N0, + O => cs_180_OBUF + ); + dadrL_BU1998 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N13360 + ); + dadrL_BU1995 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N13359 + ); + dadrL_BU1990 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N13288, + ADR2 => dadrL_N13289, + ADR3 => dadrL_N0, + O => cs_179_OBUF + ); + dadrL_BU1987 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N13289 + ); + dadrL_BU1984 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N13288 + ); + dadrL_BU1979 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N13217, + ADR2 => dadrL_N13218, + ADR3 => dadrL_N0, + O => cs_178_OBUF + ); + dadrL_BU1976 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N13218 + ); + dadrL_BU1973 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N13217 + ); + dadrL_BU1968 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N13146, + ADR2 => dadrL_N13147, + ADR3 => dadrL_N0, + O => cs_177_OBUF + ); + dadrL_BU1965 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N13147 + ); + dadrL_BU1962 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N13146 + ); + dadrL_BU1957 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N13075, + ADR2 => dadrL_N13076, + ADR3 => dadrL_N0, + O => cs_176_OBUF + ); + dadrL_BU1954 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N13076 + ); + dadrL_BU1951 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N13075 + ); + dadrL_BU1946 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N13004, + ADR2 => dadrL_N13005, + ADR3 => dadrL_N0, + O => cs_175_OBUF + ); + dadrL_BU1943 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N13005 + ); + dadrL_BU1940 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N13004 + ); + dadrL_BU1935 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N12933, + ADR2 => dadrL_N12934, + ADR3 => dadrL_N0, + O => cs_174_OBUF + ); + dadrL_BU1932 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N12934 + ); + dadrL_BU1929 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N12933 + ); + dadrL_BU1924 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N12862, + ADR2 => dadrL_N12863, + ADR3 => dadrL_N0, + O => cs_173_OBUF + ); + dadrL_BU1921 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N12863 + ); + dadrL_BU1918 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N12862 + ); + dadrL_BU1913 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N12791, + ADR2 => dadrL_N12792, + ADR3 => dadrL_N0, + O => cs_172_OBUF + ); + dadrL_BU1910 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N12792 + ); + dadrL_BU1907 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N12791 + ); + dadrL_BU1902 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N12720, + ADR2 => dadrL_N12721, + ADR3 => dadrL_N0, + O => cs_171_OBUF + ); + dadrL_BU1899 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N12721 + ); + dadrL_BU1896 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N12720 + ); + dadrL_BU1891 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N12649, + ADR2 => dadrL_N12650, + ADR3 => dadrL_N0, + O => cs_170_OBUF + ); + dadrL_BU1888 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N12650 + ); + dadrL_BU1885 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N12649 + ); + dadrL_BU1880 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N12578, + ADR2 => dadrL_N12579, + ADR3 => dadrL_N0, + O => cs_169_OBUF + ); + dadrL_BU1877 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N12579 + ); + dadrL_BU1874 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N12578 + ); + dadrL_BU1869 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N12507, + ADR2 => dadrL_N12508, + ADR3 => dadrL_N0, + O => cs_168_OBUF + ); + dadrL_BU1866 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N12508 + ); + dadrL_BU1863 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N12507 + ); + dadrL_BU1858 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N12436, + ADR2 => dadrL_N12437, + ADR3 => dadrL_N0, + O => cs_167_OBUF + ); + dadrL_BU1855 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N12437 + ); + dadrL_BU1852 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N12436 + ); + dadrL_BU1847 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N12365, + ADR2 => dadrL_N12366, + ADR3 => dadrL_N0, + O => cs_166_OBUF + ); + dadrL_BU1844 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N12366 + ); + dadrL_BU1841 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N12365 + ); + dadrL_BU1836 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N12294, + ADR2 => dadrL_N12295, + ADR3 => dadrL_N0, + O => cs_165_OBUF + ); + dadrL_BU1833 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N12295 + ); + dadrL_BU1830 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N12294 + ); + dadrL_BU1825 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N12223, + ADR2 => dadrL_N12224, + ADR3 => dadrL_N0, + O => cs_164_OBUF + ); + dadrL_BU1822 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N12224 + ); + dadrL_BU1819 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N12223 + ); + dadrL_BU1814 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N12152, + ADR2 => dadrL_N12153, + ADR3 => dadrL_N0, + O => cs_163_OBUF + ); + dadrL_BU1811 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N12153 + ); + dadrL_BU1808 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N12152 + ); + dadrL_BU1803 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N12081, + ADR2 => dadrL_N12082, + ADR3 => dadrL_N0, + O => cs_162_OBUF + ); + dadrL_BU1800 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N12082 + ); + dadrL_BU1797 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N12081 + ); + dadrL_BU1792 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N12010, + ADR2 => dadrL_N12011, + ADR3 => dadrL_N0, + O => cs_161_OBUF + ); + dadrL_BU1789 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N12011 + ); + dadrL_BU1786 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N12010 + ); + dadrL_BU1781 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N11939, + ADR2 => dadrL_N11940, + ADR3 => dadrL_N0, + O => cs_160_OBUF + ); + dadrL_BU1778 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N11940 + ); + dadrL_BU1775 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N11939 + ); + dadrL_BU1770 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N11868, + ADR2 => dadrL_N11869, + ADR3 => dadrL_N0, + O => cs_159_OBUF + ); + dadrL_BU1767 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N11869 + ); + dadrL_BU1764 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N11868 + ); + dadrL_BU1759 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N11797, + ADR2 => dadrL_N11798, + ADR3 => dadrL_N0, + O => cs_158_OBUF + ); + dadrL_BU1756 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N11798 + ); + dadrL_BU1753 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N11797 + ); + dadrL_BU1748 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N11726, + ADR2 => dadrL_N11727, + ADR3 => dadrL_N0, + O => cs_157_OBUF + ); + dadrL_BU1745 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N11727 + ); + dadrL_BU1742 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N11726 + ); + dadrL_BU1737 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N11655, + ADR2 => dadrL_N11656, + ADR3 => dadrL_N0, + O => cs_156_OBUF + ); + dadrL_BU1734 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N11656 + ); + dadrL_BU1731 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N11655 + ); + dadrL_BU1726 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N11584, + ADR2 => dadrL_N11585, + ADR3 => dadrL_N0, + O => cs_155_OBUF + ); + dadrL_BU1723 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N11585 + ); + dadrL_BU1720 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N11584 + ); + dadrL_BU1715 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N11513, + ADR2 => dadrL_N11514, + ADR3 => dadrL_N0, + O => cs_154_OBUF + ); + dadrL_BU1712 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N11514 + ); + dadrL_BU1709 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N11513 + ); + dadrL_BU1704 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N11442, + ADR2 => dadrL_N11443, + ADR3 => dadrL_N0, + O => cs_153_OBUF + ); + dadrL_BU1701 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N11443 + ); + dadrL_BU1698 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N11442 + ); + dadrL_BU1693 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N11371, + ADR2 => dadrL_N11372, + ADR3 => dadrL_N0, + O => cs_152_OBUF + ); + dadrL_BU1690 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N11372 + ); + dadrL_BU1687 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N11371 + ); + dadrL_BU1682 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N11300, + ADR2 => dadrL_N11301, + ADR3 => dadrL_N0, + O => cs_151_OBUF + ); + dadrL_BU1679 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N11301 + ); + dadrL_BU1676 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N11300 + ); + dadrL_BU1671 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N11229, + ADR2 => dadrL_N11230, + ADR3 => dadrL_N0, + O => cs_150_OBUF + ); + dadrL_BU1668 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N11230 + ); + dadrL_BU1665 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N11229 + ); + dadrL_BU1660 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N11158, + ADR2 => dadrL_N11159, + ADR3 => dadrL_N0, + O => cs_149_OBUF + ); + dadrL_BU1657 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N11159 + ); + dadrL_BU1654 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N11158 + ); + dadrL_BU1649 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N11087, + ADR2 => dadrL_N11088, + ADR3 => dadrL_N0, + O => cs_148_OBUF + ); + dadrL_BU1646 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N11088 + ); + dadrL_BU1643 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N11087 + ); + dadrL_BU1638 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N11016, + ADR2 => dadrL_N11017, + ADR3 => dadrL_N0, + O => cs_147_OBUF + ); + dadrL_BU1635 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N11017 + ); + dadrL_BU1632 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N11016 + ); + dadrL_BU1627 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N10945, + ADR2 => dadrL_N10946, + ADR3 => dadrL_N0, + O => cs_146_OBUF + ); + dadrL_BU1624 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N10946 + ); + dadrL_BU1621 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N10945 + ); + dadrL_BU1616 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N10874, + ADR2 => dadrL_N10875, + ADR3 => dadrL_N0, + O => cs_145_OBUF + ); + dadrL_BU1613 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N10875 + ); + dadrL_BU1610 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N10874 + ); + dadrL_BU1605 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N10803, + ADR2 => dadrL_N10804, + ADR3 => dadrL_N0, + O => cs_144_OBUF + ); + dadrL_BU1602 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N10804 + ); + dadrL_BU1599 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N10803 + ); + dadrL_BU1594 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N10732, + ADR2 => dadrL_N10733, + ADR3 => dadrL_N0, + O => cs_143_OBUF + ); + dadrL_BU1591 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N10733 + ); + dadrL_BU1588 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N10732 + ); + dadrL_BU1583 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N10661, + ADR2 => dadrL_N10662, + ADR3 => dadrL_N0, + O => cs_142_OBUF + ); + dadrL_BU1580 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N10662 + ); + dadrL_BU1577 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N10661 + ); + dadrL_BU1572 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N10590, + ADR2 => dadrL_N10591, + ADR3 => dadrL_N0, + O => cs_141_OBUF + ); + dadrL_BU1569 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N10591 + ); + dadrL_BU1566 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N10590 + ); + dadrL_BU1561 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N10519, + ADR2 => dadrL_N10520, + ADR3 => dadrL_N0, + O => cs_140_OBUF + ); + dadrL_BU1558 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N10520 + ); + dadrL_BU1555 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N10519 + ); + dadrL_BU1550 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N10448, + ADR2 => dadrL_N10449, + ADR3 => dadrL_N0, + O => cs_139_OBUF + ); + dadrL_BU1547 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N10449 + ); + dadrL_BU1544 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N10448 + ); + dadrL_BU1539 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N10377, + ADR2 => dadrL_N10378, + ADR3 => dadrL_N0, + O => cs_138_OBUF + ); + dadrL_BU1536 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N10378 + ); + dadrL_BU1533 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N10377 + ); + dadrL_BU1528 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N10306, + ADR2 => dadrL_N10307, + ADR3 => dadrL_N0, + O => cs_137_OBUF + ); + dadrL_BU1525 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N10307 + ); + dadrL_BU1522 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N10306 + ); + dadrL_BU1517 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N10235, + ADR2 => dadrL_N10236, + ADR3 => dadrL_N0, + O => cs_136_OBUF + ); + dadrL_BU1514 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N10236 + ); + dadrL_BU1511 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N10235 + ); + dadrL_BU1506 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N10164, + ADR2 => dadrL_N10165, + ADR3 => dadrL_N0, + O => cs_135_OBUF + ); + dadrL_BU1503 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N10165 + ); + dadrL_BU1500 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N10164 + ); + dadrL_BU1495 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N10093, + ADR2 => dadrL_N10094, + ADR3 => dadrL_N0, + O => cs_134_OBUF + ); + dadrL_BU1492 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N10094 + ); + dadrL_BU1489 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N10093 + ); + dadrL_BU1484 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N10022, + ADR2 => dadrL_N10023, + ADR3 => dadrL_N0, + O => cs_133_OBUF + ); + dadrL_BU1481 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N10023 + ); + dadrL_BU1478 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N10022 + ); + dadrL_BU1473 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N9951, + ADR2 => dadrL_N9952, + ADR3 => dadrL_N0, + O => cs_132_OBUF + ); + dadrL_BU1470 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N9952 + ); + dadrL_BU1467 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N9951 + ); + dadrL_BU1462 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N9880, + ADR2 => dadrL_N9881, + ADR3 => dadrL_N0, + O => cs_131_OBUF + ); + dadrL_BU1459 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N9881 + ); + dadrL_BU1456 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N9880 + ); + dadrL_BU1451 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N9809, + ADR2 => dadrL_N9810, + ADR3 => dadrL_N0, + O => cs_130_OBUF + ); + dadrL_BU1448 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N9810 + ); + dadrL_BU1445 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N9809 + ); + dadrL_BU1440 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N9738, + ADR2 => dadrL_N9739, + ADR3 => dadrL_N0, + O => cs_129_OBUF + ); + dadrL_BU1437 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N9739 + ); + dadrL_BU1434 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N9738 + ); + dadrL_BU1429 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N9667, + ADR2 => dadrL_N9668, + ADR3 => dadrL_N0, + O => cs_128_OBUF + ); + dadrL_BU1426 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N9668 + ); + dadrL_BU1423 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N9667 + ); + dadrL_BU1418 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N9596, + ADR2 => dadrL_N9597, + ADR3 => dadrL_N0, + O => cs_127_OBUF + ); + dadrL_BU1415 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N9597 + ); + dadrL_BU1412 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N9596 + ); + dadrL_BU1407 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N9525, + ADR2 => dadrL_N9526, + ADR3 => dadrL_N0, + O => cs_126_OBUF + ); + dadrL_BU1404 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N9526 + ); + dadrL_BU1401 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N9525 + ); + dadrL_BU1396 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N9454, + ADR2 => dadrL_N9455, + ADR3 => dadrL_N0, + O => cs_125_OBUF + ); + dadrL_BU1393 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N9455 + ); + dadrL_BU1390 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N9454 + ); + dadrL_BU1385 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N9383, + ADR2 => dadrL_N9384, + ADR3 => dadrL_N0, + O => cs_124_OBUF + ); + dadrL_BU1382 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N9384 + ); + dadrL_BU1379 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N9383 + ); + dadrL_BU1374 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N9312, + ADR2 => dadrL_N9313, + ADR3 => dadrL_N0, + O => cs_123_OBUF + ); + dadrL_BU1371 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N9313 + ); + dadrL_BU1368 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N9312 + ); + dadrL_BU1363 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N9241, + ADR2 => dadrL_N9242, + ADR3 => dadrL_N0, + O => cs_122_OBUF + ); + dadrL_BU1360 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N9242 + ); + dadrL_BU1357 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N9241 + ); + dadrL_BU1352 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N9170, + ADR2 => dadrL_N9171, + ADR3 => dadrL_N0, + O => cs_121_OBUF + ); + dadrL_BU1349 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N9171 + ); + dadrL_BU1346 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N9170 + ); + dadrL_BU1341 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N9099, + ADR2 => dadrL_N9100, + ADR3 => dadrL_N0, + O => cs_120_OBUF + ); + dadrL_BU1338 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N9100 + ); + dadrL_BU1335 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N9099 + ); + dadrL_BU1330 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N9028, + ADR2 => dadrL_N9029, + ADR3 => dadrL_N0, + O => cs_119_OBUF + ); + dadrL_BU1327 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N9029 + ); + dadrL_BU1324 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N9028 + ); + dadrL_BU1319 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N8957, + ADR2 => dadrL_N8958, + ADR3 => dadrL_N0, + O => cs_118_OBUF + ); + dadrL_BU1316 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N8958 + ); + dadrL_BU1313 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N8957 + ); + dadrL_BU1308 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N8886, + ADR2 => dadrL_N8887, + ADR3 => dadrL_N0, + O => cs_117_OBUF + ); + dadrL_BU1305 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N8887 + ); + dadrL_BU1302 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N8886 + ); + dadrL_BU1297 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N8815, + ADR2 => dadrL_N8816, + ADR3 => dadrL_N0, + O => cs_116_OBUF + ); + dadrL_BU1294 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N8816 + ); + dadrL_BU1291 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N8815 + ); + dadrL_BU1286 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N8744, + ADR2 => dadrL_N8745, + ADR3 => dadrL_N0, + O => cs_115_OBUF + ); + dadrL_BU1283 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N8745 + ); + dadrL_BU1280 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N8744 + ); + dadrL_BU1275 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N8673, + ADR2 => dadrL_N8674, + ADR3 => dadrL_N0, + O => cs_114_OBUF + ); + dadrL_BU1272 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N8674 + ); + dadrL_BU1269 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N8673 + ); + dadrL_BU1264 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N8602, + ADR2 => dadrL_N8603, + ADR3 => dadrL_N0, + O => cs_113_OBUF + ); + dadrL_BU1261 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N8603 + ); + dadrL_BU1258 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N8602 + ); + dadrL_BU1253 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N8531, + ADR2 => dadrL_N8532, + ADR3 => dadrL_N0, + O => cs_112_OBUF + ); + dadrL_BU1250 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N8532 + ); + dadrL_BU1247 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N8531 + ); + dadrL_BU1242 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N8460, + ADR2 => dadrL_N8461, + ADR3 => dadrL_N0, + O => cs_111_OBUF + ); + dadrL_BU1239 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N8461 + ); + dadrL_BU1236 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N8460 + ); + dadrL_BU1231 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N8389, + ADR2 => dadrL_N8390, + ADR3 => dadrL_N0, + O => cs_110_OBUF + ); + dadrL_BU1228 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N8390 + ); + dadrL_BU1225 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N8389 + ); + dadrL_BU1220 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N8318, + ADR2 => dadrL_N8319, + ADR3 => dadrL_N0, + O => cs_109_OBUF + ); + dadrL_BU1217 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N8319 + ); + dadrL_BU1214 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N8318 + ); + dadrL_BU1209 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N8247, + ADR2 => dadrL_N8248, + ADR3 => dadrL_N0, + O => cs_108_OBUF + ); + dadrL_BU1206 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N8248 + ); + dadrL_BU1203 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N8247 + ); + dadrL_BU1198 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N8176, + ADR2 => dadrL_N8177, + ADR3 => dadrL_N0, + O => cs_107_OBUF + ); + dadrL_BU1195 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N8177 + ); + dadrL_BU1192 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N8176 + ); + dadrL_BU1187 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N8105, + ADR2 => dadrL_N8106, + ADR3 => dadrL_N0, + O => cs_106_OBUF + ); + dadrL_BU1184 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N8106 + ); + dadrL_BU1181 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N8105 + ); + dadrL_BU1176 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N8034, + ADR2 => dadrL_N8035, + ADR3 => dadrL_N0, + O => cs_105_OBUF + ); + dadrL_BU1173 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N8035 + ); + dadrL_BU1170 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N8034 + ); + dadrL_BU1165 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N7963, + ADR2 => dadrL_N7964, + ADR3 => dadrL_N0, + O => cs_104_OBUF + ); + dadrL_BU1162 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N7964 + ); + dadrL_BU1159 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N7963 + ); + dadrL_BU1154 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N7892, + ADR2 => dadrL_N7893, + ADR3 => dadrL_N0, + O => cs_103_OBUF + ); + dadrL_BU1151 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N7893 + ); + dadrL_BU1148 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N7892 + ); + dadrL_BU1143 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N7821, + ADR2 => dadrL_N7822, + ADR3 => dadrL_N0, + O => cs_102_OBUF + ); + dadrL_BU1140 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N7822 + ); + dadrL_BU1137 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N7821 + ); + dadrL_BU1132 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N7750, + ADR2 => dadrL_N7751, + ADR3 => dadrL_N0, + O => cs_101_OBUF + ); + dadrL_BU1129 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N7751 + ); + dadrL_BU1126 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N7750 + ); + dadrL_BU1121 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N7679, + ADR2 => dadrL_N7680, + ADR3 => dadrL_N0, + O => cs_100_OBUF + ); + dadrL_BU1118 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N7680 + ); + dadrL_BU1115 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N7679 + ); + dadrL_BU1110 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N7608, + ADR2 => dadrL_N7609, + ADR3 => dadrL_N0, + O => cs_99_OBUF + ); + dadrL_BU1107 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N7609 + ); + dadrL_BU1104 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N7608 + ); + dadrL_BU1099 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N7537, + ADR2 => dadrL_N7538, + ADR3 => dadrL_N0, + O => cs_98_OBUF + ); + dadrL_BU1096 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N7538 + ); + dadrL_BU1093 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N7537 + ); + dadrL_BU1088 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N7466, + ADR2 => dadrL_N7467, + ADR3 => dadrL_N0, + O => cs_97_OBUF + ); + dadrL_BU1085 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N7467 + ); + dadrL_BU1082 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N7466 + ); + dadrL_BU1077 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N7395, + ADR2 => dadrL_N7396, + ADR3 => dadrL_N0, + O => cs_96_OBUF + ); + dadrL_BU1074 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N7396 + ); + dadrL_BU1071 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N7395 + ); + dadrL_BU1066 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N7324, + ADR2 => dadrL_N7325, + ADR3 => dadrL_N0, + O => cs_95_OBUF + ); + dadrL_BU1063 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N7325 + ); + dadrL_BU1060 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N7324 + ); + dadrL_BU1055 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N7253, + ADR2 => dadrL_N7254, + ADR3 => dadrL_N0, + O => cs_94_OBUF + ); + dadrL_BU1052 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N7254 + ); + dadrL_BU1049 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N7253 + ); + dadrL_BU1044 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N7182, + ADR2 => dadrL_N7183, + ADR3 => dadrL_N0, + O => cs_93_OBUF + ); + dadrL_BU1041 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N7183 + ); + dadrL_BU1038 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N7182 + ); + dadrL_BU1033 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N7111, + ADR2 => dadrL_N7112, + ADR3 => dadrL_N0, + O => cs_92_OBUF + ); + dadrL_BU1030 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N7112 + ); + dadrL_BU1027 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N7111 + ); + dadrL_BU1022 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N7040, + ADR2 => dadrL_N7041, + ADR3 => dadrL_N0, + O => cs_91_OBUF + ); + dadrL_BU1019 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N7041 + ); + dadrL_BU1016 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N7040 + ); + dadrL_BU1011 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N6969, + ADR2 => dadrL_N6970, + ADR3 => dadrL_N0, + O => cs_90_OBUF + ); + dadrL_BU1008 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N6970 + ); + dadrL_BU1005 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N6969 + ); + dadrL_BU1000 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N6898, + ADR2 => dadrL_N6899, + ADR3 => dadrL_N0, + O => cs_89_OBUF + ); + dadrL_BU997 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N6899 + ); + dadrL_BU994 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N6898 + ); + dadrL_BU989 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N6827, + ADR2 => dadrL_N6828, + ADR3 => dadrL_N0, + O => cs_88_OBUF + ); + dadrL_BU986 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N6828 + ); + dadrL_BU983 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N6827 + ); + dadrL_BU978 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N6756, + ADR2 => dadrL_N6757, + ADR3 => dadrL_N0, + O => cs_87_OBUF + ); + dadrL_BU975 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N6757 + ); + dadrL_BU972 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N6756 + ); + dadrL_BU967 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N6685, + ADR2 => dadrL_N6686, + ADR3 => dadrL_N0, + O => cs_86_OBUF + ); + dadrL_BU964 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N6686 + ); + dadrL_BU961 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N6685 + ); + dadrL_BU956 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N6614, + ADR2 => dadrL_N6615, + ADR3 => dadrL_N0, + O => cs_85_OBUF + ); + dadrL_BU953 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N6615 + ); + dadrL_BU950 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N6614 + ); + dadrL_BU945 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N6543, + ADR2 => dadrL_N6544, + ADR3 => dadrL_N0, + O => cs_84_OBUF + ); + dadrL_BU942 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N6544 + ); + dadrL_BU939 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N6543 + ); + dadrL_BU934 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N6472, + ADR2 => dadrL_N6473, + ADR3 => dadrL_N0, + O => cs_83_OBUF + ); + dadrL_BU931 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N6473 + ); + dadrL_BU928 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N6472 + ); + dadrL_BU923 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N6401, + ADR2 => dadrL_N6402, + ADR3 => dadrL_N0, + O => cs_82_OBUF + ); + dadrL_BU920 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N6402 + ); + dadrL_BU917 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N6401 + ); + dadrL_BU912 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N6330, + ADR2 => dadrL_N6331, + ADR3 => dadrL_N0, + O => cs_81_OBUF + ); + dadrL_BU909 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N6331 + ); + dadrL_BU906 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N6330 + ); + dadrL_BU901 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N6259, + ADR2 => dadrL_N6260, + ADR3 => dadrL_N0, + O => cs_80_OBUF + ); + dadrL_BU898 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N6260 + ); + dadrL_BU895 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N6259 + ); + dadrL_BU890 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N6188, + ADR2 => dadrL_N6189, + ADR3 => dadrL_N0, + O => cs_79_OBUF + ); + dadrL_BU887 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N6189 + ); + dadrL_BU884 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N6188 + ); + dadrL_BU879 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N6117, + ADR2 => dadrL_N6118, + ADR3 => dadrL_N0, + O => cs_78_OBUF + ); + dadrL_BU876 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N6118 + ); + dadrL_BU873 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N6117 + ); + dadrL_BU868 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N6046, + ADR2 => dadrL_N6047, + ADR3 => dadrL_N0, + O => cs_77_OBUF + ); + dadrL_BU865 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N6047 + ); + dadrL_BU862 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N6046 + ); + dadrL_BU857 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N5975, + ADR2 => dadrL_N5976, + ADR3 => dadrL_N0, + O => cs_76_OBUF + ); + dadrL_BU854 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N5976 + ); + dadrL_BU851 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N5975 + ); + dadrL_BU846 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N5904, + ADR2 => dadrL_N5905, + ADR3 => dadrL_N0, + O => cs_75_OBUF + ); + dadrL_BU843 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N5905 + ); + dadrL_BU840 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N5904 + ); + dadrL_BU835 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N5833, + ADR2 => dadrL_N5834, + ADR3 => dadrL_N0, + O => cs_74_OBUF + ); + dadrL_BU832 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N5834 + ); + dadrL_BU829 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N5833 + ); + dadrL_BU824 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N5762, + ADR2 => dadrL_N5763, + ADR3 => dadrL_N0, + O => cs_73_OBUF + ); + dadrL_BU821 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N5763 + ); + dadrL_BU818 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N5762 + ); + dadrL_BU813 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N5691, + ADR2 => dadrL_N5692, + ADR3 => dadrL_N0, + O => cs_72_OBUF + ); + dadrL_BU810 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N5692 + ); + dadrL_BU807 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N5691 + ); + dadrL_BU802 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N5620, + ADR2 => dadrL_N5621, + ADR3 => dadrL_N0, + O => cs_71_OBUF + ); + dadrL_BU799 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N5621 + ); + dadrL_BU796 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N5620 + ); + dadrL_BU791 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N5549, + ADR2 => dadrL_N5550, + ADR3 => dadrL_N0, + O => cs_70_OBUF + ); + dadrL_BU788 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N5550 + ); + dadrL_BU785 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N5549 + ); + dadrL_BU780 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N5478, + ADR2 => dadrL_N5479, + ADR3 => dadrL_N0, + O => cs_69_OBUF + ); + dadrL_BU777 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N5479 + ); + dadrL_BU774 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N5478 + ); + dadrL_BU769 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N5407, + ADR2 => dadrL_N5408, + ADR3 => dadrL_N0, + O => cs_68_OBUF + ); + dadrL_BU766 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N5408 + ); + dadrL_BU763 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N5407 + ); + dadrL_BU758 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N5336, + ADR2 => dadrL_N5337, + ADR3 => dadrL_N0, + O => cs_67_OBUF + ); + dadrL_BU755 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N5337 + ); + dadrL_BU752 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N5336 + ); + dadrL_BU747 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N5265, + ADR2 => dadrL_N5266, + ADR3 => dadrL_N0, + O => cs_66_OBUF + ); + dadrL_BU744 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N5266 + ); + dadrL_BU741 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N5265 + ); + dadrL_BU736 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N5194, + ADR2 => dadrL_N5195, + ADR3 => dadrL_N0, + O => cs_65_OBUF + ); + dadrL_BU733 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N5195 + ); + dadrL_BU730 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N5194 + ); + dadrL_BU725 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N5123, + ADR2 => dadrL_N5124, + ADR3 => dadrL_N0, + O => cs_64_OBUF + ); + dadrL_BU722 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N5124 + ); + dadrL_BU719 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N5123 + ); + dadrL_BU714 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N5052, + ADR2 => dadrL_N5053, + ADR3 => dadrL_N0, + O => cs_63_OBUF + ); + dadrL_BU711 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N5053 + ); + dadrL_BU708 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N5052 + ); + dadrL_BU703 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N4981, + ADR2 => dadrL_N4982, + ADR3 => dadrL_N0, + O => cs_62_OBUF + ); + dadrL_BU700 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N4982 + ); + dadrL_BU697 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N4981 + ); + dadrL_BU692 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N4910, + ADR2 => dadrL_N4911, + ADR3 => dadrL_N0, + O => cs_61_OBUF + ); + dadrL_BU689 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N4911 + ); + dadrL_BU686 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N4910 + ); + dadrL_BU681 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N4839, + ADR2 => dadrL_N4840, + ADR3 => dadrL_N0, + O => cs_60_OBUF + ); + dadrL_BU678 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N4840 + ); + dadrL_BU675 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N4839 + ); + dadrL_BU670 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N4768, + ADR2 => dadrL_N4769, + ADR3 => dadrL_N0, + O => cs_59_OBUF + ); + dadrL_BU667 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N4769 + ); + dadrL_BU664 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N4768 + ); + dadrL_BU659 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N4697, + ADR2 => dadrL_N4698, + ADR3 => dadrL_N0, + O => cs_58_OBUF + ); + dadrL_BU656 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N4698 + ); + dadrL_BU653 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N4697 + ); + dadrL_BU648 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N4626, + ADR2 => dadrL_N4627, + ADR3 => dadrL_N0, + O => cs_57_OBUF + ); + dadrL_BU645 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N4627 + ); + dadrL_BU642 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N4626 + ); + dadrL_BU637 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N4555, + ADR2 => dadrL_N4556, + ADR3 => dadrL_N0, + O => cs_56_OBUF + ); + dadrL_BU634 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N4556 + ); + dadrL_BU631 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N4555 + ); + dadrL_BU626 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N4484, + ADR2 => dadrL_N4485, + ADR3 => dadrL_N0, + O => cs_55_OBUF + ); + dadrL_BU623 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N4485 + ); + dadrL_BU620 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N4484 + ); + dadrL_BU615 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N4413, + ADR2 => dadrL_N4414, + ADR3 => dadrL_N0, + O => cs_54_OBUF + ); + dadrL_BU612 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N4414 + ); + dadrL_BU609 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N4413 + ); + dadrL_BU604 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N4342, + ADR2 => dadrL_N4343, + ADR3 => dadrL_N0, + O => cs_53_OBUF + ); + dadrL_BU601 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N4343 + ); + dadrL_BU598 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N4342 + ); + dadrL_BU593 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N4271, + ADR2 => dadrL_N4272, + ADR3 => dadrL_N0, + O => cs_52_OBUF + ); + dadrL_BU590 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N4272 + ); + dadrL_BU587 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N4271 + ); + dadrL_BU582 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N4200, + ADR2 => dadrL_N4201, + ADR3 => dadrL_N0, + O => cs_51_OBUF + ); + dadrL_BU579 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N4201 + ); + dadrL_BU576 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N4200 + ); + dadrL_BU571 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N4129, + ADR2 => dadrL_N4130, + ADR3 => dadrL_N0, + O => cs_50_OBUF + ); + dadrL_BU568 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N4130 + ); + dadrL_BU565 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N4129 + ); + dadrL_BU560 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N4058, + ADR2 => dadrL_N4059, + ADR3 => dadrL_N0, + O => cs_49_OBUF + ); + dadrL_BU557 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N4059 + ); + dadrL_BU554 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N4058 + ); + dadrL_BU549 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N3987, + ADR2 => dadrL_N3988, + ADR3 => dadrL_N0, + O => cs_48_OBUF + ); + dadrL_BU546 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N3988 + ); + dadrL_BU543 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N3987 + ); + dadrL_BU538 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N3916, + ADR2 => dadrL_N3917, + ADR3 => dadrL_N0, + O => cs_47_OBUF + ); + dadrL_BU535 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N3917 + ); + dadrL_BU532 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N3916 + ); + dadrL_BU527 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N3845, + ADR2 => dadrL_N3846, + ADR3 => dadrL_N0, + O => cs_46_OBUF + ); + dadrL_BU524 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N3846 + ); + dadrL_BU521 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N3845 + ); + dadrL_BU516 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N3774, + ADR2 => dadrL_N3775, + ADR3 => dadrL_N0, + O => cs_45_OBUF + ); + dadrL_BU513 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N3775 + ); + dadrL_BU510 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N3774 + ); + dadrL_BU505 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N3703, + ADR2 => dadrL_N3704, + ADR3 => dadrL_N0, + O => cs_44_OBUF + ); + dadrL_BU502 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N3704 + ); + dadrL_BU499 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N3703 + ); + dadrL_BU494 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N3632, + ADR2 => dadrL_N3633, + ADR3 => dadrL_N0, + O => cs_43_OBUF + ); + dadrL_BU491 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N3633 + ); + dadrL_BU488 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N3632 + ); + dadrL_BU483 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N3561, + ADR2 => dadrL_N3562, + ADR3 => dadrL_N0, + O => cs_42_OBUF + ); + dadrL_BU480 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N3562 + ); + dadrL_BU477 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N3561 + ); + dadrL_BU472 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N3490, + ADR2 => dadrL_N3491, + ADR3 => dadrL_N0, + O => cs_41_OBUF + ); + dadrL_BU469 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N3491 + ); + dadrL_BU466 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N3490 + ); + dadrL_BU461 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N3419, + ADR2 => dadrL_N3420, + ADR3 => dadrL_N0, + O => cs_40_OBUF + ); + dadrL_BU458 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N3420 + ); + dadrL_BU455 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N3419 + ); + dadrL_BU450 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N3348, + ADR2 => dadrL_N3349, + ADR3 => dadrL_N0, + O => cs_39_OBUF + ); + dadrL_BU447 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N3349 + ); + dadrL_BU444 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N3348 + ); + dadrL_BU439 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N3277, + ADR2 => dadrL_N3278, + ADR3 => dadrL_N0, + O => cs_38_OBUF + ); + dadrL_BU436 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N3278 + ); + dadrL_BU433 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N3277 + ); + dadrL_BU428 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N3206, + ADR2 => dadrL_N3207, + ADR3 => dadrL_N0, + O => cs_37_OBUF + ); + dadrL_BU425 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N3207 + ); + dadrL_BU422 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N3206 + ); + dadrL_BU417 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N3135, + ADR2 => dadrL_N3136, + ADR3 => dadrL_N0, + O => cs_36_OBUF + ); + dadrL_BU414 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N3136 + ); + dadrL_BU411 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N3135 + ); + dadrL_BU406 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N3064, + ADR2 => dadrL_N3065, + ADR3 => dadrL_N0, + O => cs_35_OBUF + ); + dadrL_BU403 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N3065 + ); + dadrL_BU400 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N3064 + ); + dadrL_BU395 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N2993, + ADR2 => dadrL_N2994, + ADR3 => dadrL_N0, + O => cs_34_OBUF + ); + dadrL_BU392 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N2994 + ); + dadrL_BU389 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N2993 + ); + dadrL_BU384 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N2922, + ADR2 => dadrL_N2923, + ADR3 => dadrL_N0, + O => cs_33_OBUF + ); + dadrL_BU381 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N2923 + ); + dadrL_BU378 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N2922 + ); + dadrL_BU373 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N2851, + ADR2 => dadrL_N2852, + ADR3 => dadrL_N0, + O => cs_32_OBUF + ); + dadrL_BU370 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N2852 + ); + dadrL_BU367 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N2851 + ); + dadrL_BU362 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N2780, + ADR2 => dadrL_N2781, + ADR3 => dadrL_N0, + O => cs_31_OBUF + ); + dadrL_BU359 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N2781 + ); + dadrL_BU356 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N2780 + ); + dadrL_BU351 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N2709, + ADR2 => dadrL_N2710, + ADR3 => dadrL_N0, + O => cs_30_OBUF + ); + dadrL_BU348 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N2710 + ); + dadrL_BU345 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N2709 + ); + dadrL_BU340 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N2638, + ADR2 => dadrL_N2639, + ADR3 => dadrL_N0, + O => cs_29_OBUF + ); + dadrL_BU337 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N2639 + ); + dadrL_BU334 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N2638 + ); + dadrL_BU329 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N2567, + ADR2 => dadrL_N2568, + ADR3 => dadrL_N0, + O => cs_28_OBUF + ); + dadrL_BU326 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N2568 + ); + dadrL_BU323 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N2567 + ); + dadrL_BU318 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N2496, + ADR2 => dadrL_N2497, + ADR3 => dadrL_N0, + O => cs_27_OBUF + ); + dadrL_BU315 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N2497 + ); + dadrL_BU312 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N2496 + ); + dadrL_BU307 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N2425, + ADR2 => dadrL_N2426, + ADR3 => dadrL_N0, + O => cs_26_OBUF + ); + dadrL_BU304 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N2426 + ); + dadrL_BU301 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N2425 + ); + dadrL_BU296 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N2354, + ADR2 => dadrL_N2355, + ADR3 => dadrL_N0, + O => cs_25_OBUF + ); + dadrL_BU293 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N2355 + ); + dadrL_BU290 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N2354 + ); + dadrL_BU285 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N2283, + ADR2 => dadrL_N2284, + ADR3 => dadrL_N0, + O => cs_24_OBUF + ); + dadrL_BU282 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N2284 + ); + dadrL_BU279 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N2283 + ); + dadrL_BU274 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N2212, + ADR2 => dadrL_N2213, + ADR3 => dadrL_N0, + O => cs_23_OBUF + ); + dadrL_BU271 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N2213 + ); + dadrL_BU268 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N2212 + ); + dadrL_BU263 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N2141, + ADR2 => dadrL_N2142, + ADR3 => dadrL_N0, + O => cs_22_OBUF + ); + dadrL_BU260 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N2142 + ); + dadrL_BU257 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N2141 + ); + dadrL_BU252 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N2070, + ADR2 => dadrL_N2071, + ADR3 => dadrL_N0, + O => cs_21_OBUF + ); + dadrL_BU249 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N2071 + ); + dadrL_BU246 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N2070 + ); + dadrL_BU241 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N1999, + ADR2 => dadrL_N2000, + ADR3 => dadrL_N0, + O => cs_20_OBUF + ); + dadrL_BU238 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N2000 + ); + dadrL_BU235 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N1999 + ); + dadrL_BU230 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N1928, + ADR2 => dadrL_N1929, + ADR3 => dadrL_N0, + O => cs_19_OBUF + ); + dadrL_BU227 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N1929 + ); + dadrL_BU224 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N1928 + ); + dadrL_BU219 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N1857, + ADR2 => dadrL_N1858, + ADR3 => dadrL_N0, + O => cs_18_OBUF + ); + dadrL_BU216 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N1858 + ); + dadrL_BU213 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N1857 + ); + dadrL_BU208 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N1786, + ADR2 => dadrL_N1787, + ADR3 => dadrL_N0, + O => cs_17_OBUF + ); + dadrL_BU205 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N1787 + ); + dadrL_BU202 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N1786 + ); + dadrL_BU197 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N1715, + ADR2 => dadrL_N1716, + ADR3 => dadrL_N0, + O => cs_16_OBUF + ); + dadrL_BU194 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N1716 + ); + dadrL_BU191 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N1715 + ); + dadrL_BU186 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N1644, + ADR2 => dadrL_N1645, + ADR3 => dadrL_N0, + O => cs_15_OBUF + ); + dadrL_BU183 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N1645 + ); + dadrL_BU180 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N1644 + ); + dadrL_BU175 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N1573, + ADR2 => dadrL_N1574, + ADR3 => dadrL_N0, + O => cs_14_OBUF + ); + dadrL_BU172 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N1574 + ); + dadrL_BU169 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N1573 + ); + dadrL_BU164 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N1502, + ADR2 => dadrL_N1503, + ADR3 => dadrL_N0, + O => cs_13_OBUF + ); + dadrL_BU161 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N1503 + ); + dadrL_BU158 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N1502 + ); + dadrL_BU153 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N1431, + ADR2 => dadrL_N1432, + ADR3 => dadrL_N0, + O => cs_12_OBUF + ); + dadrL_BU150 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N1432 + ); + dadrL_BU147 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N1431 + ); + dadrL_BU142 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N1360, + ADR2 => dadrL_N1361, + ADR3 => dadrL_N0, + O => cs_11_OBUF + ); + dadrL_BU139 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N1361 + ); + dadrL_BU136 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N1360 + ); + dadrL_BU131 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N1289, + ADR2 => dadrL_N1290, + ADR3 => dadrL_N0, + O => cs_10_OBUF + ); + dadrL_BU128 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N1290 + ); + dadrL_BU125 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N1289 + ); + dadrL_BU120 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N1218, + ADR2 => dadrL_N1219, + ADR3 => dadrL_N0, + O => cs_9_OBUF + ); + dadrL_BU117 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N1219 + ); + dadrL_BU114 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N1218 + ); + dadrL_BU109 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N1147, + ADR2 => dadrL_N1148, + ADR3 => dadrL_N0, + O => cs_8_OBUF + ); + dadrL_BU106 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N1148 + ); + dadrL_BU103 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N1147 + ); + dadrL_BU98 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N1076, + ADR2 => dadrL_N1077, + ADR3 => dadrL_N0, + O => cs_7_OBUF + ); + dadrL_BU95 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N1077 + ); + dadrL_BU92 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N1076 + ); + dadrL_BU87 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N1005, + ADR2 => dadrL_N1006, + ADR3 => dadrL_N0, + O => cs_6_OBUF + ); + dadrL_BU84 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N1006 + ); + dadrL_BU81 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N1005 + ); + dadrL_BU76 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N934, + ADR2 => dadrL_N935, + ADR3 => dadrL_N0, + O => cs_5_OBUF + ); + dadrL_BU73 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N935 + ); + dadrL_BU70 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N934 + ); + dadrL_BU65 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N863, + ADR2 => dadrL_N864, + ADR3 => dadrL_N0, + O => cs_4_OBUF + ); + dadrL_BU62 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N864 + ); + dadrL_BU59 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N863 + ); + dadrL_BU54 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N792, + ADR2 => dadrL_N793, + ADR3 => dadrL_N0, + O => cs_3_OBUF + ); + dadrL_BU51 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N793 + ); + dadrL_BU48 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N792 + ); + dadrL_BU43 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N721, + ADR2 => dadrL_N722, + ADR3 => dadrL_N0, + O => cs_2_OBUF + ); + dadrL_BU40 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N722 + ); + dadrL_BU37 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N721 + ); + dadrL_BU32 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N650, + ADR2 => dadrL_N651, + ADR3 => dadrL_N0, + O => cs_1_OBUF + ); + dadrL_BU29 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N651 + ); + dadrL_BU26 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N650 + ); + dadrL_BU21 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => reg_select, + ADR1 => dadrL_N579, + ADR2 => dadrL_N580, + ADR3 => dadrL_N0, + O => cs_0_OBUF + ); + dadrL_BU18 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_3_IBUF, + ADR1 => adr_bus_2_IBUF, + ADR2 => adr_bus_1_IBUF, + ADR3 => adr_bus_0_IBUF, + O => dadrL_N580 + ); + dadrL_BU15 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => adr_bus_7_IBUF, + ADR1 => adr_bus_6_IBUF, + ADR2 => adr_bus_5_IBUF, + ADR3 => adr_bus_4_IBUF, + O => dadrL_N579 + ); + dadrL_GND : X_ZERO + port map ( + O => dadrL_N0 + ); + dadrL_VCC : X_ONE + port map ( + O => NLW_dadrL_VCC_O_UNCONNECTED + ); + cs_0_OBUF_GTS_TRI_282 : X_TRI + port map ( + I => cs_0_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_0_OBUF_GTS_TRI_CTL, + O => cs(0) + ); + clk_OBUF_GTS_TRI_283 : X_TRI + port map ( + I => clk_OBUF_GTS_TRI, + CTL => NlwInverterSignal_clk_OBUF_GTS_TRI_CTL, + O => clk + ); + rw_OBUF_GTS_TRI_284 : X_TRI + port map ( + I => rw_OBUF_GTS_TRI, + CTL => NlwInverterSignal_rw_OBUF_GTS_TRI_CTL, + O => rw + ); + cs_255_OBUF_GTS_TRI_285 : X_TRI + port map ( + I => cs_255_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_255_OBUF_GTS_TRI_CTL, + O => cs(255) + ); + cs_254_OBUF_GTS_TRI_286 : X_TRI + port map ( + I => cs_254_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_254_OBUF_GTS_TRI_CTL, + O => cs(254) + ); + cs_253_OBUF_GTS_TRI_287 : X_TRI + port map ( + I => cs_253_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_253_OBUF_GTS_TRI_CTL, + O => cs(253) + ); + cs_252_OBUF_GTS_TRI_288 : X_TRI + port map ( + I => cs_252_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_252_OBUF_GTS_TRI_CTL, + O => cs(252) + ); + cs_251_OBUF_GTS_TRI_289 : X_TRI + port map ( + I => cs_251_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_251_OBUF_GTS_TRI_CTL, + O => cs(251) + ); + cs_250_OBUF_GTS_TRI_290 : X_TRI + port map ( + I => cs_250_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_250_OBUF_GTS_TRI_CTL, + O => cs(250) + ); + cs_249_OBUF_GTS_TRI_291 : X_TRI + port map ( + I => cs_249_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_249_OBUF_GTS_TRI_CTL, + O => cs(249) + ); + cs_248_OBUF_GTS_TRI_292 : X_TRI + port map ( + I => cs_248_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_248_OBUF_GTS_TRI_CTL, + O => cs(248) + ); + cs_247_OBUF_GTS_TRI_293 : X_TRI + port map ( + I => cs_247_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_247_OBUF_GTS_TRI_CTL, + O => cs(247) + ); + cs_246_OBUF_GTS_TRI_294 : X_TRI + port map ( + I => cs_246_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_246_OBUF_GTS_TRI_CTL, + O => cs(246) + ); + cs_245_OBUF_GTS_TRI_295 : X_TRI + port map ( + I => cs_245_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_245_OBUF_GTS_TRI_CTL, + O => cs(245) + ); + cs_244_OBUF_GTS_TRI_296 : X_TRI + port map ( + I => cs_244_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_244_OBUF_GTS_TRI_CTL, + O => cs(244) + ); + cs_243_OBUF_GTS_TRI_297 : X_TRI + port map ( + I => cs_243_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_243_OBUF_GTS_TRI_CTL, + O => cs(243) + ); + cs_242_OBUF_GTS_TRI_298 : X_TRI + port map ( + I => cs_242_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_242_OBUF_GTS_TRI_CTL, + O => cs(242) + ); + cs_241_OBUF_GTS_TRI_299 : X_TRI + port map ( + I => cs_241_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_241_OBUF_GTS_TRI_CTL, + O => cs(241) + ); + cs_240_OBUF_GTS_TRI_300 : X_TRI + port map ( + I => cs_240_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_240_OBUF_GTS_TRI_CTL, + O => cs(240) + ); + cs_239_OBUF_GTS_TRI_301 : X_TRI + port map ( + I => cs_239_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_239_OBUF_GTS_TRI_CTL, + O => cs(239) + ); + cs_238_OBUF_GTS_TRI_302 : X_TRI + port map ( + I => cs_238_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_238_OBUF_GTS_TRI_CTL, + O => cs(238) + ); + cs_237_OBUF_GTS_TRI_303 : X_TRI + port map ( + I => cs_237_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_237_OBUF_GTS_TRI_CTL, + O => cs(237) + ); + cs_236_OBUF_GTS_TRI_304 : X_TRI + port map ( + I => cs_236_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_236_OBUF_GTS_TRI_CTL, + O => cs(236) + ); + cs_235_OBUF_GTS_TRI_305 : X_TRI + port map ( + I => cs_235_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_235_OBUF_GTS_TRI_CTL, + O => cs(235) + ); + cs_234_OBUF_GTS_TRI_306 : X_TRI + port map ( + I => cs_234_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_234_OBUF_GTS_TRI_CTL, + O => cs(234) + ); + cs_233_OBUF_GTS_TRI_307 : X_TRI + port map ( + I => cs_233_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_233_OBUF_GTS_TRI_CTL, + O => cs(233) + ); + cs_232_OBUF_GTS_TRI_308 : X_TRI + port map ( + I => cs_232_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_232_OBUF_GTS_TRI_CTL, + O => cs(232) + ); + cs_231_OBUF_GTS_TRI_309 : X_TRI + port map ( + I => cs_231_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_231_OBUF_GTS_TRI_CTL, + O => cs(231) + ); + cs_230_OBUF_GTS_TRI_310 : X_TRI + port map ( + I => cs_230_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_230_OBUF_GTS_TRI_CTL, + O => cs(230) + ); + cs_229_OBUF_GTS_TRI_311 : X_TRI + port map ( + I => cs_229_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_229_OBUF_GTS_TRI_CTL, + O => cs(229) + ); + cs_228_OBUF_GTS_TRI_312 : X_TRI + port map ( + I => cs_228_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_228_OBUF_GTS_TRI_CTL, + O => cs(228) + ); + cs_227_OBUF_GTS_TRI_313 : X_TRI + port map ( + I => cs_227_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_227_OBUF_GTS_TRI_CTL, + O => cs(227) + ); + cs_226_OBUF_GTS_TRI_314 : X_TRI + port map ( + I => cs_226_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_226_OBUF_GTS_TRI_CTL, + O => cs(226) + ); + cs_225_OBUF_GTS_TRI_315 : X_TRI + port map ( + I => cs_225_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_225_OBUF_GTS_TRI_CTL, + O => cs(225) + ); + cs_224_OBUF_GTS_TRI_316 : X_TRI + port map ( + I => cs_224_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_224_OBUF_GTS_TRI_CTL, + O => cs(224) + ); + cs_223_OBUF_GTS_TRI_317 : X_TRI + port map ( + I => cs_223_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_223_OBUF_GTS_TRI_CTL, + O => cs(223) + ); + cs_222_OBUF_GTS_TRI_318 : X_TRI + port map ( + I => cs_222_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_222_OBUF_GTS_TRI_CTL, + O => cs(222) + ); + cs_221_OBUF_GTS_TRI_319 : X_TRI + port map ( + I => cs_221_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_221_OBUF_GTS_TRI_CTL, + O => cs(221) + ); + cs_220_OBUF_GTS_TRI_320 : X_TRI + port map ( + I => cs_220_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_220_OBUF_GTS_TRI_CTL, + O => cs(220) + ); + cs_219_OBUF_GTS_TRI_321 : X_TRI + port map ( + I => cs_219_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_219_OBUF_GTS_TRI_CTL, + O => cs(219) + ); + cs_218_OBUF_GTS_TRI_322 : X_TRI + port map ( + I => cs_218_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_218_OBUF_GTS_TRI_CTL, + O => cs(218) + ); + cs_217_OBUF_GTS_TRI_323 : X_TRI + port map ( + I => cs_217_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_217_OBUF_GTS_TRI_CTL, + O => cs(217) + ); + cs_216_OBUF_GTS_TRI_324 : X_TRI + port map ( + I => cs_216_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_216_OBUF_GTS_TRI_CTL, + O => cs(216) + ); + cs_215_OBUF_GTS_TRI_325 : X_TRI + port map ( + I => cs_215_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_215_OBUF_GTS_TRI_CTL, + O => cs(215) + ); + cs_214_OBUF_GTS_TRI_326 : X_TRI + port map ( + I => cs_214_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_214_OBUF_GTS_TRI_CTL, + O => cs(214) + ); + cs_213_OBUF_GTS_TRI_327 : X_TRI + port map ( + I => cs_213_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_213_OBUF_GTS_TRI_CTL, + O => cs(213) + ); + cs_212_OBUF_GTS_TRI_328 : X_TRI + port map ( + I => cs_212_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_212_OBUF_GTS_TRI_CTL, + O => cs(212) + ); + cs_211_OBUF_GTS_TRI_329 : X_TRI + port map ( + I => cs_211_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_211_OBUF_GTS_TRI_CTL, + O => cs(211) + ); + cs_210_OBUF_GTS_TRI_330 : X_TRI + port map ( + I => cs_210_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_210_OBUF_GTS_TRI_CTL, + O => cs(210) + ); + cs_209_OBUF_GTS_TRI_331 : X_TRI + port map ( + I => cs_209_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_209_OBUF_GTS_TRI_CTL, + O => cs(209) + ); + cs_208_OBUF_GTS_TRI_332 : X_TRI + port map ( + I => cs_208_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_208_OBUF_GTS_TRI_CTL, + O => cs(208) + ); + cs_207_OBUF_GTS_TRI_333 : X_TRI + port map ( + I => cs_207_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_207_OBUF_GTS_TRI_CTL, + O => cs(207) + ); + cs_206_OBUF_GTS_TRI_334 : X_TRI + port map ( + I => cs_206_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_206_OBUF_GTS_TRI_CTL, + O => cs(206) + ); + cs_205_OBUF_GTS_TRI_335 : X_TRI + port map ( + I => cs_205_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_205_OBUF_GTS_TRI_CTL, + O => cs(205) + ); + cs_204_OBUF_GTS_TRI_336 : X_TRI + port map ( + I => cs_204_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_204_OBUF_GTS_TRI_CTL, + O => cs(204) + ); + cs_203_OBUF_GTS_TRI_337 : X_TRI + port map ( + I => cs_203_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_203_OBUF_GTS_TRI_CTL, + O => cs(203) + ); + cs_202_OBUF_GTS_TRI_338 : X_TRI + port map ( + I => cs_202_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_202_OBUF_GTS_TRI_CTL, + O => cs(202) + ); + cs_201_OBUF_GTS_TRI_339 : X_TRI + port map ( + I => cs_201_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_201_OBUF_GTS_TRI_CTL, + O => cs(201) + ); + cs_200_OBUF_GTS_TRI_340 : X_TRI + port map ( + I => cs_200_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_200_OBUF_GTS_TRI_CTL, + O => cs(200) + ); + cs_199_OBUF_GTS_TRI_341 : X_TRI + port map ( + I => cs_199_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_199_OBUF_GTS_TRI_CTL, + O => cs(199) + ); + cs_198_OBUF_GTS_TRI_342 : X_TRI + port map ( + I => cs_198_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_198_OBUF_GTS_TRI_CTL, + O => cs(198) + ); + cs_197_OBUF_GTS_TRI_343 : X_TRI + port map ( + I => cs_197_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_197_OBUF_GTS_TRI_CTL, + O => cs(197) + ); + cs_196_OBUF_GTS_TRI_344 : X_TRI + port map ( + I => cs_196_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_196_OBUF_GTS_TRI_CTL, + O => cs(196) + ); + cs_195_OBUF_GTS_TRI_345 : X_TRI + port map ( + I => cs_195_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_195_OBUF_GTS_TRI_CTL, + O => cs(195) + ); + cs_194_OBUF_GTS_TRI_346 : X_TRI + port map ( + I => cs_194_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_194_OBUF_GTS_TRI_CTL, + O => cs(194) + ); + cs_193_OBUF_GTS_TRI_347 : X_TRI + port map ( + I => cs_193_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_193_OBUF_GTS_TRI_CTL, + O => cs(193) + ); + cs_192_OBUF_GTS_TRI_348 : X_TRI + port map ( + I => cs_192_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_192_OBUF_GTS_TRI_CTL, + O => cs(192) + ); + cs_191_OBUF_GTS_TRI_349 : X_TRI + port map ( + I => cs_191_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_191_OBUF_GTS_TRI_CTL, + O => cs(191) + ); + cs_190_OBUF_GTS_TRI_350 : X_TRI + port map ( + I => cs_190_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_190_OBUF_GTS_TRI_CTL, + O => cs(190) + ); + cs_189_OBUF_GTS_TRI_351 : X_TRI + port map ( + I => cs_189_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_189_OBUF_GTS_TRI_CTL, + O => cs(189) + ); + cs_188_OBUF_GTS_TRI_352 : X_TRI + port map ( + I => cs_188_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_188_OBUF_GTS_TRI_CTL, + O => cs(188) + ); + cs_187_OBUF_GTS_TRI_353 : X_TRI + port map ( + I => cs_187_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_187_OBUF_GTS_TRI_CTL, + O => cs(187) + ); + cs_186_OBUF_GTS_TRI_354 : X_TRI + port map ( + I => cs_186_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_186_OBUF_GTS_TRI_CTL, + O => cs(186) + ); + cs_185_OBUF_GTS_TRI_355 : X_TRI + port map ( + I => cs_185_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_185_OBUF_GTS_TRI_CTL, + O => cs(185) + ); + cs_184_OBUF_GTS_TRI_356 : X_TRI + port map ( + I => cs_184_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_184_OBUF_GTS_TRI_CTL, + O => cs(184) + ); + cs_183_OBUF_GTS_TRI_357 : X_TRI + port map ( + I => cs_183_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_183_OBUF_GTS_TRI_CTL, + O => cs(183) + ); + cs_182_OBUF_GTS_TRI_358 : X_TRI + port map ( + I => cs_182_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_182_OBUF_GTS_TRI_CTL, + O => cs(182) + ); + cs_181_OBUF_GTS_TRI_359 : X_TRI + port map ( + I => cs_181_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_181_OBUF_GTS_TRI_CTL, + O => cs(181) + ); + cs_180_OBUF_GTS_TRI_360 : X_TRI + port map ( + I => cs_180_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_180_OBUF_GTS_TRI_CTL, + O => cs(180) + ); + cs_179_OBUF_GTS_TRI_361 : X_TRI + port map ( + I => cs_179_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_179_OBUF_GTS_TRI_CTL, + O => cs(179) + ); + cs_178_OBUF_GTS_TRI_362 : X_TRI + port map ( + I => cs_178_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_178_OBUF_GTS_TRI_CTL, + O => cs(178) + ); + cs_177_OBUF_GTS_TRI_363 : X_TRI + port map ( + I => cs_177_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_177_OBUF_GTS_TRI_CTL, + O => cs(177) + ); + cs_176_OBUF_GTS_TRI_364 : X_TRI + port map ( + I => cs_176_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_176_OBUF_GTS_TRI_CTL, + O => cs(176) + ); + cs_175_OBUF_GTS_TRI_365 : X_TRI + port map ( + I => cs_175_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_175_OBUF_GTS_TRI_CTL, + O => cs(175) + ); + cs_174_OBUF_GTS_TRI_366 : X_TRI + port map ( + I => cs_174_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_174_OBUF_GTS_TRI_CTL, + O => cs(174) + ); + cs_173_OBUF_GTS_TRI_367 : X_TRI + port map ( + I => cs_173_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_173_OBUF_GTS_TRI_CTL, + O => cs(173) + ); + cs_172_OBUF_GTS_TRI_368 : X_TRI + port map ( + I => cs_172_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_172_OBUF_GTS_TRI_CTL, + O => cs(172) + ); + cs_171_OBUF_GTS_TRI_369 : X_TRI + port map ( + I => cs_171_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_171_OBUF_GTS_TRI_CTL, + O => cs(171) + ); + cs_170_OBUF_GTS_TRI_370 : X_TRI + port map ( + I => cs_170_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_170_OBUF_GTS_TRI_CTL, + O => cs(170) + ); + cs_169_OBUF_GTS_TRI_371 : X_TRI + port map ( + I => cs_169_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_169_OBUF_GTS_TRI_CTL, + O => cs(169) + ); + cs_168_OBUF_GTS_TRI_372 : X_TRI + port map ( + I => cs_168_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_168_OBUF_GTS_TRI_CTL, + O => cs(168) + ); + cs_167_OBUF_GTS_TRI_373 : X_TRI + port map ( + I => cs_167_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_167_OBUF_GTS_TRI_CTL, + O => cs(167) + ); + cs_166_OBUF_GTS_TRI_374 : X_TRI + port map ( + I => cs_166_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_166_OBUF_GTS_TRI_CTL, + O => cs(166) + ); + cs_165_OBUF_GTS_TRI_375 : X_TRI + port map ( + I => cs_165_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_165_OBUF_GTS_TRI_CTL, + O => cs(165) + ); + cs_164_OBUF_GTS_TRI_376 : X_TRI + port map ( + I => cs_164_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_164_OBUF_GTS_TRI_CTL, + O => cs(164) + ); + cs_163_OBUF_GTS_TRI_377 : X_TRI + port map ( + I => cs_163_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_163_OBUF_GTS_TRI_CTL, + O => cs(163) + ); + cs_162_OBUF_GTS_TRI_378 : X_TRI + port map ( + I => cs_162_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_162_OBUF_GTS_TRI_CTL, + O => cs(162) + ); + cs_161_OBUF_GTS_TRI_379 : X_TRI + port map ( + I => cs_161_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_161_OBUF_GTS_TRI_CTL, + O => cs(161) + ); + cs_160_OBUF_GTS_TRI_380 : X_TRI + port map ( + I => cs_160_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_160_OBUF_GTS_TRI_CTL, + O => cs(160) + ); + cs_159_OBUF_GTS_TRI_381 : X_TRI + port map ( + I => cs_159_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_159_OBUF_GTS_TRI_CTL, + O => cs(159) + ); + cs_158_OBUF_GTS_TRI_382 : X_TRI + port map ( + I => cs_158_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_158_OBUF_GTS_TRI_CTL, + O => cs(158) + ); + cs_157_OBUF_GTS_TRI_383 : X_TRI + port map ( + I => cs_157_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_157_OBUF_GTS_TRI_CTL, + O => cs(157) + ); + cs_156_OBUF_GTS_TRI_384 : X_TRI + port map ( + I => cs_156_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_156_OBUF_GTS_TRI_CTL, + O => cs(156) + ); + cs_155_OBUF_GTS_TRI_385 : X_TRI + port map ( + I => cs_155_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_155_OBUF_GTS_TRI_CTL, + O => cs(155) + ); + cs_154_OBUF_GTS_TRI_386 : X_TRI + port map ( + I => cs_154_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_154_OBUF_GTS_TRI_CTL, + O => cs(154) + ); + cs_153_OBUF_GTS_TRI_387 : X_TRI + port map ( + I => cs_153_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_153_OBUF_GTS_TRI_CTL, + O => cs(153) + ); + cs_152_OBUF_GTS_TRI_388 : X_TRI + port map ( + I => cs_152_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_152_OBUF_GTS_TRI_CTL, + O => cs(152) + ); + cs_151_OBUF_GTS_TRI_389 : X_TRI + port map ( + I => cs_151_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_151_OBUF_GTS_TRI_CTL, + O => cs(151) + ); + cs_150_OBUF_GTS_TRI_390 : X_TRI + port map ( + I => cs_150_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_150_OBUF_GTS_TRI_CTL, + O => cs(150) + ); + cs_149_OBUF_GTS_TRI_391 : X_TRI + port map ( + I => cs_149_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_149_OBUF_GTS_TRI_CTL, + O => cs(149) + ); + cs_148_OBUF_GTS_TRI_392 : X_TRI + port map ( + I => cs_148_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_148_OBUF_GTS_TRI_CTL, + O => cs(148) + ); + cs_147_OBUF_GTS_TRI_393 : X_TRI + port map ( + I => cs_147_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_147_OBUF_GTS_TRI_CTL, + O => cs(147) + ); + cs_146_OBUF_GTS_TRI_394 : X_TRI + port map ( + I => cs_146_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_146_OBUF_GTS_TRI_CTL, + O => cs(146) + ); + cs_145_OBUF_GTS_TRI_395 : X_TRI + port map ( + I => cs_145_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_145_OBUF_GTS_TRI_CTL, + O => cs(145) + ); + cs_144_OBUF_GTS_TRI_396 : X_TRI + port map ( + I => cs_144_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_144_OBUF_GTS_TRI_CTL, + O => cs(144) + ); + cs_143_OBUF_GTS_TRI_397 : X_TRI + port map ( + I => cs_143_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_143_OBUF_GTS_TRI_CTL, + O => cs(143) + ); + cs_142_OBUF_GTS_TRI_398 : X_TRI + port map ( + I => cs_142_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_142_OBUF_GTS_TRI_CTL, + O => cs(142) + ); + cs_141_OBUF_GTS_TRI_399 : X_TRI + port map ( + I => cs_141_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_141_OBUF_GTS_TRI_CTL, + O => cs(141) + ); + cs_140_OBUF_GTS_TRI_400 : X_TRI + port map ( + I => cs_140_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_140_OBUF_GTS_TRI_CTL, + O => cs(140) + ); + cs_139_OBUF_GTS_TRI_401 : X_TRI + port map ( + I => cs_139_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_139_OBUF_GTS_TRI_CTL, + O => cs(139) + ); + cs_138_OBUF_GTS_TRI_402 : X_TRI + port map ( + I => cs_138_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_138_OBUF_GTS_TRI_CTL, + O => cs(138) + ); + cs_137_OBUF_GTS_TRI_403 : X_TRI + port map ( + I => cs_137_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_137_OBUF_GTS_TRI_CTL, + O => cs(137) + ); + cs_136_OBUF_GTS_TRI_404 : X_TRI + port map ( + I => cs_136_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_136_OBUF_GTS_TRI_CTL, + O => cs(136) + ); + cs_135_OBUF_GTS_TRI_405 : X_TRI + port map ( + I => cs_135_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_135_OBUF_GTS_TRI_CTL, + O => cs(135) + ); + cs_134_OBUF_GTS_TRI_406 : X_TRI + port map ( + I => cs_134_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_134_OBUF_GTS_TRI_CTL, + O => cs(134) + ); + cs_133_OBUF_GTS_TRI_407 : X_TRI + port map ( + I => cs_133_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_133_OBUF_GTS_TRI_CTL, + O => cs(133) + ); + cs_132_OBUF_GTS_TRI_408 : X_TRI + port map ( + I => cs_132_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_132_OBUF_GTS_TRI_CTL, + O => cs(132) + ); + cs_131_OBUF_GTS_TRI_409 : X_TRI + port map ( + I => cs_131_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_131_OBUF_GTS_TRI_CTL, + O => cs(131) + ); + cs_130_OBUF_GTS_TRI_410 : X_TRI + port map ( + I => cs_130_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_130_OBUF_GTS_TRI_CTL, + O => cs(130) + ); + cs_129_OBUF_GTS_TRI_411 : X_TRI + port map ( + I => cs_129_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_129_OBUF_GTS_TRI_CTL, + O => cs(129) + ); + cs_128_OBUF_GTS_TRI_412 : X_TRI + port map ( + I => cs_128_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_128_OBUF_GTS_TRI_CTL, + O => cs(128) + ); + cs_127_OBUF_GTS_TRI_413 : X_TRI + port map ( + I => cs_127_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_127_OBUF_GTS_TRI_CTL, + O => cs(127) + ); + cs_126_OBUF_GTS_TRI_414 : X_TRI + port map ( + I => cs_126_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_126_OBUF_GTS_TRI_CTL, + O => cs(126) + ); + cs_125_OBUF_GTS_TRI_415 : X_TRI + port map ( + I => cs_125_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_125_OBUF_GTS_TRI_CTL, + O => cs(125) + ); + cs_124_OBUF_GTS_TRI_416 : X_TRI + port map ( + I => cs_124_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_124_OBUF_GTS_TRI_CTL, + O => cs(124) + ); + cs_123_OBUF_GTS_TRI_417 : X_TRI + port map ( + I => cs_123_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_123_OBUF_GTS_TRI_CTL, + O => cs(123) + ); + cs_122_OBUF_GTS_TRI_418 : X_TRI + port map ( + I => cs_122_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_122_OBUF_GTS_TRI_CTL, + O => cs(122) + ); + cs_121_OBUF_GTS_TRI_419 : X_TRI + port map ( + I => cs_121_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_121_OBUF_GTS_TRI_CTL, + O => cs(121) + ); + cs_120_OBUF_GTS_TRI_420 : X_TRI + port map ( + I => cs_120_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_120_OBUF_GTS_TRI_CTL, + O => cs(120) + ); + cs_119_OBUF_GTS_TRI_421 : X_TRI + port map ( + I => cs_119_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_119_OBUF_GTS_TRI_CTL, + O => cs(119) + ); + cs_118_OBUF_GTS_TRI_422 : X_TRI + port map ( + I => cs_118_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_118_OBUF_GTS_TRI_CTL, + O => cs(118) + ); + cs_117_OBUF_GTS_TRI_423 : X_TRI + port map ( + I => cs_117_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_117_OBUF_GTS_TRI_CTL, + O => cs(117) + ); + cs_116_OBUF_GTS_TRI_424 : X_TRI + port map ( + I => cs_116_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_116_OBUF_GTS_TRI_CTL, + O => cs(116) + ); + cs_115_OBUF_GTS_TRI_425 : X_TRI + port map ( + I => cs_115_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_115_OBUF_GTS_TRI_CTL, + O => cs(115) + ); + cs_114_OBUF_GTS_TRI_426 : X_TRI + port map ( + I => cs_114_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_114_OBUF_GTS_TRI_CTL, + O => cs(114) + ); + cs_113_OBUF_GTS_TRI_427 : X_TRI + port map ( + I => cs_113_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_113_OBUF_GTS_TRI_CTL, + O => cs(113) + ); + cs_112_OBUF_GTS_TRI_428 : X_TRI + port map ( + I => cs_112_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_112_OBUF_GTS_TRI_CTL, + O => cs(112) + ); + cs_111_OBUF_GTS_TRI_429 : X_TRI + port map ( + I => cs_111_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_111_OBUF_GTS_TRI_CTL, + O => cs(111) + ); + cs_110_OBUF_GTS_TRI_430 : X_TRI + port map ( + I => cs_110_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_110_OBUF_GTS_TRI_CTL, + O => cs(110) + ); + cs_109_OBUF_GTS_TRI_431 : X_TRI + port map ( + I => cs_109_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_109_OBUF_GTS_TRI_CTL, + O => cs(109) + ); + cs_108_OBUF_GTS_TRI_432 : X_TRI + port map ( + I => cs_108_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_108_OBUF_GTS_TRI_CTL, + O => cs(108) + ); + cs_107_OBUF_GTS_TRI_433 : X_TRI + port map ( + I => cs_107_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_107_OBUF_GTS_TRI_CTL, + O => cs(107) + ); + cs_106_OBUF_GTS_TRI_434 : X_TRI + port map ( + I => cs_106_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_106_OBUF_GTS_TRI_CTL, + O => cs(106) + ); + cs_105_OBUF_GTS_TRI_435 : X_TRI + port map ( + I => cs_105_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_105_OBUF_GTS_TRI_CTL, + O => cs(105) + ); + cs_104_OBUF_GTS_TRI_436 : X_TRI + port map ( + I => cs_104_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_104_OBUF_GTS_TRI_CTL, + O => cs(104) + ); + cs_103_OBUF_GTS_TRI_437 : X_TRI + port map ( + I => cs_103_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_103_OBUF_GTS_TRI_CTL, + O => cs(103) + ); + cs_102_OBUF_GTS_TRI_438 : X_TRI + port map ( + I => cs_102_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_102_OBUF_GTS_TRI_CTL, + O => cs(102) + ); + cs_101_OBUF_GTS_TRI_439 : X_TRI + port map ( + I => cs_101_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_101_OBUF_GTS_TRI_CTL, + O => cs(101) + ); + cs_100_OBUF_GTS_TRI_440 : X_TRI + port map ( + I => cs_100_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_100_OBUF_GTS_TRI_CTL, + O => cs(100) + ); + cs_99_OBUF_GTS_TRI_441 : X_TRI + port map ( + I => cs_99_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_99_OBUF_GTS_TRI_CTL, + O => cs(99) + ); + cs_98_OBUF_GTS_TRI_442 : X_TRI + port map ( + I => cs_98_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_98_OBUF_GTS_TRI_CTL, + O => cs(98) + ); + cs_97_OBUF_GTS_TRI_443 : X_TRI + port map ( + I => cs_97_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_97_OBUF_GTS_TRI_CTL, + O => cs(97) + ); + cs_96_OBUF_GTS_TRI_444 : X_TRI + port map ( + I => cs_96_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_96_OBUF_GTS_TRI_CTL, + O => cs(96) + ); + cs_95_OBUF_GTS_TRI_445 : X_TRI + port map ( + I => cs_95_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_95_OBUF_GTS_TRI_CTL, + O => cs(95) + ); + cs_94_OBUF_GTS_TRI_446 : X_TRI + port map ( + I => cs_94_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_94_OBUF_GTS_TRI_CTL, + O => cs(94) + ); + cs_93_OBUF_GTS_TRI_447 : X_TRI + port map ( + I => cs_93_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_93_OBUF_GTS_TRI_CTL, + O => cs(93) + ); + cs_92_OBUF_GTS_TRI_448 : X_TRI + port map ( + I => cs_92_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_92_OBUF_GTS_TRI_CTL, + O => cs(92) + ); + cs_91_OBUF_GTS_TRI_449 : X_TRI + port map ( + I => cs_91_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_91_OBUF_GTS_TRI_CTL, + O => cs(91) + ); + cs_90_OBUF_GTS_TRI_450 : X_TRI + port map ( + I => cs_90_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_90_OBUF_GTS_TRI_CTL, + O => cs(90) + ); + cs_89_OBUF_GTS_TRI_451 : X_TRI + port map ( + I => cs_89_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_89_OBUF_GTS_TRI_CTL, + O => cs(89) + ); + cs_88_OBUF_GTS_TRI_452 : X_TRI + port map ( + I => cs_88_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_88_OBUF_GTS_TRI_CTL, + O => cs(88) + ); + cs_87_OBUF_GTS_TRI_453 : X_TRI + port map ( + I => cs_87_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_87_OBUF_GTS_TRI_CTL, + O => cs(87) + ); + cs_86_OBUF_GTS_TRI_454 : X_TRI + port map ( + I => cs_86_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_86_OBUF_GTS_TRI_CTL, + O => cs(86) + ); + cs_85_OBUF_GTS_TRI_455 : X_TRI + port map ( + I => cs_85_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_85_OBUF_GTS_TRI_CTL, + O => cs(85) + ); + cs_84_OBUF_GTS_TRI_456 : X_TRI + port map ( + I => cs_84_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_84_OBUF_GTS_TRI_CTL, + O => cs(84) + ); + cs_83_OBUF_GTS_TRI_457 : X_TRI + port map ( + I => cs_83_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_83_OBUF_GTS_TRI_CTL, + O => cs(83) + ); + cs_82_OBUF_GTS_TRI_458 : X_TRI + port map ( + I => cs_82_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_82_OBUF_GTS_TRI_CTL, + O => cs(82) + ); + cs_81_OBUF_GTS_TRI_459 : X_TRI + port map ( + I => cs_81_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_81_OBUF_GTS_TRI_CTL, + O => cs(81) + ); + cs_80_OBUF_GTS_TRI_460 : X_TRI + port map ( + I => cs_80_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_80_OBUF_GTS_TRI_CTL, + O => cs(80) + ); + cs_79_OBUF_GTS_TRI_461 : X_TRI + port map ( + I => cs_79_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_79_OBUF_GTS_TRI_CTL, + O => cs(79) + ); + cs_78_OBUF_GTS_TRI_462 : X_TRI + port map ( + I => cs_78_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_78_OBUF_GTS_TRI_CTL, + O => cs(78) + ); + cs_77_OBUF_GTS_TRI_463 : X_TRI + port map ( + I => cs_77_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_77_OBUF_GTS_TRI_CTL, + O => cs(77) + ); + cs_76_OBUF_GTS_TRI_464 : X_TRI + port map ( + I => cs_76_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_76_OBUF_GTS_TRI_CTL, + O => cs(76) + ); + cs_75_OBUF_GTS_TRI_465 : X_TRI + port map ( + I => cs_75_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_75_OBUF_GTS_TRI_CTL, + O => cs(75) + ); + cs_74_OBUF_GTS_TRI_466 : X_TRI + port map ( + I => cs_74_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_74_OBUF_GTS_TRI_CTL, + O => cs(74) + ); + cs_73_OBUF_GTS_TRI_467 : X_TRI + port map ( + I => cs_73_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_73_OBUF_GTS_TRI_CTL, + O => cs(73) + ); + cs_72_OBUF_GTS_TRI_468 : X_TRI + port map ( + I => cs_72_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_72_OBUF_GTS_TRI_CTL, + O => cs(72) + ); + cs_71_OBUF_GTS_TRI_469 : X_TRI + port map ( + I => cs_71_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_71_OBUF_GTS_TRI_CTL, + O => cs(71) + ); + cs_70_OBUF_GTS_TRI_470 : X_TRI + port map ( + I => cs_70_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_70_OBUF_GTS_TRI_CTL, + O => cs(70) + ); + cs_69_OBUF_GTS_TRI_471 : X_TRI + port map ( + I => cs_69_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_69_OBUF_GTS_TRI_CTL, + O => cs(69) + ); + cs_68_OBUF_GTS_TRI_472 : X_TRI + port map ( + I => cs_68_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_68_OBUF_GTS_TRI_CTL, + O => cs(68) + ); + cs_67_OBUF_GTS_TRI_473 : X_TRI + port map ( + I => cs_67_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_67_OBUF_GTS_TRI_CTL, + O => cs(67) + ); + cs_66_OBUF_GTS_TRI_474 : X_TRI + port map ( + I => cs_66_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_66_OBUF_GTS_TRI_CTL, + O => cs(66) + ); + cs_65_OBUF_GTS_TRI_475 : X_TRI + port map ( + I => cs_65_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_65_OBUF_GTS_TRI_CTL, + O => cs(65) + ); + cs_64_OBUF_GTS_TRI_476 : X_TRI + port map ( + I => cs_64_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_64_OBUF_GTS_TRI_CTL, + O => cs(64) + ); + cs_63_OBUF_GTS_TRI_477 : X_TRI + port map ( + I => cs_63_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_63_OBUF_GTS_TRI_CTL, + O => cs(63) + ); + cs_62_OBUF_GTS_TRI_478 : X_TRI + port map ( + I => cs_62_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_62_OBUF_GTS_TRI_CTL, + O => cs(62) + ); + cs_61_OBUF_GTS_TRI_479 : X_TRI + port map ( + I => cs_61_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_61_OBUF_GTS_TRI_CTL, + O => cs(61) + ); + cs_60_OBUF_GTS_TRI_480 : X_TRI + port map ( + I => cs_60_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_60_OBUF_GTS_TRI_CTL, + O => cs(60) + ); + cs_59_OBUF_GTS_TRI_481 : X_TRI + port map ( + I => cs_59_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_59_OBUF_GTS_TRI_CTL, + O => cs(59) + ); + cs_58_OBUF_GTS_TRI_482 : X_TRI + port map ( + I => cs_58_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_58_OBUF_GTS_TRI_CTL, + O => cs(58) + ); + cs_57_OBUF_GTS_TRI_483 : X_TRI + port map ( + I => cs_57_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_57_OBUF_GTS_TRI_CTL, + O => cs(57) + ); + cs_56_OBUF_GTS_TRI_484 : X_TRI + port map ( + I => cs_56_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_56_OBUF_GTS_TRI_CTL, + O => cs(56) + ); + cs_55_OBUF_GTS_TRI_485 : X_TRI + port map ( + I => cs_55_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_55_OBUF_GTS_TRI_CTL, + O => cs(55) + ); + cs_54_OBUF_GTS_TRI_486 : X_TRI + port map ( + I => cs_54_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_54_OBUF_GTS_TRI_CTL, + O => cs(54) + ); + cs_53_OBUF_GTS_TRI_487 : X_TRI + port map ( + I => cs_53_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_53_OBUF_GTS_TRI_CTL, + O => cs(53) + ); + cs_52_OBUF_GTS_TRI_488 : X_TRI + port map ( + I => cs_52_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_52_OBUF_GTS_TRI_CTL, + O => cs(52) + ); + cs_51_OBUF_GTS_TRI_489 : X_TRI + port map ( + I => cs_51_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_51_OBUF_GTS_TRI_CTL, + O => cs(51) + ); + cs_50_OBUF_GTS_TRI_490 : X_TRI + port map ( + I => cs_50_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_50_OBUF_GTS_TRI_CTL, + O => cs(50) + ); + cs_49_OBUF_GTS_TRI_491 : X_TRI + port map ( + I => cs_49_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_49_OBUF_GTS_TRI_CTL, + O => cs(49) + ); + cs_48_OBUF_GTS_TRI_492 : X_TRI + port map ( + I => cs_48_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_48_OBUF_GTS_TRI_CTL, + O => cs(48) + ); + cs_47_OBUF_GTS_TRI_493 : X_TRI + port map ( + I => cs_47_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_47_OBUF_GTS_TRI_CTL, + O => cs(47) + ); + cs_46_OBUF_GTS_TRI_494 : X_TRI + port map ( + I => cs_46_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_46_OBUF_GTS_TRI_CTL, + O => cs(46) + ); + cs_45_OBUF_GTS_TRI_495 : X_TRI + port map ( + I => cs_45_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_45_OBUF_GTS_TRI_CTL, + O => cs(45) + ); + cs_44_OBUF_GTS_TRI_496 : X_TRI + port map ( + I => cs_44_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_44_OBUF_GTS_TRI_CTL, + O => cs(44) + ); + cs_43_OBUF_GTS_TRI_497 : X_TRI + port map ( + I => cs_43_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_43_OBUF_GTS_TRI_CTL, + O => cs(43) + ); + cs_42_OBUF_GTS_TRI_498 : X_TRI + port map ( + I => cs_42_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_42_OBUF_GTS_TRI_CTL, + O => cs(42) + ); + cs_41_OBUF_GTS_TRI_499 : X_TRI + port map ( + I => cs_41_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_41_OBUF_GTS_TRI_CTL, + O => cs(41) + ); + cs_40_OBUF_GTS_TRI_500 : X_TRI + port map ( + I => cs_40_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_40_OBUF_GTS_TRI_CTL, + O => cs(40) + ); + cs_39_OBUF_GTS_TRI_501 : X_TRI + port map ( + I => cs_39_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_39_OBUF_GTS_TRI_CTL, + O => cs(39) + ); + cs_38_OBUF_GTS_TRI_502 : X_TRI + port map ( + I => cs_38_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_38_OBUF_GTS_TRI_CTL, + O => cs(38) + ); + cs_37_OBUF_GTS_TRI_503 : X_TRI + port map ( + I => cs_37_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_37_OBUF_GTS_TRI_CTL, + O => cs(37) + ); + cs_36_OBUF_GTS_TRI_504 : X_TRI + port map ( + I => cs_36_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_36_OBUF_GTS_TRI_CTL, + O => cs(36) + ); + cs_35_OBUF_GTS_TRI_505 : X_TRI + port map ( + I => cs_35_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_35_OBUF_GTS_TRI_CTL, + O => cs(35) + ); + cs_34_OBUF_GTS_TRI_506 : X_TRI + port map ( + I => cs_34_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_34_OBUF_GTS_TRI_CTL, + O => cs(34) + ); + cs_33_OBUF_GTS_TRI_507 : X_TRI + port map ( + I => cs_33_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_33_OBUF_GTS_TRI_CTL, + O => cs(33) + ); + cs_32_OBUF_GTS_TRI_508 : X_TRI + port map ( + I => cs_32_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_32_OBUF_GTS_TRI_CTL, + O => cs(32) + ); + cs_31_OBUF_GTS_TRI_509 : X_TRI + port map ( + I => cs_31_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_31_OBUF_GTS_TRI_CTL, + O => cs(31) + ); + cs_30_OBUF_GTS_TRI_510 : X_TRI + port map ( + I => cs_30_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_30_OBUF_GTS_TRI_CTL, + O => cs(30) + ); + cs_29_OBUF_GTS_TRI_511 : X_TRI + port map ( + I => cs_29_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_29_OBUF_GTS_TRI_CTL, + O => cs(29) + ); + cs_28_OBUF_GTS_TRI_512 : X_TRI + port map ( + I => cs_28_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_28_OBUF_GTS_TRI_CTL, + O => cs(28) + ); + cs_27_OBUF_GTS_TRI_513 : X_TRI + port map ( + I => cs_27_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_27_OBUF_GTS_TRI_CTL, + O => cs(27) + ); + cs_26_OBUF_GTS_TRI_514 : X_TRI + port map ( + I => cs_26_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_26_OBUF_GTS_TRI_CTL, + O => cs(26) + ); + cs_25_OBUF_GTS_TRI_515 : X_TRI + port map ( + I => cs_25_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_25_OBUF_GTS_TRI_CTL, + O => cs(25) + ); + cs_24_OBUF_GTS_TRI_516 : X_TRI + port map ( + I => cs_24_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_24_OBUF_GTS_TRI_CTL, + O => cs(24) + ); + cs_23_OBUF_GTS_TRI_517 : X_TRI + port map ( + I => cs_23_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_23_OBUF_GTS_TRI_CTL, + O => cs(23) + ); + cs_22_OBUF_GTS_TRI_518 : X_TRI + port map ( + I => cs_22_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_22_OBUF_GTS_TRI_CTL, + O => cs(22) + ); + cs_21_OBUF_GTS_TRI_519 : X_TRI + port map ( + I => cs_21_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_21_OBUF_GTS_TRI_CTL, + O => cs(21) + ); + cs_20_OBUF_GTS_TRI_520 : X_TRI + port map ( + I => cs_20_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_20_OBUF_GTS_TRI_CTL, + O => cs(20) + ); + cs_19_OBUF_GTS_TRI_521 : X_TRI + port map ( + I => cs_19_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_19_OBUF_GTS_TRI_CTL, + O => cs(19) + ); + cs_18_OBUF_GTS_TRI_522 : X_TRI + port map ( + I => cs_18_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_18_OBUF_GTS_TRI_CTL, + O => cs(18) + ); + cs_17_OBUF_GTS_TRI_523 : X_TRI + port map ( + I => cs_17_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_17_OBUF_GTS_TRI_CTL, + O => cs(17) + ); + cs_16_OBUF_GTS_TRI_524 : X_TRI + port map ( + I => cs_16_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_16_OBUF_GTS_TRI_CTL, + O => cs(16) + ); + cs_15_OBUF_GTS_TRI_525 : X_TRI + port map ( + I => cs_15_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_15_OBUF_GTS_TRI_CTL, + O => cs(15) + ); + cs_14_OBUF_GTS_TRI_526 : X_TRI + port map ( + I => cs_14_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_14_OBUF_GTS_TRI_CTL, + O => cs(14) + ); + cs_13_OBUF_GTS_TRI_527 : X_TRI + port map ( + I => cs_13_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_13_OBUF_GTS_TRI_CTL, + O => cs(13) + ); + cs_12_OBUF_GTS_TRI_528 : X_TRI + port map ( + I => cs_12_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_12_OBUF_GTS_TRI_CTL, + O => cs(12) + ); + cs_11_OBUF_GTS_TRI_529 : X_TRI + port map ( + I => cs_11_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_11_OBUF_GTS_TRI_CTL, + O => cs(11) + ); + cs_10_OBUF_GTS_TRI_530 : X_TRI + port map ( + I => cs_10_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_10_OBUF_GTS_TRI_CTL, + O => cs(10) + ); + cs_9_OBUF_GTS_TRI_531 : X_TRI + port map ( + I => cs_9_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_9_OBUF_GTS_TRI_CTL, + O => cs(9) + ); + cs_8_OBUF_GTS_TRI_532 : X_TRI + port map ( + I => cs_8_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_8_OBUF_GTS_TRI_CTL, + O => cs(8) + ); + cs_7_OBUF_GTS_TRI_533 : X_TRI + port map ( + I => cs_7_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_7_OBUF_GTS_TRI_CTL, + O => cs(7) + ); + cs_6_OBUF_GTS_TRI_534 : X_TRI + port map ( + I => cs_6_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_6_OBUF_GTS_TRI_CTL, + O => cs(6) + ); + cs_5_OBUF_GTS_TRI_535 : X_TRI + port map ( + I => cs_5_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_5_OBUF_GTS_TRI_CTL, + O => cs(5) + ); + cs_4_OBUF_GTS_TRI_536 : X_TRI + port map ( + I => cs_4_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_4_OBUF_GTS_TRI_CTL, + O => cs(4) + ); + cs_3_OBUF_GTS_TRI_537 : X_TRI + port map ( + I => cs_3_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_3_OBUF_GTS_TRI_CTL, + O => cs(3) + ); + cs_2_OBUF_GTS_TRI_538 : X_TRI + port map ( + I => cs_2_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_2_OBUF_GTS_TRI_CTL, + O => cs(2) + ); + cs_1_OBUF_GTS_TRI_539 : X_TRI + port map ( + I => cs_1_OBUF_GTS_TRI, + CTL => NlwInverterSignal_cs_1_OBUF_GTS_TRI_CTL, + O => cs(1) + ); + NlwInverterBlock_cs_0_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_0_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_clk_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_clk_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_rw_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_rw_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_255_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_255_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_254_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_254_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_253_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_253_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_252_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_252_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_251_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_251_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_250_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_250_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_249_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_249_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_248_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_248_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_247_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_247_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_246_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_246_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_245_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_245_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_244_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_244_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_243_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_243_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_242_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_242_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_241_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_241_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_240_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_240_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_239_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_239_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_238_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_238_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_237_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_237_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_236_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_236_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_235_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_235_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_234_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_234_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_233_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_233_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_232_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_232_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_231_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_231_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_230_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_230_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_229_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_229_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_228_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_228_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_227_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_227_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_226_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_226_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_225_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_225_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_224_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_224_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_223_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_223_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_222_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_222_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_221_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_221_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_220_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_220_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_219_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_219_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_218_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_218_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_217_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_217_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_216_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_216_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_215_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_215_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_214_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_214_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_213_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_213_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_212_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_212_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_211_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_211_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_210_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_210_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_209_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_209_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_208_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_208_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_207_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_207_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_206_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_206_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_205_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_205_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_204_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_204_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_203_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_203_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_202_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_202_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_201_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_201_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_200_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_200_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_199_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_199_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_198_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_198_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_197_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_197_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_196_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_196_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_195_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_195_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_194_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_194_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_193_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_193_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_192_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_192_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_191_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_191_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_190_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_190_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_189_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_189_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_188_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_188_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_187_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_187_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_186_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_186_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_185_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_185_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_184_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_184_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_183_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_183_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_182_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_182_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_181_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_181_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_180_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_180_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_179_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_179_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_178_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_178_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_177_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_177_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_176_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_176_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_175_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_175_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_174_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_174_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_173_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_173_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_172_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_172_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_171_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_171_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_170_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_170_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_169_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_169_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_168_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_168_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_167_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_167_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_166_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_166_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_165_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_165_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_164_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_164_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_163_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_163_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_162_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_162_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_161_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_161_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_160_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_160_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_159_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_159_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_158_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_158_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_157_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_157_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_156_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_156_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_155_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_155_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_154_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_154_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_153_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_153_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_152_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_152_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_151_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_151_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_150_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_150_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_149_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_149_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_148_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_148_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_147_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_147_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_146_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_146_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_145_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_145_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_144_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_144_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_143_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_143_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_142_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_142_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_141_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_141_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_140_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_140_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_139_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_139_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_138_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_138_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_137_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_137_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_136_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_136_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_135_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_135_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_134_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_134_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_133_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_133_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_132_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_132_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_131_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_131_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_130_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_130_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_129_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_129_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_128_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_128_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_127_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_127_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_126_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_126_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_125_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_125_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_124_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_124_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_123_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_123_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_122_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_122_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_121_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_121_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_120_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_120_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_119_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_119_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_118_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_118_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_117_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_117_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_116_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_116_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_115_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_115_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_114_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_114_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_113_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_113_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_112_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_112_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_111_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_111_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_110_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_110_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_109_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_109_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_108_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_108_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_107_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_107_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_106_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_106_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_105_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_105_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_104_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_104_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_103_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_103_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_102_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_102_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_101_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_101_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_100_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_100_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_99_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_99_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_98_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_98_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_97_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_97_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_96_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_96_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_95_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_95_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_94_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_94_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_93_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_93_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_92_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_92_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_91_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_91_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_90_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_90_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_89_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_89_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_88_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_88_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_87_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_87_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_86_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_86_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_85_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_85_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_84_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_84_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_83_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_83_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_82_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_82_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_81_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_81_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_80_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_80_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_79_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_79_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_78_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_78_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_77_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_77_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_76_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_76_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_75_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_75_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_74_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_74_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_73_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_73_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_72_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_72_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_71_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_71_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_70_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_70_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_69_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_69_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_68_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_68_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_67_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_67_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_66_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_66_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_65_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_65_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_64_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_64_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_63_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_63_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_62_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_62_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_61_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_61_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_60_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_60_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_59_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_59_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_58_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_58_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_57_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_57_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_56_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_56_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_55_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_55_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_54_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_54_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_53_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_53_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_52_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_52_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_51_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_51_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_50_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_50_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_49_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_49_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_48_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_48_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_47_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_47_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_46_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_46_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_45_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_45_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_44_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_44_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_43_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_43_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_42_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_42_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_41_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_41_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_40_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_40_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_39_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_39_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_38_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_38_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_37_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_37_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_36_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_36_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_35_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_35_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_34_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_34_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_33_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_33_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_32_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_32_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_31_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_31_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_30_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_30_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_29_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_29_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_28_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_28_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_27_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_27_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_26_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_26_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_25_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_25_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_24_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_24_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_23_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_23_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_22_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_22_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_21_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_21_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_20_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_20_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_19_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_19_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_18_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_18_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_17_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_17_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_16_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_16_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_15_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_15_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_14_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_14_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_13_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_13_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_12_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_12_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_11_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_11_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_10_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_10_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_9_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_9_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_8_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_8_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_7_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_7_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_6_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_6_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_5_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_5_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_4_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_4_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_3_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_3_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_2_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_2_OBUF_GTS_TRI_CTL + ); + NlwInverterBlock_cs_1_OBUF_GTS_TRI_CTL : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_cs_1_OBUF_GTS_TRI_CTL + ); + NlwBlockTOC : X_TOC + port map (O => GTS); + +end Structure; + diff --git a/2004/n/fpga/src/fpga/decodadr.xco b/2004/n/fpga/src/fpga/decodadr.xco new file mode 100644 index 0000000..d9387c5 --- /dev/null +++ b/2004/n/fpga/src/fpga/decodadr.xco @@ -0,0 +1,41 @@ +# Xilinx CORE Generator 6.1.03i +# Username = Administrateur +# COREGenPath = D:\xilinx\coregen +# ProjectPath = D:\vhdl\robot\carte_fpga\src\fpga +# ExpandedProjectPath = D:\vhdl\robot\carte_fpga\src\fpga +# OverwriteFiles = true +# Core name: decodadr +# Number of Primitives in design: 768 +# Number of CLBs used in design: 264 +# Number of Slices used in design: 512 +# Number of LUT sites used in design: 768 +# Number of LUTs used in design: 768 +# Number of REG used in design: 0 +# Number of SRL16s used in design: 0 +# Number of Distributed RAM primitives used in design: 0 +# Number of Block Memories used in design: 0 +# Number of Dedicated Multipliers used in design: 0 +# Number of HU_SETs used: 1 +# Huset "default" = (0, 0) to (17, 16) in CLBs +# +SET BusFormat = BusFormatAngleBracketNotRipped +SET XilinxFamily = Spartan2 +SET OutputOption = OutputProducts +SET FlowVendor = Foundation_iSE +SET FormalVerification = None +SET OutputProducts = ImpNetlist ASYSymbol VHDLSim VerilogSim +SELECT Binary_Decoder Spartan2 Xilinx,_Inc. 6.0 +CSET output_sense = active_high +CSET async_init_value = 0 +CSET set_clear_priority = clear_overrides_set +CSET ce_overrides = sync_controls_override_ce +CSET number_of_outputs = 256 +CSET output_options = non_registered +CSET sync_init_value = 0 +CSET clock_enable = false +CSET create_rpm = true +CSET decoder_enable = true +CSET asynchronous_settings = none +CSET synchronous_settings = none +CSET component_name = decodadr +GENERATE diff --git a/2004/n/fpga/src/fpga/decodisa.vhd b/2004/n/fpga/src/fpga/decodisa.vhd new file mode 100644 index 0000000..463e767 --- /dev/null +++ b/2004/n/fpga/src/fpga/decodisa.vhd @@ -0,0 +1,61 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + + + +entity decodisa is +port( + adr_bus: in std_logic_vector(23 downto 0); + AEN:in std_logic; + IOR:in std_logic; + IOW:in std_logic; + + cs: out std_logic_vector(255 downto 0); + rw: out std_logic; + clk: out std_logic +); +constant adr_reseau:std_logic_vector:="0000000000000001"; +constant W_reseau:integer:=16; +constant W_sous_reseau:integer:=8; -- Attention : si changement sur ces valeurs,=> modifier le core !!! +end decodisa; + +architecture rtl of decodisa is + +component decodadr + port ( + S: IN std_logic_VECTOR((W_sous_reseau-1) downto 0); + O: OUT std_logic_VECTOR(255 downto 0); + EN: IN std_logic); +end component; + +component decodsig +port( + AEN:in std_logic; + IOR:in std_logic; + IOW:in std_logic; + rw: out std_logic; + clk: out std_logic); +end component; + +signal reg_select : std_logic; + +begin +dsig:decodsig +port map( + AEN=>AEN, + IOR=>IOR, + IOW=>IOW, + rw=>rw, + clk=>clk); + +dadrL:decodadr +port map( + S=>adr_bus((W_sous_reseau - 1) downto 0), + O=>cs, + EN=>reg_select); + +reg_select<='1' when (adr_bus((W_reseau - 1) downto W_sous_reseau)=adr_reseau) else '0'; + +end rtl; diff --git a/2004/n/fpga/src/fpga/fpga-test.vhd b/2004/n/fpga/src/fpga/fpga-test.vhd new file mode 100644 index 0000000..4595ca4 --- /dev/null +++ b/2004/n/fpga/src/fpga/fpga-test.vhd @@ -0,0 +1,142 @@ + +-- VHDL Test Bench Created from source file fpga.vhd -- 17:38:53 03/30/2004 +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +use ieee.std_logic_arith.all; +USE ieee.numeric_std.ALL; + +use work.nono_const.all; +use work.isa_const.all; + +ENTITY bch_fpga IS +END bch_fpga; + +ARCHITECTURE behavior OF bch_fpga IS + COMPONENT fpga + PORT( + rst : IN std_logic; + clk_speed : IN std_logic; + clk_ref : IN std_logic; + AEN : IN std_logic; + IOR : IN std_logic; + IOW : IN std_logic; + bus_adr : IN std_logic_vector(23 downto 0); + rxin1 : IN std_logic; + bus_data : INOUT std_logic_vector(7 downto 0); + irq : OUT std_logic + ); + END COMPONENT; + + + SIGNAL rst : std_logic:='0'; + SIGNAL clk_speed : std_logic:='0'; + SIGNAL clk_ref : std_logic:='0'; + SIGNAL AEN : std_logic; + SIGNAL IOR : std_logic; + SIGNAL IOW : std_logic; + SIGNAL bus_adr : std_logic_vector(23 downto 0); + SIGNAL bus_data : std_logic_vector(7 downto 0); + SIGNAL irq : std_logic; + SIGNAL rxin1 : std_logic:='0'; + + signal data : integer; + signal data_received : std_logic_vector(7 downto 0); + +BEGIN + + uut: fpga PORT MAP( + rst => rst, + clk_speed => clk_speed, + clk_ref => clk_ref, + AEN => AEN, + IOR => IOR, + IOW => IOW, + bus_adr => bus_adr, + bus_data => bus_data, + irq => irq, + rxin1 => rxin1 + ); + +-- master clock +clk_speed <= (Not clk_speed) after (CK_PERIOD/2); +-- Reset +rst <= '1','0' after (10*CK_PERIOD); + +-- baudrate/(16*2) used to generate half clock cycle; +clk_ref <= (not clk_ref) after 135 ns; --1,8432MHz +-- feeding back output from transmitter to the input of receiver +rxin1 <= (not rxin1) after 15751 ns; + + +check:process + -- procedure declaration + -- declared in process due to assignment to read + -- this procedure reads out data from the receiver + -- timing can be modified to model any CPU read cycle + PROCEDURE read_bus(address : in integer) IS + variable adr : std_logic_vector(23 downto 0); + BEGIN + adr:=conv_std_logic_vector(address,24); + bus_data<="ZZZZZZZZ"; + AEN<='0'; + WAIT FOR 20 ns; + bus_adr<=adr; + WAIT FOR 20 ns; + IOR<='0'; + WAIT FOR 60 ns; + data_received <= bus_data; + IOR<='1'; + WAIT FOR 20 ns; + AEN<='1'; + WAIT FOR 20 ns; + END read_bus; + + PROCEDURE write_bus(address : IN integer) IS + variable adr : std_logic_vector(23 downto 0); + variable dat : std_logic_vector(7 downto 0); + BEGIN +-- adr:=conv_std_logic_vector(address,24); +-- dat:=conv_std_logic_vector(data,8); + AEN<='0'; + WAIT FOR 20 ns; + bus_adr<=conv_std_logic_vector(address,24); + bus_data <= conv_std_logic_vector(data,8); + WAIT FOR 20 ns; + IOW<='0'; + WAIT FOR 60 ns; + IOW<='1'; + WAIT FOR 20 ns; + bus_data <= "ZZZZZZZZ"; + AEN<='1'; + WAIT FOR 20 ns; + END write_bus; + + begin + read_bus(259); + data<=179; + write_bus(259); + read_bus(259); + wait for 100 ns; + + read_bus(258); + data<=255; + write_bus(258); + read_bus(258); + wait for 100 ns; + + read_bus(257); + data<=179; + write_bus(257); + read_bus(257); + wait for 100 ns; + +end process; +END behavior; diff --git a/2004/n/fpga/src/fpga/fpga.npl b/2004/n/fpga/src/fpga/fpga.npl new file mode 100644 index 0000000..47b8714 --- /dev/null +++ b/2004/n/fpga/src/fpga/fpga.npl @@ -0,0 +1,39 @@ +JDF G +// Created by Project Navigator ver 1.0 +PROJECT fpga +DESIGN fpga +DEVFAM spartan2 +DEVFAMTIME 0 +DEVICE xc2s200 +DEVICETIME 0 +DEVPKG pq208 +DEVPKGTIME 1080594971 +DEVSPEED -6 +DEVSPEEDTIME 0 +DEVTOPLEVELMODULETYPE HDL +TOPLEVELMODULETYPETIME 0 +DEVSYNTHESISTOOL XST (VHDL/Verilog) +SYNTHESISTOOLTIME 0 +DEVSIMULATOR Modelsim +SIMULATORTIME 0 +DEVGENERATEDSIMULATIONMODEL VHDL +GENERATEDSIMULATIONMODELTIME 0 +SOURCE fpga.vhd +SOURCE isa_const.vhd +SOURCE ..\decodisa\decodadr.xco +STIMULUS ..\portserie\rxserie\bch_rxserie.vhd +SOURCE ..\portserie\rxserie\rxserie.vhd +SOURCE ..\portserie\clockgene\clockgene.vhd +SOURCE ..\portserie\fifo\fifodriver.vhd +SOURCE ..\portserie\fifo\sfifo.xco +SOURCE ..\registre\registre.vhd +STIMULUS ..\registre\test_reg.vhd +SOURCE ..\portserie\uart\rxcver.vhd +SOURCE ..\decodisa\decodisa.vhd +STIMULUS ..\decodisa\bch_decodisa.vhd +STIMULUS fpga-test.vhd +SOURCE ..\modele\nono_const.vhd +[STATUS-ALL] +decodisa.ngcFile=WARNINGS,1080659193 +[STRATEGY-LIST] +Normal=True diff --git a/2004/n/fpga/src/fpga/fpga.vhd b/2004/n/fpga/src/fpga/fpga.vhd new file mode 100644 index 0000000..95aa898 --- /dev/null +++ b/2004/n/fpga/src/fpga/fpga.vhd @@ -0,0 +1,104 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +-- Uncomment the following lines to use the declarations that are +-- provided for instantiating Xilinx primitive components. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity fpga is +port( +-- le contrôle général + rst : IN std_logic; + clk_speed : IN std_logic; + clk_ref : IN std_logic; + +-- le contrôle de bus + AEN : in std_logic; + IOR : in std_logic; + IOW : in std_logic; + bus_adr : in std_logic_vector(23 downto 0); + bus_data : INOUT std_logic_vector(7 downto 0); + irq : OUT std_logic; + +-- les entrées-sorties + rxin1:in std_logic +); +end fpga; + +architecture rtl of fpga is + +-- Déclaration des composants + COMPONENT rxserie + PORT( + rst : IN std_logic; + bus_clk : IN std_logic; + rw : IN std_logic; + clk : IN std_logic; + clk_ref : IN std_logic; + rxin : IN std_logic; + csData : IN std_logic; + csConfig : IN std_logic; + csFlag : IN std_logic; + bus_data : INOUT std_logic_vector(7 downto 0); + irqFIFO : OUT std_logic; + irqRX : OUT std_logic; + irqERR : OUT std_logic + ); + END COMPONENT; + + COMPONENT decodisa + PORT( + adr_bus : IN std_logic_vector(23 downto 0); + AEN : IN std_logic; + IOR : IN std_logic; + IOW : IN std_logic; + cs : OUT std_logic_vector(255 downto 0); + rw : OUT std_logic; + clk : OUT std_logic + ); + END COMPONENT; + + +signal cs : std_logic_vector(255 downto 0); +signal rw:std_logic; +signal bus_clk:std_logic; + +begin +-- Instanciation des composants + +-- décodeur ISA + Inst_decodisa: decodisa PORT MAP( + adr_bus => bus_adr, + AEN => AEN, + IOR => IOR, + IOW => IOW, + cs => cs, + rw => rw, + clk => bus_clk + ); + + +-- RX1 +-- adresse 1 + Inst_rxserie1: rxserie PORT MAP( + rst => rst, + bus_clk => bus_clk, + rw => rw, + bus_data => bus_data, + clk => clk_speed, + clk_ref => clk_ref, + rxin => rxin1, + irqFIFO => open, + irqRX => open, + irqERR => open, + csData => cs(1), + csConfig => cs(2), + csFlag => cs(3) + ); + + + +end rtl; diff --git a/2004/n/fpga/src/fpga/fpga_translate.vhd b/2004/n/fpga/src/fpga/fpga_translate.vhd new file mode 100644 index 0000000..b2ca18d --- /dev/null +++ b/2004/n/fpga/src/fpga/fpga_translate.vhd @@ -0,0 +1,13444 @@ +-- Xilinx Vhdl netlist produced by netgen application (version G.26) +-- Command : -intstyle ise -rpw 100 -tpw 0 -ar Structure -xon true -w -ofmt vhdl -sim fpga.ngd fpga_translate.vhd +-- Input file : fpga.ngd +-- Output file : fpga_translate.vhd +-- Design name : fpga +-- # of Entities : 1 +-- Xilinx : D:/xilinx +-- Device : 2s200pq208-6 + +-- This vhdl netlist is a simulation model and uses simulation +-- primitives which may not represent the true implementation of the +-- device, however the netlist is functionally correct and should not +-- be modified. This file cannot be synthesized and should only be used +-- with supported simulation tools. + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library SIMPRIM; +use SIMPRIM.VCOMPONENTS.ALL; +use SIMPRIM.VPACKAGE.ALL; + +entity fpga is + port ( + rst : in STD_LOGIC := 'X'; + rxin1 : in STD_LOGIC := 'X'; + clk_speed : in STD_LOGIC := 'X'; + AEN : in STD_LOGIC := 'X'; + IOR : in STD_LOGIC := 'X'; + IOW : in STD_LOGIC := 'X'; + clk_ref : in STD_LOGIC := 'X'; + irq : out STD_LOGIC; + bus_adr : in STD_LOGIC_VECTOR ( 23 downto 0 ); + bus_data : inout STD_LOGIC_VECTOR ( 7 downto 0 ) + ); +end fpga; + +architecture Structure of fpga is + signal rst_IBUF : STD_LOGIC; + signal rxin1_IBUF : STD_LOGIC; + signal bus_adr_1_IBUF : STD_LOGIC; + signal clk_speed_BUFGP : STD_LOGIC; + signal AEN_IBUF : STD_LOGIC; + signal IOR_IBUF : STD_LOGIC; + signal IOW_IBUF : STD_LOGIC; + signal clk_ref_IBUF : STD_LOGIC; + signal rw : STD_LOGIC; + signal bus_clk : STD_LOGIC; + signal bus_adr_0_IBUF : STD_LOGIC; + signal N10989 : STD_LOGIC; + signal bus_adr_15_IBUF : STD_LOGIC; + signal bus_adr_14_IBUF : STD_LOGIC; + signal bus_adr_13_IBUF : STD_LOGIC; + signal bus_adr_12_IBUF : STD_LOGIC; + signal bus_adr_11_IBUF : STD_LOGIC; + signal bus_adr_10_IBUF : STD_LOGIC; + signal bus_adr_9_IBUF : STD_LOGIC; + signal bus_adr_8_IBUF : STD_LOGIC; + signal bus_adr_7_IBUF : STD_LOGIC; + signal bus_adr_6_IBUF : STD_LOGIC; + signal bus_adr_5_IBUF : STD_LOGIC; + signal bus_adr_4_IBUF : STD_LOGIC; + signal bus_adr_3_IBUF : STD_LOGIC; + signal bus_adr_2_IBUF : STD_LOGIC; + signal Inst_rxserie1_RFLAG_REG_2_n0000 : STD_LOGIC; + signal Inst_rxserie1_RCONF_n0007 : STD_LOGIC; + signal Inst_rxserie1_RCONF_I1_N1369 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_state_read_FFd4_N1455 : STD_LOGIC; + signal N10999 : STD_LOGIC; + signal Inst_rxserie1_RFLAG_REG_6_n0000 : STD_LOGIC; + signal Inst_rxserie1_RFLAG_REG_3_n0000 : STD_LOGIC; + signal bus_data_5_IOBUF : STD_LOGIC; + signal Inst_rxserie1_state_rx_read_FFd2 : STD_LOGIC; + signal Inst_rxserie1_RC1_RXDATARDY : STD_LOGIC; + signal Inst_rxserie1_CLOCK1_ckout : STD_LOGIC; + signal Inst_rxserie1_geneck : STD_LOGIC; + signal Inst_rxserie1_rxread : STD_LOGIC; + signal Inst_rxserie1_FIFO1_state_write_FFd2 : STD_LOGIC; + signal Inst_rxserie1_RC1_OVERRUN : STD_LOGIC; + signal Inst_rxserie1_RC1_FRAMING_ERR : STD_LOGIC; + signal Inst_rxserie1_RC1_PARITY_ERR : STD_LOGIC; + signal Inst_rxserie1_I7_N1369 : STD_LOGIC; + signal Inst_rxserie1_RC1_RXCNT_3_rt : STD_LOGIC; + signal Inst_rxserie1_FIFO1_state_read_FFd2 : STD_LOGIC; + signal Inst_rxserie1_RC1_RXCNT_1_rt : STD_LOGIC; + signal Inst_rxserie1_FIFO1_wr_en : STD_LOGIC; + signal Inst_rxserie1_RFLAG_I1_N1369 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_state_write_FFd3 : STD_LOGIC; + signal Inst_rxserie1_CLOCK1_compteur_0_rt : STD_LOGIC; + signal Inst_rxserie1_RFLAG_REG_1_n0000 : STD_LOGIC; + signal Inst_rxserie1_RFLAG_REG_0_n0000 : STD_LOGIC; + signal Inst_rxserie1_RFLAG_REG_5_n0000 : STD_LOGIC; + signal N11003 : STD_LOGIC; + signal Inst_rxserie1_state_rx_read_FFd1 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_state_write_FFd1 : STD_LOGIC; + signal Inst_rxserie1_RFLAG_REG_4_n0000 : STD_LOGIC; + signal Inst_rxserie1_state_rx_read_FFd3_In : STD_LOGIC; + signal Inst_rxserie1_FIFO1_state_write_FFd3_In : STD_LOGIC; + signal Inst_rxserie1_state_rx_read_FFd4 : STD_LOGIC; + signal Inst_rxserie1_state_rx_read_FFd3 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_state_write_FFd1_In : STD_LOGIC; + signal Inst_rxserie1_RFLAG_n0007 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_state_write_FFd2_In : STD_LOGIC; + signal N4805 : STD_LOGIC; + signal bus_data_0_IOBUF : STD_LOGIC; + signal bus_data_7_IOBUF : STD_LOGIC; + signal bus_data_1_IOBUF : STD_LOGIC; + signal bus_data_6_IOBUF : STD_LOGIC; + signal bus_data_2_IOBUF : STD_LOGIC; + signal bus_data_4_IOBUF : STD_LOGIC; + signal bus_data_3_IOBUF : STD_LOGIC; + signal Inst_rxserie1_RC1_n0050 : STD_LOGIC; + signal Inst_rxserie1_RC1_Madd_n0040_inst_cy_12 : STD_LOGIC; + signal Inst_rxserie1_RC1_Madd_n0040_inst_cy_11 : STD_LOGIC; + signal Inst_rxserie1_RC1_N7296 : STD_LOGIC; + signal Inst_rxserie1_RC1_n0062 : STD_LOGIC; + signal Inst_rxserie1_RC1_HUNT : STD_LOGIC; + signal Inst_rxserie1_RC1_RX1 : STD_LOGIC; + signal Inst_rxserie1_RC1_PARITYGEN : STD_LOGIC; + signal Inst_rxserie1_RC1_n0051 : STD_LOGIC; + signal Inst_rxserie1_RC1_RXCLK : STD_LOGIC; + signal Inst_decodisa_reg_select : STD_LOGIC; + signal Inst_rxserie1_RC1_READ1 : STD_LOGIC; + signal Inst_rxserie1_RC1_IDLE1 : STD_LOGIC; + signal Inst_rxserie1_RC1_READ2 : STD_LOGIC; + signal Inst_rxserie1_RC1_n0020 : STD_LOGIC; + signal Inst_rxserie1_RC1_n0015 : STD_LOGIC; + signal Inst_rxserie1_RC1_n0021 : STD_LOGIC; + signal Inst_rxserie1_RC1_n0022 : STD_LOGIC; + signal Inst_rxserie1_RC1_n0023 : STD_LOGIC; + signal Inst_rxserie1_RC1_n0024 : STD_LOGIC; + signal Inst_rxserie1_RC1_n0019 : STD_LOGIC; + signal Inst_rxserie1_RC1_n0025 : STD_LOGIC; + signal Inst_rxserie1_RC1_n0031 : STD_LOGIC; + signal Inst_rxserie1_RC1_n0026 : STD_LOGIC; + signal Inst_rxserie1_RC1_n0027 : STD_LOGIC; + signal Inst_rxserie1_RC1_n0028 : STD_LOGIC; + signal Inst_rxserie1_RC1_n0034 : STD_LOGIC; + signal Inst_rxserie1_RC1_n0029 : STD_LOGIC; + signal Inst_rxserie1_RC1_RXPARITY : STD_LOGIC; + signal Inst_rxserie1_RC1_n0035 : STD_LOGIC; + signal Inst_rxserie1_RC1_RXSTOP : STD_LOGIC; + signal Inst_rxserie1_RC1_n0041 : STD_LOGIC; + signal Inst_rxserie1_RC1_n0036 : STD_LOGIC; + signal Inst_rxserie1_RC1_n0063 : STD_LOGIC; + signal Inst_rxserie1_RC1_Madd_n0040_inst_lut2_10 : STD_LOGIC; + signal N11001 : STD_LOGIC; + signal Inst_rxserie1_RC1_Madd_n0040_inst_cy_10 : STD_LOGIC; + signal Inst_rxserie1_RC1_IDLE : STD_LOGIC; + signal Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_5 : STD_LOGIC; + signal Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_5 : STD_LOGIC; + signal Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_1 : STD_LOGIC; + signal Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_2 : STD_LOGIC; + signal Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_3 : STD_LOGIC; + signal Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_6 : STD_LOGIC; + signal Inst_rxserie1_CLOCK1_n0005 : STD_LOGIC; + signal Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_9 : STD_LOGIC; + signal Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_4 : STD_LOGIC; + signal Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_8 : STD_LOGIC; + signal Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_2 : STD_LOGIC; + signal Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_1 : STD_LOGIC; + signal Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_0 : STD_LOGIC; + signal Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_3 : STD_LOGIC; + signal Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_7 : STD_LOGIC; + signal Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_7 : STD_LOGIC; + signal Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_8 : STD_LOGIC; + signal Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_6 : STD_LOGIC; + signal Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_4 : STD_LOGIC; + signal N10993 : STD_LOGIC; + signal Inst_rxserie1_CLOCK1_compteur_0_3_n0001 : STD_LOGIC; + signal Inst_rxserie1_CLOCK1_compteur_n0006 : STD_LOGIC; + signal Inst_rxserie1_RC1_RXCNT_2_rt : STD_LOGIC; + signal N10997 : STD_LOGIC; + signal Inst_rxserie1_CLOCK1_compteur_0_0_n0001 : STD_LOGIC; + signal N10991 : STD_LOGIC; + signal Inst_rxserie1_CLOCK1_compteur_0_0_n0000 : STD_LOGIC; + signal Inst_rxserie1_CLOCK1_compteur_0_2_n0000 : STD_LOGIC; + signal N10995 : STD_LOGIC; + signal Inst_rxserie1_CLOCK1_compteur_0_3_n0000 : STD_LOGIC; + signal Inst_rxserie1_CLOCK1_compteur_0_1_n0001 : STD_LOGIC; + signal N10987 : STD_LOGIC; + signal Inst_rxserie1_CLOCK1_compteur_0_2_n0001 : STD_LOGIC; + signal Inst_rxserie1_CLOCK1_compteur_0_1_n0000 : STD_LOGIC; + signal N11025 : STD_LOGIC; + signal N11021 : STD_LOGIC; + signal CHOICE64 : STD_LOGIC; + signal CHOICE45 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N47 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N48 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N49 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N50 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N51 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N52 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N53 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N54 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N1271 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N1143 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N1142 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N74 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N1113 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N1110 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N1107 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N1104 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N1101 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N73 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N1040 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N1037 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N1034 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N1031 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N1028 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N716 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N738 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N715 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N735 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N733 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N17 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N714 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N730 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N728 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N18 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N713 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N725 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N723 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N19 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N712 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N720 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N717 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N20 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N718 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N592 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N609 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N4 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N591 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N606 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N604 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N5 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N590 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N601 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N599 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N6 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N589 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N596 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N593 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N7 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N594 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N33 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_wr_ack : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N505 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_wr_err : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N456 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N38 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N3 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_rd_ack : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N333 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_rd_err : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N284 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N37 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N2 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N0 : STD_LOGIC; + signal Inst_rxserie1_FIFO1_fifo0_N1 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_255_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N18685 : STD_LOGIC; + signal Inst_decodisa_dadrL_N18684 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_254_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N18614 : STD_LOGIC; + signal Inst_decodisa_dadrL_N18613 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_253_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N18543 : STD_LOGIC; + signal Inst_decodisa_dadrL_N18542 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_252_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N18472 : STD_LOGIC; + signal Inst_decodisa_dadrL_N18471 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_251_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N18401 : STD_LOGIC; + signal Inst_decodisa_dadrL_N18400 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_250_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N18330 : STD_LOGIC; + signal Inst_decodisa_dadrL_N18329 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_249_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N18259 : STD_LOGIC; + signal Inst_decodisa_dadrL_N18258 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_248_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N18188 : STD_LOGIC; + signal Inst_decodisa_dadrL_N18187 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_247_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N18117 : STD_LOGIC; + signal Inst_decodisa_dadrL_N18116 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_246_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N18046 : STD_LOGIC; + signal Inst_decodisa_dadrL_N18045 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_245_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N17975 : STD_LOGIC; + signal Inst_decodisa_dadrL_N17974 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_244_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N17904 : STD_LOGIC; + signal Inst_decodisa_dadrL_N17903 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_243_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N17833 : STD_LOGIC; + signal Inst_decodisa_dadrL_N17832 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_242_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N17762 : STD_LOGIC; + signal Inst_decodisa_dadrL_N17761 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_241_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N17691 : STD_LOGIC; + signal Inst_decodisa_dadrL_N17690 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_240_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N17620 : STD_LOGIC; + signal Inst_decodisa_dadrL_N17619 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_239_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N17549 : STD_LOGIC; + signal Inst_decodisa_dadrL_N17548 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_238_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N17478 : STD_LOGIC; + signal Inst_decodisa_dadrL_N17477 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_237_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N17407 : STD_LOGIC; + signal Inst_decodisa_dadrL_N17406 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_236_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N17336 : STD_LOGIC; + signal Inst_decodisa_dadrL_N17335 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_235_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N17265 : STD_LOGIC; + signal Inst_decodisa_dadrL_N17264 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_234_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N17194 : STD_LOGIC; + signal Inst_decodisa_dadrL_N17193 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_233_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N17123 : STD_LOGIC; + signal Inst_decodisa_dadrL_N17122 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_232_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N17052 : STD_LOGIC; + signal Inst_decodisa_dadrL_N17051 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_231_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N16981 : STD_LOGIC; + signal Inst_decodisa_dadrL_N16980 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_230_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N16910 : STD_LOGIC; + signal Inst_decodisa_dadrL_N16909 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_229_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N16839 : STD_LOGIC; + signal Inst_decodisa_dadrL_N16838 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_228_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N16768 : STD_LOGIC; + signal Inst_decodisa_dadrL_N16767 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_227_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N16697 : STD_LOGIC; + signal Inst_decodisa_dadrL_N16696 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_226_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N16626 : STD_LOGIC; + signal Inst_decodisa_dadrL_N16625 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_225_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N16555 : STD_LOGIC; + signal Inst_decodisa_dadrL_N16554 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_224_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N16484 : STD_LOGIC; + signal Inst_decodisa_dadrL_N16483 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_223_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N16413 : STD_LOGIC; + signal Inst_decodisa_dadrL_N16412 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_222_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N16342 : STD_LOGIC; + signal Inst_decodisa_dadrL_N16341 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_221_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N16271 : STD_LOGIC; + signal Inst_decodisa_dadrL_N16270 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_220_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N16200 : STD_LOGIC; + signal Inst_decodisa_dadrL_N16199 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_219_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N16129 : STD_LOGIC; + signal Inst_decodisa_dadrL_N16128 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_218_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N16058 : STD_LOGIC; + signal Inst_decodisa_dadrL_N16057 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_217_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N15987 : STD_LOGIC; + signal Inst_decodisa_dadrL_N15986 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_216_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N15916 : STD_LOGIC; + signal Inst_decodisa_dadrL_N15915 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_215_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N15845 : STD_LOGIC; + signal Inst_decodisa_dadrL_N15844 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_214_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N15774 : STD_LOGIC; + signal Inst_decodisa_dadrL_N15773 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_213_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N15703 : STD_LOGIC; + signal Inst_decodisa_dadrL_N15702 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_212_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N15632 : STD_LOGIC; + signal Inst_decodisa_dadrL_N15631 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_211_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N15561 : STD_LOGIC; + signal Inst_decodisa_dadrL_N15560 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_210_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N15490 : STD_LOGIC; + signal Inst_decodisa_dadrL_N15489 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_209_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N15419 : STD_LOGIC; + signal Inst_decodisa_dadrL_N15418 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_208_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N15348 : STD_LOGIC; + signal Inst_decodisa_dadrL_N15347 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_207_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N15277 : STD_LOGIC; + signal Inst_decodisa_dadrL_N15276 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_206_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N15206 : STD_LOGIC; + signal Inst_decodisa_dadrL_N15205 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_205_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N15135 : STD_LOGIC; + signal Inst_decodisa_dadrL_N15134 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_204_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N15064 : STD_LOGIC; + signal Inst_decodisa_dadrL_N15063 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_203_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N14993 : STD_LOGIC; + signal Inst_decodisa_dadrL_N14992 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_202_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N14922 : STD_LOGIC; + signal Inst_decodisa_dadrL_N14921 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_201_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N14851 : STD_LOGIC; + signal Inst_decodisa_dadrL_N14850 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_200_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N14780 : STD_LOGIC; + signal Inst_decodisa_dadrL_N14779 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_199_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N14709 : STD_LOGIC; + signal Inst_decodisa_dadrL_N14708 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_198_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N14638 : STD_LOGIC; + signal Inst_decodisa_dadrL_N14637 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_197_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N14567 : STD_LOGIC; + signal Inst_decodisa_dadrL_N14566 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_196_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N14496 : STD_LOGIC; + signal Inst_decodisa_dadrL_N14495 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_195_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N14425 : STD_LOGIC; + signal Inst_decodisa_dadrL_N14424 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_194_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N14354 : STD_LOGIC; + signal Inst_decodisa_dadrL_N14353 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_193_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N14283 : STD_LOGIC; + signal Inst_decodisa_dadrL_N14282 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_192_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N14212 : STD_LOGIC; + signal Inst_decodisa_dadrL_N14211 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_191_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N14141 : STD_LOGIC; + signal Inst_decodisa_dadrL_N14140 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_190_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N14070 : STD_LOGIC; + signal Inst_decodisa_dadrL_N14069 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_189_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N13999 : STD_LOGIC; + signal Inst_decodisa_dadrL_N13998 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_188_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N13928 : STD_LOGIC; + signal Inst_decodisa_dadrL_N13927 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_187_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N13857 : STD_LOGIC; + signal Inst_decodisa_dadrL_N13856 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_186_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N13786 : STD_LOGIC; + signal Inst_decodisa_dadrL_N13785 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_185_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N13715 : STD_LOGIC; + signal Inst_decodisa_dadrL_N13714 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_184_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N13644 : STD_LOGIC; + signal Inst_decodisa_dadrL_N13643 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_183_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N13573 : STD_LOGIC; + signal Inst_decodisa_dadrL_N13572 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_182_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N13502 : STD_LOGIC; + signal Inst_decodisa_dadrL_N13501 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_181_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N13431 : STD_LOGIC; + signal Inst_decodisa_dadrL_N13430 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_180_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N13360 : STD_LOGIC; + signal Inst_decodisa_dadrL_N13359 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_179_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N13289 : STD_LOGIC; + signal Inst_decodisa_dadrL_N13288 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_178_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N13218 : STD_LOGIC; + signal Inst_decodisa_dadrL_N13217 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_177_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N13147 : STD_LOGIC; + signal Inst_decodisa_dadrL_N13146 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_176_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N13076 : STD_LOGIC; + signal Inst_decodisa_dadrL_N13075 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_175_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N13005 : STD_LOGIC; + signal Inst_decodisa_dadrL_N13004 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_174_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N12934 : STD_LOGIC; + signal Inst_decodisa_dadrL_N12933 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_173_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N12863 : STD_LOGIC; + signal Inst_decodisa_dadrL_N12862 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_172_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N12792 : STD_LOGIC; + signal Inst_decodisa_dadrL_N12791 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_171_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N12721 : STD_LOGIC; + signal Inst_decodisa_dadrL_N12720 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_170_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N12650 : STD_LOGIC; + signal Inst_decodisa_dadrL_N12649 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_169_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N12579 : STD_LOGIC; + signal Inst_decodisa_dadrL_N12578 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_168_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N12508 : STD_LOGIC; + signal Inst_decodisa_dadrL_N12507 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_167_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N12437 : STD_LOGIC; + signal Inst_decodisa_dadrL_N12436 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_166_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N12366 : STD_LOGIC; + signal Inst_decodisa_dadrL_N12365 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_165_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N12295 : STD_LOGIC; + signal Inst_decodisa_dadrL_N12294 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_164_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N12224 : STD_LOGIC; + signal Inst_decodisa_dadrL_N12223 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_163_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N12153 : STD_LOGIC; + signal Inst_decodisa_dadrL_N12152 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_162_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N12082 : STD_LOGIC; + signal Inst_decodisa_dadrL_N12081 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_161_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N12011 : STD_LOGIC; + signal Inst_decodisa_dadrL_N12010 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_160_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N11940 : STD_LOGIC; + signal Inst_decodisa_dadrL_N11939 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_159_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N11869 : STD_LOGIC; + signal Inst_decodisa_dadrL_N11868 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_158_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N11798 : STD_LOGIC; + signal Inst_decodisa_dadrL_N11797 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_157_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N11727 : STD_LOGIC; + signal Inst_decodisa_dadrL_N11726 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_156_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N11656 : STD_LOGIC; + signal Inst_decodisa_dadrL_N11655 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_155_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N11585 : STD_LOGIC; + signal Inst_decodisa_dadrL_N11584 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_154_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N11514 : STD_LOGIC; + signal Inst_decodisa_dadrL_N11513 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_153_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N11443 : STD_LOGIC; + signal Inst_decodisa_dadrL_N11442 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_152_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N11372 : STD_LOGIC; + signal Inst_decodisa_dadrL_N11371 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_151_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N11301 : STD_LOGIC; + signal Inst_decodisa_dadrL_N11300 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_150_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N11230 : STD_LOGIC; + signal Inst_decodisa_dadrL_N11229 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_149_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N11159 : STD_LOGIC; + signal Inst_decodisa_dadrL_N11158 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_148_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N11088 : STD_LOGIC; + signal Inst_decodisa_dadrL_N11087 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_147_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N11017 : STD_LOGIC; + signal Inst_decodisa_dadrL_N11016 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_146_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N10946 : STD_LOGIC; + signal Inst_decodisa_dadrL_N10945 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_145_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N10875 : STD_LOGIC; + signal Inst_decodisa_dadrL_N10874 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_144_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N10804 : STD_LOGIC; + signal Inst_decodisa_dadrL_N10803 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_143_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N10733 : STD_LOGIC; + signal Inst_decodisa_dadrL_N10732 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_142_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N10662 : STD_LOGIC; + signal Inst_decodisa_dadrL_N10661 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_141_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N10591 : STD_LOGIC; + signal Inst_decodisa_dadrL_N10590 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_140_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N10520 : STD_LOGIC; + signal Inst_decodisa_dadrL_N10519 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_139_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N10449 : STD_LOGIC; + signal Inst_decodisa_dadrL_N10448 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_138_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N10378 : STD_LOGIC; + signal Inst_decodisa_dadrL_N10377 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_137_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N10307 : STD_LOGIC; + signal Inst_decodisa_dadrL_N10306 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_136_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N10236 : STD_LOGIC; + signal Inst_decodisa_dadrL_N10235 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_135_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N10165 : STD_LOGIC; + signal Inst_decodisa_dadrL_N10164 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_134_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N10094 : STD_LOGIC; + signal Inst_decodisa_dadrL_N10093 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_133_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N10023 : STD_LOGIC; + signal Inst_decodisa_dadrL_N10022 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_132_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N9952 : STD_LOGIC; + signal Inst_decodisa_dadrL_N9951 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_131_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N9881 : STD_LOGIC; + signal Inst_decodisa_dadrL_N9880 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_130_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N9810 : STD_LOGIC; + signal Inst_decodisa_dadrL_N9809 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_129_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N9739 : STD_LOGIC; + signal Inst_decodisa_dadrL_N9738 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_128_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N9668 : STD_LOGIC; + signal Inst_decodisa_dadrL_N9667 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_127_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N9597 : STD_LOGIC; + signal Inst_decodisa_dadrL_N9596 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_126_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N9526 : STD_LOGIC; + signal Inst_decodisa_dadrL_N9525 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_125_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N9455 : STD_LOGIC; + signal Inst_decodisa_dadrL_N9454 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_124_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N9384 : STD_LOGIC; + signal Inst_decodisa_dadrL_N9383 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_123_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N9313 : STD_LOGIC; + signal Inst_decodisa_dadrL_N9312 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_122_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N9242 : STD_LOGIC; + signal Inst_decodisa_dadrL_N9241 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_121_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N9171 : STD_LOGIC; + signal Inst_decodisa_dadrL_N9170 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_120_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N9100 : STD_LOGIC; + signal Inst_decodisa_dadrL_N9099 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_119_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N9029 : STD_LOGIC; + signal Inst_decodisa_dadrL_N9028 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_118_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N8958 : STD_LOGIC; + signal Inst_decodisa_dadrL_N8957 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_117_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N8887 : STD_LOGIC; + signal Inst_decodisa_dadrL_N8886 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_116_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N8816 : STD_LOGIC; + signal Inst_decodisa_dadrL_N8815 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_115_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N8745 : STD_LOGIC; + signal Inst_decodisa_dadrL_N8744 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_114_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N8674 : STD_LOGIC; + signal Inst_decodisa_dadrL_N8673 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_113_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N8603 : STD_LOGIC; + signal Inst_decodisa_dadrL_N8602 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_112_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N8532 : STD_LOGIC; + signal Inst_decodisa_dadrL_N8531 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_111_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N8461 : STD_LOGIC; + signal Inst_decodisa_dadrL_N8460 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_110_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N8390 : STD_LOGIC; + signal Inst_decodisa_dadrL_N8389 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_109_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N8319 : STD_LOGIC; + signal Inst_decodisa_dadrL_N8318 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_108_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N8248 : STD_LOGIC; + signal Inst_decodisa_dadrL_N8247 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_107_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N8177 : STD_LOGIC; + signal Inst_decodisa_dadrL_N8176 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_106_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N8106 : STD_LOGIC; + signal Inst_decodisa_dadrL_N8105 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_105_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N8035 : STD_LOGIC; + signal Inst_decodisa_dadrL_N8034 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_104_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N7964 : STD_LOGIC; + signal Inst_decodisa_dadrL_N7963 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_103_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N7893 : STD_LOGIC; + signal Inst_decodisa_dadrL_N7892 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_102_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N7822 : STD_LOGIC; + signal Inst_decodisa_dadrL_N7821 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_101_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N7751 : STD_LOGIC; + signal Inst_decodisa_dadrL_N7750 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_100_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N7680 : STD_LOGIC; + signal Inst_decodisa_dadrL_N7679 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_99_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N7609 : STD_LOGIC; + signal Inst_decodisa_dadrL_N7608 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_98_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N7538 : STD_LOGIC; + signal Inst_decodisa_dadrL_N7537 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_97_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N7467 : STD_LOGIC; + signal Inst_decodisa_dadrL_N7466 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_96_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N7396 : STD_LOGIC; + signal Inst_decodisa_dadrL_N7395 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_95_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N7325 : STD_LOGIC; + signal Inst_decodisa_dadrL_N7324 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_94_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N7254 : STD_LOGIC; + signal Inst_decodisa_dadrL_N7253 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_93_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N7183 : STD_LOGIC; + signal Inst_decodisa_dadrL_N7182 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_92_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N7112 : STD_LOGIC; + signal Inst_decodisa_dadrL_N7111 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_91_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N7041 : STD_LOGIC; + signal Inst_decodisa_dadrL_N7040 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_90_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N6970 : STD_LOGIC; + signal Inst_decodisa_dadrL_N6969 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_89_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N6899 : STD_LOGIC; + signal Inst_decodisa_dadrL_N6898 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_88_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N6828 : STD_LOGIC; + signal Inst_decodisa_dadrL_N6827 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_87_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N6757 : STD_LOGIC; + signal Inst_decodisa_dadrL_N6756 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_86_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N6686 : STD_LOGIC; + signal Inst_decodisa_dadrL_N6685 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_85_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N6615 : STD_LOGIC; + signal Inst_decodisa_dadrL_N6614 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_84_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N6544 : STD_LOGIC; + signal Inst_decodisa_dadrL_N6543 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_83_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N6473 : STD_LOGIC; + signal Inst_decodisa_dadrL_N6472 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_82_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N6402 : STD_LOGIC; + signal Inst_decodisa_dadrL_N6401 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_81_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N6331 : STD_LOGIC; + signal Inst_decodisa_dadrL_N6330 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_80_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N6260 : STD_LOGIC; + signal Inst_decodisa_dadrL_N6259 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_79_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N6189 : STD_LOGIC; + signal Inst_decodisa_dadrL_N6188 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_78_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N6118 : STD_LOGIC; + signal Inst_decodisa_dadrL_N6117 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_77_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N6047 : STD_LOGIC; + signal Inst_decodisa_dadrL_N6046 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_76_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N5976 : STD_LOGIC; + signal Inst_decodisa_dadrL_N5975 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_75_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N5905 : STD_LOGIC; + signal Inst_decodisa_dadrL_N5904 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_74_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N5834 : STD_LOGIC; + signal Inst_decodisa_dadrL_N5833 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_73_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N5763 : STD_LOGIC; + signal Inst_decodisa_dadrL_N5762 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_72_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N5692 : STD_LOGIC; + signal Inst_decodisa_dadrL_N5691 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_71_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N5621 : STD_LOGIC; + signal Inst_decodisa_dadrL_N5620 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_70_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N5550 : STD_LOGIC; + signal Inst_decodisa_dadrL_N5549 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_69_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N5479 : STD_LOGIC; + signal Inst_decodisa_dadrL_N5478 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_68_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N5408 : STD_LOGIC; + signal Inst_decodisa_dadrL_N5407 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_67_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N5337 : STD_LOGIC; + signal Inst_decodisa_dadrL_N5336 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_66_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N5266 : STD_LOGIC; + signal Inst_decodisa_dadrL_N5265 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_65_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N5195 : STD_LOGIC; + signal Inst_decodisa_dadrL_N5194 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_64_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N5124 : STD_LOGIC; + signal Inst_decodisa_dadrL_N5123 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_63_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N5053 : STD_LOGIC; + signal Inst_decodisa_dadrL_N5052 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_62_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N4982 : STD_LOGIC; + signal Inst_decodisa_dadrL_N4981 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_61_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N4911 : STD_LOGIC; + signal Inst_decodisa_dadrL_N4910 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_60_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N4840 : STD_LOGIC; + signal Inst_decodisa_dadrL_N4839 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_59_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N4769 : STD_LOGIC; + signal Inst_decodisa_dadrL_N4768 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_58_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N4698 : STD_LOGIC; + signal Inst_decodisa_dadrL_N4697 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_57_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N4627 : STD_LOGIC; + signal Inst_decodisa_dadrL_N4626 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_56_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N4556 : STD_LOGIC; + signal Inst_decodisa_dadrL_N4555 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_55_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N4485 : STD_LOGIC; + signal Inst_decodisa_dadrL_N4484 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_54_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N4414 : STD_LOGIC; + signal Inst_decodisa_dadrL_N4413 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_53_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N4343 : STD_LOGIC; + signal Inst_decodisa_dadrL_N4342 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_52_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N4272 : STD_LOGIC; + signal Inst_decodisa_dadrL_N4271 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_51_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N4201 : STD_LOGIC; + signal Inst_decodisa_dadrL_N4200 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_50_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N4130 : STD_LOGIC; + signal Inst_decodisa_dadrL_N4129 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_49_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N4059 : STD_LOGIC; + signal Inst_decodisa_dadrL_N4058 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_48_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N3988 : STD_LOGIC; + signal Inst_decodisa_dadrL_N3987 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_47_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N3917 : STD_LOGIC; + signal Inst_decodisa_dadrL_N3916 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_46_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N3846 : STD_LOGIC; + signal Inst_decodisa_dadrL_N3845 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_45_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N3775 : STD_LOGIC; + signal Inst_decodisa_dadrL_N3774 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_44_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N3704 : STD_LOGIC; + signal Inst_decodisa_dadrL_N3703 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_43_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N3633 : STD_LOGIC; + signal Inst_decodisa_dadrL_N3632 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_42_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N3562 : STD_LOGIC; + signal Inst_decodisa_dadrL_N3561 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_41_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N3491 : STD_LOGIC; + signal Inst_decodisa_dadrL_N3490 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_40_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N3420 : STD_LOGIC; + signal Inst_decodisa_dadrL_N3419 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_39_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N3349 : STD_LOGIC; + signal Inst_decodisa_dadrL_N3348 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_38_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N3278 : STD_LOGIC; + signal Inst_decodisa_dadrL_N3277 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_37_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N3207 : STD_LOGIC; + signal Inst_decodisa_dadrL_N3206 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_36_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N3136 : STD_LOGIC; + signal Inst_decodisa_dadrL_N3135 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_35_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N3065 : STD_LOGIC; + signal Inst_decodisa_dadrL_N3064 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_34_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N2994 : STD_LOGIC; + signal Inst_decodisa_dadrL_N2993 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_33_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N2923 : STD_LOGIC; + signal Inst_decodisa_dadrL_N2922 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_32_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N2852 : STD_LOGIC; + signal Inst_decodisa_dadrL_N2851 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_31_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N2781 : STD_LOGIC; + signal Inst_decodisa_dadrL_N2780 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_30_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N2710 : STD_LOGIC; + signal Inst_decodisa_dadrL_N2709 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_29_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N2639 : STD_LOGIC; + signal Inst_decodisa_dadrL_N2638 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_28_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N2568 : STD_LOGIC; + signal Inst_decodisa_dadrL_N2567 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_27_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N2497 : STD_LOGIC; + signal Inst_decodisa_dadrL_N2496 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_26_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N2426 : STD_LOGIC; + signal Inst_decodisa_dadrL_N2425 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_25_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N2355 : STD_LOGIC; + signal Inst_decodisa_dadrL_N2354 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_24_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N2284 : STD_LOGIC; + signal Inst_decodisa_dadrL_N2283 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_23_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N2213 : STD_LOGIC; + signal Inst_decodisa_dadrL_N2212 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_22_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N2142 : STD_LOGIC; + signal Inst_decodisa_dadrL_N2141 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_21_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N2071 : STD_LOGIC; + signal Inst_decodisa_dadrL_N2070 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_20_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N2000 : STD_LOGIC; + signal Inst_decodisa_dadrL_N1999 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_19_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N1929 : STD_LOGIC; + signal Inst_decodisa_dadrL_N1928 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_18_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N1858 : STD_LOGIC; + signal Inst_decodisa_dadrL_N1857 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_17_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N1787 : STD_LOGIC; + signal Inst_decodisa_dadrL_N1786 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_16_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N1716 : STD_LOGIC; + signal Inst_decodisa_dadrL_N1715 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_15_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N1645 : STD_LOGIC; + signal Inst_decodisa_dadrL_N1644 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_14_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N1574 : STD_LOGIC; + signal Inst_decodisa_dadrL_N1573 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_13_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N1503 : STD_LOGIC; + signal Inst_decodisa_dadrL_N1502 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_12_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N1432 : STD_LOGIC; + signal Inst_decodisa_dadrL_N1431 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_11_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N1361 : STD_LOGIC; + signal Inst_decodisa_dadrL_N1360 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_10_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N1290 : STD_LOGIC; + signal Inst_decodisa_dadrL_N1289 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_9_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N1219 : STD_LOGIC; + signal Inst_decodisa_dadrL_N1218 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_8_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N1148 : STD_LOGIC; + signal Inst_decodisa_dadrL_N1147 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_7_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N1077 : STD_LOGIC; + signal Inst_decodisa_dadrL_N1076 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_6_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N1006 : STD_LOGIC; + signal Inst_decodisa_dadrL_N1005 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_5_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N935 : STD_LOGIC; + signal Inst_decodisa_dadrL_N934 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_4_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N864 : STD_LOGIC; + signal Inst_decodisa_dadrL_N863 : STD_LOGIC; + signal Inst_decodisa_dadrL_N793 : STD_LOGIC; + signal Inst_decodisa_dadrL_N792 : STD_LOGIC; + signal Inst_decodisa_dadrL_N722 : STD_LOGIC; + signal Inst_decodisa_dadrL_N721 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_1_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N651 : STD_LOGIC; + signal Inst_decodisa_dadrL_N650 : STD_LOGIC; + signal Inst_decodisa_dadrL_O_0_Q : STD_LOGIC; + signal Inst_decodisa_dadrL_N580 : STD_LOGIC; + signal Inst_decodisa_dadrL_N579 : STD_LOGIC; + signal Inst_decodisa_dadrL_N0 : STD_LOGIC; + signal clk_speed_BUFGP_IBUFG : STD_LOGIC; + signal GSR : STD_LOGIC; + signal Inst_rxserie1_RCONF_REG_7_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_RCONF_REG_0_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_RFLAG_REG_0_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_FIFO1_wr_en_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_RCONF_REG_6_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_RCONF_REG_5_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_RCONF_REG_4_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_RCONF_REG_3_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_RFLAG_REG_6_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_RCONF_REG_1_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_RFLAG_REG_5_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_RCONF_REG_2_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_RFLAG_REG_4_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_RFLAG_REG_3_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_RFLAG_REG_2_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_RFLAG_REG_1_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_RC1_RHR_6_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_RC1_RHR_3_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_RC1_RHR_5_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_RC1_RHR_4_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_RC1_RHR_0_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_RC1_RHR_2_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_RC1_RHR_1_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_RC1_READ2_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_RC1_IDLE1_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_RC1_READ1_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_RC1_IDLE_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_RC1_HUNT_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_RC1_RXCNT_1_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_RC1_RX1_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_RC1_RXCLK_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_RC1_RXPARITY_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_RC1_PARITYGEN_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_RC1_RXSTOP_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_RC1_RSR_7_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_RC1_RSR_6_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_RC1_RSR_5_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_RC1_RSR_4_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_RC1_RSR_3_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_RC1_RSR_2_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_RC1_RSR_1_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_RC1_RSR_0_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_RC1_RHR_7_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_RC1_RXDATARDY_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_RC1_OVERRUN_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_RC1_PARITY_ERR_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_RC1_FRAMING_ERR_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_RC1_RXCNT_3_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_RC1_RXCNT_2_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_RC1_RXCNT_0_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_CLOCK1_ckout_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_CLOCK1_compteur_9_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_CLOCK1_compteur_8_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_CLOCK1_compteur_0_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_CLOCK1_compteur_1_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_CLOCK1_compteur_2_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_CLOCK1_compteur_3_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_CLOCK1_compteur_4_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_CLOCK1_compteur_5_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_CLOCK1_compteur_6_GSR_OR : STD_LOGIC; + signal Inst_rxserie1_CLOCK1_compteur_7_GSR_OR : STD_LOGIC; + signal GTS : STD_LOGIC; + signal bus_data_0_IOBUF_OBUFT_GTS_AND : STD_LOGIC; + signal bus_data_1_IOBUF_OBUFT_GTS_AND : STD_LOGIC; + signal bus_data_2_IOBUF_OBUFT_GTS_AND : STD_LOGIC; + signal bus_data_3_IOBUF_OBUFT_GTS_AND : STD_LOGIC; + signal bus_data_4_IOBUF_OBUFT_GTS_AND : STD_LOGIC; + signal bus_data_5_IOBUF_OBUFT_GTS_AND : STD_LOGIC; + signal bus_data_6_IOBUF_OBUFT_GTS_AND : STD_LOGIC; + signal bus_data_7_IOBUF_OBUFT_GTS_AND : STD_LOGIC; + signal VCC : STD_LOGIC; + signal GND : STD_LOGIC; + signal NlwInverterSignal_Inst_rxserie1_I7_0_T : STD_LOGIC; + signal NlwInverterSignal_Inst_rxserie1_I7_7_T : STD_LOGIC; + signal NlwInverterSignal_Inst_rxserie1_I7_6_T : STD_LOGIC; + signal NlwInverterSignal_Inst_rxserie1_I7_5_T : STD_LOGIC; + signal NlwInverterSignal_Inst_rxserie1_I7_4_T : STD_LOGIC; + signal NlwInverterSignal_Inst_rxserie1_I7_3_T : STD_LOGIC; + signal NlwInverterSignal_Inst_rxserie1_I7_2_T : STD_LOGIC; + signal NlwInverterSignal_Inst_rxserie1_I7_1_T : STD_LOGIC; + signal NlwInverterSignal_Inst_rxserie1_FIFO1_wr_en_C : STD_LOGIC; + signal NlwInverterSignal_Inst_rxserie1_FIFO1_state_write_FFd1_C : STD_LOGIC; + signal NlwInverterSignal_Inst_rxserie1_RFLAG_I1_1_T : STD_LOGIC; + signal NlwInverterSignal_Inst_rxserie1_RFLAG_I1_2_T : STD_LOGIC; + signal NlwInverterSignal_Inst_rxserie1_RFLAG_I1_0_T : STD_LOGIC; + signal NlwInverterSignal_Inst_rxserie1_RFLAG_I1_7_T : STD_LOGIC; + signal NlwInverterSignal_Inst_rxserie1_RFLAG_I1_6_T : STD_LOGIC; + signal NlwInverterSignal_Inst_rxserie1_RFLAG_I1_5_T : STD_LOGIC; + signal NlwInverterSignal_Inst_rxserie1_RFLAG_I1_4_T : STD_LOGIC; + signal NlwInverterSignal_Inst_rxserie1_RFLAG_I1_3_T : STD_LOGIC; + signal NlwInverterSignal_Inst_rxserie1_RCONF_I1_1_T : STD_LOGIC; + signal NlwInverterSignal_Inst_rxserie1_RCONF_I1_2_T : STD_LOGIC; + signal NlwInverterSignal_Inst_rxserie1_RCONF_I1_0_T : STD_LOGIC; + signal NlwInverterSignal_Inst_rxserie1_RCONF_I1_7_T : STD_LOGIC; + signal NlwInverterSignal_Inst_rxserie1_RCONF_I1_6_T : STD_LOGIC; + signal NlwInverterSignal_Inst_rxserie1_RCONF_I1_5_T : STD_LOGIC; + signal NlwInverterSignal_Inst_rxserie1_RCONF_I1_4_T : STD_LOGIC; + signal NlwInverterSignal_Inst_rxserie1_RCONF_I1_3_T : STD_LOGIC; + signal NlwInverterSignal_Inst_rxserie1_FIFO1_state_write_FFd3_C : STD_LOGIC; + signal NlwInverterSignal_Inst_rxserie1_FIFO1_state_write_FFd2_C : STD_LOGIC; + signal NLW_Inst_rxserie1_FIFO1_fifo0_BU161_O_UNCONNECTED : STD_LOGIC; + signal NLW_Inst_rxserie1_FIFO1_fifo0_BU143_O_UNCONNECTED : STD_LOGIC; + signal NLW_Inst_rxserie1_FIFO1_fifo0_BU137_O_UNCONNECTED : STD_LOGIC; + signal NLW_Inst_rxserie1_FIFO1_fifo0_BU7_O_UNCONNECTED : STD_LOGIC; + signal NLW_Inst_decodisa_dadrL_VCC_O_UNCONNECTED : STD_LOGIC; + signal NlwInverterSignal_bus_data_0_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; + signal NlwInverterSignal_bus_data_0_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; + signal NlwInverterSignal_bus_data_1_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; + signal NlwInverterSignal_bus_data_1_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; + signal NlwInverterSignal_bus_data_2_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; + signal NlwInverterSignal_bus_data_2_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; + signal NlwInverterSignal_bus_data_3_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; + signal NlwInverterSignal_bus_data_3_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; + signal NlwInverterSignal_bus_data_4_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; + signal NlwInverterSignal_bus_data_4_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; + signal NlwInverterSignal_bus_data_5_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; + signal NlwInverterSignal_bus_data_5_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; + signal NlwInverterSignal_bus_data_6_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; + signal NlwInverterSignal_bus_data_6_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; + signal NlwInverterSignal_bus_data_7_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; + signal NlwInverterSignal_bus_data_7_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; + signal cs : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal Inst_rxserie1_CLOCK1_compteur_n0001 : STD_LOGIC_VECTOR ( 9 downto 0 ); + signal Inst_rxserie1_CLOCK1_compteur_n0005 : STD_LOGIC_VECTOR ( 9 downto 0 ); + signal Inst_rxserie1_RFLAG_REG : STD_LOGIC_VECTOR ( 6 downto 0 ); + signal Inst_rxserie1_RCONF_REG : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal Inst_rxserie1_inter_fifo : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal Inst_rxserie1_RC1_RHR : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal Inst_rxserie1_flagreg : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal Inst_rxserie1_RC1_n0018 : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal Inst_rxserie1_RC1_RSR : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal Inst_rxserie1_RC1_n0040 : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal Inst_rxserie1_RC1_RXCNT : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal Inst_rxserie1_CLOCK1_compteur : STD_LOGIC_VECTOR ( 9 downto 0 ); +begin + Inst_rxserie1_FIFO1_state_write_FFd1_In1 : X_LUT4 + generic map( + INIT => X"FF04" + ) + port map ( + ADR0 => Inst_rxserie1_flagreg(2), + ADR1 => Inst_rxserie1_FIFO1_state_write_FFd1, + ADR2 => Inst_rxserie1_rxread, + ADR3 => Inst_rxserie1_FIFO1_state_write_FFd2, + O => Inst_rxserie1_FIFO1_state_write_FFd1_In + ); + Inst_decodisa_n00021 : X_LUT3 + generic map( + INIT => X"F8" + ) + port map ( + ADR0 => IOW_IBUF, + ADR1 => IOR_IBUF, + ADR2 => AEN_IBUF, + O => bus_clk + ); + XST_GND : X_ZERO + port map ( + O => Inst_rxserie1_FIFO1_state_read_FFd2 + ); + Inst_rxserie1_geneck1 : X_LUT2 + generic map( + INIT => X"8" + ) + port map ( + ADR0 => Inst_rxserie1_RCONF_REG(4), + ADR1 => clk_ref_IBUF, + O => Inst_rxserie1_geneck + ); + Inst_rxserie1_CLOCK1_compteur_Mmux_n0001_Result_2_1 : X_LUT4 + generic map( + INIT => X"10FE" + ) + port map ( + ADR0 => Inst_rxserie1_CLOCK1_n0005, + ADR1 => rst_IBUF, + ADR2 => Inst_rxserie1_CLOCK1_compteur_n0005(2), + ADR3 => Inst_rxserie1_RCONF_REG(1), + O => Inst_rxserie1_CLOCK1_compteur_n0001(2) + ); + Inst_rxserie1_FIFO1_state_write_FFd3_In1 : X_LUT4 + generic map( + INIT => X"EEE0" + ) + port map ( + ADR0 => Inst_rxserie1_rxread, + ADR1 => Inst_rxserie1_flagreg(2), + ADR2 => Inst_rxserie1_FIFO1_state_write_FFd1, + ADR3 => Inst_rxserie1_FIFO1_state_write_FFd3, + O => Inst_rxserie1_FIFO1_state_write_FFd3_In + ); + Inst_rxserie1_state_rx_read_FFd2_0 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_rxserie1_state_rx_read_FFd3, + CLK => Inst_rxserie1_CLOCK1_ckout, + O => Inst_rxserie1_state_rx_read_FFd2, + CE => VCC, + SET => GND, + RST => GSR + ); + Inst_rxserie1_state_rx_read_FFd1_In11 : X_LUT2 + generic map( + INIT => X"8" + ) + port map ( + ADR0 => Inst_rxserie1_RC1_RXDATARDY, + ADR1 => Inst_rxserie1_state_rx_read_FFd1, + O => N11003 + ); + Inst_rxserie1_RCONF_REG_7 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N11001, + CE => Inst_rxserie1_RCONF_n0007, + RST => Inst_rxserie1_RCONF_REG_7_GSR_OR, + SET => Inst_rxserie1_FIFO1_state_read_FFd2, + CLK => bus_clk, + O => Inst_rxserie1_RCONF_REG(7) + ); + XST_VCC : X_ONE + port map ( + O => Inst_rxserie1_I7_N1369 + ); + Inst_rxserie1_I7_0 : X_TRI + port map ( + I => Inst_rxserie1_inter_fifo(7), + CTL => NlwInverterSignal_Inst_rxserie1_I7_0_T, + O => bus_data_7_IOBUF + ); + Inst_rxserie1_state_rx_read_FFd4_1 : X_SFF + generic map( + INIT => '1' + ) + port map ( + I => Inst_rxserie1_I7_N1369, + SRST => Inst_rxserie1_RC1_RXDATARDY, + CE => Inst_rxserie1_state_rx_read_FFd1, + CLK => Inst_rxserie1_CLOCK1_ckout, + O => Inst_rxserie1_state_rx_read_FFd4, + SET => GSR, + RST => GND, + SSET => GND + ); + Inst_rxserie1_RCONF_REG_0 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N10987, + CE => Inst_rxserie1_RCONF_n0007, + RST => Inst_rxserie1_RCONF_REG_0_GSR_OR, + SET => Inst_rxserie1_FIFO1_state_read_FFd2, + CLK => bus_clk, + O => Inst_rxserie1_RCONF_REG(0) + ); + Inst_rxserie1_rxread_2 : X_SFF + generic map( + INIT => '0' + ) + port map ( + I => Inst_rxserie1_I7_N1369, + SRST => Inst_rxserie1_state_rx_read_FFd2, + CLK => Inst_rxserie1_CLOCK1_ckout, + O => Inst_rxserie1_rxread, + CE => VCC, + SET => GND, + RST => GSR, + SSET => GND + ); + Inst_rxserie1_state_rx_read_FFd3_3 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_rxserie1_state_rx_read_FFd3_In, + CLK => Inst_rxserie1_CLOCK1_ckout, + O => Inst_rxserie1_state_rx_read_FFd3, + CE => VCC, + SET => GND, + RST => GSR + ); + Inst_rxserie1_RC1_Madd_n0040_inst_cy_10_4 : X_MUX2 + port map ( + IB => Inst_rxserie1_FIFO1_state_read_FFd2, + IA => Inst_rxserie1_I7_N1369, + SEL => Inst_rxserie1_RC1_Madd_n0040_inst_lut2_10, + O => Inst_rxserie1_RC1_Madd_n0040_inst_cy_10 + ); + Inst_rxserie1_RFLAG_REG_0 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_rxserie1_flagreg(0), + CE => Inst_rxserie1_RFLAG_n0007, + RST => Inst_rxserie1_RFLAG_REG_0_GSR_OR, + SET => Inst_rxserie1_flagreg(0), + CLK => bus_clk, + O => Inst_rxserie1_RFLAG_REG(0) + ); + Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_sum_5 : X_XOR2 + port map ( + I0 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_5, + I1 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_4, + O => Inst_rxserie1_CLOCK1_compteur_n0005(5) + ); + bus_adr_3_IBUF_5 : X_BUF + port map ( + I => bus_adr(3), + O => bus_adr_3_IBUF + ); + Inst_rxserie1_I7_7 : X_TRI + port map ( + I => Inst_rxserie1_inter_fifo(0), + CTL => NlwInverterSignal_Inst_rxserie1_I7_7_T, + O => bus_data_0_IOBUF + ); + Inst_rxserie1_I7_6 : X_TRI + port map ( + I => Inst_rxserie1_inter_fifo(1), + CTL => NlwInverterSignal_Inst_rxserie1_I7_6_T, + O => bus_data_1_IOBUF + ); + Inst_rxserie1_I7_5 : X_TRI + port map ( + I => Inst_rxserie1_inter_fifo(2), + CTL => NlwInverterSignal_Inst_rxserie1_I7_5_T, + O => bus_data_2_IOBUF + ); + Inst_rxserie1_I7_4 : X_TRI + port map ( + I => Inst_rxserie1_inter_fifo(3), + CTL => NlwInverterSignal_Inst_rxserie1_I7_4_T, + O => bus_data_3_IOBUF + ); + Inst_rxserie1_I7_3 : X_TRI + port map ( + I => Inst_rxserie1_inter_fifo(4), + CTL => NlwInverterSignal_Inst_rxserie1_I7_3_T, + O => bus_data_4_IOBUF + ); + Inst_rxserie1_I7_2 : X_TRI + port map ( + I => Inst_rxserie1_inter_fifo(5), + CTL => NlwInverterSignal_Inst_rxserie1_I7_2_T, + O => bus_data_5_IOBUF + ); + Inst_rxserie1_I7_1 : X_TRI + port map ( + I => Inst_rxserie1_inter_fifo(6), + CTL => NlwInverterSignal_Inst_rxserie1_I7_1_T, + O => bus_data_6_IOBUF + ); + Inst_rxserie1_FIFO1_state_write_FFd2_In1 : X_LUT3 + generic map( + INIT => X"04" + ) + port map ( + ADR0 => Inst_rxserie1_flagreg(2), + ADR1 => Inst_rxserie1_FIFO1_state_write_FFd3, + ADR2 => Inst_rxserie1_rxread, + O => Inst_rxserie1_FIFO1_state_write_FFd2_In + ); + bus_adr_2_IBUF_6 : X_BUF + port map ( + I => bus_adr(2), + O => bus_adr_2_IBUF + ); + Inst_rxserie1_FIFO1_wr_en_7 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_rxserie1_FIFO1_state_write_FFd2_In, + RST => Inst_rxserie1_FIFO1_wr_en_GSR_OR, + CLK => NlwInverterSignal_Inst_rxserie1_FIFO1_wr_en_C, + O => Inst_rxserie1_FIFO1_wr_en, + CE => VCC, + SET => GND + ); + Inst_rxserie1_RCONF_REG_6 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N10999, + CE => Inst_rxserie1_RCONF_n0007, + RST => Inst_rxserie1_RCONF_REG_6_GSR_OR, + SET => Inst_rxserie1_FIFO1_state_read_FFd2, + CLK => bus_clk, + O => Inst_rxserie1_RCONF_REG(6) + ); + Inst_rxserie1_FIFO1_state_read_FFd4_N14551 : X_LUT2 + generic map( + INIT => X"5" + ) + port map ( + ADR0 => rst_IBUF, + O => Inst_rxserie1_FIFO1_state_read_FFd4_N1455, + ADR1 => GND + ); + Inst_rxserie1_FIFO1_state_write_FFd1_8 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_rxserie1_FIFO1_state_write_FFd1_In, + CE => Inst_rxserie1_FIFO1_state_read_FFd4_N1455, + CLK => NlwInverterSignal_Inst_rxserie1_FIFO1_state_write_FFd1_C, + O => Inst_rxserie1_FIFO1_state_write_FFd1, + SET => GND, + RST => GSR + ); + bus_adr_4_IBUF_9 : X_BUF + port map ( + I => bus_adr(4), + O => bus_adr_4_IBUF + ); + Inst_rxserie1_state_rx_read_FFd3_In1 : X_LUT2 + generic map( + INIT => X"8" + ) + port map ( + ADR0 => Inst_rxserie1_RC1_RXDATARDY, + ADR1 => Inst_rxserie1_state_rx_read_FFd4, + O => Inst_rxserie1_state_rx_read_FFd3_In + ); + Inst_rxserie1_RC1_RXCNT_2_rt_10 : X_LUT2 + generic map( + INIT => X"A" + ) + port map ( + ADR0 => Inst_rxserie1_RC1_RXCNT(2), + O => Inst_rxserie1_RC1_RXCNT_2_rt, + ADR1 => GND + ); + Inst_rxserie1_RFLAG_I1_1 : X_TRI + port map ( + I => Inst_rxserie1_RFLAG_REG(6), + CTL => NlwInverterSignal_Inst_rxserie1_RFLAG_I1_1_T, + O => bus_data_6_IOBUF + ); + Inst_rxserie1_RFLAG_I1_2 : X_TRI + port map ( + I => Inst_rxserie1_RFLAG_REG(5), + CTL => NlwInverterSignal_Inst_rxserie1_RFLAG_I1_2_T, + O => bus_data_5_IOBUF + ); + Inst_rxserie1_RCONF_REG_5 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N10997, + CE => Inst_rxserie1_RCONF_n0007, + RST => Inst_rxserie1_RCONF_REG_5_GSR_OR, + SET => Inst_rxserie1_FIFO1_state_read_FFd2, + CLK => bus_clk, + O => Inst_rxserie1_RCONF_REG(5) + ); + Inst_rxserie1_RFLAG_I1_0 : X_TRI + port map ( + I => Inst_rxserie1_FIFO1_state_read_FFd2, + CTL => NlwInverterSignal_Inst_rxserie1_RFLAG_I1_0_T, + O => bus_data_7_IOBUF + ); + Inst_rxserie1_state_rx_read_FFd1_11 : X_SFF + generic map( + INIT => '0' + ) + port map ( + I => N11003, + SSET => Inst_rxserie1_state_rx_read_FFd2, + CLK => Inst_rxserie1_CLOCK1_ckout, + O => Inst_rxserie1_state_rx_read_FFd1, + CE => VCC, + SET => GND, + RST => GSR, + SRST => GND + ); + Inst_rxserie1_RFLAG_I1_EnableTr_INV1 : X_LUT3 + generic map( + INIT => X"DF" + ) + port map ( + ADR0 => cs(3), + ADR1 => rst_IBUF, + ADR2 => rw, + O => Inst_rxserie1_RFLAG_I1_N1369 + ); + Inst_rxserie1_RFLAG_I1_7 : X_TRI + port map ( + I => Inst_rxserie1_RFLAG_REG(0), + CTL => NlwInverterSignal_Inst_rxserie1_RFLAG_I1_7_T, + O => bus_data_0_IOBUF + ); + Inst_rxserie1_RFLAG_I1_6 : X_TRI + port map ( + I => Inst_rxserie1_RFLAG_REG(1), + CTL => NlwInverterSignal_Inst_rxserie1_RFLAG_I1_6_T, + O => bus_data_1_IOBUF + ); + Inst_rxserie1_RFLAG_I1_5 : X_TRI + port map ( + I => Inst_rxserie1_RFLAG_REG(2), + CTL => NlwInverterSignal_Inst_rxserie1_RFLAG_I1_5_T, + O => bus_data_2_IOBUF + ); + Inst_rxserie1_RFLAG_I1_4 : X_TRI + port map ( + I => Inst_rxserie1_RFLAG_REG(3), + CTL => NlwInverterSignal_Inst_rxserie1_RFLAG_I1_4_T, + O => bus_data_3_IOBUF + ); + Inst_rxserie1_RFLAG_I1_3 : X_TRI + port map ( + I => Inst_rxserie1_RFLAG_REG(4), + CTL => NlwInverterSignal_Inst_rxserie1_RFLAG_I1_3_T, + O => bus_data_4_IOBUF + ); + Inst_rxserie1_RCONF_REG_4 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N10995, + CE => Inst_rxserie1_RCONF_n0007, + RST => Inst_rxserie1_RCONF_REG_4_GSR_OR, + SET => Inst_rxserie1_FIFO1_state_read_FFd2, + CLK => bus_clk, + O => Inst_rxserie1_RCONF_REG(4) + ); + Inst_rxserie1_RFLAG_REG_6_n00001 : X_LUT2 + generic map( + INIT => X"5" + ) + port map ( + ADR0 => Inst_rxserie1_RC1_OVERRUN, + O => Inst_rxserie1_RFLAG_REG_6_n0000, + ADR1 => GND + ); + Inst_rxserie1_RFLAG_REG_0_n00001 : X_LUT2 + generic map( + INIT => X"5" + ) + port map ( + ADR0 => Inst_rxserie1_flagreg(0), + O => Inst_rxserie1_RFLAG_REG_0_n0000, + ADR1 => GND + ); + Inst_rxserie1_RFLAG_REG_1_n00001 : X_LUT2 + generic map( + INIT => X"5" + ) + port map ( + ADR0 => Inst_rxserie1_flagreg(1), + O => Inst_rxserie1_RFLAG_REG_1_n0000, + ADR1 => GND + ); + Inst_rxserie1_RFLAG_REG_2_n00001 : X_LUT2 + generic map( + INIT => X"5" + ) + port map ( + ADR0 => Inst_rxserie1_flagreg(2), + O => Inst_rxserie1_RFLAG_REG_2_n0000, + ADR1 => GND + ); + Inst_rxserie1_RFLAG_REG_3_n00001 : X_LUT2 + generic map( + INIT => X"5" + ) + port map ( + ADR0 => Inst_rxserie1_flagreg(3), + O => Inst_rxserie1_RFLAG_REG_3_n0000, + ADR1 => GND + ); + Inst_rxserie1_RFLAG_REG_4_n00001 : X_LUT2 + generic map( + INIT => X"5" + ) + port map ( + ADR0 => Inst_rxserie1_RC1_PARITY_ERR, + O => Inst_rxserie1_RFLAG_REG_4_n0000, + ADR1 => GND + ); + Inst_rxserie1_RFLAG_REG_5_n00001 : X_LUT2 + generic map( + INIT => X"5" + ) + port map ( + ADR0 => Inst_rxserie1_RC1_FRAMING_ERR, + O => Inst_rxserie1_RFLAG_REG_5_n0000, + ADR1 => GND + ); + Inst_rxserie1_RCONF_REG_3 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N10993, + CE => Inst_rxserie1_RCONF_n0007, + RST => Inst_rxserie1_RCONF_REG_3_GSR_OR, + SET => Inst_rxserie1_FIFO1_state_read_FFd2, + CLK => bus_clk, + O => Inst_rxserie1_RCONF_REG(3) + ); + bus_adr_1_IBUF_12 : X_BUF + port map ( + I => bus_adr(1), + O => bus_adr_1_IBUF + ); + Inst_rxserie1_RFLAG_REG_6 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_rxserie1_RC1_OVERRUN, + CE => Inst_rxserie1_RFLAG_n0007, + RST => Inst_rxserie1_RFLAG_REG_6_GSR_OR, + SET => Inst_rxserie1_RC1_OVERRUN, + CLK => bus_clk, + O => Inst_rxserie1_RFLAG_REG(6) + ); + Inst_rxserie1_RCONF_REG_1 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N10989, + CE => Inst_rxserie1_RCONF_n0007, + RST => Inst_rxserie1_RCONF_REG_1_GSR_OR, + SET => Inst_rxserie1_FIFO1_state_read_FFd2, + CLK => bus_clk, + O => Inst_rxserie1_RCONF_REG(1) + ); + Inst_rxserie1_RFLAG_REG_5 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_rxserie1_RC1_FRAMING_ERR, + CE => Inst_rxserie1_RFLAG_n0007, + RST => Inst_rxserie1_RFLAG_REG_5_GSR_OR, + SET => Inst_rxserie1_RC1_FRAMING_ERR, + CLK => bus_clk, + O => Inst_rxserie1_RFLAG_REG(5) + ); + Inst_rxserie1_RCONF_REG_2 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => N10991, + CE => Inst_rxserie1_RCONF_n0007, + RST => Inst_rxserie1_RCONF_REG_2_GSR_OR, + SET => Inst_rxserie1_FIFO1_state_read_FFd2, + CLK => bus_clk, + O => Inst_rxserie1_RCONF_REG(2) + ); + Inst_rxserie1_RFLAG_REG_4 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_rxserie1_RC1_PARITY_ERR, + CE => Inst_rxserie1_RFLAG_n0007, + RST => Inst_rxserie1_RFLAG_REG_4_GSR_OR, + SET => Inst_rxserie1_RC1_PARITY_ERR, + CLK => bus_clk, + O => Inst_rxserie1_RFLAG_REG(4) + ); + bus_adr_6_IBUF_13 : X_BUF + port map ( + I => bus_adr(6), + O => bus_adr_6_IBUF + ); + Inst_rxserie1_RFLAG_REG_3 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_rxserie1_flagreg(3), + CE => Inst_rxserie1_RFLAG_n0007, + RST => Inst_rxserie1_RFLAG_REG_3_GSR_OR, + SET => Inst_rxserie1_flagreg(3), + CLK => bus_clk, + O => Inst_rxserie1_RFLAG_REG(3) + ); + bus_adr_7_IBUF_14 : X_BUF + port map ( + I => bus_adr(7), + O => bus_adr_7_IBUF + ); + Inst_rxserie1_RFLAG_REG_2 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_rxserie1_flagreg(2), + CE => Inst_rxserie1_RFLAG_n0007, + RST => Inst_rxserie1_RFLAG_REG_2_GSR_OR, + SET => Inst_rxserie1_flagreg(2), + CLK => bus_clk, + O => Inst_rxserie1_RFLAG_REG(2) + ); + bus_adr_5_IBUF_15 : X_BUF + port map ( + I => bus_adr(5), + O => bus_adr_5_IBUF + ); + Inst_rxserie1_RFLAG_REG_1 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_rxserie1_flagreg(1), + CE => Inst_rxserie1_RFLAG_n0007, + RST => Inst_rxserie1_RFLAG_REG_1_GSR_OR, + SET => Inst_rxserie1_flagreg(1), + CLK => bus_clk, + O => Inst_rxserie1_RFLAG_REG(1) + ); + bus_adr_8_IBUF_16 : X_BUF + port map ( + I => bus_adr(8), + O => bus_adr_8_IBUF + ); + Inst_rxserie1_RFLAG_n00071 : X_LUT4 + generic map( + INIT => X"FB00" + ) + port map ( + ADR0 => IOR_IBUF, + ADR1 => IOW_IBUF, + ADR2 => AEN_IBUF, + ADR3 => cs(3), + O => Inst_rxserie1_RFLAG_n0007 + ); + Inst_rxserie1_RCONF_I1_1 : X_TRI + port map ( + I => Inst_rxserie1_RCONF_REG(6), + CTL => NlwInverterSignal_Inst_rxserie1_RCONF_I1_1_T, + O => bus_data_6_IOBUF + ); + Inst_rxserie1_RCONF_I1_2 : X_TRI + port map ( + I => Inst_rxserie1_RCONF_REG(5), + CTL => NlwInverterSignal_Inst_rxserie1_RCONF_I1_2_T, + O => bus_data_5_IOBUF + ); + N48051 : X_LUT4 + generic map( + INIT => X"CFDF" + ) + port map ( + ADR0 => cs(3), + ADR1 => rst_IBUF, + ADR2 => rw, + ADR3 => cs(2), + O => N4805 + ); + Inst_rxserie1_RCONF_I1_0 : X_TRI + port map ( + I => Inst_rxserie1_RCONF_REG(7), + CTL => NlwInverterSignal_Inst_rxserie1_RCONF_I1_0_T, + O => bus_data_7_IOBUF + ); + Inst_rxserie1_RCONF_n00071 : X_LUT4 + generic map( + INIT => X"FB00" + ) + port map ( + ADR0 => IOR_IBUF, + ADR1 => IOW_IBUF, + ADR2 => AEN_IBUF, + ADR3 => cs(2), + O => Inst_rxserie1_RCONF_n0007 + ); + Inst_rxserie1_RCONF_I1_EnableTr_INV1 : X_LUT3 + generic map( + INIT => X"DF" + ) + port map ( + ADR0 => cs(2), + ADR1 => rst_IBUF, + ADR2 => rw, + O => Inst_rxserie1_RCONF_I1_N1369 + ); + Inst_rxserie1_RCONF_I1_7 : X_TRI + port map ( + I => Inst_rxserie1_RCONF_REG(0), + CTL => NlwInverterSignal_Inst_rxserie1_RCONF_I1_7_T, + O => bus_data_0_IOBUF + ); + Inst_rxserie1_RCONF_I1_6 : X_TRI + port map ( + I => Inst_rxserie1_RCONF_REG(1), + CTL => NlwInverterSignal_Inst_rxserie1_RCONF_I1_6_T, + O => bus_data_1_IOBUF + ); + Inst_rxserie1_RCONF_I1_5 : X_TRI + port map ( + I => Inst_rxserie1_RCONF_REG(2), + CTL => NlwInverterSignal_Inst_rxserie1_RCONF_I1_5_T, + O => bus_data_2_IOBUF + ); + Inst_rxserie1_RCONF_I1_4 : X_TRI + port map ( + I => Inst_rxserie1_RCONF_REG(3), + CTL => NlwInverterSignal_Inst_rxserie1_RCONF_I1_4_T, + O => bus_data_3_IOBUF + ); + Inst_rxserie1_RCONF_I1_3 : X_TRI + port map ( + I => Inst_rxserie1_RCONF_REG(4), + CTL => NlwInverterSignal_Inst_rxserie1_RCONF_I1_3_T, + O => bus_data_4_IOBUF + ); + Inst_rxserie1_FIFO1_state_write_FFd3_17 : X_FF + generic map( + INIT => '1' + ) + port map ( + I => Inst_rxserie1_FIFO1_state_write_FFd3_In, + CE => Inst_rxserie1_FIFO1_state_read_FFd4_N1455, + CLK => NlwInverterSignal_Inst_rxserie1_FIFO1_state_write_FFd3_C, + O => Inst_rxserie1_FIFO1_state_write_FFd3, + SET => GSR, + RST => GND + ); + Inst_rxserie1_FIFO1_state_write_FFd2_18 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_rxserie1_FIFO1_state_write_FFd2_In, + CE => Inst_rxserie1_FIFO1_state_read_FFd4_N1455, + CLK => NlwInverterSignal_Inst_rxserie1_FIFO1_state_write_FFd2_C, + O => Inst_rxserie1_FIFO1_state_write_FFd2, + SET => GND, + RST => GSR + ); + Inst_rxserie1_CLOCK1_compteur_2_n00001 : X_LUT2 + generic map( + INIT => X"8" + ) + port map ( + ADR0 => rst_IBUF, + ADR1 => Inst_rxserie1_RCONF_REG(1), + O => Inst_rxserie1_CLOCK1_compteur_0_2_n0000 + ); + Inst_rxserie1_CLOCK1_n000539_SW0 : X_LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + ADR0 => Inst_rxserie1_CLOCK1_compteur(6), + ADR1 => Inst_rxserie1_CLOCK1_compteur(7), + ADR2 => Inst_rxserie1_CLOCK1_compteur(8), + ADR3 => Inst_rxserie1_CLOCK1_compteur(9), + O => N11021 + ); + Inst_decodisa_n00031 : X_LUT3 + generic map( + INIT => X"04" + ) + port map ( + ADR0 => IOR_IBUF, + ADR1 => IOW_IBUF, + ADR2 => AEN_IBUF, + O => rw + ); + Inst_rxserie1_RC1_Madd_n0040_inst_cy_12_19 : X_MUX2 + port map ( + IB => Inst_rxserie1_RC1_Madd_n0040_inst_cy_11, + IA => Inst_rxserie1_FIFO1_state_read_FFd2, + SEL => Inst_rxserie1_RC1_RXCNT_2_rt, + O => Inst_rxserie1_RC1_Madd_n0040_inst_cy_12 + ); + Inst_rxserie1_RC1_Madd_n0040_inst_sum_12 : X_XOR2 + port map ( + I0 => Inst_rxserie1_RC1_RXCNT_2_rt, + I1 => Inst_rxserie1_RC1_Madd_n0040_inst_cy_11, + O => Inst_rxserie1_RC1_n0040(2) + ); + Inst_rxserie1_RC1_n00631 : X_LUT4 + generic map( + INIT => X"44F4" + ) + port map ( + ADR0 => Inst_rxserie1_RC1_READ2, + ADR1 => Inst_rxserie1_RC1_READ1, + ADR2 => Inst_rxserie1_RC1_IDLE, + ADR3 => Inst_rxserie1_RC1_IDLE1, + O => Inst_rxserie1_RC1_n0063 + ); + Inst_rxserie1_RC1_n00621 : X_LUT3 + generic map( + INIT => X"BA" + ) + port map ( + ADR0 => Inst_rxserie1_RC1_N7296, + ADR1 => Inst_rxserie1_RC1_READ2, + ADR2 => Inst_rxserie1_RC1_READ1, + O => Inst_rxserie1_RC1_n0062 + ); + Inst_rxserie1_RC1_Ker72941 : X_LUT3 + generic map( + INIT => X"04" + ) + port map ( + ADR0 => Inst_rxserie1_RC1_IDLE1, + ADR1 => Inst_rxserie1_RC1_IDLE, + ADR2 => Inst_rxserie1_RC1_RXDATARDY, + O => Inst_rxserie1_RC1_N7296 + ); + Inst_rxserie1_RC1_RXCNT_1_rt_20 : X_LUT2 + generic map( + INIT => X"A" + ) + port map ( + ADR0 => Inst_rxserie1_RC1_RXCNT(1), + O => Inst_rxserie1_RC1_RXCNT_1_rt, + ADR1 => GND + ); + Inst_rxserie1_RC1_n00501 : X_LUT3 + generic map( + INIT => X"EF" + ) + port map ( + ADR0 => rxin1_IBUF, + ADR1 => Inst_rxserie1_RC1_RX1, + ADR2 => Inst_rxserie1_RC1_IDLE, + O => Inst_rxserie1_RC1_n0050 + ); + Inst_rxserie1_RC1_RHR_6 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_rxserie1_RC1_RSR(6), + CE => Inst_rxserie1_RC1_N7296, + RST => Inst_rxserie1_RC1_RHR_6_GSR_OR, + CLK => Inst_rxserie1_CLOCK1_ckout, + O => Inst_rxserie1_RC1_RHR(6), + SET => GND + ); + Inst_rxserie1_RC1_RHR_3 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_rxserie1_RC1_RSR(3), + CE => Inst_rxserie1_RC1_N7296, + RST => Inst_rxserie1_RC1_RHR_3_GSR_OR, + CLK => Inst_rxserie1_CLOCK1_ckout, + O => Inst_rxserie1_RC1_RHR(3), + SET => GND + ); + Inst_rxserie1_RC1_RHR_5 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_rxserie1_RC1_RSR(5), + CE => Inst_rxserie1_RC1_N7296, + RST => Inst_rxserie1_RC1_RHR_5_GSR_OR, + CLK => Inst_rxserie1_CLOCK1_ckout, + O => Inst_rxserie1_RC1_RHR(5), + SET => GND + ); + Inst_rxserie1_RC1_RHR_4 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_rxserie1_RC1_RSR(4), + CE => Inst_rxserie1_RC1_N7296, + RST => Inst_rxserie1_RC1_RHR_4_GSR_OR, + CLK => Inst_rxserie1_CLOCK1_ckout, + O => Inst_rxserie1_RC1_RHR(4), + SET => GND + ); + Inst_rxserie1_RC1_RHR_0 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_rxserie1_RC1_RSR(0), + CE => Inst_rxserie1_RC1_N7296, + RST => Inst_rxserie1_RC1_RHR_0_GSR_OR, + CLK => Inst_rxserie1_CLOCK1_ckout, + O => Inst_rxserie1_RC1_RHR(0), + SET => GND + ); + Inst_rxserie1_RC1_RHR_2 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_rxserie1_RC1_RSR(2), + CE => Inst_rxserie1_RC1_N7296, + RST => Inst_rxserie1_RC1_RHR_2_GSR_OR, + CLK => Inst_rxserie1_CLOCK1_ckout, + O => Inst_rxserie1_RC1_RHR(2), + SET => GND + ); + Inst_rxserie1_RC1_RHR_1 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_rxserie1_RC1_RSR(1), + CE => Inst_rxserie1_RC1_N7296, + RST => Inst_rxserie1_RC1_RHR_1_GSR_OR, + CLK => Inst_rxserie1_CLOCK1_ckout, + O => Inst_rxserie1_RC1_RHR(1), + SET => GND + ); + Inst_rxserie1_RC1_n00411 : X_LUT3 + generic map( + INIT => X"A2" + ) + port map ( + ADR0 => Inst_rxserie1_RC1_RXDATARDY, + ADR1 => Inst_rxserie1_RC1_READ1, + ADR2 => Inst_rxserie1_RC1_READ2, + O => Inst_rxserie1_RC1_n0041 + ); + Inst_rxserie1_RC1_READ2_21 : X_FF + generic map( + INIT => '1' + ) + port map ( + I => Inst_rxserie1_RC1_READ1, + SET => Inst_rxserie1_RC1_READ2_GSR_OR, + CLK => Inst_rxserie1_CLOCK1_ckout, + O => Inst_rxserie1_RC1_READ2, + CE => VCC, + RST => GND + ); + Inst_rxserie1_RC1_n00311 : X_LUT2 + generic map( + INIT => X"D" + ) + port map ( + ADR0 => Inst_rxserie1_RC1_READ1, + ADR1 => Inst_rxserie1_RC1_READ2, + O => Inst_rxserie1_RC1_n0031 + ); + Inst_rxserie1_RC1_n0018_1_1 : X_LUT3 + generic map( + INIT => X"A2" + ) + port map ( + ADR0 => Inst_rxserie1_RC1_n0040(1), + ADR1 => Inst_rxserie1_RC1_IDLE, + ADR2 => Inst_rxserie1_RC1_HUNT, + O => Inst_rxserie1_RC1_n0018(1) + ); + Inst_rxserie1_RC1_n00361 : X_LUT3 + generic map( + INIT => X"40" + ) + port map ( + ADR0 => rxin1_IBUF, + ADR1 => Inst_rxserie1_RC1_IDLE, + ADR2 => Inst_rxserie1_RC1_RX1, + O => Inst_rxserie1_RC1_n0036 + ); + Inst_rxserie1_RC1_n00351 : X_LUT3 + generic map( + INIT => X"51" + ) + port map ( + ADR0 => Inst_rxserie1_RC1_RXSTOP, + ADR1 => Inst_rxserie1_RC1_READ1, + ADR2 => Inst_rxserie1_RC1_READ2, + O => Inst_rxserie1_RC1_n0035 + ); + Inst_rxserie1_RC1_n00341 : X_LUT3 + generic map( + INIT => X"A2" + ) + port map ( + ADR0 => Inst_rxserie1_RC1_PARITYGEN, + ADR1 => Inst_rxserie1_RC1_READ1, + ADR2 => Inst_rxserie1_RC1_READ2, + O => Inst_rxserie1_RC1_n0034 + ); + Inst_rxserie1_RC1_Madd_n0040_inst_cy_11_22 : X_MUX2 + port map ( + IB => Inst_rxserie1_RC1_Madd_n0040_inst_cy_10, + IA => Inst_rxserie1_FIFO1_state_read_FFd2, + SEL => Inst_rxserie1_RC1_RXCNT_1_rt, + O => Inst_rxserie1_RC1_Madd_n0040_inst_cy_11 + ); + Inst_rxserie1_RC1_n00291 : X_LUT2 + generic map( + INIT => X"E" + ) + port map ( + ADR0 => Inst_rxserie1_RC1_IDLE, + ADR1 => Inst_rxserie1_RC1_RSR(1), + O => Inst_rxserie1_RC1_n0029 + ); + Inst_rxserie1_RC1_n00281 : X_LUT2 + generic map( + INIT => X"E" + ) + port map ( + ADR0 => Inst_rxserie1_RC1_IDLE, + ADR1 => Inst_rxserie1_RC1_RSR(2), + O => Inst_rxserie1_RC1_n0028 + ); + Inst_rxserie1_RC1_n00271 : X_LUT2 + generic map( + INIT => X"E" + ) + port map ( + ADR0 => Inst_rxserie1_RC1_IDLE, + ADR1 => Inst_rxserie1_RC1_RSR(3), + O => Inst_rxserie1_RC1_n0027 + ); + Inst_rxserie1_RC1_n00261 : X_LUT2 + generic map( + INIT => X"E" + ) + port map ( + ADR0 => Inst_rxserie1_RC1_IDLE, + ADR1 => Inst_rxserie1_RC1_RSR(4), + O => Inst_rxserie1_RC1_n0026 + ); + Inst_rxserie1_RC1_n00251 : X_LUT2 + generic map( + INIT => X"E" + ) + port map ( + ADR0 => Inst_rxserie1_RC1_IDLE, + ADR1 => Inst_rxserie1_RC1_RSR(5), + O => Inst_rxserie1_RC1_n0025 + ); + Inst_rxserie1_RC1_n00241 : X_LUT2 + generic map( + INIT => X"E" + ) + port map ( + ADR0 => Inst_rxserie1_RC1_IDLE, + ADR1 => Inst_rxserie1_RC1_RSR(6), + O => Inst_rxserie1_RC1_n0024 + ); + Inst_rxserie1_RC1_n00231 : X_LUT2 + generic map( + INIT => X"E" + ) + port map ( + ADR0 => Inst_rxserie1_RC1_IDLE, + ADR1 => Inst_rxserie1_RC1_RSR(7), + O => Inst_rxserie1_RC1_n0023 + ); + Inst_rxserie1_RC1_n00221 : X_LUT2 + generic map( + INIT => X"E" + ) + port map ( + ADR0 => Inst_rxserie1_RC1_IDLE, + ADR1 => Inst_rxserie1_RC1_RXPARITY, + O => Inst_rxserie1_RC1_n0022 + ); + Inst_rxserie1_RC1_n00211 : X_LUT2 + generic map( + INIT => X"4" + ) + port map ( + ADR0 => Inst_rxserie1_RC1_IDLE, + ADR1 => rxin1_IBUF, + O => Inst_rxserie1_RC1_n0021 + ); + Inst_rxserie1_RC1_n00201 : X_LUT3 + generic map( + INIT => X"F6" + ) + port map ( + ADR0 => Inst_rxserie1_RC1_RXSTOP, + ADR1 => Inst_rxserie1_RC1_PARITYGEN, + ADR2 => Inst_rxserie1_RC1_IDLE, + O => Inst_rxserie1_RC1_n0020 + ); + Inst_rxserie1_RC1_n00191 : X_LUT2 + generic map( + INIT => X"E" + ) + port map ( + ADR0 => Inst_rxserie1_RC1_IDLE, + ADR1 => Inst_rxserie1_RC1_RXSTOP, + O => Inst_rxserie1_RC1_n0019 + ); + Inst_rxserie1_RC1_n00511 : X_LUT3 + generic map( + INIT => X"DF" + ) + port map ( + ADR0 => Inst_rxserie1_RC1_IDLE, + ADR1 => rxin1_IBUF, + ADR2 => Inst_rxserie1_RC1_RX1, + O => Inst_rxserie1_RC1_n0051 + ); + Inst_rxserie1_RC1_Madd_n0040_inst_sum_11 : X_XOR2 + port map ( + I0 => Inst_rxserie1_RC1_RXCNT_1_rt, + I1 => Inst_rxserie1_RC1_Madd_n0040_inst_cy_10, + O => Inst_rxserie1_RC1_n0040(1) + ); + Inst_rxserie1_RC1_n0018_2_1 : X_LUT3 + generic map( + INIT => X"A2" + ) + port map ( + ADR0 => Inst_rxserie1_RC1_n0040(2), + ADR1 => Inst_rxserie1_RC1_IDLE, + ADR2 => Inst_rxserie1_RC1_HUNT, + O => Inst_rxserie1_RC1_n0018(2) + ); + Inst_rxserie1_RC1_n0018_3_1 : X_LUT3 + generic map( + INIT => X"A2" + ) + port map ( + ADR0 => Inst_rxserie1_RC1_n0040(3), + ADR1 => Inst_rxserie1_RC1_IDLE, + ADR2 => Inst_rxserie1_RC1_HUNT, + O => Inst_rxserie1_RC1_n0018(3) + ); + Inst_rxserie1_RC1_IDLE1_23 : X_FF + generic map( + INIT => '1' + ) + port map ( + I => Inst_rxserie1_RC1_IDLE, + SET => Inst_rxserie1_RC1_IDLE1_GSR_OR, + CLK => Inst_rxserie1_CLOCK1_ckout, + O => Inst_rxserie1_RC1_IDLE1, + CE => VCC, + RST => GND + ); + Inst_rxserie1_RC1_n00151 : X_LUT2 + generic map( + INIT => X"1" + ) + port map ( + ADR0 => Inst_rxserie1_RC1_IDLE, + ADR1 => Inst_rxserie1_RC1_RSR(0), + O => Inst_rxserie1_RC1_n0015 + ); + Inst_rxserie1_RC1_READ1_24 : X_FF + generic map( + INIT => '1' + ) + port map ( + I => Inst_rxserie1_rxread, + SET => Inst_rxserie1_RC1_READ1_GSR_OR, + CLK => Inst_rxserie1_CLOCK1_ckout, + O => Inst_rxserie1_RC1_READ1, + CE => VCC, + RST => GND + ); + Inst_rxserie1_RC1_IDLE_25 : X_FF + generic map( + INIT => '1' + ) + port map ( + I => Inst_rxserie1_RC1_n0015, + SET => Inst_rxserie1_RC1_IDLE_GSR_OR, + CLK => Inst_rxserie1_RC1_RXCLK, + O => Inst_rxserie1_RC1_IDLE, + CE => VCC, + RST => GND + ); + Inst_rxserie1_RC1_HUNT_26 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_rxserie1_RC1_n0036, + CE => Inst_rxserie1_RC1_n0050, + RST => Inst_rxserie1_RC1_HUNT_GSR_OR, + CLK => Inst_rxserie1_CLOCK1_ckout, + O => Inst_rxserie1_RC1_HUNT, + SET => GND + ); + Inst_rxserie1_RC1_RXCNT_1 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_rxserie1_RC1_n0018(1), + CE => Inst_rxserie1_RC1_n0051, + RST => Inst_rxserie1_RC1_RXCNT_1_GSR_OR, + CLK => Inst_rxserie1_CLOCK1_ckout, + O => Inst_rxserie1_RC1_RXCNT(1), + SET => GND + ); + Inst_rxserie1_RC1_RX1_27 : X_FF + generic map( + INIT => '1' + ) + port map ( + I => rxin1_IBUF, + SET => Inst_rxserie1_RC1_RX1_GSR_OR, + CLK => Inst_rxserie1_CLOCK1_ckout, + O => Inst_rxserie1_RC1_RX1, + CE => VCC, + RST => GND + ); + Inst_rxserie1_RC1_RXCLK_28 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_rxserie1_RC1_RXCNT(3), + RST => Inst_rxserie1_RC1_RXCLK_GSR_OR, + CLK => Inst_rxserie1_CLOCK1_ckout, + O => Inst_rxserie1_RC1_RXCLK, + CE => VCC, + SET => GND + ); + Inst_rxserie1_RC1_RXPARITY_29 : X_FF + generic map( + INIT => '1' + ) + port map ( + I => Inst_rxserie1_RC1_n0019, + SET => Inst_rxserie1_RC1_RXPARITY_GSR_OR, + CLK => Inst_rxserie1_RC1_RXCLK, + O => Inst_rxserie1_RC1_RXPARITY, + CE => VCC, + RST => GND + ); + Inst_rxserie1_RC1_PARITYGEN_30 : X_FF + generic map( + INIT => '1' + ) + port map ( + I => Inst_rxserie1_RC1_n0020, + SET => Inst_rxserie1_RC1_PARITYGEN_GSR_OR, + CLK => Inst_rxserie1_RC1_RXCLK, + O => Inst_rxserie1_RC1_PARITYGEN, + CE => VCC, + RST => GND + ); + Inst_rxserie1_RC1_RXSTOP_31 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_rxserie1_RC1_n0021, + RST => Inst_rxserie1_RC1_RXSTOP_GSR_OR, + CLK => Inst_rxserie1_RC1_RXCLK, + O => Inst_rxserie1_RC1_RXSTOP, + CE => VCC, + SET => GND + ); + Inst_rxserie1_RC1_RSR_7 : X_FF + generic map( + INIT => '1' + ) + port map ( + I => Inst_rxserie1_RC1_n0022, + SET => Inst_rxserie1_RC1_RSR_7_GSR_OR, + CLK => Inst_rxserie1_RC1_RXCLK, + O => Inst_rxserie1_RC1_RSR(7), + CE => VCC, + RST => GND + ); + Inst_rxserie1_RC1_RSR_6 : X_FF + generic map( + INIT => '1' + ) + port map ( + I => Inst_rxserie1_RC1_n0023, + SET => Inst_rxserie1_RC1_RSR_6_GSR_OR, + CLK => Inst_rxserie1_RC1_RXCLK, + O => Inst_rxserie1_RC1_RSR(6), + CE => VCC, + RST => GND + ); + Inst_rxserie1_RC1_RSR_5 : X_FF + generic map( + INIT => '1' + ) + port map ( + I => Inst_rxserie1_RC1_n0024, + SET => Inst_rxserie1_RC1_RSR_5_GSR_OR, + CLK => Inst_rxserie1_RC1_RXCLK, + O => Inst_rxserie1_RC1_RSR(5), + CE => VCC, + RST => GND + ); + Inst_rxserie1_RC1_RSR_4 : X_FF + generic map( + INIT => '1' + ) + port map ( + I => Inst_rxserie1_RC1_n0025, + SET => Inst_rxserie1_RC1_RSR_4_GSR_OR, + CLK => Inst_rxserie1_RC1_RXCLK, + O => Inst_rxserie1_RC1_RSR(4), + CE => VCC, + RST => GND + ); + Inst_rxserie1_RC1_RSR_3 : X_FF + generic map( + INIT => '1' + ) + port map ( + I => Inst_rxserie1_RC1_n0026, + SET => Inst_rxserie1_RC1_RSR_3_GSR_OR, + CLK => Inst_rxserie1_RC1_RXCLK, + O => Inst_rxserie1_RC1_RSR(3), + CE => VCC, + RST => GND + ); + Inst_rxserie1_RC1_RSR_2 : X_FF + generic map( + INIT => '1' + ) + port map ( + I => Inst_rxserie1_RC1_n0027, + SET => Inst_rxserie1_RC1_RSR_2_GSR_OR, + CLK => Inst_rxserie1_RC1_RXCLK, + O => Inst_rxserie1_RC1_RSR(2), + CE => VCC, + RST => GND + ); + Inst_rxserie1_RC1_RSR_1 : X_FF + generic map( + INIT => '1' + ) + port map ( + I => Inst_rxserie1_RC1_n0028, + SET => Inst_rxserie1_RC1_RSR_1_GSR_OR, + CLK => Inst_rxserie1_RC1_RXCLK, + O => Inst_rxserie1_RC1_RSR(1), + CE => VCC, + RST => GND + ); + Inst_rxserie1_RC1_RSR_0 : X_FF + generic map( + INIT => '1' + ) + port map ( + I => Inst_rxserie1_RC1_n0029, + SET => Inst_rxserie1_RC1_RSR_0_GSR_OR, + CLK => Inst_rxserie1_RC1_RXCLK, + O => Inst_rxserie1_RC1_RSR(0), + CE => VCC, + RST => GND + ); + Inst_rxserie1_RC1_RHR_7 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_rxserie1_RC1_RSR(7), + CE => Inst_rxserie1_RC1_N7296, + RST => Inst_rxserie1_RC1_RHR_7_GSR_OR, + CLK => Inst_rxserie1_CLOCK1_ckout, + O => Inst_rxserie1_RC1_RHR(7), + SET => GND + ); + Inst_rxserie1_RC1_RXDATARDY_32 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_rxserie1_RC1_n0031, + CE => Inst_rxserie1_RC1_n0062, + RST => Inst_rxserie1_RC1_RXDATARDY_GSR_OR, + CLK => Inst_rxserie1_CLOCK1_ckout, + O => Inst_rxserie1_RC1_RXDATARDY, + SET => GND + ); + Inst_rxserie1_RC1_OVERRUN_33 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_rxserie1_RC1_n0041, + CE => Inst_rxserie1_RC1_n0063, + RST => Inst_rxserie1_RC1_OVERRUN_GSR_OR, + CLK => Inst_rxserie1_CLOCK1_ckout, + O => Inst_rxserie1_RC1_OVERRUN, + SET => GND + ); + Inst_rxserie1_RC1_PARITY_ERR_34 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_rxserie1_RC1_n0034, + CE => Inst_rxserie1_RC1_n0062, + RST => Inst_rxserie1_RC1_PARITY_ERR_GSR_OR, + CLK => Inst_rxserie1_CLOCK1_ckout, + O => Inst_rxserie1_RC1_PARITY_ERR, + SET => GND + ); + Inst_rxserie1_RC1_FRAMING_ERR_35 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_rxserie1_RC1_n0035, + CE => Inst_rxserie1_RC1_n0062, + RST => Inst_rxserie1_RC1_FRAMING_ERR_GSR_OR, + CLK => Inst_rxserie1_CLOCK1_ckout, + O => Inst_rxserie1_RC1_FRAMING_ERR, + SET => GND + ); + Inst_rxserie1_RC1_RXCNT_3 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_rxserie1_RC1_n0018(3), + CE => Inst_rxserie1_RC1_n0051, + RST => Inst_rxserie1_RC1_RXCNT_3_GSR_OR, + CLK => Inst_rxserie1_CLOCK1_ckout, + O => Inst_rxserie1_RC1_RXCNT(3), + SET => GND + ); + Inst_rxserie1_RC1_RXCNT_2 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_rxserie1_RC1_n0018(2), + CE => Inst_rxserie1_RC1_n0051, + RST => Inst_rxserie1_RC1_RXCNT_2_GSR_OR, + CLK => Inst_rxserie1_CLOCK1_ckout, + O => Inst_rxserie1_RC1_RXCNT(2), + SET => GND + ); + Inst_rxserie1_RC1_RXCNT_0 : X_FF + generic map( + INIT => '1' + ) + port map ( + I => Inst_rxserie1_RC1_n0018(0), + CE => Inst_rxserie1_RC1_n0051, + SET => Inst_rxserie1_RC1_RXCNT_0_GSR_OR, + CLK => Inst_rxserie1_CLOCK1_ckout, + O => Inst_rxserie1_RC1_RXCNT(0), + RST => GND + ); + bus_adr_0_IBUF_36 : X_BUF + port map ( + I => bus_adr(0), + O => bus_adr_0_IBUF + ); + Inst_rxserie1_RC1_Madd_n0040_inst_sum_13 : X_XOR2 + port map ( + I0 => Inst_rxserie1_RC1_RXCNT_3_rt, + I1 => Inst_rxserie1_RC1_Madd_n0040_inst_cy_12, + O => Inst_rxserie1_RC1_n0040(3) + ); + Inst_rxserie1_RC1_Madd_n0040_inst_lut2_101 : X_LUT2 + generic map( + INIT => X"5" + ) + port map ( + ADR0 => Inst_rxserie1_RC1_RXCNT(0), + O => Inst_rxserie1_RC1_Madd_n0040_inst_lut2_10, + ADR1 => GND + ); + Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_sum_8 : X_XOR2 + port map ( + I0 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_8, + I1 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_7, + O => Inst_rxserie1_CLOCK1_compteur_n0005(8) + ); + Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_8_37 : X_MUX2 + port map ( + IB => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_7, + IA => Inst_rxserie1_CLOCK1_compteur(8), + SEL => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_8, + O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_8 + ); + Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_sum_6 : X_XOR2 + port map ( + I0 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_6, + I1 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_5, + O => Inst_rxserie1_CLOCK1_compteur_n0005(6) + ); + Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_7_38 : X_MUX2 + port map ( + IB => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_6, + IA => Inst_rxserie1_CLOCK1_compteur(7), + SEL => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_7, + O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_7 + ); + Inst_rxserie1_CLOCK1_compteur_0_n00011 : X_LUT2 + generic map( + INIT => X"8" + ) + port map ( + ADR0 => rst_IBUF, + ADR1 => Inst_rxserie1_CLOCK1_compteur_n0001(0), + O => Inst_rxserie1_CLOCK1_compteur_0_0_n0001 + ); + Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_sum_7 : X_XOR2 + port map ( + I0 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_7, + I1 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_6, + O => Inst_rxserie1_CLOCK1_compteur_n0005(7) + ); + Inst_rxserie1_CLOCK1_n000539 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => Inst_rxserie1_CLOCK1_compteur(4), + ADR1 => Inst_rxserie1_CLOCK1_compteur(5), + ADR2 => N11021, + ADR3 => CHOICE64, + O => Inst_rxserie1_CLOCK1_n0005 + ); + Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_61 : X_LUT2 + generic map( + INIT => X"5" + ) + port map ( + ADR0 => Inst_rxserie1_CLOCK1_compteur(6), + O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_6, + ADR1 => GND + ); + Inst_rxserie1_CLOCK1_ckout_39 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_rxserie1_CLOCK1_n0005, + RST => Inst_rxserie1_CLOCK1_ckout_GSR_OR, + CLK => Inst_rxserie1_geneck, + O => Inst_rxserie1_CLOCK1_ckout, + CE => VCC, + SET => GND + ); + Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_71 : X_LUT2 + generic map( + INIT => X"5" + ) + port map ( + ADR0 => Inst_rxserie1_CLOCK1_compteur(7), + O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_7, + ADR1 => GND + ); + Inst_rxserie1_CLOCK1_compteur_n00061 : X_LUT2 + generic map( + INIT => X"E" + ) + port map ( + ADR0 => Inst_rxserie1_CLOCK1_n0005, + ADR1 => rst_IBUF, + O => Inst_rxserie1_CLOCK1_compteur_n0006 + ); + Inst_rxserie1_RC1_n0018_0_1 : X_LUT3 + generic map( + INIT => X"75" + ) + port map ( + ADR0 => Inst_rxserie1_RC1_RXCNT(0), + ADR1 => Inst_rxserie1_RC1_HUNT, + ADR2 => Inst_rxserie1_RC1_IDLE, + O => Inst_rxserie1_RC1_n0018(0) + ); + Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_91 : X_LUT2 + generic map( + INIT => X"5" + ) + port map ( + ADR0 => Inst_rxserie1_CLOCK1_compteur(9), + O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_9, + ADR1 => GND + ); + Inst_rxserie1_CLOCK1_compteur_0_n00001 : X_LUT2 + generic map( + INIT => X"4" + ) + port map ( + ADR0 => Inst_rxserie1_CLOCK1_compteur_n0001(0), + ADR1 => rst_IBUF, + O => Inst_rxserie1_CLOCK1_compteur_0_0_n0000 + ); + Inst_rxserie1_CLOCK1_compteur_9 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_rxserie1_CLOCK1_compteur_n0001(9), + RST => Inst_rxserie1_CLOCK1_compteur_9_GSR_OR, + SET => Inst_rxserie1_FIFO1_state_read_FFd2, + CLK => Inst_rxserie1_geneck, + O => Inst_rxserie1_CLOCK1_compteur(9), + CE => VCC + ); + Inst_rxserie1_CLOCK1_compteur_8 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_rxserie1_CLOCK1_compteur_n0001(8), + RST => Inst_rxserie1_CLOCK1_compteur_8_GSR_OR, + SET => Inst_rxserie1_FIFO1_state_read_FFd2, + CLK => Inst_rxserie1_geneck, + O => Inst_rxserie1_CLOCK1_compteur(8), + CE => VCC + ); + Inst_rxserie1_CLOCK1_compteur_0 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_rxserie1_CLOCK1_compteur_n0001(0), + RST => Inst_rxserie1_CLOCK1_compteur_0_GSR_OR, + SET => Inst_rxserie1_CLOCK1_compteur_0_0_n0001, + CLK => Inst_rxserie1_geneck, + O => Inst_rxserie1_CLOCK1_compteur(0), + CE => VCC + ); + Inst_rxserie1_CLOCK1_compteur_1 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_rxserie1_CLOCK1_compteur_n0001(1), + RST => Inst_rxserie1_CLOCK1_compteur_1_GSR_OR, + SET => Inst_rxserie1_CLOCK1_compteur_0_1_n0001, + CLK => Inst_rxserie1_geneck, + O => Inst_rxserie1_CLOCK1_compteur(1), + CE => VCC + ); + Inst_rxserie1_CLOCK1_compteur_2 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_rxserie1_CLOCK1_compteur_n0001(2), + RST => Inst_rxserie1_CLOCK1_compteur_2_GSR_OR, + SET => Inst_rxserie1_CLOCK1_compteur_0_2_n0001, + CLK => Inst_rxserie1_geneck, + O => Inst_rxserie1_CLOCK1_compteur(2), + CE => VCC + ); + Inst_rxserie1_CLOCK1_compteur_3 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_rxserie1_CLOCK1_compteur_n0001(3), + RST => Inst_rxserie1_CLOCK1_compteur_3_GSR_OR, + SET => Inst_rxserie1_CLOCK1_compteur_0_3_n0001, + CLK => Inst_rxserie1_geneck, + O => Inst_rxserie1_CLOCK1_compteur(3), + CE => VCC + ); + Inst_rxserie1_CLOCK1_compteur_4 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_rxserie1_CLOCK1_compteur_n0001(4), + RST => Inst_rxserie1_CLOCK1_compteur_4_GSR_OR, + SET => Inst_rxserie1_FIFO1_state_read_FFd2, + CLK => Inst_rxserie1_geneck, + O => Inst_rxserie1_CLOCK1_compteur(4), + CE => VCC + ); + Inst_rxserie1_CLOCK1_compteur_5 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_rxserie1_CLOCK1_compteur_n0001(5), + RST => Inst_rxserie1_CLOCK1_compteur_5_GSR_OR, + SET => Inst_rxserie1_FIFO1_state_read_FFd2, + CLK => Inst_rxserie1_geneck, + O => Inst_rxserie1_CLOCK1_compteur(5), + CE => VCC + ); + Inst_rxserie1_CLOCK1_compteur_6 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_rxserie1_CLOCK1_compteur_n0001(6), + RST => Inst_rxserie1_CLOCK1_compteur_6_GSR_OR, + SET => Inst_rxserie1_FIFO1_state_read_FFd2, + CLK => Inst_rxserie1_geneck, + O => Inst_rxserie1_CLOCK1_compteur(6), + CE => VCC + ); + Inst_rxserie1_CLOCK1_compteur_7 : X_FF + generic map( + INIT => '0' + ) + port map ( + I => Inst_rxserie1_CLOCK1_compteur_n0001(7), + RST => Inst_rxserie1_CLOCK1_compteur_7_GSR_OR, + SET => Inst_rxserie1_FIFO1_state_read_FFd2, + CLK => Inst_rxserie1_geneck, + O => Inst_rxserie1_CLOCK1_compteur(7), + CE => VCC + ); + bus_adr_9_IBUF_40 : X_BUF + port map ( + I => bus_adr(9), + O => bus_adr_9_IBUF + ); + bus_adr_15_IBUF_41 : X_BUF + port map ( + I => bus_adr(15), + O => bus_adr_15_IBUF + ); + bus_adr_10_IBUF_42 : X_BUF + port map ( + I => bus_adr(10), + O => bus_adr_10_IBUF + ); + clk_ref_IBUF_43 : X_BUF + port map ( + I => clk_ref, + O => clk_ref_IBUF + ); + bus_adr_11_IBUF_44 : X_BUF + port map ( + I => bus_adr(11), + O => bus_adr_11_IBUF + ); + IOW_IBUF_45 : X_BUF + port map ( + I => IOW, + O => IOW_IBUF + ); + bus_adr_12_IBUF_46 : X_BUF + port map ( + I => bus_adr(12), + O => bus_adr_12_IBUF + ); + IOR_IBUF_47 : X_BUF + port map ( + I => IOR, + O => IOR_IBUF + ); + bus_adr_13_IBUF_48 : X_BUF + port map ( + I => bus_adr(13), + O => bus_adr_13_IBUF + ); + AEN_IBUF_49 : X_BUF + port map ( + I => AEN, + O => AEN_IBUF + ); + bus_adr_14_IBUF_50 : X_BUF + port map ( + I => bus_adr(14), + O => bus_adr_14_IBUF + ); + rxin1_IBUF_51 : X_BUF + port map ( + I => rxin1, + O => rxin1_IBUF + ); + Inst_rxserie1_CLOCK1_compteur_3_n00011 : X_LUT2 + generic map( + INIT => X"8" + ) + port map ( + ADR0 => rst_IBUF, + ADR1 => Inst_rxserie1_CLOCK1_compteur_n0001(3), + O => Inst_rxserie1_CLOCK1_compteur_0_3_n0001 + ); + Inst_rxserie1_CLOCK1_compteur_3_n00001 : X_LUT2 + generic map( + INIT => X"4" + ) + port map ( + ADR0 => Inst_rxserie1_CLOCK1_compteur_n0001(3), + ADR1 => rst_IBUF, + O => Inst_rxserie1_CLOCK1_compteur_0_3_n0000 + ); + rst_IBUF_52 : X_BUF + port map ( + I => rst, + O => rst_IBUF + ); + Inst_rxserie1_CLOCK1_compteur_2_n00011 : X_LUT2 + generic map( + INIT => X"4" + ) + port map ( + ADR0 => Inst_rxserie1_RCONF_REG(1), + ADR1 => rst_IBUF, + O => Inst_rxserie1_CLOCK1_compteur_0_2_n0001 + ); + Inst_rxserie1_CLOCK1_compteur_1_n00011 : X_LUT2 + generic map( + INIT => X"8" + ) + port map ( + ADR0 => rst_IBUF, + ADR1 => Inst_rxserie1_CLOCK1_compteur_n0001(1), + O => Inst_rxserie1_CLOCK1_compteur_0_1_n0001 + ); + Inst_rxserie1_CLOCK1_compteur_1_n00001 : X_LUT2 + generic map( + INIT => X"4" + ) + port map ( + ADR0 => Inst_rxserie1_CLOCK1_compteur_n0001(1), + ADR1 => rst_IBUF, + O => Inst_rxserie1_CLOCK1_compteur_0_1_n0000 + ); + Inst_rxserie1_CLOCK1_compteur_Mmux_n0001_Result_0_1 : X_LUT4 + generic map( + INIT => X"E444" + ) + port map ( + ADR0 => Inst_rxserie1_CLOCK1_compteur_n0006, + ADR1 => Inst_rxserie1_CLOCK1_compteur_n0005(0), + ADR2 => Inst_rxserie1_RCONF_REG(1), + ADR3 => Inst_rxserie1_RCONF_REG(0), + O => Inst_rxserie1_CLOCK1_compteur_n0001(0) + ); + Inst_rxserie1_CLOCK1_compteur_Mmux_n0001_Result_1_1 : X_LUT4 + generic map( + INIT => X"4EE4" + ) + port map ( + ADR0 => Inst_rxserie1_CLOCK1_compteur_n0006, + ADR1 => Inst_rxserie1_CLOCK1_compteur_n0005(1), + ADR2 => Inst_rxserie1_RCONF_REG(0), + ADR3 => Inst_rxserie1_RCONF_REG(1), + O => Inst_rxserie1_CLOCK1_compteur_n0001(1) + ); + Inst_rxserie1_CLOCK1_compteur_Mmux_n0001_Result_4_1 : X_LUT3 + generic map( + INIT => X"04" + ) + port map ( + ADR0 => Inst_rxserie1_CLOCK1_n0005, + ADR1 => Inst_rxserie1_CLOCK1_compteur_n0005(4), + ADR2 => rst_IBUF, + O => Inst_rxserie1_CLOCK1_compteur_n0001(4) + ); + Inst_rxserie1_CLOCK1_compteur_Mmux_n0001_Result_3_1 : X_LUT4 + generic map( + INIT => X"444E" + ) + port map ( + ADR0 => Inst_rxserie1_CLOCK1_compteur_n0006, + ADR1 => Inst_rxserie1_CLOCK1_compteur_n0005(3), + ADR2 => Inst_rxserie1_RCONF_REG(1), + ADR3 => Inst_rxserie1_RCONF_REG(0), + O => Inst_rxserie1_CLOCK1_compteur_n0001(3) + ); + Inst_rxserie1_CLOCK1_compteur_Mmux_n0001_Result_5_1 : X_LUT3 + generic map( + INIT => X"04" + ) + port map ( + ADR0 => Inst_rxserie1_CLOCK1_n0005, + ADR1 => Inst_rxserie1_CLOCK1_compteur_n0005(5), + ADR2 => rst_IBUF, + O => Inst_rxserie1_CLOCK1_compteur_n0001(5) + ); + Inst_rxserie1_CLOCK1_compteur_Mmux_n0001_Result_6_1 : X_LUT3 + generic map( + INIT => X"04" + ) + port map ( + ADR0 => Inst_rxserie1_CLOCK1_n0005, + ADR1 => Inst_rxserie1_CLOCK1_compteur_n0005(6), + ADR2 => rst_IBUF, + O => Inst_rxserie1_CLOCK1_compteur_n0001(6) + ); + Inst_rxserie1_CLOCK1_compteur_Mmux_n0001_Result_7_1 : X_LUT3 + generic map( + INIT => X"04" + ) + port map ( + ADR0 => Inst_rxserie1_CLOCK1_n0005, + ADR1 => Inst_rxserie1_CLOCK1_compteur_n0005(7), + ADR2 => rst_IBUF, + O => Inst_rxserie1_CLOCK1_compteur_n0001(7) + ); + Inst_rxserie1_CLOCK1_compteur_Mmux_n0001_Result_8_1 : X_LUT3 + generic map( + INIT => X"04" + ) + port map ( + ADR0 => Inst_rxserie1_CLOCK1_n0005, + ADR1 => Inst_rxserie1_CLOCK1_compteur_n0005(8), + ADR2 => rst_IBUF, + O => Inst_rxserie1_CLOCK1_compteur_n0001(8) + ); + Inst_rxserie1_CLOCK1_compteur_Mmux_n0001_Result_9_1 : X_LUT3 + generic map( + INIT => X"04" + ) + port map ( + ADR0 => Inst_rxserie1_CLOCK1_n0005, + ADR1 => Inst_rxserie1_CLOCK1_compteur_n0005(9), + ADR2 => rst_IBUF, + O => Inst_rxserie1_CLOCK1_compteur_n0001(9) + ); + Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_81 : X_LUT2 + generic map( + INIT => X"5" + ) + port map ( + ADR0 => Inst_rxserie1_CLOCK1_compteur(8), + O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_8, + ADR1 => GND + ); + Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_6_53 : X_MUX2 + port map ( + IB => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_5, + IA => Inst_rxserie1_CLOCK1_compteur(6), + SEL => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_6, + O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_6 + ); + Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_sum_9 : X_XOR2 + port map ( + I0 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_9, + I1 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_8, + O => Inst_rxserie1_CLOCK1_compteur_n0005(9) + ); + Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_0_54 : X_MUX2 + port map ( + IB => Inst_rxserie1_I7_N1369, + IA => Inst_rxserie1_FIFO1_state_read_FFd2, + SEL => Inst_rxserie1_CLOCK1_compteur_0_rt, + O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_0 + ); + Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_sum_0 : X_XOR2 + port map ( + I0 => Inst_rxserie1_CLOCK1_compteur_0_rt, + I1 => Inst_rxserie1_I7_N1369, + O => Inst_rxserie1_CLOCK1_compteur_n0005(0) + ); + Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_11 : X_LUT2 + generic map( + INIT => X"5" + ) + port map ( + ADR0 => Inst_rxserie1_CLOCK1_compteur(1), + O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_1, + ADR1 => GND + ); + Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_1_55 : X_MUX2 + port map ( + IB => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_0, + IA => Inst_rxserie1_CLOCK1_compteur(1), + SEL => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_1, + O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_1 + ); + Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_sum_1 : X_XOR2 + port map ( + I0 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_1, + I1 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_0, + O => Inst_rxserie1_CLOCK1_compteur_n0005(1) + ); + Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_21 : X_LUT2 + generic map( + INIT => X"5" + ) + port map ( + ADR0 => Inst_rxserie1_CLOCK1_compteur(2), + O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_2, + ADR1 => GND + ); + Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_2_56 : X_MUX2 + port map ( + IB => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_1, + IA => Inst_rxserie1_CLOCK1_compteur(2), + SEL => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_2, + O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_2 + ); + Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_sum_2 : X_XOR2 + port map ( + I0 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_2, + I1 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_1, + O => Inst_rxserie1_CLOCK1_compteur_n0005(2) + ); + Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_31 : X_LUT2 + generic map( + INIT => X"5" + ) + port map ( + ADR0 => Inst_rxserie1_CLOCK1_compteur(3), + O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_3, + ADR1 => GND + ); + Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_3_57 : X_MUX2 + port map ( + IB => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_2, + IA => Inst_rxserie1_CLOCK1_compteur(3), + SEL => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_3, + O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_3 + ); + Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_sum_3 : X_XOR2 + port map ( + I0 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_3, + I1 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_2, + O => Inst_rxserie1_CLOCK1_compteur_n0005(3) + ); + Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_41 : X_LUT2 + generic map( + INIT => X"5" + ) + port map ( + ADR0 => Inst_rxserie1_CLOCK1_compteur(4), + O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_4, + ADR1 => GND + ); + Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_4_58 : X_MUX2 + port map ( + IB => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_3, + IA => Inst_rxserie1_CLOCK1_compteur(4), + SEL => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_4, + O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_4 + ); + Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_sum_4 : X_XOR2 + port map ( + I0 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_4, + I1 => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_3, + O => Inst_rxserie1_CLOCK1_compteur_n0005(4) + ); + Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_51 : X_LUT2 + generic map( + INIT => X"5" + ) + port map ( + ADR0 => Inst_rxserie1_CLOCK1_compteur(5), + O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_5, + ADR1 => GND + ); + Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_5_59 : X_MUX2 + port map ( + IB => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_4, + IA => Inst_rxserie1_CLOCK1_compteur(5), + SEL => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_lut2_5, + O => Inst_rxserie1_CLOCK1_compteur_Msub_n0000_inst_cy_5 + ); + Inst_rxserie1_CLOCK1_n000529 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => Inst_rxserie1_CLOCK1_compteur(0), + ADR1 => Inst_rxserie1_CLOCK1_compteur(1), + ADR2 => Inst_rxserie1_CLOCK1_compteur(2), + ADR3 => Inst_rxserie1_CLOCK1_compteur(3), + O => CHOICE64 + ); + Inst_rxserie1_RC1_RXCNT_3_rt_60 : X_LUT2 + generic map( + INIT => X"A" + ) + port map ( + ADR0 => Inst_rxserie1_RC1_RXCNT(3), + O => Inst_rxserie1_RC1_RXCNT_3_rt, + ADR1 => GND + ); + Inst_rxserie1_CLOCK1_compteur_0_rt_61 : X_LUT2 + generic map( + INIT => X"A" + ) + port map ( + ADR0 => Inst_rxserie1_CLOCK1_compteur(0), + O => Inst_rxserie1_CLOCK1_compteur_0_rt, + ADR1 => GND + ); + Inst_decodisa_reg_select24 : X_LUT3 + generic map( + INIT => X"04" + ) + port map ( + ADR0 => bus_adr_15_IBUF, + ADR1 => bus_adr_8_IBUF, + ADR2 => AEN_IBUF, + O => CHOICE45 + ); + Inst_decodisa_reg_select32 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => bus_adr_9_IBUF, + ADR1 => bus_adr_10_IBUF, + ADR2 => bus_adr_11_IBUF, + ADR3 => N11025, + O => Inst_decodisa_reg_select + ); + Inst_decodisa_reg_select32_SW0 : X_LUT4 + generic map( + INIT => X"FFEF" + ) + port map ( + ADR0 => bus_adr_12_IBUF, + ADR1 => bus_adr_13_IBUF, + ADR2 => CHOICE45, + ADR3 => bus_adr_14_IBUF, + O => N11025 + ); + bus_data_5_IOBUF_PULLUP : X_PU + port map ( + O => bus_data_5_IOBUF + ); + bus_data_0_IOBUF_PULLUP : X_PU + port map ( + O => bus_data_0_IOBUF + ); + bus_data_7_IOBUF_PULLUP : X_PU + port map ( + O => bus_data_7_IOBUF + ); + bus_data_1_IOBUF_PULLUP : X_PU + port map ( + O => bus_data_1_IOBUF + ); + bus_data_6_IOBUF_PULLUP : X_PU + port map ( + O => bus_data_6_IOBUF + ); + bus_data_2_IOBUF_PULLUP : X_PU + port map ( + O => bus_data_2_IOBUF + ); + bus_data_4_IOBUF_PULLUP : X_PU + port map ( + O => bus_data_4_IOBUF + ); + bus_data_3_IOBUF_PULLUP : X_PU + port map ( + O => bus_data_3_IOBUF + ); + Inst_rxserie1_FIFO1_fifo0_BU232 : X_SFF + generic map( + INIT => '0' + ) + port map ( + CE => Inst_rxserie1_FIFO1_fifo0_N37, + CLK => clk_speed_BUFGP, + I => Inst_rxserie1_FIFO1_fifo0_N47, + O => Inst_rxserie1_inter_fifo(7), + SRST => rst_IBUF, + SET => GND, + RST => GSR, + SSET => GND + ); + Inst_rxserie1_FIFO1_fifo0_BU230 : X_SFF + generic map( + INIT => '0' + ) + port map ( + CE => Inst_rxserie1_FIFO1_fifo0_N37, + CLK => clk_speed_BUFGP, + I => Inst_rxserie1_FIFO1_fifo0_N48, + O => Inst_rxserie1_inter_fifo(6), + SRST => rst_IBUF, + SET => GND, + RST => GSR, + SSET => GND + ); + Inst_rxserie1_FIFO1_fifo0_BU228 : X_SFF + generic map( + INIT => '0' + ) + port map ( + CE => Inst_rxserie1_FIFO1_fifo0_N37, + CLK => clk_speed_BUFGP, + I => Inst_rxserie1_FIFO1_fifo0_N49, + O => Inst_rxserie1_inter_fifo(5), + SRST => rst_IBUF, + SET => GND, + RST => GSR, + SSET => GND + ); + Inst_rxserie1_FIFO1_fifo0_BU226 : X_SFF + generic map( + INIT => '0' + ) + port map ( + CE => Inst_rxserie1_FIFO1_fifo0_N37, + CLK => clk_speed_BUFGP, + I => Inst_rxserie1_FIFO1_fifo0_N50, + O => Inst_rxserie1_inter_fifo(4), + SRST => rst_IBUF, + SET => GND, + RST => GSR, + SSET => GND + ); + Inst_rxserie1_FIFO1_fifo0_BU224 : X_SFF + generic map( + INIT => '0' + ) + port map ( + CE => Inst_rxserie1_FIFO1_fifo0_N37, + CLK => clk_speed_BUFGP, + I => Inst_rxserie1_FIFO1_fifo0_N51, + O => Inst_rxserie1_inter_fifo(3), + SRST => rst_IBUF, + SET => GND, + RST => GSR, + SSET => GND + ); + Inst_rxserie1_FIFO1_fifo0_BU222 : X_SFF + generic map( + INIT => '0' + ) + port map ( + CE => Inst_rxserie1_FIFO1_fifo0_N37, + CLK => clk_speed_BUFGP, + I => Inst_rxserie1_FIFO1_fifo0_N52, + O => Inst_rxserie1_inter_fifo(2), + SRST => rst_IBUF, + SET => GND, + RST => GSR, + SSET => GND + ); + Inst_rxserie1_FIFO1_fifo0_BU220 : X_SFF + generic map( + INIT => '0' + ) + port map ( + CE => Inst_rxserie1_FIFO1_fifo0_N37, + CLK => clk_speed_BUFGP, + I => Inst_rxserie1_FIFO1_fifo0_N53, + O => Inst_rxserie1_inter_fifo(1), + SRST => rst_IBUF, + SET => GND, + RST => GSR, + SSET => GND + ); + Inst_rxserie1_FIFO1_fifo0_BU218 : X_SFF + generic map( + INIT => '0' + ) + port map ( + CE => Inst_rxserie1_FIFO1_fifo0_N37, + CLK => clk_speed_BUFGP, + I => Inst_rxserie1_FIFO1_fifo0_N54, + O => Inst_rxserie1_inter_fifo(0), + SRST => rst_IBUF, + SET => GND, + RST => GSR, + SSET => GND + ); + Inst_rxserie1_FIFO1_fifo0_BU214 : X_SRL16E + generic map( + INIT => X"0000" + ) + port map ( + CE => Inst_rxserie1_FIFO1_fifo0_N38, + D => Inst_rxserie1_RC1_RHR(7), + Q => Inst_rxserie1_FIFO1_fifo0_N47, + CLK => clk_speed_BUFGP, + A0 => Inst_rxserie1_FIFO1_fifo0_N7, + A1 => Inst_rxserie1_FIFO1_fifo0_N6, + A2 => Inst_rxserie1_FIFO1_fifo0_N5, + A3 => Inst_rxserie1_FIFO1_fifo0_N4 + ); + Inst_rxserie1_FIFO1_fifo0_BU213 : X_SRL16E + generic map( + INIT => X"0000" + ) + port map ( + CE => Inst_rxserie1_FIFO1_fifo0_N38, + D => Inst_rxserie1_RC1_RHR(6), + Q => Inst_rxserie1_FIFO1_fifo0_N48, + CLK => clk_speed_BUFGP, + A0 => Inst_rxserie1_FIFO1_fifo0_N7, + A1 => Inst_rxserie1_FIFO1_fifo0_N6, + A2 => Inst_rxserie1_FIFO1_fifo0_N5, + A3 => Inst_rxserie1_FIFO1_fifo0_N4 + ); + Inst_rxserie1_FIFO1_fifo0_BU212 : X_SRL16E + generic map( + INIT => X"0000" + ) + port map ( + CE => Inst_rxserie1_FIFO1_fifo0_N38, + D => Inst_rxserie1_RC1_RHR(5), + Q => Inst_rxserie1_FIFO1_fifo0_N49, + CLK => clk_speed_BUFGP, + A0 => Inst_rxserie1_FIFO1_fifo0_N7, + A1 => Inst_rxserie1_FIFO1_fifo0_N6, + A2 => Inst_rxserie1_FIFO1_fifo0_N5, + A3 => Inst_rxserie1_FIFO1_fifo0_N4 + ); + Inst_rxserie1_FIFO1_fifo0_BU211 : X_SRL16E + generic map( + INIT => X"0000" + ) + port map ( + CE => Inst_rxserie1_FIFO1_fifo0_N38, + D => Inst_rxserie1_RC1_RHR(4), + Q => Inst_rxserie1_FIFO1_fifo0_N50, + CLK => clk_speed_BUFGP, + A0 => Inst_rxserie1_FIFO1_fifo0_N7, + A1 => Inst_rxserie1_FIFO1_fifo0_N6, + A2 => Inst_rxserie1_FIFO1_fifo0_N5, + A3 => Inst_rxserie1_FIFO1_fifo0_N4 + ); + Inst_rxserie1_FIFO1_fifo0_BU210 : X_SRL16E + generic map( + INIT => X"0000" + ) + port map ( + CE => Inst_rxserie1_FIFO1_fifo0_N38, + D => Inst_rxserie1_RC1_RHR(3), + Q => Inst_rxserie1_FIFO1_fifo0_N51, + CLK => clk_speed_BUFGP, + A0 => Inst_rxserie1_FIFO1_fifo0_N7, + A1 => Inst_rxserie1_FIFO1_fifo0_N6, + A2 => Inst_rxserie1_FIFO1_fifo0_N5, + A3 => Inst_rxserie1_FIFO1_fifo0_N4 + ); + Inst_rxserie1_FIFO1_fifo0_BU209 : X_SRL16E + generic map( + INIT => X"0000" + ) + port map ( + CE => Inst_rxserie1_FIFO1_fifo0_N38, + D => Inst_rxserie1_RC1_RHR(2), + Q => Inst_rxserie1_FIFO1_fifo0_N52, + CLK => clk_speed_BUFGP, + A0 => Inst_rxserie1_FIFO1_fifo0_N7, + A1 => Inst_rxserie1_FIFO1_fifo0_N6, + A2 => Inst_rxserie1_FIFO1_fifo0_N5, + A3 => Inst_rxserie1_FIFO1_fifo0_N4 + ); + Inst_rxserie1_FIFO1_fifo0_BU208 : X_SRL16E + generic map( + INIT => X"0000" + ) + port map ( + CE => Inst_rxserie1_FIFO1_fifo0_N38, + D => Inst_rxserie1_RC1_RHR(1), + Q => Inst_rxserie1_FIFO1_fifo0_N53, + CLK => clk_speed_BUFGP, + A0 => Inst_rxserie1_FIFO1_fifo0_N7, + A1 => Inst_rxserie1_FIFO1_fifo0_N6, + A2 => Inst_rxserie1_FIFO1_fifo0_N5, + A3 => Inst_rxserie1_FIFO1_fifo0_N4 + ); + Inst_rxserie1_FIFO1_fifo0_BU207 : X_SRL16E + generic map( + INIT => X"0000" + ) + port map ( + CE => Inst_rxserie1_FIFO1_fifo0_N38, + D => Inst_rxserie1_RC1_RHR(0), + Q => Inst_rxserie1_FIFO1_fifo0_N54, + CLK => clk_speed_BUFGP, + A0 => Inst_rxserie1_FIFO1_fifo0_N7, + A1 => Inst_rxserie1_FIFO1_fifo0_N6, + A2 => Inst_rxserie1_FIFO1_fifo0_N5, + A3 => Inst_rxserie1_FIFO1_fifo0_N4 + ); + Inst_rxserie1_FIFO1_fifo0_BU204 : X_SFF + generic map( + INIT => '1' + ) + port map ( + CE => Inst_rxserie1_FIFO1_fifo0_N1, + CLK => clk_speed_BUFGP, + I => Inst_rxserie1_FIFO1_fifo0_N1271, + O => Inst_rxserie1_flagreg(3), + SSET => rst_IBUF, + SET => GSR, + RST => GND, + SRST => GND + ); + Inst_rxserie1_FIFO1_fifo0_BU203 : X_LUT4 + generic map( + INIT => X"eeee" + ) + port map ( + ADR0 => Inst_rxserie1_FIFO1_fifo0_N1143, + ADR1 => Inst_rxserie1_FIFO1_fifo0_N1142, + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N1271 + ); + Inst_rxserie1_FIFO1_fifo0_BU196 : X_LUT4 + generic map( + INIT => X"2222" + ) + port map ( + ADR0 => Inst_rxserie1_FIFO1_fifo0_N73, + ADR1 => Inst_rxserie1_FIFO1_wr_en, + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N1143 + ); + Inst_rxserie1_FIFO1_fifo0_BU190 : X_LUT4 + generic map( + INIT => X"4040" + ) + port map ( + ADR0 => Inst_rxserie1_FIFO1_wr_en, + ADR1 => Inst_rxserie1_FIFO1_state_read_FFd2, + ADR2 => Inst_rxserie1_FIFO1_fifo0_N74, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N1142 + ); + Inst_rxserie1_FIFO1_fifo0_BU183 : X_MUX2 + port map ( + IB => Inst_rxserie1_FIFO1_fifo0_N1110, + IA => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N74, + SEL => Inst_rxserie1_FIFO1_fifo0_N1113 + ); + Inst_rxserie1_FIFO1_fifo0_BU182 : X_LUT4 + generic map( + INIT => X"9999" + ) + port map ( + ADR0 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR1 => Inst_rxserie1_flagreg(2), + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N1113 + ); + Inst_rxserie1_FIFO1_fifo0_BU180 : X_MUX2 + port map ( + IB => Inst_rxserie1_FIFO1_fifo0_N1104, + IA => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N1110, + SEL => Inst_rxserie1_FIFO1_fifo0_N1107 + ); + Inst_rxserie1_FIFO1_fifo0_BU179 : X_LUT4 + generic map( + INIT => X"9009" + ) + port map ( + ADR0 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR1 => Inst_rxserie1_FIFO1_fifo0_N18, + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N17, + O => Inst_rxserie1_FIFO1_fifo0_N1107 + ); + Inst_rxserie1_FIFO1_fifo0_BU177 : X_MUX2 + port map ( + IB => Inst_rxserie1_FIFO1_fifo0_N1, + IA => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N1104, + SEL => Inst_rxserie1_FIFO1_fifo0_N1101 + ); + Inst_rxserie1_FIFO1_fifo0_BU176 : X_LUT4 + generic map( + INIT => X"9009" + ) + port map ( + ADR0 => Inst_rxserie1_FIFO1_fifo0_N1, + ADR1 => Inst_rxserie1_FIFO1_fifo0_N20, + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N19, + O => Inst_rxserie1_FIFO1_fifo0_N1101 + ); + Inst_rxserie1_FIFO1_fifo0_BU172 : X_MUX2 + port map ( + IB => Inst_rxserie1_FIFO1_fifo0_N1037, + IA => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N73, + SEL => Inst_rxserie1_FIFO1_fifo0_N1040 + ); + Inst_rxserie1_FIFO1_fifo0_BU171 : X_LUT4 + generic map( + INIT => X"9999" + ) + port map ( + ADR0 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR1 => Inst_rxserie1_flagreg(2), + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N1040 + ); + Inst_rxserie1_FIFO1_fifo0_BU169 : X_MUX2 + port map ( + IB => Inst_rxserie1_FIFO1_fifo0_N1031, + IA => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N1037, + SEL => Inst_rxserie1_FIFO1_fifo0_N1034 + ); + Inst_rxserie1_FIFO1_fifo0_BU168 : X_LUT4 + generic map( + INIT => X"9009" + ) + port map ( + ADR0 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR1 => Inst_rxserie1_FIFO1_fifo0_N18, + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N17, + O => Inst_rxserie1_FIFO1_fifo0_N1034 + ); + Inst_rxserie1_FIFO1_fifo0_BU166 : X_MUX2 + port map ( + IB => Inst_rxserie1_FIFO1_fifo0_N1, + IA => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N1031, + SEL => Inst_rxserie1_FIFO1_fifo0_N1028 + ); + Inst_rxserie1_FIFO1_fifo0_BU165 : X_LUT4 + generic map( + INIT => X"9009" + ) + port map ( + ADR0 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR1 => Inst_rxserie1_FIFO1_fifo0_N20, + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N19, + O => Inst_rxserie1_FIFO1_fifo0_N1028 + ); + Inst_rxserie1_FIFO1_fifo0_BU161 : X_LUT4 + generic map( + INIT => X"eeee" + ) + port map ( + ADR0 => Inst_rxserie1_flagreg(2), + ADR1 => Inst_rxserie1_flagreg(2), + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => NLW_Inst_rxserie1_FIFO1_fifo0_BU161_O_UNCONNECTED + ); + Inst_rxserie1_FIFO1_fifo0_BU155 : X_LUT4 + generic map( + INIT => X"eeee" + ) + port map ( + ADR0 => Inst_rxserie1_flagreg(2), + ADR1 => Inst_rxserie1_FIFO1_fifo0_N17, + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_flagreg(1) + ); + Inst_rxserie1_FIFO1_fifo0_BU149 : X_LUT4 + generic map( + INIT => X"eeee" + ) + port map ( + ADR0 => Inst_rxserie1_flagreg(2), + ADR1 => Inst_rxserie1_FIFO1_fifo0_N18, + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_flagreg(0) + ); + Inst_rxserie1_FIFO1_fifo0_BU143 : X_LUT4 + generic map( + INIT => X"eeee" + ) + port map ( + ADR0 => Inst_rxserie1_flagreg(2), + ADR1 => Inst_rxserie1_FIFO1_fifo0_N19, + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => NLW_Inst_rxserie1_FIFO1_fifo0_BU143_O_UNCONNECTED + ); + Inst_rxserie1_FIFO1_fifo0_BU137 : X_LUT4 + generic map( + INIT => X"eeee" + ) + port map ( + ADR0 => Inst_rxserie1_flagreg(2), + ADR1 => Inst_rxserie1_FIFO1_fifo0_N20, + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => NLW_Inst_rxserie1_FIFO1_fifo0_BU137_O_UNCONNECTED + ); + Inst_rxserie1_FIFO1_fifo0_BU131 : X_SFF + generic map( + INIT => '0' + ) + port map ( + CE => Inst_rxserie1_FIFO1_fifo0_N33, + CLK => clk_speed_BUFGP, + I => Inst_rxserie1_FIFO1_fifo0_N716, + O => Inst_rxserie1_flagreg(2), + SRST => rst_IBUF, + SET => GND, + RST => GSR, + SSET => GND + ); + Inst_rxserie1_FIFO1_fifo0_BU129 : X_XOR2 + port map ( + I0 => Inst_rxserie1_FIFO1_fifo0_N735, + I1 => Inst_rxserie1_FIFO1_fifo0_N738, + O => Inst_rxserie1_FIFO1_fifo0_N716 + ); + Inst_rxserie1_FIFO1_fifo0_BU128 : X_LUT4 + generic map( + INIT => X"9999" + ) + port map ( + ADR0 => Inst_rxserie1_flagreg(2), + ADR1 => Inst_rxserie1_FIFO1_fifo0_N3, + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N738 + ); + Inst_rxserie1_FIFO1_fifo0_BU126 : X_SFF + generic map( + INIT => '0' + ) + port map ( + CE => Inst_rxserie1_FIFO1_fifo0_N33, + CLK => clk_speed_BUFGP, + I => Inst_rxserie1_FIFO1_fifo0_N715, + O => Inst_rxserie1_FIFO1_fifo0_N17, + SRST => rst_IBUF, + SET => GND, + RST => GSR, + SSET => GND + ); + Inst_rxserie1_FIFO1_fifo0_BU124 : X_XOR2 + port map ( + I0 => Inst_rxserie1_FIFO1_fifo0_N730, + I1 => Inst_rxserie1_FIFO1_fifo0_N733, + O => Inst_rxserie1_FIFO1_fifo0_N715 + ); + Inst_rxserie1_FIFO1_fifo0_BU123 : X_MUX2 + port map ( + IB => Inst_rxserie1_FIFO1_fifo0_N730, + IA => Inst_rxserie1_FIFO1_fifo0_N17, + O => Inst_rxserie1_FIFO1_fifo0_N735, + SEL => Inst_rxserie1_FIFO1_fifo0_N733 + ); + Inst_rxserie1_FIFO1_fifo0_BU122 : X_LUT4 + generic map( + INIT => X"9999" + ) + port map ( + ADR0 => Inst_rxserie1_FIFO1_fifo0_N17, + ADR1 => Inst_rxserie1_FIFO1_fifo0_N3, + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N733 + ); + Inst_rxserie1_FIFO1_fifo0_BU120 : X_SFF + generic map( + INIT => '0' + ) + port map ( + CE => Inst_rxserie1_FIFO1_fifo0_N33, + CLK => clk_speed_BUFGP, + I => Inst_rxserie1_FIFO1_fifo0_N714, + O => Inst_rxserie1_FIFO1_fifo0_N18, + SRST => rst_IBUF, + SET => GND, + RST => GSR, + SSET => GND + ); + Inst_rxserie1_FIFO1_fifo0_BU118 : X_XOR2 + port map ( + I0 => Inst_rxserie1_FIFO1_fifo0_N725, + I1 => Inst_rxserie1_FIFO1_fifo0_N728, + O => Inst_rxserie1_FIFO1_fifo0_N714 + ); + Inst_rxserie1_FIFO1_fifo0_BU117 : X_MUX2 + port map ( + IB => Inst_rxserie1_FIFO1_fifo0_N725, + IA => Inst_rxserie1_FIFO1_fifo0_N18, + O => Inst_rxserie1_FIFO1_fifo0_N730, + SEL => Inst_rxserie1_FIFO1_fifo0_N728 + ); + Inst_rxserie1_FIFO1_fifo0_BU116 : X_LUT4 + generic map( + INIT => X"9999" + ) + port map ( + ADR0 => Inst_rxserie1_FIFO1_fifo0_N18, + ADR1 => Inst_rxserie1_FIFO1_fifo0_N3, + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N728 + ); + Inst_rxserie1_FIFO1_fifo0_BU114 : X_SFF + generic map( + INIT => '0' + ) + port map ( + CE => Inst_rxserie1_FIFO1_fifo0_N33, + CLK => clk_speed_BUFGP, + I => Inst_rxserie1_FIFO1_fifo0_N713, + O => Inst_rxserie1_FIFO1_fifo0_N19, + SRST => rst_IBUF, + SET => GND, + RST => GSR, + SSET => GND + ); + Inst_rxserie1_FIFO1_fifo0_BU112 : X_XOR2 + port map ( + I0 => Inst_rxserie1_FIFO1_fifo0_N720, + I1 => Inst_rxserie1_FIFO1_fifo0_N723, + O => Inst_rxserie1_FIFO1_fifo0_N713 + ); + Inst_rxserie1_FIFO1_fifo0_BU111 : X_MUX2 + port map ( + IB => Inst_rxserie1_FIFO1_fifo0_N720, + IA => Inst_rxserie1_FIFO1_fifo0_N19, + O => Inst_rxserie1_FIFO1_fifo0_N725, + SEL => Inst_rxserie1_FIFO1_fifo0_N723 + ); + Inst_rxserie1_FIFO1_fifo0_BU110 : X_LUT4 + generic map( + INIT => X"9999" + ) + port map ( + ADR0 => Inst_rxserie1_FIFO1_fifo0_N19, + ADR1 => Inst_rxserie1_FIFO1_fifo0_N3, + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N723 + ); + Inst_rxserie1_FIFO1_fifo0_BU108 : X_SFF + generic map( + INIT => '0' + ) + port map ( + CE => Inst_rxserie1_FIFO1_fifo0_N33, + CLK => clk_speed_BUFGP, + I => Inst_rxserie1_FIFO1_fifo0_N712, + O => Inst_rxserie1_FIFO1_fifo0_N20, + SRST => rst_IBUF, + SET => GND, + RST => GSR, + SSET => GND + ); + Inst_rxserie1_FIFO1_fifo0_BU106 : X_XOR2 + port map ( + I0 => Inst_rxserie1_FIFO1_fifo0_N718, + I1 => Inst_rxserie1_FIFO1_fifo0_N717, + O => Inst_rxserie1_FIFO1_fifo0_N712 + ); + Inst_rxserie1_FIFO1_fifo0_BU105 : X_MUX2 + port map ( + IB => Inst_rxserie1_FIFO1_fifo0_N718, + IA => Inst_rxserie1_FIFO1_fifo0_N20, + O => Inst_rxserie1_FIFO1_fifo0_N720, + SEL => Inst_rxserie1_FIFO1_fifo0_N717 + ); + Inst_rxserie1_FIFO1_fifo0_BU104 : X_LUT4 + generic map( + INIT => X"6666" + ) + port map ( + ADR0 => Inst_rxserie1_FIFO1_fifo0_N20, + ADR1 => Inst_rxserie1_FIFO1_fifo0_N3, + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N717 + ); + Inst_rxserie1_FIFO1_fifo0_BU102 : X_LUT4 + generic map( + INIT => X"5555" + ) + port map ( + ADR0 => Inst_rxserie1_FIFO1_fifo0_N3, + ADR1 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N718 + ); + Inst_rxserie1_FIFO1_fifo0_BU97 : X_SFF + generic map( + INIT => '1' + ) + port map ( + CE => Inst_rxserie1_FIFO1_fifo0_N33, + CLK => clk_speed_BUFGP, + I => Inst_rxserie1_FIFO1_fifo0_N592, + O => Inst_rxserie1_FIFO1_fifo0_N4, + SSET => rst_IBUF, + SET => GSR, + RST => GND, + SRST => GND + ); + Inst_rxserie1_FIFO1_fifo0_BU95 : X_XOR2 + port map ( + I0 => Inst_rxserie1_FIFO1_fifo0_N606, + I1 => Inst_rxserie1_FIFO1_fifo0_N609, + O => Inst_rxserie1_FIFO1_fifo0_N592 + ); + Inst_rxserie1_FIFO1_fifo0_BU94 : X_LUT4 + generic map( + INIT => X"9999" + ) + port map ( + ADR0 => Inst_rxserie1_FIFO1_fifo0_N4, + ADR1 => Inst_rxserie1_FIFO1_fifo0_N3, + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N609 + ); + Inst_rxserie1_FIFO1_fifo0_BU92 : X_SFF + generic map( + INIT => '1' + ) + port map ( + CE => Inst_rxserie1_FIFO1_fifo0_N33, + CLK => clk_speed_BUFGP, + I => Inst_rxserie1_FIFO1_fifo0_N591, + O => Inst_rxserie1_FIFO1_fifo0_N5, + SSET => rst_IBUF, + SET => GSR, + RST => GND, + SRST => GND + ); + Inst_rxserie1_FIFO1_fifo0_BU90 : X_XOR2 + port map ( + I0 => Inst_rxserie1_FIFO1_fifo0_N601, + I1 => Inst_rxserie1_FIFO1_fifo0_N604, + O => Inst_rxserie1_FIFO1_fifo0_N591 + ); + Inst_rxserie1_FIFO1_fifo0_BU89 : X_MUX2 + port map ( + IB => Inst_rxserie1_FIFO1_fifo0_N601, + IA => Inst_rxserie1_FIFO1_fifo0_N5, + O => Inst_rxserie1_FIFO1_fifo0_N606, + SEL => Inst_rxserie1_FIFO1_fifo0_N604 + ); + Inst_rxserie1_FIFO1_fifo0_BU88 : X_LUT4 + generic map( + INIT => X"9999" + ) + port map ( + ADR0 => Inst_rxserie1_FIFO1_fifo0_N5, + ADR1 => Inst_rxserie1_FIFO1_fifo0_N3, + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N604 + ); + Inst_rxserie1_FIFO1_fifo0_BU86 : X_SFF + generic map( + INIT => '1' + ) + port map ( + CE => Inst_rxserie1_FIFO1_fifo0_N33, + CLK => clk_speed_BUFGP, + I => Inst_rxserie1_FIFO1_fifo0_N590, + O => Inst_rxserie1_FIFO1_fifo0_N6, + SSET => rst_IBUF, + SET => GSR, + RST => GND, + SRST => GND + ); + Inst_rxserie1_FIFO1_fifo0_BU84 : X_XOR2 + port map ( + I0 => Inst_rxserie1_FIFO1_fifo0_N596, + I1 => Inst_rxserie1_FIFO1_fifo0_N599, + O => Inst_rxserie1_FIFO1_fifo0_N590 + ); + Inst_rxserie1_FIFO1_fifo0_BU83 : X_MUX2 + port map ( + IB => Inst_rxserie1_FIFO1_fifo0_N596, + IA => Inst_rxserie1_FIFO1_fifo0_N6, + O => Inst_rxserie1_FIFO1_fifo0_N601, + SEL => Inst_rxserie1_FIFO1_fifo0_N599 + ); + Inst_rxserie1_FIFO1_fifo0_BU82 : X_LUT4 + generic map( + INIT => X"9999" + ) + port map ( + ADR0 => Inst_rxserie1_FIFO1_fifo0_N6, + ADR1 => Inst_rxserie1_FIFO1_fifo0_N3, + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N599 + ); + Inst_rxserie1_FIFO1_fifo0_BU80 : X_SFF + generic map( + INIT => '1' + ) + port map ( + CE => Inst_rxserie1_FIFO1_fifo0_N33, + CLK => clk_speed_BUFGP, + I => Inst_rxserie1_FIFO1_fifo0_N589, + O => Inst_rxserie1_FIFO1_fifo0_N7, + SSET => rst_IBUF, + SET => GSR, + RST => GND, + SRST => GND + ); + Inst_rxserie1_FIFO1_fifo0_BU78 : X_XOR2 + port map ( + I0 => Inst_rxserie1_FIFO1_fifo0_N594, + I1 => Inst_rxserie1_FIFO1_fifo0_N593, + O => Inst_rxserie1_FIFO1_fifo0_N589 + ); + Inst_rxserie1_FIFO1_fifo0_BU77 : X_MUX2 + port map ( + IB => Inst_rxserie1_FIFO1_fifo0_N594, + IA => Inst_rxserie1_FIFO1_fifo0_N7, + O => Inst_rxserie1_FIFO1_fifo0_N596, + SEL => Inst_rxserie1_FIFO1_fifo0_N593 + ); + Inst_rxserie1_FIFO1_fifo0_BU76 : X_LUT4 + generic map( + INIT => X"6666" + ) + port map ( + ADR0 => Inst_rxserie1_FIFO1_fifo0_N7, + ADR1 => Inst_rxserie1_FIFO1_fifo0_N3, + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N593 + ); + Inst_rxserie1_FIFO1_fifo0_BU74 : X_LUT4 + generic map( + INIT => X"5555" + ) + port map ( + ADR0 => Inst_rxserie1_FIFO1_fifo0_N3, + ADR1 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N594 + ); + Inst_rxserie1_FIFO1_fifo0_BU69 : X_LUT4 + generic map( + INIT => X"6666" + ) + port map ( + ADR0 => Inst_rxserie1_FIFO1_fifo0_N2, + ADR1 => Inst_rxserie1_FIFO1_fifo0_N3, + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N33 + ); + Inst_rxserie1_FIFO1_fifo0_BU63 : X_SFF + generic map( + INIT => '1' + ) + port map ( + CE => Inst_rxserie1_FIFO1_fifo0_N1, + CLK => clk_speed_BUFGP, + I => Inst_rxserie1_FIFO1_fifo0_N505, + O => Inst_rxserie1_FIFO1_fifo0_wr_ack, + SSET => rst_IBUF, + SET => GSR, + RST => GND, + SRST => GND + ); + Inst_rxserie1_FIFO1_fifo0_BU62 : X_LUT4 + generic map( + INIT => X"bbbb" + ) + port map ( + ADR0 => Inst_rxserie1_flagreg(2), + ADR1 => Inst_rxserie1_FIFO1_wr_en, + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N505 + ); + Inst_rxserie1_FIFO1_fifo0_BU55 : X_SFF + generic map( + INIT => '1' + ) + port map ( + CE => Inst_rxserie1_FIFO1_fifo0_N1, + CLK => clk_speed_BUFGP, + I => Inst_rxserie1_FIFO1_fifo0_N456, + O => Inst_rxserie1_FIFO1_fifo0_wr_err, + SSET => rst_IBUF, + SET => GSR, + RST => GND, + SRST => GND + ); + Inst_rxserie1_FIFO1_fifo0_BU54 : X_LUT4 + generic map( + INIT => X"7777" + ) + port map ( + ADR0 => Inst_rxserie1_flagreg(2), + ADR1 => Inst_rxserie1_FIFO1_wr_en, + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N456 + ); + Inst_rxserie1_FIFO1_fifo0_BU47 : X_LUT4 + generic map( + INIT => X"2222" + ) + port map ( + ADR0 => Inst_rxserie1_FIFO1_wr_en, + ADR1 => Inst_rxserie1_flagreg(2), + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N38 + ); + Inst_rxserie1_FIFO1_fifo0_BU41 : X_LUT4 + generic map( + INIT => X"2222" + ) + port map ( + ADR0 => Inst_rxserie1_FIFO1_wr_en, + ADR1 => Inst_rxserie1_flagreg(2), + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N3 + ); + Inst_rxserie1_FIFO1_fifo0_BU35 : X_SFF + generic map( + INIT => '1' + ) + port map ( + CE => Inst_rxserie1_FIFO1_fifo0_N1, + CLK => clk_speed_BUFGP, + I => Inst_rxserie1_FIFO1_fifo0_N333, + O => Inst_rxserie1_FIFO1_fifo0_rd_ack, + SSET => rst_IBUF, + SET => GSR, + RST => GND, + SRST => GND + ); + Inst_rxserie1_FIFO1_fifo0_BU34 : X_LUT4 + generic map( + INIT => X"bbbb" + ) + port map ( + ADR0 => Inst_rxserie1_flagreg(3), + ADR1 => Inst_rxserie1_FIFO1_state_read_FFd2, + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N333 + ); + Inst_rxserie1_FIFO1_fifo0_BU27 : X_SFF + generic map( + INIT => '1' + ) + port map ( + CE => Inst_rxserie1_FIFO1_fifo0_N1, + CLK => clk_speed_BUFGP, + I => Inst_rxserie1_FIFO1_fifo0_N284, + O => Inst_rxserie1_FIFO1_fifo0_rd_err, + SSET => rst_IBUF, + SET => GSR, + RST => GND, + SRST => GND + ); + Inst_rxserie1_FIFO1_fifo0_BU26 : X_LUT4 + generic map( + INIT => X"7777" + ) + port map ( + ADR0 => Inst_rxserie1_flagreg(3), + ADR1 => Inst_rxserie1_FIFO1_state_read_FFd2, + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N284 + ); + Inst_rxserie1_FIFO1_fifo0_BU19 : X_LUT4 + generic map( + INIT => X"2222" + ) + port map ( + ADR0 => Inst_rxserie1_FIFO1_state_read_FFd2, + ADR1 => Inst_rxserie1_flagreg(3), + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N37 + ); + Inst_rxserie1_FIFO1_fifo0_BU13 : X_LUT4 + generic map( + INIT => X"2222" + ) + port map ( + ADR0 => Inst_rxserie1_FIFO1_state_read_FFd2, + ADR1 => Inst_rxserie1_flagreg(3), + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => Inst_rxserie1_FIFO1_fifo0_N2 + ); + Inst_rxserie1_FIFO1_fifo0_BU7 : X_LUT4 + generic map( + INIT => X"eeee" + ) + port map ( + ADR0 => Inst_rxserie1_flagreg(2), + ADR1 => Inst_rxserie1_flagreg(2), + ADR2 => Inst_rxserie1_FIFO1_fifo0_N0, + ADR3 => Inst_rxserie1_FIFO1_fifo0_N0, + O => NLW_Inst_rxserie1_FIFO1_fifo0_BU7_O_UNCONNECTED + ); + Inst_rxserie1_FIFO1_fifo0_GND : X_ZERO + port map ( + O => Inst_rxserie1_FIFO1_fifo0_N0 + ); + Inst_rxserie1_FIFO1_fifo0_VCC : X_ONE + port map ( + O => Inst_rxserie1_FIFO1_fifo0_N1 + ); + bus_data_5_IOBUF_OBUFT : X_TRI + port map ( + CTL => bus_data_5_IOBUF_OBUFT_GTS_AND, + I => bus_data_5_IOBUF, + O => bus_data(5) + ); + bus_data_5_IOBUF_IBUF : X_BUF + port map ( + I => bus_data(5), + O => N10997 + ); + bus_data_0_IOBUF_OBUFT : X_TRI + port map ( + CTL => bus_data_0_IOBUF_OBUFT_GTS_AND, + I => bus_data_0_IOBUF, + O => bus_data(0) + ); + bus_data_0_IOBUF_IBUF : X_BUF + port map ( + I => bus_data(0), + O => N10987 + ); + bus_data_7_IOBUF_OBUFT : X_TRI + port map ( + CTL => bus_data_7_IOBUF_OBUFT_GTS_AND, + I => bus_data_7_IOBUF, + O => bus_data(7) + ); + bus_data_7_IOBUF_IBUF : X_BUF + port map ( + I => bus_data(7), + O => N11001 + ); + bus_data_1_IOBUF_OBUFT : X_TRI + port map ( + CTL => bus_data_1_IOBUF_OBUFT_GTS_AND, + I => bus_data_1_IOBUF, + O => bus_data(1) + ); + bus_data_1_IOBUF_IBUF : X_BUF + port map ( + I => bus_data(1), + O => N10989 + ); + bus_data_6_IOBUF_OBUFT : X_TRI + port map ( + CTL => bus_data_6_IOBUF_OBUFT_GTS_AND, + I => bus_data_6_IOBUF, + O => bus_data(6) + ); + bus_data_6_IOBUF_IBUF : X_BUF + port map ( + I => bus_data(6), + O => N10999 + ); + bus_data_2_IOBUF_OBUFT : X_TRI + port map ( + CTL => bus_data_2_IOBUF_OBUFT_GTS_AND, + I => bus_data_2_IOBUF, + O => bus_data(2) + ); + bus_data_2_IOBUF_IBUF : X_BUF + port map ( + I => bus_data(2), + O => N10991 + ); + bus_data_4_IOBUF_OBUFT : X_TRI + port map ( + CTL => bus_data_4_IOBUF_OBUFT_GTS_AND, + I => bus_data_4_IOBUF, + O => bus_data(4) + ); + bus_data_4_IOBUF_IBUF : X_BUF + port map ( + I => bus_data(4), + O => N10995 + ); + bus_data_3_IOBUF_OBUFT : X_TRI + port map ( + CTL => bus_data_3_IOBUF_OBUFT_GTS_AND, + I => bus_data_3_IOBUF, + O => bus_data(3) + ); + bus_data_3_IOBUF_IBUF : X_BUF + port map ( + I => bus_data(3), + O => N10993 + ); + Inst_decodisa_dadrL_BU2826 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N18684, + ADR2 => Inst_decodisa_dadrL_N18685, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_255_Q + ); + Inst_decodisa_dadrL_BU2823 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N18685 + ); + Inst_decodisa_dadrL_BU2820 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N18684 + ); + Inst_decodisa_dadrL_BU2815 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N18613, + ADR2 => Inst_decodisa_dadrL_N18614, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_254_Q + ); + Inst_decodisa_dadrL_BU2812 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N18614 + ); + Inst_decodisa_dadrL_BU2809 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N18613 + ); + Inst_decodisa_dadrL_BU2804 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N18542, + ADR2 => Inst_decodisa_dadrL_N18543, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_253_Q + ); + Inst_decodisa_dadrL_BU2801 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N18543 + ); + Inst_decodisa_dadrL_BU2798 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N18542 + ); + Inst_decodisa_dadrL_BU2793 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N18471, + ADR2 => Inst_decodisa_dadrL_N18472, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_252_Q + ); + Inst_decodisa_dadrL_BU2790 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N18472 + ); + Inst_decodisa_dadrL_BU2787 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N18471 + ); + Inst_decodisa_dadrL_BU2782 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N18400, + ADR2 => Inst_decodisa_dadrL_N18401, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_251_Q + ); + Inst_decodisa_dadrL_BU2779 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N18401 + ); + Inst_decodisa_dadrL_BU2776 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N18400 + ); + Inst_decodisa_dadrL_BU2771 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N18329, + ADR2 => Inst_decodisa_dadrL_N18330, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_250_Q + ); + Inst_decodisa_dadrL_BU2768 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N18330 + ); + Inst_decodisa_dadrL_BU2765 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N18329 + ); + Inst_decodisa_dadrL_BU2760 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N18258, + ADR2 => Inst_decodisa_dadrL_N18259, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_249_Q + ); + Inst_decodisa_dadrL_BU2757 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N18259 + ); + Inst_decodisa_dadrL_BU2754 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N18258 + ); + Inst_decodisa_dadrL_BU2749 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N18187, + ADR2 => Inst_decodisa_dadrL_N18188, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_248_Q + ); + Inst_decodisa_dadrL_BU2746 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N18188 + ); + Inst_decodisa_dadrL_BU2743 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N18187 + ); + Inst_decodisa_dadrL_BU2738 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N18116, + ADR2 => Inst_decodisa_dadrL_N18117, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_247_Q + ); + Inst_decodisa_dadrL_BU2735 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N18117 + ); + Inst_decodisa_dadrL_BU2732 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N18116 + ); + Inst_decodisa_dadrL_BU2727 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N18045, + ADR2 => Inst_decodisa_dadrL_N18046, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_246_Q + ); + Inst_decodisa_dadrL_BU2724 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N18046 + ); + Inst_decodisa_dadrL_BU2721 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N18045 + ); + Inst_decodisa_dadrL_BU2716 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N17974, + ADR2 => Inst_decodisa_dadrL_N17975, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_245_Q + ); + Inst_decodisa_dadrL_BU2713 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N17975 + ); + Inst_decodisa_dadrL_BU2710 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N17974 + ); + Inst_decodisa_dadrL_BU2705 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N17903, + ADR2 => Inst_decodisa_dadrL_N17904, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_244_Q + ); + Inst_decodisa_dadrL_BU2702 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N17904 + ); + Inst_decodisa_dadrL_BU2699 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N17903 + ); + Inst_decodisa_dadrL_BU2694 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N17832, + ADR2 => Inst_decodisa_dadrL_N17833, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_243_Q + ); + Inst_decodisa_dadrL_BU2691 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N17833 + ); + Inst_decodisa_dadrL_BU2688 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N17832 + ); + Inst_decodisa_dadrL_BU2683 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N17761, + ADR2 => Inst_decodisa_dadrL_N17762, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_242_Q + ); + Inst_decodisa_dadrL_BU2680 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N17762 + ); + Inst_decodisa_dadrL_BU2677 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N17761 + ); + Inst_decodisa_dadrL_BU2672 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N17690, + ADR2 => Inst_decodisa_dadrL_N17691, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_241_Q + ); + Inst_decodisa_dadrL_BU2669 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N17691 + ); + Inst_decodisa_dadrL_BU2666 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N17690 + ); + Inst_decodisa_dadrL_BU2661 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N17619, + ADR2 => Inst_decodisa_dadrL_N17620, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_240_Q + ); + Inst_decodisa_dadrL_BU2658 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N17620 + ); + Inst_decodisa_dadrL_BU2655 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N17619 + ); + Inst_decodisa_dadrL_BU2650 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N17548, + ADR2 => Inst_decodisa_dadrL_N17549, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_239_Q + ); + Inst_decodisa_dadrL_BU2647 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N17549 + ); + Inst_decodisa_dadrL_BU2644 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N17548 + ); + Inst_decodisa_dadrL_BU2639 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N17477, + ADR2 => Inst_decodisa_dadrL_N17478, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_238_Q + ); + Inst_decodisa_dadrL_BU2636 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N17478 + ); + Inst_decodisa_dadrL_BU2633 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N17477 + ); + Inst_decodisa_dadrL_BU2628 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N17406, + ADR2 => Inst_decodisa_dadrL_N17407, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_237_Q + ); + Inst_decodisa_dadrL_BU2625 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N17407 + ); + Inst_decodisa_dadrL_BU2622 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N17406 + ); + Inst_decodisa_dadrL_BU2617 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N17335, + ADR2 => Inst_decodisa_dadrL_N17336, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_236_Q + ); + Inst_decodisa_dadrL_BU2614 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N17336 + ); + Inst_decodisa_dadrL_BU2611 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N17335 + ); + Inst_decodisa_dadrL_BU2606 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N17264, + ADR2 => Inst_decodisa_dadrL_N17265, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_235_Q + ); + Inst_decodisa_dadrL_BU2603 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N17265 + ); + Inst_decodisa_dadrL_BU2600 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N17264 + ); + Inst_decodisa_dadrL_BU2595 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N17193, + ADR2 => Inst_decodisa_dadrL_N17194, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_234_Q + ); + Inst_decodisa_dadrL_BU2592 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N17194 + ); + Inst_decodisa_dadrL_BU2589 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N17193 + ); + Inst_decodisa_dadrL_BU2584 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N17122, + ADR2 => Inst_decodisa_dadrL_N17123, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_233_Q + ); + Inst_decodisa_dadrL_BU2581 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N17123 + ); + Inst_decodisa_dadrL_BU2578 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N17122 + ); + Inst_decodisa_dadrL_BU2573 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N17051, + ADR2 => Inst_decodisa_dadrL_N17052, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_232_Q + ); + Inst_decodisa_dadrL_BU2570 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N17052 + ); + Inst_decodisa_dadrL_BU2567 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N17051 + ); + Inst_decodisa_dadrL_BU2562 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N16980, + ADR2 => Inst_decodisa_dadrL_N16981, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_231_Q + ); + Inst_decodisa_dadrL_BU2559 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N16981 + ); + Inst_decodisa_dadrL_BU2556 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N16980 + ); + Inst_decodisa_dadrL_BU2551 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N16909, + ADR2 => Inst_decodisa_dadrL_N16910, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_230_Q + ); + Inst_decodisa_dadrL_BU2548 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N16910 + ); + Inst_decodisa_dadrL_BU2545 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N16909 + ); + Inst_decodisa_dadrL_BU2540 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N16838, + ADR2 => Inst_decodisa_dadrL_N16839, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_229_Q + ); + Inst_decodisa_dadrL_BU2537 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N16839 + ); + Inst_decodisa_dadrL_BU2534 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N16838 + ); + Inst_decodisa_dadrL_BU2529 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N16767, + ADR2 => Inst_decodisa_dadrL_N16768, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_228_Q + ); + Inst_decodisa_dadrL_BU2526 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N16768 + ); + Inst_decodisa_dadrL_BU2523 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N16767 + ); + Inst_decodisa_dadrL_BU2518 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N16696, + ADR2 => Inst_decodisa_dadrL_N16697, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_227_Q + ); + Inst_decodisa_dadrL_BU2515 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N16697 + ); + Inst_decodisa_dadrL_BU2512 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N16696 + ); + Inst_decodisa_dadrL_BU2507 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N16625, + ADR2 => Inst_decodisa_dadrL_N16626, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_226_Q + ); + Inst_decodisa_dadrL_BU2504 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N16626 + ); + Inst_decodisa_dadrL_BU2501 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N16625 + ); + Inst_decodisa_dadrL_BU2496 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N16554, + ADR2 => Inst_decodisa_dadrL_N16555, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_225_Q + ); + Inst_decodisa_dadrL_BU2493 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N16555 + ); + Inst_decodisa_dadrL_BU2490 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N16554 + ); + Inst_decodisa_dadrL_BU2485 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N16483, + ADR2 => Inst_decodisa_dadrL_N16484, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_224_Q + ); + Inst_decodisa_dadrL_BU2482 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N16484 + ); + Inst_decodisa_dadrL_BU2479 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N16483 + ); + Inst_decodisa_dadrL_BU2474 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N16412, + ADR2 => Inst_decodisa_dadrL_N16413, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_223_Q + ); + Inst_decodisa_dadrL_BU2471 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N16413 + ); + Inst_decodisa_dadrL_BU2468 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N16412 + ); + Inst_decodisa_dadrL_BU2463 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N16341, + ADR2 => Inst_decodisa_dadrL_N16342, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_222_Q + ); + Inst_decodisa_dadrL_BU2460 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N16342 + ); + Inst_decodisa_dadrL_BU2457 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N16341 + ); + Inst_decodisa_dadrL_BU2452 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N16270, + ADR2 => Inst_decodisa_dadrL_N16271, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_221_Q + ); + Inst_decodisa_dadrL_BU2449 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N16271 + ); + Inst_decodisa_dadrL_BU2446 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N16270 + ); + Inst_decodisa_dadrL_BU2441 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N16199, + ADR2 => Inst_decodisa_dadrL_N16200, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_220_Q + ); + Inst_decodisa_dadrL_BU2438 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N16200 + ); + Inst_decodisa_dadrL_BU2435 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N16199 + ); + Inst_decodisa_dadrL_BU2430 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N16128, + ADR2 => Inst_decodisa_dadrL_N16129, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_219_Q + ); + Inst_decodisa_dadrL_BU2427 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N16129 + ); + Inst_decodisa_dadrL_BU2424 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N16128 + ); + Inst_decodisa_dadrL_BU2419 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N16057, + ADR2 => Inst_decodisa_dadrL_N16058, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_218_Q + ); + Inst_decodisa_dadrL_BU2416 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N16058 + ); + Inst_decodisa_dadrL_BU2413 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N16057 + ); + Inst_decodisa_dadrL_BU2408 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N15986, + ADR2 => Inst_decodisa_dadrL_N15987, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_217_Q + ); + Inst_decodisa_dadrL_BU2405 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N15987 + ); + Inst_decodisa_dadrL_BU2402 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N15986 + ); + Inst_decodisa_dadrL_BU2397 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N15915, + ADR2 => Inst_decodisa_dadrL_N15916, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_216_Q + ); + Inst_decodisa_dadrL_BU2394 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N15916 + ); + Inst_decodisa_dadrL_BU2391 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N15915 + ); + Inst_decodisa_dadrL_BU2386 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N15844, + ADR2 => Inst_decodisa_dadrL_N15845, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_215_Q + ); + Inst_decodisa_dadrL_BU2383 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N15845 + ); + Inst_decodisa_dadrL_BU2380 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N15844 + ); + Inst_decodisa_dadrL_BU2375 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N15773, + ADR2 => Inst_decodisa_dadrL_N15774, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_214_Q + ); + Inst_decodisa_dadrL_BU2372 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N15774 + ); + Inst_decodisa_dadrL_BU2369 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N15773 + ); + Inst_decodisa_dadrL_BU2364 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N15702, + ADR2 => Inst_decodisa_dadrL_N15703, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_213_Q + ); + Inst_decodisa_dadrL_BU2361 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N15703 + ); + Inst_decodisa_dadrL_BU2358 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N15702 + ); + Inst_decodisa_dadrL_BU2353 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N15631, + ADR2 => Inst_decodisa_dadrL_N15632, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_212_Q + ); + Inst_decodisa_dadrL_BU2350 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N15632 + ); + Inst_decodisa_dadrL_BU2347 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N15631 + ); + Inst_decodisa_dadrL_BU2342 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N15560, + ADR2 => Inst_decodisa_dadrL_N15561, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_211_Q + ); + Inst_decodisa_dadrL_BU2339 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N15561 + ); + Inst_decodisa_dadrL_BU2336 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N15560 + ); + Inst_decodisa_dadrL_BU2331 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N15489, + ADR2 => Inst_decodisa_dadrL_N15490, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_210_Q + ); + Inst_decodisa_dadrL_BU2328 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N15490 + ); + Inst_decodisa_dadrL_BU2325 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N15489 + ); + Inst_decodisa_dadrL_BU2320 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N15418, + ADR2 => Inst_decodisa_dadrL_N15419, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_209_Q + ); + Inst_decodisa_dadrL_BU2317 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N15419 + ); + Inst_decodisa_dadrL_BU2314 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N15418 + ); + Inst_decodisa_dadrL_BU2309 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N15347, + ADR2 => Inst_decodisa_dadrL_N15348, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_208_Q + ); + Inst_decodisa_dadrL_BU2306 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N15348 + ); + Inst_decodisa_dadrL_BU2303 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N15347 + ); + Inst_decodisa_dadrL_BU2298 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N15276, + ADR2 => Inst_decodisa_dadrL_N15277, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_207_Q + ); + Inst_decodisa_dadrL_BU2295 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N15277 + ); + Inst_decodisa_dadrL_BU2292 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N15276 + ); + Inst_decodisa_dadrL_BU2287 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N15205, + ADR2 => Inst_decodisa_dadrL_N15206, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_206_Q + ); + Inst_decodisa_dadrL_BU2284 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N15206 + ); + Inst_decodisa_dadrL_BU2281 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N15205 + ); + Inst_decodisa_dadrL_BU2276 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N15134, + ADR2 => Inst_decodisa_dadrL_N15135, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_205_Q + ); + Inst_decodisa_dadrL_BU2273 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N15135 + ); + Inst_decodisa_dadrL_BU2270 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N15134 + ); + Inst_decodisa_dadrL_BU2265 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N15063, + ADR2 => Inst_decodisa_dadrL_N15064, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_204_Q + ); + Inst_decodisa_dadrL_BU2262 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N15064 + ); + Inst_decodisa_dadrL_BU2259 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N15063 + ); + Inst_decodisa_dadrL_BU2254 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N14992, + ADR2 => Inst_decodisa_dadrL_N14993, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_203_Q + ); + Inst_decodisa_dadrL_BU2251 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N14993 + ); + Inst_decodisa_dadrL_BU2248 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N14992 + ); + Inst_decodisa_dadrL_BU2243 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N14921, + ADR2 => Inst_decodisa_dadrL_N14922, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_202_Q + ); + Inst_decodisa_dadrL_BU2240 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N14922 + ); + Inst_decodisa_dadrL_BU2237 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N14921 + ); + Inst_decodisa_dadrL_BU2232 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N14850, + ADR2 => Inst_decodisa_dadrL_N14851, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_201_Q + ); + Inst_decodisa_dadrL_BU2229 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N14851 + ); + Inst_decodisa_dadrL_BU2226 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N14850 + ); + Inst_decodisa_dadrL_BU2221 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N14779, + ADR2 => Inst_decodisa_dadrL_N14780, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_200_Q + ); + Inst_decodisa_dadrL_BU2218 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N14780 + ); + Inst_decodisa_dadrL_BU2215 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N14779 + ); + Inst_decodisa_dadrL_BU2210 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N14708, + ADR2 => Inst_decodisa_dadrL_N14709, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_199_Q + ); + Inst_decodisa_dadrL_BU2207 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N14709 + ); + Inst_decodisa_dadrL_BU2204 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N14708 + ); + Inst_decodisa_dadrL_BU2199 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N14637, + ADR2 => Inst_decodisa_dadrL_N14638, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_198_Q + ); + Inst_decodisa_dadrL_BU2196 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N14638 + ); + Inst_decodisa_dadrL_BU2193 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N14637 + ); + Inst_decodisa_dadrL_BU2188 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N14566, + ADR2 => Inst_decodisa_dadrL_N14567, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_197_Q + ); + Inst_decodisa_dadrL_BU2185 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N14567 + ); + Inst_decodisa_dadrL_BU2182 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N14566 + ); + Inst_decodisa_dadrL_BU2177 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N14495, + ADR2 => Inst_decodisa_dadrL_N14496, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_196_Q + ); + Inst_decodisa_dadrL_BU2174 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N14496 + ); + Inst_decodisa_dadrL_BU2171 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N14495 + ); + Inst_decodisa_dadrL_BU2166 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N14424, + ADR2 => Inst_decodisa_dadrL_N14425, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_195_Q + ); + Inst_decodisa_dadrL_BU2163 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N14425 + ); + Inst_decodisa_dadrL_BU2160 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N14424 + ); + Inst_decodisa_dadrL_BU2155 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N14353, + ADR2 => Inst_decodisa_dadrL_N14354, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_194_Q + ); + Inst_decodisa_dadrL_BU2152 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N14354 + ); + Inst_decodisa_dadrL_BU2149 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N14353 + ); + Inst_decodisa_dadrL_BU2144 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N14282, + ADR2 => Inst_decodisa_dadrL_N14283, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_193_Q + ); + Inst_decodisa_dadrL_BU2141 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N14283 + ); + Inst_decodisa_dadrL_BU2138 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N14282 + ); + Inst_decodisa_dadrL_BU2133 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N14211, + ADR2 => Inst_decodisa_dadrL_N14212, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_192_Q + ); + Inst_decodisa_dadrL_BU2130 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N14212 + ); + Inst_decodisa_dadrL_BU2127 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N14211 + ); + Inst_decodisa_dadrL_BU2122 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N14140, + ADR2 => Inst_decodisa_dadrL_N14141, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_191_Q + ); + Inst_decodisa_dadrL_BU2119 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N14141 + ); + Inst_decodisa_dadrL_BU2116 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N14140 + ); + Inst_decodisa_dadrL_BU2111 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N14069, + ADR2 => Inst_decodisa_dadrL_N14070, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_190_Q + ); + Inst_decodisa_dadrL_BU2108 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N14070 + ); + Inst_decodisa_dadrL_BU2105 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N14069 + ); + Inst_decodisa_dadrL_BU2100 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N13998, + ADR2 => Inst_decodisa_dadrL_N13999, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_189_Q + ); + Inst_decodisa_dadrL_BU2097 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N13999 + ); + Inst_decodisa_dadrL_BU2094 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N13998 + ); + Inst_decodisa_dadrL_BU2089 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N13927, + ADR2 => Inst_decodisa_dadrL_N13928, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_188_Q + ); + Inst_decodisa_dadrL_BU2086 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N13928 + ); + Inst_decodisa_dadrL_BU2083 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N13927 + ); + Inst_decodisa_dadrL_BU2078 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N13856, + ADR2 => Inst_decodisa_dadrL_N13857, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_187_Q + ); + Inst_decodisa_dadrL_BU2075 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N13857 + ); + Inst_decodisa_dadrL_BU2072 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N13856 + ); + Inst_decodisa_dadrL_BU2067 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N13785, + ADR2 => Inst_decodisa_dadrL_N13786, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_186_Q + ); + Inst_decodisa_dadrL_BU2064 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N13786 + ); + Inst_decodisa_dadrL_BU2061 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N13785 + ); + Inst_decodisa_dadrL_BU2056 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N13714, + ADR2 => Inst_decodisa_dadrL_N13715, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_185_Q + ); + Inst_decodisa_dadrL_BU2053 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N13715 + ); + Inst_decodisa_dadrL_BU2050 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N13714 + ); + Inst_decodisa_dadrL_BU2045 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N13643, + ADR2 => Inst_decodisa_dadrL_N13644, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_184_Q + ); + Inst_decodisa_dadrL_BU2042 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N13644 + ); + Inst_decodisa_dadrL_BU2039 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N13643 + ); + Inst_decodisa_dadrL_BU2034 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N13572, + ADR2 => Inst_decodisa_dadrL_N13573, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_183_Q + ); + Inst_decodisa_dadrL_BU2031 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N13573 + ); + Inst_decodisa_dadrL_BU2028 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N13572 + ); + Inst_decodisa_dadrL_BU2023 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N13501, + ADR2 => Inst_decodisa_dadrL_N13502, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_182_Q + ); + Inst_decodisa_dadrL_BU2020 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N13502 + ); + Inst_decodisa_dadrL_BU2017 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N13501 + ); + Inst_decodisa_dadrL_BU2012 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N13430, + ADR2 => Inst_decodisa_dadrL_N13431, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_181_Q + ); + Inst_decodisa_dadrL_BU2009 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N13431 + ); + Inst_decodisa_dadrL_BU2006 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N13430 + ); + Inst_decodisa_dadrL_BU2001 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N13359, + ADR2 => Inst_decodisa_dadrL_N13360, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_180_Q + ); + Inst_decodisa_dadrL_BU1998 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N13360 + ); + Inst_decodisa_dadrL_BU1995 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N13359 + ); + Inst_decodisa_dadrL_BU1990 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N13288, + ADR2 => Inst_decodisa_dadrL_N13289, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_179_Q + ); + Inst_decodisa_dadrL_BU1987 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N13289 + ); + Inst_decodisa_dadrL_BU1984 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N13288 + ); + Inst_decodisa_dadrL_BU1979 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N13217, + ADR2 => Inst_decodisa_dadrL_N13218, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_178_Q + ); + Inst_decodisa_dadrL_BU1976 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N13218 + ); + Inst_decodisa_dadrL_BU1973 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N13217 + ); + Inst_decodisa_dadrL_BU1968 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N13146, + ADR2 => Inst_decodisa_dadrL_N13147, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_177_Q + ); + Inst_decodisa_dadrL_BU1965 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N13147 + ); + Inst_decodisa_dadrL_BU1962 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N13146 + ); + Inst_decodisa_dadrL_BU1957 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N13075, + ADR2 => Inst_decodisa_dadrL_N13076, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_176_Q + ); + Inst_decodisa_dadrL_BU1954 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N13076 + ); + Inst_decodisa_dadrL_BU1951 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N13075 + ); + Inst_decodisa_dadrL_BU1946 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N13004, + ADR2 => Inst_decodisa_dadrL_N13005, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_175_Q + ); + Inst_decodisa_dadrL_BU1943 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N13005 + ); + Inst_decodisa_dadrL_BU1940 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N13004 + ); + Inst_decodisa_dadrL_BU1935 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N12933, + ADR2 => Inst_decodisa_dadrL_N12934, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_174_Q + ); + Inst_decodisa_dadrL_BU1932 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N12934 + ); + Inst_decodisa_dadrL_BU1929 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N12933 + ); + Inst_decodisa_dadrL_BU1924 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N12862, + ADR2 => Inst_decodisa_dadrL_N12863, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_173_Q + ); + Inst_decodisa_dadrL_BU1921 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N12863 + ); + Inst_decodisa_dadrL_BU1918 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N12862 + ); + Inst_decodisa_dadrL_BU1913 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N12791, + ADR2 => Inst_decodisa_dadrL_N12792, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_172_Q + ); + Inst_decodisa_dadrL_BU1910 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N12792 + ); + Inst_decodisa_dadrL_BU1907 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N12791 + ); + Inst_decodisa_dadrL_BU1902 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N12720, + ADR2 => Inst_decodisa_dadrL_N12721, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_171_Q + ); + Inst_decodisa_dadrL_BU1899 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N12721 + ); + Inst_decodisa_dadrL_BU1896 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N12720 + ); + Inst_decodisa_dadrL_BU1891 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N12649, + ADR2 => Inst_decodisa_dadrL_N12650, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_170_Q + ); + Inst_decodisa_dadrL_BU1888 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N12650 + ); + Inst_decodisa_dadrL_BU1885 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N12649 + ); + Inst_decodisa_dadrL_BU1880 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N12578, + ADR2 => Inst_decodisa_dadrL_N12579, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_169_Q + ); + Inst_decodisa_dadrL_BU1877 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N12579 + ); + Inst_decodisa_dadrL_BU1874 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N12578 + ); + Inst_decodisa_dadrL_BU1869 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N12507, + ADR2 => Inst_decodisa_dadrL_N12508, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_168_Q + ); + Inst_decodisa_dadrL_BU1866 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N12508 + ); + Inst_decodisa_dadrL_BU1863 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N12507 + ); + Inst_decodisa_dadrL_BU1858 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N12436, + ADR2 => Inst_decodisa_dadrL_N12437, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_167_Q + ); + Inst_decodisa_dadrL_BU1855 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N12437 + ); + Inst_decodisa_dadrL_BU1852 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N12436 + ); + Inst_decodisa_dadrL_BU1847 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N12365, + ADR2 => Inst_decodisa_dadrL_N12366, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_166_Q + ); + Inst_decodisa_dadrL_BU1844 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N12366 + ); + Inst_decodisa_dadrL_BU1841 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N12365 + ); + Inst_decodisa_dadrL_BU1836 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N12294, + ADR2 => Inst_decodisa_dadrL_N12295, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_165_Q + ); + Inst_decodisa_dadrL_BU1833 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N12295 + ); + Inst_decodisa_dadrL_BU1830 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N12294 + ); + Inst_decodisa_dadrL_BU1825 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N12223, + ADR2 => Inst_decodisa_dadrL_N12224, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_164_Q + ); + Inst_decodisa_dadrL_BU1822 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N12224 + ); + Inst_decodisa_dadrL_BU1819 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N12223 + ); + Inst_decodisa_dadrL_BU1814 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N12152, + ADR2 => Inst_decodisa_dadrL_N12153, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_163_Q + ); + Inst_decodisa_dadrL_BU1811 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N12153 + ); + Inst_decodisa_dadrL_BU1808 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N12152 + ); + Inst_decodisa_dadrL_BU1803 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N12081, + ADR2 => Inst_decodisa_dadrL_N12082, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_162_Q + ); + Inst_decodisa_dadrL_BU1800 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N12082 + ); + Inst_decodisa_dadrL_BU1797 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N12081 + ); + Inst_decodisa_dadrL_BU1792 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N12010, + ADR2 => Inst_decodisa_dadrL_N12011, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_161_Q + ); + Inst_decodisa_dadrL_BU1789 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N12011 + ); + Inst_decodisa_dadrL_BU1786 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N12010 + ); + Inst_decodisa_dadrL_BU1781 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N11939, + ADR2 => Inst_decodisa_dadrL_N11940, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_160_Q + ); + Inst_decodisa_dadrL_BU1778 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N11940 + ); + Inst_decodisa_dadrL_BU1775 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N11939 + ); + Inst_decodisa_dadrL_BU1770 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N11868, + ADR2 => Inst_decodisa_dadrL_N11869, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_159_Q + ); + Inst_decodisa_dadrL_BU1767 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N11869 + ); + Inst_decodisa_dadrL_BU1764 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N11868 + ); + Inst_decodisa_dadrL_BU1759 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N11797, + ADR2 => Inst_decodisa_dadrL_N11798, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_158_Q + ); + Inst_decodisa_dadrL_BU1756 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N11798 + ); + Inst_decodisa_dadrL_BU1753 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N11797 + ); + Inst_decodisa_dadrL_BU1748 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N11726, + ADR2 => Inst_decodisa_dadrL_N11727, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_157_Q + ); + Inst_decodisa_dadrL_BU1745 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N11727 + ); + Inst_decodisa_dadrL_BU1742 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N11726 + ); + Inst_decodisa_dadrL_BU1737 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N11655, + ADR2 => Inst_decodisa_dadrL_N11656, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_156_Q + ); + Inst_decodisa_dadrL_BU1734 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N11656 + ); + Inst_decodisa_dadrL_BU1731 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N11655 + ); + Inst_decodisa_dadrL_BU1726 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N11584, + ADR2 => Inst_decodisa_dadrL_N11585, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_155_Q + ); + Inst_decodisa_dadrL_BU1723 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N11585 + ); + Inst_decodisa_dadrL_BU1720 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N11584 + ); + Inst_decodisa_dadrL_BU1715 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N11513, + ADR2 => Inst_decodisa_dadrL_N11514, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_154_Q + ); + Inst_decodisa_dadrL_BU1712 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N11514 + ); + Inst_decodisa_dadrL_BU1709 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N11513 + ); + Inst_decodisa_dadrL_BU1704 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N11442, + ADR2 => Inst_decodisa_dadrL_N11443, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_153_Q + ); + Inst_decodisa_dadrL_BU1701 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N11443 + ); + Inst_decodisa_dadrL_BU1698 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N11442 + ); + Inst_decodisa_dadrL_BU1693 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N11371, + ADR2 => Inst_decodisa_dadrL_N11372, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_152_Q + ); + Inst_decodisa_dadrL_BU1690 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N11372 + ); + Inst_decodisa_dadrL_BU1687 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N11371 + ); + Inst_decodisa_dadrL_BU1682 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N11300, + ADR2 => Inst_decodisa_dadrL_N11301, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_151_Q + ); + Inst_decodisa_dadrL_BU1679 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N11301 + ); + Inst_decodisa_dadrL_BU1676 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N11300 + ); + Inst_decodisa_dadrL_BU1671 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N11229, + ADR2 => Inst_decodisa_dadrL_N11230, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_150_Q + ); + Inst_decodisa_dadrL_BU1668 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N11230 + ); + Inst_decodisa_dadrL_BU1665 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N11229 + ); + Inst_decodisa_dadrL_BU1660 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N11158, + ADR2 => Inst_decodisa_dadrL_N11159, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_149_Q + ); + Inst_decodisa_dadrL_BU1657 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N11159 + ); + Inst_decodisa_dadrL_BU1654 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N11158 + ); + Inst_decodisa_dadrL_BU1649 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N11087, + ADR2 => Inst_decodisa_dadrL_N11088, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_148_Q + ); + Inst_decodisa_dadrL_BU1646 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N11088 + ); + Inst_decodisa_dadrL_BU1643 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N11087 + ); + Inst_decodisa_dadrL_BU1638 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N11016, + ADR2 => Inst_decodisa_dadrL_N11017, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_147_Q + ); + Inst_decodisa_dadrL_BU1635 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N11017 + ); + Inst_decodisa_dadrL_BU1632 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N11016 + ); + Inst_decodisa_dadrL_BU1627 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N10945, + ADR2 => Inst_decodisa_dadrL_N10946, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_146_Q + ); + Inst_decodisa_dadrL_BU1624 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N10946 + ); + Inst_decodisa_dadrL_BU1621 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N10945 + ); + Inst_decodisa_dadrL_BU1616 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N10874, + ADR2 => Inst_decodisa_dadrL_N10875, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_145_Q + ); + Inst_decodisa_dadrL_BU1613 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N10875 + ); + Inst_decodisa_dadrL_BU1610 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N10874 + ); + Inst_decodisa_dadrL_BU1605 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N10803, + ADR2 => Inst_decodisa_dadrL_N10804, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_144_Q + ); + Inst_decodisa_dadrL_BU1602 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N10804 + ); + Inst_decodisa_dadrL_BU1599 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N10803 + ); + Inst_decodisa_dadrL_BU1594 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N10732, + ADR2 => Inst_decodisa_dadrL_N10733, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_143_Q + ); + Inst_decodisa_dadrL_BU1591 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N10733 + ); + Inst_decodisa_dadrL_BU1588 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N10732 + ); + Inst_decodisa_dadrL_BU1583 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N10661, + ADR2 => Inst_decodisa_dadrL_N10662, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_142_Q + ); + Inst_decodisa_dadrL_BU1580 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N10662 + ); + Inst_decodisa_dadrL_BU1577 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N10661 + ); + Inst_decodisa_dadrL_BU1572 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N10590, + ADR2 => Inst_decodisa_dadrL_N10591, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_141_Q + ); + Inst_decodisa_dadrL_BU1569 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N10591 + ); + Inst_decodisa_dadrL_BU1566 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N10590 + ); + Inst_decodisa_dadrL_BU1561 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N10519, + ADR2 => Inst_decodisa_dadrL_N10520, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_140_Q + ); + Inst_decodisa_dadrL_BU1558 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N10520 + ); + Inst_decodisa_dadrL_BU1555 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N10519 + ); + Inst_decodisa_dadrL_BU1550 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N10448, + ADR2 => Inst_decodisa_dadrL_N10449, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_139_Q + ); + Inst_decodisa_dadrL_BU1547 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N10449 + ); + Inst_decodisa_dadrL_BU1544 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N10448 + ); + Inst_decodisa_dadrL_BU1539 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N10377, + ADR2 => Inst_decodisa_dadrL_N10378, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_138_Q + ); + Inst_decodisa_dadrL_BU1536 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N10378 + ); + Inst_decodisa_dadrL_BU1533 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N10377 + ); + Inst_decodisa_dadrL_BU1528 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N10306, + ADR2 => Inst_decodisa_dadrL_N10307, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_137_Q + ); + Inst_decodisa_dadrL_BU1525 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N10307 + ); + Inst_decodisa_dadrL_BU1522 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N10306 + ); + Inst_decodisa_dadrL_BU1517 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N10235, + ADR2 => Inst_decodisa_dadrL_N10236, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_136_Q + ); + Inst_decodisa_dadrL_BU1514 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N10236 + ); + Inst_decodisa_dadrL_BU1511 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N10235 + ); + Inst_decodisa_dadrL_BU1506 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N10164, + ADR2 => Inst_decodisa_dadrL_N10165, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_135_Q + ); + Inst_decodisa_dadrL_BU1503 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N10165 + ); + Inst_decodisa_dadrL_BU1500 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N10164 + ); + Inst_decodisa_dadrL_BU1495 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N10093, + ADR2 => Inst_decodisa_dadrL_N10094, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_134_Q + ); + Inst_decodisa_dadrL_BU1492 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N10094 + ); + Inst_decodisa_dadrL_BU1489 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N10093 + ); + Inst_decodisa_dadrL_BU1484 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N10022, + ADR2 => Inst_decodisa_dadrL_N10023, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_133_Q + ); + Inst_decodisa_dadrL_BU1481 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N10023 + ); + Inst_decodisa_dadrL_BU1478 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N10022 + ); + Inst_decodisa_dadrL_BU1473 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N9951, + ADR2 => Inst_decodisa_dadrL_N9952, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_132_Q + ); + Inst_decodisa_dadrL_BU1470 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N9952 + ); + Inst_decodisa_dadrL_BU1467 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N9951 + ); + Inst_decodisa_dadrL_BU1462 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N9880, + ADR2 => Inst_decodisa_dadrL_N9881, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_131_Q + ); + Inst_decodisa_dadrL_BU1459 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N9881 + ); + Inst_decodisa_dadrL_BU1456 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N9880 + ); + Inst_decodisa_dadrL_BU1451 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N9809, + ADR2 => Inst_decodisa_dadrL_N9810, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_130_Q + ); + Inst_decodisa_dadrL_BU1448 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N9810 + ); + Inst_decodisa_dadrL_BU1445 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N9809 + ); + Inst_decodisa_dadrL_BU1440 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N9738, + ADR2 => Inst_decodisa_dadrL_N9739, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_129_Q + ); + Inst_decodisa_dadrL_BU1437 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N9739 + ); + Inst_decodisa_dadrL_BU1434 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N9738 + ); + Inst_decodisa_dadrL_BU1429 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N9667, + ADR2 => Inst_decodisa_dadrL_N9668, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_128_Q + ); + Inst_decodisa_dadrL_BU1426 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N9668 + ); + Inst_decodisa_dadrL_BU1423 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N9667 + ); + Inst_decodisa_dadrL_BU1418 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N9596, + ADR2 => Inst_decodisa_dadrL_N9597, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_127_Q + ); + Inst_decodisa_dadrL_BU1415 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N9597 + ); + Inst_decodisa_dadrL_BU1412 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N9596 + ); + Inst_decodisa_dadrL_BU1407 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N9525, + ADR2 => Inst_decodisa_dadrL_N9526, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_126_Q + ); + Inst_decodisa_dadrL_BU1404 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N9526 + ); + Inst_decodisa_dadrL_BU1401 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N9525 + ); + Inst_decodisa_dadrL_BU1396 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N9454, + ADR2 => Inst_decodisa_dadrL_N9455, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_125_Q + ); + Inst_decodisa_dadrL_BU1393 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N9455 + ); + Inst_decodisa_dadrL_BU1390 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N9454 + ); + Inst_decodisa_dadrL_BU1385 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N9383, + ADR2 => Inst_decodisa_dadrL_N9384, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_124_Q + ); + Inst_decodisa_dadrL_BU1382 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N9384 + ); + Inst_decodisa_dadrL_BU1379 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N9383 + ); + Inst_decodisa_dadrL_BU1374 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N9312, + ADR2 => Inst_decodisa_dadrL_N9313, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_123_Q + ); + Inst_decodisa_dadrL_BU1371 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N9313 + ); + Inst_decodisa_dadrL_BU1368 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N9312 + ); + Inst_decodisa_dadrL_BU1363 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N9241, + ADR2 => Inst_decodisa_dadrL_N9242, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_122_Q + ); + Inst_decodisa_dadrL_BU1360 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N9242 + ); + Inst_decodisa_dadrL_BU1357 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N9241 + ); + Inst_decodisa_dadrL_BU1352 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N9170, + ADR2 => Inst_decodisa_dadrL_N9171, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_121_Q + ); + Inst_decodisa_dadrL_BU1349 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N9171 + ); + Inst_decodisa_dadrL_BU1346 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N9170 + ); + Inst_decodisa_dadrL_BU1341 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N9099, + ADR2 => Inst_decodisa_dadrL_N9100, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_120_Q + ); + Inst_decodisa_dadrL_BU1338 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N9100 + ); + Inst_decodisa_dadrL_BU1335 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N9099 + ); + Inst_decodisa_dadrL_BU1330 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N9028, + ADR2 => Inst_decodisa_dadrL_N9029, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_119_Q + ); + Inst_decodisa_dadrL_BU1327 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N9029 + ); + Inst_decodisa_dadrL_BU1324 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N9028 + ); + Inst_decodisa_dadrL_BU1319 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N8957, + ADR2 => Inst_decodisa_dadrL_N8958, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_118_Q + ); + Inst_decodisa_dadrL_BU1316 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N8958 + ); + Inst_decodisa_dadrL_BU1313 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N8957 + ); + Inst_decodisa_dadrL_BU1308 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N8886, + ADR2 => Inst_decodisa_dadrL_N8887, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_117_Q + ); + Inst_decodisa_dadrL_BU1305 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N8887 + ); + Inst_decodisa_dadrL_BU1302 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N8886 + ); + Inst_decodisa_dadrL_BU1297 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N8815, + ADR2 => Inst_decodisa_dadrL_N8816, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_116_Q + ); + Inst_decodisa_dadrL_BU1294 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N8816 + ); + Inst_decodisa_dadrL_BU1291 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N8815 + ); + Inst_decodisa_dadrL_BU1286 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N8744, + ADR2 => Inst_decodisa_dadrL_N8745, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_115_Q + ); + Inst_decodisa_dadrL_BU1283 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N8745 + ); + Inst_decodisa_dadrL_BU1280 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N8744 + ); + Inst_decodisa_dadrL_BU1275 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N8673, + ADR2 => Inst_decodisa_dadrL_N8674, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_114_Q + ); + Inst_decodisa_dadrL_BU1272 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N8674 + ); + Inst_decodisa_dadrL_BU1269 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N8673 + ); + Inst_decodisa_dadrL_BU1264 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N8602, + ADR2 => Inst_decodisa_dadrL_N8603, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_113_Q + ); + Inst_decodisa_dadrL_BU1261 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N8603 + ); + Inst_decodisa_dadrL_BU1258 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N8602 + ); + Inst_decodisa_dadrL_BU1253 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N8531, + ADR2 => Inst_decodisa_dadrL_N8532, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_112_Q + ); + Inst_decodisa_dadrL_BU1250 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N8532 + ); + Inst_decodisa_dadrL_BU1247 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N8531 + ); + Inst_decodisa_dadrL_BU1242 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N8460, + ADR2 => Inst_decodisa_dadrL_N8461, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_111_Q + ); + Inst_decodisa_dadrL_BU1239 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N8461 + ); + Inst_decodisa_dadrL_BU1236 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N8460 + ); + Inst_decodisa_dadrL_BU1231 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N8389, + ADR2 => Inst_decodisa_dadrL_N8390, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_110_Q + ); + Inst_decodisa_dadrL_BU1228 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N8390 + ); + Inst_decodisa_dadrL_BU1225 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N8389 + ); + Inst_decodisa_dadrL_BU1220 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N8318, + ADR2 => Inst_decodisa_dadrL_N8319, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_109_Q + ); + Inst_decodisa_dadrL_BU1217 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N8319 + ); + Inst_decodisa_dadrL_BU1214 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N8318 + ); + Inst_decodisa_dadrL_BU1209 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N8247, + ADR2 => Inst_decodisa_dadrL_N8248, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_108_Q + ); + Inst_decodisa_dadrL_BU1206 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N8248 + ); + Inst_decodisa_dadrL_BU1203 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N8247 + ); + Inst_decodisa_dadrL_BU1198 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N8176, + ADR2 => Inst_decodisa_dadrL_N8177, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_107_Q + ); + Inst_decodisa_dadrL_BU1195 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N8177 + ); + Inst_decodisa_dadrL_BU1192 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N8176 + ); + Inst_decodisa_dadrL_BU1187 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N8105, + ADR2 => Inst_decodisa_dadrL_N8106, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_106_Q + ); + Inst_decodisa_dadrL_BU1184 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N8106 + ); + Inst_decodisa_dadrL_BU1181 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N8105 + ); + Inst_decodisa_dadrL_BU1176 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N8034, + ADR2 => Inst_decodisa_dadrL_N8035, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_105_Q + ); + Inst_decodisa_dadrL_BU1173 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N8035 + ); + Inst_decodisa_dadrL_BU1170 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N8034 + ); + Inst_decodisa_dadrL_BU1165 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N7963, + ADR2 => Inst_decodisa_dadrL_N7964, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_104_Q + ); + Inst_decodisa_dadrL_BU1162 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N7964 + ); + Inst_decodisa_dadrL_BU1159 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N7963 + ); + Inst_decodisa_dadrL_BU1154 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N7892, + ADR2 => Inst_decodisa_dadrL_N7893, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_103_Q + ); + Inst_decodisa_dadrL_BU1151 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N7893 + ); + Inst_decodisa_dadrL_BU1148 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N7892 + ); + Inst_decodisa_dadrL_BU1143 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N7821, + ADR2 => Inst_decodisa_dadrL_N7822, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_102_Q + ); + Inst_decodisa_dadrL_BU1140 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N7822 + ); + Inst_decodisa_dadrL_BU1137 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N7821 + ); + Inst_decodisa_dadrL_BU1132 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N7750, + ADR2 => Inst_decodisa_dadrL_N7751, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_101_Q + ); + Inst_decodisa_dadrL_BU1129 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N7751 + ); + Inst_decodisa_dadrL_BU1126 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N7750 + ); + Inst_decodisa_dadrL_BU1121 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N7679, + ADR2 => Inst_decodisa_dadrL_N7680, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_100_Q + ); + Inst_decodisa_dadrL_BU1118 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N7680 + ); + Inst_decodisa_dadrL_BU1115 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N7679 + ); + Inst_decodisa_dadrL_BU1110 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N7608, + ADR2 => Inst_decodisa_dadrL_N7609, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_99_Q + ); + Inst_decodisa_dadrL_BU1107 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N7609 + ); + Inst_decodisa_dadrL_BU1104 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N7608 + ); + Inst_decodisa_dadrL_BU1099 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N7537, + ADR2 => Inst_decodisa_dadrL_N7538, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_98_Q + ); + Inst_decodisa_dadrL_BU1096 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N7538 + ); + Inst_decodisa_dadrL_BU1093 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N7537 + ); + Inst_decodisa_dadrL_BU1088 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N7466, + ADR2 => Inst_decodisa_dadrL_N7467, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_97_Q + ); + Inst_decodisa_dadrL_BU1085 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N7467 + ); + Inst_decodisa_dadrL_BU1082 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N7466 + ); + Inst_decodisa_dadrL_BU1077 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N7395, + ADR2 => Inst_decodisa_dadrL_N7396, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_96_Q + ); + Inst_decodisa_dadrL_BU1074 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N7396 + ); + Inst_decodisa_dadrL_BU1071 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N7395 + ); + Inst_decodisa_dadrL_BU1066 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N7324, + ADR2 => Inst_decodisa_dadrL_N7325, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_95_Q + ); + Inst_decodisa_dadrL_BU1063 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N7325 + ); + Inst_decodisa_dadrL_BU1060 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N7324 + ); + Inst_decodisa_dadrL_BU1055 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N7253, + ADR2 => Inst_decodisa_dadrL_N7254, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_94_Q + ); + Inst_decodisa_dadrL_BU1052 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N7254 + ); + Inst_decodisa_dadrL_BU1049 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N7253 + ); + Inst_decodisa_dadrL_BU1044 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N7182, + ADR2 => Inst_decodisa_dadrL_N7183, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_93_Q + ); + Inst_decodisa_dadrL_BU1041 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N7183 + ); + Inst_decodisa_dadrL_BU1038 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N7182 + ); + Inst_decodisa_dadrL_BU1033 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N7111, + ADR2 => Inst_decodisa_dadrL_N7112, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_92_Q + ); + Inst_decodisa_dadrL_BU1030 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N7112 + ); + Inst_decodisa_dadrL_BU1027 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N7111 + ); + Inst_decodisa_dadrL_BU1022 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N7040, + ADR2 => Inst_decodisa_dadrL_N7041, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_91_Q + ); + Inst_decodisa_dadrL_BU1019 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N7041 + ); + Inst_decodisa_dadrL_BU1016 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N7040 + ); + Inst_decodisa_dadrL_BU1011 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N6969, + ADR2 => Inst_decodisa_dadrL_N6970, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_90_Q + ); + Inst_decodisa_dadrL_BU1008 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N6970 + ); + Inst_decodisa_dadrL_BU1005 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N6969 + ); + Inst_decodisa_dadrL_BU1000 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N6898, + ADR2 => Inst_decodisa_dadrL_N6899, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_89_Q + ); + Inst_decodisa_dadrL_BU997 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N6899 + ); + Inst_decodisa_dadrL_BU994 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N6898 + ); + Inst_decodisa_dadrL_BU989 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N6827, + ADR2 => Inst_decodisa_dadrL_N6828, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_88_Q + ); + Inst_decodisa_dadrL_BU986 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N6828 + ); + Inst_decodisa_dadrL_BU983 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N6827 + ); + Inst_decodisa_dadrL_BU978 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N6756, + ADR2 => Inst_decodisa_dadrL_N6757, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_87_Q + ); + Inst_decodisa_dadrL_BU975 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N6757 + ); + Inst_decodisa_dadrL_BU972 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N6756 + ); + Inst_decodisa_dadrL_BU967 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N6685, + ADR2 => Inst_decodisa_dadrL_N6686, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_86_Q + ); + Inst_decodisa_dadrL_BU964 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N6686 + ); + Inst_decodisa_dadrL_BU961 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N6685 + ); + Inst_decodisa_dadrL_BU956 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N6614, + ADR2 => Inst_decodisa_dadrL_N6615, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_85_Q + ); + Inst_decodisa_dadrL_BU953 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N6615 + ); + Inst_decodisa_dadrL_BU950 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N6614 + ); + Inst_decodisa_dadrL_BU945 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N6543, + ADR2 => Inst_decodisa_dadrL_N6544, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_84_Q + ); + Inst_decodisa_dadrL_BU942 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N6544 + ); + Inst_decodisa_dadrL_BU939 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N6543 + ); + Inst_decodisa_dadrL_BU934 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N6472, + ADR2 => Inst_decodisa_dadrL_N6473, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_83_Q + ); + Inst_decodisa_dadrL_BU931 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N6473 + ); + Inst_decodisa_dadrL_BU928 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N6472 + ); + Inst_decodisa_dadrL_BU923 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N6401, + ADR2 => Inst_decodisa_dadrL_N6402, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_82_Q + ); + Inst_decodisa_dadrL_BU920 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N6402 + ); + Inst_decodisa_dadrL_BU917 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N6401 + ); + Inst_decodisa_dadrL_BU912 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N6330, + ADR2 => Inst_decodisa_dadrL_N6331, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_81_Q + ); + Inst_decodisa_dadrL_BU909 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N6331 + ); + Inst_decodisa_dadrL_BU906 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N6330 + ); + Inst_decodisa_dadrL_BU901 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N6259, + ADR2 => Inst_decodisa_dadrL_N6260, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_80_Q + ); + Inst_decodisa_dadrL_BU898 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N6260 + ); + Inst_decodisa_dadrL_BU895 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N6259 + ); + Inst_decodisa_dadrL_BU890 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N6188, + ADR2 => Inst_decodisa_dadrL_N6189, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_79_Q + ); + Inst_decodisa_dadrL_BU887 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N6189 + ); + Inst_decodisa_dadrL_BU884 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N6188 + ); + Inst_decodisa_dadrL_BU879 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N6117, + ADR2 => Inst_decodisa_dadrL_N6118, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_78_Q + ); + Inst_decodisa_dadrL_BU876 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N6118 + ); + Inst_decodisa_dadrL_BU873 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N6117 + ); + Inst_decodisa_dadrL_BU868 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N6046, + ADR2 => Inst_decodisa_dadrL_N6047, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_77_Q + ); + Inst_decodisa_dadrL_BU865 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N6047 + ); + Inst_decodisa_dadrL_BU862 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N6046 + ); + Inst_decodisa_dadrL_BU857 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N5975, + ADR2 => Inst_decodisa_dadrL_N5976, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_76_Q + ); + Inst_decodisa_dadrL_BU854 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N5976 + ); + Inst_decodisa_dadrL_BU851 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N5975 + ); + Inst_decodisa_dadrL_BU846 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N5904, + ADR2 => Inst_decodisa_dadrL_N5905, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_75_Q + ); + Inst_decodisa_dadrL_BU843 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N5905 + ); + Inst_decodisa_dadrL_BU840 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N5904 + ); + Inst_decodisa_dadrL_BU835 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N5833, + ADR2 => Inst_decodisa_dadrL_N5834, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_74_Q + ); + Inst_decodisa_dadrL_BU832 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N5834 + ); + Inst_decodisa_dadrL_BU829 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N5833 + ); + Inst_decodisa_dadrL_BU824 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N5762, + ADR2 => Inst_decodisa_dadrL_N5763, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_73_Q + ); + Inst_decodisa_dadrL_BU821 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N5763 + ); + Inst_decodisa_dadrL_BU818 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N5762 + ); + Inst_decodisa_dadrL_BU813 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N5691, + ADR2 => Inst_decodisa_dadrL_N5692, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_72_Q + ); + Inst_decodisa_dadrL_BU810 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N5692 + ); + Inst_decodisa_dadrL_BU807 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N5691 + ); + Inst_decodisa_dadrL_BU802 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N5620, + ADR2 => Inst_decodisa_dadrL_N5621, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_71_Q + ); + Inst_decodisa_dadrL_BU799 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N5621 + ); + Inst_decodisa_dadrL_BU796 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N5620 + ); + Inst_decodisa_dadrL_BU791 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N5549, + ADR2 => Inst_decodisa_dadrL_N5550, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_70_Q + ); + Inst_decodisa_dadrL_BU788 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N5550 + ); + Inst_decodisa_dadrL_BU785 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N5549 + ); + Inst_decodisa_dadrL_BU780 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N5478, + ADR2 => Inst_decodisa_dadrL_N5479, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_69_Q + ); + Inst_decodisa_dadrL_BU777 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N5479 + ); + Inst_decodisa_dadrL_BU774 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N5478 + ); + Inst_decodisa_dadrL_BU769 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N5407, + ADR2 => Inst_decodisa_dadrL_N5408, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_68_Q + ); + Inst_decodisa_dadrL_BU766 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N5408 + ); + Inst_decodisa_dadrL_BU763 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N5407 + ); + Inst_decodisa_dadrL_BU758 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N5336, + ADR2 => Inst_decodisa_dadrL_N5337, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_67_Q + ); + Inst_decodisa_dadrL_BU755 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N5337 + ); + Inst_decodisa_dadrL_BU752 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N5336 + ); + Inst_decodisa_dadrL_BU747 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N5265, + ADR2 => Inst_decodisa_dadrL_N5266, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_66_Q + ); + Inst_decodisa_dadrL_BU744 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N5266 + ); + Inst_decodisa_dadrL_BU741 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N5265 + ); + Inst_decodisa_dadrL_BU736 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N5194, + ADR2 => Inst_decodisa_dadrL_N5195, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_65_Q + ); + Inst_decodisa_dadrL_BU733 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N5195 + ); + Inst_decodisa_dadrL_BU730 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N5194 + ); + Inst_decodisa_dadrL_BU725 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N5123, + ADR2 => Inst_decodisa_dadrL_N5124, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_64_Q + ); + Inst_decodisa_dadrL_BU722 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N5124 + ); + Inst_decodisa_dadrL_BU719 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N5123 + ); + Inst_decodisa_dadrL_BU714 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N5052, + ADR2 => Inst_decodisa_dadrL_N5053, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_63_Q + ); + Inst_decodisa_dadrL_BU711 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N5053 + ); + Inst_decodisa_dadrL_BU708 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N5052 + ); + Inst_decodisa_dadrL_BU703 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N4981, + ADR2 => Inst_decodisa_dadrL_N4982, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_62_Q + ); + Inst_decodisa_dadrL_BU700 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N4982 + ); + Inst_decodisa_dadrL_BU697 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N4981 + ); + Inst_decodisa_dadrL_BU692 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N4910, + ADR2 => Inst_decodisa_dadrL_N4911, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_61_Q + ); + Inst_decodisa_dadrL_BU689 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N4911 + ); + Inst_decodisa_dadrL_BU686 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N4910 + ); + Inst_decodisa_dadrL_BU681 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N4839, + ADR2 => Inst_decodisa_dadrL_N4840, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_60_Q + ); + Inst_decodisa_dadrL_BU678 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N4840 + ); + Inst_decodisa_dadrL_BU675 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N4839 + ); + Inst_decodisa_dadrL_BU670 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N4768, + ADR2 => Inst_decodisa_dadrL_N4769, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_59_Q + ); + Inst_decodisa_dadrL_BU667 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N4769 + ); + Inst_decodisa_dadrL_BU664 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N4768 + ); + Inst_decodisa_dadrL_BU659 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N4697, + ADR2 => Inst_decodisa_dadrL_N4698, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_58_Q + ); + Inst_decodisa_dadrL_BU656 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N4698 + ); + Inst_decodisa_dadrL_BU653 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N4697 + ); + Inst_decodisa_dadrL_BU648 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N4626, + ADR2 => Inst_decodisa_dadrL_N4627, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_57_Q + ); + Inst_decodisa_dadrL_BU645 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N4627 + ); + Inst_decodisa_dadrL_BU642 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N4626 + ); + Inst_decodisa_dadrL_BU637 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N4555, + ADR2 => Inst_decodisa_dadrL_N4556, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_56_Q + ); + Inst_decodisa_dadrL_BU634 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N4556 + ); + Inst_decodisa_dadrL_BU631 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N4555 + ); + Inst_decodisa_dadrL_BU626 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N4484, + ADR2 => Inst_decodisa_dadrL_N4485, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_55_Q + ); + Inst_decodisa_dadrL_BU623 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N4485 + ); + Inst_decodisa_dadrL_BU620 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N4484 + ); + Inst_decodisa_dadrL_BU615 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N4413, + ADR2 => Inst_decodisa_dadrL_N4414, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_54_Q + ); + Inst_decodisa_dadrL_BU612 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N4414 + ); + Inst_decodisa_dadrL_BU609 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N4413 + ); + Inst_decodisa_dadrL_BU604 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N4342, + ADR2 => Inst_decodisa_dadrL_N4343, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_53_Q + ); + Inst_decodisa_dadrL_BU601 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N4343 + ); + Inst_decodisa_dadrL_BU598 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N4342 + ); + Inst_decodisa_dadrL_BU593 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N4271, + ADR2 => Inst_decodisa_dadrL_N4272, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_52_Q + ); + Inst_decodisa_dadrL_BU590 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N4272 + ); + Inst_decodisa_dadrL_BU587 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N4271 + ); + Inst_decodisa_dadrL_BU582 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N4200, + ADR2 => Inst_decodisa_dadrL_N4201, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_51_Q + ); + Inst_decodisa_dadrL_BU579 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N4201 + ); + Inst_decodisa_dadrL_BU576 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N4200 + ); + Inst_decodisa_dadrL_BU571 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N4129, + ADR2 => Inst_decodisa_dadrL_N4130, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_50_Q + ); + Inst_decodisa_dadrL_BU568 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N4130 + ); + Inst_decodisa_dadrL_BU565 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N4129 + ); + Inst_decodisa_dadrL_BU560 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N4058, + ADR2 => Inst_decodisa_dadrL_N4059, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_49_Q + ); + Inst_decodisa_dadrL_BU557 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N4059 + ); + Inst_decodisa_dadrL_BU554 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N4058 + ); + Inst_decodisa_dadrL_BU549 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N3987, + ADR2 => Inst_decodisa_dadrL_N3988, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_48_Q + ); + Inst_decodisa_dadrL_BU546 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N3988 + ); + Inst_decodisa_dadrL_BU543 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N3987 + ); + Inst_decodisa_dadrL_BU538 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N3916, + ADR2 => Inst_decodisa_dadrL_N3917, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_47_Q + ); + Inst_decodisa_dadrL_BU535 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N3917 + ); + Inst_decodisa_dadrL_BU532 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N3916 + ); + Inst_decodisa_dadrL_BU527 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N3845, + ADR2 => Inst_decodisa_dadrL_N3846, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_46_Q + ); + Inst_decodisa_dadrL_BU524 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N3846 + ); + Inst_decodisa_dadrL_BU521 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N3845 + ); + Inst_decodisa_dadrL_BU516 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N3774, + ADR2 => Inst_decodisa_dadrL_N3775, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_45_Q + ); + Inst_decodisa_dadrL_BU513 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N3775 + ); + Inst_decodisa_dadrL_BU510 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N3774 + ); + Inst_decodisa_dadrL_BU505 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N3703, + ADR2 => Inst_decodisa_dadrL_N3704, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_44_Q + ); + Inst_decodisa_dadrL_BU502 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N3704 + ); + Inst_decodisa_dadrL_BU499 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N3703 + ); + Inst_decodisa_dadrL_BU494 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N3632, + ADR2 => Inst_decodisa_dadrL_N3633, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_43_Q + ); + Inst_decodisa_dadrL_BU491 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N3633 + ); + Inst_decodisa_dadrL_BU488 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N3632 + ); + Inst_decodisa_dadrL_BU483 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N3561, + ADR2 => Inst_decodisa_dadrL_N3562, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_42_Q + ); + Inst_decodisa_dadrL_BU480 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N3562 + ); + Inst_decodisa_dadrL_BU477 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N3561 + ); + Inst_decodisa_dadrL_BU472 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N3490, + ADR2 => Inst_decodisa_dadrL_N3491, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_41_Q + ); + Inst_decodisa_dadrL_BU469 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N3491 + ); + Inst_decodisa_dadrL_BU466 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N3490 + ); + Inst_decodisa_dadrL_BU461 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N3419, + ADR2 => Inst_decodisa_dadrL_N3420, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_40_Q + ); + Inst_decodisa_dadrL_BU458 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N3420 + ); + Inst_decodisa_dadrL_BU455 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N3419 + ); + Inst_decodisa_dadrL_BU450 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N3348, + ADR2 => Inst_decodisa_dadrL_N3349, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_39_Q + ); + Inst_decodisa_dadrL_BU447 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N3349 + ); + Inst_decodisa_dadrL_BU444 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N3348 + ); + Inst_decodisa_dadrL_BU439 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N3277, + ADR2 => Inst_decodisa_dadrL_N3278, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_38_Q + ); + Inst_decodisa_dadrL_BU436 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N3278 + ); + Inst_decodisa_dadrL_BU433 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N3277 + ); + Inst_decodisa_dadrL_BU428 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N3206, + ADR2 => Inst_decodisa_dadrL_N3207, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_37_Q + ); + Inst_decodisa_dadrL_BU425 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N3207 + ); + Inst_decodisa_dadrL_BU422 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N3206 + ); + Inst_decodisa_dadrL_BU417 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N3135, + ADR2 => Inst_decodisa_dadrL_N3136, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_36_Q + ); + Inst_decodisa_dadrL_BU414 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N3136 + ); + Inst_decodisa_dadrL_BU411 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N3135 + ); + Inst_decodisa_dadrL_BU406 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N3064, + ADR2 => Inst_decodisa_dadrL_N3065, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_35_Q + ); + Inst_decodisa_dadrL_BU403 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N3065 + ); + Inst_decodisa_dadrL_BU400 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N3064 + ); + Inst_decodisa_dadrL_BU395 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N2993, + ADR2 => Inst_decodisa_dadrL_N2994, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_34_Q + ); + Inst_decodisa_dadrL_BU392 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N2994 + ); + Inst_decodisa_dadrL_BU389 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N2993 + ); + Inst_decodisa_dadrL_BU384 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N2922, + ADR2 => Inst_decodisa_dadrL_N2923, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_33_Q + ); + Inst_decodisa_dadrL_BU381 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N2923 + ); + Inst_decodisa_dadrL_BU378 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N2922 + ); + Inst_decodisa_dadrL_BU373 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N2851, + ADR2 => Inst_decodisa_dadrL_N2852, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_32_Q + ); + Inst_decodisa_dadrL_BU370 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N2852 + ); + Inst_decodisa_dadrL_BU367 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N2851 + ); + Inst_decodisa_dadrL_BU362 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N2780, + ADR2 => Inst_decodisa_dadrL_N2781, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_31_Q + ); + Inst_decodisa_dadrL_BU359 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N2781 + ); + Inst_decodisa_dadrL_BU356 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N2780 + ); + Inst_decodisa_dadrL_BU351 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N2709, + ADR2 => Inst_decodisa_dadrL_N2710, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_30_Q + ); + Inst_decodisa_dadrL_BU348 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N2710 + ); + Inst_decodisa_dadrL_BU345 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N2709 + ); + Inst_decodisa_dadrL_BU340 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N2638, + ADR2 => Inst_decodisa_dadrL_N2639, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_29_Q + ); + Inst_decodisa_dadrL_BU337 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N2639 + ); + Inst_decodisa_dadrL_BU334 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N2638 + ); + Inst_decodisa_dadrL_BU329 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N2567, + ADR2 => Inst_decodisa_dadrL_N2568, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_28_Q + ); + Inst_decodisa_dadrL_BU326 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N2568 + ); + Inst_decodisa_dadrL_BU323 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N2567 + ); + Inst_decodisa_dadrL_BU318 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N2496, + ADR2 => Inst_decodisa_dadrL_N2497, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_27_Q + ); + Inst_decodisa_dadrL_BU315 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N2497 + ); + Inst_decodisa_dadrL_BU312 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N2496 + ); + Inst_decodisa_dadrL_BU307 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N2425, + ADR2 => Inst_decodisa_dadrL_N2426, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_26_Q + ); + Inst_decodisa_dadrL_BU304 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N2426 + ); + Inst_decodisa_dadrL_BU301 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N2425 + ); + Inst_decodisa_dadrL_BU296 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N2354, + ADR2 => Inst_decodisa_dadrL_N2355, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_25_Q + ); + Inst_decodisa_dadrL_BU293 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N2355 + ); + Inst_decodisa_dadrL_BU290 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N2354 + ); + Inst_decodisa_dadrL_BU285 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N2283, + ADR2 => Inst_decodisa_dadrL_N2284, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_24_Q + ); + Inst_decodisa_dadrL_BU282 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N2284 + ); + Inst_decodisa_dadrL_BU279 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N2283 + ); + Inst_decodisa_dadrL_BU274 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N2212, + ADR2 => Inst_decodisa_dadrL_N2213, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_23_Q + ); + Inst_decodisa_dadrL_BU271 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N2213 + ); + Inst_decodisa_dadrL_BU268 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N2212 + ); + Inst_decodisa_dadrL_BU263 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N2141, + ADR2 => Inst_decodisa_dadrL_N2142, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_22_Q + ); + Inst_decodisa_dadrL_BU260 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N2142 + ); + Inst_decodisa_dadrL_BU257 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N2141 + ); + Inst_decodisa_dadrL_BU252 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N2070, + ADR2 => Inst_decodisa_dadrL_N2071, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_21_Q + ); + Inst_decodisa_dadrL_BU249 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N2071 + ); + Inst_decodisa_dadrL_BU246 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N2070 + ); + Inst_decodisa_dadrL_BU241 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N1999, + ADR2 => Inst_decodisa_dadrL_N2000, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_20_Q + ); + Inst_decodisa_dadrL_BU238 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N2000 + ); + Inst_decodisa_dadrL_BU235 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N1999 + ); + Inst_decodisa_dadrL_BU230 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N1928, + ADR2 => Inst_decodisa_dadrL_N1929, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_19_Q + ); + Inst_decodisa_dadrL_BU227 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N1929 + ); + Inst_decodisa_dadrL_BU224 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N1928 + ); + Inst_decodisa_dadrL_BU219 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N1857, + ADR2 => Inst_decodisa_dadrL_N1858, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_18_Q + ); + Inst_decodisa_dadrL_BU216 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N1858 + ); + Inst_decodisa_dadrL_BU213 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N1857 + ); + Inst_decodisa_dadrL_BU208 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N1786, + ADR2 => Inst_decodisa_dadrL_N1787, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_17_Q + ); + Inst_decodisa_dadrL_BU205 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N1787 + ); + Inst_decodisa_dadrL_BU202 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N1786 + ); + Inst_decodisa_dadrL_BU197 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N1715, + ADR2 => Inst_decodisa_dadrL_N1716, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_16_Q + ); + Inst_decodisa_dadrL_BU194 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N1716 + ); + Inst_decodisa_dadrL_BU191 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N1715 + ); + Inst_decodisa_dadrL_BU186 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N1644, + ADR2 => Inst_decodisa_dadrL_N1645, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_15_Q + ); + Inst_decodisa_dadrL_BU183 : X_LUT4 + generic map( + INIT => X"8000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N1645 + ); + Inst_decodisa_dadrL_BU180 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N1644 + ); + Inst_decodisa_dadrL_BU175 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N1573, + ADR2 => Inst_decodisa_dadrL_N1574, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_14_Q + ); + Inst_decodisa_dadrL_BU172 : X_LUT4 + generic map( + INIT => X"0080" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N1574 + ); + Inst_decodisa_dadrL_BU169 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N1573 + ); + Inst_decodisa_dadrL_BU164 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N1502, + ADR2 => Inst_decodisa_dadrL_N1503, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_13_Q + ); + Inst_decodisa_dadrL_BU161 : X_LUT4 + generic map( + INIT => X"0800" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N1503 + ); + Inst_decodisa_dadrL_BU158 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N1502 + ); + Inst_decodisa_dadrL_BU153 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N1431, + ADR2 => Inst_decodisa_dadrL_N1432, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_12_Q + ); + Inst_decodisa_dadrL_BU150 : X_LUT4 + generic map( + INIT => X"0008" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N1432 + ); + Inst_decodisa_dadrL_BU147 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N1431 + ); + Inst_decodisa_dadrL_BU142 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N1360, + ADR2 => Inst_decodisa_dadrL_N1361, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_11_Q + ); + Inst_decodisa_dadrL_BU139 : X_LUT4 + generic map( + INIT => X"2000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N1361 + ); + Inst_decodisa_dadrL_BU136 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N1360 + ); + Inst_decodisa_dadrL_BU131 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N1289, + ADR2 => Inst_decodisa_dadrL_N1290, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_10_Q + ); + Inst_decodisa_dadrL_BU128 : X_LUT4 + generic map( + INIT => X"0020" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N1290 + ); + Inst_decodisa_dadrL_BU125 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N1289 + ); + Inst_decodisa_dadrL_BU120 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N1218, + ADR2 => Inst_decodisa_dadrL_N1219, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_9_Q + ); + Inst_decodisa_dadrL_BU117 : X_LUT4 + generic map( + INIT => X"0200" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N1219 + ); + Inst_decodisa_dadrL_BU114 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N1218 + ); + Inst_decodisa_dadrL_BU109 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N1147, + ADR2 => Inst_decodisa_dadrL_N1148, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_8_Q + ); + Inst_decodisa_dadrL_BU106 : X_LUT4 + generic map( + INIT => X"0002" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N1148 + ); + Inst_decodisa_dadrL_BU103 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N1147 + ); + Inst_decodisa_dadrL_BU98 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N1076, + ADR2 => Inst_decodisa_dadrL_N1077, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_7_Q + ); + Inst_decodisa_dadrL_BU95 : X_LUT4 + generic map( + INIT => X"4000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N1077 + ); + Inst_decodisa_dadrL_BU92 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N1076 + ); + Inst_decodisa_dadrL_BU87 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N1005, + ADR2 => Inst_decodisa_dadrL_N1006, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_6_Q + ); + Inst_decodisa_dadrL_BU84 : X_LUT4 + generic map( + INIT => X"0040" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N1006 + ); + Inst_decodisa_dadrL_BU81 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N1005 + ); + Inst_decodisa_dadrL_BU76 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N934, + ADR2 => Inst_decodisa_dadrL_N935, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_5_Q + ); + Inst_decodisa_dadrL_BU73 : X_LUT4 + generic map( + INIT => X"0400" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N935 + ); + Inst_decodisa_dadrL_BU70 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N934 + ); + Inst_decodisa_dadrL_BU65 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N863, + ADR2 => Inst_decodisa_dadrL_N864, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_4_Q + ); + Inst_decodisa_dadrL_BU62 : X_LUT4 + generic map( + INIT => X"0004" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N864 + ); + Inst_decodisa_dadrL_BU59 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N863 + ); + Inst_decodisa_dadrL_BU54 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N792, + ADR2 => Inst_decodisa_dadrL_N793, + ADR3 => Inst_decodisa_dadrL_N0, + O => cs(3) + ); + Inst_decodisa_dadrL_BU51 : X_LUT4 + generic map( + INIT => X"1000" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N793 + ); + Inst_decodisa_dadrL_BU48 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N792 + ); + Inst_decodisa_dadrL_BU43 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N721, + ADR2 => Inst_decodisa_dadrL_N722, + ADR3 => Inst_decodisa_dadrL_N0, + O => cs(2) + ); + Inst_decodisa_dadrL_BU40 : X_LUT4 + generic map( + INIT => X"0010" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N722 + ); + Inst_decodisa_dadrL_BU37 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N721 + ); + Inst_decodisa_dadrL_BU32 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N650, + ADR2 => Inst_decodisa_dadrL_N651, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_1_Q + ); + Inst_decodisa_dadrL_BU29 : X_LUT4 + generic map( + INIT => X"0100" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N651 + ); + Inst_decodisa_dadrL_BU26 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N650 + ); + Inst_decodisa_dadrL_BU21 : X_LUT4 + generic map( + INIT => X"8080" + ) + port map ( + ADR0 => Inst_decodisa_reg_select, + ADR1 => Inst_decodisa_dadrL_N579, + ADR2 => Inst_decodisa_dadrL_N580, + ADR3 => Inst_decodisa_dadrL_N0, + O => Inst_decodisa_dadrL_O_0_Q + ); + Inst_decodisa_dadrL_BU18 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => bus_adr_3_IBUF, + ADR1 => bus_adr_2_IBUF, + ADR2 => bus_adr_1_IBUF, + ADR3 => bus_adr_0_IBUF, + O => Inst_decodisa_dadrL_N580 + ); + Inst_decodisa_dadrL_BU15 : X_LUT4 + generic map( + INIT => X"0001" + ) + port map ( + ADR0 => bus_adr_7_IBUF, + ADR1 => bus_adr_6_IBUF, + ADR2 => bus_adr_5_IBUF, + ADR3 => bus_adr_4_IBUF, + O => Inst_decodisa_dadrL_N579 + ); + Inst_decodisa_dadrL_GND : X_ZERO + port map ( + O => Inst_decodisa_dadrL_N0 + ); + Inst_decodisa_dadrL_VCC : X_ONE + port map ( + O => NLW_Inst_decodisa_dadrL_VCC_O_UNCONNECTED + ); + clk_speed_BUFGP_BUFG : X_CKBUF + port map ( + I => clk_speed_BUFGP_IBUFG, + O => clk_speed_BUFGP + ); + clk_speed_BUFGP_IBUFG_69 : X_CKBUF + port map ( + I => clk_speed, + O => clk_speed_BUFGP_IBUFG + ); + Inst_rxserie1_RCONF_REG_7_GSR_OR_70 : X_OR2 + port map ( + I0 => rst_IBUF, + I1 => GSR, + O => Inst_rxserie1_RCONF_REG_7_GSR_OR + ); + Inst_rxserie1_RCONF_REG_0_GSR_OR_71 : X_OR2 + port map ( + I0 => rst_IBUF, + I1 => GSR, + O => Inst_rxserie1_RCONF_REG_0_GSR_OR + ); + Inst_rxserie1_RFLAG_REG_0_GSR_OR_72 : X_OR2 + port map ( + I0 => Inst_rxserie1_RFLAG_REG_0_n0000, + I1 => GSR, + O => Inst_rxserie1_RFLAG_REG_0_GSR_OR + ); + Inst_rxserie1_FIFO1_wr_en_GSR_OR_73 : X_OR2 + port map ( + I0 => rst_IBUF, + I1 => GSR, + O => Inst_rxserie1_FIFO1_wr_en_GSR_OR + ); + Inst_rxserie1_RCONF_REG_6_GSR_OR_74 : X_OR2 + port map ( + I0 => rst_IBUF, + I1 => GSR, + O => Inst_rxserie1_RCONF_REG_6_GSR_OR + ); + Inst_rxserie1_RCONF_REG_5_GSR_OR_75 : X_OR2 + port map ( + I0 => rst_IBUF, + I1 => GSR, + O => Inst_rxserie1_RCONF_REG_5_GSR_OR + ); + Inst_rxserie1_RCONF_REG_4_GSR_OR_76 : X_OR2 + port map ( + I0 => rst_IBUF, + I1 => GSR, + O => Inst_rxserie1_RCONF_REG_4_GSR_OR + ); + Inst_rxserie1_RCONF_REG_3_GSR_OR_77 : X_OR2 + port map ( + I0 => rst_IBUF, + I1 => GSR, + O => Inst_rxserie1_RCONF_REG_3_GSR_OR + ); + Inst_rxserie1_RFLAG_REG_6_GSR_OR_78 : X_OR2 + port map ( + I0 => Inst_rxserie1_RFLAG_REG_6_n0000, + I1 => GSR, + O => Inst_rxserie1_RFLAG_REG_6_GSR_OR + ); + Inst_rxserie1_RCONF_REG_1_GSR_OR_79 : X_OR2 + port map ( + I0 => rst_IBUF, + I1 => GSR, + O => Inst_rxserie1_RCONF_REG_1_GSR_OR + ); + Inst_rxserie1_RFLAG_REG_5_GSR_OR_80 : X_OR2 + port map ( + I0 => Inst_rxserie1_RFLAG_REG_5_n0000, + I1 => GSR, + O => Inst_rxserie1_RFLAG_REG_5_GSR_OR + ); + Inst_rxserie1_RCONF_REG_2_GSR_OR_81 : X_OR2 + port map ( + I0 => rst_IBUF, + I1 => GSR, + O => Inst_rxserie1_RCONF_REG_2_GSR_OR + ); + Inst_rxserie1_RFLAG_REG_4_GSR_OR_82 : X_OR2 + port map ( + I0 => Inst_rxserie1_RFLAG_REG_4_n0000, + I1 => GSR, + O => Inst_rxserie1_RFLAG_REG_4_GSR_OR + ); + Inst_rxserie1_RFLAG_REG_3_GSR_OR_83 : X_OR2 + port map ( + I0 => Inst_rxserie1_RFLAG_REG_3_n0000, + I1 => GSR, + O => Inst_rxserie1_RFLAG_REG_3_GSR_OR + ); + Inst_rxserie1_RFLAG_REG_2_GSR_OR_84 : X_OR2 + port map ( + I0 => Inst_rxserie1_RFLAG_REG_2_n0000, + I1 => GSR, + O => Inst_rxserie1_RFLAG_REG_2_GSR_OR + ); + Inst_rxserie1_RFLAG_REG_1_GSR_OR_85 : X_OR2 + port map ( + I0 => Inst_rxserie1_RFLAG_REG_1_n0000, + I1 => GSR, + O => Inst_rxserie1_RFLAG_REG_1_GSR_OR + ); + Inst_rxserie1_RC1_RHR_6_GSR_OR_86 : X_OR2 + port map ( + I0 => rst_IBUF, + I1 => GSR, + O => Inst_rxserie1_RC1_RHR_6_GSR_OR + ); + Inst_rxserie1_RC1_RHR_3_GSR_OR_87 : X_OR2 + port map ( + I0 => rst_IBUF, + I1 => GSR, + O => Inst_rxserie1_RC1_RHR_3_GSR_OR + ); + Inst_rxserie1_RC1_RHR_5_GSR_OR_88 : X_OR2 + port map ( + I0 => rst_IBUF, + I1 => GSR, + O => Inst_rxserie1_RC1_RHR_5_GSR_OR + ); + Inst_rxserie1_RC1_RHR_4_GSR_OR_89 : X_OR2 + port map ( + I0 => rst_IBUF, + I1 => GSR, + O => Inst_rxserie1_RC1_RHR_4_GSR_OR + ); + Inst_rxserie1_RC1_RHR_0_GSR_OR_90 : X_OR2 + port map ( + I0 => rst_IBUF, + I1 => GSR, + O => Inst_rxserie1_RC1_RHR_0_GSR_OR + ); + Inst_rxserie1_RC1_RHR_2_GSR_OR_91 : X_OR2 + port map ( + I0 => rst_IBUF, + I1 => GSR, + O => Inst_rxserie1_RC1_RHR_2_GSR_OR + ); + Inst_rxserie1_RC1_RHR_1_GSR_OR_92 : X_OR2 + port map ( + I0 => rst_IBUF, + I1 => GSR, + O => Inst_rxserie1_RC1_RHR_1_GSR_OR + ); + Inst_rxserie1_RC1_READ2_GSR_OR_93 : X_OR2 + port map ( + I0 => rst_IBUF, + I1 => GSR, + O => Inst_rxserie1_RC1_READ2_GSR_OR + ); + Inst_rxserie1_RC1_IDLE1_GSR_OR_94 : X_OR2 + port map ( + I0 => rst_IBUF, + I1 => GSR, + O => Inst_rxserie1_RC1_IDLE1_GSR_OR + ); + Inst_rxserie1_RC1_READ1_GSR_OR_95 : X_OR2 + port map ( + I0 => rst_IBUF, + I1 => GSR, + O => Inst_rxserie1_RC1_READ1_GSR_OR + ); + Inst_rxserie1_RC1_IDLE_GSR_OR_96 : X_OR2 + port map ( + I0 => rst_IBUF, + I1 => GSR, + O => Inst_rxserie1_RC1_IDLE_GSR_OR + ); + Inst_rxserie1_RC1_HUNT_GSR_OR_97 : X_OR2 + port map ( + I0 => rst_IBUF, + I1 => GSR, + O => Inst_rxserie1_RC1_HUNT_GSR_OR + ); + Inst_rxserie1_RC1_RXCNT_1_GSR_OR_98 : X_OR2 + port map ( + I0 => rst_IBUF, + I1 => GSR, + O => Inst_rxserie1_RC1_RXCNT_1_GSR_OR + ); + Inst_rxserie1_RC1_RX1_GSR_OR_99 : X_OR2 + port map ( + I0 => rst_IBUF, + I1 => GSR, + O => Inst_rxserie1_RC1_RX1_GSR_OR + ); + Inst_rxserie1_RC1_RXCLK_GSR_OR_100 : X_OR2 + port map ( + I0 => rst_IBUF, + I1 => GSR, + O => Inst_rxserie1_RC1_RXCLK_GSR_OR + ); + Inst_rxserie1_RC1_RXPARITY_GSR_OR_101 : X_OR2 + port map ( + I0 => rst_IBUF, + I1 => GSR, + O => Inst_rxserie1_RC1_RXPARITY_GSR_OR + ); + Inst_rxserie1_RC1_PARITYGEN_GSR_OR_102 : X_OR2 + port map ( + I0 => rst_IBUF, + I1 => GSR, + O => Inst_rxserie1_RC1_PARITYGEN_GSR_OR + ); + Inst_rxserie1_RC1_RXSTOP_GSR_OR_103 : X_OR2 + port map ( + I0 => rst_IBUF, + I1 => GSR, + O => Inst_rxserie1_RC1_RXSTOP_GSR_OR + ); + Inst_rxserie1_RC1_RSR_7_GSR_OR_104 : X_OR2 + port map ( + I0 => rst_IBUF, + I1 => GSR, + O => Inst_rxserie1_RC1_RSR_7_GSR_OR + ); + Inst_rxserie1_RC1_RSR_6_GSR_OR_105 : X_OR2 + port map ( + I0 => rst_IBUF, + I1 => GSR, + O => Inst_rxserie1_RC1_RSR_6_GSR_OR + ); + Inst_rxserie1_RC1_RSR_5_GSR_OR_106 : X_OR2 + port map ( + I0 => rst_IBUF, + I1 => GSR, + O => Inst_rxserie1_RC1_RSR_5_GSR_OR + ); + Inst_rxserie1_RC1_RSR_4_GSR_OR_107 : X_OR2 + port map ( + I0 => rst_IBUF, + I1 => GSR, + O => Inst_rxserie1_RC1_RSR_4_GSR_OR + ); + Inst_rxserie1_RC1_RSR_3_GSR_OR_108 : X_OR2 + port map ( + I0 => rst_IBUF, + I1 => GSR, + O => Inst_rxserie1_RC1_RSR_3_GSR_OR + ); + Inst_rxserie1_RC1_RSR_2_GSR_OR_109 : X_OR2 + port map ( + I0 => rst_IBUF, + I1 => GSR, + O => Inst_rxserie1_RC1_RSR_2_GSR_OR + ); + Inst_rxserie1_RC1_RSR_1_GSR_OR_110 : X_OR2 + port map ( + I0 => rst_IBUF, + I1 => GSR, + O => Inst_rxserie1_RC1_RSR_1_GSR_OR + ); + Inst_rxserie1_RC1_RSR_0_GSR_OR_111 : X_OR2 + port map ( + I0 => rst_IBUF, + I1 => GSR, + O => Inst_rxserie1_RC1_RSR_0_GSR_OR + ); + Inst_rxserie1_RC1_RHR_7_GSR_OR_112 : X_OR2 + port map ( + I0 => rst_IBUF, + I1 => GSR, + O => Inst_rxserie1_RC1_RHR_7_GSR_OR + ); + Inst_rxserie1_RC1_RXDATARDY_GSR_OR_113 : X_OR2 + port map ( + I0 => rst_IBUF, + I1 => GSR, + O => Inst_rxserie1_RC1_RXDATARDY_GSR_OR + ); + Inst_rxserie1_RC1_OVERRUN_GSR_OR_114 : X_OR2 + port map ( + I0 => rst_IBUF, + I1 => GSR, + O => Inst_rxserie1_RC1_OVERRUN_GSR_OR + ); + Inst_rxserie1_RC1_PARITY_ERR_GSR_OR_115 : X_OR2 + port map ( + I0 => rst_IBUF, + I1 => GSR, + O => Inst_rxserie1_RC1_PARITY_ERR_GSR_OR + ); + Inst_rxserie1_RC1_FRAMING_ERR_GSR_OR_116 : X_OR2 + port map ( + I0 => rst_IBUF, + I1 => GSR, + O => Inst_rxserie1_RC1_FRAMING_ERR_GSR_OR + ); + Inst_rxserie1_RC1_RXCNT_3_GSR_OR_117 : X_OR2 + port map ( + I0 => rst_IBUF, + I1 => GSR, + O => Inst_rxserie1_RC1_RXCNT_3_GSR_OR + ); + Inst_rxserie1_RC1_RXCNT_2_GSR_OR_118 : X_OR2 + port map ( + I0 => rst_IBUF, + I1 => GSR, + O => Inst_rxserie1_RC1_RXCNT_2_GSR_OR + ); + Inst_rxserie1_RC1_RXCNT_0_GSR_OR_119 : X_OR2 + port map ( + I0 => rst_IBUF, + I1 => GSR, + O => Inst_rxserie1_RC1_RXCNT_0_GSR_OR + ); + Inst_rxserie1_CLOCK1_ckout_GSR_OR_120 : X_OR2 + port map ( + I0 => rst_IBUF, + I1 => GSR, + O => Inst_rxserie1_CLOCK1_ckout_GSR_OR + ); + Inst_rxserie1_CLOCK1_compteur_9_GSR_OR_121 : X_OR2 + port map ( + I0 => rst_IBUF, + I1 => GSR, + O => Inst_rxserie1_CLOCK1_compteur_9_GSR_OR + ); + Inst_rxserie1_CLOCK1_compteur_8_GSR_OR_122 : X_OR2 + port map ( + I0 => rst_IBUF, + I1 => GSR, + O => Inst_rxserie1_CLOCK1_compteur_8_GSR_OR + ); + Inst_rxserie1_CLOCK1_compteur_0_GSR_OR_123 : X_OR2 + port map ( + I0 => Inst_rxserie1_CLOCK1_compteur_0_0_n0000, + I1 => GSR, + O => Inst_rxserie1_CLOCK1_compteur_0_GSR_OR + ); + Inst_rxserie1_CLOCK1_compteur_1_GSR_OR_124 : X_OR2 + port map ( + I0 => Inst_rxserie1_CLOCK1_compteur_0_1_n0000, + I1 => GSR, + O => Inst_rxserie1_CLOCK1_compteur_1_GSR_OR + ); + Inst_rxserie1_CLOCK1_compteur_2_GSR_OR_125 : X_OR2 + port map ( + I0 => Inst_rxserie1_CLOCK1_compteur_0_2_n0000, + I1 => GSR, + O => Inst_rxserie1_CLOCK1_compteur_2_GSR_OR + ); + Inst_rxserie1_CLOCK1_compteur_3_GSR_OR_126 : X_OR2 + port map ( + I0 => Inst_rxserie1_CLOCK1_compteur_0_3_n0000, + I1 => GSR, + O => Inst_rxserie1_CLOCK1_compteur_3_GSR_OR + ); + Inst_rxserie1_CLOCK1_compteur_4_GSR_OR_127 : X_OR2 + port map ( + I0 => rst_IBUF, + I1 => GSR, + O => Inst_rxserie1_CLOCK1_compteur_4_GSR_OR + ); + Inst_rxserie1_CLOCK1_compteur_5_GSR_OR_128 : X_OR2 + port map ( + I0 => rst_IBUF, + I1 => GSR, + O => Inst_rxserie1_CLOCK1_compteur_5_GSR_OR + ); + Inst_rxserie1_CLOCK1_compteur_6_GSR_OR_129 : X_OR2 + port map ( + I0 => rst_IBUF, + I1 => GSR, + O => Inst_rxserie1_CLOCK1_compteur_6_GSR_OR + ); + Inst_rxserie1_CLOCK1_compteur_7_GSR_OR_130 : X_OR2 + port map ( + I0 => rst_IBUF, + I1 => GSR, + O => Inst_rxserie1_CLOCK1_compteur_7_GSR_OR + ); + bus_data_0_IOBUF_OBUFT_GTS_AND_131 : X_AND2 + port map ( + I0 => NlwInverterSignal_bus_data_0_IOBUF_OBUFT_GTS_AND_IN0, + I1 => NlwInverterSignal_bus_data_0_IOBUF_OBUFT_GTS_AND_IN1, + O => bus_data_0_IOBUF_OBUFT_GTS_AND + ); + bus_data_1_IOBUF_OBUFT_GTS_AND_132 : X_AND2 + port map ( + I0 => NlwInverterSignal_bus_data_1_IOBUF_OBUFT_GTS_AND_IN0, + I1 => NlwInverterSignal_bus_data_1_IOBUF_OBUFT_GTS_AND_IN1, + O => bus_data_1_IOBUF_OBUFT_GTS_AND + ); + bus_data_2_IOBUF_OBUFT_GTS_AND_133 : X_AND2 + port map ( + I0 => NlwInverterSignal_bus_data_2_IOBUF_OBUFT_GTS_AND_IN0, + I1 => NlwInverterSignal_bus_data_2_IOBUF_OBUFT_GTS_AND_IN1, + O => bus_data_2_IOBUF_OBUFT_GTS_AND + ); + bus_data_3_IOBUF_OBUFT_GTS_AND_134 : X_AND2 + port map ( + I0 => NlwInverterSignal_bus_data_3_IOBUF_OBUFT_GTS_AND_IN0, + I1 => NlwInverterSignal_bus_data_3_IOBUF_OBUFT_GTS_AND_IN1, + O => bus_data_3_IOBUF_OBUFT_GTS_AND + ); + bus_data_4_IOBUF_OBUFT_GTS_AND_135 : X_AND2 + port map ( + I0 => NlwInverterSignal_bus_data_4_IOBUF_OBUFT_GTS_AND_IN0, + I1 => NlwInverterSignal_bus_data_4_IOBUF_OBUFT_GTS_AND_IN1, + O => bus_data_4_IOBUF_OBUFT_GTS_AND + ); + bus_data_5_IOBUF_OBUFT_GTS_AND_136 : X_AND2 + port map ( + I0 => NlwInverterSignal_bus_data_5_IOBUF_OBUFT_GTS_AND_IN0, + I1 => NlwInverterSignal_bus_data_5_IOBUF_OBUFT_GTS_AND_IN1, + O => bus_data_5_IOBUF_OBUFT_GTS_AND + ); + bus_data_6_IOBUF_OBUFT_GTS_AND_137 : X_AND2 + port map ( + I0 => NlwInverterSignal_bus_data_6_IOBUF_OBUFT_GTS_AND_IN0, + I1 => NlwInverterSignal_bus_data_6_IOBUF_OBUFT_GTS_AND_IN1, + O => bus_data_6_IOBUF_OBUFT_GTS_AND + ); + bus_data_7_IOBUF_OBUFT_GTS_AND_138 : X_AND2 + port map ( + I0 => NlwInverterSignal_bus_data_7_IOBUF_OBUFT_GTS_AND_IN0, + I1 => NlwInverterSignal_bus_data_7_IOBUF_OBUFT_GTS_AND_IN1, + O => bus_data_7_IOBUF_OBUFT_GTS_AND + ); + NlwBlock_fpga_VCC : X_ONE + port map ( + O => VCC + ); + NlwBlock_fpga_GND : X_ZERO + port map ( + O => GND + ); + NlwInverterBlock_Inst_rxserie1_I7_0_T : X_INV + port map ( + I => Inst_rxserie1_I7_N1369, + O => NlwInverterSignal_Inst_rxserie1_I7_0_T + ); + NlwInverterBlock_Inst_rxserie1_I7_7_T : X_INV + port map ( + I => Inst_rxserie1_I7_N1369, + O => NlwInverterSignal_Inst_rxserie1_I7_7_T + ); + NlwInverterBlock_Inst_rxserie1_I7_6_T : X_INV + port map ( + I => Inst_rxserie1_I7_N1369, + O => NlwInverterSignal_Inst_rxserie1_I7_6_T + ); + NlwInverterBlock_Inst_rxserie1_I7_5_T : X_INV + port map ( + I => Inst_rxserie1_I7_N1369, + O => NlwInverterSignal_Inst_rxserie1_I7_5_T + ); + NlwInverterBlock_Inst_rxserie1_I7_4_T : X_INV + port map ( + I => Inst_rxserie1_I7_N1369, + O => NlwInverterSignal_Inst_rxserie1_I7_4_T + ); + NlwInverterBlock_Inst_rxserie1_I7_3_T : X_INV + port map ( + I => Inst_rxserie1_I7_N1369, + O => NlwInverterSignal_Inst_rxserie1_I7_3_T + ); + NlwInverterBlock_Inst_rxserie1_I7_2_T : X_INV + port map ( + I => Inst_rxserie1_I7_N1369, + O => NlwInverterSignal_Inst_rxserie1_I7_2_T + ); + NlwInverterBlock_Inst_rxserie1_I7_1_T : X_INV + port map ( + I => Inst_rxserie1_I7_N1369, + O => NlwInverterSignal_Inst_rxserie1_I7_1_T + ); + NlwInverterBlock_Inst_rxserie1_FIFO1_wr_en_C : X_INV + port map ( + I => clk_speed_BUFGP, + O => NlwInverterSignal_Inst_rxserie1_FIFO1_wr_en_C + ); + NlwInverterBlock_Inst_rxserie1_FIFO1_state_write_FFd1_C : X_INV + port map ( + I => clk_speed_BUFGP, + O => NlwInverterSignal_Inst_rxserie1_FIFO1_state_write_FFd1_C + ); + NlwInverterBlock_Inst_rxserie1_RFLAG_I1_1_T : X_INV + port map ( + I => Inst_rxserie1_RFLAG_I1_N1369, + O => NlwInverterSignal_Inst_rxserie1_RFLAG_I1_1_T + ); + NlwInverterBlock_Inst_rxserie1_RFLAG_I1_2_T : X_INV + port map ( + I => Inst_rxserie1_RFLAG_I1_N1369, + O => NlwInverterSignal_Inst_rxserie1_RFLAG_I1_2_T + ); + NlwInverterBlock_Inst_rxserie1_RFLAG_I1_0_T : X_INV + port map ( + I => Inst_rxserie1_RFLAG_I1_N1369, + O => NlwInverterSignal_Inst_rxserie1_RFLAG_I1_0_T + ); + NlwInverterBlock_Inst_rxserie1_RFLAG_I1_7_T : X_INV + port map ( + I => Inst_rxserie1_RFLAG_I1_N1369, + O => NlwInverterSignal_Inst_rxserie1_RFLAG_I1_7_T + ); + NlwInverterBlock_Inst_rxserie1_RFLAG_I1_6_T : X_INV + port map ( + I => Inst_rxserie1_RFLAG_I1_N1369, + O => NlwInverterSignal_Inst_rxserie1_RFLAG_I1_6_T + ); + NlwInverterBlock_Inst_rxserie1_RFLAG_I1_5_T : X_INV + port map ( + I => Inst_rxserie1_RFLAG_I1_N1369, + O => NlwInverterSignal_Inst_rxserie1_RFLAG_I1_5_T + ); + NlwInverterBlock_Inst_rxserie1_RFLAG_I1_4_T : X_INV + port map ( + I => Inst_rxserie1_RFLAG_I1_N1369, + O => NlwInverterSignal_Inst_rxserie1_RFLAG_I1_4_T + ); + NlwInverterBlock_Inst_rxserie1_RFLAG_I1_3_T : X_INV + port map ( + I => Inst_rxserie1_RFLAG_I1_N1369, + O => NlwInverterSignal_Inst_rxserie1_RFLAG_I1_3_T + ); + NlwInverterBlock_Inst_rxserie1_RCONF_I1_1_T : X_INV + port map ( + I => Inst_rxserie1_RCONF_I1_N1369, + O => NlwInverterSignal_Inst_rxserie1_RCONF_I1_1_T + ); + NlwInverterBlock_Inst_rxserie1_RCONF_I1_2_T : X_INV + port map ( + I => Inst_rxserie1_RCONF_I1_N1369, + O => NlwInverterSignal_Inst_rxserie1_RCONF_I1_2_T + ); + NlwInverterBlock_Inst_rxserie1_RCONF_I1_0_T : X_INV + port map ( + I => Inst_rxserie1_RCONF_I1_N1369, + O => NlwInverterSignal_Inst_rxserie1_RCONF_I1_0_T + ); + NlwInverterBlock_Inst_rxserie1_RCONF_I1_7_T : X_INV + port map ( + I => Inst_rxserie1_RCONF_I1_N1369, + O => NlwInverterSignal_Inst_rxserie1_RCONF_I1_7_T + ); + NlwInverterBlock_Inst_rxserie1_RCONF_I1_6_T : X_INV + port map ( + I => Inst_rxserie1_RCONF_I1_N1369, + O => NlwInverterSignal_Inst_rxserie1_RCONF_I1_6_T + ); + NlwInverterBlock_Inst_rxserie1_RCONF_I1_5_T : X_INV + port map ( + I => Inst_rxserie1_RCONF_I1_N1369, + O => NlwInverterSignal_Inst_rxserie1_RCONF_I1_5_T + ); + NlwInverterBlock_Inst_rxserie1_RCONF_I1_4_T : X_INV + port map ( + I => Inst_rxserie1_RCONF_I1_N1369, + O => NlwInverterSignal_Inst_rxserie1_RCONF_I1_4_T + ); + NlwInverterBlock_Inst_rxserie1_RCONF_I1_3_T : X_INV + port map ( + I => Inst_rxserie1_RCONF_I1_N1369, + O => NlwInverterSignal_Inst_rxserie1_RCONF_I1_3_T + ); + NlwInverterBlock_Inst_rxserie1_FIFO1_state_write_FFd3_C : X_INV + port map ( + I => clk_speed_BUFGP, + O => NlwInverterSignal_Inst_rxserie1_FIFO1_state_write_FFd3_C + ); + NlwInverterBlock_Inst_rxserie1_FIFO1_state_write_FFd2_C : X_INV + port map ( + I => clk_speed_BUFGP, + O => NlwInverterSignal_Inst_rxserie1_FIFO1_state_write_FFd2_C + ); + NlwInverterBlock_bus_data_0_IOBUF_OBUFT_GTS_AND_IN0 : X_INV + port map ( + I => N4805, + O => NlwInverterSignal_bus_data_0_IOBUF_OBUFT_GTS_AND_IN0 + ); + NlwInverterBlock_bus_data_0_IOBUF_OBUFT_GTS_AND_IN1 : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_bus_data_0_IOBUF_OBUFT_GTS_AND_IN1 + ); + NlwInverterBlock_bus_data_1_IOBUF_OBUFT_GTS_AND_IN0 : X_INV + port map ( + I => N4805, + O => NlwInverterSignal_bus_data_1_IOBUF_OBUFT_GTS_AND_IN0 + ); + NlwInverterBlock_bus_data_1_IOBUF_OBUFT_GTS_AND_IN1 : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_bus_data_1_IOBUF_OBUFT_GTS_AND_IN1 + ); + NlwInverterBlock_bus_data_2_IOBUF_OBUFT_GTS_AND_IN0 : X_INV + port map ( + I => N4805, + O => NlwInverterSignal_bus_data_2_IOBUF_OBUFT_GTS_AND_IN0 + ); + NlwInverterBlock_bus_data_2_IOBUF_OBUFT_GTS_AND_IN1 : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_bus_data_2_IOBUF_OBUFT_GTS_AND_IN1 + ); + NlwInverterBlock_bus_data_3_IOBUF_OBUFT_GTS_AND_IN0 : X_INV + port map ( + I => N4805, + O => NlwInverterSignal_bus_data_3_IOBUF_OBUFT_GTS_AND_IN0 + ); + NlwInverterBlock_bus_data_3_IOBUF_OBUFT_GTS_AND_IN1 : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_bus_data_3_IOBUF_OBUFT_GTS_AND_IN1 + ); + NlwInverterBlock_bus_data_4_IOBUF_OBUFT_GTS_AND_IN0 : X_INV + port map ( + I => N4805, + O => NlwInverterSignal_bus_data_4_IOBUF_OBUFT_GTS_AND_IN0 + ); + NlwInverterBlock_bus_data_4_IOBUF_OBUFT_GTS_AND_IN1 : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_bus_data_4_IOBUF_OBUFT_GTS_AND_IN1 + ); + NlwInverterBlock_bus_data_5_IOBUF_OBUFT_GTS_AND_IN0 : X_INV + port map ( + I => N4805, + O => NlwInverterSignal_bus_data_5_IOBUF_OBUFT_GTS_AND_IN0 + ); + NlwInverterBlock_bus_data_5_IOBUF_OBUFT_GTS_AND_IN1 : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_bus_data_5_IOBUF_OBUFT_GTS_AND_IN1 + ); + NlwInverterBlock_bus_data_6_IOBUF_OBUFT_GTS_AND_IN0 : X_INV + port map ( + I => N4805, + O => NlwInverterSignal_bus_data_6_IOBUF_OBUFT_GTS_AND_IN0 + ); + NlwInverterBlock_bus_data_6_IOBUF_OBUFT_GTS_AND_IN1 : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_bus_data_6_IOBUF_OBUFT_GTS_AND_IN1 + ); + NlwInverterBlock_bus_data_7_IOBUF_OBUFT_GTS_AND_IN0 : X_INV + port map ( + I => N4805, + O => NlwInverterSignal_bus_data_7_IOBUF_OBUFT_GTS_AND_IN0 + ); + NlwInverterBlock_bus_data_7_IOBUF_OBUFT_GTS_AND_IN1 : X_INV + port map ( + I => GTS, + O => NlwInverterSignal_bus_data_7_IOBUF_OBUFT_GTS_AND_IN1 + ); + NlwBlockROC : X_ROC + generic map (ROC_WIDTH => 100 ns) + port map (O => GSR); + NlwBlockTOC : X_TOC + port map (O => GTS); + +end Structure; + diff --git a/2004/n/fpga/src/fpga/isa_const.vhd b/2004/n/fpga/src/fpga/isa_const.vhd new file mode 100644 index 0000000..cbc10d5 --- /dev/null +++ b/2004/n/fpga/src/fpga/isa_const.vhd @@ -0,0 +1,34 @@ +-- isa_const.vhd +-- Eurobot 2004 : APB Team +-- Auteur : Pierre-André Galmes +-- Fichier de déclaration de constantes. + +-- RQ : pour une indentation bien sous vim : +-- 1 - ":set shiftwidth=4" +-- 2 - se placer sous "package nono_const is" +-- 3 - tapez : = puis shift+G + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + + +-- Constantes relatives au bus ISA +package isa_const is + + -- Temps d'une période d'horloge sur le bus ISA + -- bus à 8MHz + constant ISA_CK_PERIOD : time := 125 ns; + + -- Ligne RW : lecture et écriture + constant ISA_READ : std_logic := '0'; + constant ISA_WRITE : std_logic := '1'; + + -- Nombre de bits du bus d'adresse + constant NB_BIT_ADDRESS_ISA : integer := 20; + subtype T_ADDRESS_ISA is std_logic_vector((NB_BIT_ADDRESS_ISA - 1) downto 0); + +end isa_const; + + diff --git a/2004/n/fpga/src/fpga/nono_const.vhd b/2004/n/fpga/src/fpga/nono_const.vhd new file mode 100644 index 0000000..470fc42 --- /dev/null +++ b/2004/n/fpga/src/fpga/nono_const.vhd @@ -0,0 +1,72 @@ +-- nono_const.vhd +-- Eurobot 2004 : APB Team +-- Auteur : Pierre-André Galmes +-- Fichier de déclaration de constantes. + +-- RQ : pour une indentation bien sous vim : +-- 1 - ":set shiftwidth=4" +-- 2 - se placer sous "package nono_const is" +-- 3 - tapez : = puis shift+G + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + + +-- Constantes relatives +package nono_const is + + -- Temps d'une période d'horloge sur la carte + -- f=33,33MHz + constant CK_PERIOD : time := 30 ns; + + -- diviseur pour le clockgene des ports série. + -- Pour 1.8432MHz, avec 1 de diviseur, on a 0% + constant DIVIS_CK_SERIAL :integer := 1; + + -- Pour 33,33MHz, et avec 18 de diviseur, on obtient + -- une erreur sur le baudrate de 0.46% + + + -- Taille d'une addresse sur la carte + -- RQ : 10 = nb suffisant + -- 12 = 3 digit en héxa + constant NB_BIT_ADDRESS : integer := 10; + + -- Taille des données sur la carte + constant NB_BIT_DATA : integer := 8; + + -- Définition de nouveaux types : T_ADDRESS et T_DATA + --subtype T_ADDRESS is unsigned ((NB_BIT_ADDRESS - 1) downto 0); + --subtype T_DATA is unsigned ((NB_BIT_DATA - 1) downto 0); + subtype T_ADDRESS is std_logic_vector ((NB_BIT_ADDRESS - 1) downto 0); + subtype T_DATA is std_logic_vector ((NB_BIT_DATA - 1) downto 0); + + -- Les différentes banques d'adresses (4 x 256) + -- Rq pour Pierre : ça va influer sur le bloc de gestion du bus + constant START_ADDR_B0 : T_ADDRESS := "0000000000"; + constant START_ADDR_B1 : T_ADDRESS := "0100000000"; + constant START_ADDR_B2 : T_ADDRESS := "1000000000"; + constant START_ADDR_B3 : T_ADDRESS := "1100000000"; + + -- Les addresses des différents registres. + + -- gestion des interruptions + constant A_INTERRUPT_MANAGER : T_ADDRESS := START_ADDR_B0 + x"00"; + -- Bloc d'IO1 + constant A_IO1_REG_DATA : T_ADDRESS := START_ADDR_B0 + x"01"; + constant A_IO1_REG_DIRECTION : T_ADDRESS := START_ADDR_B0 + x"02"; + constant A_IO1_REG_INTERRUPT_MASK : T_ADDRESS := START_ADDR_B0 + x"03"; + constant A_IO1_READ_OUTPUT : T_ADDRESS := START_ADDR_B0 + x"04"; + -- Bloc d'IO2 + constant A_IO2_REG_DATA : T_ADDRESS := START_ADDR_B0 + x"05"; + constant A_IO2_REG_DIRECTION : T_ADDRESS := START_ADDR_B0 + x"06"; + constant A_IO2_REG_INTERRUPT_MASK : T_ADDRESS := START_ADDR_B0 + x"07"; + constant A_IO2_READ_OUTPUT : T_ADDRESS := START_ADDR_B0 + x"08"; + -- Bloc port série + -- Bloc caméra + -- Bloc PWM + -- Bloc I²C + -- Bloc servo-moteurs +end nono_const; diff --git a/2004/n/fpga/src/fpga/rxserie.vhd b/2004/n/fpga/src/fpga/rxserie.vhd new file mode 100644 index 0000000..a26b365 --- /dev/null +++ b/2004/n/fpga/src/fpga/rxserie.vhd @@ -0,0 +1,254 @@ +-- ------------------------------------------- +-- Port série RX pour le fpga robot +-- ------------------------------------------- +-- +-- * Prend 3 adresses mémoire : +-- 0 - Rxdata +-- 1 - Flag : (x ! x ! FNE ! FFull ! FL3 ! FL2 ! FL1 ! FL0 ) +-- 2 - Config : (x ! x ! x ! On/Off ! FNEIF ! FFIF ! BdR1 ! BdR0) +-- * Mettre le bit On/Off à 1 pour activer la reception +-- * Chaque lecture dans rxdata dépile la donnée de la fifo +-- * Dès que le registre à décalage est plein, il empile la donnée dans la +-- fifo. +-- * Deux bits de stop +-- * Quand la fifo est pleine, met le flag FifoFull (FF) à 1. Chaque front +-- montant du flag FF met à 1 le flag d'interruption FFIF et génère une +-- interruption. Il faut alors mettre à 0 FFIF, qui sera remis à 1 au +-- prochain front montant de FF +-- * Quand il y a au moins une donnée dans la pile, le bit FifiNonEmpty (FNE) +-- est à 1. Quand FNE passe de 0 à 1, le flag FNEIF passe à 1 et génère une +-- interruption. Il faut alors mettre à 0 FNEIF, qui repassera à 1 au +-- prochain front montant de FNE +-- * On peut lire l'état de la pile dans le registre de flags (FifoLevel1/0) +-- * Baudrate disponible : +-- BdR1/0 ! Baudrate +-- 00 ! 9600 +-- 01 ! 19200 +-- 10 ! 57600 +-- 11 ! 115200 + + +-- Config : (x ! x ! EIEn ! On/Off ! DRIEn ! FFIEn ! BdR1 ! BdR0) +-- Flag : (x ! PErr ! FErr ! OErr ! Empty ! Full ! FLI1 ! FLI0 ) + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +use work.nono_const.all; + +entity rxserie is + port ( + rst : in std_logic; + bus_clk : in std_logic; + rw : in std_logic; -- read (0) / write (1) + bus_data : inout T_DATA; + clk: in std_logic; + clk_ref: in std_logic; + rxin: in std_logic; + irqFIFO: out std_logic; + irqRX: out std_logic; + irqERR: out std_logic; + csData : in std_logic; + csConfig : in std_logic; + csFlag : in std_logic + ); +end rxserie; + +architecture rtl of rxserie is +-- composants +component clockgene + port( + rst: in std_logic; + ckin: in std_logic; + ckout: out std_logic; + param: in std_logic_vector(1 downto 0) + ); +end component; + +component regIO + port( + cs: in std_logic; + bus_data: inout T_DATA; + input: in T_DATA; + output: out T_DATA; + rw: in std_logic; + load: in std_logic; + ck: in std_logic; + rst: in std_logic); +end component; + +component fifodriver + port( + clk: in std_logic; + rst: in std_logic; + readreq: in std_logic; + writereq: in std_logic; + din: IN std_logic_VECTOR(7 downto 0); + dout: OUT std_logic_VECTOR(7 downto 0); + dready: out std_logic; + full: OUT std_logic; + empty: OUT std_logic; + data_count: OUT std_logic_VECTOR(1 downto 0)); +END COMPONENT; + +component RXCVER + port ( + MCLKX16 : in std_logic; -- input clock, 16x baudrate clock used for synchronization + READ : in std_logic; -- Read Strobe + RX : in std_logic; -- Receive Input Line + RESET : in std_logic; -- Global Reset + RXRDY : out std_logic; -- Receiver data ready to read + PARITY_ERR : out std_logic; -- Receiver parity error flag + FRAMING_ERR : out std_logic; -- Receiver framing error flag + OVERRUN : out std_logic; -- Receiver overrun error flag + DATA : out std_logic_vector(7 downto 0) -- 8 bit output data bus + ); +end component; + + +-- signaux +signal rxready:std_logic; -- Receiver data ready to read +signal rxread:std_logic; +signal rxparERR:std_logic:='0'; -- Receiver parity error flag +signal rxfrmERR:std_logic:='0'; -- Receiver framing error flag +signal rxovrrERR:std_logic:='0'; -- Receiver overrun error flag + +signal rxck: std_logic; +signal geneck:std_logic; + +signal fifoEmpty: std_logic; +signal fifoFull: std_logic; +signal fifoLevel: std_logic_vector(1 downto 0); +signal fifopurge: std_logic:='0'; +signal fifockin: std_logic; +signal fifockout: std_logic; +signal fifodready: std_logic; + +signal confreg: T_DATA:="00000000"; +signal flagreg: T_DATA:="00000000"; +signal inter_data: T_DATA; +signal inter_bus: T_DATA; +signal inter_fifo: T_DATA; + +signal state_rx_read:integer:=0; + +signal dummy : T_DATA :=(others =>'0'); +signal un: std_logic :='1'; + + +begin +CLOCK1 : clockgene +port map( + rst => rst, + ckin=>geneck, + ckout=>rxck, + param=>confreg(1 downto 0)); + +FIFO1: fifodriver port map( + clk => clk, + rst => fifopurge, + readreq => fifockout, + writereq => fifockin, + din => inter_data, + dout => inter_fifo, + dready => fifodready, + full => fifoFull, + empty => fifoEmpty, + data_count => fifoLevel(1 downto 0)); + +-- Config : (x ! x ! EIEn ! On/Off ! DRIEn ! FFIEn ! BdR1 ! BdR0) +RCONF : regIO port map( + cs=>csConfig, + bus_data=>bus_data, + input=>dummy, + output=>confreg, + rw=>rw, + load=>dummy(0), + ck=>bus_clk, + rst=>rst); + +-- Flag : (x ! PErr ! FErr ! OErr ! Empty ! Full ! FLI1 ! FLI0 ) +RFLAG : regIO port map( + cs=>csFlag, + bus_data=>bus_data, + input=>flagreg, + output=>open, + rw=>rw, + load=>un, + ck=>bus_clk, + rst=>rst); + +RC1:RXCVER +port map( + MCLKX16 =>rxck, -- input clock, 16x baudrate clock used for synchronization + READ =>rxread, --rxread, -- Read Strobe + RX =>rxin, -- Receive Input Line + RESET =>rst, -- Global Reset + RXRDY =>rxready, -- Receiver data ready to read + PARITY_ERR =>rxparERR, -- Receiver parity error flag + FRAMING_ERR =>rxfrmERR, -- Receiver framing error flag + OVERRUN =>rxovrrERR, -- Receiver overrun error flag + DATA =>inter_data -- 8 bit output data bus + ); + + +-- config +geneck <= (confreg(4) and clk_ref); -- On/Off et clk_ref --confreg(4) +fifopurge<=rst; + +-- flags +flagreg(1 downto 0) <= fifoLevel(1 downto 0); +flagreg(2) <= fifoFull; +flagreg(3) <= fifoEmpty; +flagreg(4) <= rxparERR; -- Receiver parity error flag +flagreg(5) <= rxfrmERR; -- Receiver framing error flag +flagreg(6) <= rxovrrERR; -- Receiver overrun error flag + + +-- controle des flux +fifockout <= (csData and bus_clk and rw and (not rst)); +fifockin <= ((not rxread) and (not fifoFull)); + +inter_bus <= inter_fifo when (fifockout='1') else (others => 'Z'); + +bus_data <= inter_bus; + +-- irq +irqFifo <= (fifoLevel(1) and fifoLevel(0));-- and confreg(2); --fifo almost full AND Int/En +irqRx <= (not fifoEmpty);-- and confreg(3); +irqErr <= (rxparERR or rxovrrERR or rxfrmERR or fifoFull);-- and confreg(5); + +-- sortie de donnée du récepteur +process(rxck) +begin + if(rxck'event and rxck='1') then + rxread<='1'; + case state_rx_read is + when 0 => if(rxready='1') then + state_rx_read<=1; + end if; + when 1 => state_rx_read<=2; + when 2 => rxread<='0'; + state_rx_read<=3; + when 3 => if(rxready='0') then + state_rx_read<=0; + end if; + when others => null; + end case; + end if; +end process; + +end rtl; + + + + + + + + + + diff --git a/2004/n/fpga/src/fpga/sfifo.xco b/2004/n/fpga/src/fpga/sfifo.xco new file mode 100644 index 0000000..1b1ff61 --- /dev/null +++ b/2004/n/fpga/src/fpga/sfifo.xco @@ -0,0 +1,41 @@ +# Xilinx CORE Generator 6.1.03i +# Username = Administrateur +# COREGenPath = D:\xilinx\coregen +# ProjectPath = D:\vhdl\robot\carte_fpga\src\fpga +# ExpandedProjectPath = D:\vhdl\robot\carte_fpga\src\fpga +# OverwriteFiles = true +# Core name: sfifo +# Number of Primitives in design: 87 +# Number of CLBs used in design cannot be determined when there is no RPMed logic +# Number of Slices used in design cannot be determined when there is no RPMed logic +# Number of LUT sites used in design: 43 +# Number of LUTs used in design: 35 +# Number of REG used in design: 22 +# Number of SRL16s used in design: 8 +# Number of Distributed RAM primitives used in design: 0 +# Number of Block Memories used in design: 0 +# Number of Dedicated Multipliers used in design: 0 +# Number of HU_SETs used: 0 +# +SET BusFormat = BusFormatAngleBracketNotRipped +SET XilinxFamily = Spartan2 +SET OutputOption = OutputProducts +SET FlowVendor = Foundation_iSE +SET FormalVerification = None +SET OutputProducts = ImpNetlist ASYSymbol VHDLSim VerilogSim +SELECT Synchronous_FIFO Spartan2 Xilinx,_Inc. 4.0 +CSET data_width = 8 +CSET read_error_sense = Active_Low +CSET read_error_flag = true +CSET write_acknowledge_flag = true +CSET write_error_flag = true +CSET data_count = true +CSET memory_type = Distributed_Memory +CSET read_acknowledge_sense = Active_Low +CSET component_name = sfifo +CSET fifo_depth = 16 +CSET read_acknowledge_flag = true +CSET data_count_width = 2 +CSET write_error_sense = Active_Low +CSET write_acknowledge_sense = Active_Low +GENERATE diff --git a/2004/n/fpga/src/modele/nono_const.vhd b/2004/n/fpga/src/modele/nono_const.vhd index 82ad0d5..f784cb4 100644 --- a/2004/n/fpga/src/modele/nono_const.vhd +++ b/2004/n/fpga/src/modele/nono_const.vhd @@ -12,7 +12,8 @@ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; - + +use work.isa_const.all; -- Constantes relatives package nono_const is @@ -22,9 +23,12 @@ package nono_const is constant CK_PERIOD : time := 30 ns; -- diviseur pour le clockgene des ports série. + -- Pour 1.8432MHz, avec 1 de diviseur, on a 0% + constant DIVIS_CK_SERIAL :integer := 1; + -- Pour 33,33MHz, et avec 18 de diviseur, on obtient -- une erreur sur le baudrate de 0.46% - constant DIVIS_CK_SERIAL :integer := 18; + -- Taille d'une addresse sur la carte -- RQ : 10 = nb suffisant diff --git a/2004/n/fpga/src/portserie/clockgene/clockgene.vhd b/2004/n/fpga/src/portserie/clockgene/clockgene.vhd index b98a6b3..554d561 100644 --- a/2004/n/fpga/src/portserie/clockgene/clockgene.vhd +++ b/2004/n/fpga/src/portserie/clockgene/clockgene.vhd @@ -9,8 +9,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; use work.nono_const.all; -- pour la valeur de DIVIS_CK_SERIAL @@ -31,9 +30,8 @@ port( ); end clockgene; - architecture rtl of clockgene is -signal compteur:std_logic_vector(10 downto 0):=(others=>'0'); +signal compteur:std_logic_vector(9 downto 0):="0000000000"; signal div_param:integer; -- le diviseur paramétrable signal clr:std_logic; @@ -48,7 +46,7 @@ begin when "01" => div_param <= (DIVIS_CK_SERIAL*6); -- 19200 * 6 =115200 when "10" => div_param <= (DIVIS_CK_SERIAL*2); -- 57600 * 2 =115200 when "11" => div_param <= DIVIS_CK_SERIAL; -- 115200 * 1=115200 - when others => null; + when others => div_param <= (DIVIS_CK_SERIAL*12); -- 9600 * 12 =115200 end case; end process; @@ -57,13 +55,13 @@ begin begin if(clr='1') then ckout<='0'; - compteur<=(others=>'0'); + compteur<=conv_std_logic_vector(div_param, 10); elsif(ckin'event and ckin='1') then - if(compteur = div_param) then + if(compteur = "0000000000") then ckout<='1'; - compteur<=(others=>'0'); + compteur<=conv_std_logic_vector(div_param, 10); else - compteur <= compteur + 1; + compteur <= conv_std_logic_vector( (unsigned(compteur) - 1),10); ckout<='0'; end if; end if; diff --git a/2004/n/fpga/src/portserie/fifo/bch_fifodriver.vhd b/2004/n/fpga/src/portserie/fifo/bch_fifodriver.vhd index a109693..94fa9a2 100644 --- a/2004/n/fpga/src/portserie/fifo/bch_fifodriver.vhd +++ b/2004/n/fpga/src/portserie/fifo/bch_fifodriver.vhd @@ -41,7 +41,7 @@ signal data_count: std_logic_VECTOR(1 downto 0); BEGIN -Inst_fifodriver: fifodriver PORT MAP( +uut: fifodriver PORT MAP( clk => clk, rst => rst, readreq => readreq, @@ -55,11 +55,11 @@ Inst_fifodriver: fifodriver PORT MAP( ); - din <= std_logic_vector(unsigned(din) + 1) after 8 ns; - rst<='1' , '0' after 10 ns; - clk <= not clk after 1 ns; - writereq <= not writereq after 13 ns; - readreq <= not readreq after 17 ns; + din <= std_logic_vector(unsigned(din) + 1) after 400 ns; + rst<='1' , '0' after 510 ns; + clk <= not clk after 25 ns; + writereq <= not writereq after 700 ns; + readreq <= not readreq after 900 ns; diff --git a/2004/n/fpga/src/portserie/fifo/bch_sfifo.vhd b/2004/n/fpga/src/portserie/fifo/bch_sfifo.vhd index a3d930d..68b409f 100644 --- a/2004/n/fpga/src/portserie/fifo/bch_sfifo.vhd +++ b/2004/n/fpga/src/portserie/fifo/bch_sfifo.vhd @@ -44,7 +44,7 @@ signal wr_err: std_logic; -- Component Instantiation -U0 : sfifo +uut : sfifo port map ( clk => clk, sinit => sinit, @@ -60,11 +60,9 @@ U0 : sfifo wr_err => wr_err, data_count => data_count); - - din <= std_logic_vector(unsigned(din) + 1) after 8 ns; sinit <= '1' , '0' after 10 ns; clk <= not clk after 3 ns; rd_en <= '0' , '1' after 50 ns; - END; + END behavior; diff --git a/2004/n/fpga/src/portserie/fifo/fifo.npl b/2004/n/fpga/src/portserie/fifo/fifo.npl index c8ba229..81fdd87 100644 --- a/2004/n/fpga/src/portserie/fifo/fifo.npl +++ b/2004/n/fpga/src/portserie/fifo/fifo.npl @@ -20,13 +20,16 @@ DEVGENERATEDSIMULATIONMODEL VHDL GENERATEDSIMULATIONMODELTIME 0 STIMULUS bch_afifo.vhd SOURCE fifodriver.vhd -STIMULUS bch_fifodriver.vhd SOURCE ..\..\modele\nono_const.vhd -SOURCE sfifo.xco STIMULUS bch_sfifo.vhd +SOURCE sfifo.xco +STIMULUS bch_fifodriver.vhd [Normal] p_CompxlibTargetSimulator=xstvhd, spartan2, Design.t_compLibraries, 1078952453, ModelSim SE [STATUS-ALL] -bch_fifodriver.vhd.testbenchRpt=ERRORS,0 +fifodriver.ngcFile=WARNINGS,1079734309 +fifodriver.ngdFile=WARNINGS,1079734329 +fifodriver.postMapVHDLSimModel=WARNINGS,1079734429 +sfifo.ngcFile=ERRORS,0 [STRATEGY-LIST] Normal=True diff --git a/2004/n/fpga/src/portserie/fifo/fifodriver.vhd b/2004/n/fpga/src/portserie/fifo/fifodriver.vhd index 3830e93..11d1955 100644 --- a/2004/n/fpga/src/portserie/fifo/fifodriver.vhd +++ b/2004/n/fpga/src/portserie/fifo/fifodriver.vhd @@ -61,7 +61,7 @@ signal wr_err:std_logic; begin -- Component Instantiation -U0 : sfifo +fifo0 : sfifo port map ( clk => clk, sinit => rst, diff --git a/2004/n/fpga/src/portserie/fifo/sfifo.xco b/2004/n/fpga/src/portserie/fifo/sfifo.xco index 306f531..236a635 100644 --- a/2004/n/fpga/src/portserie/fifo/sfifo.xco +++ b/2004/n/fpga/src/portserie/fifo/sfifo.xco @@ -5,13 +5,13 @@ # ExpandedProjectPath = D:\vhdl\robot\carte_fpga\src\portserie\fifo # OverwriteFiles = true # Core name: sfifo -# Number of Primitives in design: 120 +# Number of Primitives in design: 87 # Number of CLBs used in design cannot be determined when there is no RPMed logic # Number of Slices used in design cannot be determined when there is no RPMed logic -# Number of LUT sites used in design: 70 -# Number of LUTs used in design: 46 -# Number of REG used in design: 24 -# Number of SRL16s used in design: 24 +# Number of LUT sites used in design: 43 +# Number of LUTs used in design: 35 +# Number of REG used in design: 22 +# Number of SRL16s used in design: 8 # Number of Distributed RAM primitives used in design: 0 # Number of Block Memories used in design: 0 # Number of Dedicated Multipliers used in design: 0 @@ -25,18 +25,18 @@ SET FormalVerification = None SET OutputProducts = ImpNetlist ASYSymbol VHDLSim VerilogSim SELECT Synchronous_FIFO Spartan2 Xilinx,_Inc. 4.0 CSET data_width = 8 -CSET read_error_sense = active_high +CSET read_error_sense = Active_Low CSET read_error_flag = true CSET write_acknowledge_flag = true CSET write_error_flag = true CSET data_count = true CSET memory_type = Distributed_Memory -CSET read_acknowledge_sense = active_high +CSET read_acknowledge_sense = Active_Low CSET component_name = sfifo -CSET fifo_depth = 32 +CSET fifo_depth = 16 CSET read_acknowledge_flag = true CSET data_count_width = 2 -CSET write_error_sense = active_high -CSET write_acknowledge_sense = active_high +CSET write_error_sense = Active_Low +CSET write_acknowledge_sense = Active_Low GENERATE diff --git a/2004/n/fpga/src/portserie/portserie/bch_txserie.vhd b/2004/n/fpga/src/portserie/portserie/bch_txserie.vhd index 3400854..25fadff 100644 --- a/2004/n/fpga/src/portserie/portserie/bch_txserie.vhd +++ b/2004/n/fpga/src/portserie/portserie/bch_txserie.vhd @@ -22,6 +22,7 @@ component txserie rw : in std_logic; -- read (0) / write (1) bus_data : inout T_DATA:=(others => 'Z'); clk: in std_logic; + clk_ref: in std_logic; txout: out std_logic; minIRQ: out std_logic; csData : in std_logic; @@ -35,6 +36,7 @@ end component; signal simclk:std_logic:='0'; signal rst : std_logic; signal clk : std_logic; +signal clk_ref : std_logic:='0'; signal rw : std_logic; signal bus_data : T_DATA:=(others => 'Z'); signal masterck: std_logic:='0'; @@ -44,18 +46,19 @@ signal csData : std_logic; signal csConfig : std_logic; signal csFlag : std_logic; -signal state:integer:=-3; +signal state:integer:=-30; begin - U1 : txserie + UUT : txserie port map( rst => rst, bus_clk => clk, rw =>rw, bus_data => bus_data, clk => masterck, + clk_ref => clk_ref, txout => txout, minIRQ => minirq, csData => csData, @@ -66,6 +69,7 @@ begin rst<='1','0' after 5 ns; simclk<= not simclk after 10 ns; masterck<= not masterck after 3 ns; + clk_ref <= not clk_ref after 10 ns; combi:process(state) begin @@ -77,10 +81,10 @@ begin csFlag <= '0'; case state is - when 1 => bus_data<="00010110"; + when 1 => bus_data<="01110111"; csConfig<='1'; rw<='0'; - when 2 => bus_data<="00010110"; + when 2 => bus_data<="01110111"; csConfig<='1'; rw<='0'; clk<='1'; diff --git a/2004/n/fpga/src/portserie/portserie/portserie.npl b/2004/n/fpga/src/portserie/portserie/portserie.npl index 1743fbf..b293bd4 100644 --- a/2004/n/fpga/src/portserie/portserie/portserie.npl +++ b/2004/n/fpga/src/portserie/portserie/portserie.npl @@ -30,7 +30,9 @@ SOURCE ..\fifo\sfifo.xco STIMULUS bch_txmit.vhd STIMULUS ..\fifo\bch_fifodriver.vhd SOURCE ..\clockgene\clockgene.vhd +STIMULUS bch_clockgene.vhd [Normal] +p_CompxlibOutputDir=xstvhd, spartan2, Design.t_compLibraries, 1079779592, D:\xilinx\vhdl\src p_CompxlibTargetSimulator=xstvhd, spartan2, Design.t_compLibraries, 1078871494, ModelSim SE [STRATEGY-LIST] Normal=True diff --git a/2004/n/fpga/src/portserie/portserie/sfifo.xco b/2004/n/fpga/src/portserie/portserie/sfifo.xco index a2badbd..cc7276e 100644 --- a/2004/n/fpga/src/portserie/portserie/sfifo.xco +++ b/2004/n/fpga/src/portserie/portserie/sfifo.xco @@ -18,11 +18,12 @@ # Number of HU_SETs used: 0 # SET BusFormat = BusFormatAngleBracketNotRipped +SET SimulationOutputProducts = VHDL SET XilinxFamily = Spartan2 -SET OutputOption = OutputProducts +SET OutputOption = DesignFlow +SET DesignFlow = VHDL SET FlowVendor = Foundation_iSE SET FormalVerification = None -SET OutputProducts = ImpNetlist ASYSymbol VHDLSim VerilogSim SELECT Synchronous_FIFO Spartan2 Xilinx,_Inc. 4.0 CSET data_width = 8 CSET read_error_sense = Active_Low diff --git a/2004/n/fpga/src/portserie/portserie/txserie.vhd b/2004/n/fpga/src/portserie/portserie/txserie.vhd index b1ceb53..2b94529 100644 --- a/2004/n/fpga/src/portserie/portserie/txserie.vhd +++ b/2004/n/fpga/src/portserie/portserie/txserie.vhd @@ -46,6 +46,7 @@ entity txserie is rw : in std_logic; -- read (0) / write (1) bus_data : inout T_DATA:=(others => 'Z'); clk: in std_logic; + clk_ref: in std_logic; txout: out std_logic; minIRQ: out std_logic; csData : in std_logic; @@ -115,16 +116,15 @@ signal txck: std_logic; signal geneck:std_logic; signal txload: std_logic:='0'; -signal loadingtx: std_logic:='0'; signal confreg: T_DATA:="00000000"; signal flagreg: T_DATA:="00000000"; signal inter_data: T_DATA; -signal inter_fifo_bus: T_DATA; +--signal inter_fifo_bus: T_DATA; signal txready: std_logic:='1'; signal fifodready :std_logic; -signal state:integer:=1; -signal state_next:integer:=1; +--signal state:integer:=1; +--signal state_next:integer:=1; signal state_txload:integer:=0; signal dummy : T_DATA :=(others =>'0'); @@ -135,7 +135,7 @@ signal un: std_logic :='1'; begin CLOCK1 : clockgene port map( rst => rst, - ckin=>geneck, + ckin=>clk_ref,--geneck, ckout=>txck, param=>confreg(1 downto 0)); @@ -185,7 +185,7 @@ RFLAG : regIO port map( -- signaux -- config -geneck <= (confreg(4) and clk); -- On/Off et masterck +geneck <= (clk_ref);-- and confreg(4); -- On/Off et masterck fifopurge <= '1' when (rst='1') else confreg(3); -- reset or purge -- flags @@ -208,22 +208,29 @@ begin state_txload <= 3; elsif(fifodready='1') then state_txload <= 1; + else + state_txload <= 0; end if; when 1 => if(txready='1') then state_txload <= 2; txload <= '1'; + else + state_txload <= 1; end if; when 2 => if(txready='0') then state_txload <= 0; else txload <= '1'; + state_txload <= 2; end if; when 3 => if(fifodready='1') then state_txload <= 2; txload <= '1'; + else + state_txload <= 3; end if; - when others => null; + when others => state_txload <= 0; end case; end process; diff --git a/2004/n/fpga/src/portserie/rxserie/bch_rxserie.vhd b/2004/n/fpga/src/portserie/rxserie/bch_rxserie.vhd index ec71a5c..b575b9d 100644 --- a/2004/n/fpga/src/portserie/rxserie/bch_rxserie.vhd +++ b/2004/n/fpga/src/portserie/rxserie/bch_rxserie.vhd @@ -20,14 +20,15 @@ use work.isa_const.all; rw : in std_logic; -- read (0) / write (1) bus_data : inout T_DATA; clk: in std_logic; + clk_ref: in std_logic; rxin: in std_logic; irqFIFO: out std_logic; irqRX: out std_logic; + irqERR: out std_logic; csData : in std_logic; csConfig : in std_logic; csFlag : in std_logic); END COMPONENT; - signal rst: std_logic; @@ -36,9 +37,11 @@ signal rw: std_logic; signal bus_data: T_DATA; signal data_received: T_DATA; signal clk: std_logic:='0'; +signal clk_ref: std_logic:='0'; signal rxin: std_logic:='1'; signal irqFIFO: std_logic; signal irqRX: std_logic; +signal irqERR: std_logic; signal csData: std_logic; signal csConfig: std_logic; signal csFlag: std_logic; @@ -47,34 +50,35 @@ signal csFlag: std_logic; BEGIN - Inst_rxserie: rxserie PORT MAP( + uut: rxserie PORT MAP( rst => rst, bus_clk => bus_clk, rw => rw, bus_data => bus_data, clk => clk, + clk_ref => clk_ref, rxin => rxin, irqFIFO => irqFIFO, irqRX => irqRX, + irqERR => irqERR, csData => csData, csConfig => csConfig, csFlag => csFlag ); --- baudrate/(16*2) used to generate half clock cycle; +-- master clock clk <= (Not clk) after (CK_PERIOD/2); -- Reset Uart rst <= '1','0' after (10*CK_PERIOD); --- feeding back output from transmitter to the input of receiver -rxin <= not rxin after 12 us; +-- baudrate/(16*2) used to generate half clock cycle; +clk_ref <= (not clk_ref) after 135 ns; --1,8432MHz +-- feeding back output from transmitter to the input of receiver +rxin <= not rxin after 15751 ns; --- csData => csData, --- csConfig => csConfig, --- csFlag => csFlag check:process @@ -124,12 +128,12 @@ begin csData<='1'; read_bus; - WAIT FOR 10 us; + WAIT FOR 100 us; csFlag<='1'; read_bus; - WAIT FOR 10 us; + WAIT FOR 100 us; end process; END; diff --git a/2004/n/fpga/src/portserie/rxserie/rxserie.npl b/2004/n/fpga/src/portserie/rxserie/rxserie.npl index 597ac7c..a400a08 100644 --- a/2004/n/fpga/src/portserie/rxserie/rxserie.npl +++ b/2004/n/fpga/src/portserie/rxserie/rxserie.npl @@ -29,10 +29,20 @@ SOURCE sfifo.xco STIMULUS bch_rxserie.vhd SOURCE ..\..\modele\nono_const.vhd SOURCE ..\..\modele\isa_const.vhd +STIMULUS ..\..\registre\test_reg.vhd [Normal] +p_CompxlibOutputDir=xstvhd, spartan2, Design.t_compLibraries, 1079483024, D:\xilinx\vhdl\src p_CompxlibTargetSimulator=xstvhd, spartan2, Design.t_compLibraries, 1079088462, ModelSim SE +p_ModelSimListWin=xstvhd, spartan2, VHDL Test Bench.t_MSimulatePostTranslateVhdlModel, 1079738242, False +p_ModelSimProcWin=xstvhd, spartan2, VHDL Test Bench.t_MSimulatePostTranslateVhdlModel, 1079738242, False +p_ModelSimSimRunTime_tb=xstvhd, spartan2, VHDL Test Bench.t_MSimulatePostTranslateVhdlModel, 1080007098, 1000us +p_ModelSimSourceWin=xstvhd, spartan2, VHDL Test Bench.t_MSimulatePostTranslateVhdlModel, 1079738242, False +p_ModelSimUutInstName_postPar=xstvhd, spartan2, VHDL Test Bench.t_MSimulatePostPlace&RouteVhdlModel, 1079653969, UUT +p_ModelSimVarsWin=xstvhd, spartan2, VHDL Test Bench.t_MSimulatePostTranslateVhdlModel, 1079738242, False +_VhdlSimDo_post=xstvhd, spartan2, VHDL Test Bench.t_MSimulatePostTranslateVhdlModel, 1079736489, True [STATUS-ALL] -rxserie.ngcFile=WARNINGS,1079226990 -rxserie.ngdFile=WARNINGS,1079300826 +rxserie.ngcFile=WARNINGS,1080007519 +rxserie.ngdFile=WARNINGS,1080007524 +rxserie.postMapVHDLSimModel=WARNINGS,1080007527 [STRATEGY-LIST] Normal=True diff --git a/2004/n/fpga/src/portserie/rxserie/rxserie.vhd b/2004/n/fpga/src/portserie/rxserie/rxserie.vhd index 1ee58ec..e0ec325 100644 --- a/2004/n/fpga/src/portserie/rxserie/rxserie.vhd +++ b/2004/n/fpga/src/portserie/rxserie/rxserie.vhd @@ -46,6 +46,7 @@ entity rxserie is rw : in std_logic; -- read (0) / write (1) bus_data : inout T_DATA; clk: in std_logic; + clk_ref: in std_logic; rxin: in std_logic; irqFIFO: out std_logic; irqRX: out std_logic; @@ -110,7 +111,7 @@ end component; -- signaux signal rxready:std_logic; -- Receiver data ready to read -signal rxread:std_logic; +signal rxread:std_logic:='0'; signal rxparERR:std_logic:='0'; -- Receiver parity error flag signal rxfrmERR:std_logic:='0'; -- Receiver framing error flag signal rxovrrERR:std_logic:='0'; -- Receiver overrun error flag @@ -195,7 +196,7 @@ port map( -- config -geneck <= (confreg(4) and clk); -- On/Off et masterck --confreg(4) +geneck <= (confreg(4) and clk_ref); -- On/Off et clk_ref --confreg(4) fifopurge<=rst; -- flags @@ -208,7 +209,7 @@ flagreg(6) <= rxovrrERR; -- Receiver overrun error flag -- controle des flux -fifockout <= (csData and bus_clk and rw and (not rst)); +fifockout <= '1' when (csData='1' and rw='1' and rst='0') else '0'; fifockin <= ((not rxread) and (not fifoFull)); inter_bus <= inter_fifo when (fifockout='1') else (others => 'Z'); @@ -216,9 +217,9 @@ inter_bus <= inter_fifo when (fifockout='1') else (others => 'Z'); bus_data <= inter_bus; -- irq -irqFifo <= (fifoLevel(1) and fifoLevel(0)) and confreg(2); --fifo almost full AND Int/En -irqRx <= (not fifoEmpty) and confreg(3); -irqErr <= (rxparERR or rxovrrERR or rxfrmERR or fifoFull) and confreg(5); +irqFifo <= (fifoLevel(1) and fifoLevel(0));-- and confreg(2); --fifo almost full AND Int/En +irqRx <= (not fifoEmpty);-- and confreg(3); +irqErr <= (rxparERR or rxovrrERR or rxfrmERR or fifoFull);-- and confreg(5); -- sortie de donnée du récepteur process(rxck) diff --git a/2004/n/fpga/src/portserie/rxserie/sfifo.xco b/2004/n/fpga/src/portserie/rxserie/sfifo.xco index afcd6a7..61a5042 100644 --- a/2004/n/fpga/src/portserie/rxserie/sfifo.xco +++ b/2004/n/fpga/src/portserie/rxserie/sfifo.xco @@ -25,18 +25,17 @@ SET FormalVerification = None SET OutputProducts = ImpNetlist ASYSymbol VHDLSim VerilogSim SELECT Synchronous_FIFO Spartan2 Xilinx,_Inc. 4.0 CSET data_width = 8 -CSET read_error_sense = active_high +CSET read_error_sense = Active_Low CSET read_error_flag = true CSET write_acknowledge_flag = true CSET write_error_flag = true CSET data_count = true CSET memory_type = Distributed_Memory -CSET read_acknowledge_sense = active_high +CSET read_acknowledge_sense = Active_Low CSET component_name = sfifo CSET fifo_depth = 16 CSET read_acknowledge_flag = true CSET data_count_width = 2 -CSET write_error_sense = active_high -CSET write_acknowledge_sense = active_high +CSET write_error_sense = Active_Low +CSET write_acknowledge_sense = Active_Low GENERATE - diff --git a/2004/n/fpga/src/portserie/uart/txmit.vhd b/2004/n/fpga/src/portserie/uart/txmit.vhd index 0088729..76bfbf8 100644 --- a/2004/n/fpga/src/portserie/uart/txmit.vhd +++ b/2004/n/fpga/src/portserie/uart/txmit.vhd @@ -7,10 +7,10 @@ entity TXMIT is MCLKX16 : in std_logic; WRITE : in std_logic; RESET : in std_logic; - DATA : in std_logic_vector(7 downto 0); + DATA : in std_logic_vector(7 downto 0); - TX : out std_logic; - TXRDY : out std_logic + TX : out std_logic; + TXRDY : out std_logic ); end TXMIT; @@ -45,10 +45,12 @@ begin TXDONE <= not (TAG2 or TAG1 or TSR(7) or TSR(6) or TSR(5) or TSR(4) or TSR(3) or TSR(2) or TSR(1) or TSR(0)); + +-- *** AJOUT *** + -- Ready for new date to be written, when no data is in transmit hold register. +-- (ajout :) et quand la transmission est finie ! - -- Ready for new date to be written, when no data is in transmit hold register. - - TXRDY <= not TXDATARDY; + TXRDY <= TXDONE and not TXDATARDY; -- Latch data[7:0] into the transmit hold register at posedge of write. -- cgit v1.2.3