From 9af50d6e5cf0681b276438acfd92c9975290f1b2 Mon Sep 17 00:00:00 2001 From: Ken Sarkies Date: Fri, 31 Aug 2012 21:47:30 +0930 Subject: STM32F1xx Additional minor changes to adc.h and adc.c --- include/libopencm3/stm32/f1/adc.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'include/libopencm3') diff --git a/include/libopencm3/stm32/f1/adc.h b/include/libopencm3/stm32/f1/adc.h index 64865f4..5a3fd20 100644 --- a/include/libopencm3/stm32/f1/adc.h +++ b/include/libopencm3/stm32/f1/adc.h @@ -187,9 +187,9 @@ LGPL License Terms @ref lgpl_license #define ADC_CHANNEL15 0x0F #define ADC_CHANNEL16 0x10 #define ADC_CHANNEL17 0x11 +/**@}*/ #define ADC_MASK 0x1F #define ADC_SHIFT 0 -/**@}*/ /* --- ADC_SR values ------------------------------------------------------- */ @@ -248,9 +248,9 @@ LGPL License Terms @ref lgpl_license #define ADC_CR1_DUALMOD_SIM (0x8 << 16) /** Alternate trigger mode only. */ #define ADC_CR1_DUALMOD_ATM (0x9 << 16) +/**@}*/ #define ADC_CR1_DUALMOD_MASK (0xF << 16) #define ADC_CR1_DUALMOD_SHIFT 16 -/**@}*/ /* DISCNUM[2:0]: Discontinous mode channel count. */ /****************************************************************************/ @@ -266,9 +266,9 @@ LGPL License Terms @ref lgpl_license #define ADC_CR1_DISCNUM_6CHANNELS (0x5 << 13) #define ADC_CR1_DISCNUM_7CHANNELS (0x6 << 13) #define ADC_CR1_DISCNUM_8CHANNELS (0x7 << 13) +/**@}*/ #define ADC_CR1_DISCNUM_MASK (0x7 << 13) #define ADC_CR1_DISCNUM_SHIFT 13 -/**@}*/ /* JDISCEN: */ /** Discontinous mode on injected channels. */ #define ADC_CR1_JDISCEN (1 << 12) @@ -325,9 +325,9 @@ LGPL License Terms @ref lgpl_license #define ADC_CR1_AWDCH_CHANNEL15 (0x0F << 0) #define ADC_CR1_AWDCH_CHANNEL16 (0x10 << 0) #define ADC_CR1_AWDCH_CHANNEL17 (0x11 << 0) +/**@}*/ #define ADC_CR1_AWDCH_MASK (0x1F << 0) #define ADC_CR1_AWDCH_SHIFT 0 -/**@}*/ /* --- ADC_CR2 values ------------------------------------------------------ */ -- cgit v1.2.3