From 6ee8e44bd7743806eeb1ba0983fd1113c519f71c Mon Sep 17 00:00:00 2001 From: Ken Sarkies Date: Wed, 10 Oct 2012 21:31:31 +1030 Subject: Initial documentation for stm32/usart.c, usart.h Some minor documentation corrections to timer.h --- include/libopencm3/stm32/timer.h | 26 +++++++------- include/libopencm3/stm32/usart.h | 77 ++++++++++++++++++++++++++++++++++------ 2 files changed, 79 insertions(+), 24 deletions(-) (limited to 'include/libopencm3/stm32') diff --git a/include/libopencm3/stm32/timer.h b/include/libopencm3/stm32/timer.h index 61d40e9..4977674 100644 --- a/include/libopencm3/stm32/timer.h +++ b/include/libopencm3/stm32/timer.h @@ -1,6 +1,6 @@ /** @defgroup STM32F_tim_defines Timers Defines -@brief libopencm3 Defined Constants and Types for the STM32F1xx Timers +@brief libopencm3 Defined Constants and Types for the STM32 Timers @ingroup STM32F_defines @@ -44,7 +44,7 @@ LGPL License Terms @ref lgpl_license /* Timer register base adresses (for convenience) */ /****************************************************************************/ /** @defgroup tim_reg_base Timer register base addresses -@ingroup STM32F1xx_tim_defines +@ingroup STM32F_tim_defines @{*/ #define TIM1 TIM1_BASE @@ -251,7 +251,7 @@ LGPL License Terms @ref lgpl_license /****************************************************************************/ /** @defgroup tim_x_cr1_cdr TIMx_CR1 CKD[1:0] Clock Division Ratio -@ingroup STM32F1xx_tim_defines +@ingroup STM32F_tim_defines @{*/ /* CKD[1:0]: Clock division */ @@ -267,7 +267,7 @@ LGPL License Terms @ref lgpl_license /* CMS[1:0]: Center-aligned mode selection */ /****************************************************************************/ /** @defgroup tim_x_cr1_cms TIMx_CR1 CMS[1:0]: Center-aligned Mode Selection -@ingroup STM32F1xx_tim_defines +@ingroup STM32F_tim_defines @{*/ #define TIM_CR1_CMS_EDGE (0x0 << 5) @@ -280,7 +280,7 @@ LGPL License Terms @ref lgpl_license /* DIR: Direction */ /****************************************************************************/ /** @defgroup tim_x_cr1_dir TIMx_CR1 DIR: Direction -@ingroup STM32F1xx_tim_defines +@ingroup STM32F_tim_defines @{*/ #define TIM_CR1_DIR_UP (0 << 4) @@ -303,7 +303,7 @@ LGPL License Terms @ref lgpl_license /****************************************************************************/ /** @defgroup tim_x_cr2_ois TIMx_CR2_OIS: Force Output Idle State Control Values -@ingroup STM32F1xx_tim_defines +@ingroup STM32F_tim_defines @{*/ /* OIS4:*//** Output idle state 4 (OC4 output) */ @@ -335,7 +335,7 @@ LGPL License Terms @ref lgpl_license /* MMS[2:0]: Master mode selection */ /****************************************************************************/ /** @defgroup tim_mastermode TIMx_CR2 MMS[6:4]: Master Mode Selection -@ingroup STM32F1xx_tim_defines +@ingroup STM32F_tim_defines @{*/ #define TIM_CR2_MMS_RESET (0x0 << 4) @@ -397,7 +397,7 @@ LGPL License Terms @ref lgpl_license /* TS[2:0]: Trigger selection */ /** @defgroup tim_ts TS Trigger selection -@ingroup STM32F1xx_tim_defines +@ingroup STM32F_tim_defines @{*/ /** Internal Trigger 0 (ITR0) */ @@ -421,7 +421,7 @@ LGPL License Terms @ref lgpl_license /* SMS[2:0]: Slave mode selection */ /** @defgroup tim_sms SMS Slave mode selection -@ingroup STM32F1xx_tim_defines +@ingroup STM32F_tim_defines @{*/ /** Slave mode disabled */ @@ -451,7 +451,7 @@ and generates an update of the registers. */ /****************************************************************************/ /** @defgroup tim_irq_enable TIMx_DIER Timer DMA and Interrupt Enable Values -@ingroup STM32F1xx_tim_defines +@ingroup STM32F_tim_defines @{*/ /* TDE:*//** Trigger DMA request enable */ @@ -503,7 +503,7 @@ and generates an update of the registers. */ /* --- TIMx_SR values ------------------------------------------------------ */ /****************************************************************************/ /** @defgroup tim_sr_values TIMx_SR Timer Status Register Flags -@ingroup STM32F1xx_tim_defines +@ingroup STM32F_tim_defines @{*/ @@ -548,7 +548,7 @@ and generates an update of the registers. */ /****************************************************************************/ /** @defgroup tim_event_gen TIMx_EGR Timer Event Generator Values -@ingroup STM32F1xx_tim_defines +@ingroup STM32F_tim_defines @{*/ @@ -908,7 +908,7 @@ and generates an update of the registers. */ /* LOCK[1:0]: Lock configuration */ /****************************************************************************/ /** @defgroup tim_lock TIM_BDTR_LOCK Timer Lock Values -@ingroup STM32F1xx_tim_defines +@ingroup STM32F_tim_defines @{*/ #define TIM_BDTR_LOCK_OFF (0x0 << 8) diff --git a/include/libopencm3/stm32/usart.h b/include/libopencm3/stm32/usart.h index 9ec6c3d..911781b 100644 --- a/include/libopencm3/stm32/usart.h +++ b/include/libopencm3/stm32/usart.h @@ -1,3 +1,18 @@ +/** @defgroup STM32F_usart_defines USART Defines + +@brief libopencm3 Defined Constants and Types for the STM32F Digital to Analog Converter + +@ingroup STM32F_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2009 Uwe Hermann + +@date 1 September 2012 + +LGPL License Terms @ref lgpl_license + */ + /* * This file is part of the libopencm3 project. * @@ -17,6 +32,8 @@ * along with this library. If not, see . */ +/**@{*/ + #ifndef LIBOPENCM3_USART_H #define LIBOPENCM3_USART_H @@ -25,9 +42,15 @@ /* --- Convenience macros -------------------------------------------------- */ +/****************************************************************************/ +/** @defgroup usart_reg_base USART register base addresses +@ingroup STM32F_usart_defines + +@{*/ #define USART1 USART1_BASE #define USART2 USART2_BASE #define USART3 USART3_BASE +/**@}*/ #define UART4 UART4_BASE #define UART5 UART5_BASE @@ -90,37 +113,43 @@ #define UART5_GTPR USART_GTPR(UART5_BASE) /* --- USART_SR values ----------------------------------------------------- */ +/****************************************************************************/ +/** @defgroup usart_sr_flags USART Status register Flags +@ingroup STM32F_usart_defines -/* CTS: CTS flag */ -/* Note: N/A on UART4/5 */ +@{*/ + +/** CTS: CTS flag */ +/** @note: undefined on UART4 and UART5 */ #define USART_SR_CTS (1 << 9) -/* LBD: LIN break detection flag */ +/** LBD: LIN break detection flag */ #define USART_SR_LBD (1 << 8) -/* TXE: Transmit data buffer empty */ +/** TXE: Transmit data buffer empty */ #define USART_SR_TXE (1 << 7) -/* TC: Transmission complete */ +/** TC: Transmission complete */ #define USART_SR_TC (1 << 6) -/* RXNE: Read data register not empty */ +/** RXNE: Read data register not empty */ #define USART_SR_RXNE (1 << 5) -/* IDLE: Idle line detected */ +/** IDLE: Idle line detected */ #define USART_SR_IDLE (1 << 4) -/* ORE: Overrun error */ +/** ORE: Overrun error */ #define USART_SR_ORE (1 << 3) -/* NE: Noise error flag */ +/** NE: Noise error flag */ #define USART_SR_NE (1 << 2) -/* FE: Framing error */ +/** FE: Framing error */ #define USART_SR_FE (1 << 1) -/* PE: Parity error */ +/** PE: Parity error */ #define USART_SR_PE (1 << 0) +/**@}*/ /* --- USART_DR values ----------------------------------------------------- */ @@ -269,27 +298,51 @@ /* --- Convenience defines ------------------------------------------------- */ /* CR1_PCE / CR1_PS combined values */ +/****************************************************************************/ +/** @defgroup usart_cr1_parity USART Parity Selection +@ingroup STM32F_usart_defines + +@{*/ #define USART_PARITY_NONE 0x00 #define USART_PARITY_EVEN USART_CR1_PCE #define USART_PARITY_ODD (USART_CR1_PS | USART_CR1_PCE) +/**@}*/ #define USART_PARITY_MASK (USART_CR1_PS | USART_CR1_PCE) /* CR1_TE/CR1_RE combined values */ +/****************************************************************************/ +/** @defgroup usart_cr1_mode USART Tx/Rx Mode Selection +@ingroup STM32F_usart_defines + +@{*/ #define USART_MODE_RX USART_CR1_RE #define USART_MODE_TX USART_CR1_TE #define USART_MODE_TX_RX (USART_CR1_RE | USART_CR1_TE) +/**@}*/ #define USART_MODE_MASK (USART_CR1_RE | USART_CR1_TE) +/****************************************************************************/ +/** @defgroup usart_cr2_stopbits USART Stop Bit Selection +@ingroup STM32F_usart_defines + +@{*/ #define USART_STOPBITS_1 USART_CR2_STOPBITS_1 /* 1 stop bit */ #define USART_STOPBITS_0_5 USART_CR2_STOPBITS_0_5 /* 0.5 stop bits */ #define USART_STOPBITS_2 USART_CR2_STOPBITS_2 /* 2 stop bits */ #define USART_STOPBITS_1_5 USART_CR2_STOPBITS_1_5 /* 1.5 stop bits */ +/**@}*/ /* CR3_CTSE/CR3_RTSE combined values */ +/****************************************************************************/ +/** @defgroup usart_cr3_flowcontrol USART Hardware Flow Control Selection +@ingroup STM32F_usart_defines + +@{*/ #define USART_FLOWCONTROL_NONE 0x00 #define USART_FLOWCONTROL_RTS USART_CR3_RTSE #define USART_FLOWCONTROL_CTS USART_CR3_CTSE #define USART_FLOWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) +/**@}*/ #define USART_FLOWCONTROL_MASK (USART_CR3_RTSE | USART_CR3_CTSE) /* --- Function prototypes ------------------------------------------------- */ @@ -318,3 +371,5 @@ void usart_disable_tx_dma(u32 usart); END_DECLS #endif +/**@}*/ + -- cgit v1.2.3